1291 files changed, 44294 insertions, 26755 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index acda512da2e2..4877a8c8ee16 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -151,4 +151,11 @@ config HAVE_MIXED_BREAKPOINTS_REGS
 config HAVE_USER_RETURN_NOTIFIER
         bool
 
+config HAVE_PERF_EVENTS_NMI
+        bool
+        help
+          System hardware can generate an NMI using the perf event
+          subsystem.  Also has support for calculating CPU cycle events
+          to determine how many clock cycles in a given period.
+
 source "kernel/gcov/Kconfig"
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 3e2e540a0f2a..b9647bb66d13 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -47,10 +47,6 @@ config GENERIC_CALIBRATE_DELAY
         bool
         default y
 
-config GENERIC_TIME
-        bool
-        default y
-
 config GENERIC_CMOS_UPDATE
         def_bool y
 
diff --git a/arch/alpha/include/asm/local64.h b/arch/alpha/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/alpha/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 98922f7d2d12..9e10882c81d7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,7 @@ config ARM
         default y
         select HAVE_AOUT
         select HAVE_IDE
+        select HAVE_MEMBLOCK
         select RTC_LIB
         select SYS_SUPPORTS_APM_EMULATION
         select GENERIC_ATOMIC64 if (!CPU_32v6K)
@@ -24,6 +25,7 @@ config ARM
         select HAVE_KERNEL_LZMA
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
+        select HAVE_REGS_AND_STACK_ACCESS_API
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -41,10 +43,6 @@ config SYS_SUPPORTS_APM_EMULATION
 config GENERIC_GPIO
         bool
 
-config GENERIC_TIME
-        bool
-        default y
-
 config ARCH_USES_GETTIMEOFFSET
         bool
         default n
@@ -55,7 +53,7 @@ config GENERIC_CLOCKEVENTS
 config GENERIC_CLOCKEVENTS_BROADCAST
         bool
         depends on GENERIC_CLOCKEVENTS
-        default y if SMP && !LOCAL_TIMERS
+        default y if SMP
 
 config HAVE_TCM
         bool
@@ -301,6 +299,7 @@ config ARCH_CNS3XXX
         select CPU_V6
         select GENERIC_CLOCKEVENTS
         select ARM_GIC
+        select PCI_DOMAINS if PCI
         help
           Support for Cavium Networks CNS3XXX platform.
 
@@ -439,21 +438,6 @@ config ARCH_IXP4XX
         help
           Support for Intel's IXP4XX (XScale) family of processors.
 
-config ARCH_L7200
-        bool "LinkUp-L7200"
-        select CPU_ARM720T
-        select FIQ
-        select ARCH_USES_GETTIMEOFFSET
-        help
-          Say Y here if you intend to run this kernel on a LinkUp Systems
-          L7200 Software Development Board which uses an ARM720T processor.
-          Information on this board can be obtained at:
-
-          <http://www.linkupsys.com/>
-
-          If you have any questions or comments about the Linux kernel port
-          to this board, send e-mail to <sjhill@cotw.com>.
-
 config ARCH_DOVE
         bool "Marvell Dove"
         select PCI
@@ -482,6 +466,19 @@ config ARCH_LOKI
         help
           Support for the Marvell Loki (88RC8480) SoC.
 
+config ARCH_LPC32XX
+        bool "NXP LPC32XX"
+        select CPU_ARM926T
+        select ARCH_REQUIRE_GPIOLIB
+        select HAVE_IDE
+        select ARM_AMBA
+        select USB_ARCH_HAS_OHCI
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        help
+          Support for the NXP LPC32XX family of processors
+
 config ARCH_MV78XX0
         bool "Marvell MV78xx0"
         select CPU_FEROCEON
@@ -586,6 +583,7 @@ config ARCH_MSM
         bool "Qualcomm MSM"
         select HAVE_CLK
         select GENERIC_CLOCKEVENTS
+        select ARCH_REQUIRE_GPIOLIB
         help
           Support for Qualcomm MSM/QSD based systems.  This runs on the
           apps processor of the MSM/QSD and depends on a shared memory
@@ -719,7 +717,6 @@ config ARCH_SHARK
 config ARCH_LH7A40X
         bool "Sharp LH7A40X"
         select CPU_ARM922T
-        select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
         select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
         select ARCH_USES_GETTIMEOFFSET
         help
@@ -845,6 +842,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
 
 source "arch/arm/mach-loki/Kconfig"
 
+source "arch/arm/mach-lpc32xx/Kconfig"
+
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1031,11 +1030,6 @@ endmenu
 
 source "arch/arm/common/Kconfig"
 
-config FORCE_MAX_ZONEORDER
-        int
-        depends on SA1111
-        default "9"
-
 menu "Bus support"
 
 config ARM_AMBA
@@ -1060,7 +1054,7 @@ config ISA_DMA_API
         bool
 
 config PCI
-        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1172,9 +1166,10 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+                ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
         default y
-        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1185,10 +1180,10 @@ source kernel/Kconfig.preempt
 
 config HZ
         int
-        default 128 if ARCH_L7200
         default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
+        default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
         default 100
 
 config THUMB2_KERNEL
@@ -1241,10 +1236,6 @@ config OABI_COMPAT
 config ARCH_HAS_HOLES_MEMORYMODEL
         bool
 
-# Discontigmem is deprecated
-config ARCH_DISCONTIGMEM_ENABLE
-        bool
-
 config ARCH_SPARSEMEM_ENABLE
         bool
 
@@ -1252,13 +1243,7 @@ config ARCH_SPARSEMEM_DEFAULT
         def_bool ARCH_SPARSEMEM_ENABLE
 
 config ARCH_SELECT_MEMORY_MODEL
-        def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
-
-config NODES_SHIFT
-        int
-        default "4" if ARCH_LH7A40X
-        default "2"
-        depends on NEED_MULTIPLE_NODES
+        def_bool ARCH_SPARSEMEM_ENABLE
 
 config HIGHMEM
         bool "High Memory Support (EXPERIMENTAL)"
@@ -1290,8 +1275,33 @@ config HW_PERF_EVENTS
           Enable hardware performance counter support for perf events. If
           disabled, perf events will use software events only.
 
+config SPARSE_IRQ
+        def_bool n
+        help
+          This enables support for sparse irqs. This is useful in general
+          as most CPUs have a fairly sparse array of IRQ vectors, which
+          the irq_desc then maps directly on to. Systems with a high
+          number of off-chip IRQs will want to treat this as
+          experimental until they have been independently verified.
+
 source "mm/Kconfig"
 
+config FORCE_MAX_ZONEORDER
+        int "Maximum zone order" if ARCH_SHMOBILE
+        range 11 64 if ARCH_SHMOBILE
+        default "9" if SA1111
+        default "11"
+        help
+          The kernel memory allocator divides physically contiguous memory
+          blocks into "zones", where each zone is a power of two number of
+          pages.  This option selects the largest power of two that the kernel
+          keeps in the memory allocator.  If you need to allocate very large
+          blocks of physically contiguous memory, then you may need to
+          increase this value.
+
+          This config option is actually maximum order plus one. For example,
+          a value of 11 means that the largest free memory block is 2^10 pages.
+
 config LEDS
         bool "Timer and CPU usage LEDs"
         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
@@ -1375,6 +1385,24 @@ config UACCESS_WITH_MEMCPY
           However, if the CPU data cache is using a write-allocate mode,
           this option is unlikely to provide any performance gain.
 
+config CC_STACKPROTECTOR
+        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+        help
+          This option turns on the -fstack-protector GCC feature. This
+          feature puts, at the beginning of functions, a canary value on
+          the stack just before the return address, and validates
+          the value just before actually returning.  Stack based buffer
+          overflows (that need to overwrite this return address) now also
+          overwrite the canary, which gets detected and the attack is then
+          neutralized via a kernel panic.
+          This feature requires gcc version 4.2 or above.
+
+config DEPRECATED_PARAM_STRUCT
+        bool "Provide old way to pass kernel parameters"
+        help
+          This was deprecated in 2001 and announced to live on for 5 years.
+          Some old boot loaders still use this way.
+
 endmenu
 
 menu "Boot options"
@@ -1485,6 +1513,105 @@ config ATAGS_PROC
           Should the atags used to boot the kernel be exported in an "atags"
           file in procfs. Useful with kexec.
 
+config AUTO_ZRELADDR
+        bool "Auto calculation of the decompressed kernel image address"
+        depends on !ZBOOT_ROM && !ARCH_U300
+        help
+          ZRELADDR is the physical address where the decompressed kernel
+          image will be placed. If AUTO_ZRELADDR is selected, the address
+          will be determined at run-time by masking the current IP with
+          0xf8000000. This assumes the zImage being placed in the first 128MB
+          from start of memory.
+
+config ZRELADDR
+        hex "Physical address of the decompressed kernel image"
+        depends on !AUTO_ZRELADDR
+        default 0x00008000 if ARCH_BCMRING ||\
+                ARCH_CNS3XXX ||\
+                ARCH_DOVE ||\
+                ARCH_EBSA110 ||\
+                ARCH_FOOTBRIDGE ||\
+                ARCH_INTEGRATOR ||\
+                ARCH_IOP13XX ||\
+                ARCH_IOP33X ||\
+                ARCH_IXP2000 ||\
+                ARCH_IXP23XX ||\
+                ARCH_IXP4XX ||\
+                ARCH_KIRKWOOD ||\
+                ARCH_KS8695 ||\
+                ARCH_LOKI ||\
+                ARCH_MMP ||\
+                ARCH_MV78XX0 ||\
+                ARCH_NOMADIK ||\
+                ARCH_NUC93X ||\
+                ARCH_NS9XXX ||\
+                ARCH_ORION5X ||\
+                ARCH_SPEAR3XX ||\
+                ARCH_SPEAR6XX ||\
+                ARCH_U8500 ||\
+                ARCH_VERSATILE ||\
+                ARCH_W90X900
+        default 0x08008000 if ARCH_MX1 ||\
+                ARCH_SHARK
+        default 0x10008000 if ARCH_MSM ||\
+                ARCH_OMAP1 ||\
+                ARCH_RPC
+        default 0x20008000 if ARCH_S5P6440 ||\
+                ARCH_S5P6442 ||\
+                ARCH_S5PC100 ||\
+                ARCH_S5PV210
+        default 0x30008000 if ARCH_S3C2410 ||\
+                ARCH_S3C2400 ||\
+                ARCH_S3C2412 ||\
+                ARCH_S3C2416 ||\
+                ARCH_S3C2440 ||\
+                ARCH_S3C2443
+        default 0x40008000 if ARCH_STMP378X ||\
+                ARCH_STMP37XX ||\
+                ARCH_SH7372 ||\
+                ARCH_SH7377
+        default 0x50008000 if ARCH_S3C64XX ||\
+                ARCH_SH7367
+        default 0x60008000 if ARCH_VEXPRESS
+        default 0x80008000 if ARCH_MX25 ||\
+                ARCH_MX3 ||\
+                ARCH_NETX ||\
+                ARCH_OMAP2PLUS ||\
+                ARCH_PNX4008
+        default 0x90008000 if ARCH_MX5 ||\
+                ARCH_MX91231
+        default 0xa0008000 if ARCH_IOP32X ||\
+                ARCH_PXA ||\
+                MACH_MX27
+        default 0xc0008000 if ARCH_LH7A40X ||\
+                MACH_MX21
+        default 0xf0008000 if ARCH_AAEC2000 ||\
+                ARCH_L7200
+        default 0xc0028000 if ARCH_CLPS711X
+        default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+        default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+        default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
+        default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
+        default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
+        default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
+        default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
+        default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
+        default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
+        default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
+        default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
+        default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
+        default 0xc0208000 if ARCH_SA1100 && SA1111
+        default 0xc0008000 if ARCH_SA1100 && !SA1111
+        default 0x30108000 if ARCH_S3C2410 && PM_H1940
+        default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
+        default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
+        help
+          ZRELADDR is the physical address where the decompressed kernel
+          image will be placed. ZRELADDR has to be specified when the
+          assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
+          selected.
+
 endmenu
 
 menu "CPU Power Management"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313724d2..63d998e8c672 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
 KBUILD_CFLAGS   +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
 endif
 
+ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
+KBUILD_CFLAGS   +=-fstack-protector
+endif
+
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
 KBUILD_CPPFLAGS += -mbig-endian
 AS              += -EB
@@ -139,14 +143,14 @@ machine-$(CONFIG_ARCH_IXP23XX)		:= ixp23xx
 machine-$(CONFIG_ARCH_IXP4XX)           := ixp4xx
 machine-$(CONFIG_ARCH_KIRKWOOD)         := kirkwood
 machine-$(CONFIG_ARCH_KS8695)           := ks8695
-machine-$(CONFIG_ARCH_L7200)            := l7200
 machine-$(CONFIG_ARCH_LH7A40X)          := lh7a40x
 machine-$(CONFIG_ARCH_LOKI)             := loki
+machine-$(CONFIG_ARCH_LPC32XX)          := lpc32xx
 machine-$(CONFIG_ARCH_MMP)              := mmp
 machine-$(CONFIG_ARCH_MSM)              := msm
 machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
-machine-$(CONFIG_ARCH_MX1)              := mx1
-machine-$(CONFIG_ARCH_MX2)              := mx2
+machine-$(CONFIG_ARCH_MX1)              := imx
+machine-$(CONFIG_ARCH_MX2)              := imx
 machine-$(CONFIG_ARCH_MX25)             := mx25
 machine-$(CONFIG_ARCH_MX3)              := mx3
 machine-$(CONFIG_ARCH_MX5)              := mx5
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4113e2..f705213caa88 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -14,18 +14,16 @@
 MKIMAGE         := $(srctree)/scripts/mkuboot.sh
 
 ifneq ($(MACHINE),)
-include $(srctree)/$(MACHINE)/Makefile.boot
+-include $(srctree)/$(MACHINE)/Makefile.boot
 endif
 
 # Note: the following conditions must always be true:
-#   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
-ZRELADDR    := $(zreladdr-y)
 PARAMS_PHYS := $(params_phys-y)
 INITRD_PHYS := $(initrd_phys-y)
 
-export ZRELADDR INITRD_PHYS PARAMS_PHYS
+export INITRD_PHYS PARAMS_PHYS
 
 targets := Image zImage xipImage bootpImage uImage
 
@@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE  $@
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
 else
-$(obj)/uImage: LOADADDR=$(ZRELADDR)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
 endif
 
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 53faa9063a03..7636c9b3f9a7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -4,6 +4,7 @@
 # create a compressed vmlinuz image from the original vmlinux
 #
 
+AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
 HEAD    = head.o
 OBJS    = misc.o decompress.o
 FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
@@ -19,10 +20,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
 OBJS            += head-shark.o ofw-shark.o
 endif
 
-ifeq ($(CONFIG_ARCH_L7200),y)
-OBJS            += head-l7200.o
-endif
-
 ifeq ($(CONFIG_ARCH_P720T),y)
 # Borrow this code from SA1100
 OBJS            += head-sa1100.o
@@ -71,6 +68,9 @@ targets       := vmlinux vmlinux.lds \
                  piggy.$(suffix_y) piggy.$(suffix_y).o \
                  font.o font.c head.o misc.o $(OBJS)
 
+# Make sure files are removed during clean
+extra-y       += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S
+
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)
 KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
@@ -79,19 +79,9 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
-# linker symbols.  We only define initrd_phys and params_phys if the
-# machine class defined the corresponding makefile variable.
-LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
-ifneq ($(INITRD_PHYS),)
-LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
-endif
-ifneq ($(PARAMS_PHYS),)
-LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
-endif
 # ?
 LDFLAGS_vmlinux += -p
 # Report unresolved symbol references
diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug
deleted file mode 100644
index 491a037b2973..000000000000
--- a/arch/arm/boot/compressed/Makefile.debug
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# linux/arch/arm/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux
-#
-
-COMPRESSED_EXTRA=../../lib/ll_char_wr.o
-OBJECTS=misc-debug.o ll_char_wr.aout.o
-
-CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
-
-test-gzip: piggy.aout.o $(OBJECTS)
-        $(CC) -o $@ $(OBJECTS) piggy.aout.o
-
-misc-debug.o: misc.c
-        $(CC) $(CFLAGS) -o $@ misc.c
-
-piggy.aout.o: piggy.o
-        arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
-
-ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
-        arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
-
diff --git a/arch/arm/boot/compressed/head-l7200.S b/arch/arm/boot/compressed/head-l7200.S
deleted file mode 100644
index d0e3b20856cd..000000000000
--- a/arch/arm/boot/compressed/head-l7200.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/* 
- * linux/arch/arm/boot/compressed/head-l7200.S
- * 
- * Copyright (C) 2000 Steve Hill <sjhill@cotw.com>
- * 
- * Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This
- * is merged with head.S by the linker.
- */
-
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_ARCH_L7200
-#error What am I doing here...
-#endif
-
-                .section        ".start", "ax"
-
-__L7200_start:
-                mov     r0, #0x00100000         @ FLASH address of initrd
-                mov     r2, #0xf1000000         @ RAM address of initrd
-                add     r3, r2, #0x00700000     @ Size of initrd 
-1:
-                ldmia   r0!, {r4, r5, r6, r7}
-                stmia   r2!, {r4, r5, r6, r7}
-                cmp     r2, r3
-                ble     1b
-
-                mov     r8, #0                  @ Zero it out
-                mov     r7, #MACH_TYPE_L7200    @ Set architecture ID
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5191b1532e8..abf4d65acf62 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -170,9 +170,16 @@ not_angel:
 
                 .text
                 adr     r0, LC0
- ARM(           ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
- THUMB(         ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip}   )
+ ARM(           ldmia   r0, {r1, r2, r3, r5, r6, r11, ip, sp})
+ THUMB(         ldmia   r0, {r1, r2, r3, r5, r6, r11, ip}       )
  THUMB(         ldr     sp, [r0, #32]                           )
+#ifdef CONFIG_AUTO_ZRELADDR
+                @ determine final kernel image address
+                and     r4, pc, #0xf8000000
+                add     r4, r4, #TEXT_OFFSET
+#else
+                ldr     r4, =CONFIG_ZRELADDR
+#endif
                 subs    r0, r0, r1              @ calculate the delta offset
 
                                                 @ if delta is zero, we are
@@ -310,18 +317,17 @@ wont_overwrite:	mov	r0, r4
 LC0:            .word   LC0                     @ r1
                 .word   __bss_start             @ r2
                 .word   _end                    @ r3
-                .word   zreladdr                @ r4
                 .word   _start                  @ r5
                 .word   _image_size             @ r6
                 .word   _got_start              @ r11
                 .word   _got_end                @ ip
-                .word   user_stack+4096         @ sp
+                .word   user_stack_end          @ sp
 LC1:            .word   reloc_end - reloc_start
                 .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
                 .globl  params
-params:         ldr     r0, =params_phys
+params:         ldr     r0, =0x10000100         @ params_phys for RPC
                 mov     pc, lr
                 .ltorg
                 .align
@@ -339,9 +345,8 @@ params:		ldr	r0, =params_phys
  *  r4 = kernel execution address
  *  r7 = architecture number
  *  r8 = atags pointer
- *  r9 = run-time address of "start"  (???)
  * On exit,
- *  r1, r2, r3, r9, r10, r12 corrupted
+ *  r0, r1, r2, r3, r9, r10, r12 corrupted
  * This routine must preserve:
  *  r4, r5, r6, r7, r8
  */
@@ -396,12 +401,18 @@ __armv3_mpu_cache_on:
 
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+                /*
+                 * ?? ARMv3 MMU does not allow reading the control register,
+                 * does this really work on ARMv3 MPU?
+                 */
                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                                                 @ .... .... .... WC.M
                 orr     r0, r0, #0x000d         @ .... .... .... 11.1
+                /* ?? this overwrites the value constructed above? */
                 mov     r0, #0
                 mcr     p15, 0, r0, c1, c0, 0   @ write control reg
 
+                /* ?? invalidate for the second time? */
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                 mov     pc, lr
 
@@ -771,8 +782,10 @@ proc_types:
  * Turn off the Cache and MMU.  ARMv3 does not support
  * reading the control register, but ARMv4 does.
  *
- * On exit, r0, r1, r2, r3, r9, r12 corrupted
- * This routine must preserve: r4, r6, r7
+ * On exit,
+ *  r0, r1, r2, r3, r9, r12 corrupted
+ * This routine must preserve:
+ *  r4, r6, r7
  */
                 .align  5
 cache_off:      mov     r3, #12                 @ cache_off function
@@ -845,7 +858,7 @@ __armv3_mmu_cache_off:
  * Clean and flush the cache to maintain consistency.
  *
  * On exit,
- *  r1, r2, r3, r9, r11, r12 corrupted
+ *  r1, r2, r3, r9, r10, r11, r12 corrupted
  * This routine must preserve:
  *  r0, r4, r5, r6, r7
  */
@@ -988,7 +1001,7 @@ no_cache_id:
 __armv3_mmu_cache_flush:
 __armv3_mpu_cache_flush:
                 mov     r1, #0
-                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+                mcr     p15, 0, r1, c7, c0, 0   @ invalidate whole cache v3
                 mov     pc, lr
 
 /*
@@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush:
 phexbuf:        .space  12
                 .size   phexbuf, . - phexbuf
 
+@ phex corrupts {r0, r1, r2, r3}
 phex:           adr     r3, phexbuf
                 mov     r2, #0
                 strb    r2, [r3, r1]
@@ -1015,6 +1029,7 @@ phex:		adr	r3, phexbuf
                 strb    r2, [r3, r1]
                 b       1b
 
+@ puts corrupts {r0, r1, r2, r3}
 puts:           loadsp  r3, r1
 1:              ldrb    r2, [r0], #1
                 teq     r2, #0
@@ -1029,12 +1044,14 @@ puts:		loadsp	r3, r1
                 teq     r0, #0
                 bne     1b
                 mov     pc, lr
+@ putc corrupts {r0, r1, r2, r3}
 putc:
                 mov     r2, r0
                 mov     r0, #0
                 loadsp  r3, r1
                 b       2b
 
+@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
 memdump:        mov     r12, r0
                 mov     r10, lr
                 mov     r11, #0
@@ -1070,3 +1087,4 @@ reloc_end:
                 .align
                 .section ".stack", "w"
 user_stack:     .space  4096
+user_stack_end:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index d2b2ef41cd4f..e653a6d3c8d9 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
 
 #include <asm/unaligned.h>
 
-#ifdef STANDALONE_DEBUG
-#define putstr printf
-#else
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -116,7 +113,6 @@ static void putstr(const char *ptr)
         flush();
 }
 
-#endif
 
 void *memcpy(void *__dest, __const void *__src, size_t __n)
 {
@@ -186,7 +182,6 @@ asmlinkage void __div0(void)
 
 extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
 
-#ifndef STANDALONE_DEBUG
 
 unsigned long
 decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
@@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
         putstr(" done, booting the kernel.\n");
         return output_ptr;
 }
-#else
-
-char output_buffer[1500*1024];
-
-int main()
-{
-        output_data = output_buffer;
-
-        putstr("Uncompressing Linux...");
-        decompress(input_data, input_data_end - input_data,
-                        NULL, NULL, output_data, NULL, error);
-        putstr("done.\n");
-        return 0;
-}
-#endif
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 337741f734ac..7dfa9a85bc0c 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq)
         spin_unlock(&irq_controller_lock);
 }
 
+static int gic_set_type(unsigned int irq, unsigned int type)
+{
+        void __iomem *base = gic_dist_base(irq);
+        unsigned int gicirq = gic_irq(irq);
+        u32 enablemask = 1 << (gicirq % 32);
+        u32 enableoff = (gicirq / 32) * 4;
+        u32 confmask = 0x2 << ((gicirq % 16) * 2);
+        u32 confoff = (gicirq / 16) * 4;
+        bool enabled = false;
+        u32 val;
+
+        /* Interrupt configuration for SGIs can't be changed */
+        if (gicirq < 16)
+                return -EINVAL;
+
+        if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+                return -EINVAL;
+
+        spin_lock(&irq_controller_lock);
+
+        val = readl(base + GIC_DIST_CONFIG + confoff);
+        if (type == IRQ_TYPE_LEVEL_HIGH)
+                val &= ~confmask;
+        else if (type == IRQ_TYPE_EDGE_RISING)
+                val |= confmask;
+
+        /*
+         * As recommended by the spec, disable the interrupt before changing
+         * the configuration
+         */
+        if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+                writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+                enabled = true;
+        }
+
+        writel(val, base + GIC_DIST_CONFIG + confoff);
+
+        if (enabled)
+                writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+
+        spin_unlock(&irq_controller_lock);
+
+        return 0;
+}
+
 #ifdef CONFIG_SMP
 static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
 {
@@ -161,6 +206,7 @@ static struct irq_chip gic_chip = {
         .ack            = gic_ack_irq,
         .mask           = gic_mask_irq,
         .unmask         = gic_unmask_irq,
+        .set_type       = gic_set_type,
 #ifdef CONFIG_SMP
         .set_affinity   = gic_set_cpu,
 #endif
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 6f80665f477e..517d50ddbeb3 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -185,13 +185,10 @@ static struct sa1111_dev_info sa1111_devices[] = {
         },
 };
 
-void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes)
+void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
 {
         unsigned int sz = SZ_1M >> PAGE_SHIFT;
 
-        if (node != 0)
-                sz = 0;
-
         size[1] = size[0] - sz;
         size[0] = sz;
 }
@@ -1028,13 +1025,12 @@ static int sa1111_remove(struct platform_device *pdev)
         struct sa1111 *sachip = platform_get_drvdata(pdev);
 
         if (sachip) {
-                __sa1111_remove(sachip);
-                platform_set_drvdata(pdev, NULL);
-
 #ifdef CONFIG_PM
                 kfree(sachip->saved_state);
                 sachip->saved_state = NULL;
 #endif
+                __sa1111_remove(sachip);
+                platform_set_drvdata(pdev, NULL);
         }
 
         return 0;
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index f2e3a9088df6..ccc9c9959b82 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
 CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+CONFIG_MACH_GURUPLUG=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
+CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_NETSPACE_V2=y
+CONFIG_MACH_INETSPACE_V2=y
+CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_NET2BIG_V2=y
+CONFIG_MACH_NET5BIG_V2=y
+CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/lusl7200_defconfig b/arch/arm/configs/lusl7200_defconfig
deleted file mode 100644
index 816fc42884c9..000000000000
--- a/arch/arm/configs/lusl7200_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_HOTPLUG is not set
-CONFIG_MODULES=y
-CONFIG_ARCH_L7200=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x00010000
-CONFIG_ZBOOT_ROM_BSS=0xf03e0000
-CONFIG_ZBOOT_ROM=y
-CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M"
-CONFIG_BINFMT_AOUT=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_EXT2_FS=y
-CONFIG_DEBUG_USER=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662feb9f1d..6750b8e45a49 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
 extern void elf_set_personality(const struct elf32_hdr *);
 #define SET_PERSONALITY(ex)     elf_set_personality(&(ex))
 
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index f7bd52b1c365..c1062c317103 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -19,6 +19,7 @@
 #define HWCAP_NEON      4096
 #define HWCAP_VFPv3     8192
 #define HWCAP_VFPv3D16  16384
+#define HWCAP_TLS       32768
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index c980156f3263..1261b1f928d9 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -26,6 +26,7 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
+#include <asm/system.h>
 
 /*
  * ISA I/O bus memory addresses are 1:1 with the physical address.
@@ -179,25 +180,38 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  * IO port primitives for more information.
  */
 #ifdef __mem_pci
-#define readb(c) ({ __u8  __v = __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
+#define readb_relaxed(c) ({ u8  __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
                                         __raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
+#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
                                         __raw_readl(__mem_pci(c))); __v; })
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
+
+#define writeb_relaxed(v,c)     ((void)__raw_writeb(v,__mem_pci(c)))
+#define writew_relaxed(v,c)     ((void)__raw_writew((__force u16) \
+                                        cpu_to_le16(v),__mem_pci(c)))
+#define writel_relaxed(v,c)     ((void)__raw_writel((__force u32) \
+                                        cpu_to_le32(v),__mem_pci(c)))
+
+#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+#define __iormb()               rmb()
+#define __iowmb()               wmb()
+#else
+#define __iormb()               do { } while (0)
+#define __iowmb()               do { } while (0)
+#endif
+
+#define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)             ({ __iowmb(); writeb_relaxed(v,c); })
+#define writew(v,c)             ({ __iowmb(); writew_relaxed(v,c); })
+#define writel(v,c)             ({ __iowmb(); writel_relaxed(v,c); })
 
 #define readsb(p,d,l)           __raw_readsb(__mem_pci(p),d,l)
 #define readsw(p,d,l)           __raw_readsw(__mem_pci(p),d,l)
 #define readsl(p,d,l)           __raw_readsl(__mem_pci(p),d,l)
 
-#define writeb(v,c)             __raw_writeb(v,__mem_pci(c))
-#define writew(v,c)             __raw_writew((__force __u16) \
-                                        cpu_to_le16(v),__mem_pci(c))
-#define writel(v,c)             __raw_writel((__force __u32) \
-                                        cpu_to_le32(v),__mem_pci(c))
-
 #define writesb(p,d,l)          __raw_writesb(__mem_pci(p),d,l)
 #define writesw(p,d,l)          __raw_writesw(__mem_pci(p),d,l)
 #define writesl(p,d,l)          __raw_writesl(__mem_pci(p),d,l)
@@ -244,13 +258,13 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  * io{read,write}{8,16,32} macros
  */
 #ifndef ioread8
-#define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __v; })
-#define ioread16(p)     ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; })
-#define ioread32(p)     ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; })
+#define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
+#define ioread16(p)     ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
+#define ioread32(p)     ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
 
-#define iowrite8(v,p)   __raw_writeb(v, p)
-#define iowrite16(v,p)  __raw_writew((__force __u16)cpu_to_le16(v), p)
-#define iowrite32(v,p)  __raw_writel((__force __u32)cpu_to_le32(v), p)
+#define iowrite8(v,p)   ({ __iowmb(); (void)__raw_writeb(v, p); })
+#define iowrite16(v,p)  ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); })
+#define iowrite32(v,p)  ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); })
 
 #define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 #define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 237282f7c762..2721a5814cb9 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -7,6 +7,8 @@
 #define irq_canonicalize(i)     (i)
 #endif
 
+#define NR_IRQS_LEGACY  16
+
 /*
  * Use this value to indicate lack of interrupt
  * capability
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index df15a0dc228e..8ec9ef5c3c7b 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -19,10 +19,26 @@
 
 #ifndef __ASSEMBLY__
 
-struct kimage;
-/* Provide a dummy definition to avoid build failures. */
+/**
+ * crash_setup_regs() - save registers for the panic kernel
+ * @newregs: registers are saved here
+ * @oldregs: registers to be saved (may be %NULL)
+ *
+ * Function copies machine registers from @oldregs to @newregs. If @oldregs is
+ * %NULL then current registers are stored there.
+ */
 static inline void crash_setup_regs(struct pt_regs *newregs,
-                                        struct pt_regs *oldregs) { }
+                                    struct pt_regs *oldregs)
+{
+        if (oldregs) {
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        } else {
+                __asm__ __volatile__ ("stmia %0, {r0 - r15}"
+                                      : : "r" (&newregs->ARM_r0));
+                __asm__ __volatile__ ("mrs %0, cpsr"
+                                      : "=r" (newregs->ARM_cpsr));
+        }
+}
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h
index 67af4b841984..08265993227f 100644
--- a/arch/arm/include/asm/kgdb.h
+++ b/arch/arm/include/asm/kgdb.h
@@ -70,11 +70,11 @@ extern int kgdb_fault_expected;
 #define _GP_REGS                16
 #define _FP_REGS                8
 #define _EXTRA_REGS             2
-#define GDB_MAX_REGS            (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+#define DBG_MAX_REG_NUM         (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
 
 #define KGDB_MAX_NO_CPUS        1
 #define BUFMAX                  400
-#define NUMREGBYTES             (GDB_MAX_REGS << 2)
+#define NUMREGBYTES             (DBG_MAX_REG_NUM << 2)
 #define NUMCRITREGBYTES         (32 << 2)
 
 #define _R0                     0
@@ -93,7 +93,7 @@ extern int kgdb_fault_expected;
 #define _SPT                    13
 #define _LR                     14
 #define _PC                     15
-#define _CPSR                   (GDB_MAX_REGS - 1)
+#define _CPSR                   (DBG_MAX_REG_NUM - 1)
 
 /*
  * So that we can denote the end of a frame for tracing,
diff --git a/arch/arm/include/asm/local64.h b/arch/arm/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/arm/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index c59842dc7cb8..8a0dd18ba642 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -20,6 +20,7 @@ struct machine_desc {
          * by assembler code in head.S, head-common.S
          */
         unsigned int            nr;             /* architecture number  */
+        unsigned int            nr_irqs;        /* number of IRQs */
         unsigned int            phys_io;        /* start of physical io */
         unsigned int            io_pg_offst;    /* byte offset for io 
                                                  * page tabe entry      */
@@ -37,6 +38,7 @@ struct machine_desc {
         void                    (*fixup)(struct machine_desc *,
                                          struct tag *, char **,
                                          struct meminfo *);
+        void                    (*reserve)(void);/* reserve mem blocks  */
         void                    (*map_io)(void);/* IO mapping function  */
         void                    (*init_irq)(void);
         struct sys_timer        *timer;         /* system tick timer    */
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 8920b2d6e3b8..ce3eee9fe26c 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,6 +17,7 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
+extern unsigned int arch_nr_irqs;
 extern void (*init_arch_irq)(void);
 extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, void *);
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 742c2aaeb020..d2fedb5aeb1f 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -27,6 +27,8 @@ struct map_desc {
 #define MT_MEMORY               9
 #define MT_ROM                  10
 #define MT_MEMORY_NONCACHED     11
+#define MT_MEMORY_DTCM          12
+#define MT_MEMORY_ITCM          13
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 52f0da1e97df..16330bd0657c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -46,6 +46,7 @@ struct pci_sys_data {
                                         /* IRQ mapping                          */
         int             (*map_irq)(struct pci_dev *, u8, u8);
         struct hw_pci   *hw;
+        void            *private_data;  /* platform controller private data     */
 };
 
 /*
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
new file mode 100644
index 000000000000..fdbc43b2e6c0
--- /dev/null
+++ b/arch/arm/include/asm/memblock.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_ARM_MEMBLOCK_H
+#define _ASM_ARM_MEMBLOCK_H
+
+#ifdef CONFIG_MMU
+extern phys_addr_t lowmem_end_addr;
+#define MEMBLOCK_REAL_LIMIT     lowmem_end_addr
+#else
+#define MEMBLOCK_REAL_LIMIT     0
+#endif
+
+struct meminfo;
+struct machine_desc;
+
+extern void arm_memblock_init(struct meminfo *, struct machine_desc *);
+
+#endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4312ee5e3d0b..23c2e8e5c0fa 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -124,6 +124,15 @@
 #endif /* !CONFIG_MMU */
 
 /*
+ * We fix the TCM memories max 32 KiB ITCM resp DTCM at these
+ * locations
+ */
+#ifdef CONFIG_HAVE_TCM
+#define ITCM_OFFSET     UL(0xfffe0000)
+#define DTCM_OFFSET     UL(0xfffe8000)
+#endif
+
+/*
  * Physical vs virtual RAM address space conversion.  These are
  * private definitions which should NOT be used outside memory.h
  * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
@@ -158,7 +167,7 @@
 #endif
 
 #ifndef arch_adjust_zones
-#define arch_adjust_zones(node,size,holes) do { } while (0)
+#define arch_adjust_zones(size,holes) do { } while (0)
 #elif !defined(CONFIG_ZONE_DMA)
 #error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
 #endif
@@ -234,76 +243,11 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  *  virt_to_page(k)     convert a _valid_ virtual address to struct page *
  *  virt_addr_valid(k)  indicates whether a virtual address is valid
  */
-#ifndef CONFIG_DISCONTIGMEM
-
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
 
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
 
-#define PHYS_TO_NID(addr)       (0)
-
-#else /* CONFIG_DISCONTIGMEM */
-
-/*
- * This is more complex.  We have a set of mem_map arrays spread
- * around in memory.
- */
-#include <linux/numa.h>
-
-#define arch_pfn_to_nid(pfn)    PFN_TO_NID(pfn)
-#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
-
-#define virt_to_page(kaddr)                                     \
-        (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
-
-#define virt_addr_valid(kaddr)  (KVADDR_TO_NID(kaddr) < MAX_NUMNODES)
-
-/*
- * Common discontigmem stuff.
- *  PHYS_TO_NID is used by the ARM kernel/setup.c
- */
-#define PHYS_TO_NID(addr)       PFN_TO_NID((addr) >> PAGE_SHIFT)
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-#ifdef NODE_MEM_SIZE_BITS
-#define NODE_MEM_SIZE_MASK      ((1 << NODE_MEM_SIZE_BITS) - 1)
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-        (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
-
-#endif /* NODE_MEM_SIZE_BITS */
-
-#endif /* !CONFIG_DISCONTIGMEM */
-
 /*
  * Optional coherency support.  Currently used only by selected
  * Intel XSC3-based systems.
diff --git a/arch/arm/include/asm/mmzone.h b/arch/arm/include/asm/mmzone.h
deleted file mode 100644
index ae63a4fd28c8..000000000000
--- a/arch/arm/include/asm/mmzone.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- *  arch/arm/include/asm/mmzone.h
- *
- *  1999-12-29  Nicolas Pitre           Created
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_MMZONE_H
-#define __ASM_MMZONE_H
-
-/*
- * Currently defined in arch/arm/mm/discontig.c
- */
-extern pg_data_t discontig_node_data[];
-
-/*
- * Return a pointer to the node data for node n.
- */
-#define NODE_DATA(nid)          (&discontig_node_data[nid])
-
-/*
- * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
- */
-#define NODE_MEM_MAP(nid)       (NODE_DATA(nid)->node_mem_map)
-
-#include <mach/memory.h>
-
-#endif
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 9dcb11e59026..c974be8913a7 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define predicate(x)            ((x) & 0xf0000000)
 #define PREDICATE_ALWAYS        0xe0000000
 
+/*
+ * kprobe-based event tracer support
+ */
+#include <linux/stddef.h>
+#include <linux/types.h>
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
+
+extern int regs_query_register_offset(const char *name);
+extern const char *regs_query_register_name(unsigned int offset);
+extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
+extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+                                               unsigned int n);
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:          pt_regs from which register value is gotten
+ * @offset:    offset number of the register.
+ *
+ * regs_get_register returns the value of a register whose offset from @regs.
+ * The @offset is the offset of the register in struct pt_regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+                                              unsigned int offset)
+{
+        if (unlikely(offset > MAX_REG_OFFSET))
+                return 0;
+        return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/* Valid only for Kernel mode traps. */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+        return regs->ARM_sp;
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index f392fb4437af..f1e5a9bca249 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -201,8 +201,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
 struct membank {
         unsigned long start;
         unsigned long size;
-        unsigned short node;
-        unsigned short highmem;
+        unsigned int highmem;
 };
 
 struct meminfo {
@@ -212,9 +211,8 @@ struct meminfo {
 
 extern struct meminfo meminfo;
 
-#define for_each_nodebank(iter,mi,no)                   \
-        for (iter = 0; iter < (mi)->nr_banks; iter++)   \
-                if ((mi)->bank[iter].node == no)
+#define for_each_bank(iter,mi)                          \
+        for (iter = 0; iter < (mi)->nr_banks; iter++)
 
 #define bank_pfn_start(bank)    __phys_to_pfn((bank)->start)
 #define bank_pfn_end(bank)      __phys_to_pfn((bank)->start + (bank)->size)
diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
new file mode 100644
index 000000000000..de003327be97
--- /dev/null
+++ b/arch/arm/include/asm/stackprotector.h
@@ -0,0 +1,38 @@
+/*
+ * GCC stack protector support.
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on ARM.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+        unsigned long canary;
+
+        /* Try to get a semi random initial value. */
+        get_random_bytes(&canary, sizeof(canary));
+        canary ^= LINUX_VERSION_CODE;
+
+        current->stack_canary = canary;
+        __stack_chk_guard = current->stack_canary;
+}
+
+#endif  /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f48002734..8ba1ccf82a02 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -83,7 +83,7 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
 
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                        struct pt_regs *),
-                     int sig, const char *name);
+                     int sig, int code, const char *name);
 
 #define xchg(ptr,x) \
         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
new file mode 100644
index 000000000000..e71d6ff8d104
--- /dev/null
+++ b/arch/arm/include/asm/tls.h
@@ -0,0 +1,46 @@
+#ifndef __ASMARM_TLS_H
+#define __ASMARM_TLS_H
+
+#ifdef __ASSEMBLY__
+        .macro set_tls_none, tp, tmp1, tmp2
+        .endm
+
+        .macro set_tls_v6k, tp, tmp1, tmp2
+        mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+        .endm
+
+        .macro set_tls_v6, tp, tmp1, tmp2
+        ldr     \tmp1, =elf_hwcap
+        ldr     \tmp1, [\tmp1, #0]
+        mov     \tmp2, #0xffff0fff
+        tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
+        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
+        .endm
+
+        .macro set_tls_software, tp, tmp1, tmp2
+        mov     \tmp1, #0xffff0fff
+        str     \tp, [\tmp1, #-15]              @ set TLS value at 0xffff0ff0
+        .endm
+#endif
+
+#ifdef CONFIG_TLS_REG_EMUL
+#define tls_emu         1
+#define has_tls_reg             1
+#define set_tls         set_tls_none
+#elif __LINUX_ARM_ARCH__ >= 7 ||                                        \
+        (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define tls_emu         0
+#define has_tls_reg             1
+#define set_tls         set_tls_v6k
+#elif __LINUX_ARM_ARCH__ == 6
+#define tls_emu         0
+#define has_tls_reg             (elf_hwcap & HWCAP_TLS)
+#define set_tls         set_tls_v6
+#else
+#define tls_emu         0
+#define has_tls_reg             0
+#define set_tls         set_tls_software
+#endif
+
+#endif  /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 422f3cc204a2..3d5fc41ae8d3 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -3,6 +3,8 @@
  *
  * Assembler-only file containing VFP macros and register definitions.
  */
+#include <asm/hwcap.h>
+
 #include "vfp.h"
 
 @ Macros to allow building with old toolkits (with no VFP support)
@@ -22,12 +24,20 @@
         LDC     p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+        ldr     \tmp, [\tmp, #0]
+        tst     \tmp, #HWCAP_VFPv3D16
+        ldceq   p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#else
         VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
         and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
         cmp     \tmp, #2                            @ 32 x 64bit registers?
         ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
         addne   \base, \base, #32*4                 @ step over unused register space
 #endif
+#endif
         .endm
 
         @ write all the working registers out of the VFP
@@ -38,10 +48,18 @@
         STC     p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+        ldr     \tmp, [\tmp, #0]
+        tst     \tmp, #HWCAP_VFPv3D16
+        stceq   p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#else
         VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
         and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
         cmp     \tmp, #2                            @ 32 x 64bit registers?
         stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
         addne   \base, \base, #32*4                 @ step over unused register space
 #endif
+#endif
         .endm
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c28e13..980b78e31328 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y           := compat.o elf.o entry-armv.o entry-common.o irq.o \
+obj-y           := elf.o entry-armv.o entry-common.o irq.o \
                    process.o ptrace.o return_address.o setup.o signal.o \
                    sys_arm.o stacktrace.o time.o traps.o
 
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+
 obj-$(CONFIG_LEDS)              += leds.o
 obj-$(CONFIG_OC_ETM)            += etm.o
 
@@ -39,6 +41,7 @@ obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_ARM_UNWIND)        += unwind.o
 obj-$(CONFIG_HAVE_TCM)          += tcm.o
+obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 883511522fca..85f2a019f77b 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -40,6 +40,9 @@
 int main(void)
 {
   DEFINE(TSK_ACTIVE_MM,         offsetof(struct task_struct, active_mm));
+#ifdef CONFIG_CC_STACKPROTECTOR
+  DEFINE(TSK_STACK_CANARY,      offsetof(struct task_struct, stack_canary));
+#endif
   BLANK();
   DEFINE(TI_FLAGS,              offsetof(struct thread_info, flags));
   DEFINE(TI_PREEMPT,            offsetof(struct thread_info, preempt_count));
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/compat.c
index 0a1385442f43..925652318b8b 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/compat.c
@@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
         struct param_struct *params = (struct param_struct *)tags;
         build_tag_list(params, &params->u2);
 }
-
-void __init squash_mem_tags(struct tag *tag)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM)
-                        tag->hdr.tag = ATAG_NONE;
-}
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
index 27e61a68bd1c..39264ab1b9c6 100644
--- a/arch/arm/kernel/compat.h
+++ b/arch/arm/kernel/compat.h
@@ -9,5 +9,3 @@
 */
 
 extern void convert_to_tag_list(struct tag *tags);
-
-extern void squash_mem_tags(struct tag *tag);
diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
new file mode 100644
index 000000000000..cd3b853a8a6d
--- /dev/null
+++ b/arch/arm/kernel/crash_dump.c
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/kernel/crash_dump.c
+ *
+ * Copyright (C) 2010 Nokia Corporation.
+ * Author: Mika Westerberg
+ *
+ * This code is taken from arch/x86/kernel/crash_dump_64.c
+ *   Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
+ *   Copyright (C) IBM Corporation, 2004. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/crash_dump.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+/* stores the physical address of elf header of crash image */
+unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
+
+/**
+ * copy_oldmem_page() - copy one page from old kernel memory
+ * @pfn: page frame number to be copied
+ * @buf: buffer where the copied page is placed
+ * @csize: number of bytes to copy
+ * @offset: offset in bytes into the page
+ * @userbuf: if set, @buf is int he user address space
+ *
+ * This function copies one page from old kernel memory into buffer pointed by
+ * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
+ * copied or negative error in case of failure.
+ */
+ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
+                         size_t csize, unsigned long offset,
+                         int userbuf)
+{
+        void *vaddr;
+
+        if (!csize)
+                return 0;
+
+        vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
+        if (!vaddr)
+                return -ENOMEM;
+
+        if (userbuf) {
+                if (copy_to_user(buf, vaddr + offset, csize)) {
+                        iounmap(vaddr);
+                        return -EFAULT;
+                }
+        } else {
+                memcpy(buf, vaddr + offset, csize);
+        }
+
+        iounmap(vaddr);
+        return csize;
+}
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3fd7861de4d1..bb8e93a76407 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -22,6 +22,7 @@
 #include <asm/thread_notify.h>
 #include <asm/unwind.h>
 #include <asm/unistd.h>
+#include <asm/tls.h>
 
 #include "entry-header.S"
 
@@ -735,11 +736,11 @@ ENTRY(__switch_to)
 #ifdef CONFIG_MMU
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-#if defined(CONFIG_HAS_TLS_REG)
-        mcr     p15, 0, r3, c13, c0, 3          @ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
-        mov     r4, #0xffff0fff
-        str     r3, [r4, #-15]                  @ TLS val at 0xffff0ff0
+        set_tls r3, r4, r5
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+        ldr     r7, [r2, #TI_TASK]
+        ldr     r8, =__stack_chk_guard
+        ldr     r7, [r7, #TSK_STACK_CANARY]
 #endif
 #ifdef CONFIG_MMU
         mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
@@ -749,6 +750,9 @@ ENTRY(__switch_to)
         ldr     r0, =thread_notify_head
         mov     r1, #THREAD_NOTIFY_SWITCH
         bl      atomic_notifier_call_chain
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+        str     r7, [r8]
+#endif
  THUMB( mov     ip, r4                     )
         mov     r0, r5
  ARM(   ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
@@ -1005,17 +1009,12 @@ kuser_cmpxchg_fixup:
  */
 
 __kuser_get_tls:                                @ 0xffff0fe0
-
-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
-        ldr     r0, [pc, #(16 - 8)]             @ TLS stored at 0xffff0ff0
-#else
-        mrc     p15, 0, r0, c13, c0, 3          @ read TLS register
-#endif
+        ldr     r0, [pc, #(16 - 8)]     @ read TLS, set in kuser_get_tls_init
         usr_ret lr
-
-        .rep    5
-        .word   0                       @ pad up to __kuser_helper_version
-        .endr
+        mrc     p15, 0, r0, c13, c0, 3  @ 0xffff0fe8 hardware TLS code
+        .rep    4
+        .word   0                       @ 0xffff0ff0 software TLS value, then
+        .endr                           @ pad up to __kuser_helper_version
 
 /*
  * Reference declaration:
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3b3d2c80509c..c0d5c3b3a760 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -47,12 +47,14 @@
 #define irq_finish(irq) do { } while (0)
 #endif
 
+unsigned int arch_nr_irqs;
 void (*init_arch_irq)(void) __initdata = NULL;
 unsigned long irq_err_count;
 
 int show_interrupts(struct seq_file *p, void *v)
 {
         int i = *(loff_t *) v, cpu;
+        struct irq_desc *desc;
         struct irqaction * action;
         unsigned long flags;
 
@@ -67,24 +69,25 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_putc(p, '\n');
         }
 
-        if (i < NR_IRQS) {
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
+        if (i < nr_irqs) {
+                desc = irq_to_desc(i);
+                raw_spin_lock_irqsave(&desc->lock, flags);
+                action = desc->action;
                 if (!action)
                         goto unlock;
 
                 seq_printf(p, "%3d: ", i);
                 for_each_present_cpu(cpu)
                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-                seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
+                seq_printf(p, " %10s", desc->chip->name ? : "-");
                 seq_printf(p, "  %s", action->name);
                 for (action = action->next; action; action = action->next)
                         seq_printf(p, ", %s", action->name);
 
                 seq_putc(p, '\n');
 unlock:
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == NR_IRQS) {
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
+        } else if (i == nr_irqs) {
 #ifdef CONFIG_FIQ
                 show_fiq_list(p, v);
 #endif
@@ -112,7 +115,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
          * Some hardware gives randomly wrong interrupts.  Rather
          * than crashing, do something sensible.
          */
-        if (unlikely(irq >= NR_IRQS)) {
+        if (unlikely(irq >= nr_irqs)) {
                 if (printk_ratelimit())
                         printk(KERN_WARNING "Bad IRQ%u\n", irq);
                 ack_bad_irq(irq);
@@ -132,12 +135,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
         struct irq_desc *desc;
         unsigned long flags;
 
-        if (irq >= NR_IRQS) {
+        if (irq >= nr_irqs) {
                 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
                 return;
         }
 
-        desc = irq_desc + irq;
+        desc = irq_to_desc(irq);
         raw_spin_lock_irqsave(&desc->lock, flags);
         desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
         if (iflags & IRQF_VALID)
@@ -151,14 +154,25 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
 
 void __init init_IRQ(void)
 {
+        struct irq_desc *desc;
         int irq;
 
-        for (irq = 0; irq < NR_IRQS; irq++)
-                irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+        for (irq = 0; irq < nr_irqs; irq++) {
+                desc = irq_to_desc_alloc_node(irq, 0);
+                desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+        }
 
         init_arch_irq();
 }
 
+#ifdef CONFIG_SPARSE_IRQ
+int __init arch_probe_nr_irqs(void)
+{
+        nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
+        return 0;
+}
+#endif
+
 #ifdef CONFIG_HOTPLUG_CPU
 
 static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
@@ -178,10 +192,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 void migrate_irqs(void)
 {
         unsigned int i, cpu = smp_processor_id();
+        struct irq_desc *desc;
 
-        for (i = 0; i < NR_IRQS; i++) {
-                struct irq_desc *desc = irq_desc + i;
-
+        for_each_irq_desc(i, desc) {
                 if (desc->node == cpu) {
                         unsigned int newcpu = cpumask_any_and(desc->affinity,
                                                               cpu_online_mask);
diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c
index c868a8864117..778c2f7024ff 100644
--- a/arch/arm/kernel/kgdb.c
+++ b/arch/arm/kernel/kgdb.c
@@ -10,57 +10,62 @@
  *           Deepak Saxena <dsaxena@plexity.net>
  */
 #include <linux/irq.h>
+#include <linux/kdebug.h>
 #include <linux/kgdb.h>
 #include <asm/traps.h>
 
-/* Make a local copy of the registers passed into the handler (bletch) */
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs)
+struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
 {
-        int regno;
-
-        /* Initialize all to zero. */
-        for (regno = 0; regno < GDB_MAX_REGS; regno++)
-                gdb_regs[regno] = 0;
+        { "r0", 4, offsetof(struct pt_regs, ARM_r0)},
+        { "r1", 4, offsetof(struct pt_regs, ARM_r1)},
+        { "r2", 4, offsetof(struct pt_regs, ARM_r2)},
+        { "r3", 4, offsetof(struct pt_regs, ARM_r3)},
+        { "r4", 4, offsetof(struct pt_regs, ARM_r4)},
+        { "r5", 4, offsetof(struct pt_regs, ARM_r5)},
+        { "r6", 4, offsetof(struct pt_regs, ARM_r6)},
+        { "r7", 4, offsetof(struct pt_regs, ARM_r7)},
+        { "r8", 4, offsetof(struct pt_regs, ARM_r8)},
+        { "r9", 4, offsetof(struct pt_regs, ARM_r9)},
+        { "r10", 4, offsetof(struct pt_regs, ARM_r10)},
+        { "fp", 4, offsetof(struct pt_regs, ARM_fp)},
+        { "ip", 4, offsetof(struct pt_regs, ARM_ip)},
+        { "sp", 4, offsetof(struct pt_regs, ARM_sp)},
+        { "lr", 4, offsetof(struct pt_regs, ARM_lr)},
+        { "pc", 4, offsetof(struct pt_regs, ARM_pc)},
+        { "f0", 12, -1 },
+        { "f1", 12, -1 },
+        { "f2", 12, -1 },
+        { "f3", 12, -1 },
+        { "f4", 12, -1 },
+        { "f5", 12, -1 },
+        { "f6", 12, -1 },
+        { "f7", 12, -1 },
+        { "fps", 4, -1 },
+        { "cpsr", 4, offsetof(struct pt_regs, ARM_cpsr)},
+};
 
-        gdb_regs[_R0]           = kernel_regs->ARM_r0;
-        gdb_regs[_R1]           = kernel_regs->ARM_r1;
-        gdb_regs[_R2]           = kernel_regs->ARM_r2;
-        gdb_regs[_R3]           = kernel_regs->ARM_r3;
-        gdb_regs[_R4]           = kernel_regs->ARM_r4;
-        gdb_regs[_R5]           = kernel_regs->ARM_r5;
-        gdb_regs[_R6]           = kernel_regs->ARM_r6;
-        gdb_regs[_R7]           = kernel_regs->ARM_r7;
-        gdb_regs[_R8]           = kernel_regs->ARM_r8;
-        gdb_regs[_R9]           = kernel_regs->ARM_r9;
-        gdb_regs[_R10]          = kernel_regs->ARM_r10;
-        gdb_regs[_FP]           = kernel_regs->ARM_fp;
-        gdb_regs[_IP]           = kernel_regs->ARM_ip;
-        gdb_regs[_SPT]          = kernel_regs->ARM_sp;
-        gdb_regs[_LR]           = kernel_regs->ARM_lr;
-        gdb_regs[_PC]           = kernel_regs->ARM_pc;
-        gdb_regs[_CPSR]         = kernel_regs->ARM_cpsr;
+char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
+{
+        if (regno >= DBG_MAX_REG_NUM || regno < 0)
+                return NULL;
+
+        if (dbg_reg_def[regno].offset != -1)
+                memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
+                       dbg_reg_def[regno].size);
+        else
+                memset(mem, 0, dbg_reg_def[regno].size);
+        return dbg_reg_def[regno].name;
 }
 
-/* Copy local gdb registers back to kgdb regs, for later copy to kernel */
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *kernel_regs)
+int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
 {
-        kernel_regs->ARM_r0     = gdb_regs[_R0];
-        kernel_regs->ARM_r1     = gdb_regs[_R1];
-        kernel_regs->ARM_r2     = gdb_regs[_R2];
-        kernel_regs->ARM_r3     = gdb_regs[_R3];
-        kernel_regs->ARM_r4     = gdb_regs[_R4];
-        kernel_regs->ARM_r5     = gdb_regs[_R5];
-        kernel_regs->ARM_r6     = gdb_regs[_R6];
-        kernel_regs->ARM_r7     = gdb_regs[_R7];
-        kernel_regs->ARM_r8     = gdb_regs[_R8];
-        kernel_regs->ARM_r9     = gdb_regs[_R9];
-        kernel_regs->ARM_r10    = gdb_regs[_R10];
-        kernel_regs->ARM_fp     = gdb_regs[_FP];
-        kernel_regs->ARM_ip     = gdb_regs[_IP];
-        kernel_regs->ARM_sp     = gdb_regs[_SPT];
-        kernel_regs->ARM_lr     = gdb_regs[_LR];
-        kernel_regs->ARM_pc     = gdb_regs[_PC];
-        kernel_regs->ARM_cpsr   = gdb_regs[_CPSR];
+        if (regno >= DBG_MAX_REG_NUM || regno < 0)
+                return -EINVAL;
+
+        if (dbg_reg_def[regno].offset != -1)
+                memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
+                       dbg_reg_def[regno].size);
+        return 0;
 }
 
 void
@@ -176,6 +181,33 @@ void kgdb_roundup_cpus(unsigned long flags)
        local_irq_disable();
 }
 
+static int __kgdb_notify(struct die_args *args, unsigned long cmd)
+{
+        struct pt_regs *regs = args->regs;
+
+        if (kgdb_handle_exception(1, args->signr, cmd, regs))
+                return NOTIFY_DONE;
+        return NOTIFY_STOP;
+}
+static int
+kgdb_notify(struct notifier_block *self, unsigned long cmd, void *ptr)
+{
+        unsigned long flags;
+        int ret;
+
+        local_irq_save(flags);
+        ret = __kgdb_notify(ptr, cmd);
+        local_irq_restore(flags);
+
+        return ret;
+}
+
+static struct notifier_block kgdb_notifier = {
+        .notifier_call  = kgdb_notify,
+        .priority       = -INT_MAX,
+};
+
+
 /**
  *      kgdb_arch_init - Perform any architecture specific initalization.
  *
@@ -184,6 +216,11 @@ void kgdb_roundup_cpus(unsigned long flags)
  */
 int kgdb_arch_init(void)
 {
+        int ret = register_die_notifier(&kgdb_notifier);
+
+        if (ret != 0)
+                return ret;
+
         register_undef_hook(&kgdb_brkpt_hook);
         register_undef_hook(&kgdb_compiled_brkpt_hook);
 
@@ -200,6 +237,7 @@ void kgdb_arch_exit(void)
 {
         unregister_undef_hook(&kgdb_brkpt_hook);
         unregister_undef_hook(&kgdb_compiled_brkpt_hook);
+        unregister_die_notifier(&kgdb_notifier);
 }
 
 /*
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 598ca61e7bca..1fc74cbd1a19 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -37,12 +37,12 @@ void machine_kexec_cleanup(struct kimage *image)
 {
 }
 
-void machine_shutdown(void)
-{
-}
-
 void machine_crash_shutdown(struct pt_regs *regs)
 {
+        local_irq_disable();
+        crash_save_cpu(regs, smp_processor_id());
+
+        printk(KERN_INFO "Loading crashdump kernel...\n");
 }
 
 void machine_kexec(struct kimage *image)
@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image)
                            (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
         printk(KERN_INFO "Bye!\n");
 
-        cpu_proc_fin();
+        local_irq_disable();
+        local_fiq_disable();
         setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
+        flush_cache_all();
+        cpu_proc_fin();
+        flush_cache_all();
         cpu_reset(reboot_code_buffer_phys);
 }
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index de12536d687f..417c392ddf1c 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -164,20 +164,20 @@ armpmu_event_set_period(struct perf_event *event,
                         struct hw_perf_event *hwc,
                         int idx)
 {
-        s64 left = atomic64_read(&hwc->period_left);
+        s64 left = local64_read(&hwc->period_left);
         s64 period = hwc->sample_period;
         int ret = 0;
 
         if (unlikely(left <= -period)) {
                 left = period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
 
         if (unlikely(left <= 0)) {
                 left += period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
@@ -185,7 +185,7 @@ armpmu_event_set_period(struct perf_event *event,
         if (left > (s64)armpmu->max_period)
                 left = armpmu->max_period;
 
-        atomic64_set(&hwc->prev_count, (u64)-left);
+        local64_set(&hwc->prev_count, (u64)-left);
 
         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 
@@ -204,18 +204,18 @@ armpmu_event_update(struct perf_event *event,
         u64 delta;
 
 again:
-        prev_raw_count = atomic64_read(&hwc->prev_count);
+        prev_raw_count = local64_read(&hwc->prev_count);
         new_raw_count = armpmu->read_counter(idx);
 
-        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
                              new_raw_count) != prev_raw_count)
                 goto again;
 
         delta = (new_raw_count << shift) - (prev_raw_count << shift);
         delta >>= shift;
 
-        atomic64_add(delta, &event->count);
-        atomic64_sub(delta, &hwc->period_left);
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
 
         return new_raw_count;
 }
@@ -478,7 +478,7 @@ __hw_perf_event_init(struct perf_event *event)
         if (!hwc->sample_period) {
                 hwc->sample_period  = armpmu->max_period;
                 hwc->last_period    = hwc->sample_period;
-                atomic64_set(&hwc->period_left, hwc->sample_period);
+                local64_set(&hwc->period_left, hwc->sample_period);
         }
 
         err = 0;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index a4a9cc88bec7..401e38be1f78 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -28,7 +28,9 @@
 #include <linux/tick.h>
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
+#include <linux/random.h>
 
+#include <asm/cacheflush.h>
 #include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/system.h>
@@ -36,6 +38,12 @@
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
 
+#ifdef CONFIG_CC_STACKPROTECTOR
+#include <linux/stackprotector.h>
+unsigned long __stack_chk_guard __read_mostly;
+EXPORT_SYMBOL(__stack_chk_guard);
+#endif
+
 static const char *processor_modes[] = {
   "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
   "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -84,10 +92,9 @@ __setup("hlt", hlt_setup);
 
 void arm_machine_restart(char mode, const char *cmd)
 {
-        /*
-         * Clean and disable cache, and turn off interrupts
-         */
-        cpu_proc_fin();
+        /* Disable interrupts first */
+        local_irq_disable();
+        local_fiq_disable();
 
         /*
          * Tell the mm system that we are going to reboot -
@@ -96,6 +103,15 @@ void arm_machine_restart(char mode, const char *cmd)
          */
         setup_mm_for_reboot(mode);
 
+        /* Clean and invalidate caches */
+        flush_cache_all();
+
+        /* Turn off caching */
+        cpu_proc_fin();
+
+        /* Push out any further dirty data, and ensure cache is empty */
+        flush_cache_all();
+
         /*
          * Now call the architecture specific reboot code.
          */
@@ -189,19 +205,29 @@ int __init reboot_setup(char *str)
 
 __setup("reboot=", reboot_setup);
 
-void machine_halt(void)
+void machine_shutdown(void)
 {
+#ifdef CONFIG_SMP
+        smp_send_stop();
+#endif
 }
 
+void machine_halt(void)
+{
+        machine_shutdown();
+        while (1);
+}
 
 void machine_power_off(void)
 {
+        machine_shutdown();
         if (pm_power_off)
                 pm_power_off();
 }
 
 void machine_restart(char *cmd)
 {
+        machine_shutdown();
         arm_pm_restart(reboot_mode, cmd);
 }
 
@@ -426,3 +452,9 @@ unsigned long get_wchan(struct task_struct *p)
         } while (count ++ < 16);
         return 0;
 }
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+        unsigned long range_end = mm->brk + 0x02000000;
+        return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
+}
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3f562a7c0a99..f99d489822d5 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -52,6 +52,102 @@
 #define BREAKINST_THUMB 0xde01
 #endif
 
+struct pt_regs_offset {
+        const char *name;
+        int offset;
+};
+
+#define REG_OFFSET_NAME(r) \
+        {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+static const struct pt_regs_offset regoffset_table[] = {
+        REG_OFFSET_NAME(r0),
+        REG_OFFSET_NAME(r1),
+        REG_OFFSET_NAME(r2),
+        REG_OFFSET_NAME(r3),
+        REG_OFFSET_NAME(r4),
+        REG_OFFSET_NAME(r5),
+        REG_OFFSET_NAME(r6),
+        REG_OFFSET_NAME(r7),
+        REG_OFFSET_NAME(r8),
+        REG_OFFSET_NAME(r9),
+        REG_OFFSET_NAME(r10),
+        REG_OFFSET_NAME(fp),
+        REG_OFFSET_NAME(ip),
+        REG_OFFSET_NAME(sp),
+        REG_OFFSET_NAME(lr),
+        REG_OFFSET_NAME(pc),
+        REG_OFFSET_NAME(cpsr),
+        REG_OFFSET_NAME(ORIG_r0),
+        REG_OFFSET_END,
+};
+
+/**
+ * regs_query_register_offset() - query register offset from its name
+ * @name:       the name of a register
+ *
+ * regs_query_register_offset() returns the offset of a register in struct
+ * pt_regs from its name. If the name is invalid, this returns -EINVAL;
+ */
+int regs_query_register_offset(const char *name)
+{
+        const struct pt_regs_offset *roff;
+        for (roff = regoffset_table; roff->name != NULL; roff++)
+                if (!strcmp(roff->name, name))
+                        return roff->offset;
+        return -EINVAL;
+}
+
+/**
+ * regs_query_register_name() - query register name from its offset
+ * @offset:     the offset of a register in struct pt_regs.
+ *
+ * regs_query_register_name() returns the name of a register from its
+ * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
+ */
+const char *regs_query_register_name(unsigned int offset)
+{
+        const struct pt_regs_offset *roff;
+        for (roff = regoffset_table; roff->name != NULL; roff++)
+                if (roff->offset == offset)
+                        return roff->name;
+        return NULL;
+}
+
+/**
+ * regs_within_kernel_stack() - check the address in the stack
+ * @regs:      pt_regs which contains kernel stack pointer.
+ * @addr:      address which is checked.
+ *
+ * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
+ * If @addr is within the kernel stack, it returns true. If not, returns false.
+ */
+bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
+{
+        return ((addr & ~(THREAD_SIZE - 1))  ==
+                (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:       pt_regs which contains kernel stack pointer.
+ * @n:          stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specified by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
+{
+        unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+        addr += n;
+        if (regs_within_kernel_stack(regs, (unsigned long)addr))
+                return *addr;
+        else
+                return 0;
+}
+
 /*
  * this routine will get a word off of the processes privileged stack.
  * the offset is how far from the base addr as stored in the THREAD.
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 61930eb09029..fd26f8d65151 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -10,6 +10,12 @@ relocate_new_kernel:
         ldr     r0,kexec_indirection_page
         ldr     r1,kexec_start_address
 
+        /*
+         * If there is no indirection page (we are doing crashdumps)
+         * skip any relocation.
+         */
+        cmp     r0, #0
+        beq     2f
 
 0:      /* top, read another word for the indirection page */
         ldr     r3, [r0],#4
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999bdc7c..d5231ae7355a 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -19,12 +19,15 @@
 #include <linux/seq_file.h>
 #include <linux/screen_info.h>
 #include <linux/init.h>
+#include <linux/kexec.h>
+#include <linux/crash_dump.h>
 #include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <linux/fs.h>
 #include <linux/proc_fs.h>
+#include <linux/memblock.h>
 
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -44,7 +47,9 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
+#endif
 #include "atags.h"
 #include "tcm.h"
 
@@ -269,6 +274,21 @@ static void __init cacheid_init(void)
 extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
+static void __init feat_v6_fixup(void)
+{
+        int id = read_cpuid_id();
+
+        if ((id & 0xff0f0000) != 0x41070000)
+                return;
+
+        /*
+         * HWCAP_TLS is available only on 1136 r1p0 and later,
+         * see also kuser_get_tls_init.
+         */
+        if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
+                elf_hwcap &= ~HWCAP_TLS;
+}
+
 static void __init setup_processor(void)
 {
         struct proc_info_list *list;
@@ -311,6 +331,8 @@ static void __init setup_processor(void)
         elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+        feat_v6_fixup();
+
         cacheid_init();
         cpu_proc_init();
 }
@@ -402,13 +424,12 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
         size -= start & ~PAGE_MASK;
         bank->start = PAGE_ALIGN(start);
         bank->size  = size & PAGE_MASK;
-        bank->node  = PHYS_TO_NID(start);
 
         /*
          * Check whether this memory region has non-zero size or
          * invalid node number.
          */
-        if (bank->size == 0 || bank->node >= MAX_NUMNODES)
+        if (bank->size == 0)
                 return -EINVAL;
 
         meminfo.nr_banks++;
@@ -663,6 +684,86 @@ static int __init customize_machine(void)
 }
 arch_initcall(customize_machine);
 
+#ifdef CONFIG_KEXEC
+static inline unsigned long long get_total_mem(void)
+{
+        unsigned long total;
+
+        total = max_low_pfn - min_low_pfn;
+        return total << PAGE_SHIFT;
+}
+
+/**
+ * reserve_crashkernel() - reserves memory are for crash kernel
+ *
+ * This function reserves memory area given in "crashkernel=" kernel command
+ * line parameter. The memory reserved is used by a dump capture kernel when
+ * primary kernel is crashing.
+ */
+static void __init reserve_crashkernel(void)
+{
+        unsigned long long crash_size, crash_base;
+        unsigned long long total_mem;
+        int ret;
+
+        total_mem = get_total_mem();
+        ret = parse_crashkernel(boot_command_line, total_mem,
+                                &crash_size, &crash_base);
+        if (ret)
+                return;
+
+        ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
+        if (ret < 0) {
+                printk(KERN_WARNING "crashkernel reservation failed - "
+                       "memory is in use (0x%lx)\n", (unsigned long)crash_base);
+                return;
+        }
+
+        printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
+               "for crashkernel (System RAM: %ldMB)\n",
+               (unsigned long)(crash_size >> 20),
+               (unsigned long)(crash_base >> 20),
+               (unsigned long)(total_mem >> 20));
+
+        crashk_res.start = crash_base;
+        crashk_res.end = crash_base + crash_size - 1;
+        insert_resource(&iomem_resource, &crashk_res);
+}
+#else
+static inline void reserve_crashkernel(void) {}
+#endif /* CONFIG_KEXEC */
+
+/*
+ * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
+ * is_kdump_kernel() to determine if we are booting after a panic. Hence
+ * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
+ */
+
+#ifdef CONFIG_CRASH_DUMP
+/*
+ * elfcorehdr= specifies the location of elf core header stored by the crashed
+ * kernel. This option will be passed by kexec loader to the capture kernel.
+ */
+static int __init setup_elfcorehdr(char *arg)
+{
+        char *end;
+
+        if (!arg)
+                return -EINVAL;
+
+        elfcorehdr_addr = memparse(arg, &end);
+        return end > arg ? 0 : -EINVAL;
+}
+early_param("elfcorehdr", setup_elfcorehdr);
+#endif /* CONFIG_CRASH_DUMP */
+
+static void __init squash_mem_tags(struct tag *tag)
+{
+        for (; tag->hdr.size; tag = tag_next(tag))
+                if (tag->hdr.tag == ATAG_MEM)
+                        tag->hdr.tag = ATAG_NONE;
+}
+
 void __init setup_arch(char **cmdline_p)
 {
         struct tag *tags = (struct tag *)&init_tags;
@@ -683,12 +784,14 @@ void __init setup_arch(char **cmdline_p)
         else if (mdesc->boot_params)
                 tags = phys_to_virt(mdesc->boot_params);
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
         /*
          * If we have the old style parameters, convert them to
          * a tag list.
          */
         if (tags->hdr.tag != ATAG_CORE)
                 convert_to_tag_list(tags);
+#endif
         if (tags->hdr.tag != ATAG_CORE)
                 tags = (struct tag *)&init_tags;
 
@@ -716,12 +819,15 @@ void __init setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+        arm_memblock_init(&meminfo, mdesc);
+
         paging_init(mdesc);
         request_standard_resources(&meminfo, mdesc);
 
 #ifdef CONFIG_SMP
         smp_init_cpus();
 #endif
+        reserve_crashkernel();
 
         cpu_init();
         tcm_init();
@@ -729,6 +835,7 @@ void __init setup_arch(char **cmdline_p)
         /*
          * Set up various architecture-specific pointers
          */
+        arch_nr_irqs = mdesc->nr_irqs;
         init_arch_irq = mdesc->init_irq;
         system_timer = mdesc->timer;
         init_machine = mdesc->init_machine;
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index b8c3d0f689d9..40dc74f2b27f 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -429,7 +429,11 @@ static void smp_timer_broadcast(const struct cpumask *mask)
 {
         send_ipi_message(mask, IPI_TIMER);
 }
+#else
+#define smp_timer_broadcast     NULL
+#endif
 
+#ifndef CONFIG_LOCAL_TIMERS
 static void broadcast_timer_set_mode(enum clock_event_mode mode,
         struct clock_event_device *evt)
 {
@@ -444,7 +448,6 @@ static void local_timer_setup(struct clock_event_device *evt)
         evt->rating     = 400;
         evt->mult       = 1;
         evt->set_mode   = broadcast_timer_set_mode;
-        evt->broadcast  = smp_timer_broadcast;
 
         clockevents_register_device(evt);
 }
@@ -456,6 +459,7 @@ void __cpuinit percpu_timer_setup(void)
         struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 
         evt->cpumask = cpumask_of(cpu);
+        evt->broadcast = smp_timer_broadcast;
 
         local_timer_setup(evt);
 }
@@ -467,10 +471,13 @@ static DEFINE_SPINLOCK(stop_lock);
  */
 static void ipi_cpu_stop(unsigned int cpu)
 {
-        spin_lock(&stop_lock);
-        printk(KERN_CRIT "CPU%u: stopping\n", cpu);
-        dump_stack();
-        spin_unlock(&stop_lock);
+        if (system_state == SYSTEM_BOOTING ||
+            system_state == SYSTEM_RUNNING) {
+                spin_lock(&stop_lock);
+                printk(KERN_CRIT "CPU%u: stopping\n", cpu);
+                dump_stack();
+                spin_unlock(&stop_lock);
+        }
 
         set_cpu_online(cpu, false);
 
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 7c5f0c024db7..35882fbf37f9 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -132,7 +132,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
         twd_calibrate_rate();
 
         clk->name = "local_timer";
-        clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
+                        CLOCK_EVT_FEAT_C3STOP;
         clk->rating = 350;
         clk->set_mode = twd_set_mode;
         clk->set_next_event = twd_set_next_event;
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index e50303868f1b..26685c2f7a49 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -13,38 +13,35 @@
 #include <linux/ioport.h>
 #include <linux/genalloc.h>
 #include <linux/string.h> /* memcpy */
-#include <asm/page.h> /* PAGE_SHIFT */
 #include <asm/cputype.h>
 #include <asm/mach/map.h>
 #include <mach/memory.h>
 #include "tcm.h"
 
-/* Scream and warn about misuse */
-#if !defined(ITCM_OFFSET) || !defined(ITCM_END) || \
-    !defined(DTCM_OFFSET) || !defined(DTCM_END)
-#error "TCM support selected but offsets not defined!"
-#endif
-
 static struct gen_pool *tcm_pool;
 
 /* TCM section definitions from the linker */
 extern char __itcm_start, __sitcm_text, __eitcm_text;
 extern char __dtcm_start, __sdtcm_data, __edtcm_data;
 
+/* These will be increased as we run */
+u32 dtcm_end = DTCM_OFFSET;
+u32 itcm_end = ITCM_OFFSET;
+
 /*
  * TCM memory resources
  */
 static struct resource dtcm_res = {
         .name = "DTCM RAM",
         .start = DTCM_OFFSET,
-        .end = DTCM_END,
+        .end = DTCM_OFFSET,
         .flags = IORESOURCE_MEM
 };
 
 static struct resource itcm_res = {
         .name = "ITCM RAM",
         .start = ITCM_OFFSET,
-        .end = ITCM_END,
+        .end = ITCM_OFFSET,
         .flags = IORESOURCE_MEM
 };
 
@@ -52,8 +49,8 @@ static struct map_desc dtcm_iomap[] __initdata = {
         {
                 .virtual        = DTCM_OFFSET,
                 .pfn            = __phys_to_pfn(DTCM_OFFSET),
-                .length         = (DTCM_END - DTCM_OFFSET + 1),
-                .type           = MT_UNCACHED
+                .length         = 0,
+                .type           = MT_MEMORY_DTCM
         }
 };
 
@@ -61,8 +58,8 @@ static struct map_desc itcm_iomap[] __initdata = {
         {
                 .virtual        = ITCM_OFFSET,
                 .pfn            = __phys_to_pfn(ITCM_OFFSET),
-                .length         = (ITCM_END - ITCM_OFFSET + 1),
-                .type           = MT_UNCACHED
+                .length         = 0,
+                .type           = MT_MEMORY_ITCM
         }
 };
 
@@ -93,14 +90,24 @@ void tcm_free(void *addr, size_t len)
 }
 EXPORT_SYMBOL(tcm_free);
 
-
-static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
+static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
+                                  u32 *offset)
 {
         const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
                                     256, 512, 1024, -1, -1, -1, -1 };
         u32 tcm_region;
         int tcm_size;
 
+        /*
+         * If there are more than one TCM bank of this type,
+         * select the TCM bank to operate on in the TCM selection
+         * register.
+         */
+        if (banks > 1)
+                asm("mcr        p15, 0, %0, c9, c2, 0"
+                    : /* No output operands */
+                    : "r" (bank));
+
         /* Read the special TCM region register c9, 0 */
         if (!type)
                 asm("mrc        p15, 0, %0, c9, c1, 0"
@@ -111,26 +118,24 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
 
         tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
         if (tcm_size < 0) {
-                pr_err("CPU: %sTCM of unknown size!\n",
-                        type ? "I" : "D");
+                pr_err("CPU: %sTCM%d of unknown size\n",
+                       type ? "I" : "D", bank);
+                return -EINVAL;
+        } else if (tcm_size > 32) {
+                pr_err("CPU: %sTCM%d larger than 32k found\n",
+                       type ? "I" : "D", bank);
+                return -EINVAL;
         } else {
-                pr_info("CPU: found %sTCM %dk @ %08x, %senabled\n",
+                pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
                         type ? "I" : "D",
+                        bank,
                         tcm_size,
                         (tcm_region & 0xfffff000U),
                         (tcm_region & 1) ? "" : "not ");
         }
 
-        if (tcm_size != expected_size) {
-                pr_crit("CPU: %sTCM was detected %dk but expected %dk!\n",
-                       type ? "I" : "D",
-                       tcm_size,
-                       expected_size);
-                /* Adjust to the expected size? what can we do... */
-        }
-
         /* Force move the TCM bank to where we want it, enable */
-        tcm_region = offset | (tcm_region & 0x00000ffeU) | 1;
+        tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
 
         if (!type)
                 asm("mcr        p15, 0, %0, c9, c1, 0"
@@ -141,10 +146,15 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
                     : /* No output operands */
                     : "r" (tcm_region));
 
-        pr_debug("CPU: moved %sTCM %dk to %08x, enabled\n",
-                 type ? "I" : "D",
-                 tcm_size,
-                 (tcm_region & 0xfffff000U));
+        /* Increase offset */
+        *offset += (tcm_size << 10);
+
+        pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
+                type ? "I" : "D",
+                bank,
+                tcm_size,
+                (tcm_region & 0xfffff000U));
+        return 0;
 }
 
 /*
@@ -153,34 +163,52 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
 void __init tcm_init(void)
 {
         u32 tcm_status = read_cpuid_tcmstatus();
+        u8 dtcm_banks = (tcm_status >> 16) & 0x03;
+        u8 itcm_banks = (tcm_status & 0x03);
         char *start;
         char *end;
         char *ram;
+        int ret;
+        int i;
 
         /* Setup DTCM if present */
-        if (tcm_status & (1 << 16)) {
-                setup_tcm_bank(0, DTCM_OFFSET,
-                               (DTCM_END - DTCM_OFFSET + 1) >> 10);
+        if (dtcm_banks > 0) {
+                for (i = 0; i < dtcm_banks; i++) {
+                        ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
+                        if (ret)
+                                return;
+                }
+                dtcm_res.end = dtcm_end - 1;
                 request_resource(&iomem_resource, &dtcm_res);
+                dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
                 iotable_init(dtcm_iomap, 1);
                 /* Copy data from RAM to DTCM */
                 start = &__sdtcm_data;
                 end   = &__edtcm_data;
                 ram   = &__dtcm_start;
+                /* This means you compiled more code than fits into DTCM */
+                BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET));
                 memcpy(start, ram, (end-start));
                 pr_debug("CPU DTCM: copied data from %p - %p\n", start, end);
         }
 
         /* Setup ITCM if present */
-        if (tcm_status & 1) {
-                setup_tcm_bank(1, ITCM_OFFSET,
-                               (ITCM_END - ITCM_OFFSET + 1) >> 10);
+        if (itcm_banks > 0) {
+                for (i = 0; i < itcm_banks; i++) {
+                        ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
+                        if (ret)
+                                return;
+                }
+                itcm_res.end = itcm_end - 1;
                 request_resource(&iomem_resource, &itcm_res);
+                itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
                 iotable_init(itcm_iomap, 1);
                 /* Copy code from RAM to ITCM */
                 start = &__sitcm_text;
                 end   = &__eitcm_text;
                 ram   = &__itcm_start;
+                /* This means you compiled more code than fits into ITCM */
+                BUG_ON((end - start) > (itcm_end - ITCM_OFFSET));
                 memcpy(start, ram, (end-start));
                 pr_debug("CPU ITCM: copied code from %p - %p\n", start, end);
         }
@@ -208,10 +236,10 @@ static int __init setup_tcm_pool(void)
         pr_debug("Setting up TCM memory pool\n");
 
         /* Add the rest of DTCM to the TCM pool */
-        if (tcm_status & (1 << 16)) {
-                if (dtcm_pool_start < DTCM_END) {
+        if (tcm_status & (0x03 << 16)) {
+                if (dtcm_pool_start < dtcm_end) {
                         ret = gen_pool_add(tcm_pool, dtcm_pool_start,
-                                           DTCM_END - dtcm_pool_start + 1, -1);
+                                           dtcm_end - dtcm_pool_start, -1);
                         if (ret) {
                                 pr_err("CPU DTCM: could not add DTCM " \
                                        "remainder to pool!\n");
@@ -219,16 +247,16 @@ static int __init setup_tcm_pool(void)
                         }
                         pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
                                  "the TCM memory pool\n",
-                                 DTCM_END - dtcm_pool_start + 1,
+                                 dtcm_end - dtcm_pool_start,
                                  dtcm_pool_start);
                 }
         }
 
         /* Add the rest of ITCM to the TCM pool */
-        if (tcm_status & 1) {
-                if (itcm_pool_start < ITCM_END) {
+        if (tcm_status & 0x03) {
+                if (itcm_pool_start < itcm_end) {
                         ret = gen_pool_add(tcm_pool, itcm_pool_start,
-                                           ITCM_END - itcm_pool_start + 1, -1);
+                                           itcm_end - itcm_pool_start, -1);
                         if (ret) {
                                 pr_err("CPU ITCM: could not add ITCM " \
                                        "remainder to pool!\n");
@@ -236,7 +264,7 @@ static int __init setup_tcm_pool(void)
                         }
                         pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
                                  "the TCM memory pool\n",
-                                 ITCM_END - itcm_pool_start + 1,
+                                 itcm_end - itcm_pool_start,
                                  itcm_pool_start);
                 }
         }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e5327b2a..cda78d59aa31 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -30,6 +30,7 @@
 #include <asm/unistd.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
+#include <asm/tls.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 
         case NR(set_tls):
                 thread->tp_value = regs->ARM_r0;
-#if defined(CONFIG_HAS_TLS_REG)
-                asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
-#elif !defined(CONFIG_TLS_REG_EMUL)
-                /*
-                 * User space must never try to access this directly.
-                 * Expect your app to break eventually if you do so.
-                 * The user helper at 0xffff0fe0 must be used instead.
-                 * (see entry-armv.S for details)
-                 */
-                *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
-#endif
+                if (tls_emu)
+                        return 0;
+                if (has_tls_reg) {
+                        asm ("mcr p15, 0, %0, c13, c0, 3"
+                                : : "r" (regs->ARM_r0));
+                } else {
+                        /*
+                         * User space must never try to access this directly.
+                         * Expect your app to break eventually if you do so.
+                         * The user helper at 0xffff0fe0 must be used instead.
+                         * (see entry-armv.S for details)
+                         */
+                        *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
+                }
                 return 0;
 
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
@@ -743,6 +747,16 @@ void __init trap_init(void)
         return;
 }
 
+static void __init kuser_get_tls_init(unsigned long vectors)
+{
+        /*
+         * vectors + 0xfe0 = __kuser_get_tls
+         * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
+         */
+        if (tls_emu || has_tls_reg)
+                memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
+}
+
 void __init early_trap_init(void)
 {
         unsigned long vectors = CONFIG_VECTORS_BASE;
@@ -761,6 +775,11 @@ void __init early_trap_init(void)
         memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
 
         /*
+         * Do processor specific fixups for the kuser helpers
+         */
+        kuser_get_tls_init(vectors);
+
+        /*
          * Copy signal return handlers into the vector page, and
          * set sigreturn to be a pointer to these.
          */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 030ba7219f48..59ff42ddf0ae 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -41,7 +41,6 @@ else
 endif
 
 lib-$(CONFIG_ARCH_RPC)          += ecard.o io-acorn.o floppydma.o
-lib-$(CONFIG_ARCH_L7200)        += io-acorn.o
 lib-$(CONFIG_ARCH_SHARK)        += io-shark.o
 
 $(obj)/csumpartialcopy.o:       $(obj)/csumpartialcopygeneric.S
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index 59ff6fdc1e63..7d08b43d2c0e 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -71,7 +71,7 @@
                 .pushsection .fixup,"ax"
                 .align  4
 9001:           mov     r4, #-EFAULT
-                ldr     r5, [fp, #4]            @ *err_ptr
+                ldr     r5, [sp, #8*4]          @ *err_ptr
                 str     r4, [r5]
                 ldmia   sp, {r1, r2}            @ retrieve dst, len
                 add     r2, r2, r1
diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h
index c00822543d9f..4f93c567a35a 100644
--- a/arch/arm/mach-aaec2000/include/mach/memory.h
+++ b/arch/arm/mach-aaec2000/include/mach/memory.h
@@ -14,14 +14,4 @@
 
 #define PHYS_OFFSET     UL(0xf0000000)
 
-/*
- * The nodes are the followings:
- *
- *   node 0: 0xf000.0000 - 0xf3ff.ffff
- *   node 1: 0xf400.0000 - 0xf7ff.ffff
- *   node 2: 0xf800.0000 - 0xfbff.ffff
- *   node 3: 0xfc00.0000 - 0xffff.ffff
- */
-#define NODE_MEM_SIZE_BITS      26
-
 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 841eaf8f27e2..939bccd70569 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
 
 endif
 
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
 # ----------------------------------------------------------
 
 if ARCH_AT91SAM9G45
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1f821e58222..ca2ac003f41f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20)	+= board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 
+# AT91SAM9260/AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
+
 # AT91SAM9G45 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 85166b7e69a1..753c0d31a3d3 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,6 +20,7 @@
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -176,6 +177,13 @@ static struct clk mmc1_clk = {
         .type           = CLK_TYPE_PERIPHERAL,
 };
 
+/* Video decoder clock - Only for sam9m10/sam9m11 */
+static struct clk vdec_clk = {
+        .name           = "vdec_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
 /* One additional fake clock for ohci */
 static struct clk ohci_clk = {
         .name           = "ohci_clk",
@@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
+                clk_register(&vdec_clk);
+
         clk_register(&pck0);
         clk_register(&pck1);
 }
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
index a4102d72cc9b..c49f5c003ee1 100644
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
@@ -26,6 +26,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/at73c213.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = {
         }
 };
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+        REGULATOR_SUPPLY("AVDD", "0-001b"),
+        REGULATOR_SUPPLY("HPVDD", "0-001b"),
+        REGULATOR_SUPPLY("DBVDD", "0-001b"),
+        REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+        .constraints    = {
+                .name   = "3V3",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .consumer_supplies = ek_audio_consumer_supplies,
+        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+        .supply_name    = "board-3V3",
+        .microvolts     = 3300000,
+        .gpio           = -EINVAL,
+        .enabled_at_boot = 0,
+        .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_vdd_pdata,
+        },
+};
+static void __init ek_add_regulators(void)
+{
+        platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("24c512", 0x50),
@@ -256,6 +299,8 @@ static void __init ek_board_init(void)
         ek_add_device_nand();
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
+        /* Regulators */
+        ek_add_regulators();
         /* MMC */
 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
         at91_add_device_mci(0, &ek_mmc_data);
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index c11fd47aec5d..6ea9808b8868 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -27,6 +27,9 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void)
 static void __init ek_add_device_buttons(void) {}
 #endif
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+        REGULATOR_SUPPLY("AVDD", "0-001b"),
+        REGULATOR_SUPPLY("HPVDD", "0-001b"),
+        REGULATOR_SUPPLY("DBVDD", "0-001b"),
+        REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+        .constraints    = {
+                .name   = "3V3",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .consumer_supplies = ek_audio_consumer_supplies,
+        .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+        .supply_name    = "board-3V3",
+        .microvolts     = 3300000,
+        .gpio           = -EINVAL,
+        .enabled_at_boot = 0,
+        .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_vdd_pdata,
+        },
+};
+static void __init ek_add_regulators(void)
+{
+        platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
         {
@@ -294,6 +337,8 @@ static void __init ek_board_init(void)
         ek_add_device_nand();
         /* Ethernet */
         at91_add_device_eth(&ek_macb_data);
+        /* Regulators */
+        ek_add_regulators();
         /* MMC */
         at91_add_device_mmc(0, &ek_mmc_data);
         /* I2C */
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644
index 000000000000..2c08ae4ad3a1
--- /dev/null
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-at91/board-snapper9260.c
+ *
+ *  Copyright (C) 2010 Bluewater System Ltd
+ *
+ * Author: Andre Renaud <andre@bluewatersys.com>
+ * Author: Ryan Mallon  <ryan@bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+#define SNAPPER9260_IO_EXP_GPIO(x)      (NR_BUILTIN_GPIO + (x))
+
+static void __init snapper9260_map_io(void)
+{
+        at91sam9260_initialize(18432000);
+
+        /* Debug on ttyS0 */
+        at91_register_uart(0, 0, 0);
+        at91_set_serial_console(0);
+
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                           ATMEL_UART_CTS | ATMEL_UART_RTS);
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                           ATMEL_UART_CTS | ATMEL_UART_RTS);
+        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
+}
+
+static void __init snapper9260_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+static struct at91_usbh_data __initdata snapper9260_usbh_data = {
+        .ports          = 2,
+};
+
+static struct at91_udc_data __initdata snapper9260_udc_data = {
+        .vbus_pin               = SNAPPER9260_IO_EXP_GPIO(5),
+        .vbus_active_low        = 1,
+        .vbus_polled            = 1,
+};
+
+static struct at91_eth_data snapper9260_macb_data = {
+        .is_rmii        = 1,
+};
+
+static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
+        {
+                .name   = "Preboot",
+                .offset = 0,
+                .size   = SZ_128K,
+        },
+        {
+                .name   = "Bootloader",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = SZ_256K,
+        },
+        {
+                .name   = "Environment",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = SZ_128K,
+        },
+        {
+                .name   = "Kernel",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = SZ_4M,
+        },
+        {
+                .name   = "Filesystem",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init
+snapper9260_nand_partition_info(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
+        return snapper9260_nand_partitions;
+}
+
+static struct atmel_nand_data __initdata snapper9260_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC13,
+        .partition_info = snapper9260_nand_partition_info,
+        .bus_width_16   = 0,
+};
+
+static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 0,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 0,
+
+        .ncs_read_pulse         = 5,
+        .nrd_pulse              = 2,
+        .ncs_write_pulse        = 5,
+        .nwe_pulse              = 2,
+
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+
+        .mode                   = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+                                   AT91_SMC_EXNWMODE_DISABLE),
+        .tdf_cycles             = 1,
+};
+
+static struct pca953x_platform_data snapper9260_io_expander_data = {
+        .gpio_base              = SNAPPER9260_IO_EXP_GPIO(0),
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
+        {
+                /* IO expander */
+                I2C_BOARD_INFO("max7312", 0x28),
+                .platform_data = &snapper9260_io_expander_data,
+        },
+        {
+                /* Audio codec */
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+        {
+                /* RTC */
+                I2C_BOARD_INFO("isl1208", 0x6f),
+        },
+};
+
+static void __init snapper9260_add_device_nand(void)
+{
+        at91_set_A_periph(AT91_PIN_PC14, 0);
+        sam9_smc_configure(3, &snapper9260_nand_smc_config);
+        at91_add_device_nand(&snapper9260_nand_data);
+}
+
+static void __init snapper9260_board_init(void)
+{
+        at91_add_device_i2c(snapper9260_i2c_devices,
+                            ARRAY_SIZE(snapper9260_i2c_devices));
+        at91_add_device_serial();
+        at91_add_device_usbh(&snapper9260_usbh_data);
+        at91_add_device_udc(&snapper9260_udc_data);
+        at91_add_device_eth(&snapper9260_macb_data);
+        at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
+                                                 ATMEL_SSC_TD | ATMEL_SSC_RD));
+        snapper9260_add_device_nand();
+}
+
+MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = snapper9260_map_io,
+        .init_irq       = snapper9260_init_irq,
+        .init_machine   = snapper9260_board_init,
+MACHINE_END
+
+
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index d8c1ededaa75..9c6af9737485 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -84,7 +84,7 @@
  */
 #define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
 #define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC    (0xffffe600 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
 #define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
index 1499b1cbffdd..976f4a6c3353 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -15,7 +15,7 @@
 #ifndef AT91CAP9_DDRSDR_H
 #define AT91CAP9_DDRSDR_H
 
-#define AT91_DDRSDRC_MR         (AT91_DDRSDRC + 0x00)   /* Mode Register */
+#define AT91_DDRSDRC_MR         0x00    /* Mode Register */
 #define         AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
 #define                 AT91_DDRSDRC_MODE_NORMAL                0
 #define                 AT91_DDRSDRC_MODE_NOP           1
@@ -25,10 +25,10 @@
 #define                 AT91_DDRSDRC_MODE_EXT_LMR       5
 #define                 AT91_DDRSDRC_MODE_DEEP          6
 
-#define AT91_DDRSDRC_RTR        (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
+#define AT91_DDRSDRC_RTR        0x04    /* Refresh Timer Register */
 #define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_DDRSDRC_CR         (AT91_DDRSDRC + 0x08)   /* Configuration Register */
+#define AT91_DDRSDRC_CR         0x08    /* Configuration Register */
 #define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
 #define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
 #define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
@@ -49,7 +49,7 @@
 #define         AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
 #define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
 
-#define AT91_DDRSDRC_T0PR       (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
+#define AT91_DDRSDRC_T0PR       0x0C    /* Timing 0 Register */
 #define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
 #define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
 #define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
@@ -59,13 +59,13 @@
 #define         AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
 #define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
 
-#define AT91_DDRSDRC_T1PR       (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
+#define AT91_DDRSDRC_T1PR       0x10    /* Timing 1 Register */
 #define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
 #define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
 #define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
 #define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
 
-#define AT91_DDRSDRC_LPR        (AT91_DDRSDRC + 0x18)   /* Low Power Register */
+#define AT91_DDRSDRC_LPR        0x18    /* Low Power Register */
 #define         AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
 #define                 AT91_DDRSDRC_LPCB_DISABLE               0
 #define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
@@ -80,14 +80,14 @@
 #define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
 #define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
 
-#define AT91_DDRSDRC_MDR        (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
+#define AT91_DDRSDRC_MDR        0x1C    /* Memory Device Register */
 #define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
 #define                 AT91_DDRSDRC_MD_SDR             0
 #define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
 #define                 AT91_DDRSDRC_MD_DDR             2
 #define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
 
-#define AT91_DDRSDRC_DLLR       (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
+#define AT91_DDRSDRC_DLLR       0x20    /* DLL Information Register */
 #define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 #define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 #define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
@@ -98,5 +98,11 @@
 #define         AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
 #define         AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+        at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+        at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 43c396b9b4cb..4e79036d3b80 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -84,7 +84,7 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 87de8be17484..2b5618518129 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,7 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
 #define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
new file mode 100644
index 000000000000..d27b15ba8ebf
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -0,0 +1,130 @@
+/*
+ * Header file for the Atmel DDR/SDR SDRAM Controller
+ *
+ * Copyright (C) 2010 Atmel Corporation
+ *      Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9_DDRSDR_H
+#define AT91SAM9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR         0x00    /* Mode Register */
+#define         AT91_DDRSDRC_MODE       (0x7 << 0)              /* Command Mode */
+#define                 AT91_DDRSDRC_MODE_NORMAL        0
+#define                 AT91_DDRSDRC_MODE_NOP           1
+#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                 AT91_DDRSDRC_MODE_LMR           3
+#define                 AT91_DDRSDRC_MODE_REFRESH       4
+#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                 AT91_DDRSDRC_MODE_DEEP          6
+
+#define AT91_DDRSDRC_RTR        0x04    /* Refresh Timer Register */
+#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR         0x08    /* Configuration Register */
+#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                 AT91_DDRSDRC_NR_11      (0 << 2)
+#define                 AT91_DDRSDRC_NR_12      (1 << 2)
+#define                 AT91_DDRSDRC_NR_13      (2 << 2)
+#define                 AT91_DDRSDRC_NR_14      (3 << 2)
+#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
+#define         AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
+#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+#define         AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL */
+#define         AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver */
+#define         AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared */
+#define         AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y */
+
+#define AT91_DDRSDRC_T0PR       0x0C    /* Timing 0 Register */
+#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define         AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
+#define         AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay */
+#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR       0x10    /* Timing 1 Register */
+#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+
+#define AT91_DDRSDRC_T2PR       0x14    /* Timing 2 Register */
+#define         AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
+#define         AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
+#define         AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
+#define         AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
+
+#define AT91_DDRSDRC_LPR        0x1C    /* Low Power Register */
+#define         AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
+#define                 AT91_DDRSDRC_LPCB_DISABLE               0
+#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define         AT91_DDRSDRC_CLKFR      (1 << 2)        /* Clock Frozen */
+#define         AT91_DDRSDRC_PASR       (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_DDRSDRC_TCSR       (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_DDRSDRC_DS         (3 << 10)       /* Drive Strength */
+#define         AT91_DDRSDRC_TIMEOUT    (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+#define         AT91_DDRSDRC_APDE       (1 << 16)        /* Active power down exit time */
+#define         AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
+
+#define AT91_DDRSDRC_MDR        0x20    /* Memory Device Register */
+#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                 AT91_DDRSDRC_MD_SDR             0
+#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+#define                 AT91_DDRSDRC_MD_DDR2            6
+#define         AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
+#define                 AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
+#define                 AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
+
+#define AT91_DDRSDRC_DLL        0x24    /* DLL Information Register */
+#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+
+#define AT91_DDRSDRC_HS         0x2C    /* High Speed Register */
+#define         AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
+
+#define AT91_DDRSDRC_DELAY(n)   (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
+
+#define AT91_DDRSDRC_WPMR       0xE4    /* Write Protect Mode Register */
+#define         AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
+#define         AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
+#define         AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
+
+#define AT91_DDRSDRC_WPSR       0xE8    /* Write Protect Status Register */
+#define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
+#define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
+
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+        at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+        at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index b7260389f7ca..100f5a592926 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -17,7 +17,7 @@
 #define AT91SAM9_SDRAMC_H
 
 /* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR          0x00    /* SDRAM Controller Mode Register */
 #define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
 #define                 AT91_SDRAMC_MODE_NORMAL         0
 #define                 AT91_SDRAMC_MODE_NOP            1
@@ -27,10 +27,10 @@
 #define                 AT91_SDRAMC_MODE_EXT_LMR        5
 #define                 AT91_SDRAMC_MODE_DEEP           6
 
-#define AT91_SDRAMC_TR          (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR          0x04    /* SDRAM Controller Refresh Timer Register */
 #define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_SDRAMC_CR          (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR          0x08    /* SDRAM Controller Configuration Register */
 #define         AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
 #define                 AT91_SDRAMC_NC_8        (0 << 0)
 #define                 AT91_SDRAMC_NC_9        (1 << 0)
@@ -57,7 +57,7 @@
 #define         AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
 #define         AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
 
-#define AT91_SDRAMC_LPR         (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR         0x10    /* SDRAM Controller Low Power Register */
 #define         AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
 #define                 AT91_SDRAMC_LPCB_DISABLE                0
 #define                 AT91_SDRAMC_LPCB_SELF_REFRESH           1
@@ -71,16 +71,21 @@
 #define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
 #define                 AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
 
-#define AT91_SDRAMC_IER         (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER         0x14    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR         0x18    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR         0x1C    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR         0x20    /* SDRAM Controller Interrupt Status Register */
 #define         AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
 
-#define AT91_SDRAMC_MDR         (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR         0x24    /* SDRAM Memory Device Register */
 #define         AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
 #define                 AT91_SDRAMC_MD_SDRAM            0
 #define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+        at91_sys_read(AT91_SDRAMC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+        at91_sys_write(AT91_SDRAMC##num + reg, value)
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index fc2de6c09c86..87ba8517ad98 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -74,7 +74,7 @@
  */
 #define AT91_DMA        (0xffffe600 - AT91_BASE_SYS)
 #define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed848c9f8..58528aa9c8a8 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
  /* USB Device */
 struct at91_udc_data {
         u8      vbus_pin;               /* high == host powering us */
+        u8      vbus_active_low;        /* vbus polarity */
+        u8      vbus_polled;            /* Use polling, not interrupt */
         u8      pullup_pin;             /* active == D+ pulled up */
         u8      pullup_active_low;      /* true == pullup_pin is active low */
 };
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 833659d1200a..3bef931d0b1c 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
 
 #define ARCH_EXID_AT91SAM9M11   0x00000001
 #define ARCH_EXID_AT91SAM9M10   0x00000002
+#define ARCH_EXID_AT91SAM9G46   0x00000003
 #define ARCH_EXID_AT91SAM9G45   0x00000004
 
 static inline unsigned long at91_exid_identify(void)
@@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void)
 #ifdef CONFIG_ARCH_AT91SAM9G45
 #define cpu_is_at91sam9g45()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
 #define cpu_is_at91sam9g45es()  (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
+#define cpu_is_at91sam9m10()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
+#define cpu_is_at91sam9m46()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
+#define cpu_is_at91sam9m11()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
 #else
 #define cpu_is_at91sam9g45()    (0)
 #define cpu_is_at91sam9g45es()  (0)
+#define cpu_is_at91sam9m10()    (0)
+#define cpu_is_at91sam9g46()    (0)
+#define cpu_is_at91sam9m11()    (0)
 #endif
 
 #ifdef CONFIG_ARCH_AT91CAP9
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 04c91e31c9c5..bfdd8ab26dc8 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -19,6 +19,7 @@
 #define PIN_BASE                NR_AIC_IRQS
 
 #define MAX_GPIO_BANKS          5
+#define NR_BUILTIN_GPIO         (PIN_BASE + (MAX_GPIO_BANKS * 32))
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 08322c44df1a..8c87d0c1b8f8 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
         u32 saved_lpr, lpr;
 
-        saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+        saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
 
         lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-        at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
         return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
+
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
+
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static u32 saved_lpr1;
+
+static inline u32 sdram_selfrefresh_enable(void)
+{
+        /* Those tow values allow us to delay self-refresh activation
+         * to the maximum. */
+        u32 lpr0, lpr1;
+        u32 saved_lpr0;
+
+        saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+        lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+        lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+        saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+        lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
+        lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+        /* self-refresh mode now */
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
+        at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+
+        return saved_lpr0;
+}
+
+#define sdram_selfrefresh_disable(saved_lpr0)   \
+        do { \
+                at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
+                at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
+        } while (0)
 
 #else
 #include <mach/at91sam9_sdramc.h>
@@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define AT91_SDRAMC     AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
         u32 saved_lpr, lpr;
 
-        saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+        saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 
         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-        at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
         return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
 
 #endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 9c5b48e68a71..b6b00a1f6125 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,10 +16,12 @@
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
 
-#ifdef CONFIG_ARCH_AT91RM9200
+#if defined(CONFIG_ARCH_AT91RM9200)
 #include <mach/at91rm9200_mc.h>
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #include <mach/at91cap9_ddrsdr.h>
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
 #else
 #include <mach/at91sam9_sdramc.h>
 #endif
@@ -30,7 +32,6 @@
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define AT91_SDRAMC     AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
         /*
          * Register usage:
          *  R1 = Base address of AT91_PMC
-         *  R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
+         *  R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
          *  R3 = temporary register
          *  R4 = temporary register
+         *  R5 = Base address of second RAM Controller or 0 if not present
          */
         ldr     r1, .at91_va_base_pmc
         ldr     r2, .at91_va_base_sdramc
+        ldr     r5, .at91_va_base_ramc1
 
         /* Drain write buffer */
         mcr     p15, 0, r0, c7, c10, 4
@@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
         /* Put SDRAM in self-refresh mode */
         mov     r3, #1
         str     r3, [r2, #AT91_SDRAMC_SRR]
-#elif defined(CONFIG_ARCH_AT91CAP9)
-        /* Enable SDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
-        str     r3, .saved_sam9_lpr
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
 
-        mov     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-        str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+        /* prepare for DDRAM self-refresh mode */
+        ldr     r3, [r2, #AT91_DDRSDRC_LPR]
+        str     r3, .saved_sam9_lpr
+        bic     r3, #AT91_DDRSDRC_LPCB
+        orr     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+        /* figure out if we use the second ram controller */
+        cmp     r5, #0
+        ldrne   r4, [r5, #AT91_DDRSDRC_LPR]
+        strne   r4, .saved_sam9_lpr1
+        bicne   r4, #AT91_DDRSDRC_LPCB
+        orrne   r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+        /* Enable DDRAM self-refresh mode */
+        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        strne   r4, [r5, #AT91_DDRSDRC_LPR]
 #else
         /* Enable SDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+        ldr     r3, [r2, #AT91_SDRAMC_LPR]
         str     r3, .saved_sam9_lpr
 
-        mov     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
-        str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+        bic     r3, #AT91_SDRAMC_LPCB
+        orr     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
+        str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
         /* Save Master clock setting */
@@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
 
 #ifdef CONFIG_ARCH_AT91RM9200
         /* Do nothing - self-refresh is automatically disabled. */
-#elif defined(CONFIG_ARCH_AT91CAP9)
-        /* Restore LPR on AT91CAP9 */
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
+        /* Restore LPR on AT91 with DDRAM */
         ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+        str     r3, [r2, #AT91_DDRSDRC_LPR]
+
+        /* if we use the second ram controller */
+        cmp     r5, #0
+        ldrne   r4, .saved_sam9_lpr1
+        strne   r4, [r5, #AT91_DDRSDRC_LPR]
+
 #else
-        /* Restore LPR on AT91SAM9 */
+        /* Restore LPR on AT91 with SDRAM */
         ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+        str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
         /* Restore registers, and return */
@@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
 .saved_sam9_lpr:
         .word 0
 
+.saved_sam9_lpr1:
+        .word 0
+
 .at91_va_base_pmc:
         .word AT91_VA_BASE_SYS + AT91_PMC
 
 #ifdef CONFIG_ARCH_AT91RM9200
 .at91_va_base_sdramc:
         .word AT91_VA_BASE_SYS
-#elif defined(CONFIG_ARCH_AT91CAP9)
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
 .at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC
+        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
 #else
 .at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC
+        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
+#endif
+
+.at91_va_base_ramc1:
+#if defined(CONFIG_ARCH_AT91SAM9G45)
+        .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
+#else
+        .word 0
 #endif
 
 ENTRY(at91_slow_clock_sz)
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 72e405df0fb0..d3f959e92b2d 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -91,14 +91,23 @@ static struct clk uart_clk = {
         .parent = &pll1_clk,
 };
 
+static struct clk dummy_apb_pclk = {
+        .name = "BUSCLK",
+        .type = CLK_TYPE_PRIMARY,
+        .mode = CLK_MODE_XTAL,
+};
+
 static struct clk_lookup lookups[] = {
-        {                       /* UART0 */
-         .dev_id = "uarta",
-         .clk = &uart_clk,
-         }, {                   /* UART1 */
-             .dev_id = "uartb",
-             .clk = &uart_clk,
-             }
+        {                       /* Bus clock */
+                .con_id = "apb_pclk",
+                .clk = &dummy_apb_pclk,
+        }, {                    /* UART0 */
+                .dev_id = "uarta",
+                .clk = &uart_clk,
+        }, {                    /* UART1 */
+                .dev_id = "uartb",
+                .clk = &uart_clk,
+        }
 };
 
 static struct amba_device *amba_devs[] __initdata = {
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index dbaae5f746a1..eb34bd1251d4 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -30,7 +30,6 @@ config ARCH_CLEP7312
 config ARCH_EDB7211
         bool "EDB7211"
         select ISA
-        select ARCH_DISCONTIGMEM_ENABLE
         select ARCH_SPARSEMEM_ENABLE
         select ARCH_SELECT_MEMORY_MODEL
         help
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 09fb57e45213..3c3bf45039ff 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -32,7 +32,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
         mi->nr_banks=1;
         mi->bank[0].start = 0xc0000000;
         mi->bank[0].size = 0x01000000;
-        mi->bank[0].node = 0;
 }
 
 
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index dc81cc68595d..4a7a2322979a 100644
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/init.h>
+#include <linux/memblock.h>
 #include <linux/types.h>
 #include <linux/string.h>
 
@@ -29,6 +30,12 @@
 
 extern void edb7211_map_io(void);
 
+/* Reserve screen memory region at the start of main system memory. */
+static void __init edb7211_reserve(void)
+{
+        memblock_reserve(PHYS_OFFSET, 0x00020000);
+}
+
 static void __init
 fixup_edb7211(struct machine_desc *desc, struct tag *tags,
               char **cmdline, struct meminfo *mi)
@@ -43,10 +50,8 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
          */
         mi->bank[0].start = 0xc0000000;
         mi->bank[0].size = 8*1024*1024;
-        mi->bank[0].node = 0;
         mi->bank[1].start = 0xc1000000;
         mi->bank[1].size = 8*1024*1024;
-        mi->bank[1].node = 1;
         mi->nr_banks = 2;
 }
 
@@ -57,6 +62,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         .boot_params    = 0xc0020100,   /* 0xc0000000 - 0xc001ffff can be video RAM */
         .fixup          = fixup_edb7211,
         .map_io         = edb7211_map_io,
+        .reserve        = edb7211_reserve,
         .init_irq       = clps711x_init_irq,
         .timer          = &clps711x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 7430e4049d87..a696099aa4f8 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -39,7 +39,6 @@ struct meminfo memmap = {
                 {
                         .start  = 0xC0000000,
                         .size   = 0x01000000,
-                        .node   = 0
                 },
         },
 };
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
index f70d52be48a2..f45c8e892cb5 100644
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -20,7 +20,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-
 /*
  * Physical DRAM offset.
  */
@@ -72,7 +71,6 @@
  *      node 2:  0xd0000000 - 0xd7ffffff
  *      node 3:  0xd8000000 - 0xdfffffff
  */
-#define NODE_MEM_SIZE_BITS      24
 #define SECTION_SIZE_BITS       24
 #define MAX_PHYSMEM_BITS        32
 
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 427507a2d696..11033f1c2e23 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,2 +1,3 @@
-obj-$(CONFIG_ARCH_CNS3XXX)              += core.o pm.o
+obj-$(CONFIG_ARCH_CNS3XXX)              += core.o pm.o devices.o
+obj-$(CONFIG_PCI)                       += pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)            += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2e30c8288740..9df8391fd78a 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -32,6 +32,7 @@
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
 #include "core.h"
+#include "devices.h"
 
 /*
  * NOR Flash
@@ -117,6 +118,9 @@ static void __init cns3420_init(void)
 {
         platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+        cns3xxx_ahci_init();
+        cns3xxx_sdhci_init();
+
         pm_power_off = cns3xxx_power_off;
 }
 
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644
index 000000000000..50b4d31c27c0
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -0,0 +1,111 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *                Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *                Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/compiler.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <mach/cns3xxx.h>
+#include <mach/irqs.h>
+#include "core.h"
+#include "devices.h"
+
+/*
+ * AHCI
+ */
+static struct resource cns3xxx_ahci_resource[] = {
+        [0] = {
+                .start  = CNS3XXX_SATA2_BASE,
+                .end    = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_CNS3XXX_SATA,
+                .end    = IRQ_CNS3XXX_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_ahci_pdev = {
+        .name           = "ahci",
+        .id             = 0,
+        .resource       = cns3xxx_ahci_resource,
+        .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
+        .dev            = {
+                .dma_mask               = &cns3xxx_ahci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init cns3xxx_ahci_init(void)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(MISC_SATA_POWER_MODE);
+        tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+        tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+        __raw_writel(tmp, MISC_SATA_POWER_MODE);
+
+        /* Enable SATA PHY */
+        cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+        cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+
+        /* Enable SATA Clock */
+        cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+
+        /* De-Asscer SATA Reset */
+        cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+
+        platform_device_register(&cns3xxx_ahci_pdev);
+}
+
+/*
+ * SDHCI
+ */
+static struct resource cns3xxx_sdhci_resources[] = {
+        [0] = {
+                .start = CNS3XXX_SDIO_BASE,
+                .end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_CNS3XXX_SDIO,
+                .end   = IRQ_CNS3XXX_SDIO,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cns3xxx_sdhci_pdev = {
+        .name           = "sdhci-cns3xxx",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(cns3xxx_sdhci_resources),
+        .resource       = cns3xxx_sdhci_resources,
+};
+
+void __init cns3xxx_sdhci_init(void)
+{
+        u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+        u32 gpioa_pins = __raw_readl(gpioa);
+
+        /* MMC/SD pins share with GPIOA */
+        gpioa_pins |= 0x1fff0004;
+        __raw_writel(gpioa_pins, gpioa);
+
+        cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+        cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+
+        platform_device_register(&cns3xxx_sdhci_pdev);
+}
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644
index 000000000000..27e15a10aa85
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -0,0 +1,20 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *                Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *                Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_DEVICES_H_
+#define __CNS3XXX_DEVICES_H_
+
+void __init cns3xxx_ahci_init(void);
+void __init cns3xxx_sdhci_init(void);
+
+#endif /* __CNS3XXX_DEVICES_H_ */
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 8a2f5a21d4ee..6dbce13771ca 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -247,37 +247,36 @@
  * Misc block
  */
 #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
-
-#define MISC_MEMORY_REMAP_REG                   MISC_MEM_MAP_VALUE(0x00)
-#define MISC_CHIP_CONFIG_REG                    MISC_MEM_MAP_VALUE(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG               MISC_MEM_MAP_VALUE(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG          MISC_MEM_MAP_VALUE(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG          MISC_MEM_MAP_VALUE(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG               MISC_MEM_MAP_VALUE(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG               MISC_MEM_MAP_VALUE(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A       MISC_MEM_MAP_VALUE(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B       MISC_MEM_MAP_VALUE(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG           MISC_MEM_MAP_VALUE(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG           MISC_MEM_MAP_VALUE(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x30)
-#define MISC_IO_PULL_CTRL_REG                   MISC_MEM_MAP_VALUE(0x34)
-#define MISC_E_FUSE_31_0_REG                    MISC_MEM_MAP_VALUE(0x40)
-#define MISC_E_FUSE_63_32_REG                   MISC_MEM_MAP_VALUE(0x44)
-#define MISC_E_FUSE_95_64_REG                   MISC_MEM_MAP_VALUE(0x48)
-#define MISC_E_FUSE_127_96_REG                  MISC_MEM_MAP_VALUE(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG                MISC_MEM_MAP_VALUE(0x50)
-#define MISC_SOFTWARE_TEST_2_REG                MISC_MEM_MAP_VALUE(0x54)
-
-#define MISC_SATA_POWER_MODE                    MISC_MEM_MAP_VALUE(0x310)
-
-#define MISC_USB_CFG_REG                        MISC_MEM_MAP_VALUE(0x800)
-#define MISC_USB_STS_REG                        MISC_MEM_MAP_VALUE(0x804)
-#define MISC_USBPHY00_CFG_REG                   MISC_MEM_MAP_VALUE(0x808)
-#define MISC_USBPHY01_CFG_REG                   MISC_MEM_MAP_VALUE(0x80c)
-#define MISC_USBPHY10_CFG_REG                   MISC_MEM_MAP_VALUE(0x810)
-#define MISC_USBPHY11_CFG_REG                   MISC_MEM_MAP_VALUE(0x814)
+
+#define MISC_MEMORY_REMAP_REG                   MISC_MEM_MAP(0x00)
+#define MISC_CHIP_CONFIG_REG                    MISC_MEM_MAP(0x04)
+#define MISC_DEBUG_PROBE_DATA_REG               MISC_MEM_MAP(0x08)
+#define MISC_DEBUG_PROBE_SELECTION_REG          MISC_MEM_MAP(0x0C)
+#define MISC_IO_PIN_FUNC_SELECTION_REG          MISC_MEM_MAP(0x10)
+#define MISC_GPIOA_PIN_ENABLE_REG               MISC_MEM_MAP(0x14)
+#define MISC_GPIOB_PIN_ENABLE_REG               MISC_MEM_MAP(0x18)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A       MISC_MEM_MAP(0x1C)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B       MISC_MEM_MAP(0x20)
+#define MISC_GPIOA_15_0_PULL_CTRL_REG           MISC_MEM_MAP(0x24)
+#define MISC_GPIOA_16_31_PULL_CTRL_REG          MISC_MEM_MAP(0x28)
+#define MISC_GPIOB_15_0_PULL_CTRL_REG           MISC_MEM_MAP(0x2C)
+#define MISC_GPIOB_16_31_PULL_CTRL_REG          MISC_MEM_MAP(0x30)
+#define MISC_IO_PULL_CTRL_REG                   MISC_MEM_MAP(0x34)
+#define MISC_E_FUSE_31_0_REG                    MISC_MEM_MAP(0x40)
+#define MISC_E_FUSE_63_32_REG                   MISC_MEM_MAP(0x44)
+#define MISC_E_FUSE_95_64_REG                   MISC_MEM_MAP(0x48)
+#define MISC_E_FUSE_127_96_REG                  MISC_MEM_MAP(0x4C)
+#define MISC_SOFTWARE_TEST_1_REG                MISC_MEM_MAP(0x50)
+#define MISC_SOFTWARE_TEST_2_REG                MISC_MEM_MAP(0x54)
+
+#define MISC_SATA_POWER_MODE                    MISC_MEM_MAP(0x310)
+
+#define MISC_USB_CFG_REG                        MISC_MEM_MAP(0x800)
+#define MISC_USB_STS_REG                        MISC_MEM_MAP(0x804)
+#define MISC_USBPHY00_CFG_REG                   MISC_MEM_MAP(0x808)
+#define MISC_USBPHY01_CFG_REG                   MISC_MEM_MAP(0x80c)
+#define MISC_USBPHY10_CFG_REG                   MISC_MEM_MAP(0x810)
+#define MISC_USBPHY11_CFG_REG                   MISC_MEM_MAP(0x814)
 
 #define MISC_PCIEPHY_CMCTL(x)                   MISC_MEM_MAP(0x900 + (x) * 0x004)
 #define MISC_PCIEPHY_CTL(x)                     MISC_MEM_MAP(0x940 + (x) * 0x100)
@@ -300,21 +299,21 @@
 /*
  * Power management and clock control
  */
-#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
-
-#define PM_CLK_GATE_REG                                 PMU_REG_VALUE(0x000)
-#define PM_SOFT_RST_REG                                 PMU_REG_VALUE(0x004)
-#define PM_HS_CFG_REG                                   PMU_REG_VALUE(0x008)
-#define PM_CACTIVE_STA_REG                              PMU_REG_VALUE(0x00C)
-#define PM_PWR_STA_REG                                  PMU_REG_VALUE(0x010)
-#define PM_CLK_CTRL_REG                                 PMU_REG_VALUE(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG                         PMU_REG_VALUE(0x018)
-#define PM_PLL_HM_PD_CTRL_REG                           PMU_REG_VALUE(0x01C)
-#define PM_REGULAT_CTRL_REG                             PMU_REG_VALUE(0x020)
-#define PM_WDT_CTRL_REG                                 PMU_REG_VALUE(0x024)
-#define PM_WU_CTRL0_REG                                 PMU_REG_VALUE(0x028)
-#define PM_WU_CTRL1_REG                                 PMU_REG_VALUE(0x02C)
-#define PM_CSR_REG                                      PMU_REG_VALUE(0x030)
+#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
+
+#define PM_CLK_GATE_REG                                 PMU_MEM_MAP(0x000)
+#define PM_SOFT_RST_REG                                 PMU_MEM_MAP(0x004)
+#define PM_HS_CFG_REG                                   PMU_MEM_MAP(0x008)
+#define PM_CACTIVE_STA_REG                              PMU_MEM_MAP(0x00C)
+#define PM_PWR_STA_REG                                  PMU_MEM_MAP(0x010)
+#define PM_CLK_CTRL_REG                                 PMU_MEM_MAP(0x014)
+#define PM_PLL_LCD_I2S_CTRL_REG                         PMU_MEM_MAP(0x018)
+#define PM_PLL_HM_PD_CTRL_REG                           PMU_MEM_MAP(0x01C)
+#define PM_REGULAT_CTRL_REG                             PMU_MEM_MAP(0x020)
+#define PM_WDT_CTRL_REG                                 PMU_MEM_MAP(0x024)
+#define PM_WU_CTRL0_REG                                 PMU_MEM_MAP(0x028)
+#define PM_WU_CTRL1_REG                                 PMU_MEM_MAP(0x02C)
+#define PM_CSR_REG                                      PMU_MEM_MAP(0x030)
 
 /* PM_CLK_GATE_REG */
 #define PM_CLK_GATE_REG_OFFSET_SDIO                     (25)
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644
index 000000000000..38088c36936c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -0,0 +1,389 @@
+/*
+ * PCI-E support for CNS3xxx
+ *
+ * Copyright 2008 Cavium Networks
+ *                Richard Liu <richard.liu@caviumnetworks.com>
+ * Copyright 2010 MontaVista Software, LLC.
+ *                Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <asm/mach/map.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+enum cns3xxx_access_type {
+        CNS3XXX_HOST_TYPE = 0,
+        CNS3XXX_CFG0_TYPE,
+        CNS3XXX_CFG1_TYPE,
+        CNS3XXX_NUM_ACCESS_TYPES,
+};
+
+struct cns3xxx_pcie {
+        struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
+        unsigned int irqs[2];
+        struct resource res_io;
+        struct resource res_mem;
+        struct hw_pci hw_pci;
+
+        bool linked;
+};
+
+static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
+
+static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
+{
+        struct pci_sys_data *root = sysdata;
+
+        return &cns3xxx_pcie[root->domain];
+}
+
+static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+{
+        return sysdata_to_cnspci(dev->sysdata);
+}
+
+static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
+{
+        return sysdata_to_cnspci(bus->sysdata);
+}
+
+static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
+                                  unsigned int devfn, int where)
+{
+        struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
+        int busno = bus->number;
+        int slot = PCI_SLOT(devfn);
+        int offset;
+        enum cns3xxx_access_type type;
+        void __iomem *base;
+
+        /* If there is no link, just show the CNS PCI bridge. */
+        if (!cnspci->linked && (busno > 0 || slot > 0))
+                return NULL;
+
+        /*
+         * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
+         * we still want to access it. For this to work, we must place
+         * the first device on the same bus as the CNS PCI bridge.
+         */
+        if (busno == 0) {
+                if (slot > 1)
+                        return NULL;
+                type = slot;
+        } else {
+                type = CNS3XXX_CFG1_TYPE;
+        }
+
+        base = (void __iomem *)cnspci->cfg_bases[type].virtual;
+        offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
+
+        return base + offset;
+}
+
+static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                                   int where, int size, u32 *val)
+{
+        u32 v;
+        void __iomem *base;
+        u32 mask = (0x1ull << (size * 8)) - 1;
+        int shift = (where % 4) * 8;
+
+        base = cns3xxx_pci_cfg_base(bus, devfn, where);
+        if (!base) {
+                *val = 0xffffffff;
+                return PCIBIOS_SUCCESSFUL;
+        }
+
+        v = __raw_readl(base);
+
+        if (bus->number == 0 && devfn == 0 &&
+                        (where & 0xffc) == PCI_CLASS_REVISION) {
+                /*
+                 * RC's class is 0xb, but Linux PCI driver needs 0x604
+                 * for a PCIe bridge. So we must fixup the class code
+                 * to 0x604 here.
+                 */
+                v &= 0xff;
+                v |= 0x604 << 16;
+        }
+
+        *val = (v >> shift) & mask;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+                                    int where, int size, u32 val)
+{
+        u32 v;
+        void __iomem *base;
+        u32 mask = (0x1ull << (size * 8)) - 1;
+        int shift = (where % 4) * 8;
+
+        base = cns3xxx_pci_cfg_base(bus, devfn, where);
+        if (!base)
+                return PCIBIOS_SUCCESSFUL;
+
+        v = __raw_readl(base);
+
+        v &= ~(mask << shift);
+        v |= (val & mask) << shift;
+
+        __raw_writel(v, base);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+        struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
+        struct resource *res_io = &cnspci->res_io;
+        struct resource *res_mem = &cnspci->res_mem;
+        struct resource **sysres = sys->resource;
+
+        BUG_ON(request_resource(&iomem_resource, res_io) ||
+               request_resource(&iomem_resource, res_mem));
+
+        sysres[0] = res_io;
+        sysres[1] = res_mem;
+
+        return 1;
+}
+
+static struct pci_ops cns3xxx_pcie_ops = {
+        .read = cns3xxx_pci_read_config,
+        .write = cns3xxx_pci_write_config,
+};
+
+static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+}
+
+static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
+        int irq = cnspci->irqs[slot];
+
+        pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
+                pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
+                PCI_FUNC(dev->devfn), slot, pin, irq);
+
+        return irq;
+}
+
+static struct cns3xxx_pcie cns3xxx_pcie[] = {
+        [0] = {
+                .cfg_bases = {
+                        [CNS3XXX_HOST_TYPE] = {
+                                .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG0_TYPE] = {
+                                .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG1_TYPE] = {
+                                .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                },
+                .res_io = {
+                        .name = "PCIe0 I/O space",
+                        .start = CNS3XXX_PCIE0_IO_BASE,
+                        .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_IO,
+                },
+                .res_mem = {
+                        .name = "PCIe0 non-prefetchable",
+                        .start = CNS3XXX_PCIE0_MEM_BASE,
+                        .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+                .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
+                .hw_pci = {
+                        .domain = 0,
+                        .swizzle = pci_std_swizzle,
+                        .nr_controllers = 1,
+                        .setup = cns3xxx_pci_setup,
+                        .scan = cns3xxx_pci_scan_bus,
+                        .map_irq = cns3xxx_pcie_map_irq,
+                },
+        },
+        [1] = {
+                .cfg_bases = {
+                        [CNS3XXX_HOST_TYPE] = {
+                                .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG0_TYPE] = {
+                                .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG1_TYPE] = {
+                                .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                },
+                .res_io = {
+                        .name = "PCIe1 I/O space",
+                        .start = CNS3XXX_PCIE1_IO_BASE,
+                        .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_IO,
+                },
+                .res_mem = {
+                        .name = "PCIe1 non-prefetchable",
+                        .start = CNS3XXX_PCIE1_MEM_BASE,
+                        .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+                .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
+                .hw_pci = {
+                        .domain = 1,
+                        .swizzle = pci_std_swizzle,
+                        .nr_controllers = 1,
+                        .setup = cns3xxx_pci_setup,
+                        .scan = cns3xxx_pci_scan_bus,
+                        .map_irq = cns3xxx_pcie_map_irq,
+                },
+        },
+};
+
+static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
+{
+        int port = cnspci->hw_pci.domain;
+        u32 reg;
+        unsigned long time;
+
+        reg = __raw_readl(MISC_PCIE_CTRL(port));
+        /*
+         * Enable Application Request to 1, it will exit L1 automatically,
+         * but when chip back, it will use another clock, still can use 0x1.
+         */
+        reg |= 0x3;
+        __raw_writel(reg, MISC_PCIE_CTRL(port));
+
+        pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
+        pr_info("PCIe: Port[%d] Check data link layer...", port);
+
+        time = jiffies;
+        while (1) {
+                reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
+                if (reg & 0x1) {
+                        pr_info("Link up.\n");
+                        cnspci->linked = 1;
+                        break;
+                } else if (time_after(jiffies, time + 50)) {
+                        pr_info("Device not found.\n");
+                        break;
+                }
+        }
+}
+
+static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
+{
+        int port = cnspci->hw_pci.domain;
+        struct pci_sys_data sd = {
+                .domain = port,
+        };
+        struct pci_bus bus = {
+                .number = 0,
+                .ops = &cns3xxx_pcie_ops,
+                .sysdata = &sd,
+        };
+        u32 io_base = cnspci->res_io.start >> 16;
+        u32 mem_base = cnspci->res_mem.start >> 16;
+        u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
+        u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
+        u32 devfn = 0;
+        u8 tmp8;
+        u16 pos;
+        u16 dc;
+
+        host_base = (__pfn_to_phys(host_base) - 1) >> 16;
+        cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
+
+        pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
+        pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
+        pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
+
+        pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
+        pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
+        pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
+
+        pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
+
+        if (!cnspci->linked)
+                return;
+
+        /* Set Device Max_Read_Request_Size to 128 byte */
+        devfn = PCI_DEVFN(1, 0);
+        pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
+        pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+        dc &= ~(0x3 << 12);     /* Clear Device Control Register [14:12] */
+        pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
+        pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+        if (!(dc & (0x3 << 12)))
+                pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
+
+        /* Disable PCIe0 Interrupt Mask INTA to INTD */
+        __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
+}
+
+static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+                                      struct pt_regs *regs)
+{
+        if (fsr & (1 << 10))
+                regs->ARM_pc += 4;
+        return 0;
+}
+
+static int __init cns3xxx_pcie_init(void)
+{
+        int i;
+
+        hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+                        "imprecise external abort");
+
+        for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+                iotable_init(cns3xxx_pcie[i].cfg_bases,
+                             ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+                cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+                cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+                cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+                cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+                pci_common_init(&cns3xxx_pcie[i].hw_pci);
+        }
+
+        pci_assign_unassigned_resources();
+
+        return 0;
+}
+device_initcall(cns3xxx_pcie_init);
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 725e1a4fc231..38e44706feab 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,18 +6,25 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
-        PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+        u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+        reg |= (block & PM_CLK_GATE_REG_MASK);
+        __raw_writel(reg, PM_CLK_GATE_REG);
 }
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
-        PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+        u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
+        reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
+        __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 
         /* Wait for 300us for the PLL output clock locked. */
         udelay(300);
@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
+        u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
         /* write '1' to power down */
-        PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+        reg |= (block & CNS3XXX_PWR_PLL_ALL);
+        __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
+        u32 reg = __raw_readl(PM_SOFT_RST_REG);
+
         /*
          * bit 0, 28, 29 => program low to reset,
          * the other else program low and then high
          */
         if (block & 0x30000001) {
-                PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+                reg &= ~(block & PM_SOFT_RST_REG_MASK);
         } else {
-                PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
-                PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+                reg &= ~(block & PM_SOFT_RST_REG_MASK);
+                reg |= (block & PM_SOFT_RST_REG_MASK);
         }
+
+        __raw_writel(reg, PM_SOFT_RST_REG);
 }
 
 void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
  */
 int cns3xxx_cpu_clock(void)
 {
+        u32 reg = __raw_readl(PM_CLK_CTRL_REG);
         int cpu;
         int cpu_sel;
         int div_sel;
 
-        cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
-        div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+        cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+        div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
 
         cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
 
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 2ec3095ffb7b..b280efb1fa12 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/tps6507x.h>
 #include <linux/mfd/tps6507x.h>
 #include <linux/input/tps6507x-ts.h>
 
@@ -469,6 +470,11 @@ struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
         },
 };
 
+/* We take advantage of the fact that both defdcdc{2,3} are tied high */
+static struct tps6507x_reg_platform_data tps6507x_platform_data = {
+        .defdcdc_default = true,
+};
+
 struct regulator_init_data tps65070_regulator_data[] = {
         /* dcdc1 */
         {
@@ -494,6 +500,7 @@ struct regulator_init_data tps65070_regulator_data[] = {
                 },
                 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
                 .consumer_supplies = tps65070_dcdc2_consumers,
+                .driver_data = &tps6507x_platform_data,
         },
 
         /* dcdc3 */
@@ -507,6 +514,7 @@ struct regulator_init_data tps65070_regulator_data[] = {
                 },
                 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
                 .consumer_supplies = tps65070_dcdc3_consumers,
+                .driver_data = &tps6507x_platform_data,
         },
 
         /* ldo1 */
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index a91edfb8beea..22eb97c1c30b 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -48,19 +48,16 @@
  * below 128M
  */
 static inline void
-__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
+__arch_adjust_zones(unsigned long *size, unsigned long *holes)
 {
         unsigned int sz = (128<<20) >> PAGE_SHIFT;
 
-        if (node != 0)
-                sz = 0;
-
         size[1] = size[0] - sz;
         size[0] = sz;
 }
 
-#define arch_adjust_zones(node, zone_size, holes) \
-        if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes)
+#define arch_adjust_zones(zone_size, holes) \
+        if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
 
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + (128<<20) - 1)
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + (128<<20))
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 5da2cf402c81..f7a12586a1f5 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -752,6 +752,67 @@ void __init dove_xor1_init(void)
         platform_device_register(&dove_xor11_channel);
 }
 
+/*****************************************************************************
+ * SDIO
+ ****************************************************************************/
+static u64 sdio_dmamask = DMA_BIT_MASK(32);
+
+static struct resource dove_sdio0_resources[] = {
+        {
+                .start  = DOVE_SDIO0_PHYS_BASE,
+                .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SDIO0,
+                .end    = IRQ_DOVE_SDIO0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dove_sdio0 = {
+        .name           = "sdhci-mv",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &sdio_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = dove_sdio0_resources,
+        .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
+};
+
+void __init dove_sdio0_init(void)
+{
+        platform_device_register(&dove_sdio0);
+}
+
+static struct resource dove_sdio1_resources[] = {
+        {
+                .start  = DOVE_SDIO1_PHYS_BASE,
+                .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SDIO1,
+                .end    = IRQ_DOVE_SDIO1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dove_sdio1 = {
+        .name           = "sdhci-mv",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &sdio_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = dove_sdio1_resources,
+        .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
+};
+
+void __init dove_sdio1_init(void)
+{
+        platform_device_register(&dove_sdio1);
+}
+
 void __init dove_init(void)
 {
         int tclk;
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index b29e8937de4f..a51517c3fe76 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -36,5 +36,7 @@ void dove_uart3_init(void);
 void dove_spi0_init(void);
 void dove_spi1_init(void);
 void dove_i2c_init(void);
+void dove_sdio0_init(void);
+void dove_sdio1_init(void);
 
 #endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index f2971b745224..bef70460fbc6 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -82,6 +82,8 @@ static void __init dove_db_init(void)
         dove_ehci0_init();
         dove_ehci1_init();
         dove_sata_init(&dove_db_sata_data);
+        dove_sdio0_init();
+        dove_sdio1_init();
         dove_spi0_init();
         dove_spi1_init();
         dove_uart0_init();
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3a1a855bfdca..f744f676783f 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data adssphere_flash_data = {
-        .width          = 4,
-};
-
-static struct resource adssphere_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device adssphere_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &adssphere_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &adssphere_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
         .phy_id         = 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
 static void __init adssphere_init_machine(void)
 {
         ep93xx_init_devices();
-        platform_device_register(&adssphere_flash);
-
+        ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
         ep93xx_register_eth(&adssphere_eth_data, 1);
 }
 
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index e29bdef9b2e2..7f3039761d91 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = {
         INIT_CK(NULL,                   "pll1",         &clk_pll1),
         INIT_CK(NULL,                   "fclk",         &clk_f),
         INIT_CK(NULL,                   "hclk",         &clk_h),
-        INIT_CK(NULL,                   "pclk",         &clk_p),
+        INIT_CK(NULL,                   "apb_pclk",     &clk_p),
         INIT_CK(NULL,                   "pll2",         &clk_pll2),
         INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
         INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 9092677f63eb..8e37a045188c 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -29,6 +29,7 @@
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
@@ -215,8 +216,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
         spin_lock_irqsave(&syscon_swlock, flags);
 
         val = __raw_readl(EP93XX_SYSCON_DEVCFG);
-        val |= set_bits;
         val &= ~clear_bits;
+        val |= set_bits;
         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
         __raw_writel(val, EP93XX_SYSCON_DEVCFG);
 
@@ -348,6 +349,43 @@ static struct platform_device ep93xx_ohci_device = {
 
 
 /*************************************************************************
+ * EP93xx physmap'ed flash
+ *************************************************************************/
+static struct physmap_flash_data ep93xx_flash_data;
+
+static struct resource ep93xx_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device ep93xx_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &ep93xx_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &ep93xx_flash_resource,
+};
+
+/**
+ * ep93xx_register_flash() - Register the external flash device.
+ * @width:      bank width in octets
+ * @start:      resource start address
+ * @size:       resource size
+ */
+void __init ep93xx_register_flash(unsigned int width,
+                                  resource_size_t start, resource_size_t size)
+{
+        ep93xx_flash_data.width         = width;
+
+        ep93xx_flash_resource.start     = start;
+        ep93xx_flash_resource.end       = start + size - 1;
+
+        platform_device_register(&ep93xx_flash);
+}
+
+
+/*************************************************************************
  * EP93xx ethernet peripheral handling
  *************************************************************************/
 static struct ep93xx_eth_data ep93xx_eth_data;
@@ -620,6 +658,11 @@ static struct platform_device ep93xx_fb_device = {
         .resource               = ep93xx_fb_resource,
 };
 
+static struct platform_device ep93xx_bl_device = {
+        .name           = "ep93xx-bl",
+        .id             = -1,
+};
+
 /**
  * ep93xx_register_fb - Register the framebuffer platform device.
  * @data:       platform specific framebuffer configuration (__initdata)
@@ -628,6 +671,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
 {
         ep93xxfb_data = *data;
         platform_device_register(&ep93xx_fb_device);
+        platform_device_register(&ep93xx_bl_device);
 }
 
 
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 3884182cd362..c2ce9034ba87 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,7 +27,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -38,39 +37,13 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data edb93xx_flash_data;
-
-static struct resource edb93xx_flash_resource = {
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device edb93xx_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb93xx_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb93xx_flash_resource,
-};
-
-static void __init __edb93xx_register_flash(unsigned int width,
-                        resource_size_t start, resource_size_t size)
-{
-        edb93xx_flash_data.width        = width;
-        edb93xx_flash_resource.start    = start;
-        edb93xx_flash_resource.end      = start + size - 1;
-
-        platform_device_register(&edb93xx_flash);
-}
-
 static void __init edb93xx_register_flash(void)
 {
         if (machine_is_edb9307() || machine_is_edb9312() ||
             machine_is_edb9315()) {
-                __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
+                ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
         } else {
-                __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
+                ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
         }
 }
 
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index a809618e9f05..d97168c0ba33 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data gesbc9312_flash_data = {
-        .width          = 4,
-};
-
-static struct resource gesbc9312_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device gesbc9312_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &gesbc9312_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &gesbc9312_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
         .phy_id         = 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
 static void __init gesbc9312_init_machine(void)
 {
         ep93xx_init_devices();
-        platform_device_register(&gesbc9312_flash);
-
+        ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
         ep93xx_register_eth(&gesbc9312_eth_data, 0);
 }
 
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 9a4413dd44bb..a6c09176334c 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
 
 unsigned int ep93xx_chip_revision(void);
 
+void ep93xx_register_flash(unsigned int width,
+                           resource_size_t start, resource_size_t size);
+
 void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
 void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
                          struct i2c_board_info *devices, int num);
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 1cc911b4efa6..2ba776320a82 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -31,31 +30,6 @@
  * Micro9-Lite uses a separate MTD map driver for flash support
  * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
  *************************************************************************/
-static struct physmap_flash_data micro9_flash_data;
-
-static struct resource micro9_flash_resource = {
-        .start          = EP93XX_CS1_PHYS_BASE,
-        .end            = EP93XX_CS1_PHYS_BASE + SZ_64M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device micro9_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &micro9_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &micro9_flash_resource,
-};
-
-static void __init __micro9_register_flash(unsigned int width)
-{
-        micro9_flash_data.width = width;
-
-        platform_device_register(&micro9_flash);
-}
-
 static unsigned int __init micro9_detect_bootwidth(void)
 {
         u32 v;
@@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void)
 
 static void __init micro9_register_flash(void)
 {
+        unsigned int width;
+
         if (machine_is_micro9())
-                __micro9_register_flash(4);
+                width = 4;
         else if (machine_is_micro9m() || machine_is_micro9s())
-                __micro9_register_flash(micro9_detect_bootwidth());
+                width = micro9_detect_bootwidth();
+        else
+                width = 0;
+
+        if (width)
+                ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
 }
 
 
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 388aec95f60e..5dded5884133 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -18,7 +18,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -29,26 +28,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-static struct physmap_flash_data simone_flash_data = {
-        .width          = 2,
-};
-
-static struct resource simone_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device simone_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = &simone_flash_resource,
-        .dev = {
-                .platform_data  = &simone_flash_data,
-        },
-};
-
 static struct ep93xx_eth_data __initdata simone_eth_data = {
         .phy_id         = 1,
 };
@@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
 static void __init simone_init_machine(void)
 {
         ep93xx_init_devices();
-
-        platform_device_register(&simone_flash);
+        ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
         ep93xx_register_eth(&simone_eth_data, 1);
         ep93xx_register_fb(&simone_fb_info);
         ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index ae7319e588c7..93aeab8af705 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -17,7 +17,6 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/m48t86.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
@@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = {
 };
 
 
-/*************************************************************************
- * NOR flash (TS-7200 only)
- *************************************************************************/
-static struct physmap_flash_data ts72xx_nor_data = {
-        .width          = 2,
-};
-
-static struct resource ts72xx_nor_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device ts72xx_nor_flash = {
-        .name                   = "physmap-flash",
-        .id                     = 0,
-        .dev.platform_data      = &ts72xx_nor_data,
-        .resource               = &ts72xx_nor_resource,
-        .num_resources          = 1,
-};
-
 static void __init ts72xx_register_flash(void)
 {
+        /*
+         * TS7200 has NOR flash all other TS72xx board have NAND flash.
+         */
         if (board_is_ts7200()) {
-                platform_device_register(&ts72xx_nor_flash);
+                ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
         } else {
                 resource_size_t start;
 
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-imx/Kconfig
index 742fd4e6dcb9..c5c0369bb481 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,42 +1,103 @@
+config IMX_HAVE_DMA_V1
+        bool
+
+if ARCH_MX1
+
+config SOC_IMX1
+        select CPU_ARM920T
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        bool
+
+comment "MX1 platforms:"
+config MACH_MXLADS
+        bool
+
+config ARCH_MX1ADS
+        bool "MX1ADS platform"
+        select MACH_MXLADS
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Say Y here if you are using Motorola MX1ADS/MXLADS boards
+
+config MACH_SCB9328
+        bool "Synertronixx scb9328"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Say Y here if you are using a Synertronixx scb9328 board
+
+endif
+
 if ARCH_MX2
 
+config SOC_IMX21
+        select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        bool
+
+config SOC_IMX27
+        select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        bool
+
 choice
         prompt "CPUs:"
         default MACH_MX21
 
 config MACH_MX21
         bool "i.MX21 support"
-        select ARCH_MXC_AUDMUX_V1
+        select SOC_IMX21
         help
           This enables support for Freescale's MX2 based i.MX21 processor.
 
 config MACH_MX27
         bool "i.MX27 support"
-        select ARCH_MXC_AUDMUX_V1
+        select SOC_IMX27
         help
           This enables support for Freescale's MX2 based i.MX27 processor.
 
 endchoice
 
-comment "MX2 platforms:"
+endif
+
+if MACH_MX21
+
+comment "MX21 platforms:"
 
 config MACH_MX21ADS
         bool "MX21ADS platform"
-        depends on MACH_MX21
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for MX21ADS platform. This includes specific
           configurations for the board and its peripherals.
 
+endif
+
+if MACH_MX27
+
+comment "MX27 platforms:"
+
 config MACH_MX27ADS
         bool "MX27ADS platform"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for MX27ADS platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCM038
         bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -58,7 +119,9 @@ endchoice
 
 config MACH_CPUIMX27
         bool "Eukrea CPUIMX27 module"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for Eukrea CPUIMX27 platform. This includes
           specific configurations for the module and its peripherals.
@@ -67,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2
         bool "CPUIMX27 integrates SDHC2 module"
         depends on MACH_CPUIMX27
         help
-          This adds support for the internal SDHC2 used on CPUIMX27 used
+          This adds support for the internal SDHC2 used on CPUIMX27
           for wifi or eMMC.
 
+config MACH_EUKREA_CPUIMX27_USEUART4
+        bool "CPUIMX27 integrates UART4 module"
+        depends on MACH_CPUIMX27
+        help
+          This adds support for the internal UART4 used on CPUIMX27
+          for bluetooth.
+
 choice
         prompt "Baseboard"
         depends on MACH_CPUIMX27
@@ -78,6 +148,8 @@ choice
 config MACH_EUKREA_MBIMX27_BASEBOARD
         prompt "Eukrea MBIMX27 development board"
         bool
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMX27 evaluation board.
@@ -86,21 +158,24 @@ endchoice
 
 config MACH_MX27_3DS
         bool "MX27PDK platform"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX27PDK platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_IMX27LITE
         bool "LogicPD MX27 LITEKIT platform"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX27 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for phyCARD-s (aka pca100) platform. This
@@ -108,7 +183,9 @@ config MACH_PCA100
 
 config MACH_MXT_TD60
         bool "Maxtrack i-MXT TD60"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for i-MXT (aka td60) platform. This
           includes specific configurations for the module and its peripherals.
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-imx/Makefile
index e3254faac828..46a9fdfbbd15 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,14 +4,24 @@
 
 # Object file lists.
 
-obj-y   :=  devices.o serial.o
+obj-y   :=  devices.o
 
-obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
+obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
-obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
-obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
+obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
+obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+
+obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
+
+# Support for CMOS sensor interface
+obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+
+obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
+obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
 
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index e867398a8fdb..7988a85cf07d 100644
--- a/arch/arm/mach-mx2/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -1,3 +1,7 @@
+zreladdr-$(CONFIG_ARCH_MX1)     := 0x08008000
+params_phys-$(CONFIG_ARCH_MX1)  := 0x08000100
+initrd_phys-$(CONFIG_ARCH_MX1)  := 0x08800000
+
 zreladdr-$(CONFIG_MACH_MX21)    := 0xC0008000
 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-imx/clock-imx1.c
index 6cf2d4a7511d..c05096c38301 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -2,18 +2,17 @@
  *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
 #include <linux/kernel.h>
@@ -29,7 +28,41 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include "crm_regs.h"
+
+#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+/* CCM register addresses */
+#define CCM_CSCR        IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
+#define CCM_PCDR        IO_ADDR_CCM(0x20)
+
+#define CCM_CSCR_CLKO_OFFSET    29
+#define CCM_CSCR_CLKO_MASK      (0x7 << 29)
+#define CCM_CSCR_USB_OFFSET     26
+#define CCM_CSCR_USB_MASK       (0x7 << 26)
+#define CCM_CSCR_OSC_EN_SHIFT   17
+#define CCM_CSCR_SYSTEM_SEL     (1 << 16)
+#define CCM_CSCR_BCLK_OFFSET    10
+#define CCM_CSCR_BCLK_MASK      (0xf << 10)
+#define CCM_CSCR_PRESC          (1 << 15)
+
+#define CCM_PCDR_PCLK3_OFFSET   16
+#define CCM_PCDR_PCLK3_MASK     (0x7f << 16)
+#define CCM_PCDR_PCLK2_OFFSET   4
+#define CCM_PCDR_PCLK2_MASK     (0xf << 4)
+#define CCM_PCDR_PCLK1_OFFSET   0
+#define CCM_PCDR_PCLK1_MASK     0xf
+
+#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+/* SCM register addresses */
+#define SCM_GCCR        IO_ADDR_SCM(0xc)
+
+#define SCM_GCCR_DMA_CLK_EN_OFFSET      3
+#define SCM_GCCR_CSI_CLK_EN_OFFSET      2
+#define SCM_GCCR_MMA_CLK_EN_OFFSET      1
+#define SCM_GCCR_USBD_CLK_EN_OFFSET     0
 
 static int _clk_enable(struct clk *clk)
 {
@@ -596,7 +629,8 @@ int __init mx1_clocks_init(unsigned long fref)
         clk_enable(&hclk);
         clk_enable(&fclk);
 
-        mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
+        mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+                        MX1_TIM1_INT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bb419ef4d133..bb419ef4d133 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 0f0823c8b170..5a1aa15c8a16 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
         _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-        _REGISTER_CLOCK(NULL, "csi", csi_clk)
+        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
         _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index d8d3b2d84dc5..d8d3b2d84dc5 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
new file mode 100644
index 000000000000..a8d94f078196
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx1.h>
+#include <mach/devices-common.h>
+
+#define imx1_add_i2c_imx(pdata)         \
+        imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
+
+#define imx1_add_imx_uart0(pdata)       \
+        imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
+#define imx1_add_imx_uart1(pdata)       \
+        imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
new file mode 100644
index 000000000000..42788e99d127
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx21.h>
+#include <mach/devices-common.h>
+
+#define imx21_add_i2c_imx(pdata)        \
+        imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
+
+#define imx21_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
+#define imx21_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
+#define imx21_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
+#define imx21_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
+
+#define imx21_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
+
+#define imx21_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
+#define imx21_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
new file mode 100644
index 000000000000..65e7bb7ec2e8
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx27.h>
+#include <mach/devices-common.h>
+
+#define imx27_add_i2c_imx0(pdata)       \
+        imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
+#define imx27_add_i2c_imx1(pdata)       \
+        imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
+
+#define imx27_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
+#define imx27_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
+#define imx27_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
+#define imx27_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
+#define imx27_add_imx_uart4(pdata)      \
+        imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
+#define imx27_add_imx_uart5(pdata)      \
+        imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
+
+#define imx27_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
+
+#define imx27_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
+#define imx27_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
+#define imx27_add_spi_imx2(pdata)       \
+        imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-imx/devices.c
index a0aeb8a4adc1..9c271a752b84 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -11,6 +11,9 @@
  *
  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -32,6 +35,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <linux/serial.h>
 
 #include <mach/irqs.h>
 #include <mach/hardware.h>
@@ -40,38 +44,179 @@
 
 #include "devices.h"
 
-/*
- * SPI master controller
- *
- * - i.MX1: 2 channel (slighly different register setting)
- * - i.MX21: 2 channel
- * - i.MX27: 3 channel
- */
-#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)                                 \
-        static struct resource mxc_spi_resources ## n[] = {                     \
-                {                                                               \
-                        .start = baseaddr,                                      \
-                        .end = baseaddr + SZ_4K - 1,                            \
-                        .flags = IORESOURCE_MEM,                                \
-                }, {                                                            \
-                        .start = irq,                                           \
-                        .end = irq,                                             \
-                        .flags = IORESOURCE_IRQ,                                \
-                },                                                              \
-        };                                                                      \
-                                                                                \
-        struct platform_device mxc_spi_device ## n = {                          \
-                .name = "spi_imx",                                              \
-                .id = n,                                                        \
-                .num_resources = ARRAY_SIZE(mxc_spi_resources ## n),            \
-                .resource = mxc_spi_resources ## n,                             \
+#if defined(CONFIG_ARCH_MX1)
+static struct resource imx1_camera_resources[] = {
+        {
+                .start  = 0x00224000,
+                .end    = 0x00224010,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_CSI_INT,
+                .end    = MX1_CSI_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device imx1_camera_device = {
+        .name           = "mx1-camera",
+        .id             = 0, /* This is used to put cameras on this interface */
+        .dev            = {
+                .dma_mask = &imx1_camera_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource       = imx1_camera_resources,
+        .num_resources  = ARRAY_SIZE(imx1_camera_resources),
+};
+
+static struct resource imx_rtc_resources[] = {
+        {
+                .start  = 0x00204000,
+                .end    = 0x00204024,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_RTC_INT,
+                .end    = MX1_RTC_INT,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_RTC_SAMINT,
+                .end    = MX1_RTC_SAMINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_rtc_device = {
+        .name           = "rtc-imx",
+        .id             = 0,
+        .resource       = imx_rtc_resources,
+        .num_resources  = ARRAY_SIZE(imx_rtc_resources),
+};
+
+static struct resource imx_wdt_resources[] = {
+        {
+                .start  = 0x00201000,
+                .end    = 0x00201008,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_WDT_INT,
+                .end    = MX1_WDT_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_wdt_device = {
+        .name           = "imx-wdt",
+        .id             = 0,
+        .resource       = imx_wdt_resources,
+        .num_resources  = ARRAY_SIZE(imx_wdt_resources),
+};
+
+static struct resource imx_usb_resources[] = {
+        {
+                .start  = 0x00212000,
+                .end    = 0x00212148,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_USBD_INT0,
+                .end    = MX1_USBD_INT0,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT1,
+                .end    = MX1_USBD_INT1,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT2,
+                .end    = MX1_USBD_INT2,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT3,
+                .end    = MX1_USBD_INT3,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT4,
+                .end    = MX1_USBD_INT4,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT5,
+                .end    = MX1_USBD_INT5,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT6,
+                .end    = MX1_USBD_INT6,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_usb_device = {
+        .name           = "imx_udc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(imx_usb_resources),
+        .resource       = imx_usb_resources,
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        {
+                .chip.label = "gpio-0",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+                .irq = MX1_GPIO_INT_PORTA,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        }, {
+                .chip.label = "gpio-1",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
+                .irq = MX1_GPIO_INT_PORTB,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        }, {
+                .chip.label = "gpio-2",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
+                .irq = MX1_GPIO_INT_PORTC,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        }, {
+                .chip.label = "gpio-3",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
+                .irq = MX1_GPIO_INT_PORTD,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
         }
+};
+
+int __init imx1_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
+#endif
 
-DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
-DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 
 #ifdef CONFIG_MACH_MX27
-DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
+static struct resource mx27_camera_resources[] = {
+        {
+               .start = MX27_CSI_BASE_ADDR,
+               .end = MX27_CSI_BASE_ADDR + 0x1f,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MX27_EMMA_PRP_BASE_ADDR,
+               .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MX27_INT_CSI,
+               .end = MX27_INT_CSI,
+               .flags = IORESOURCE_IRQ,
+        },{
+               .start = MX27_INT_EMMAPRP,
+               .end = MX27_INT_EMMAPRP,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mx27_camera_device = {
+        .name = "mx2-camera",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mx27_camera_resources),
+        .resource = mx27_camera_resources,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
 #endif
 
 /*
@@ -140,34 +285,6 @@ struct platform_device mxc_w1_master_device = {
         .resource = mxc_w1_master_resources,
 };
 
-#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq)                      \
-        static struct resource pfx ## _nand_resources[] = {             \
-                {                                                       \
-                        .start = baseaddr,                              \
-                        .end = baseaddr + SZ_4K - 1,                    \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = irq,                                   \
-                        .end = irq,                                     \
-                        .flags = IORESOURCE_IRQ,                        \
-                },                                                      \
-        };                                                              \
-                                                                        \
-        struct platform_device pfx ## _nand_device = {                  \
-                .name = "mxc_nand",                                     \
-                .id = 0,                                                \
-                .num_resources = ARRAY_SIZE(pfx ## _nand_resources),    \
-                .resource = pfx ## _nand_resources,                     \
-        }
-
-#ifdef CONFIG_MACH_MX21
-DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
-#endif
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
-#endif
-
 /*
  * lcdc:
  * - i.MX1: the basic controller
@@ -218,32 +335,6 @@ struct platform_device mxc_fec_device = {
 };
 #endif
 
-#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)                         \
-        static struct resource mxc_i2c_resources ## n[] = {             \
-                {                                                       \
-                        .start = baseaddr,                              \
-                        .end = baseaddr + SZ_4K - 1,                    \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = irq,                                   \
-                        .end = irq,                                     \
-                        .flags = IORESOURCE_IRQ,                        \
-                }                                                       \
-        };                                                              \
-                                                                        \
-        struct platform_device mxc_i2c_device ## n = {                  \
-                .name = "imx-i2c",                                      \
-                .id = n,                                                \
-                .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n),    \
-                .resource = mxc_i2c_resources ## n,                     \
-        }
-
-DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
-#endif
-
 static struct resource mxc_pwm_resources[] = {
         {
                 .start = MX2x_PWM_BASE_ADDR,
@@ -454,26 +545,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
 #ifdef CONFIG_MACH_MX21
 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
+
+int __init imx21_register_gpios(void)
+{
+        return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
+}
 #endif
 
 #ifdef CONFIG_MACH_MX27
 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
-#endif
 
-int __init mxc_register_gpios(void)
+int __init imx27_register_gpios(void)
 {
-#ifdef CONFIG_MACH_MX21
-        if (cpu_is_mx21())
-                return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
-        else
-#endif
-#ifdef CONFIG_MACH_MX27
-        if (cpu_is_mx27())
-                return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
-        else
-#endif
-                return 0;
+        return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
 }
+#endif
 
 #ifdef CONFIG_MACH_MX21
 static struct resource mx21_usbhc_resources[] = {
@@ -501,3 +587,23 @@ struct platform_device mx21_usbhc_device = {
 };
 #endif
 
+static struct resource imx_kpp_resources[] = {
+        {
+                .start  = MX2x_KPP_BASE_ADDR,
+                .end    = MX2x_KPP_BASE_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MX2x_INT_KPP,
+                .end    = MX2x_INT_KPP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_kpp_device = {
+        .name = "imx-keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(imx_kpp_resources),
+        .resource = imx_kpp_resources,
+};
+
+#endif
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-imx/devices.h
index 84ed51380174..efd4527506a5 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -1,3 +1,11 @@
+#ifdef CONFIG_ARCH_MX1
+extern struct platform_device imx1_camera_device;
+extern struct platform_device imx_rtc_device;
+extern struct platform_device imx_wdt_device;
+extern struct platform_device imx_usb_device;
+#endif
+
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 extern struct platform_device mxc_gpt1;
 extern struct platform_device mxc_gpt2;
 #ifdef CONFIG_MACH_MX27
@@ -6,37 +14,19 @@ extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 #endif
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
-extern struct platform_device mxc_uart_device5;
 extern struct platform_device mxc_w1_master_device;
-#ifdef CONFIG_MACH_MX21
-extern struct platform_device imx21_nand_device;
-#endif
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device imx27_nand_device;
-#endif
 extern struct platform_device mxc_fb_device;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
-extern struct platform_device mxc_i2c_device0;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_i2c_device1;
-#endif
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mx27_camera_device;
 extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_spi_device2;
-#endif
 extern struct platform_device mx21_usbhc_device;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
+extern struct platform_device imx_kpp_device;
+#endif
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/mach-imx/dma-v1.c
index e16014b0d13c..3e8c47c63bac 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-mxc/dma-mx1-mx2.c
+ *  linux/arch/arm/plat-mxc/dma-v1.c
  *
  *  i.MX DMA registration and IRQ dispatching
  *
@@ -34,7 +34,7 @@
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
-#include <mach/dma-mx1-mx2.h>
+#include <mach/dma-v1.h>
 
 #define DMA_DCR     0x00                /* Control Register */
 #define DMA_DISR    0x04                /* Interrupt status Register */
@@ -310,7 +310,7 @@ imx_dma_setup_sg(int channel,
         imxdma->resbytes = dma_length;
 
         if (!sg || !sgcount) {
-                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
                        channel);
                 return -EINVAL;
         }
@@ -760,7 +760,6 @@ EXPORT_SYMBOL(imx_dma_free);
  * @name: the driver/caller own non-%NULL identification
  *
  * This function tries to find a free channel in the specified priority group
- * This function tries to find a free channel in the specified priority group
  * if the priority cannot be achieved it tries to look for free channel
  * in the higher and then even lower priority groups.
  *
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index f3b169d5245f..4edc5f439201 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
  *
  * Based on pcm970-baseboard.c which is :
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -24,6 +24,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/backlight.h>
+#include <video/platform_lcd.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach/arch.h>
 
@@ -32,8 +35,11 @@
 #include <mach/imxfb.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
-#include <mach/imx-uart.h>
+#include <mach/spi.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_mbimx27_pins[] = {
@@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = {
         PE10_PF_UART3_CTS,
         PE11_PF_UART3_RTS,
         /* UART4 */
+#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
         PB26_AF_UART4_RTS,
         PB28_AF_UART4_TXD,
         PB29_AF_UART4_CTS,
         PB31_AF_UART4_RXD,
+#endif
         /* SDHC1*/
         PE18_PF_SD1_D0,
         PE19_PF_SD1_D1,
@@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = {
         PA30_PF_CONTRAST,
         PA31_PF_OE_ACD,
         /* SPI1 */
-        PD28_PF_CSPI1_SS0,
         PD29_PF_CSPI1_SCLK,
         PD30_PF_CSPI1_MISO,
         PD31_PF_CSPI1_MOSI,
+        /* SSI4 */
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+        || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
+        PC16_PF_SSI4_FS,
+        PC17_PF_SSI4_RXD | GPIO_PUEN,
+        PC18_PF_SSI4_TXD | GPIO_PUEN,
+        PC19_PF_SSI4_CLK,
+#endif
+};
+
+static const uint32_t eukrea_mbimx27_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(1, 1, KEY_LEFT),
+};
+
+static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
+        .keymap         = eukrea_mbimx27_keymap,
+        .keymap_size    = ARRAY_SIZE(eukrea_mbimx27_keymap),
 };
 
 static struct gpio_led gpio_leds[] = {
@@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = {
                 .active_low             = 1,
                 .gpio                   = GPIO_PORTF | 19,
         },
-        {
-                .name                   = "backlight",
-                .default_trigger        = "backlight",
-                .active_low             = 0,
-                .gpio                   = GPIO_PORTE | 5,
-        },
 };
 
 static struct gpio_led_platform_data gpio_led_info = {
@@ -127,7 +148,7 @@ static struct platform_device leds_gpio = {
 static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
         {
                 .mode = {
-                        .name           = "CMO-QGVA",
+                        .name           = "CMO-QVGA",
                         .refresh        = 60,
                         .xres           = 320,
                         .yres           = 240,
@@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
                 },
                 .pcr            = 0xFAD08B80,
                 .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "DVI-VGA",
+                        .refresh        = 60,
+                        .xres           = 640,
+                        .yres           = 480,
+                        .pixclock       = 32000,
+                        .hsync_len      = 1,
+                        .left_margin    = 35,
+                        .right_margin   = 0,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 0,
+                },
+                .pcr            = 0xFA208B80,
+                .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "DVI-SVGA",
+                        .refresh        = 60,
+                        .xres           = 800,
+                        .yres           = 600,
+                        .pixclock       = 25000,
+                        .hsync_len      = 1,
+                        .left_margin    = 35,
+                        .right_margin   = 0,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 0,
+                },
+                .pcr            = 0xFA208B80,
+                .bpp            = 16,
         },
 };
 
@@ -153,16 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
         .dmacr          = 0x00040060,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
+static void eukrea_mbimx27_bl_set_intensity(int intensity)
+{
+        if (intensity)
+                gpio_direction_output(GPIO_PORTE | 5, 1);
+        else
+                gpio_direction_output(GPIO_PORTE | 5, 0);
+}
+
+static struct generic_bl_info eukrea_mbimx27_bl_info = {
+        .name                   = "eukrea_mbimx27-bl",
+        .max_intensity          = 0xff,
+        .default_intensity      = 0xff,
+        .set_bl_intensity       = eukrea_mbimx27_bl_set_intensity,
+};
+
+static struct platform_device eukrea_mbimx27_bl_dev = {
+        .name                   = "generic-bl",
+        .id                     = 1,
+        .dev = {
+                .platform_data  = &eukrea_mbimx27_bl_info,
         },
 };
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(GPIO_PORTA | 25, 1);
+        else
+                gpio_direction_output(GPIO_PORTA | 25, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
+        .set_power              = eukrea_mbimx27_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimx27_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.platform_data      = &eukrea_mbimx27_lcd_power_data,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
         || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 
 #define ADS7846_PENDOWN (GPIO_PORTD | 25)
@@ -173,7 +262,6 @@ static void ads7846_dev_init(void)
                 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
                 return;
         }
-
         gpio_direction_input(ADS7846_PENDOWN);
 }
 
@@ -186,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = {
         .get_pendown_state      = ads7846_get_pendown_state,
         .keep_vref_on           = 1,
 };
+#endif
 
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
         [0] = {
                 .modalias       = "ads7846",
@@ -201,16 +291,30 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
 
 static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
 
-static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
         .chipselect     = eukrea_mbimx27_spi_cs,
         .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
 };
 #endif
 
+static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
 static struct platform_device *platform_devices[] __initdata = {
         &leds_gpio,
 };
 
+static struct imxmmc_platform_data sdhc_pdata = {
+        .dat3_card_detect = 1,
+};
+
+struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
+        .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
+};
+
 /*
  * system init for baseboard usage. Will be called by cpuimx27 init.
  *
@@ -222,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void)
         mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
                 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+        || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
+        /* SSI unit master I2S codec connected to SSI_PINS_4*/
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_TFSDIR |
+                        MXC_AUDMUX_V1_PCR_TCLKDIR |
+                        MXC_AUDMUX_V1_PCR_RFSDIR |
+                        MXC_AUDMUX_V1_PCR_RCLKDIR |
+                        MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                        MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+        );
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+        );
+#endif
+
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
+#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
+        imx27_add_imx_uart3(&uart_pdata);
+#endif
 
         mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
-        mxc_register_device(&mxc_sdhc_device0, NULL);
+        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
+
+        mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
         || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        /* SPI and ADS7846 Touchscreen controler init */
-        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        /* ADS7846 Touchscreen controller init */
         mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
-        mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+        ads7846_dev_init();
+#endif
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        /* SPI_CS0 init */
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
         spi_register_board_info(eukrea_mbimx27_spi_board_info,
                         ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
-        ads7846_dev_init();
 #endif
 
         /* Leds configuration */
@@ -244,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void)
         mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
         /* Backlight */
         mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
+        gpio_request(GPIO_PORTE | 5, "backlight");
+        platform_device_register(&eukrea_mbimx27_bl_dev);
+        /* LCD Reset */
+        mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
+        gpio_request(GPIO_PORTA | 25, "lcd_enable");
+        platform_device_register(&eukrea_mbimx27_lcd_powerdev);
+
+        mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
new file mode 100644
index 000000000000..df5f522da6b3
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,10 @@
+#ifndef __MACH_DMA_MX1_MX2_H__
+#define __MACH_DMA_MX1_MX2_H__
+/*
+ * Don't use this header in new code, it will go away when all users are
+ * converted to mach/dma-v1.h
+ */
+
+#include <mach/dma-v1.h>
+
+#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-v1.h
index 7c4870bd5a21..287431cc13e5 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/mach-imx/include/mach/dma-v1.h
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+ *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
  *
  *  i.MX DMA registration and IRQ dispatching
  *
@@ -22,8 +22,10 @@
  * MA 02110-1301, USA.
  */
 
-#ifndef __ASM_ARCH_MXC_DMA_H
-#define __ASM_ARCH_MXC_DMA_H
+#ifndef __MACH_DMA_V1_H__
+#define __MACH_DMA_V1_H__
+
+#define imx_has_dma_v1()        (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
 #define IMX_DMA_CHANNELS  16
 
@@ -102,4 +104,4 @@ enum imx_dma_prio {
 
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
-#endif  /* _ASM_ARCH_MXC_DMA_H */
+#endif  /* __MACH_DMA_V1_H__ */
diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 1f616dcaabc9..575ff1ae85a7 100644
--- a/arch/arm/mach-mx2/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -26,20 +26,24 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include <mach/board-eukrea_cpuimx27.h>
+#include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_cpuimx27_pins[] = {
@@ -49,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = {
         PE14_PF_UART1_CTS,
         PE15_PF_UART1_RTS,
         /* UART4 */
+#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
         PB26_AF_UART4_RTS,
         PB28_AF_UART4_TXD,
         PB29_AF_UART4_CTS,
         PB31_AF_UART4_RXD,
+#endif
         /* FEC */
         PD0_AIN_FEC_TXD0,
         PD1_AIN_FEC_TXD1,
@@ -76,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = {
         PD17_PF_I2C_DATA,
         PD18_PF_I2C_CLK,
         /* SDHC2 */
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         PB4_PF_SD2_D0,
         PB5_PF_SD2_D1,
         PB6_PF_SD2_D2,
         PB7_PF_SD2_D3,
         PB8_PF_SD2_CMD,
         PB9_PF_SD2_CLK,
+#endif
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         /* Quad UART's IRQ */
-        GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
 #endif
+        /* OTG */
+        PC7_PF_USBOTG_DATA5,
+        PC8_PF_USBOTG_DATA6,
+        PC9_PF_USBOTG_DATA0,
+        PC10_PF_USBOTG_DATA2,
+        PC11_PF_USBOTG_DATA1,
+        PC12_PF_USBOTG_DATA4,
+        PC13_PF_USBOTG_DATA3,
+        PE0_PF_USBOTG_NXT,
+        PE1_PF_USBOTG_STP,
+        PE2_PF_USBOTG_DIR,
+        PE24_PF_USBOTG_CLK,
+        PE25_PF_USBOTG_DATA7,
+        /* USBH2 */
+        PA0_PF_USBH2_CLK,
+        PA1_PF_USBH2_DIR,
+        PA2_PF_USBH2_DATA7,
+        PA3_PF_USBH2_NXT,
+        PA4_PF_USBH2_STP,
+        PD19_AF_USBH2_DATA4,
+        PD20_AF_USBH2_DATA3,
+        PD21_AF_USBH2_DATA6,
+        PD22_AF_USBH2_DATA0,
+        PD23_AF_USBH2_DATA2,
+        PD24_AF_USBH2_DATA1,
+        PD26_AF_USBH2_DATA5,
 };
 
 static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
@@ -111,15 +145,12 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
         .resource = &eukrea_cpuimx27_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+static const struct mxc_nand_platform_data
+cpuimx27_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -127,9 +158,11 @@ static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_cpuimx27_nor_mtd_device,
         &mxc_fec_device,
+        &mxc_wdt,
+        &mxc_w1_master_device,
 };
 
-static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -182,34 +215,83 @@ static struct platform_device serial_device = {
 };
 #endif
 
+#if defined(CONFIG_USB_ULPI)
+static struct mxc_usbh_platform_data otg_pdata = {
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+#endif
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx27_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
+
 static void __init eukrea_cpuimx27_init(void)
 {
         mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
                 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+        imx27_add_imx_uart0(&uart_pdata);
 
-        mxc_register_device(&imx27_nand_device,
-                        &eukrea_cpuimx27_nand_board_info);
+        imx27_add_mxc_nand(&cpuimx27_nand_board_info);
 
         i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+        imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         /* SDHC2 can be used for Wifi */
         mxc_register_device(&mxc_sdhc_device1, NULL);
+#endif
+#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
         /* in which case UART4 is also used for Bluetooth */
-        mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+        imx27_add_imx_uart3(&uart_pdata);
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         platform_device_register(&serial_device);
 #endif
 
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+                mxc_register_device(&mxc_otg_host, &otg_pdata);
+        }
+
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+        if (!otg_mode_host)
+                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
 #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
         eukrea_mbimx27_baseboard_init();
 #endif
diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index b5710bf18b96..22a2b5d91213 100644
--- a/arch/arm/mach-mx2/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -26,10 +22,9 @@
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27lite.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27lite_pins[] = {
@@ -59,7 +54,7 @@ static unsigned int mx27lite_pins[] = {
         PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -71,7 +66,7 @@ static void __init mx27lite_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
                 "imx27lite");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx27_add_imx_uart0(&uart_pdata);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 51f3cfd83db2..77a760cfadc0 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -26,10 +26,10 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/i2c.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 #include <mach/irqs.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 static int mx1ads_pins[] = {
@@ -58,12 +58,12 @@ static int mx1ads_pins[] = {
  * UARTs platform data
  */
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart0_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+       
+static const struct imxuart_platform_data uart1_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 /*
@@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = {
 };
 
 static struct resource flash_resource = {
-        .start  = IMX_CS0_PHYS,
-        .end    = IMX_CS0_PHYS + SZ_32M - 1,
+        .start  = MX1_CS0_PHYS,
+        .end    = MX1_CS0_PHYS + SZ_32M - 1,
         .flags  = IORESOURCE_MEM,
 };
 
@@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = {
         }
 };
 
-static struct imxi2c_platform_data mx1ads_i2c_data = {
+static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -121,8 +121,8 @@ static void __init mx1ads_init(void)
                 ARRAY_SIZE(mx1ads_pins), "mx1ads");
 
         /* UART */
-        mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
-        mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
+        imx1_add_imx_uart0(&uart0_pdata);
+        imx1_add_imx_uart1(&uart1_pdata);
 
         /* Physmap flash */
         mxc_register_device(&flash_device, &mx1ads_flash_data);
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
         i2c_register_board_info(0, mx1ads_i2c_devices,
                                 ARRAY_SIZE(mx1ads_i2c_devices));
 
-        mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
+        imx1_add_i2c_imx(&mx1ads_i2c_data);
 }
 
 static void __init mx1ads_timer_init(void)
@@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = {
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
         /* Maintainer: Sascha Hauer, Pengutronix */
-        .phys_io        = IMX_IO_PHYS,
-        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
+        .phys_io        = MX1_IO_BASE_ADDR,
+        .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX1_PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
         .init_irq       = mx1_init_irq,
@@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-        .phys_io        = IMX_IO_PHYS,
-        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
+        .phys_io        = MX1_IO_BASE_ADDR,
+        .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX1_PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
         .init_irq       = mx1_init_irq,
diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 113e58d7cb40..96d7f8189f32 100644
--- a/arch/arm/mach-mx2/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -28,15 +24,49 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/imx-uart.h>
 #include <mach/imxfb.h>
 #include <mach/iomux-mx21.h>
 #include <mach/mxc_nand.h>
 #include <mach/mmc.h>
-#include <mach/board-mx21ads.h>
 
+#include "devices-imx21.h"
 #include "devices.h"
 
+/*
+ * Memory-mapped I/O on MX21ADS base board
+ */
+#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
+#define MX21ADS_MMIO_SIZE        SZ_16M
+
+#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
+                (MX21ADS_MMIO_BASE_ADDR + (offset))
+
+#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
+#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
+#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
+#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
+
+/* MX21ADS_IO_REG bit definitions */
+#define MX21ADS_IO_SD_WP        0x0001 /* read */
+#define MX21ADS_IO_TP6          0x0001 /* write */
+#define MX21ADS_IO_SW_SEL       0x0002 /* read */
+#define MX21ADS_IO_TP7          0x0002 /* write */
+#define MX21ADS_IO_RESET_E_UART 0x0004
+#define MX21ADS_IO_RESET_BASE   0x0008
+#define MX21ADS_IO_CSI_CTL2     0x0010
+#define MX21ADS_IO_CSI_CTL1     0x0020
+#define MX21ADS_IO_CSI_CTL0     0x0040
+#define MX21ADS_IO_UART1_EN     0x0080
+#define MX21ADS_IO_UART4_EN     0x0100
+#define MX21ADS_IO_LCDON        0x0200
+#define MX21ADS_IO_IRDA_EN      0x0400
+#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
+#define MX21ADS_IO_IRDA_MD0_B   0x1000
+#define MX21ADS_IO_IRDA_MD1     0x2000
+#define MX21ADS_IO_LED4_ON      0x4000
+#define MX21ADS_IO_LED3_ON      0x8000
+
 static unsigned int mx21ads_pins[] = {
 
         /* CS8900A */
@@ -133,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = {
         .resource = &mx21ads_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata_rts __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxuart_platform_data uart_norts_pdata = {
+static const struct imxuart_platform_data uart_pdata_norts __initconst = {
 };
 
-
 static int mx21ads_fb_init(struct platform_device *pdev)
 {
         u16 tmp;
@@ -227,7 +256,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
         .exit = mx21ads_sdhc_exit,
 };
 
-static struct mxc_nand_platform_data mx21ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx21ads_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -263,12 +293,12 @@ static void __init mx21ads_board_init(void)
         mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
                         "mx21ads");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
-        mxc_register_device(&mxc_uart_device3, &uart_pdata);
+        imx21_add_imx_uart0(&uart_pdata_rts);
+        imx21_add_imx_uart2(&uart_pdata_norts);
+        imx21_add_imx_uart3(&uart_pdata_rts);
         mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
-        mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
+        imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index b2f4e0db3fb3..e66ffaa1c26c 100644
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -12,23 +12,25 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX27 3-Stack Development System
+ *  - i.MX27 Platform Development Kit (i.MX27 PDK)
  */
 
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/input/matrix_keypad.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27pdk.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27pdk_pins[] = {
@@ -58,7 +60,7 @@ static unsigned int mx27pdk_pins[] = {
         PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -66,12 +68,34 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_fec_device,
 };
 
+/*
+ * Matrix keyboard
+ */
+
+static const uint32_t mx27_3ds_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(1, 1, KEY_LEFT),
+        KEY(1, 2, KEY_ENTER),
+        KEY(2, 0, KEY_F6),
+        KEY(2, 1, KEY_F8),
+        KEY(2, 2, KEY_F9),
+        KEY(2, 3, KEY_F10),
+};
+
+static struct matrix_keymap_data mx27_3ds_keymap_data = {
+        .keymap         = mx27_3ds_keymap,
+        .keymap_size    = ARRAY_SIZE(mx27_3ds_keymap),
+};
+
 static void __init mx27pdk_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
                 "mx27pdk");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx27_add_imx_uart0(&uart_pdata);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 6ce323669e58..9c77da98a10e 100644
--- a/arch/arm/mach-mx2/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -32,16 +28,44 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <mach/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27ads.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xf4300000
+#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
+                (PBC_BASE_ADDRESS + (offset))
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+
 static unsigned int mx27ads_pins[] = {
         /* UART0 */
         PE12_PF_UART1_TXD,
@@ -141,7 +165,8 @@ static unsigned int mx27ads_pins[] = {
         PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mx27ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx27ads_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -168,7 +193,7 @@ static struct platform_device mx27ads_nor_mtd_device = {
         .resource = &mx27ads_flash_resource,
 };
 
-static struct imxi2c_platform_data mx27ads_i2c_data = {
+static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -263,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_w1_master_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mx27ads_board_init(void)
@@ -284,18 +297,18 @@ static void __init mx27ads_board_init(void)
         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
                         "mx27ads");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-        mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
-        mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
-        mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
-        mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
+        imx27_add_imx_uart0(&uart_pdata);
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
+        imx27_add_imx_uart3(&uart_pdata);
+        imx27_add_imx_uart4(&uart_pdata);
+        imx27_add_imx_uart5(&uart_pdata);
+        imx27_add_mxc_nand(&mx27ads_nand_board_info);
 
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, mx27ads_i2c_devices,
                                 ARRAY_SIZE(mx27ads_i2c_devices));
-        mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
+        imx27_add_i2c_imx1(&mx27ads_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
         mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
@@ -342,4 +355,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         .init_machine   = mx27ads_board_init,
         .timer          = &mx27ads_timer,
 MACHINE_END
-
diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index bc3855992677..a3a1e452d4c5 100644
--- a/arch/arm/mach-mx2/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -32,14 +28,13 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mxt_td60_pins[] __initdata = {
@@ -128,12 +123,13 @@ static unsigned int mxt_td60_pins[] __initdata = {
         PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
+static const struct mxc_nand_platform_data
+mxt_td60_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -173,7 +169,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = {
         },
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c2_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -239,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_fec_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mxt_td60_board_init(void)
@@ -254,10 +244,10 @@ static void __init mxt_td60_board_init(void)
         mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
                         "MXT_TD60");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-        mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
+        imx27_add_imx_uart0(&uart_pdata);
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
+        imx27_add_mxc_nand(&mxt_td60_nand_board_info);
 
         i2c_register_board_info(0, mxt_td60_i2c_devices,
                                 ARRAY_SIZE(mxt_td60_i2c_devices));
@@ -265,8 +255,8 @@ static void __init mxt_td60_board_init(void)
         i2c_register_board_info(1, mxt_td60_i2c2_devices,
                                 ARRAY_SIZE(mxt_td60_i2c2_devices));
 
-        mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
-        mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
+        imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
+        imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
 
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index a87422ed4ff5..6c92deaf468f 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,12 +36,7 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/i2c.h>
 #include <asm/mach/time.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
-#include <mach/imx-uart.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 #include <mach/mxc_nand.h>
@@ -49,11 +44,16 @@
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
+#include <mach/imxfb.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
+#define SPI1_SS0 (GPIO_PORTD + 28)
+#define SPI1_SS1 (GPIO_PORTD + 27)
+#define SD2_CD (GPIO_PORTC + 29)
 
 static int pca100_pins[] = {
         /* UART1 */
@@ -68,6 +68,7 @@ static int pca100_pins[] = {
         PB7_PF_SD2_D3,
         PB8_PF_SD2_CMD,
         PB9_PF_SD2_CLK,
+        SD2_CD | GPIO_GPIO | GPIO_IN,
         /* FEC */
         PD0_AIN_FEC_TXD0,
         PD1_AIN_FEC_TXD1,
@@ -131,13 +132,42 @@ static int pca100_pins[] = {
         PD23_AF_USBH2_DATA2,
         PD24_AF_USBH2_DATA1,
         PD26_AF_USBH2_DATA5,
+        /* display */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA26_PF_PS,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA31_PF_OE_ACD,
+        /* free GPIO */
+        GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
+        GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
+        GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data pca100_nand_board_info = {
+static const struct mxc_nand_platform_data
+pca100_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -148,7 +178,7 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_wdt,
 };
 
-static struct imxi2c_platform_data pca100_i2c_1_data = {
+static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -189,9 +219,9 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
         },
 };
 
-static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
-static struct spi_imx_master pca100_spi_0_data = {
+static const struct spi_imx_master pca100_spi0_data __initconst = {
         .chipselect     = pca100_spi_cs,
         .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
@@ -253,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = {
         .exit = pca100_sdhc2_exit,
 };
 
+#if defined(CONFIG_USB_ULPI)
 static int otg_phy_init(struct platform_device *pdev)
 {
         gpio_set_value(OTG_PHY_CS_GPIO, 0);
@@ -276,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -297,6 +329,45 @@ static int __init pca100_otg_mode(char *options)
 }
 __setup("otg_mode=", pca100_otg_mode);
 
+/* framebuffer info */
+static struct imx_fb_videomode pca100_fb_modes[] = {
+        {
+                .mode = {
+                        .name           = "EMERGING-ETV570G0DHU",
+                        .refresh        = 60,
+                        .xres           = 640,
+                        .yres           = 480,
+                        .pixclock       = 39722, /* in ps (25.175 MHz) */
+                        .hsync_len      = 30,
+                        .left_margin    = 114,
+                        .right_margin   = 16,
+                        .vsync_len      = 3,
+                        .upper_margin   = 32,
+                        .lower_margin   = 0,
+                },
+                /*
+                 * TFT
+                 * Pixel pol active high
+                 * HSYNC active low
+                 * VSYNC active low
+                 * use HSYNC for ACD count
+                 * line clock disable while idle
+                 * always enable line clock even if no data
+                 */
+                .pcr = 0xf0c08080,
+                .bpp = 16,
+        },
+};
+
+static struct imx_fb_platform_data pca100_fb_data = {
+        .mode = pca100_fb_modes,
+        .num_modes = ARRAY_SIZE(pca100_fb_modes),
+
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020010,
+};
+
 static void __init pca100_init(void)
 {
         int ret;
@@ -320,33 +391,24 @@ static void __init pca100_init(void)
 
         mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx27_add_imx_uart0(&uart_pdata);
 
-        mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
         mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 
-        mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
+        imx27_add_mxc_nand(&pca100_nand_board_info);
 
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, pca100_i2c_devices,
                                 ARRAY_SIZE(pca100_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
-
-        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
-
-        /* GPIO0_IRQ */
-        mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
-        /* GPIO1_IRQ */
-        mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
-        /* GPIO2_IRQ */
-        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
+        imx27_add_i2c_imx1(&pca100_i2c1_data);
 
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
+        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
         spi_register_board_info(pca100_spi_board_info,
                                 ARRAY_SIZE(pca100_spi_board_info));
-        mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+        imx27_add_spi_imx0(&pca100_spi_0_data);
 #endif
 
         gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
@@ -372,6 +434,8 @@ static void __init pca100_init(void)
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
         }
 
+        mxc_register_device(&mxc_fb_device, &pca100_fb_data);
+
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 36c89431679a..9212e8f37001 100644
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -35,14 +35,12 @@
 #include <mach/board-pcm038.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int pcm038_pins[] = {
@@ -162,17 +160,12 @@ static struct platform_device pcm038_nor_mtd_device = {
         .resource = &pcm038_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data pcm038_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm038_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -192,7 +185,7 @@ static void __init pcm038_init_sram(void)
         mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
 }
 
-static struct imxi2c_platform_data pcm038_i2c_1_data = {
+static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -215,7 +208,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
 
 static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
 
-static struct spi_imx_master pcm038_spi_0_data = {
+static const struct spi_imx_master pcm038_spi0_data __initconst = {
         .chipselect = pcm038_spi_cs,
         .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
 };
@@ -305,18 +298,18 @@ static void __init pcm038_init(void)
 
         pcm038_init_sram();
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+        imx27_add_imx_uart0(&uart_pdata);
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
 
         mxc_gpio_mode(PE16_AF_OWIRE);
-        mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
+        imx27_add_mxc_nand(&pcm038_nand_board_info);
 
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, pcm038_i2c_devices,
                                 ARRAY_SIZE(pcm038_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
+        imx27_add_i2c_imx1(&pcm038_i2c1_data);
 
         /* PE18 for user-LED D40 */
         mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@@ -326,7 +319,7 @@ static void __init pcm038_init(void)
         /* MC13783 IRQ */
         mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
 
-        mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data);
+        imx27_add_spi_imx0(&pcm038_spi0_data);
         spi_register_board_info(pcm038_spi_board_info,
                                 ARRAY_SIZE(pcm038_spi_board_info));
 
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 7587a7a12460..88bf0d1e26e6 100644
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -22,17 +22,17 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 /*
  * This scb9328 has a 32MiB flash
  */
 static struct resource flash_resource = {
-        .start  = IMX_CS0_PHYS,
-        .end    = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1,
+        .start  = MX1_CS0_PHYS,
+        .end    = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
         .flags  = IORESOURCE_MEM,
 };
 
@@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = {
 static struct resource dm9000x_resources[] = {
         {
                 .name   = "address area",
-                .start  = IMX_CS5_PHYS,
-                .end    = IMX_CS5_PHYS + 1,
+                .start  = MX1_CS5_PHYS,
+                .end    = MX1_CS5_PHYS + 1,
                 .flags  = IORESOURCE_MEM,       /* address access */
         }, {
                 .name   = "data area",
-                .start  = IMX_CS5_PHYS + 4,
-                .end    = IMX_CS5_PHYS + 5,
+                .start  = MX1_CS5_PHYS + 4,
+                .end    = MX1_CS5_PHYS + 5,
                 .flags  = IORESOURCE_MEM,       /* data access */
         }, {
                 .start  = IRQ_GPIOC(3),
@@ -108,14 +108,13 @@ static int uart1_mxc_init(struct platform_device *pdev)
                         ARRAY_SIZE(mxc_uart1_pins), "UART1");
 }
 
-static int uart1_mxc_exit(struct platform_device *pdev)
+static void uart1_mxc_exit(struct platform_device *pdev)
 {
         mxc_gpio_release_multiple_pins(mxc_uart1_pins,
                         ARRAY_SIZE(mxc_uart1_pins));
-        return 0;
 }
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .init = uart1_mxc_init,
         .exit = uart1_mxc_exit,
         .flags = IMXUART_HAVE_RTSCTS,
@@ -131,7 +130,7 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init scb9328_init(void)
 {
-        mxc_register_device(&imx_uart1_device, &uart_pdata);
+        imx1_add_imx_uart0(&uart_pdata);
 
         printk(KERN_INFO"Scb9328: Adding devices\n");
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-imx/mm-imx1.c
index 7f9fc1034c08..9be92b96dc89 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -3,7 +3,7 @@
  *  Created: april 20th, 2004
  *  Copyright: Synertronixx GmbH
  *
- *  Common code for i.MX machines
+ *  Common code for i.MX1 machines
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -31,23 +26,25 @@
 
 static struct map_desc imx_io_desc[] __initdata = {
         {
-                .virtual        = IMX_IO_BASE,
-                .pfn            = __phys_to_pfn(IMX_IO_PHYS),
-                .length         = IMX_IO_SIZE,
-                .type           = MT_DEVICE
+                .virtual = MX1_IO_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
+                .length = MX1_IO_SIZE,
+                .type = MT_DEVICE
         }
 };
 
 void __init mx1_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX1);
-        mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
+        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
 
         iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
 
+int imx1_register_gpios(void);
+
 void __init mx1_init_irq(void)
 {
-        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+        mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
+        imx1_register_gpios();
 }
-
diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 64134314d012..12faeeaa0a97 100644
--- a/arch/arm/mach-mx2/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx21.c
+ * arch/arm/mach-imx/mm-imx21.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
@@ -77,7 +77,10 @@ void __init mx21_map_io(void)
         iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
 }
 
+int imx21_register_gpios(void);
+
 void __init mx21_init_irq(void)
 {
         mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
+        imx21_register_gpios();
 }
diff --git a/arch/arm/mach-mx2/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 3366ed44cfd5..a24622957ff2 100644
--- a/arch/arm/mach-mx2/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx27.c
+ * arch/arm/mach-imx/mm-imx27.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
@@ -77,7 +77,10 @@ void __init mx27_map_io(void)
         iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
 }
 
+int imx27_register_gpios(void);
+
 void __init mx27_init_irq(void)
 {
         mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
+        imx27_register_gpios();
 }
diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
index b09ee12a4ff0..b09ee12a4ff0 100644
--- a/arch/arm/mach-mx1/ksym_mx1.c
+++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S
index 9c69aa65bf17..9c69aa65bf17 100644
--- a/arch/arm/mach-mx1/mx1_camera_fiq.S
+++ b/arch/arm/mach-imx/mx1-camera-fiq.S
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index f490a406d57e..f490a406d57e 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
new file mode 100644
index 000000000000..afc17ce0bb54
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -0,0 +1,46 @@
+/*
+ * i.MX27 Power Management Routines
+ *
+ * Based on Freescale's BSP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <mach/system.h>
+#include <mach/mx27.h>
+
+static int mx27_suspend_enter(suspend_state_t state)
+{
+        u32 cscr;
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                /* Clear MPEN and SPEN to disable MPLL/SPLL */
+                cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+                cscr &= 0xFFFFFFFC;
+                __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+                /* Executes WFI */
+                arch_idle();
+                break;
+
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static struct platform_suspend_ops mx27_suspend_ops = {
+        .enter = mx27_suspend_enter,
+        .valid = suspend_valid_only_mem,
+};
+
+static int __init mx27_pm_init(void)
+{
+        suspend_set_ops(&mx27_suspend_ops);
+        return 0;
+}
+
+device_initcall(mx27_pm_init);
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
new file mode 100644
index 000000000000..5f96e1518aa9
--- /dev/null
+++ b/arch/arm/mach-integrator/common.h
@@ -0,0 +1 @@
+void integrator_reserve(void);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index b02cfc06e0ae..8f4fb6d638f7 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -14,6 +14,7 @@
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/memblock.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/termios.h>
@@ -30,6 +31,7 @@
 #include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
+#include <asm/pgtable.h>
 
 static struct amba_pl010_data integrator_uart_data;
 
@@ -119,8 +121,13 @@ static struct clk uartclk = {
         .rate   = 14745600,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-        {       /* UART0 */
+        {       /* Bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "mb:16",
                 .clk            = &uartclk,
         }, {    /* UART1 */
@@ -215,3 +222,13 @@ void cm_control(u32 mask, u32 set)
 }
 
 EXPORT_SYMBOL(cm_control);
+
+/*
+ * We need to stop things allocating the low memory; ideally we need a
+ * better implementation of GFP_DMA which does not assume that DMA-able
+ * memory starts at zero.
+ */
+void __init integrator_reserve(void)
+{
+        memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
+}
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 227cf4d05088..6ab5a03ab9d8 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -48,6 +48,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
+#include "common.h"
+
 /* 
  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  * is the (PA >> 12).
@@ -502,6 +504,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = ap_map_io,
+        .reserve        = integrator_reserve,
         .init_irq       = ap_init_irq,
         .timer          = &ap_timer,
         .init_machine   = ap_init,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index cde57b2b83b5..05db40e3c4f7 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -43,6 +43,8 @@
 
 #include <plat/timer-sp.h>
 
+#include "common.h"
+
 #define INTCP_PA_FLASH_BASE             0x24000000
 #define INTCP_FLASH_SIZE                SZ_32M
 
@@ -601,6 +603,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = intcp_map_io,
+        .reserve        = integrator_reserve,
         .init_irq       = intcp_init_irq,
         .timer          = &cp_timer,
         .init_machine   = intcp_init,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 9cef0590d5aa..6467d99fa2ee 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -505,10 +505,10 @@ void __init pci_v3_preinit(void)
         /*
          * Hook in our fault handler for PCI errors
          */
-        hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch");
-        hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch");
-        hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
-        hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
+        hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
+        hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
+        hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
+        hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
 
         spin_lock_irqsave(&v3_lock, flags);
 
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 25b1da9a5035..7415e4338651 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -69,6 +69,4 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
 #endif /* CONFIG_ARCH_IOP13XX */
 #endif /* !ASSEMBLY */
 
-#define PFN_TO_NID(addr)        (0)
-
 #endif
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 6d5a90813d31..773ea0c95b9f 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -987,7 +987,7 @@ void __init iop13xx_pci_init(void)
                 iop13xx_atux_setup();
         }
 
-        hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
+        hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
                         "imprecise external abort");
 }
 
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 90771cad06f8..f797c5f538b0 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -209,7 +209,7 @@ ixp2000_pci_preinit(void)
                         "the needed workaround has not been configured in");
 #endif
 
-        hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS,
+        hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0,
                                 "PCI config cycle to non-existent device");
 }
 
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 4b0e598a91c9..563819a83292 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -229,7 +229,7 @@ void __init ixp23xx_pci_preinit(void)
 {
         ixp23xx_pci_common_init();
 
-        hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
+        hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
                         "PCI config cycle to non-existent device");
 
         *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index e3181534c7f9..61cd4d64b985 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -348,7 +348,7 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
  * This is really ugly and we need a better way of specifying
  * DMA-capable regions of memory.
  */
-void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
+void __init ixp4xx_adjust_zones(unsigned long *zone_size,
         unsigned long *zhole_size)
 {
         unsigned int sz = SZ_64M >> PAGE_SHIFT;
@@ -356,7 +356,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
         /*
          * Only adjust if > 64M on current system
          */
-        if (node || (zone_size[0] <= sz))
+        if (zone_size[0] <= sz)
                 return;
 
         zone_size[1] = zone_size[0] - sz;
@@ -382,7 +382,8 @@ void __init ixp4xx_pci_preinit(void)
 
 
         /* hook in our fault handler for PCI errors */
-        hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");
+        hook_fault_code(16+6, abort_handler, SIGBUS, 0,
+                        "imprecise external abort");
 
         pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 98f5e5e20980..0136eaa29224 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -16,10 +16,10 @@
 
 #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
 
-void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
+void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
 
-#define arch_adjust_zones(node, size, holes) \
-        ixp4xx_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+        ixp4xx_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD (SZ_64M - 1)
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_64M)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163b1fe3..cc25501b57fa 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
           Say 'Y' here if you want your kernel to support the
           Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+        bool "Marvell OpenRD Ultimate Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
         bool "LaCie Network Space v2 NAS Board"
         help
@@ -87,6 +94,12 @@ config MACH_INETSPACE_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Internet Space v2 NAS.
 
+config MACH_NETSPACE_MAX_V2
+        bool "LaCie Network Space Max v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space Max v2 NAS.
+
 config MACH_NET2BIG_V2
         bool "LaCie 2Big Network v2 NAS Board"
         help
@@ -99,6 +112,12 @@ config MACH_NET5BIG_V2
           Say 'Y' here if you want your kernel to support the
           LaCie 5Big Network v2 NAS.
 
+config MACH_T5325
+        bool "HP t5325 Thin Client"
+        help
+          Say 'Y' here if you want your kernel to support the
+          HP t5325 Thin Client.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index c0cd5d362002..295d7baa6ae1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
 obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
 obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o
 obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o
 obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o
+obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168fc699..8d03bcef5182 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0            0x3e
 #define ATTR_PCIE_IO            0xe0
 #define ATTR_PCIE_MEM           0xe8
+#define ATTR_PCIE1_IO           0xd0
+#define ATTR_PCIE1_MEM          0xd8
 #define ATTR_SRAM               0x01
 
 /*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
                       TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
         setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
                       TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
+        setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+                      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+        setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+                      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 
         /*
          * Setup window for NAND controller.
          */
-        setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+        setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
                       TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
         /*
          * Setup window for SRAM.
          */
-        setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+        setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
                       TARGET_SRAM, ATTR_SRAM, -1);
 
         /*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa5e66a..9dd67c7b4459 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
                 .length         = KIRKWOOD_PCIE_IO_SIZE,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
+                .length         = KIRKWOOD_PCIE1_IO_SIZE,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = KIRKWOOD_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
                 .length         = KIRKWOOD_REGS_SIZE,
@@ -402,7 +407,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
         u32 dev, rev;
 
         kirkwood_pcie_id(&dev, &rev);
-        if (rev == 0)  /* catch all Kirkwood Z0's */
+        if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
                 mvsdio_data->clock = 100000000;
         else
                 mvsdio_data->clock = 200000000;
@@ -847,8 +852,10 @@ int __init kirkwood_find_tclk(void)
         u32 dev, rev;
 
         kirkwood_pcie_id(&dev, &rev);
-        if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
-                                        rev == MV88F6281_REV_A1))
+
+        if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+                                        rev == MV88F6281_REV_A1)) ||
+            (dev == MV88F6282_DEV_ID))
                 return 200000000;
 
         return 166666667;
@@ -891,13 +898,22 @@ static char * __init kirkwood_id(void)
                         return "MV88F6192-Z0";
                 else if (rev == MV88F6192_REV_A0)
                         return "MV88F6192-A0";
+                else if (rev == MV88F6192_REV_A1)
+                        return "MV88F6192-A1";
                 else
                         return "MV88F6192-Rev-Unsupported";
         } else if (dev == MV88F6180_DEV_ID) {
                 if (rev == MV88F6180_REV_A0)
                         return "MV88F6180-Rev-A0";
+                else if (rev == MV88F6180_REV_A1)
+                        return "MV88F6180-Rev-A1";
                 else
                         return "MV88F6180-Rev-Unsupported";
+        } else if (dev == MV88F6282_DEV_ID) {
+                if (rev == MV88F6282_REV_A0)
+                        return "MV88F6282-Rev-A0";
+                else
+                        return "MV88F6282-Rev-Unsupported";
         } else {
                 return "Device-Unknown";
         }
@@ -949,12 +965,14 @@ void __init kirkwood_init(void)
 static int __init kirkwood_clock_gate(void)
 {
         unsigned int curr = readl(CLOCK_GATING_CTRL);
+        u32 dev, rev;
 
+        kirkwood_pcie_id(&dev, &rev);
         printk(KERN_DEBUG "Gating clock of unused units\n");
         printk(KERN_DEBUG "before: 0x%08x\n", curr);
 
         /* Make sure those units are accessible */
-        writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
+        writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
         /* For SATA: first shutdown the phy */
         if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -979,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
                 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
         }
 
+        /* For PCIe 1: first shutdown the phy */
+        if (dev == MV88F6282_DEV_ID) {
+                if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
+                        writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
+                        while (1)
+                                if (readl(PCIE1_STATUS) & 0x1)
+                                        break;
+                        writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
+                }
+        } else  /* keep this bit set for devices that don't have PCIe1 */
+                kirkwood_clk_ctrl |= CGC_PEX1;
+
         /* Now gate clock the required units */
         writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
         printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a5692e..5b2c1c18d641 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
 struct mtd_partition;
 struct mtd_info;
 
+#define KW_PCIE0        (1 << 0)
+#define KW_PCIE1        (1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4bcace9..16f6691e7c68 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
 };
 
 static unsigned int db88f6281_mpp_config[] __initdata = {
+        MPP0_NF_IO2,
+        MPP1_NF_IO3,
+        MPP2_NF_IO4,
+        MPP3_NF_IO5,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
         MPP37_GPIO,
         MPP38_GPIO,
         0
@@ -74,9 +82,15 @@ static void __init db88f6281_init(void)
 
 static int __init db88f6281_pci_init(void)
 {
-        if (machine_is_db88f6281_bp())
-                kirkwood_pcie_init();
+        if (machine_is_db88f6281_bp()) {
+                u32 dev, rev;
 
+                kirkwood_pcie_id(&dev, &rev);
+                if (dev == MV88F6282_DEV_ID)
+                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+                else
+                        kirkwood_pcie_init(KW_PCIE0);
+        }
         return 0;
 }
 subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f5017c50e..aff0e1327e38 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
 #define CGC_SATA1               (1 << 15)
 #define CGC_XOR1                (1 << 16)
 #define CGC_CRYPTO              (1 << 17)
+#define CGC_PEX1                (1 << 18)
 #define CGC_GE1                 (1 << 19)
 #define CGC_TDM                 (1 << 20)
-#define CGC_RESERVED            ((1 << 18) | (0x6 << 21))
+#define CGC_RESERVED            (0x6 << 21)
 
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a45a67e..9da2eb59180b 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10     7
 #define IRQ_KIRKWOOD_XOR_11     8
 #define IRQ_KIRKWOOD_PCIE       9
+#define IRQ_KIRKWOOD_PCIE1      10
 #define IRQ_KIRKWOOD_GE00_SUM   11
 #define IRQ_KIRKWOOD_GE01_SUM   15
 #define IRQ_KIRKWOOD_USB        19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0ee22bd..d141af4c2744 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
  * Marvell Kirkwood address maps.
  *
  * phys
- * e0000000     PCIe Memory space
+ * e0000000     PCIe #0 Memory space
+ * e8000000     PCIe #1 Memory space
  * f1000000     on-chip peripheral registers
- * f2000000     PCIe I/O space
- * f3000000     NAND controller address window
- * f4000000     Security Accelerator SRAM
+ * f2000000     PCIe #0 I/O space
+ * f3000000     PCIe #1 I/O space
+ * f4000000     NAND controller address window
+ * f5000000     Security Accelerator SRAM
  *
  * virt         phys            size
- * fee00000     f1000000        1M      on-chip peripheral registers
- * fef00000     f2000000        1M      PCIe I/O space
+ * fed00000     f1000000        1M      on-chip peripheral registers
+ * fee00000     f2000000        1M      PCIe #0 I/O space
+ * fef00000     f3000000        1M      PCIe #1 I/O space
  */
 
-#define KIRKWOOD_SRAM_PHYS_BASE         0xf4000000
+#define KIRKWOOD_SRAM_PHYS_BASE         0xf5000000
 #define KIRKWOOD_SRAM_SIZE              SZ_2K
 
-#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
+#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf4000000
 #define KIRKWOOD_NAND_MEM_SIZE          SZ_1K
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE     0xfef00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE          SZ_1M
+
 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
 
 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
+#define KIRKWOOD_REGS_VIRT_BASE         0xfed00000
 #define KIRKWOOD_REGS_SIZE              SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
 #define KIRKWOOD_PCIE_MEM_BUS_BASE      0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE    0xe8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE     0xe8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE         SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +84,9 @@
 #define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL          (PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS             (PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_STATUS            (PCIE1_VIRT_BASE | 0x1a04)
 
 #define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
@@ -107,8 +122,12 @@
 #define MV88F6192_DEV_ID        0x6192
 #define MV88F6192_REV_Z0        0
 #define MV88F6192_REV_A0        2
+#define MV88F6192_REV_A1        3
 
 #define MV88F6180_DEV_ID        0x6180
 #define MV88F6180_REV_A0        2
+#define MV88F6180_REV_A1        3
 
+#define MV88F6282_DEV_ID        0x6282
+#define MV88F6282_REV_A0        0
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
new file mode 100644
index 000000000000..e21272e5f668
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/leds-ns2.h
+ *
+ * Platform data structure for Network Space v2 LED driver
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_LEDS_NS2_H
+#define __MACH_LEDS_NS2_H
+
+struct ns2_led {
+        const char      *name;
+        const char      *default_trigger;
+        unsigned        cmd;
+        unsigned        slow;
+};
+
+struct ns2_led_platform_data {
+        int             num_leds;
+        struct ns2_led  *leds;
+};
+
+#endif /* __MACH_LEDS_NS2_H */
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f64e38c..065187d177c6 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
 
         kirkwood_pcie_id(&dev, &rev);
 
-        if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
+        if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
+            (dev == MV88F6282_DEV_ID))
                 return MPP_F6281_MASK;
         if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
                 return MPP_F6192_MASK;
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278ed311..9b0a94d85c3e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
 #ifndef __KIRKWOOD_MPP_H
 #define __KIRKWOOD_MPP_H
 
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
         /* MPP number */                ((_num) & 0xff) | \
         /* MPP select value */          (((_sel) & 0xf) << 8) | \
         /* may be input signal */       ((!!(_in)) << 12) | \
@@ -19,282 +19,332 @@
         /* available on F6180 */        ((!!(_F6180)) << 14) | \
         /* available on F6190 */        ((!!(_F6190)) << 15) | \
         /* available on F6192 */        ((!!(_F6192)) << 16) | \
-        /* available on F6281 */        ((!!(_F6281)) << 17))
+        /* available on F6281 */        ((!!(_F6281)) << 17) | \
+        /* available on F6282 */        ((!!(_F6282)) << 18))
 
 #define MPP_NUM(x)      ((x) & 0xff)
 #define MPP_SEL(x)      (((x) >> 8) & 0xf)
 
-                                /*   num sel  i  o  6180 6190 6192 6281 */
-
-#define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
-#define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
-
-#define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
-#define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
-#define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
-#define MPP_F6281_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
-
-#define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP0_NF_IO2             MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP1_NF_IO3             MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP2_NF_IO4             MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP3_NF_IO5             MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP3_SPI_MISO           MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
-
-#define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP4_NF_IO6             MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP4_UART0_RXD          MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP4_PTP_CLK            MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP5_NF_IO7             MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
-#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
-#define MPP8_TW_SDA             MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP8_MII0_RXERR         MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
-#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP8_PTP_CLK            MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP8_MII0_COL           MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP9_TW_SCK             MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP9_UART0_CTS          MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP9_UART1_CTS          MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP9_MII0_CRS           MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
-
-#define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP11_SPI_MISO          MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP11_UART0_RXD         MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
-#define MPP11_PTP_CLK           MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
-#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
-
-#define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP13_SD_CMD            MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP14_SD_D0             MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP14_UART1_RXD         MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP14_MII0_COL          MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP15_SD_D1             MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP16_SD_D2             MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP16_UART0_CTS         MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP16_UART1_RXD         MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP16_MII0_CRS          MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SD_D3             MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP18_NF_IO0            MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP19_NF_IO1            MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP20_TSMP0             MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP20_GE1_0             MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP20_AUDIO_SPDIFI      MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
-#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP21_TSMP1             MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP21_GE1_1             MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP21_AUDIO_SPDIFO      MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP22_TSMP2             MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP22_GE1_2             MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP23_TSMP3             MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP23_GE1_3             MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP23_AUDIO_I2SBCLK     MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP24_TSMP4             MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP24_TDM_SPI_CS0       DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP24_GE1_4             MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP24_AUDIO_I2SDO       MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP25_TSMP5             MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP25_GE1_5             MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP25_AUDIO_I2SLRCLK    MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP26_TSMP6             MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP26_GE1_6             MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP26_AUDIO_I2SMCLK     MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP27_TSMP7             MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP27_GE1_7             MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP27_AUDIO_I2SDI       MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP28_TSMP8             MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP28_GE1_8             MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP28_AUDIO_EXTCLK      MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP29_TSMP9             MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP29_GE1_9             MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP30_TSMP10            MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP30_TDM_PCLK          MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP30_GE1_10            MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP31_TSMP11            MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP31_TDM_FS            MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP31_GE1_11            MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP32_TSMP12            MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP32_TDM_DRX           MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP32_GE1_12            MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP33_GPIO              MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP33_GE1_13            MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP34_GE1_14            MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP35_GE1_15            MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP35_MII0_RXERR        MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
-
-#define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP36_TSMP0             MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP36_AUDIO_SPDIFI      MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP37_TSMP1             MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP37_AUDIO_SPDIFO      MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP38_TSMP2             MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP39_TSMP3             MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP39_AUDIO_I2SBCLK     MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP40_TSMP4             MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP40_AUDIO_I2SDO       MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP41_TSMP5             MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
-#define MPP41_AUDIO_I2SLRC      MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP42_TSMP6             MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP42_AUDIO_I2SMCLK     MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP43_TSMP7             MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP43_AUDIO_I2SDI       MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP44_TSMP8             MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP44_AUDIO_EXTCLK      MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TSMP9             MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TDM_PCLK          MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TSMP10            MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TDM_FS            MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TSMP11            MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TDM_DRX           MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
-
-#define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
-
-#define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP49_PTP_CLK           MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
+                                /*   num sel  i  o  6180 6190 6192 6281 6282 */
+
+#define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
+#define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
+
+#define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
+#define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
+#define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
+#define MPP_F6281_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   1,   0 )
+#define MPP_F6282_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_NF_IO2             MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP1_NF_IO3             MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP2_NF_IO4             MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP3_NF_IO5             MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP3_SPI_MISO           MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_NF_IO6             MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_UART0_RXD          MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP4_LCD_VGA_HSYNC      MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP4_PTP_CLK            MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+
+#define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_NF_IO7             MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP5_LCD_VGA_VSYNC      MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_LCD_PWM            MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_TW0_SDA            MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_MII0_RXERR         MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
+#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP8_PTP_CLK            MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP8_MII0_COL           MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_TW0_SCK            MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_UART0_CTS          MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_UART1_CTS          MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP9_MII0_CRS           MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP11_SPI_MISO          MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_UART0_RXD         MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_CLK           MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+
+#define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_TW1_SDA           MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
+
+#define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_SD_CMD            MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP13_AU_SPDIFRMCLK     MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP13_LCDPWM            MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_SD_D0             MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_UART1_RXD         MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP14_AU_SPDIFI         MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_AU_I2SDI          MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_MII0_COL          MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SD_D1             MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP15_SPI_CSn           MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_SD_D2             MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_UART0_CTS         MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_UART1_RXD         MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP16_LCD_EXT_REF_CLK   MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP16_MII0_CRS          MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SD_D3             MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP17_SATA1_ACTn        MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP17_TW1_SCK           MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP18_NF_IO0            MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP18_PEX0_CLKREQ       MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP19_NF_IO1            MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+
+#define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP20_TSMP0             MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_GE1_TXD0          MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP20_AU_SPDIFI         MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_LCD_D0            MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP21_TSMP1             MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_GE1_TXD1          MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP21_AU_SPDIFO         MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP21_LCD_D1            MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP22_TSMP2             MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_GE1_TXD2          MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP22_AU_SPDIFRMKCLK    MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_LCD_D2            MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP23_TSMP3             MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP23_GE1_TXD3          MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP23_AU_I2SBCLK        MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP23_LCD_D3            MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP24_TSMP4             MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP24_TDM_SPI_CS0       MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_GE1_RXD0          MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP24_AU_I2SDO          MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_LCD_D4            MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP25_TSMP5             MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_GE1_RXD1          MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP25_AU_I2SLRCLK       MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_LCD_D5            MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP26_TSMP6             MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP26_GE1_RXD2          MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP26_AU_I2SMCLK        MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP26_LCD_D6            MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP27_TSMP7             MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP27_GE1_RXD3          MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP27_AU_I2SDI          MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP27_LCD_D7            MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP28_TSMP8             MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP28_GE1_COL           MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP28_AU_EXTCLK         MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP28_LCD_D8            MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP29_TSMP9             MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP29_GE1_TCLK          MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP29_LCD_D9            MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP30_TSMP10            MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_TDM_PCLK          MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_GE1_RXCTL         MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP30_LCD_D10           MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP31_TSMP11            MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_TDM_FS            MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_GE1_RXCLK         MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP31_LCD_D11           MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP32_TSMP12            MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP32_TDM_DRX           MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP32_GE1_TCLKOUT       MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP32_LCD_D12           MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP33_GPO               MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP33_GE1_TXCTL         MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP33_LCD_D13           MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP34_GE1_TXEN          MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP34_SATA1_ACTn        MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP34_LCD_D14           MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP35_GE1_RXERR         MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP35_LCD_D15           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP35_MII0_RXERR        MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP36_TSMP0             MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP36_AU_SPDIFI         MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP36_TW1_SDA           MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TSMP1             MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP37_AU_SPDIFO         MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TW1_SCK           MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP38_TSMP2             MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP38_AU_SPDIFRMLCLK    MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP38_LCD_D18           MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP39_TSMP3             MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP39_AU_I2SBCLK        MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP39_LCD_D19           MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP40_TSMP4             MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP40_AU_I2SDO          MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP40_LCD_D20           MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP41_TSMP5             MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP41_AU_I2SLRCLK       MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP41_LCD_D21           MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP42_TSMP6             MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP42_AU_I2SMCLK        MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP42_LCD_D22           MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP43_TSMP7             MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP43_AU_I2SDI          MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP43_LCD_D23           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP44_TSMP8             MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP44_AU_EXTCLK         MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP44_LCD_CLK           MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TSMP9             MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TDM_PCLK          MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP245_LCD_E            MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TSMP10            MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TDM_FS            MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_LCD_HSYNC         MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TSMP11            MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TDM_DRX           MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP47_LCD_VSYNC         MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP48_LCD_D16           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   0 )
+#define MPP49_GPO               MPP( 49, 0x0, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   0 )
+#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP49_PTP_CLK           MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
+#define MPP49_PEX0_CLKREQ       MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_LCD_D17           MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 
 #define MPP_MAX                 49
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711b1c67..c6b92b42eb4e 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
         if (machine_is_mv88f6281gtw_ge())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d72681..d26bf324738b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -39,6 +39,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
+#include <mach/leds-ns2.h>
 #include <plat/time.h>
 #include "common.h"
 #include "mpp.h"
@@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void)
         }
         if (err)
                 pr_err("netspace_v2: failed to setup SATA0 power\n");
+
+        if (machine_is_netspace_max_v2()) {
+                err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
+                if (err == 0) {
+                        err = gpio_direction_output(
+                                        NETSPACE_V2_GPIO_SATA1_POWER, 1);
+                        if (err)
+                                gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
+                }
+                if (err)
+                        pr_err("netspace_v2: failed to setup SATA1 power\n");
+        }
 }
 
 /*****************************************************************************
@@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = {
  * GPIO LEDs
  ****************************************************************************/
 
-/*
- * The blue front LED is wired to a CPLD and can blink in relation with the
- * SATA activity.
- *
- * The following array detail the different LED registers and the combination
- * of their possible values:
- *
- *  cmd_led   |  slow_led  | /SATA active | LED state
- *            |            |              |
- *     1      |     0      |      x       |  off
- *     -      |     1      |      x       |  on
- *     0      |     0      |      1       |  on
- *     0      |     0      |      0       |  blink (rate 300ms)
- */
-
 #define NETSPACE_V2_GPIO_RED_LED        12
-#define NETSPACE_V2_GPIO_BLUE_LED_SLOW  29
-#define NETSPACE_V2_GPIO_BLUE_LED_CMD   30
-
 
 static struct gpio_led netspace_v2_gpio_led_pins[] = {
         {
-                .name                   = "ns_v2:blue:sata",
-                .default_trigger        = "default-on",
-                .gpio                   = NETSPACE_V2_GPIO_BLUE_LED_CMD,
-                .active_low             = 1,
-        },
-        {
-                .name                   = "ns_v2:red:fail",
-                .gpio                   = NETSPACE_V2_GPIO_RED_LED,
+                .name   = "ns_v2:red:fail",
+                .gpio   = NETSPACE_V2_GPIO_RED_LED,
         },
 };
 
@@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = {
         },
 };
 
-static void __init netspace_v2_gpio_leds_init(void)
-{
-        int err;
+/*****************************************************************************
+ * Dual-GPIO CPLD LEDs
+ ****************************************************************************/
 
-        /* Configure register slow_led to allow SATA activity LED blinking */
-        err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow");
-        if (err == 0) {
-                err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0);
-                if (err)
-                        gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
-        }
-        if (err)
-                pr_err("netspace_v2: failed to configure blue LED slow GPIO\n");
+#define NETSPACE_V2_GPIO_BLUE_LED_SLOW  29
+#define NETSPACE_V2_GPIO_BLUE_LED_CMD   30
 
-        platform_device_register(&netspace_v2_gpio_leds);
-}
+static struct ns2_led netspace_v2_led_pins[] = {
+        {
+                .name   = "ns_v2:blue:sata",
+                .cmd    = NETSPACE_V2_GPIO_BLUE_LED_CMD,
+                .slow   = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
+        },
+};
+
+static struct ns2_led_platform_data netspace_v2_leds_data = {
+        .num_leds       = ARRAY_SIZE(netspace_v2_led_pins),
+        .leds           = netspace_v2_led_pins,
+};
+
+static struct platform_device netspace_v2_leds = {
+        .name           = "leds-ns2",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &netspace_v2_leds_data,
+        },
+};
 
 /*****************************************************************************
  * Timer
@@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
         MPP4_NF_IO6,
         MPP5_NF_IO7,
         MPP6_SYSRST_OUTn,
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP7_GPO,               /* Fan speed (bit 1) */
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP12_GPO,              /* Red led */
         MPP14_GPIO,             /* USB fuse */
         MPP16_GPIO,             /* SATA 0 power */
+        MPP17_GPIO,             /* SATA 1 power */
         MPP18_NF_IO0,
         MPP19_NF_IO1,
         MPP20_SATA1_ACTn,
         MPP21_SATA0_ACTn,
+        MPP22_GPIO,             /* Fan speed (bit 0) */
+        MPP23_GPIO,             /* Fan power */
         MPP24_GPIO,             /* USB mode select */
         MPP25_GPIO,             /* Fan rotation fail */
         MPP26_GPIO,             /* USB device vbus */
@@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
         MPP30_GPIO,             /* Blue led (command register) */
         MPP31_GPIO,             /* Board power off */
         MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
+        MPP33_GPO,              /* Fan speed (bit 2) */
         0
 };
 
@@ -299,7 +304,8 @@ static void __init netspace_v2_init(void)
         i2c_register_board_info(0, netspace_v2_i2c_info,
                                 ARRAY_SIZE(netspace_v2_i2c_info));
 
-        netspace_v2_gpio_leds_init();
+        platform_device_register(&netspace_v2_leds);
+        platform_device_register(&netspace_v2_gpio_leds);
         platform_device_register(&netspace_v2_gpio_buttons);
 
         if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
         .timer          = &netspace_v2_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_NETSPACE_MAX_V2
+MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = netspace_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &netspace_v2_timer,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb0228e4f..2bd14c5079de 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP6_SYSRST_OUTn,
         MPP7_GPO,               /* Request power-off */
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_GPIO,             /* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP6_SYSRST_OUTn,
         MPP7_GPO,               /* Request power-off */
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_GPIO,             /* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP15_GPIO,             /* Rear power switch (auto|off) */
         MPP16_GPIO,             /* SATA HDD1 power */
         MPP17_GPIO,             /* SATA HDD2 power */
-        MPP20_GE1_0,
-        MPP21_GE1_1,
-        MPP22_GE1_2,
-        MPP23_GE1_3,
-        MPP24_GE1_4,
-        MPP25_GE1_5,
-        MPP26_GE1_6,
-        MPP27_GE1_7,
+        MPP20_GE1_TXD0,
+        MPP21_GE1_TXD1,
+        MPP22_GE1_TXD2,
+        MPP23_GE1_TXD3,
+        MPP24_GE1_RXD0,
+        MPP25_GE1_RXD1,
+        MPP26_GE1_RXD2,
+        MPP27_GE1_RXD3,
         MPP28_GPIO,             /* USB enable host vbus */
         MPP29_GPIO,             /* CPLD extension ALE */
-        MPP30_GE1_10,
-        MPP31_GE1_11,
-        MPP32_GE1_12,
-        MPP33_GE1_13,
+        MPP30_GE1_RXCTL,
+        MPP31_GE1_RXCLK,
+        MPP32_GE1_TCLKOUT,
+        MPP33_GE1_TXCTL,
         MPP34_GPIO,             /* Rear Push button */
         MPP35_GPIO,             /* Inhibit switch power-off */
         MPP36_GPIO,             /* SATA HDD1 presence */
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec33796..fd64cd2b4e0a 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-kirkwood/openrd-setup.c
  *
- * Marvell OpenRD (Base|Client) Board Setup
+ * Marvell OpenRD (Base|Client|Ultimate) Board Setup
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -73,9 +73,15 @@ static void __init openrd_init(void)
 
         kirkwood_ehci_init();
 
+        if (machine_is_openrd_ultimate()) {
+                openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+                openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
+        }
+
         kirkwood_ge00_init(&openrd_ge00_data);
-        if (machine_is_openrd_client())
+        if (!machine_is_openrd_base())
                 kirkwood_ge01_init(&openrd_ge01_data);
+
         kirkwood_sata_init(&openrd_sata_data);
         kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,8 +90,10 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-        if (machine_is_openrd_base() || machine_is_openrd_client())
-                kirkwood_pcie_init();
+        if (machine_is_openrd_base() ||
+            machine_is_openrd_client() ||
+            machine_is_openrd_ultimate())
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
@@ -116,3 +124,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
         .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = openrd_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff50d39..55e7f00836b7 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+        *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE       ((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+        u8                      root_bus_nr;
+        void __iomem            *base;
+        spinlock_t              conf_lock;
+        int                     irq;
+        struct resource         res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static int pcie_port_map[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
 {
-        *dev = orion_pcie_dev_id(PCIE_BASE);
-        *rev = orion_pcie_rev(PCIE_BASE);
+        struct pci_sys_data *sys = bus->sysdata;
+        return sys->private_data;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
         /*
          * Don't go out when trying to access --
          * 1. nonexisting device on local bus
          * 2. where there's no device connected (no link)
          */
-        if (bus == 0 && dev == 0)
+        if (bus == pp->root_bus_nr && dev == 0)
                 return 1;
 
-        if (!orion_pcie_link_up(PCIE_BASE))
+        if (!orion_pcie_link_up(pp->base))
                 return 0;
 
-        if (bus == 0 && dev != 1)
+        if (bus == pp->root_bus_nr && dev != 1)
                 return 0;
 
         return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                         int size, u32 *val)
 {
+        struct pcie_port *pp = bus_to_port(bus);
         unsigned long flags;
         int ret;
 
-        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
                 *val = 0xffffffff;
                 return PCIBIOS_DEVICE_NOT_FOUND;
         }
 
-        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-        ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
 
         return ret;
 }
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
                         int where, int size, u32 val)
 {
+        struct pcie_port *pp = bus_to_port(bus);
         unsigned long flags;
         int ret;
 
-        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
-        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-        ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
 
         return ret;
 }
@@ -93,50 +108,98 @@ static struct pci_ops pcie_ops = {
         .write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-        struct resource *res;
-        extern unsigned int kirkwood_clk_ctrl;
+        pp->base = (void __iomem *)PCIE_VIRT_BASE;
+        pp->irq = IRQ_KIRKWOOD_PCIE;
 
         /*
-         * Generic PCIe unit setup.
+         * IORESOURCE_IO
          */
-        orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+        pp->res[0].name = "PCIe 0 I/O Space";
+        pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+        pp->res[0].flags = IORESOURCE_IO;
 
         /*
-         * Request resources.
+         * IORESOURCE_MEM
          */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-        if (!res)
-                panic("pcie_setup unable to alloc resources");
+        pp->res[1].name = "PCIe 0 MEM";
+        pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+        pp->res[1].flags = IORESOURCE_MEM;
+}
+
+static void __init pcie1_ioresources_init(struct pcie_port *pp)
+{
+        pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+        pp->irq = IRQ_KIRKWOOD_PCIE1;
 
         /*
          * IORESOURCE_IO
          */
-        res[0].name = "PCIe I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-        res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCIe IO resource failed\n");
-        sys->resource[0] = &res[0];
+        pp->res[0].name = "PCIe 1 I/O Space";
+        pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+        pp->res[0].flags = IORESOURCE_IO;
 
         /*
          * IORESOURCE_MEM
          */
-        res[1].name = "PCIe Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-        res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
-                panic("Request PCIe Memory resource failed\n");
-        sys->resource[1] = &res[1];
+        pp->res[1].name = "PCIe 1 MEM";
+        pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+        pp->res[1].flags = IORESOURCE_MEM;
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        extern unsigned int kirkwood_clk_ctrl;
+        struct pcie_port *pp;
+        int index;
 
+        if (nr >= num_pcie_ports)
+                return 0;
+
+        index = pcie_port_map[nr];
+        printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+
+        pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+        if (!pp)
+                panic("PCIe: failed to allocate pcie_port data");
+        sys->private_data = pp;
+        pp->root_bus_nr = sys->busnr;
+        spin_lock_init(&pp->conf_lock);
+
+        switch (index) {
+        case 0:
+                kirkwood_clk_ctrl |= CGC_PEX0;
+                pcie0_ioresources_init(pp);
+                break;
+        case 1:
+                kirkwood_clk_ctrl |= CGC_PEX1;
+                pcie1_ioresources_init(pp);
+                break;
+        default:
+                panic("PCIe setup: invalid controller %d", index);
+        }
+
+        if (request_resource(&ioport_resource, &pp->res[0]))
+                panic("Request PCIe%d IO resource failed\n", index);
+        if (request_resource(&iomem_resource, &pp->res[1]))
+                panic("Request PCIe%d Memory resource failed\n", index);
+
+        sys->resource[0] = &pp->res[0];
+        sys->resource[1] = &pp->res[1];
         sys->resource[2] = NULL;
         sys->io_offset = 0;
 
-        kirkwood_clk_ctrl |= CGC_PEX0;
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+
+        orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
         return 1;
 }
@@ -163,7 +226,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
         struct pci_bus *bus;
 
-        if (nr == 0) {
+        if (nr < num_pcie_ports) {
                 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
         } else {
                 bus = NULL;
@@ -175,18 +238,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        return IRQ_KIRKWOOD_PCIE;
+        struct pcie_port *pp = bus_to_port(dev->bus);
+
+        return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-        .nr_controllers = 1,
         .swizzle        = pci_std_swizzle,
         .setup          = kirkwood_pcie_setup,
         .scan           = kirkwood_pcie_scan_bus,
         .map_irq        = kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
 {
+        printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+        if (orion_pcie_link_up((void __iomem *)base)) {
+                printk(KERN_INFO "link up\n");
+                pcie_port_map[num_pcie_ports++] = index;
+        } else
+                printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(unsigned int portmask)
+{
+        if (portmask & KW_PCIE0)
+                add_pcie_port(0, PCIE_VIRT_BASE);
+
+        if (portmask & KW_PCIE1)
+                add_pcie_port(1, PCIE1_VIRT_BASE);
+
+        kirkwood_pci.nr_controllers = num_pcie_ports;
         pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304158f6..c34718c2cfe5 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
         if (machine_is_rd88f6192_nas())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708ddbc83e..3d1477135e12 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
         if (machine_is_rd88f6281())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
new file mode 100644
index 000000000000..d01bf89cedbe
--- /dev/null
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -0,0 +1,194 @@
+/*
+ *
+ * HP t5325 Thin Client setup
+ *
+ * Copyright (C) 2010  Martin Michlmayr <tbm@cyrius.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/i2c.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+struct mtd_partition hp_t5325_partitions[] = {
+        {
+                .name           = "u-boot env",
+                .size           = SZ_64K,
+                .offset         = SZ_512K + SZ_256K,
+        },
+        {
+                .name           = "permanent u-boot env",
+                .size           = SZ_64K,
+                .offset         = MTDPART_OFS_APPEND,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "HP env",
+                .size           = SZ_64K,
+                .offset         = MTDPART_OFS_APPEND,
+        },
+        {
+                .name           = "u-boot",
+                .size           = SZ_512K,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "SSD firmware",
+                .size           = SZ_256K,
+                .offset         = SZ_512K,
+        },
+};
+
+const struct flash_platform_data hp_t5325_flash = {
+        .type           = "mx25l8005",
+        .name           = "spi_flash",
+        .parts          = hp_t5325_partitions,
+        .nr_parts       = ARRAY_SIZE(hp_t5325_partitions),
+};
+
+struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &hp_t5325_flash,
+                .irq            = -1,
+        },
+};
+
+static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data hp_t5325_sata_data = {
+        .n_ports        = 2,
+};
+
+static struct gpio_keys_button hp_t5325_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = 45,
+                .desc           = "Power",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data hp_t5325_button_data = {
+        .buttons        = hp_t5325_buttons,
+        .nbuttons       = ARRAY_SIZE(hp_t5325_buttons),
+};
+
+static struct platform_device hp_t5325_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &hp_t5325_button_data,
+        }
+};
+
+static unsigned int hp_t5325_mpp_config[] __initdata = {
+        MPP0_NF_IO2,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP6_SYSRST_OUTn,
+        MPP7_SPI_SCn,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_SD_CLK,
+        MPP13_GPIO,
+        MPP14_GPIO,
+        MPP15_GPIO,
+        MPP16_GPIO,
+        MPP17_GPIO,
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
+        MPP20_GPIO,
+        MPP21_GPIO,
+        MPP22_GPIO,
+        MPP23_GPIO,
+        MPP32_GPIO,
+        MPP33_GE1_TXCTL,
+        MPP39_AU_I2SBCLK,
+        MPP40_AU_I2SDO,
+        MPP41_AU_I2SLRCLK,
+        MPP42_AU_I2SMCLK,
+        MPP45_GPIO,             /* Power button */
+        MPP48_GPIO,             /* Board power off */
+        0
+};
+
+#define HP_T5325_GPIO_POWER_OFF         48
+
+static void hp_t5325_power_off(void)
+{
+        gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
+}
+
+static void __init hp_t5325_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(hp_t5325_mpp_config);
+
+        kirkwood_uart0_init();
+        spi_register_board_info(hp_t5325_spi_slave_info,
+                                ARRAY_SIZE(hp_t5325_spi_slave_info));
+        kirkwood_spi_init();
+        kirkwood_i2c_init();
+        kirkwood_ge00_init(&hp_t5325_ge00_data);
+        kirkwood_sata_init(&hp_t5325_sata_data);
+        kirkwood_ehci_init();
+        platform_device_register(&hp_t5325_button_device);
+
+        if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = hp_t5325_power_off;
+        else
+                pr_err("t5325: failed to configure power-off GPIO\n");
+}
+
+static int __init hp_t5325_pci_init(void)
+{
+        if (machine_is_t5325())
+                kirkwood_pcie_init(KW_PCIE0);
+
+        return 0;
+}
+subsys_initcall(hp_t5325_pci_init);
+
+MACHINE_START(T5325, "HP t5325 Thin Client")
+        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = hp_t5325_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0fe80e0..a5bd7fde04a9 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP4_SATA1_ACTn,
         MPP5_SATA0_ACTn,
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_UART1_TXD,        /* PIC controller */
@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
         MPP15_GPIO,             /* USB Copy button */
         MPP16_GPIO,             /* Reset button */
         MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+        MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
         0
 };
 
@@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void)
 
 static int __init ts219_pci_init(void)
 {
-   if (machine_is_ts219())
-           kirkwood_pcie_init();
+        if (machine_is_ts219())
+                kirkwood_pcie_init(KW_PCIE0);
 
-   return 0;
+        return 0;
 }
 subsys_initcall(ts219_pci_init);
 
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d9e74b..2e14afef07a2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -2,7 +2,7 @@
  *
  * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
  *
- * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2009-2010  Martin Michlmayr <tbm@cyrius.com>
  * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -17,6 +17,7 @@
 #include <linux/i2c.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
+#include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <asm/mach-types.h>
@@ -26,6 +27,8 @@
 #include "mpp.h"
 #include "tsx1x-common.h"
 
+#define QNAP_TS41X_JUMPER_JP1   45
+
 static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
         I2C_BOARD_INFO("s35390a", 0x30),
 };
@@ -78,31 +81,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP6_SYSRST_OUTn,
         MPP7_PEX_RST_OUTn,
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_UART1_TXD,        /* PIC controller */
         MPP14_UART1_RXD,        /* PIC controller */
         MPP15_SATA0_ACTn,
         MPP16_SATA1_ACTn,
-        MPP20_GE1_0,
-        MPP21_GE1_1,
-        MPP22_GE1_2,
-        MPP23_GE1_3,
-        MPP24_GE1_4,
-        MPP25_GE1_5,
-        MPP26_GE1_6,
-        MPP27_GE1_7,
-        MPP30_GE1_10,
-        MPP31_GE1_11,
-        MPP32_GE1_12,
-        MPP33_GE1_13,
+        MPP20_GE1_TXD0,
+        MPP21_GE1_TXD1,
+        MPP22_GE1_TXD2,
+        MPP23_GE1_TXD3,
+        MPP24_GE1_RXD0,
+        MPP25_GE1_RXD1,
+        MPP26_GE1_RXD2,
+        MPP27_GE1_RXD3,
+        MPP30_GE1_RXCTL,
+        MPP31_GE1_RXCLK,
+        MPP32_GE1_TCLKOUT,
+        MPP33_GE1_TXCTL,
         MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
         MPP37_GPIO,             /* Reset button */
         MPP43_GPIO,             /* USB Copy button */
         MPP44_GPIO,             /* Board ID: 0: TS-419U, 1: TS-419 */
-        MPP45_GPIO,             /* JP1: 0: console, 1: LCD */
+        MPP45_GPIO,             /* JP1: 0: LCD, 1: serial console */
         MPP46_GPIO,             /* External SATA HDD1 error indicator */
         MPP47_GPIO,             /* External SATA HDD2 error indicator */
         MPP48_GPIO,             /* External SATA HDD3 error indicator */
@@ -131,12 +134,14 @@ static void __init qnap_ts41x_init(void)
 
         pm_power_off = qnap_tsx1x_power_off;
 
+        if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0)
+                gpio_export(QNAP_TS41X_JUMPER_JP1, 0);
 }
 
 static int __init ts41x_pci_init(void)
 {
         if (machine_is_ts41x())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index 78499667eb7b..5fcd082a17f9 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -268,8 +268,8 @@ static void __init ks8695_pci_preinit(void)
         __raw_writel(0, KS8695_PCI_VA + KS8695_PIOBAC);
 
         /* hook in fault handlers */
-        hook_fault_code(8, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch");
-        hook_fault_code(10, ks8695_pci_fault, SIGBUS, "external abort on non-linefetch");
+        hook_fault_code(8, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
+        hook_fault_code(10, ks8695_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
 }
 
 static void ks8695_show_pciregs(void)
diff --git a/arch/arm/mach-l7200/Makefile b/arch/arm/mach-l7200/Makefile
deleted file mode 100644
index 4bd8ebd70e7b..000000000000
--- a/arch/arm/mach-l7200/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y                   := core.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
-
diff --git a/arch/arm/mach-l7200/Makefile.boot b/arch/arm/mach-l7200/Makefile.boot
deleted file mode 100644
index 6c72ecbe6b64..000000000000
--- a/arch/arm/mach-l7200/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   := 0xf0008000
-
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
deleted file mode 100644
index 50d23246d4f0..000000000000
--- a/arch/arm/mach-l7200/core.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- *  linux/arch/arm/mm/mm-lusl7200.c
- *
- *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- *  Extra MM routines for L7200 architecture
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/device.h>
-
-#include <asm/types.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/page.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-/*
- * IRQ base register
- */
-#define IRQ_BASE        (IO_BASE_2 + 0x1000)
-
-/* 
- * Normal IRQ registers
- */
-#define IRQ_STATUS      (*(volatile unsigned long *) (IRQ_BASE + 0x000))
-#define IRQ_RAWSTATUS   (*(volatile unsigned long *) (IRQ_BASE + 0x004))
-#define IRQ_ENABLE      (*(volatile unsigned long *) (IRQ_BASE + 0x008))
-#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c))
-#define IRQ_SOFT        (*(volatile unsigned long *) (IRQ_BASE + 0x010))
-#define IRQ_SOURCESEL   (*(volatile unsigned long *) (IRQ_BASE + 0x018))
-
-/* 
- * Fast IRQ registers
- */
-#define FIQ_STATUS      (*(volatile unsigned long *) (IRQ_BASE + 0x100))
-#define FIQ_RAWSTATUS   (*(volatile unsigned long *) (IRQ_BASE + 0x104))
-#define FIQ_ENABLE      (*(volatile unsigned long *) (IRQ_BASE + 0x108))
-#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c))
-#define FIQ_SOFT        (*(volatile unsigned long *) (IRQ_BASE + 0x110))
-#define FIQ_SOURCESEL   (*(volatile unsigned long *) (IRQ_BASE + 0x118))
-
-static void l7200_mask_irq(unsigned int irq)
-{
-        IRQ_ENABLECLEAR = 1 << irq;
-}
-
-static void l7200_unmask_irq(unsigned int irq)
-{
-        IRQ_ENABLE = 1 << irq;
-}
-
-static struct irq_chip l7200_irq_chip = {
-        .ack            = l7200_mask_irq,
-        .mask           = l7200_mask_irq,
-        .unmask         = l7200_unmask_irq
-};
- 
-static void __init l7200_init_irq(void)
-{
-        int irq;
-
-        IRQ_ENABLECLEAR = 0xffffffff;   /* clear all interrupt enables */
-        FIQ_ENABLECLEAR = 0xffffffff;   /* clear all fast interrupt enables */
-
-        for (irq = 0; irq < NR_IRQS; irq++) {
-                set_irq_chip(irq, &l7200_irq_chip);
-                set_irq_flags(irq, IRQF_VALID);
-                set_irq_handler(irq, handle_level_irq);
-        }
-
-        init_FIQ();
-}
-
-static struct map_desc l7200_io_desc[] __initdata = {
-        { IO_BASE,      IO_START,       IO_SIZE,        MT_DEVICE },
-        { IO_BASE_2,    IO_START_2,     IO_SIZE_2,      MT_DEVICE },
-        { AUX_BASE,     AUX_START,      AUX_SIZE,       MT_DEVICE },
-        { FLASH1_BASE,  FLASH1_START,   FLASH1_SIZE,    MT_DEVICE },
-        { FLASH2_BASE,  FLASH2_START,   FLASH2_SIZE,    MT_DEVICE }
-};
-
-static void __init l7200_map_io(void)
-{
-        iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc));
-}
-
-MACHINE_START(L7200, "LinkUp Systems L7200")
-        /* Maintainer: Steve Hill / Scott McConnell */
-        .phys_io        = 0x80040000,
-        .io_pg_offst    = ((0xd0000000) >> 18) & 0xfffc,
-        .map_io         = l7200_map_io,
-        .init_irq       = l7200_init_irq,
-MACHINE_END
-
diff --git a/arch/arm/mach-l7200/include/mach/aux_reg.h b/arch/arm/mach-l7200/include/mach/aux_reg.h
deleted file mode 100644
index 4671558cdd51..000000000000
--- a/arch/arm/mach-l7200/include/mach/aux_reg.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/aux_reg.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   08-02-2000 SJH     Created file
- */
-#ifndef _ASM_ARCH_AUXREG_H
-#define _ASM_ARCH_AUXREG_H
-
-#include <mach/hardware.h>
-
-#define l7200aux_reg    *((volatile unsigned int *) (AUX_BASE))
-
-/*
- * Auxillary register values
- */
-#define AUX_CLEAR               0x00000000
-#define AUX_DIAG_LED_ON         0x00000002
-#define AUX_RTS_UART1           0x00000004
-#define AUX_DTR_UART1           0x00000008
-#define AUX_KBD_COLUMN_12_HIGH  0x00000010
-#define AUX_KBD_COLUMN_12_OFF   0x00000020
-#define AUX_KBD_COLUMN_13_HIGH  0x00000040
-#define AUX_KBD_COLUMN_13_OFF   0x00000080
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
deleted file mode 100644
index b69ed344c7c9..000000000000
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-l7200/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .equ    io_virt, IO_BASE
-                .equ    io_phys, IO_START
-
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #io_phys           @ physical base address
-                movne   \rx, #io_virt           @ virtual address
-                add     \rx, \rx, #0x00044000   @ UART1
-@               add     \rx, \rx, #0x00045000   @ UART2
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/arch/arm/mach-l7200/include/mach/entry-macro.S b/arch/arm/mach-l7200/include/mach/entry-macro.S
deleted file mode 100644
index 1726d91fc1d3..000000000000
--- a/arch/arm/mach-l7200/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for L7200-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-
-                .equ    irq_base_addr,  IO_BASE_2
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqstat, #irq_base_addr                @ Virt addr IRQ regs
-                add     \irqstat, \irqstat, #0x00001000         @ Status reg
-                ldr     \irqstat, [\irqstat, #0]                @ get interrupts
-                mov     \irqnr, #0
-1001:           tst     \irqstat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \irqstat, \irqstat, lsr #1
-                tsteq   \irqnr, #32
-                beq     1001b
-                teq     \irqnr, #32
-                .endm
-
diff --git a/arch/arm/mach-l7200/include/mach/gp_timers.h b/arch/arm/mach-l7200/include/mach/gp_timers.h
deleted file mode 100644
index 2b7086a26b81..000000000000
--- a/arch/arm/mach-l7200/include/mach/gp_timers.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/gp_timers.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   07-28-2000 SJH     Created file
- *   08-02-2000 SJH     Used structure for registers
- */
-#ifndef _ASM_ARCH_GPTIMERS_H
-#define _ASM_ARCH_GPTIMERS_H
-
-#include <mach/hardware.h>
-
-/*
- * Layout of L7200 general purpose timer registers
- */
-struct GPT_Regs {
-        unsigned int TIMERLOAD;
-        unsigned int TIMERVALUE;
-        unsigned int TIMERCONTROL;
-        unsigned int TIMERCLEAR;
-};
-
-#define GPT_BASE                (IO_BASE_2 + 0x3000)
-#define l7200_timer1_regs       ((volatile struct GPT_Regs *) (GPT_BASE))
-#define l7200_timer2_regs       ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
-
-/*
- * General register values
- */
-#define GPT_PRESCALE_1          0x00000000
-#define GPT_PRESCALE_16         0x00000004
-#define GPT_PRESCALE_256        0x00000008
-#define GPT_MODE_FREERUN        0x00000000
-#define GPT_MODE_PERIODIC       0x00000040
-#define GPT_ENABLE              0x00000080
-#define GPT_BZTOG               0x00000100
-#define GPT_BZMOD               0x00000200
-#define GPT_LOAD_MASK           0x0000ffff
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/gpio.h b/arch/arm/mach-l7200/include/mach/gpio.h
deleted file mode 100644
index c7b0a5d7b8bb..000000000000
--- a/arch/arm/mach-l7200/include/mach/gpio.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/****************************************************************************/
-/*
- *      arch/arm/mach-l7200/include/mach/gpio.h
- *
- *      Registers and  helper functions for the L7200 Link-Up Systems
- *      GPIO.
- *
- *      (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define GPIO_OFF   0x00005000  /* Offset from IO_START to the GPIO reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
-#define GPIO_BASE  (IO_BASE_2  + GPIO_OFF) /* Virtual addr of the GPIO reg. */
-
-/* Offsets from the start of the GPIO for all the registers. */
-#define PADR_OFF     0x000
-#define PADDR_OFF    0x004
-#define PASBSR_OFF   0x008
-#define PAEENR_OFF   0x00c
-#define PAESNR_OFF   0x010
-#define PAESTR_OFF   0x014
-#define PAIMR_OFF    0x018
-#define PAINT_OFF    0x01c
-
-#define PBDR_OFF     0x020
-#define PBDDR_OFF    0x024
-#define PBSBSR_OFF   0x028
-#define PBIMR_OFF    0x038
-#define PBINT_OFF    0x03c
-
-#define PCDR_OFF     0x040
-#define PCDDR_OFF    0x044
-#define PCSBSR_OFF   0x048
-#define PCIMR_OFF    0x058
-#define PCINT_OFF    0x05c
-
-#define PDDR_OFF     0x060
-#define PDDDR_OFF    0x064
-#define PDSBSR_OFF   0x068
-#define PDEENR_OFF   0x06c
-#define PDESNR_OFF   0x070
-#define PDESTR_OFF   0x074
-#define PDIMR_OFF    0x078
-#define PDINT_OFF    0x07c
-
-#define PEDR_OFF     0x080
-#define PEDDR_OFF    0x084
-#define PESBSR_OFF   0x088
-#define PEEENR_OFF   0x08c
-#define PEESNR_OFF   0x090
-#define PEESTR_OFF   0x094
-#define PEIMR_OFF    0x098
-#define PEINT_OFF    0x09c
-
-/* Define the GPIO registers for use by device drivers and the kernel. */
-#define PADR   (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
-#define PADDR  (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
-#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
-#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
-#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
-#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
-#define PAIMR  (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
-#define PAINT  (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
-
-#define PBDR   (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
-#define PBDDR  (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
-#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
-#define PBIMR  (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
-#define PBINT  (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
-
-#define PCDR   (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
-#define PCDDR  (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
-#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
-#define PCIMR  (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
-#define PCINT  (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
-
-#define PDDR   (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
-#define PDDDR  (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
-#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
-#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
-#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
-#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
-#define PDIMR  (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
-#define PDINT  (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
-
-#define PEDR   (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
-#define PEDDR  (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
-#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
-#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
-#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
-#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
-#define PEIMR  (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
-#define PEINT  (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
-
-#define VEE_EN         0x02
-#define BACKLIGHT_EN   0x04
diff --git a/arch/arm/mach-l7200/include/mach/hardware.h b/arch/arm/mach-l7200/include/mach/hardware.h
deleted file mode 100644
index c31909cfc254..000000000000
--- a/arch/arm/mach-l7200/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/hardware.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * This file contains the hardware definitions for the 
- * LinkUp Systems L7200 SOC development board.
- *
- * Changelog:
- *   02-01-2000  RS     Created L7200 version, derived from rpc code
- *   03-21-2000 SJH     Cleaned up file
- *   04-21-2000  RS     Changed mapping of I/O in virtual space
- *   04-25-2000 SJH     Removed unused symbols and such
- *   05-05-2000 SJH     Complete rewrite
- *   07-31-2000 SJH     Added undocumented debug auxillary port to
- *                      get at last two columns for keyboard driver
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               0xf0000000
-#define RAM_SIZE                0x02000000
-#define RAM_BASE                0xc0000000
-
-#define IO_START                0x80000000      /* I/O */
-#define IO_SIZE                 0x01000000
-#define IO_BASE                 0xd0000000
-
-#define IO_START_2              0x90000000      /* I/O */
-#define IO_SIZE_2               0x01000000
-#define IO_BASE_2               0xd1000000
-
-#define AUX_START               0x1a000000      /* AUX PORT */
-#define AUX_SIZE                0x01000000
-#define AUX_BASE                0xd2000000
-
-#define FLASH1_START            0x00000000      /* FLASH BANK 1 */
-#define FLASH1_SIZE             0x01000000
-#define FLASH1_BASE             0xd3000000
-
-#define FLASH2_START            0x10000000      /* FLASH BANK 2 */
-#define FLASH2_SIZE             0x01000000
-#define FLASH2_BASE             0xd4000000
-
-#define ISA_START               0x20000000      /* ISA */
-#define ISA_SIZE                0x20000000
-#define ISA_BASE                0xe0000000
-
-#define PCIO_BASE               IO_BASE
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
deleted file mode 100644
index a770a89fb708..000000000000
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/io.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-21-2000  SJH     Created from arch/arm/mach-nexuspci/include/mach/io.h
- *  08-31-2000  SJH     Added in IO functions necessary for new drivers
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * There are not real ISA nor PCI buses, so we fake it.
- */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/irqs.h b/arch/arm/mach-l7200/include/mach/irqs.h
deleted file mode 100644
index 7edffd713c5b..000000000000
--- a/arch/arm/mach-l7200/include/mach/irqs.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/irqs.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000 RS      Create l7200 version
- *   03-28-2000 SJH     Removed unused interrupt
- *   07-28-2000 SJH     Added pseudo-keyboard interrupt
- */
-
-/*
- * NOTE: The second timer (Timer 2) is used as the keyboard
- *       interrupt when the keyboard driver is enabled.
- */
-
-#define NR_IRQS          32
-
-#define IRQ_STWDOG        0   /* Watchdog timer */
-#define IRQ_PROG          1   /* Programmable interrupt */
-#define IRQ_DEBUG_RX      2   /* Comm Rx debug */
-#define IRQ_DEBUG_TX      3   /* Comm Tx debug */
-#define IRQ_GCTC1         4   /* Timer 1 */
-#define IRQ_GCTC2         5   /* Timer 2 / Keyboard */
-#define IRQ_DMA           6   /* DMA controller */
-#define IRQ_CLCD          7   /* Color LCD controller */
-#define IRQ_SM_RX         8   /* Smart card */
-#define IRQ_SM_TX         9   /* Smart cart */
-#define IRQ_SM_RST       10   /* Smart card */
-#define IRQ_SIB          11   /* Serial Interface Bus */
-#define IRQ_MMC          12   /* MultiMediaCard */
-#define IRQ_SSP1         13   /* Synchronous Serial Port 1 */
-#define IRQ_SSP2         14   /* Synchronous Serial Port 1 */
-#define IRQ_SPI          15   /* SPI slave */
-#define IRQ_UART_1       16   /* UART 1 */
-#define IRQ_UART_2       17   /* UART 2 */
-#define IRQ_IRDA         18   /* IRDA */
-#define IRQ_RTC_TICK     19   /* Real Time Clock tick */
-#define IRQ_RTC_ALARM    20   /* Real Time Clock alarm */
-#define IRQ_GPIO         21   /* General Purpose IO */
-#define IRQ_GPIO_DMA     22   /* General Purpose IO, DMA */
-#define IRQ_M2M          23   /* Memory to memory DMA  */
-#define IRQ_RESERVED     24   /* RESERVED, don't use */
-#define IRQ_INTF         25   /* External active low interrupt */
-#define IRQ_INT0         26   /* External active low interrupt */
-#define IRQ_INT1         27   /* External active low interrupt */
-#define IRQ_INT2         28   /* External active low interrupt */
-#define IRQ_UCB1200      29   /* Interrupt generated by UCB1200*/
-#define IRQ_BAT_LO       30   /* Low batery or external power */
-#define IRQ_MEDIA_CHG    31   /* Media change interrupt */
-
-/*
- * This is the offset of the FIQ "IRQ" numbers
- */
-#define FIQ_START       64
diff --git a/arch/arm/mach-l7200/include/mach/memory.h b/arch/arm/mach-l7200/include/mach/memory.h
deleted file mode 100644
index 9fb40ed2f03b..000000000000
--- a/arch/arm/mach-l7200/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/memory.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *
- * Changelog:
- *  03-13-2000  SJH     Created
- *  04-13-2000  RS      Changed bus macros for new addr
- *  05-03-2000  SJH     Removed bus macros and fixed virt_to_phys macro
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset on the L7200 SDB.
- */
-#define PHYS_OFFSET     UL(0xf0000000)
-
-/*
- * Cache flushing area - ROM
- */
-#define FLUSH_BASE_PHYS         0x40000000
-#define FLUSH_BASE              0xdf000000
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/pmpcon.h b/arch/arm/mach-l7200/include/mach/pmpcon.h
deleted file mode 100644
index 3959871e8361..000000000000
--- a/arch/arm/mach-l7200/include/mach/pmpcon.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/pmpcon.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   DC/DC converter register.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMPCON_OFF 0x00006000  /* Offset from IO_START_2. */
-
-/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
-
-#define PMPCON_START (IO_START_2 + PMPCON_OFF)  /* Physical address of reg. */
-#define PMPCON_BASE  (IO_BASE_2  + PMPCON_OFF)  /* Virtual address of reg. */
-
-
-#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
-
-#define PWM2_50CYCLE 0x800
-#define CONTRAST     0x9
-
-#define PWM1H (CONTRAST)
-#define PWM1L (CONTRAST << 4)
-
-#define PMPCON_VALUE  (PWM2_50CYCLE | PWM1L | PWM1H) 
-        
-/* PMPCON = 0x811;   // too light and fuzzy
- * PMPCON = 0x844;   
- * PMPCON = 0x866;   // better color poor depth
- * PMPCON = 0x888;   // Darker but better depth 
- * PMPCON = 0x899;   // Darker even better depth
- * PMPCON = 0x8aa;   // too dark even better depth
- * PMPCON = 0X8cc;   // Way too dark
- */
-
-/* As CONTRAST value increases the greater the depth perception and
- * the darker the colors.
- */
diff --git a/arch/arm/mach-l7200/include/mach/pmu.h b/arch/arm/mach-l7200/include/mach/pmu.h
deleted file mode 100644
index a2da7aedf208..000000000000
--- a/arch/arm/mach-l7200/include/mach/pmu.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/pmu.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   Power Management Unit (PMU).
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define PMU_OFF   0x00050000  /* Offset from IO_START to the PMU registers. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define PMU_START (IO_START + PMU_OFF)  /* Physical addr. of the PMU reg. */
-#define PMU_BASE  (IO_BASE  + PMU_OFF)  /* Virtual addr. of the PMU reg. */
-
-
-/* Define the PMU registers for use by device drivers and the kernel. */
-
-typedef struct {
-     unsigned int CURRENT;  /* Current configuration register */
-     unsigned int NEXT;     /* Next configuration register */
-     unsigned int reserved;
-     unsigned int RUN;      /* Run configuration register */
-     unsigned int COMM;     /* Configuration command register */
-     unsigned int SDRAM;    /* SDRAM configuration bypass register */
-} pmu_interface;
-
-#define PMU ((volatile pmu_interface *)(PMU_BASE))
-
-
-/* Macro's for reading the common register fields. */
-
-#define GET_TRANSOP(reg)  ((reg >> 25) & 0x03) /* Bits 26-25 */
-#define GET_OSCEN(reg)    ((reg >> 16) & 0x01)
-#define GET_OSCMUX(reg)   ((reg >> 15) & 0x01)
-#define GET_PLLMUL(reg)   ((reg >>  9) & 0x3f) /* Bits 14-9 */
-#define GET_PLLEN(reg)    ((reg >>  8) & 0x01)
-#define GET_PLLMUX(reg)   ((reg >>  7) & 0x01)
-#define GET_BCLK_DIV(reg) ((reg >>  3) & 0x03) /* Bits 4-3 */
-#define GET_SDRB_SEL(reg) ((reg >>  2) & 0x01)
-#define GET_SDRF_SEL(reg) ((reg >>  1) & 0x01)
-#define GET_FASTBUS(reg)  (reg & 0x1)
-
-/* CFG_NEXT register */
-
-#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f)   /* Bits 24-18 */
-#define CFG_NEXT_INTRET        ((PMU->NEXT >> 17) & 0x01)
-#define CFG_NEXT_SDR_STOP      ((PMU->NEXT >>  6) & 0x01)
-#define CFG_NEXT_SYSCLKEN      ((PMU->NEXT >>  5) & 0x01)
-
-/* Useful field values that can be used to construct the
- * CFG_NEXT and CFG_RUN registers.
- */
-
-#define TRANSOP_NOP      0<<25  /* NOCHANGE_NOSTALL */
-#define NOCHANGE_STALL   1<<25
-#define CHANGE_NOSTALL   2<<25
-#define CHANGE_STALL     3<<25
-
-#define INTRET           1<<17
-#define OSCEN            1<<16
-#define OSCMUX           1<<15
-
-/* PLL frequencies */
-
-#define PLLMUL_0         0<<9         /*  3.6864 MHz */
-#define PLLMUL_1         1<<9         /*  ?????? MHz */
-#define PLLMUL_5         5<<9         /*  18.432 MHz */
-#define PLLMUL_10       10<<9         /*  36.864 MHz */
-#define PLLMUL_18       18<<9         /*  ?????? MHz */
-#define PLLMUL_20       20<<9         /*  73.728 MHz */
-#define PLLMUL_32       32<<9         /*  ?????? MHz */
-#define PLLMUL_35       35<<9         /* 129.024 MHz */
-#define PLLMUL_36       36<<9         /*  ?????? MHz */
-#define PLLMUL_39       39<<9         /*  ?????? MHz */
-#define PLLMUL_40       40<<9         /* 147.456 MHz */
-
-/* Clock recovery times */
-
-#define CRCLOCK_1        1<<18
-#define CRCLOCK_2        2<<18
-#define CRCLOCK_4        4<<18
-#define CRCLOCK_8        8<<18
-#define CRCLOCK_16      16<<18
-#define CRCLOCK_32      32<<18
-#define CRCLOCK_63      63<<18
-#define CRCLOCK_127    127<<18
-
-#define PLLEN            1<<8
-#define PLLMUX           1<<7
-#define SDR_STOP         1<<6
-#define SYSCLKEN         1<<5
-
-#define BCLK_DIV_4       2<<3
-#define BCLK_DIV_2       1<<3
-#define BCLK_DIV_1       0<<3
-
-#define SDRB_SEL         1<<2
-#define SDRF_SEL         1<<1
-#define FASTBUS          1<<0
-
-
-/* CFG_SDRAM */
-
-#define SDRREFFQ         1<<0  /* Only if SDRSTOPRQ is not set. */
-#define SDRREFACK        1<<1  /* Read-only */
-#define SDRSTOPRQ        1<<2  /* Only if SDRREFFQ is not set. */
-#define SDRSTOPACK       1<<3  /* Read-only */
-#define PICEN            1<<4  /* Enable Co-procesor */
-#define PICTEST          1<<5
-
-#define GET_SDRREFFQ    ((PMU->SDRAM >> 0) & 0x01)
-#define GET_SDRREFACK   ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
-#define GET_SDRSTOPRQ   ((PMU->SDRAM >> 2) & 0x01)
-#define GET_SDRSTOPACK  ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
-#define GET_PICEN       ((PMU->SDRAM >> 4) & 0x01)
-#define GET_PICTEST     ((PMU->SDRAM >> 5) & 0x01)
diff --git a/arch/arm/mach-l7200/include/mach/serial.h b/arch/arm/mach-l7200/include/mach/serial.h
deleted file mode 100644
index adc05e5f8378..000000000000
--- a/arch/arm/mach-l7200/include/mach/serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/serial.h
- *
- * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  03-20-2000  SJH     Created
- *  03-26-2000  SJH     Added flags for serial ports
- *  03-27-2000  SJH     Corrected BASE_BAUD value
- *  04-14-2000  RS      Made register addr dependent on IO_BASE
- *  05-03-2000  SJH     Complete rewrite
- *  05-09-2000  SJH     Stripped out architecture specific serial stuff
- *                      and placed it in a separate file
- *  07-28-2000  SJH     Moved base baud rate variable
- */
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD       3686400
-
-/*
- * Standard COM flags
- */
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-
-#define STD_SERIAL_PORT_DEFNS           \
-        /* MAGIC UART CLK   PORT       IRQ     FLAGS */                 \
-        { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS },  /* ttyLU0 */ \
-        { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS },  /* ttyLU1 */ \
-
-#define EXTRA_SERIAL_PORT_DEFNS
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/serial_l7200.h b/arch/arm/mach-l7200/include/mach/serial_l7200.h
deleted file mode 100644
index 645f1c5e568d..000000000000
--- a/arch/arm/mach-l7200/include/mach/serial_l7200.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/serial_l7200.h
- *
- * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-09-2000  SJH     Created
- */
-#ifndef __ASM_ARCH_SERIAL_L7200_H
-#define __ASM_ARCH_SERIAL_L7200_H
-
-#include <mach/memory.h>
-
-/*
- * This assumes you have a 3.6864 MHz clock for your UART.
- */
-#define BASE_BAUD 3686400
-
-/*
- * UART base register addresses
- */
-#define UART1_BASE      (IO_BASE + 0x00044000)
-#define UART2_BASE      (IO_BASE + 0x00045000)
-
-/*
- * UART register offsets
- */
-#define UARTDR                  0x00    /* Tx/Rx data */
-#define RXSTAT                  0x04    /* Rx status */
-#define H_UBRLCR                0x08    /* mode register high */
-#define M_UBRLCR                0x0C    /* mode reg mid (MSB of baud)*/
-#define L_UBRLCR                0x10    /* mode reg low (LSB of baud)*/
-#define UARTCON                 0x14    /* control register */
-#define UARTFLG                 0x18    /* flag register */
-#define UARTINTSTAT             0x1C    /* FIFO IRQ status register */
-#define UARTINTMASK             0x20    /* FIFO IRQ mask register */
-
-/*
- * UART baud rate register values
- */
-#define BR_110                  0x827
-#define BR_1200                 0x06e
-#define BR_2400                 0x05f
-#define BR_4800                 0x02f
-#define BR_9600                 0x017
-#define BR_14400                0x00f
-#define BR_19200                0x00b
-#define BR_38400                0x005
-#define BR_57600                0x003
-#define BR_76800                0x002
-#define BR_115200               0x001
-
-/*
- * Receiver status register (RXSTAT) mask values
- */
-#define RXSTAT_NO_ERR           0x00    /* No error */
-#define RXSTAT_FRM_ERR          0x01    /* Framing error */
-#define RXSTAT_PAR_ERR          0x02    /* Parity error */
-#define RXSTAT_OVR_ERR          0x04    /* Overrun error */
-
-/*
- * High byte of UART bit rate and line control register (H_UBRLCR) values
- */
-#define UBRLCR_BRK              0x01    /* generate break on tx */
-#define UBRLCR_PEN              0x02    /* enable parity */
-#define UBRLCR_PDIS             0x00    /* disable parity */
-#define UBRLCR_EVEN             0x04    /* 1= even parity,0 = odd parity */
-#define UBRLCR_STP2             0x08    /* transmit 2 stop bits */
-#define UBRLCR_FIFO             0x10    /* enable FIFO */
-#define UBRLCR_LEN5             0x60    /* word length5 */
-#define UBRLCR_LEN6             0x40    /* word length6 */
-#define UBRLCR_LEN7             0x20    /* word length7 */
-#define UBRLCR_LEN8             0x00    /* word length8 */
-
-/*
- * UART control register (UARTCON) values
- */
-#define UARTCON_UARTEN          0x01    /* Enable UART */
-#define UARTCON_DMAONERR        0x08    /* Mask RxDmaRq when errors occur */
-
-/*
- * UART flag register (UARTFLG) mask values
- */
-#define UARTFLG_UTXFF           0x20    /* Transmit FIFO full */
-#define UARTFLG_URXFE           0x10    /* Receiver FIFO empty */
-#define UARTFLG_UBUSY           0x08    /* Transmitter busy */
-#define UARTFLG_DCD             0x04    /* Data carrier detect */
-#define UARTFLG_DSR             0x02    /* Data set ready */
-#define UARTFLG_CTS             0x01    /* Clear to send */
-
-/*
- * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
- */
-#define UART_TXINT              0x01    /* TX interrupt */
-#define UART_RXINT              0x02    /* RX interrupt */
-#define UART_RXERRINT           0x04    /* RX error interrupt */
-#define UART_MSINT              0x08    /* Modem Status interrupt */
-#define UART_UDINT              0x10    /* UART Disabled interrupt */
-#define UART_ALLIRQS            0x1f    /* All interrupts */
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/sib.h b/arch/arm/mach-l7200/include/mach/sib.h
deleted file mode 100644
index 965728712cf3..000000000000
--- a/arch/arm/mach-l7200/include/mach/sib.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/sib.h
- *
- *  Registers and helper functions for the Serial Interface Bus.
- *
- *  (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SIB_OFF   0x00040000  /* Offset from IO_START to the SIB reg's. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
-#define SIB_BASE  (IO_BASE  + SIB_OFF) /* Virtual addr of the SIB reg.  */
-
-/* Offsets from the start of the SIB for all the registers. */
-
-/* Define the SIB registers for use by device drivers and the kernel. */
-
-typedef struct
-{
-     unsigned int MCCR;    /* SIB Control Register           Offset: 0x00 */
-     unsigned int RES1;    /* Reserved                       Offset: 0x04 */
-     unsigned int MCDR0;   /* SIB Data Register 0            Offset: 0x08 */
-     unsigned int MCDR1;   /* SIB Data Register 1            Offset: 0x0c */
-     unsigned int MCDR2;   /* SIB Data Register 2 (UCB1x00)  Offset: 0x10 */
-     unsigned int RES2;    /* Reserved                       Offset: 0x14 */
-     unsigned int MCSR;    /* SIB Status Register            Offset: 0x18 */
-} SIB_Interface;
-
-#define SIB ((volatile SIB_Interface *) (SIB_BASE))
-
-/* MCCR */
-
-#define INTERNAL_FREQ   9216000  /* Hertz */
-#define AUDIO_FREQ         5000  /* Hertz */
-#define TELECOM_FREQ       5000  /* Hertz */
-
-#define AUDIO_DIVIDE    (INTERNAL_FREQ / (32 * AUDIO_FREQ))
-#define TELECOM_DIVIDE  (INTERNAL_FREQ / (32 * TELECOM_FREQ))
-
-#define MCCR_ASD57      AUDIO_DIVIDE
-#define MCCR_TSD57      (TELECOM_DIVIDE << 8)
-#define MCCR_MCE        (1 << 16)             /* SIB enable */
-#define MCCR_ECS        (1 << 17)             /* External Clock Select */
-#define MCCR_ADM        (1 << 18)             /* A/D Data Sampling */
-#define MCCR_PMC        (1 << 26)             /* PIN Multiplexer Control */
-
-
-#define GET_ASD ((SIB->MCCR >>  0) & 0x3f) /* Audio Sample Rate Div. */
-#define GET_TSD ((SIB->MCCR >>  8) & 0x3f) /* Telcom Sample Rate Div. */
-#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
-#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
-#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
-#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ 
-#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
-#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ 
-#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
-#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
-#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
-#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
-#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
-#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
-
-/* MCDR0 */
-
-#define AUDIO_RECV     ((SIB->MCDR0 >> 4) & 0xfff)
-#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
-
-/* MCDR1 */
-
-#define TELECOM_RECV     ((SIB->MCDR1 >> 2) & 032fff)
-#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
-
-
-/* MCSR */
-
-#define MCSR_ATU (1 << 4)  /* Audio Transmit FIFO Underrun */
-#define MCSR_ARO (1 << 5)  /* Audio Receive  FIFO Underrun */
-#define MCSR_TTU (1 << 6)  /* TELECOM Transmit FIFO Underrun */
-#define MCSR_TRO (1 << 7)  /* TELECOM Receive  FIFO Underrun */
-
-#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
-
-
-#define GET_ATS ((SIB->MCSR >>  0) & 0x01) /* Audio Transmit FIFO Service Req*/
-#define GET_ARS ((SIB->MCSR >>  1) & 0x01) /* Audio Recv FIFO Service Request*/
-#define GET_TTS ((SIB->MCSR >>  2) & 0x01) /* TELECOM Transmit FIFO  Flag */
-#define GET_TRS ((SIB->MCSR >>  3) & 0x01) /* TELECOM Recv FIFO Service Req. */
-#define GET_ATU ((SIB->MCSR >>  4) & 0x01) /* Audio Transmit FIFO Underrun */
-#define GET_ARO ((SIB->MCSR >>  5) & 0x01) /* Audio Receive  FIFO Underrun */
-#define GET_TTU ((SIB->MCSR >>  6) & 0x01) /* TELECOM Transmit FIFO Underrun */
-#define GET_TRO ((SIB->MCSR >>  7) & 0x01) /* TELECOM Receive  FIFO Underrun */
-#define GET_ANF ((SIB->MCSR >>  8) & 0x01) /* Audio Transmit FIFO not full */
-#define GET_ANE ((SIB->MCSR >>  9) & 0x01) /* Audio Receive FIFO not empty */
-#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
-#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
-#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
-#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
-#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
-#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
-
-/* MCDR2 */
-
-#define MCDR2_rW               (1 << 16)
-
-#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
-#define MCDR2_WRITE_COMPLETE   GET_CWC
-
-#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
-#define MCDR2_READ_COMPLETE      GET_CRC
-#define MCDR2_READ               (SIB->MCDR2 & 0xffff)
diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h
deleted file mode 100644
index e9729a35751d..000000000000
--- a/arch/arm/mach-l7200/include/mach/sys-clock.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/****************************************************************************/
-/*
- *  arch/arm/mach-l7200/include/mach/sys-clock.h
- *
- *   Registers and  helper functions for the L7200 Link-Up Systems
- *   System clocks.
- *
- *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License. See the file COPYING in the main directory of this archive for
- *  more details.
- */
-
-/****************************************************************************/
-
-#define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
-
-/* IO_START and IO_BASE are defined in hardware.h */
-
-#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF)  /* Physical address */
-#define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
-
-/* Define the interface to the SYS_CLOCK */
-
-typedef struct
-{
-     unsigned int ENABLE;
-     unsigned int ESYNC;
-     unsigned int SELECT;
-} sys_clock_interface;
-
-#define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
-
-//#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
-//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
-//#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
-
-/* SYS_CLOCK -> ENABLE */
-
-#define SYN_EN          1<<0
-#define B18M_EN         1<<1
-#define CLK3M6_EN       1<<2
-#define BUART_EN        1<<3
-#define CLK18MU_EN      1<<4
-#define FIR_EN          1<<5
-#define MIRN_EN         1<<6
-#define UARTM_EN        1<<7
-#define SIBADC_EN       1<<8
-#define ALTD_EN         1<<9
-#define CLCLK_EN        1<<10
-
-/* SYS_CLOCK -> SELECT */
-
-#define CLK18M_DIV      1<<0
-#define MIR_SEL         1<<1
-#define SSP_SEL         1<<4
-#define MM_DIV          1<<5
-#define MM_SEL          1<<6
-#define ADC_SEL_2       0<<7
-#define ADC_SEL_4       1<<7
-#define ADC_SEL_8       3<<7
-#define ADC_SEL_16      7<<7
-#define ADC_SEL_32      0x0f<<7
-#define ADC_SEL_64      0x1f<<7
-#define ADC_SEL_128     0x3f<<7
-#define ALTD_SEL        1<<13
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h
deleted file mode 100644
index e0dd3b6ae4aa..000000000000
--- a/arch/arm/mach-l7200/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/system.h
- *
- * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog
- *  03-21-2000  SJH     Created
- *  04-26-2000  SJH     Fixed functions
- *  05-03-2000  SJH     Removed usage of obsolete 'iomd.h'
- *  05-31-2000  SJH     Properly implemented 'arch_idle'
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/hardware.h>
-
-static inline void arch_idle(void)
-{
-        *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (mode == 's') {
-                cpu_reset(0);
-        }
-}
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/time.h b/arch/arm/mach-l7200/include/mach/time.h
deleted file mode 100644
index 061771c2c2bd..000000000000
--- a/arch/arm/mach-l7200/include/mach/time.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/time.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *   01-02-2000 RS      Created l7200 version, derived from rpc code
- *   05-03-2000 SJH     Complete rewrite
- */
-#ifndef _ASM_ARCH_TIME_H
-#define _ASM_ARCH_TIME_H
-
-#include <mach/irqs.h>
-
-/*
- * RTC base register address
- */
-#define RTC_BASE        (IO_BASE_2 + 0x2000)
-
-/*
- * RTC registers
- */
-#define RTC_RTCDR       (*(volatile unsigned char *) (RTC_BASE + 0x000))
-#define RTC_RTCMR       (*(volatile unsigned char *) (RTC_BASE + 0x004))
-#define RTC_RTCS        (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCC        (*(volatile unsigned char *) (RTC_BASE + 0x008))
-#define RTC_RTCDV       (*(volatile unsigned char *) (RTC_BASE + 0x00c))
-#define RTC_RTCCR       (*(volatile unsigned char *) (RTC_BASE + 0x010))
-
-/*
- * RTCCR register values
- */
-#define RTC_RATE_32     0x00      /* 32 Hz tick */
-#define RTC_RATE_64     0x10      /* 64 Hz tick */
-#define RTC_RATE_128    0x20      /* 128 Hz tick */
-#define RTC_RATE_256    0x30      /* 256 Hz tick */
-#define RTC_EN_ALARM    0x01      /* Enable alarm */
-#define RTC_EN_TIC      0x04      /* Enable counter */
-#define RTC_EN_STWDOG   0x08      /* Enable watchdog */
-
-/*
- * Handler for RTC timer interrupt
- */
-static irqreturn_t
-timer_interrupt(int irq, void *dev_id)
-{
-        struct pt_regs *regs = get_irq_regs();
-        do_timer(1);
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(regs));
-#endif
-        do_profile(regs);
-        RTC_RTCC = 0;                           /* Clear interrupt */
-
-        return IRQ_HANDLED;
-}
-
-/*
- * Set up RTC timer interrupt, and return the current time in seconds.
- */
-void __init time_init(void)
-{
-        RTC_RTCC = 0;                           /* Clear interrupt */
-
-        timer_irq.handler = timer_interrupt;
-
-        setup_irq(IRQ_RTC_TICK, &timer_irq);
-
-        RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC;  /* Set rate and enable timer */
-}
-
-#endif
diff --git a/arch/arm/mach-l7200/include/mach/timex.h b/arch/arm/mach-l7200/include/mach/timex.h
deleted file mode 100644
index ffc96a63b5a2..000000000000
--- a/arch/arm/mach-l7200/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/timex.h
- *
- * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
- *                    Steve Hill (sjhill@cotw.com)
- *
- * 04-21-2000  RS Created file
- * 05-03-2000 SJH Tick rate was wrong
- *
- */
-
-/*
- * On the ARM720T, clock ticks are set to 128 Hz.
- *
- * NOTE: The actual RTC value is set in 'time.h' which
- *       must be changed when choosing a different tick
- *       rate. The value of HZ in 'param.h' must also
- *       be changed to match below.
- */
-#define CLOCK_TICK_RATE         128
diff --git a/arch/arm/mach-l7200/include/mach/uncompress.h b/arch/arm/mach-l7200/include/mach/uncompress.h
deleted file mode 100644
index 591c962bb315..000000000000
--- a/arch/arm/mach-l7200/include/mach/uncompress.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/uncompress.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
- *
- * Changelog:
- *  05-01-2000  SJH     Created
- *  05-13-2000  SJH     Filled in function bodies
- *  07-26-2000  SJH     Removed hard coded baud rate
- */
-
-#include <mach/hardware.h>
-
-#define IO_UART  IO_START + 0x00044000
-
-#define __raw_writeb(v,p)       (*(volatile unsigned char *)(p) = (v))
-#define __raw_readb(p)          (*(volatile unsigned char *)(p))
-
-static inline void putc(int c)
-{
-        while(__raw_readb(IO_UART + 0x18) & 0x20 ||
-              __raw_readb(IO_UART + 0x18) & 0x08)
-                barrier();
-
-        __raw_writeb(c, IO_UART + 0x00);
-}
-
-static inline void flush(void)
-{
-}
-
-static __inline__ void arch_decomp_setup(void)
-{
-        __raw_writeb(0x00, IO_UART + 0x08);     /* Set HSB */
-        __raw_writeb(0x00, IO_UART + 0x20);     /* Disable IRQs */
-        __raw_writeb(0x01, IO_UART + 0x14);     /* Enable UART */
-}
-
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-l7200/include/mach/vmalloc.h b/arch/arm/mach-l7200/include/mach/vmalloc.h
deleted file mode 100644
index 85f0abbf15f1..000000000000
--- a/arch/arm/mach-l7200/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * arch/arm/mach-l7200/include/mach/vmalloc.h
- */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
index 189d20e543e7..edb8f5faf5d5 100644
--- a/arch/arm/mach-lh7a40x/include/mach/memory.h
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -19,50 +19,6 @@
  */
 #define PHYS_OFFSET     UL(0xc0000000)
 
-#ifdef CONFIG_DISCONTIGMEM
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define KVADDR_TO_NID(addr) \
-  (  ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) &  1)\
-   | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
-# else  /* 2 banks per node */
-#  define KVADDR_TO_NID(addr) \
-      (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
-# endif
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define PFN_TO_NID(pfn) \
-  (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) &  1)\
- | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
-# else  /* 2 banks per node */
-#  define PFN_TO_NID(pfn) \
-    (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
-#endif
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-
-# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
-#  define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
-# else  /* 2 banks per node */
-#  define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
-# endif
-
-#endif
-
 /*
  * Sparsemem version of the above
  */
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
new file mode 100644
index 000000000000..fde663508696
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -0,0 +1,33 @@
+if ARCH_LPC32XX
+
+menu "Individual UART enable selections"
+
+config ARCH_LPC32XX_UART3_SELECT
+        bool "Add support for standard UART3"
+        help
+         Adds support for standard UART 3 when the 8250 serial support
+         is enabled.
+
+config ARCH_LPC32XX_UART4_SELECT
+        bool "Add support for standard UART4"
+        help
+         Adds support for standard UART 4 when the 8250 serial support
+         is enabled.
+
+config ARCH_LPC32XX_UART5_SELECT
+        bool "Add support for standard UART5"
+        default y
+        help
+         Adds support for standard UART 5 when the 8250 serial support
+         is enabled.
+
+config ARCH_LPC32XX_UART6_SELECT
+        bool "Add support for standard UART6"
+        help
+         Adds support for standard UART 6 when the 8250 serial support
+         is enabled.
+
+endmenu
+
+endif
+
diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
new file mode 100644
index 000000000000..a5fc5d0eeaeb
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y   := timer.o irq.o common.o serial.o clock.o
+obj-y   += gpiolib.o pm.o suspend.o
+obj-y   += phy3250.o
+
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
new file mode 100644
index 000000000000..b796b41ebf8f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -0,0 +1,4 @@
+   zreladdr-y   := 0x80008000
+params_phys-y   := 0x80000100
+initrd_phys-y   := 0x82000000
+
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
new file mode 100644
index 000000000000..32d63796430a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -0,0 +1,1137 @@
+/*
+ * arch/arm/mach-lpc32xx/clock.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * LPC32xx clock management driver overview
+ *
+ * The LPC32XX contains a number of high level system clocks that can be
+ * generated from different sources. These system clocks are used to
+ * generate the CPU and bus rates and the individual peripheral clocks in
+ * the system. When Linux is started by the boot loader, the system
+ * clocks are already running. Stopping a system clock during normal
+ * Linux operation should never be attempted, as peripherals that require
+ * those clocks will quit working (ie, DRAM).
+ *
+ * The LPC32xx high level clock tree looks as follows. Clocks marked with
+ * an asterisk are always on and cannot be disabled. Clocks marked with
+ * an ampersand can only be disabled in CPU suspend mode. Clocks marked
+ * with a caret are always on if it is the selected clock for the SYSCLK
+ * source. The clock that isn't used for SYSCLK can be enabled and
+ * disabled normally.
+ *                               32KHz oscillator*
+ *                               /      |      \
+ *                             RTC*   PLL397^ TOUCH
+ *                                     /
+ *               Main oscillator^     /
+ *                   |        \      /
+ *                   |         SYSCLK&
+ *                   |            \
+ *                   |             \
+ *                USB_PLL       HCLK_PLL&
+ *                   |           |    |
+ *            USB host/device  PCLK&  |
+ *                               |    |
+ *                             Peripherals
+ *
+ * The CPU and chip bus rates are derived from the HCLK PLL, which can
+ * generate various clock rates up to 266MHz and beyond. The internal bus
+ * rates (PCLK and HCLK) are generated from dividers based on the HCLK
+ * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
+ * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
+ * level clocks are based on either HCLK or PCLK, but have their own
+ * dividers as part of the IP itself. Because of this, the system clock
+ * rates should not be changed.
+ *
+ * The HCLK PLL is clocked from SYSCLK, which can be derived from the
+ * main oscillator or PLL397. PLL397 generates a rate that is 397 times
+ * the 32KHz oscillator rate. The main oscillator runs at the selected
+ * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
+ * is normally 13MHz, but depends on the selection of external crystals
+ * or oscillators. If USB operation is required, the main oscillator must
+ * be used in the system.
+ *
+ * Switching SYSCLK between sources during normal Linux operation is not
+ * supported. SYSCLK is preset in the bootloader. Because of the
+ * complexities of clock management during clock frequency changes,
+ * there are some limitations to the clock driver explained below:
+ * - The PLL397 and main oscillator can be enabled and disabled by the
+ *   clk_enable() and clk_disable() functions unless SYSCLK is based
+ *   on that clock. This allows the other oscillator that isn't driving
+ *   the HCLK PLL to be used as another system clock that can be routed
+ *   to an external pin.
+ * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
+ *   this driver.
+ * - HCLK and PCLK rates cannot be changed as part of this driver.
+ * - Most peripherals have their own dividers are part of the peripheral
+ *   block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
+ *   will also impact the individual peripheral rates.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+
+#include <mach/hardware.h>
+#include <asm/clkdev.h>
+#include <mach/clkdev.h>
+#include <mach/platform.h>
+#include "clock.h"
+#include "common.h"
+
+static struct clk clk_armpll;
+static struct clk clk_usbpll;
+static DEFINE_MUTEX(clkm_lock);
+
+/*
+ * Post divider values for PLLs based on selected register value
+ */
+static const u32 pll_postdivs[4] = {1, 2, 4, 8};
+
+static unsigned long local_return_parent_rate(struct clk *clk)
+{
+        /*
+         * If a clock has a rate of 0, then it inherits it's parent
+         * clock rate
+         */
+        while (clk->rate == 0)
+                clk = clk->parent;
+
+        return clk->rate;
+}
+
+/* 32KHz clock has a fixed rate and is not stoppable */
+static struct clk osc_32KHz = {
+        .rate           = LPC32XX_CLOCK_OSC_FREQ,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int local_pll397_enable(struct clk *clk, int enable)
+{
+        u32 reg;
+        unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
+
+        if (enable == 0) {
+                reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+                __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
+        } else {
+                /* Enable PLL397 */
+                reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+                __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
+
+                /* Wait for PLL397 lock */
+                while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
+                        LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
+                        (timeout > jiffies))
+                        cpu_relax();
+
+                if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
+                        LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
+                        return -ENODEV;
+        }
+
+        return 0;
+}
+
+static int local_oscmain_enable(struct clk *clk, int enable)
+{
+        u32 reg;
+        unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+
+        if (enable == 0) {
+                reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
+                __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+        } else {
+                /* Enable main oscillator */
+                reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
+                __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+
+                /* Wait for main oscillator to start */
+                while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
+                        LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
+                        (timeout > jiffies))
+                        cpu_relax();
+
+                if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
+                        LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
+                        return -ENODEV;
+        }
+
+        return 0;
+}
+
+static struct clk osc_pll397 = {
+        .parent         = &osc_32KHz,
+        .enable         = local_pll397_enable,
+        .rate           = LPC32XX_CLOCK_OSC_FREQ * 397,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk osc_main = {
+        .enable         = local_oscmain_enable,
+        .rate           = LPC32XX_MAIN_OSC_FREQ,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_sys;
+
+/*
+ * Convert a PLL register value to a PLL output frequency
+ */
+u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
+{
+        struct clk_pll_setup pllcfg;
+
+        pllcfg.cco_bypass_b15 = 0;
+        pllcfg.direct_output_b14 = 0;
+        pllcfg.fdbk_div_ctrl_b13 = 0;
+        if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
+                pllcfg.cco_bypass_b15 = 1;
+        if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
+                pllcfg.direct_output_b14 = 1;
+        if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
+                pllcfg.fdbk_div_ctrl_b13 = 1;
+        pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
+        pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
+        pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
+
+        return clk_check_pll_setup(inputclk, &pllcfg);
+}
+
+/*
+ * Setup the HCLK PLL with a PLL structure
+ */
+static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
+{
+        u32 tv, tmp = 0;
+
+        if (PllSetup->analog_on != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
+        if (PllSetup->cco_bypass_b15 != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
+        if (PllSetup->direct_output_b14 != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
+        if (PllSetup->fdbk_div_ctrl_b13 != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
+
+        tv = ffs(PllSetup->pll_p) - 1;
+        if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
+                return 0;
+
+        tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
+        tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
+        tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
+
+        return tmp;
+}
+
+/*
+ * Update the ARM core PLL frequency rate variable from the actual PLL setting
+ */
+static void local_update_armpll_rate(void)
+{
+        u32 clkin, pllreg;
+
+        clkin = clk_armpll.parent->rate;
+        pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
+
+        clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
+}
+
+/*
+ * Find a PLL configuration for the selected input frequency
+ */
+static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
+        struct clk_pll_setup *pllsetup)
+{
+        u32 ifreq, freqtol, m, n, p, fclkout;
+
+        /* Determine frequency tolerance limits */
+        freqtol = target_freq / 250;
+        ifreq = pllin_freq;
+
+        /* Is direct bypass mode possible? */
+        if (abs(pllin_freq - target_freq) <= freqtol) {
+                pllsetup->analog_on = 0;
+                pllsetup->cco_bypass_b15 = 1;
+                pllsetup->direct_output_b14 = 1;
+                pllsetup->fdbk_div_ctrl_b13 = 1;
+                pllsetup->pll_p = pll_postdivs[0];
+                pllsetup->pll_n = 1;
+                pllsetup->pll_m = 1;
+                return clk_check_pll_setup(ifreq, pllsetup);
+        } else if (target_freq <= ifreq) {
+                pllsetup->analog_on = 0;
+                pllsetup->cco_bypass_b15 = 1;
+                pllsetup->direct_output_b14 = 0;
+                pllsetup->fdbk_div_ctrl_b13 = 1;
+                pllsetup->pll_n = 1;
+                pllsetup->pll_m = 1;
+                for (p = 0; p <= 3; p++) {
+                        pllsetup->pll_p = pll_postdivs[p];
+                        fclkout = clk_check_pll_setup(ifreq, pllsetup);
+                        if (abs(target_freq - fclkout) <= freqtol)
+                                return fclkout;
+                }
+        }
+
+        /* Is direct mode possible? */
+        pllsetup->analog_on = 1;
+        pllsetup->cco_bypass_b15 = 0;
+        pllsetup->direct_output_b14 = 1;
+        pllsetup->fdbk_div_ctrl_b13 = 0;
+        pllsetup->pll_p = pll_postdivs[0];
+        for (m = 1; m <= 256; m++) {
+                for (n = 1; n <= 4; n++) {
+                        /* Compute output frequency for this value */
+                        pllsetup->pll_n = n;
+                        pllsetup->pll_m = m;
+                        fclkout = clk_check_pll_setup(ifreq,
+                                pllsetup);
+                        if (abs(target_freq - fclkout) <=
+                                freqtol)
+                                return fclkout;
+                }
+        }
+
+        /* Is integer mode possible? */
+        pllsetup->analog_on = 1;
+        pllsetup->cco_bypass_b15 = 0;
+        pllsetup->direct_output_b14 = 0;
+        pllsetup->fdbk_div_ctrl_b13 = 1;
+        for (m = 1; m <= 256; m++) {
+                for (n = 1; n <= 4; n++) {
+                        for (p = 0; p < 4; p++) {
+                                /* Compute output frequency */
+                                pllsetup->pll_p = pll_postdivs[p];
+                                pllsetup->pll_n = n;
+                                pllsetup->pll_m = m;
+                                fclkout = clk_check_pll_setup(
+                                        ifreq, pllsetup);
+                                if (abs(target_freq - fclkout) <= freqtol)
+                                        return fclkout;
+                        }
+                }
+        }
+
+        /* Try non-integer mode */
+        pllsetup->analog_on = 1;
+        pllsetup->cco_bypass_b15 = 0;
+        pllsetup->direct_output_b14 = 0;
+        pllsetup->fdbk_div_ctrl_b13 = 0;
+        for (m = 1; m <= 256; m++) {
+                for (n = 1; n <= 4; n++) {
+                        for (p = 0; p < 4; p++) {
+                                /* Compute output frequency */
+                                pllsetup->pll_p = pll_postdivs[p];
+                                pllsetup->pll_n = n;
+                                pllsetup->pll_m = m;
+                                fclkout = clk_check_pll_setup(
+                                        ifreq, pllsetup);
+                                if (abs(target_freq - fclkout) <= freqtol)
+                                        return fclkout;
+                        }
+                }
+        }
+
+        return 0;
+}
+
+static struct clk clk_armpll = {
+        .parent         = &clk_sys,
+        .get_rate       = local_return_parent_rate,
+};
+
+/*
+ * Setup the USB PLL with a PLL structure
+ */
+static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
+{
+        u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
+        reg |= tmp;
+        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+        return clk_check_pll_setup(clk_usbpll.parent->rate,
+                pHCLKPllSetup);
+}
+
+static int local_usbpll_enable(struct clk *clk, int enable)
+{
+        u32 reg;
+        int ret = -ENODEV;
+        unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+
+        if (enable == 0) {
+                reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
+                        LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
+                __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+        } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
+                reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+                __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+                /* Wait for PLL lock */
+                while ((timeout > jiffies) & (ret == -ENODEV)) {
+                        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+                        if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
+                                ret = 0;
+                }
+
+                if (ret == 0) {
+                        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+                        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+                }
+        }
+
+        return ret;
+}
+
+static unsigned long local_usbpll_round_rate(struct clk *clk,
+        unsigned long rate)
+{
+        u32 clkin, usbdiv;
+        struct clk_pll_setup pllsetup;
+
+        /*
+         * Unlike other clocks, this clock has a KHz input rate, so bump
+         * it up to work with the PLL function
+         */
+        rate = rate * 1000;
+
+        clkin = clk->parent->rate;
+        usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
+                LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
+        clkin = clkin / usbdiv;
+
+        /* Try to find a good rate setup */
+        if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
+                return 0;
+
+        return clk_check_pll_setup(clkin, &pllsetup);
+}
+
+static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 clkin, reg, usbdiv;
+        struct clk_pll_setup pllsetup;
+
+        /*
+         * Unlike other clocks, this clock has a KHz input rate, so bump
+         * it up to work with the PLL function
+         */
+        rate = rate * 1000;
+
+        clkin = clk->get_rate(clk);
+        usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
+                LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
+        clkin = clkin / usbdiv;
+
+        /* Try to find a good rate setup */
+        if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
+                return -EINVAL;
+
+        local_usbpll_enable(clk, 0);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+        pllsetup.analog_on = 1;
+        local_clk_usbpll_setup(&pllsetup);
+
+        clk->rate = clk_check_pll_setup(clkin, &pllsetup);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+        return 0;
+}
+
+static struct clk clk_usbpll = {
+        .parent         = &osc_main,
+        .set_rate       = local_usbpll_set_rate,
+        .enable         = local_usbpll_enable,
+        .rate           = 48000, /* In KHz */
+        .get_rate       = local_return_parent_rate,
+        .round_rate     = local_usbpll_round_rate,
+};
+
+static u32 clk_get_hclk_div(void)
+{
+        static const u32 hclkdivs[4] = {1, 2, 4, 4};
+        return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
+                __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
+}
+
+static struct clk clk_hclk = {
+        .parent         = &clk_armpll,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_pclk = {
+        .parent         = &clk_armpll,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int local_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(clk->enable_reg);
+
+        if (enable == 0)
+                tmp &= ~clk->enable_mask;
+        else
+                tmp |= clk->enable_mask;
+
+        __raw_writel(tmp, clk->enable_reg);
+
+        return 0;
+}
+
+/* Peripheral clock sources */
+static struct clk clk_timer0 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer1 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer2 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer3 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_wdt = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_vfp9 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_DEBUG_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_dma = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_DMA_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart3 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart4 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart5 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart6 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c0 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c1 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c2 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = io_p2v(LPC32XX_USB_BASE + 0xFF4),
+        .enable_mask    = 0x4,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_ssp0 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_ssp1 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_kscan = {
+        .parent         = &osc_32KHz,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_KEY_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_nand = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2s0 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2s1 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_net = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_MACCLK_CTRL,
+        .enable_mask    = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
+                LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
+                LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_rtc = {
+        .parent         = &osc_32KHz,
+        .rate           = 1, /* 1 Hz */
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_usbd = {
+        .parent         = &clk_usbpll,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int tsc_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        /* Make sure 32KHz clock is the selected clock */
+        tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+        tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+        __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+
+        if (enable == 0)
+                __raw_writel(0, clk->enable_reg);
+        else
+                __raw_writel(clk->enable_mask, clk->enable_reg);
+
+        return 0;
+}
+
+static struct clk clk_tsc = {
+        .parent         = &osc_32KHz,
+        .enable         = tsc_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int mmc_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
+                ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+
+        /* If rate is 0, disable clock */
+        if (enable != 0)
+                tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+
+        __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
+
+        return 0;
+}
+
+static unsigned long mmc_get_rate(struct clk *clk)
+{
+        u32 div, rate, oldclk;
+
+        /* The MMC clock must be on when accessing an MMC register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+                LPC32XX_CLKPWR_MS_CTRL);
+        div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+        __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
+
+        /* Get the parent clock rate */
+        rate = clk->parent->get_rate(clk->parent);
+
+        /* Get the MMC controller clock divider value */
+        div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
+
+        if (!div)
+                div = 1;
+
+        return rate / div;
+}
+
+static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long div, prate;
+
+        /* Get the parent clock rate */
+        prate = clk->parent->get_rate(clk->parent);
+
+        if (rate >= prate)
+                return prate;
+
+        div = prate / rate;
+        if (div > 0xf)
+                div = 0xf;
+
+        return prate / div;
+}
+
+static int mmc_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 oldclk, tmp;
+        unsigned long prate, div, crate = mmc_round_rate(clk, rate);
+
+        prate = clk->parent->get_rate(clk->parent);
+
+        div = prate / crate;
+
+        /* The MMC clock must be on when accessing an MMC register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+                LPC32XX_CLKPWR_MS_CTRL);
+        tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
+                ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
+        tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
+        __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
+
+        __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
+
+        return 0;
+}
+
+static struct clk clk_mmc = {
+        .parent         = &clk_armpll,
+        .set_rate       = mmc_set_rate,
+        .get_rate       = mmc_get_rate,
+        .round_rate     = mmc_round_rate,
+        .enable         = mmc_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_MS_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+};
+
+static unsigned long clcd_get_rate(struct clk *clk)
+{
+        u32 tmp, div, rate, oldclk;
+
+        /* The LCD clock must be on when accessing an LCD register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+                LPC32XX_CLKPWR_LCDCLK_CTRL);
+        tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
+        __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        rate = clk->parent->get_rate(clk->parent);
+
+        /* Only supports internal clocking */
+        if (tmp & TIM2_BCD)
+                return rate;
+
+        div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
+        tmp = rate / (2 + div);
+
+        return tmp;
+}
+
+static int clcd_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 tmp, prate, div, oldclk;
+
+        /* The LCD clock must be on when accessing an LCD register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+                LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
+        prate = clk->parent->get_rate(clk->parent);
+
+        if (rate < prate) {
+                /* Find closest divider */
+                div = prate / rate;
+                if (div >= 2) {
+                        div -= 2;
+                        tmp &= ~TIM2_BCD;
+                }
+
+                tmp &= ~(0xF800001F);
+                tmp |= (div & 0x1F);
+                tmp |= (((div >> 5) & 0x1F) << 27);
+        }
+
+        __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
+        __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        return 0;
+}
+
+static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 prate, div;
+
+        prate = clk->parent->get_rate(clk->parent);
+
+        if (rate >= prate)
+                rate = prate;
+        else {
+                div = prate / rate;
+                if (div > 0x3ff)
+                        div = 0x3ff;
+
+                rate = prate / div;
+        }
+
+        return rate;
+}
+
+static struct clk clk_lcd = {
+        .parent         = &clk_hclk,
+        .set_rate       = clcd_set_rate,
+        .get_rate       = clcd_get_rate,
+        .round_rate     = clcd_round_rate,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_LCDCLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+};
+
+static inline void clk_lock(void)
+{
+        mutex_lock(&clkm_lock);
+}
+
+static inline void clk_unlock(void)
+{
+        mutex_unlock(&clkm_lock);
+}
+
+static void local_clk_disable(struct clk *clk)
+{
+        WARN_ON(clk->usecount == 0);
+
+        /* Don't attempt to disable clock if it has no users */
+        if (clk->usecount > 0) {
+                clk->usecount--;
+
+                /* Only disable clock when it has no more users */
+                if ((clk->usecount == 0) && (clk->enable))
+                        clk->enable(clk, 0);
+
+                /* Check parent clocks, they may need to be disabled too */
+                if (clk->parent)
+                        local_clk_disable(clk->parent);
+        }
+}
+
+static int local_clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        /* Enable parent clocks first and update use counts */
+        if (clk->parent)
+                ret = local_clk_enable(clk->parent);
+
+        if (!ret) {
+                /* Only enable clock if it's currently disabled */
+                if ((clk->usecount == 0) && (clk->enable))
+                        ret = clk->enable(clk, 1);
+
+                if (!ret)
+                        clk->usecount++;
+                else if (clk->parent)
+                        local_clk_disable(clk->parent);
+        }
+
+        return ret;
+}
+
+/*
+ * clk_enable - inform the system when the clock source should be running.
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret;
+
+        clk_lock();
+        ret = local_clk_enable(clk);
+        clk_unlock();
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/*
+ * clk_disable - inform the system when the clock source is no longer required
+ */
+void clk_disable(struct clk *clk)
+{
+        clk_lock();
+        local_clk_disable(clk);
+        clk_unlock();
+}
+EXPORT_SYMBOL(clk_disable);
+
+/*
+ * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+
+        clk_lock();
+        rate = clk->get_rate(clk);
+        clk_unlock();
+
+        return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/*
+ * clk_set_rate - set the clock rate for a clock source
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        /*
+         * Most system clocks can only be enabled or disabled, with
+         * the actual rate set as part of the peripheral dividers
+         * instead of high level clock control
+         */
+        if (clk->set_rate) {
+                clk_lock();
+                ret = clk->set_rate(clk, rate);
+                clk_unlock();
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+/*
+ * clk_round_rate - adjust a rate to the exact rate a clock can provide
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        clk_lock();
+
+        if (clk->round_rate)
+                rate = clk->round_rate(clk, rate);
+        else
+                rate = clk->get_rate(clk);
+
+        clk_unlock();
+
+        return rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+/*
+ * clk_set_parent - set the parent clock source for this clock
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        /* Clock re-parenting is not supported */
+        return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/*
+ * clk_get_parent - get the parent clock source for this clock
+ */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = (d), \
+                .con_id = (n), \
+                .clk = &(c), \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
+        _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
+        _REGISTER_CLOCK(NULL, "osc_main", osc_main)
+        _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
+        _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
+        _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
+        _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
+        _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
+        _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
+        _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
+        _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
+        _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
+        _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
+        _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
+        _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
+        _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
+        _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
+        _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
+        _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
+        _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
+        _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
+        _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
+        _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
+        _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
+        _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
+        _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
+        _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
+        _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
+        _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
+        _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
+        _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
+        _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
+        _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
+        _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
+};
+
+static int __init clk_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        /*
+         * Setup muxed SYSCLK for HCLK PLL base -this selects the
+         * parent clock used for the ARM PLL and is used to derive
+         * the many system clock rates in the device.
+         */
+        if (clk_is_sysclk_mainosc() != 0)
+                clk_sys.parent = &osc_main;
+        else
+                clk_sys.parent = &osc_pll397;
+
+        clk_sys.rate = clk_sys.parent->rate;
+
+        /* Compute the current ARM PLL and USB PLL frequencies */
+        local_update_armpll_rate();
+
+        /* Compute HCLK and PCLK bus rates */
+        clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
+        clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
+
+        /*
+         * Enable system clocks - this step is somewhat formal, as the
+         * clocks are already running, but it does get the clock data
+         * inline with the actual system state. Never disable these
+         * clocks as they will only stop if the system is going to sleep.
+         * In that case, the chip/system power management functions will
+         * handle clock gating.
+         */
+        if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
+                printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
+
+        /*
+         * Timers 0 and 1 were enabled and are being used by the high
+         * resolution tick function prior to this driver being initialized.
+         * Tag them now as used.
+         */
+        if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
+                printk(KERN_ERR "Error enabling timer tick clocks\n");
+
+        return 0;
+}
+core_initcall(clk_init);
+
diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
new file mode 100644
index 000000000000..c0a8434307f7
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-lpc32xx/clock.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LPC32XX_CLOCK_H
+#define __LPC32XX_CLOCK_H
+
+struct clk {
+        struct list_head node;
+        struct clk *parent;
+        u32 rate;
+        u32 usecount;
+
+        int (*set_rate) (struct clk *, unsigned long);
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        unsigned long (*get_rate) (struct clk *clk);
+        int (*enable) (struct clk *, int);
+
+        /* Register address and bit mask for simple clocks */
+        void __iomem *enable_reg;
+        u32 enable_mask;
+};
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
new file mode 100644
index 000000000000..ee24dc28e93e
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -0,0 +1,271 @@
+/*
+ * arch/arm/mach-lpc32xx/common.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/i2c-pnx.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/i2c.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Watchdog timer
+ */
+static struct resource watchdog_resources[] = {
+        [0] = {
+                .start = LPC32XX_WDTIM_BASE,
+                .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device lpc32xx_watchdog_device = {
+        .name = "pnx4008-watchdog",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(watchdog_resources),
+        .resource = watchdog_resources,
+};
+
+/*
+ * I2C busses
+ */
+static struct i2c_pnx_data i2c0_data = {
+        .name = I2C_CHIP_NAME "1",
+        .base = LPC32XX_I2C1_BASE,
+        .irq = IRQ_LPC32XX_I2C_1,
+};
+
+static struct i2c_pnx_data i2c1_data = {
+        .name = I2C_CHIP_NAME "2",
+        .base = LPC32XX_I2C2_BASE,
+        .irq = IRQ_LPC32XX_I2C_2,
+};
+
+static struct i2c_pnx_data i2c2_data = {
+        .name = "USB-I2C",
+        .base = LPC32XX_OTG_I2C_BASE,
+        .irq = IRQ_LPC32XX_USB_I2C,
+};
+
+struct platform_device lpc32xx_i2c0_device = {
+        .name = "pnx-i2c",
+        .id = 0,
+        .dev = {
+                .platform_data = &i2c0_data,
+        },
+};
+
+struct platform_device lpc32xx_i2c1_device = {
+        .name = "pnx-i2c",
+        .id = 1,
+        .dev = {
+                .platform_data = &i2c1_data,
+        },
+};
+
+struct platform_device lpc32xx_i2c2_device = {
+        .name = "pnx-i2c",
+        .id = 2,
+        .dev = {
+                .platform_data = &i2c2_data,
+        },
+};
+
+/*
+ * Returns the unique ID for the device
+ */
+void lpc32xx_get_uid(u32 devid[4])
+{
+        int i;
+
+        for (i = 0; i < 4; i++)
+                devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
+}
+
+/*
+ * Returns SYSCLK source
+ * 0 = PLL397, 1 = main oscillator
+ */
+int clk_is_sysclk_mainosc(void)
+{
+        if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
+                LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
+                return 1;
+
+        return 0;
+}
+
+/*
+ * System reset via the watchdog timer
+ */
+void lpc32xx_watchdog_reset(void)
+{
+        /* Make sure WDT clocks are enabled */
+        __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+                LPC32XX_CLKPWR_TIMER_CLK_CTRL);
+
+        /* Instant assert of RESETOUT_N with pulse length 1mS */
+        __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
+        __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
+}
+
+/*
+ * Detects and returns IRAM size for the device variation
+ */
+#define LPC32XX_IRAM_BANK_SIZE SZ_128K
+static u32 iram_size;
+u32 lpc32xx_return_iram_size(void)
+{
+        if (iram_size == 0) {
+                u32 savedval1, savedval2;
+                void __iomem *iramptr1, *iramptr2;
+
+                iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
+                iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
+                savedval1 = __raw_readl(iramptr1);
+                savedval2 = __raw_readl(iramptr2);
+
+                if (savedval1 == savedval2) {
+                        __raw_writel(savedval2 + 1, iramptr2);
+                        if (__raw_readl(iramptr1) == savedval2 + 1)
+                                iram_size = LPC32XX_IRAM_BANK_SIZE;
+                        else
+                                iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
+                        __raw_writel(savedval2, iramptr2);
+                } else
+                        iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
+        }
+
+        return iram_size;
+}
+
+/*
+ * Computes PLL rate from PLL register and input clock
+ */
+u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
+{
+        u32 ilfreq, p, m, n, fcco, fref, cfreq;
+        int mode;
+
+        /*
+         * PLL requirements
+         * ifreq must be >= 1MHz and <= 20MHz
+         * FCCO must be >= 156MHz and <= 320MHz
+         * FREF must be >= 1MHz and <= 27MHz
+         * Assume the passed input data is not valid
+         */
+
+        ilfreq = ifreq;
+        m = pllsetup->pll_m;
+        n = pllsetup->pll_n;
+        p = pllsetup->pll_p;
+
+        mode = (pllsetup->cco_bypass_b15 << 2) |
+                (pllsetup->direct_output_b14 << 1) |
+        pllsetup->fdbk_div_ctrl_b13;
+
+        switch (mode) {
+        case 0x0: /* Non-integer mode */
+                cfreq = (m * ilfreq) / (2 * p * n);
+                fcco = (m * ilfreq) / n;
+                fref = ilfreq / n;
+                break;
+
+        case 0x1: /* integer mode */
+                cfreq = (m * ilfreq) / n;
+                fcco = (m * ilfreq) / (n * 2 * p);
+                fref = ilfreq / n;
+                break;
+
+        case 0x2:
+        case 0x3: /* Direct mode */
+                cfreq = (m * ilfreq) / n;
+                fcco = cfreq;
+                fref = ilfreq / n;
+                break;
+
+        case 0x4:
+        case 0x5: /* Bypass mode */
+                cfreq = ilfreq / (2 * p);
+                fcco = 156000000;
+                fref = 1000000;
+                break;
+
+        case 0x6:
+        case 0x7: /* Direct bypass mode */
+        default:
+                cfreq = ilfreq;
+                fcco = 156000000;
+                fref = 1000000;
+                break;
+        }
+
+        if (fcco < 156000000 || fcco > 320000000)
+                cfreq = 0;
+
+        if (fref < 1000000 || fref > 27000000)
+                cfreq = 0;
+
+        return (u32) cfreq;
+}
+
+u32 clk_get_pclk_div(void)
+{
+        return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
+}
+
+static struct map_desc lpc32xx_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
+                .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
+                .length         = LPC32XX_AHB0_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
+                .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
+                .length         = LPC32XX_AHB1_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
+                .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
+                .length         = LPC32XX_FABAPB_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
+                .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
+                .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
+                .type           = MT_DEVICE
+        },
+};
+
+void __init lpc32xx_map_io(void)
+{
+        iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
+}
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
new file mode 100644
index 000000000000..f82211fd80c1
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-lpc32xx/common.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2009-2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LPC32XX_COMMON_H
+#define __LPC32XX_COMMON_H
+
+#include <linux/platform_device.h>
+
+/*
+ * Arch specific platform device structures
+ */
+extern struct platform_device lpc32xx_watchdog_device;
+extern struct platform_device lpc32xx_i2c0_device;
+extern struct platform_device lpc32xx_i2c1_device;
+extern struct platform_device lpc32xx_i2c2_device;
+
+/*
+ * Other arch specific structures and functions
+ */
+extern struct sys_timer lpc32xx_timer;
+extern void __init lpc32xx_init_irq(void);
+extern void __init lpc32xx_map_io(void);
+extern void __init lpc32xx_serial_init(void);
+extern void __init lpc32xx_gpio_init(void);
+
+/*
+ * Structure used for setting up and querying the PLLS
+ */
+struct clk_pll_setup {
+        int analog_on;
+        int cco_bypass_b15;
+        int direct_output_b14;
+        int fdbk_div_ctrl_b13;
+        int pll_p;
+        int pll_n;
+        u32 pll_m;
+};
+
+extern int clk_is_sysclk_mainosc(void);
+extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
+extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
+extern u32 clk_get_pclk_div(void);
+
+/*
+ * Returns the LPC32xx unique 128-bit chip ID
+ */
+extern void lpc32xx_get_uid(u32 devid[4]);
+
+extern void lpc32xx_watchdog_reset(void);
+extern u32 lpc32xx_return_iram_size(void);
+
+/*
+ * Pointers used for sizing and copying suspend function data
+ */
+extern int lpc32xx_sys_suspend(void);
+extern int lpc32xx_sys_suspend_sz;
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
new file mode 100644
index 000000000000..69061ea8997a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -0,0 +1,446 @@
+/*
+ * arch/arm/mach-lpc32xx/gpiolib.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+#define LPC32XX_GPIO_P3_INP_STATE               _GPREG(0x000)
+#define LPC32XX_GPIO_P3_OUTP_SET                _GPREG(0x004)
+#define LPC32XX_GPIO_P3_OUTP_CLR                _GPREG(0x008)
+#define LPC32XX_GPIO_P3_OUTP_STATE              _GPREG(0x00C)
+#define LPC32XX_GPIO_P2_DIR_SET                 _GPREG(0x010)
+#define LPC32XX_GPIO_P2_DIR_CLR                 _GPREG(0x014)
+#define LPC32XX_GPIO_P2_DIR_STATE               _GPREG(0x018)
+#define LPC32XX_GPIO_P2_INP_STATE               _GPREG(0x01C)
+#define LPC32XX_GPIO_P2_OUTP_SET                _GPREG(0x020)
+#define LPC32XX_GPIO_P2_OUTP_CLR                _GPREG(0x024)
+#define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
+#define LPC32XX_GPIO_P0_INP_STATE               _GPREG(0x040)
+#define LPC32XX_GPIO_P0_OUTP_SET                _GPREG(0x044)
+#define LPC32XX_GPIO_P0_OUTP_CLR                _GPREG(0x048)
+#define LPC32XX_GPIO_P0_OUTP_STATE              _GPREG(0x04C)
+#define LPC32XX_GPIO_P0_DIR_SET                 _GPREG(0x050)
+#define LPC32XX_GPIO_P0_DIR_CLR                 _GPREG(0x054)
+#define LPC32XX_GPIO_P0_DIR_STATE               _GPREG(0x058)
+#define LPC32XX_GPIO_P1_INP_STATE               _GPREG(0x060)
+#define LPC32XX_GPIO_P1_OUTP_SET                _GPREG(0x064)
+#define LPC32XX_GPIO_P1_OUTP_CLR                _GPREG(0x068)
+#define LPC32XX_GPIO_P1_OUTP_STATE              _GPREG(0x06C)
+#define LPC32XX_GPIO_P1_DIR_SET                 _GPREG(0x070)
+#define LPC32XX_GPIO_P1_DIR_CLR                 _GPREG(0x074)
+#define LPC32XX_GPIO_P1_DIR_STATE               _GPREG(0x078)
+
+#define GPIO012_PIN_TO_BIT(x)                   (1 << (x))
+#define GPIO3_PIN_TO_BIT(x)                     (1 << ((x) + 25))
+#define GPO3_PIN_TO_BIT(x)                      (1 << (x))
+#define GPIO012_PIN_IN_SEL(x, y)                (((x) >> (y)) & 1)
+#define GPIO3_PIN_IN_SHIFT(x)                   ((x) == 5 ? 24 : 10 + (x))
+#define GPIO3_PIN_IN_SEL(x, y)                  ((x) >> GPIO3_PIN_IN_SHIFT(y))
+#define GPIO3_PIN5_IN_SEL(x)                    (((x) >> 24) & 1)
+#define GPI3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
+
+struct gpio_regs {
+        void __iomem *inp_state;
+        void __iomem *outp_set;
+        void __iomem *outp_clr;
+        void __iomem *dir_set;
+        void __iomem *dir_clr;
+};
+
+/*
+ * GPIO names
+ */
+static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
+        "p0.0", "p0.1", "p0.2", "p0.3",
+        "p0.4", "p0.5", "p0.6", "p0.7"
+};
+
+static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
+        "p1.0", "p1.1", "p1.2", "p1.3",
+        "p1.4", "p1.5", "p1.6", "p1.7",
+        "p1.8", "p1.9", "p1.10", "p1.11",
+        "p1.12", "p1.13", "p1.14", "p1.15",
+        "p1.16", "p1.17", "p1.18", "p1.19",
+        "p1.20", "p1.21", "p1.22", "p1.23",
+};
+
+static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
+        "p2.0", "p2.1", "p2.2", "p2.3",
+        "p2.4", "p2.5", "p2.6", "p2.7",
+        "p2.8", "p2.9", "p2.10", "p2.11",
+        "p2.12"
+};
+
+static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
+        "gpi000", "gpio01", "gpio02", "gpio03",
+        "gpio04", "gpio05"
+};
+
+static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
+        "gpi00", "gpi01", "gpi02", "gpi03",
+        "gpi04", "gpi05", "gpi06", "gpi07",
+        "gpi08", "gpi09",  NULL,    NULL,
+         NULL,    NULL,    NULL,   "gpi15",
+        "gpi16", "gpi17", "gpi18", "gpi19",
+        "gpi20", "gpi21", "gpi22", "gpi23",
+        "gpi24", "gpi25", "gpi26", "gpi27"
+};
+
+static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
+        "gpo00", "gpo01", "gpo02", "gpo03",
+        "gpo04", "gpo05", "gpo06", "gpo07",
+        "gpo08", "gpo09", "gpo10", "gpo11",
+        "gpo12", "gpo13", "gpo14", "gpo15",
+        "gpo16", "gpo17", "gpo18", "gpo19",
+        "gpo20", "gpo21", "gpo22", "gpo23"
+};
+
+static struct gpio_regs gpio_grp_regs_p0 = {
+        .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p1 = {
+        .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p2 = {
+        .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p3 = {
+        .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
+};
+
+struct lpc32xx_gpio_chip {
+        struct gpio_chip        chip;
+        struct gpio_regs        *gpio_grp;
+};
+
+static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
+        struct gpio_chip *gpc)
+{
+        return container_of(gpc, struct lpc32xx_gpio_chip, chip);
+}
+
+static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int input)
+{
+        if (input)
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->dir_clr);
+        else
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->dir_set);
+}
+
+static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int input)
+{
+        u32 u = GPIO3_PIN_TO_BIT(pin);
+
+        if (input)
+                __raw_writel(u, group->gpio_grp->dir_clr);
+        else
+                __raw_writel(u, group->gpio_grp->dir_set);
+}
+
+static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int high)
+{
+        if (high)
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->outp_set);
+        else
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->outp_clr);
+}
+
+static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int high)
+{
+        u32 u = GPIO3_PIN_TO_BIT(pin);
+
+        if (high)
+                __raw_writel(u, group->gpio_grp->outp_set);
+        else
+                __raw_writel(u, group->gpio_grp->outp_clr);
+}
+
+static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int high)
+{
+        if (high)
+                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
+        else
+                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
+}
+
+static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
+        unsigned pin)
+{
+        return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
+                pin);
+}
+
+static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin)
+{
+        int state = __raw_readl(group->gpio_grp->inp_state);
+
+        /*
+         * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
+         * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
+         */
+        return GPIO3_PIN_IN_SEL(state, pin);
+}
+
+static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin)
+{
+        return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
+        unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p012(group, pin, 1);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
+        unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p3(group, pin, 1);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
+        unsigned pin)
+{
+        return 0;
+}
+
+static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        return __get_gpio_state_p012(group, pin);
+}
+
+static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        return __get_gpio_state_p3(group, pin);
+}
+
+static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        return __get_gpi_state_p3(group, pin);
+}
+
+static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p012(group, pin, 0);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p3(group, pin, 0);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        return 0;
+}
+
+static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_level_p012(group, pin, value);
+}
+
+static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_level_p3(group, pin, value);
+}
+
+static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpo_level_p3(group, pin, value);
+}
+
+static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+        if (pin < chip->ngpio)
+                return 0;
+
+        return -EINVAL;
+}
+
+static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
+        {
+                .chip = {
+                        .label                  = "gpio_p0",
+                        .direction_input        = lpc32xx_gpio_dir_input_p012,
+                        .get                    = lpc32xx_gpio_get_value_p012,
+                        .direction_output       = lpc32xx_gpio_dir_output_p012,
+                        .set                    = lpc32xx_gpio_set_value_p012,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P0_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P0_MAX,
+                        .names                  = gpio_p0_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p0,
+        },
+        {
+                .chip = {
+                        .label                  = "gpio_p1",
+                        .direction_input        = lpc32xx_gpio_dir_input_p012,
+                        .get                    = lpc32xx_gpio_get_value_p012,
+                        .direction_output       = lpc32xx_gpio_dir_output_p012,
+                        .set                    = lpc32xx_gpio_set_value_p012,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P1_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P1_MAX,
+                        .names                  = gpio_p1_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p1,
+        },
+        {
+                .chip = {
+                        .label                  = "gpio_p2",
+                        .direction_input        = lpc32xx_gpio_dir_input_p012,
+                        .get                    = lpc32xx_gpio_get_value_p012,
+                        .direction_output       = lpc32xx_gpio_dir_output_p012,
+                        .set                    = lpc32xx_gpio_set_value_p012,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P2_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P2_MAX,
+                        .names                  = gpio_p2_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p2,
+        },
+        {
+                .chip = {
+                        .label                  = "gpio_p3",
+                        .direction_input        = lpc32xx_gpio_dir_input_p3,
+                        .get                    = lpc32xx_gpio_get_value_p3,
+                        .direction_output       = lpc32xx_gpio_dir_output_p3,
+                        .set                    = lpc32xx_gpio_set_value_p3,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P3_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P3_MAX,
+                        .names                  = gpio_p3_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p3,
+        },
+        {
+                .chip = {
+                        .label                  = "gpi_p3",
+                        .direction_input        = lpc32xx_gpio_dir_in_always,
+                        .get                    = lpc32xx_gpi_get_value,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPI_P3_GRP,
+                        .ngpio                  = LPC32XX_GPI_P3_MAX,
+                        .names                  = gpi_p3_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p3,
+        },
+        {
+                .chip = {
+                        .label                  = "gpo_p3",
+                        .direction_output       = lpc32xx_gpio_dir_out_always,
+                        .set                    = lpc32xx_gpo_set_value,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPO_P3_GRP,
+                        .ngpio                  = LPC32XX_GPO_P3_MAX,
+                        .names                  = gpo_p3_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p3,
+        },
+};
+
+void __init lpc32xx_gpio_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
+                gpiochip_add(&lpc32xx_gpiochip[i].chip);
+}
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
index 1ac4e1682e5c..9bf0637e29ce 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
@@ -1,5 +1,9 @@
 /*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ * arch/arm/mach-lpc32xx/include/mach/clkdev.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,12 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
-#define __ASM_ARCH_MXC_BOARD_PCM043_H__
+#ifndef __ASM_ARCH_CLKDEV_H
+#define __ASM_ARCH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
 
-#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 383f1c04df06..621744d6b152 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -1,5 +1,9 @@
 /*
- *  Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved
+ * arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,18 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
+/*
+ * Debug output is hardcoded to standard UART 5
+*/
+
+        .macro  addruart,rx, tmp
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                         @ MMU enabled?
+        ldreq   \rx, =0x40090000
+        ldrne   \rx, =0xF4090000
+        .endm
 
-#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..870227c96602
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#define LPC32XX_INTC_MASKED_STATUS_OFS  0x8
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+/*
+ * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
+ * as set if an interrupt is pending.
+ */
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
+        clz     \irqnr, \irqstat
+        rsb     \irqnr, \irqnr, #31
+        teq     \irqstat, #0
+        .endm
+
+        .macro  irq_prio_table
+        .endm
+
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
new file mode 100644
index 000000000000..67d03da1eee9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -0,0 +1,74 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/gpio.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+/*
+ * Note!
+ * Muxed GP pins need to be setup to the GP state in the board level
+ * code prior to using this driver.
+ * GPI pins : 28xP3 group
+ * GPO pins : 24xP3 group
+ * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
+ */
+
+#define LPC32XX_GPIO_P0_MAX 8
+#define LPC32XX_GPIO_P1_MAX 24
+#define LPC32XX_GPIO_P2_MAX 13
+#define LPC32XX_GPIO_P3_MAX 6
+#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPO_P3_MAX 24
+
+#define LPC32XX_GPIO_P0_GRP 0
+#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
+#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
+#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
+#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
+#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
+
+/*
+ * A specific GPIO can be selected with this macro
+ * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+ * See the LPC32x0 User's guide for GPIO group numbers
+ */
+#define LPC32XX_GPIO(x, y) ((x) + (y))
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return __gpio_to_irq(gpio);
+}
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
new file mode 100644
index 000000000000..33e1dde37bd9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/hardware.h
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Start of virtual addresses for IO devices
+ */
+#define IO_BASE         0xF0000000
+
+/*
+ * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
+ */
+#define IO_ADDRESS(x)   (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+                         IO_BASE)
+
+#define io_p2v(x)       ((void __iomem *) (unsigned long) IO_ADDRESS(x))
+#define io_v2p(x)       ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
new file mode 100644
index 000000000000..034dc9286bcc
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/i2c.h
@@ -0,0 +1,63 @@
+/*
+ * PNX4008-specific tweaks for I2C IP3204 block
+ *
+ * Author: Vitaly Wool <vwool@ru.mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
+
+enum {
+        mstatus_tdi = 0x00000001,
+        mstatus_afi = 0x00000002,
+        mstatus_nai = 0x00000004,
+        mstatus_drmi = 0x00000008,
+        mstatus_active = 0x00000020,
+        mstatus_scl = 0x00000040,
+        mstatus_sda = 0x00000080,
+        mstatus_rff = 0x00000100,
+        mstatus_rfe = 0x00000200,
+        mstatus_tff = 0x00000400,
+        mstatus_tfe = 0x00000800,
+};
+
+enum {
+        mcntrl_tdie = 0x00000001,
+        mcntrl_afie = 0x00000002,
+        mcntrl_naie = 0x00000004,
+        mcntrl_drmie = 0x00000008,
+        mcntrl_daie = 0x00000020,
+        mcntrl_rffie = 0x00000040,
+        mcntrl_tffie = 0x00000080,
+        mcntrl_reset = 0x00000100,
+        mcntrl_cdbmode = 0x00000400,
+};
+
+enum {
+        rw_bit = 1 << 0,
+        start_bit = 1 << 8,
+        stop_bit = 1 << 9,
+};
+
+#define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
+#define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
+#define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
+#define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
+#define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
+#define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
+#define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
+#define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
+#define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
+#define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
+#define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
+#define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
+#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
+
+#define I2C_CHIP_NAME           "PNX4008-I2C"
+
+#endif                          /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/mach-lpc32xx/include/mach/io.h
index 13411709b13a..9b59ab5cef89 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/mach-lpc32xx/include/mach/io.h
@@ -1,5 +1,9 @@
 /*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ * arch/arm/mach-lpc32xx/include/mach/io.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,14 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
-#define __ASM_ARCH_MXC_BOARD_PCM037_H__
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff
+
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
 
-#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
new file mode 100644
index 000000000000..2667f52e3b04
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/irqs.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_IRQS_H
+#define __ASM_ARM_ARCH_IRQS_H
+
+#define LPC32XX_SIC1_IRQ(n)             (32 + (n))
+#define LPC32XX_SIC2_IRQ(n)             (64 + (n))
+
+/*
+ * MIC interrupts
+ */
+#define IRQ_LPC32XX_SUB1IRQ             0
+#define IRQ_LPC32XX_SUB2IRQ             1
+#define IRQ_LPC32XX_PWM3                3
+#define IRQ_LPC32XX_PWM4                4
+#define IRQ_LPC32XX_HSTIMER             5
+#define IRQ_LPC32XX_WATCH               6
+#define IRQ_LPC32XX_UART_IIR3           7
+#define IRQ_LPC32XX_UART_IIR4           8
+#define IRQ_LPC32XX_UART_IIR5           9
+#define IRQ_LPC32XX_UART_IIR6           10
+#define IRQ_LPC32XX_FLASH               11
+#define IRQ_LPC32XX_SD1                 13
+#define IRQ_LPC32XX_LCD                 14
+#define IRQ_LPC32XX_SD0                 15
+#define IRQ_LPC32XX_TIMER0              16
+#define IRQ_LPC32XX_TIMER1              17
+#define IRQ_LPC32XX_TIMER2              18
+#define IRQ_LPC32XX_TIMER3              19
+#define IRQ_LPC32XX_SSP0                20
+#define IRQ_LPC32XX_SSP1                21
+#define IRQ_LPC32XX_I2S0                22
+#define IRQ_LPC32XX_I2S1                23
+#define IRQ_LPC32XX_UART_IIR7           24
+#define IRQ_LPC32XX_UART_IIR2           25
+#define IRQ_LPC32XX_UART_IIR1           26
+#define IRQ_LPC32XX_MSTIMER             27
+#define IRQ_LPC32XX_DMA                 28
+#define IRQ_LPC32XX_ETHERNET            29
+#define IRQ_LPC32XX_SUB1FIQ             30
+#define IRQ_LPC32XX_SUB2FIQ             31
+
+/*
+ * SIC1 interrupts start at offset 32
+ */
+#define IRQ_LPC32XX_JTAG_COMM_TX        LPC32XX_SIC1_IRQ(1)
+#define IRQ_LPC32XX_JTAG_COMM_RX        LPC32XX_SIC1_IRQ(2)
+#define IRQ_LPC32XX_GPI_11              LPC32XX_SIC1_IRQ(4)
+#define IRQ_LPC32XX_TS_P                LPC32XX_SIC1_IRQ(6)
+#define IRQ_LPC32XX_TS_IRQ              LPC32XX_SIC1_IRQ(7)
+#define IRQ_LPC32XX_TS_AUX              LPC32XX_SIC1_IRQ(8)
+#define IRQ_LPC32XX_SPI2                LPC32XX_SIC1_IRQ(12)
+#define IRQ_LPC32XX_PLLUSB              LPC32XX_SIC1_IRQ(13)
+#define IRQ_LPC32XX_PLLHCLK             LPC32XX_SIC1_IRQ(14)
+#define IRQ_LPC32XX_PLL397              LPC32XX_SIC1_IRQ(17)
+#define IRQ_LPC32XX_I2C_2               LPC32XX_SIC1_IRQ(18)
+#define IRQ_LPC32XX_I2C_1               LPC32XX_SIC1_IRQ(19)
+#define IRQ_LPC32XX_RTC                 LPC32XX_SIC1_IRQ(20)
+#define IRQ_LPC32XX_KEY                 LPC32XX_SIC1_IRQ(22)
+#define IRQ_LPC32XX_SPI1                LPC32XX_SIC1_IRQ(23)
+#define IRQ_LPC32XX_SW                  LPC32XX_SIC1_IRQ(24)
+#define IRQ_LPC32XX_USB_OTG_TIMER       LPC32XX_SIC1_IRQ(25)
+#define IRQ_LPC32XX_USB_OTG_ATX         LPC32XX_SIC1_IRQ(26)
+#define IRQ_LPC32XX_USB_HOST            LPC32XX_SIC1_IRQ(27)
+#define IRQ_LPC32XX_USB_DEV_DMA         LPC32XX_SIC1_IRQ(28)
+#define IRQ_LPC32XX_USB_DEV_LP          LPC32XX_SIC1_IRQ(29)
+#define IRQ_LPC32XX_USB_DEV_HP          LPC32XX_SIC1_IRQ(30)
+#define IRQ_LPC32XX_USB_I2C             LPC32XX_SIC1_IRQ(31)
+
+/*
+ * SIC2 interrupts start at offset 64
+ */
+#define IRQ_LPC32XX_GPIO_00             LPC32XX_SIC2_IRQ(0)
+#define IRQ_LPC32XX_GPIO_01             LPC32XX_SIC2_IRQ(1)
+#define IRQ_LPC32XX_GPIO_02             LPC32XX_SIC2_IRQ(2)
+#define IRQ_LPC32XX_GPIO_03             LPC32XX_SIC2_IRQ(3)
+#define IRQ_LPC32XX_GPIO_04             LPC32XX_SIC2_IRQ(4)
+#define IRQ_LPC32XX_GPIO_05             LPC32XX_SIC2_IRQ(5)
+#define IRQ_LPC32XX_SPI2_DATAIN         LPC32XX_SIC2_IRQ(6)
+#define IRQ_LPC32XX_U2_HCTS             LPC32XX_SIC2_IRQ(7)
+#define IRQ_LPC32XX_P0_P1_IRQ           LPC32XX_SIC2_IRQ(8)
+#define IRQ_LPC32XX_GPI_08              LPC32XX_SIC2_IRQ(9)
+#define IRQ_LPC32XX_GPI_09              LPC32XX_SIC2_IRQ(10)
+#define IRQ_LPC32XX_GPI_19              LPC32XX_SIC2_IRQ(11)
+#define IRQ_LPC32XX_U7_HCTS             LPC32XX_SIC2_IRQ(12)
+#define IRQ_LPC32XX_GPI_07              LPC32XX_SIC2_IRQ(15)
+#define IRQ_LPC32XX_SDIO                LPC32XX_SIC2_IRQ(18)
+#define IRQ_LPC32XX_U5_RX               LPC32XX_SIC2_IRQ(19)
+#define IRQ_LPC32XX_SPI1_DATAIN         LPC32XX_SIC2_IRQ(20)
+#define IRQ_LPC32XX_GPI_00              LPC32XX_SIC2_IRQ(22)
+#define IRQ_LPC32XX_GPI_01              LPC32XX_SIC2_IRQ(23)
+#define IRQ_LPC32XX_GPI_02              LPC32XX_SIC2_IRQ(24)
+#define IRQ_LPC32XX_GPI_03              LPC32XX_SIC2_IRQ(25)
+#define IRQ_LPC32XX_GPI_04              LPC32XX_SIC2_IRQ(26)
+#define IRQ_LPC32XX_GPI_05              LPC32XX_SIC2_IRQ(27)
+#define IRQ_LPC32XX_GPI_06              LPC32XX_SIC2_IRQ(28)
+#define IRQ_LPC32XX_SYSCLK              LPC32XX_SIC2_IRQ(31)
+
+#define NR_IRQS                         96
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h
new file mode 100644
index 000000000000..044e1acecbe6
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/memory.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/memory.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset of bank 0
+ */
+#define PHYS_OFFSET     UL(0x80000000)
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
new file mode 100644
index 000000000000..14ea8d1aadb5
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -0,0 +1,694 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/platform.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
+
+#define _SBF(f, v)                              ((v) << (f))
+#define _BIT(n)                                 _SBF(n, 1)
+
+/*
+ * AHB 0 physical base addresses
+ */
+#define LPC32XX_SLC_BASE                        0x20020000
+#define LPC32XX_SSP0_BASE                       0x20084000
+#define LPC32XX_SPI1_BASE                       0x20088000
+#define LPC32XX_SSP1_BASE                       0x2008C000
+#define LPC32XX_SPI2_BASE                       0x20090000
+#define LPC32XX_I2S0_BASE                       0x20094000
+#define LPC32XX_SD_BASE                         0x20098000
+#define LPC32XX_I2S1_BASE                       0x2009C000
+#define LPC32XX_MLC_BASE                        0x200A8000
+#define LPC32XX_AHB0_START                      LPC32XX_SLC_BASE
+#define LPC32XX_AHB0_SIZE                       0x00089000
+
+/*
+ * AHB 1 physical base addresses
+ */
+#define LPC32XX_DMA_BASE                        0x31000000
+#define LPC32XX_USB_BASE                        0x31020000
+#define LPC32XX_USBH_BASE                       0x31020000
+#define LPC32XX_USB_OTG_BASE                    0x31020000
+#define LPC32XX_OTG_I2C_BASE                    0x31020300
+#define LPC32XX_LCD_BASE                        0x31040000
+#define LPC32XX_ETHERNET_BASE                   0x31060000
+#define LPC32XX_EMC_BASE                        0x31080000
+#define LPC32XX_ETB_CFG_BASE                    0x310C0000
+#define LPC32XX_ETB_DATA_BASE                   0x310E0000
+#define LPC32XX_AHB1_START                      LPC32XX_DMA_BASE
+#define LPC32XX_AHB1_SIZE                       0x000E1000
+
+/*
+ * FAB physical base addresses
+ */
+#define LPC32XX_CLK_PM_BASE                     0x40004000
+#define LPC32XX_MIC_BASE                        0x40008000
+#define LPC32XX_SIC1_BASE                       0x4000C000
+#define LPC32XX_SIC2_BASE                       0x40010000
+#define LPC32XX_HS_UART1_BASE                   0x40014000
+#define LPC32XX_HS_UART2_BASE                   0x40018000
+#define LPC32XX_HS_UART7_BASE                   0x4001C000
+#define LPC32XX_RTC_BASE                        0x40024000
+#define LPC32XX_RTC_RAM_BASE                    0x40024080
+#define LPC32XX_GPIO_BASE                       0x40028000
+#define LPC32XX_PWM3_BASE                       0x4002C000
+#define LPC32XX_PWM4_BASE                       0x40030000
+#define LPC32XX_MSTIM_BASE                      0x40034000
+#define LPC32XX_HSTIM_BASE                      0x40038000
+#define LPC32XX_WDTIM_BASE                      0x4003C000
+#define LPC32XX_DEBUG_CTRL_BASE                 0x40040000
+#define LPC32XX_TIMER0_BASE                     0x40044000
+#define LPC32XX_ADC_BASE                        0x40048000
+#define LPC32XX_TIMER1_BASE                     0x4004C000
+#define LPC32XX_KSCAN_BASE                      0x40050000
+#define LPC32XX_UART_CTRL_BASE                  0x40054000
+#define LPC32XX_TIMER2_BASE                     0x40058000
+#define LPC32XX_PWM1_BASE                       0x4005C000
+#define LPC32XX_PWM2_BASE                       0x4005C004
+#define LPC32XX_TIMER3_BASE                     0x40060000
+
+/*
+ * APB physical base addresses
+ */
+#define LPC32XX_UART3_BASE                      0x40080000
+#define LPC32XX_UART4_BASE                      0x40088000
+#define LPC32XX_UART5_BASE                      0x40090000
+#define LPC32XX_UART6_BASE                      0x40098000
+#define LPC32XX_I2C1_BASE                       0x400A0000
+#define LPC32XX_I2C2_BASE                       0x400A8000
+
+/*
+ * FAB and APB base and sizing
+ */
+#define LPC32XX_FABAPB_START                    LPC32XX_CLK_PM_BASE
+#define LPC32XX_FABAPB_SIZE                     0x000A5000
+
+/*
+ * Internal memory bases and sizes
+ */
+#define LPC32XX_IRAM_BASE                       0x08000000
+#define LPC32XX_IROM_BASE                       0x0C000000
+
+/*
+ * External Static Memory Bank Address Space Bases
+ */
+#define LPC32XX_EMC_CS0_BASE                    0xE0000000
+#define LPC32XX_EMC_CS1_BASE                    0xE1000000
+#define LPC32XX_EMC_CS2_BASE                    0xE2000000
+#define LPC32XX_EMC_CS3_BASE                    0xE3000000
+
+/*
+ * External SDRAM Memory Bank Address Space Bases
+ */
+#define LPC32XX_EMC_DYCS0_BASE                  0x80000000
+#define LPC32XX_EMC_DYCS1_BASE                  0xA0000000
+
+/*
+ * Clock and crystal information
+ */
+#define LPC32XX_MAIN_OSC_FREQ                   13000000
+#define LPC32XX_CLOCK_OSC_FREQ                  32768
+
+/*
+ * Clock and Power control register offsets
+ */
+#define _PMREG(x)                               io_p2v(LPC32XX_CLK_PM_BASE +\
+                                                (x))
+#define LPC32XX_CLKPWR_DEBUG_CTRL               _PMREG(0x000)
+#define LPC32XX_CLKPWR_BOOTMAP                  _PMREG(0x014)
+#define LPC32XX_CLKPWR_P01_ER                   _PMREG(0x018)
+#define LPC32XX_CLKPWR_USBCLK_PDIV              _PMREG(0x01C)
+#define LPC32XX_CLKPWR_INT_ER                   _PMREG(0x020)
+#define LPC32XX_CLKPWR_INT_RS                   _PMREG(0x024)
+#define LPC32XX_CLKPWR_INT_SR                   _PMREG(0x028)
+#define LPC32XX_CLKPWR_INT_AP                   _PMREG(0x02C)
+#define LPC32XX_CLKPWR_PIN_ER                   _PMREG(0x030)
+#define LPC32XX_CLKPWR_PIN_RS                   _PMREG(0x034)
+#define LPC32XX_CLKPWR_PIN_SR                   _PMREG(0x038)
+#define LPC32XX_CLKPWR_PIN_AP                   _PMREG(0x03C)
+#define LPC32XX_CLKPWR_HCLK_DIV                 _PMREG(0x040)
+#define LPC32XX_CLKPWR_PWR_CTRL                 _PMREG(0x044)
+#define LPC32XX_CLKPWR_PLL397_CTRL              _PMREG(0x048)
+#define LPC32XX_CLKPWR_MAIN_OSC_CTRL            _PMREG(0x04C)
+#define LPC32XX_CLKPWR_SYSCLK_CTRL              _PMREG(0x050)
+#define LPC32XX_CLKPWR_LCDCLK_CTRL              _PMREG(0x054)
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL             _PMREG(0x058)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1           _PMREG(0x060)
+#define LPC32XX_CLKPWR_USB_CTRL                 _PMREG(0x064)
+#define LPC32XX_CLKPWR_SDRAMCLK_CTRL            _PMREG(0x068)
+#define LPC32XX_CLKPWR_DDR_LAP_NOM              _PMREG(0x06C)
+#define LPC32XX_CLKPWR_DDR_LAP_COUNT            _PMREG(0x070)
+#define LPC32XX_CLKPWR_DDR_LAP_DELAY            _PMREG(0x074)
+#define LPC32XX_CLKPWR_SSP_CLK_CTRL             _PMREG(0x078)
+#define LPC32XX_CLKPWR_I2S_CLK_CTRL             _PMREG(0x07C)
+#define LPC32XX_CLKPWR_MS_CTRL                  _PMREG(0x080)
+#define LPC32XX_CLKPWR_MACCLK_CTRL              _PMREG(0x090)
+#define LPC32XX_CLKPWR_TEST_CLK_SEL             _PMREG(0x0A4)
+#define LPC32XX_CLKPWR_SFW_INT                  _PMREG(0x0A8)
+#define LPC32XX_CLKPWR_I2C_CLK_CTRL             _PMREG(0x0AC)
+#define LPC32XX_CLKPWR_KEY_CLK_CTRL             _PMREG(0x0B0)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL             _PMREG(0x0B4)
+#define LPC32XX_CLKPWR_PWM_CLK_CTRL             _PMREG(0x0B8)
+#define LPC32XX_CLKPWR_TIMER_CLK_CTRL           _PMREG(0x0BC)
+#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1   _PMREG(0x0C0)
+#define LPC32XX_CLKPWR_SPI_CLK_CTRL             _PMREG(0x0C4)
+#define LPC32XX_CLKPWR_NAND_CLK_CTRL            _PMREG(0x0C8)
+#define LPC32XX_CLKPWR_UART3_CLK_CTRL           _PMREG(0x0D0)
+#define LPC32XX_CLKPWR_UART4_CLK_CTRL           _PMREG(0x0D4)
+#define LPC32XX_CLKPWR_UART5_CLK_CTRL           _PMREG(0x0D8)
+#define LPC32XX_CLKPWR_UART6_CLK_CTRL           _PMREG(0x0DC)
+#define LPC32XX_CLKPWR_IRDA_CLK_CTRL            _PMREG(0x0E0)
+#define LPC32XX_CLKPWR_UART_CLK_CTRL            _PMREG(0x0E4)
+#define LPC32XX_CLKPWR_DMA_CLK_CTRL             _PMREG(0x0E8)
+#define LPC32XX_CLKPWR_AUTOCLOCK                _PMREG(0x0EC)
+#define LPC32XX_CLKPWR_DEVID(x)                 _PMREG(0x130 + (x))
+
+/*
+ * clkpwr_debug_ctrl register definitions
+*/
+#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT     _BIT(4)
+
+/*
+ * clkpwr_bootmap register definitions
+ */
+#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT          _BIT(1)
+
+/*
+ * clkpwr_start_gpio register bit definitions
+ */
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT       _BIT(31)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT       _BIT(30)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT       _BIT(29)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT       _BIT(28)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT       _BIT(27)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT       _BIT(26)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT       _BIT(25)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT       _BIT(24)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT       _BIT(23)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT       _BIT(22)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT       _BIT(21)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT       _BIT(20)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT       _BIT(19)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT       _BIT(18)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT        _BIT(17)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT        _BIT(16)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT        _BIT(15)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT        _BIT(14)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT        _BIT(13)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT        _BIT(12)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT        _BIT(11)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT        _BIT(10)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT        _BIT(9)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT        _BIT(8)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT        _BIT(7)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT        _BIT(6)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT        _BIT(5)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT        _BIT(4)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT        _BIT(3)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT        _BIT(2)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT        _BIT(1)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT        _BIT(0)
+
+/*
+ * clkpwr_usbclk_pdiv register definitions
+ */
+#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK         0xF
+
+/*
+ * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
+ * clkpwr_start_pol_int, register bit definitions
+ */
+#define LPC32XX_CLKPWR_INTSRC_ADC_BIT           _BIT(31)
+#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT          _BIT(30)
+#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT        _BIT(29)
+#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT  _BIT(26)
+#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT       _BIT(25)
+#define LPC32XX_CLKPWR_INTSRC_RTC_BIT           _BIT(24)
+#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT    _BIT(23)
+#define LPC32XX_CLKPWR_INTSRC_USB_BIT           _BIT(22)
+#define LPC32XX_CLKPWR_INTSRC_I2C_BIT           _BIT(21)
+#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT   _BIT(20)
+#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT     _BIT(19)
+#define LPC32XX_CLKPWR_INTSRC_KEY_BIT           _BIT(16)
+#define LPC32XX_CLKPWR_INTSRC_MAC_BIT           _BIT(7)
+#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT          _BIT(6)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT       _BIT(5)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT       _BIT(4)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT       _BIT(3)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT       _BIT(2)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT       _BIT(1)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT       _BIT(0)
+
+/*
+ * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
+ * clkpwr_start_pol_pin register bit definitions
+ */
+#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT         _BIT(31)
+#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT       _BIT(30)
+#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT       _BIT(28)
+#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT         _BIT(26)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT        _BIT(25)
+#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT         _BIT(24)
+#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT       _BIT(23)
+#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT         _BIT(22)
+#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT         _BIT(21)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT     _BIT(18)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT     _BIT(17)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT        _BIT(16)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT        _BIT(15)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT        _BIT(14)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT        _BIT(13)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT        _BIT(12)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT        _BIT(11)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT        _BIT(10)
+#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT      _BIT(9)
+#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT    _BIT(8)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT        _BIT(7)
+#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT    _BIT(6)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT        _BIT(5)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT        _BIT(4)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT        _BIT(3)
+
+/*
+ * clkpwr_hclk_div register definitions
+ */
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP      (0x0 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM      (0x1 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF      (0x2 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n)      (((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n)      ((n) & 0x3)
+
+/*
+ * clkpwr_pwr_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK          _BIT(10)
+#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH          _BIT(9)
+#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH      _BIT(8)
+#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH     _BIT(7)
+#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT       _BIT(5)
+#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT       _BIT(4)
+#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN         _BIT(3)
+#define LPC32XX_CLKPWR_SELECT_RUN_MODE          _BIT(2)
+#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN         _BIT(1)
+#define LPC32XX_CLKPWR_STOP_MODE_CTRL           _BIT(0)
+
+/*
+ * clkpwr_pll397_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS        _BIT(10)
+#define LPC32XX_CLKPWR_PLL397_BYPASS            _BIT(9)
+#define LPC32XX_CLKPWR_PLL397_BIAS_NORM         0x000
+#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5        0x040
+#define LPC32XX_CLKPWR_PLL397_BIAS_N25          0x080
+#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5        0x0C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5        0x100
+#define LPC32XX_CLKPWR_PLL397_BIAS_P25          0x140
+#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5        0x180
+#define LPC32XX_CLKPWR_PLL397_BIAS_P50          0x1C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_MASK         0x1C0
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS       _BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS       _BIT(0)
+
+/*
+ * clkpwr_main_osc_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n)          (((n) & 0x7F) << 2)
+#define LPC32XX_CLKPWR_MOSC_CAP_MASK            (0x7F << 2)
+#define LPC32XX_CLKPWR_TEST_MODE                _BIT(1)
+#define LPC32XX_CLKPWR_MOSC_DISABLE             _BIT(0)
+
+/*
+ * clkpwr_sysclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n)       (((n) & 0x3FF) << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK          (0x3FF << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397        _BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX        _BIT(0)
+
+/*
+ * clkpwr_lcdclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12    0x000
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16    0x040
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15    0x080
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24    0x0C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M    0x100
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C    0x140
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M   0x180
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C   0x1C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK      0x01C0
+#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN           0x020
+#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n)    ((n - 1) & 0x1F)
+#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK       0x001F
+
+/*
+ * clkpwr_hclkpll_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP         _BIT(16)
+#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS       _BIT(15)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS   _BIT(14)
+#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK    _BIT(13)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n)  (((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n)  (((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n)          (((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS          _BIT(0)
+
+/*
+ * clkpwr_adc_clk_ctrl_1 register definitions
+ */
+#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n)        (((n) & 0xFF) << 0)
+#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL        _BIT(8)
+
+/*
+ * clkpwr_usb_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN          _BIT(24)
+#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN        _BIT(23)
+#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN       _BIT(22)
+#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN      _BIT(21)
+#define LPC32XX_CLKPWR_USBCTRL_PU_ADD           (0x0 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER       (0x1 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_PD_ADD           (0x3 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2          _BIT(18)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1          _BIT(17)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP        _BIT(16)
+#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS       _BIT(15)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS   _BIT(14)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK    _BIT(13)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n)  (((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n)  (((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n)    (((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_STS          _BIT(0)
+
+/*
+ * clkpwr_sdramclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK      _BIT(22)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW          _BIT(21)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT      _BIT(20)
+#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET      _BIT(19)
+#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n)       (((n) & 0x1F) << 14)
+#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS      _BIT(13)
+#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n)      (((n) & 0x7) << 10)
+#define LPC32XX_CLKPWR_SDRCLK_USE_CAL           _BIT(9)
+#define LPC32XX_CLKPWR_SDRCLK_DO_CAL            _BIT(8)
+#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC        _BIT(7)
+#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n)        (((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_SDRCLK_USE_DDR           _BIT(1)
+#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS           _BIT(0)
+
+/*
+ * clkpwr_ssp_blk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX       _BIT(5)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX       _BIT(4)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX       _BIT(3)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX       _BIT(2)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN       _BIT(1)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN       _BIT(0)
+
+/*
+ * clkpwr_i2s_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX   _BIT(6)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX   _BIT(5)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA     _BIT(4)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX   _BIT(3)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX   _BIT(2)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN       _BIT(1)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN       _BIT(0)
+
+/*
+ * clkpwr_ms_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS     _BIT(10)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN       _BIT(9)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS       _BIT(8)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS        _BIT(7)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS        _BIT(6)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN         _BIT(5)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n)     ((n) & 0xF)
+
+/*
+ * clkpwr_macclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS      0x00
+#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS     0x08
+#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS    0x18
+#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK         0x18
+#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN        _BIT(2)
+#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN       _BIT(1)
+#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN        _BIT(0)
+
+/*
+ * clkpwr_test_clk_sel register definitions
+ */
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK      (0x0 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC         (0x1 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC        (0x2 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK        (0x3 << 5)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN      _BIT(4)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK        (0x0 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK      (0x1 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK      (0x2 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC        (0x5 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397      (0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK        (0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN      _BIT(0)
+
+/*
+ * clkpwr_sw_int register definitions
+ */
+#define LPC32XX_CLKPWR_SW_INT(n)                (_BIT(0) | (((n) & 0x7F) << 1))
+#define LPC32XX_CLKPWR_SW_GET_ARG(n)            (((n) & 0xFE) >> 1)
+
+/*
+ * clkpwr_i2c_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE    _BIT(4)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE      _BIT(3)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE      _BIT(2)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN        _BIT(1)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN        _BIT(0)
+
+/*
+ * clkpwr_key_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN        0x1
+
+/*
+ * clkpwr_adc_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN      0x1
+
+/*
+ * clkpwr_pwm_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n)       (((n) & 0xF) << 8)
+#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n)       (((n) & 0xF) << 4)
+#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK      0x8
+#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN        0x4
+#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK      0x2
+#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN        0x1
+
+/*
+ * clkpwr_timer_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN        0x2
+#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN           0x1
+
+/*
+ * clkpwr_timers_pwms_clk_ctrl_1 register definitions
+ */
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN      0x20
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN      0x10
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN      0x08
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN      0x04
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN        0x02
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN        0x01
+
+/*
+ * clkpwr_spi_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO     0x80
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK       0x40
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI2          0x20
+#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN        0x10
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO     0x08
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK       0x04
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI1          0x02
+#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN        0x01
+
+/*
+ * clkpwr_nand_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC       0x20
+#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB          0x10
+#define LPC32XX_CLKPWR_NANDCLK_DMA_INT          0x08
+#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC          0x04
+#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN        0x02
+#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN        0x01
+
+/*
+ * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
+ * and clkpwr_uart6_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_UART_Y_DIV(y)            ((y) & 0xFF)
+#define LPC32XX_CLKPWR_UART_X_DIV(x)            (((x) & 0xFF) << 8)
+#define LPC32XX_CLKPWR_UART_USE_HCLK            _BIT(16)
+
+/*
+ * clkpwr_irda_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_IRDA_Y_DIV(y)            ((y) & 0xFF)
+#define LPC32XX_CLKPWR_IRDA_X_DIV(x)            (((x) & 0xFF) << 8)
+
+/*
+ * clkpwr_uart_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN     _BIT(3)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN     _BIT(2)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN     _BIT(1)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN     _BIT(0)
+
+/*
+ * clkpwr_dmaclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN        0x1
+
+/*
+ * clkpwr_autoclock register definitions
+ */
+#define LPC32XX_CLKPWR_AUTOCLK_USB_EN           0x40
+#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN          0x02
+#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN          0x01
+
+/*
+ * Interrupt controller register offsets
+ */
+#define LPC32XX_INTC_MASK(x)                    io_p2v((x) + 0x00)
+#define LPC32XX_INTC_RAW_STAT(x)                io_p2v((x) + 0x04)
+#define LPC32XX_INTC_STAT(x)                    io_p2v((x) + 0x08)
+#define LPC32XX_INTC_POLAR(x)                   io_p2v((x) + 0x0C)
+#define LPC32XX_INTC_ACT_TYPE(x)                io_p2v((x) + 0x10)
+#define LPC32XX_INTC_TYPE(x)                    io_p2v((x) + 0x14)
+
+/*
+ * Timer/counter register offsets
+ */
+#define LCP32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
+#define LCP32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
+#define LCP32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
+#define LCP32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
+#define LCP32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
+#define LCP32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
+#define LCP32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
+#define LCP32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
+#define LCP32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
+#define LCP32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
+#define LCP32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
+#define LCP32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
+#define LCP32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
+#define LCP32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
+#define LCP32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
+#define LCP32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
+#define LCP32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
+
+/*
+ * ir register definitions
+ */
+#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
+#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
+
+/*
+ * tcr register definitions
+ */
+#define LCP32XX_TIMER_CNTR_TCR_EN               0x1
+#define LCP32XX_TIMER_CNTR_TCR_RESET            0x2
+
+/*
+ * mcr register definitions
+ */
+#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
+#define LCP32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
+#define LCP32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
+
+/*
+ * Standard UART register offsets
+ */
+#define LPC32XX_UART_DLL_FIFO(x)                io_p2v((x) + 0x00)
+#define LPC32XX_UART_DLM_IER(x)                 io_p2v((x) + 0x04)
+#define LPC32XX_UART_IIR_FCR(x)                 io_p2v((x) + 0x08)
+#define LPC32XX_UART_LCR(x)                     io_p2v((x) + 0x0C)
+#define LPC32XX_UART_MODEM_CTRL(x)              io_p2v((x) + 0x10)
+#define LPC32XX_UART_LSR(x)                     io_p2v((x) + 0x14)
+#define LPC32XX_UART_MODEM_STATUS(x)            io_p2v((x) + 0x18)
+#define LPC32XX_UART_RXLEV(x)                   io_p2v((x) + 0x1C)
+
+/*
+ * UART control structure offsets
+ */
+#define _UCREG(x)                               io_p2v(\
+                                                LPC32XX_UART_CTRL_BASE + (x))
+#define LPC32XX_UARTCTL_CTRL                    _UCREG(0x00)
+#define LPC32XX_UARTCTL_CLKMODE                 _UCREG(0x04)
+#define LPC32XX_UARTCTL_CLOOP                   _UCREG(0x08)
+
+/*
+ * ctrl register definitions
+ */
+#define LPC32XX_UART_U3_MD_CTRL_EN              _BIT(11)
+#define LPC32XX_UART_IRRX6_INV_EN               _BIT(10)
+#define LPC32XX_UART_HDPX_EN                    _BIT(9)
+#define LPC32XX_UART_UART6_IRDAMOD_BYPASS       _BIT(5)
+#define LPC32XX_RT_IRTX6_INV_EN                 _BIT(4)
+#define LPC32XX_RT_IRTX6_INV_MIR_EN             _BIT(3)
+#define LPC32XX_RT_RX_IRPULSE_3_16_115K         _BIT(2)
+#define LPC32XX_RT_TX_IRPULSE_3_16_115K         _BIT(1)
+#define LPC32XX_UART_U5_ROUTE_TO_USB            _BIT(0)
+
+/*
+ * clkmode register definitions
+ */
+#define LPC32XX_UART_ENABLED_CLOCKS(n)          (((n) >> 16) & 0x7F)
+#define LPC32XX_UART_ENABLED_CLOCK(n, u)        (((n) >> (16 + (u))) & 0x1)
+#define LPC32XX_UART_ENABLED_CLKS_ANY           _BIT(14)
+#define LPC32XX_UART_CLKMODE_OFF                0x0
+#define LPC32XX_UART_CLKMODE_ON                 0x1
+#define LPC32XX_UART_CLKMODE_AUTO               0x2
+#define LPC32XX_UART_CLKMODE_MASK(u)            (0x3 << ((((u) - 3) * 2) + 4))
+#define LPC32XX_UART_CLKMODE_LOAD(m, u)         ((m) << ((((u) - 3) * 2) + 4))
+
+/*
+ * GPIO Module Register offsets
+ */
+#define _GPREG(x)                               io_p2v(LPC32XX_GPIO_BASE + (x))
+#define LPC32XX_GPIO_P_MUX_SET                  _GPREG(0x100)
+#define LPC32XX_GPIO_P_MUX_CLR                  _GPREG(0x104)
+#define LPC32XX_GPIO_P_MUX_STATE                _GPREG(0x108)
+#define LPC32XX_GPIO_P3_MUX_SET                 _GPREG(0x110)
+#define LPC32XX_GPIO_P3_MUX_CLR                 _GPREG(0x114)
+#define LPC32XX_GPIO_P3_MUX_STATE               _GPREG(0x118)
+#define LPC32XX_GPIO_P0_MUX_SET                 _GPREG(0x120)
+#define LPC32XX_GPIO_P0_MUX_CLR                 _GPREG(0x124)
+#define LPC32XX_GPIO_P0_MUX_STATE               _GPREG(0x128)
+#define LPC32XX_GPIO_P1_MUX_SET                 _GPREG(0x130)
+#define LPC32XX_GPIO_P1_MUX_CLR                 _GPREG(0x134)
+#define LPC32XX_GPIO_P1_MUX_STATE               _GPREG(0x138)
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
new file mode 100644
index 000000000000..df3b0dea4d7b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/system.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        extern void lpc32xx_watchdog_reset(void);
+
+        switch (mode) {
+        case 's':
+        case 'h':
+                printk(KERN_CRIT "RESET: Rebooting system\n");
+
+                /* Disable interrupts */
+                local_irq_disable();
+
+                lpc32xx_watchdog_reset();
+                break;
+
+        default:
+                /* Do nothing */
+                break;
+        }
+
+        /* Wait for watchdog to reset system */
+        while (1)
+                ;
+}
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-lpc32xx/include/mach/timex.h
new file mode 100644
index 000000000000..8d4066b16b3f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/timex.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/timex.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/*
+ * Rate in Hz of the main system oscillator. This value should match
+ * the value 'MAIN_OSC_FREQ' in platform.h
+ */
+#define CLOCK_TICK_RATE 13000000
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c142487d299a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/uncompress.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
+#define __ASM_ARM_ARCH_UNCOMPRESS_H
+
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+/*
+ * Uncompress output is hardcoded to standard UART 5
+ */
+
+#define UART_FIFO_CTL_TX_RESET  (1 << 2)
+#define UART_STATUS_TX_MT       (1 << 6)
+
+#define _UARTREG(x)             (void __iomem *)(LPC32XX_UART5_BASE + (x))
+
+#define LPC32XX_UART_DLLFIFO_O  0x00
+#define LPC32XX_UART_IIRFCR_O   0x08
+#define LPC32XX_UART_LSR_O      0x14
+
+static inline void putc(int ch)
+{
+        /* Wait for transmit FIFO to empty */
+        while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
+                UART_STATUS_TX_MT) == 0)
+                ;
+
+        __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
+}
+
+static inline void flush(void)
+{
+        __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
+                UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
+}
+
+/* NULL functions; we don't presently need them */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..d1d936c7236d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END     0xF0000000
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
new file mode 100644
index 000000000000..bd0df26c415b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -0,0 +1,432 @@
+/*
+ * arch/arm/mach-lpc32xx/irq.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Default value representing the Activation polarity of all internal
+ * interrupt sources
+ */
+#define MIC_APR_DEFAULT         0x3FF0EFE0
+#define SIC1_APR_DEFAULT        0xFBD27186
+#define SIC2_APR_DEFAULT        0x801810C0
+
+/*
+ * Default value representing the Activation Type of all internal
+ * interrupt sources. All are level sensitive.
+ */
+#define MIC_ATR_DEFAULT         0x00000000
+#define SIC1_ATR_DEFAULT        0x00026000
+#define SIC2_ATR_DEFAULT        0x00000000
+
+struct lpc32xx_event_group_regs {
+        void __iomem *enab_reg;
+        void __iomem *edge_reg;
+        void __iomem *maskstat_reg;
+        void __iomem *rawstat_reg;
+};
+
+static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
+        .enab_reg = LPC32XX_CLKPWR_INT_ER,
+        .edge_reg = LPC32XX_CLKPWR_INT_AP,
+        .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
+        .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
+};
+
+static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
+        .enab_reg = LPC32XX_CLKPWR_PIN_ER,
+        .edge_reg = LPC32XX_CLKPWR_PIN_AP,
+        .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
+        .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
+};
+
+struct lpc32xx_event_info {
+        const struct lpc32xx_event_group_regs *event_group;
+        u32 mask;
+};
+
+/*
+ * Maps an IRQ number to and event mask and register
+ */
+static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
+        [IRQ_LPC32XX_GPI_08] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
+        },
+        [IRQ_LPC32XX_GPI_09] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
+        },
+        [IRQ_LPC32XX_GPI_19] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
+        },
+        [IRQ_LPC32XX_GPI_07] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
+        },
+        [IRQ_LPC32XX_GPI_00] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
+        },
+        [IRQ_LPC32XX_GPI_01] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
+        },
+        [IRQ_LPC32XX_GPI_02] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
+        },
+        [IRQ_LPC32XX_GPI_03] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
+        },
+        [IRQ_LPC32XX_GPI_04] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
+        },
+        [IRQ_LPC32XX_GPI_05] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
+        },
+        [IRQ_LPC32XX_GPI_06] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_00] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_01] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_02] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_03] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_04] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_05] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
+        },
+        [IRQ_LPC32XX_KEY] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
+        },
+        [IRQ_LPC32XX_USB_OTG_ATX] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
+        },
+        [IRQ_LPC32XX_USB_HOST] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
+        },
+        [IRQ_LPC32XX_RTC] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
+        },
+        [IRQ_LPC32XX_MSTIMER] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
+        },
+        [IRQ_LPC32XX_TS_AUX] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
+        },
+        [IRQ_LPC32XX_TS_P] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
+        },
+        [IRQ_LPC32XX_TS_IRQ] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
+        },
+};
+
+static void get_controller(unsigned int irq, unsigned int *base,
+        unsigned int *irqbit)
+{
+        if (irq < 32) {
+                *base = LPC32XX_MIC_BASE;
+                *irqbit = 1 << irq;
+        } else if (irq < 64) {
+                *base = LPC32XX_SIC1_BASE;
+                *irqbit = 1 << (irq - 32);
+        } else {
+                *base = LPC32XX_SIC2_BASE;
+                *irqbit = 1 << (irq - 64);
+        }
+}
+
+static void lpc32xx_mask_irq(unsigned int irq)
+{
+        unsigned int reg, ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
+        __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
+}
+
+static void lpc32xx_unmask_irq(unsigned int irq)
+{
+        unsigned int reg, ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
+        __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
+}
+
+static void lpc32xx_ack_irq(unsigned int irq)
+{
+        unsigned int ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
+
+        /* Also need to clear pending wake event */
+        if (lpc32xx_events[irq].mask != 0)
+                __raw_writel(lpc32xx_events[irq].mask,
+                        lpc32xx_events[irq].event_group->rawstat_reg);
+}
+
+static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
+        int use_edge)
+{
+        unsigned int reg, ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        /* Activation level, high or low */
+        reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
+        if (use_high_level)
+                reg |= mask;
+        else
+                reg &= ~mask;
+        __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
+
+        /* Activation type, edge or level */
+        reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
+        if (use_edge)
+                reg |= mask;
+        else
+                reg &= ~mask;
+        __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
+
+        /* Use same polarity for the wake events */
+        if (lpc32xx_events[irq].mask != 0) {
+                reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
+
+                if (use_high_level)
+                        reg |= lpc32xx_events[irq].mask;
+                else
+                        reg &= ~lpc32xx_events[irq].mask;
+
+                __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
+        }
+}
+
+static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
+{
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                /* Rising edge sensitive */
+                __lpc32xx_set_irq_type(irq, 1, 1);
+                break;
+
+        case IRQ_TYPE_EDGE_FALLING:
+                /* Falling edge sensitive */
+                __lpc32xx_set_irq_type(irq, 0, 1);
+                break;
+
+        case IRQ_TYPE_LEVEL_LOW:
+                /* Low level sensitive */
+                __lpc32xx_set_irq_type(irq, 0, 0);
+                break;
+
+        case IRQ_TYPE_LEVEL_HIGH:
+                /* High level sensitive */
+                __lpc32xx_set_irq_type(irq, 1, 0);
+                break;
+
+        /* Other modes are not supported */
+        default:
+                return -EINVAL;
+        }
+
+        /* Ok to use the level handler for all types */
+        set_irq_handler(irq, handle_level_irq);
+
+        return 0;
+}
+
+static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
+{
+        unsigned long eventreg;
+
+        if (lpc32xx_events[irqno].mask != 0) {
+                eventreg = __raw_readl(lpc32xx_events[irqno].
+                        event_group->enab_reg);
+
+                if (state)
+                        eventreg |= lpc32xx_events[irqno].mask;
+                else
+                        eventreg &= ~lpc32xx_events[irqno].mask;
+
+                __raw_writel(eventreg,
+                        lpc32xx_events[irqno].event_group->enab_reg);
+
+                return 0;
+        }
+
+        /* Clear event */
+        __raw_writel(lpc32xx_events[irqno].mask,
+                lpc32xx_events[irqno].event_group->rawstat_reg);
+
+        return -ENODEV;
+}
+
+static void __init lpc32xx_set_default_mappings(unsigned int apr,
+        unsigned int atr, unsigned int offset)
+{
+        unsigned int i;
+
+        /* Set activation levels for each interrupt */
+        i = 0;
+        while (i < 32) {
+                __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
+                        ((atr >> i) & 0x1));
+                i++;
+        }
+}
+
+static struct irq_chip lpc32xx_irq_chip = {
+        .ack = lpc32xx_ack_irq,
+        .mask = lpc32xx_mask_irq,
+        .unmask = lpc32xx_unmask_irq,
+        .set_type = lpc32xx_set_irq_type,
+        .set_wake = lpc32xx_irq_wake
+};
+
+static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
+
+        while (ints != 0) {
+                int irqno = fls(ints) - 1;
+
+                ints &= ~(1 << irqno);
+
+                generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
+        }
+}
+
+static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
+
+        while (ints != 0) {
+                int irqno = fls(ints) - 1;
+
+                ints &= ~(1 << irqno);
+
+                generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
+        }
+}
+
+void __init lpc32xx_init_irq(void)
+{
+        unsigned int i;
+
+        /* Setup MIC */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
+        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
+        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
+
+        /* Setup SIC1 */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
+        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
+        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
+
+        /* Setup SIC2 */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
+        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
+        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
+
+        /* Configure supported IRQ's */
+        for (i = 0; i < NR_IRQS; i++) {
+                set_irq_chip(i, &lpc32xx_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+
+        /* Set default mappings */
+        lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
+        lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
+        lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
+
+        /* mask all interrupts except SUBIRQ */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
+
+        /* MIC SUBIRQx interrupts will route handling to the chain handlers */
+        set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
+        set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
+
+        /* Initially disable all wake events */
+        __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
+        __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
+        __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
+
+        /*
+         * Default wake activation polarities, all pin sources are low edge
+         * triggered
+         */
+        __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
+                LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
+                LPC32XX_CLKPWR_INTSRC_RTC_BIT,
+                LPC32XX_CLKPWR_INT_AP);
+        __raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
+
+        /* Clear latched wake event states */
+        __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
+                LPC32XX_CLKPWR_PIN_RS);
+        __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
+                LPC32XX_CLKPWR_INT_RS);
+}
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
new file mode 100644
index 000000000000..bc9a42da2145
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -0,0 +1,397 @@
+/*
+ * arch/arm/mach-lpc32xx/phy3250.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/amba/pl022.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Mapped GPIOLIB GPIOs
+ */
+#define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+#define LCD_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
+#define BKL_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
+
+/*
+ * AMBA LCD controller
+ */
+static struct clcd_panel conn_lcd_panel = {
+        .mode           = {
+                .name           = "QVGA portrait",
+                .refresh        = 60,
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = 191828,
+                .left_margin    = 22,
+                .right_margin   = 11,
+                .upper_margin   = 2,
+                .lower_margin   = 1,
+                .hsync_len      = 5,
+                .vsync_len      = 2,
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = (TIM2_IVS | TIM2_IHS),
+        .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
+                                CNTL_LCDBPP16_565),
+        .bpp            = 16,
+};
+#define PANEL_SIZE (3 * SZ_64K)
+
+static int lpc32xx_clcd_setup(struct clcd_fb *fb)
+{
+        dma_addr_t dma;
+
+        fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+                PANEL_SIZE, &dma, GFP_KERNEL);
+        if (!fb->fb.screen_base) {
+                printk(KERN_ERR "CLCD: unable to map framebuffer\n");
+                return -ENOMEM;
+        }
+
+        fb->fb.fix.smem_start = dma;
+        fb->fb.fix.smem_len = PANEL_SIZE;
+        fb->panel = &conn_lcd_panel;
+
+        if (gpio_request(LCD_POWER_GPIO, "LCD power"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        LCD_POWER_GPIO);
+        else if (gpio_direction_output(LCD_POWER_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        LCD_POWER_GPIO);
+
+        if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        BKL_POWER_GPIO);
+        else if (gpio_direction_output(BKL_POWER_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        BKL_POWER_GPIO);
+
+        return 0;
+}
+
+static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+        return dma_mmap_writecombine(&fb->dev->dev, vma,
+                fb->fb.screen_base, fb->fb.fix.smem_start,
+                fb->fb.fix.smem_len);
+}
+
+static void lpc32xx_clcd_remove(struct clcd_fb *fb)
+{
+        dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+                fb->fb.screen_base, fb->fb.fix.smem_start);
+}
+
+/*
+ * On some early LCD modules (1307.0), the backlight logic is inverted.
+ * For those board variants, swap the disable and enable states for
+ * BKL_POWER_GPIO.
+*/
+static void clcd_disable(struct clcd_fb *fb)
+{
+        gpio_set_value(BKL_POWER_GPIO, 0);
+        gpio_set_value(LCD_POWER_GPIO, 0);
+}
+
+static void clcd_enable(struct clcd_fb *fb)
+{
+        gpio_set_value(BKL_POWER_GPIO, 1);
+        gpio_set_value(LCD_POWER_GPIO, 1);
+}
+
+static struct clcd_board lpc32xx_clcd_data = {
+        .name           = "Phytec LCD",
+        .check          = clcdfb_check,
+        .decode         = clcdfb_decode,
+        .disable        = clcd_disable,
+        .enable         = clcd_enable,
+        .setup          = lpc32xx_clcd_setup,
+        .mmap           = lpc32xx_clcd_mmap,
+        .remove         = lpc32xx_clcd_remove,
+};
+
+static struct amba_device lpc32xx_clcd_device = {
+        .dev                            = {
+                .coherent_dma_mask      = ~0,
+                .init_name              = "dev:clcd",
+                .platform_data          = &lpc32xx_clcd_data,
+        },
+        .res                            = {
+                .start                  = LPC32XX_LCD_BASE,
+                .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
+                .flags                  = IORESOURCE_MEM,
+        },
+        .dma_mask                       = ~0,
+        .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
+};
+
+/*
+ * AMBA SSP (SPI)
+ */
+static void phy3250_spi_cs_set(u32 control)
+{
+        gpio_set_value(SPI0_CS_GPIO, (int) control);
+}
+
+static struct pl022_config_chip spi0_chip_info = {
+        .lbm                    = LOOPBACK_DISABLED,
+        .com_mode               = INTERRUPT_TRANSFER,
+        .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
+        .hierarchy              = SSP_MASTER,
+        .slave_tx_disable       = 0,
+        .endian_tx              = SSP_TX_LSB,
+        .endian_rx              = SSP_RX_LSB,
+        .data_size              = SSP_DATA_BITS_8,
+        .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
+        .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
+        .clk_phase              = SSP_CLK_FIRST_EDGE,
+        .clk_pol                = SSP_CLK_POL_IDLE_LOW,
+        .ctrl_len               = SSP_BITS_8,
+        .wait_state             = SSP_MWIRE_WAIT_ZERO,
+        .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
+        .cs_control             = phy3250_spi_cs_set,
+};
+
+static struct pl022_ssp_controller lpc32xx_ssp0_data = {
+        .bus_id                 = 0,
+        .num_chipselect         = 1,
+        .enable_dma             = 0,
+};
+
+static struct amba_device lpc32xx_ssp0_device = {
+        .dev                            = {
+                .coherent_dma_mask      = ~0,
+                .init_name              = "dev:ssp0",
+                .platform_data          = &lpc32xx_ssp0_data,
+        },
+        .res                            = {
+                .start                  = LPC32XX_SSP0_BASE,
+                .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
+                .flags                  = IORESOURCE_MEM,
+        },
+        .dma_mask                       = ~0,
+        .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
+};
+
+/* AT25 driver registration */
+static int __init phy3250_spi_board_register(void)
+{
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+        static struct spi_board_info info[] = {
+                {
+                        .modalias = "spidev",
+                        .max_speed_hz = 5000000,
+                        .bus_num = 0,
+                        .chip_select = 0,
+                        .controller_data = &spi0_chip_info,
+                },
+        };
+
+#else
+        static struct spi_eeprom eeprom = {
+                .name = "at25256a",
+                .byte_len = 0x8000,
+                .page_size = 64,
+                .flags = EE_ADDR2,
+        };
+
+        static struct spi_board_info info[] = {
+                {
+                        .modalias = "at25",
+                        .max_speed_hz = 5000000,
+                        .bus_num = 0,
+                        .chip_select = 0,
+                        .platform_data = &eeprom,
+                        .controller_data = &spi0_chip_info,
+                },
+        };
+#endif
+        return spi_register_board_info(info, ARRAY_SIZE(info));
+}
+arch_initcall(phy3250_spi_board_register);
+
+static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+static struct gpio_led phy_leds[] = {
+        {
+                .name                   = "led0",
+                .gpio                   = LED_GPIO,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+};
+
+static struct gpio_led_platform_data led_data = {
+        .leds = phy_leds,
+        .num_leds = ARRAY_SIZE(phy_leds),
+};
+
+static struct platform_device lpc32xx_gpio_led_device = {
+        .name                   = "leds-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &led_data,
+};
+
+static struct platform_device *phy3250_devs[] __initdata = {
+        &lpc32xx_i2c0_device,
+        &lpc32xx_i2c1_device,
+        &lpc32xx_i2c2_device,
+        &lpc32xx_watchdog_device,
+        &lpc32xx_gpio_led_device,
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        &lpc32xx_clcd_device,
+        &lpc32xx_ssp0_device,
+};
+
+/*
+ * Board specific functions
+ */
+static void __init phy3250_board_init(void)
+{
+        u32 tmp;
+        int i;
+
+        lpc32xx_gpio_init();
+
+        /* Register GPIOs used on this board */
+        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        SPI0_CS_GPIO);
+        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        SPI0_CS_GPIO);
+
+        /* Setup network interface for RMII mode */
+        tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
+        tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
+        tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
+        __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
+
+        /* Setup SLC NAND controller muxing */
+        __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
+                LPC32XX_CLKPWR_NAND_CLK_CTRL);
+
+        /* Setup LCD muxing to RGB565 */
+        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
+                ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
+                LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
+        tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
+        __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        /* Set up I2C pull levels */
+        tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
+        tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
+                LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
+        __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
+
+        /* Disable IrDA pulsing support on UART6 */
+        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+        tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
+        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
+        /* Enable DMA for I2S1 channel */
+        tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
+        tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
+        __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
+
+        lpc32xx_serial_init();
+
+        /*
+         * AMBA peripheral clocks need to be enabled prior to AMBA device
+         * detection or a data fault will occur, so enable the clocks
+         * here. However, we don't want to enable them if the peripheral
+         * isn't included in the image
+         */
+#ifdef CONFIG_FB_ARMCLCD
+        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+        __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
+                LPC32XX_CLKPWR_LCDCLK_CTRL);
+#endif
+#ifdef CONFIG_SPI_PL022
+        tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
+        __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
+                LPC32XX_CLKPWR_SSP_CLK_CTRL);
+#endif
+
+        platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+
+        /* Test clock needed for UDA1380 initial init */
+        __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
+                LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
+                LPC32XX_CLKPWR_TEST_CLK_SEL);
+
+        i2c_register_board_info(0, phy3250_i2c_board_info,
+                ARRAY_SIZE(phy3250_i2c_board_info));
+}
+
+static int __init lpc32xx_display_uid(void)
+{
+        u32 uid[4];
+
+        lpc32xx_get_uid(uid);
+
+        printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
+                uid[3], uid[2], uid[1], uid[0]);
+
+        return 1;
+}
+arch_initcall(lpc32xx_display_uid);
+
+MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
+        /* Maintainer: Kevin Wells, NXP Semiconductors */
+        .phys_io        = LPC32XX_UART5_BASE,
+        .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = lpc32xx_map_io,
+        .init_irq       = lpc32xx_init_irq,
+        .timer          = &lpc32xx_timer,
+        .init_machine   = phy3250_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
new file mode 100644
index 000000000000..a6e2aed9a49f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -0,0 +1,146 @@
+/*
+ * arch/arm/mach-lpc32xx/pm.c
+ *
+ * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
+ * Modified by Kevin Wells <kevin.wells@nxp.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * LPC32XX CPU and system power management
+ *
+ * The LCP32XX has three CPU modes for controlling system power: run,
+ * direct-run, and halt modes. When switching between halt and run modes,
+ * the CPU transistions through direct-run mode. For Linux, direct-run
+ * mode is not used in normal operation. Halt mode is used when the
+ * system is fully suspended.
+ *
+ * Run mode:
+ * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
+ * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
+ * the HCLK_PLL rate. Linux runs in this mode.
+ *
+ * Direct-run mode:
+ * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
+ * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
+ * source or the frequency of the main oscillator. In this mode, the
+ * HCLK_PLL can be safely enabled, changed, or disabled.
+ *
+ * Halt mode:
+ * SYSCLK is gated off and the CPU and system clocks are halted.
+ * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
+ * key scanner, etc.) still operate if enabled. In this state, an enabled
+ * system event (ie, GPIO state change, RTC match, key press, etc.) will
+ * wake the system up back into direct-run mode.
+ *
+ * DRAM refresh
+ * DRAM clocking and refresh are slightly different for systems with DDR
+ * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
+ * SDRAM will still be accessible in direct-run mode. In DDR based systems,
+ * a transistion to direct-run mode will stop all DDR accesses (no clocks).
+ * Because of this, the code to switch power modes and the code to enter
+ * and exit DRAM self-refresh modes must not be executed in DRAM. A small
+ * section of IRAM is used instead for this.
+ *
+ * Suspend is handled with the following logic:
+ *  Backup a small area of IRAM used for the suspend code
+ *  Copy suspend code to IRAM
+ *  Transfer control to code in IRAM
+ *  Places DRAMs in self-refresh mode
+ *  Enter direct-run mode
+ *  Save state of HCLK_PLL PLL
+ *  Disable HCLK_PLL PLL
+ *  Enter halt mode - CPU and buses will stop
+ *  System enters direct-run mode when an enabled event occurs
+ *  HCLK PLL state is restored
+ *  Run mode is entered
+ *  DRAMS are placed back into normal mode
+ *  Code execution returns from IRAM
+ *  IRAM code are used for suspend is restored
+ *  Suspend mode is exited
+ */
+
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+#include "clock.h"
+
+#define TEMP_IRAM_AREA  IO_ADDRESS(LPC32XX_IRAM_BASE)
+
+/*
+ * Both STANDBY and MEM suspend states are handled the same with no
+ * loss of CPU or memory state
+ */
+static int lpc32xx_pm_enter(suspend_state_t state)
+{
+        int (*lpc32xx_suspend_ptr) (void);
+        void *iram_swap_area;
+
+        /* Allocate some space for temporary IRAM storage */
+        iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
+        if (!iram_swap_area) {
+                printk(KERN_ERR
+                       "PM Suspend: cannot allocate memory to save portion "
+                        "of SRAM\n");
+                return -ENOMEM;
+        }
+
+        /* Backup a small area of IRAM used for the suspend code */
+        memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
+                lpc32xx_sys_suspend_sz);
+
+        /*
+         * Copy code to suspend system into IRAM. The suspend code
+         * needs to run from IRAM as DRAM may no longer be available
+         * when the PLL is stopped.
+         */
+        memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
+                lpc32xx_sys_suspend_sz);
+        flush_icache_range((unsigned long)TEMP_IRAM_AREA,
+                (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
+
+        /* Transfer to suspend code in IRAM */
+        lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
+        flush_cache_all();
+        (void) lpc32xx_suspend_ptr();
+
+        /* Restore original IRAM contents */
+        memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
+                lpc32xx_sys_suspend_sz);
+
+        kfree(iram_swap_area);
+
+        return 0;
+}
+
+static struct platform_suspend_ops lpc32xx_pm_ops = {
+        .valid  = suspend_valid_only_mem,
+        .enter  = lpc32xx_pm_enter,
+};
+
+#define EMC_DYN_MEM_CTRL_OFS 0x20
+#define EMC_SRMMC           (1 << 3)
+#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
+static int __init lpc32xx_pm_init(void)
+{
+        /*
+         * Setup SDRAM self-refresh clock to automatically disable o
+         * start of self-refresh. This only needs to be done once.
+         */
+        __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
+
+        suspend_set_ops(&lpc32xx_pm_ops);
+
+        return 0;
+}
+arch_initcall(lpc32xx_pm_init);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
new file mode 100644
index 000000000000..429cfdbb2b3d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -0,0 +1,190 @@
+/*
+ * arch/arm/mach-lpc32xx/serial.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+#define LPC32XX_SUART_FIFO_SIZE 64
+
+/* Standard 8250/16550 compatible serial ports */
+static struct plat_serial8250_port serial_std_platform_data[] = {
+#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART5_BASE),
+                .mapbase        = LPC32XX_UART5_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR5,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART3_BASE),
+                .mapbase        = LPC32XX_UART3_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR3,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART4_BASE),
+                .mapbase        = LPC32XX_UART4_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR4,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART6_BASE),
+                .mapbase        = LPC32XX_UART6_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR6,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+        { },
+};
+
+struct uartinit {
+        char *uart_ck_name;
+        u32 ck_mode_mask;
+        void __iomem *pdiv_clk_reg;
+};
+
+static struct uartinit uartinit_data[] __initdata = {
+#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
+        {
+                .uart_ck_name = "uart5_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
+        {
+                .uart_ck_name = "uart3_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
+        {
+                .uart_ck_name = "uart4_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
+        {
+                .uart_ck_name = "uart6_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
+        },
+#endif
+};
+
+static struct platform_device serial_std_platform_device = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = serial_std_platform_data,
+        },
+};
+
+static struct platform_device *lpc32xx_serial_devs[] __initdata = {
+        &serial_std_platform_device,
+};
+
+void __init lpc32xx_serial_init(void)
+{
+        u32 tmp, clkmodes = 0;
+        struct clk *clk;
+        unsigned int puart;
+        int i, j;
+
+        /* UART clocks are off, let clock driver manage them */
+        __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
+
+        for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
+                clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
+                if (!IS_ERR(clk)) {
+                        clk_enable(clk);
+                        serial_std_platform_data[i].uartclk =
+                                clk_get_rate(clk);
+                }
+
+                /* Fall back on main osc rate if clock rate return fails */
+                if (serial_std_platform_data[i].uartclk == 0)
+                        serial_std_platform_data[i].uartclk =
+                                LPC32XX_MAIN_OSC_FREQ;
+
+                /* Setup UART clock modes for all UARTs, disable autoclock */
+                clkmodes |= uartinit_data[i].ck_mode_mask;
+
+                /* pre-UART clock divider set to 1 */
+                __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
+        }
+
+        /* This needs to be done after all UART clocks are setup */
+        __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
+        for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
+                /* Force a flush of the RX FIFOs to work around a HW bug */
+                puart = serial_std_platform_data[i].mapbase;
+                __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
+                __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
+                j = LPC32XX_SUART_FIFO_SIZE;
+                while (j--)
+                        tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
+                __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
+        }
+
+        /* Disable UART5->USB transparent mode or USB won't work */
+        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+        tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
+        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
+        platform_add_devices(lpc32xx_serial_devs,
+                ARRAY_SIZE(lpc32xx_serial_devs));
+}
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
new file mode 100644
index 000000000000..374f9f07fe48
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -0,0 +1,151 @@
+/*
+ * arch/arm/mach-lpc32xx/suspend.S
+ *
+ * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
+ * Modified by Kevin Wells <kevin.wells@nxp.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+/* Using named register defines makes the code easier to follow */
+#define WORK1_REG                       r0
+#define WORK2_REG                       r1
+#define SAVED_HCLK_DIV_REG              r2
+#define SAVED_HCLK_PLL_REG              r3
+#define SAVED_DRAM_CLKCTRL_REG          r4
+#define SAVED_PWR_CTRL_REG              r5
+#define CLKPWRBASE_REG                  r6
+#define EMCBASE_REG                     r7
+
+#define LPC32XX_EMC_STATUS_OFFS         0x04
+#define LPC32XX_EMC_STATUS_BUSY         0x1
+#define LPC32XX_EMC_STATUS_SELF_RFSH    0x4
+
+#define LPC32XX_CLKPWR_PWR_CTRL_OFFS    0x44
+#define LPC32XX_CLKPWR_HCLK_DIV_OFFS    0x40
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
+
+#define CLKPWR_PCLK_DIV_MASK            0xFFFFFE7F
+
+        .text
+
+ENTRY(lpc32xx_sys_suspend)
+        @ Save a copy of the used registers in IRAM, r0 is corrupted
+        adr     r0, tmp_stack_end
+        stmfd   r0!, {r3 - r7, sp, lr}
+
+        @ Load a few common register addresses
+        adr     WORK1_REG, reg_bases
+        ldr     CLKPWRBASE_REG, [WORK1_REG, #0]
+        ldr     EMCBASE_REG, [WORK1_REG, #4]
+
+        ldr     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        orr     WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
+
+        @ Wait for SDRAM busy status to go busy and then idle
+        @ This guarantees a small windows where DRAM isn't busy
+1:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        bne     1b @ Branch while idle
+2:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        beq     2b @ Branch until idle
+
+        @ Setup self-refresh with support for manual exit of
+        @ self-refresh mode
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        orr     WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+        str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Wait for self-refresh acknowledge, clocks to the DRAM device
+        @ will automatically stop on start of self-refresh
+3:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+        cmp     WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+        bne     3b @ Branch until self-refresh mode starts
+
+        @ Enter direct-run mode from run mode
+        bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Safe disable of DRAM clock in EMC block, prevents DDR sync
+        @ issues on restart
+        ldr     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+        and     WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
+        str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+
+        @ Save HCLK PLL state and disable HCLK PLL
+        ldr     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+        bic     WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
+        str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+
+        @ Enter stop mode until an enabled event occurs
+        orr     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        .rept 9
+        nop
+        .endr
+
+        @ Clear stop status
+        bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
+
+        @ Restore original HCLK PLL value and wait for PLL lock
+        str     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+4:
+        ldr     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
+        bne     4b
+
+        @ Re-enter run mode with self-refresh flag cleared, but no DRAM
+        @ update yet. DRAM is still in self-refresh
+        str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Restore original DRAM clock mode to restore DRAM clocks
+        str     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+
+        @ Clear self-refresh mode
+        orr     WORK1_REG, SAVED_PWR_CTRL_REG,\
+                #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Wait for EMC to clear self-refresh mode
+5:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+        bne     5b @ Branch until self-refresh has exited
+
+        @ restore regs and return
+        adr     r0, tmp_stack
+        ldmfd   r0!, {r3 - r7, sp, pc}
+
+reg_bases:
+        .long   IO_ADDRESS(LPC32XX_CLK_PM_BASE)
+        .long   IO_ADDRESS(LPC32XX_EMC_BASE)
+
+tmp_stack:
+        .long   0, 0, 0, 0, 0, 0, 0
+tmp_stack_end:
+
+ENTRY(lpc32xx_sys_suspend_sz)
+        .word   . - lpc32xx_sys_suspend
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
new file mode 100644
index 000000000000..630dd4a74b26
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -0,0 +1,182 @@
+/*
+ * arch/arm/mach-lpc32xx/timer.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2009 - 2010 NXP Semiconductors
+ * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
+ *                    Ed Schouten <e.schouten@fontys.nl>
+ *                    Laurens Timmermans <l.timmermans@fontys.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/time.h>
+#include <linux/err.h>
+#include <linux/clockchips.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
+{
+        return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
+}
+
+static struct clocksource lpc32xx_clksrc = {
+        .name   = "lpc32xx_clksrc",
+        .shift  = 24,
+        .rating = 300,
+        .read   = lpc32xx_clksrc_read,
+        .mask   = CLOCKSOURCE_MASK(32),
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int lpc32xx_clkevt_next_event(unsigned long delta,
+    struct clock_event_device *dev)
+{
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+
+        return 0;
+}
+
+static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
+    struct clock_event_device *dev)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                WARN_ON(1);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                /*
+                 * Disable the timer. When using oneshot, we must also
+                 * disable the timer to wait for the first call to
+                 * set_next_event().
+                 */
+                __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+                break;
+
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device lpc32xx_clkevt = {
+        .name           = "lpc32xx_clkevt",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .rating         = 300,
+        .set_next_event = lpc32xx_clkevt_next_event,
+        .set_mode       = lpc32xx_clkevt_mode,
+};
+
+static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &lpc32xx_clkevt;
+
+        /* Clear match */
+        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction lpc32xx_timer_irq = {
+        .name           = "LPC32XX Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = lpc32xx_timer_interrupt,
+};
+
+/*
+ * The clock management driver isn't initialized at this point, so the
+ * clocks need to be enabled here manually and then tagged as used in
+ * the clock driver initialization
+ */
+static void __init lpc32xx_timer_init(void)
+{
+        u32 clkrate, pllreg;
+
+        /* Enable timer clock */
+        __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
+                LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
+                LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
+
+        /*
+         * The clock driver isn't initialized at this point. So determine if
+         * the SYSCLK is driven from the PLL397 or main oscillator and then use
+         * it to compute the PLL frequency and the PCLK divider to get the base
+         * timer rates. This rate is needed to compute the tick rate.
+         */
+        if (clk_is_sysclk_mainosc() != 0)
+                clkrate = LPC32XX_MAIN_OSC_FREQ;
+        else
+                clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
+
+        /* Get ARM HCLKPLL register and convert it into a frequency */
+        pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
+        clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
+
+        /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
+        clkrate = clkrate / clk_get_pclk_div();
+
+        /* Initial timer setup */
+        __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+        __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
+                LCP32XX_TIMER_CNTR_MCR_STOP(0) |
+                LCP32XX_TIMER_CNTR_MCR_RESET(0),
+                LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+
+        /* Setup tick interrupt */
+        setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
+
+        /* Setup the clockevent structure. */
+        lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
+                lpc32xx_clkevt.shift);
+        lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
+                &lpc32xx_clkevt);
+        lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
+                &lpc32xx_clkevt) + 1;
+        lpc32xx_clkevt.cpumask = cpumask_of(0);
+        clockevents_register_device(&lpc32xx_clkevt);
+
+        /* Use timer1 as clock source. */
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+        lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
+                lpc32xx_clksrc.shift);
+        clocksource_register(&lpc32xx_clksrc);
+}
+
+struct sys_timer lpc32xx_timer = {
+        .init           = &lpc32xx_timer_init,
+};
+
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 66677f0acaed..7ff8020d4d24 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 
-obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o
+obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
index af5e85b91d02..f060a3959a75 100644
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ b/arch/arm/mach-msm/acpuclock-arm11.c
@@ -98,7 +98,7 @@ struct clkctl_acpu_speed {
 
 /*
  * ACPU speed table. Complete table is shown but certain speeds are commented
- * out to optimized speed switching. Initalize loops_per_jiffy to 0.
+ * out to optimized speed switching. Initialize loops_per_jiffy to 0.
  *
  * Table stepping up/down is optimized for 256mhz jumps while staying on the
  * same PLL.
@@ -494,7 +494,7 @@ uint32_t acpuclk_get_switch_time(void)
  * Clock driver initialization
  *---------------------------------------------------------------------------*/
 
-/* Initalize the lpj field in the acpu_freq_tbl. */
+/* Initialize the lpj field in the acpu_freq_tbl. */
 static void __init lpj_init(void)
 {
         int i;
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
new file mode 100644
index 000000000000..523d213bf79e
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -0,0 +1,112 @@
+/*
+ * linux/arch/arm/mach-msm/gpio.c
+ *
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2008 Google, Inc.
+ * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include "board-trout.h"
+
+struct msm_gpio_chip {
+        struct gpio_chip        chip;
+        void __iomem            *reg;   /* Base of register bank */
+        u8                      shadow;
+};
+
+#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
+
+static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+        unsigned mask = 1 << offset;
+
+        return !!(readb(msm_gpio->reg) & mask);
+}
+
+static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+        unsigned mask = 1 << offset;
+
+        if (val)
+                msm_gpio->shadow |= mask;
+        else
+                msm_gpio->shadow &= ~mask;
+
+        writeb(msm_gpio->shadow, msm_gpio->reg);
+}
+
+static int msm_gpiolib_direction_input(struct gpio_chip *chip,
+                                        unsigned offset)
+{
+        msm_gpiolib_set(chip, offset, 0);
+        return 0;
+}
+
+static int msm_gpiolib_direction_output(struct gpio_chip *chip,
+                                         unsigned offset, int val)
+{
+        msm_gpiolib_set(chip, offset, val);
+        return 0;
+}
+
+#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val)           \
+        {                                                               \
+                .chip = {                                               \
+                        .label            = name,                       \
+                        .direction_input  = msm_gpiolib_direction_input,\
+                        .direction_output = msm_gpiolib_direction_output, \
+                        .get              = msm_gpiolib_get,            \
+                        .set              = msm_gpiolib_set,            \
+                        .base             = base_gpio,                  \
+                        .ngpio            = 8,                          \
+                },                                                      \
+                .reg = (void *) reg_num + TROUT_CPLD_BASE,              \
+                .shadow = shadow_val,                                   \
+        }
+
+static struct msm_gpio_chip msm_gpio_banks[] = {
+#if defined(CONFIG_MSM_DEBUG_UART1)
+        /* H2W pins <-> UART1 */
+        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x40),
+#else
+        /* H2W pins <-> UART3, Bluetooth <-> UART1 */
+        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x80),
+#endif
+        /* I2C pull */
+        TROUT_GPIO_BANK("MISC3", 0x02,   TROUT_GPIO_MISC3_BASE, 0x04),
+        TROUT_GPIO_BANK("MISC4", 0x04,   TROUT_GPIO_MISC4_BASE, 0),
+        /* mmdi 32k en */
+        TROUT_GPIO_BANK("MISC5", 0x06,   TROUT_GPIO_MISC5_BASE, 0x04),
+        TROUT_GPIO_BANK("INT2", 0x08,    TROUT_GPIO_INT2_BASE,  0),
+        TROUT_GPIO_BANK("MISC1", 0x0a,   TROUT_GPIO_MISC1_BASE, 0),
+        TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
+};
+
+/*
+ * Called from the processor-specific init to enable GPIO pin support.
+ */
+int __init trout_init_gpio(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
+                gpiochip_add(&msm_gpio_banks[i].chip);
+
+        return 0;
+}
+
+postcore_initcall(trout_init_gpio);
+
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index dca5a5f062dc..e69a1502e4e8 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -50,7 +50,6 @@ static void __init trout_fixup(struct machine_desc *desc, struct tag *tags,
 {
         mi->nr_banks = 1;
         mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
         mi->bank[0].size = (101*1024*1024);
 }
 
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 4f345a5a0a61..651851c3e1dd 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -1,5 +1,162 @@
+/* linux/arch/arm/mach-msm/board-trout.h
+** Author: Brian Swetland <swetland@google.com>
+*/
+#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+
+#include <mach/board.h>
+
+#define MSM_SMI_BASE            0x00000000
+#define MSM_SMI_SIZE            0x00800000
+
+#define MSM_EBI_BASE            0x10000000
+#define MSM_EBI_SIZE            0x06e00000
+
+#define MSM_PMEM_GPU0_BASE      0x00000000
+#define MSM_PMEM_GPU0_SIZE      0x00700000
+
+#define MSM_PMEM_MDP_BASE       0x02000000
+#define MSM_PMEM_MDP_SIZE       0x00800000
+
+#define MSM_PMEM_ADSP_BASE      0x02800000
+#define MSM_PMEM_ADSP_SIZE      0x00800000
+
+#define MSM_PMEM_CAMERA_BASE    0x03000000
+#define MSM_PMEM_CAMERA_SIZE    0x00800000
+
+#define MSM_FB_BASE             0x03800000
+#define MSM_FB_SIZE             0x00100000
+
+#define MSM_LINUX_BASE          MSM_EBI_BASE
+#define MSM_LINUX_SIZE          0x06500000
+
+#define MSM_PMEM_GPU1_SIZE      0x800000
+#define MSM_PMEM_GPU1_BASE      (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
+
+#define MSM_RAM_CONSOLE_BASE    (MSM_EBI_BASE + 0x6d00000)
+#define MSM_RAM_CONSOLE_SIZE    (128 * SZ_1K)
+
+#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
+#error invalid memory map
+#endif
+
+#define DECLARE_MSM_IOMAP
+#include <mach/msm_iomap.h>
+
+#define TROUT_4_BALL_UP_0     1
+#define TROUT_4_BALL_LEFT_0   18
+#define TROUT_4_BALL_DOWN_0   57
+#define TROUT_4_BALL_RIGHT_0  91
+
+#define TROUT_5_BALL_UP_0     94
+#define TROUT_5_BALL_LEFT_0   18
+#define TROUT_5_BALL_DOWN_0   90
+#define TROUT_5_BALL_RIGHT_0  19
+
+#define TROUT_POWER_KEY     20
+
+#define TROUT_4_TP_LS_EN    19
+#define TROUT_5_TP_LS_EN    1
 
 #define TROUT_CPLD_BASE   0xE8100000
 #define TROUT_CPLD_START  0x98000000
 #define TROUT_CPLD_SIZE   SZ_4K
 
+#define TROUT_GPIO_CABLE_IN1            (83)
+#define TROUT_GPIO_CABLE_IN2            (49)
+
+#define TROUT_GPIO_START (128)
+
+#define TROUT_GPIO_INT_MASK0_REG            (0x0c)
+#define TROUT_GPIO_INT_STAT0_REG            (0x0e)
+#define TROUT_GPIO_INT_MASK1_REG            (0x14)
+#define TROUT_GPIO_INT_STAT1_REG            (0x10)
+
+#define TROUT_GPIO_HAPTIC_PWM               (28)
+#define TROUT_GPIO_PS_HOLD                  (25)
+
+#define TROUT_GPIO_MISC2_BASE               (TROUT_GPIO_START + 0x00)
+#define TROUT_GPIO_MISC3_BASE               (TROUT_GPIO_START + 0x08)
+#define TROUT_GPIO_MISC4_BASE               (TROUT_GPIO_START + 0x10)
+#define TROUT_GPIO_MISC5_BASE               (TROUT_GPIO_START + 0x18)
+#define TROUT_GPIO_INT2_BASE                (TROUT_GPIO_START + 0x20)
+#define TROUT_GPIO_MISC1_BASE               (TROUT_GPIO_START + 0x28)
+#define TROUT_GPIO_VIRTUAL_BASE             (TROUT_GPIO_START + 0x30)
+#define TROUT_GPIO_INT5_BASE                (TROUT_GPIO_START + 0x48)
+
+#define TROUT_GPIO_CHARGER_EN               (TROUT_GPIO_MISC2_BASE + 0)
+#define TROUT_GPIO_ISET                     (TROUT_GPIO_MISC2_BASE + 1)
+#define TROUT_GPIO_H2W_DAT_DIR              (TROUT_GPIO_MISC2_BASE + 2)
+#define TROUT_GPIO_H2W_CLK_DIR              (TROUT_GPIO_MISC2_BASE + 3)
+#define TROUT_GPIO_H2W_DAT_GPO              (TROUT_GPIO_MISC2_BASE + 4)
+#define TROUT_GPIO_H2W_CLK_GPO              (TROUT_GPIO_MISC2_BASE + 5)
+#define TROUT_GPIO_H2W_SEL0                 (TROUT_GPIO_MISC2_BASE + 6)
+#define TROUT_GPIO_H2W_SEL1                 (TROUT_GPIO_MISC2_BASE + 7)
+
+#define TROUT_GPIO_SPOTLIGHT_EN             (TROUT_GPIO_MISC3_BASE + 0)
+#define TROUT_GPIO_FLASH_EN                 (TROUT_GPIO_MISC3_BASE + 1)
+#define TROUT_GPIO_I2C_PULL                 (TROUT_GPIO_MISC3_BASE + 2)
+#define TROUT_GPIO_TP_I2C_PULL              (TROUT_GPIO_MISC3_BASE + 3)
+#define TROUT_GPIO_TP_EN                    (TROUT_GPIO_MISC3_BASE + 4)
+#define TROUT_GPIO_JOG_EN                   (TROUT_GPIO_MISC3_BASE + 5)
+#define TROUT_GPIO_UI_LED_EN                (TROUT_GPIO_MISC3_BASE + 6)
+#define TROUT_GPIO_QTKEY_LED_EN             (TROUT_GPIO_MISC3_BASE + 7)
+
+#define TROUT_GPIO_VCM_PWDN                 (TROUT_GPIO_MISC4_BASE + 0)
+#define TROUT_GPIO_USB_H2W_SW               (TROUT_GPIO_MISC4_BASE + 1)
+#define TROUT_GPIO_COMPASS_RST_N            (TROUT_GPIO_MISC4_BASE + 2)
+#define TROUT_GPIO_HAPTIC_EN_UP             (TROUT_GPIO_MISC4_BASE + 3)
+#define TROUT_GPIO_HAPTIC_EN_MAIN           (TROUT_GPIO_MISC4_BASE + 4)
+#define TROUT_GPIO_USB_PHY_RST_N            (TROUT_GPIO_MISC4_BASE + 5)
+#define TROUT_GPIO_WIFI_PA_RESETX           (TROUT_GPIO_MISC4_BASE + 6)
+#define TROUT_GPIO_WIFI_EN                  (TROUT_GPIO_MISC4_BASE + 7)
+
+#define TROUT_GPIO_BT_32K_EN                (TROUT_GPIO_MISC5_BASE + 0)
+#define TROUT_GPIO_MAC_32K_EN               (TROUT_GPIO_MISC5_BASE + 1)
+#define TROUT_GPIO_MDDI_32K_EN              (TROUT_GPIO_MISC5_BASE + 2)
+#define TROUT_GPIO_COMPASS_32K_EN           (TROUT_GPIO_MISC5_BASE + 3)
+
+#define TROUT_GPIO_NAVI_ACT_N               (TROUT_GPIO_INT2_BASE + 0)
+#define TROUT_GPIO_COMPASS_IRQ              (TROUT_GPIO_INT2_BASE + 1)
+#define TROUT_GPIO_SLIDING_DET              (TROUT_GPIO_INT2_BASE + 2)
+#define TROUT_GPIO_AUD_HSMIC_DET_N          (TROUT_GPIO_INT2_BASE + 3)
+#define TROUT_GPIO_SD_DOOR_N                (TROUT_GPIO_INT2_BASE + 4)
+#define TROUT_GPIO_CAM_BTN_STEP1_N          (TROUT_GPIO_INT2_BASE + 5)
+#define TROUT_GPIO_CAM_BTN_STEP2_N          (TROUT_GPIO_INT2_BASE + 6)
+#define TROUT_GPIO_TP_ATT_N                 (TROUT_GPIO_INT2_BASE + 7)
+#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE   (TROUT_GPIO_NAVI_ACT_N)
+#define TROUT_GPIO_BANK0_LAST_INT_SOURCE    (TROUT_GPIO_TP_ATT_N)
+
+#define TROUT_GPIO_H2W_DAT_GPI              (TROUT_GPIO_MISC1_BASE + 0)
+#define TROUT_GPIO_H2W_CLK_GPI              (TROUT_GPIO_MISC1_BASE + 1)
+#define TROUT_GPIO_CPLD128_VER_0            (TROUT_GPIO_MISC1_BASE + 4)
+#define TROUT_GPIO_CPLD128_VER_1            (TROUT_GPIO_MISC1_BASE + 5)
+#define TROUT_GPIO_CPLD128_VER_2            (TROUT_GPIO_MISC1_BASE + 6)
+#define TROUT_GPIO_CPLD128_VER_3            (TROUT_GPIO_MISC1_BASE + 7)
+
+#define TROUT_GPIO_SDMC_CD_N                (TROUT_GPIO_VIRTUAL_BASE + 0)
+#define TROUT_GPIO_END                      (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE   (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_LAST_INT_SOURCE    (TROUT_GPIO_SDMC_CD_N)
+
+#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
+        (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
+
+#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
+#define TROUT_INT_BANK0_COUNT (8)
+#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_BANK1_COUNT (1)
+#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
+                        TROUT_INT_BANK1_COUNT - 1)
+#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
+        (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
+        (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
+
+#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
+#define TROUT_BANK_TO_MASK_REG(bank) \
+        (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
+#define TROUT_BANK_TO_STAT_REG(bank) \
+        (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
+
+#endif /* GUARD */
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 262b441b4374..83e47c0d5c2e 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -16,6 +16,13 @@
 #ifndef __ASM_ARCH_MSM_GPIO_H
 #define __ASM_ARCH_MSM_GPIO_H
 
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
 /**
  * struct msm_gpio - GPIO pin description
  * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
deleted file mode 100644
index eb7660f5d4b7..000000000000
--- a/arch/arm/mach-mx1/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if ARCH_MX1
-
-comment "MX1 platforms:"
-
-config MACH_MXLADS
-        bool
-
-config ARCH_MX1ADS
-        bool "MX1ADS platform"
-        select MACH_MXLADS
-        help
-          Say Y here if you are using Motorola MX1ADS/MXLADS boards
-
-config MACH_SCB9328
-        bool "Synertronixx scb9328"
-        help
-          Say Y here if you are using a Synertronixx scb9328 board
-
-endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
deleted file mode 100644
index fc2ddf82441b..000000000000
--- a/arch/arm/mach-mx1/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS
-obj-y                   += generic.o clock.o devices.o
-
-# Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o
-
-# Specific board support
-obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
-obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot
deleted file mode 100644
index 8ed1492288a2..000000000000
--- a/arch/arm/mach-mx1/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y   := 0x08008000
-params_phys-y   := 0x08000100
-initrd_phys-y   := 0x08800000
-
diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h
deleted file mode 100644
index 22e866ff0c09..000000000000
--- a/arch/arm/mach-mx1/crm_regs.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This file may be distributed under the terms of the GNU General
- * Public License, version 2.
- */
-
-#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-
-#define CCM_BASE        IO_ADDRESS(CCM_BASE_ADDR)
-#define SCM_BASE        IO_ADDRESS(SCM_BASE_ADDR)
-
-/* CCM register addresses */
-#define CCM_CSCR        (CCM_BASE + 0x0)
-#define CCM_MPCTL0      (CCM_BASE + 0x4)
-#define CCM_MPCTL1      (CCM_BASE + 0x8)
-#define CCM_SPCTL0      (CCM_BASE + 0xC)
-#define CCM_SPCTL1      (CCM_BASE + 0x10)
-#define CCM_PCDR        (CCM_BASE + 0x20)
-
-#define CCM_CSCR_CLKO_OFFSET    29
-#define CCM_CSCR_CLKO_MASK      (0x7 << 29)
-#define CCM_CSCR_USB_OFFSET     26
-#define CCM_CSCR_USB_MASK       (0x7 << 26)
-#define CCM_CSCR_SPLL_RESTART   (1 << 22)
-#define CCM_CSCR_MPLL_RESTART   (1 << 21)
-#define CCM_CSCR_OSC_EN_SHIFT   17
-#define CCM_CSCR_SYSTEM_SEL     (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET    10
-#define CCM_CSCR_BCLK_MASK      (0xF << 10)
-#define CCM_CSCR_PRESC          (1 << 15)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-#define CCM_PCDR_PCLK3_OFFSET   16
-#define CCM_PCDR_PCLK3_MASK     (0x7F << 16)
-#define CCM_PCDR_PCLK2_OFFSET   4
-#define CCM_PCDR_PCLK2_MASK     (0xF << 4)
-#define CCM_PCDR_PCLK1_OFFSET   0
-#define CCM_PCDR_PCLK1_MASK     0xF
-
-/* SCM register addresses */
-#define SCM_SIDR        (SCM_BASE + 0x0)
-#define SCM_FMCR        (SCM_BASE + 0x4)
-#define SCM_GPCR        (SCM_BASE + 0x8)
-#define SCM_GCCR        (SCM_BASE + 0xC)
-
-#define SCM_GCCR_DMA_CLK_EN_OFFSET      3
-#define SCM_GCCR_CSI_CLK_EN_OFFSET      2
-#define SCM_GCCR_MMA_CLK_EN_OFFSET      1
-#define SCM_GCCR_USBD_CLK_EN_OFFSET     0
-
-#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
deleted file mode 100644
index b6be29d1cb08..000000000000
--- a/arch/arm/mach-mx1/devices.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-
-#include "devices.h"
-
-static struct resource imx_csi_resources[] = {
-        {
-                .start  = 0x00224000,
-                .end    = 0x00224010,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = CSI_INT,
-                .end    = CSI_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 imx_csi_dmamask = 0xffffffffUL;
-
-struct platform_device imx_csi_device = {
-        .name           = "mx1-camera",
-        .id             = 0, /* This is used to put cameras on this interface */
-        .dev            = {
-                .dma_mask = &imx_csi_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-        },
-        .resource       = imx_csi_resources,
-        .num_resources  = ARRAY_SIZE(imx_csi_resources),
-};
-
-static struct resource imx_i2c_resources[] = {
-        {
-                .start  = 0x00217000,
-                .end    = 0x00217010,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = I2C_INT,
-                .end    = I2C_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_i2c_device = {
-        .name           = "imx-i2c",
-        .id             = 0,
-        .resource       = imx_i2c_resources,
-        .num_resources  = ARRAY_SIZE(imx_i2c_resources),
-};
-
-static struct resource imx_uart1_resources[] = {
-        {
-                .start  = UART1_BASE_ADDR,
-                .end    = UART1_BASE_ADDR + 0xD0,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = UART1_MINT_RX,
-                .end    = UART1_MINT_RX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART1_MINT_TX,
-                .end    = UART1_MINT_TX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART1_MINT_RTS,
-                .end    = UART1_MINT_RTS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_uart1_device = {
-        .name           = "imx-uart",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(imx_uart1_resources),
-        .resource       = imx_uart1_resources,
-};
-
-static struct resource imx_uart2_resources[] = {
-        {
-                .start  = UART2_BASE_ADDR,
-                .end    = UART2_BASE_ADDR + 0xD0,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = UART2_MINT_RX,
-                .end    = UART2_MINT_RX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART2_MINT_TX,
-                .end    = UART2_MINT_TX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART2_MINT_RTS,
-                .end    = UART2_MINT_RTS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_uart2_device = {
-        .name           = "imx-uart",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(imx_uart2_resources),
-        .resource       = imx_uart2_resources,
-};
-
-static struct resource imx_rtc_resources[] = {
-        {
-                .start  = 0x00204000,
-                .end    = 0x00204024,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = RTC_INT,
-                .end    = RTC_INT,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = RTC_SAMINT,
-                .end    = RTC_SAMINT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_rtc_device = {
-        .name           = "rtc-imx",
-        .id             = 0,
-        .resource       = imx_rtc_resources,
-        .num_resources  = ARRAY_SIZE(imx_rtc_resources),
-};
-
-static struct resource imx_wdt_resources[] = {
-        {
-                .start  = 0x00201000,
-                .end    = 0x00201008,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = WDT_INT,
-                .end    = WDT_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_wdt_device = {
-        .name           = "imx-wdt",
-        .id             = 0,
-        .resource       = imx_wdt_resources,
-        .num_resources  = ARRAY_SIZE(imx_wdt_resources),
-};
-
-static struct resource imx_usb_resources[] = {
-        {
-                .start  = 0x00212000,
-                .end    = 0x00212148,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = USBD_INT0,
-                .end    = USBD_INT0,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT1,
-                .end    = USBD_INT1,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT2,
-                .end    = USBD_INT2,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT3,
-                .end    = USBD_INT3,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT4,
-                .end    = USBD_INT4,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT5,
-                .end    = USBD_INT5,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT6,
-                .end    = USBD_INT6,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_usb_device = {
-        .name           = "imx_udc",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(imx_usb_resources),
-        .resource       = imx_usb_resources,
-};
-
-/* GPIO port description */
-static struct mxc_gpio_port imx_gpio_ports[] = {
-        {
-                .chip.label = "gpio-0",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
-                .irq = GPIO_INT_PORTA,
-                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        }, {
-                .chip.label = "gpio-1",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
-                .irq = GPIO_INT_PORTB,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        }, {
-                .chip.label = "gpio-2",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
-                .irq = GPIO_INT_PORTC,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        }, {
-                .chip.label = "gpio-3",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
-                .irq = GPIO_INT_PORTD,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        }
-};
-
-int __init mxc_register_gpios(void)
-{
-        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
-}
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
deleted file mode 100644
index 0da5d7cce3a2..000000000000
--- a/arch/arm/mach-mx1/devices.h
+++ /dev/null
@@ -1,7 +0,0 @@
-extern struct platform_device imx_csi_device;
-extern struct platform_device imx_i2c_device;
-extern struct platform_device imx_uart1_device;
-extern struct platform_device imx_uart2_device;
-extern struct platform_device imx_rtc_device;
-extern struct platform_device imx_wdt_device;
-extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
deleted file mode 100644
index 1c0c835b2252..000000000000
--- a/arch/arm/mach-mx2/serial.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include "devices.h"
-
-static struct resource uart0[] = {
-        {
-                .start = MX2x_UART1_BASE_ADDR,
-                .end = MX2x_UART1_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART1,
-                .end = MX2x_INT_UART1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = MX2x_UART2_BASE_ADDR,
-                .end = MX2x_UART2_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART2,
-                .end = MX2x_INT_UART2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = MX2x_UART3_BASE_ADDR,
-                .end = MX2x_UART3_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART3,
-                .end = MX2x_INT_UART3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-        {
-                .start = MX2x_UART4_BASE_ADDR,
-                .end = MX2x_UART4_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART4,
-                .end = MX2x_INT_UART4,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device3 = {
-        .name = "imx-uart",
-        .id = 3,
-        .resource = uart3,
-        .num_resources = ARRAY_SIZE(uart3),
-};
-
-#ifdef CONFIG_MACH_MX27
-static struct resource uart4[] = {
-        {
-                .start = MX27_UART5_BASE_ADDR,
-                .end = MX27_UART5_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_UART5,
-                .end = MX27_INT_UART5,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device4 = {
-        .name = "imx-uart",
-        .id = 4,
-        .resource = uart4,
-        .num_resources = ARRAY_SIZE(uart4),
-};
-
-static struct resource uart5[] = {
-        {
-                .start = MX27_UART6_BASE_ADDR,
-                .end = MX27_UART6_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_UART6,
-                .end = MX27_INT_UART6,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device5 = {
-        .name = "imx-uart",
-        .id = 5,
-        .resource = uart5,
-        .num_resources = ARRAY_SIZE(uart5),
-};
-#endif
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 54d217314ee9..c71a7bc19284 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -4,5 +4,28 @@ comment "MX25 platforms:"
 
 config MACH_MX25_3DS
         bool "Support MX25PDK (3DS) Platform"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+
+config MACH_EUKREA_CPUIMX25
+        bool "Support Eukrea CPUIMX25 Platform"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select MXC_ULPI if USB_ULPI
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX25
+        default MACH_EUKREA_MBIMXSD25_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD25_BASEBOARD
+        prompt "Eukrea MBIMXSD development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMXSD evaluation board.
+
+endchoice
 
 endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 10cebc5ced8c..d9e46ce00a4e 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,5 @@
 obj-y                           := mm.o devices.o
 obj-$(CONFIG_ARCH_MX25)         += clock.o
-obj-$(CONFIG_MACH_MX25_3DS)     += mach-mx25pdk.o
+obj-$(CONFIG_MACH_MX25_3DS)     += mach-mx25_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX25)              += mach-cpuimx25.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 155014993b13..40c7cc41cee3 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk)
         return get_rate_per(15);
 }
 
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+        return get_rate_per(14);
+}
+
+static unsigned long get_rate_ssi1(struct clk *clk)
+{
+        return get_rate_per(13);
+}
+
 static unsigned long get_rate_i2c(struct clk *clk)
 {
         return get_rate_per(6);
@@ -129,9 +139,17 @@ static unsigned long get_rate_lcdc(struct clk *clk)
         return get_rate_per(7);
 }
 
+static unsigned long get_rate_csi(struct clk *clk)
+{
+        return get_rate_per(0);
+}
+
 static unsigned long get_rate_otg(struct clk *clk)
 {
-        return 48000000; /* FIXME */
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        unsigned long rate = get_rate_upll();
+
+        return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
 }
 
 static int clk_cgcr_enable(struct clk *clk)
@@ -166,14 +184,40 @@ static void clk_cgcr_disable(struct clk *clk)
                 .secondary      = s,                    \
         }
 
+/*
+ * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
+ * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
+ * taken from the Freescale released BSP.
+ *
+ * bit  reg     offset  clock
+ *
+ * 0    CGCR1   0       AUDMUX
+ * 12   CGCR1   12      ESAI
+ * 16   CGCR1   16      GPIO1
+ * 17   CGCR1   17      GPIO2
+ * 18   CGCR1   18      GPIO3
+ * 23   CGCR1   23      I2C1
+ * 24   CGCR1   24      I2C2
+ * 25   CGCR1   25      I2C3
+ * 27   CGCR1   27      IOMUXC
+ * 28   CGCR1   28      KPP
+ * 30   CGCR1   30      OWIRE
+ * 36   CGCR2   4       RTIC
+ * 51   CGCR2   19      WDOG
+ */
+
 DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
 DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
+DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
+DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
+DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
 DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
@@ -191,6 +235,13 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 DEFINE_CLOCK(fec_clk,    0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(lcdc_clk,   0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
+DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
+DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
+DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
+DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(can2_clk,   0, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c)        \
         {                               \
@@ -217,7 +268,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
-        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
         _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
@@ -225,6 +276,13 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
+        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
 };
 
 int __init mx25_clocks_init(void)
@@ -238,9 +296,13 @@ int __init mx25_clocks_init(void)
         __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
         __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
         __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+        clk_enable(&uart1_clk);
+#endif
 
-        /* Clock source for lcdc is upll */
-        __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);
+        /* Clock source for lcdc and csi is upll */
+        __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
+                        CRM_BASE + 0x64);
 
         mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
 
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
new file mode 100644
index 000000000000..d86a7c3ca8b0
--- /dev/null
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx25.h>
+#include <mach/devices-common.h>
+
+#define imx25_add_flexcan0(pdata)       \
+        imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
+#define imx25_add_flexcan1(pdata)       \
+        imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
+
+#define imx25_add_imx_i2c0(pdata)       \
+        imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
+#define imx25_add_imx_i2c1(pdata)       \
+        imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
+#define imx25_add_imx_i2c2(pdata)       \
+        imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
+
+#define imx25_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
+#define imx25_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
+#define imx25_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
+#define imx25_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
+#define imx25_add_imx_uart4(pdata)      \
+        imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
+
+#define imx25_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
+
+#define imx25_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
+#define imx25_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
+#define imx25_add_spi_imx2(pdata)       \
+        imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3a405fa400eb..3468eb15b236 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -22,103 +22,6 @@
 #include <mach/mx25.h>
 #include <mach/irqs.h>
 
-static struct resource uart0[] = {
-        {
-                .start = 0x43f90000,
-                .end = 0x43f93fff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 45,
-                .end = 45,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = 0x43f94000,
-                .end = 0x43f97fff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 32,
-                .end = 32,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = 0x5000c000,
-                .end = 0x5000ffff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 18,
-                .end = 18,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-        {
-                .start = 0x50008000,
-                .end = 0x5000bfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 5,
-                .end = 5,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device3 = {
-        .name = "imx-uart",
-        .id = 3,
-        .resource = uart3,
-        .num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-        {
-                .start = 0x5002c000,
-                .end = 0x5002ffff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 40,
-                .end = 40,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device4 = {
-        .name = "imx-uart",
-        .id = 4,
-        .resource = uart4,
-        .num_resources = ARRAY_SIZE(uart4),
-};
-
-#define MX25_OTG_BASE_ADDR 0x53FF4000
-
 static u64 otg_dmamask = DMA_BIT_MASK(32);
 
 static struct resource mxc_otg_resources[] = {
@@ -181,63 +84,6 @@ struct platform_device mxc_usbh2 = {
         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-static struct resource mxc_spi_resources0[] = {
-        {
-               .start = 0x43fa4000,
-               .end = 0x43fa7fff,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = 14,
-               .end = 14,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device0 = {
-        .name = "spi_imx",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
-        .resource = mxc_spi_resources0,
-};
-
-static struct resource mxc_spi_resources1[] = {
-        {
-               .start = 0x50010000,
-               .end = 0x50013fff,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = 13,
-               .end = 13,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device1 = {
-        .name = "spi_imx",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
-        .resource = mxc_spi_resources1,
-};
-
-static struct resource mxc_spi_resources2[] = {
-        {
-               .start = 0x50004000,
-               .end = 0x50007fff,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = 0,
-               .end = 0,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device2 = {
-        .name = "spi_imx",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
-        .resource = mxc_spi_resources2,
-};
-
 static struct resource mxc_pwm_resources0[] = {
         {
                 .start  = 0x53fe0000,
@@ -333,63 +179,6 @@ struct platform_device mxc_pwm_device3 = {
         .resource = mxc_pwm_resources3,
 };
 
-static struct resource mxc_i2c_1_resources[] = {
-        {
-                .start  = 0x43f80000,
-                .end    = 0x43f83fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = 3,
-                .end    = 3,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_i2c_device0 = {
-        .name = "imx-i2c",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
-        .resource = mxc_i2c_1_resources,
-};
-
-static struct resource mxc_i2c_2_resources[] = {
-        {
-                .start  = 0x43f98000,
-                .end    = 0x43f9bfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = 4,
-                .end    = 4,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_i2c_device1 = {
-        .name = "imx-i2c",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
-        .resource = mxc_i2c_2_resources,
-};
-
-static struct resource mxc_i2c_3_resources[] = {
-        {
-                .start  = 0x43f84000,
-                .end    = 0x43f87fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = 10,
-                .end    = 10,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_i2c_device2 = {
-        .name = "imx-i2c",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
-        .resource = mxc_i2c_3_resources,
-};
-
 static struct mxc_gpio_port imx_gpio_ports[] = {
         {
                 .chip.label = "gpio-0",
@@ -414,7 +203,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
         }
 };
 
-int __init mxc_register_gpios(void)
+int __init imx25_register_gpios(void)
 {
         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
@@ -439,26 +228,6 @@ struct platform_device mx25_fec_device = {
         .resource       = mx25_fec_resources,
 };
 
-static struct resource mxc_nand_resources[] = {
-        {
-                .start  = MX25_NFC_BASE_ADDR,
-                .end    = MX25_NFC_BASE_ADDR + 0x1fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_NANDFC,
-                .end    = MX25_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_nand_device = {
-        .name           = "mxc_nand",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(mxc_nand_resources),
-        .resource       = mxc_nand_resources,
-};
-
 static struct resource mx25_rtc_resources[] = {
         {
                 .start  = MX25_DRYICE_BASE_ADDR,
@@ -515,3 +284,83 @@ struct platform_device mxc_wdt = {
         .num_resources = ARRAY_SIZE(mxc_wdt_resources),
         .resource = mxc_wdt_resources,
 };
+
+static struct resource mx25_kpp_resources[] = {
+        {
+                .start  = MX25_KPP_BASE_ADDR,
+                .end    = MX25_KPP_BASE_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MX25_INT_KPP,
+                .end    = MX25_INT_KPP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mx25_kpp_device = {
+        .name   = "imx-keypad",
+        .id     = -1,
+        .num_resources  = ARRAY_SIZE(mx25_kpp_resources),
+        .resource       = mx25_kpp_resources,
+};
+
+static struct resource imx_ssi_resources0[] = {
+        {
+                .start  = MX25_SSI1_BASE_ADDR,
+                .end    = MX25_SSI1_BASE_ADDR + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX25_INT_SSI1,
+                .end    = MX25_INT_SSI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource imx_ssi_resources1[] = {
+        {
+                .start  = MX25_SSI2_BASE_ADDR,
+                .end    = MX25_SSI2_BASE_ADDR + 0x3fff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MX25_INT_SSI2,
+                .end    = MX25_INT_SSI2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_ssi_device0 = {
+        .name = "imx-ssi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
+        .resource = imx_ssi_resources0,
+};
+
+struct platform_device imx_ssi_device1 = {
+        .name = "imx-ssi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
+        .resource = imx_ssi_resources1,
+};
+
+static struct resource mx25_csi_resources[] = {
+        {
+                .start  = MX25_CSI_BASE_ADDR,
+                .end    = MX25_CSI_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MX25_INT_CSI,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+struct platform_device mx25_csi_device = {
+        .name   = "mx2-camera",
+        .id     = 0,
+        .num_resources  = ARRAY_SIZE(mx25_csi_resources),
+        .resource       = mx25_csi_resources,
+        .dev            = {
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index cee12c0a0be6..4aceb68e35a7 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -1,24 +1,16 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_otg;
 extern struct platform_device otg_udc_device;
 extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
 extern struct platform_device mxc_pwm_device0;
 extern struct platform_device mxc_pwm_device1;
 extern struct platform_device mxc_pwm_device2;
 extern struct platform_device mxc_pwm_device3;
 extern struct platform_device mxc_keypad_device;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx25_fec_device;
-extern struct platform_device mxc_nand_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mx25_kpp_device;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
+extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..91931dcb0689
--- /dev/null
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+
+#include <mach/hardware.h>
+#include <mach/iomux-mx25.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/mx25.h>
+#include <mach/imx-uart.h>
+#include <mach/imxfb.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
+
+#include "devices-imx25.h"
+#include "devices.h"
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+        /* LCD */
+        MX25_PAD_LD0__LD0,
+        MX25_PAD_LD1__LD1,
+        MX25_PAD_LD2__LD2,
+        MX25_PAD_LD3__LD3,
+        MX25_PAD_LD4__LD4,
+        MX25_PAD_LD5__LD5,
+        MX25_PAD_LD6__LD6,
+        MX25_PAD_LD7__LD7,
+        MX25_PAD_LD8__LD8,
+        MX25_PAD_LD9__LD9,
+        MX25_PAD_LD10__LD10,
+        MX25_PAD_LD11__LD11,
+        MX25_PAD_LD12__LD12,
+        MX25_PAD_LD13__LD13,
+        MX25_PAD_LD14__LD14,
+        MX25_PAD_LD15__LD15,
+        MX25_PAD_GPIO_E__LD16,
+        MX25_PAD_GPIO_F__LD17,
+        MX25_PAD_HSYNC__HSYNC,
+        MX25_PAD_VSYNC__VSYNC,
+        MX25_PAD_LSCLK__LSCLK,
+        MX25_PAD_OE_ACD__OE_ACD,
+        MX25_PAD_CONTRAST__CONTRAST,
+        /* LCD_PWR */
+        MX25_PAD_PWM__GPIO_1_26,
+        /* LED */
+        MX25_PAD_POWER_FAIL__GPIO_3_19,
+        /* SWITCH */
+        MX25_PAD_VSTBY_ACK__GPIO_3_18,
+        /* UART2 */
+        MX25_PAD_UART2_RTS__UART2_RTS,
+        MX25_PAD_UART2_CTS__UART2_CTS,
+        MX25_PAD_UART2_TXD__UART2_TXD,
+        MX25_PAD_UART2_RXD__UART2_RXD,
+        /* SD1 */
+        MX25_PAD_SD1_CMD__SD1_CMD,
+        MX25_PAD_SD1_CLK__SD1_CLK,
+        MX25_PAD_SD1_DATA0__SD1_DATA0,
+        MX25_PAD_SD1_DATA1__SD1_DATA1,
+        MX25_PAD_SD1_DATA2__SD1_DATA2,
+        MX25_PAD_SD1_DATA3__SD1_DATA3,
+        /* SD1 CD */
+        MX25_PAD_DE_B__GPIO_2_20,
+        /* I2S */
+        MX25_PAD_KPP_COL3__AUD5_TXFS,
+        MX25_PAD_KPP_COL2__AUD5_TXC,
+        MX25_PAD_KPP_COL1__AUD5_RXD,
+        MX25_PAD_KPP_COL0__AUD5_TXD,
+};
+
+#define GPIO_LED1       83
+#define GPIO_SWITCH1    82
+#define GPIO_SD1CD      52
+#define GPIO_LCDPWR     26
+
+static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
+        {
+                .mode   = {
+                        .name           = "CMO-QVGA",
+                        .refresh        = 60,
+                        .xres           = 320,
+                        .yres           = 240,
+                        .pixclock       = KHZ2PICOS(6500),
+                        .left_margin    = 30,
+                        .right_margin   = 38,
+                        .upper_margin   = 20,
+                        .lower_margin   = 3,
+                        .hsync_len      = 15,
+                        .vsync_len      = 4,
+                },
+                .bpp    = 16,
+                .pcr    = 0xCAD08B80,
+        },
+};
+
+static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
+        .mode           = eukrea_mximxsd_modes,
+        .num_modes      = ARRAY_SIZE(eukrea_mximxsd_modes),
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00040060,
+};
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(GPIO_LCDPWR, 1);
+        else
+                gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+        .set_power              = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_LED1,
+        },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+        .leds           = eukrea_mbimxsd_leds,
+        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &eukrea_mbimxsd_led_info,
+        },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+        {
+                .gpio           = GPIO_SWITCH1,
+                .code           = BTN_0,
+                .desc           = "BP1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+        .buttons        = eukrea_mbimxsd_gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &eukrea_mbimxsd_button_data,
+        }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_mbimxsd_leds_gpio,
+        &eukrea_mbimxsd_button_device,
+        &eukrea_mbimxsd_lcd_powerdev,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx25 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
+                printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+        /* SSI unit master I2S codec connected to SSI_AUD5*/
+        mxc_audmux_v2_configure_port(0,
+                        MXC_AUDMUX_V2_PTCR_SYN |
+                        MXC_AUDMUX_V2_PTCR_TFSDIR |
+                        MXC_AUDMUX_V2_PTCR_TFSEL(4) |
+                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                        MXC_AUDMUX_V2_PTCR_TCSEL(4),
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(4)
+        );
+        mxc_audmux_v2_configure_port(4,
+                        MXC_AUDMUX_V2_PTCR_SYN,
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+        );
+#endif
+
+        imx25_add_imx_uart1(&uart_pdata);
+        mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
+        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+        gpio_request(GPIO_LED1, "LED1");
+        gpio_direction_output(GPIO_LED1, 1);
+        gpio_free(GPIO_LED1);
+
+        gpio_request(GPIO_SWITCH1, "SWITCH1");
+        gpio_direction_input(GPIO_SWITCH1);
+        gpio_free(GPIO_SWITCH1);
+
+        gpio_request(GPIO_LCDPWR, "LCDPWR");
+        gpio_direction_output(GPIO_LCDPWR, 1);
+        gpio_free(GPIO_SWITCH1);
+
+        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
new file mode 100644
index 000000000000..56b2e26d23b4
--- /dev/null
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
+ * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/fec.h>
+#include <linux/platform_device.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include <mach/imxfb.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+#include <mach/iomux-mx25.h>
+
+#include "devices-imx25.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct pad_desc eukrea_cpuimx25_pads[] = {
+        /* FEC - RMII */
+        MX25_PAD_FEC_MDC__FEC_MDC,
+        MX25_PAD_FEC_MDIO__FEC_MDIO,
+        MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+        MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+        MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+        MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+        MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        /* I2C1 */
+        MX25_PAD_I2C1_CLK__I2C1_CLK,
+        MX25_PAD_I2C1_DAT__I2C1_DAT,
+};
+
+static struct fec_platform_data mx25_fec_pdata = {
+        .phy    = PHY_INTERFACE_MODE_RMII,
+};
+
+static const struct mxc_nand_platform_data
+eukrea_cpuimx25_nand_board_info __initconst = {
+        .width          = 1,
+        .hw_ecc         = 1,
+        .flash_bbt      = 1,
+};
+
+static const struct imxi2c_platform_data
+eukrea_cpuimx25_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+        .portsc = MXC_EHCI_MODE_UTMI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .portsc = MXC_EHCI_MODE_SERIAL,
+        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+                  MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx25_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
+
+static void __init eukrea_cpuimx25_init(void)
+{
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
+                        ARRAY_SIZE(eukrea_cpuimx25_pads)))
+                printk(KERN_ERR "error setting cpuimx25 pads !\n");
+
+        imx25_add_imx_uart0(&uart_pdata);
+        imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
+        mxc_register_device(&mx25_rtc_device, NULL);
+        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+
+        i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
+                                ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
+        imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+                mxc_register_device(&mxc_otg, &otg_pdata);
+        }
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+        if (!otg_mode_host)
+                mxc_register_device(&otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+        eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx25_timer_init(void)
+{
+        mx25_clocks_init();
+}
+
+static struct sys_timer eukrea_cpuimx25_timer = {
+        .init   = eukrea_cpuimx25_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
+        /* Maintainer: Eukrea Electromatique */
+        .phys_io        = MX25_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = MX25_PHYS_OFFSET + 0x100,
+        .map_io         = mx25_map_io,
+        .init_irq       = mx25_init_irq,
+        .init_machine   = eukrea_cpuimx25_init,
+        .timer          = &eukrea_cpuimx25_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 83d74109e7d8..62bc21f11a71 100644
--- a/arch/arm/mach-mx25/mach-mx25pdk.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -16,6 +16,12 @@
  * Boston, MA  02110-1301, USA.
  */
 
+/*
+ * This machine is known as:
+ *  - i.MX25 3-Stack Development System
+ *  - i.MX25 Platform Development Kit (i.MX25 PDK)
+ */
+
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/delay.h>
@@ -24,6 +30,7 @@
 #include <linux/gpio.h>
 #include <linux/fec.h>
 #include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -32,14 +39,14 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx25.h>
-#include <mach/mxc_nand.h>
 #include <mach/imxfb.h>
-#include "devices.h"
 #include <mach/iomux-mx25.h>
 
-static struct imxuart_platform_data uart_pdata = {
+#include "devices-imx25.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -80,6 +87,16 @@ static struct pad_desc mx25pdk_pads[] = {
         MX25_PAD_LSCLK__LSCLK,
         MX25_PAD_OE_ACD__OE_ACD,
         MX25_PAD_CONTRAST__CONTRAST,
+
+        /* Keypad */
+        MX25_PAD_KPP_ROW0__KPP_ROW0,
+        MX25_PAD_KPP_ROW1__KPP_ROW1,
+        MX25_PAD_KPP_ROW2__KPP_ROW2,
+        MX25_PAD_KPP_ROW3__KPP_ROW3,
+        MX25_PAD_KPP_COL0__KPP_COL0,
+        MX25_PAD_KPP_COL1__KPP_COL1,
+        MX25_PAD_KPP_COL2__KPP_COL2,
+        MX25_PAD_KPP_COL3__KPP_COL3,
 };
 
 static struct fec_platform_data mx25_fec_pdata = {
@@ -103,7 +120,8 @@ static void __init mx25pdk_fec_reset(void)
         gpio_set_value(FEC_RESET_B_GPIO, 1);
 }
 
-static struct mxc_nand_platform_data mx25pdk_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx25pdk_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
         .flash_bbt      = 1,
@@ -137,19 +155,45 @@ static struct imx_fb_platform_data mx25pdk_fb_pdata = {
         .dmacr          = 0x00020010,
 };
 
+static const uint32_t mx25pdk_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_DOWN),
+        KEY(0, 2, KEY_VOLUMEDOWN),
+        KEY(0, 3, KEY_HOME),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(1, 1, KEY_LEFT),
+        KEY(1, 2, KEY_ENTER),
+        KEY(1, 3, KEY_VOLUMEUP),
+        KEY(2, 0, KEY_F6),
+        KEY(2, 1, KEY_F8),
+        KEY(2, 2, KEY_F9),
+        KEY(2, 3, KEY_F10),
+        KEY(3, 0, KEY_F1),
+        KEY(3, 1, KEY_F2),
+        KEY(3, 2, KEY_F3),
+        KEY(3, 3, KEY_POWER),
+};
+
+static struct matrix_keymap_data mx25pdk_keymap_data = {
+        .keymap         = mx25pdk_keymap,
+        .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
+};
+
 static void __init mx25pdk_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
                         ARRAY_SIZE(mx25pdk_pads));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx25_add_imx_uart0(&uart_pdata);
         mxc_register_device(&mxc_usbh2, NULL);
-        mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
+        imx25_add_mxc_nand(&mx25pdk_nand_board_info);
         mxc_register_device(&mx25_rtc_device, NULL);
         mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
+        mxc_register_device(&mxc_wdt, NULL);
 
         mx25pdk_fec_reset();
         mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+        mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
 }
 
 static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
index a7e587ff3e9e..bb677111fb0f 100644
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-mx25/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
@@ -69,8 +65,11 @@ void __init mx25_map_io(void)
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx25_register_gpios(void);
+
 void __init mx25_init_irq(void)
 {
         mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
+        imx25_register_gpios();
 }
 
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753fdf25e..85beece802aa 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -15,6 +15,8 @@ comment "MX3 platforms:"
 config MACH_MX31ADS
         bool "Support MX31ADS platforms"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         default y
         help
           Include support for MX31ADS platform. This includes specific
@@ -34,6 +36,9 @@ config MACH_MX31ADS_WM1133_EV1
 config MACH_PCM037
         bool "Support Phytec pcm037 (i.MX31) platforms"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm037 platform. This includes
@@ -42,6 +47,7 @@ config MACH_PCM037
 config MACH_PCM037_EET
         bool "Support pcm037 EET board extensions"
         depends on MACH_PCM037
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Add support for PCM037 EET baseboard extensions. If you are using the
           OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
@@ -51,6 +57,9 @@ config MACH_MX31LITE
         bool "Support MX31 LITEKIT (LogicPD)"
         select ARCH_MX31
         select MXC_ULPI if USB_ULPI
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for MX31 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
@@ -58,6 +67,10 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
         bool "Support MX31PDK (3DS)"
         select ARCH_MX31
+        select MXC_DEBUG_BOARD
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for MX31PDK (3DS) platform. This includes specific
           configurations for the board and its peripherals.
@@ -74,6 +87,9 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
 config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for mx31moboard platform. This includes specific
@@ -82,6 +98,8 @@ config MACH_MX31MOBOARD
 config MACH_MX31LILLY
         bool "Support MX31 LILLY-1131 platforms (INCO startec)"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for mx31 based LILLY1131 modules. This includes
@@ -90,6 +108,7 @@ config MACH_MX31LILLY
 config MACH_QONG
         bool "Support Dave/DENX QongEVB-LITE platform"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for Dave/DENX QongEVB-LITE platform. This includes
           specific configurations for the board and its peripherals.
@@ -97,6 +116,10 @@ config MACH_QONG
 config MACH_PCM043
         bool "Support Phytec pcm043 (i.MX35) platforms"
         select ARCH_MX35
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_FLEXCAN
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm043 platform. This includes
@@ -105,6 +128,9 @@ config MACH_PCM043
 config MACH_ARMADILLO5X0
         bool "Support Atmark Armadillo-500 Development Base Board"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         select MXC_ULPI if USB_ULPI
         help
           Include support for Atmark Armadillo-500 platform. This includes
@@ -113,6 +139,7 @@ config MACH_ARMADILLO5X0
 config MACH_MX35_3DS
         bool "Support MX35PDK platform"
         select ARCH_MX35
+        select IMX_HAVE_PLATFORM_IMX_UART
         default n
         help
           Include support for MX35PDK platform. This includes specific
@@ -121,8 +148,34 @@ config MACH_MX35_3DS
 config MACH_KZM_ARM11_01
         bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for KZM-ARM11-01. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_EUKREA_CPUIMX35
+        bool "Support Eukrea CPUIMX35 Platform"
+        select ARCH_MX35
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for Eukrea CPUIMX35 platform. This includes
+          specific configurations for the board and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX35
+        default MACH_EUKREA_MBIMXSD35_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD35_BASEBOARD
+        prompt "Eukrea MBIMXSD development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMXSD evaluation board.
+
+endchoice
+
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5d650fda5d5d..2bd7beceb991 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -22,5 +22,7 @@ obj-$(CONFIG_MACH_MX31MOBOARD)	+= mach-mx31moboard.o mx31moboard-devboard.o \
 obj-$(CONFIG_MACH_QONG)         += mach-qong.o
 obj-$(CONFIG_MACH_PCM043)       += mach-pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
-obj-$(CONFIG_MACH_MX35_3DS)     += mach-mx35pdk.o
+obj-$(CONFIG_MACH_MX35_3DS)     += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35)      += mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 9f3e943e2232..d3af0fdf8475 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_ahb, NULL);
 DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
 DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
 DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
@@ -428,8 +428,8 @@ static struct clk nfc_clk = {
 static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
         _REGISTER_CLOCK(NULL, "ata", ata_clk)
-        _REGISTER_CLOCK(NULL, "can", can1_clk)
-        _REGISTER_CLOCK(NULL, "can", can2_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
         _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
         _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
         _REGISTER_CLOCK(NULL, "ect", ect_clk)
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
new file mode 100644
index 000000000000..3b1a44a20585
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx31.h>
+#include <mach/devices-common.h>
+
+#define imx31_add_imx_i2c0(pdata)       \
+        imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
+#define imx31_add_imx_i2c1(pdata)       \
+        imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata)
+#define imx31_add_imx_i2c2(pdata)       \
+        imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
+
+#define imx31_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
+#define imx31_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
+#define imx31_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
+#define imx31_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
+#define imx31_add_imx_uart4(pdata)      \
+        imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
+
+#define imx31_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
+
+#define imx31_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
+#define imx31_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
+#define imx31_add_spi_imx2(pdata)       \
+        imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
new file mode 100644
index 000000000000..f6a431a4c3d2
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx35.h>
+#include <mach/devices-common.h>
+
+#define imx35_add_flexcan0(pdata)       \
+        imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
+#define imx35_add_flexcan1(pdata)       \
+        imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
+
+#define imx35_add_imx_i2c0(pdata)       \
+        imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
+#define imx35_add_imx_i2c1(pdata)       \
+        imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
+#define imx35_add_imx_i2c2(pdata)       \
+        imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
+
+#define imx35_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
+#define imx35_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata)
+#define imx35_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata)
+
+#define imx35_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
+
+#define imx35_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
+#define imx35_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index db7acd6e9101..a4fd1a26fc91 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -25,108 +25,10 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx3_camera.h>
 
 #include "devices.h"
 
-static struct resource uart0[] = {
-        {
-                .start = UART1_BASE_ADDR,
-                .end = UART1_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART1,
-                .end = MXC_INT_UART1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = UART2_BASE_ADDR,
-                .end = UART2_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART2,
-                .end = MXC_INT_UART2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = UART3_BASE_ADDR,
-                .end = UART3_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART3,
-                .end = MXC_INT_UART3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-#ifdef CONFIG_ARCH_MX31
-static struct resource uart3[] = {
-        {
-                .start = UART4_BASE_ADDR,
-                .end = UART4_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART4,
-                .end = MXC_INT_UART4,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device3 = {
-        .name = "imx-uart",
-        .id = 3,
-        .resource = uart3,
-        .num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-        {
-                .start = UART5_BASE_ADDR,
-                .end = UART5_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART5,
-                .end = MXC_INT_UART5,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device4 = {
-        .name = "imx-uart",
-        .id = 4,
-        .resource = uart4,
-        .num_resources = ARRAY_SIZE(uart4),
-};
-#endif /* CONFIG_ARCH_MX31 */
-
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
         {
@@ -147,7 +49,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
         }
 };
 
-int __init mxc_register_gpios(void)
+int __init imx3x_register_gpios(void)
 {
         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
@@ -167,82 +69,6 @@ struct platform_device mxc_w1_master_device = {
         .resource = mxc_w1_master_resources,
 };
 
-static struct resource mxc_nand_resources[] = {
-        {
-                .start  = 0, /* runtime dependent */
-                .end    = 0,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MXC_INT_NANDFC,
-                .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_nand_device = {
-        .name = "mxc_nand",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_nand_resources),
-        .resource = mxc_nand_resources,
-};
-
-static struct resource mxc_i2c0_resources[] = {
-        {
-                .start = I2C_BASE_ADDR,
-                .end = I2C_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_I2C,
-                .end = MXC_INT_I2C,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device0 = {
-        .name = "imx-i2c",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
-        .resource = mxc_i2c0_resources,
-};
-
-static struct resource mxc_i2c1_resources[] = {
-        {
-                .start = I2C2_BASE_ADDR,
-                .end = I2C2_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_I2C2,
-                .end = MXC_INT_I2C2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device1 = {
-        .name = "imx-i2c",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
-        .resource = mxc_i2c1_resources,
-};
-
-static struct resource mxc_i2c2_resources[] = {
-        {
-                .start = I2C3_BASE_ADDR,
-                .end = I2C3_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_I2C3,
-                .end = MXC_INT_I2C3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device2 = {
-        .name = "imx-i2c",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
-        .resource = mxc_i2c2_resources,
-};
-
 #ifdef CONFIG_ARCH_MX31
 static struct resource mxcsdhc0_resources[] = {
         {
@@ -455,68 +281,7 @@ struct platform_device mxc_usbh2 = {
         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-/*
- * SPI master controller
- * 3 channels
- */
-static struct resource mxc_spi_0_resources[] = {
-        {
-               .start = CSPI1_BASE_ADDR,
-               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = MXC_INT_CSPI1,
-               .end = MXC_INT_CSPI1,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource mxc_spi_1_resources[] = {
-        {
-                .start = CSPI2_BASE_ADDR,
-                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_CSPI2,
-                .end = MXC_INT_CSPI2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource mxc_spi_2_resources[] = {
-        {
-                .start = CSPI3_BASE_ADDR,
-                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_CSPI3,
-                .end = MXC_INT_CSPI3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device0 = {
-        .name = "spi_imx",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_spi_0_resources),
-        .resource = mxc_spi_0_resources,
-};
-
-struct platform_device mxc_spi_device1 = {
-        .name = "spi_imx",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_spi_1_resources),
-        .resource = mxc_spi_1_resources,
-};
-
-struct platform_device mxc_spi_device2 = {
-        .name = "spi_imx",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_spi_2_resources),
-        .resource = mxc_spi_2_resources,
-};
-
-#ifdef CONFIG_ARCH_MX35
+#if defined(CONFIG_ARCH_MX35)
 static struct resource mxc_fec_resources[] = {
         {
                 .start  = MXC_FEC_BASE_ADDR,
@@ -628,16 +393,15 @@ struct platform_device imx_kpp_device = {
 
 static int __init mx3_devices_init(void)
 {
+#if defined(CONFIG_ARCH_MX31)
         if (cpu_is_mx31()) {
-                mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
-                mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
                 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
                 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
                 mxc_register_device(&mxc_rnga_device, NULL);
         }
+#endif
+#if defined(CONFIG_ARCH_MX35)
         if (cpu_is_mx35()) {
-                mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
-                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
                 otg_resources[0].start = MX35_OTG_BASE_ADDR;
                 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
                 otg_resources[1].start = MXC_INT_USBOTG;
@@ -653,6 +417,7 @@ static int __init mx3_devices_init(void)
                 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
                 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
         }
+#endif
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 2c3c8646a29e..e5535234839f 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,14 +1,4 @@
-
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
-extern struct platform_device mxc_nand_device;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
@@ -20,9 +10,6 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..1dc5004df866
--- /dev/null
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx35.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/audmux.h>
+#include <mach/ssi.h>
+
+#include "devices-imx35.h"
+#include "devices.h"
+
+static const struct fb_videomode fb_modedb[] = {
+        {
+                .name           = "CMO_QVGA",
+                .refresh        = 60,
+                .xres           = 320,
+                .yres           = 240,
+                .pixclock       = KHZ2PICOS(6500),
+                .left_margin    = 68,
+                .right_margin   = 20,
+                .upper_margin   = 15,
+                .lower_margin   = 4,
+                .hsync_len      = 30,
+                .vsync_len      = 3,
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "CMO_QVGA",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+        /* LCD */
+        MX35_PAD_LD0__IPU_DISPB_DAT_0,
+        MX35_PAD_LD1__IPU_DISPB_DAT_1,
+        MX35_PAD_LD2__IPU_DISPB_DAT_2,
+        MX35_PAD_LD3__IPU_DISPB_DAT_3,
+        MX35_PAD_LD4__IPU_DISPB_DAT_4,
+        MX35_PAD_LD5__IPU_DISPB_DAT_5,
+        MX35_PAD_LD6__IPU_DISPB_DAT_6,
+        MX35_PAD_LD7__IPU_DISPB_DAT_7,
+        MX35_PAD_LD8__IPU_DISPB_DAT_8,
+        MX35_PAD_LD9__IPU_DISPB_DAT_9,
+        MX35_PAD_LD10__IPU_DISPB_DAT_10,
+        MX35_PAD_LD11__IPU_DISPB_DAT_11,
+        MX35_PAD_LD12__IPU_DISPB_DAT_12,
+        MX35_PAD_LD13__IPU_DISPB_DAT_13,
+        MX35_PAD_LD14__IPU_DISPB_DAT_14,
+        MX35_PAD_LD15__IPU_DISPB_DAT_15,
+        MX35_PAD_LD16__IPU_DISPB_DAT_16,
+        MX35_PAD_LD17__IPU_DISPB_DAT_17,
+        MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+        MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+        /* Backlight */
+        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+        /* LCD_PWR */
+        MX35_PAD_D3_CLS__GPIO1_4,
+        /* LED */
+        MX35_PAD_LD23__GPIO3_29,
+        /* SWITCH */
+        MX35_PAD_LD19__GPIO3_25,
+        /* UART2 */
+        MX35_PAD_CTS2__UART2_CTS,
+        MX35_PAD_RTS2__UART2_RTS,
+        MX35_PAD_TXD2__UART2_TXD_MUX,
+        MX35_PAD_RXD2__UART2_RXD_MUX,
+        /* I2S */
+        MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+        MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+        MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+        MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+};
+
+#define GPIO_LED1       (2 * 32 + 29)
+#define GPIO_SWITCH1    (2 * 32 + 25)
+#define GPIO_LCDPWR     (4)
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(GPIO_LCDPWR, 1);
+        else
+                gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+        .set_power              = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_LED1,
+        },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+        .leds           = eukrea_mbimxsd_leds,
+        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &eukrea_mbimxsd_led_info,
+        },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+        {
+                .gpio           = GPIO_SWITCH1,
+                .code           = BTN_0,
+                .desc           = "BP1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+        .buttons        = eukrea_mbimxsd_gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &eukrea_mbimxsd_button_data,
+        }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_mbimxsd_leds_gpio,
+        &eukrea_mbimxsd_button_device,
+        &eukrea_mbimxsd_lcd_powerdev,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx35 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
+                printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+        /* SSI unit master I2S codec connected to SSI_AUD4 */
+        mxc_audmux_v2_configure_port(0,
+                        MXC_AUDMUX_V2_PTCR_SYN |
+                        MXC_AUDMUX_V2_PTCR_TFSDIR |
+                        MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                        MXC_AUDMUX_V2_PTCR_TCSEL(3),
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+        );
+        mxc_audmux_v2_configure_port(3,
+                        MXC_AUDMUX_V2_PTCR_SYN,
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+        );
+#endif
+
+        imx35_add_imx_uart1(&uart_pdata);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+        gpio_request(GPIO_LED1, "LED1");
+        gpio_direction_output(GPIO_LED1, 1);
+        gpio_free(GPIO_LED1);
+
+        gpio_request(GPIO_SWITCH1, "SWITCH1");
+        gpio_direction_input(GPIO_SWITCH1);
+        gpio_free(GPIO_SWITCH1);
+
+        gpio_request(GPIO_LCDPWR, "LCDPWR");
+        gpio_direction_output(GPIO_LCDPWR, 1);
+        gpio_free(GPIO_SWITCH1);
+
+        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 5f72ec91af2d..96aadcadb4ff 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -48,16 +48,14 @@
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/board-armadillo5x0.h>
 #include <mach/mmc.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "crm_regs.h"
 
@@ -301,7 +299,8 @@ static struct platform_device armadillo5x0_button_device = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+armadillo5x0_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
 };
@@ -493,13 +492,12 @@ static struct platform_device armadillo5x0_smc911x_device = {
 };
 
 /* UART device data */
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static struct platform_device *devices[] __initdata = {
         &armadillo5x0_smc911x_device,
-        &mxc_i2c_device1,
         &armadillo5x0_button_device,
 };
 
@@ -512,10 +510,11 @@ static void __init armadillo5x0_init(void)
                         ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        imx31_add_imx_i2c1(NULL);
 
         /* Register UART */
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
 
         /* SMSC9118 IRQ pin */
         gpio_direction_input(MX31_PIN_GPIO1_0);
@@ -532,7 +531,7 @@ static void __init armadillo5x0_init(void)
                             &armadillo5x0_nor_flash_pdata);
 
         /* Register NAND Flash */
-        mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata);
+        imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
 
         /* set NAND page size to 2k if not configured via boot mode pins */
         __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
new file mode 100644
index 000000000000..63f970f340a2
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx35.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data
+eukrea_cpuimx35_i2c0_data __initconst = {
+        .bitrate = 50000,
+};
+
+#define TSC2007_IRQGPIO         (2 * 32 + 2)
+static int ts_get_pendown_state(void)
+{
+        int val = 0;
+        gpio_free(TSC2007_IRQGPIO);
+        gpio_request(TSC2007_IRQGPIO, NULL);
+        gpio_direction_input(TSC2007_IRQGPIO);
+
+        val = gpio_get_value(TSC2007_IRQGPIO);
+
+        gpio_free(TSC2007_IRQGPIO);
+        gpio_request(TSC2007_IRQGPIO, NULL);
+
+        return val ? 0 : 1;
+}
+
+static int ts_init(void)
+{
+        gpio_request(TSC2007_IRQGPIO, NULL);
+        return 0;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+        .model                  = 2007,
+        .x_plate_ohms           = 180,
+        .get_pendown_state      = ts_get_pendown_state,
+        .init_platform_hw       = ts_init,
+};
+
+static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        }, {
+                I2C_BOARD_INFO("tsc2007", 0x48),
+                .type           = "tsc2007",
+                .platform_data  = &tsc2007_info,
+                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+        },
+};
+
+static struct platform_device *devices[] __initdata = {
+        &mxc_fec_device,
+        &imx_wdt_device0,
+};
+
+static struct pad_desc eukrea_cpuimx35_pads[] = {
+        /* UART1 */
+        MX35_PAD_CTS1__UART1_CTS,
+        MX35_PAD_RTS1__UART1_RTS,
+        MX35_PAD_TXD1__UART1_TXD_MUX,
+        MX35_PAD_RXD1__UART1_RXD_MUX,
+        /* FEC */
+        MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+        MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX35_PAD_FEC_COL__FEC_COL,
+        MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+        MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+        MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX35_PAD_FEC_MDC__FEC_MDC,
+        MX35_PAD_FEC_MDIO__FEC_MDIO,
+        MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+        MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+        MX35_PAD_FEC_CRS__FEC_CRS,
+        MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+        MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+        MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+        MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+        MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+        MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+        /* I2C1 */
+        MX35_PAD_I2C1_CLK__I2C1_SCL,
+        MX35_PAD_I2C1_DAT__I2C1_SDA,
+        /* TSC2007 IRQ */
+        MX35_PAD_ATA_DA2__GPIO3_2,
+};
+
+static const struct mxc_nand_platform_data
+eukrea_cpuimx35_nand_board_info __initconst = {
+        .width          = 1,
+        .hw_ecc         = 1,
+        .flash_bbt      = 1,
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+        .portsc = MXC_EHCI_MODE_UTMI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh1_pdata = {
+        .portsc = MXC_EHCI_MODE_SERIAL,
+        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+                  MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx35_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
+                        ARRAY_SIZE(eukrea_cpuimx35_pads));
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        imx35_add_imx_uart0(&uart_pdata);
+        imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
+
+        i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
+                        ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
+        imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+                mxc_register_device(&mxc_otg_host, &otg_pdata);
+        }
+        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+#endif
+        if (!otg_mode_host)
+                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+        eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx35_timer_init(void)
+{
+        mx35_clocks_init();
+}
+
+struct sys_timer eukrea_cpuimx35_timer = {
+        .init   = eukrea_cpuimx35_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
+        /* Maintainer: Eukrea Electromatique */
+        .phys_io        = MX35_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .map_io         = mx35_map_io,
+        .init_irq       = mx35_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &eukrea_cpuimx35_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index f085d5d1a6de..5b23e416d6c7 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -16,10 +16,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
@@ -37,13 +33,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <mach/board-kzmarm11.h>
 #include <mach/clock.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/memory.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 #define KZM_ARM11_IO_ADDRESS(x) (                                       \
@@ -51,6 +46,23 @@
         IMX_IO_ADDRESS(x, MX31_CS5) ?:                                  \
         MX31_IO_ADDRESS(x))
 
+/*
+ *  KZM-ARM11-01 Board Control Registers on FPGA
+ */
+#define KZM_ARM11_CTL1          (MX31_CS4_BASE_ADDR + 0x1000)
+#define KZM_ARM11_CTL2          (MX31_CS4_BASE_ADDR + 0x1001)
+#define KZM_ARM11_RSW1          (MX31_CS4_BASE_ADDR + 0x1002)
+#define KZM_ARM11_BACK_LIGHT    (MX31_CS4_BASE_ADDR + 0x1004)
+#define KZM_ARM11_FPGA_REV      (MX31_CS4_BASE_ADDR + 0x1008)
+#define KZM_ARM11_7SEG_LED      (MX31_CS4_BASE_ADDR + 0x1010)
+#define KZM_ARM11_LEDS          (MX31_CS4_BASE_ADDR + 0x1020)
+#define KZM_ARM11_DIPSW2        (MX31_CS4_BASE_ADDR + 0x1003)
+
+/*
+ * External UART for touch panel on FPGA
+ */
+#define KZM_ARM11_16550         (MX31_CS4_BASE_ADDR + 0x1050)
+
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 /*
  * KZM-ARM11-01 has an external UART on FPGA
@@ -173,15 +185,14 @@ static inline int kzm_init_smsc9118(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init kzm_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
 }
 #else
 static inline void kzm_init_imx_uart(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e57291b79d..6fe69e124d30 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -22,7 +18,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -37,19 +32,47 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31_3ds.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/mxc_nand.h>
-#include <mach/spi.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
-/*!
- * @file mx31_3ds.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Definitions for components on the Debug board */
+
+/* Base address of CPLD controller on the Debug board */
+#define DEBUG_BASE_ADDRESS              CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR               MX3x_CS5_BASE_ADDR
+
+/* CPLD config and interrupt base address */
+#define CPLD_ADDR                       (DEBUG_BASE_ADDRESS + 0x20000)
+
+/* status, interrupt */
+#define CPLD_INT_STATUS_REG             (CPLD_ADDR + 0x10)
+#define CPLD_INT_MASK_REG               (CPLD_ADDR + 0x38)
+#define CPLD_INT_RESET_REG              (CPLD_ADDR + 0x20)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER1_REG          (CPLD_ADDR + 0x40)
+#define CPLD_MAGIC_NUMBER2_REG          (CPLD_ADDR + 0x48)
+/* CPLD code version */
+#define CPLD_CODE_VER_REG               (CPLD_ADDR + 0x50)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER3_REG          (CPLD_ADDR + 0x58)
+
+/* CPLD IRQ line for external uart, external ethernet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
+
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_ENET          (MXC_EXP_IO_BASE + 0)
+
+#define MXC_MAX_EXP_IO_LINES    16
+
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 static int mx31_3ds_pins[] = {
@@ -145,7 +168,7 @@ static int spi1_internal_chipselect[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
         .chipselect     = spi1_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
 };
@@ -165,7 +188,8 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+mx31_3ds_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
@@ -182,8 +206,10 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
 
 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
 
-static void mx31_3ds_usbotg_init(void)
+static int mx31_3ds_usbotg_init(void)
 {
+        int err;
+
         mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
@@ -197,10 +223,25 @@ static void mx31_3ds_usbotg_init(void)
         mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
 
-        gpio_request(USBOTG_RST_B, "otgusb-reset");
-        gpio_direction_output(USBOTG_RST_B, 0);
+        err = gpio_request(USBOTG_RST_B, "otgusb-reset");
+        if (err) {
+                pr_err("Failed to request the USB OTG reset gpio\n");
+                return err;
+        }
+
+        err = gpio_direction_output(USBOTG_RST_B, 0);
+        if (err) {
+                pr_err("Failed to drive the USB OTG reset gpio\n");
+                goto usbotg_free_reset;
+        }
+
         mdelay(1);
         gpio_set_value(USBOTG_RST_B, 1);
+        return 0;
+
+usbotg_free_reset:
+        gpio_free(USBOTG_RST_B);
+        return err;
 }
 
 static struct fsl_usb2_platform_data usbotg_pdata = {
@@ -208,178 +249,16 @@ static struct fsl_usb2_platform_data usbotg_pdata = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 /*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-        {
-                .start          = LAN9217_BASE_ADDR,
-                .end            = LAN9217_BASE_ADDR + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = EXPIO_INT_ENET,
-                .end            = EXPIO_INT_ENET,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smsc911x_resources),
-        .resource       = smsc911x_resources,
-        .dev            = {
-                .platform_data = &smsc911x_config,
-        },
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-        uint32_t imr_val;
-        uint32_t int_valid;
-        uint32_t expio_irq;
-
-        imr_val = __raw_readw(CPLD_INT_MASK_REG);
-        int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-        expio_irq = MXC_EXP_IO_BASE;
-        for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-                if ((int_valid & 1) == 0)
-                        continue;
-                generic_handle_irq(expio_irq);
-        }
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-        uint16_t reg;
-        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-        /* mask the interrupt */
-        reg = __raw_readw(CPLD_INT_MASK_REG);
-        reg |= 1 << expio;
-        __raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-        /* clear the interrupt status */
-        __raw_writew(1 << expio, CPLD_INT_RESET_REG);
-        __raw_writew(0, CPLD_INT_RESET_REG);
-        /* mask the interrupt */
-        expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-        uint16_t reg;
-        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-        /* unmask the interrupt */
-        reg = __raw_readw(CPLD_INT_MASK_REG);
-        reg &= ~(1 << expio);
-        __raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-        .ack = expio_ack_irq,
-        .mask = expio_mask_irq,
-        .unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-        int i;
-        int ret;
-
-        /* Check if there's a debug board connected */
-        if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-            (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-            (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-                /* No Debug board found */
-                return -ENODEV;
-        }
-
-        pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-                __raw_readw(CPLD_CODE_VER_REG));
-
-        /*
-         * Configure INT line as GPIO input
-         */
-        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-        if (ret)
-                pr_warning("could not get LAN irq gpio\n");
-        else
-                gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-        /* Disable the interrupts and clear the status */
-        __raw_writew(0, CPLD_INT_MASK_REG);
-        __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-        __raw_writew(0, CPLD_INT_RESET_REG);
-        __raw_writew(0x1F, CPLD_INT_MASK_REG);
-        for (i = MXC_EXP_IO_BASE;
-             i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-             i++) {
-                set_irq_chip(i, &expio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-        set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-        return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-        {
-                .virtual = MX31_CS5_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-                .length = MX31_CS5_SIZE,
-                .type = MT_DEVICE,
-        },
-};
-
-/*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
         mx31_map_io();
-        iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -390,10 +269,10 @@ static void __init mxc_board_init(void)
         mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
                                       "mx31_3ds");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
-        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        imx31_add_spi_imx0(&spi1_pdata);
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
@@ -402,8 +281,9 @@ static void __init mxc_board_init(void)
         mx31_3ds_usbotg_init();
         mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-        if (!mx31_3ds_init_expio())
-                platform_device_register(&smsc911x_device);
+        if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+                printk(KERN_WARNING "Init of the debugboard failed, all "
+                                    "devices on the board are unusable.\n");
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index b3d1a1895c20..94b3e7c42404 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -33,8 +29,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31ads.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -43,14 +37,45 @@
 #include <linux/mfd/wm8350/pmic.h>
 #endif
 
+#include "devices-imx31.h"
 #include "devices.h"
 
-/*!
- * @file mx31ads.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
+/* Offsets for the PBC Controller register */
+
+/* PBC Board interrupt status register */
+#define PBC_INTSTATUS           0x000016
+
+/* PBC Board interrupt current status register */
+#define PBC_INTCURR_STATUS      0x000018
+
+/* PBC Interrupt mask register set address */
+#define PBC_INTMASK_SET         0x00001A
+
+/* PBC Interrupt mask register clear address */
+#define PBC_INTMASK_CLEAR       0x00001C
+
+/* External UART A */
+#define PBC_SC16C652_UARTA      0x010000
+
+/* External UART B */
+#define PBC_SC16C652_UARTB      0x010010
+
+#define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
+
+#define MXC_MAX_EXP_IO_LINES    16
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
@@ -98,7 +123,7 @@ static inline int mxc_init_extuart(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -112,7 +137,7 @@ static unsigned int uart_pins[] = {
 static inline void mxc_init_imx_uart(void)
 {
         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -475,7 +500,7 @@ static void mxc_init_i2c(void)
         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 
-        mxc_register_device(&mxc_i2c_device1, NULL);
+        imx31_add_imx_i2c1(NULL);
 }
 #else
 static void mxc_init_i2c(void)
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index b2c7f512070f..8f66f65e80e2 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -46,10 +42,10 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -269,12 +265,12 @@ static int spi_internal_chipselect[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
         .chipselect = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
         .chipselect = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -289,6 +285,7 @@ static struct spi_board_info mc13783_dev __initdata = {
         .bus_num        = 1,
         .chip_select    = 0,
         .platform_data  = &mc13783_pdata,
+        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -331,8 +328,8 @@ static void __init mx31lilly_board_init(void)
         mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
         mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
 
-        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
-        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        imx31_add_spi_imx0(&spi0_pdata);
+        imx31_add_spi_imx1(&spi1_pdata);
         spi_register_board_info(&mc13783_dev, 1);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 2b6d11400877..da236c497d2a 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -42,14 +38,12 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/board-mx31lite.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
-#include <mach/mxc_nand.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -69,7 +63,8 @@ static unsigned int mx31lite_pins[] = {
         MX31_PIN_CSPI2_SS2__SS2,
 };
 
-static struct mxc_nand_platform_data mx31lite_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx31lite_nand_board_info __initconst  = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -112,7 +107,7 @@ static int spi_internal_chipselect[] = {
         MXC_SPI_CS(0),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
         .chipselect     = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -253,9 +248,9 @@ static void __init mxc_board_init(void)
 
         /* NOR and NAND flash */
         platform_device_register(&physmap_flash_device);
-        mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+        imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
-        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        imx31_add_spi_imx1(&spi1_pdata);
         spi_register_board_info(&mc13783_spi_dev, 1);
 
 #if defined(CONFIG_USB_ULPI)
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 62b5e40165df..67776bc61c33 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -42,16 +38,15 @@
 #include <mach/board-mx31moboard.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
-#include <mach/i2c.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/mx3_camera.h>
 #include <mach/spi.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int moboard_pins[] = {
@@ -130,24 +125,36 @@ static struct platform_device mx31moboard_flash = {
 
 static int moboard_uart0_init(struct platform_device *pdev)
 {
-        gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
-        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
-        return 0;
+        int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+        if (ret)
+                return ret;
+
+        ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
+        if (ret)
+                gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
+
+        return ret;
+}
+
+static void moboard_uart0_exit(struct platform_device *pdev)
+{
+        gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
 }
 
-static struct imxuart_platform_data uart0_pdata = {
+static const struct imxuart_platform_data uart0_pdata __initconst = {
         .init = moboard_uart0_init,
+        .exit = moboard_uart0_exit,
 };
 
-static struct imxuart_platform_data uart4_pdata = {
+static const struct imxuart_platform_data uart4_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxi2c_platform_data moboard_i2c0_pdata = {
+static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
         .bitrate = 400000,
 };
 
-static struct imxi2c_platform_data moboard_i2c1_pdata = {
+static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -156,7 +163,7 @@ static int moboard_spi1_cs[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master moboard_spi1_master = {
+static const struct spi_imx_master moboard_spi1_pdata __initconst = {
         .chipselect     = moboard_spi1_cs,
         .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
 };
@@ -286,7 +293,7 @@ static int moboard_spi2_cs[] = {
         MXC_SPI_CS(1),
 };
 
-static struct spi_imx_master moboard_spi2_master = {
+static const struct spi_imx_master moboard_spi2_pdata __initconst = {
         .chipselect     = moboard_spi2_cs,
         .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
 };
@@ -499,15 +506,14 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart0_pdata);
-
-        mxc_register_device(&mxc_uart_device4, &uart4_pdata);
+        imx31_add_imx_uart0(&uart0_pdata);
+        imx31_add_imx_uart4(&uart4_pdata);
 
-        mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
-        mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
+        imx31_add_imx_i2c0(&moboard_i2c0_data);
+        imx31_add_imx_i2c1(&moboard_i2c1_data);
 
-        mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
-        mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
+        imx31_add_spi_imx1(&moboard_spi1_pdata);
+        imx31_add_spi_imx2(&moboard_spi2_pdata);
 
         gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
         gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index bcac84d4dca4..1c30d7212f17 100644
--- a/arch/arm/mach-mx3/mach-mx35pdk.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -12,10 +12,12 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX35 3-Stack Development System
+ *  - i.MX35 Platform Development Kit (i.MX35 PDK)
  */
 
 #include <linux/types.h>
@@ -32,12 +34,12 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx35.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -90,7 +92,7 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx35_add_imx_uart0(&uart_pdata);
 
         mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index cce410662383..8a292dd1a714 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -43,20 +39,17 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/board-pcm037.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
 #include <mach/mmc.h>
 #include <mach/mx3_camera.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "pcm037.h"
 
@@ -225,7 +218,7 @@ static struct platform_device pcm037_flash = {
         .num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -279,16 +272,17 @@ static struct platform_device pcm037_sram_device = {
         .resource = &pcm038_sram_resource,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_1_data = {
+static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_2_data = {
+static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
         .bitrate = 20000,
 };
 
@@ -545,6 +539,7 @@ static struct platform_device pcm970_sja1000 = {
         .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
 };
 
+#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -554,6 +549,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -581,7 +577,6 @@ __setup("otg_mode=", pcm037_otg_mode);
 static void __init mxc_board_init(void)
 {
         int ret;
-        u32 tmp;
 
         mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 
@@ -614,9 +609,10 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
+        imx31_add_imx_uart1(&uart_pdata);
+        imx31_add_imx_uart2(&uart_pdata);
 
         mxc_register_device(&mxc_w1_master_device, NULL);
 
@@ -634,10 +630,10 @@ static void __init mxc_board_init(void)
         i2c_register_board_info(1, pcm037_i2c_devices,
                         ARRAY_SIZE(pcm037_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
-        mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
+        imx31_add_imx_i2c1(&pcm037_i2c1_data);
+        imx31_add_imx_i2c2(&pcm037_i2c2_data);
 
-        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+        imx31_add_mxc_nand(&pcm037_nand_board_info);
         mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index 8d386000fc40..c8b98218efee 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -13,9 +13,6 @@
 #include <linux/spi/spi.h>
 
 #include <mach/common.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
 #include <mach/iomux-mx3.h>
 
 #include <asm/mach-types.h>
@@ -64,7 +61,7 @@ static struct spi_board_info pcm037_spi_dev[] = {
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
 
-struct spi_imx_master pcm037_spi1_master = {
+static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
         .chipselect = pcm037_spi1_cs,
         .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
 };
@@ -184,7 +181,7 @@ static int eet_init_devices(void)
         /* SPI */
         spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-        mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master);
+        imx35_add_spi_imx0(&pcm037_spi1_pdata);
 #endif
 
         platform_device_register(&pcm037_gpio_keys_device);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 78d9185a9d4b..47f5311b301a 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -40,19 +36,15 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-#include <mach/i2c.h>
-#endif
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
 static const struct fb_videomode fb_modedb[] = {
@@ -122,12 +114,12 @@ static struct platform_device pcm043_flash = {
         .num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-static struct imxi2c_platform_data pcm043_i2c_1_data = {
+static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
         .bitrate = 50000,
 };
 
@@ -222,6 +214,9 @@ static struct pad_desc pcm043_pads[] = {
         MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
         MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
         MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+        /* CAN2 */
+        MX35_PAD_TX5_RX0__CAN2_TXCAN,
+        MX35_PAD_TX4_RX1__CAN2_RXCAN,
 };
 
 #define AC97_GPIO_TXFS  (1 * 32 + 31)
@@ -304,11 +299,13 @@ static struct imx_ssi_platform_data pcm043_ssi_pdata = {
         .flags = IMX_SSI_USE_AC97,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
 
+#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata = {
         .portsc = MXC_EHCI_MODE_UTMI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -319,6 +316,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
         .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                   MXC_EHCI_IPPUE_DOWN,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -361,17 +359,17 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+        imx35_add_imx_uart0(&uart_pdata);
+        imx35_add_mxc_nand(&pcm037_nand_board_info);
         mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx35_add_imx_uart1(&uart_pdata);
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
         i2c_register_board_info(0, pcm043_i2c_devices,
                         ARRAY_SIZE(pcm043_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
+        imx35_add_imx_i2c0(&pcm043_i2c0_data);
 #endif
 
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
@@ -390,6 +388,7 @@ static void __init mxc_board_init(void)
         if (!otg_mode_host)
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 
+        imx35_add_flexcan1(NULL);
 }
 
 static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index e5b5b8323a17..d44ac70222a5 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -34,9 +30,9 @@
 #include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <mach/board-qong.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
 /* FPGA defines */
@@ -62,7 +58,7 @@
  * This file contains the board-specific initialization routines.
  */
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -73,11 +69,11 @@ static int uart_pins[] = {
         MX31_PIN_RXD1__RXD1
 };
 
-static inline void mxc_init_imx_uart(void)
+static inline void __init mxc_init_imx_uart(void)
 {
         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
                         "uart-0");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
 }
 
 static struct resource dnet_resources[] = {
@@ -116,7 +112,7 @@ static struct physmap_flash_data qong_flash_data = {
 
 static struct resource qong_flash_resource = {
         .start = MX31_CS0_BASE_ADDR,
-        .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
+        .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
         .flags = IORESOURCE_MEM,
 };
 
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 6858a4f9806c..20e48c0195c4 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
@@ -97,9 +93,12 @@ void __init mx35_map_io(void)
 }
 #endif
 
+int imx3x_register_gpios(void);
+
 void __init mx31_init_irq(void)
 {
         mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+        imx3x_register_gpios();
 }
 
 void __init mx35_init_irq(void)
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 7aebd74a12e8..827fd3c80201 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
@@ -36,13 +32,13 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
 #include <mach/mmc.h>
 #include <mach/mx3fb.h>
 #include <mach/ipu.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -96,7 +92,7 @@ static unsigned int lilly_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -217,9 +213,9 @@ void __init mx31lilly_db_init(void)
         mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
                                         ARRAY_SIZE(lilly_db_board_pins),
                                         "development board pins");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
+        imx31_add_imx_uart2(&uart_pdata);
         mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
         mx31lilly_init_fb();
 }
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 5f05bfbec380..7b0e74e275ba 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
@@ -37,12 +33,11 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lite.h>
 #include <mach/mmc.h>
-#include <mach/spi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -76,7 +71,7 @@ static unsigned int litekit_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -161,7 +156,7 @@ static int spi_internal_chipselect[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
         .chipselect     = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -201,9 +196,9 @@ void __init mx31lite_db_init(void)
         mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
                                         ARRAY_SIZE(litekit_db_board_pins),
                                         "development board pins");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
         mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
-        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+        imx31_add_spi_imx0(&spi0_pdata);
         platform_device_register(&litekit_led_device);
         mxc_register_device(&imx_wdt_device0, NULL);
         mxc_register_device(&imx_rtc_device0, NULL);
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 582299cb2c08..fc395a7a8599 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
@@ -27,13 +23,13 @@
 #include <linux/usb/otg.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int devboard_pins[] = {
@@ -56,7 +52,7 @@ static unsigned int devboard_pins[] = {
         MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -230,7 +226,7 @@ void __init mx31moboard_devboard_init(void)
         mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
                 "devboard");
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
 
         mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
 
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 4930f8c27e66..0551eb39d97e 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 293eea6d9d97..40c3e7564cb6 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -30,7 +26,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31moboard.h>
 #include <mach/mxc_ehci.h>
@@ -38,6 +33,7 @@
 
 #include <media/soc_camera.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int smartbot_pins[] = {
@@ -59,7 +55,7 @@ static unsigned int smartbot_pins[] = {
         MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -183,8 +179,7 @@ void __init mx31moboard_smartbot_init(int board)
         mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
                 "smartbot");
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-
+        imx31_add_imx_uart1(&uart_pdata);
 
         switch (board) {
         case MX31SMARTBOT:
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51e676c..0848db5dd364 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,31 @@ config MACH_MX51_BABBAGE
           u-boot. This includes specific configurations for the board and its
           peripherals.
 
+config MACH_MX51_3DS
+        bool "Support MX51PDK (3DS)"
+        select MXC_DEBUG_BOARD
+        help
+          Include support for MX51PDK (3DS) platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX51
+        bool "Support Eukrea CPUIMX51 module"
+        help
+          Include support for Eukrea CPUIMX51 platform. This includes
+          specific configurations for the module and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX51
+        default MACH_EUKREA_MBIMX51_BASEBOARD
+
+config MACH_EUKREA_MBIMX51_BASEBOARD
+        prompt "Eukrea MBIMX51 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMX51 evaluation board.
+
+endchoice
+
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f869ef51..86c66e7f52f3 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,6 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
new file mode 100644
index 000000000000..623607a20f57
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -0,0 +1,293 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * based on board-mx51_babbage.c which is
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices.h"
+
+#define CPUIMX51_USBH1_STP      (0*32 + 27)
+#define CPUIMX51_QUARTA_GPIO    (2*32 + 28)
+#define CPUIMX51_QUARTB_GPIO    (2*32 + 25)
+#define CPUIMX51_QUARTC_GPIO    (2*32 + 26)
+#define CPUIMX51_QUARTD_GPIO    (2*32 + 27)
+#define CPUIMX51_QUARTA_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
+#define CPUIMX51_QUARTB_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
+#define CPUIMX51_QUARTC_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
+#define CPUIMX51_QUARTD_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
+#define CPUIMX51_QUART_XTAL     14745600
+#define CPUIMX51_QUART_REGSHIFT 17
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET          0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
+
+#define MX51_USB_PLLDIV_12_MHZ          0x00
+#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define MX51_USB_PLL_DIV_24_MHZ         0x02
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
+                .irq = CPUIMX51_QUARTA_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
+                .irq = CPUIMX51_QUARTB_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
+                .irq = CPUIMX51_QUARTC_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
+                .irq = CPUIMX51_QUARTD_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+        }
+};
+
+static struct platform_device serial_device = {
+        .name = "serial8250",
+        .id = 0,
+        .dev = {
+                .platform_data = serial_platform_data,
+        },
+};
+#endif
+
+static struct platform_device *devices[] __initdata = {
+        &mxc_fec_device,
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        &serial_device,
+#endif
+};
+
+static struct pad_desc eukrea_cpuimx51_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+
+        /* I2C2 */
+        MX51_PAD_GPIO_1_2__I2C2_SCL,
+        MX51_PAD_GPIO_1_3__I2C2_SDA,
+        MX51_PAD_NANDF_D10__GPIO_3_30,
+
+        /* QUART IRQ */
+        MX51_PAD_NANDF_D15__GPIO_3_25,
+        MX51_PAD_NANDF_D14__GPIO_3_26,
+        MX51_PAD_NANDF_D13__GPIO_3_27,
+        MX51_PAD_NANDF_D12__GPIO_3_28,
+
+        /* USB HOST1 */
+        MX51_PAD_USBH1_CLK__USBH1_CLK,
+        MX51_PAD_USBH1_DIR__USBH1_DIR,
+        MX51_PAD_USBH1_NXT__USBH1_NXT,
+        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+        MX51_PAD_USBH1_STP__USBH1_STP,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
+        .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_19_2_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* The clock for the USBH1 ULPI port will come externally from the PHY. */
+        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init           = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static struct mxc_usbh_platform_data usbh1_config = {
+        .init           = initialize_usbh1_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx51_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init eukrea_cpuimx51_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
+                                        ARRAY_SIZE(eukrea_cpuimx51_pads));
+
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
+        gpio_direction_input(CPUIMX51_QUARTA_GPIO);
+        gpio_free(CPUIMX51_QUARTA_GPIO);
+        gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
+        gpio_direction_input(CPUIMX51_QUARTB_GPIO);
+        gpio_free(CPUIMX51_QUARTB_GPIO);
+        gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
+        gpio_direction_input(CPUIMX51_QUARTC_GPIO);
+        gpio_free(CPUIMX51_QUARTC_GPIO);
+        gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
+        gpio_direction_input(CPUIMX51_QUARTD_GPIO);
+        gpio_free(CPUIMX51_QUARTD_GPIO);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
+        i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
+                                ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
+
+        if (otg_mode_host)
+                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        else {
+                initialize_otg_port(NULL);
+                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+        }
+        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
+        eukrea_mbimx51_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx51_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = eukrea_cpuimx51_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
+        /* Maintainer: Eric Bénard <eric@eukrea.com> */
+        .phys_io = MX51_AIPS1_BASE_ADDR,
+        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params = PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine = eukrea_cpuimx51_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 000000000000..f95c2fd94667
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/imx-uart.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices.h"
+
+#define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+static struct pad_desc mx51_3ds_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+
+        /* UART2 */
+        MX51_PAD_UART2_RXD__UART2_RXD,
+        MX51_PAD_UART2_TXD__UART2_TXD,
+        MX51_PAD_EIM_D25__UART2_CTS,
+        MX51_PAD_EIM_D26__UART2_RTS,
+
+        /* UART3 */
+        MX51_PAD_UART3_RXD__UART3_RXD,
+        MX51_PAD_UART3_TXD__UART3_TXD,
+        MX51_PAD_EIM_D24__UART3_CTS,
+        MX51_PAD_EIM_D27__UART3_RTS,
+
+        /* CPLD PARENT IRQ PIN */
+        MX51_PAD_GPIO_1_6__GPIO_1_6,
+
+        /* KPP */
+        MX51_PAD_KEY_ROW0__KEY_ROW0,
+        MX51_PAD_KEY_ROW1__KEY_ROW1,
+        MX51_PAD_KEY_ROW2__KEY_ROW2,
+        MX51_PAD_KEY_ROW3__KEY_ROW3,
+        MX51_PAD_KEY_COL0__KEY_COL0,
+        MX51_PAD_KEY_COL1__KEY_COL1,
+        MX51_PAD_KEY_COL2__KEY_COL2,
+        MX51_PAD_KEY_COL3__KEY_COL3,
+        MX51_PAD_KEY_COL4__KEY_COL4,
+        MX51_PAD_KEY_COL5__KEY_COL5,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+        KEY(0, 0, KEY_1),
+        KEY(0, 1, KEY_2),
+        KEY(0, 2, KEY_3),
+        KEY(0, 3, KEY_F1),
+        KEY(0, 4, KEY_UP),
+        KEY(0, 5, KEY_F2),
+
+        KEY(1, 0, KEY_4),
+        KEY(1, 1, KEY_5),
+        KEY(1, 2, KEY_6),
+        KEY(1, 3, KEY_LEFT),
+        KEY(1, 4, KEY_SELECT),
+        KEY(1, 5, KEY_RIGHT),
+
+        KEY(2, 0, KEY_7),
+        KEY(2, 1, KEY_8),
+        KEY(2, 2, KEY_9),
+        KEY(2, 3, KEY_F3),
+        KEY(2, 4, KEY_DOWN),
+        KEY(2, 5, KEY_F4),
+
+        KEY(3, 0, KEY_0),
+        KEY(3, 1, KEY_OK),
+        KEY(3, 2, KEY_ESC),
+        KEY(3, 3, KEY_ENTER),
+        KEY(3, 4, KEY_MENU),
+        KEY(3, 5, KEY_BACK)
+};
+
+static struct matrix_keymap_data mx51_3ds_map_data = {
+        .keymap         = mx51_3ds_board_keymap,
+        .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+        mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+                                        ARRAY_SIZE(mx51_3ds_pads));
+        mxc_init_imx_uart();
+
+        if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+                printk(KERN_WARNING "Init of the debugboard failed, all "
+                                    "devices on the board are unusable.\n");
+
+        mxc_init_keypad();
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io = MX51_AIPS1_BASE_ADDR,
+        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params = PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine = mxc_board_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ed885f9d7b73..6e384d92e625 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -12,6 +12,7 @@
 
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -21,6 +22,7 @@
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -64,6 +66,18 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_EIM_D27__UART3_RTS,
         MX51_PAD_EIM_D24__UART3_CTS,
 
+        /* I2C1 */
+        MX51_PAD_EIM_D16__I2C1_SDA,
+        MX51_PAD_EIM_D19__I2C1_SCL,
+
+        /* I2C2 */
+        MX51_PAD_KEY_COL4__I2C2_SCL,
+        MX51_PAD_KEY_COL5__I2C2_SDA,
+
+        /* HSI2C */
+        MX51_PAD_I2C1_CLK__HSI2C_CLK,
+        MX51_PAD_I2C1_DAT__HSI2C_DAT,
+
         /* USB HOST1 */
         MX51_PAD_USBH1_CLK__USBH1_CLK,
         MX51_PAD_USBH1_DIR__USBH1_DIR,
@@ -78,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
         /* USB HUB reset line*/
-        MX51_PAD_GPIO_1_7__GPIO1_7,
+        MX51_PAD_GPIO_1_7__GPIO_1_7,
 };
 
 /* Serial ports */
@@ -99,6 +113,14 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
+static struct imxi2c_platform_data babbage_i2c_data = {
+        .bitrate = 100000,
+};
+
+static struct imxi2c_platform_data babbage_hsi2c_data = {
+        .bitrate = 400000,
+};
+
 static int gpio_usbh1_active(void)
 {
         struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
@@ -230,6 +252,10 @@ static void __init mxc_board_init(void)
         mxc_init_imx_uart();
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
+        mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
+        mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
+        mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
+
         if (otg_mode_host)
                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
         else {
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d3370e..6af69def357f 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
         .parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+        .id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)     \
         static struct clk name = {                      \
                 .id             = i,                    \
@@ -798,6 +802,14 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
+/* I2C */
+DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+
 /* FEC */
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
@@ -815,12 +827,16 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
         _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+        _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449aacdc..1920ff4963b2 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -93,6 +93,64 @@ struct platform_device mxc_fec_device = {
         .resource = mxc_fec_resources,
 };
 
+static struct resource mxc_i2c0_resources[] = {
+        {
+                .start = MX51_I2C1_BASE_ADDR,
+                .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MX51_MXC_INT_I2C1,
+                .end = MX51_MXC_INT_I2C1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_i2c_device0 = {
+        .name = "imx-i2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
+        .resource = mxc_i2c0_resources,
+};
+
+static struct resource mxc_i2c1_resources[] = {
+        {
+                .start = MX51_I2C2_BASE_ADDR,
+                .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MX51_MXC_INT_I2C2,
+                .end = MX51_MXC_INT_I2C2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_i2c_device1 = {
+        .name = "imx-i2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
+        .resource = mxc_i2c1_resources,
+};
+
+static struct resource mxc_hsi2c_resources[] = {
+        {
+                .start = MX51_HSI2C_DMA_BASE_ADDR,
+                .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MX51_MXC_INT_HS_I2C,
+                .end = MX51_MXC_INT_HS_I2C,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_hsi2c_device = {
+        .name = "imx-i2c",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
+        .resource = mxc_hsi2c_resources
+};
+
 static u64 usb_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource usbotg_resources[] = {
@@ -168,34 +226,57 @@ struct platform_device mxc_wdt = {
         .resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+        {
+                .start = MX51_MXC_INT_KPP,
+                .end = MX51_MXC_INT_KPP,
+                .flags = IORESOURCE_IRQ,
+        } , {
+                .start = MX51_KPP_BASE_ADDR,
+                .end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_keypad_device = {
+        .name = "imx-keypad",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_kpp_resources),
+        .resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
         {
                 .chip.label = "gpio-0",
                 .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO1_LOW,
+                .irq_high = MX51_MXC_INT_GPIO1_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START
         },
         {
                 .chip.label = "gpio-1",
                 .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO2_LOW,
+                .irq_high = MX51_MXC_INT_GPIO2_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
         },
         {
                 .chip.label = "gpio-2",
                 .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO3_LOW,
+                .irq_high = MX51_MXC_INT_GPIO3_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
         },
         {
                 .chip.label = "gpio-3",
                 .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO4_LOW,
+                .irq_high = MX51_MXC_INT_GPIO4_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
         },
 };
 
-int __init mxc_register_gpios(void)
+int __init imx51_register_gpios(void)
 {
         return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae71cd5b..e509cfaad1d4 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,7 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_hsi2c_device;
+extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
new file mode 100644
index 000000000000..ffa93d1d6ef8
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -0,0 +1,200 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/leds.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/mach/arch.h>
+
+#include "devices.h"
+
+#define MBIMX51_TSC2007_GPIO    (2*32 + 30)
+#define MBIMX51_TSC2007_IRQ     (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
+#define MBIMX51_LED0            (2*32 + 5)
+#define MBIMX51_LED1            (2*32 + 6)
+#define MBIMX51_LED2            (2*32 + 7)
+#define MBIMX51_LED3            (2*32 + 8)
+
+static struct gpio_led mbimx51_leds[] = {
+        {
+                .name                   = "led0",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED0,
+        },
+        {
+                .name                   = "led1",
+                .default_trigger        = "nand-disk",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED1,
+        },
+        {
+                .name                   = "led2",
+                .default_trigger        = "mmc0",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED2,
+        },
+        {
+                .name                   = "led3",
+                .default_trigger        = "default-on",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED3,
+        },
+};
+
+static struct gpio_led_platform_data mbimx51_leds_info = {
+        .leds           = mbimx51_leds,
+        .num_leds       = ARRAY_SIZE(mbimx51_leds),
+};
+
+static struct platform_device mbimx51_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &mbimx51_leds_info,
+        },
+};
+
+static struct platform_device *devices[] __initdata = {
+        &mbimx51_leds_gpio,
+};
+
+static struct pad_desc mbimx51_pads[] = {
+        /* UART2 */
+        MX51_PAD_UART2_RXD__UART2_RXD,
+        MX51_PAD_UART2_TXD__UART2_TXD,
+
+        /* UART3 */
+        MX51_PAD_UART3_RXD__UART3_RXD,
+        MX51_PAD_UART3_TXD__UART3_TXD,
+        MX51_PAD_KEY_COL4__UART3_RTS,
+        MX51_PAD_KEY_COL5__UART3_CTS,
+
+        /* TSC2007 IRQ */
+        MX51_PAD_NANDF_D10__GPIO_3_30,
+
+        /* LEDS */
+        MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
+        MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
+        MX51_PAD_DISPB2_SER_CLK__GPIO_3_7,
+        MX51_PAD_DISPB2_SER_RS__GPIO_3_8,
+
+        /* KPP */
+        MX51_PAD_KEY_ROW0__KEY_ROW0,
+        MX51_PAD_KEY_ROW1__KEY_ROW1,
+        MX51_PAD_KEY_ROW2__KEY_ROW2,
+        MX51_PAD_KEY_ROW3__KEY_ROW3,
+        MX51_PAD_KEY_COL0__KEY_COL0,
+        MX51_PAD_KEY_COL1__KEY_COL1,
+        MX51_PAD_KEY_COL2__KEY_COL2,
+        MX51_PAD_KEY_COL3__KEY_COL3,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int mbimx51_keymap[] = {
+        KEY(0, 0, KEY_1),
+        KEY(0, 1, KEY_2),
+        KEY(0, 2, KEY_3),
+        KEY(0, 3, KEY_UP),
+
+        KEY(1, 0, KEY_4),
+        KEY(1, 1, KEY_5),
+        KEY(1, 2, KEY_6),
+        KEY(1, 3, KEY_LEFT),
+
+        KEY(2, 0, KEY_7),
+        KEY(2, 1, KEY_8),
+        KEY(2, 2, KEY_9),
+        KEY(2, 3, KEY_RIGHT),
+
+        KEY(3, 0, KEY_0),
+        KEY(3, 1, KEY_DOWN),
+        KEY(3, 2, KEY_ESC),
+        KEY(3, 3, KEY_ENTER),
+};
+
+static struct matrix_keymap_data mbimx51_map_data = {
+        .keymap         = mbimx51_keymap,
+        .keymap_size    = ARRAY_SIZE(mbimx51_keymap),
+};
+
+static int tsc2007_get_pendown_state(void)
+{
+        return !gpio_get_value(MBIMX51_TSC2007_GPIO);
+}
+
+struct tsc2007_platform_data tsc2007_data = {
+        .model = 2007,
+        .x_plate_ohms = 180,
+        .get_pendown_state = tsc2007_get_pendown_state,
+};
+
+static struct i2c_board_info mbimx51_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tsc2007", 0x48),
+                .irq  = MBIMX51_TSC2007_IRQ,
+                .platform_data = &tsc2007_data,
+        },
+};
+
+/*
+ * baseboard initialization.
+ */
+void __init eukrea_mbimx51_baseboard_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
+                                        ARRAY_SIZE(mbimx51_pads));
+
+        mxc_register_device(&mxc_uart_device1, NULL);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+
+        gpio_request(MBIMX51_LED0, "LED0");
+        gpio_direction_output(MBIMX51_LED0, 1);
+        gpio_free(MBIMX51_LED0);
+        gpio_request(MBIMX51_LED1, "LED1");
+        gpio_direction_output(MBIMX51_LED1, 1);
+        gpio_free(MBIMX51_LED1);
+        gpio_request(MBIMX51_LED2, "LED2");
+        gpio_direction_output(MBIMX51_LED2, 1);
+        gpio_free(MBIMX51_LED2);
+        gpio_request(MBIMX51_LED3, "LED3");
+        gpio_direction_output(MBIMX51_LED3, 1);
+        gpio_free(MBIMX51_LED3);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        mxc_register_device(&mxc_keypad_device, &mbimx51_map_data);
+
+        gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
+        gpio_direction_input(MBIMX51_TSC2007_GPIO);
+        set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
+        i2c_register_board_info(1, mbimx51_i2c_devices,
+                                ARRAY_SIZE(mbimx51_i2c_devices));
+}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index b7677ef80cc4..bc3f30db8d9a 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -65,6 +65,8 @@ void __init mx51_map_io(void)
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx51_register_gpios(void);
+
 void __init mx51_init_irq(void)
 {
         unsigned long tzic_addr;
@@ -80,4 +82,5 @@ void __init mx51_init_irq(void)
                 panic("unable to map TZIC interrupt controller\n");
 
         tzic_init_irq(tzic_virt);
+        imx51_register_gpios();
 }
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
index ce4f59058189..b989baccd675 100644
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -11,11 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
index 353bd977b393..027af4f0d18a 100644
--- a/arch/arm/mach-mxc91231/devices.c
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -135,7 +135,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
         },
 };
 
-int __init mxc_register_gpios(void)
+int __init mxc91231_register_gpios(void)
 {
         return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 6becda3ff331..aeccfd755fee 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -15,11 +15,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #include <linux/mm.h>
@@ -88,7 +83,10 @@ void __init mxc91231_map_io(void)
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int mxc91231_register_gpios(void);
+
 void __init mxc91231_init_irq(void)
 {
+        mxc91231_register_gpios();
         mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
 }
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
index f035f4185274..89f793adf776 100644
--- a/arch/arm/mach-nomadik/clock.c
+++ b/arch/arm/mach-nomadik/clock.c
@@ -53,6 +53,10 @@ static struct clk clk_default;
         }
 
 static struct clk_lookup lookups[] = {
+        {
+                .con_id         = "apb_pclk",
+                .clk            = &clk_default,
+        },
         CLK(&clk_24, "mtu0"),
         CLK(&clk_24, "mtu1"),
         CLK(&clk_48, "uart0"),
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index fdd1dd53fa9c..0a9d61d2d229 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -301,6 +301,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = ams_delta_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = ams_delta_init_irq,
         .init_machine   = ams_delta_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 096f2ed102cb..059bac60b35a 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -378,6 +378,7 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_fsample_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_fsample_init_irq,
         .init_machine   = omap_fsample_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e1195a3467b8..7a65684d2a15 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -98,6 +98,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_generic_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_generic_init_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index d1100e4f65ac..68b2beda8b99 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -467,6 +467,7 @@ MACHINE_START(OMAP_H2, "TI-H2")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = h2_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = h2_init_irq,
         .init_machine   = h2_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index a53ab8297d25..0b0825fe6751 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -437,6 +437,7 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = h3_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = h3_init_irq,
         .init_machine   = h3_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 8e313b4b99a9..d70a4f0923f5 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -304,6 +304,7 @@ MACHINE_START(HERALD, "HTC Herald")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = htcherald_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = htcherald_init_irq,
         .init_machine   = htcherald_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 5d12fd35681b..91064b37859a 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -463,6 +463,7 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = innovator_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = innovator_init_irq,
         .init_machine   = innovator_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 71e1a3fad0ea..8c28b10f3dae 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -400,6 +400,7 @@ MACHINE_START(NOKIA770, "Nokia 770")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_nokia770_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_nokia770_init_irq,
         .init_machine   = omap_nokia770_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 80d862001def..e2a72af30890 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -584,6 +584,7 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = osk_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = osk_init_irq,
         .init_machine   = osk_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 569b4c9085cd..61a2321b9732 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -373,6 +373,7 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_palmte_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_palmte_init_irq,
         .init_machine   = omap_palmte_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 6ad49a2cc1a0..21c01c6afcc1 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -321,6 +321,7 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_palmtt_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_palmtt_init_irq,
         .init_machine   = omap_palmtt_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 6641de9257ef..f32492451533 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -338,10 +338,12 @@ omap_palmz71_map_io(void)
 }
 
 MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
-        .phys_io = 0xfff00000,
-        .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
-        .boot_params = 0x10000100,.map_io = omap_palmz71_map_io,
-        .init_irq = omap_palmz71_init_irq,
-        .init_machine = omap_palmz71_init,
-        .timer = &omap_timer,
+        .phys_io        = 0xfff00000,
+        .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
+        .boot_params    = 0x10000100,
+        .map_io         = omap_palmz71_map_io,
+        .reserve        = omap_reserve,
+        .init_irq       = omap_palmz71_init_irq,
+        .init_machine   = omap_palmz71_init,
+        .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index e854d5741c88..8b5ab1fcc405 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -339,6 +339,7 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_perseus2_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_perseus2_init_irq,
         .init_machine   = omap_perseus2_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2fb1e5f8e2ec..995566b862bb 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -423,7 +423,8 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = omap_sx1_map_io,
-        .init_irq               = omap_sx1_init_irq,
+        .reserve        = omap_reserve,
+        .init_irq       = omap_sx1_init_irq,
         .init_machine   = omap_sx1_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 87b9436fe7c0..4c483dc1de5c 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -287,6 +287,7 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
         .boot_params    = 0x10000100,
         .map_io         = voiceblue_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = voiceblue_init_irq,
         .init_machine   = voiceblue_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index d9b8d82530ae..0ce3fec2d257 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -22,7 +22,6 @@
 
 extern void omap_check_revision(void);
 extern void omap_sram_init(void);
-extern void omapfb_reserve_sdram(void);
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -122,7 +121,6 @@ void __init omap1_map_common_io(void)
 #endif
 
         omap_sram_init();
-        omapfb_reserve_sdram();
 }
 
 /*
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index a11a575745e4..42f49f785c93 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -248,6 +248,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_2430sdp_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_2430sdp_init_irq,
         .init_machine   = omap_2430sdp_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index f474a80b8867..dd9c03171a19 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -815,6 +815,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_3430sdp_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_3430sdp_init_irq,
         .init_machine   = omap_3430sdp_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 504d2bd222fe..57290fb3fcd7 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -108,6 +108,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_sdp_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_sdp_init_irq,
         .init_machine   = omap_sdp_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index e4a5d66b83b8..4bb2c5d151ec 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -402,6 +402,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_4430sdp_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_4430sdp_init_irq,
         .init_machine   = omap_4430sdp_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index af383a876943..7da92defcde0 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -472,6 +472,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
         .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = am3517_evm_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = am3517_evm_init_irq,
         .init_machine   = am3517_evm_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index aa69fb999748..bd75642aee65 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -346,6 +346,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_apollon_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_apollon_init_irq,
         .init_machine   = omap_apollon_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e679a2cc86c3..bc4c3f807068 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -837,6 +837,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
         .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = cm_t35_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = cm_t35_init_irq,
         .init_machine   = cm_t35_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 77022b588816..922b7464807f 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -825,6 +825,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
         .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = devkit8000_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = devkit8000_init_irq,
         .init_machine   = devkit8000_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 16cc06860670..9242902d3a43 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -59,6 +59,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_generic_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_generic_init_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 0665f2c8dc8e..16703fdb3515 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -378,6 +378,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_h4_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_h4_init_irq,
         .init_machine   = omap_h4_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index d55c57b761a9..759e39d1a702 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -543,6 +543,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = igep2_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = igep2_init_irq,
         .init_machine   = igep2_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index fefd7e6e9779..9cd2669113e4 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -417,6 +417,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_ldp_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_ldp_init_irq,
         .init_machine   = omap_ldp_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 3ccc34ebdcc7..2565ff08a221 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -667,6 +667,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = n8x0_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = n8x0_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
@@ -677,6 +678,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = n8x0_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = n8x0_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
@@ -687,6 +689,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = n8x0_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = n8x0_init_irq,
         .init_machine   = n8x0_init_machine,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 69b154cdc75d..0ab0c26db4dd 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -519,6 +519,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_beagle_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap3_beagle_init_irq,
         .init_machine   = omap3_beagle_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b95261013812..a3d2e285e116 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -727,6 +727,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_evm_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap3_evm_init_irq,
         .init_machine   = omap3_evm_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index db06dc910ba7..c0f4f12eba54 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -601,6 +601,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3pandora_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap3pandora_init_irq,
         .init_machine   = omap3pandora_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 2f5f8233dd5b..f05b867c5851 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -571,6 +571,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
         .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap3_touchbook_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap3_touchbook_init_irq,
         .init_machine   = omap3_touchbook_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 79ac41400c21..87acb2f198ec 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -495,6 +495,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = overo_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = overo_init_irq,
         .init_machine   = overo_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 1b86b5bb87a2..3bd956f9e19f 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -154,6 +154,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
         .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = rx51_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = rx51_init_irq,
         .init_machine   = rx51_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 803ef14cbf2d..ffe188cb18e9 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -95,6 +95,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
         .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_zoom2_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_zoom2_init_irq,
         .init_machine   = omap_zoom2_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index 33147042485f..5b605eba3e7b 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -77,6 +77,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
         .io_pg_offst    = (ZOOM_UART_VIRT >> 18) & 0xfffc,
         .boot_params    = 0x80000100,
         .map_io         = omap_zoom_map_io,
+        .reserve        = omap_reserve,
         .init_irq       = omap_zoom_init_irq,
         .init_machine   = omap_zoom_init,
         .timer          = &omap_timer,
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 41b155acfca7..d33744117ce2 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3166,6 +3166,10 @@ static struct clk uart4_ick_am35xx = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .ops            = &clkops_null,
+};
 
 /*
  * clkdev
@@ -3173,6 +3177,7 @@ static struct clk uart4_ick_am35xx = {
 
 /* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
+        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index b32ccd954a1b..ed8d330522f1 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -463,7 +463,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
         }
         if (!ret) {
                 /*
-                 * Switch the parent clock in the heirarchy, and make sure
+                 * Switch the parent clock in the hierarchy, and make sure
                  * that the new parent's usecount is correct.  Note: we
                  * enable the new parent before disabling the old to avoid
                  * any unnecessary hardware disable->enable transitions.
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3cfb425ea67e..4e1f53d0b880 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,7 +33,6 @@
 #include <plat/sdrc.h>
 #include <plat/gpmc.h>
 #include <plat/serial.h>
-#include <plat/vram.h>
 
 #include "clock2xxx.h"
 #include "clock3xxx.h"
@@ -241,8 +240,6 @@ static void __init _omap2_map_common_io(void)
 
         omap2_check_revision();
         omap_sram_init();
-        omapfb_reserve_sdram();
-        omap_vram_reserve_sdram();
 }
 
 #ifdef CONFIG_ARCH_OMAP2420
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index d522cd70bf53..ba53191ae4c5 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -60,7 +60,7 @@
 #define SDRC_DLLA_CTRL_V        OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
         .text
-/* Function to aquire the semaphore in scratchpad */
+/* Function to acquire the semaphore in scratchpad */
 ENTRY(lock_scratchpad_sem)
         stmfd   sp!, {lr}       @ save registers on stack
 wait_sem:
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 905719a677ae..c897e03e413d 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -26,6 +26,7 @@ config MACH_KUROBOX_PRO
 config MACH_DNS323
         bool "D-Link DNS-323"
         select I2C_BOARDINFO
+        select PHYLIB
         help
           Say 'Y' here if you want your kernel to support the
           D-Link DNS-323 platform.
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index fe0de1698edc..a47100d46a4e 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -3,6 +3,10 @@
  *
  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
  *
+ * Support for HW Rev C1:
+ *
+ * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as
  * published by the Free Software Foundation; either version 2 of the
@@ -23,6 +27,8 @@
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/phy.h>
+#include <linux/marvell_phy.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -31,6 +37,7 @@
 #include "common.h"
 #include "mpp.h"
 
+/* Rev A1 and B1 */
 #define DNS323_GPIO_LED_RIGHT_AMBER     1
 #define DNS323_GPIO_LED_LEFT_AMBER      2
 #define DNS323_GPIO_SYSTEM_UP           3
@@ -42,6 +49,23 @@
 #define DNS323_GPIO_KEY_POWER           9
 #define DNS323_GPIO_KEY_RESET           10
 
+/* Rev C1 */
+#define DNS323C_GPIO_KEY_POWER          1
+#define DNS323C_GPIO_POWER_OFF          2
+#define DNS323C_GPIO_LED_RIGHT_AMBER    8
+#define DNS323C_GPIO_LED_LEFT_AMBER     9
+#define DNS323C_GPIO_LED_POWER          17
+#define DNS323C_GPIO_FAN_BIT1           18
+#define DNS323C_GPIO_FAN_BIT0           19
+
+/* Exposed to userspace, do not change */
+enum {
+        DNS323_REV_A1,  /* 0 */
+        DNS323_REV_B1,  /* 1 */
+        DNS323_REV_C1,  /* 2 */
+};
+
+
 /****************************************************************************
  * PCI setup
  */
@@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = {
         .map_irq        = dns323_pci_map_irq,
 };
 
-static int __init dns323_dev_id(void)
-{
-        u32 dev, rev;
-
-        orion5x_pcie_id(&dev, &rev);
-
-        return dev;
-}
-
 static int __init dns323_pci_init(void)
 {
-        /* The 5182 doesn't really use its PCI bus, and initialising PCI
+        /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
          * gets in the way of initialising the SATA controller.
          */
-        if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID)
+        if (machine_is_dns323() && system_rev == DNS323_REV_A1)
                 pci_common_init(&dns323_pci);
 
         return 0;
@@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void)
         }
 
         iounmap(mac_page);
-        printk("DNS323: Found ethernet MAC address: ");
+        printk("DNS-323: Found ethernet MAC address: ");
         for (i = 0; i < 6; i++)
                 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
 
@@ -259,12 +274,11 @@ static int dns323_gpio_blink_set(unsigned gpio, int state,
         return 0;
 }
 
-static struct gpio_led dns323_leds[] = {
+static struct gpio_led dns323ab_leds[] = {
         {
                 .name = "power:blue",
                 .gpio = DNS323_GPIO_LED_POWER2,
-                .default_trigger = "timer",
-                .active_low = 1,
+                .default_trigger = "default-on",
         }, {
                 .name = "right:amber",
                 .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
@@ -276,9 +290,34 @@ static struct gpio_led dns323_leds[] = {
         },
 };
 
-static struct gpio_led_platform_data dns323_led_data = {
-        .num_leds       = ARRAY_SIZE(dns323_leds),
-        .leds           = dns323_leds,
+
+static struct gpio_led dns323c_leds[] = {
+        {
+                .name = "power:blue",
+                .gpio = DNS323C_GPIO_LED_POWER,
+                .default_trigger = "timer",
+                .active_low = 1,
+        }, {
+                .name = "right:amber",
+                .gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
+                .active_low = 1,
+        }, {
+                .name = "left:amber",
+                .gpio = DNS323C_GPIO_LED_LEFT_AMBER,
+                .active_low = 1,
+        },
+};
+
+
+static struct gpio_led_platform_data dns323ab_led_data = {
+        .num_leds       = ARRAY_SIZE(dns323ab_leds),
+        .leds           = dns323ab_leds,
+        .gpio_blink_set = dns323_gpio_blink_set,
+};
+
+static struct gpio_led_platform_data dns323c_led_data = {
+        .num_leds       = ARRAY_SIZE(dns323c_leds),
+        .leds           = dns323c_leds,
         .gpio_blink_set = dns323_gpio_blink_set,
 };
 
@@ -286,7 +325,7 @@ static struct platform_device dns323_gpio_leds = {
         .name           = "leds-gpio",
         .id             = -1,
         .dev            = {
-                .platform_data  = &dns323_led_data,
+                .platform_data  = &dns323ab_led_data,
         },
 };
 
@@ -294,7 +333,7 @@ static struct platform_device dns323_gpio_leds = {
  * GPIO Attached Keys
  */
 
-static struct gpio_keys_button dns323_buttons[] = {
+static struct gpio_keys_button dns323ab_buttons[] = {
         {
                 .code           = KEY_RESTART,
                 .gpio           = DNS323_GPIO_KEY_RESET,
@@ -308,9 +347,23 @@ static struct gpio_keys_button dns323_buttons[] = {
         },
 };
 
-static struct gpio_keys_platform_data dns323_button_data = {
-        .buttons        = dns323_buttons,
-        .nbuttons       = ARRAY_SIZE(dns323_buttons),
+static struct gpio_keys_platform_data dns323ab_button_data = {
+        .buttons        = dns323ab_buttons,
+        .nbuttons       = ARRAY_SIZE(dns323ab_buttons),
+};
+
+static struct gpio_keys_button dns323c_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = DNS323C_GPIO_KEY_POWER,
+                .desc           = "Power Button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data dns323c_button_data = {
+        .buttons        = dns323c_buttons,
+        .nbuttons       = ARRAY_SIZE(dns323c_buttons),
 };
 
 static struct platform_device dns323_button_device = {
@@ -318,7 +371,7 @@ static struct platform_device dns323_button_device = {
         .id             = -1,
         .num_resources  = 0,
         .dev            = {
-                .platform_data  = &dns323_button_data,
+                .platform_data  = &dns323ab_button_data,
         },
 };
 
@@ -332,7 +385,7 @@ static struct mv_sata_platform_data dns323_sata_data = {
 /****************************************************************************
  * General Setup
  */
-static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
         {  0, MPP_PCIE_RST_OUTn },
         {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
         {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
@@ -356,7 +409,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
         { -1 },
 };
 
-static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
         {  0, MPP_UNUSED },
         {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
         {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
@@ -380,15 +433,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
         { -1 },
 };
 
+static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* ? input */
+        {  1, MPP_GPIO },               /* input power switch (0 = pressed) */
+        {  2, MPP_GPIO },               /* output power off */
+        {  3, MPP_UNUSED },             /* ? output */
+        {  4, MPP_UNUSED },             /* ? output */
+        {  5, MPP_UNUSED },             /* ? output */
+        {  6, MPP_UNUSED },             /* ? output */
+        {  7, MPP_UNUSED },             /* ? output */
+        {  8, MPP_GPIO },               /* i/o right amber LED */
+        {  9, MPP_GPIO },               /* i/o left amber LED */
+        { 10, MPP_GPIO },               /* input */
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },
+        { 13, MPP_SATA_LED },
+        { 14, MPP_SATA_LED },
+        { 15, MPP_SATA_LED },
+        { 16, MPP_UNUSED },
+        { 17, MPP_GPIO },               /* power button LED */
+        { 18, MPP_GPIO },               /* fan speed bit 0 */
+        { 19, MPP_GPIO },               /* fan speed bit 1 */
+        { -1 },
+};
+
+/* Rev C1 Fan speed notes:
+ *
+ * The fan is controlled by 2 GPIOs on this board. The settings
+ * of the bits is as follow:
+ *
+ *  GPIO 18    GPIO 19    Fan
+ *
+ *    0          0        stopped
+ *    0          1        low speed
+ *    1          0        high speed
+ *    1          1        don't do that (*)
+ *
+ * (*) I think the two bits control two feed-in resistors into a fixed
+ *     PWN circuit, setting both bits will basically go a 'bit' faster
+ *     than high speed, but d-link doesn't do it and you may get out of
+ *     HW spec so don't do it.
+ */
+
 /*
- * On the DNS-323 the following devices are attached via I2C:
+ * On the DNS-323 A1 and B1 the following devices are attached via I2C:
  *
  *  i2c addr | chip        | description
  *  0x3e     | GMT G760Af  | fan speed PWM controller
  *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
  *  0x68     | ST M41T80   | RTC w/ alarm
  */
-static struct i2c_board_info __initdata dns323_i2c_devices[] = {
+static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("g760a", 0x3e),
         }, {
@@ -398,36 +493,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
         },
 };
 
+/*
+ * On the DNS-323 C1 the following devices are attached via I2C:
+ *
+ *  i2c addr | chip        | description
+ *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
+ *  0x68     | ST M41T80   | RTC w/ alarm
+ */
+static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("lm75", 0x48),
+        }, {
+                I2C_BOARD_INFO("m41t80", 0x68),
+        },
+};
+
 /* DNS-323 rev. A specific power off method */
 static void dns323a_power_off(void)
 {
-        pr_info("%s: triggering power-off...\n", __func__);
+        pr_info("DNS-323: Triggering power-off...\n");
         gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
 }
 
 /* DNS-323 rev B specific power off method */
 static void dns323b_power_off(void)
 {
-        pr_info("%s: triggering power-off...\n", __func__);
+        pr_info("DNS-323: Triggering power-off...\n");
         /* Pin has to be changed to 1 and back to 0 to do actual power off. */
         gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
         mdelay(100);
         gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
 }
 
+/* DNS-323 rev. C specific power off method */
+static void dns323c_power_off(void)
+{
+        pr_info("DNS-323: Triggering power-off...\n");
+        gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
+}
+
+static int dns323c_phy_fixup(struct phy_device *phy)
+{
+        phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
+
+        return 0;
+}
+
+static int __init dns323_identify_rev(void)
+{
+        u32 dev, rev, i, reg;
+
+        pr_debug("DNS-323: Identifying board ... \n");
+
+        /* Rev A1 has a 5181 */
+        orion5x_pcie_id(&dev, &rev);
+        if (dev == MV88F5181_DEV_ID) {
+                pr_debug("DNS-323: 5181 found, board is A1\n");
+                return DNS323_REV_A1;
+        }
+        pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
+
+        /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
+         * a bit gross but we want to do that without links into the eth
+         * driver so let's poke at it directly. We default to rev B1 in
+         * case the accesses fail
+         */
+
+#define ETH_SMI_REG             (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
+#define  SMI_BUSY               0x10000000
+#define  SMI_READ_VALID         0x08000000
+#define  SMI_OPCODE_READ        0x04000000
+#define  SMI_OPCODE_WRITE       0x00000000
+
+        for (i = 0; i < 1000; i++) {
+                reg = readl(ETH_SMI_REG);
+                if (!(reg & SMI_BUSY))
+                        break;
+        }
+        if (i >= 1000) {
+                pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
+                return DNS323_REV_B1;
+        }
+        writel((3 << 21)        /* phy ID reg */ |
+               (8 << 16)        /* phy addr */ |
+               SMI_OPCODE_READ, ETH_SMI_REG);
+        for (i = 0; i < 1000; i++) {
+                reg = readl(ETH_SMI_REG);
+                if (reg & SMI_READ_VALID)
+                        break;
+        }
+        if (i >= 1000) {
+                pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
+                return DNS323_REV_B1;
+        }
+        pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
+
+        /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
+         * but I don't see that making a difference here, at least with
+         * any known Marvell PHY ID
+         */
+        switch(reg & 0xfff0) {
+        case 0x0cc0: /* MV88E1111 */
+                return DNS323_REV_B1;
+        case 0x0e10: /* MV88E1118 */
+                return DNS323_REV_C1;
+        default:
+                pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
+                           reg & 0xffff);
+        }
+        return DNS323_REV_B1;
+}
+
 static void __init dns323_init(void)
 {
         /* Setup basic Orion functions. Need to be called early. */
         orion5x_init();
 
+        /* Identify revision */
+        system_rev = dns323_identify_rev();
+        pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
+
         /* Just to be tricky, the 5182 has a completely different
          * set of MPP modes to the 5181.
          */
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
-                orion5x_mpp_conf(dns323_mv88f5182_mpp_modes);
-        else {
-                orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
+        switch(system_rev) {
+        case DNS323_REV_A1:
+                orion5x_mpp_conf(dns323a_mpp_modes);
                 writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
+                break;
+        case DNS323_REV_B1:
+                orion5x_mpp_conf(dns323b_mpp_modes);
+                break;
+        case DNS323_REV_C1:
+                orion5x_mpp_conf(dns323c_mpp_modes);
+                break;
         }
 
         /* setup flash mapping
@@ -436,53 +635,96 @@ static void __init dns323_init(void)
         orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
         platform_device_register(&dns323_nor_flash);
 
-        /* The 5181 power LED is active low and requires
-         * DNS323_GPIO_LED_POWER1 to also be low.
-         */
-        if (dns323_dev_id() == MV88F5181_DEV_ID) {
-                dns323_leds[0].active_low = 1;
-                gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
-                gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+        /* Sort out LEDs, Buttons and i2c devices */
+        switch(system_rev) {
+        case DNS323_REV_A1:
+                /* The 5181 power LED is active low and requires
+                 * DNS323_GPIO_LED_POWER1 to also be low.
+                 */
+                 dns323ab_leds[0].active_low = 1;
+                 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
+                 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+                /* Fall through */
+        case DNS323_REV_B1:
+                i2c_register_board_info(0, dns323ab_i2c_devices,
+                                ARRAY_SIZE(dns323ab_i2c_devices));
+                break;
+        case DNS323_REV_C1:
+                /* Hookup LEDs & Buttons */
+                dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
+                dns323_button_device.dev.platform_data = &dns323c_button_data;
+
+                /* Hookup i2c devices and fan driver */
+                i2c_register_board_info(0, dns323c_i2c_devices,
+                                ARRAY_SIZE(dns323c_i2c_devices));
+                platform_device_register_simple("dns323c-fan", 0, NULL, 0);
+
+                /* Register fixup for the PHY LEDs */
+                phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
+                                           MARVELL_PHY_ID_MASK,
+                                           dns323c_phy_fixup);
         }
 
         platform_device_register(&dns323_gpio_leds);
-
         platform_device_register(&dns323_button_device);
 
-        i2c_register_board_info(0, dns323_i2c_devices,
-                                ARRAY_SIZE(dns323_i2c_devices));
-
         /*
          * Configure peripherals.
          */
         if (dns323_read_mac_addr() < 0)
-                printk("DNS323: Failed to read MAC address\n");
-
+                printk("DNS-323: Failed to read MAC address\n");
         orion5x_ehci0_init();
         orion5x_eth_init(&dns323_eth_data);
         orion5x_i2c_init();
         orion5x_uart0_init();
 
-        /* The 5182 has its SATA controller on-chip, and needs its own little
-         * init routine.
-         */
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
+        /* Remaining GPIOs */
+        switch(system_rev) {
+        case DNS323_REV_A1:
+                /* Poweroff GPIO */
+                if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                    gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                        pr_err("DNS-323: failed to setup power-off GPIO\n");
+                pm_power_off = dns323a_power_off;
+                break;
+        case DNS323_REV_B1:
+                /* 5182 built-in SATA init */
                 orion5x_sata_init(&dns323_sata_data);
 
-        /* The 5182 has flag to indicate the system is up. Without this flag
-         * set, power LED will flash and cannot be controlled via leds-gpio.
-         */
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
-                gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1);
-
-        /* Register dns323 specific power-off method */
-        if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
-            gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
-                pr_err("DNS323: failed to setup power-off GPIO\n");
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
+                /* The DNS323 rev B1 has flag to indicate the system is up.
+                 * Without this flag set, power LED will flash and cannot be
+                 * controlled via leds-gpio.
+                 */
+                if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
+                        gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
+
+                /* Poweroff GPIO */
+                if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                    gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                        pr_err("DNS-323: failed to setup power-off GPIO\n");
                 pm_power_off = dns323b_power_off;
-        else
-                pm_power_off = dns323a_power_off;
+                break;
+        case DNS323_REV_C1:
+                /* 5182 built-in SATA init */
+                orion5x_sata_init(&dns323_sata_data);
+
+                /* Poweroff GPIO */
+                if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                    gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
+                        pr_err("DNS-323: failed to setup power-off GPIO\n");
+                pm_power_off = dns323c_power_off;
+
+                /* Now, -this- should theorically be done by the sata_mv driver
+                 * once I figure out what's going on there. Maybe the behaviour
+                 * of the LEDs should be somewhat passed via the platform_data.
+                 * for now, just whack the register and make the LEDs happy
+                 *
+                 * Note: AFAIK, rev B1 needs the same treatement but I'll let
+                 * somebody else test it.
+                 */
+                writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+                break;
+        }
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 60e734c10458..a1d6e46ab035 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd)
          */
         orion5x_setbits(RSTOUTn_MASK, (1 << 2));
         orion5x_setbits(CPU_SOFT_RESET, 1);
+        mdelay(200);
+        orion5x_clrbits(CPU_SOFT_RESET, 1);
 }
 
 
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 161fc2d61207..0f3130599770 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -35,7 +35,7 @@ static int cmx2xx_it8152_irq_gpio;
  * This is really ugly and we need a better way of specifying
  * DMA-capable regions of memory.
  */
-void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size,
+void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
         unsigned long *zhole_size)
 {
         unsigned int sz = SZ_64M >> PAGE_SHIFT;
@@ -46,7 +46,7 @@ void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size,
                 /*
                  * Only adjust if > 64M on current system
                  */
-                if (node || (zone_size[0] <= sz))
+                if (zone_size[0] <= sz)
                         return;
 
                 zone_size[1] = zone_size[0] - sz;
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 51ffa6afb675..461ba4080155 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -715,7 +715,6 @@ static void __init fixup_corgi(struct machine_desc *desc,
         sharpsl_save_param();
         mi->nr_banks=1;
         mi->bank[0].start = 0xa0000000;
-        mi->bank[0].node = 0;
         if (machine_is_corgi())
                 mi->bank[0].size = (32*1024*1024);
         else
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 96ed13081639..a0ab3082a000 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -34,7 +34,6 @@ void __init eseries_fixup(struct machine_desc *desc,
 {
         mi->nr_banks=1;
         mi->bank[0].start = 0xa0000000;
-        mi->bank[0].node = 0;
         if (machine_is_e800())
                 mi->bank[0].size = (128*1024*1024);
         else
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 890fb90a672f..c6305c5b8a72 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -26,8 +26,7 @@ extern unsigned int get_clk_frequency_khz(int info);
 
 #define SET_BANK(__nr,__start,__size) \
         mi->bank[__nr].start = (__start), \
-        mi->bank[__nr].size = (__size), \
-        mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
+        mi->bank[__nr].size = (__size)
 
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index f626730ee42e..92361a66b223 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -17,24 +17,11 @@
  */
 #define PHYS_OFFSET     UL(0xa0000000)
 
-/*
- * The nodes are matched with the physical SDRAM banks as follows:
- *
- *      node 0:  0xa0000000-0xa3ffffff  -->  0xc0000000-0xc3ffffff
- *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
- *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
- *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
- *
- * This needs a node mem size of 26 bits.
- */
-#define NODE_MEM_SIZE_BITS      26
-
 #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
-                             unsigned long *holes);
+void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
 
-#define arch_adjust_zones(node, size, holes) \
-        cmx2xx_pci_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+        cmx2xx_pci_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_64M - 1)
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_64M)
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5305a3993e69..5e92d84fe50d 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -21,6 +21,7 @@
 #include <linux/irq.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/memblock.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
@@ -396,6 +397,11 @@ static void __init palmt5_udc_init(void)
         }
 }
 
+static void __init palmt5_reserve(void)
+{
+        memblock_reserve(0xa0200000, 0x1000);
+}
+
 static void __init palmt5_init(void)
 {
         pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config));
@@ -421,6 +427,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .reserve        = palmt5_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmt5_init
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index d8b4469607a1..3d0c9cc2a406 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -20,6 +20,7 @@
 #include <linux/irq.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/memblock.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
@@ -633,6 +634,12 @@ static void __init treo_lcd_power_init(void)
         treo_lcd_screen.pxafb_lcd_power = treo_lcd_power;
 }
 
+static void __init treo_reserve(void)
+{
+        memblock_reserve(0xa0000000, 0x1000);
+        memblock_reserve(0xa2000000, 0x1000);
+}
+
 static void __init treo_init(void)
 {
         pxa_set_ffuart_info(NULL);
@@ -668,6 +675,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
         .io_pg_offst    = io_p2v(0x40000000),
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = treo680_init,
@@ -691,6 +699,7 @@ MACHINE_START(CENTRO, "Palm Centro 685")
         .io_pg_offst    = io_p2v(0x40000000),
         .boot_params    = 0xa0000100,
         .map_io         = pxa_map_io,
+        .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
        .init_machine   = centro_init,
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index f4abdaafdac4..bc2758b54446 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -463,7 +463,6 @@ static void __init fixup_poodle(struct machine_desc *desc,
         sharpsl_save_param();
         mi->nr_banks=1;
         mi->bank[0].start = 0xa0000000;
-        mi->bank[0].node = 0;
         mi->bank[0].size = (32*1024*1024);
 }
 
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c1048a35f187..51756c723557 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -847,7 +847,6 @@ static void __init fixup_spitz(struct machine_desc *desc,
         sharpsl_save_param();
         mi->nr_banks = 1;
         mi->bank[0].start = 0xa0000000;
-        mi->bank[0].node = 0;
         mi->bank[0].size = (64*1024*1024);
 }
 
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 7512b822c6ca..83cc3a18c2e9 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -948,7 +948,6 @@ static void __init fixup_tosa(struct machine_desc *desc,
         sharpsl_save_param();
         mi->nr_banks=1;
         mi->bank[0].start = 0xa0000000;
-        mi->bank[0].node = 0;
         mi->bank[0].size = (64*1024*1024);
 }
 
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 595be19f8ad5..2fa38df28414 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -61,12 +61,11 @@ void __iomem *gic_cpu_base_addr;
 /*
  * Adjust the zones if there are restrictions for DMA access.
  */
-void __init realview_adjust_zones(int node, unsigned long *size,
-                                  unsigned long *hole)
+void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
 {
         unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
 
-        if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
+        if (!machine_is_realview_pbx() || size[0] <= dma_size)
                 return;
 
         size[ZONE_NORMAL] = size[0] - dma_size;
@@ -232,12 +231,27 @@ static unsigned int realview_mmc_status(struct device *dev)
         struct amba_device *adev = container_of(dev, struct amba_device, dev);
         u32 mask;
 
+        if (machine_is_realview_pb1176()) {
+                static bool inserted = false;
+
+                /*
+                 * The PB1176 does not have the status register,
+                 * assume it is inserted at startup, then invert
+                 * for each call so card insertion/removal will
+                 * be detected anyway. This will not be called if
+                 * GPIO on PL061 is active, which is the proper
+                 * way to do this on the PB1176.
+                 */
+                inserted = !inserted;
+                return inserted ? 0 : 1;
+        }
+
         if (adev->res.start == REALVIEW_MMCI0_BASE)
                 mask = 1;
         else
                 mask = 2;
 
-        return !(readl(REALVIEW_SYSMCI) & mask);
+        return readl(REALVIEW_SYSMCI) & mask;
 }
 
 struct mmci_platform_data realview_mmc0_plat_data = {
@@ -300,8 +314,13 @@ static struct clk ref24_clk = {
         .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-        {       /* UART0 */
+        {       /* Bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "dev:uart0",
                 .clk            = &ref24_clk,
         }, {    /* UART1 */
@@ -313,6 +332,12 @@ static struct clk_lookup lookups[] = {
         }, {    /* UART3 */
                 .dev_id         = "fpga:uart3",
                 .clk            = &ref24_clk,
+        }, {    /* UART3 is on the dev chip in PB1176 */
+                .dev_id         = "dev:uart3",
+                .clk            = &ref24_clk,
+        }, {    /* UART4 only exists in PB1176 */
+                .dev_id         = "fpga:uart4",
+                .clk            = &ref24_clk,
         }, {    /* KMI0 */
                 .dev_id         = "fpga:kmi0",
                 .clk            = &ref24_clk,
@@ -322,12 +347,15 @@ static struct clk_lookup lookups[] = {
         }, {    /* MMC0 */
                 .dev_id         = "fpga:mmc0",
                 .clk            = &ref24_clk,
-        }, {    /* EB:CLCD */
+        }, {    /* CLCD is in the PB1176 and EB DevChip */
                 .dev_id         = "dev:clcd",
                 .clk            = &oscvco_clk,
         }, {    /* PB:CLCD */
                 .dev_id         = "issp:clcd",
                 .clk            = &oscvco_clk,
+        }, {    /* SSP */
+                .dev_id         = "dev:ssp0",
+                .clk            = &ref24_clk,
         }
 };
 
@@ -342,7 +370,7 @@ static int __init clk_init(void)
 
         return 0;
 }
-arch_initcall(clk_init);
+core_initcall(clk_init);
 
 /*
  * CLCD support.
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 2f5ccb298858..002ab5d8c11c 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -26,6 +26,7 @@
 /*
  * Peripheral addresses
  */
+#define REALVIEW_PB1176_UART4_BASE              0x10009000 /* UART 4 */
 #define REALVIEW_PB1176_SCTL_BASE               0x10100000 /* System controller */
 #define REALVIEW_PB1176_SMC_BASE                0x10111000 /* SMC */
 #define REALVIEW_PB1176_DMC_BASE                0x10109000 /* DMC configuration */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 830055bb8628..5c3c625e3e04 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -40,6 +40,7 @@
 #define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
 #define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
 #define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_SSP          (IRQ_DC1176_GIC_START + 17)     /* SSP port */
 #define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
 #define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
 #define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
@@ -73,7 +74,6 @@
 #define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
 
 #define IRQ_PB1176_GPIO0        -1
-#define IRQ_PB1176_SSP          -1
 #define IRQ_PB1176_SCTL         -1
 
 #define NR_GIC_PB1176           2
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index 2417bbcf97fd..5dafc157b276 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -30,10 +30,9 @@
 #endif
 
 #if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA)
-extern void realview_adjust_zones(int node, unsigned long *size,
-                                  unsigned long *hole);
-#define arch_adjust_zones(node, size, hole) \
-        realview_adjust_zones(node, size, hole)
+extern void realview_adjust_zones(unsigned long *size, unsigned long *hole);
+#define arch_adjust_zones(size, hole) \
+        realview_adjust_zones(size, hole)
 
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_256M - 1)
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_256M)
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 4425018fab82..991c1f8390e2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -129,6 +130,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView EB AMBA devices
  */
@@ -213,7 +220,7 @@ AMBA_DEVICE(sci0,  "dev:sci0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
 AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
 AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
-AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   NULL);
+AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -324,6 +331,26 @@ static struct platform_device pmu_device = {
         .resource               = pmu_resources,
 };
 
+static struct resource char_lcd_resources[] = {
+        {
+                .start = REALVIEW_CHAR_LCD_BASE,
+                .end   = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_EB_CHARLCD,
+                .end    = IRQ_EB_CHARLCD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device char_lcd_device = {
+        .name           =       "arm-charlcd",
+        .id             =       -1,
+        .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+        .resource       =       char_lcd_resources,
+};
+
 static void __init gic_init_irq(void)
 {
         if (core_tile_eb11mp() || core_tile_a9mp()) {
@@ -442,6 +469,7 @@ static void __init realview_eb_init(void)
 
         realview_flash_register(&realview_eb_flash_resource, 1);
         platform_device_register(&realview_i2c_device);
+        platform_device_register(&char_lcd_device);
         eth_device_register();
         realview_usb_register(realview_eb_isp1761_resources);
 
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 099a1f125cf8..d2be12eb829e 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -123,6 +124,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PB1176 AMBA devices
  */
@@ -144,8 +151,6 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define MPMC_DMA        { 0, 0 }
 #define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
 #define PB1176_CLCD_DMA { 0, 0 }
-#define DMAC_IRQ        { IRQ_PB1176_DMAC, NO_IRQ }
-#define DMAC_DMA        { 0, 0 }
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 #define SCTL_DMA        { 0, 0 }
 #define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
@@ -166,7 +171,9 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define PB1176_UART2_DMA        { 11, 10 }
 #define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
 #define PB1176_UART3_DMA        { 0x86, 0x87 }
-#define PB1176_SSP_IRQ          { IRQ_PB1176_SSP, NO_IRQ }
+#define PB1176_UART4_IRQ        { IRQ_PB1176_UART4, NO_IRQ }
+#define PB1176_UART4_DMA        { 0, 0 }
+#define PB1176_SSP_IRQ          { IRQ_DC1176_SSP, NO_IRQ }
 #define PB1176_SSP_DMA          { 9, 8 }
 
 /* FPGA Primecells */
@@ -174,7 +181,7 @@ AMBA_DEVICE(aaci,	"fpga:aaci",	AACI,		NULL);
 AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
 AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
 AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PB1176_UART3,   NULL);
+AMBA_DEVICE(uart4,      "fpga:uart4",   PB1176_UART4,   NULL);
 
 /* DevChip Primecells */
 AMBA_DEVICE(smc,        "dev:smc",      PB1176_SMC,     NULL);
@@ -188,18 +195,16 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PB1176_UART0,   NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PB1176_UART1,   NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PB1176_UART2,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB1176_SSP,     NULL);
-
-/* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PB1176_CLCD,    &clcd_plat_data);
-//AMBA_DEVICE(dmac,     "issp:dmac",    PB1176_DMAC,    NULL);
+AMBA_DEVICE(uart3,      "dev:uart3",    PB1176_UART3,   NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PB1176_SSP,     &ssp0_plat_data);
+AMBA_DEVICE(clcd,       "dev:clcd",     PB1176_CLCD,    &clcd_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
-//      &dmac_device,
         &uart0_device,
         &uart1_device,
         &uart2_device,
         &uart3_device,
+        &uart4_device,
         &smc_device,
         &clcd_device,
         &sctl_device,
@@ -276,6 +281,26 @@ static struct platform_device pmu_device = {
         .resource               = &pmu_resource,
 };
 
+static struct resource char_lcd_resources[] = {
+        {
+                .start = REALVIEW_CHAR_LCD_BASE,
+                .end   = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_PB1176_CHARLCD,
+                .end    = IRQ_PB1176_CHARLCD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device char_lcd_device = {
+        .name           =       "arm-charlcd",
+        .id             =       -1,
+        .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+        .resource       =       char_lcd_resources,
+};
+
 static void __init gic_init_irq(void)
 {
         /* ARM1176 DevChip GIC, primary */
@@ -338,6 +363,7 @@ static void __init realview_pb1176_init(void)
         platform_device_register(&realview_i2c_device);
         realview_usb_register(realview_pb1176_isp1761_resources);
         platform_device_register(&pmu_device);
+        platform_device_register(&char_lcd_device);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 0e07a5ccb75f..d591bc00b86e 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -124,6 +125,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PB11MPCore AMBA devices
  */
@@ -190,7 +197,7 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PB11MP_UART0,   NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PB11MP_UART1,   NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PB11MP_UART2,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB11MP_SSP,     NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,       "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index ac2f06f1ca50..6c37621217bc 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -25,6 +25,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -114,6 +115,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PBA8Core AMBA devices
  */
@@ -180,7 +187,7 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PBA8_UART0,     NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PBA8_UART1,     NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PBA8_UART2,     NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBA8_SSP,       NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PBA8_SSP,       &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,       "issp:clcd",    PBA8_CLCD,      &clcd_plat_data);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 08fd683adc4c..9428eff0b116 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -24,6 +24,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
@@ -136,6 +137,12 @@ static struct pl061_platform_data gpio2_plat_data = {
         .irq_base       = -1,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 /*
  * RealView PBXCore AMBA devices
  */
@@ -202,7 +209,7 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,      "dev:uart0",    PBX_UART0,      NULL);
 AMBA_DEVICE(uart1,      "dev:uart1",    PBX_UART1,      NULL);
 AMBA_DEVICE(uart2,      "dev:uart2",    PBX_UART2,      NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBX_SSP,        NULL);
+AMBA_DEVICE(ssp0,       "dev:ssp0",     PBX_SSP,        &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,       "issp:clcd",    PBX_CLCD,       &clcd_plat_data);
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 779b45b3f80f..3ba3bab139d0 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/memblock.h>
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/sysdev.h>
@@ -304,6 +305,13 @@ static void __init h1940_map_io(void)
         s3c_pm_init();
 }
 
+/* H1940 and RX3715 need to reserve this for suspend */
+static void __init h1940_reserve(void)
+{
+        memblock_reserve(0x30003000, 0x1000);
+        memblock_reserve(0x30081000, 0x1000);
+}
+
 static void __init h1940_init_irq(void)
 {
         s3c24xx_init_irq();
@@ -346,6 +354,7 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = h1940_map_io,
+        .reserve        = h1940_reserve,
         .init_irq       = h1940_init_irq,
         .init_machine   = h1940_init,
         .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index ba93a356a839..054c9f92232a 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -119,7 +119,6 @@ static void __init smdk2413_fixup(struct machine_desc *desc,
                 mi->nr_banks=1;
                 mi->bank[0].start = 0x30000000;
                 mi->bank[0].size = SZ_64M;
-                mi->bank[0].node = 0;
         }
 }
 
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 3ca9265b6997..f291ac25d312 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -137,7 +137,6 @@ static void __init vstms_fixup(struct machine_desc *desc,
                 mi->nr_banks=1;
                 mi->bank[0].start = 0x30000000;
                 mi->bank[0].size = SZ_64M;
-                mi->bank[0].node = 0;
         }
 }
 
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 8603b577a24b..142d1f921176 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/memblock.h>
 #include <linux/delay.h>
 #include <linux/timer.h>
 #include <linux/init.h>
@@ -570,12 +571,20 @@ static void __init rx1950_init_machine(void)
         platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
 }
 
+/* H1940 and RX3715 need to reserve this for suspend */
+static void __init rx1950_reserve(void)
+{
+        memblock_reserve(0x30003000, 0x1000);
+        memblock_reserve(0x30081000, 0x1000);
+}
+
 MACHINE_START(RX1950, "HP iPAQ RX1950")
     /* Maintainers: Vasily Khoruzhick */
     .phys_io = S3C2410_PA_UART,
         .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params = S3C2410_SDRAM_PA + 0x100,
         .map_io = rx1950_map_io,
+        .reserve        = rx1950_reserve,
         .init_irq = s3c24xx_init_irq,
         .init_machine = rx1950_init_machine,
         .timer = &s3c24xx_timer,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index d2946de3f365..6bb44f75a9ce 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/memblock.h>
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/tty.h>
@@ -191,6 +192,13 @@ static void __init rx3715_map_io(void)
         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
 }
 
+/* H1940 and RX3715 need to reserve this for suspend */
+static void __init rx3715_reserve(void)
+{
+        memblock_reserve(0x30003000, 0x1000);
+        memblock_reserve(0x30081000, 0x1000);
+}
+
 static void __init rx3715_init_irq(void)
 {
         s3c24xx_init_irq();
@@ -214,6 +222,7 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
         .boot_params    = S3C2410_SDRAM_PA + 0x100,
         .map_io         = rx3715_map_io,
+        .reserve        = rx3715_reserve,
         .init_irq       = rx3715_init_irq,
         .init_machine   = rx3715_init_machine,
         .timer          = &s3c24xx_timer,
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 5d5f330c5d94..16e682d5dbb7 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -11,7 +11,7 @@
  * published by the Free Software Foundation.
  *
  * ChangeLog:
- *  2006 Pavel Machek <pavel@suse.cz>
+ *  2006 Pavel Machek <pavel@ucw.cz>
  *  03-06-2004 John Lenz <lenz@cs.wisc.edu>
  *  06-04-2002 Chris Larson <kergoth@digitalnemesis.net>
  *  04-16-2001 Lineo Japan,Inc. ...
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index ec03f187c52b..b7a9a601c2d1 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -13,8 +13,7 @@ extern void __init sa1100_init_gpio(void);
 
 #define SET_BANK(__nr,__start,__size) \
         mi->bank[__nr].start = (__start), \
-        mi->bank[__nr].size = (__size), \
-        mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
+        mi->bank[__nr].size = (__size)
 
 extern void (*sa1100fb_backlight_power)(int on);
 extern void (*sa1100fb_lcd_power)(int on);
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index d5277f9bee77..128a1dfa96b9 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -17,10 +17,10 @@
 #ifndef __ASSEMBLY__
 
 #ifdef CONFIG_SA1111
-void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
+void sa1111_adjust_zones(unsigned long *size, unsigned long *holes);
 
-#define arch_adjust_zones(node, size, holes) \
-        sa1111_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+        sa1111_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_1M - 1)
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_1M)
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index 3053e5b7f168..d9c4812f1c31 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -19,9 +19,8 @@
 
 #ifndef __ASSEMBLY__
 
-static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) 
+static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size)
 {
-  if (node != 0) return;
   /* Only the first 4 MB (=1024 Pages) are usable for DMA */
   /* See dev / -> .properties in OpenFirmware. */
   zone_size[1] = zone_size[0] - 1024;
@@ -30,8 +29,8 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig
   zhole_size[0] = 0;
 }
 
-#define arch_adjust_zones(node, size, holes) \
-        __arch_adjust_zones(node, size, holes)
+#define arch_adjust_zones(size, holes) \
+        __arch_adjust_zones(size, holes)
 
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_4M - 1)
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_4M)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f2b88c5fe142..4c704b4e8b34 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -70,6 +70,18 @@ endmenu
 
 menu "Timer and clock configuration"
 
+config SHMOBILE_TIMER_HZ
+        int "Kernel HZ (jiffies per second)"
+        range 32 1024
+        default "128"
+        help
+          Allows the configuration of the timer frequency. It is customary
+          to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
+          case of low timer frequencies other values may be more suitable.
+          SH-Mobile systems using a 32768 Hz RCLK for clock events may want
+          to select a HZ value such as 128 that can evenly divide RCLK.
+          A HZ value that does not divide evenly may cause timer drift.
+
 config SH_TIMER_CMT
         bool "CMT timer driver"
         default y
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 5179b72e1ee3..132256bb8c81 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -2,7 +2,6 @@
 #define __ASM_MACH_IRQS_H
 
 #define NR_IRQS         512
-#define NR_IRQS_LEGACY  8
 
 #define evt2irq(evt)            (((evt) >> 5) - 16)
 #define irq2evt(irq)            (((irq) + 16) << 5)
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 39f6ccf22294..18febf92f20a 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -341,8 +341,11 @@ static struct clk gpio_clk = {
         .recalc = &follow_parent,
 };
 
+static struct clk dummy_apb_pclk;
+
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+        { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
         /* root clks */
         { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
         { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 13e27c769685..36ff056b7321 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -428,8 +428,11 @@ static struct clk gpio2_clk = {
         .recalc = &follow_parent,
 };
 
+static struct clk dummy_apb_pclk;
+
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
+        { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
         /* root clks */
         { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
         { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 5af71d5ba665..5d12d547789e 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -1212,6 +1212,8 @@ static struct clk ppm_clk = {
 };
 #endif
 
+static struct clk dummy_apb_pclk;
+
 #define DEF_LOOKUP(devid, clkref)               \
         {                                       \
         .dev_id = devid,                        \
@@ -1223,6 +1225,10 @@ static struct clk ppm_clk = {
  * look up through clockdevice.
  */
 static struct clk_lookup lookups[] = {
+        {
+                .con_id = "apb_pclk",
+                .clk = &dummy_apb_pclk,
+        },
         /* Connected directly to the AMBA bus */
         DEF_LOOKUP("amba",      &amba_clk),
         DEF_LOOKUP("cpu",       &cpu_clk),
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 5f34eb674d68..653b3e0ab7ba 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1561,13 +1561,6 @@ static void __init u300_init_check_chip(void)
         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
                "(chip ID 0x%04x)\n", chipname, val);
 
-#ifdef CONFIG_MACH_U300_BS26
-        if ((val & 0xFF00U) != 0xc800) {
-                printk(KERN_ERR "Platform configured for BS25/BS26 " \
-                       "with DB3150 but %s detected, expect problems!",
-                       chipname);
-        }
-#endif
 #ifdef CONFIG_MACH_U300_BS330
         if ((val & 0xFF00U) != 0xd800) {
                 printk(KERN_ERR "Platform configured for BS330 " \
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
index 5f61fd45a0c8..d92790140fe5 100644
--- a/arch/arm/mach-u300/gpio.c
+++ b/arch/arm/mach-u300/gpio.c
@@ -523,7 +523,7 @@ static void gpio_set_initial_values(void)
 
         /*
          * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
-         * to output and 'GPIO_IN' to input for each port. And initalize
+         * to output and 'GPIO_IN' to input for each port. And initialize
          * default value on outputs.
          */
         for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
index ab000df7fc03..bf134bcc129d 100644
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -35,14 +35,6 @@
 #endif
 
 /*
- * TCM memory whereabouts
- */
-#define ITCM_OFFSET     0xffff2000
-#define ITCM_END        0xffff3fff
-#define DTCM_OFFSET     0xffff4000
-#define DTCM_END        0xffff5fff
-
-/*
  * We enable a real big DMA buffer if need be.
  */
 #define CONSISTENT_DMA_SIZE SZ_4M
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index d2a0b8847a18..bfcda9820888 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -14,6 +14,7 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/memblock.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -22,6 +23,21 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+static void __init u300_reserve(void)
+{
+        /*
+         * U300 - This platform family can share physical memory
+         * between two ARM cpus, one running Linux and the other
+         * running another OS.
+         */
+#ifdef CONFIG_MACH_U300_SINGLE_RAM
+#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
+        CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
+        memblock_reserve(PHYS_OFFSET, 0x00100000);
+#endif
+#endif
+}
+
 static void __init u300_init_machine(void)
 {
         u300_init_devices();
@@ -49,6 +65,7 @@ MACHINE_START(U300, MACH_U300_STRING)
         .io_pg_offst    = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = BOOT_PARAMS_OFFSET,
         .map_io         = u300_map_io,
+        .reserve        = u300_reserve,
         .init_irq       = u300_init_irq,
         .timer          = &u300_timer,
         .init_machine   = u300_init_machine,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index bb8d7b771817..0e8fd135a57d 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -13,19 +13,42 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/spi/spi.h>
+#include <linux/mfd/ab8500.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include <plat/pincfg.h>
 #include <plat/i2c.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 
+#include "pins-db8500.h"
+
+static pin_cfg_t mop500_pins[] = {
+        /* SSP0 */
+        GPIO143_SSP0_CLK,
+        GPIO144_SSP0_FRM,
+        GPIO145_SSP0_RXD,
+        GPIO146_SSP0_TXD,
+
+        /* I2C */
+        GPIO147_I2C0_SCL,
+        GPIO148_I2C0_SDA,
+        GPIO16_I2C1_SCL,
+        GPIO17_I2C1_SDA,
+        GPIO10_I2C2_SDA,
+        GPIO11_I2C2_SCL,
+        GPIO229_I2C3_SDA,
+        GPIO230_I2C3_SCL,
+};
+
 static void ab4500_spi_cs_control(u32 command)
 {
         /* set the FRM signal, which is CS  - TODO */
@@ -48,15 +71,20 @@ struct pl022_config_chip ab4500_chip_info = {
         .cs_control = ab4500_spi_cs_control,
 };
 
+static struct ab8500_platform_data ab8500_platdata = {
+        .irq_base       = MOP500_AB8500_IRQ_BASE,
+};
+
 static struct spi_board_info u8500_spi_devices[] = {
         {
                 .modalias = "ab8500",
                 .controller_data = &ab4500_chip_info,
+                .platform_data = &ab8500_platdata,
                 .max_speed_hz = 12000000,
                 .bus_num = 0,
                 .chip_select = 0,
                 .mode = SPI_MODE_0,
-                .irq = IRQ_AB4500,
+                .irq = IRQ_DB8500_AB8500,
         },
 };
 
@@ -118,6 +146,10 @@ static void __init u8500_init_machine(void)
 {
         int i;
 
+        u8500_init_devices();
+
+        nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
+
         u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data;
         ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
         ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
@@ -133,8 +165,6 @@ static void __init u8500_init_machine(void)
 
         spi_register_board_info(u8500_spi_devices,
                         ARRAY_SIZE(u8500_spi_devices));
-
-        u8500_init_devices();
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 0a1318fc8e2b..d8ab7f184fe4 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -453,7 +453,11 @@ static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
 static DEFINE_PRCC_CLK(7, wdg_ed,       1, -1, NULL);
 static DEFINE_PRCC_CLK(7, cfgreg_ed,    0, -1, NULL);
 
+static struct clk clk_dummy_apb_pclk;
+
 static struct clk_lookup u8500_common_clks[] = {
+        CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
+
         /* Peripheral Cluster #1 */
         CLK(gpio0,      "gpio.0",       NULL),
         CLK(gpio0,      "gpio.1",       NULL),
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 822903421943..654fca944e65 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -65,7 +65,7 @@ struct amba_device u8500_ssp0_device = {
                 .end   = U8500_SSP0_BASE + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
         },
-        .irq = {IRQ_SSP0, NO_IRQ },
+        .irq = {IRQ_DB8500_SSP0, NO_IRQ },
         /* ST-Ericsson modified id */
         .periphid = SSP_PER_ID,
 };
@@ -77,8 +77,8 @@ static struct resource u8500_i2c0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_I2C0,
-                .end    = IRQ_I2C0,
+                .start  = IRQ_DB8500_I2C0,
+                .end    = IRQ_DB8500_I2C0,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -97,8 +97,8 @@ static struct resource u8500_i2c4_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_I2C4,
-                .end    = IRQ_I2C4,
+                .start  = IRQ_DB8500_I2C4,
+                .end    = IRQ_DB8500_I2C4,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -130,8 +130,8 @@ static struct resource dma40_resources[] = {
                 .name = "lcla",
         },
         [3] = {
-                .start = IRQ_DMA,
-                .end = IRQ_DMA,
+                .start = IRQ_DB8500_DMA,
+                .end   = IRQ_DB8500_DMA,
                 .flags = IORESOURCE_IRQ}
 };
 
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
new file mode 100644
index 000000000000..cca4f705601e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_BOARD_MOP500_H
+#define __MACH_IRQS_BOARD_MOP500_H
+
+#define AB8500_NR_IRQS                  104
+
+#define MOP500_AB8500_IRQ_BASE          IRQ_BOARD_START
+#define MOP500_AB8500_IRQ_END           (MOP500_AB8500_IRQ_BASE \
+                                         + AB8500_NR_IRQS)
+#define MOP500_IRQ_END                  MOP500_AB8500_IRQ_END
+
+#if MOP500_IRQ_END > IRQ_BOARD_END
+#undef IRQ_BOARD_END
+#define IRQ_BOARD_END   MOP500_IRQ_END
+#endif
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
new file mode 100644
index 000000000000..6fbfe5e2065a
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB5500_H
+#define __MACH_IRQS_DB5500_H
+
+#define IRQ_DB5500_MTU0                 (IRQ_SHPI_START + 4)
+#define IRQ_DB5500_SPI2                 (IRQ_SHPI_START + 6)
+#define IRQ_DB5500_PMU0                 (IRQ_SHPI_START + 7)
+#define IRQ_DB5500_SPI0                 (IRQ_SHPI_START + 8)
+#define IRQ_DB5500_RTT                  (IRQ_SHPI_START + 9)
+#define IRQ_DB5500_PKA                  (IRQ_SHPI_START + 10)
+#define IRQ_DB5500_UART0                (IRQ_SHPI_START + 11)
+#define IRQ_DB5500_I2C3                 (IRQ_SHPI_START + 12)
+#define IRQ_DB5500_L2CC                 (IRQ_SHPI_START + 13)
+#define IRQ_DB5500_MSP0                 (IRQ_SHPI_START + 14)
+#define IRQ_DB5500_CRYP1                (IRQ_SHPI_START + 15)
+#define IRQ_DB5500_PMU1                 (IRQ_SHPI_START + 16)
+#define IRQ_DB5500_MTU1                 (IRQ_SHPI_START + 17)
+#define IRQ_DB5500_RTC                  (IRQ_SHPI_START + 18)
+#define IRQ_DB5500_UART1                (IRQ_SHPI_START + 19)
+#define IRQ_DB5500_USB_WAKEUP           (IRQ_SHPI_START + 20)
+#define IRQ_DB5500_I2C0                 (IRQ_SHPI_START + 21)
+#define IRQ_DB5500_I2C1                 (IRQ_SHPI_START + 22)
+#define IRQ_DB5500_USBOTG               (IRQ_SHPI_START + 23)
+#define IRQ_DB5500_DMA_SECURE           (IRQ_SHPI_START + 24)
+#define IRQ_DB5500_DMA                  (IRQ_SHPI_START + 25)
+#define IRQ_DB5500_UART2                (IRQ_SHPI_START + 26)
+#define IRQ_DB5500_ICN_PMU1             (IRQ_SHPI_START + 27)
+#define IRQ_DB5500_ICN_PMU2             (IRQ_SHPI_START + 28)
+#define IRQ_DB5500_UART3                (IRQ_SHPI_START + 29)
+#define IRQ_DB5500_SPI3                 (IRQ_SHPI_START + 30)
+#define IRQ_DB5500_SDMMC4               (IRQ_SHPI_START + 31)
+#define IRQ_DB5500_IRRC                 (IRQ_SHPI_START + 33)
+#define IRQ_DB5500_IRDA_FT              (IRQ_SHPI_START + 34)
+#define IRQ_DB5500_IRDA_SD              (IRQ_SHPI_START + 35)
+#define IRQ_DB5500_IRDA_FI              (IRQ_SHPI_START + 36)
+#define IRQ_DB5500_IRDA_FD              (IRQ_SHPI_START + 37)
+#define IRQ_DB5500_FSMC_CODEREADY       (IRQ_SHPI_START + 38)
+#define IRQ_DB5500_FSMC_NANDWAIT        (IRQ_SHPI_START + 39)
+#define IRQ_DB5500_AB5500               (IRQ_SHPI_START + 40)
+#define IRQ_DB5500_SDMMC2               (IRQ_SHPI_START + 41)
+#define IRQ_DB5500_SIA                  (IRQ_SHPI_START + 42)
+#define IRQ_DB5500_SIA2                 (IRQ_SHPI_START + 43)
+#define IRQ_DB5500_HVA                  (IRQ_SHPI_START + 44)
+#define IRQ_DB5500_HVA2                 (IRQ_SHPI_START + 45)
+#define IRQ_DB5500_PRCMU0               (IRQ_SHPI_START + 46)
+#define IRQ_DB5500_PRCMU1               (IRQ_SHPI_START + 47)
+#define IRQ_DB5500_DISP                 (IRQ_SHPI_START + 48)
+#define IRQ_DB5500_SDMMC1               (IRQ_SHPI_START + 50)
+#define IRQ_DB5500_MSP1                 (IRQ_SHPI_START + 52)
+#define IRQ_DB5500_KBD                  (IRQ_SHPI_START + 53)
+#define IRQ_DB5500_I2C2                 (IRQ_SHPI_START + 55)
+#define IRQ_DB5500_B2R2                 (IRQ_SHPI_START + 56)
+#define IRQ_DB5500_CRYP0                (IRQ_SHPI_START + 57)
+#define IRQ_DB5500_SDMMC3               (IRQ_SHPI_START + 59)
+#define IRQ_DB5500_SDMMC0               (IRQ_SHPI_START + 60)
+#define IRQ_DB5500_HSEM                 (IRQ_SHPI_START + 61)
+#define IRQ_DB5500_SBAG                 (IRQ_SHPI_START + 63)
+#define IRQ_DB5500_SPI1                 (IRQ_SHPI_START + 96)
+#define IRQ_DB5500_MSP2                 (IRQ_SHPI_START + 98)
+#define IRQ_DB5500_SRPTIMER             (IRQ_SHPI_START + 101)
+#define IRQ_DB5500_CTI0                 (IRQ_SHPI_START + 108)
+#define IRQ_DB5500_CTI1                 (IRQ_SHPI_START + 109)
+#define IRQ_DB5500_ICN_ERR              (IRQ_SHPI_START + 110)
+#define IRQ_DB5500_MALI_PPMMU           (IRQ_SHPI_START + 112)
+#define IRQ_DB5500_MALI_PP              (IRQ_SHPI_START + 113)
+#define IRQ_DB5500_MALI_GPMMU           (IRQ_SHPI_START + 114)
+#define IRQ_DB5500_MALI_GP              (IRQ_SHPI_START + 115)
+#define IRQ_DB5500_MALI                 (IRQ_SHPI_START + 116)
+#define IRQ_DB5500_PRCMU_SEM            (IRQ_SHPI_START + 118)
+#define IRQ_DB5500_GPIO0                (IRQ_SHPI_START + 119)
+#define IRQ_DB5500_GPIO1                (IRQ_SHPI_START + 120)
+#define IRQ_DB5500_GPIO2                (IRQ_SHPI_START + 121)
+#define IRQ_DB5500_GPIO3                (IRQ_SHPI_START + 122)
+#define IRQ_DB5500_GPIO4                (IRQ_SHPI_START + 123)
+#define IRQ_DB5500_GPIO5                (IRQ_SHPI_START + 124)
+#define IRQ_DB5500_GPIO6                (IRQ_SHPI_START + 125)
+#define IRQ_DB5500_GPIO7                (IRQ_SHPI_START + 126)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
new file mode 100644
index 000000000000..8b5d9f0a1633
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB8500_H
+#define __MACH_IRQS_DB8500_H
+
+#define IRQ_DB8500_MTU0                 (IRQ_SHPI_START + 4)
+#define IRQ_DB8500_SPI2                 (IRQ_SHPI_START + 6)
+#define IRQ_DB8500_PMU                  (IRQ_SHPI_START + 7)
+#define IRQ_DB8500_SPI0                 (IRQ_SHPI_START + 8)
+#define IRQ_DB8500_RTT                  (IRQ_SHPI_START + 9)
+#define IRQ_DB8500_PKA                  (IRQ_SHPI_START + 10)
+#define IRQ_DB8500_UART0                (IRQ_SHPI_START + 11)
+#define IRQ_DB8500_I2C3                 (IRQ_SHPI_START + 12)
+#define IRQ_DB8500_L2CC                 (IRQ_SHPI_START + 13)
+#define IRQ_DB8500_SSP0                 (IRQ_SHPI_START + 14)
+#define IRQ_DB8500_CRYP1                (IRQ_SHPI_START + 15)
+#define IRQ_DB8500_MSP1_RX              (IRQ_SHPI_START + 16)
+#define IRQ_DB8500_MTU1                 (IRQ_SHPI_START + 17)
+#define IRQ_DB8500_RTC                  (IRQ_SHPI_START + 18)
+#define IRQ_DB8500_UART1                (IRQ_SHPI_START + 19)
+#define IRQ_DB8500_USB_WAKEUP           (IRQ_SHPI_START + 20)
+#define IRQ_DB8500_I2C0                 (IRQ_SHPI_START + 21)
+#define IRQ_DB8500_I2C1                 (IRQ_SHPI_START + 22)
+#define IRQ_DB8500_USBOTG               (IRQ_SHPI_START + 23)
+#define IRQ_DB8500_DMA_SECURE           (IRQ_SHPI_START + 24)
+#define IRQ_DB8500_DMA                  (IRQ_SHPI_START + 25)
+#define IRQ_DB8500_UART2                (IRQ_SHPI_START + 26)
+#define IRQ_DB8500_ICN_PMU1             (IRQ_SHPI_START + 27)
+#define IRQ_DB8500_ICN_PMU2             (IRQ_SHPI_START + 28)
+#define IRQ_DB8500_HSIR_EXCEP           (IRQ_SHPI_START + 29)
+#define IRQ_DB8500_MSP0                 (IRQ_SHPI_START + 31)
+#define IRQ_DB8500_HSIR_CH0_OVRRUN      (IRQ_SHPI_START + 32)
+#define IRQ_DB8500_HSIR_CH1_OVRRUN      (IRQ_SHPI_START + 33)
+#define IRQ_DB8500_HSIR_CH2_OVRRUN      (IRQ_SHPI_START + 34)
+#define IRQ_DB8500_HSIR_CH3_OVRRUN      (IRQ_SHPI_START + 35)
+#define IRQ_DB8500_HSIR_CH4_OVRRUN      (IRQ_SHPI_START + 36)
+#define IRQ_DB8500_HSIR_CH5_OVRRUN      (IRQ_SHPI_START + 37)
+#define IRQ_DB8500_HSIR_CH6_OVRRUN      (IRQ_SHPI_START + 38)
+#define IRQ_DB8500_HSIR_CH7_OVRRUN      (IRQ_SHPI_START + 39)
+#define IRQ_DB8500_AB8500               (IRQ_SHPI_START + 40)
+#define IRQ_DB8500_SDMMC2               (IRQ_SHPI_START + 41)
+#define IRQ_DB8500_SIA                  (IRQ_SHPI_START + 42)
+#define IRQ_DB8500_SIA2                 (IRQ_SHPI_START + 43)
+#define IRQ_DB8500_SVA                  (IRQ_SHPI_START + 44)
+#define IRQ_DB8500_SVA2                 (IRQ_SHPI_START + 45)
+#define IRQ_DB8500_PRCMU0               (IRQ_SHPI_START + 46)
+#define IRQ_DB8500_PRCMU1               (IRQ_SHPI_START + 47)
+#define IRQ_DB8500_DISP                 (IRQ_SHPI_START + 48)
+#define IRQ_DB8500_SPI3                 (IRQ_SHPI_START + 49)
+#define IRQ_DB8500_SDMMC1               (IRQ_SHPI_START + 50)
+#define IRQ_DB8500_I2C4                 (IRQ_SHPI_START + 51)
+#define IRQ_DB8500_SSP1                 (IRQ_SHPI_START + 52)
+#define IRQ_DB8500_SKE                  (IRQ_SHPI_START + 53)
+#define IRQ_DB8500_KB                   (IRQ_SHPI_START + 54)
+#define IRQ_DB8500_I2C2                 (IRQ_SHPI_START + 55)
+#define IRQ_DB8500_B2R2                 (IRQ_SHPI_START + 56)
+#define IRQ_DB8500_CRYP0                (IRQ_SHPI_START + 57)
+#define IRQ_DB8500_SDMMC3               (IRQ_SHPI_START + 59)
+#define IRQ_DB8500_SDMMC0               (IRQ_SHPI_START + 60)
+#define IRQ_DB8500_HSEM                 (IRQ_SHPI_START + 61)
+#define IRQ_DB8500_MSP1                 (IRQ_SHPI_START + 62)
+#define IRQ_DB8500_SBAG                 (IRQ_SHPI_START + 63)
+#define IRQ_DB8500_SPI1                 (IRQ_SHPI_START + 96)
+#define IRQ_DB8500_SRPTIMER             (IRQ_SHPI_START + 97)
+#define IRQ_DB8500_MSP2                 (IRQ_SHPI_START + 98)
+#define IRQ_DB8500_SDMMC4               (IRQ_SHPI_START + 99)
+#define IRQ_DB8500_SDMMC5               (IRQ_SHPI_START + 100)
+#define IRQ_DB8500_HSIRD0               (IRQ_SHPI_START + 104)
+#define IRQ_DB8500_HSIRD1               (IRQ_SHPI_START + 105)
+#define IRQ_DB8500_HSITD0               (IRQ_SHPI_START + 106)
+#define IRQ_DB8500_HSITD1               (IRQ_SHPI_START + 107)
+#define IRQ_DB8500_CTI0                 (IRQ_SHPI_START + 108)
+#define IRQ_DB8500_CTI1                 (IRQ_SHPI_START + 109)
+#define IRQ_DB8500_ICN_ERR              (IRQ_SHPI_START + 110)
+#define IRQ_DB8500_MALI_PPMMU           (IRQ_SHPI_START + 112)
+#define IRQ_DB8500_MALI_PP              (IRQ_SHPI_START + 113)
+#define IRQ_DB8500_MALI_GPMMU           (IRQ_SHPI_START + 114)
+#define IRQ_DB8500_MALI_GP              (IRQ_SHPI_START + 115)
+#define IRQ_DB8500_MALI                 (IRQ_SHPI_START + 116)
+#define IRQ_DB8500_PRCMU_SEM            (IRQ_SHPI_START + 118)
+#define IRQ_DB8500_GPIO0                (IRQ_SHPI_START + 119)
+#define IRQ_DB8500_GPIO1                (IRQ_SHPI_START + 120)
+#define IRQ_DB8500_GPIO2                (IRQ_SHPI_START + 121)
+#define IRQ_DB8500_GPIO3                (IRQ_SHPI_START + 122)
+#define IRQ_DB8500_GPIO4                (IRQ_SHPI_START + 123)
+#define IRQ_DB8500_GPIO5                (IRQ_SHPI_START + 124)
+#define IRQ_DB8500_GPIO6                (IRQ_SHPI_START + 125)
+#define IRQ_DB8500_GPIO7                (IRQ_SHPI_START + 126)
+#define IRQ_DB8500_GPIO8                (IRQ_SHPI_START + 127)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 7970684b1d09..10385bdc2b77 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,7 +10,8 @@
 #ifndef ASM_ARCH_IRQS_H
 #define ASM_ARCH_IRQS_H
 
-#include <mach/hardware.h>
+#include <mach/irqs-db5500.h>
+#include <mach/irqs-db8500.h>
 
 #define IRQ_LOCALTIMER                  29
 #define IRQ_LOCALWDOG                   30
@@ -67,12 +68,21 @@
 /* There are 128 shared peripheral interrupts assigned to
  * INTID[160:32]. The first 32 interrupts are reserved.
  */
-#define U8500_SOC_NR_IRQS               161
+#define DBX500_NR_INTERNAL_IRQS         161
 
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO                 288
-#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + U8500_SOC_NR_IRQS)
-#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - U8500_SOC_NR_IRQS)
-#define NR_IRQS                         NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + DBX500_NR_INTERNAL_IRQS)
+#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - DBX500_NR_INTERNAL_IRQS)
+#define IRQ_BOARD_START                 NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
 
-#endif /*ASM_ARCH_IRQS_H*/
+/* This will be overridden by board-specific irq headers */
+#define IRQ_BOARD_END                   IRQ_BOARD_START
+
+#ifdef CONFIG_MACH_U8500_MOP
+#include <mach/irqs-board-mop500.h>
+#endif
+
+#define NR_IRQS                         IRQ_BOARD_END
+
+#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 8552eb188b50..0271ca0a83df 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -30,22 +30,22 @@
 static void putc(const char c)
 {
         /* Do nothing if the UART is not enabled. */
-        if (!(readb(U8500_UART_CR) & 0x1))
+        if (!(__raw_readb(U8500_UART_CR) & 0x1))
                 return;
 
         if (c == '\n')
                 putc('\r');
 
-        while (readb(U8500_UART_FR) & (1 << 5))
+        while (__raw_readb(U8500_UART_FR) & (1 << 5))
                 barrier();
-        writeb(c, U8500_UART_DR);
+        __raw_writeb(c, U8500_UART_DR);
 }
 
 static void flush(void)
 {
-        if (!(readb(U8500_UART_CR) & 0x1))
+        if (!(__raw_readb(U8500_UART_CR) & 0x1))
                 return;
-        while (readb(U8500_UART_FR) & (1 << 3))
+        while (__raw_readb(U8500_UART_FR) & (1 << 3))
                 barrier();
 }
 
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
new file mode 100644
index 000000000000..9055d5d3233c
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -0,0 +1,742 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ */
+
+#ifndef __MACH_PINS_DB8500_H
+#define __MACH_PINS_DB8500_H
+
+/*
+ * TODO: Eventually encode all non-board specific pull up/down configuration
+ * here.
+ */
+
+#define GPIO0_GPIO              PIN_CFG(0, GPIO)
+#define GPIO0_U0_CTSn           PIN_CFG(0, ALT_A)
+#define GPIO0_TRIG_OUT          PIN_CFG(0, ALT_B)
+#define GPIO0_IP_TDO            PIN_CFG(0, ALT_C)
+
+#define GPIO1_GPIO              PIN_CFG(1, GPIO)
+#define GPIO1_U0_RTSn           PIN_CFG(1, ALT_A)
+#define GPIO1_TRIG_IN           PIN_CFG(1, ALT_B)
+#define GPIO1_IP_TDI            PIN_CFG(1, ALT_C)
+
+#define GPIO2_GPIO              PIN_CFG(2, GPIO)
+#define GPIO2_U0_RXD            PIN_CFG(2, ALT_A)
+#define GPIO2_NONE              PIN_CFG(2, ALT_B)
+#define GPIO2_IP_TMS            PIN_CFG(2, ALT_C)
+
+#define GPIO3_GPIO              PIN_CFG(3, GPIO)
+#define GPIO3_U0_TXD            PIN_CFG(3, ALT_A)
+#define GPIO3_NONE              PIN_CFG(3, ALT_B)
+#define GPIO3_IP_TCK            PIN_CFG(3, ALT_C)
+
+#define GPIO4_GPIO              PIN_CFG(4, GPIO)
+#define GPIO4_U1_RXD            PIN_CFG(4, ALT_A)
+#define GPIO4_I2C4_SCL          PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_IP_TRSTn          PIN_CFG(4, ALT_C)
+
+#define GPIO5_GPIO              PIN_CFG(5, GPIO)
+#define GPIO5_U1_TXD            PIN_CFG(5, ALT_A)
+#define GPIO5_I2C4_SDA          PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_IP_GPIO6          PIN_CFG(5, ALT_C)
+
+#define GPIO6_GPIO              PIN_CFG(6, GPIO)
+#define GPIO6_U1_CTSn           PIN_CFG(6, ALT_A)
+#define GPIO6_I2C1_SCL          PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_IP_GPIO0          PIN_CFG(6, ALT_C)
+
+#define GPIO7_GPIO              PIN_CFG(7, GPIO)
+#define GPIO7_U1_RTSn           PIN_CFG(7, ALT_A)
+#define GPIO7_I2C1_SDA          PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_IP_GPIO1          PIN_CFG(7, ALT_C)
+
+#define GPIO8_GPIO              PIN_CFG(8, GPIO)
+#define GPIO8_IPI2C_SDA         PIN_CFG_PULL(8, ALT_A, UP)
+#define GPIO8_I2C2_SDA          PIN_CFG_PULL(8, ALT_B, UP)
+
+#define GPIO9_GPIO              PIN_CFG(9, GPIO)
+#define GPIO9_IPI2C_SCL         PIN_CFG_PULL(9, ALT_A, UP)
+#define GPIO9_I2C2_SCL          PIN_CFG_PULL(9, ALT_B, UP)
+
+#define GPIO10_GPIO             PIN_CFG(10, GPIO)
+#define GPIO10_IPI2C_SDA        PIN_CFG_PULL(10, ALT_A, UP)
+#define GPIO10_I2C2_SDA         PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_IP_GPIO3         PIN_CFG(10, ALT_C)
+
+#define GPIO11_GPIO             PIN_CFG(11, GPIO)
+#define GPIO11_IPI2C_SCL        PIN_CFG_PULL(11, ALT_A, UP)
+#define GPIO11_I2C2_SCL         PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_IP_GPIO2         PIN_CFG(11, ALT_C)
+
+#define GPIO12_GPIO             PIN_CFG(12, GPIO)
+#define GPIO12_MSP0_TXD         PIN_CFG(12, ALT_A)
+#define GPIO12_MSP0_RXD         PIN_CFG(12, ALT_B)
+
+#define GPIO13_GPIO             PIN_CFG(13, GPIO)
+#define GPIO13_MSP0_TFS         PIN_CFG(13, ALT_A)
+
+#define GPIO14_GPIO             PIN_CFG(14, GPIO)
+#define GPIO14_MSP0_TCK         PIN_CFG(14, ALT_A)
+
+#define GPIO15_GPIO             PIN_CFG(15, GPIO)
+#define GPIO15_MSP0_RXD         PIN_CFG(15, ALT_A)
+#define GPIO15_MSP0_TXD         PIN_CFG(15, ALT_B)
+
+#define GPIO16_GPIO             PIN_CFG(16, GPIO)
+#define GPIO16_MSP0_RFS         PIN_CFG(16, ALT_A)
+#define GPIO16_I2C1_SCL         PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_SLIM0_DAT        PIN_CFG(16, ALT_C)
+
+#define GPIO17_GPIO             PIN_CFG(17, GPIO)
+#define GPIO17_MSP0_RCK         PIN_CFG(17, ALT_A)
+#define GPIO17_I2C1_SDA         PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
+
+#define GPIO18_GPIO             PIN_CFG(18, GPIO)
+#define GPIO18_MC0_CMDDIR       PIN_CFG(18, ALT_A)
+#define GPIO18_U2_RXD           PIN_CFG(18, ALT_B)
+#define GPIO18_MS_IEP           PIN_CFG(18, ALT_C)
+
+#define GPIO19_GPIO             PIN_CFG(19, GPIO)
+#define GPIO19_MC0_DAT0DIR      PIN_CFG(19, ALT_A)
+#define GPIO19_U2_TXD           PIN_CFG(19, ALT_B)
+#define GPIO19_MS_DAT0DIR       PIN_CFG(19, ALT_C)
+
+#define GPIO20_GPIO             PIN_CFG(20, GPIO)
+#define GPIO20_MC0_DAT2DIR      PIN_CFG(20, ALT_A)
+#define GPIO20_UARTMOD_TXD      PIN_CFG(20, ALT_B)
+#define GPIO20_IP_TRIGOUT       PIN_CFG(20, ALT_C)
+
+#define GPIO21_GPIO             PIN_CFG(21, GPIO)
+#define GPIO21_MC0_DAT31DIR     PIN_CFG(21, ALT_A)
+#define GPIO21_MSP0_SCK         PIN_CFG(21, ALT_B)
+#define GPIO21_MS_DAT31DIR      PIN_CFG(21, ALT_C)
+
+#define GPIO22_GPIO             PIN_CFG(22, GPIO)
+#define GPIO22_MC0_FBCLK        PIN_CFG(22, ALT_A)
+#define GPIO22_UARTMOD_RXD      PIN_CFG(22, ALT_B)
+#define GPIO22_MS_FBCLK         PIN_CFG(22, ALT_C)
+
+#define GPIO23_GPIO             PIN_CFG(23, GPIO)
+#define GPIO23_MC0_CLK          PIN_CFG(23, ALT_A)
+#define GPIO23_STMMOD_CLK       PIN_CFG(23, ALT_B)
+#define GPIO23_MS_CLK           PIN_CFG(23, ALT_C)
+
+#define GPIO24_GPIO             PIN_CFG(24, GPIO)
+#define GPIO24_MC0_CMD          PIN_CFG(24, ALT_A)
+#define GPIO24_UARTMOD_RXD      PIN_CFG(24, ALT_B)
+#define GPIO24_MS_BS            PIN_CFG(24, ALT_C)
+
+#define GPIO25_GPIO             PIN_CFG(25, GPIO)
+#define GPIO25_MC0_DAT0         PIN_CFG(25, ALT_A)
+#define GPIO25_STMMOD_DAT0      PIN_CFG(25, ALT_B)
+#define GPIO25_MS_DAT0          PIN_CFG(25, ALT_C)
+
+#define GPIO26_GPIO             PIN_CFG(26, GPIO)
+#define GPIO26_MC0_DAT1         PIN_CFG(26, ALT_A)
+#define GPIO26_STMMOD_DAT1      PIN_CFG(26, ALT_B)
+#define GPIO26_MS_DAT1          PIN_CFG(26, ALT_C)
+
+#define GPIO27_GPIO             PIN_CFG(27, GPIO)
+#define GPIO27_MC0_DAT2         PIN_CFG(27, ALT_A)
+#define GPIO27_STMMOD_DAT2      PIN_CFG(27, ALT_B)
+#define GPIO27_MS_DAT2          PIN_CFG(27, ALT_C)
+
+#define GPIO28_GPIO             PIN_CFG(28, GPIO)
+#define GPIO28_MC0_DAT3         PIN_CFG(28, ALT_A)
+#define GPIO28_STMMOD_DAT3      PIN_CFG(28, ALT_B)
+#define GPIO28_MS_DAT3          PIN_CFG(28, ALT_C)
+
+#define GPIO29_GPIO             PIN_CFG(29, GPIO)
+#define GPIO29_MC0_DAT4         PIN_CFG(29, ALT_A)
+#define GPIO29_SPI3_CLK         PIN_CFG(29, ALT_B)
+#define GPIO29_U2_RXD           PIN_CFG(29, ALT_C)
+
+#define GPIO30_GPIO             PIN_CFG(30, GPIO)
+#define GPIO30_MC0_DAT5         PIN_CFG(30, ALT_A)
+#define GPIO30_SPI3_RXD         PIN_CFG(30, ALT_B)
+#define GPIO30_U2_TXD           PIN_CFG(30, ALT_C)
+
+#define GPIO31_GPIO             PIN_CFG(31, GPIO)
+#define GPIO31_MC0_DAT6         PIN_CFG(31, ALT_A)
+#define GPIO31_SPI3_FRM         PIN_CFG(31, ALT_B)
+#define GPIO31_U2_CTSn          PIN_CFG(31, ALT_C)
+
+#define GPIO32_GPIO             PIN_CFG(32, GPIO)
+#define GPIO32_MC0_DAT7         PIN_CFG(32, ALT_A)
+#define GPIO32_SPI3_TXD         PIN_CFG(32, ALT_B)
+#define GPIO32_U2_RTSn          PIN_CFG(32, ALT_C)
+
+#define GPIO33_GPIO             PIN_CFG(33, GPIO)
+#define GPIO33_MSP1_TXD         PIN_CFG(33, ALT_A)
+#define GPIO33_MSP1_RXD         PIN_CFG(33, ALT_B)
+#define GPIO33_U0_DTRn          PIN_CFG(33, ALT_C)
+
+#define GPIO34_GPIO             PIN_CFG(34, GPIO)
+#define GPIO34_MSP1_TFS         PIN_CFG(34, ALT_A)
+#define GPIO34_NONE             PIN_CFG(34, ALT_B)
+#define GPIO34_U0_DCDn          PIN_CFG(34, ALT_C)
+
+#define GPIO35_GPIO             PIN_CFG(35, GPIO)
+#define GPIO35_MSP1_TCK         PIN_CFG(35, ALT_A)
+#define GPIO35_NONE             PIN_CFG(35, ALT_B)
+#define GPIO35_U0_DSRn          PIN_CFG(35, ALT_C)
+
+#define GPIO36_GPIO             PIN_CFG(36, GPIO)
+#define GPIO36_MSP1_RXD         PIN_CFG(36, ALT_A)
+#define GPIO36_MSP1_TXD         PIN_CFG(36, ALT_B)
+#define GPIO36_U0_RIn           PIN_CFG(36, ALT_C)
+
+#define GPIO64_GPIO             PIN_CFG(64, GPIO)
+#define GPIO64_LCDB_DE          PIN_CFG(64, ALT_A)
+#define GPIO64_KP_O1            PIN_CFG(64, ALT_B)
+#define GPIO64_IP_GPIO4         PIN_CFG(64, ALT_C)
+
+#define GPIO65_GPIO             PIN_CFG(65, GPIO)
+#define GPIO65_LCDB_HSO         PIN_CFG(65, ALT_A)
+#define GPIO65_KP_O0            PIN_CFG(65, ALT_B)
+#define GPIO65_IP_GPIO5         PIN_CFG(65, ALT_C)
+
+#define GPIO66_GPIO             PIN_CFG(66, GPIO)
+#define GPIO66_LCDB_VSO         PIN_CFG(66, ALT_A)
+#define GPIO66_KP_I1            PIN_CFG(66, ALT_B)
+#define GPIO66_IP_GPIO6         PIN_CFG(66, ALT_C)
+
+#define GPIO67_GPIO             PIN_CFG(67, GPIO)
+#define GPIO67_LCDB_CLK         PIN_CFG(67, ALT_A)
+#define GPIO67_KP_I0            PIN_CFG(67, ALT_B)
+#define GPIO67_IP_GPIO7         PIN_CFG(67, ALT_C)
+
+#define GPIO68_GPIO             PIN_CFG(68, GPIO)
+#define GPIO68_LCD_VSI0         PIN_CFG(68, ALT_A)
+#define GPIO68_KP_O7            PIN_CFG(68, ALT_B)
+#define GPIO68_SM_CLE           PIN_CFG(68, ALT_C)
+
+#define GPIO69_GPIO             PIN_CFG(69, GPIO)
+#define GPIO69_LCD_VSI1         PIN_CFG(69, ALT_A)
+#define GPIO69_KP_I7            PIN_CFG(69, ALT_B)
+#define GPIO69_SM_ALE           PIN_CFG(69, ALT_C)
+
+#define GPIO70_GPIO             PIN_CFG(70, GPIO)
+#define GPIO70_LCD_D0           PIN_CFG(70, ALT_A)
+#define GPIO70_KP_O5            PIN_CFG(70, ALT_B)
+#define GPIO70_STMAPE_CLK       PIN_CFG(70, ALT_C)
+
+#define GPIO71_GPIO             PIN_CFG(71, GPIO)
+#define GPIO71_LCD_D1           PIN_CFG(71, ALT_A)
+#define GPIO71_KP_O4            PIN_CFG(71, ALT_B)
+#define GPIO71_STMAPE_DAT3      PIN_CFG(71, ALT_C)
+
+#define GPIO72_GPIO             PIN_CFG(72, GPIO)
+#define GPIO72_LCD_D2           PIN_CFG(72, ALT_A)
+#define GPIO72_KP_O3            PIN_CFG(72, ALT_B)
+#define GPIO72_STMAPE_DAT2      PIN_CFG(72, ALT_C)
+
+#define GPIO73_GPIO             PIN_CFG(73, GPIO)
+#define GPIO73_LCD_D3           PIN_CFG(73, ALT_A)
+#define GPIO73_KP_O2            PIN_CFG(73, ALT_B)
+#define GPIO73_STMAPE_DAT1      PIN_CFG(73, ALT_C)
+
+#define GPIO74_GPIO             PIN_CFG(74, GPIO)
+#define GPIO74_LCD_D4           PIN_CFG(74, ALT_A)
+#define GPIO74_KP_I5            PIN_CFG(74, ALT_B)
+#define GPIO74_STMAPE_DAT0      PIN_CFG(74, ALT_C)
+
+#define GPIO75_GPIO             PIN_CFG(75, GPIO)
+#define GPIO75_LCD_D5           PIN_CFG(75, ALT_A)
+#define GPIO75_KP_I4            PIN_CFG(75, ALT_B)
+#define GPIO75_U2_RXD           PIN_CFG(75, ALT_C)
+
+#define GPIO76_GPIO             PIN_CFG(76, GPIO)
+#define GPIO76_LCD_D6           PIN_CFG(76, ALT_A)
+#define GPIO76_KP_I3            PIN_CFG(76, ALT_B)
+#define GPIO76_U2_TXD           PIN_CFG(76, ALT_C)
+
+#define GPIO77_GPIO             PIN_CFG(77, GPIO)
+#define GPIO77_LCD_D7           PIN_CFG(77, ALT_A)
+#define GPIO77_KP_I2            PIN_CFG(77, ALT_B)
+#define GPIO77_NONE             PIN_CFG(77, ALT_C)
+
+#define GPIO78_GPIO             PIN_CFG(78, GPIO)
+#define GPIO78_LCD_D8           PIN_CFG(78, ALT_A)
+#define GPIO78_KP_O6            PIN_CFG(78, ALT_B)
+#define GPIO78_IP_GPIO2         PIN_CFG(78, ALT_C)
+
+#define GPIO79_GPIO             PIN_CFG(79, GPIO)
+#define GPIO79_LCD_D9           PIN_CFG(79, ALT_A)
+#define GPIO79_KP_I6            PIN_CFG(79, ALT_B)
+#define GPIO79_IP_GPIO3         PIN_CFG(79, ALT_C)
+
+#define GPIO80_GPIO             PIN_CFG(80, GPIO)
+#define GPIO80_LCD_D10          PIN_CFG(80, ALT_A)
+#define GPIO80_KP_SKA0          PIN_CFG(80, ALT_B)
+#define GPIO80_IP_GPIO4         PIN_CFG(80, ALT_C)
+
+#define GPIO81_GPIO             PIN_CFG(81, GPIO)
+#define GPIO81_LCD_D11          PIN_CFG(81, ALT_A)
+#define GPIO81_KP_SKB0          PIN_CFG(81, ALT_B)
+#define GPIO81_IP_GPIO5         PIN_CFG(81, ALT_C)
+
+#define GPIO82_GPIO             PIN_CFG(82, GPIO)
+#define GPIO82_LCD_D12          PIN_CFG(82, ALT_A)
+#define GPIO82_KP_O5            PIN_CFG(82, ALT_B)
+
+#define GPIO83_GPIO             PIN_CFG(83, GPIO)
+#define GPIO83_LCD_D13          PIN_CFG(83, ALT_A)
+#define GPIO83_KP_O4            PIN_CFG(83, ALT_B)
+
+#define GPIO84_GPIO             PIN_CFG(84, GPIO)
+#define GPIO84_LCD_D14          PIN_CFG(84, ALT_A)
+#define GPIO84_KP_I5            PIN_CFG(84, ALT_B)
+
+#define GPIO85_GPIO             PIN_CFG(85, GPIO)
+#define GPIO85_LCD_D15          PIN_CFG(85, ALT_A)
+#define GPIO85_KP_I4            PIN_CFG(85, ALT_B)
+
+#define GPIO86_GPIO             PIN_CFG(86, GPIO)
+#define GPIO86_LCD_D16          PIN_CFG(86, ALT_A)
+#define GPIO86_SM_ADQ0          PIN_CFG(86, ALT_B)
+#define GPIO86_MC5_DAT0         PIN_CFG(86, ALT_C)
+
+#define GPIO87_GPIO             PIN_CFG(87, GPIO)
+#define GPIO87_LCD_D17          PIN_CFG(87, ALT_A)
+#define GPIO87_SM_ADQ1          PIN_CFG(87, ALT_B)
+#define GPIO87_MC5_DAT1         PIN_CFG(87, ALT_C)
+
+#define GPIO88_GPIO             PIN_CFG(88, GPIO)
+#define GPIO88_LCD_D18          PIN_CFG(88, ALT_A)
+#define GPIO88_SM_ADQ2          PIN_CFG(88, ALT_B)
+#define GPIO88_MC5_DAT2         PIN_CFG(88, ALT_C)
+
+#define GPIO89_GPIO             PIN_CFG(89, GPIO)
+#define GPIO89_LCD_D19          PIN_CFG(89, ALT_A)
+#define GPIO89_SM_ADQ3          PIN_CFG(89, ALT_B)
+#define GPIO89_MC5_DAT3         PIN_CFG(89, ALT_C)
+
+#define GPIO90_GPIO             PIN_CFG(90, GPIO)
+#define GPIO90_LCD_D20          PIN_CFG(90, ALT_A)
+#define GPIO90_SM_ADQ4          PIN_CFG(90, ALT_B)
+#define GPIO90_MC5_CMD          PIN_CFG(90, ALT_C)
+
+#define GPIO91_GPIO             PIN_CFG(91, GPIO)
+#define GPIO91_LCD_D21          PIN_CFG(91, ALT_A)
+#define GPIO91_SM_ADQ5          PIN_CFG(91, ALT_B)
+#define GPIO91_MC5_FBCLK        PIN_CFG(91, ALT_C)
+
+#define GPIO92_GPIO             PIN_CFG(92, GPIO)
+#define GPIO92_LCD_D22          PIN_CFG(92, ALT_A)
+#define GPIO92_SM_ADQ6          PIN_CFG(92, ALT_B)
+#define GPIO92_MC5_CLK          PIN_CFG(92, ALT_C)
+
+#define GPIO93_GPIO             PIN_CFG(93, GPIO)
+#define GPIO93_LCD_D23          PIN_CFG(93, ALT_A)
+#define GPIO93_SM_ADQ7          PIN_CFG(93, ALT_B)
+#define GPIO93_MC5_DAT4         PIN_CFG(93, ALT_C)
+
+#define GPIO94_GPIO             PIN_CFG(94, GPIO)
+#define GPIO94_KP_O7            PIN_CFG(94, ALT_A)
+#define GPIO94_SM_ADVn          PIN_CFG(94, ALT_B)
+#define GPIO94_MC5_DAT5         PIN_CFG(94, ALT_C)
+
+#define GPIO95_GPIO             PIN_CFG(95, GPIO)
+#define GPIO95_KP_I7            PIN_CFG(95, ALT_A)
+#define GPIO95_SM_CS0n          PIN_CFG(95, ALT_B)
+#define GPIO95_SM_PS0n          PIN_CFG(95, ALT_C)
+
+#define GPIO96_GPIO             PIN_CFG(96, GPIO)
+#define GPIO96_KP_O6            PIN_CFG(96, ALT_A)
+#define GPIO96_SM_OEn           PIN_CFG(96, ALT_B)
+#define GPIO96_MC5_DAT6         PIN_CFG(96, ALT_C)
+
+#define GPIO97_GPIO             PIN_CFG(97, GPIO)
+#define GPIO97_KP_I6            PIN_CFG(97, ALT_A)
+#define GPIO97_SM_WEn           PIN_CFG(97, ALT_B)
+#define GPIO97_MC5_DAT7         PIN_CFG(97, ALT_C)
+
+#define GPIO128_GPIO            PIN_CFG(128, GPIO)
+#define GPIO128_MC2_CLK         PIN_CFG(128, ALT_A)
+#define GPIO128_SM_CKO          PIN_CFG(128, ALT_B)
+
+#define GPIO129_GPIO            PIN_CFG(129, GPIO)
+#define GPIO129_MC2_CMD         PIN_CFG(129, ALT_A)
+#define GPIO129_SM_WAIT0n       PIN_CFG(129, ALT_B)
+
+#define GPIO130_GPIO            PIN_CFG(130, GPIO)
+#define GPIO130_MC2_FBCLK       PIN_CFG(130, ALT_A)
+#define GPIO130_SM_FBCLK        PIN_CFG(130, ALT_B)
+#define GPIO130_MC2_RSTN        PIN_CFG(130, ALT_C)
+
+#define GPIO131_GPIO            PIN_CFG(131, GPIO)
+#define GPIO131_MC2_DAT0        PIN_CFG(131, ALT_A)
+#define GPIO131_SM_ADQ8         PIN_CFG(131, ALT_B)
+
+#define GPIO132_GPIO            PIN_CFG(132, GPIO)
+#define GPIO132_MC2_DAT1        PIN_CFG(132, ALT_A)
+#define GPIO132_SM_ADQ9         PIN_CFG(132, ALT_B)
+
+#define GPIO133_GPIO            PIN_CFG(133, GPIO)
+#define GPIO133_MC2_DAT2        PIN_CFG(133, ALT_A)
+#define GPIO133_SM_ADQ10        PIN_CFG(133, ALT_B)
+
+#define GPIO134_GPIO            PIN_CFG(134, GPIO)
+#define GPIO134_MC2_DAT3        PIN_CFG(134, ALT_A)
+#define GPIO134_SM_ADQ11        PIN_CFG(134, ALT_B)
+
+#define GPIO135_GPIO            PIN_CFG(135, GPIO)
+#define GPIO135_MC2_DAT4        PIN_CFG(135, ALT_A)
+#define GPIO135_SM_ADQ12        PIN_CFG(135, ALT_B)
+
+#define GPIO136_GPIO            PIN_CFG(136, GPIO)
+#define GPIO136_MC2_DAT5        PIN_CFG(136, ALT_A)
+#define GPIO136_SM_ADQ13        PIN_CFG(136, ALT_B)
+
+#define GPIO137_GPIO            PIN_CFG(137, GPIO)
+#define GPIO137_MC2_DAT6        PIN_CFG(137, ALT_A)
+#define GPIO137_SM_ADQ14        PIN_CFG(137, ALT_B)
+
+#define GPIO138_GPIO            PIN_CFG(138, GPIO)
+#define GPIO138_MC2_DAT7        PIN_CFG(138, ALT_A)
+#define GPIO138_SM_ADQ15        PIN_CFG(138, ALT_B)
+
+#define GPIO139_GPIO            PIN_CFG(139, GPIO)
+#define GPIO139_SSP1_RXD        PIN_CFG(139, ALT_A)
+#define GPIO139_SM_WAIT1n       PIN_CFG(139, ALT_B)
+#define GPIO139_KP_O8           PIN_CFG(139, ALT_C)
+
+#define GPIO140_GPIO            PIN_CFG(140, GPIO)
+#define GPIO140_SSP1_TXD        PIN_CFG(140, ALT_A)
+#define GPIO140_IP_GPIO7        PIN_CFG(140, ALT_B)
+#define GPIO140_KP_SKA1         PIN_CFG(140, ALT_C)
+
+#define GPIO141_GPIO            PIN_CFG(141, GPIO)
+#define GPIO141_SSP1_CLK        PIN_CFG(141, ALT_A)
+#define GPIO141_IP_GPIO2        PIN_CFG(141, ALT_B)
+#define GPIO141_KP_O9           PIN_CFG(141, ALT_C)
+
+#define GPIO142_GPIO            PIN_CFG(142, GPIO)
+#define GPIO142_SSP1_FRM        PIN_CFG(142, ALT_A)
+#define GPIO142_IP_GPIO3        PIN_CFG(142, ALT_B)
+#define GPIO142_KP_SKB1         PIN_CFG(142, ALT_C)
+
+#define GPIO143_GPIO            PIN_CFG(143, GPIO)
+#define GPIO143_SSP0_CLK        PIN_CFG(143, ALT_A)
+
+#define GPIO144_GPIO            PIN_CFG(144, GPIO)
+#define GPIO144_SSP0_FRM        PIN_CFG(144, ALT_A)
+
+#define GPIO145_GPIO            PIN_CFG(145, GPIO)
+#define GPIO145_SSP0_RXD        PIN_CFG(145, ALT_A)
+
+#define GPIO146_GPIO            PIN_CFG(146, GPIO)
+#define GPIO146_SSP0_TXD        PIN_CFG(146, ALT_A)
+
+#define GPIO147_GPIO            PIN_CFG(147, GPIO)
+#define GPIO147_I2C0_SCL        PIN_CFG_PULL(147, ALT_A, UP)
+
+#define GPIO148_GPIO            PIN_CFG(148, GPIO)
+#define GPIO148_I2C0_SDA        PIN_CFG_PULL(148, ALT_A, UP)
+
+#define GPIO149_GPIO            PIN_CFG(149, GPIO)
+#define GPIO149_IP_GPIO0        PIN_CFG(149, ALT_A)
+#define GPIO149_SM_CS1n         PIN_CFG(149, ALT_B)
+#define GPIO149_SM_PS1n         PIN_CFG(149, ALT_C)
+
+#define GPIO150_GPIO            PIN_CFG(150, GPIO)
+#define GPIO150_IP_GPIO1        PIN_CFG(150, ALT_A)
+#define GPIO150_LCDA_CLK        PIN_CFG(150, ALT_B)
+
+#define GPIO151_GPIO            PIN_CFG(151, GPIO)
+#define GPIO151_KP_SKA0         PIN_CFG(151, ALT_A)
+#define GPIO151_LCD_VSI0        PIN_CFG(151, ALT_B)
+#define GPIO151_KP_O8           PIN_CFG(151, ALT_C)
+
+#define GPIO152_GPIO            PIN_CFG(152, GPIO)
+#define GPIO152_KP_SKB0         PIN_CFG(152, ALT_A)
+#define GPIO152_LCD_VSI1        PIN_CFG(152, ALT_B)
+#define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
+
+#define GPIO153_GPIO            PIN_CFG(153, GPIO)
+#define GPIO153_KP_I7           PIN_CFG(153, ALT_A)
+#define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
+#define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
+
+#define GPIO154_GPIO            PIN_CFG(154, GPIO)
+#define GPIO154_KP_I6           PIN_CFG(154, ALT_A)
+#define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
+#define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
+
+#define GPIO155_GPIO            PIN_CFG(155, GPIO)
+#define GPIO155_KP_I5           PIN_CFG(155, ALT_A)
+#define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
+#define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
+
+#define GPIO156_GPIO            PIN_CFG(156, GPIO)
+#define GPIO156_KP_I4           PIN_CFG(156, ALT_A)
+#define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
+#define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
+
+#define GPIO157_GPIO            PIN_CFG(157, GPIO)
+#define GPIO157_KP_O7           PIN_CFG(157, ALT_A)
+#define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
+#define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
+
+#define GPIO158_GPIO            PIN_CFG(158, GPIO)
+#define GPIO158_KP_O6           PIN_CFG(158, ALT_A)
+#define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
+#define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
+
+#define GPIO159_GPIO            PIN_CFG(159, GPIO)
+#define GPIO159_KP_O5           PIN_CFG(159, ALT_A)
+#define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
+#define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
+
+#define GPIO160_GPIO            PIN_CFG(160, GPIO)
+#define GPIO160_KP_O4           PIN_CFG(160, ALT_A)
+#define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
+#define GPIO160_NONE            PIN_CFG(160, ALT_C)
+
+#define GPIO161_GPIO            PIN_CFG(161, GPIO)
+#define GPIO161_KP_I3           PIN_CFG(161, ALT_A)
+#define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
+#define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
+
+#define GPIO162_GPIO            PIN_CFG(162, GPIO)
+#define GPIO162_KP_I2           PIN_CFG(162, ALT_A)
+#define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
+#define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
+
+#define GPIO163_GPIO            PIN_CFG(163, GPIO)
+#define GPIO163_KP_I1           PIN_CFG(163, ALT_A)
+#define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
+#define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
+
+#define GPIO164_GPIO            PIN_CFG(164, GPIO)
+#define GPIO164_KP_I0           PIN_CFG(164, ALT_A)
+#define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
+#define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
+
+#define GPIO165_GPIO            PIN_CFG(165, GPIO)
+#define GPIO165_KP_O3           PIN_CFG(165, ALT_A)
+#define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
+#define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
+
+#define GPIO166_GPIO            PIN_CFG(166, GPIO)
+#define GPIO166_KP_O2           PIN_CFG(166, ALT_A)
+#define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
+#define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
+
+#define GPIO167_GPIO            PIN_CFG(167, GPIO)
+#define GPIO167_KP_O1           PIN_CFG(167, ALT_A)
+#define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
+#define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
+
+#define GPIO168_GPIO            PIN_CFG(168, GPIO)
+#define GPIO168_KP_O0           PIN_CFG(168, ALT_A)
+#define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
+#define GPIO168_NONE            PIN_CFG(168, ALT_C)
+
+#define GPIO169_GPIO            PIN_CFG(169, GPIO)
+#define GPIO169_RF_PURn         PIN_CFG(169, ALT_A)
+#define GPIO169_LCDA_DE         PIN_CFG(169, ALT_B)
+#define GPIO169_USBSIM_PDC      PIN_CFG(169, ALT_C)
+
+#define GPIO170_GPIO            PIN_CFG(170, GPIO)
+#define GPIO170_MODEM_STATE     PIN_CFG(170, ALT_A)
+#define GPIO170_LCDA_VSO        PIN_CFG(170, ALT_B)
+#define GPIO170_KP_SKA1         PIN_CFG(170, ALT_C)
+
+#define GPIO171_GPIO            PIN_CFG(171, GPIO)
+#define GPIO171_MODEM_PWREN     PIN_CFG(171, ALT_A)
+#define GPIO171_LCDA_HSO        PIN_CFG(171, ALT_B)
+#define GPIO171_KP_SKB1         PIN_CFG(171, ALT_C)
+
+#define GPIO192_GPIO            PIN_CFG(192, GPIO)
+#define GPIO192_MSP2_SCK        PIN_CFG(192, ALT_A)
+
+#define GPIO193_GPIO            PIN_CFG(193, GPIO)
+#define GPIO193_MSP2_TXD        PIN_CFG(193, ALT_A)
+
+#define GPIO194_GPIO            PIN_CFG(194, GPIO)
+#define GPIO194_MSP2_TCK        PIN_CFG(194, ALT_A)
+
+#define GPIO195_GPIO            PIN_CFG(195, GPIO)
+#define GPIO195_MSP2_TFS        PIN_CFG(195, ALT_A)
+
+#define GPIO196_GPIO            PIN_CFG(196, GPIO)
+#define GPIO196_MSP2_RXD        PIN_CFG(196, ALT_A)
+
+#define GPIO197_GPIO            PIN_CFG(197, GPIO)
+#define GPIO197_MC4_DAT3        PIN_CFG(197, ALT_A)
+
+#define GPIO198_GPIO            PIN_CFG(198, GPIO)
+#define GPIO198_MC4_DAT2        PIN_CFG(198, ALT_A)
+
+#define GPIO199_GPIO            PIN_CFG(199, GPIO)
+#define GPIO199_MC4_DAT1        PIN_CFG(199, ALT_A)
+
+#define GPIO200_GPIO            PIN_CFG(200, GPIO)
+#define GPIO200_MC4_DAT0        PIN_CFG(200, ALT_A)
+
+#define GPIO201_GPIO            PIN_CFG(201, GPIO)
+#define GPIO201_MC4_CMD         PIN_CFG(201, ALT_A)
+
+#define GPIO202_GPIO            PIN_CFG(202, GPIO)
+#define GPIO202_MC4_FBCLK       PIN_CFG(202, ALT_A)
+#define GPIO202_PWL             PIN_CFG(202, ALT_B)
+#define GPIO202_MC4_RSTN        PIN_CFG(202, ALT_C)
+
+#define GPIO203_GPIO            PIN_CFG(203, GPIO)
+#define GPIO203_MC4_CLK         PIN_CFG(203, ALT_A)
+
+#define GPIO204_GPIO            PIN_CFG(204, GPIO)
+#define GPIO204_MC4_DAT7        PIN_CFG(204, ALT_A)
+
+#define GPIO205_GPIO            PIN_CFG(205, GPIO)
+#define GPIO205_MC4_DAT6        PIN_CFG(205, ALT_A)
+
+#define GPIO206_GPIO            PIN_CFG(206, GPIO)
+#define GPIO206_MC4_DAT5        PIN_CFG(206, ALT_A)
+
+#define GPIO207_GPIO            PIN_CFG(207, GPIO)
+#define GPIO207_MC4_DAT4        PIN_CFG(207, ALT_A)
+
+#define GPIO208_GPIO            PIN_CFG(208, GPIO)
+#define GPIO208_MC1_CLK         PIN_CFG(208, ALT_A)
+
+#define GPIO209_GPIO            PIN_CFG(209, GPIO)
+#define GPIO209_MC1_FBCLK       PIN_CFG(209, ALT_A)
+#define GPIO209_SPI1_CLK        PIN_CFG(209, ALT_B)
+
+#define GPIO210_GPIO            PIN_CFG(210, GPIO)
+#define GPIO210_MC1_CMD         PIN_CFG(210, ALT_A)
+
+#define GPIO211_GPIO            PIN_CFG(211, GPIO)
+#define GPIO211_MC1_DAT0        PIN_CFG(211, ALT_A)
+
+#define GPIO212_GPIO            PIN_CFG(212, GPIO)
+#define GPIO212_MC1_DAT1        PIN_CFG(212, ALT_A)
+#define GPIO212_SPI1_FRM        PIN_CFG(212, ALT_B)
+
+#define GPIO213_GPIO            PIN_CFG(213, GPIO)
+#define GPIO213_MC1_DAT2        PIN_CFG(213, ALT_A)
+#define GPIO213_SPI1_TXD        PIN_CFG(213, ALT_B)
+
+#define GPIO214_GPIO            PIN_CFG(214, GPIO)
+#define GPIO214_MC1_DAT3        PIN_CFG(214, ALT_A)
+#define GPIO214_SPI1_RXD        PIN_CFG(214, ALT_B)
+
+#define GPIO215_GPIO            PIN_CFG(215, GPIO)
+#define GPIO215_MC1_CMDDIR      PIN_CFG(215, ALT_A)
+#define GPIO215_MC3_DAT2DIR     PIN_CFG(215, ALT_B)
+#define GPIO215_CLKOUT1         PIN_CFG(215, ALT_C)
+
+#define GPIO216_GPIO            PIN_CFG(216, GPIO)
+#define GPIO216_MC1_DAT2DIR     PIN_CFG(216, ALT_A)
+#define GPIO216_MC3_CMDDIR      PIN_CFG(216, ALT_B)
+#define GPIO216_I2C3_SDA        PIN_CFG_PULL(216, ALT_C, UP)
+
+#define GPIO217_GPIO            PIN_CFG(217, GPIO)
+#define GPIO217_MC1_DAT0DIR     PIN_CFG(217, ALT_A)
+#define GPIO217_MC3_DAT31DIR    PIN_CFG(217, ALT_B)
+#define GPIO217_CLKOUT2         PIN_CFG(217, ALT_C)
+
+#define GPIO218_GPIO            PIN_CFG(218, GPIO)
+#define GPIO218_MC1_DAT31DIR    PIN_CFG(218, ALT_A)
+#define GPIO218_MC3_DAT0DIR     PIN_CFG(218, ALT_B)
+#define GPIO218_I2C3_SCL        PIN_CFG_PULL(218, ALT_C, UP)
+
+#define GPIO219_GPIO            PIN_CFG(219, GPIO)
+#define GPIO219_HSIR_FLA0       PIN_CFG(219, ALT_A)
+#define GPIO219_MC3_CLK         PIN_CFG(219, ALT_B)
+
+#define GPIO220_GPIO            PIN_CFG(220, GPIO)
+#define GPIO220_HSIR_DAT0       PIN_CFG(220, ALT_A)
+#define GPIO220_MC3_FBCLK       PIN_CFG(220, ALT_B)
+#define GPIO220_SPI0_CLK        PIN_CFG(220, ALT_C)
+
+#define GPIO221_GPIO            PIN_CFG(221, GPIO)
+#define GPIO221_HSIR_RDY0       PIN_CFG(221, ALT_A)
+#define GPIO221_MC3_CMD         PIN_CFG(221, ALT_B)
+
+#define GPIO222_GPIO            PIN_CFG(222, GPIO)
+#define GPIO222_HSIT_FLA0       PIN_CFG(222, ALT_A)
+#define GPIO222_MC3_DAT0        PIN_CFG(222, ALT_B)
+
+#define GPIO223_GPIO            PIN_CFG(223, GPIO)
+#define GPIO223_HSIT_DAT0       PIN_CFG(223, ALT_A)
+#define GPIO223_MC3_DAT1        PIN_CFG(223, ALT_B)
+#define GPIO223_SPI0_FRM        PIN_CFG(223, ALT_C)
+
+#define GPIO224_GPIO            PIN_CFG(224, GPIO)
+#define GPIO224_HSIT_RDY0       PIN_CFG(224, ALT_A)
+#define GPIO224_MC3_DAT2        PIN_CFG(224, ALT_B)
+#define GPIO224_SPI0_TXD        PIN_CFG(224, ALT_C)
+
+#define GPIO225_GPIO            PIN_CFG(225, GPIO)
+#define GPIO225_HSIT_CAWAKE0    PIN_CFG(225, ALT_A)
+#define GPIO225_MC3_DAT3        PIN_CFG(225, ALT_B)
+#define GPIO225_SPI0_RXD        PIN_CFG(225, ALT_C)
+
+#define GPIO226_GPIO            PIN_CFG(226, GPIO)
+#define GPIO226_HSIT_ACWAKE0    PIN_CFG(226, ALT_A)
+#define GPIO226_PWL             PIN_CFG(226, ALT_B)
+#define GPIO226_USBSIM_PDC      PIN_CFG(226, ALT_C)
+
+#define GPIO227_GPIO            PIN_CFG(227, GPIO)
+#define GPIO227_CLKOUT1         PIN_CFG(227, ALT_A)
+
+#define GPIO228_GPIO            PIN_CFG(228, GPIO)
+#define GPIO228_CLKOUT2         PIN_CFG(228, ALT_A)
+
+#define GPIO229_GPIO            PIN_CFG(229, GPIO)
+#define GPIO229_CLKOUT1         PIN_CFG(229, ALT_A)
+#define GPIO229_PWL             PIN_CFG(229, ALT_B)
+#define GPIO229_I2C3_SDA        PIN_CFG_PULL(229, ALT_C, UP)
+
+#define GPIO230_GPIO            PIN_CFG(230, GPIO)
+#define GPIO230_CLKOUT2         PIN_CFG(230, ALT_A)
+#define GPIO230_PWL             PIN_CFG(230, ALT_B)
+#define GPIO230_I2C3_SCL        PIN_CFG_PULL(230, ALT_C, UP)
+
+#define GPIO256_GPIO            PIN_CFG(256, GPIO)
+#define GPIO256_USB_NXT         PIN_CFG(256, ALT_A)
+
+#define GPIO257_GPIO            PIN_CFG(257, GPIO)
+#define GPIO257_USB_STP         PIN_CFG(257, ALT_A)
+
+#define GPIO258_GPIO            PIN_CFG(258, GPIO)
+#define GPIO258_USB_XCLK        PIN_CFG(258, ALT_A)
+#define GPIO258_NONE            PIN_CFG(258, ALT_B)
+#define GPIO258_DDR_TRIG        PIN_CFG(258, ALT_C)
+
+#define GPIO259_GPIO            PIN_CFG(259, GPIO)
+#define GPIO259_USB_DIR         PIN_CFG(259, ALT_A)
+
+#define GPIO260_GPIO            PIN_CFG(260, GPIO)
+#define GPIO260_USB_DAT7        PIN_CFG(260, ALT_A)
+
+#define GPIO261_GPIO            PIN_CFG(261, GPIO)
+#define GPIO261_USB_DAT6        PIN_CFG(261, ALT_A)
+
+#define GPIO262_GPIO            PIN_CFG(262, GPIO)
+#define GPIO262_USB_DAT5        PIN_CFG(262, ALT_A)
+
+#define GPIO263_GPIO            PIN_CFG(263, GPIO)
+#define GPIO263_USB_DAT4        PIN_CFG(263, ALT_A)
+
+#define GPIO264_GPIO            PIN_CFG(264, GPIO)
+#define GPIO264_USB_DAT3        PIN_CFG(264, ALT_A)
+
+#define GPIO265_GPIO            PIN_CFG(265, GPIO)
+#define GPIO265_USB_DAT2        PIN_CFG(265, ALT_A)
+
+#define GPIO266_GPIO            PIN_CFG(266, GPIO)
+#define GPIO266_USB_DAT1        PIN_CFG(266, ALT_A)
+
+#define GPIO267_GPIO            PIN_CFG(267, GPIO)
+#define GPIO267_USB_DAT0        PIN_CFG(267, ALT_A)
+
+#endif
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3dff8641b03f..e38acb0f89c8 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -28,6 +28,7 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/pl022.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
 
@@ -354,6 +355,21 @@ static struct mmci_platform_data mmc0_plat_data = {
         .gpio_cd        = -1,
 };
 
+static struct resource char_lcd_resources[] = {
+        {
+                .start = VERSATILE_CHAR_LCD_BASE,
+                .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device char_lcd_device = {
+        .name           =       "arm-charlcd",
+        .id             =       -1,
+        .num_resources  =       ARRAY_SIZE(char_lcd_resources),
+        .resource       =       char_lcd_resources,
+};
+
 /*
  * Clock handling
  */
@@ -400,8 +416,13 @@ static struct clk ref24_clk = {
         .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup lookups[] = {
-        {       /* UART0 */
+        {       /* AMBA bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "dev:f1",
                 .clk            = &ref24_clk,
         }, {    /* UART1 */
@@ -425,6 +446,9 @@ static struct clk_lookup lookups[] = {
         }, {    /* MMC1 */
                 .dev_id         = "fpga:0b",
                 .clk            = &ref24_clk,
+        }, {    /* SSP */
+                .dev_id         = "dev:f4",
+                .clk            = &ref24_clk,
         }, {    /* CLCD */
                 .dev_id         = "dev:20",
                 .clk            = &osc4_clk,
@@ -703,6 +727,12 @@ static struct pl061_platform_data gpio1_plat_data = {
         .irq_base       = IRQ_GPIO1_START,
 };
 
+static struct pl022_ssp_controller ssp0_plat_data = {
+        .bus_id = 0,
+        .enable_dma = 0,
+        .num_chipselect = 1,
+};
+
 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 #define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
@@ -772,7 +802,7 @@ AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
-AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
+AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -843,6 +873,7 @@ void __init versatile_init(void)
         platform_device_register(&versatile_flash_device);
         platform_device_register(&versatile_i2c_device);
         platform_device_register(&smc91x_device);
+        platform_device_register(&char_lcd_device);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 334f0df4e948..13c7e5f90a82 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -304,7 +304,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 }
 
 
-struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
 {
         return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
 }
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 6353459bb567..577df6cccb08 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -16,6 +16,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/smp_twd.h>
 
 #include <mach/clkdev.h>
 #include <mach/ct-ca9x4.h>
@@ -53,6 +54,7 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = {
 
 static void __init ct_ca9x4_map_io(void)
 {
+        twd_base = MMIO_P2V(A9_MPCORE_TWD);
         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index 8650f04136ef..f9e2f8d22962 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -28,6 +28,7 @@
 #define A9_MPCORE_SCU           (CT_CA9X4_MPIC + 0x0000)
 #define A9_MPCORE_GIC_CPU       (CT_CA9X4_MPIC + 0x0100)
 #define A9_MPCORE_GIT           (CT_CA9X4_MPIC + 0x0200)
+#define A9_MPCORE_TWD           (CT_CA9X4_MPIC + 0x0600)
 #define A9_MPCORE_GIC_DIST      (CT_CA9X4_MPIC + 0x1000)
 
 /*
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index d250711b8c7a..817f0ad38a0b 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -241,7 +241,7 @@ static struct platform_device v2m_flash_device = {
 
 static unsigned int v2m_mmci_status(struct device *dev)
 {
-        return !(readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0));
+        return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
 }
 
 static struct mmci_platform_data v2m_mmci_data = {
@@ -298,8 +298,13 @@ static struct clk osc2_clk = {
         .rate   = 24000000,
 };
 
+static struct clk dummy_apb_pclk;
+
 static struct clk_lookup v2m_lookups[] = {
-        {       /* UART0 */
+        {       /* AMBA bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* UART0 */
                 .dev_id         = "mb:uart0",
                 .clk            = &osc2_clk,
         }, {    /* UART1 */
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index b2eda4dc1c34..7a1fa6adb7c3 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -36,6 +36,8 @@
 #include <mach/nuc900_spi.h>
 #include <mach/map.h>
 #include <mach/fb.h>
+#include <mach/regs-ldm.h>
+#include <mach/w90p910_keypad.h>
 
 #include "cpu.h"
 
@@ -207,7 +209,7 @@ static struct nuc900_spi_info nuc900_spiflash_data = {
         .divider        = 24,
         .sleep          = 0,
         .txnum          = 0,
-        .txbitlen       = 1,
+        .txbitlen       = 8,
         .bus_num        = 0,
 };
 
@@ -256,7 +258,7 @@ static struct spi_board_info nuc900_spi_board_info[] __initdata = {
                 .modalias = "m25p80",
                 .max_speed_hz = 20000000,
                 .bus_num = 0,
-                .chip_select = 1,
+                .chip_select = 0,
                 .platform_data = &nuc900_spi_flash_data,
                 .mode = SPI_MODE_0,
         },
@@ -361,6 +363,39 @@ struct platform_device nuc900_device_fmi = {
 
 /* KPI controller*/
 
+static int nuc900_keymap[] = {
+        KEY(0, 0, KEY_A),
+        KEY(0, 1, KEY_B),
+        KEY(0, 2, KEY_C),
+        KEY(0, 3, KEY_D),
+
+        KEY(1, 0, KEY_E),
+        KEY(1, 1, KEY_F),
+        KEY(1, 2, KEY_G),
+        KEY(1, 3, KEY_H),
+
+        KEY(2, 0, KEY_I),
+        KEY(2, 1, KEY_J),
+        KEY(2, 2, KEY_K),
+        KEY(2, 3, KEY_L),
+
+        KEY(3, 0, KEY_M),
+        KEY(3, 1, KEY_N),
+        KEY(3, 2, KEY_O),
+        KEY(3, 3, KEY_P),
+};
+
+static struct matrix_keymap_data nuc900_map_data = {
+        .keymap                 = nuc900_keymap,
+        .keymap_size            = ARRAY_SIZE(nuc900_keymap),
+};
+
+struct w90p910_keypad_platform_data nuc900_keypad_info = {
+        .keymap_data    = &nuc900_map_data,
+        .prescale       = 0xfa,
+        .debounce       = 0x50,
+};
+
 static struct resource nuc900_kpi_resource[] = {
         [0] = {
                 .start = W90X900_PA_KPI,
@@ -380,9 +415,49 @@ struct platform_device nuc900_device_kpi = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(nuc900_kpi_resource),
         .resource       = nuc900_kpi_resource,
+        .dev            = {
+                                .platform_data = &nuc900_keypad_info,
+                        }
 };
 
-#ifdef CONFIG_FB_NUC900
+/* LCD controller*/
+
+static struct nuc900fb_display __initdata nuc900_lcd_info[] = {
+        /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
+        [0] = {
+                .type           = LCM_DCCS_VA_SRC_RGB565,
+                .width          = 320,
+                .height         = 240,
+                .xres           = 320,
+                .yres           = 240,
+                .bpp            = 16,
+                .pixclock       = 200000,
+                .left_margin    = 34,
+                .right_margin   = 54,
+                .hsync_len      = 10,
+                .upper_margin   = 18,
+                .lower_margin   = 4,
+                .vsync_len      = 1,
+                .dccs           = 0x8e00041a,
+                .devctl         = 0x060800c0,
+                .fbctrl         = 0x00a000a0,
+                .scale          = 0x04000400,
+        },
+};
+
+static struct nuc900fb_mach_info nuc900_fb_info __initdata = {
+#if defined(CONFIG_GPM1040A0_320X240)
+        .displays               = &nuc900_lcd_info[0],
+#else
+        .displays               = nuc900_lcd_info,
+#endif
+        .num_displays           = ARRAY_SIZE(nuc900_lcd_info),
+        .default_display        = 0,
+        .gpio_dir               = 0x00000004,
+        .gpio_dir_mask          = 0xFFFFFFFD,
+        .gpio_data              = 0x00000004,
+        .gpio_data_mask         = 0xFFFFFFFD,
+};
 
 static struct resource nuc900_lcd_resource[] = {
         [0] = {
@@ -406,23 +481,10 @@ struct platform_device nuc900_device_lcd = {
         .dev              = {
                 .dma_mask               = &nuc900_device_lcd_dmamask,
                 .coherent_dma_mask      = -1,
+                .platform_data = &nuc900_fb_info,
         }
 };
 
-void  nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd)
-{
-        struct nuc900fb_mach_info *npd;
-
-        npd = kmalloc(sizeof(*npd), GFP_KERNEL);
-        if (npd) {
-                memcpy(npd, pd, sizeof(*npd));
-                nuc900_device_lcd.dev.platform_data = npd;
-        } else {
-                printk(KERN_ERR "no memory for LCD platform data\n");
-        }
-}
-#endif
-
 /* AUDIO controller*/
 static u64 nuc900_device_audio_dmamask = -1;
 static struct resource nuc900_ac97_resource[] = {
diff --git a/arch/arm/mach-w90x900/include/mach/regs-gcr.h b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
new file mode 100644
index 000000000000..6087abd93ef5
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/regs-gcr.h
+ *
+ * Copyright (c) 2010 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_GCR_H
+#define __ASM_ARCH_REGS_GCR_H
+
+/* Global control registers */
+
+#define GCR_BA          W90X900_VA_GCR
+#define REG_PDID        (GCR_BA+0x000)
+#define REG_PWRON       (GCR_BA+0x004)
+#define REG_ARBCON      (GCR_BA+0x008)
+#define REG_MFSEL       (GCR_BA+0x00C)
+#define REG_EBIDPE      (GCR_BA+0x010)
+#define REG_LCDDPE      (GCR_BA+0x014)
+#define REG_GPIOCPE     (GCR_BA+0x018)
+#define REG_GPIODPE     (GCR_BA+0x01C)
+#define REG_GPIOEPE     (GCR_BA+0x020)
+#define REG_GPIOFPE     (GCR_BA+0x024)
+#define REG_GPIOGPE     (GCR_BA+0x028)
+#define REG_GPIOHPE     (GCR_BA+0x02C)
+#define REG_GPIOIPE     (GCR_BA+0x030)
+#define REG_GTMP1       (GCR_BA+0x034)
+#define REG_GTMP2       (GCR_BA+0x038)
+#define REG_GTMP3       (GCR_BA+0x03C)
+
+#endif /*  __ASM_ARCH_REGS_GCR_H */
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index b3edc3cccf52..04d295f89eb0 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -20,51 +20,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <mach/map.h>
-#include <mach/regs-ldm.h>
 #include <mach/fb.h>
 
 #include "nuc950.h"
 
-#ifdef CONFIG_FB_NUC900
-/* LCD Controller */
-static struct nuc900fb_display __initdata nuc950_lcd_info[] = {
-        /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
-        [0] = {
-                .type           = LCM_DCCS_VA_SRC_RGB565,
-                .width          = 320,
-                .height         = 240,
-                .xres           = 320,
-                .yres           = 240,
-                .bpp            = 16,
-                .pixclock       = 200000,
-                .left_margin    = 34,
-                .right_margin   = 54,
-                .hsync_len      = 10,
-                .upper_margin   = 18,
-                .lower_margin   = 4,
-                .vsync_len      = 1,
-                .dccs           = 0x8e00041a,
-                .devctl         = 0x060800c0,
-                .fbctrl         = 0x00a000a0,
-                .scale          = 0x04000400,
-        },
-};
-
-static struct nuc900fb_mach_info nuc950_fb_info __initdata = {
-#if defined(CONFIG_GPM1040A0_320X240)
-        .displays               = &nuc950_lcd_info[0],
-#else
-        .displays               = nuc950_lcd_info,
-#endif
-        .num_displays           = ARRAY_SIZE(nuc950_lcd_info),
-        .default_display        = 0,
-        .gpio_dir               = 0x00000004,
-        .gpio_dir_mask          = 0xFFFFFFFD,
-        .gpio_data              = 0x00000004,
-        .gpio_data_mask         = 0xFFFFFFFD,
-};
-#endif
-
 static void __init nuc950evb_map_io(void)
 {
         nuc950_map_io();
@@ -74,9 +33,6 @@ static void __init nuc950evb_map_io(void)
 static void __init nuc950evb_init(void)
 {
         nuc950_board_init();
-#ifdef CONFIG_FB_NUC900
-        nuc900_fb_set_platdata(&nuc950_fb_info);
-#endif
 }
 
 MACHINE_START(W90P950EVB, "W90P950EVB")
diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c
index 656f03b3b629..1523f4136985 100644
--- a/arch/arm/mach-w90x900/nuc910.c
+++ b/arch/arm/mach-w90x900/nuc910.c
@@ -26,6 +26,8 @@
 static struct platform_device *nuc910_dev[] __initdata = {
         &nuc900_device_ts,
         &nuc900_device_rtc,
+        &nuc900_device_lcd,
+        &nuc900_device_kpi,
 };
 
 /* define specific CPU platform io map */
diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c
index 4d1f1ab044c4..5704f74a50ee 100644
--- a/arch/arm/mach-w90x900/nuc950.c
+++ b/arch/arm/mach-w90x900/nuc950.c
@@ -26,9 +26,7 @@
 static struct platform_device *nuc950_dev[] __initdata = {
         &nuc900_device_kpi,
         &nuc900_device_fmi,
-#ifdef CONFIG_FB_NUC900
         &nuc900_device_lcd,
-#endif
 };
 
 /* define specific CPU platform io map */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 101105e52610..87ec141fcaa6 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -717,17 +717,6 @@ config TLS_REG_EMUL
           a few prototypes like that in existence) and therefore access to
           that required register must be emulated.
 
-config HAS_TLS_REG
-        bool
-        depends on !TLS_REG_EMUL
-        default y if SMP || CPU_32v7
-        help
-          This selects support for the CP15 thread register.
-          It is defined to be available on some ARMv6 processors (including
-          all SMP capable ARMv6's) or later processors.  User space may
-          assume directly accessing that register and always obtain the
-          expected value only on ARMv7 and above.
-
 config NEEDS_SYSCALL_FOR_CMPXCHG
         bool
         help
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index e8d34a80851c..d63b6c413758 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -15,7 +15,6 @@ endif
 obj-$(CONFIG_MODULES)           += proc-syms.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)    += alignment.o
-obj-$(CONFIG_DISCONTIGMEM)      += discontig.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
 
 obj-$(CONFIG_CPU_ABRT_NOMMU)    += abort-nommu.o
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 6f98c358989a..d073b64ae87e 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -924,8 +924,20 @@ static int __init alignment_init(void)
                 ai_usermode = UM_FIXUP;
         }
 
-        hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
-        hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
+        hook_fault_code(1, do_alignment, SIGBUS, BUS_ADRALN,
+                        "alignment exception");
+
+        /*
+         * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
+         * fault, not as alignment error.
+         *
+         * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
+         * needed.
+         */
+        if (cpu_architecture() <= CPU_ARCH_ARMv6) {
+                hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
+                                "alignment exception");
+        }
 
         return 0;
 }
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index df4955885b21..9982eb385c0f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -32,14 +32,14 @@ static uint32_t l2x0_way_mask;	/* Bitmask of active ways */
 static inline void cache_wait(void __iomem *reg, unsigned long mask)
 {
         /* wait for the operation to complete */
-        while (readl(reg) & mask)
+        while (readl_relaxed(reg) & mask)
                 ;
 }
 
 static inline void cache_sync(void)
 {
         void __iomem *base = l2x0_base;
-        writel(0, base + L2X0_CACHE_SYNC);
+        writel_relaxed(0, base + L2X0_CACHE_SYNC);
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
@@ -47,14 +47,14 @@ static inline void l2x0_clean_line(unsigned long addr)
 {
         void __iomem *base = l2x0_base;
         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
 }
 
 static inline void l2x0_inv_line(unsigned long addr)
 {
         void __iomem *base = l2x0_base;
         cache_wait(base + L2X0_INV_LINE_PA, 1);
-        writel(addr, base + L2X0_INV_LINE_PA);
+        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 
 #ifdef CONFIG_PL310_ERRATA_588369
@@ -75,9 +75,9 @@ static inline void l2x0_flush_line(unsigned long addr)
 
         /* Clean by PA followed by Invalidate by PA */
         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
         cache_wait(base + L2X0_INV_LINE_PA, 1);
-        writel(addr, base + L2X0_INV_LINE_PA);
+        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
 #else
 
@@ -90,7 +90,7 @@ static inline void l2x0_flush_line(unsigned long addr)
 {
         void __iomem *base = l2x0_base;
         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-        writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
+        writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
 }
 #endif
 
@@ -109,7 +109,7 @@ static inline void l2x0_inv_all(void)
 
         /* invalidate all ways */
         spin_lock_irqsave(&l2x0_lock, flags);
-        writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
         cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
         cache_sync();
         spin_unlock_irqrestore(&l2x0_lock, flags);
@@ -215,8 +215,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 
         l2x0_base = base;
 
-        cache_id = readl(l2x0_base + L2X0_CACHE_ID);
-        aux = readl(l2x0_base + L2X0_AUX_CTRL);
+        cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
         aux &= aux_mask;
         aux |= aux_val;
@@ -248,15 +248,15 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
          * If you are booting from non-secure mode
          * accessing the below registers will fault.
          */
-        if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
 
                 /* l2x0 controller is disabled */
-                writel(aux, l2x0_base + L2X0_AUX_CTRL);
+                writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
 
                 l2x0_inv_all();
 
                 /* enable L2X0 */
-                writel(1, l2x0_base + L2X0_CTRL);
+                writel_relaxed(1, l2x0_base + L2X0_CTRL);
         }
 
         outer_cache.inv_range = l2x0_inv_range;
diff --git a/arch/arm/mm/discontig.c b/arch/arm/mm/discontig.c
deleted file mode 100644
index c8c0c4b0f0a3..000000000000
--- a/arch/arm/mm/discontig.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * linux/arch/arm/mm/discontig.c
- *
- * Discontiguous memory support.
- *
- * Initial code: Copyright (C) 1999-2000 Nicolas Pitre
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/mmzone.h>
-#include <linux/bootmem.h>
-
-#if MAX_NUMNODES != 4 && MAX_NUMNODES != 16
-# error Fix Me Please
-#endif
-
-/*
- * Our node_data structure for discontiguous memory.
- */
-
-pg_data_t discontig_node_data[MAX_NUMNODES] = {
-  { .bdata = &bootmem_node_data[0] },
-  { .bdata = &bootmem_node_data[1] },
-  { .bdata = &bootmem_node_data[2] },
-  { .bdata = &bootmem_node_data[3] },
-#if MAX_NUMNODES == 16
-  { .bdata = &bootmem_node_data[4] },
-  { .bdata = &bootmem_node_data[5] },
-  { .bdata = &bootmem_node_data[6] },
-  { .bdata = &bootmem_node_data[7] },
-  { .bdata = &bootmem_node_data[8] },
-  { .bdata = &bootmem_node_data[9] },
-  { .bdata = &bootmem_node_data[10] },
-  { .bdata = &bootmem_node_data[11] },
-  { .bdata = &bootmem_node_data[12] },
-  { .bdata = &bootmem_node_data[13] },
-  { .bdata = &bootmem_node_data[14] },
-  { .bdata = &bootmem_node_data[15] },
-#endif
-};
-
-EXPORT_SYMBOL(discontig_node_data);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 9e7742f0a102..c704eed63c5d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -183,6 +183,8 @@ static void *
 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
 {
         struct arm_vmregion *c;
+        size_t align;
+        int bit;
 
         if (!consistent_pte[0]) {
                 printk(KERN_ERR "%s: not initialised\n", __func__);
@@ -191,9 +193,20 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
         }
 
         /*
+         * Align the virtual region allocation - maximum alignment is
+         * a section size, minimum is a page size.  This helps reduce
+         * fragmentation of the DMA space, and also prevents allocations
+         * smaller than a section from crossing a section boundary.
+         */
+        bit = fls(size - 1) + 1;
+        if (bit > SECTION_SHIFT)
+                bit = SECTION_SHIFT;
+        align = 1 << bit;
+
+        /*
          * Allocate a virtual address in the consistent mapping region.
          */
-        c = arm_vmregion_alloc(&consistent_head, size,
+        c = arm_vmregion_alloc(&consistent_head, align, size,
                             gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
         if (c) {
                 pte_t *pte;
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index cbfb2edcf7d1..23b0b03af5ea 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -413,7 +413,16 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
         pmd_k = pmd_offset(pgd_k, addr);
         pmd   = pmd_offset(pgd, addr);
 
-        if (pmd_none(*pmd_k))
+        /*
+         * On ARM one Linux PGD entry contains two hardware entries (see page
+         * tables layout in pgtable.h). We normally guarantee that we always
+         * fill both L1 entries. But create_mapping() doesn't follow the rule.
+         * It can create inidividual L1 entries, so here we have to call
+         * pmd_none() check for the entry really corresponded to address, not
+         * for the first of pair.
+         */
+        index = (addr >> SECTION_SHIFT) & 1;
+        if (pmd_none(pmd_k[index]))
                 goto bad_area;
 
         copy_pmd(pmd, pmd_k);
@@ -463,15 +472,10 @@ static struct fsr_info {
          * defines these to be "precise" aborts.
          */
         { do_bad,               SIGSEGV, 0,             "vector exception"                 },
-        { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
+        { do_bad,               SIGBUS,  BUS_ADRALN,    "alignment exception"              },
         { do_bad,               SIGKILL, 0,             "terminal exception"               },
-        { do_bad,               SIGILL,  BUS_ADRALN,    "alignment exception"              },
-/* Do we need runtime check ? */
-#if __LINUX_ARM_ARCH__ < 6
+        { do_bad,               SIGBUS,  BUS_ADRALN,    "alignment exception"              },
         { do_bad,               SIGBUS,  0,             "external abort on linefetch"      },
-#else
-        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "I-cache maintenance fault"        },
-#endif
         { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "section translation fault"        },
         { do_bad,               SIGBUS,  0,             "external abort on linefetch"      },
         { do_page_fault,        SIGSEGV, SEGV_MAPERR,   "page translation fault"           },
@@ -508,13 +512,15 @@ static struct fsr_info {
 
 void __init
 hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
-                int sig, const char *name)
+                int sig, int code, const char *name)
 {
-        if (nr >= 0 && nr < ARRAY_SIZE(fsr_info)) {
-                fsr_info[nr].fn   = fn;
-                fsr_info[nr].sig  = sig;
-                fsr_info[nr].name = name;
-        }
+        if (nr < 0 || nr >= ARRAY_SIZE(fsr_info))
+                BUG();
+
+        fsr_info[nr].fn   = fn;
+        fsr_info[nr].sig  = sig;
+        fsr_info[nr].code = code;
+        fsr_info[nr].name = name;
 }
 
 /*
@@ -594,3 +600,25 @@ do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
         arm_notify_die("", regs, &info, ifsr, 0);
 }
 
+static int __init exceptions_init(void)
+{
+        if (cpu_architecture() >= CPU_ARCH_ARMv6) {
+                hook_fault_code(4, do_translation_fault, SIGSEGV, SEGV_MAPERR,
+                                "I-cache maintenance fault");
+        }
+
+        if (cpu_architecture() >= CPU_ARCH_ARMv7) {
+                /*
+                 * TODO: Access flag faults introduced in ARMv6K.
+                 * Runtime check for 'K' extension is needed
+                 */
+                hook_fault_code(3, do_bad, SIGSEGV, SEGV_MAPERR,
+                                "section access flag fault");
+                hook_fault_code(6, do_bad, SIGSEGV, SEGV_MAPERR,
+                                "section access flag fault");
+        }
+
+        return 0;
+}
+
+arch_initcall(exceptions_init);
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 086816b205b8..6ab244062b4a 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -163,19 +163,22 @@ static DEFINE_PER_CPU(int, kmap_high_l1_vipt_depth);
 
 void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte)
 {
-        unsigned int idx, cpu = smp_processor_id();
-        int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
+        unsigned int idx, cpu;
+        int *depth;
         unsigned long vaddr, flags;
         pte_t pte, *ptep;
 
+        if (!in_interrupt())
+                preempt_disable();
+
+        cpu = smp_processor_id();
+        depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
+
         idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
         vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
         ptep = TOP_PTE(vaddr);
         pte = mk_pte(page, kmap_prot);
 
-        if (!in_interrupt())
-                preempt_disable();
-
         raw_local_irq_save(flags);
         (*depth)++;
         if (pte_val(*ptep) == pte_val(pte)) {
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f6a999465323..7185b00650fe 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -17,6 +17,7 @@
 #include <linux/initrd.h>
 #include <linux/highmem.h>
 #include <linux/gfp.h>
+#include <linux/memblock.h>
 
 #include <asm/mach-types.h>
 #include <asm/sections.h>
@@ -79,38 +80,37 @@ struct meminfo meminfo;
 void show_mem(void)
 {
         int free = 0, total = 0, reserved = 0;
-        int shared = 0, cached = 0, slab = 0, node, i;
+        int shared = 0, cached = 0, slab = 0, i;
         struct meminfo * mi = &meminfo;
 
         printk("Mem-info:\n");
         show_free_areas();
-        for_each_online_node(node) {
-                for_each_nodebank (i,mi,node) {
-                        struct membank *bank = &mi->bank[i];
-                        unsigned int pfn1, pfn2;
-                        struct page *page, *end;
-
-                        pfn1 = bank_pfn_start(bank);
-                        pfn2 = bank_pfn_end(bank);
-
-                        page = pfn_to_page(pfn1);
-                        end  = pfn_to_page(pfn2 - 1) + 1;
-
-                        do {
-                                total++;
-                                if (PageReserved(page))
-                                        reserved++;
-                                else if (PageSwapCache(page))
-                                        cached++;
-                                else if (PageSlab(page))
-                                        slab++;
-                                else if (!page_count(page))
-                                        free++;
-                                else
-                                        shared += page_count(page) - 1;
-                                page++;
-                        } while (page < end);
-                }
+
+        for_each_bank (i, mi) {
+                struct membank *bank = &mi->bank[i];
+                unsigned int pfn1, pfn2;
+                struct page *page, *end;
+
+                pfn1 = bank_pfn_start(bank);
+                pfn2 = bank_pfn_end(bank);
+
+                page = pfn_to_page(pfn1);
+                end  = pfn_to_page(pfn2 - 1) + 1;
+
+                do {
+                        total++;
+                        if (PageReserved(page))
+                                reserved++;
+                        else if (PageSwapCache(page))
+                                cached++;
+                        else if (PageSlab(page))
+                                slab++;
+                        else if (!page_count(page))
+                                free++;
+                        else
+                                shared += page_count(page) - 1;
+                        page++;
+                } while (page < end);
         }
 
         printk("%d pages of RAM\n", total);
@@ -121,7 +121,7 @@ void show_mem(void)
         printk("%d pages swap cached\n", cached);
 }
 
-static void __init find_node_limits(int node, struct meminfo *mi,
+static void __init find_limits(struct meminfo *mi,
         unsigned long *min, unsigned long *max_low, unsigned long *max_high)
 {
         int i;
@@ -129,7 +129,7 @@ static void __init find_node_limits(int node, struct meminfo *mi,
         *min = -1UL;
         *max_low = *max_high = 0;
 
-        for_each_nodebank(i, mi, node) {
+        for_each_bank (i, mi) {
                 struct membank *bank = &mi->bank[i];
                 unsigned long start, end;
 
@@ -147,155 +147,64 @@ static void __init find_node_limits(int node, struct meminfo *mi,
         }
 }
 
-/*
- * FIXME: We really want to avoid allocating the bootmap bitmap
- * over the top of the initrd.  Hopefully, this is located towards
- * the start of a bank, so if we allocate the bootmap bitmap at
- * the end, we won't clash.
- */
-static unsigned int __init
-find_bootmap_pfn(int node, struct meminfo *mi, unsigned int bootmap_pages)
-{
-        unsigned int start_pfn, i, bootmap_pfn;
-
-        start_pfn   = PAGE_ALIGN(__pa(_end)) >> PAGE_SHIFT;
-        bootmap_pfn = 0;
-
-        for_each_nodebank(i, mi, node) {
-                struct membank *bank = &mi->bank[i];
-                unsigned int start, end;
-
-                start = bank_pfn_start(bank);
-                end   = bank_pfn_end(bank);
-
-                if (end < start_pfn)
-                        continue;
-
-                if (start < start_pfn)
-                        start = start_pfn;
-
-                if (end <= start)
-                        continue;
-
-                if (end - start >= bootmap_pages) {
-                        bootmap_pfn = start;
-                        break;
-                }
-        }
-
-        if (bootmap_pfn == 0)
-                BUG();
-
-        return bootmap_pfn;
-}
-
-static int __init check_initrd(struct meminfo *mi)
-{
-        int initrd_node = -2;
-#ifdef CONFIG_BLK_DEV_INITRD
-        unsigned long end = phys_initrd_start + phys_initrd_size;
-
-        /*
-         * Make sure that the initrd is within a valid area of
-         * memory.
-         */
-        if (phys_initrd_size) {
-                unsigned int i;
-
-                initrd_node = -1;
-
-                for (i = 0; i < mi->nr_banks; i++) {
-                        struct membank *bank = &mi->bank[i];
-                        if (bank_phys_start(bank) <= phys_initrd_start &&
-                            end <= bank_phys_end(bank))
-                                initrd_node = bank->node;
-                }
-        }
-
-        if (initrd_node == -1) {
-                printk(KERN_ERR "INITRD: 0x%08lx+0x%08lx extends beyond "
-                       "physical memory - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
-                phys_initrd_start = phys_initrd_size = 0;
-        }
-#endif
-
-        return initrd_node;
-}
-
-static void __init bootmem_init_node(int node, struct meminfo *mi,
+static void __init arm_bootmem_init(struct meminfo *mi,
         unsigned long start_pfn, unsigned long end_pfn)
 {
-        unsigned long boot_pfn;
         unsigned int boot_pages;
+        phys_addr_t bitmap;
         pg_data_t *pgdat;
         int i;
 
         /*
-         * Allocate the bootmem bitmap page.
+         * Allocate the bootmem bitmap page.  This must be in a region
+         * of memory which has already been mapped.
          */
         boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
-        boot_pfn = find_bootmap_pfn(node, mi, boot_pages);
+        bitmap = memblock_alloc_base(boot_pages << PAGE_SHIFT, L1_CACHE_BYTES,
+                                __pfn_to_phys(end_pfn));
 
         /*
-         * Initialise the bootmem allocator for this node, handing the
+         * Initialise the bootmem allocator, handing the
          * memory banks over to bootmem.
          */
-        node_set_online(node);
-        pgdat = NODE_DATA(node);
-        init_bootmem_node(pgdat, boot_pfn, start_pfn, end_pfn);
+        node_set_online(0);
+        pgdat = NODE_DATA(0);
+        init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn);
 
-        for_each_nodebank(i, mi, node) {
+        for_each_bank(i, mi) {
                 struct membank *bank = &mi->bank[i];
                 if (!bank->highmem)
-                        free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
+                        free_bootmem(bank_phys_start(bank), bank_phys_size(bank));
         }
 
         /*
-         * Reserve the bootmem bitmap for this node.
+         * Reserve the memblock reserved regions in bootmem.
          */
-        reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
-                             boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
-}
-
-static void __init bootmem_reserve_initrd(int node)
-{
-#ifdef CONFIG_BLK_DEV_INITRD
-        pg_data_t *pgdat = NODE_DATA(node);
-        int res;
-
-        res = reserve_bootmem_node(pgdat, phys_initrd_start,
-                             phys_initrd_size, BOOTMEM_EXCLUSIVE);
-
-        if (res == 0) {
-                initrd_start = __phys_to_virt(phys_initrd_start);
-                initrd_end = initrd_start + phys_initrd_size;
-        } else {
-                printk(KERN_ERR
-                        "INITRD: 0x%08lx+0x%08lx overlaps in-use "
-                        "memory region - disabling initrd\n",
-                        phys_initrd_start, phys_initrd_size);
+        for (i = 0; i < memblock.reserved.cnt; i++) {
+                phys_addr_t start = memblock_start_pfn(&memblock.reserved, i);
+                if (start >= start_pfn &&
+                    memblock_end_pfn(&memblock.reserved, i) <= end_pfn)
+                        reserve_bootmem_node(pgdat, __pfn_to_phys(start),
+                                memblock_size_bytes(&memblock.reserved, i),
+                                BOOTMEM_DEFAULT);
         }
-#endif
 }
 
-static void __init bootmem_free_node(int node, struct meminfo *mi)
+static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min,
+        unsigned long max_low, unsigned long max_high)
 {
         unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
-        unsigned long min, max_low, max_high;
         int i;
 
-        find_node_limits(node, mi, &min, &max_low, &max_high);
-
         /*
-         * initialise the zones within this node.
+         * initialise the zones.
          */
         memset(zone_size, 0, sizeof(zone_size));
 
         /*
-         * The size of this node has already been determined.  If we need
-         * to do anything fancy with the allocation of this memory to the
-         * zones, now is the time to do it.
+         * The memory size has already been determined.  If we need
+         * to do anything fancy with the allocation of this memory
+         * to the zones, now is the time to do it.
          */
         zone_size[0] = max_low - min;
 #ifdef CONFIG_HIGHMEM
@@ -303,11 +212,11 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
 #endif
 
         /*
-         * For each bank in this node, calculate the size of the holes.
-         *  holes = node_size - sum(bank_sizes_in_node)
+         * Calculate the size of the holes.
+         *  holes = node_size - sum(bank_sizes)
          */
         memcpy(zhole_size, zone_size, sizeof(zhole_size));
-        for_each_nodebank(i, mi, node) {
+        for_each_bank(i, mi) {
                 int idx = 0;
 #ifdef CONFIG_HIGHMEM
                 if (mi->bank[i].highmem)
@@ -320,24 +229,23 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
          * Adjust the sizes according to any special requirements for
          * this machine type.
          */
-        arch_adjust_zones(node, zone_size, zhole_size);
+        arch_adjust_zones(zone_size, zhole_size);
 
-        free_area_init_node(node, zone_size, min, zhole_size);
+        free_area_init_node(0, zone_size, min, zhole_size);
 }
 
 #ifndef CONFIG_SPARSEMEM
 int pfn_valid(unsigned long pfn)
 {
-        struct meminfo *mi = &meminfo;
-        unsigned int left = 0, right = mi->nr_banks;
+        struct memblock_region *mem = &memblock.memory;
+        unsigned int left = 0, right = mem->cnt;
 
         do {
                 unsigned int mid = (right + left) / 2;
-                struct membank *bank = &mi->bank[mid];
 
-                if (pfn < bank_pfn_start(bank))
+                if (pfn < memblock_start_pfn(mem, mid))
                         right = mid;
-                else if (pfn >= bank_pfn_end(bank))
+                else if (pfn >= memblock_end_pfn(mem, mid))
                         left = mid + 1;
                 else
                         return 1;
@@ -346,73 +254,69 @@ int pfn_valid(unsigned long pfn)
 }
 EXPORT_SYMBOL(pfn_valid);
 
-static void arm_memory_present(struct meminfo *mi, int node)
+static void arm_memory_present(void)
 {
 }
 #else
-static void arm_memory_present(struct meminfo *mi, int node)
+static void arm_memory_present(void)
 {
         int i;
-        for_each_nodebank(i, mi, node) {
-                struct membank *bank = &mi->bank[i];
-                memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
-        }
+        for (i = 0; i < memblock.memory.cnt; i++)
+                memory_present(0, memblock_start_pfn(&memblock.memory, i),
+                                  memblock_end_pfn(&memblock.memory, i));
 }
 #endif
 
-void __init bootmem_init(void)
+void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 {
-        struct meminfo *mi = &meminfo;
-        unsigned long min, max_low, max_high;
-        int node, initrd_node;
+        int i;
 
-        /*
-         * Locate which node contains the ramdisk image, if any.
-         */
-        initrd_node = check_initrd(mi);
+        memblock_init();
+        for (i = 0; i < mi->nr_banks; i++)
+                memblock_add(mi->bank[i].start, mi->bank[i].size);
 
-        max_low = max_high = 0;
+        /* Register the kernel text, kernel data and initrd with memblock. */
+#ifdef CONFIG_XIP_KERNEL
+        memblock_reserve(__pa(_data), _end - _data);
+#else
+        memblock_reserve(__pa(_stext), _end - _stext);
+#endif
+#ifdef CONFIG_BLK_DEV_INITRD
+        if (phys_initrd_size) {
+                memblock_reserve(phys_initrd_start, phys_initrd_size);
 
-        /*
-         * Run through each node initialising the bootmem allocator.
-         */
-        for_each_node(node) {
-                unsigned long node_low, node_high;
+                /* Now convert initrd to virtual addresses */
+                initrd_start = __phys_to_virt(phys_initrd_start);
+                initrd_end = initrd_start + phys_initrd_size;
+        }
+#endif
 
-                find_node_limits(node, mi, &min, &node_low, &node_high);
+        arm_mm_memblock_reserve();
 
-                if (node_low > max_low)
-                        max_low = node_low;
-                if (node_high > max_high)
-                        max_high = node_high;
+        /* reserve any platform specific memblock areas */
+        if (mdesc->reserve)
+                mdesc->reserve();
 
-                /*
-                 * If there is no memory in this node, ignore it.
-                 * (We can't have nodes which have no lowmem)
-                 */
-                if (node_low == 0)
-                        continue;
+        memblock_analyze();
+        memblock_dump_all();
+}
 
-                bootmem_init_node(node, mi, min, node_low);
+void __init bootmem_init(void)
+{
+        struct meminfo *mi = &meminfo;
+        unsigned long min, max_low, max_high;
 
-                /*
-                 * Reserve any special node zero regions.
-                 */
-                if (node == 0)
-                        reserve_node_zero(NODE_DATA(node));
+        max_low = max_high = 0;
 
-                /*
-                 * If the initrd is in this node, reserve its memory.
-                 */
-                if (node == initrd_node)
-                        bootmem_reserve_initrd(node);
+        find_limits(mi, &min, &max_low, &max_high);
 
-                /*
-                 * Sparsemem tries to allocate bootmem in memory_present(),
-                 * so must be done after the fixed reservations
-                 */
-                arm_memory_present(mi, node);
-        }
+        arm_bootmem_init(mi, min, max_low);
+
+        /*
+         * Sparsemem tries to allocate bootmem in memory_present(),
+         * so must be done after the fixed reservations
+         */
+        arm_memory_present();
 
         /*
          * sparse_init() needs the bootmem allocator up and running.
@@ -420,12 +324,11 @@ void __init bootmem_init(void)
         sparse_init();
 
         /*
-         * Now free memory in each node - free_area_init_node needs
+         * Now free the memory - free_area_init_node needs
          * the sparse mem_map arrays initialized by sparse_init()
          * for memmap_init_zone(), otherwise all PFNs are invalid.
          */
-        for_each_node(node)
-                bootmem_free_node(node, mi);
+        arm_bootmem_free(mi, min, max_low, max_high);
 
         high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
 
@@ -460,7 +363,7 @@ static inline int free_area(unsigned long pfn, unsigned long end, char *s)
 }
 
 static inline void
-free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
+free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
         struct page *start_pg, *end_pg;
         unsigned long pg, pgend;
@@ -483,40 +386,39 @@ free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
          * free the section of the memmap array.
          */
         if (pg < pgend)
-                free_bootmem_node(NODE_DATA(node), pg, pgend - pg);
+                free_bootmem(pg, pgend - pg);
 }
 
 /*
  * The mem_map array can get very big.  Free the unused area of the memory map.
  */
-static void __init free_unused_memmap_node(int node, struct meminfo *mi)
+static void __init free_unused_memmap(struct meminfo *mi)
 {
         unsigned long bank_start, prev_bank_end = 0;
         unsigned int i;
 
         /*
-         * [FIXME] This relies on each bank being in address order.  This
-         * may not be the case, especially if the user has provided the
-         * information on the command line.
+         * This relies on each bank being in address order.
+         * The banks are sorted previously in bootmem_init().
          */
-        for_each_nodebank(i, mi, node) {
+        for_each_bank(i, mi) {
                 struct membank *bank = &mi->bank[i];
 
                 bank_start = bank_pfn_start(bank);
-                if (bank_start < prev_bank_end) {
-                        printk(KERN_ERR "MEM: unordered memory banks.  "
-                                "Not freeing memmap.\n");
-                        break;
-                }
 
                 /*
                  * If we had a previous bank, and there is a space
                  * between the current bank and the previous, free it.
                  */
-                if (prev_bank_end && prev_bank_end != bank_start)
-                        free_memmap(node, prev_bank_end, bank_start);
+                if (prev_bank_end && prev_bank_end < bank_start)
+                        free_memmap(prev_bank_end, bank_start);
 
-                prev_bank_end = bank_pfn_end(bank);
+                /*
+                 * Align up here since the VM subsystem insists that the
+                 * memmap entries are valid from the bank end aligned to
+                 * MAX_ORDER_NR_PAGES.
+                 */
+                prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
         }
 }
 
@@ -528,21 +430,19 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
 void __init mem_init(void)
 {
         unsigned long reserved_pages, free_pages;
-        int i, node;
+        int i;
+#ifdef CONFIG_HAVE_TCM
+        /* These pointers are filled in on TCM detection */
+        extern u32 dtcm_end;
+        extern u32 itcm_end;
+#endif
 
-#ifndef CONFIG_DISCONTIGMEM
         max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
-#endif
 
         /* this will put all unused low memory onto the freelists */
-        for_each_online_node(node) {
-                pg_data_t *pgdat = NODE_DATA(node);
+        free_unused_memmap(&meminfo);
 
-                free_unused_memmap_node(node, &meminfo);
-
-                if (pgdat->node_spanned_pages != 0)
-                        totalram_pages += free_all_bootmem_node(pgdat);
-        }
+        totalram_pages += free_all_bootmem();
 
 #ifdef CONFIG_SA1111
         /* now that our DMA memory is actually so designated, we can free it */
@@ -552,39 +452,35 @@ void __init mem_init(void)
 
 #ifdef CONFIG_HIGHMEM
         /* set highmem page free */
-        for_each_online_node(node) {
-                for_each_nodebank (i, &meminfo, node) {
-                        unsigned long start = bank_pfn_start(&meminfo.bank[i]);
-                        unsigned long end = bank_pfn_end(&meminfo.bank[i]);
-                        if (start >= max_low_pfn + PHYS_PFN_OFFSET)
-                                totalhigh_pages += free_area(start, end, NULL);
-                }
+        for_each_bank (i, &meminfo) {
+                unsigned long start = bank_pfn_start(&meminfo.bank[i]);
+                unsigned long end = bank_pfn_end(&meminfo.bank[i]);
+                if (start >= max_low_pfn + PHYS_PFN_OFFSET)
+                        totalhigh_pages += free_area(start, end, NULL);
         }
         totalram_pages += totalhigh_pages;
 #endif
 
         reserved_pages = free_pages = 0;
 
-        for_each_online_node(node) {
-                for_each_nodebank(i, &meminfo, node) {
-                        struct membank *bank = &meminfo.bank[i];
-                        unsigned int pfn1, pfn2;
-                        struct page *page, *end;
-
-                        pfn1 = bank_pfn_start(bank);
-                        pfn2 = bank_pfn_end(bank);
-
-                        page = pfn_to_page(pfn1);
-                        end  = pfn_to_page(pfn2 - 1) + 1;
-
-                        do {
-                                if (PageReserved(page))
-                                        reserved_pages++;
-                                else if (!page_count(page))
-                                        free_pages++;
-                                page++;
-                        } while (page < end);
-                }
+        for_each_bank(i, &meminfo) {
+                struct membank *bank = &meminfo.bank[i];
+                unsigned int pfn1, pfn2;
+                struct page *page, *end;
+
+                pfn1 = bank_pfn_start(bank);
+                pfn2 = bank_pfn_end(bank);
+
+                page = pfn_to_page(pfn1);
+                end  = pfn_to_page(pfn2 - 1) + 1;
+
+                do {
+                        if (PageReserved(page))
+                                reserved_pages++;
+                        else if (!page_count(page))
+                                free_pages++;
+                        page++;
+                } while (page < end);
         }
 
         /*
@@ -611,6 +507,10 @@ void __init mem_init(void)
 
         printk(KERN_NOTICE "Virtual kernel memory layout:\n"
                         "    vector  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#ifdef CONFIG_HAVE_TCM
+                        "    DTCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+                        "    ITCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#endif
                         "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #ifdef CONFIG_MMU
                         "    DMA     : 0x%08lx - 0x%08lx   (%4ld MB)\n"
@@ -627,6 +527,10 @@ void __init mem_init(void)
 
                         MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
                                 (PAGE_SIZE)),
+#ifdef CONFIG_HAVE_TCM
+                        MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
+                        MLK(ITCM_OFFSET, (unsigned long) itcm_end),
+#endif
                         MLK(FIXADDR_START, FIXADDR_TOP),
 #ifdef CONFIG_MMU
                         MLM(CONSISTENT_BASE, CONSISTENT_END),
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 28c8b950ef04..ab506272b2d3 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -42,78 +42,11 @@
  */
 #define VM_ARM_SECTION_MAPPING  0x80000000
 
-static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
-                          unsigned long phys_addr, const struct mem_type *type)
-{
-        pgprot_t prot = __pgprot(type->prot_pte);
-        pte_t *pte;
-
-        pte = pte_alloc_kernel(pmd, addr);
-        if (!pte)
-                return -ENOMEM;
-
-        do {
-                if (!pte_none(*pte))
-                        goto bad;
-
-                set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
-                phys_addr += PAGE_SIZE;
-        } while (pte++, addr += PAGE_SIZE, addr != end);
-        return 0;
-
- bad:
-        printk(KERN_CRIT "remap_area_pte: page already exists\n");
-        BUG();
-}
-
-static inline int remap_area_pmd(pgd_t *pgd, unsigned long addr,
-                                 unsigned long end, unsigned long phys_addr,
-                                 const struct mem_type *type)
-{
-        unsigned long next;
-        pmd_t *pmd;
-        int ret = 0;
-
-        pmd = pmd_alloc(&init_mm, pgd, addr);
-        if (!pmd)
-                return -ENOMEM;
-
-        do {
-                next = pmd_addr_end(addr, end);
-                ret = remap_area_pte(pmd, addr, next, phys_addr, type);
-                if (ret)
-                        return ret;
-                phys_addr += next - addr;
-        } while (pmd++, addr = next, addr != end);
-        return ret;
-}
-
-static int remap_area_pages(unsigned long start, unsigned long pfn,
-                            size_t size, const struct mem_type *type)
-{
-        unsigned long addr = start;
-        unsigned long next, end = start + size;
-        unsigned long phys_addr = __pfn_to_phys(pfn);
-        pgd_t *pgd;
-        int err = 0;
-
-        BUG_ON(addr >= end);
-        pgd = pgd_offset_k(addr);
-        do {
-                next = pgd_addr_end(addr, end);
-                err = remap_area_pmd(pgd, addr, next, phys_addr, type);
-                if (err)
-                        break;
-                phys_addr += next - addr;
-        } while (pgd++, addr = next, addr != end);
-
-        return err;
-}
-
 int ioremap_page(unsigned long virt, unsigned long phys,
                  const struct mem_type *mtype)
 {
-        return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype);
+        return ioremap_page_range(virt, virt + PAGE_SIZE, phys,
+                                  __pgprot(mtype->prot_pte));
 }
 EXPORT_SYMBOL(ioremap_page);
 
@@ -268,6 +201,12 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
                 return NULL;
 
+        /*
+         * Don't allow RAM to be mapped - this causes problems with ARMv6+
+         */
+        if (WARN_ON(pfn_valid(pfn)))
+                return NULL;
+
         type = get_mem_type(mtype);
         if (!type)
                 return NULL;
@@ -294,7 +233,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
                 err = remap_area_sections(addr, pfn, size, type);
         } else
 #endif
-                err = remap_area_pages(addr, pfn, size, type);
+                err = ioremap_page_range(addr, addr + size, __pfn_to_phys(pfn),
+                                         __pgprot(type->prot_pte));
 
         if (err) {
                 vunmap((void *)addr);
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 815d08eecbb0..6630620380a4 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -28,7 +28,5 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
 
 #endif
 
-struct pglist_data;
-
 void __init bootmem_init(void);
-void reserve_node_zero(struct pglist_data *pgdat);
+void arm_mm_memblock_reserve(void);
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index f5abc51c5a07..4f5b39687df5 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -7,6 +7,7 @@
 #include <linux/shm.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/random.h>
 #include <asm/cputype.h>
 #include <asm/system.h>
 
@@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
                 start_addr = addr = TASK_UNMAPPED_BASE;
                 mm->cached_hole_size = 0;
         }
+        /* 8 bits of randomness in 20 address space bits */
+        if (current->flags & PF_RANDOMIZE)
+                addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
 
 full_search:
         if (do_align)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 285894171186..6e1c4f6a2b3f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -11,13 +11,12 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/init.h>
-#include <linux/bootmem.h>
 #include <linux/mman.h>
 #include <linux/nodemask.h>
+#include <linux/memblock.h>
 #include <linux/sort.h>
 
 #include <asm/cputype.h>
-#include <asm/mach-types.h>
 #include <asm/sections.h>
 #include <asm/cachetype.h>
 #include <asm/setup.h>
@@ -258,6 +257,19 @@ static struct mem_type mem_types[] = {
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
+        [MT_MEMORY_DTCM] = {
+                .prot_pte       = L_PTE_PRESENT | L_PTE_YOUNG |
+                                  L_PTE_DIRTY | L_PTE_WRITE,
+                .prot_l1        = PMD_TYPE_TABLE,
+                .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
+                .domain         = DOMAIN_KERNEL,
+        },
+        [MT_MEMORY_ITCM] = {
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_USER | L_PTE_EXEC,
+                .prot_l1   = PMD_TYPE_TABLE,
+                .domain    = DOMAIN_IO,
+        },
 };
 
 const struct mem_type *get_mem_type(unsigned int type)
@@ -488,18 +500,28 @@ static void __init build_mem_type_table(void)
 
 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 
-static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
-                                  unsigned long end, unsigned long pfn,
-                                  const struct mem_type *type)
+static void __init *early_alloc(unsigned long sz)
 {
-        pte_t *pte;
+        void *ptr = __va(memblock_alloc(sz, sz));
+        memset(ptr, 0, sz);
+        return ptr;
+}
 
+static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
+{
         if (pmd_none(*pmd)) {
-                pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
-                __pmd_populate(pmd, __pa(pte) | type->prot_l1);
+                pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
+                __pmd_populate(pmd, __pa(pte) | prot);
         }
+        BUG_ON(pmd_bad(*pmd));
+        return pte_offset_kernel(pmd, addr);
+}
 
-        pte = pte_offset_kernel(pmd, addr);
+static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
+                                  unsigned long end, unsigned long pfn,
+                                  const struct mem_type *type)
+{
+        pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
         do {
                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
                 pfn++;
@@ -668,7 +690,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
                 create_mapping(io_desc + i);
 }
 
-static unsigned long __initdata vmalloc_reserve = SZ_128M;
+static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
 
 /*
  * vmalloc=size forces the vmalloc area to be exactly 'size'
@@ -677,7 +699,7 @@ static unsigned long __initdata vmalloc_reserve = SZ_128M;
  */
 static int __init early_vmalloc(char *arg)
 {
-        vmalloc_reserve = memparse(arg, NULL);
+        unsigned long vmalloc_reserve = memparse(arg, NULL);
 
         if (vmalloc_reserve < SZ_16M) {
                 vmalloc_reserve = SZ_16M;
@@ -692,22 +714,26 @@ static int __init early_vmalloc(char *arg)
                         "vmalloc area is too big, limiting to %luMB\n",
                         vmalloc_reserve >> 20);
         }
+
+        vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
         return 0;
 }
 early_param("vmalloc", early_vmalloc);
 
-#define VMALLOC_MIN     (void *)(VMALLOC_END - vmalloc_reserve)
+phys_addr_t lowmem_end_addr;
 
 static void __init sanity_check_meminfo(void)
 {
         int i, j, highmem = 0;
 
+        lowmem_end_addr = __pa(vmalloc_min - 1) + 1;
+
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
                 *bank = meminfo.bank[i];
 
 #ifdef CONFIG_HIGHMEM
-                if (__va(bank->start) > VMALLOC_MIN ||
+                if (__va(bank->start) > vmalloc_min ||
                     __va(bank->start) < (void *)PAGE_OFFSET)
                         highmem = 1;
 
@@ -717,8 +743,8 @@ static void __init sanity_check_meminfo(void)
                  * Split those memory banks which are partially overlapping
                  * the vmalloc area greatly simplifying things later.
                  */
-                if (__va(bank->start) < VMALLOC_MIN &&
-                    bank->size > VMALLOC_MIN - __va(bank->start)) {
+                if (__va(bank->start) < vmalloc_min &&
+                    bank->size > vmalloc_min - __va(bank->start)) {
                         if (meminfo.nr_banks >= NR_BANKS) {
                                 printk(KERN_CRIT "NR_BANKS too low, "
                                                  "ignoring high memory\n");
@@ -727,12 +753,12 @@ static void __init sanity_check_meminfo(void)
                                         (meminfo.nr_banks - i) * sizeof(*bank));
                                 meminfo.nr_banks++;
                                 i++;
-                                bank[1].size -= VMALLOC_MIN - __va(bank->start);
-                                bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
+                                bank[1].size -= vmalloc_min - __va(bank->start);
+                                bank[1].start = __pa(vmalloc_min - 1) + 1;
                                 bank[1].highmem = highmem = 1;
                                 j++;
                         }
-                        bank->size = VMALLOC_MIN - __va(bank->start);
+                        bank->size = vmalloc_min - __va(bank->start);
                 }
 #else
                 bank->highmem = highmem;
@@ -741,7 +767,7 @@ static void __init sanity_check_meminfo(void)
                  * Check whether this memory bank would entirely overlap
                  * the vmalloc area.
                  */
-                if (__va(bank->start) >= VMALLOC_MIN ||
+                if (__va(bank->start) >= vmalloc_min ||
                     __va(bank->start) < (void *)PAGE_OFFSET) {
                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
                                "(vmalloc region overlap).\n",
@@ -753,9 +779,9 @@ static void __init sanity_check_meminfo(void)
                  * Check whether this memory bank would partially overlap
                  * the vmalloc area.
                  */
-                if (__va(bank->start + bank->size) > VMALLOC_MIN ||
+                if (__va(bank->start + bank->size) > vmalloc_min ||
                     __va(bank->start + bank->size) < __va(bank->start)) {
-                        unsigned long newsize = VMALLOC_MIN - __va(bank->start);
+                        unsigned long newsize = vmalloc_min - __va(bank->start);
                         printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
                                "to -%.8lx (vmalloc region overlap).\n",
                                bank->start, bank->start + bank->size - 1,
@@ -827,101 +853,23 @@ static inline void prepare_page_table(void)
 }
 
 /*
- * Reserve the various regions of node 0
+ * Reserve the special regions of memory
  */
-void __init reserve_node_zero(pg_data_t *pgdat)
+void __init arm_mm_memblock_reserve(void)
 {
-        unsigned long res_size = 0;
-
-        /*
-         * Register the kernel text and data with bootmem.
-         * Note that this can only be in node 0.
-         */
-#ifdef CONFIG_XIP_KERNEL
-        reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
-                        BOOTMEM_DEFAULT);
-#else
-        reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
-                        BOOTMEM_DEFAULT);
-#endif
-
         /*
          * Reserve the page tables.  These are already in use,
          * and can only be in node 0.
          */
-        reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
-                             PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
-
-        /*
-         * Hmm... This should go elsewhere, but we really really need to
-         * stop things allocating the low memory; ideally we need a better
-         * implementation of GFP_DMA which does not assume that DMA-able
-         * memory starts at zero.
-         */
-        if (machine_is_integrator() || machine_is_cintegrator())
-                res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
-
-        /*
-         * These should likewise go elsewhere.  They pre-reserve the
-         * screen memory region at the start of main system memory.
-         */
-        if (machine_is_edb7211())
-                res_size = 0x00020000;
-        if (machine_is_p720t())
-                res_size = 0x00014000;
-
-        /* H1940, RX3715 and RX1950 need to reserve this for suspend */
-
-        if (machine_is_h1940() || machine_is_rx3715()
-                || machine_is_rx1950()) {
-                reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
-                                BOOTMEM_DEFAULT);
-                reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
-                                BOOTMEM_DEFAULT);
-        }
-
-        if (machine_is_palmld() || machine_is_palmtx()) {
-                reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
-                                BOOTMEM_EXCLUSIVE);
-                reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
-                                BOOTMEM_EXCLUSIVE);
-        }
-
-        if (machine_is_treo680() || machine_is_centro()) {
-                reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
-                                BOOTMEM_EXCLUSIVE);
-                reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
-                                BOOTMEM_EXCLUSIVE);
-        }
-
-        if (machine_is_palmt5())
-                reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
-                                BOOTMEM_EXCLUSIVE);
-
-        /*
-         * U300 - This platform family can share physical memory
-         * between two ARM cpus, one running Linux and the other
-         * running another OS.
-         */
-        if (machine_is_u300()) {
-#ifdef CONFIG_MACH_U300_SINGLE_RAM
-#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) &&    \
-        CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
-                res_size = 0x00100000;
-#endif
-#endif
-        }
+        memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
 
 #ifdef CONFIG_SA1111
         /*
          * Because of the SA1111 DMA bug, we want to preserve our
          * precious DMA-able memory...
          */
-        res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
+        memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 #endif
-        if (res_size)
-                reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
-                                BOOTMEM_DEFAULT);
 }
 
 /*
@@ -940,7 +888,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
         /*
          * Allocate the vector page early.
          */
-        vectors = alloc_bootmem_low_pages(PAGE_SIZE);
+        vectors = early_alloc(PAGE_SIZE);
 
         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
                 pmd_clear(pmd_off_k(addr));
@@ -1011,11 +959,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 static void __init kmap_init(void)
 {
 #ifdef CONFIG_HIGHMEM
-        pmd_t *pmd = pmd_off_k(PKMAP_BASE);
-        pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
-        BUG_ON(!pmd_none(*pmd) || !pte);
-        __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE);
-        pkmap_page_table = pte + PTRS_PER_PTE;
+        pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
+                PKMAP_BASE, _PAGE_KERNEL_TABLE);
 #endif
 }
 
@@ -1066,17 +1011,16 @@ void __init paging_init(struct machine_desc *mdesc)
         sanity_check_meminfo();
         prepare_page_table();
         map_lowmem();
-        bootmem_init();
         devicemaps_init(mdesc);
         kmap_init();
 
         top_pmd = pmd_off_k(0xffff0000);
 
-        /*
-         * allocate the zero page.  Note that this always succeeds and
-         * returns a zeroed result.
-         */
-        zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
+        /* allocate the zero page. */
+        zero_page = early_alloc(PAGE_SIZE);
+
+        bootmem_init();
+
         empty_zero_page = virt_to_page(zero_page);
         __flush_dcache_page(NULL, empty_zero_page);
 }
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 33b327379f07..687d02319a41 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -6,8 +6,8 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/pagemap.h>
-#include <linux/bootmem.h>
 #include <linux/io.h>
+#include <linux/memblock.h>
 
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
@@ -17,30 +17,14 @@
 
 #include "mm.h"
 
-/*
- * Reserve the various regions of node 0
- */
-void __init reserve_node_zero(pg_data_t *pgdat)
+void __init arm_mm_memblock_reserve(void)
 {
         /*
-         * Register the kernel text and data with bootmem.
-         * Note that this can only be in node 0.
-         */
-#ifdef CONFIG_XIP_KERNEL
-        reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
-                        BOOTMEM_DEFAULT);
-#else
-        reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
-                        BOOTMEM_DEFAULT);
-#endif
-
-        /*
          * Register the exception vector page.
          * some architectures which the DRAM is the exception vector to trap,
          * alloc_page breaks with error, although it is not NULL, but "0."
          */
-        reserve_bootmem_node(pgdat, CONFIG_VECTORS_BASE, PAGE_SIZE,
-                        BOOTMEM_DEFAULT);
+        memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
 }
 
 /*
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 72507c630ceb..203a4e944d9e 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init)
  * cpu_arm1020_proc_fin()
  */
 ENTRY(cpu_arm1020_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm1020_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm1020_reset(loc)
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index d27829805609..1a511e765909 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init)
  * cpu_arm1020e_proc_fin()
  */
 ENTRY(cpu_arm1020e_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm1020e_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm1020e_reset(loc)
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index ce13e4a827de..1ffa4eb9c34f 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init)
  * cpu_arm1022_proc_fin()
  */
 ENTRY(cpu_arm1022_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm1022_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm1022_reset(loc)
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 636672a29c6d..5697c34b95b0 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init)
  * cpu_arm1026_proc_fin()
  */
 ENTRY(cpu_arm1026_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm1026_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm1026_reset(loc)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 795dc615f43b..64e0b327c7c5 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init)
 
 ENTRY(cpu_arm6_proc_fin)
 ENTRY(cpu_arm7_proc_fin)
-                mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-                msr     cpsr_c, r0
                 mov     r0, #0x31                       @ ....S..DP...M
                 mcr     p15, 0, r0, c1, c0, 0           @ disable caches
                 mov     pc, lr
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0b62de244666..9d96824134fc 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init)
                 mov     pc, lr
 
 ENTRY(cpu_arm720_proc_fin)
-                stmfd   sp!, {lr}
-                mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-                msr     cpsr_c, ip
                 mrc     p15, 0, r0, c1, c0, 0
                 bic     r0, r0, #0x1000                 @ ...i............
                 bic     r0, r0, #0x000e                 @ ............wca.
                 mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-                mcr     p15, 0, r1, c7, c7, 0           @ invalidate cache
-                ldmfd   sp!, {pc}
+                mov     pc, lr
 
 /*
  * Function: arm720_proc_do_idle(void)
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 01860cdeb2ec..6c1a9ab059ae 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm)
  * cpu_arm740_proc_fin()
  */
 ENTRY(cpu_arm740_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
         mrc     p15, 0, r0, c1, c0, 0
         bic     r0, r0, #0x3f000000             @ bank/f/lock/s
         bic     r0, r0, #0x0000000c             @ w-buffer/cache
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        mcr     p15, 0, r0, c7, c0, 0           @ invalidate cache
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm740_reset(loc)
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 1201b9863829..6a850dbba22e 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm)
  * cpu_arm7tdmi_proc_fin()
  */
 ENTRY(cpu_arm7tdmi_proc_fin)
-                mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-                msr     cpsr_c, r0
                 mov     pc, lr
 
 /*
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 8be81992645d..86f80aa56216 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init)
  * cpu_arm920_proc_fin()
  */
 ENTRY(cpu_arm920_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
-        bl      arm920_flush_kern_cache_all
-#else
-        bl      v4wt_flush_kern_cache_all
-#endif
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm920_reset(loc)
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index c0ff8e4b1074..f76ce9b62883 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init)
  * cpu_arm922_proc_fin()
  */
 ENTRY(cpu_arm922_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
-        bl      arm922_flush_kern_cache_all
-#else
-        bl      v4wt_flush_kern_cache_all
-#endif
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm922_reset(loc)
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 3c6cffe400f6..657bd3f7c153 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init)
  * cpu_arm925_proc_fin()
  */
 ENTRY(cpu_arm925_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm925_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm925_reset(loc)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 75b707c9cce1..73f1f3c68910 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init)
  * cpu_arm926_proc_fin()
  */
 ENTRY(cpu_arm926_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm926_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm926_reset(loc)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 1af1657819eb..fffb061a45a5 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm)
  * cpu_arm940_proc_fin()
  */
 ENTRY(cpu_arm940_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm940_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x00001000             @ i-cache
         bic     r0, r0, #0x00000004             @ d-cache
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm940_reset(loc)
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1664b6aaff79..249a6053760a 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm)
  * cpu_arm946_proc_fin()
  */
 ENTRY(cpu_arm946_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      arm946_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x00001000             @ i-cache
         bic     r0, r0, #0x00000004             @ d-cache
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_arm946_reset(loc)
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 28545c29dbcd..db475667fac2 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm)
  * cpu_arm9tdmi_proc_fin()
  */
 ENTRY(cpu_arm9tdmi_proc_fin)
-                mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-                msr     cpsr_c, r0
                 mov     pc, lr
 
 /*
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 08f5ac237ad4..7803fdf70029 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init)
  * cpu_fa526_proc_fin()
  */
 ENTRY(cpu_fa526_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      fa_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
         nop
         nop
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_fa526_reset(loc)
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 53e632343849..b304d0104a4e 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init)
  * cpu_feroceon_proc_fin()
  */
 ENTRY(cpu_feroceon_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      feroceon_flush_kern_cache_all
-
 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
         !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
         mov     r0, #0
@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_feroceon_reset(loc)
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index caa31154e7db..5f6892fcc167 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init)
  * cpu_mohawk_proc_fin()
  */
 ENTRY(cpu_mohawk_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      mohawk_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1800                 @ ...iz...........
         bic     r0, r0, #0x0006                 @ .............ca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_mohawk_reset(loc)
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 7b706b389906..a201eb04b5e1 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
  * cpu_sa110_proc_fin()
  */
 ENTRY(cpu_sa110_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      v4wb_flush_kern_cache_all       @ clean caches
-1:      mov     r0, #0
+        mov     r0, #0
         mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_sa110_reset(loc)
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 5c47760c2064..7ddc4805bf97 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init)
  *  - Clean and turn off caches.
  */
 ENTRY(cpu_sa1100_proc_fin)
-        stmfd   sp!, {lr}
-        mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, ip
-        bl      v4wb_flush_kern_cache_all
         mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  * cpu_sa1100_reset(loc)
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7a5337ed7d68..22aac8515196 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init)
         mov     pc, lr
 
 ENTRY(cpu_v6_proc_fin)
-        stmfd   sp!, {lr}
-        cpsid   if                              @ disable interrupts
-        bl      v6_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x0006                 @ .............ca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 
 /*
  *      cpu_v6_reset(loc)
@@ -239,7 +236,8 @@ __v6_proc_info:
         b       __v6_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
+        /* See also feat_v6_fixup() for HWCAP_TLS */
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
         .long   cpu_v6_name
         .long   v6_processor_functions
         .long   v6wbi_tlb_fns
@@ -262,7 +260,7 @@ __pj4_v6_proc_info:
         b       __v6_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
         .long   cpu_pj4_name
         .long   v6_processor_functions
         .long   v6wbi_tlb_fns
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a3b7aa..6a8506d99ee9 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init)
 ENDPROC(cpu_v7_proc_init)
 
 ENTRY(cpu_v7_proc_fin)
-        stmfd   sp!, {lr}
-        cpsid   if                              @ disable interrupts
-        bl      v7_flush_kern_cache_all
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x0006                 @ .............ca.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldmfd   sp!, {pc}
+        mov     pc, lr
 ENDPROC(cpu_v7_proc_fin)
 
 /*
@@ -344,7 +341,7 @@ __v7_proc_info:
         b       __v7_setup
         .long   cpu_arch_name
         .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
         .long   cpu_v7_name
         .long   v7_processor_functions
         .long   v7wbi_tlb_fns
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e5797f1c1db7..361a51e49030 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init)
  * cpu_xsc3_proc_fin()
  */
 ENTRY(cpu_xsc3_proc_fin)
-        str     lr, [sp, #-4]!
-        mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
-        msr     cpsr_c, r0
-        bl      xsc3_flush_kern_cache_all       @ clean caches
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1800                 @ ...IZ...........
         bic     r0, r0, #0x0006                 @ .............CA.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldr     pc, [sp], #4
+        mov     pc, lr
 
 /*
  * cpu_xsc3_reset(loc)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 63037e2162f2..14075979bcba 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init)
  * cpu_xscale_proc_fin()
  */
 ENTRY(cpu_xscale_proc_fin)
-        str     lr, [sp, #-4]!
-        mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
-        msr     cpsr_c, r0
-        bl      xscale_flush_kern_cache_all     @ clean caches
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1800                 @ ...IZ...........
         bic     r0, r0, #0x0006                 @ .............CA.
         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-        ldr     pc, [sp], #4
+        mov     pc, lr
 
 /*
  * cpu_xscale_reset(loc)
diff --git a/arch/arm/mm/vmregion.c b/arch/arm/mm/vmregion.c
index 19e09bdb1b8a..935993e1b1ef 100644
--- a/arch/arm/mm/vmregion.c
+++ b/arch/arm/mm/vmregion.c
@@ -35,7 +35,8 @@
  */
 
 struct arm_vmregion *
-arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp)
+arm_vmregion_alloc(struct arm_vmregion_head *head, size_t align,
+                   size_t size, gfp_t gfp)
 {
         unsigned long addr = head->vm_start, end = head->vm_end - size;
         unsigned long flags;
@@ -58,7 +59,7 @@ arm_vmregion_alloc(struct arm_vmregion_head *head, size_t size, gfp_t gfp)
                         goto nospc;
                 if ((addr + size) <= c->vm_start)
                         goto found;
-                addr = c->vm_end;
+                addr = ALIGN(c->vm_end, align);
                 if (addr > end)
                         goto nospc;
         }
diff --git a/arch/arm/mm/vmregion.h b/arch/arm/mm/vmregion.h
index 6b2cdbdf3a85..15e9f044db9f 100644
--- a/arch/arm/mm/vmregion.h
+++ b/arch/arm/mm/vmregion.h
@@ -21,7 +21,7 @@ struct arm_vmregion {
         int                     vm_active;
 };
 
-struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, gfp_t);
+struct arm_vmregion *arm_vmregion_alloc(struct arm_vmregion_head *, size_t, size_t, gfp_t);
 struct arm_vmregion *arm_vmregion_find(struct arm_vmregion_head *, unsigned long);
 struct arm_vmregion *arm_vmregion_find_remove(struct arm_vmregion_head *, unsigned long);
 void arm_vmregion_free(struct arm_vmregion_head *, struct arm_vmregion *);
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index ce31f316ac75..43f2b158237c 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -359,7 +359,7 @@ static void __init iop3xx_atu_debug(void)
         DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
         DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
 
-        hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
+        hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
 }
 
 /* for platforms that might be host-bus-adapters */
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 6c8a02ad98e3..85d3e55ca4a9 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -29,6 +29,11 @@
 #include <mach/time.h>
 
 /*
+ * Minimum clocksource/clockevent timer range in seconds
+ */
+#define IOP_MIN_RANGE 4
+
+/*
  * IOP clocksource (free-running timer 1).
  */
 static cycle_t iop_clocksource_read(struct clocksource *unused)
@@ -44,27 +49,6 @@ static struct clocksource iop_clocksource = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find shift and mult values for hz. */
-        shift = 32;
-        do {
-                temp = (u64) NSEC_PER_SEC << shift;
-                do_div(temp, hz);
-                if ((temp >> 32) == 0)
-                        break;
-        } while (--shift != 0);
-
-        cs->shift = shift;
-        cs->mult = (u32) temp;
-
-        printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
-               cs->name, cs->shift, cs->mult);
-}
-
 /*
  * IOP sched_clock() implementation via its clocksource.
  */
@@ -130,27 +114,6 @@ static struct clock_event_device iop_clockevent = {
         .set_mode       = iop_set_mode,
 };
 
-static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find shift and mult values for hz. */
-        shift = 32;
-        do {
-                temp = (u64) hz << shift;
-                do_div(temp, NSEC_PER_SEC);
-                if ((temp >> 32) == 0)
-                        break;
-        } while (--shift != 0);
-
-        ce->shift = shift;
-        ce->mult = (u32) temp;
-
-        printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
-               ce->name, ce->shift, ce->mult);
-}
-
 static irqreturn_t
 iop_timer_interrupt(int irq, void *dev_id)
 {
@@ -190,7 +153,8 @@ void __init iop_init_time(unsigned long tick_rate)
          */
         write_tmr0(timer_ctl & ~IOP_TMR_EN);
         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
-        iop_clockevent_set_hz(&iop_clockevent, tick_rate);
+        clockevents_calc_mult_shift(&iop_clockevent,
+                                    tick_rate, IOP_MIN_RANGE);
         iop_clockevent.max_delta_ns =
                 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
         iop_clockevent.min_delta_ns =
@@ -207,6 +171,7 @@ void __init iop_init_time(unsigned long tick_rate)
         write_trr1(0xffffffff);
         write_tcr1(0xffffffff);
         write_tmr1(timer_ctl);
-        iop_clocksource_set_hz(&iop_clocksource, tick_rate);
+        clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
+                                    IOP_MIN_RANGE);
         clocksource_register(&iop_clocksource);
 }
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
new file mode 100644
index 000000000000..639c54a07992
--- /dev/null
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)    (n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)      (n + 0x8000)
+#define UARTB_BASE_ADDR(n)      (n + 0x10000)
+
+#define BOARD_IO_ADDR(n)        (n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG          0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG      0x08
+/* status, interrupt */
+#define INTR_STATUS_REG 0x10
+#define INTR_MASK_REG           0x38
+#define INTR_RESET_REG          0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG       0x40
+#define MAGIC_NUMBER2_REG       0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG       0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG       0x58
+/* module reset register*/
+#define MODULE_RESET_REG        0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG        0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES    16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET          (MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A       (MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B       (MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A      (MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B      (MXC_BOARD_IRQ_START + 4)
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+        {
+                .flags = IORESOURCE_MEM,
+        } , {
+                .start = EXPIO_INT_ENET,
+                .end = EXPIO_INT_ENET,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+        .name = "smsc911x",
+        .id = 0,
+        .dev = {
+                .platform_data = &smsc911x_config,
+        },
+        .num_resources = ARRAY_SIZE(smsc911x_resources),
+        .resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 imr_val;
+        u32 int_valid;
+        u32 expio_irq;
+
+        desc->chip->mask(irq);  /* irq = gpio irq number */
+
+        imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+        int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+        expio_irq = MXC_BOARD_IRQ_START;
+        for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+                struct irq_desc *d;
+                if ((int_valid & 1) == 0)
+                        continue;
+                d = irq_desc + expio_irq;
+                if (unlikely(!(d->handle_irq)))
+                        pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+                else
+                        d->handle_irq(expio_irq, d);
+        }
+
+        desc->chip->ack(irq);
+        desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+        u16 reg;
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+        reg = __raw_readw(brd_io + INTR_MASK_REG);
+        reg |= (1 << expio);
+        __raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+        __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+        __raw_writew(0, brd_io + INTR_RESET_REG);
+        expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+        u16 reg;
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+        reg = __raw_readw(brd_io + INTR_MASK_REG);
+        reg &= ~(1 << expio);
+        __raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+        .ack = expio_ack_irq,
+        .mask = expio_mask_irq,
+        .unmask = expio_unmask_irq,
+};
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+        int i;
+
+        brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+        if (brd_io == NULL)
+                return -ENOMEM;
+
+        if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+            (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+            (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+                pr_info("3-Stack Debug board not detected\n");
+                iounmap(brd_io);
+                brd_io = NULL;
+                return -ENODEV;
+        }
+
+        pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+                readw(brd_io + CPLD_CODE_VER_REG));
+
+        /*
+         * Configure INT line as GPIO input
+         */
+        gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+        gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+        /* disable the interrupt and clear the status */
+        __raw_writew(0, brd_io + INTR_MASK_REG);
+        __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+        __raw_writew(0, brd_io + INTR_RESET_REG);
+        __raw_writew(0x1F, brd_io + INTR_MASK_REG);
+        for (i = MXC_EXP_IO_BASE;
+             i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+                set_irq_chip(i, &expio_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+        set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+        /* Register Lan device on the debugboard */
+        smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+        smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+        platform_device_register(&smsc_lan9217_device);
+
+        return 0;
+}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f289bd..0527e65318f4 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -1,5 +1,7 @@
 if ARCH_MXC
 
+source "arch/arm/plat-mxc/devices/Kconfig"
+
 menu "Freescale MXC Implementations"
 
 choice
@@ -8,15 +10,12 @@ choice
 
 config ARCH_MX1
         bool "MX1-based"
-        select CPU_ARM920T
-        select IMX_HAVE_IOMUX_V1
+        select SOC_IMX1
         help
           This enables support for systems based on the Freescale i.MX1 family
 
 config ARCH_MX2
         bool "MX2-based"
-        select CPU_ARM926T
-        select IMX_HAVE_IOMUX_V1
         help
           This enables support for systems based on the Freescale i.MX2 family
 
@@ -25,6 +24,7 @@ config ARCH_MX25
         select CPU_ARM926T
         select ARCH_MXC_IOMUX_V3
         select HAVE_FB_IMX
+        select ARCH_MXC_AUDMUX_V2
         help
           This enables support for systems based on the Freescale i.MX25 family
 
@@ -48,8 +48,7 @@ config ARCH_MX5
 
 endchoice
 
-source "arch/arm/mach-mx1/Kconfig"
-source "arch/arm/mach-mx2/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 source "arch/arm/mach-mx25/Kconfig"
 source "arch/arm/mach-mxc91231/Kconfig"
@@ -81,6 +80,17 @@ config MXC_PWM
         help
           Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+        bool "Enable MXC debug board(for 3-stack)"
+        help
+          The debug board is an integral part of the MXC 3-stack(PDK)
+          platforms, it can be attached or removed from the peripheral
+          board. On debug board, several debug devices(ethernet, UART,
+          buttons, LEDs and JTAG) are implemented. Between the MCU and
+          these devices, a CPLD is added as a bridge which performs
+          data/address de-multiplexing and decode, signal level shift,
+          interrupt control and various board functions.
+
 config MXC_ULPI
         bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c5e0c0..78d405ed8616 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
 # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 
-obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
-obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
@@ -17,7 +15,10 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
+
+obj-y += devices/
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index b62917ca3f95..1180bef7664b 100644
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0c2cc5cd4d83..f9e7cdbd0005 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>
@@ -191,6 +187,7 @@ static int mxc_audmux_v2_init(void)
 {
         int ret;
 
+#if defined(CONFIG_ARCH_MX3)
         if (cpu_is_mx31())
                 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
 
@@ -204,7 +201,19 @@ static int mxc_audmux_v2_init(void)
                 }
                 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
         }
-
+#endif
+#if defined(CONFIG_ARCH_MX25)
+        if (cpu_is_mx25()) {
+                audmux_clk = clk_get(NULL, "audmux");
+                if (IS_ERR(audmux_clk)) {
+                        ret = PTR_ERR(audmux_clk);
+                        printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
+                                        ret);
+                        return ret;
+                }
+                audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
+        }
+#endif
         audmux_debugfs_init();
 
         return 0;
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 323ff8ccc877..2ed3ab173add 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -52,13 +52,14 @@ static void __clk_disable(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
                 return;
-
-        __clk_disable(clk->parent);
-        __clk_disable(clk->secondary);
-
         WARN_ON(!clk->usecount);
-        if (!(--clk->usecount) && clk->disable)
-                clk->disable(clk);
+
+        if (!(--clk->usecount)) {
+                if (clk->disable)
+                        clk->disable(clk);
+                __clk_disable(clk->parent);
+                __clk_disable(clk->secondary);
+        }
 }
 
 static int __clk_enable(struct clk *clk)
@@ -66,12 +67,13 @@ static int __clk_enable(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        __clk_enable(clk->parent);
-        __clk_enable(clk->secondary);
-
-        if (clk->usecount++ == 0 && clk->enable)
-                clk->enable(clk);
+        if (clk->usecount++ == 0) {
+                __clk_enable(clk->parent);
+                __clk_enable(clk->secondary);
 
+                if (clk->enable)
+                        clk->enable(clk);
+        }
         return 0;
 }
 
@@ -160,17 +162,28 @@ EXPORT_SYMBOL(clk_set_rate);
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
         int ret = -EINVAL;
+        struct clk *old;
 
         if (clk == NULL || IS_ERR(clk) || parent == NULL ||
             IS_ERR(parent) || clk->set_parent == NULL)
                 return ret;
 
+        if (clk->usecount)
+                clk_enable(parent);
+
         mutex_lock(&clocks_mutex);
         ret = clk->set_parent(clk, parent);
-        if (ret == 0)
+        if (ret == 0) {
+                old = clk->parent;
                 clk->parent = parent;
+        } else {
+                old = parent;
+        }
         mutex_unlock(&clocks_mutex);
 
+        if (clk->usecount)
+                clk_disable(old);
+
         return ret;
 }
 EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 56f2fb5cc456..735776d84956 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/err.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 
@@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
         return ret;
 }
 
+struct platform_device *__init imx_add_platform_device(const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data)
+{
+        int ret = -ENOMEM;
+        struct platform_device *pdev;
+
+        pdev = platform_device_alloc(name, id);
+        if (!pdev)
+                goto err;
+
+        if (res) {
+                ret = platform_device_add_resources(pdev, res, num_resources);
+                if (ret)
+                        goto err;
+        }
+
+        if (data) {
+                ret = platform_device_add_data(pdev, data, size_data);
+                if (ret)
+                        goto err;
+        }
+
+        ret = platform_device_add(pdev);
+        if (ret) {
+err:
+                platform_device_put(pdev);
+                return ERR_PTR(ret);
+        }
+
+        return pdev;
+}
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
new file mode 100644
index 000000000000..9ab784b776f9
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -0,0 +1,15 @@
+config IMX_HAVE_PLATFORM_FLEXCAN
+        select HAVE_CAN_FLEXCAN
+        bool
+
+config IMX_HAVE_PLATFORM_IMX_I2C
+        bool
+
+config IMX_HAVE_PLATFORM_IMX_UART
+        bool
+
+config IMX_HAVE_PLATFORM_MXC_NAND
+        bool
+
+config IMX_HAVE_PLATFORM_SPI_IMX
+        bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
new file mode 100644
index 000000000000..347da5161f7e
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -0,0 +1,8 @@
+ifdef CONFIG_CAN_FLEXCAN
+# the ifdef can be removed once the flexcan driver has been merged
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) +=  platform-flexcan.o
+endif
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c
new file mode 100644
index 000000000000..5e97a01f14f3
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-flexcan.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_flexcan(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct flexcan_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
new file mode 100644
index 000000000000..d0af9f7d8aed
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_i2c(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct imxi2c_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
new file mode 100644
index 000000000000..fa3dff1433e8
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irqrx, resource_size_t irqtx,
+                resource_size_t irqrts,
+                const struct imxuart_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irqrx,
+                        .end = irqrx,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = irqtx,
+                        .end = irqtx,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = irqrts,
+                        .end = irqrx,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct imxuart_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
new file mode 100644
index 000000000000..1c286418d123
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata,
+                resource_size_t iosize)
+{
+        static int id = 0;
+        
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata)
+{
+        return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
+}
+
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata)
+{
+        return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
new file mode 100644
index 000000000000..2831a6d3eb4b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_spi_imx(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct spi_imx_master *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 2a8646173c2f..35a064ff02ba 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -11,10 +11,6 @@
  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/platform_device.h>
@@ -73,7 +69,51 @@
 int mxc_initialize_usb_hw(int port, unsigned int flags)
 {
         unsigned int v;
-#ifdef CONFIG_ARCH_MX3
+#if defined(CONFIG_ARCH_MX25)
+        if (cpu_is_mx25()) {
+                v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                                     USBCTRL_OTGBASE_OFFSET));
+
+                switch (port) {
+                case 0: /* OTG port */
+                        v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                        << MX35_OTG_SIC_SHIFT;
+                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                                v |= MX35_OTG_PM_BIT;
+
+                        break;
+                case 1: /* H1 port */
+                        v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                                MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                                << MX35_H1_SIC_SHIFT;
+                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                                v |= MX35_H1_PM_BIT;
+
+                        if (!(flags & MXC_EHCI_TTL_ENABLED))
+                                v |= MX35_H1_TLL_BIT;
+
+                        if (flags & MXC_EHCI_INTERNAL_PHY)
+                                v |= MX35_H1_USBTE_BIT;
+
+                        if (flags & MXC_EHCI_IPPUE_DOWN)
+                                v |= MX35_H1_IPPUE_DOWN_BIT;
+
+                        if (flags & MXC_EHCI_IPPUE_UP)
+                                v |= MX35_H1_IPPUE_UP_BIT;
+
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                                     USBCTRL_OTGBASE_OFFSET));
+                return 0;
+        }
+#endif /* CONFIG_ARCH_MX25 */
+#if defined(CONFIG_ARCH_MX3)
         if (cpu_is_mx31()) {
                 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 71437c61cfd7..57ec4a896a5d 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -214,13 +214,16 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
         struct mxc_gpio_port *port =
                 container_of(chip, struct mxc_gpio_port, chip);
         u32 l;
+        unsigned long flags;
 
+        spin_lock_irqsave(&port->lock, flags);
         l = __raw_readl(port->base + GPIO_GDIR);
         if (dir)
                 l |= 1 << offset;
         else
                 l &= ~(1 << offset);
         __raw_writel(l, port->base + GPIO_GDIR);
+        spin_unlock_irqrestore(&port->lock, flags);
 }
 
 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -229,9 +232,12 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
                 container_of(chip, struct mxc_gpio_port, chip);
         void __iomem *reg = port->base + GPIO_DR;
         u32 l;
+        unsigned long flags;
 
+        spin_lock_irqsave(&port->lock, flags);
         l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
         __raw_writel(l, reg);
+        spin_unlock_irqrestore(&port->lock, flags);
 }
 
 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -285,6 +291,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 port[i].chip.base = i * 32;
                 port[i].chip.ngpio = 32;
 
+                spin_lock_init(&port[i].lock);
+
                 /* its a serious configuration bug when it fails */
                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
@@ -292,6 +300,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                         /* setup one handler for each entry */
                         set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
                         set_irq_data(port[i].irq, &port[i]);
+                        if (port[i].irq_high) {
+                                /* setup handler for GPIO 16 to 31 */
+                                set_irq_chained_handler(port[i].irq_high,
+                                                mx3_gpio_irq_handler);
+                                set_irq_data(port[i].irq_high, &port[i]);
+                        }
                 }
         }
 
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
new file mode 100644
index 000000000000..a384fdd49c62
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_3DS_DB_H__
+#define __ASM_ARCH_MXC_3DS_DB_H__
+
+extern int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
deleted file mode 100644
index 0376c133c9f4..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>.
- * All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
deleted file mode 100644
index 93cc66f104c7..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  Copyright (C) 2009  Yoichi Yuasa <yuasa@linux-mips.org>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
-#define __ARM_ARCH_BOARD_KZM_ARM11_H
-
-/*
- *  KZM-ARM11-01 Board Control Registers on FPGA
- */
-#define KZM_ARM11_CTL1          (MX31_CS4_BASE_ADDR + 0x1000)
-#define KZM_ARM11_CTL2          (MX31_CS4_BASE_ADDR + 0x1001)
-#define KZM_ARM11_RSW1          (MX31_CS4_BASE_ADDR + 0x1002)
-#define KZM_ARM11_BACK_LIGHT    (MX31_CS4_BASE_ADDR + 0x1004)
-#define KZM_ARM11_FPGA_REV      (MX31_CS4_BASE_ADDR + 0x1008)
-#define KZM_ARM11_7SEG_LED      (MX31_CS4_BASE_ADDR + 0x1010)
-#define KZM_ARM11_LEDS          (MX31_CS4_BASE_ADDR + 0x1020)
-#define KZM_ARM11_DIPSW2        (MX31_CS4_BASE_ADDR + 0x1003)
-
-/*
- * External UART for touch panel on FPGA
- */
-#define KZM_ARM11_16550         (MX31_CS4_BASE_ADDR + 0x1050)
-
-#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
-
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
deleted file mode 100644
index 0cf4fa29510c..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-
-/*
- * Memory-mapped I/O on MX21ADS base board
- */
-#define MX21ADS_MMIO_BASE_ADDR   0xF5000000
-#define MX21ADS_MMIO_SIZE        SZ_16M
-
-#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
-                (MX21ADS_MMIO_BASE_ADDR + (offset))
-
-#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
-#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
-#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
-#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
-#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
-
-/* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP        0x0001 /* read */
-#define MX21ADS_IO_TP6          0x0001 /* write */
-#define MX21ADS_IO_SW_SEL       0x0002 /* read */
-#define MX21ADS_IO_TP7          0x0002 /* write */
-#define MX21ADS_IO_RESET_E_UART 0x0004
-#define MX21ADS_IO_RESET_BASE   0x0008
-#define MX21ADS_IO_CSI_CTL2     0x0010
-#define MX21ADS_IO_CSI_CTL1     0x0020
-#define MX21ADS_IO_CSI_CTL0     0x0040
-#define MX21ADS_IO_UART1_EN     0x0080
-#define MX21ADS_IO_UART4_EN     0x0100
-#define MX21ADS_IO_LCDON        0x0200
-#define MX21ADS_IO_IRDA_EN      0x0400
-#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
-#define MX21ADS_IO_IRDA_MD0_B   0x1000
-#define MX21ADS_IO_IRDA_MD1     0x2000
-#define MX21ADS_IO_LED4_ON      0x4000
-#define MX21ADS_IO_LED3_ON      0x8000
-
-#endif                          /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
deleted file mode 100644
index 7776d230327f..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-
-/* external interrupt multiplexer */
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-
-#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
-#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
-#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
-#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
-
-#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
-                                MXC_MAX_VIRTUAL_INTS)
-
-/*
- * @name Memory Size parameters
- */
-
-/*
- * Size of SDRAM memory
- */
-#define SDRAM_MEM_SIZE          SZ_128M
-
-/*
- * PBC Controller parameters
- */
-
-/*
- * Base address of PBC controller, CS4
- */
-#define PBC_BASE_ADDRESS        0xf4300000
-#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
-                (PBC_BASE_ADDRESS + (offset))
-
-/*
- * PBC Interupt name definitions
- */
-#define PBC_GPIO1_0  0
-#define PBC_GPIO1_1  1
-#define PBC_GPIO1_2  2
-#define PBC_GPIO1_3  3
-#define PBC_GPIO1_4  4
-#define PBC_GPIO1_5  5
-
-#define PBC_INTR_MAX_NUM 6
-#define PBC_INTR_SHARED_MAX_NUM 8
-
-/* When the PBC address connection is fixed in h/w, defined as 1 */
-#define PBC_ADDR_SH             0
-
-/* Offsets for the PBC Controller register */
-/*
- * PBC Board version register offset
- */
-#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 set address.
- */
-#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 clear address.
- */
-#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 set address.
- */
-#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 clear address.
- */
-#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 clear address.
- */
-#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 4 clear address.
- */
-#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
-/*PBC_ADDR_SH
- * PBC Board status register 1.
- */
-#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt status register.
- */
-#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt current status register.
- */
-#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register set address.
- */
-#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register clear address.
- */
-#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
-/*
- * External UART A.
- */
-#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Status.
- */
-#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Set.
- */
-#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Clear.
- */
-#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller IO base address.
- */
-#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller Memory base address.
- */
-#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller DMA base address.
- */
-#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
-
-/* PBC Board Version Register bit definition */
-#define PBC_VERSION_ADS         0x8000  /* Bit15=1 means version for ads */
-#define PBC_VERSION_EVB_REVB    0x4000  /* BIT14=1 means version for evb revb */
-
-/* PBC Board Control Register 1 bit definitions */
-#define PBC_BCTRL1_ERST         0x0001  /* Ethernet Reset */
-#define PBC_BCTRL1_URST         0x0002  /* Reset External UART controller */
-#define PBC_BCTRL1_FRST         0x0004  /* FEC Reset */
-#define PBC_BCTRL1_ESLEEP       0x0010  /* Enable ethernet Sleep */
-#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
-
-/* PBC Board Control Register 2 bit definitions */
-#define PBC_BCTRL2_VCC_EN       0x0004  /*   Enable VCC */
-#define PBC_BCTRL2_VPP_EN       0x0008  /*   Enable Vpp */
-#define PBC_BCTRL2_ATAFEC_EN    0X0010
-#define PBC_BCTRL2_ATAFEC_SEL   0X0020
-#define PBC_BCTRL2_ATA_EN       0X0040
-#define PBC_BCTRL2_IRDA_SD      0X0080
-#define PBC_BCTRL2_IRDA_EN      0X0100
-#define PBC_BCTRL2_CCTL10       0X0200
-#define PBC_BCTRL2_CCTL11       0X0400
-
-/* PBC Board Control Register 3 bit definitions */
-#define PBC_BCTRL3_HSH_EN       0X0020
-#define PBC_BCTRL3_FSH_MOD      0X0040
-#define PBC_BCTRL3_OTG_HS_EN    0X0080
-#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
-#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
-#define PBC_BCTRL3_USB_OTG_ON   0X0800
-#define PBC_BCTRL3_USB_FSH_ON   0X1000
-
-/* PBC Board Control Register 4 bit definitions */
-#define PBC_BCTRL4_REGEN_SEL    0X0001
-#define PBC_BCTRL4_USER_OFF     0X0002
-#define PBC_BCTRL4_VIB_EN       0X0004
-#define PBC_BCTRL4_PWRGT1_EN    0X0008
-#define PBC_BCTRL4_PWRGT2_EN    0X0010
-#define PBC_BCTRL4_STDBY_PRI    0X0020
-
-#ifndef __ASSEMBLY__
-/*
- * Enumerations for SD cards and memory stick card. This corresponds to
- * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
- */
-enum mxc_card_no {
-        MXC_CARD_SD2 = 0,
-        MXC_CARD_SD3,
-        MXC_CARD_MS,
-        MXC_CARD_SD1,
-        MXC_CARD_MIN = MXC_CARD_SD2,
-        MXC_CARD_MAX = MXC_CARD_SD1,
-};
-#endif
-
-#define MXC_CPLD_VER_1_50       0x01
-
-/*
- * PBC BSTAT Register bit definitions
- */
-#define PBC_BSTAT_PRI_INT       0X0001
-#define PBC_BSTAT_USB_BYP       0X0002
-#define PBC_BSTAT_ATA_IOCS16    0X0004
-#define PBC_BSTAT_ATA_CBLID     0X0008
-#define PBC_BSTAT_ATA_DASP      0X0010
-#define PBC_BSTAT_PWR_RDY       0X0020
-#define PBC_BSTAT_SD3_WP        0X0100
-#define PBC_BSTAT_SD2_WP        0X0200
-#define PBC_BSTAT_SD1_WP        0X0400
-#define PBC_BSTAT_SD3_DET       0X0800
-#define PBC_BSTAT_SD2_DET       0X1000
-#define PBC_BSTAT_SD1_DET       0X2000
-#define PBC_BSTAT_MS_DET        0X4000
-#define PBC_BSTAT_SD3_DET_BIT   11
-#define PBC_BSTAT_SD2_DET_BIT   12
-#define PBC_BSTAT_SD1_DET_BIT   13
-#define PBC_BSTAT_MS_DET_BIT    14
-#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
-                                 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
-                                 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
-                                 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
-                                        0x0))))
-
-/*
- * PBC UART Control Register bit definitions
- */
-#define PBC_UCTRL_DCE_DCD       0X0001
-#define PBC_UCTRL_DCE_DSR       0X0002
-#define PBC_UCTRL_DCE_RI        0X0004
-#define PBC_UCTRL_DTE_DTR       0X0100
-
-/*
- * PBC UART Status Register bit definitions
- */
-#define PBC_USTAT_DTE_DCD       0X0001
-#define PBC_USTAT_DTE_DSR       0X0002
-#define PBC_USTAT_DTE_RI        0X0004
-#define PBC_USTAT_DCE_DTR       0X0100
-
-/*
- * PBC Interupt mask register bit definitions
- */
-#define PBC_INTR_SD3_R_EN_BIT   4
-#define PBC_INTR_SD2_R_EN_BIT   0
-#define PBC_INTR_SD1_R_EN_BIT   6
-#define PBC_INTR_MS_R_EN_BIT    5
-#define PBC_INTR_SD3_EN_BIT     13
-#define PBC_INTR_SD2_EN_BIT     12
-#define PBC_INTR_MS_EN_BIT      14
-#define PBC_INTR_SD1_EN_BIT     15
-
-#define PBC_INTR_SD2_R_EN       0x0001
-#define PBC_INTR_LOW_BAT        0X0002
-#define PBC_INTR_OTG_FSOVER     0X0004
-#define PBC_INTR_FSH_OVER       0X0008
-#define PBC_INTR_SD3_R_EN       0x0010
-#define PBC_INTR_MS_R_EN        0x0020
-#define PBC_INTR_SD1_R_EN       0x0040
-#define PBC_INTR_FEC_INT        0X0080
-#define PBC_INTR_ENET_INT       0X0100
-#define PBC_INTR_OTGFS_INT      0X0200
-#define PBC_INTR_XUART_INT      0X0400
-#define PBC_INTR_CCTL12         0X0800
-#define PBC_INTR_SD2_EN         0x1000
-#define PBC_INTR_SD3_EN         0x2000
-#define PBC_INTR_MS_EN          0x4000
-#define PBC_INTR_SD1_EN         0x8000
-
-
-
-/* For interrupts like xuart, enet etc */
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
-#define MXC_MAX_EXP_IO_LINES    16
-
-/*
- * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
- *
- */
-#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
-
-/*
- * This is System IRQ used by CS8900A for interrupt generation
- * taken from platform.h
- */
-#define CS8900AIRQ              EXPIO_INT_ENET_INT
-/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
-#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
-
-#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
-
-/*
-* This is used to detect if the CPLD version is for mx27 evb board rev-a
-*/
-#define PBC_CPLD_VERSION_IS_REVA() \
-        ((__raw_readw(PBC_VERSION_REG) & \
-        (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
-        == 0)
-
-/* This is used to active or inactive ata signal in CPLD .
- *  It is dependent with hardware
- */
-#define PBC_ATA_SIGNAL_ACTIVE() \
-        __raw_writew(           \
-                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-                PBC_BCTRL2_CLEAR_REG)
-
-#define PBC_ATA_SIGNAL_INACTIVE() \
-        __raw_writew(  \
-                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-                PBC_BCTRL2_SET_REG)
-
-#define MXC_BD_LED1             (1 << 5)
-#define MXC_BD_LED2             (1 << 6)
-#define MXC_BD_LED_ON(led) \
-        __raw_writew(led, PBC_BCTRL1_SET_REG)
-#define MXC_BD_LED_OFF(led) \
-        __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
-
-/* to determine the correct external crystal reference */
-#define CKIH_27MHZ_BIT_SET      (1 << 3)
-
-#endif                          /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
deleted file mode 100644
index ea87551d2736..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
deleted file mode 100644
index fec1bcfa9164..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
deleted file mode 100644
index da92933a233b..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-
-/* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS              CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR               CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR                       (DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG                    (CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG             (CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG               (CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG              (CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG          (CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG          (CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG               (CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG          (CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG           (CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG           (CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET          (MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A       (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B       (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A      (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B      (MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES    16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 095a199591c6..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-
-#include <mach/hardware.h>
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
-/* Offsets for the PBC Controller register */
-
-/* PBC Board status register offset */
-#define PBC_BSTAT               0x000002
-
-/* PBC Board control register 1 set address */
-#define PBC_BCTRL1_SET          0x000004
-
-/* PBC Board control register 1 clear address */
-#define PBC_BCTRL1_CLEAR        0x000006
-
-/* PBC Board control register 2 set address */
-#define PBC_BCTRL2_SET          0x000008
-
-/* PBC Board control register 2 clear address */
-#define PBC_BCTRL2_CLEAR        0x00000A
-
-/* PBC Board control register 3 set address */
-#define PBC_BCTRL3_SET          0x00000C
-
-/* PBC Board control register 3 clear address */
-#define PBC_BCTRL3_CLEAR        0x00000E
-
-/* PBC Board control register 4 set address */
-#define PBC_BCTRL4_SET          0x000010
-
-/* PBC Board control register 4 clear address */
-#define PBC_BCTRL4_CLEAR        0x000012
-
-/* PBC Board status register 1 */
-#define PBC_BSTAT1              0x000014
-
-/* PBC Board interrupt status register */
-#define PBC_INTSTATUS           0x000016
-
-/* PBC Board interrupt current status register */
-#define PBC_INTCURR_STATUS      0x000018
-
-/* PBC Interrupt mask register set address */
-#define PBC_INTMASK_SET         0x00001A
-
-/* PBC Interrupt mask register clear address */
-#define PBC_INTMASK_CLEAR       0x00001C
-
-/* External UART A */
-#define PBC_SC16C652_UARTA      0x010000
-
-/* External UART B */
-#define PBC_SC16C652_UARTB      0x010010
-
-/* Ethernet Controller IO base address */
-#define PBC_CS8900A_IOBASE      0x020000
-
-/* Ethernet Controller Memory base address */
-#define PBC_CS8900A_MEMBASE     0x021000
-
-/* Ethernet Controller DMA base address */
-#define PBC_CS8900A_DMABASE     0x022000
-
-/* External chip select 0 */
-#define PBC_XCS0                0x040000
-
-/* LCD Display enable */
-#define PBC_LCD_EN_B            0x060000
-
-/* Code test debug enable */
-#define PBC_CODE_B              0x070000
-
-/* PSRAM memory select */
-#define PBC_PSRAM_B             0x5000000
-
-#define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
-#define PBC_INTCURR_STATUS_REG  (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
-
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_RES7          (MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SYNTH_IRQ     (MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_CE_INT1       (MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_CE_INT2       (MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_RES15         (MXC_EXP_IO_BASE + 15)
-
-#define MXC_MAX_EXP_IO_LINES    16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index eb5a5024622e..0df71bfefbb1 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -31,7 +31,7 @@ enum mx31lilly_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lilly_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 2b2da0367578..c1ad0ae807cc 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -32,7 +32,7 @@ enum mx31lite_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lite_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 36ff3cedee1a..de14543891cf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -31,7 +31,7 @@ enum mx31moboard_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31moboard_devboard_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 410f9786ed22..6f371e35753d 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -22,7 +22,7 @@
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
  * inside pcm038_init().
  *
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
deleted file mode 100644
index 6d88c7af4b23..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
-#define __ASM_ARCH_MXC_BOARD_QONG_H__
-
-/* NOR FLASH */
-#define QONG_NOR_SIZE           (128*1024*1024)
-
-#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 0b6e11eaeb8c..25606409aabc 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -23,8 +23,8 @@
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
 #include <mach/mx25.h>
-#define UART_PADDR      UART1_BASE_ADDR
-#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#define UART_PADDR      MX25_UART1_BASE_ADDR
+#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
 #endif
 
 #ifdef CONFIG_ARCH_MX2
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644
index 000000000000..c5f68c587309
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+struct platform_device *imx_add_platform_device(const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data);
+
+#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE)
+#include <linux/can/platform/flexcan.h>
+struct platform_device *__init imx_add_flexcan(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct flexcan_platform_data *pdata);
+#else
+/* the ifdef can be removed once the flexcan driver has been merged */
+struct flexcan_platform_data;
+static inline struct platform_device *__init imx_add_flexcan(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct flexcan_platform_data *pdata)
+{
+        return NULL;
+}
+#endif
+
+#include <mach/i2c.h>
+struct platform_device *__init imx_add_imx_i2c(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct imxi2c_platform_data *pdata);
+
+#include <mach/imx-uart.h>
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irqrx, resource_size_t irqtx,
+                resource_size_t irqrts,
+                const struct imxuart_platform_data *pdata);
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct imxuart_platform_data *pdata);
+
+#include <mach/mxc_nand.h>
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata);
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata);
+
+#include <mach/spi.h>
+struct platform_device *__init imx_add_spi_imx(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index a1fd5830af48..634e3f4c454d 100644
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
  *
  * Based on board-pcm038.h which is :
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -19,22 +19,29 @@
  * MA 02110-1301, USA.
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
-#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+#ifndef __MACH_EUKREA_BASEBOARDS_H__
+#define __MACH_EUKREA_BASEBOARDS_H__
 
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
  * its own devices, it calls baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
- * inside eukrea_cpuimx27_init().
+ * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
+ * eukrea_cpuimx35_init() or eukrea_cpuimx51_init().
  *
  * This example here is for the development board. Refer
- * eukrea_mbimx27-baseboard.c
+ * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
+ * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
+ * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
+ * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
  */
 
+extern void eukrea_mbimx25_baseboard_init(void);
 extern void eukrea_mbimx27_baseboard_init(void);
+extern void eukrea_mbimx35_baseboard_init(void);
+extern void eukrea_mbimx51_baseboard_init(void);
 
 #endif
 
-#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
+#endif /* __MACH_EUKREA_BASEBOARDS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 894d2f87c856..661fbc605759 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -33,9 +33,11 @@
 struct mxc_gpio_port {
         void __iomem *base;
         int irq;
+        int irq_high;
         int virtual_irq_start;
         struct gpio_chip chip;
         u32 both_edges;
+        spinlock_t lock;
 };
 
 int mxc_gpio_init(struct mxc_gpio_port*, int);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f39220d1b67a..d7f52c91f82e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -252,6 +252,7 @@
 #define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__PWM4_PWMO    IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
@@ -371,30 +372,41 @@
 #define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
+#define KPP_CTL_ROW     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define KPP_CTL_COL     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
 #define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
 #define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL0__AUD5_TXD     IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL1__AUD5_RXD     IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL2__UART4_RTS    IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL2__AUD5_TXC     IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL3__UART4_CTS    IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL3__AUD5_TXFS    IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d953d0..21bfa46785bb 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
         IOMUX_CONFIG_ALT5,
         IOMUX_CONFIG_ALT6,
         IOMUX_CONFIG_ALT7,
-        IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
-        IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
+        IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
+        IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* Pad control groupings */
@@ -38,6 +38,8 @@ typedef enum iomux_config {
                                 PAD_CTL_SRE_FAST)
 #define MX51_UART3_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
                                 PAD_CTL_SRE_FAST)
+#define MX51_I2C_PAD_CTRL       (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
 #define MX51_USBH1_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
                                 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
                                 PAD_CTL_PKE | PAD_CTL_HYS)
@@ -46,289 +48,278 @@ typedef enum iomux_config {
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
  */
 
-/*
- * FIXME: This was converted using scripts from existing Freescale code to
- * this form used upstream. Need to verify the name format.
- */
-
-/*                                              PAD      MUX   ALT INPSE PATH PADCTRL */
-
-#define MX51_PAD_GPIO_2_0__EIM_D16      IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17      IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18      IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19      IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20      IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21      IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5      IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22      IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23      IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS     IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD     IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD     IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS     IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28       IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29       IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30       IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31       IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16     IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17     IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18     IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19     IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20     IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21     IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22     IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23     IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24     IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25     IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26     IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27     IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0       IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1       IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2     IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3     IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE      IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0     IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1     IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2     IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3     IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4     IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5     IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK   IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA      IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE      IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1     IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B   IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B   IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE    IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE    IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B   IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0    IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1    IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2   IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3   IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND   IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4   IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6   IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0   IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1   IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2   IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3   IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4   IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5   IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6   IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7   IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT       IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15   IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14   IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13   IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12   IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11   IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10   IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9    IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8     IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7     IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6     IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5     IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4     IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3     IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2     IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1     IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0     IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8     IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9     IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10     IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11     IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12     IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13     IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14     IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15     IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16     IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17     IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18     IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19     IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK   IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0   IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12     IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13    IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14    IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15    IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16    IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17    IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18    IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19    IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC  IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC  IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0   IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK    IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT    IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK  IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS  IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI  IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO  IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0   IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1   IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY   IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK  IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD   IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD   IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE  IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0     IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1     IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2     IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3     IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0     IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1     IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2     IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3     IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4     IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5     IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK   IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR   IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP   IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27   IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT   IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11    IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12    IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13    IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS    IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS    IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3     IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2     IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4     IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2     IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3     IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6  IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7  IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8  IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9  IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0      IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1      IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD       IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK       IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0   IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1   IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2   IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3   IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2      IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3      IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4      IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5      IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6      IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7      IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8      IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-                                                (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9      IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0       IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1       IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2       IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3       IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4       IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5       IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6       IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7       IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8       IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9       IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10     IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11     IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12     IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13     IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14     IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15     IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+/*                                                        PAD    MUX   ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \
+                                                        0x09b4, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \
+                                                        0x09b0, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5              IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__HSI2C_CLK            IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__HSI2C_DAT            IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \
+                                                        0x09b8, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, 0,     0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \
+                                                        0x09bc, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0             IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1             IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2             IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__I2C2_SCL             IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
+                                                        0x9b8,   3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3             IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__I2C2_SDA             IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
+                                                        0x9bc,   3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4             IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5             IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6             IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7             IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8             IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9             IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 3887f3fe29d4..15d59510f597 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __MACH_IOMUX_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d31d5ba..0880a4a1aed1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST                (1 << 0)
 #define PAD_CTL_SRE_SLOW                (0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT      4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA      (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB      (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC      (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD      (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE      (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF      (5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index c4b40c35a6a1..564ec9dbc93d 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -44,12 +44,12 @@
  */
 #define CONSISTENT_DMA_SIZE SZ_8M
 
-#elif defined(CONFIG_MX1_VIDEO)
+#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT)
 /*
  * Increase size of DMA-consistent memory region.
  * This is required for i.MX camera driver to capture at least four VGA frames.
  */
 #define CONSISTENT_DMA_SIZE SZ_4M
-#endif /* CONFIG_MX1_VIDEO */
+#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */
 
 #endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index de2128dada5c..29115f405af9 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -31,6 +31,9 @@ struct imxmmc_platform_data {
 
         /* adjust slot voltage */
         void (*setpower)(struct device *, unsigned int vdd);
+
+        /* enable card detect using DAT3 */
+        int dat3_card_detect;
 };
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 5eba7e6785de..641b24618239 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -91,24 +91,24 @@
 #define MX1_SIM_DATA_INT        16
 #define MX1_RTC_INT             17
 #define MX1_RTC_SAMINT          18
-#define MX1_UART2_MINT_PFERR    19
-#define MX1_UART2_MINT_RTS      20
-#define MX1_UART2_MINT_DTR      21
-#define MX1_UART2_MINT_UARTC    22
-#define MX1_UART2_MINT_TX       23
-#define MX1_UART2_MINT_RX       24
-#define MX1_UART1_MINT_PFERR    25
-#define MX1_UART1_MINT_RTS      26
-#define MX1_UART1_MINT_DTR      27
-#define MX1_UART1_MINT_UARTC    28
-#define MX1_UART1_MINT_TX       29
-#define MX1_UART1_MINT_RX       30
+#define MX1_INT_UART2PFERR      19
+#define MX1_INT_UART2RTS        20
+#define MX1_INT_UART2DTR        21
+#define MX1_INT_UART2UARTC      22
+#define MX1_INT_UART2TX         23
+#define MX1_INT_UART2RX         24
+#define MX1_INT_UART1PFERR      25
+#define MX1_INT_UART1RTS        26
+#define MX1_INT_UART1DTR        27
+#define MX1_INT_UART1UARTC      28
+#define MX1_INT_UART1TX         29
+#define MX1_INT_UART1RX         30
 #define MX1_VOICE_DAC_INT       31
 #define MX1_VOICE_ADC_INT       32
 #define MX1_PEN_DATA_INT        33
 #define MX1_PWM_INT             34
 #define MX1_SDHC_INT            35
-#define MX1_I2C_INT             39
+#define MX1_INT_I2C             39
 #define MX1_CSPI_INT            41
 #define MX1_SSI_TX_INT          42
 #define MX1_SSI_TX_ERR_INT      43
@@ -245,7 +245,7 @@
 #define PEN_DATA_INT MX1_PEN_DATA_INT
 #define PWM_INT MX1_PWM_INT
 #define SDHC_INT MX1_SDHC_INT
-#define I2C_INT MX1_I2C_INT
+#define I2C_INT MX1_INT_I2C
 #define CSPI_INT MX1_CSPI_INT
 #define SSI_TX_INT MX1_SSI_TX_INT
 #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4eb6e334bda5..4a6f800990f8 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -11,6 +11,12 @@
 #define MX25_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX25_AVIC_SIZE                  SZ_1M
 
+#define MX25_I2C1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x80000)
+#define MX25_I2C3_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x84000)
+#define MX25_CAN1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x88000)
+#define MX25_CAN2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x8c000)
+#define MX25_I2C2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x98000)
+#define MX25_CSPI1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0xa4000)
 #define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
 
 #define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -27,22 +33,48 @@
         IMX_IO_ADDRESS(x, MX25_AIPS2) ?:                        \
         IMX_IO_ADDRESS(x, MX25_AVIC))
 
+#define MX25_AIPS1_IO_ADDRESS(x) \
+        (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
+
 #define MX25_UART1_BASE_ADDR            0x43f90000
 #define MX25_UART2_BASE_ADDR            0x43f94000
+#define MX25_AUDMUX_BASE_ADDR           0x43fb0000
+#define MX25_UART3_BASE_ADDR            0x5000c000
+#define MX25_UART4_BASE_ADDR            0x50008000
+#define MX25_UART5_BASE_ADDR            0x5002c000
 
+#define MX25_CSPI3_BASE_ADDR            0x50004000
+#define MX25_CSPI2_BASE_ADDR            0x50010000
 #define MX25_FEC_BASE_ADDR              0x50038000
+#define MX25_SSI2_BASE_ADDR             0x50014000
+#define MX25_SSI1_BASE_ADDR             0x50034000
 #define MX25_NFC_BASE_ADDR              0xbb000000
 #define MX25_DRYICE_BASE_ADDR           0x53ffc000
 #define MX25_LCDC_BASE_ADDR             0x53fbc000
+#define MX25_KPP_BASE_ADDR              0x43fa8000
+#define MX25_OTG_BASE_ADDR              0x53ff4000
+#define MX25_CSI_BASE_ADDR              0x53ff8000
 
-#define MX25_INT_DRYICE 25
-#define MX25_INT_FEC    57
-#define MX25_INT_NANDFC 33
-#define MX25_INT_LCDC   39
-
-#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
-#define UART1_BASE_ADDR                 MX25_UART1_BASE_ADDR
-#define UART2_BASE_ADDR                 MX25_UART2_BASE_ADDR
-#endif
+#define MX25_INT_CSPI3          0
+#define MX25_INT_I2C1           3
+#define MX25_INT_I2C2           4
+#define MX25_INT_UART4          5
+#define MX25_INT_I2C3           10
+#define MX25_INT_SSI2           11
+#define MX25_INT_SSI1           12
+#define MX25_INT_CSPI2          13
+#define MX25_INT_CSPI1          14
+#define MX25_INT_CSI            17
+#define MX25_INT_UART3          18
+#define MX25_INT_KPP            24
+#define MX25_INT_DRYICE         25
+#define MX25_INT_UART2          32
+#define MX25_INT_NANDFC         33
+#define MX25_INT_LCDC           39
+#define MX25_INT_UART5          40
+#define MX25_INT_CAN1           43
+#define MX25_INT_CAN2           44
+#define MX25_INT_UART1          45
+#define MX25_INT_FEC            57
 
 #endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index bae9cd75beee..a8ab2e02a8ca 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -48,7 +48,7 @@
 #define MX27_CSPI2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0f000)
 #define MX27_SSI1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x10000)
 #define MX27_SSI2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_I2C1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x12000)
 #define MX27_SDHC1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x13000)
 #define MX27_SDHC2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x14000)
 #define MX27_GPIO_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x15000)
@@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_INT_SDHC3          9
 #define MX27_INT_SDHC2          10
 #define MX27_INT_SDHC1          11
-#define MX27_INT_I2C            12
+#define MX27_INT_I2C1           12
 #define MX27_INT_SSI2           13
 #define MX27_INT_SSI1           14
 #define MX27_INT_CSPI2          15
diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
new file mode 100644
index 000000000000..3c080a32dbf5
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -0,0 +1,46 @@
+/*
+ * mx2-cam.h - i.MX27/i.MX25 camera driver header file
+ *
+ * Copyright (C) 2003, Intel Corporation
+ * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MX2_CAM_H_
+#define __MACH_MX2_CAM_H_
+
+#define MX2_CAMERA_SWAP16               (1 << 0)
+#define MX2_CAMERA_EXT_VSYNC            (1 << 1)
+#define MX2_CAMERA_CCIR                 (1 << 2)
+#define MX2_CAMERA_CCIR_INTERLACE       (1 << 3)
+#define MX2_CAMERA_HSYNC_HIGH           (1 << 4)
+#define MX2_CAMERA_GATED_CLOCK          (1 << 5)
+#define MX2_CAMERA_INV_DATA             (1 << 6)
+#define MX2_CAMERA_PCLK_SAMPLE_RISING   (1 << 7)
+#define MX2_CAMERA_PACK_DIR_MSB         (1 << 8)
+
+/**
+ * struct mx2_camera_platform_data - optional platform data for mx2_camera
+ * @flags: any combination of MX2_CAMERA_*
+ * @clk: clock rate of the csi block / 2
+ */
+struct mx2_camera_platform_data {
+        unsigned long flags;
+        unsigned long clk;
+};
+
+#endif /* __MACH_MX2_CAM_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e119c2b5..afee3ab9d62e 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -23,7 +23,7 @@
 #define MX31_ETB_SLOT4_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x10000)
 #define MX31_ETB_SLOT5_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x14000)
 #define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x80000)
 #define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
 #define MX31_OTG_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
 #define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
@@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_FIRI           7
 #define MX31_INT_MMC_SDHC2      8
 #define MX31_INT_MMC_SDHC1      9
-#define MX31_INT_I2C            10
+#define MX31_INT_I2C1           10
 #define MX31_INT_SSI2           11
 #define MX31_INT_SSI1           12
 #define MX31_INT_CSPI2          13
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae5..af3038c12e39 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
 #define MX35_ETB_SLOT4_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x10000)
 #define MX35_ETB_SLOT5_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x14000)
 #define MX35_ECT_CTIO_BASE_ADDR                 (MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C1_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x80000)
 #define MX35_I2C3_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x84000)
 #define MX35_UART1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x90000)
 #define MX35_UART2_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -60,6 +60,8 @@
 #define MX35_RTC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xd8000)
 #define MX35_WDOG_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xdc000)
 #define MX35_PWM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_CAN1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe4000)
+#define MX35_CAN2_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe8000)
 #define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
 #define MX35_OTG_BASE_ADDR              0x53ff4000
 
@@ -123,7 +125,7 @@
 #define MX35_INT_MMC_SDHC1      7
 #define MX35_INT_MMC_SDHC2      8
 #define MX35_INT_MMC_SDHC3      9
-#define MX35_INT_I2C            10
+#define MX35_INT_I2C1           10
 #define MX35_INT_SSI1           11
 #define MX35_INT_SSI2           12
 #define MX35_INT_CSPI2          13
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
index 36d7ff27b5e2..f226ee3777e1 100644
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #ifndef _MX3_CAMERA_H_
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 5182b986b785..0ca3101ebf36 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __MACH_MXC91231_H__
 #define __MACH_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 5d2d21d414e0..04c0d060d814 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -20,9 +20,13 @@
 #ifndef __ASM_ARCH_NAND_H
 #define __ASM_ARCH_NAND_H
 
+#include <linux/mtd/partitions.h>
+
 struct mxc_nand_platform_data {
-        int width;      /* data bus width in bytes */
-        int hw_ecc:1;   /* 0 if supress hardware ECC */
-        int flash_bbt:1; /* set to 1 to use a flash based bbt */
+        unsigned int width;     /* data bus width in bytes */
+        unsigned int hw_ecc:1;  /* 0 if supress hardware ECC */
+        unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
+        struct mtd_partition *parts;    /* partition table */
+        int nr_parts;                   /* size of parts */
 };
 #endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index ef00199568de..4acd1143a9bd 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 024416ed11cd..2d9624697cc9 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_TIMEX_H__
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index b6d3d0fddc48..d9bd37e4667a 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
 #define __ASM_ARCH_MXC_UNCOMPRESS_H__
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 44243a278434..ef6379c474be 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_VMALLOC_H__
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 778ddfe57d89..7331f2ace5fe 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase)
         for (i = 0; i < 8; i++)
                 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 
-        /* init architectures chained interrupt handler */
-        mxc_register_gpios();
-
 #ifdef CONFIG_FIQ
         /* Initialize FIQ */
         init_FIQ();
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 97f42799fa58..925bce4607e7 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 9b86d2a60d43..b3da9aad4295 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
                 set_irq_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
-        mxc_register_gpios();
-
         pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
 
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 5a6ef252c38b..977c8f9a07a2 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,7 @@
 #include <linux/irq.h>
 #include <linux/slab.h>
 
+#include <plat/pincfg.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 
@@ -46,28 +47,217 @@ struct nmk_gpio_chip {
         u32 edge_falling;
 };
 
+static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
+                                unsigned offset, int gpio_mode)
+{
+        u32 bit = 1 << offset;
+        u32 afunc, bfunc;
+
+        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
+        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
+        if (gpio_mode & NMK_GPIO_ALT_A)
+                afunc |= bit;
+        if (gpio_mode & NMK_GPIO_ALT_B)
+                bfunc |= bit;
+        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
+        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+}
+
+static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
+                                unsigned offset, enum nmk_gpio_slpm mode)
+{
+        u32 bit = 1 << offset;
+        u32 slpm;
+
+        slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
+        if (mode == NMK_GPIO_SLPM_NOCHANGE)
+                slpm |= bit;
+        else
+                slpm &= ~bit;
+        writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
+}
+
+static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
+                                unsigned offset, enum nmk_gpio_pull pull)
+{
+        u32 bit = 1 << offset;
+        u32 pdis;
+
+        pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
+        if (pull == NMK_GPIO_PULL_NONE)
+                pdis |= bit;
+        else
+                pdis &= ~bit;
+        writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
+
+        if (pull == NMK_GPIO_PULL_UP)
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
+        else if (pull == NMK_GPIO_PULL_DOWN)
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
+}
+
+static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
+                                  unsigned offset)
+{
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
+}
+
+static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
+                             pin_cfg_t cfg)
+{
+        static const char *afnames[] = {
+                [NMK_GPIO_ALT_GPIO]     = "GPIO",
+                [NMK_GPIO_ALT_A]        = "A",
+                [NMK_GPIO_ALT_B]        = "B",
+                [NMK_GPIO_ALT_C]        = "C"
+        };
+        static const char *pullnames[] = {
+                [NMK_GPIO_PULL_NONE]    = "none",
+                [NMK_GPIO_PULL_UP]      = "up",
+                [NMK_GPIO_PULL_DOWN]    = "down",
+                [3] /* illegal */       = "??"
+        };
+        static const char *slpmnames[] = {
+                [NMK_GPIO_SLPM_INPUT]           = "input",
+                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change",
+        };
+
+        int pin = PIN_NUM(cfg);
+        int pull = PIN_PULL(cfg);
+        int af = PIN_ALT(cfg);
+        int slpm = PIN_SLPM(cfg);
+
+        dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n",
+                pin, afnames[af], pullnames[pull], slpmnames[slpm]);
+
+        __nmk_gpio_make_input(nmk_chip, offset);
+        __nmk_gpio_set_pull(nmk_chip, offset, pull);
+        __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
+        __nmk_gpio_set_mode(nmk_chip, offset, af);
+}
+
+/**
+ * nmk_config_pin - configure a pin's mux attributes
+ * @cfg: pin confguration
+ *
+ * Configures a pin's mode (alternate function or GPIO), its pull up status,
+ * and its sleep mode based on the specified configuration.  The @cfg is
+ * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
+ * are constructed using, and can be further enhanced with, the macros in
+ * plat/pincfg.h.
+ *
+ * If a pin's mode is set to GPIO, it is configured as an input to avoid
+ * side-effects.  The gpio can be manipulated later using standard GPIO API
+ * calls.
+ */
+int nmk_config_pin(pin_cfg_t cfg)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        int gpio = PIN_NUM(cfg);
+        unsigned long flags;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(nmk_config_pin);
+
+/**
+ * nmk_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several pins using nmk_config_pin().  Refer to that function for
+ * further information.
+ */
+int nmk_config_pins(pin_cfg_t *cfgs, int num)
+{
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < num; i++) {
+                int ret = nmk_config_pin(cfgs[i]);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(nmk_config_pins);
+
+/**
+ * nmk_gpio_set_slpm() - configure the sleep mode of a pin
+ * @gpio: pin number
+ * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
+ *
+ * Sets the sleep mode of a pin.  If @mode is NMK_GPIO_SLPM_INPUT, the pin is
+ * changed to an input (with pullup/down enabled) in sleep and deep sleep.  If
+ * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
+ * configured even when in sleep and deep sleep.
+ */
+int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
+}
+
+/**
+ * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
+ * @gpio: pin number
+ * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
+ *
+ * Enables/disables pull up/down on a specified pin.  This only takes effect if
+ * the pin is configured as an input (either explicitly or by the alternate
+ * function).
+ *
+ * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
+ * configured as an input.  Otherwise, due to the way the controller registers
+ * work, this function will change the value output on the pin.
+ */
+int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
+}
+
 /* Mode functions */
 int nmk_gpio_set_mode(int gpio, int gpio_mode)
 {
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
-        u32 afunc, bfunc, bit;
 
         nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
         if (!nmk_chip)
                 return -EINVAL;
 
-        bit = 1 << (gpio - nmk_chip->chip.base);
-
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
-        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
-        if (gpio_mode & NMK_GPIO_ALT_A)
-                afunc |= bit;
-        if (gpio_mode & NMK_GPIO_ALT_B)
-                bfunc |= bit;
-        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
-        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+        __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
         return 0;
@@ -111,32 +301,41 @@ static void nmk_gpio_irq_ack(unsigned int irq)
         writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
 }
 
+enum nmk_gpio_irq_type {
+        NORMAL,
+        WAKE,
+};
+
 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
-                                  int gpio, bool enable)
+                                  int gpio, enum nmk_gpio_irq_type which,
+                                  bool enable)
 {
+        u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
+        u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
         u32 bitmask = nmk_gpio_get_bitmask(gpio);
         u32 reg;
 
         /* we must individually set/clear the two edges */
         if (nmk_chip->edge_rising & bitmask) {
-                reg = readl(nmk_chip->addr + NMK_GPIO_RIMSC);
+                reg = readl(nmk_chip->addr + rimsc);
                 if (enable)
                         reg |= bitmask;
                 else
                         reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + NMK_GPIO_RIMSC);
+                writel(reg, nmk_chip->addr + rimsc);
         }
         if (nmk_chip->edge_falling & bitmask) {
-                reg = readl(nmk_chip->addr + NMK_GPIO_FIMSC);
+                reg = readl(nmk_chip->addr + fimsc);
                 if (enable)
                         reg |= bitmask;
                 else
                         reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + NMK_GPIO_FIMSC);
+                writel(reg, nmk_chip->addr + fimsc);
         }
 }
 
-static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
+static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
+                               bool enable)
 {
         int gpio;
         struct nmk_gpio_chip *nmk_chip;
@@ -147,26 +346,35 @@ static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
         nmk_chip = get_irq_chip_data(irq);
         bitmask = nmk_gpio_get_bitmask(gpio);
         if (!nmk_chip)
-                return;
+                return -EINVAL;
 
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_gpio_irq_modify(nmk_chip, gpio, enable);
+        __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+        return 0;
 }
 
 static void nmk_gpio_irq_mask(unsigned int irq)
 {
-        nmk_gpio_irq_modify(irq, false);
-};
+        nmk_gpio_irq_modify(irq, NORMAL, false);
+}
 
 static void nmk_gpio_irq_unmask(unsigned int irq)
 {
-        nmk_gpio_irq_modify(irq, true);
+        nmk_gpio_irq_modify(irq, NORMAL, true);
+}
+
+static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        return nmk_gpio_irq_modify(irq, WAKE, on);
 }
 
 static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
 {
-        bool enabled = !(irq_to_desc(irq)->status & IRQ_DISABLED);
+        struct irq_desc *desc = irq_to_desc(irq);
+        bool enabled = !(desc->status & IRQ_DISABLED);
+        bool wake = desc->wake_depth;
         int gpio;
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
@@ -186,7 +394,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
         spin_lock_irqsave(&nmk_chip->lock, flags);
 
         if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, false);
+                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
+
+        if (wake)
+                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
 
         nmk_chip->edge_rising &= ~bitmask;
         if (type & IRQ_TYPE_EDGE_RISING)
@@ -197,7 +408,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
                 nmk_chip->edge_falling |= bitmask;
 
         if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, true);
+                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
+
+        if (wake)
+                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
 
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
@@ -210,6 +424,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
         .mask           = nmk_gpio_irq_mask,
         .unmask         = nmk_gpio_irq_unmask,
         .set_type       = nmk_gpio_irq_set_type,
+        .set_wake       = nmk_gpio_irq_set_wake,
 };
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -266,16 +481,6 @@ static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
         return 0;
 }
 
-static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
-                                int val)
-{
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-
-        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
-        return 0;
-}
-
 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
 {
         struct nmk_gpio_chip *nmk_chip =
@@ -298,12 +503,33 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
                 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
 }
 
+static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
+                                int val)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
+        nmk_gpio_set_output(chip, offset, val);
+
+        return 0;
+}
+
+static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+
+        return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
+}
+
 /* This structure is replicated for each GPIO block allocated at probe time */
 static struct gpio_chip nmk_gpio_template = {
         .direction_input        = nmk_gpio_make_input,
         .get                    = nmk_gpio_get_input,
         .direction_output       = nmk_gpio_make_output,
         .set                    = nmk_gpio_set_output,
+        .to_irq                 = nmk_gpio_to_irq,
         .ngpio                  = NMK_GPIO_PER_CHIP,
         .can_sleep              = 0,
 };
@@ -393,30 +619,12 @@ out:
         return ret;
 }
 
-static int __exit nmk_gpio_remove(struct platform_device *dev)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        struct resource *res;
-
-        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-
-        nmk_chip = platform_get_drvdata(dev);
-        gpiochip_remove(&nmk_chip->chip);
-        clk_disable(nmk_chip->clk);
-        clk_put(nmk_chip->clk);
-        kfree(nmk_chip);
-        release_mem_region(res->start, resource_size(res));
-        return 0;
-}
-
-
 static struct platform_driver nmk_gpio_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name = "gpio",
                 },
         .probe = nmk_gpio_probe,
-        .remove = __exit_p(nmk_gpio_remove),
         .suspend = NULL, /* to be done */
         .resume = NULL,
 };
@@ -426,7 +634,7 @@ static int __init nmk_gpio_init(void)
         return platform_driver_register(&nmk_gpio_driver);
 }
 
-arch_initcall(nmk_gpio_init);
+core_initcall(nmk_gpio_init);
 
 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
 MODULE_DESCRIPTION("Nomadik GPIO Driver");
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 4200811249ca..aba355101f49 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -55,6 +55,21 @@
 #define NMK_GPIO_ALT_B  2
 #define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
 
+/* Pull up/down values */
+enum nmk_gpio_pull {
+        NMK_GPIO_PULL_NONE,
+        NMK_GPIO_PULL_UP,
+        NMK_GPIO_PULL_DOWN,
+};
+
+/* Sleep mode */
+enum nmk_gpio_slpm {
+        NMK_GPIO_SLPM_INPUT,
+        NMK_GPIO_SLPM_NOCHANGE,
+};
+
+extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
+extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
 extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
 extern int nmk_gpio_get_mode(int gpio);
 
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 42c907258b14..65704a3d4241 100644
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,6 +1,12 @@
 #ifndef __PLAT_MTU_H
 #define __PLAT_MTU_H
 
+/*
+ * Guaranteed runtime conversion range in seconds for
+ * the clocksource and clockevent.
+ */
+#define MTU_MIN_RANGE 4
+
 /* should be set by the platform code */
 extern void __iomem *mtu_base;
 
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
new file mode 100644
index 000000000000..7eed11c1038d
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ *
+ * Based on arch/arm/mach-pxa/include/mach/mfp.h:
+ *   Copyright (C) 2007 Marvell International Ltd.
+ *   eric miao <eric.miao@marvell.com>
+ */
+
+#ifndef __PLAT_PINCFG_H
+#define __PLAT_PINCFG_H
+
+/*
+ * pin configurations are represented by 32-bit integers:
+ *
+ *      bit  0.. 8 - Pin Number (512 Pins Maximum)
+ *      bit  9..10 - Alternate Function Selection
+ *      bit 11..12 - Pull up/down state
+ *      bit     13 - Sleep mode behaviour
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ *                   pull up/down = disabled
+ *                   sleep mode = input
+ *
+ * PIN_CFG         - default config with alternate function
+ * PIN_CFG_PULL    - default config with alternate function and pull up/down
+ */
+
+typedef unsigned long pin_cfg_t;
+
+#define PIN_NUM_MASK            0x1ff
+#define PIN_NUM(x)              ((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT           9
+#define PIN_ALT_MASK            (0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x)              (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO                (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A               (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B               (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C               (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT          11
+#define PIN_PULL_MASK           (0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x)             (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE           (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP             (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN           (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT          13
+#define PIN_SLPM_MASK           (0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x)             (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_INPUT          (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE       (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+
+#define PIN_CFG_DEFAULT         (PIN_PULL_NONE | PIN_SLPM_INPUT)
+
+#define PIN_CFG(num, alt)               \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_PULL(num, alt, pull)    \
+        ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
+         (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
+
+extern int nmk_config_pin(pin_cfg_t cfg);
+extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
+
+#endif
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 08aaa4a7f65f..ea3ca86c5283 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -42,7 +42,6 @@ static struct clocksource nmdk_clksrc = {
         .rating         = 200,
         .read           = nmdk_read_timer_dummy,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -82,6 +81,12 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_UNUSED:
                 /* disable irq */
                 writel(0, mtu_base + MTU_IMSC);
+                /* disable timer */
+                cr = readl(mtu_base + MTU_CR(1));
+                cr &= ~MTU_CRn_ENA;
+                writel(cr, mtu_base + MTU_CR(1));
+                /* load some high default value */
+                writel(0xffffffff, mtu_base + MTU_LR(1));
                 break;
         case CLOCK_EVT_MODE_RESUME:
                 break;
@@ -98,7 +103,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
 static struct clock_event_device nmdk_clkevt = {
         .name           = "mtu_1",
         .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
         .rating         = 200,
         .set_mode       = nmdk_clkevt_mode,
         .set_next_event = nmdk_clkevt_next,
@@ -151,6 +155,7 @@ void __init nmdk_timer_init(void)
         } else {
                 cr |= MTU_CRn_PRESCALE_1;
         }
+        clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
 
         /* Timer 0 is the free running clocksource */
         writel(cr, mtu_base + MTU_CR(0));
@@ -158,7 +163,6 @@ void __init nmdk_timer_init(void)
         writel(0, mtu_base + MTU_BGLR(0));
         writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
 
-        nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
         /* Now the scheduling clock is ready */
         nmdk_clksrc.read = nmdk_read_timer;
 
@@ -175,8 +179,10 @@ void __init nmdk_timer_init(void)
         } else {
                 cr |= MTU_CRn_PRESCALE_1;
         }
+        clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
+
         writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
-        nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
+
         nmdk_clkevt.max_delta_ns =
                 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
         nmdk_clkevt.min_delta_ns =
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 219c01e82bc5..ebed82699eb2 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -22,6 +22,7 @@
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/omapfb.h>
 
 #include <mach/hardware.h>
 #include <asm/system.h>
@@ -35,6 +36,7 @@
 #include <plat/mux.h>
 #include <plat/fpga.h>
 #include <plat/serial.h>
+#include <plat/vram.h>
 
 #include <plat/clock.h>
 
@@ -81,6 +83,12 @@ const void *omap_get_var_config(u16 tag, size_t *len)
 }
 EXPORT_SYMBOL(omap_get_var_config);
 
+void __init omap_reserve(void)
+{
+        omapfb_reserve_sdram_memblock();
+        omap_vram_reserve_sdram_memblock();
+}
+
 /*
  * 32KHz clocksource ... always available, on pretty most chips except
  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index d3eea4f47533..0054b9501a53 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -26,7 +26,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/bootmem.h>
+#include <linux/memblock.h>
 #include <linux/io.h>
 #include <linux/omapfb.h>
 
@@ -171,49 +171,78 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
         return 0;
 }
 
+static int valid_sdram(unsigned long addr, unsigned long size)
+{
+        struct memblock_property res;
+
+        res.base = addr;
+        res.size = size;
+        return !memblock_find(&res) && res.base == addr && res.size == size;
+}
+
+static int reserve_sdram(unsigned long addr, unsigned long size)
+{
+        if (memblock_is_region_reserved(addr, size))
+                return -EBUSY;
+        if (memblock_reserve(addr, size))
+                return -ENOMEM;
+        return 0;
+}
+
 /*
  * Called from map_io. We need to call to this early enough so that we
  * can reserve the fixed SDRAM regions before VM could get hold of them.
  */
-void __init omapfb_reserve_sdram(void)
+void __init omapfb_reserve_sdram_memblock(void)
 {
-        struct bootmem_data     *bdata;
-        unsigned long           sdram_start, sdram_size;
-        unsigned long           reserved;
-        int                     i;
+        unsigned long reserved = 0;
+        int i;
 
         if (config_invalid)
                 return;
 
-        bdata = NODE_DATA(0)->bdata;
-        sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
-        sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
-        reserved = 0;
         for (i = 0; ; i++) {
-                struct omapfb_mem_region        rg;
+                struct omapfb_mem_region rg;
 
                 if (get_fbmem_region(i, &rg) < 0)
                         break;
+
                 if (i == OMAPFB_PLANE_NUM) {
-                        printk(KERN_ERR
-                                "Extraneous FB mem configuration entries\n");
+                        pr_err("Extraneous FB mem configuration entries\n");
                         config_invalid = 1;
                         return;
                 }
+
                 /* Check if it's our memory type. */
-                if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SDRAM,
-                                          sdram_start, sdram_size) < 0 ||
-                    (rg.type != OMAPFB_MEMTYPE_SDRAM))
+                if (rg.type != OMAPFB_MEMTYPE_SDRAM)
                         continue;
-                BUG_ON(omapfb_config.mem_desc.region[i].size);
-                if (check_fbmem_region(i, &rg, sdram_start, sdram_size) < 0) {
+
+                /* Check if the region falls within SDRAM */
+                if (rg.paddr && !valid_sdram(rg.paddr, rg.size))
+                        continue;
+
+                if (rg.size == 0) {
+                        pr_err("Zero size for FB region %d\n", i);
                         config_invalid = 1;
                         return;
                 }
+
                 if (rg.paddr) {
-                        reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT);
+                        if (reserve_sdram(rg.paddr, rg.size)) {
+                                pr_err("Trying to use reserved memory for FB region %d\n",
+                                        i);
+                                config_invalid = 1;
+                                return;
+                        }
                         reserved += rg.size;
                 }
+
+                if (omapfb_config.mem_desc.region[i].size) {
+                        pr_err("FB region %d already set\n", i);
+                        config_invalid = 1;
+                        return;
+                }
+
                 omapfb_config.mem_desc.region[i] = rg;
                 configured_regions++;
         }
@@ -359,7 +388,10 @@ static inline int omap_init_fb(void)
 
 arch_initcall(omap_init_fb);
 
-void omapfb_reserve_sdram(void) {}
+void omapfb_reserve_sdram_memblock(void)
+{
+}
+
 unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
                                   unsigned long sram_vstart,
                                   unsigned long sram_size,
@@ -375,7 +407,10 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data)
 {
 }
 
-void omapfb_reserve_sdram(void) {}
+void omapfb_reserve_sdram_memblock(void)
+{
+}
+
 unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
                                   unsigned long sram_vstart,
                                   unsigned long sram_size,
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index d265018f5e6b..5e4afbee0fd7 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -34,6 +34,8 @@ struct sys_timer;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 
+extern void omap_reserve(void);
+
 /*
  * IO bases for various OMAP processors
  * Except the tap base, rest all the io bases
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
index edd4987758a6..0aa4ecd12c7d 100644
--- a/arch/arm/plat-omap/include/plat/vram.h
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -38,7 +38,7 @@ extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
 extern void omap_vram_set_sdram_vram(u32 size, u32 start);
 extern void omap_vram_set_sram_vram(u32 size, u32 start);
 
-extern void omap_vram_reserve_sdram(void);
+extern void omap_vram_reserve_sdram_memblock(void);
 extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
                                             unsigned long sram_vstart,
                                             unsigned long sram_size,
@@ -48,7 +48,7 @@ extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
 static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
 static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
 
-static inline void omap_vram_reserve_sdram(void) { }
+static inline void omap_vram_reserve_sdram_memblock(void) { }
 static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
                                             unsigned long sram_vstart,
                                             unsigned long sram_size,
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 54c84a492a0f..779553a1595e 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <linux/delay.h>
 
 /*
  * PCIe unit register offsets.
@@ -46,6 +47,8 @@
 #define  PCIE_STAT_BUS_OFFS             8
 #define  PCIE_STAT_BUS_MASK             0xff
 #define  PCIE_STAT_LINK_DOWN            1
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET          (1<<20)
 
 
 u32 __init orion_pcie_dev_id(void __iomem *base)
@@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
         writel(stat, base + PCIE_STAT_OFF);
 }
 
+void __init orion_pcie_reset(void __iomem *base)
+{
+        u32 reg;
+        int i;
+
+        /*
+         * MV-S104860-U0, Rev. C:
+         * PCI Express Unit Soft Reset
+         * When set, generates an internal reset in the PCI Express unit.
+         * This bit should be cleared after the link is re-established.
+         */
+        reg = readl(base + PCIE_DEBUG_CTRL);
+        reg |= PCIE_DEBUG_SOFT_RESET;
+        writel(reg, base + PCIE_DEBUG_CTRL);
+
+        for (i = 0; i < 20; i++) {
+                mdelay(10);
+
+                if (orion_pcie_link_up(base))
+                        break;
+        }
+
+        reg &= ~(PCIE_DEBUG_SOFT_RESET);
+        writel(reg, base + PCIE_DEBUG_CTRL);
+}
+
 /*
  * Setup PCIE BARs and Address Decode Wins:
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -153,6 +182,11 @@ void __init orion_pcie_setup(void __iomem *base,
         u32 mask;
 
         /*
+         * soft reset PCIe unit
+         */
+        orion_pcie_reset(base);
+
+        /*
          * Point PCIe unit MBUS decode windows to DRAM space.
          */
         orion_pcie_setup_wins(base, dram);
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index 8474d05274bd..931d26d1a54b 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -43,7 +43,7 @@
 #include <plat/cpu.h>
 #include <plat/pll.h>
 
-/* initalise all the clocks */
+/* initialise all the clocks */
 
 void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
                                            unsigned long hclk,
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 8bf79f3efdfb..90a20512d68d 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -391,7 +391,7 @@ void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
                 (clkp->enable)(clkp, 0);
 }
 
-/* initalise all the clocks */
+/* initialise all the clocks */
 
 int __init s3c24xx_register_baseclocks(unsigned long xtal)
 {
diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
new file mode 100644
index 000000000000..3a70c125fe51
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/keypad.h
@@ -0,0 +1,43 @@
+/*
+ * Samsung Platform - Keypad platform data definitions
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_SAMSUNG_KEYPAD_H
+#define __PLAT_SAMSUNG_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+#define SAMSUNG_MAX_ROWS        8
+#define SAMSUNG_MAX_COLS        8
+
+/**
+ * struct samsung_keypad_platdata - Platform device data for Samsung Keypad.
+ * @keymap_data: pointer to &matrix_keymap_data.
+ * @rows: number of keypad row supported.
+ * @cols: number of keypad col supported.
+ * @no_autorepeat: disable key autorepeat.
+ * @wakeup: controls whether the device should be set up as wakeup source.
+ * @cfg_gpio: configure the GPIO.
+ *
+ * Initialisation data specific to either the machine or the platform
+ * for the device driver to use or call-back when configuring gpio.
+ */
+struct samsung_keypad_platdata {
+        const struct matrix_keymap_data *keymap_data;
+        unsigned int rows;
+        unsigned int cols;
+        bool no_autorepeat;
+        bool wakeup;
+
+        void (*cfg_gpio)(unsigned int rows, unsigned int cols);
+};
+
+#endif /* __PLAT_SAMSUNG_KEYPAD_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
index d2aab3adcdeb..555eec6dc1cb 100644
--- a/arch/arm/plat-spear/padmux.c
+++ b/arch/arm/plat-spear/padmux.c
@@ -66,7 +66,7 @@ static int pmx_mode_set(struct pmx_mode *mode)
  * If peripheral is not supported by current mode then request is rejected.
  * Conflicts between peripherals are not handled and peripherals will be
  * enabled in the order they are present in pmx_dev array.
- * In case of conflicts last peripheral enalbed will be present.
+ * In case of conflicts last peripheral enabled will be present.
  * Returns -ve on Err otherwise 0
  */
 static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index a1025d38f383..ab211652e4ca 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -58,6 +58,11 @@
 
 #define INT_STATUS              0x1
 
+/*
+ * Minimum clocksource/clockevent timer range in seconds
+ */
+#define SPEAR_MIN_RANGE 4
+
 static __iomem void *gpt_base;
 static struct clk *gpt_clk;
 
@@ -66,44 +71,6 @@ static void clockevent_set_mode(enum clock_event_mode mode,
 static int clockevent_next_event(unsigned long evt,
                                  struct clock_event_device *clk_event_dev);
 
-/*
- * Following clocksource_set_clock and clockevent_set_clock picked
- * from arch/mips/kernel/time.c
- */
-
-void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find a shift value */
-        for (shift = 32; shift > 0; shift--) {
-                temp = (u64) NSEC_PER_SEC << shift;
-                do_div(temp, clock);
-                if ((temp >> 32) == 0)
-                        break;
-        }
-        cs->shift = shift;
-        cs->mult = (u32) temp;
-}
-
-void __init clockevent_set_clock(struct clock_event_device *cd,
-        unsigned int clock)
-{
-        u64 temp;
-        u32 shift;
-
-        /* Find a shift value */
-        for (shift = 32; shift > 0; shift--) {
-                temp = (u64) clock << shift;
-                do_div(temp, NSEC_PER_SEC);
-                if ((temp >> 32) == 0)
-                        break;
-        }
-        cd->shift = shift;
-        cd->mult = (u32) temp;
-}
-
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
         return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
@@ -138,7 +105,7 @@ static void spear_clocksource_init(void)
         val |= CTRL_ENABLE ;
         writew(val, gpt_base + CR(CLKSRC));
 
-        clocksource_set_clock(&clksrc, tick_rate);
+        clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE);
 
         /* register the clocksource */
         clocksource_register(&clksrc);
@@ -233,7 +200,7 @@ static void __init spear_clockevent_init(void)
         tick_rate = clk_get_rate(gpt_clk);
         tick_rate >>= CTRL_PRESCALER16;
 
-        clockevent_set_clock(&clkevt, tick_rate);
+        clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
 
         clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
                         &clkevt);
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 9b1a66816aa6..5cf88e8427b1 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,3 +2,7 @@ obj-y	:= clock.o
 obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
 obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o
 obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o
+ifeq ($(CONFIG_LEDS_CLASS),y)
+obj-$(CONFIG_ARCH_REALVIEW) += leds.o
+obj-$(CONFIG_ARCH_VERSATILE) += leds.o
+endif
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
new file mode 100644
index 000000000000..3169fa555ea6
--- /dev/null
+++ b/arch/arm/plat-versatile/leds.c
@@ -0,0 +1,103 @@
+/*
+ * Driver for the 8 user LEDs found on the RealViews and Versatiles
+ * Based on DaVinci's DM365 board code
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Linus Walleij <triad@df.lth.se>
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#ifdef VERSATILE_SYS_BASE
+#define LEDREG  (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
+#endif
+
+#ifdef REALVIEW_SYS_BASE
+#define LEDREG  (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
+#endif
+
+struct versatile_led {
+        struct led_classdev     cdev;
+        u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+        const char *name;
+        const char *trigger;
+} versatile_leds[] = {
+        { "versatile:0", "heartbeat", },
+        { "versatile:1", "mmc0", },
+        { "versatile:2", },
+        { "versatile:3", },
+        { "versatile:4", },
+        { "versatile:5", },
+        { "versatile:6", },
+        { "versatile:7", },
+};
+
+static void versatile_led_set(struct led_classdev *cdev,
+                              enum led_brightness b)
+{
+        struct versatile_led *led = container_of(cdev,
+                                                 struct versatile_led, cdev);
+        u32 reg = readl(LEDREG);
+
+        if (b != LED_OFF)
+                reg |= led->mask;
+        else
+                reg &= ~led->mask;
+        writel(reg, LEDREG);
+}
+
+static enum led_brightness versatile_led_get(struct led_classdev *cdev)
+{
+        struct versatile_led *led = container_of(cdev,
+                                                 struct versatile_led, cdev);
+        u32 reg = readl(LEDREG);
+
+        return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init versatile_leds_init(void)
+{
+        int i;
+
+        /* All ON */
+        writel(0xff, LEDREG);
+        for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) {
+                struct versatile_led *led;
+
+                led = kzalloc(sizeof(*led), GFP_KERNEL);
+                if (!led)
+                        break;
+
+                led->cdev.name = versatile_leds[i].name;
+                led->cdev.brightness_set = versatile_led_set;
+                led->cdev.brightness_get = versatile_led_get;
+                led->cdev.default_trigger = versatile_leds[i].trigger;
+                led->mask = BIT(i);
+
+                if (led_classdev_register(NULL, &led->cdev) < 0) {
+                        kfree(led);
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(versatile_leds_init);
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 315a540c7ce5..8063a322c790 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -15,6 +15,7 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 
+#include <asm/cputype.h>
 #include <asm/thread_notify.h>
 #include <asm/vfp.h>
 
@@ -549,10 +550,13 @@ static int __init vfp_init(void)
                 /*
                  * Check for the presence of the Advanced SIMD
                  * load/store instructions, integer and single
-                 * precision floating point operations.
+                 * precision floating point operations. Only check
+                 * for NEON if the hardware has the MVFR registers.
                  */
-                if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
-                        elf_hwcap |= HWCAP_NEON;
+                if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
+                        if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
+                                elf_hwcap |= HWCAP_NEON;
+                }
 #endif
         }
         return 0;
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index f2b319333184..f51572772e21 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -45,9 +45,6 @@ config GENERIC_IRQ_PROBE
 config RWSEM_GENERIC_SPINLOCK
         def_bool y
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_CLOCKEVENTS
         def_bool y
 
diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
index ead8a75203a9..22fb66590dcd 100644
--- a/arch/avr32/Makefile
+++ b/arch/avr32/Makefile
@@ -13,7 +13,7 @@ KBUILD_DEFCONFIG	:= atstk1002_defconfig
 
 KBUILD_CFLAGS   += -pipe -fno-builtin -mno-pic
 KBUILD_AFLAGS   += -mrelax -mno-pic
-CFLAGS_MODULE   += -mno-relax
+KBUILD_CFLAGS_MODULE += -mno-relax
 LDFLAGS_vmlinux += --relax
 
 cpuflags-$(CONFIG_PLATFORM_AT32AP)      += -march=ap
diff --git a/arch/avr32/include/asm/local64.h b/arch/avr32/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/avr32/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index f66294b4f9d2..c88fd3584122 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -614,9 +614,6 @@ comment "Kernel Timer/Scheduler"
 
 source kernel/Kconfig.hz
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_CLOCKEVENTS
         bool "Generic clock events"
         default y
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 5a97a31d4bbd..9d5ffaf5492a 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -18,8 +18,8 @@ ifeq ($(CONFIG_ROMKERNEL),y)
 KBUILD_CFLAGS           += -mlong-calls
 endif
 KBUILD_AFLAGS           += $(call cc-option,-mno-fdpic)
-CFLAGS_MODULE    += -mlong-calls
-LDFLAGS_MODULE   += -m elf32bfin
+KBUILD_CFLAGS_MODULE    += -mlong-calls
+KBUILD_LDFLAGS_MODULE   += -m elf32bfin
 KALLSYMS         += --symbol-prefix=_
 
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
diff --git a/arch/blackfin/include/asm/local64.h b/arch/blackfin/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/blackfin/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index e25bf4440b51..887ef855be2a 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -20,9 +20,6 @@ config RWSEM_GENERIC_SPINLOCK
 config RWSEM_XCHGADD_ALGORITHM
         bool
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_CMOS_UPDATE
         def_bool y
 
diff --git a/arch/cris/arch-v32/mm/intmem.c b/arch/cris/arch-v32/mm/intmem.c
index 9e8b69cdf19e..1b17d92cef8e 100644
--- a/arch/cris/arch-v32/mm/intmem.c
+++ b/arch/cris/arch-v32/mm/intmem.c
@@ -33,8 +33,8 @@ static void crisv32_intmem_init(void)
 {
         static int initiated = 0;
         if (!initiated) {
-                struct intmem_allocation* alloc =
-                  (struct intmem_allocation*)kmalloc(sizeof *alloc, GFP_KERNEL);
+                struct intmem_allocation* alloc;
+                alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
                 INIT_LIST_HEAD(&intmem_allocations);
                 intmem_virtual = ioremap(MEM_INTMEM_START + RESERVED_SIZE,
                                          MEM_INTMEM_SIZE - RESERVED_SIZE);
@@ -62,9 +62,8 @@ void* crisv32_intmem_alloc(unsigned size, unsigned align)
                 if (allocation->status == STATUS_FREE &&
                     allocation->size >= size + alignment) {
                         if (allocation->size > size + alignment) {
-                                struct intmem_allocation* alloc =
-                                        (struct intmem_allocation*)
-                                        kmalloc(sizeof *alloc, GFP_ATOMIC);
+                                struct intmem_allocation* alloc;
+                                alloc = kmalloc(sizeof *alloc, GFP_ATOMIC);
                                 alloc->status = STATUS_FREE;
                                 alloc->size = allocation->size - size -
                                         alignment;
@@ -74,9 +73,7 @@ void* crisv32_intmem_alloc(unsigned size, unsigned align)
 
                                 if (alignment) {
                                         struct intmem_allocation *tmp;
-                                        tmp = (struct intmem_allocation *)
-                                                kmalloc(sizeof *tmp,
-                                                        GFP_ATOMIC);
+                                        tmp = kmalloc(sizeof *tmp, GFP_ATOMIC);
                                         tmp->offset = allocation->offset;
                                         tmp->size = alignment;
                                         tmp->status = STATUS_FREE;
diff --git a/arch/cris/include/asm/local64.h b/arch/cris/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/cris/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index 4b5830bcbe2e..16399bd24993 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -40,10 +40,6 @@ config GENERIC_HARDIRQS_NO__DO_IRQ
         bool
         default y
 
-config GENERIC_TIME
-        bool
-        default y
-
 config TIME_LOW_RES
         bool
         default y
diff --git a/arch/frv/Makefile b/arch/frv/Makefile
index 310c47a663f8..7ff84575b186 100644
--- a/arch/frv/Makefile
+++ b/arch/frv/Makefile
@@ -23,20 +23,14 @@
 # Copyright (C) 1994 by Hamish Macdonald
 #
 
-CCSPECS := $(shell $(CC) -v 2>&1 | grep "^Reading specs from " | head -1 | cut -c20-)
-CCDIR   := $(strip $(patsubst %/specs,%,$(CCSPECS)))
-CPUCLASS := fr400
-
-# test for cross compiling
-COMPILE_ARCH = $(shell uname -m)
-
 ifdef CONFIG_MMU
 UTS_SYSNAME = -DUTS_SYSNAME=\"Linux\"
 else
 UTS_SYSNAME = -DUTS_SYSNAME=\"uClinux\"
 endif
 
-ARCHMODFLAGS    += -G0 -mlong-calls
+KBUILD_AFLAGS_MODULE += -G0 -mlong-calls
+KBUILD_CFLAGS_MODULE += -G0 -mlong-calls
 
 ifdef CONFIG_GPREL_DATA_8
 KBUILD_CFLAGS   += -G8
@@ -54,7 +48,6 @@ endif
 
 ifdef CONFIG_GC_SECTIONS
 KBUILD_CFLAGS   += -ffunction-sections -fdata-sections
-LINKFLAGS       += --gc-sections
 endif
 
 ifndef CONFIG_FRAME_POINTER
@@ -64,16 +57,13 @@ endif
 ifdef CONFIG_CPU_FR451_COMPILE
 KBUILD_CFLAGS   += -mcpu=fr450
 KBUILD_AFLAGS   += -mcpu=fr450
-ASFLAGS         += -mcpu=fr450
 else
 ifdef CONFIG_CPU_FR551_COMPILE
 KBUILD_CFLAGS   += -mcpu=fr550
 KBUILD_AFLAGS   += -mcpu=fr550
-ASFLAGS         += -mcpu=fr550
 else
 KBUILD_CFLAGS   += -mcpu=fr400
 KBUILD_AFLAGS   += -mcpu=fr400
-ASFLAGS         += -mcpu=fr400
 endif
 endif
 
@@ -83,14 +73,12 @@ endif
 KBUILD_CFLAGS   += -mno-fdpic -mgpr-32 -msoft-float -mno-media
 KBUILD_CFLAGS   += -ffixed-fcc3 -ffixed-cc3 -ffixed-gr15 -ffixed-icc2
 KBUILD_AFLAGS   += -mno-fdpic
-ASFLAGS         += -mno-fdpic
 
 # make sure the .S files get compiled with debug info
 # and disable optimisations that are unhelpful whilst debugging
 ifdef CONFIG_DEBUG_INFO
 #KBUILD_CFLAGS  += -O1
 KBUILD_AFLAGS   += -Wa,--gdwarf2
-ASFLAGS         += -Wa,--gdwarf2
 endif
 
 head-y          := arch/frv/kernel/head.o arch/frv/kernel/init_task.o
@@ -105,11 +93,5 @@ all: Image
 Image: vmlinux
         $(Q)$(MAKE) $(build)=arch/frv/boot $@
 
-bootstrap:
-        $(Q)$(MAKEBOOT) bootstrap
-
 archclean:
         $(Q)$(MAKE) $(clean)=arch/frv/boot
-
-archdep: scripts/mkdep symlinks
-        $(Q)$(MAKE) $(build)=arch/frv/boot dep
diff --git a/arch/frv/include/asm/local64.h b/arch/frv/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/frv/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/frv/kernel/local64.h b/arch/frv/kernel/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/frv/kernel/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 53cc669e6d59..988b6ff34cc4 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -62,10 +62,6 @@ config GENERIC_CALIBRATE_DELAY
         bool
         default y
 
-config GENERIC_TIME
-        bool
-        default y
-
 config GENERIC_BUG
         bool
         depends on BUG
diff --git a/arch/h8300/include/asm/local64.h b/arch/h8300/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/h8300/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/h8300/kernel/timer/itu.c b/arch/h8300/kernel/timer/itu.c
index 4883ba7103a8..a2ae5e952137 100644
--- a/arch/h8300/kernel/timer/itu.c
+++ b/arch/h8300/kernel/timer/itu.c
@@ -73,7 +73,7 @@ void __init h8300_timer_setup(void)
 
         setup_irq(ITUIRQ, &itu_irq);
 
-        /* initalize timer */
+        /* initialize timer */
         ctrl_outb(0, TSTR);
         ctrl_outb(CCLR0 | div, ITUBASE + TCR);
         ctrl_outb(0x01, ITUBASE + TIER);
diff --git a/arch/h8300/kernel/timer/timer16.c b/arch/h8300/kernel/timer/timer16.c
index 042dbb53f3fb..ae0d38161139 100644
--- a/arch/h8300/kernel/timer/timer16.c
+++ b/arch/h8300/kernel/timer/timer16.c
@@ -68,7 +68,7 @@ void __init h8300_timer_setup(void)
 
         setup_irq(_16IRQ, &timer16_irq);
 
-        /* initalize timer */
+        /* initialize timer */
         ctrl_outb(0, TSTR);
         ctrl_outb(CCLR0 | div, _16BASE + TCR);
         ctrl_outw(cnt, _16BASE + GRA);
diff --git a/arch/h8300/kernel/timer/timer8.c b/arch/h8300/kernel/timer/timer8.c
index 38be0cabef0d..3946c0fa8374 100644
--- a/arch/h8300/kernel/timer/timer8.c
+++ b/arch/h8300/kernel/timer/timer8.c
@@ -94,7 +94,7 @@ void __init h8300_timer_setup(void)
         ctrl_bclr(0, MSTPCRL)
 #endif
 
-        /* initalize timer */
+        /* initialize timer */
         ctrl_outw(cnt, _8BASE + TCORA);
         ctrl_outw(0x0000, _8BASE + _8TCSR);
         ctrl_outw((CMIEA|CCLR_CMA|CKS2) << 8 | div,
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 95610820041e..8711d13cd79f 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -82,10 +82,6 @@ config GENERIC_CALIBRATE_DELAY
         bool
         default y
 
-config GENERIC_TIME
-        bool
-        default y
-
 config GENERIC_TIME_VSYSCALL
         bool
         default y
diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile
index 8ae0d2604ce1..be7bfa12b705 100644
--- a/arch/ia64/Makefile
+++ b/arch/ia64/Makefile
@@ -22,13 +22,13 @@ CHECKFLAGS	+= -m64 -D__ia64=1 -D__ia64__=1 -D_LP64 -D__LP64__
 
 OBJCOPYFLAGS    := --strip-all
 LDFLAGS_vmlinux := -static
-LDFLAGS_MODULE  += -T $(srctree)/arch/ia64/module.lds
-AFLAGS_KERNEL   := -mconstant-gp
+KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/ia64/module.lds
+KBUILD_AFLAGS_KERNEL := -mconstant-gp
 EXTRA           :=
 
 cflags-y        := -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f12-f15,f32-f127 \
                    -falign-functions=32 -frename-registers -fno-optimize-sibling-calls
-CFLAGS_KERNEL   := -mconstant-gp
+KBUILD_CFLAGS_KERNEL := -mconstant-gp
 
 GAS_STATUS      = $(shell $(srctree)/arch/ia64/scripts/check-gas "$(CC)" "$(OBJDUMP)")
 KBUILD_CPPFLAGS += $(shell $(srctree)/arch/ia64/scripts/toolchain-flags "$(CC)" "$(OBJDUMP)" "$(READELF)")
diff --git a/arch/ia64/configs/bigsur_defconfig b/arch/ia64/configs/bigsur_defconfig
index 312b12094a1d..c5fe20553dad 100644
--- a/arch/ia64/configs/bigsur_defconfig
+++ b/arch/ia64/configs/bigsur_defconfig
@@ -1,1358 +1,118 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.16-rc5
-# Mon Feb 27 16:10:42 2006
-#
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-# CONFIG_CPUSETS is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-CONFIG_SLUB=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_DMA_IS_DMA32=y
-# CONFIG_IA64_GENERIC is not set
-CONFIG_IA64_DIG=y
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-CONFIG_ITANIUM=y
-# CONFIG_MCKINLEY is not set
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_BRL_EMU=y
-CONFIG_IA64_L1_CACHE_SHIFT=6
-# CONFIG_IA64_CYCLONE is not set
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-# CONFIG_HOTPLUG_CPU is not set
-# CONFIG_SCHED_SMT is not set
-CONFIG_PREEMPT=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-# CONFIG_VIRTUAL_MEM_MAP is not set
-# CONFIG_IA64_MCA_RECOVERY is not set
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
 CONFIG_ACPI_BUTTON=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-# CONFIG_ACPI_CONTAINER is not set
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY_PROC=y
-# CONFIG_PCI_DEBUG is not set
-
-#
-# PCI Hotplug Support
-#
-# CONFIG_HOTPLUG_PCI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
+CONFIG_AUTOFS4_FS=m
+CONFIG_AUTOFS_FS=m
+CONFIG_BINFMT_MISC=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=m
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=m
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_SHARE_IRQ=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=m
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-CONFIG_IDEDMA_PCI_AUTO=y
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-# CONFIG_BLK_DEV_CMD64X is not set
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=m
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=m
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-CONFIG_IDEDMA_AUTO=y
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=m
 CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-
-#
-# SCSI Transport Attributes
-#
-CONFIG_SCSI_SPI_ATTRS=m
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_FC is not set
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
+CONFIG_CIFS=m
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_STATS=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_ZERO=m
-# CONFIG_DM_MULTIPATH is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-
-#
-# Tulip family network device support
-#
-# CONFIG_NET_TULIP is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-CONFIG_EEPRO100=y
-# CONFIG_E100 is not set
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_ACPI=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
 CONFIG_DRM=m
-# CONFIG_DRM_TDFX is not set
 CONFIG_DRM_R128=m
-# CONFIG_DRM_RADEON is not set
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_SIS is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HPET is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_I810 is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PROSAVAGE is not set
-# CONFIG_I2C_SAVAGE4 is not set
-# CONFIG_SCx200_ACB is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-# CONFIG_I2C_VOODOO3 is not set
-# CONFIG_I2C_PCA_ISA is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-# CONFIG_SND_SEQ_DUMMY is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_SEQUENCER_OSS is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_AC97_BUS=m
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-CONFIG_SND_CS4281=m
-# CONFIG_SND_CS46XX is not set
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-# CONFIG_SND_FM801 is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_OHCI_HCD is not set
-CONFIG_USB_UHCI_HCD=m
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-CONFIG_USB_HIDINPUT=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_USB_MON=y
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS)
-#
-
-#
-# File systems
-#
+CONFIG_DUMMY=y
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_EXPORT=y
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_SECURITY=y
-CONFIG_XFS_POSIX_ACL=y
-# CONFIG_XFS_RT is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C=y
+CONFIG_IA64_DIG=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE=m
+CONFIG_INET=y
 CONFIG_INOTIFY=y
-# CONFIG_QUOTA is not set
-CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_INPUT_EVDEV=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MII=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-# CONFIG_CIFS_STATS2 is not set
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
 CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=m
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-
-#
-# Instrumentation Support
-#
-CONFIG_PROFILING=y
+CONFIG_NR_CPUS=2
 CONFIG_OPROFILE=y
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_VM is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_IA64_GRANULE_16MB is not set
-CONFIG_IA64_GRANULE_64MB=y
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PREEMPT=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROFILING=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SGI_PARTITION=y
+CONFIG_SMP=y
+CONFIG_SND_CS4281=m
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SOUND=m
+CONFIG_SYSVIPC=y
+CONFIG_TMPFS=y
+CONFIG_UDF_FS=m
+CONFIG_UNIX=y
+CONFIG_USB_ACM=m
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=m
+CONFIG_USB_MON=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_VFAT_FS=y
+# CONFIG_VIRTUAL_MEM_MAP is not set
+CONFIG_XFS_FS=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_QUOTA=y
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig
index 6a4cc506fb5f..01ba5305e98c 100644
--- a/arch/ia64/configs/generic_defconfig
+++ b/arch/ia64/configs/generic_defconfig
@@ -1,1455 +1,133 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc7
-# Mon Dec  8 08:12:07 2008
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=20
-CONFIG_CGROUPS=y
-# CONFIG_CGROUP_DEBUG is not set
-# CONFIG_CGROUP_NS is not set
-# CONFIG_CGROUP_FREEZER is not set
-# CONFIG_CGROUP_DEVICE is not set
-CONFIG_CPUSETS=y
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUP_CPUACCT is not set
-# CONFIG_RESOURCE_COUNTERS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_PROC_PID_CPUSET=y
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_PCI_QUIRKS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-CONFIG_BLOCK_COMPAT=y
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_FREEZER is not set
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_IA64_UNCACHED_ALLOCATOR=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_PARAVIRT_GUEST is not set
-CONFIG_IA64_GENERIC=y
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_DIG_VTD is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_SGI_UV is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_IA64_XEN_GUEST is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-# CONFIG_IA64_PAGE_SIZE_16KB is not set
-CONFIG_IA64_PAGE_SIZE_64KB=y
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-# CONFIG_SCHED_HRTICK is not set
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
-CONFIG_SMP=y
-CONFIG_NR_CPUS=4096
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-# CONFIG_SCHED_SMT is not set
-# CONFIG_PERMIT_BSP_REMOVE is not set
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-CONFIG_DISCONTIGMEM_MANUAL=y
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_DISCONTIGMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_NEED_MULTIPLE_NODES=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MIGRATION=y
-CONFIG_RESOURCES_64BIT=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_NR_QUICK=1
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
-CONFIG_NUMA=y
-CONFIG_NODES_SHIFT=10
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
-CONFIG_HAVE_ARCH_NODEDATA_EXTENSION=y
-CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_MC_ERR_INJECT is not set
-CONFIG_SGI_SN=y
-# CONFIG_IA64_ESI is not set
-# CONFIG_IA64_HP_AML_NFW is not set
-
-#
-# SN Devices
-#
-CONFIG_SGI_IOC3=m
-CONFIG_KEXEC=y
-CONFIG_CRASH_DUMP=y
-
-#
-# Firmware Drivers
-#
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_DMIID=y
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_HAVE_AOUT is not set
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_PROCFS=y
-CONFIG_ACPI_PROCFS_POWER=y
-CONFIG_ACPI_SYSFS_POWER=y
-CONFIG_ACPI_PROC_EVENT=y
 CONFIG_ACPI_BUTTON=m
-CONFIG_ACPI_FAN=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_NUMA=y
-# CONFIG_ACPI_CUSTOM_DSDT is not set
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_SYSCALL=y
-# CONFIG_PCIEPORTBUS is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-# CONFIG_HOTPLUG_PCI_SGI is not set
-# CONFIG_PCCARD is not set
-CONFIG_DMAR=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_AGP_HP_ZX1=m
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
+CONFIG_AGP_SGI_TIOCA=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_LRO=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_OLD_REGULATORY=y
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_ATA_PIIX=y
+CONFIG_ATA=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_AUTOFS_FS=m
+CONFIG_BINFMT_MISC=m
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_BLK_DEV_HD is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_SGI_IOC4=y
-# CONFIG_TIFM_CORE is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_SGI_XP=m
-# CONFIG_HP_ILO is not set
-# CONFIG_C2PORT is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=y
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-CONFIG_IDE_TIMINGS=y
-CONFIG_IDE_ATAPI=y
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_IDE_GD=y
-CONFIG_IDE_GD_ATA=y
-# CONFIG_IDE_GD_ATAPI is not set
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDESCSI=m
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEDMA_SFF=y
-
-#
-# PCI IDE chipsets support
-#
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-CONFIG_BLK_DEV_SGIIOC4=y
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-CONFIG_BLK_DEV_IDEDMA=y
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SGIIOC4=y
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CGROUPS=y
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-CONFIG_SCSI_SAS_ATTRS=y
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_MVSAS is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-# CONFIG_SCSI_IPR is not set
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-# CONFIG_SCSI_DH is not set
-CONFIG_ATA=y
-CONFIG_ATA_NONSTANDARD=y
-CONFIG_ATA_ACPI=y
-CONFIG_SATA_PMP=y
-# CONFIG_SATA_AHCI is not set
-# CONFIG_SATA_SIL24 is not set
-CONFIG_ATA_SFF=y
-# CONFIG_SATA_SVW is not set
-CONFIG_ATA_PIIX=y
-# CONFIG_SATA_MV is not set
-# CONFIG_SATA_NV is not set
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
-# CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SX4 is not set
-# CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIS is not set
-# CONFIG_SATA_ULI is not set
-# CONFIG_SATA_VIA is not set
-CONFIG_SATA_VITESSE=y
-# CONFIG_SATA_INIC162X is not set
-# CONFIG_PATA_ACPI is not set
-# CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
-# CONFIG_PATA_ARTOP is not set
-# CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_CMD640_PCI is not set
-# CONFIG_PATA_CMD64X is not set
-# CONFIG_PATA_CS5520 is not set
-# CONFIG_PATA_CS5530 is not set
-# CONFIG_PATA_CYPRESS is not set
-# CONFIG_PATA_EFAR is not set
-# CONFIG_ATA_GENERIC is not set
-# CONFIG_PATA_HPT366 is not set
-# CONFIG_PATA_HPT37X is not set
-# CONFIG_PATA_HPT3X2N is not set
-# CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IT821X is not set
-# CONFIG_PATA_IT8213 is not set
-# CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_TRIFLEX is not set
-# CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
-# CONFIG_PATA_NETCELL is not set
-# CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87410 is not set
-# CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OPTI is not set
-# CONFIG_PATA_OPTIDMA is not set
-# CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RZ1000 is not set
-# CONFIG_PATA_SC1200 is not set
-# CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_PDC2027X is not set
-# CONFIG_PATA_SIL680 is not set
-# CONFIG_PATA_SIS is not set
-# CONFIG_PATA_VIA is not set
-# CONFIG_PATA_WINBOND is not set
-# CONFIG_PATA_SCH is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-# CONFIG_MD_RAID456 is not set
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+CONFIG_CONNECTOR=y
+CONFIG_CPUSETS=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-# CONFIG_DM_DELAY is not set
-# CONFIG_DM_UEVENT is not set
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=y
-CONFIG_FUSION_MAX_SGE=128
-# CONFIG_FUSION_CTL is not set
-# CONFIG_FUSION_LOGGING is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# Enable only one of the two stacks, unless you know what you are doing
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_IEEE1394 is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_SB1000 is not set
-# CONFIG_ARCNET is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-CONFIG_EEPRO100=m
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_R6040 is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-# CONFIG_ATL2 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000E is not set
-# CONFIG_IP1000 is not set
-CONFIG_IGB=y
-# CONFIG_IGB_LRO is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-# CONFIG_ATL1E is not set
-# CONFIG_JME is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_ENIC is not set
-# CONFIG_IXGBE is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_NIU is not set
-# CONFIG_MLX4_EN is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TEHUTI is not set
-# CONFIG_BNX2X is not set
-# CONFIG_QLGE is not set
-# CONFIG_SFC is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-CONFIG_NETCONSOLE=y
-# CONFIG_NETCONSOLE_DYNAMIC is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_RISCOM8 is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
-# CONFIG_STALDRV is not set
-# CONFIG_NOZOMI is not set
-CONFIG_SGI_SNSC=y
-CONFIG_SGI_TIOCX=y
-CONFIG_SGI_MBCS=m
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_SGI_L1_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_SERIAL_SGI_IOC4=y
-# CONFIG_SERIAL_SGI_IOC3 is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_MMTIMER=y
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_I5K_AMB is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-CONFIG_THERMAL=m
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
-CONFIG_AGP_HP_ZX1=m
-CONFIG_AGP_SGI_TIOCA=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_ZERO=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-# CONFIG_SND_AC97_POWER_SAVE is not set
-CONFIG_SND_PCI=y
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AW2 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-# CONFIG_SND_OXYGEN is not set
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-# CONFIG_SND_DARLA20 is not set
-# CONFIG_SND_GINA20 is not set
-# CONFIG_SND_LAYLA20 is not set
-# CONFIG_SND_DARLA24 is not set
-# CONFIG_SND_GINA24 is not set
-# CONFIG_SND_LAYLA24 is not set
-# CONFIG_SND_MONA is not set
-# CONFIG_SND_MIA is not set
-# CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_INDIGO is not set
-# CONFIG_SND_INDIGOIO is not set
-# CONFIG_SND_INDIGODJ is not set
-CONFIG_SND_EMU10K1=m
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=m
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_HIFIER is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RIPTIDE is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VIRTUOSO is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-# CONFIG_SND_SOC is not set
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BRIGHT=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DELL=m
-CONFIG_HID_EZKEY=m
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_SAS=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
 CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
 CONFIG_HID_PANTHERLORD=m
-# CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=m
 CONFIG_HID_SAMSUNG=m
 CONFIG_HID_SONY=m
 CONFIG_HID_SUNPLUS=m
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=m
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_WHCI_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-
-#
-# Enable Host or Gadget support to see Inventra options
-#
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-# CONFIG_UWB is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PAGE_SIZE_64KB=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE=y
+CONFIG_IGB=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_INET=y
+CONFIG_INFINIBAND_IPOIB=m
 CONFIG_INFINIBAND=m
-# CONFIG_INFINIBAND_USER_MAD is not set
-# CONFIG_INFINIBAND_USER_ACCESS is not set
-CONFIG_INFINIBAND_ADDR_TRANS=y
 CONFIG_INFINIBAND_MTHCA=m
-CONFIG_INFINIBAND_MTHCA_DEBUG=y
-# CONFIG_INFINIBAND_IPATH is not set
-# CONFIG_INFINIBAND_AMSO1100 is not set
-# CONFIG_MLX4_INFINIBAND is not set
-# CONFIG_INFINIBAND_NES is not set
-CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_CM is not set
-CONFIG_INFINIBAND_IPOIB_DEBUG=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
-# CONFIG_INFINIBAND_SRP is not set
-# CONFIG_INFINIBAND_ISER is not set
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-CONFIG_STAGING_EXCLUDE_BUILD=y
-
-#
-# HP Simulator drivers
-#
-# CONFIG_HP_SIMETH is not set
-# CONFIG_HP_SIMSERIAL is not set
-# CONFIG_HP_SIMSCSI is not set
-CONFIG_MSPEC=m
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
-CONFIG_XFS_FS=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_DEBUG is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KEXEC=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MSPEC=m
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_XPRT_RDMA=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1465,15 +143,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1481,194 +158,79 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=2048
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SATA_VITESSE=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_SGI_IOC4=y
+CONFIG_SERIAL_SGI_L1_CONSOLE=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_IOC4=y
+CONFIG_SGI_MBCS=m
+CONFIG_SGI_PARTITION=y
+CONFIG_SGI_SNSC=y
+CONFIG_SGI_TIOCX=y
+CONFIG_SGI_XP=m
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_DUMMY=m
+CONFIG_SND_EMU10K1=m
+CONFIG_SND_FM801=m
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_VIRMIDI=m
+CONFIG_SOUND=m
+CONFIG_SYN_COOKIES=y
 CONFIG_SYSCTL_SYSCALL_CHECK=y
-
-#
-# Tracers
-#
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_CRYPTO_DEV_HIFN_795X is not set
-CONFIG_HAVE_KVM=y
-CONFIG_VIRTUALIZATION=y
-# CONFIG_KVM is not set
-# CONFIG_VIRTIO_PCI is not set
-# CONFIG_VIRTIO_BALLOON is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB=m
+CONFIG_USB_MON=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/gensparse_defconfig b/arch/ia64/configs/gensparse_defconfig
index 2dc185b0f9a3..18989a084143 100644
--- a/arch/ia64/configs/gensparse_defconfig
+++ b/arch/ia64/configs/gensparse_defconfig
@@ -1,1267 +1,110 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.16-rc5
-# Thu Mar  2 16:39:10 2006
-#
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_CPUSETS is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-CONFIG_SLUB=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_DMA_IS_DMA32=y
-CONFIG_IA64_GENERIC=y
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-# CONFIG_IA64_SGI_SN_XP is not set
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=512
-CONFIG_IA64_NR_NODES=256
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_SCHED_SMT is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_NEED_MULTIPLE_NODES=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPARSEMEM_EXTREME=y
-# CONFIG_MEMORY_HOTPLUG is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MIGRATION=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
-CONFIG_NUMA=y
-CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-CONFIG_SGI_SN=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
 CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY_PROC=y
-# CONFIG_PCI_DEBUG is not set
-
-#
-# PCI Hotplug Support
-#
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-# CONFIG_HOTPLUG_PCI_SGI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_AGP_HP_ZX1=m
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
+CONFIG_AGP_SGI_TIOCA=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=y
-CONFIG_BLK_DEV_IDESCSI=m
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=y
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-CONFIG_IDEDMA_PCI_AUTO=y
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-CONFIG_BLK_DEV_SGIIOC4=y
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-CONFIG_IDEDMA_AUTO=y
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SGIIOC4=y
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-CONFIG_SCSI_SATA=y
-# CONFIG_SCSI_SATA_AHCI is not set
-# CONFIG_SCSI_SATA_SVW is not set
-# CONFIG_SCSI_ATA_PIIX is not set
-# CONFIG_SCSI_SATA_MV is not set
-# CONFIG_SCSI_SATA_NV is not set
-# CONFIG_SCSI_PDC_ADMA is not set
-# CONFIG_SCSI_SATA_QSTOR is not set
-# CONFIG_SCSI_SATA_PROMISE is not set
-# CONFIG_SCSI_SATA_SX4 is not set
-# CONFIG_SCSI_SATA_SIL is not set
-# CONFIG_SCSI_SATA_SIL24 is not set
-# CONFIG_SCSI_SATA_SIS is not set
-# CONFIG_SCSI_SATA_ULI is not set
-# CONFIG_SCSI_SATA_VIA is not set
-CONFIG_SCSI_SATA_VITESSE=y
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_FC is not set
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-# CONFIG_DM_MULTIPATH_EMC is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=m
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-# CONFIG_FUSION_CTL is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-
-#
-# Tulip family network device support
-#
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-CONFIG_EEPRO100=m
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000_NAPI is not set
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-CONFIG_NETCONSOLE=y
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_STALDRV is not set
-CONFIG_SGI_SNSC=y
-CONFIG_SGI_TIOCX=y
-CONFIG_SGI_MBCS=m
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_ACPI=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_SGI_L1_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_SERIAL_SGI_IOC4=y
-CONFIG_SERIAL_SGI_IOC3=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
-CONFIG_AGP_HP_ZX1=m
-CONFIG_AGP_SGI_TIOCA=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_ZERO=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-# CONFIG_HPET_RTC_IRQ is not set
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_MMTIMER=y
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PRINTK=y
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_AC97_BUS=m
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-
-#
-# PCI devices
-#
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_EMU10K1=m
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=m
-# CONFIG_SND_FM801_TEA575X is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=m
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-CONFIG_USB_HIDINPUT=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_USB_MON=y
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# InfiniBand support
-#
-CONFIG_INFINIBAND=m
-# CONFIG_INFINIBAND_USER_MAD is not set
-# CONFIG_INFINIBAND_USER_ACCESS is not set
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-# CONFIG_INFINIBAND_SRP is not set
-
-#
-# SN Devices
-#
-CONFIG_SGI_IOC4=y
-CONFIG_SGI_IOC3=y
-
-#
-# EDAC - error detection and reporting (RAS)
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_SECURITY is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE_GENERIC=y
+CONFIG_IDE=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_INET=y
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_MTHCA=m
 CONFIG_INOTIFY=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_KALLSYMS_ALL=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFS_DIRECTIO=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1277,15 +120,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1293,100 +135,77 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-
-#
-# HP Simulator drivers
-#
-# CONFIG_HP_SIMETH is not set
-# CONFIG_HP_SIMSERIAL is not set
-# CONFIG_HP_SIMSCSI is not set
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=20
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_VM is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_NR_CPUS=512
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_SGI_IOC3=y
+CONFIG_SERIAL_SGI_IOC4=y
+CONFIG_SERIAL_SGI_L1_CONSOLE=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_IOC3=y
+CONFIG_SGI_IOC4=y
+CONFIG_SGI_MBCS=m
+CONFIG_SGI_PARTITION=y
+CONFIG_SGI_SNSC=y
+CONFIG_SGI_TIOCX=y
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_DUMMY=m
+CONFIG_SND_EMU10K1=m
+CONFIG_SND_FM801=m
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_VIRMIDI=m
+CONFIG_SOUND=m
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB=m
+CONFIG_USB_MON=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/sim_defconfig b/arch/ia64/configs/sim_defconfig
index 21a23cdfd41c..585222b368c3 100644
--- a/arch/ia64/configs/sim_defconfig
+++ b/arch/ia64/configs/sim_defconfig
@@ -1,723 +1,57 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.16-rc5
-# Mon Feb 27 16:13:41 2006
-#
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_CPUSETS is not set
-CONFIG_INITRAMFS_SOURCE=""
+CONFIG_BINFMT_MISC=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-CONFIG_SLUB=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_OBSOLETE_MODPARM=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_DMA_IS_DMA32=y
-# CONFIG_IA64_GENERIC is not set
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXT2_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_HP_SIMETH=y
+CONFIG_HP_SIMSCSI=y
+CONFIG_HP_SIMSERIAL_CONSOLE=y
+CONFIG_HP_SIMSERIAL=y
+CONFIG_HUGETLBFS=y
 CONFIG_IA64_HP_SIM=y
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-# CONFIG_IA64_PAGE_SIZE_16KB is not set
 CONFIG_IA64_PAGE_SIZE_64KB=y
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-# CONFIG_IA64_CYCLONE is not set
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=64
-# CONFIG_HOTPLUG_CPU is not set
-# CONFIG_SCHED_SMT is not set
-CONFIG_PREEMPT=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-# CONFIG_VIRTUAL_MEM_MAP is not set
-# CONFIG_IA64_MCA_RECOVERY is not set
-# CONFIG_PERFMON is not set
 CONFIG_IA64_PALINFO=m
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management and ACPI
-#
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_UNIX is not set
-# CONFIG_NET_KEY is not set
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
 CONFIG_INET=y
+CONFIG_INOTIFY=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
 CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
 # CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_MCKINLEY=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NET=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD=y
+CONFIG_NFS_FS=y
+CONFIG_NR_CPUS=64
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PREEMPT=y
+CONFIG_PROC_KCORE=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
-
-#
-# SCSI Transport Attributes
-#
+CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_SPI_ATTRS=y
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
-# CONFIG_NETDEVICES is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
+CONFIG_SCSI=y
 # CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_AGP is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
+CONFIG_SMP=y
+# CONFIG_STANDALONE is not set
+CONFIG_SYSVIPC=y
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS)
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_NFS_DIRECTIO=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-
-#
-# HP Simulator drivers
-#
-CONFIG_HP_SIMETH=y
-CONFIG_HP_SIMSERIAL=y
-CONFIG_HP_SIMSERIAL_CONSOLE=y
-CONFIG_HP_SIMSCSI=y
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_MAGIC_SYSRQ is not set
-CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_VM is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_IA64_GRANULE_16MB is not set
-CONFIG_IA64_GRANULE_64MB=y
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Hardware crypto devices
-#
diff --git a/arch/ia64/configs/tiger_defconfig b/arch/ia64/configs/tiger_defconfig
index c5a5ea9d54ae..498618ea00ea 100644
--- a/arch/ia64/configs/tiger_defconfig
+++ b/arch/ia64/configs/tiger_defconfig
@@ -1,1134 +1,113 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22
-# Thu Jul 19 13:54:47 2007
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=20
-# CONFIG_CPUSETS is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_IA64_GENERIC is not set
-CONFIG_IA64_DIG=y
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-# CONFIG_IA64_PAGE_SIZE_16KB is not set
-CONFIG_IA64_PAGE_SIZE_64KB=y
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-# CONFIG_SCHED_SMT is not set
-CONFIG_PERMIT_BSP_REMOVE=y
-CONFIG_FORCE_CPEI_RETARGET=y
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_NR_QUICK=1
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_MC_ERR_INJECT is not set
-# CONFIG_IA64_ESI is not set
-CONFIG_KEXEC=y
-# CONFIG_CRASH_DUMP is not set
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_DMIID=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=m
-
-# CONFIG_DMAR is not set
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
-CONFIG_ACPI_PROCFS=y
 CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_FAN=m
-# CONFIG_ACPI_DOCK is not set
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_SYSCALL=y
-# CONFIG_PCIEPORTBUS is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCI_MSI is not set
-# CONFIG_PCI_DEBUG is not set
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=m
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=y
-CONFIG_BLK_DEV_IDESCSI=m
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-# CONFIG_MD_RAID456 is not set
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_ZERO=m
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=y
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_IEEE1394 is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-# CONFIG_ARCNET is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-CONFIG_EEPRO100=m
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000_NAPI is not set
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-CONFIG_NETCONSOLE=y
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_MOXA_SMARTIO_NEW is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
-# CONFIG_STALDRV is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-# CONFIG_HPET_RTC_IRQ is not set
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_SM501 is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_PERSIST is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_MON is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Userspace I/O
-#
-# CONFIG_UIO is not set
-# CONFIG_MSPEC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_SECURITY is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_FORCE_CPEI_RETARGET=y
+CONFIG_FUSION_CTL=y
+CONFIG_FUSION_FC=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_DIG=y
+CONFIG_IA64_GRANULE_16MB=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PAGE_SIZE_64KB=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_INET=y
 CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KEXEC=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFS_DIRECTIO=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-# CONFIG_SUNRPC_BIND34 is not set
-CONFIG_RPCSEC_GSS_KRB5=y
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1144,15 +123,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1160,120 +138,50 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-
-#
-# Distributed Lock Manager
-#
-# CONFIG_DLM is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_HW=y
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_PERMIT_BSP_REMOVE=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_PARTITION=y
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB=y
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/xen_domu_defconfig b/arch/ia64/configs/xen_domu_defconfig
index c67eafc4bb38..5f6d284723a4 100644
--- a/arch/ia64/configs/xen_domu_defconfig
+++ b/arch/ia64/configs/xen_domu_defconfig
@@ -1,1374 +1,121 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc1
-# Fri Jan 16 11:49:59 2009
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=20
-CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
-# CONFIG_GROUP_SCHED is not set
-
-#
-# Control Group support
-#
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_STRIP_GENERATED=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_PCI_QUIRKS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-CONFIG_FREEZER=y
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-CONFIG_AUDIT_ARCH=y
-CONFIG_PARAVIRT_GUEST=y
-CONFIG_PARAVIRT=y
-CONFIG_XEN=y
-CONFIG_XEN_XENCOMM=y
-CONFIG_NO_IDLE_HZ=y
-# CONFIG_IA64_GENERIC is not set
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_DIG_VTD is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_SGI_UV is not set
-# CONFIG_IA64_HP_SIM is not set
-CONFIG_IA64_XEN_GUEST=y
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-# CONFIG_SCHED_HRTICK is not set
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-# CONFIG_SCHED_SMT is not set
-CONFIG_PERMIT_BSP_REMOVE=y
-CONFIG_FORCE_CPEI_RETARGET=y
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MIGRATION=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_NR_QUICK=1
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_MC_ERR_INJECT is not set
-# CONFIG_IA64_ESI is not set
-# CONFIG_IA64_HP_AML_NFW is not set
-CONFIG_KEXEC=y
-# CONFIG_CRASH_DUMP is not set
-
-#
-# Firmware Drivers
-#
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_DMIID=y
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_HAVE_AOUT is not set
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_ACPI=y
-CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_PROCFS=y
-CONFIG_ACPI_PROCFS_POWER=y
-CONFIG_ACPI_SYSFS_POWER=y
-CONFIG_ACPI_PROC_EVENT=y
 CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_FAN=m
-# CONFIG_ACPI_DOCK is not set
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-# CONFIG_ACPI_CUSTOM_DSDT is not set
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_SYSCALL=y
-# CONFIG_PCIEPORTBUS is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
-# CONFIG_PCI_DEBUG is not set
-# CONFIG_PCI_STUB is not set
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-# CONFIG_PCCARD is not set
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NET_NS is not set
-CONFIG_COMPAT_NET_DEV_OPS=y
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_AGP=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_PNP=y
-CONFIG_PNP_DEBUG_MESSAGES=y
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=m
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_XEN_BLKDEV_FRONTEND=y
-# CONFIG_BLK_DEV_HD is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HP_ILO is not set
-# CONFIG_C2PORT is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=y
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-CONFIG_IDE_TIMINGS=y
-CONFIG_IDE_ATAPI=y
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_IDE_GD=y
-CONFIG_IDE_GD_ATA=y
-# CONFIG_IDE_GD_ATAPI is not set
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEDMA_SFF=y
-
-#
-# PCI IDE chipsets support
-#
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8172 is not set
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-CONFIG_BLK_DEV_IDEDMA=y
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_CXGB3_ISCSI is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_FCOE is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_MVSAS is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-# CONFIG_MD_RAID456 is not set
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_ZERO=m
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-# CONFIG_DM_UEVENT is not set
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=y
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=y
-# CONFIG_FUSION_LOGGING is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# Enable only one of the two stacks, unless you know what you are doing
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_IEEE1394 is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_SB1000 is not set
-# CONFIG_ARCNET is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_R6040 is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SMSC9420 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-# CONFIG_ATL2 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000E is not set
-# CONFIG_IP1000 is not set
-# CONFIG_IGB is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-# CONFIG_ATL1E is not set
-# CONFIG_JME is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3_DEPENDS=y
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_ENIC is not set
-# CONFIG_IXGBE is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_NIU is not set
-# CONFIG_MLX4_EN is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TEHUTI is not set
-# CONFIG_BNX2X is not set
-# CONFIG_QLGE is not set
-# CONFIG_SFC is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-CONFIG_XEN_NETDEV_FRONTEND=y
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-CONFIG_NETCONSOLE=y
-# CONFIG_NETCONSOLE_DYNAMIC is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_RISCOM8 is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
-# CONFIG_STALDRV is not set
-# CONFIG_NOZOMI is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_ALGOBIT=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_ISCH is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Graphics adapter I2C/DDC channel drivers
-#
-# CONFIG_I2C_VOODOO3 is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_AT24 is not set
-# CONFIG_SENSORS_EEPROM is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_I5K_AMB is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-CONFIG_THERMAL=m
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_FORCE_CPEI_RETARGET=y
+CONFIG_FUSION_CTL=y
+CONFIG_FUSION_FC=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
 CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
 CONFIG_HID_NTRIG=y
 CONFIG_HID_PANTHERLORD=y
-# CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
-# CONFIG_GREENASIA_FF is not set
 CONFIG_HID_TOPSEED=y
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_WHCI_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_UWB is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_INFINIBAND is not set
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_UIO is not set
-CONFIG_XEN_BALLOON=y
-CONFIG_XEN_SCRUB_PAGES=y
-CONFIG_XENFS=y
-CONFIG_XEN_COMPAT_XENFS=y
-# CONFIG_STAGING is not set
-# CONFIG_MSPEC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
-CONFIG_XFS_FS=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_DEBUG is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-CONFIG_DNOTIFY=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_GRANULE_16MB=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IA64_XEN_GUEST=y
+CONFIG_IDE=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET=y
 CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KEXEC=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1384,15 +131,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1400,200 +146,54 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=2048
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARAVIRT_GUEST=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_PERMIT_BSP_REMOVE=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-
-#
-# Tracers
-#
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_CRYPTO_DEV_HIFN_795X is not set
-CONFIG_HAVE_KVM=y
-CONFIG_VIRTUALIZATION=y
-# CONFIG_KVM is not set
-# CONFIG_VIRTIO_PCI is not set
-# CONFIG_VIRTIO_BALLOON is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
-# CONFIG_IOMMU_API is not set
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_PARTITION=y
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB=y
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/zx1_defconfig b/arch/ia64/configs/zx1_defconfig
index 3cec65b534c2..de0b68e0d48e 100644
--- a/arch/ia64/configs/zx1_defconfig
+++ b/arch/ia64/configs/zx1_defconfig
@@ -1,1460 +1,85 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21-rc3
-# Thu Mar  8 11:04:20 2007
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-# CONFIG_CPUSETS is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLUB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_MMU=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_IA64_GENERIC is not set
-# CONFIG_IA64_DIG is not set
-CONFIG_IA64_HP_ZX1=y
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-# CONFIG_IA64_CYCLONE is not set
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-# CONFIG_SCHED_SMT is not set
-# CONFIG_PERMIT_BSP_REMOVE is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_ESI is not set
-# CONFIG_KEXEC is not set
-CONFIG_CRASH_DUMP=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
 CONFIG_ACPI_PROCFS=y
-CONFIG_ACPI_BUTTON=y
-CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_DOCK is not set
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=y
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=y
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCIEPORTBUS is not set
-# CONFIG_PCI_MSI is not set
-# CONFIG_PCI_DEBUG is not set
-
-#
-# PCI Hotplug Support
-#
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK is not set
-# CONFIG_NF_CONNTRACK_ENABLED is not set
-# CONFIG_NETFILTER_XTABLES is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_TCPPROBE is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_AGP_HP_ZX1=y
+CONFIG_AGP=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=y
+CONFIG_BLK_DEV_CMD64X=y
+CONFIG_BLK_DEV_GENERIC=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_SHARE_IRQ=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
-CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_PCI_AUTO is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
-# CONFIG_BLK_DEV_PIIX is not set
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=y
-CONFIG_CHR_DEV_OSST=y
-CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_CHR_DEV_OSST=y
 CONFIG_CHR_DEV_SG=y
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-# CONFIG_SCSI_SCAN_ASYNC is not set
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=y
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DRM_RADEON=y
+CONFIG_DRM=y
 CONFIG_DUMMY=y
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-
-#
-# Tulip family network device support
-#
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=y
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-# CONFIG_EEPRO100 is not set
-CONFIG_E100=y
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
 CONFIG_E1000=y
-# CONFIG_E1000_NAPI is not set
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=y
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
+CONFIG_E100=y
+CONFIG_EFI_PARTITION=y
 CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_AGP=y
-CONFIG_AGP_HP_ZX1=y
-CONFIG_DRM=y
-# CONFIG_DRM_TDFX is not set
-# CONFIG_DRM_R128 is not set
-CONFIG_DRM_RADEON=y
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_SIS is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HPET is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCF=y
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_I810 is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PASEMI is not set
-# CONFIG_I2C_PROSAVAGE is not set
-# CONFIG_I2C_SAVAGE4 is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-# CONFIG_I2C_VOODOO3 is not set
-# CONFIG_I2C_PCA_ISA is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_SM501 is not set
-
-#
-# Multimedia devices
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-CONFIG_VIDEO_V4L2=y
-
-#
-# Video Capture Adapters
-#
-
-#
-# Video Capture Adapters
-#
-# CONFIG_VIDEO_ADV_DEBUG is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_BT848 is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_TUNER_3036 is not set
-# CONFIG_VIDEO_STRADIS is not set
-# CONFIG_VIDEO_ZORAN is not set
-# CONFIG_VIDEO_SAA7134 is not set
-# CONFIG_VIDEO_MXB is not set
-# CONFIG_VIDEO_DPC is not set
-# CONFIG_VIDEO_HEXIUM_ORION is not set
-# CONFIG_VIDEO_HEXIUM_GEMINI is not set
-# CONFIG_VIDEO_CX88 is not set
-# CONFIG_VIDEO_CAFE_CCIC is not set
-
-#
-# V4L USB devices
-#
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_VICAM is not set
-# CONFIG_USB_IBMCAM is not set
-# CONFIG_USB_KONICAWC is not set
-# CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_VIDEO_OVCAMCHIP is not set
-# CONFIG_USB_W9968CF is not set
-# CONFIG_USB_OV511 is not set
-# CONFIG_USB_SE401 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_STV680 is not set
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_PWC is not set
-
-#
-# Radio Adapters
-#
-# CONFIG_RADIO_GEMTEK_PCI is not set
-# CONFIG_RADIO_MAXIRADIO is not set
-# CONFIG_RADIO_MAESTRO is not set
-# CONFIG_USB_DSBR is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_DDC=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-CONFIG_FB_BACKLIGHT=y
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frambuffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_MATROX is not set
-CONFIG_FB_RADEON=y
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-CONFIG_FB_RADEON_DEBUG=y
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_HWDEP=y
-CONFIG_SND_RAWMIDI=y
-CONFIG_SND_SEQUENCER=y
-# CONFIG_SND_SEQ_DUMMY is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_MPU401_UART=y
-CONFIG_SND_OPL3_LIB=y
-CONFIG_SND_AC97_CODEC=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-# CONFIG_SND_CS4281 is not set
-# CONFIG_SND_CS46XX is not set
-# CONFIG_SND_DARLA20 is not set
-# CONFIG_SND_GINA20 is not set
-# CONFIG_SND_LAYLA20 is not set
-# CONFIG_SND_DARLA24 is not set
-# CONFIG_SND_GINA24 is not set
-# CONFIG_SND_LAYLA24 is not set
-# CONFIG_SND_MONA is not set
-# CONFIG_SND_MIA is not set
-# CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_INDIGO is not set
-# CONFIG_SND_INDIGOIO is not set
-# CONFIG_SND_INDIGODJ is not set
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=y
-# CONFIG_SND_FM801_TEA575X_BOOL is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RIPTIDE is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# SoC audio support
-#
-# CONFIG_SND_SOC is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=y
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=y
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-CONFIG_USB_HIDDEV=y
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_USB_MON=y
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-# CONFIG_MSPEC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS_XATTR=y
-# CONFIG_EXT2_FS_POSIX_ACL is not set
-# CONFIG_EXT2_FS_SECURITY is not set
-# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_INOTIFY is not set
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_FB_RADEON_DEBUG=y
+CONFIG_FB_RADEON=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_FC=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HWMON is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_IA64_HP_ZX1=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IA64_PRINT_HAZARDS=y
+CONFIG_IDE=y
+CONFIG_INET=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_JOYDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=y
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
+CONFIG_KPROBES=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MODULES=y
 CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NETFILTER=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-CONFIG_RPCSEC_GSS_KRB5=y
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1251=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=y
 CONFIG_NLS_CODEPAGE_775=y
@@ -1470,15 +95,14 @@ CONFIG_NLS_CODEPAGE_864=y
 CONFIG_NLS_CODEPAGE_865=y
 CONFIG_NLS_CODEPAGE_866=y
 CONFIG_NLS_CODEPAGE_869=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_874=y
 CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_936=y
 CONFIG_NLS_CODEPAGE_949=y
-CONFIG_NLS_CODEPAGE_874=y
-CONFIG_NLS_ISO8859_8=y
-# CONFIG_NLS_CODEPAGE_1250 is not set
-CONFIG_NLS_CODEPAGE_1251=y
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=y
 CONFIG_NLS_ISO8859_3=y
@@ -1486,125 +110,52 @@ CONFIG_NLS_ISO8859_4=y
 CONFIG_NLS_ISO8859_5=y
 CONFIG_NLS_ISO8859_6=y
 CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_8=y
 CONFIG_NLS_ISO8859_9=y
-CONFIG_NLS_ISO8859_13=y
-CONFIG_NLS_ISO8859_14=y
-CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_KOI8_R=y
 CONFIG_NLS_KOI8_U=y
 CONFIG_NLS_UTF8=y
-
-#
-# Distributed Lock Manager
-#
-# CONFIG_DLM is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-CONFIG_KPROBES=y
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_LKDTM is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-CONFIG_IA64_PRINT_HAZARDS=y
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_MANAGER=y
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_NR_CPUS=16
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_PROC_KCORE=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SMP=y
+CONFIG_SND_FM801=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND=y
+CONFIG_SOUND=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP_MMIO=y
+CONFIG_TULIP_MWI=y
+CONFIG_TULIP_NAPI_HW_MITIGATION=y
+CONFIG_TULIP_NAPI=y
+CONFIG_TULIP=y
+CONFIG_UDF_FS=y
+CONFIG_UNIX=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB=y
+CONFIG_VFAT_FS=y
diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h
index a362e67e0ca6..2f229e5de498 100644
--- a/arch/ia64/include/asm/kvm_host.h
+++ b/arch/ia64/include/asm/kvm_host.h
@@ -235,6 +235,7 @@ struct kvm_vm_data {
 #define KVM_REQ_PTC_G           32
 #define KVM_REQ_RESUME          33
 
+#define KVM_HPAGE_GFN_SHIFT(x)  0
 #define KVM_NR_PAGE_SIZES       1
 #define KVM_PAGES_PER_HPAGE(x)  1
 
diff --git a/arch/ia64/include/asm/local64.h b/arch/ia64/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/ia64/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/ia64/include/asm/page.h b/arch/ia64/include/asm/page.h
index 5f271bc712ee..41b6d31110fd 100644
--- a/arch/ia64/include/asm/page.h
+++ b/arch/ia64/include/asm/page.h
@@ -41,7 +41,7 @@
 #define PAGE_SIZE               (__IA64_UL_CONST(1) << PAGE_SHIFT)
 #define PAGE_MASK               (~(PAGE_SIZE - 1))
 
-#define PERCPU_PAGE_SHIFT       16      /* log2() of max. size of per-CPU area */
+#define PERCPU_PAGE_SHIFT       18      /* log2() of max. size of per-CPU area */
 #define PERCPU_PAGE_SIZE        (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
 
 
diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c
index 6c8922856049..4a746ea838ff 100644
--- a/arch/ia64/kernel/msi_ia64.c
+++ b/arch/ia64/kernel/msi_ia64.c
@@ -25,7 +25,7 @@ static int ia64_set_msi_irq_affinity(unsigned int irq,
         if (irq_prepare_move(irq, cpu))
                 return -1;
 
-        read_msi_msg(irq, &msg);
+        get_cached_msi_msg(irq, &msg);
 
         addr = msg.address_lo;
         addr &= MSI_ADDR_DEST_ID_MASK;
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index ab985f785c14..744329072f33 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -1696,8 +1696,8 @@ pfm_poll(struct file *filp, poll_table * wait)
         return mask;
 }
 
-static int
-pfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+static long
+pfm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
         DPRINT(("pfm_ioctl called\n"));
         return -EINVAL;
@@ -2174,15 +2174,15 @@ pfm_no_open(struct inode *irrelevant, struct file *dontcare)
 
 
 static const struct file_operations pfm_file_ops = {
-        .llseek   = no_llseek,
-        .read     = pfm_read,
-        .write    = pfm_write,
-        .poll     = pfm_poll,
-        .ioctl    = pfm_ioctl,
-        .open     = pfm_no_open,        /* special open code to disallow open via /proc */
-        .fasync   = pfm_fasync,
-        .release  = pfm_close,
-        .flush    = pfm_flush
+        .llseek         = no_llseek,
+        .read           = pfm_read,
+        .write          = pfm_write,
+        .poll           = pfm_poll,
+        .unlocked_ioctl = pfm_ioctl,
+        .open           = pfm_no_open,  /* special open code to disallow open via /proc */
+        .fasync         = pfm_fasync,
+        .release        = pfm_close,
+        .flush          = pfm_flush
 };
 
 static int
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index 653b3c46ea82..ed6f22eb5b12 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -471,7 +471,8 @@ void update_vsyscall_tz(void)
 {
 }
 
-void update_vsyscall(struct timespec *wall, struct clocksource *c, u32 mult)
+void update_vsyscall(struct timespec *wall, struct timespec *wtm,
+                        struct clocksource *c, u32 mult)
 {
         unsigned long flags;
 
@@ -487,9 +488,9 @@ void update_vsyscall(struct timespec *wall, struct clocksource *c, u32 mult)
         /* copy kernel time structures */
         fsyscall_gtod_data.wall_time.tv_sec = wall->tv_sec;
         fsyscall_gtod_data.wall_time.tv_nsec = wall->tv_nsec;
-        fsyscall_gtod_data.monotonic_time.tv_sec = wall_to_monotonic.tv_sec
+        fsyscall_gtod_data.monotonic_time.tv_sec = wtm->tv_sec
                                                         + wall->tv_sec;
-        fsyscall_gtod_data.monotonic_time.tv_nsec = wall_to_monotonic.tv_nsec
+        fsyscall_gtod_data.monotonic_time.tv_nsec = wtm->tv_nsec
                                                         + wall->tv_nsec;
 
         /* normalize */
diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S
index e07218a2577f..5a4d044dcb1c 100644
--- a/arch/ia64/kernel/vmlinux.lds.S
+++ b/arch/ia64/kernel/vmlinux.lds.S
@@ -6,204 +6,209 @@
 
 #include <asm-generic/vmlinux.lds.h>
 
-#define IVT_TEXT                                                        \
-                VMLINUX_SYMBOL(__start_ivt_text) = .;                   \
-                *(.text..ivt)                                           \
-                VMLINUX_SYMBOL(__end_ivt_text) = .;
-
 OUTPUT_FORMAT("elf64-ia64-little")
 OUTPUT_ARCH(ia64)
 ENTRY(phys_start)
 jiffies = jiffies_64;
+
 PHDRS {
-  code   PT_LOAD;
-  percpu PT_LOAD;
-  data   PT_LOAD;
-  note   PT_NOTE;
-  unwind 0x70000001; /* PT_IA_64_UNWIND, but ld doesn't match the name */
+        code   PT_LOAD;
+        percpu PT_LOAD;
+        data   PT_LOAD;
+        note   PT_NOTE;
+        unwind 0x70000001; /* PT_IA_64_UNWIND, but ld doesn't match the name */
 }
-SECTIONS
-{
-  /* unwind exit sections must be discarded before the rest of the
-     sections get included. */
-  /DISCARD/ : {
-        *(.IA_64.unwind.exit.text)
-        *(.IA_64.unwind_info.exit.text)
-        *(.comment)
-        *(.note)
-  }
-
-  v = PAGE_OFFSET;      /* this symbol is here to make debugging easier... */
-  phys_start = _start - LOAD_OFFSET;
-
-  code : { } :code
-  . = KERNEL_START;
-
-  _text = .;
-  _stext = .;
-
-  .text : AT(ADDR(.text) - LOAD_OFFSET)
-    {
-        IVT_TEXT
-        TEXT_TEXT
-        SCHED_TEXT
-        LOCK_TEXT
-        KPROBES_TEXT
-        *(.gnu.linkonce.t*)
-    }
-  .text2 : AT(ADDR(.text2) - LOAD_OFFSET)
-        { *(.text2) }
-#ifdef CONFIG_SMP
-  .text..lock : AT(ADDR(.text..lock) - LOAD_OFFSET)
-        { *(.text..lock) }
-#endif
-  _etext = .;
 
-  /* Read-only data */
+SECTIONS {
+        /*
+         * unwind exit sections must be discarded before
+         * the rest of the sections get included.
+         */
+        /DISCARD/ : {
+                *(.IA_64.unwind.exit.text)
+                *(.IA_64.unwind_info.exit.text)
+                *(.comment)
+                *(.note)
+        }
 
-  NOTES :code :note             /* put .notes in text and mark in PT_NOTE  */
-  code_continues : {} :code     /* switch back to regular program...  */
+        v = PAGE_OFFSET; /* this symbol is here to make debugging easier... */
+        phys_start = _start - LOAD_OFFSET;
+
+        code : {
+        } :code
+        . = KERNEL_START;
+
+        _text = .;
+        _stext = .;
+
+        .text : AT(ADDR(.text) - LOAD_OFFSET) {
+                __start_ivt_text = .;
+                *(.text..ivt)
+                __end_ivt_text = .;
+                TEXT_TEXT
+                SCHED_TEXT
+                LOCK_TEXT
+                KPROBES_TEXT
+                *(.gnu.linkonce.t*)
+        }
 
-  EXCEPTION_TABLE(16)
+        .text2 : AT(ADDR(.text2) - LOAD_OFFSET) {
+                *(.text2)
+        }
 
-  /* MCA table */
-  . = ALIGN(16);
-  __mca_table : AT(ADDR(__mca_table) - LOAD_OFFSET)
-        {
-          __start___mca_table = .;
-          *(__mca_table)
-          __stop___mca_table = .;
+#ifdef CONFIG_SMP
+        .text..lock : AT(ADDR(.text..lock) - LOAD_OFFSET) {
+                *(.text..lock)
+        }
+#endif
+        _etext = .;
+
+        /*
+         * Read-only data
+         */
+        NOTES :code :note       /* put .notes in text and mark in PT_NOTE  */
+        code_continues : {
+        } : code               /* switch back to regular program...  */
+
+        EXCEPTION_TABLE(16)
+
+        /* MCA table */
+        . = ALIGN(16);
+        __mca_table : AT(ADDR(__mca_table) - LOAD_OFFSET) {
+                __start___mca_table = .;
+                *(__mca_table)
+                __stop___mca_table = .;
         }
 
-  .data..patch.phys_stack_reg : AT(ADDR(.data..patch.phys_stack_reg) - LOAD_OFFSET)
-        {
-          __start___phys_stack_reg_patchlist = .;
-          *(.data..patch.phys_stack_reg)
-          __end___phys_stack_reg_patchlist = .;
+        .data..patch.phys_stack_reg : AT(ADDR(.data..patch.phys_stack_reg) - LOAD_OFFSET) {
+                __start___phys_stack_reg_patchlist = .;
+                *(.data..patch.phys_stack_reg)
+                __end___phys_stack_reg_patchlist = .;
         }
 
-  /* Global data */
-  _data = .;
+        /*
+         * Global data
+         */
+        _data = .;
 
-  /* Unwind info & table: */
-  . = ALIGN(8);
-  .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - LOAD_OFFSET)
-        { *(.IA_64.unwind_info*) }
-  .IA_64.unwind : AT(ADDR(.IA_64.unwind) - LOAD_OFFSET)
-        {
-          __start_unwind = .;
-          *(.IA_64.unwind*)
-          __end_unwind = .;
+        /* Unwind info & table: */
+        . = ALIGN(8);
+        .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - LOAD_OFFSET) {
+                *(.IA_64.unwind_info*)
+        }
+        .IA_64.unwind : AT(ADDR(.IA_64.unwind) - LOAD_OFFSET) {
+                __start_unwind = .;
+                *(.IA_64.unwind*)
+                __end_unwind = .;
         } :code :unwind
-  code_continues2 : {} : code
+        code_continues2 : {
+        } : code
 
-  RODATA
+        RODATA
 
-  .opd : AT(ADDR(.opd) - LOAD_OFFSET)
-        { *(.opd) }
-
-  /* Initialization code and data: */
+        .opd : AT(ADDR(.opd) - LOAD_OFFSET) {
+                *(.opd)
+        }
 
-  . = ALIGN(PAGE_SIZE);
-  __init_begin = .;
+        /*
+         * Initialization code and data:
+         */
+        . = ALIGN(PAGE_SIZE);
+        __init_begin = .;
 
-  INIT_TEXT_SECTION(PAGE_SIZE)
-  INIT_DATA_SECTION(16)
+        INIT_TEXT_SECTION(PAGE_SIZE)
+        INIT_DATA_SECTION(16)
 
-  .data..patch.vtop : AT(ADDR(.data..patch.vtop) - LOAD_OFFSET)
-        {
-          __start___vtop_patchlist = .;
-          *(.data..patch.vtop)
-          __end___vtop_patchlist = .;
+        .data..patch.vtop : AT(ADDR(.data..patch.vtop) - LOAD_OFFSET) {
+                __start___vtop_patchlist = .;
+                *(.data..patch.vtop)
+                __end___vtop_patchlist = .;
         }
 
-  .data..patch.rse : AT(ADDR(.data..patch.rse) - LOAD_OFFSET)
-        {
-          __start___rse_patchlist = .;
-          *(.data..patch.rse)
-          __end___rse_patchlist = .;
+        .data..patch.rse : AT(ADDR(.data..patch.rse) - LOAD_OFFSET) {
+                __start___rse_patchlist = .;
+                *(.data..patch.rse)
+                __end___rse_patchlist = .;
         }
 
-  .data..patch.mckinley_e9 : AT(ADDR(.data..patch.mckinley_e9) - LOAD_OFFSET)
-        {
-          __start___mckinley_e9_bundles = .;
-          *(.data..patch.mckinley_e9)
-          __end___mckinley_e9_bundles = .;
+        .data..patch.mckinley_e9 : AT(ADDR(.data..patch.mckinley_e9) - LOAD_OFFSET) {
+                __start___mckinley_e9_bundles = .;
+                *(.data..patch.mckinley_e9)
+                __end___mckinley_e9_bundles = .;
         }
 
 #if defined(CONFIG_PARAVIRT)
-  . = ALIGN(16);
-  .paravirt_bundles : AT(ADDR(.paravirt_bundles) - LOAD_OFFSET)
-        {
-          __start_paravirt_bundles = .;
-          *(.paravirt_bundles)
-          __stop_paravirt_bundles = .;
-        }
-  . = ALIGN(16);
-  .paravirt_insts : AT(ADDR(.paravirt_insts) - LOAD_OFFSET)
-        {
-          __start_paravirt_insts = .;
-          *(.paravirt_insts)
-          __stop_paravirt_insts = .;
-        }
-  . = ALIGN(16);
-  .paravirt_branches : AT(ADDR(.paravirt_branches) - LOAD_OFFSET)
-        {
-          __start_paravirt_branches = .;
-          *(.paravirt_branches)
-          __stop_paravirt_branches = .;
+        . = ALIGN(16);
+        .paravirt_bundles : AT(ADDR(.paravirt_bundles) - LOAD_OFFSET) {
+                __start_paravirt_bundles = .;
+                *(.paravirt_bundles)
+                __stop_paravirt_bundles = .;
+        }
+        . = ALIGN(16);
+        .paravirt_insts : AT(ADDR(.paravirt_insts) - LOAD_OFFSET) {
+                __start_paravirt_insts = .;
+                *(.paravirt_insts)
+                __stop_paravirt_insts = .;
+        }
+        . = ALIGN(16);
+        .paravirt_branches : AT(ADDR(.paravirt_branches) - LOAD_OFFSET) {
+                __start_paravirt_branches = .;
+                *(.paravirt_branches)
+                __stop_paravirt_branches = .;
         }
 #endif
 
 #if defined(CONFIG_IA64_GENERIC)
-  /* Machine Vector */
-  . = ALIGN(16);
-  .machvec : AT(ADDR(.machvec) - LOAD_OFFSET)
-        {
-          machvec_start = .;
-          *(.machvec)
-          machvec_end = .;
+        /* Machine Vector */
+        . = ALIGN(16);
+        .machvec : AT(ADDR(.machvec) - LOAD_OFFSET) {
+                machvec_start = .;
+                *(.machvec)
+                machvec_end = .;
         }
 #endif
 
 #ifdef  CONFIG_SMP
-  . = ALIGN(PERCPU_PAGE_SIZE);
-  __cpu0_per_cpu = .;
-  . = . + PERCPU_PAGE_SIZE;     /* cpu0 per-cpu space */
+        . = ALIGN(PERCPU_PAGE_SIZE);
+        __cpu0_per_cpu = .;
+        . = . + PERCPU_PAGE_SIZE;   /* cpu0 per-cpu space */
 #endif
 
-  . = ALIGN(PAGE_SIZE);
-  __init_end = .;
+        . = ALIGN(PAGE_SIZE);
+        __init_end = .;
 
-  .data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET)
-        {
-        PAGE_ALIGNED_DATA(PAGE_SIZE)
-          . = ALIGN(PAGE_SIZE);
-          __start_gate_section = .;
-          *(.data..gate)
-          __stop_gate_section = .;
+        .data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET) {
+                PAGE_ALIGNED_DATA(PAGE_SIZE)
+                . = ALIGN(PAGE_SIZE);
+                __start_gate_section = .;
+                *(.data..gate)
+                __stop_gate_section = .;
 #ifdef CONFIG_XEN
-          . = ALIGN(PAGE_SIZE);
-          __xen_start_gate_section = .;
-          *(.data..gate.xen)
-          __xen_stop_gate_section = .;
+                . = ALIGN(PAGE_SIZE);
+                __xen_start_gate_section = .;
+                *(.data..gate.xen)
+                __xen_stop_gate_section = .;
 #endif
         }
-  . = ALIGN(PAGE_SIZE);         /* make sure the gate page doesn't expose
-                                 * kernel data
-                                 */
-
-  /* Per-cpu data: */
-  . = ALIGN(PERCPU_PAGE_SIZE);
-  PERCPU_VADDR(PERCPU_ADDR, :percpu)
-  __phys_per_cpu_start = __per_cpu_load;
-  . = __phys_per_cpu_start + PERCPU_PAGE_SIZE;  /* ensure percpu data fits
-                                                 * into percpu page size
-                                                 */
-
-  data : { } :data
-  .data : AT(ADDR(.data) - LOAD_OFFSET)
-        {
+        /*
+         * make sure the gate page doesn't expose
+         * kernel data
+         */
+        . = ALIGN(PAGE_SIZE);
+
+        /* Per-cpu data: */
+        . = ALIGN(PERCPU_PAGE_SIZE);
+        PERCPU_VADDR(PERCPU_ADDR, :percpu)
+        __phys_per_cpu_start = __per_cpu_load;
+        /*
+         * ensure percpu data fits
+         * into percpu page size
+         */
+        . = __phys_per_cpu_start + PERCPU_PAGE_SIZE;
+
+        data : {
+        } :data
+        .data : AT(ADDR(.data) - LOAD_OFFSET) {
                 INIT_TASK_DATA(PAGE_SIZE)
                 CACHELINE_ALIGNED_DATA(SMP_CACHE_BYTES)
                 READ_MOSTLY_DATA(SMP_CACHE_BYTES)
@@ -213,26 +218,37 @@ SECTIONS
                 CONSTRUCTORS
         }
 
-  . = ALIGN(16);        /* gp must be 16-byte aligned for exc. table */
-  .got : AT(ADDR(.got) - LOAD_OFFSET)
-        { *(.got.plt) *(.got) }
-  __gp = ADDR(.got) + 0x200000;
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata : AT(ADDR(.sdata) - LOAD_OFFSET)
-        { *(.sdata) *(.sdata1) *(.srdata) }
-  _edata  =  .;
+        . = ALIGN(16);  /* gp must be 16-byte aligned for exc. table */
+        .got : AT(ADDR(.got) - LOAD_OFFSET) {
+                *(.got.plt)
+                *(.got)
+        }
+        __gp = ADDR(.got) + 0x200000;
+
+        /*
+         * We want the small data sections together,
+         * so single-instruction offsets can access
+         * them all, and initialized data all before
+         * uninitialized, so we can shorten the
+         * on-disk segment size.
+         */
+        .sdata : AT(ADDR(.sdata) - LOAD_OFFSET) {
+                *(.sdata)
+                *(.sdata1)
+                *(.srdata)
+        }
+        _edata  =  .;
 
-  BSS_SECTION(0, 0, 0)
+        BSS_SECTION(0, 0, 0)
 
-  _end = .;
+        _end = .;
 
-  code : { } :code
+        code : {
+        } :code
 
-  STABS_DEBUG
-  DWARF_DEBUG
+        STABS_DEBUG
+        DWARF_DEBUG
 
-  /* Default discards */
-  DISCARDS
+        /* Default discards */
+        DISCARDS
 }
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 21b701374f72..f56a6316e134 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -725,8 +725,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
         int r;
         sigset_t sigsaved;
 
-        vcpu_load(vcpu);
-
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 
@@ -748,7 +746,6 @@ out:
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 
-        vcpu_put(vcpu);
         return r;
 }
 
@@ -883,8 +880,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         struct vpd *vpd = to_host(vcpu->kvm, vcpu->arch.vpd);
         int i;
 
-        vcpu_load(vcpu);
-
         for (i = 0; i < 16; i++) {
                 vpd->vgr[i] = regs->vpd.vgr[i];
                 vpd->vbgr[i] = regs->vpd.vbgr[i];
@@ -931,8 +926,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         vcpu->arch.itc_offset = regs->saved_itc - kvm_get_itc(vcpu);
         set_bit(KVM_REQ_RESUME, &vcpu->requests);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -1237,7 +1230,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         p_ctx->cr[2] = (unsigned long)kvm_vmm_info->vmm_ivt;
         p_ctx->cr[8] = 0x3c;
 
-        /*Initilize region register*/
+        /*Initialize region register*/
         p_ctx->rr[0] = 0x30;
         p_ctx->rr[1] = 0x30;
         p_ctx->rr[2] = 0x30;
@@ -1246,7 +1239,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         p_ctx->rr[5] = 0x30;
         p_ctx->rr[7] = 0x30;
 
-        /*Initilize branch register 0*/
+        /*Initialize branch register 0*/
         p_ctx->br[0] = *(unsigned long *)kvm_vmm_info->vmm_entry;
 
         vcpu->arch.vmm_rr = kvm->arch.vmm_init_rr;
@@ -1707,7 +1700,7 @@ static int kvm_relocate_vmm(struct kvm_vmm_info *vmm_info,
         BUG_ON(!module);
 
         if (!kvm_vmm_base) {
-                printk("kvm: kvm area hasn't been initilized yet!!\n");
+                printk("kvm: kvm area hasn't been initialized yet!!\n");
                 return -EFAULT;
         }
 
@@ -1802,35 +1795,24 @@ void kvm_arch_exit(void)
         kvm_vmm_info = NULL;
 }
 
-static int kvm_ia64_sync_dirty_log(struct kvm *kvm,
-                struct kvm_dirty_log *log)
+static void kvm_ia64_sync_dirty_log(struct kvm *kvm,
+                                    struct kvm_memory_slot *memslot)
 {
-        struct kvm_memory_slot *memslot;
-        int r, i;
+        int i;
         long base;
         unsigned long n;
         unsigned long *dirty_bitmap = (unsigned long *)(kvm->arch.vm_base +
                         offsetof(struct kvm_vm_data, kvm_mem_dirty_log));
 
-        r = -EINVAL;
-        if (log->slot >= KVM_MEMORY_SLOTS)
-                goto out;
-
-        memslot = &kvm->memslots->memslots[log->slot];
-        r = -ENOENT;
-        if (!memslot->dirty_bitmap)
-                goto out;
-
         n = kvm_dirty_bitmap_bytes(memslot);
         base = memslot->base_gfn / BITS_PER_LONG;
 
+        spin_lock(&kvm->arch.dirty_log_lock);
         for (i = 0; i < n/sizeof(long); ++i) {
                 memslot->dirty_bitmap[i] = dirty_bitmap[base + i];
                 dirty_bitmap[base + i] = 0;
         }
-        r = 0;
-out:
-        return r;
+        spin_unlock(&kvm->arch.dirty_log_lock);
 }
 
 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
@@ -1842,12 +1824,17 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
         int is_dirty = 0;
 
         mutex_lock(&kvm->slots_lock);
-        spin_lock(&kvm->arch.dirty_log_lock);
 
-        r = kvm_ia64_sync_dirty_log(kvm, log);
-        if (r)
+        r = -EINVAL;
+        if (log->slot >= KVM_MEMORY_SLOTS)
+                goto out;
+
+        memslot = &kvm->memslots->memslots[log->slot];
+        r = -ENOENT;
+        if (!memslot->dirty_bitmap)
                 goto out;
 
+        kvm_ia64_sync_dirty_log(kvm, memslot);
         r = kvm_get_dirty_log(kvm, log, &is_dirty);
         if (r)
                 goto out;
@@ -1855,14 +1842,12 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
         /* If nothing is dirty, don't bother messing with page tables. */
         if (is_dirty) {
                 kvm_flush_remote_tlbs(kvm);
-                memslot = &kvm->memslots->memslots[log->slot];
                 n = kvm_dirty_bitmap_bytes(memslot);
                 memset(memslot->dirty_bitmap, 0, n);
         }
         r = 0;
 out:
         mutex_unlock(&kvm->slots_lock);
-        spin_unlock(&kvm->arch.dirty_log_lock);
         return r;
 }
 
@@ -1953,11 +1938,6 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
         return vcpu->arch.timer_fired;
 }
 
-gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
-{
-        return gfn;
-}
-
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 {
         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) ||
@@ -1967,9 +1947,7 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
                                     struct kvm_mp_state *mp_state)
 {
-        vcpu_load(vcpu);
         mp_state->mp_state = vcpu->arch.mp_state;
-        vcpu_put(vcpu);
         return 0;
 }
 
@@ -2000,10 +1978,8 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 {
         int r = 0;
 
-        vcpu_load(vcpu);
         vcpu->arch.mp_state = mp_state->mp_state;
         if (vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)
                 r = vcpu_reset(vcpu);
-        vcpu_put(vcpu);
         return r;
 }
diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c
index ebfdd6a9ae1a..0c72dd463831 100644
--- a/arch/ia64/sn/kernel/msi_sn.c
+++ b/arch/ia64/sn/kernel/msi_sn.c
@@ -175,7 +175,7 @@ static int sn_set_msi_irq_affinity(unsigned int irq,
          * Release XIO resources for the old MSI PCI address
          */
 
-        read_msi_msg(irq, &msg);
+        get_cached_msi_msg(irq, &msg);
         sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
         pdev = sn_pdev->pdi_linux_pcidev;
         provider = SN_PCIDEV_BUSPROVIDER(pdev);
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
index d00dfc180021..dbc4cbecb5ed 100644
--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -507,7 +507,7 @@ static void __init sn_init_pdas(char **cmdline_p)
         cnodeid_t cnode;
 
         /*
-         * Allocate & initalize the nodepda for each node.
+         * Allocate & initialize the nodepda for each node.
          */
         for_each_online_node(cnode) {
                 nodepdaindr[cnode] =
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 3a9319f93e89..836abbbc9c04 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -44,9 +44,6 @@ config HZ
         int
         default 100
 
-config GENERIC_TIME
-        def_bool y
-
 config ARCH_USES_GETTIMEOFFSET
         def_bool y
 
diff --git a/arch/m32r/Makefile b/arch/m32r/Makefile
index 469766b24e22..8ff5ba0ea26c 100644
--- a/arch/m32r/Makefile
+++ b/arch/m32r/Makefile
@@ -12,8 +12,8 @@ OBJCOPYFLAGS	:= -O binary -R .note -R .comment -S
 LDFLAGS_vmlinux :=
 
 KBUILD_CFLAGS += -pipe -fno-schedule-insns
-CFLAGS_KERNEL += -mmodel=medium
-CFLAGS_MODULE += -mmodel=large
+KBUILD_CFLAGS_KERNEL += -mmodel=medium
+KBUILD_CFLAGS_MODULE += -mmodel=large
 
 ifdef CONFIG_CHIP_VDEC2
 cflags-$(CONFIG_ISA_M32R2)      += -DNO_FPU -Wa,-bitinst
diff --git a/arch/m32r/include/asm/local64.h b/arch/m32r/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/m32r/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 2e3737b92ffc..8030e2481d97 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -59,9 +59,6 @@ config HZ
         int
         default 100
 
-config GENERIC_TIME
-        def_bool y
-
 config ARCH_USES_GETTIMEOFFSET
         def_bool y
 
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 570d85c3f97f..b06a7e3cbcd6 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -18,7 +18,7 @@ KBUILD_DEFCONFIG := multi_defconfig
 # override top level makefile
 AS += -m68020
 LDFLAGS := -m m68kelf
-LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds
+KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds
 ifneq ($(SUBARCH),$(ARCH))
         ifeq ($(CROSS_COMPILE),)
                 CROSS_COMPILE := $(call cc-cross-prefix, \
diff --git a/arch/m68k/include/asm/local64.h b/arch/m68k/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/m68k/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index efeb6033fc17..2609c394e1df 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -63,10 +63,6 @@ config GENERIC_CALIBRATE_DELAY
         bool
         default y
 
-config GENERIC_TIME
-        bool
-        default y
-
 config GENERIC_CMOS_UPDATE
         bool
         default y
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 505a08592423..692fdfce2a23 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -14,9 +14,12 @@ config MICROBLAZE
         select USB_ARCH_HAS_EHCI
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select HAVE_OPROFILE
+        select HAVE_ARCH_KGDB
         select HAVE_DMA_ATTRS
         select HAVE_DMA_API_DEBUG
         select TRACING_SUPPORT
+        select OF
+        select OF_FLATTREE
 
 config SWAP
         def_bool n
@@ -48,9 +51,6 @@ config GENERIC_IRQ_PROBE
 config GENERIC_CALIBRATE_DELAY
         def_bool y
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_TIME_VSYSCALL
         def_bool n
 
@@ -75,9 +75,6 @@ config LOCKDEP_SUPPORT
 config HAVE_LATENCYTOP_SUPPORT
         def_bool y
 
-config DTC
-        def_bool y
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
@@ -124,18 +121,6 @@ config CMDLINE_FORCE
           Set this to have arguments from the default kernel command string
           override those passed by the boot loader.
 
-config OF
-        def_bool y
-        select OF_FLATTREE
-
-config PROC_DEVICETREE
-        bool "Support for device tree in /proc"
-        depends on PROC_FS
-        help
-          This option adds a device-tree directory under /proc which contains
-          an image of the device tree that the kernel copies from Open
-          Firmware or other boot firmware. If unsure, say Y here.
-
 endmenu
 
 menu "Advanced setup"
@@ -223,6 +208,36 @@ config TASK_SIZE
         hex "Size of user task space" if TASK_SIZE_BOOL
         default "0x80000000"
 
+choice
+        prompt "Page size"
+        default MICROBLAZE_4K_PAGES
+        depends on ADVANCED_OPTIONS && !MMU
+        help
+          Select the kernel logical page size. Increasing the page size
+          will reduce software overhead at each page boundary, allow
+          hardware prefetch mechanisms to be more effective, and allow
+          larger dma transfers increasing IO efficiency and reducing
+          overhead. However the utilization of memory will increase.
+          For example, each cached file will using a multiple of the
+          page size to hold its contents and the difference between the
+          end of file and the end of page is wasted.
+
+          If unsure, choose 4K_PAGES.
+
+config MICROBLAZE_4K_PAGES
+        bool "4k page size"
+
+config MICROBLAZE_8K_PAGES
+        bool "8k page size"
+
+config MICROBLAZE_16K_PAGES
+        bool "16k page size"
+
+config MICROBLAZE_32K_PAGES
+        bool "32k page size"
+
+endchoice
+
 endmenu
 
 source "mm/Kconfig"
diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug
index 9dc708a7f700..e6e5e0da28c3 100644
--- a/arch/microblaze/Kconfig.debug
+++ b/arch/microblaze/Kconfig.debug
@@ -10,6 +10,7 @@ source "lib/Kconfig.debug"
 
 config EARLY_PRINTK
         bool "Early printk function for kernel"
+        depends on SERIAL_UARTLITE_CONSOLE
         default n
         help
           This option turns on/off early printk messages to console.
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index 72f6e8583746..592c7079de88 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -25,7 +25,7 @@ ifeq (,$(findstring spartan2,$(CONFIG_XILINX_MICROBLAZE0_FAMILY)))
   ifeq ($(CPU_MAJOR),3)
     CPUFLAGS-1 += -mno-xl-soft-mul
   else
-    # USE_HW_MUL can be 0, 1, or 2, defining a heirarchy of HW Mul support.
+    # USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
     CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
     CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
   endif
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index 57f50c2371c6..be01d78750d9 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -35,13 +35,14 @@ quiet_cmd_cp = CP      $< $@$2
         cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)
 
 quiet_cmd_strip = STRIP   $@
-      cmd_strip = $(STRIP) -K _start -K _end -K __log_buf -K _fdt_start vmlinux -o $@
+        cmd_strip = $(STRIP) -K microblaze_start -K _end -K __log_buf \
+                                -K _fdt_start vmlinux -o $@
 
 quiet_cmd_uimage = UIMAGE  $@.ub
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
-                   -C none -n 'Linux-$(KERNELRELEASE)' \
-                   -a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
-                   -d $@ $@.ub
+        cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
+                -C none -n 'Linux-$(KERNELRELEASE)' \
+                -a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
+                -d $@ $@.ub
 
 $(obj)/simpleImage.%: vmlinux FORCE
         $(call if_changed,cp,.unstrip)
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
index a6edd356cd08..7ebd955460d9 100644
--- a/arch/microblaze/include/asm/cacheflush.h
+++ b/arch/microblaze/include/asm/cacheflush.h
@@ -17,6 +17,7 @@
 
 /* Somebody depends on this; sigh... */
 #include <linux/mm.h>
+#include <linux/io.h>
 
 /* Look at Documentation/cachetlb.txt */
 
@@ -60,7 +61,6 @@ void microblaze_cache_init(void);
 #define invalidate_icache()                             mbc->iin();
 #define invalidate_icache_range(start, end)             mbc->iinr(start, end);
 
-
 #define flush_icache_user_range(vma, pg, adr, len)      flush_icache();
 #define flush_icache_page(vma, pg)                      do { } while (0)
 
@@ -72,9 +72,15 @@ void microblaze_cache_init(void);
 #define flush_dcache()                                  mbc->dfl();
 #define flush_dcache_range(start, end)                  mbc->dflr(start, end);
 
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-/* D-cache aliasing problem can't happen - cache is between MMU and ram */
-#define flush_dcache_page(page)                 do { } while (0)
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+/* MS: We have to implement it because of rootfs-jffs2 issue on WB */
+#define flush_dcache_page(page) \
+do { \
+        unsigned long addr = (unsigned long) page_address(page); /* virtual */ \
+        addr = (u32)virt_to_phys((void *)addr); \
+        flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
+} while (0);
+
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
 
@@ -97,8 +103,10 @@ void microblaze_cache_init(void);
 
 #define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
 do {                                                                    \
+        u32 addr = virt_to_phys(dst);                                   \
+        invalidate_icache_range((unsigned) (addr), (unsigned) (addr) + (len));\
         memcpy((dst), (src), (len));                                    \
-        flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
+        flush_dcache_range((unsigned) (addr), (unsigned) (addr) + (len));\
 } while (0)
 
 #define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
diff --git a/arch/microblaze/include/asm/dma-mapping.h b/arch/microblaze/include/asm/dma-mapping.h
index 18b3731c8509..507389580709 100644
--- a/arch/microblaze/include/asm/dma-mapping.h
+++ b/arch/microblaze/include/asm/dma-mapping.h
@@ -79,12 +79,6 @@ static inline int dma_supported(struct device *dev, u64 mask)
         return ops->dma_supported(dev, mask);
 }
 
-#ifdef CONFIG_PCI
-/* We have our own implementation of pci_set_dma_mask() */
-#define HAVE_ARCH_PCI_SET_DMA_MASK
-
-#endif
-
 static inline int dma_set_mask(struct device *dev, u64 dma_mask)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
diff --git a/arch/microblaze/include/asm/elf.h b/arch/microblaze/include/asm/elf.h
index 7d4acf2b278e..732caf1be741 100644
--- a/arch/microblaze/include/asm/elf.h
+++ b/arch/microblaze/include/asm/elf.h
@@ -77,7 +77,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #define ELF_DATA        ELFDATA2MSB
 #endif
 
-#define ELF_EXEC_PAGESIZE       4096
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 
 #define ELF_CORE_COPY_REGS(_dest, _regs)                        \
diff --git a/arch/microblaze/include/asm/exceptions.h b/arch/microblaze/include/asm/exceptions.h
index 4c7b5d037c88..6479097b802b 100644
--- a/arch/microblaze/include/asm/exceptions.h
+++ b/arch/microblaze/include/asm/exceptions.h
@@ -14,6 +14,11 @@
 #define _ASM_MICROBLAZE_EXCEPTIONS_H
 
 #ifdef __KERNEL__
+
+#ifndef CONFIG_MMU
+#define EX_HANDLER_STACK_SIZ    (4*19)
+#endif
+
 #ifndef __ASSEMBLY__
 
 /* Macros to enable and disable HW exceptions in the MSR */
@@ -64,22 +69,6 @@ asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,
 void die(const char *str, struct pt_regs *fp, long err);
 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr);
 
-#if defined(CONFIG_KGDB)
-void (*debugger)(struct pt_regs *regs);
-int (*debugger_bpt)(struct pt_regs *regs);
-int (*debugger_sstep)(struct pt_regs *regs);
-int (*debugger_iabr_match)(struct pt_regs *regs);
-int (*debugger_dabr_match)(struct pt_regs *regs);
-void (*debugger_fault_handler)(struct pt_regs *regs);
-#else
-#define debugger(regs)                  do { } while (0)
-#define debugger_bpt(regs)              0
-#define debugger_sstep(regs)            0
-#define debugger_iabr_match(regs)       0
-#define debugger_dabr_match(regs)       0
-#define debugger_fault_handler          ((void (*)(struct pt_regs *))0)
-#endif
-
 #endif /*__ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_MICROBLAZE_EXCEPTIONS_H */
diff --git a/arch/microblaze/include/asm/irq.h b/arch/microblaze/include/asm/irq.h
index 31a35c33df63..ec5583d6111c 100644
--- a/arch/microblaze/include/asm/irq.h
+++ b/arch/microblaze/include/asm/irq.h
@@ -27,17 +27,6 @@ extern unsigned int nr_irq;
 struct pt_regs;
 extern void do_IRQ(struct pt_regs *regs);
 
-/**
- * irq_of_parse_and_map - Parse and Map an interrupt into linux virq space
- * @device: Device node of the device whose interrupt is to be mapped
- * @index: Index of the interrupt to map
- *
- * This function is a wrapper that chains of_irq_map_one() and
- * irq_create_of_mapping() to make things easier to callers
- */
-struct device_node;
-extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
-
 /** FIXME - not implement
  * irq_dispose_mapping - Unmap an interrupt
  * @virq: linux virq number of the interrupt to unmap
@@ -62,17 +51,4 @@ struct irq_host;
 extern unsigned int irq_create_mapping(struct irq_host *host,
                                         irq_hw_number_t hwirq);
 
-/**
- * irq_create_of_mapping - Map a hardware interrupt into linux virq space
- * @controller: Device node of the interrupt controller
- * @inspec: Interrupt specifier from the device-tree
- * @intsize: Size of the interrupt specifier from the device-tree
- *
- * This function is identical to irq_create_mapping except that it takes
- * as input informations straight from the device-tree (typically the results
- * of the of_irq_map_*() functions.
- */
-extern unsigned int irq_create_of_mapping(struct device_node *controller,
-                                        u32 *intspec, unsigned int intsize);
-
 #endif /* _ASM_MICROBLAZE_IRQ_H */
diff --git a/arch/microblaze/include/asm/kgdb.h b/arch/microblaze/include/asm/kgdb.h
new file mode 100644
index 000000000000..78b17d40b235
--- /dev/null
+++ b/arch/microblaze/include/asm/kgdb.h
@@ -0,0 +1,28 @@
+#ifdef __KERNEL__
+#ifndef __MICROBLAZE_KGDB_H__
+#define __MICROBLAZE_KGDB_H__
+
+#ifndef __ASSEMBLY__
+
+#define CACHE_FLUSH_IS_SAFE     1
+#define BUFMAX                  2048
+
+/*
+ * 32 32-bit general purpose registers (r0-r31)
+ *  6 32-bit special registers (pc, msr, ear, esr, fsr, btr)
+ * 12 32-bit PVR
+ *   7 32-bit MMU Regs (redr, rpid, rzpr, rtlbx, rtlbsx, rtlblo, rtlbhi)
+ * ------
+ *  57 registers
+ */
+#define NUMREGBYTES     (57 * 4)
+
+#define BREAK_INSTR_SIZE        4
+static inline void arch_kgdb_breakpoint(void)
+{
+        __asm__ __volatile__("brki r16, 0x18;");
+}
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MICROBLAZE_KGDB_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/microblaze/include/asm/local64.h b/arch/microblaze/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/microblaze/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/microblaze/include/asm/of_device.h b/arch/microblaze/include/asm/of_device.h
deleted file mode 100644
index 73cb98040982..000000000000
--- a/arch/microblaze/include/asm/of_device.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2007-2008 Michal Simek <monstr@monstr.eu>
- *
- * based on PowerPC of_device.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef _ASM_MICROBLAZE_OF_DEVICE_H
-#define _ASM_MICROBLAZE_OF_DEVICE_H
-#ifdef __KERNEL__
-
-#include <linux/device.h>
-#include <linux/of.h>
-
-/*
- * The of_device is a kind of "base class" that is a superset of
- * struct device for use by devices attached to an OF node and
- * probed using OF properties.
- */
-struct of_device {
-        struct device           dev; /* Generic device interface */
-        struct pdev_archdata    archdata;
-};
-
-extern ssize_t of_device_get_modalias(struct of_device *ofdev,
-                                        char *str, ssize_t len);
-
-extern struct of_device *of_device_alloc(struct device_node *np,
-                                         const char *bus_id,
-                                         struct device *parent);
-
-extern int of_device_uevent(struct device *dev,
-                            struct kobj_uevent_env *env);
-
-extern void of_device_make_bus_id(struct of_device *dev);
-
-/* This is just here during the transition */
-#include <linux/of_device.h>
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_MICROBLAZE_OF_DEVICE_H */
diff --git a/arch/microblaze/include/asm/of_platform.h b/arch/microblaze/include/asm/of_platform.h
deleted file mode 100644
index 37491276c6ca..000000000000
--- a/arch/microblaze/include/asm/of_platform.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
- *                      <benh@kernel.crashing.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MICROBLAZE_OF_PLATFORM_H
-#define _ASM_MICROBLAZE_OF_PLATFORM_H
-
-/* This is just here during the transition */
-#include <linux/of_platform.h>
-
-/*
- * The list of OF IDs below is used for matching bus types in the
- * system whose devices are to be exposed as of_platform_devices.
- *
- * This is the default list valid for most platforms. This file provides
- * functions who can take an explicit list if necessary though
- *
- * The search is always performed recursively looking for children of
- * the provided device_node and recursively if such a children matches
- * a bus type in the list
- */
-
-static const struct of_device_id of_default_bus_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .type = "plb5", },
-        { .type = "plb4", },
-        { .type = "opb", },
-        { .type = "simple", },
-        {},
-};
-
-/* Platform devices and busses creation */
-extern struct of_device *of_platform_device_create(struct device_node *np,
-                                                const char *bus_id,
-                                                struct device *parent);
-/* pseudo "matches" value to not do deep probe */
-#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
-
-extern int of_platform_bus_probe(struct device_node *root,
-                                const struct of_device_id *matches,
-                                struct device *parent);
-
-extern struct of_device *of_find_device_by_phandle(phandle ph);
-
-extern void of_instantiate_rtc(void);
-
-#endif /* _ASM_MICROBLAZE_OF_PLATFORM_H */
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 464ff32bee3d..4f268faa0126 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -23,8 +23,16 @@
 #ifdef __KERNEL__
 
 /* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT      (12)
-#define PAGE_SIZE       (_AC(1, UL) << PAGE_SHIFT)
+#if defined(CONFIG_MICROBLAZE_32K_PAGES)
+#define PAGE_SHIFT              15
+#elif defined(CONFIG_MICROBLAZE_16K_PAGES)
+#define PAGE_SHIFT              14
+#elif defined(CONFIG_MICROBLAZE_8K_PAGES)
+#define PAGE_SHIFT              13
+#else
+#define PAGE_SHIFT              12
+#endif
+#define PAGE_SIZE       (ASM_CONST(1) << PAGE_SHIFT)
 #define PAGE_MASK       (~(PAGE_SIZE-1))
 
 #define LOAD_OFFSET     ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR))
@@ -39,13 +47,6 @@
 #define PAGE_UP(addr)   (((addr)+((PAGE_SIZE)-1))&(~((PAGE_SIZE)-1)))
 #define PAGE_DOWN(addr) ((addr)&(~((PAGE_SIZE)-1)))
 
-/* align addr on a size boundary - adjust address up/down if needed */
-#define _ALIGN_UP(addr, size)   (((addr)+((size)-1))&(~((size)-1)))
-#define _ALIGN_DOWN(addr, size) ((addr)&(~((size)-1)))
-
-/* align addr on a size boundary - adjust address up if needed */
-#define _ALIGN(addr, size)      _ALIGN_UP(addr, size)
-
 #ifndef CONFIG_MMU
 /*
  * PAGE_OFFSET -- the first address of the first page of memory. When not
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index 0c77cda9f5d8..0c68764ab547 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -172,13 +172,8 @@ static inline int pci_has_flag(int flag)
 
 extern struct list_head hose_list;
 
-extern unsigned long pci_address_to_pio(phys_addr_t address);
 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 #else
-static inline unsigned long pci_address_to_pio(phys_addr_t address)
-{
-        return (unsigned long)-1;
-}
 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 {
         return 0;
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h
index e7d67a329bd7..101fa098f62a 100644
--- a/arch/microblaze/include/asm/prom.h
+++ b/arch/microblaze/include/asm/prom.h
@@ -20,9 +20,6 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
-#include <linux/of_fdt.h>
-#include <linux/proc_fs.h>
-#include <linux/platform_device.h>
 #include <asm/irq.h>
 #include <asm/atomic.h>
 
@@ -50,29 +47,10 @@ extern void pci_create_OF_bus_map(void);
  * OF address retreival & translation
  */
 
-/* Translate an OF address block into a CPU physical address
- */
-extern u64 of_translate_address(struct device_node *np, const u32 *addr);
-
-/* Extract an address from a device, returns the region size and
- * the address space flags too. The PCI version uses a BAR number
- * instead of an absolute index
- */
-extern const u32 *of_get_address(struct device_node *dev, int index,
-                        u64 *size, unsigned int *flags);
-extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no,
-                        u64 *size, unsigned int *flags);
-
-/* Get an address as a resource. Note that if your address is
- * a PIO address, the conversion will fail if the physical address
- * can't be internally converted to an IO token with
- * pci_address_to_pio(), that is because it's either called to early
- * or it can't be matched to any host bridge IO space
- */
-extern int of_address_to_resource(struct device_node *dev, int index,
-                                struct resource *r);
-extern int of_pci_address_to_resource(struct device_node *dev, int bar,
-                                struct resource *r);
+#ifdef CONFIG_PCI
+extern unsigned long pci_address_to_pio(phys_addr_t address);
+#define pci_address_to_pio pci_address_to_pio
+#endif  /* CONFIG_PCI */
 
 /* Parse the ibm,dma-window property of an OF node into the busno, phys and
  * size parameters.
@@ -88,69 +66,6 @@ struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
 /* Get the MAC address */
 extern const void *of_get_mac_address(struct device_node *np);
 
-/*
- * OF interrupt mapping
- */
-
-/* This structure is returned when an interrupt is mapped. The controller
- * field needs to be put() after use
- */
-
-#define OF_MAX_IRQ_SPEC         4 /* We handle specifiers of at most 4 cells */
-
-struct of_irq {
-        struct device_node *controller; /* Interrupt controller node */
-        u32 size; /* Specifier size */
-        u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
-};
-
-/**
- * of_irq_map_init - Initialize the irq remapper
- * @flags:      flags defining workarounds to enable
- *
- * Some machines have bugs in the device-tree which require certain workarounds
- * to be applied. Call this before any interrupt mapping attempts to enable
- * those workarounds.
- */
-#define OF_IMAP_OLDWORLD_MAC    0x00000001
-#define OF_IMAP_NO_PHANDLE      0x00000002
-
-extern void of_irq_map_init(unsigned int flags);
-
-/**
- * of_irq_map_raw - Low level interrupt tree parsing
- * @parent:     the device interrupt parent
- * @intspec:    interrupt specifier ("interrupts" property of the device)
- * @ointsize:   size of the passed in interrupt specifier
- * @addr:       address specifier (start of "reg" property of the device)
- * @out_irq:    structure of_irq filled by this function
- *
- * Returns 0 on success and a negative number on error
- *
- * This function is a low-level interrupt tree walking function. It
- * can be used to do a partial walk with synthetized reg and interrupts
- * properties, for example when resolving PCI interrupts when no device
- * node exist for the parent.
- *
- */
-
-extern int of_irq_map_raw(struct device_node *parent, const u32 *intspec,
-                        u32 ointsize, const u32 *addr,
-                        struct of_irq *out_irq);
-
-/**
- * of_irq_map_one - Resolve an interrupt for a device
- * @device:     the device whose interrupt is to be resolved
- * @index:      index of the interrupt to resolve
- * @out_irq:    structure of_irq filled by this function
- *
- * This function resolves an interrupt, walking the tree, for a given
- * device-tree node. It's the high level pendant to of_irq_map_raw().
- * It also implements the workarounds for OldWolrd Macs.
- */
-extern int of_irq_map_one(struct device_node *device, int index,
-                        struct of_irq *out_irq);
-
 /**
  * of_irq_map_pci - Resolve the interrupt for a PCI device
  * @pdev:       the device whose interrupt is to be resolved
@@ -163,20 +78,18 @@ extern int of_irq_map_one(struct device_node *device, int index,
  * resolving using the OF tree walking.
  */
 struct pci_dev;
+struct of_irq;
 extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
 
-extern int of_irq_to_resource(struct device_node *dev, int index,
-                        struct resource *r);
-
-/**
- * of_iomap - Maps the memory mapped IO for a given device_node
- * @device:     the device whose io range will be mapped
- * @index:      index of the io range
- *
- * Returns a pointer to the mapped memory
- */
-extern void __iomem *of_iomap(struct device_node *device, int index);
-
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
+
+/* These includes are put at the bottom because they may contain things
+ * that are overridden by this file.  Ideally they shouldn't be included
+ * by this file, but there are a bunch of .c files that currently depend
+ * on it.  Eventually they will be cleaned up. */
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
 #endif /* _ASM_MICROBLAZE_PROM_H */
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index e38abc7714b6..9578666e98ba 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -16,7 +16,7 @@
 #define PVR_MSR_BIT 0x400
 
 struct pvr_s {
-        unsigned pvr[16];
+        unsigned pvr[12];
 };
 
 /* The following taken from Xilinx's standalone BSP pvr.h */
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index 7f31394985e0..782b5c89248e 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -28,8 +28,6 @@ void disable_early_printk(void);
 void heartbeat(void);
 void setup_heartbeat(void);
 
-unsigned long long sched_clock(void);
-
 #   ifdef CONFIG_MMU
 extern void mmu_reset(void);
 extern void early_console_reg_tlb_alloc(unsigned int addr);
diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
index 48c4f0335e3f..e6a2284571dc 100644
--- a/arch/microblaze/include/asm/system.h
+++ b/arch/microblaze/include/asm/system.h
@@ -45,7 +45,6 @@ extern struct task_struct *_switch_to(struct thread_info *prev,
 #define smp_rmb()               rmb()
 #define smp_wmb()               wmb()
 
-void show_trace(struct task_struct *task, unsigned long *stack);
 void __bad_xchg(volatile void *ptr, int size);
 
 static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
@@ -101,10 +100,7 @@ extern struct dentry *of_debugfs_root;
  * MicroBlaze doesn't handle unaligned accesses in hardware.
  *
  * Based on this we force the IP header alignment in network drivers.
- * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
- * cacheline alignment of buffers.
  */
 #define NET_IP_ALIGN    2
-#define NET_SKB_PAD     L1_CACHE_BYTES
 
 #endif /* _ASM_MICROBLAZE_SYSTEM_H */
diff --git a/arch/microblaze/include/asm/topology.h b/arch/microblaze/include/asm/topology.h
index 96bcea5a9920..5428f333a02c 100644
--- a/arch/microblaze/include/asm/topology.h
+++ b/arch/microblaze/include/asm/topology.h
@@ -1,11 +1 @@
 #include <asm-generic/topology.h>
-
-#ifndef _ASM_MICROBLAZE_TOPOLOGY_H
-#define _ASM_MICROBLAZE_TOPOLOGY_H
-
-struct device_node;
-static inline int of_node_to_nid(struct device_node *device)
-{
-        return 0;
-}
-#endif /* _ASM_MICROBLAZE_TOPOLOGY_H */
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 26460d15b338..d840f4a2d3c9 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -359,7 +359,7 @@ extern long __user_bad(void);
         __copy_tofrom_user((__force void __user *)(to), \
                                 (void __user *)(from), (n))
 #define __copy_from_user_inatomic(to, from, n) \
-                copy_from_user((to), (from), (n))
+                __copy_from_user((to), (from), (n))
 
 static inline long copy_from_user(void *to,
                 const void __user *from, unsigned long n)
@@ -373,7 +373,7 @@ static inline long copy_from_user(void *to,
 #define __copy_to_user(to, from, n)     \
                 __copy_tofrom_user((void __user *)(to), \
                         (__force const void __user *)(from), (n))
-#define __copy_to_user_inatomic(to, from, n)    copy_to_user((to), (from), (n))
+#define __copy_to_user_inatomic(to, from, n) __copy_to_user((to), (from), (n))
 
 static inline long copy_to_user(void __user *to,
                 const void *from, unsigned long n)
diff --git a/arch/microblaze/include/asm/unwind.h b/arch/microblaze/include/asm/unwind.h
new file mode 100644
index 000000000000..d248b7de4b13
--- /dev/null
+++ b/arch/microblaze/include/asm/unwind.h
@@ -0,0 +1,29 @@
+/*
+ * Backtrace support for Microblaze
+ *
+ * Copyright (C) 2010  Digital Design Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __MICROBLAZE_UNWIND_H
+#define __MICROBLAZE_UNWIND_H
+
+struct stack_trace;
+
+struct trap_handler_info {
+        unsigned long start_addr;
+        unsigned long end_addr;
+        const char    *trap_name;
+};
+extern struct trap_handler_info microblaze_trap_handlers;
+
+extern const char _hw_exception_handler;
+extern const char ex_handler_unhandled;
+
+void microblaze_unwind(struct task_struct *task, struct stack_trace *trace);
+
+#endif  /* __MICROBLAZE_UNWIND_H */
+
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index e51bc1520825..f0cb5c26c81c 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -15,9 +15,9 @@ endif
 extra-y := head.o vmlinux.lds
 
 obj-y += dma.o exceptions.o \
-        hw_exception_handler.o init_task.o intc.o irq.o of_device.o \
-        of_platform.o process.o prom.o prom_parse.o ptrace.o \
-        setup.o signal.o sys_microblaze.o timer.o traps.o reset.o
+        hw_exception_handler.o init_task.o intc.o irq.o \
+        process.o prom.o prom_parse.o ptrace.o \
+        reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
 obj-y += cpu/
 
@@ -28,5 +28,6 @@ obj-$(CONFIG_MODULES)		+= microblaze_ksyms.o module.o
 obj-$(CONFIG_MMU)               += misc.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_FUNCTION_TRACER)   += ftrace.o mcount.o
+obj-$(CONFIG_KGDB)              += kgdb.o
 
 obj-y   += entry$(MMU).o
diff --git a/arch/microblaze/kernel/cpu/mb.c b/arch/microblaze/kernel/cpu/mb.c
index 4216eb1eaa32..7086e3564281 100644
--- a/arch/microblaze/kernel/cpu/mb.c
+++ b/arch/microblaze/kernel/cpu/mb.c
@@ -126,6 +126,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                         cpuinfo.pvr_user1,
                         cpuinfo.pvr_user2);
 
+        count += seq_printf(m, "Page size:\t%lu\n", PAGE_SIZE);
         return 0;
 }
 
diff --git a/arch/microblaze/kernel/entry-nommu.S b/arch/microblaze/kernel/entry-nommu.S
index 8cc18cd2cce6..ca84368570b6 100644
--- a/arch/microblaze/kernel/entry-nommu.S
+++ b/arch/microblaze/kernel/entry-nommu.S
@@ -588,3 +588,31 @@ sys_rt_sigsuspend_wrapper:
 #include "syscall_table.S"
 
 syscall_table_size=(.-sys_call_table)
+
+type_SYSCALL:
+        .ascii "SYSCALL\0"
+type_IRQ:
+        .ascii "IRQ\0"
+type_IRQ_PREEMPT:
+        .ascii "IRQ (PREEMPTED)\0"
+type_SYSCALL_PREEMPT:
+        .ascii " SYSCALL (PREEMPTED)\0"
+
+        /*
+         * Trap decoding for stack unwinder
+         * Tuples are (start addr, end addr, string)
+         * If return address lies on [start addr, end addr],
+         * unwinder displays 'string'
+         */
+
+        .align 4
+.global microblaze_trap_handlers
+microblaze_trap_handlers:
+        /* Exact matches come first */
+        .word ret_to_user  ; .word ret_to_user    ; .word type_SYSCALL
+        .word ret_from_intr; .word ret_from_intr  ; .word type_IRQ
+        /* Fuzzy matches go here */
+        .word ret_from_intr; .word no_intr_resched; .word type_IRQ_PREEMPT
+        .word work_pending ; .word no_work_pending; .word type_SYSCALL_PREEMPT
+        /* End of table */
+        .word 0             ; .word 0               ; .word 0
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index c0ede25c5b99..304882e56459 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -48,128 +48,107 @@
  */
 #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
         .macro  clear_bip
-        msrclr  r11, MSR_BIP
-        nop
+        msrclr  r0, MSR_BIP
         .endm
 
         .macro  set_bip
-        msrset  r11, MSR_BIP
-        nop
+        msrset  r0, MSR_BIP
         .endm
 
         .macro  clear_eip
-        msrclr  r11, MSR_EIP
-        nop
+        msrclr  r0, MSR_EIP
         .endm
 
         .macro  set_ee
-        msrset  r11, MSR_EE
-        nop
+        msrset  r0, MSR_EE
         .endm
 
         .macro  disable_irq
-        msrclr  r11, MSR_IE
-        nop
+        msrclr  r0, MSR_IE
         .endm
 
         .macro  enable_irq
-        msrset  r11, MSR_IE
-        nop
+        msrset  r0, MSR_IE
         .endm
 
         .macro  set_ums
-        msrset  r11, MSR_UMS
-        nop
-        msrclr  r11, MSR_VMS
-        nop
+        msrset  r0, MSR_UMS
+        msrclr  r0, MSR_VMS
         .endm
 
         .macro  set_vms
-        msrclr  r11, MSR_UMS
-        nop
-        msrset  r11, MSR_VMS
-        nop
+        msrclr  r0, MSR_UMS
+        msrset  r0, MSR_VMS
+        .endm
+
+        .macro  clear_ums
+        msrclr  r0, MSR_UMS
         .endm
 
         .macro  clear_vms_ums
-        msrclr  r11, MSR_VMS
-        nop
-        msrclr  r11, MSR_UMS
-        nop
+        msrclr  r0, MSR_VMS | MSR_UMS
         .endm
 #else
         .macro  clear_bip
         mfs     r11, rmsr
-        nop
         andi    r11, r11, ~MSR_BIP
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  set_bip
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_BIP
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  clear_eip
         mfs     r11, rmsr
-        nop
         andi    r11, r11, ~MSR_EIP
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  set_ee
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_EE
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  disable_irq
         mfs     r11, rmsr
-        nop
         andi    r11, r11, ~MSR_IE
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  enable_irq
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_IE
         mts     rmsr, r11
-        nop
         .endm
 
         .macro set_ums
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_VMS
         andni   r11, r11, MSR_UMS
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  set_vms
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_VMS
         andni   r11, r11, MSR_UMS
         mts     rmsr, r11
-        nop
+        .endm
+
+        .macro  clear_ums
+        mfs     r11, rmsr
+        andni   r11, r11, MSR_UMS
+        mts     rmsr,r11
         .endm
 
         .macro  clear_vms_ums
         mfs     r11, rmsr
-        nop
         andni   r11, r11, (MSR_VMS|MSR_UMS)
         mts     rmsr,r11
-        nop
         .endm
 #endif
 
@@ -180,18 +159,22 @@
 
 /* turn on virtual protected mode save */
 #define VM_ON           \
-        set_ums;                \
+        set_ums;        \
         rted    r0, 2f; \
-2: nop;
+        nop; \
+2:
 
 /* turn off virtual protected mode save and user mode save*/
 #define VM_OFF                  \
-        clear_vms_ums;                  \
+        clear_vms_ums;          \
         rted    r0, TOPHYS(1f); \
-1: nop;
+        nop; \
+1:
 
 #define SAVE_REGS \
         swi     r2, r1, PTO+PT_R2;      /* Save SDA */                  \
+        swi     r3, r1, PTO+PT_R3;                                      \
+        swi     r4, r1, PTO+PT_R4;                                      \
         swi     r5, r1, PTO+PT_R5;                                      \
         swi     r6, r1, PTO+PT_R6;                                      \
         swi     r7, r1, PTO+PT_R7;                                      \
@@ -218,14 +201,14 @@
         swi     r30, r1, PTO+PT_R30;                                    \
         swi     r31, r1, PTO+PT_R31;    /* Save current task reg */     \
         mfs     r11, rmsr;              /* save MSR */                  \
-        nop;                                                            \
         swi     r11, r1, PTO+PT_MSR;
 
 #define RESTORE_REGS \
         lwi     r11, r1, PTO+PT_MSR;                                    \
         mts     rmsr , r11;                                             \
-        nop;                                                            \
         lwi     r2, r1, PTO+PT_R2;      /* restore SDA */               \
+        lwi     r3, r1, PTO+PT_R3;                                      \
+        lwi     r4, r1, PTO+PT_R4;                                      \
         lwi     r5, r1, PTO+PT_R5;                                      \
         lwi     r6, r1, PTO+PT_R6;                                      \
         lwi     r7, r1, PTO+PT_R7;                                      \
@@ -252,6 +235,39 @@
         lwi     r30, r1, PTO+PT_R30;                                    \
         lwi     r31, r1, PTO+PT_R31;    /* Restore cur task reg */
 
+#define SAVE_STATE      \
+        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */     \
+        /* See if already in kernel mode.*/                             \
+        mfs     r1, rmsr;                                               \
+        andi    r1, r1, MSR_UMS;                                        \
+        bnei    r1, 1f;                                         \
+        /* Kernel-mode state save.  */                                  \
+        /* Reload kernel stack-ptr. */                                  \
+        lwi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP));                      \
+        /* FIXME: I can add these two lines to one */                   \
+        /* tophys(r1,r1); */                                            \
+        /* addik        r1, r1, -STATE_SAVE_SIZE; */                    \
+        addik   r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \
+        SAVE_REGS                                                       \
+        brid    2f;                                                     \
+        swi     r1, r1, PTO+PT_MODE;                                    \
+1:      /* User-mode state save.  */                                    \
+        lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\
+        tophys(r1,r1);                                                  \
+        lwi     r1, r1, TS_THREAD_INFO; /* get the thread info */       \
+        /* MS these three instructions can be added to one */           \
+        /* addik        r1, r1, THREAD_SIZE; */                         \
+        /* tophys(r1,r1); */                                            \
+        /* addik        r1, r1, -STATE_SAVE_SIZE; */                    \
+        addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \
+        SAVE_REGS                                                       \
+        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));                     \
+        swi     r11, r1, PTO+PT_R1; /* Store user SP.  */               \
+        swi     r0, r1, PTO + PT_MODE; /* Was in user-mode.  */         \
+        /* MS: I am clearing UMS even in case when I come from kernel space */ \
+        clear_ums;                                                      \
+2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
+
 .text
 
 /*
@@ -267,45 +283,23 @@
  * are masked. This is nice, means we don't have to CLI before state save
  */
 C_ENTRY(_user_exception):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         addi    r14, r14, 4     /* return address is 4 byte after call */
-        swi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* Save r11 */
-
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));/* See if already in kernel mode.*/
-        beqi    r11, 1f;                /* Jump ahead if coming from user */
-/* Kernel-mode state save. */
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
-        tophys(r1,r11);
-        swi     r11, r1, (PT_R1-PT_SIZE); /* Save original SP. */
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
-
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */
-        SAVE_REGS
-
-        addi    r11, r0, 1;             /* Was in kernel-mode. */
-        swi     r11, r1, PTO+PT_MODE; /* pt_regs -> kernel mode */
-        brid    2f;
-        nop;                            /* Fill delay slot */
+        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
 
-/* User-mode state save.  */
-1:
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
         lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
         tophys(r1,r1);
         lwi     r1, r1, TS_THREAD_INFO; /* get stack from task_struct */
-/* calculate kernel stack pointer from task struct 8k */
-        addik   r1, r1, THREAD_SIZE;
-        tophys(r1,r1);
-
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */
+        /* MS these three instructions can be added to one */
+        /* addik        r1, r1, THREAD_SIZE; */
+        /* tophys(r1,r1); */
+        /* addik        r1, r1, -STATE_SAVE_SIZE; */
+        addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE;
         SAVE_REGS
 
-        swi     r0, r1, PTO+PT_MODE;                    /* Was in user-mode. */
         lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         swi     r11, r1, PTO+PT_R1;             /* Store user SP.  */
-        addi    r11, r0, 1;
-        swi     r11, r0, TOPHYS(PER_CPU(KM));   /* Now we're in kernel-mode.  */
-2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
+        clear_ums;
+        lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
         /* Save away the syscall number.  */
         swi     r12, r1, PTO+PT_R0;
         tovirt(r1,r1)
@@ -316,10 +310,8 @@ C_ENTRY(_user_exception):
  * register should point to the location where
  * the called function should return.  [note that MAKE_SYS_CALL uses label 1] */
 
-        # Step into virtual mode.
-        set_vms;
-        addik   r11, r0, 3f
-        rtid    r11, 0
+        /* Step into virtual mode */
+        rtbd    r0, 3f
         nop
 3:
         lwi     r11, CURRENT_TASK, TS_THREAD_INFO /* get thread info */
@@ -363,24 +355,17 @@ C_ENTRY(_user_exception):
         # Find and jump into the syscall handler.
         lwi     r12, r12, sys_call_table
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_trap-8
+        addi    r15, r0, ret_from_trap-8
         bra     r12
 
         /* The syscall number is invalid, return an error.  */
 5:
+        rtsd    r15, 8;         /* looks like a normal subroutine return */
         addi    r3, r0, -ENOSYS;
-        rtsd    r15,8;          /* looks like a normal subroutine return */
-        or      r0, r0, r0
-
 
 /* Entry point used to return from a syscall/trap */
 /* We re-enable BIP bit before state restore */
 C_ENTRY(ret_from_trap):
-        set_bip;                        /*  Ints masked for state restore*/
-        lwi     r11, r1, PTO+PT_MODE;
-/* See if returning to kernel mode, if so, skip resched &c.  */
-        bnei    r11, 2f;
-
         swi     r3, r1, PTO + PT_R3
         swi     r4, r1, PTO + PT_R4
 
@@ -413,32 +398,19 @@ C_ENTRY(ret_from_trap):
         andi    r11, r11, _TIF_SIGPENDING;
         beqi    r11, 1f;                /* Signals to handle, handle them */
 
-        la      r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
+        addik   r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
         addi    r7, r0, 1;              /* Arg 3: int in_syscall */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0;             /* Arg 2: sigset_t *oldset */
 
 /* Finally, return to user state.  */
-1:
-        lwi     r3, r1, PTO + PT_R3; /* restore syscall result */
-        lwi     r4, r1, PTO + PT_R4;
-
-        swi     r0, r0, PER_CPU(KM);    /* Now officially in user state. */
+1:      set_bip;                        /*  Ints masked for state restore */
         swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
         VM_OFF;
         tophys(r1,r1);
         RESTORE_REGS;
         addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
         lwi     r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */
-        bri     6f;
-
-/* Return to kernel state.  */
-2:      VM_OFF;
-        tophys(r1,r1);
-        RESTORE_REGS;
-        addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
-        tovirt(r1,r1);
-6:
 TRAP_return:            /* Make global symbol for debugging */
         rtbd    r14, 0; /* Instructions to return from an IRQ */
         nop;
@@ -450,12 +422,11 @@ TRAP_return:		/* Make global symbol for debugging */
 C_ENTRY(sys_fork_wrapper):
         addi    r5, r0, SIGCHLD                 /* Arg 0: flags */
         lwi     r6, r1, PTO+PT_R1       /* Arg 1: child SP (use parent's) */
-        la      r7, r1, PTO                     /* Arg 2: parent context */
+        addik   r7, r1, PTO                     /* Arg 2: parent context */
         add     r8. r0, r0                      /* Arg 3: (unused) */
         add     r9, r0, r0;                     /* Arg 4: (unused) */
-        add     r10, r0, r0;                    /* Arg 5: (unused) */
         brid    do_fork         /* Do real work (tail-call) */
-        nop;
+        add     r10, r0, r0;                    /* Arg 5: (unused) */
 
 /* This the initial entry point for a new child thread, with an appropriate
    stack in place that makes it look the the child is in the middle of an
@@ -466,35 +437,31 @@ C_ENTRY(ret_from_fork):
         bralid  r15, schedule_tail; /* ...which is schedule_tail's arg */
         add     r3, r5, r0;     /* switch_thread returns the prev task */
                                 /* ( in the delay slot ) */
-        add     r3, r0, r0;     /* Child's fork call should return 0. */
         brid    ret_from_trap;  /* Do normal trap return */
-        nop;
+        add     r3, r0, r0;     /* Child's fork call should return 0. */
 
 C_ENTRY(sys_vfork):
         brid    microblaze_vfork        /* Do real work (tail-call) */
-        la      r5, r1, PTO
+        addik   r5, r1, PTO
 
 C_ENTRY(sys_clone):
         bnei    r6, 1f;                 /* See if child SP arg (arg 1) is 0. */
-        lwi     r6, r1, PTO+PT_R1;      /* If so, use paret's stack ptr */
-1:      la      r7, r1, PTO;                    /* Arg 2: parent context */
+        lwi     r6, r1, PTO + PT_R1;    /* If so, use paret's stack ptr */
+1:      addik   r7, r1, PTO;                    /* Arg 2: parent context */
         add     r8, r0, r0;                     /* Arg 3: (unused) */
         add     r9, r0, r0;                     /* Arg 4: (unused) */
-        add     r10, r0, r0;                    /* Arg 5: (unused) */
         brid    do_fork         /* Do real work (tail-call) */
-        nop;
+        add     r10, r0, r0;                    /* Arg 5: (unused) */
 
 C_ENTRY(sys_execve):
-        la      r8, r1, PTO;            /* add user context as 4th arg */
         brid    microblaze_execve;      /* Do real work (tail-call).*/
-        nop;
+        addik   r8, r1, PTO;            /* add user context as 4th arg */
 
 C_ENTRY(sys_rt_sigreturn_wrapper):
         swi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
         swi     r4, r1, PTO+PT_R4;
-        la      r5, r1, PTO;            /* add user context as 1st arg */
         brlid   r15, sys_rt_sigreturn   /* Do real work */
-        nop;
+        addik   r5, r1, PTO;            /* add user context as 1st arg */
         lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
         lwi     r4, r1, PTO+PT_R4;
         bri ret_from_trap /* fall through will not work here due to align */
@@ -503,83 +470,23 @@ C_ENTRY(sys_rt_sigreturn_wrapper):
 /*
  * HW EXCEPTION rutine start
  */
-
-#define SAVE_STATE      \
-        swi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* Save r11 */  \
-        set_bip;        /*equalize initial state for all possible entries*/\
-        clear_eip;                                                      \
-        enable_irq;                                                     \
-        set_ee;                                                         \
-        /* See if already in kernel mode.*/                             \
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));                           \
-        beqi    r11, 1f;                /* Jump ahead if coming from user */\
-        /* Kernel-mode state save.  */                                  \
-        /* Reload kernel stack-ptr. */                                  \
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));                     \
-        tophys(r1,r11);                                                 \
-        swi     r11, r1, (PT_R1-PT_SIZE); /* Save original SP. */       \
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */\
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */\
-        /* store return registers separately because                    \
-         * this macros is use for others exceptions */                  \
-        swi     r3, r1, PTO + PT_R3;                                    \
-        swi     r4, r1, PTO + PT_R4;                                    \
-        SAVE_REGS                                                       \
-        /* PC, before IRQ/trap - this is one instruction above */       \
-        swi     r17, r1, PTO+PT_PC;                                     \
-                                                                        \
-        addi    r11, r0, 1;             /* Was in kernel-mode.  */      \
-        swi     r11, r1, PTO+PT_MODE;                                   \
-        brid    2f;                                                     \
-        nop;                            /* Fill delay slot */           \
-1:      /* User-mode state save.  */                                    \
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */\
-        lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\
-        tophys(r1,r1);                                                  \
-        lwi     r1, r1, TS_THREAD_INFO; /* get the thread info */       \
-        addik   r1, r1, THREAD_SIZE;    /* calculate kernel stack pointer */\
-        tophys(r1,r1);                                                  \
-                                                                        \
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */\
-        /* store return registers separately because this macros        \
-         * is use for others exceptions */                              \
-        swi     r3, r1, PTO + PT_R3;                                    \
-        swi     r4, r1, PTO + PT_R4;                                    \
-        SAVE_REGS                                                       \
-        /* PC, before IRQ/trap - this is one instruction above FIXME*/  \
-        swi     r17, r1, PTO+PT_PC;                                     \
-                                                                        \
-        swi     r0, r1, PTO+PT_MODE; /* Was in user-mode.  */           \
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));                     \
-        swi     r11, r1, PTO+PT_R1; /* Store user SP.  */               \
-        addi    r11, r0, 1;                                             \
-        swi     r11, r0, TOPHYS(PER_CPU(KM)); /* Now we're in kernel-mode.*/\
-2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));        \
-        /* Save away the syscall number.  */                            \
-        swi     r0, r1, PTO+PT_R0;                                      \
-        tovirt(r1,r1)
-
 C_ENTRY(full_exception_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         /* adjust exception address for privileged instruction
          * for finding where is it */
         addik   r17, r17, -4
         SAVE_STATE /* Save registers */
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* FIXME this can be store directly in PT_ESR reg.
          * I tested it but there is a fault */
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc - 8
-        la      r5, r1, PTO              /* parameter struct pt_regs * regs */
+        addik   r15, r0, ret_from_exc - 8
         mfs     r6, resr
-        nop
         mfs     r7, rfsr;               /* save FSR */
-        nop
         mts     rfsr, r0;       /* Clear sticky fsr */
-        nop
-        la      r12, r0, full_exception
-        set_vms;
-        rtbd    r12, 0;
-        nop;
+        rted    r0, full_exception
+        addik   r5, r1, PTO              /* parameter struct pt_regs * regs */
 
 /*
  * Unaligned data trap.
@@ -592,19 +499,27 @@ C_ENTRY(full_exception_trap):
  * The assembler routine is in "arch/microblaze/kernel/hw_exception_handler.S"
  */
 C_ENTRY(unaligned_data_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
+        /* MS: I have to save r11 value and then restore it because
+         * set_bit, clear_eip, set_ee use r11 as temp register if MSR
+         * instructions are not used. We don't need to do if MSR instructions
+         * are used and they use r0 instead of r11.
+         * I am using ENTRY_SP which should be primary used only for stack
+         * pointer saving. */
+        swi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
+        set_bip;        /* equalize initial state for all possible entries */
+        clear_eip;
+        set_ee;
+        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         SAVE_STATE              /* Save registers.*/
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc-8
+        addik   r15, r0, ret_from_exc-8
         mfs     r3, resr                /* ESR */
-        nop
         mfs     r4, rear                /* EAR */
-        nop
-        la      r7, r1, PTO             /* parameter struct pt_regs * regs */
-        la      r12, r0, _unaligned_data_exception
-        set_vms;
-        rtbd    r12, 0; /* interrupts enabled */
-        nop;
+        rtbd    r0, _unaligned_data_exception
+        addik   r7, r1, PTO             /* parameter struct pt_regs * regs */
 
 /*
  * Page fault traps.
@@ -625,38 +540,32 @@ C_ENTRY(unaligned_data_trap):
  */
 /* data and intruction trap - which is choose is resolved int fault.c */
 C_ENTRY(page_fault_data_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         SAVE_STATE              /* Save registers.*/
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc-8
-        la      r5, r1, PTO             /* parameter struct pt_regs * regs */
+        addik   r15, r0, ret_from_exc-8
         mfs     r6, rear                /* parameter unsigned long address */
-        nop
         mfs     r7, resr                /* parameter unsigned long error_code */
-        nop
-        la      r12, r0, do_page_fault
-        set_vms;
-        rtbd    r12, 0; /* interrupts enabled */
-        nop;
+        rted    r0, do_page_fault
+        addik   r5, r1, PTO             /* parameter struct pt_regs * regs */
 
 C_ENTRY(page_fault_instr_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         SAVE_STATE              /* Save registers.*/
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc-8
-        la      r5, r1, PTO             /* parameter struct pt_regs * regs */
+        addik   r15, r0, ret_from_exc-8
         mfs     r6, rear                /* parameter unsigned long address */
-        nop
         ori     r7, r0, 0               /* parameter unsigned long error_code */
-        la      r12, r0, do_page_fault
-        set_vms;
-        rtbd    r12, 0; /* interrupts enabled */
-        nop;
+        rted    r0, do_page_fault
+        addik   r5, r1, PTO             /* parameter struct pt_regs * regs */
 
 /* Entry point used to return from an exception.  */
 C_ENTRY(ret_from_exc):
-        set_bip;                        /*  Ints masked for state restore*/
-        lwi     r11, r1, PTO+PT_MODE;
+        lwi     r11, r1, PTO + PT_MODE;
         bnei    r11, 2f;                /* See if returning to kernel mode, */
                                         /* ... if so, skip resched &c.  */
 
@@ -687,32 +596,27 @@ C_ENTRY(ret_from_exc):
          * traps), but signal handlers may want to examine or change the
          * complete register state.  Here we save anything not saved by
          * the normal entry sequence, so that it may be safely restored
-         * (in a possibly modified form) after do_signal returns.
-         * store return registers separately because this macros is use
-         * for others exceptions */
-        la      r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
+         * (in a possibly modified form) after do_signal returns. */
+        addik   r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
         addi    r7, r0, 0;              /* Arg 3: int in_syscall */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0;             /* Arg 2: sigset_t *oldset */
 
 /* Finally, return to user state.  */
-1:      swi     r0, r0, PER_CPU(KM);    /* Now officially in user state. */
+1:      set_bip;                        /* Ints masked for state restore */
         swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
         VM_OFF;
         tophys(r1,r1);
 
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
         RESTORE_REGS;
         addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
 
         lwi     r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer. */
         bri     6f;
 /* Return to kernel state.  */
-2:      VM_OFF;
+2:      set_bip;                        /* Ints masked for state restore */
+        VM_OFF;
         tophys(r1,r1);
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
         RESTORE_REGS;
         addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
 
@@ -736,36 +640,23 @@ C_ENTRY(_interrupt):
 /* MS: we are in physical address */
 /* Save registers, switch to proper stack, convert SP to virtual.*/
         swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
-        swi     r11, r0, TOPHYS(PER_CPU(R11_SAVE));
         /* MS: See if already in kernel mode. */
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));
-        beqi    r11, 1f; /* MS: Jump ahead if coming from user */
+        mfs     r1, rmsr
+        nop
+        andi    r1, r1, MSR_UMS
+        bnei    r1, 1f
 
 /* Kernel-mode state save. */
-        or      r11, r1, r0
-        tophys(r1,r11); /* MS: I have in r1 physical address where stack is */
-/* MS: Save original SP - position PT_R1 to next stack frame 4 *1 - 152*/
-        swi     r11, r1, (PT_R1 - PT_SIZE);
-/* MS: restore r11 because of saving in SAVE_REGS */
-        lwi     r11, r0, TOPHYS(PER_CPU(R11_SAVE));
+        lwi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
+        tophys(r1,r1); /* MS: I have in r1 physical address where stack is */
         /* save registers */
 /* MS: Make room on the stack -> activation record */
         addik   r1, r1, -STATE_SAVE_SIZE;
-/* MS: store return registers separately because
- * this macros is use for others exceptions */
-        swi     r3, r1, PTO + PT_R3;
-        swi     r4, r1, PTO + PT_R4;
         SAVE_REGS
-        /* MS: store mode */
-        addi    r11, r0, 1; /* MS: Was in kernel-mode. */
-        swi     r11, r1, PTO + PT_MODE; /* MS: and save it */
         brid    2f;
-        nop; /* MS: Fill delay slot */
-
+        swi     r1, r1, PTO + PT_MODE; /* 0 - user mode, 1 - kernel mode */
 1:
 /* User-mode state save. */
-/* MS: restore r11 -> FIXME move before SAVE_REG */
-        lwi     r11, r0, TOPHYS(PER_CPU(R11_SAVE));
  /* MS: get the saved current */
         lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
         tophys(r1,r1);
@@ -774,27 +665,18 @@ C_ENTRY(_interrupt):
         tophys(r1,r1);
         /* save registers */
         addik   r1, r1, -STATE_SAVE_SIZE;
-        swi     r3, r1, PTO+PT_R3;
-        swi     r4, r1, PTO+PT_R4;
         SAVE_REGS
         /* calculate mode */
         swi     r0, r1, PTO + PT_MODE;
         lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         swi     r11, r1, PTO+PT_R1;
-        /* setup kernel mode to KM */
-        addi    r11, r0, 1;
-        swi     r11, r0, TOPHYS(PER_CPU(KM));
-
+        clear_ums;
 2:
         lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
-        swi     r0, r1, PTO + PT_R0;
         tovirt(r1,r1)
-        la      r5, r1, PTO;
-        set_vms;
-        la      r11, r0, do_IRQ;
-        la      r15, r0, irq_call;
-irq_call:rtbd   r11, 0;
-        nop;
+        addik   r15, r0, irq_call;
+irq_call:rtbd   r0, do_IRQ;
+        addik   r5, r1, PTO;
 
 /* MS: we are in virtual mode */
 ret_from_irq:
@@ -815,7 +697,7 @@ ret_from_irq:
         beqid   r11, no_intr_resched
 /* Handle a signal return; Pending signals should be in r18. */
         addi    r7, r0, 0; /* Arg 3: int in_syscall */
-        la      r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
+        addik   r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0; /* Arg 2: sigset_t *oldset */
 
@@ -823,12 +705,9 @@ ret_from_irq:
 no_intr_resched:
     /* Disable interrupts, we are now committed to the state restore */
         disable_irq
-        swi     r0, r0, PER_CPU(KM); /* MS: Now officially in user state. */
         swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE);
         VM_OFF;
         tophys(r1,r1);
-        lwi     r3, r1, PTO + PT_R3; /* MS: restore saved r3, r4 registers */
-        lwi     r4, r1, PTO + PT_R4;
         RESTORE_REGS
         addik   r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */
         lwi     r1, r1, PT_R1 - PT_SIZE;
@@ -857,8 +736,6 @@ restore:
 #endif
         VM_OFF /* MS: turn off MMU */
         tophys(r1,r1)
-        lwi     r3, r1, PTO + PT_R3; /* MS: restore saved r3, r4 registers */
-        lwi     r4, r1, PTO + PT_R4;
         RESTORE_REGS
         addik   r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */
         tovirt(r1,r1);
@@ -868,86 +745,91 @@ IRQ_return: /* MS: Make global symbol for debugging */
         nop
 
 /*
- * `Debug' trap
- *  We enter dbtrap in "BIP" (breakpoint) mode.
- *  So we exit the breakpoint mode with an 'rtbd' and proceed with the
- *  original dbtrap.
- *  however, wait to save state first
+ * Debug trap for KGDB. Enter to _debug_exception by brki r16, 0x18
+ * and call handling function with saved pt_regs
  */
 C_ENTRY(_debug_exception):
         /* BIP bit is set on entry, no interrupts can occur */
         swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
 
-        swi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* Save r11 */
-        set_bip;        /*equalize initial state for all possible entries*/
-        clear_eip;
-        enable_irq;
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));/* See if already in kernel mode.*/
-        beqi    r11, 1f;                /* Jump ahead if coming from user */
-        /* Kernel-mode state save.  */
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
-        tophys(r1,r11);
-        swi     r11, r1, (PT_R1-PT_SIZE); /* Save original SP. */
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
+        mfs     r1, rmsr
+        nop
+        andi    r1, r1, MSR_UMS
+        bnei    r1, 1f
+/* MS: Kernel-mode state save - kgdb */
+        lwi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
 
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */
-        swi     r3, r1, PTO + PT_R3;
-        swi     r4, r1, PTO + PT_R4;
+        /* BIP bit is set on entry, no interrupts can occur */
+        addik   r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE;
         SAVE_REGS;
+        /* save all regs to pt_reg structure */
+        swi     r0, r1, PTO+PT_R0;      /* R0 must be saved too */
+        swi     r14, r1, PTO+PT_R14     /* rewrite saved R14 value */
+        swi     r16, r1, PTO+PT_R16
+        swi     r16, r1, PTO+PT_PC; /* PC and r16 are the same */
+        swi     r17, r1, PTO+PT_R17
+        /* save special purpose registers to pt_regs */
+        mfs     r11, rear;
+        swi     r11, r1, PTO+PT_EAR;
+        mfs     r11, resr;
+        swi     r11, r1, PTO+PT_ESR;
+        mfs     r11, rfsr;
+        swi     r11, r1, PTO+PT_FSR;
+
+        /* stack pointer is in physical address at it is decrease
+         * by STATE_SAVE_SIZE but we need to get correct R1 value */
+        addik   r11, r1, CONFIG_KERNEL_START - CONFIG_KERNEL_BASE_ADDR + STATE_SAVE_SIZE;
+        swi     r11, r1, PTO+PT_R1
+        /* MS: r31 - current pointer isn't changed */
+        tovirt(r1,r1)
+#ifdef CONFIG_KGDB
+        addi    r5, r1, PTO /* pass pt_reg address as the first arg */
+        la      r15, r0, dbtrap_call; /* return address */
+        rtbd    r0, microblaze_kgdb_break
+        nop;
+#endif
+        /* MS: Place handler for brki from kernel space if KGDB is OFF.
+         * It is very unlikely that another brki instruction is called. */
+        bri 0
 
-        addi    r11, r0, 1;             /* Was in kernel-mode.  */
-        swi     r11, r1, PTO + PT_MODE;
-        brid    2f;
-        nop;                            /* Fill delay slot */
-1:      /* User-mode state save.  */
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
-        lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
+/* MS: User-mode state save - gdb */
+1:      lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
         tophys(r1,r1);
         lwi     r1, r1, TS_THREAD_INFO; /* get the thread info */
         addik   r1, r1, THREAD_SIZE;    /* calculate kernel stack pointer */
         tophys(r1,r1);
 
         addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */
-        swi     r3, r1, PTO + PT_R3;
-        swi     r4, r1, PTO + PT_R4;
         SAVE_REGS;
-
-        swi     r0, r1, PTO+PT_MODE; /* Was in user-mode.  */
+        swi     r17, r1, PTO+PT_R17;
+        swi     r16, r1, PTO+PT_R16;
+        swi     r16, r1, PTO+PT_PC;     /* Save LP */
+        swi     r0, r1, PTO + PT_MODE; /* Was in user-mode.  */
         lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         swi     r11, r1, PTO+PT_R1; /* Store user SP.  */
-        addi    r11, r0, 1;
-        swi     r11, r0, TOPHYS(PER_CPU(KM));   /* Now we're in kernel-mode.  */
-2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
-        /* Save away the syscall number.  */
-        swi     r0, r1, PTO+PT_R0;
+        lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
         tovirt(r1,r1)
-
-        addi    r5, r0, SIGTRAP              /* send the trap signal */
-        add     r6, r0, CURRENT_TASK; /* Get current task ptr into r11 */
-        addk    r7, r0, r0                   /* 3rd param zero */
-
         set_vms;
-        la      r11, r0, send_sig;
-        la      r15, r0, dbtrap_call;
-dbtrap_call:    rtbd    r11, 0;
-        nop;
+        addik   r5, r1, PTO;
+        addik   r15, r0, dbtrap_call;
+dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */
+        rtbd    r0, sw_exception
+        nop
 
-        set_bip;                        /*  Ints masked for state restore*/
-        lwi     r11, r1, PTO+PT_MODE;
+        /* MS: The first instruction for the second part of the gdb/kgdb */
+        set_bip; /* Ints masked for state restore */
+        lwi     r11, r1, PTO + PT_MODE;
         bnei    r11, 2f;
-
+/* MS: Return to user space - gdb */
         /* Get current task ptr into r11 */
         lwi     r11, CURRENT_TASK, TS_THREAD_INFO;      /* get thread info */
         lwi     r11, r11, TI_FLAGS;     /* get flags in thread info */
         andi    r11, r11, _TIF_NEED_RESCHED;
         beqi    r11, 5f;
 
-/* Call the scheduler before returning from a syscall/trap. */
-
+        /* Call the scheduler before returning from a syscall/trap. */
         bralid  r15, schedule;  /* Call scheduler */
         nop;                            /* delay slot */
-        /* XXX Is PT_DTRACE handling needed here? */
-        /* XXX m68knommu also checks TASK_STATE & TASK_COUNTER here.  */
 
         /* Maybe handle a signal */
 5:      lwi     r11, CURRENT_TASK, TS_THREAD_INFO;      /* get thread info */
@@ -955,54 +837,40 @@ dbtrap_call:	rtbd	r11, 0;
         andi    r11, r11, _TIF_SIGPENDING;
         beqi    r11, 1f;                /* Signals to handle, handle them */
 
-/* Handle a signal return; Pending signals should be in r18.  */
-        /* Not all registers are saved by the normal trap/interrupt entry
-           points (for instance, call-saved registers (because the normal
-           C-compiler calling sequence in the kernel makes sure they're
-           preserved), and call-clobbered registers in the case of
-           traps), but signal handlers may want to examine or change the
-           complete register state.  Here we save anything not saved by
-           the normal entry sequence, so that it may be safely restored
-           (in a possibly modified form) after do_signal returns.  */
-
-        la      r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
+        addik   r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
         addi  r7, r0, 0;        /* Arg 3: int in_syscall */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0;             /* Arg 2: sigset_t *oldset */
 
-
 /* Finally, return to user state.  */
-1:      swi     r0, r0, PER_CPU(KM);    /* Now officially in user state. */
-        swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
+1:      swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
         VM_OFF;
         tophys(r1,r1);
-
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
+        /* MS: Restore all regs */
         RESTORE_REGS
-        addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
-
-
-        lwi     r1, r1, PT_R1 - PT_SIZE;
-                                        /* Restore user stack pointer. */
-        bri     6f;
+        lwi     r17, r1, PTO+PT_R17;
+        lwi     r16, r1, PTO+PT_R16;
+        addik   r1, r1, STATE_SAVE_SIZE  /* Clean up stack space */
+        lwi     r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer */
+DBTRAP_return_user: /* MS: Make global symbol for debugging */
+        rtbd    r16, 0; /* MS: Instructions to return from a debug trap */
+        nop;
 
-/* Return to kernel state.  */
+/* MS: Return to kernel state - kgdb */
 2:      VM_OFF;
         tophys(r1,r1);
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
+        /* MS: Restore all regs */
         RESTORE_REGS
-        addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
-
+        lwi     r14, r1, PTO+PT_R14;
+        lwi     r16, r1, PTO+PT_PC;
+        lwi     r17, r1, PTO+PT_R17;
+        addik   r1, r1, STATE_SAVE_SIZE; /* MS: Clean up stack space */
         tovirt(r1,r1);
-6:
-DBTRAP_return:          /* Make global symbol for debugging */
-        rtbd    r14, 0; /* Instructions to return from an IRQ */
+DBTRAP_return_kernel: /* MS: Make global symbol for debugging */
+        rtbd    r16, 0; /* MS: Instructions to return from a debug trap */
         nop;
 
 
-
 ENTRY(_switch_to)
         /* prepare return value */
         addk    r3, r0, CURRENT_TASK
@@ -1037,16 +905,12 @@ ENTRY(_switch_to)
         swi     r30, r11, CC_R30
         /* special purpose registers */
         mfs     r12, rmsr
-        nop
         swi     r12, r11, CC_MSR
         mfs     r12, rear
-        nop
         swi     r12, r11, CC_EAR
         mfs     r12, resr
-        nop
         swi     r12, r11, CC_ESR
         mfs     r12, rfsr
-        nop
         swi     r12, r11, CC_FSR
 
         /* update r31, the current-give me pointer to task which will be next */
@@ -1085,10 +949,8 @@ ENTRY(_switch_to)
         /* special purpose registers */
         lwi     r12, r11, CC_FSR
         mts     rfsr, r12
-        nop
         lwi     r12, r11, CC_MSR
         mts     rmsr, r12
-        nop
 
         rtsd    r15, 8
         nop
@@ -1096,15 +958,6 @@ ENTRY(_switch_to)
 ENTRY(_reset)
         brai    0x70; /* Jump back to FS-boot */
 
-ENTRY(_break)
-        mfs     r5, rmsr
-        nop
-        swi     r5, r0, 0x250 + TOPHYS(r0_ram)
-        mfs     r5, resr
-        nop
-        swi     r5, r0, 0x254 + TOPHYS(r0_ram)
-        bri     0
-
         /* These are compiled and loaded into high memory, then
          * copied into place in mach_early_setup */
         .section        .init.ivt, "ax"
@@ -1116,14 +969,38 @@ ENTRY(_break)
         nop
         brai    TOPHYS(_user_exception); /* syscall handler */
         brai    TOPHYS(_interrupt);     /* Interrupt handler */
-        brai    TOPHYS(_break);         /* nmi trap handler */
+        brai    TOPHYS(_debug_exception);       /* debug trap handler */
         brai    TOPHYS(_hw_exception_handler);  /* HW exception handler */
 
-        .org    0x60
-        brai    TOPHYS(_debug_exception);       /* debug trap handler*/
-
 .section .rodata,"a"
 #include "syscall_table.S"
 
 syscall_table_size=(.-sys_call_table)
 
+type_SYSCALL:
+        .ascii "SYSCALL\0"
+type_IRQ:
+        .ascii "IRQ\0"
+type_IRQ_PREEMPT:
+        .ascii "IRQ (PREEMPTED)\0"
+type_SYSCALL_PREEMPT:
+        .ascii " SYSCALL (PREEMPTED)\0"
+
+        /*
+         * Trap decoding for stack unwinder
+         * Tuples are (start addr, end addr, string)
+         * If return address lies on [start addr, end addr],
+         * unwinder displays 'string'
+         */
+
+        .align 4
+.global microblaze_trap_handlers
+microblaze_trap_handlers:
+        /* Exact matches come first */
+        .word ret_from_trap; .word ret_from_trap   ; .word type_SYSCALL
+        .word ret_from_irq ; .word ret_from_irq    ; .word type_IRQ
+        /* Fuzzy matches go here */
+        .word ret_from_irq ; .word no_intr_resched ; .word type_IRQ_PREEMPT
+        .word ret_from_trap; .word TRAP_return     ; .word type_SYSCALL_PREEMPT
+        /* End of table */
+        .word 0               ; .word 0               ; .word 0
diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c
index 02cbdfe5aa8d..b98ee8d0c1cd 100644
--- a/arch/microblaze/kernel/exceptions.c
+++ b/arch/microblaze/kernel/exceptions.c
@@ -48,12 +48,17 @@ void die(const char *str, struct pt_regs *fp, long err)
         do_exit(err);
 }
 
+/* for user application debugging */
+void sw_exception(struct pt_regs *regs)
+{
+        _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16);
+}
+
 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 {
         siginfo_t info;
 
         if (kernel_mode(regs)) {
-                debugger(regs);
                 die("Exception in kernel mode", regs, signr);
         }
         info.si_signo = signr;
@@ -143,7 +148,7 @@ asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,
 #ifdef CONFIG_MMU
         case MICROBLAZE_PRIVILEGED_EXCEPTION:
                 pr_debug(KERN_WARNING "Privileged exception\n");
-                /* "brk r0,r0" - used as debug breakpoint */
+                /* "brk r0,r0" - used as debug breakpoint - old toolchain */
                 if (get_user(code, (unsigned long *)regs->pc) == 0
                         && code == 0x980c0000) {
                         _exception(SIGTRAP, regs, TRAP_BRKPT, addr);
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 1bf739888260..42434008209e 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -43,10 +43,10 @@
 .global empty_zero_page
 .align 12
 empty_zero_page:
-        .space  4096
+        .space  PAGE_SIZE
 .global swapper_pg_dir
 swapper_pg_dir:
-        .space  4096
+        .space  PAGE_SIZE
 
 #endif /* CONFIG_MMU */
 
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 995a2123635b..781195438ee6 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -78,9 +78,6 @@
 #include <asm/asm-offsets.h>
 
 /* Helpful Macros */
-#ifndef CONFIG_MMU
-#define EX_HANDLER_STACK_SIZ    (4*19)
-#endif
 #define NUM_TO_REG(num)         r ## num
 
 #ifdef CONFIG_MMU
@@ -988,6 +985,7 @@ ex_unaligned_fixup:
 .end _unaligned_data_exception
 #endif /* CONFIG_MMU */
 
+.global ex_handler_unhandled
 ex_handler_unhandled:
 /* FIXME add handle function for unhandled exception - dump register */
         bri 0
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 8f120aca123d..a9345fb4906a 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -17,26 +17,17 @@
 #include <linux/seq_file.h>
 #include <linux/kernel_stat.h>
 #include <linux/irq.h>
+#include <linux/of_irq.h>
 
 #include <asm/prom.h>
 
-unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
-{
-        struct of_irq oirq;
-
-        if (of_irq_map_one(dev, index, &oirq))
-                return NO_IRQ;
-
-        return oirq.specifier[0];
-}
-EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
-
 static u32 concurrent_irq;
 
 void __irq_entry do_IRQ(struct pt_regs *regs)
 {
         unsigned int irq;
         struct pt_regs *old_regs = set_irq_regs(regs);
+        trace_hardirqs_off();
 
         irq_enter();
         irq = get_irq(regs);
@@ -53,6 +44,7 @@ next_irq:
 
         irq_exit();
         set_irq_regs(old_regs);
+        trace_hardirqs_on();
 }
 
 int show_interrupts(struct seq_file *p, void *v)
@@ -104,7 +96,7 @@ unsigned int irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq)
 EXPORT_SYMBOL_GPL(irq_create_mapping);
 
 unsigned int irq_create_of_mapping(struct device_node *controller,
-                                        u32 *intspec, unsigned int intsize)
+                                   const u32 *intspec, unsigned int intsize)
 {
         return intspec[0];
 }
diff --git a/arch/microblaze/kernel/kgdb.c b/arch/microblaze/kernel/kgdb.c
new file mode 100644
index 000000000000..bfc006b7f2d8
--- /dev/null
+++ b/arch/microblaze/kernel/kgdb.c
@@ -0,0 +1,147 @@
+/*
+ * Microblaze KGDB support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kgdb.h>
+#include <linux/kdebug.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <asm/asm-offsets.h>
+#include <asm/pvr.h>
+
+#define GDB_REG         0
+#define GDB_PC          32
+#define GDB_MSR         33
+#define GDB_EAR         34
+#define GDB_ESR         35
+#define GDB_FSR         36
+#define GDB_BTR         37
+#define GDB_PVR         38
+#define GDB_REDR        50
+#define GDB_RPID        51
+#define GDB_RZPR        52
+#define GDB_RTLBX       53
+#define GDB_RTLBSX      54 /* mfs can't read it */
+#define GDB_RTLBLO      55
+#define GDB_RTLBHI      56
+
+/* keep pvr separately because it is unchangeble */
+struct pvr_s pvr;
+
+void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        int i;
+        unsigned long *pt_regb = (unsigned long *)regs;
+        int temp;
+        /* registers r0 - r31, pc, msr, ear, esr, fsr + do not save pt_mode */
+        for (i = 0; i < (sizeof(struct pt_regs) / 4) - 1; i++)
+                gdb_regs[i] = pt_regb[i];
+
+        /* Branch target register can't be changed */
+        __asm__ __volatile__ ("mfs %0, rbtr;" : "=r"(temp) : );
+        gdb_regs[GDB_BTR] = temp;
+
+        /* pvr part  - we have 11 pvr regs */
+        for (i = 0; i < sizeof(struct pvr_s)/4; i++)
+                gdb_regs[GDB_PVR + i] = pvr.pvr[i];
+
+        /* read special registers - can't be changed */
+        __asm__ __volatile__ ("mfs %0, redr;" : "=r"(temp) : );
+        gdb_regs[GDB_REDR] = temp;
+        __asm__ __volatile__ ("mfs %0, rpid;" : "=r"(temp) : );
+        gdb_regs[GDB_RPID] = temp;
+        __asm__ __volatile__ ("mfs %0, rzpr;" : "=r"(temp) : );
+        gdb_regs[GDB_RZPR] = temp;
+        __asm__ __volatile__ ("mfs %0, rtlbx;" : "=r"(temp) : );
+        gdb_regs[GDB_RTLBX] = temp;
+        __asm__ __volatile__ ("mfs %0, rtlblo;" : "=r"(temp) : );
+        gdb_regs[GDB_RTLBLO] = temp;
+        __asm__ __volatile__ ("mfs %0, rtlbhi;" : "=r"(temp) : );
+        gdb_regs[GDB_RTLBHI] = temp;
+}
+
+void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        int i;
+        unsigned long *pt_regb = (unsigned long *)regs;
+
+        /* pt_regs and gdb_regs have the same 37 values.
+         * The rest of gdb_regs are unused and can't be changed.
+         * r0 register value can't be changed too. */
+        for (i = 1; i < (sizeof(struct pt_regs) / 4) - 1; i++)
+                pt_regb[i] = gdb_regs[i];
+}
+
+void microblaze_kgdb_break(struct pt_regs *regs)
+{
+        if (kgdb_handle_exception(1, SIGTRAP, 0, regs) != 0)
+                return 0;
+
+        /* Jump over the first arch_kgdb_breakpoint which is barrier to
+         * get kgdb work. The same solution is used for powerpc */
+        if (*(u32 *) (regs->pc) == *(u32 *) (&arch_kgdb_ops.gdb_bpt_instr))
+                regs->pc += BREAK_INSTR_SIZE;
+}
+
+/* untested */
+void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
+{
+        int i;
+        unsigned long *pt_regb = (unsigned long *)(p->thread.regs);
+
+        /* registers r0 - r31, pc, msr, ear, esr, fsr + do not save pt_mode */
+        for (i = 0; i < (sizeof(struct pt_regs) / 4) - 1; i++)
+                gdb_regs[i] = pt_regb[i];
+
+        /* pvr part  - we have 11 pvr regs */
+        for (i = 0; i < sizeof(struct pvr_s)/4; i++)
+                gdb_regs[GDB_PVR + i] = pvr.pvr[i];
+}
+
+void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
+{
+        regs->pc = ip;
+}
+
+int kgdb_arch_handle_exception(int vector, int signo, int err_code,
+                               char *remcom_in_buffer, char *remcom_out_buffer,
+                               struct pt_regs *regs)
+{
+        char *ptr;
+        unsigned long address;
+        int cpu = smp_processor_id();
+
+        switch (remcom_in_buffer[0]) {
+        case 'c':
+                /* handle the optional parameter */
+                ptr = &remcom_in_buffer[1];
+                if (kgdb_hex2long(&ptr, &address))
+                        regs->pc = address;
+
+                return 0;
+        }
+        return -1; /* this means that we do not want to exit from the handler */
+}
+
+int kgdb_arch_init(void)
+{
+        get_pvr(&pvr); /* Fill PVR structure */
+        return 0;
+}
+
+void kgdb_arch_exit(void)
+{
+        /* Nothing to do */
+}
+
+/*
+ * Global data
+ */
+struct kgdb_arch arch_kgdb_ops = {
+        .gdb_bpt_instr = {0xba, 0x0c, 0x00, 0x18}, /* brki r16, 0x18 */
+};
diff --git a/arch/microblaze/kernel/misc.S b/arch/microblaze/kernel/misc.S
index 0fb5fc6c1fc2..206da3da361f 100644
--- a/arch/microblaze/kernel/misc.S
+++ b/arch/microblaze/kernel/misc.S
@@ -76,7 +76,7 @@ early_console_reg_tlb_alloc:
          * the UARTs nice and early.  We use a 4k real==virtual mapping.
          */
         ori     r4, r0, MICROBLAZE_TLB_SIZE - 1
-        mts     rtlbx, r4 /* TLB slot 2 */
+        mts     rtlbx, r4 /* TLB slot 63 */
 
         or      r4,r5,r0
         andi    r4,r4,0xfffff000
diff --git a/arch/microblaze/kernel/of_device.c b/arch/microblaze/kernel/of_device.c
deleted file mode 100644
index b372787886ed..000000000000
--- a/arch/microblaze/kernel/of_device.c
+++ /dev/null
@@ -1,112 +0,0 @@
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/slab.h>
-#include <linux/of_device.h>
-
-#include <linux/errno.h>
-
-void of_device_make_bus_id(struct of_device *dev)
-{
-        static atomic_t bus_no_reg_magic;
-        struct device_node *node = dev->dev.of_node;
-        const u32 *reg;
-        u64 addr;
-        int magic;
-
-        /*
-         * For MMIO, get the physical address
-         */
-        reg = of_get_property(node, "reg", NULL);
-        if (reg) {
-                addr = of_translate_address(node, reg);
-                if (addr != OF_BAD_ADDR) {
-                        dev_set_name(&dev->dev, "%llx.%s",
-                                     (unsigned long long)addr, node->name);
-                        return;
-                }
-        }
-
-        /*
-         * No BusID, use the node name and add a globally incremented
-         * counter (and pray...)
-         */
-        magic = atomic_add_return(1, &bus_no_reg_magic);
-        dev_set_name(&dev->dev, "%s.%d", node->name, magic - 1);
-}
-EXPORT_SYMBOL(of_device_make_bus_id);
-
-struct of_device *of_device_alloc(struct device_node *np,
-                                  const char *bus_id,
-                                  struct device *parent)
-{
-        struct of_device *dev;
-
-        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-        if (!dev)
-                return NULL;
-
-        dev->dev.of_node = of_node_get(np);
-        dev->dev.dma_mask = &dev->archdata.dma_mask;
-        dev->dev.parent = parent;
-        dev->dev.release = of_release_dev;
-
-        if (bus_id)
-                dev_set_name(&dev->dev, bus_id);
-        else
-                of_device_make_bus_id(dev);
-
-        return dev;
-}
-EXPORT_SYMBOL(of_device_alloc);
-
-int of_device_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
-        struct of_device *ofdev;
-        const char *compat;
-        int seen = 0, cplen, sl;
-
-        if (!dev)
-                return -ENODEV;
-
-        ofdev = to_of_device(dev);
-
-        if (add_uevent_var(env, "OF_NAME=%s", ofdev->dev.of_node->name))
-                return -ENOMEM;
-
-        if (add_uevent_var(env, "OF_TYPE=%s", ofdev->dev.of_node->type))
-                return -ENOMEM;
-
-        /* Since the compatible field can contain pretty much anything
-         * it's not really legal to split it out with commas. We split it
-         * up using a number of environment variables instead. */
-
-        compat = of_get_property(ofdev->dev.of_node, "compatible", &cplen);
-        while (compat && *compat && cplen > 0) {
-                if (add_uevent_var(env, "OF_COMPATIBLE_%d=%s", seen, compat))
-                        return -ENOMEM;
-
-                sl = strlen(compat) + 1;
-                compat += sl;
-                cplen -= sl;
-                seen++;
-        }
-
-        if (add_uevent_var(env, "OF_COMPATIBLE_N=%d", seen))
-                return -ENOMEM;
-
-        /* modalias is trickier, we add it in 2 steps */
-        if (add_uevent_var(env, "MODALIAS="))
-                return -ENOMEM;
-        sl = of_device_get_modalias(ofdev, &env->buf[env->buflen-1],
-                                    sizeof(env->buf) - env->buflen);
-        if (sl >= (sizeof(env->buf) - env->buflen))
-                return -ENOMEM;
-        env->buflen += sl;
-
-        return 0;
-}
-EXPORT_SYMBOL(of_device_uevent);
diff --git a/arch/microblaze/kernel/of_platform.c b/arch/microblaze/kernel/of_platform.c
deleted file mode 100644
index ccf6f4257f4b..000000000000
--- a/arch/microblaze/kernel/of_platform.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- *    Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
- *                       <benh@kernel.crashing.org>
- *    and                Arnd Bergmann, IBM Corp.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- *
- */
-
-#undef DEBUG
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/pci.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-
-#include <linux/errno.h>
-#include <linux/topology.h>
-#include <asm/atomic.h>
-
-struct bus_type of_platform_bus_type = {
-       .uevent  = of_device_uevent,
-};
-EXPORT_SYMBOL(of_platform_bus_type);
-
-static int __init of_bus_driver_init(void)
-{
-        return of_bus_type_init(&of_platform_bus_type, "of_platform");
-}
-postcore_initcall(of_bus_driver_init);
-
-struct of_device *of_platform_device_create(struct device_node *np,
-                                            const char *bus_id,
-                                            struct device *parent)
-{
-        struct of_device *dev;
-
-        dev = of_device_alloc(np, bus_id, parent);
-        if (!dev)
-                return NULL;
-
-        dev->archdata.dma_mask = 0xffffffffUL;
-        dev->dev.bus = &of_platform_bus_type;
-
-        /* We do not fill the DMA ops for platform devices by default.
-         * This is currently the responsibility of the platform code
-         * to do such, possibly using a device notifier
-         */
-
-        if (of_device_register(dev) != 0) {
-                of_device_free(dev);
-                return NULL;
-        }
-
-        return dev;
-}
-EXPORT_SYMBOL(of_platform_device_create);
-
-/**
- * of_platform_bus_create - Create an OF device for a bus node and all its
- * children. Optionally recursively instanciate matching busses.
- * @bus: device node of the bus to instanciate
- * @matches: match table, NULL to use the default, OF_NO_DEEP_PROBE to
- * disallow recursive creation of child busses
- */
-static int of_platform_bus_create(const struct device_node *bus,
-                                  const struct of_device_id *matches,
-                                  struct device *parent)
-{
-        struct device_node *child;
-        struct of_device *dev;
-        int rc = 0;
-
-        for_each_child_of_node(bus, child) {
-                pr_debug("   create child: %s\n", child->full_name);
-                dev = of_platform_device_create(child, NULL, parent);
-                if (dev == NULL)
-                        rc = -ENOMEM;
-                else if (!of_match_node(matches, child))
-                        continue;
-                if (rc == 0) {
-                        pr_debug("   and sub busses\n");
-                        rc = of_platform_bus_create(child, matches, &dev->dev);
-                }
-                if (rc) {
-                        of_node_put(child);
-                        break;
-                }
-        }
-        return rc;
-}
-
-
-/**
- * of_platform_bus_probe - Probe the device-tree for platform busses
- * @root: parent of the first level to probe or NULL for the root of the tree
- * @matches: match table, NULL to use the default
- * @parent: parent to hook devices from, NULL for toplevel
- *
- * Note that children of the provided root are not instanciated as devices
- * unless the specified root itself matches the bus list and is not NULL.
- */
-
-int of_platform_bus_probe(struct device_node *root,
-                          const struct of_device_id *matches,
-                          struct device *parent)
-{
-        struct device_node *child;
-        struct of_device *dev;
-        int rc = 0;
-
-        if (matches == NULL)
-                matches = of_default_bus_ids;
-        if (matches == OF_NO_DEEP_PROBE)
-                return -EINVAL;
-        if (root == NULL)
-                root = of_find_node_by_path("/");
-        else
-                of_node_get(root);
-
-        pr_debug("of_platform_bus_probe()\n");
-        pr_debug(" starting at: %s\n", root->full_name);
-
-        /* Do a self check of bus type, if there's a match, create
-         * children
-         */
-        if (of_match_node(matches, root)) {
-                pr_debug(" root match, create all sub devices\n");
-                dev = of_platform_device_create(root, NULL, parent);
-                if (dev == NULL) {
-                        rc = -ENOMEM;
-                        goto bail;
-                }
-                pr_debug(" create all sub busses\n");
-                rc = of_platform_bus_create(root, matches, &dev->dev);
-                goto bail;
-        }
-        for_each_child_of_node(root, child) {
-                if (!of_match_node(matches, child))
-                        continue;
-
-                pr_debug("  match: %s\n", child->full_name);
-                dev = of_platform_device_create(child, NULL, parent);
-                if (dev == NULL)
-                        rc = -ENOMEM;
-                else
-                        rc = of_platform_bus_create(child, matches, &dev->dev);
-                if (rc) {
-                        of_node_put(child);
-                        break;
-                }
-        }
- bail:
-        of_node_put(root);
-        return rc;
-}
-EXPORT_SYMBOL(of_platform_bus_probe);
-
-static int of_dev_node_match(struct device *dev, void *data)
-{
-        return to_of_device(dev)->dev.of_node == data;
-}
-
-struct of_device *of_find_device_by_node(struct device_node *np)
-{
-        struct device *dev;
-
-        dev = bus_find_device(&of_platform_bus_type,
-                              NULL, np, of_dev_node_match);
-        if (dev)
-                return to_of_device(dev);
-        return NULL;
-}
-EXPORT_SYMBOL(of_find_device_by_node);
-
-static int of_dev_phandle_match(struct device *dev, void *data)
-{
-        phandle *ph = data;
-        return to_of_device(dev)->dev.of_node->phandle == *ph;
-}
-
-struct of_device *of_find_device_by_phandle(phandle ph)
-{
-        struct device *dev;
-
-        dev = bus_find_device(&of_platform_bus_type,
-                              NULL, &ph, of_dev_phandle_match);
-        if (dev)
-                return to_of_device(dev);
-        return NULL;
-}
-EXPORT_SYMBOL(of_find_device_by_phandle);
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index 09bed44dfcd3..ba7c4b16ed35 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -76,8 +76,11 @@ __setup("hlt", hlt_setup);
 void default_idle(void)
 {
         if (likely(hlt_counter)) {
-                while (!need_resched())
-                        cpu_relax();
+                local_irq_disable();
+                stop_critical_timings();
+                cpu_relax();
+                start_critical_timings();
+                local_irq_enable();
         } else {
                 clear_thread_flag(TIF_POLLING_NRFLAG);
                 smp_mb__after_clear_bit();
diff --git a/arch/microblaze/kernel/prom_parse.c b/arch/microblaze/kernel/prom_parse.c
index bf7e6c27e318..d33ba17601fa 100644
--- a/arch/microblaze/kernel/prom_parse.c
+++ b/arch/microblaze/kernel/prom_parse.c
@@ -6,219 +6,11 @@
 #include <linux/module.h>
 #include <linux/ioport.h>
 #include <linux/etherdevice.h>
+#include <linux/of_address.h>
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 
-#define PRu64   "%llx"
-
-/* Max address size we deal with */
-#define OF_MAX_ADDR_CELLS       4
-#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
-                        (ns) > 0)
-
-static struct of_bus *of_match_bus(struct device_node *np);
-static int __of_address_to_resource(struct device_node *dev,
-                const u32 *addrp, u64 size, unsigned int flags,
-                struct resource *r);
-
-/* Debug utility */
-#ifdef DEBUG
-static void of_dump_addr(const char *s, const u32 *addr, int na)
-{
-        printk(KERN_INFO "%s", s);
-        while (na--)
-                printk(KERN_INFO " %08x", *(addr++));
-        printk(KERN_INFO "\n");
-}
-#else
-static void of_dump_addr(const char *s, const u32 *addr, int na) { }
-#endif
-
-/* Callbacks for bus specific translators */
-struct of_bus {
-        const char      *name;
-        const char      *addresses;
-        int             (*match)(struct device_node *parent);
-        void            (*count_cells)(struct device_node *child,
-                                        int *addrc, int *sizec);
-        u64             (*map)(u32 *addr, const u32 *range,
-                                int na, int ns, int pna);
-        int             (*translate)(u32 *addr, u64 offset, int na);
-        unsigned int    (*get_flags)(const u32 *addr);
-};
-
-/*
- * Default translator (generic bus)
- */
-
-static void of_bus_default_count_cells(struct device_node *dev,
-                                        int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = of_n_addr_cells(dev);
-        if (sizec)
-                *sizec = of_n_size_cells(dev);
-}
-
-static u64 of_bus_default_map(u32 *addr, const u32 *range,
-                int na, int ns, int pna)
-{
-        u64 cp, s, da;
-
-        cp = of_read_number(range, na);
-        s  = of_read_number(range + na + pna, ns);
-        da = of_read_number(addr, na);
-
-        pr_debug("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n",
-                cp, s, da);
-
-        if (da < cp || da >= (cp + s))
-                return OF_BAD_ADDR;
-        return da - cp;
-}
-
-static int of_bus_default_translate(u32 *addr, u64 offset, int na)
-{
-        u64 a = of_read_number(addr, na);
-        memset(addr, 0, na * 4);
-        a += offset;
-        if (na > 1)
-                addr[na - 2] = a >> 32;
-        addr[na - 1] = a & 0xffffffffu;
-
-        return 0;
-}
-
-static unsigned int of_bus_default_get_flags(const u32 *addr)
-{
-        return IORESOURCE_MEM;
-}
-
 #ifdef CONFIG_PCI
-/*
- * PCI bus specific translator
- */
-
-static int of_bus_pci_match(struct device_node *np)
-{
-        /* "vci" is for the /chaos bridge on 1st-gen PCI powermacs */
-        return !strcmp(np->type, "pci") || !strcmp(np->type, "vci");
-}
-
-static void of_bus_pci_count_cells(struct device_node *np,
-                                int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = 3;
-        if (sizec)
-                *sizec = 2;
-}
-
-static u64 of_bus_pci_map(u32 *addr, const u32 *range, int na, int ns, int pna)
-{
-        u64 cp, s, da;
-
-        /* Check address type match */
-        if ((addr[0] ^ range[0]) & 0x03000000)
-                return OF_BAD_ADDR;
-
-        /* Read address values, skipping high cell */
-        cp = of_read_number(range + 1, na - 1);
-        s  = of_read_number(range + na + pna, ns);
-        da = of_read_number(addr + 1, na - 1);
-
-        pr_debug("OF: PCI map, cp="PRu64", s="PRu64", da="PRu64"\n", cp, s, da);
-
-        if (da < cp || da >= (cp + s))
-                return OF_BAD_ADDR;
-        return da - cp;
-}
-
-static int of_bus_pci_translate(u32 *addr, u64 offset, int na)
-{
-        return of_bus_default_translate(addr + 1, offset, na - 1);
-}
-
-static unsigned int of_bus_pci_get_flags(const u32 *addr)
-{
-        unsigned int flags = 0;
-        u32 w = addr[0];
-
-        switch ((w >> 24) & 0x03) {
-        case 0x01:
-                flags |= IORESOURCE_IO;
-                break;
-        case 0x02: /* 32 bits */
-        case 0x03: /* 64 bits */
-                flags |= IORESOURCE_MEM;
-                break;
-        }
-        if (w & 0x40000000)
-                flags |= IORESOURCE_PREFETCH;
-        return flags;
-}
-
-const u32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size,
-                        unsigned int *flags)
-{
-        const u32 *prop;
-        unsigned int psize;
-        struct device_node *parent;
-        struct of_bus *bus;
-        int onesize, i, na, ns;
-
-        /* Get parent & match bus type */
-        parent = of_get_parent(dev);
-        if (parent == NULL)
-                return NULL;
-        bus = of_match_bus(parent);
-        if (strcmp(bus->name, "pci")) {
-                of_node_put(parent);
-                return NULL;
-        }
-        bus->count_cells(dev, &na, &ns);
-        of_node_put(parent);
-        if (!OF_CHECK_COUNTS(na, ns))
-                return NULL;
-
-        /* Get "reg" or "assigned-addresses" property */
-        prop = of_get_property(dev, bus->addresses, &psize);
-        if (prop == NULL)
-                return NULL;
-        psize /= 4;
-
-        onesize = na + ns;
-        for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++)
-                if ((prop[0] & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0)) {
-                        if (size)
-                                *size = of_read_number(prop + na, ns);
-                        if (flags)
-                                *flags = bus->get_flags(prop);
-                        return prop;
-                }
-        return NULL;
-}
-EXPORT_SYMBOL(of_get_pci_address);
-
-int of_pci_address_to_resource(struct device_node *dev, int bar,
-                                struct resource *r)
-{
-        const u32       *addrp;
-        u64             size;
-        unsigned int    flags;
-
-        addrp = of_get_pci_address(dev, bar, &size, &flags);
-        if (addrp == NULL)
-                return -EINVAL;
-        return __of_address_to_resource(dev, addrp, size, flags, r);
-}
-EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
-
-static u8 of_irq_pci_swizzle(u8 slot, u8 pin)
-{
-        return (((pin - 1) + slot) % 4) + 1;
-}
-
 int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
 {
         struct device_node *dn, *ppnode;
@@ -293,331 +85,6 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
 EXPORT_SYMBOL_GPL(of_irq_map_pci);
 #endif /* CONFIG_PCI */
 
-/*
- * ISA bus specific translator
- */
-
-static int of_bus_isa_match(struct device_node *np)
-{
-        return !strcmp(np->name, "isa");
-}
-
-static void of_bus_isa_count_cells(struct device_node *child,
-                                int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = 2;
-        if (sizec)
-                *sizec = 1;
-}
-
-static u64 of_bus_isa_map(u32 *addr, const u32 *range, int na, int ns, int pna)
-{
-        u64 cp, s, da;
-
-        /* Check address type match */
-        if ((addr[0] ^ range[0]) & 0x00000001)
-                return OF_BAD_ADDR;
-
-        /* Read address values, skipping high cell */
-        cp = of_read_number(range + 1, na - 1);
-        s  = of_read_number(range + na + pna, ns);
-        da = of_read_number(addr + 1, na - 1);
-
-        pr_debug("OF: ISA map, cp="PRu64", s="PRu64", da="PRu64"\n", cp, s, da);
-
-        if (da < cp || da >= (cp + s))
-                return OF_BAD_ADDR;
-        return da - cp;
-}
-
-static int of_bus_isa_translate(u32 *addr, u64 offset, int na)
-{
-        return of_bus_default_translate(addr + 1, offset, na - 1);
-}
-
-static unsigned int of_bus_isa_get_flags(const u32 *addr)
-{
-        unsigned int flags = 0;
-        u32 w = addr[0];
-
-        if (w & 1)
-                flags |= IORESOURCE_IO;
-        else
-                flags |= IORESOURCE_MEM;
-        return flags;
-}
-
-/*
- * Array of bus specific translators
- */
-
-static struct of_bus of_busses[] = {
-#ifdef CONFIG_PCI
-        /* PCI */
-        {
-                .name = "pci",
-                .addresses = "assigned-addresses",
-                .match = of_bus_pci_match,
-                .count_cells = of_bus_pci_count_cells,
-                .map = of_bus_pci_map,
-                .translate = of_bus_pci_translate,
-                .get_flags = of_bus_pci_get_flags,
-        },
-#endif /* CONFIG_PCI */
-        /* ISA */
-        {
-                .name = "isa",
-                .addresses = "reg",
-                .match = of_bus_isa_match,
-                .count_cells = of_bus_isa_count_cells,
-                .map = of_bus_isa_map,
-                .translate = of_bus_isa_translate,
-                .get_flags = of_bus_isa_get_flags,
-        },
-        /* Default */
-        {
-                .name = "default",
-                .addresses = "reg",
-                .match = NULL,
-                .count_cells = of_bus_default_count_cells,
-                .map = of_bus_default_map,
-                .translate = of_bus_default_translate,
-                .get_flags = of_bus_default_get_flags,
-        },
-};
-
-static struct of_bus *of_match_bus(struct device_node *np)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(of_busses); i++)
-                if (!of_busses[i].match || of_busses[i].match(np))
-                        return &of_busses[i];
-        BUG();
-        return NULL;
-}
-
-static int of_translate_one(struct device_node *parent, struct of_bus *bus,
-                        struct of_bus *pbus, u32 *addr,
-                        int na, int ns, int pna)
-{
-        const u32 *ranges;
-        unsigned int rlen;
-        int rone;
-        u64 offset = OF_BAD_ADDR;
-
-        /* Normally, an absence of a "ranges" property means we are
-         * crossing a non-translatable boundary, and thus the addresses
-         * below the current not cannot be converted to CPU physical ones.
-         * Unfortunately, while this is very clear in the spec, it's not
-         * what Apple understood, and they do have things like /uni-n or
-         * /ht nodes with no "ranges" property and a lot of perfectly
-         * useable mapped devices below them. Thus we treat the absence of
-         * "ranges" as equivalent to an empty "ranges" property which means
-         * a 1:1 translation at that level. It's up to the caller not to try
-         * to translate addresses that aren't supposed to be translated in
-         * the first place. --BenH.
-         */
-        ranges = of_get_property(parent, "ranges", (int *) &rlen);
-        if (ranges == NULL || rlen == 0) {
-                offset = of_read_number(addr, na);
-                memset(addr, 0, pna * 4);
-                pr_debug("OF: no ranges, 1:1 translation\n");
-                goto finish;
-        }
-
-        pr_debug("OF: walking ranges...\n");
-
-        /* Now walk through the ranges */
-        rlen /= 4;
-        rone = na + pna + ns;
-        for (; rlen >= rone; rlen -= rone, ranges += rone) {
-                offset = bus->map(addr, ranges, na, ns, pna);
-                if (offset != OF_BAD_ADDR)
-                        break;
-        }
-        if (offset == OF_BAD_ADDR) {
-                pr_debug("OF: not found !\n");
-                return 1;
-        }
-        memcpy(addr, ranges + na, 4 * pna);
-
- finish:
-        of_dump_addr("OF: parent translation for:", addr, pna);
-        pr_debug("OF: with offset: "PRu64"\n", offset);
-
-        /* Translate it into parent bus space */
-        return pbus->translate(addr, offset, pna);
-}
-
-/*
- * Translate an address from the device-tree into a CPU physical address,
- * this walks up the tree and applies the various bus mappings on the
- * way.
- *
- * Note: We consider that crossing any level with #size-cells == 0 to mean
- * that translation is impossible (that is we are not dealing with a value
- * that can be mapped to a cpu physical address). This is not really specified
- * that way, but this is traditionally the way IBM at least do things
- */
-u64 of_translate_address(struct device_node *dev, const u32 *in_addr)
-{
-        struct device_node *parent = NULL;
-        struct of_bus *bus, *pbus;
-        u32 addr[OF_MAX_ADDR_CELLS];
-        int na, ns, pna, pns;
-        u64 result = OF_BAD_ADDR;
-
-        pr_debug("OF: ** translation for device %s **\n", dev->full_name);
-
-        /* Increase refcount at current level */
-        of_node_get(dev);
-
-        /* Get parent & match bus type */
-        parent = of_get_parent(dev);
-        if (parent == NULL)
-                goto bail;
-        bus = of_match_bus(parent);
-
-        /* Cound address cells & copy address locally */
-        bus->count_cells(dev, &na, &ns);
-        if (!OF_CHECK_COUNTS(na, ns)) {
-                printk(KERN_ERR "prom_parse: Bad cell count for %s\n",
-                        dev->full_name);
-                goto bail;
-        }
-        memcpy(addr, in_addr, na * 4);
-
-        pr_debug("OF: bus is %s (na=%d, ns=%d) on %s\n",
-                bus->name, na, ns, parent->full_name);
-        of_dump_addr("OF: translating address:", addr, na);
-
-        /* Translate */
-        for (;;) {
-                /* Switch to parent bus */
-                of_node_put(dev);
-                dev = parent;
-                parent = of_get_parent(dev);
-
-                /* If root, we have finished */
-                if (parent == NULL) {
-                        pr_debug("OF: reached root node\n");
-                        result = of_read_number(addr, na);
-                        break;
-                }
-
-                /* Get new parent bus and counts */
-                pbus = of_match_bus(parent);
-                pbus->count_cells(dev, &pna, &pns);
-                if (!OF_CHECK_COUNTS(pna, pns)) {
-                        printk(KERN_ERR "prom_parse: Bad cell count for %s\n",
-                                dev->full_name);
-                        break;
-                }
-
-                pr_debug("OF: parent bus is %s (na=%d, ns=%d) on %s\n",
-                        pbus->name, pna, pns, parent->full_name);
-
-                /* Apply bus translation */
-                if (of_translate_one(dev, bus, pbus, addr, na, ns, pna))
-                        break;
-
-                /* Complete the move up one level */
-                na = pna;
-                ns = pns;
-                bus = pbus;
-
-                of_dump_addr("OF: one level translation:", addr, na);
-        }
- bail:
-        of_node_put(parent);
-        of_node_put(dev);
-
-        return result;
-}
-EXPORT_SYMBOL(of_translate_address);
-
-const u32 *of_get_address(struct device_node *dev, int index, u64 *size,
-                        unsigned int *flags)
-{
-        const u32 *prop;
-        unsigned int psize;
-        struct device_node *parent;
-        struct of_bus *bus;
-        int onesize, i, na, ns;
-
-        /* Get parent & match bus type */
-        parent = of_get_parent(dev);
-        if (parent == NULL)
-                return NULL;
-        bus = of_match_bus(parent);
-        bus->count_cells(dev, &na, &ns);
-        of_node_put(parent);
-        if (!OF_CHECK_COUNTS(na, ns))
-                return NULL;
-
-        /* Get "reg" or "assigned-addresses" property */
-        prop = of_get_property(dev, bus->addresses, (int *) &psize);
-        if (prop == NULL)
-                return NULL;
-        psize /= 4;
-
-        onesize = na + ns;
-        for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++)
-                if (i == index) {
-                        if (size)
-                                *size = of_read_number(prop + na, ns);
-                        if (flags)
-                                *flags = bus->get_flags(prop);
-                        return prop;
-                }
-        return NULL;
-}
-EXPORT_SYMBOL(of_get_address);
-
-static int __of_address_to_resource(struct device_node *dev, const u32 *addrp,
-                                u64 size, unsigned int flags,
-                                struct resource *r)
-{
-        u64 taddr;
-
-        if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
-                return -EINVAL;
-        taddr = of_translate_address(dev, addrp);
-        if (taddr == OF_BAD_ADDR)
-                return -EINVAL;
-        memset(r, 0, sizeof(struct resource));
-        if (flags & IORESOURCE_IO) {
-                unsigned long port;
-                port = -1; /* pci_address_to_pio(taddr); */
-                if (port == (unsigned long)-1)
-                        return -EINVAL;
-                r->start = port;
-                r->end = port + size - 1;
-        } else {
-                r->start = taddr;
-                r->end = taddr + size - 1;
-        }
-        r->flags = flags;
-        r->name = dev->name;
-        return 0;
-}
-
-int of_address_to_resource(struct device_node *dev, int index,
-                        struct resource *r)
-{
-        const u32       *addrp;
-        u64             size;
-        unsigned int    flags;
-
-        addrp = of_get_address(dev, index, &size, &flags);
-        if (addrp == NULL)
-                return -EINVAL;
-        return __of_address_to_resource(dev, addrp, size, flags, r);
-}
-EXPORT_SYMBOL_GPL(of_address_to_resource);
-
 void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
                 unsigned long *busno, unsigned long *phys, unsigned long *size)
 {
@@ -644,308 +111,6 @@ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
         *size = of_read_number(dma_window, cells);
 }
 
-/*
- * Interrupt remapper
- */
-
-static unsigned int of_irq_workarounds;
-static struct device_node *of_irq_dflt_pic;
-
-static struct device_node *of_irq_find_parent(struct device_node *child)
-{
-        struct device_node *p;
-        const phandle *parp;
-
-        if (!of_node_get(child))
-                return NULL;
-
-        do {
-                parp = of_get_property(child, "interrupt-parent", NULL);
-                if (parp == NULL)
-                        p = of_get_parent(child);
-                else {
-                        if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
-                                p = of_node_get(of_irq_dflt_pic);
-                        else
-                                p = of_find_node_by_phandle(*parp);
-                }
-                of_node_put(child);
-                child = p;
-        } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
-
-        return p;
-}
-
-/* This doesn't need to be called if you don't have any special workaround
- * flags to pass
- */
-void of_irq_map_init(unsigned int flags)
-{
-        of_irq_workarounds = flags;
-
-        /* OldWorld, don't bother looking at other things */
-        if (flags & OF_IMAP_OLDWORLD_MAC)
-                return;
-
-        /* If we don't have phandles, let's try to locate a default interrupt
-         * controller (happens when booting with BootX). We do a first match
-         * here, hopefully, that only ever happens on machines with one
-         * controller.
-         */
-        if (flags & OF_IMAP_NO_PHANDLE) {
-                struct device_node *np;
-
-                for (np = NULL; (np = of_find_all_nodes(np)) != NULL;) {
-                        if (of_get_property(np, "interrupt-controller", NULL)
-                                == NULL)
-                                continue;
-                        /* Skip /chosen/interrupt-controller */
-                        if (strcmp(np->name, "chosen") == 0)
-                                continue;
-                        /* It seems like at least one person on this planet
-                         * wants to use BootX on a machine with an AppleKiwi
-                         * controller which happens to pretend to be an
-                         * interrupt controller too.
-                         */
-                        if (strcmp(np->name, "AppleKiwi") == 0)
-                                continue;
-                        /* I think we found one ! */
-                        of_irq_dflt_pic = np;
-                        break;
-                }
-        }
-
-}
-
-int of_irq_map_raw(struct device_node *parent, const u32 *intspec, u32 ointsize,
-                const u32 *addr, struct of_irq *out_irq)
-{
-        struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
-        const u32 *tmp, *imap, *imask;
-        u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
-        int imaplen, match, i;
-
-        pr_debug("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],"
-                "ointsize=%d\n",
-                parent->full_name, intspec[0], intspec[1], ointsize);
-
-        ipar = of_node_get(parent);
-
-        /* First get the #interrupt-cells property of the current cursor
-         * that tells us how to interpret the passed-in intspec. If there
-         * is none, we are nice and just walk up the tree
-         */
-        do {
-                tmp = of_get_property(ipar, "#interrupt-cells", NULL);
-                if (tmp != NULL) {
-                        intsize = *tmp;
-                        break;
-                }
-                tnode = ipar;
-                ipar = of_irq_find_parent(ipar);
-                of_node_put(tnode);
-        } while (ipar);
-        if (ipar == NULL) {
-                pr_debug(" -> no parent found !\n");
-                goto fail;
-        }
-
-        pr_debug("of_irq_map_raw: ipar=%s, size=%d\n",
-                        ipar->full_name, intsize);
-
-        if (ointsize != intsize)
-                return -EINVAL;
-
-        /* Look for this #address-cells. We have to implement the old linux
-         * trick of looking for the parent here as some device-trees rely on it
-         */
-        old = of_node_get(ipar);
-        do {
-                tmp = of_get_property(old, "#address-cells", NULL);
-                tnode = of_get_parent(old);
-                of_node_put(old);
-                old = tnode;
-        } while (old && tmp == NULL);
-        of_node_put(old);
-        old = NULL;
-        addrsize = (tmp == NULL) ? 2 : *tmp;
-
-        pr_debug(" -> addrsize=%d\n", addrsize);
-
-        /* Now start the actual "proper" walk of the interrupt tree */
-        while (ipar != NULL) {
-                /* Now check if cursor is an interrupt-controller and if it is
-                 * then we are done
-                 */
-                if (of_get_property(ipar, "interrupt-controller", NULL) !=
-                                NULL) {
-                        pr_debug(" -> got it !\n");
-                        memcpy(out_irq->specifier, intspec,
-                                intsize * sizeof(u32));
-                        out_irq->size = intsize;
-                        out_irq->controller = ipar;
-                        of_node_put(old);
-                        return 0;
-                }
-
-                /* Now look for an interrupt-map */
-                imap = of_get_property(ipar, "interrupt-map", &imaplen);
-                /* No interrupt map, check for an interrupt parent */
-                if (imap == NULL) {
-                        pr_debug(" -> no map, getting parent\n");
-                        newpar = of_irq_find_parent(ipar);
-                        goto skiplevel;
-                }
-                imaplen /= sizeof(u32);
-
-                /* Look for a mask */
-                imask = of_get_property(ipar, "interrupt-map-mask", NULL);
-
-                /* If we were passed no "reg" property and we attempt to parse
-                 * an interrupt-map, then #address-cells must be 0.
-                 * Fail if it's not.
-                 */
-                if (addr == NULL && addrsize != 0) {
-                        pr_debug(" -> no reg passed in when needed !\n");
-                        goto fail;
-                }
-
-                /* Parse interrupt-map */
-                match = 0;
-                while (imaplen > (addrsize + intsize + 1) && !match) {
-                        /* Compare specifiers */
-                        match = 1;
-                        for (i = 0; i < addrsize && match; ++i) {
-                                u32 mask = imask ? imask[i] : 0xffffffffu;
-                                match = ((addr[i] ^ imap[i]) & mask) == 0;
-                        }
-                        for (; i < (addrsize + intsize) && match; ++i) {
-                                u32 mask = imask ? imask[i] : 0xffffffffu;
-                                match =
-                                        ((intspec[i-addrsize] ^ imap[i])
-                                                & mask) == 0;
-                        }
-                        imap += addrsize + intsize;
-                        imaplen -= addrsize + intsize;
-
-                        pr_debug(" -> match=%d (imaplen=%d)\n", match, imaplen);
-
-                        /* Get the interrupt parent */
-                        if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
-                                newpar = of_node_get(of_irq_dflt_pic);
-                        else
-                                newpar =
-                                        of_find_node_by_phandle((phandle)*imap);
-                        imap++;
-                        --imaplen;
-
-                        /* Check if not found */
-                        if (newpar == NULL) {
-                                pr_debug(" -> imap parent not found !\n");
-                                goto fail;
-                        }
-
-                        /* Get #interrupt-cells and #address-cells of new
-                         * parent
-                         */
-                        tmp = of_get_property(newpar, "#interrupt-cells", NULL);
-                        if (tmp == NULL) {
-                                pr_debug(" -> parent lacks "
-                                                "#interrupt-cells!\n");
-                                goto fail;
-                        }
-                        newintsize = *tmp;
-                        tmp = of_get_property(newpar, "#address-cells", NULL);
-                        newaddrsize = (tmp == NULL) ? 0 : *tmp;
-
-                        pr_debug(" -> newintsize=%d, newaddrsize=%d\n",
-                                newintsize, newaddrsize);
-
-                        /* Check for malformed properties */
-                        if (imaplen < (newaddrsize + newintsize))
-                                goto fail;
-
-                        imap += newaddrsize + newintsize;
-                        imaplen -= newaddrsize + newintsize;
-
-                        pr_debug(" -> imaplen=%d\n", imaplen);
-                }
-                if (!match)
-                        goto fail;
-
-                of_node_put(old);
-                old = of_node_get(newpar);
-                addrsize = newaddrsize;
-                intsize = newintsize;
-                intspec = imap - intsize;
-                addr = intspec - addrsize;
-
-skiplevel:
-                /* Iterate again with new parent */
-                pr_debug(" -> new parent: %s\n",
-                                newpar ? newpar->full_name : "<>");
-                of_node_put(ipar);
-                ipar = newpar;
-                newpar = NULL;
-        }
-fail:
-        of_node_put(ipar);
-        of_node_put(old);
-        of_node_put(newpar);
-
-        return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(of_irq_map_raw);
-
-int of_irq_map_one(struct device_node *device,
-                        int index, struct of_irq *out_irq)
-{
-        struct device_node *p;
-        const u32 *intspec, *tmp, *addr;
-        u32 intsize, intlen;
-        int res;
-
-        pr_debug("of_irq_map_one: dev=%s, index=%d\n",
-                        device->full_name, index);
-
-        /* Get the interrupts property */
-        intspec = of_get_property(device, "interrupts", (int *) &intlen);
-        if (intspec == NULL)
-                return -EINVAL;
-        intlen /= sizeof(u32);
-
-        pr_debug(" intspec=%d intlen=%d\n", *intspec, intlen);
-
-        /* Get the reg property (if any) */
-        addr = of_get_property(device, "reg", NULL);
-
-        /* Look for the interrupt parent. */
-        p = of_irq_find_parent(device);
-        if (p == NULL)
-                return -EINVAL;
-
-        /* Get size of interrupt specifier */
-        tmp = of_get_property(p, "#interrupt-cells", NULL);
-        if (tmp == NULL) {
-                of_node_put(p);
-                return -EINVAL;
-        }
-        intsize = *tmp;
-
-        pr_debug(" intsize=%d intlen=%d\n", intsize, intlen);
-
-        /* Check index */
-        if ((index + 1) * intsize > intlen)
-                return -EINVAL;
-
-        /* Get new specifier and map it */
-        res = of_irq_map_raw(p, intspec + index * intsize, intsize,
-                                addr, out_irq);
-        of_node_put(p);
-        return res;
-}
-EXPORT_SYMBOL_GPL(of_irq_map_one);
-
 /**
  * Search the device tree for the best MAC address to use.  'mac-address' is
  * checked first, because that is supposed to contain to "most recent" MAC
@@ -983,43 +148,3 @@ const void *of_get_mac_address(struct device_node *np)
         return NULL;
 }
 EXPORT_SYMBOL(of_get_mac_address);
-
-int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
-{
-        struct of_irq out_irq;
-        int irq;
-        int res;
-
-        res = of_irq_map_one(dev, index, &out_irq);
-
-        /* Get irq for the device */
-        if (res) {
-                pr_debug("IRQ not found... code = %d", res);
-                return NO_IRQ;
-        }
-        /* Assuming single interrupt controller... */
-        irq = out_irq.specifier[0];
-
-        pr_debug("IRQ found = %d", irq);
-
-        /* Only dereference the resource if both the
-         * resource and the irq are valid. */
-        if (r && irq != NO_IRQ) {
-                r->start = r->end = irq;
-                r->flags = IORESOURCE_IRQ;
-        }
-
-        return irq;
-}
-EXPORT_SYMBOL_GPL(of_irq_to_resource);
-
-void __iomem *of_iomap(struct device_node *np, int index)
-{
-        struct resource res;
-
-        if (of_address_to_resource(np, index, &res))
-                return NULL;
-
-        return ioremap(res.start, 1 + res.end - res.start);
-}
-EXPORT_SYMBOL(of_iomap);
diff --git a/arch/microblaze/kernel/ptrace.c b/arch/microblaze/kernel/ptrace.c
index a4a7770c6140..dc03ffc8174a 100644
--- a/arch/microblaze/kernel/ptrace.c
+++ b/arch/microblaze/kernel/ptrace.c
@@ -38,6 +38,8 @@
 #include <asm/processor.h>
 #include <linux/uaccess.h>
 #include <asm/asm-offsets.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
 
 /* Returns the address where the register at REG_OFFS in P is stashed away. */
 static microblaze_reg_t *reg_save_addr(unsigned reg_offs,
@@ -101,8 +103,21 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         microblaze_reg_t *reg_addr = reg_save_addr(addr, child);
                         if (request == PTRACE_PEEKUSR)
                                 val = *reg_addr;
-                        else
+                        else {
+#if 1
                                 *reg_addr = data;
+#else
+                                /* MS potential problem on WB system
+                                 * Be aware that reg_addr is virtual address
+                                 * virt_to_phys conversion is necessary.
+                                 * This could be sensible solution.
+                                 */
+                                u32 paddr = virt_to_phys((u32)reg_addr);
+                                invalidate_icache_range(paddr, paddr + 4);
+                                *reg_addr = data;
+                                flush_dcache_range(paddr, paddr + 4);
+#endif
+                        }
                 } else
                         rval = -EIO;
 
diff --git a/arch/microblaze/kernel/reset.c b/arch/microblaze/kernel/reset.c
index a1721a33042e..bd8ccab5ceff 100644
--- a/arch/microblaze/kernel/reset.c
+++ b/arch/microblaze/kernel/reset.c
@@ -24,8 +24,8 @@ static int of_reset_gpio_handle(void)
         int ret; /* variable which stored handle reset gpio pin */
         struct device_node *root; /* root node */
         struct device_node *gpio; /* gpio node */
-        struct of_gpio_chip *of_gc = NULL;
-        enum of_gpio_flags flags ;
+        struct gpio_chip *gc;
+        u32 flags;
         const void *gpio_spec;
 
         /* find out root node */
@@ -39,19 +39,19 @@ static int of_reset_gpio_handle(void)
                 goto err0;
         }
 
-        of_gc = gpio->data;
-        if (!of_gc) {
+        gc = of_node_to_gpiochip(gpio);
+        if (!gc) {
                 pr_debug("%s: gpio controller %s isn't registered\n",
                          root->full_name, gpio->full_name);
                 ret = -ENODEV;
                 goto err1;
         }
 
-        ret = of_gc->xlate(of_gc, root, gpio_spec, &flags);
+        ret = gc->of_xlate(gc, root, gpio_spec, &flags);
         if (ret < 0)
                 goto err1;
 
-        ret += of_gc->gc.base;
+        ret += gc->base;
 err1:
         of_node_put(gpio);
 err0:
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 17c98dbcec88..f5f768842354 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -213,15 +213,9 @@ static struct notifier_block dflt_plat_bus_notifier = {
         .priority = INT_MAX,
 };
 
-static struct notifier_block dflt_of_bus_notifier = {
-        .notifier_call = dflt_bus_notify,
-        .priority = INT_MAX,
-};
-
 static int __init setup_bus_notifier(void)
 {
         bus_register_notifier(&platform_bus_type, &dflt_plat_bus_notifier);
-        bus_register_notifier(&of_platform_bus_type, &dflt_of_bus_notifier);
 
         return 0;
 }
diff --git a/arch/microblaze/kernel/stacktrace.c b/arch/microblaze/kernel/stacktrace.c
index 123692f22647..84bc6686102c 100644
--- a/arch/microblaze/kernel/stacktrace.c
+++ b/arch/microblaze/kernel/stacktrace.c
@@ -14,52 +14,18 @@
 #include <linux/thread_info.h>
 #include <linux/ptrace.h>
 #include <linux/module.h>
+#include <asm/unwind.h>
 
-/* FIXME initial support */
 void save_stack_trace(struct stack_trace *trace)
 {
-        unsigned long *sp;
-        unsigned long addr;
-        asm("addik %0, r1, 0" : "=r" (sp));
-
-        while (!kstack_end(sp)) {
-                addr = *sp++;
-                if (__kernel_text_address(addr)) {
-                        if (trace->skip > 0)
-                                trace->skip--;
-                        else
-                                trace->entries[trace->nr_entries++] = addr;
-
-                        if (trace->nr_entries >= trace->max_entries)
-                                break;
-                }
-        }
+        /* Exclude our helper functions from the trace*/
+        trace->skip += 2;
+        microblaze_unwind(NULL, trace);
 }
 EXPORT_SYMBOL_GPL(save_stack_trace);
 
 void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 {
-        unsigned int *sp;
-        unsigned long addr;
-
-        struct thread_info *ti = task_thread_info(tsk);
-
-        if (tsk == current)
-                asm("addik %0, r1, 0" : "=r" (sp));
-        else
-                sp = (unsigned int *)ti->cpu_context.r1;
-
-        while (!kstack_end(sp)) {
-                addr = *sp++;
-                if (__kernel_text_address(addr)) {
-                        if (trace->skip > 0)
-                                trace->skip--;
-                        else
-                                trace->entries[trace->nr_entries++] = addr;
-
-                        if (trace->nr_entries >= trace->max_entries)
-                                break;
-                }
-        }
+        microblaze_unwind(tsk, trace);
 }
 EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index ed61b2f17719..b1380ae93ae1 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -28,6 +28,7 @@
 #include <asm/prom.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <linux/cnt32_to_63.h>
 
 #ifdef CONFIG_SELFMOD_TIMER
 #include <asm/selfmod.h>
@@ -135,7 +136,7 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode,
 static struct clock_event_device clockevent_microblaze_timer = {
         .name           = "microblaze_clockevent",
         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
-        .shift          = 24,
+        .shift          = 8,
         .rating         = 300,
         .set_next_event = microblaze_timer_set_next_event,
         .set_mode       = microblaze_timer_set_mode,
@@ -195,7 +196,7 @@ static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
 static struct cyclecounter microblaze_cc = {
         .read = microblaze_cc_read,
         .mask = CLOCKSOURCE_MASK(32),
-        .shift = 24,
+        .shift = 8,
 };
 
 int __init init_microblaze_timecounter(void)
@@ -213,7 +214,7 @@ static struct clocksource clocksource_microblaze = {
         .rating         = 300,
         .read           = microblaze_read,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 24, /* I can shift it */
+        .shift          = 8, /* I can shift it */
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -235,6 +236,12 @@ static int __init microblaze_clocksource_init(void)
         return 0;
 }
 
+/*
+ * We have to protect accesses before timer initialization
+ * and return 0 for sched_clock function below.
+ */
+static int timer_initialized;
+
 void __init time_init(void)
 {
         u32 irq, i = 0;
@@ -289,4 +296,15 @@ void __init time_init(void)
 #endif
         microblaze_clocksource_init();
         microblaze_clockevent_init();
+        timer_initialized = 1;
+}
+
+unsigned long long notrace sched_clock(void)
+{
+        if (timer_initialized) {
+                struct clocksource *cs = &clocksource_microblaze;
+                cycle_t cyc = cnt32_to_63(cs->read(NULL));
+                return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+        }
+        return 0;
 }
diff --git a/arch/microblaze/kernel/traps.c b/arch/microblaze/kernel/traps.c
index 75e49202a5ed..ba034d421ec2 100644
--- a/arch/microblaze/kernel/traps.c
+++ b/arch/microblaze/kernel/traps.c
@@ -16,13 +16,14 @@
 
 #include <asm/exceptions.h>
 #include <asm/system.h>
+#include <asm/unwind.h>
 
 void trap_init(void)
 {
         __enable_hw_exceptions();
 }
 
-static unsigned long kstack_depth_to_print = 24;
+static unsigned long kstack_depth_to_print;     /* 0 == entire stack */
 
 static int __init kstack_setup(char *s)
 {
@@ -30,31 +31,47 @@ static int __init kstack_setup(char *s)
 }
 __setup("kstack=", kstack_setup);
 
-void show_trace(struct task_struct *task, unsigned long *stack)
+void show_stack(struct task_struct *task, unsigned long *sp)
 {
-        unsigned long addr;
-
-        if (!stack)
-                stack = (unsigned long *)&stack;
+        unsigned long words_to_show;
+        u32 fp = (u32) sp;
+
+        if (fp == 0) {
+                if (task) {
+                        fp = ((struct thread_info *)
+                                (task->stack))->cpu_context.r1;
+                } else {
+                        /* Pick up caller of dump_stack() */
+                        fp = (u32)&sp - 8;
+                }
+        }
 
-        printk(KERN_NOTICE "Call Trace: ");
-#ifdef CONFIG_KALLSYMS
-        printk(KERN_NOTICE "\n");
-#endif
-        while (!kstack_end(stack)) {
-                addr = *stack++;
-                /*
-                 * If the address is either in the text segment of the
-                 * kernel, or in the region which contains vmalloc'ed
-                 * memory, it *may* be the address of a calling
-                 * routine; if so, print it so that someone tracing
-                 * down the cause of the crash will be able to figure
-                 * out the call path that was taken.
-                 */
-                if (kernel_text_address(addr))
-                        print_ip_sym(addr);
+        words_to_show = (THREAD_SIZE - (fp & (THREAD_SIZE - 1))) >> 2;
+        if (kstack_depth_to_print && (words_to_show > kstack_depth_to_print))
+                words_to_show = kstack_depth_to_print;
+
+        pr_info("Kernel Stack:\n");
+
+        /*
+         * Make the first line an 'odd' size if necessary to get
+         * remaining lines to start at an address multiple of 0x10
+         */
+        if (fp & 0xF) {
+                unsigned long line1_words = (0x10 - (fp & 0xF)) >> 2;
+                if (line1_words < words_to_show) {
+                        print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32,
+                                       4, (void *)fp, line1_words << 2, 0);
+                        fp += line1_words << 2;
+                        words_to_show -= line1_words;
+                }
         }
-        printk(KERN_NOTICE "\n");
+        print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4, (void *)fp,
+                       words_to_show << 2, 0);
+        printk(KERN_INFO "\n\n");
+
+        pr_info("Call Trace:\n");
+        microblaze_unwind(task, NULL);
+        pr_info("\n");
 
         if (!task)
                 task = current;
@@ -62,34 +79,6 @@ void show_trace(struct task_struct *task, unsigned long *stack)
         debug_show_held_locks(task);
 }
 
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
-        unsigned long *stack;
-        int i;
-
-        if (sp == NULL) {
-                if (task)
-                        sp = (unsigned long *) ((struct thread_info *)
-                                                (task->stack))->cpu_context.r1;
-                else
-                        sp = (unsigned long *)&sp;
-        }
-
-        stack = sp;
-
-        printk(KERN_INFO "\nStack:\n  ");
-
-        for (i = 0; i < kstack_depth_to_print; i++) {
-                if (kstack_end(sp))
-                        break;
-                if (i && ((i % 8) == 0))
-                        printk("\n  ");
-                printk("%08lx ", *sp++);
-        }
-        printk("\n");
-        show_trace(task, stack);
-}
-
 void dump_stack(void)
 {
         show_stack(NULL, NULL);
diff --git a/arch/microblaze/kernel/unwind.c b/arch/microblaze/kernel/unwind.c
new file mode 100644
index 000000000000..fefac5c33586
--- /dev/null
+++ b/arch/microblaze/kernel/unwind.c
@@ -0,0 +1,318 @@
+/*
+ * Backtrace support for Microblaze
+ *
+ * Copyright (C) 2010  Digital Design Corporation
+ *
+ * Based on arch/sh/kernel/cpu/sh5/unwind.c code which is:
+ * Copyright (C) 2004  Paul Mundt
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+/* #define DEBUG 1 */
+#include <linux/kallsyms.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <asm/sections.h>
+#include <asm/exceptions.h>
+#include <asm/unwind.h>
+
+struct stack_trace;
+
+/*
+ * On Microblaze, finding the previous stack frame is a little tricky.
+ * At this writing (3/2010), Microblaze does not support CONFIG_FRAME_POINTERS,
+ * and even if it did, gcc (4.1.2) does not store the frame pointer at
+ * a consistent offset within each frame. To determine frame size, it is
+ * necessary to search for the assembly instruction that creates or reclaims
+ * the frame and extract the size from it.
+ *
+ * Microblaze stores the stack pointer in r1, and creates a frame via
+ *
+ *     addik r1, r1, -FRAME_SIZE
+ *
+ * The frame is reclaimed via
+ *
+ *     addik r1, r1, FRAME_SIZE
+ *
+ * Frame creation occurs at or near the top of a function.
+ * Depending on the compiler, reclaim may occur at the end, or before
+ * a mid-function return.
+ *
+ * A stack frame is usually not created in a leaf function.
+ *
+ */
+
+/**
+ * get_frame_size - Extract the stack adjustment from an
+ *                  "addik r1, r1, adjust" instruction
+ * @instr : Microblaze instruction
+ *
+ * Return - Number of stack bytes the instruction reserves or reclaims
+ */
+inline long get_frame_size(unsigned long instr)
+{
+        return abs((s16)(instr & 0xFFFF));
+}
+
+/**
+ * find_frame_creation - Search backward to find the instruction that creates
+ *                       the stack frame (hopefully, for the same function the
+ *                       initial PC is in).
+ * @pc : Program counter at which to begin the search
+ *
+ * Return - PC at which stack frame creation occurs
+ *          NULL if this cannot be found, i.e. a leaf function
+ */
+static unsigned long *find_frame_creation(unsigned long *pc)
+{
+        int i;
+
+        /* NOTE: Distance to search is arbitrary
+         *       250 works well for most things,
+         *       750 picks up things like tcp_recvmsg(),
+         *      1000 needed for fat_fill_super()
+         */
+        for (i = 0; i < 1000; i++, pc--) {
+                unsigned long instr;
+                s16 frame_size;
+
+                if (!kernel_text_address((unsigned long) pc))
+                        return NULL;
+
+                instr = *pc;
+
+                /* addik r1, r1, foo ? */
+                if ((instr & 0xFFFF0000) != 0x30210000)
+                        continue;       /* No */
+
+                frame_size = get_frame_size(instr);
+                if ((frame_size < 8) || (frame_size & 3)) {
+                        pr_debug("    Invalid frame size %d at 0x%p\n",
+                                 frame_size, pc);
+                        return NULL;
+                }
+
+                pr_debug("    Found frame creation at 0x%p, size %d\n", pc,
+                         frame_size);
+                return pc;
+        }
+
+        return NULL;
+}
+
+/**
+ * lookup_prev_stack_frame - Find the stack frame of the previous function.
+ * @fp          : Frame (stack) pointer for current function
+ * @pc          : Program counter within current function
+ * @leaf_return : r15 value within current function. If the current function
+ *                is a leaf, this is the caller's return address.
+ * @pprev_fp    : On exit, set to frame (stack) pointer for previous function
+ * @pprev_pc    : On exit, set to current function caller's return address
+ *
+ * Return - 0 on success, -EINVAL if the previous frame cannot be found
+ */
+static int lookup_prev_stack_frame(unsigned long fp, unsigned long pc,
+                                   unsigned long leaf_return,
+                                   unsigned long *pprev_fp,
+                                   unsigned long *pprev_pc)
+{
+        unsigned long *prologue = NULL;
+
+        /* _switch_to is a special leaf function */
+        if (pc != (unsigned long) &_switch_to)
+                prologue = find_frame_creation((unsigned long *)pc);
+
+        if (prologue) {
+                long frame_size = get_frame_size(*prologue);
+
+                *pprev_fp = fp + frame_size;
+                *pprev_pc = *(unsigned long *)fp;
+        } else {
+                if (!leaf_return)
+                        return -EINVAL;
+                *pprev_pc = leaf_return;
+                *pprev_fp = fp;
+        }
+
+        /* NOTE: don't check kernel_text_address here, to allow display
+         *       of userland return address
+         */
+        return (!*pprev_pc || (*pprev_pc & 3)) ? -EINVAL : 0;
+}
+
+static void microblaze_unwind_inner(struct task_struct *task,
+                                    unsigned long pc, unsigned long fp,
+                                    unsigned long leaf_return,
+                                    struct stack_trace *trace);
+
+/**
+ * unwind_trap - Unwind through a system trap, that stored previous state
+ *               on the stack.
+ */
+#ifdef CONFIG_MMU
+static inline void unwind_trap(struct task_struct *task, unsigned long pc,
+                                unsigned long fp, struct stack_trace *trace)
+{
+        /* To be implemented */
+}
+#else
+static inline void unwind_trap(struct task_struct *task, unsigned long pc,
+                                unsigned long fp, struct stack_trace *trace)
+{
+        const struct pt_regs *regs = (const struct pt_regs *) fp;
+        microblaze_unwind_inner(task, regs->pc, regs->r1, regs->r15, trace);
+}
+#endif
+
+/**
+ * microblaze_unwind_inner - Unwind the stack from the specified point
+ * @task  : Task whose stack we are to unwind (may be NULL)
+ * @pc    : Program counter from which we start unwinding
+ * @fp    : Frame (stack) pointer from which we start unwinding
+ * @leaf_return : Value of r15 at pc. If the function is a leaf, this is
+ *                                the caller's return address.
+ * @trace : Where to store stack backtrace (PC values).
+ *          NULL == print backtrace to kernel log
+ */
+void microblaze_unwind_inner(struct task_struct *task,
+                             unsigned long pc, unsigned long fp,
+                             unsigned long leaf_return,
+                             struct stack_trace *trace)
+{
+        int ofs = 0;
+
+        pr_debug("    Unwinding with PC=%p, FP=%p\n", (void *)pc, (void *)fp);
+        if (!pc || !fp || (pc & 3) || (fp & 3)) {
+                pr_debug("    Invalid state for unwind, aborting\n");
+                return;
+        }
+        for (; pc != 0;) {
+                unsigned long next_fp, next_pc = 0;
+                unsigned long return_to = pc +  2 * sizeof(unsigned long);
+                const struct trap_handler_info *handler =
+                        &microblaze_trap_handlers;
+
+                /* Is previous function the HW exception handler? */
+                if ((return_to >= (unsigned long)&_hw_exception_handler)
+                    &&(return_to < (unsigned long)&ex_handler_unhandled)) {
+                        /*
+                         * HW exception handler doesn't save all registers,
+                         * so we open-code a special case of unwind_trap()
+                         */
+#ifndef CONFIG_MMU
+                        const struct pt_regs *regs =
+                                (const struct pt_regs *) fp;
+#endif
+                        pr_info("HW EXCEPTION\n");
+#ifndef CONFIG_MMU
+                        microblaze_unwind_inner(task, regs->r17 - 4,
+                                                fp + EX_HANDLER_STACK_SIZ,
+                                                regs->r15, trace);
+#endif
+                        return;
+                }
+
+                /* Is previous function a trap handler? */
+                for (; handler->start_addr; ++handler) {
+                        if ((return_to >= handler->start_addr)
+                            && (return_to <= handler->end_addr)) {
+                                if (!trace)
+                                        pr_info("%s\n", handler->trap_name);
+                                unwind_trap(task, pc, fp, trace);
+                                return;
+                        }
+                }
+                pc -= ofs;
+
+                if (trace) {
+#ifdef CONFIG_STACKTRACE
+                        if (trace->skip > 0)
+                                trace->skip--;
+                        else
+                                trace->entries[trace->nr_entries++] = pc;
+
+                        if (trace->nr_entries >= trace->max_entries)
+                                break;
+#endif
+                } else {
+                        /* Have we reached userland? */
+                        if (unlikely(pc == task_pt_regs(task)->pc)) {
+                                pr_info("[<%p>] PID %lu [%s]\n",
+                                        (void *) pc,
+                                        (unsigned long) task->pid,
+                                        task->comm);
+                                break;
+                        } else
+                                print_ip_sym(pc);
+                }
+
+                /* Stop when we reach anything not part of the kernel */
+                if (!kernel_text_address(pc))
+                        break;
+
+                if (lookup_prev_stack_frame(fp, pc, leaf_return, &next_fp,
+                                            &next_pc) == 0) {
+                        ofs = sizeof(unsigned long);
+                        pc = next_pc & ~3;
+                        fp = next_fp;
+                        leaf_return = 0;
+                } else {
+                        pr_debug("    Failed to find previous stack frame\n");
+                        break;
+                }
+
+                pr_debug("    Next PC=%p, next FP=%p\n",
+                         (void *)next_pc, (void *)next_fp);
+        }
+}
+
+/**
+ * microblaze_unwind - Stack unwinder for Microblaze (external entry point)
+ * @task  : Task whose stack we are to unwind (NULL == current)
+ * @trace : Where to store stack backtrace (PC values).
+ *          NULL == print backtrace to kernel log
+ */
+void microblaze_unwind(struct task_struct *task, struct stack_trace *trace)
+{
+        if (task) {
+                if (task == current) {
+                        const struct pt_regs *regs = task_pt_regs(task);
+                        microblaze_unwind_inner(task, regs->pc, regs->r1,
+                                                regs->r15, trace);
+                } else {
+                        struct thread_info *thread_info =
+                                (struct thread_info *)(task->stack);
+                        const struct cpu_context *cpu_context =
+                                &thread_info->cpu_context;
+
+                        microblaze_unwind_inner(task,
+                                                (unsigned long) &_switch_to,
+                                                cpu_context->r1,
+                                                cpu_context->r15, trace);
+                }
+        } else {
+                unsigned long pc, fp;
+
+                __asm__ __volatile__ ("or %0, r1, r0" : "=r" (fp));
+
+                __asm__ __volatile__ (
+                        "brlid %0, 0f;"
+                        "nop;"
+                        "0:"
+                        : "=r" (pc)
+                );
+
+                /* Since we are not a leaf function, use leaf_return = 0 */
+                microblaze_unwind_inner(current, pc, fp, 0, trace);
+        }
+}
+
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index db72d7124602..a09f2962fbec 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -10,7 +10,7 @@
 
 OUTPUT_FORMAT("elf32-microblaze", "elf32-microblaze", "elf32-microblaze")
 OUTPUT_ARCH(microblaze)
-ENTRY(_start)
+ENTRY(microblaze_start)
 
 #include <asm/page.h>
 #include <asm-generic/vmlinux.lds.h>
@@ -20,7 +20,7 @@ jiffies = jiffies_64 + 4;
 
 SECTIONS {
         . = CONFIG_KERNEL_START;
-        _start = CONFIG_KERNEL_BASE_ADDR;
+        microblaze_start = CONFIG_KERNEL_BASE_ADDR;
         .text : AT(ADDR(.text) - LOAD_OFFSET) {
                 _text = . ;
                 _stext = . ;
@@ -55,7 +55,7 @@ SECTIONS {
          */
         .sdata2 : AT(ADDR(.sdata2) - LOAD_OFFSET) {
                 _ssrw = .;
-                . = ALIGN(4096); /* page aligned when MMU used - origin 0x8 */
+                . = ALIGN(PAGE_SIZE); /* page aligned when MMU used */
                 *(.sdata2)
         . = ALIGN(8);
         _essrw = .;
@@ -70,7 +70,7 @@ SECTIONS {
         /* Reserve some low RAM for r0 based memory references */
         . = ALIGN(0x4) ;
         r0_ram = . ;
-        . = . +  4096;  /* a page should be enough */
+        . = . +  PAGE_SIZE;     /* a page should be enough */
 
         /* Under the microblaze ABI, .sdata and .sbss must be contiguous */
         . = ALIGN(8);
@@ -120,7 +120,7 @@ SECTIONS {
 
         __init_end_before_initramfs = .;
 
-        .init.ramfs ALIGN(4096) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
+        .init.ramfs ALIGN(PAGE_SIZE) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
                 __initramfs_start = .;
                 *(.init.ramfs)
                 __initramfs_end = .;
@@ -132,11 +132,11 @@ SECTIONS {
  * so that __init_end == __bss_start. This will make image.elf
  * consistent with the image.bin
  */
-                /* . = ALIGN(4096); */
+                /* . = ALIGN(PAGE_SIZE); */
         }
         __init_end = .;
 
-        .bss ALIGN (4096) : AT(ADDR(.bss) - LOAD_OFFSET) {
+        .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) {
                 /* page aligned when MMU used */
                 __bss_start = . ;
                         *(.bss*)
@@ -145,7 +145,7 @@ SECTIONS {
                 __bss_stop = . ;
                 _ebss = . ;
         }
-        . = ALIGN(4096);
+        . = ALIGN(PAGE_SIZE);
         _end = .;
 
         DISCARDS
diff --git a/arch/microblaze/mm/fault.c b/arch/microblaze/mm/fault.c
index bab922993185..57bd2a09610c 100644
--- a/arch/microblaze/mm/fault.c
+++ b/arch/microblaze/mm/fault.c
@@ -37,10 +37,6 @@
 #include <linux/uaccess.h>
 #include <asm/exceptions.h>
 
-#if defined(CONFIG_KGDB)
-int debugger_kernel_faults = 1;
-#endif
-
 static unsigned long pte_misses;        /* updated by do_page_fault() */
 static unsigned long pte_errors;        /* updated by do_page_fault() */
 
@@ -81,10 +77,6 @@ void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig)
         }
 
         /* kernel has accessed a bad area */
-#if defined(CONFIG_KGDB)
-        if (debugger_kernel_faults)
-                debugger(regs);
-#endif
         die("kernel access of bad area", regs, sig);
 }
 
@@ -115,13 +107,6 @@ void do_page_fault(struct pt_regs *regs, unsigned long address,
         if ((error_code & 0x13) == 0x13 || (error_code & 0x11) == 0x11)
                 is_write = 0;
 
-#if defined(CONFIG_KGDB)
-        if (debugger_fault_handler && regs->trap == 0x300) {
-                debugger_fault_handler(regs);
-                return;
-        }
-#endif /* CONFIG_KGDB */
-
         if (unlikely(in_atomic() || !mm)) {
                 if (kernel_mode(regs))
                         goto bad_area_nosemaphore;
@@ -226,7 +211,6 @@ good_area:
          * make sure we exit gracefully rather than endlessly redo
          * the fault.
          */
-survive:
         fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0);
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index db5934989926..65eb00419d19 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -134,13 +134,8 @@ void __init setup_memory(void)
          * for 4GB of memory, using 4kB pages), plus 1 page
          * (in case the address isn't page-aligned).
          */
-#ifndef CONFIG_MMU
-        map_size = init_bootmem_node(NODE_DATA(0), PFN_UP(TOPHYS((u32)klimit)),
-                                        min_low_pfn, max_low_pfn);
-#else
-        map_size = init_bootmem_node(&contig_page_data,
+        map_size = init_bootmem_node(NODE_DATA(0),
                 PFN_UP(TOPHYS((u32)klimit)), min_low_pfn, max_low_pfn);
-#endif
         memblock_reserve(PFN_UP(TOPHYS((u32)klimit)) << PAGE_SHIFT, map_size);
 
         /* free bootmem is whole main memory */
diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
new file mode 100644
index 000000000000..e322d65f33a4
--- /dev/null
+++ b/arch/mips/Kbuild
@@ -0,0 +1,15 @@
+# Fail on warnings - also for files referenced in subdirs
+# -Werror can be disabled for specific files using:
+# CFLAGS_<file.o> := -Wno-error
+subdir-ccflags-y := -Werror
+
+# platform specific definitions
+include arch/mips/Kbuild.platforms
+obj-y := $(platform-y)
+
+# mips object files
+# The object files are linked as core-y files would be linked
+
+obj-y += kernel/
+obj-y += mm/
+obj-y += math-emu/
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
new file mode 100644
index 000000000000..78439b8a83c4
--- /dev/null
+++ b/arch/mips/Kbuild.platforms
@@ -0,0 +1,32 @@
+# All platforms listed in alphabetic order
+
+platforms += alchemy
+platforms += ar7
+platforms += bcm47xx
+platforms += bcm63xx
+platforms += cavium-octeon
+platforms += cobalt
+platforms += dec
+platforms += emma
+platforms += jazz
+platforms += jz4740
+platforms += lasat
+platforms += loongson
+platforms += mipssim
+platforms += mti-malta
+platforms += pmc-sierra
+platforms += pnx833x
+platforms += pnx8550
+platforms += powertv
+platforms += rb532
+platforms += sgi-ip22
+platforms += sgi-ip27
+platforms += sgi-ip32
+platforms += sibyte
+platforms += sni
+platforms += txx9
+platforms += vr41xx
+platforms += wrppmc
+
+# include the platform specific files
+include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cdaae942623d..3ad59dde4852 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -10,6 +10,8 @@ config MIPS
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FTRACE_MCOUNT_RECORD
         select HAVE_FUNCTION_GRAPH_TRACER
+        select HAVE_KPROBES
+        select HAVE_KRETPROBES
         select RTC_LIB if !MACH_LOONGSON
 
 mainmenu "Linux/MIPS Kernel Configuration"
@@ -23,8 +25,17 @@ choice
         prompt "System type"
         default SGI_IP22
 
-config MACH_ALCHEMY
+config MIPS_ALCHEMY
         bool "Alchemy processor based machines"
+        select 64BIT_PHYS_ADDR
+        select CEVT_R4K_LIB
+        select CSRC_R4K_LIB
+        select IRQ_CPU
+        select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_APM_EMULATION
+        select GENERIC_GPIO
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select SYS_SUPPORTS_ZBOOT
 
 config AR7
@@ -62,6 +73,7 @@ config BCM47XX
         select SSB_DRIVER_MIPS
         select SSB_DRIVER_EXTIF
         select SSB_EMBEDDED
+        select SSB_B43_PCI_BRIDGE if PCI
         select SSB_PCICORE_HOSTMODE if PCI
         select GENERIC_GPIO
         select SYS_HAS_EARLY_PRINTK
@@ -162,6 +174,18 @@ config MACH_JAZZ
          Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
          Olivetti M700-10 workstations.
 
+config MACH_JZ4740
+        bool "Ingenic JZ4740 based machines"
+        select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select SYS_HAS_EARLY_PRINTK
+        select HAVE_PWM
+
 config LASAT
         bool "LASAT Networks platforms"
         select CEVT_R4K
@@ -686,6 +710,7 @@ endchoice
 source "arch/mips/alchemy/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
+source "arch/mips/jz4740/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
 source "arch/mips/powertv/Kconfig"
@@ -733,10 +758,6 @@ config GENERIC_CLOCKEVENTS
         bool
         default y
 
-config GENERIC_TIME
-        bool
-        default y
-
 config GENERIC_CMOS_UPDATE
         bool
         default y
@@ -892,6 +913,9 @@ config CPU_LITTLE_ENDIAN
 
 endchoice
 
+config EXPORT_UASM
+        bool
+
 config SYS_SUPPORTS_APM_EMULATION
         bool
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0b9c01add0a0..f4a4b663ebb3 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -93,7 +93,8 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
 cflags-y                        += -G 0 -mno-abicalls -fno-pic -pipe
 cflags-y                        += -msoft-float
 LDFLAGS_vmlinux                 += -G 0 -static -n -nostdlib
-MODFLAGS                        += -mlong-calls
+KBUILD_AFLAGS_MODULE            += -mlong-calls
+KBUILD_CFLAGS_MODULE            += -mlong-calls
 
 cflags-y += -ffreestanding
 
@@ -130,26 +131,6 @@ cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
 cflags-$(CONFIG_CPU_VR41XX)     += -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)      += -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_TX49XX)     += -march=r4600 -Wa,--trap
-# only gcc >= 4.4 have the loongson-specific support
-cflags-$(CONFIG_CPU_LOONGSON2)  += -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2E) += \
-        $(call cc-option,-march=loongson2e,-march=r4600)
-cflags-$(CONFIG_CPU_LOONGSON2F) += \
-        $(call cc-option,-march=loongson2f,-march=r4600)
-# enable the workarounds for loongson2f
-ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
-  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
-    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
-  else
-    cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
-  endif
-  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
-    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
-  else
-    cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
-  endif
-endif
-
 cflags-$(CONFIG_CPU_MIPS32_R1)  += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
                         -Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)  += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -185,7 +166,8 @@ cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)
 
 ifdef CONFIG_CPU_SB1
 ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
-MODFLAGS        += -msb1-pass1-workarounds
+KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds
+KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds
 endif
 endif
 
@@ -209,455 +191,7 @@ endif
 #
 # Board-dependent options and extra files
 #
-
-#
-# Texas Instruments AR7
-#
-core-$(CONFIG_AR7)              += arch/mips/ar7/
-cflags-$(CONFIG_AR7)            += -I$(srctree)/arch/mips/include/asm/mach-ar7
-load-$(CONFIG_AR7)              += 0xffffffff94100000
-
-#
-# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
-#
-core-$(CONFIG_MACH_JAZZ)        += arch/mips/jazz/
-cflags-$(CONFIG_MACH_JAZZ)      += -I$(srctree)/arch/mips/include/asm/mach-jazz
-load-$(CONFIG_MACH_JAZZ)        += 0xffffffff80080000
-
-#
-# Common Alchemy Au1x00 stuff
-#
-core-$(CONFIG_SOC_AU1X00)       += arch/mips/alchemy/common/
-
-#
-# AMD Alchemy Pb1000 eval board
-#
-core-$(CONFIG_MIPS_PB1000)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1000)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1000)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1100 eval board
-#
-core-$(CONFIG_MIPS_PB1100)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1100)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1100)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1500 eval board
-#
-core-$(CONFIG_MIPS_PB1500)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1500)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1500)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1550 eval board
-#
-core-$(CONFIG_MIPS_PB1550)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1550)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1550)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1200 eval board
-#
-core-$(CONFIG_MIPS_PB1200)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1200)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1200)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1000 eval board
-#
-core-$(CONFIG_MIPS_DB1000)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1000)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1000)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1100 eval board
-#
-core-$(CONFIG_MIPS_DB1100)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1100)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1100)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1500 eval board
-#
-core-$(CONFIG_MIPS_DB1500)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1500)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1500)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1550 eval board
-#
-core-$(CONFIG_MIPS_DB1550)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1550)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1550)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1200 eval board
-#
-core-$(CONFIG_MIPS_DB1200)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1200)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1200)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Bosporus eval board
-#
-core-$(CONFIG_MIPS_BOSPORUS)    += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_BOSPORUS)  += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_BOSPORUS)    += 0xffffffff80100000
-
-#
-# AMD Alchemy Mirage eval board
-#
-core-$(CONFIG_MIPS_MIRAGE)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_MIRAGE)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_MIRAGE)      += 0xffffffff80100000
-
-#
-# 4G-Systems eval board
-#
-libs-$(CONFIG_MIPS_MTX1)        += arch/mips/alchemy/mtx-1/
-load-$(CONFIG_MIPS_MTX1)        += 0xffffffff80100000
-
-#
-# MyCable eval board
-#
-libs-$(CONFIG_MIPS_XXS1500)     += arch/mips/alchemy/xxs1500/
-load-$(CONFIG_MIPS_XXS1500)     += 0xffffffff80100000
-
-# must be last for Alchemy systems for GPIO to work properly
-cflags-$(CONFIG_SOC_AU1X00)     += -I$(srctree)/arch/mips/include/asm/mach-au1x00
-
-
-#
-# Cobalt Server
-#
-core-$(CONFIG_MIPS_COBALT)      += arch/mips/cobalt/
-cflags-$(CONFIG_MIPS_COBALT)    += -I$(srctree)/arch/mips/include/asm/mach-cobalt
-load-$(CONFIG_MIPS_COBALT)      += 0xffffffff80080000
-
-#
-# DECstation family
-#
-core-$(CONFIG_MACH_DECSTATION)  += arch/mips/dec/
-cflags-$(CONFIG_MACH_DECSTATION)+= -I$(srctree)/arch/mips/include/asm/mach-dec
-libs-$(CONFIG_MACH_DECSTATION)  += arch/mips/dec/prom/
-load-$(CONFIG_MACH_DECSTATION)  += 0xffffffff80040000
-
-#
-# Wind River PPMC Board (4KC + GT64120)
-#
-core-$(CONFIG_WR_PPMC)          += arch/mips/gt64120/wrppmc/
-cflags-$(CONFIG_WR_PPMC)                += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
-load-$(CONFIG_WR_PPMC)          += 0xffffffff80100000
-
-#
-# Loongson family
-#
-core-$(CONFIG_MACH_LOONGSON) += arch/mips/loongson/
-cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
-                    -mno-branch-likely
-load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
-load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
-
-#
-# MIPS Malta board
-#
-core-$(CONFIG_MIPS_MALTA)       += arch/mips/mti-malta/
-cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
-load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
-all-$(CONFIG_MIPS_MALTA)        := $(COMPRESSION_FNAME).bin
-
-#
-# MIPS SIM
-#
-core-$(CONFIG_MIPS_SIM)         += arch/mips/mipssim/
-cflags-$(CONFIG_MIPS_SIM)       += -I$(srctree)/arch/mips/include/asm/mach-mipssim
-load-$(CONFIG_MIPS_SIM)         += 0x80100000
-
-#
-# PMC-Sierra MSP SOCs
-#
-core-$(CONFIG_PMC_MSP)          += arch/mips/pmc-sierra/msp71xx/
-cflags-$(CONFIG_PMC_MSP)        += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
-                                        -mno-branch-likely
-load-$(CONFIG_PMC_MSP)          += 0xffffffff80100000
-
-#
-# PMC-Sierra Yosemite
-#
-core-$(CONFIG_PMC_YOSEMITE)     += arch/mips/pmc-sierra/yosemite/
-cflags-$(CONFIG_PMC_YOSEMITE)   += -I$(srctree)/arch/mips/include/asm/mach-yosemite
-load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
-
-#
-# LASAT platforms
-#
-core-$(CONFIG_LASAT)            += arch/mips/lasat/
-cflags-$(CONFIG_LASAT)          += -I$(srctree)/arch/mips/include/asm/mach-lasat
-load-$(CONFIG_LASAT)            += 0xffffffff80000000
-
-#
-# Common VR41xx
-#
-core-$(CONFIG_MACH_VR41XX)      += arch/mips/vr41xx/common/
-cflags-$(CONFIG_MACH_VR41XX)    += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
-
-#
-# ZAO Networks Capcella (VR4131)
-#
-load-$(CONFIG_ZAO_CAPCELLA)     += 0xffffffff80000000
-
-#
-# Victor MP-C303/304 (VR4122)
-#
-load-$(CONFIG_VICTOR_MPC30X)    += 0xffffffff80001000
-
-#
-# IBM WorkPad z50 (VR4121)
-#
-core-$(CONFIG_IBM_WORKPAD)      += arch/mips/vr41xx/ibm-workpad/
-load-$(CONFIG_IBM_WORKPAD)      += 0xffffffff80004000
-
-#
-# CASIO CASSIPEIA E-55/65 (VR4111)
-#
-core-$(CONFIG_CASIO_E55)        += arch/mips/vr41xx/casio-e55/
-load-$(CONFIG_CASIO_E55)        += 0xffffffff80004000
-
-#
-# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
-#
-load-$(CONFIG_TANBAC_TB022X)    += 0xffffffff80000000
-
-# NXP STB225
-core-$(CONFIG_SOC_PNX833X)              += arch/mips/nxp/pnx833x/common/
-cflags-$(CONFIG_SOC_PNX833X)    += -Iarch/mips/include/asm/mach-pnx833x
-libs-$(CONFIG_NXP_STB220)               += arch/mips/nxp/pnx833x/stb22x/
-load-$(CONFIG_NXP_STB220)               += 0xffffffff80001000
-libs-$(CONFIG_NXP_STB225)               += arch/mips/nxp/pnx833x/stb22x/
-load-$(CONFIG_NXP_STB225)               += 0xffffffff80001000
-
-#
-# Common NXP PNX8550
-#
-core-$(CONFIG_SOC_PNX8550)      += arch/mips/nxp/pnx8550/common/
-cflags-$(CONFIG_SOC_PNX8550)    += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
-
-#
-# NXP PNX8550 JBS board
-#
-libs-$(CONFIG_PNX8550_JBS)      += arch/mips/nxp/pnx8550/jbs/
-#cflags-$(CONFIG_PNX8550_JBS)   += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
-load-$(CONFIG_PNX8550_JBS)      += 0xffffffff80060000
-
-# NXP PNX8550 STB810 board
-#
-libs-$(CONFIG_PNX8550_STB810)   += arch/mips/nxp/pnx8550/stb810/
-load-$(CONFIG_PNX8550_STB810)   += 0xffffffff80060000
-
-#
-# Common NEC EMMAXXX
-#
-core-$(CONFIG_SOC_EMMA2RH)      += arch/mips/emma/common/
-cflags-$(CONFIG_SOC_EMMA2RH)    += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
-
-#
-# NEC EMMA2RH Mark-eins
-#
-core-$(CONFIG_NEC_MARKEINS)     += arch/mips/emma/markeins/
-load-$(CONFIG_NEC_MARKEINS)     += 0xffffffff88100000
-
-#
-# Cisco PowerTV Platform
-#
-core-$(CONFIG_POWERTV)          += arch/mips/powertv/
-cflags-$(CONFIG_POWERTV)        += -I$(srctree)/arch/mips/include/asm/mach-powertv
-load-$(CONFIG_POWERTV)          += 0xffffffff90800000
-
-#
-# SGI IP22 (Indy/Indigo2)
-#
-# Set the load address to >= 0xffffffff88069000 if you want to leave space for
-# symmon, 0xffffffff80002000 for production kernels.  Note that the value must
-# be aligned to a multiple of the kernel stack size or the handling of the
-# current variable will break so for 64-bit kernels we have to raise the start
-# address by 8kb.
-#
-core-$(CONFIG_SGI_IP22)         += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP22)       += -I$(srctree)/arch/mips/include/asm/mach-ip22
-ifdef CONFIG_32BIT
-load-$(CONFIG_SGI_IP22)         += 0xffffffff88002000
-endif
-ifdef CONFIG_64BIT
-load-$(CONFIG_SGI_IP22)         += 0xffffffff88004000
-endif
-
-#
-# SGI-IP27 (Origin200/2000)
-#
-# Set the load address to >= 0xc000000000300000 if you want to leave space for
-# symmon, 0xc00000000001c000 for production kernels.  Note that the value must
-# be 16kb aligned or the handling of the current variable will break.
-#
-ifdef CONFIG_SGI_IP27
-core-$(CONFIG_SGI_IP27)         += arch/mips/sgi-ip27/
-cflags-$(CONFIG_SGI_IP27)       += -I$(srctree)/arch/mips/include/asm/mach-ip27
-ifdef CONFIG_MAPPED_KERNEL
-load-$(CONFIG_SGI_IP27)         += 0xc00000004001c000
-OBJCOPYFLAGS                    := --change-addresses=0x3fffffff80000000
-dataoffset-$(CONFIG_SGI_IP27)   += 0x01000000
-else
-load-$(CONFIG_SGI_IP27)         += 0xa80000000001c000
-OBJCOPYFLAGS                    := --change-addresses=0x57ffffff80000000
-endif
-endif
-
-#
-# SGI IP28 (Indigo2 R10k)
-#
-# Set the load address to >= 0xa800000020080000 if you want to leave space for
-# symmon, 0xa800000020004000 for production kernels ?  Note that the value must
-# be 16kb aligned or the handling of the current variable will break.
-# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
-#
-ifdef CONFIG_SGI_IP28
-  ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
-      $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
-  endif
-endif
-core-$(CONFIG_SGI_IP28)         += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP28)       += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
-load-$(CONFIG_SGI_IP28)         += 0xa800000020004000
-
-#
-# SGI-IP32 (O2)
-#
-# Set the load address to >= 80069000 if you want to leave space for symmon,
-# 0xffffffff80004000 for production kernels.  Note that the value must be aligned to
-# a multiple of the kernel stack size or the handling of the current variable
-# will break.
-#
-core-$(CONFIG_SGI_IP32)         += arch/mips/sgi-ip32/
-cflags-$(CONFIG_SGI_IP32)       += -I$(srctree)/arch/mips/include/asm/mach-ip32
-load-$(CONFIG_SGI_IP32)         += 0xffffffff80004000
-
-#
-# Sibyte SB1250/BCM1480 SOC
-#
-# This is a LIB so that it links at the end, and initcalls are later
-# the sequence; but it is built as an object so that modules don't get
-# removed (as happens, even if they have __initcall/module_init)
-#
-core-$(CONFIG_SIBYTE_BCM112X)   += arch/mips/sibyte/sb1250/
-core-$(CONFIG_SIBYTE_BCM112X)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM112X) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
-
-core-$(CONFIG_SIBYTE_SB1250)    += arch/mips/sibyte/sb1250/
-core-$(CONFIG_SIBYTE_SB1250)    += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_SB1250)  += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
-
-core-$(CONFIG_SIBYTE_BCM1x55)   += arch/mips/sibyte/bcm1480/
-core-$(CONFIG_SIBYTE_BCM1x55)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x55) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
-
-core-$(CONFIG_SIBYTE_BCM1x80)   += arch/mips/sibyte/bcm1480/
-core-$(CONFIG_SIBYTE_BCM1x80)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x80) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
-
-#
-# Sibyte BCM91120x (Carmel) board
-# Sibyte BCM91120C (CRhine) board
-# Sibyte BCM91125C (CRhone) board
-# Sibyte BCM91125E (Rhone) board
-# Sibyte SWARM board
-# Sibyte BCM91x80 (BigSur) board
-#
-core-$(CONFIG_SIBYTE_CARMEL)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CARMEL)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_CRHINE)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CRHINE)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_CRHONE)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CRHONE)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_RHONE)     += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_RHONE)     := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_SENTOSA)   += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_SENTOSA)   := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_SWARM)     += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_SWARM)     := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_BIGSUR)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_BIGSUR)    := 0xffffffff80100000
-
-#
-# Broadcom BCM47XX boards
-#
-core-$(CONFIG_BCM47XX)          += arch/mips/bcm47xx/
-cflags-$(CONFIG_BCM47XX)        += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
-load-$(CONFIG_BCM47XX)          := 0xffffffff80001000
-
-#
-# Broadcom BCM63XX boards
-#
-core-$(CONFIG_BCM63XX)          += arch/mips/bcm63xx/
-cflags-$(CONFIG_BCM63XX)        += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
-load-$(CONFIG_BCM63XX)          := 0xffffffff80010000
-
-#
-# SNI RM
-#
-core-$(CONFIG_SNI_RM)           += arch/mips/sni/
-cflags-$(CONFIG_SNI_RM)         += -I$(srctree)/arch/mips/include/asm/mach-rm
-ifdef CONFIG_CPU_LITTLE_ENDIAN
-load-$(CONFIG_SNI_RM)           += 0xffffffff80600000
-else
-load-$(CONFIG_SNI_RM)           += 0xffffffff80030000
-endif
-all-$(CONFIG_SNI_RM)            := $(COMPRESSION_FNAME).ecoff
-
-#
-# Common TXx9
-#
-core-$(CONFIG_MACH_TX39XX)      += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX39XX) += -I$(srctree)/arch/mips/include/asm/mach-tx39xx
-load-$(CONFIG_MACH_TX39XX)      += 0xffffffff80050000
-core-$(CONFIG_MACH_TX49XX)      += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX49XX) += -I$(srctree)/arch/mips/include/asm/mach-tx49xx
-load-$(CONFIG_MACH_TX49XX)      += 0xffffffff80100000
-
-#
-# Toshiba JMR-TX3927 board
-#
-core-$(CONFIG_TOSHIBA_JMR3927)  += arch/mips/txx9/jmr3927/
-
-#
-# Routerboard 532 board
-#
-core-$(CONFIG_MIKROTIK_RB532)   += arch/mips/rb532/
-cflags-$(CONFIG_MIKROTIK_RB532) += -I$(srctree)/arch/mips/include/asm/mach-rc32434
-load-$(CONFIG_MIKROTIK_RB532)   += 0xffffffff80101000
-
-#
-# Toshiba RBTX49XX boards
-#
-core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
-core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
-core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
-
-#
-# Cavium Octeon
-#
-core-$(CONFIG_CPU_CAVIUM_OCTEON)        += arch/mips/cavium-octeon/
-cflags-$(CONFIG_CPU_CAVIUM_OCTEON)      += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
-core-$(CONFIG_CPU_CAVIUM_OCTEON)        += arch/mips/cavium-octeon/executive/
-ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
-load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff84100000
-else
-load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff81100000
-endif
+include $(srctree)/arch/mips/Kbuild.platforms
 
 cflags-y                        += -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)           += arch/mips/pci/
@@ -706,7 +240,8 @@ head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
 
 libs-y                  += arch/mips/lib/
 
-core-y                  += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
+# See arch/mips/Kbuild for content of core part of the kernel
+core-y += arch/mips/
 
 drivers-$(CONFIG_OPROFILE)      += arch/mips/oprofile/
 
@@ -726,6 +261,9 @@ endif
 vmlinux.32: vmlinux
         $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 
+
+#obj-$(CONFIG_KPROBES)          += kprobes.o
+
 #
 # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
 # ELF files from 32-bit files by conversion.
@@ -733,35 +271,19 @@ vmlinux.32: vmlinux
 vmlinux.64: vmlinux
         $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
 
-makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
-makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
-           VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
-
 all:    $(all-y)
 
-vmlinuz: vmlinux FORCE
-        +@$(call makezboot,$@)
+# boot
+vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE
+        $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@
 
-vmlinuz.bin: vmlinux
-        +@$(call makezboot,$@)
+# boot/compressed
+vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE
+        $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
+           VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@
 
-vmlinuz.ecoff: vmlinux
-        +@$(call makezboot,$@)
 
-vmlinuz.srec: vmlinux
-        +@$(call makezboot,$@)
-
-vmlinux.bin: $(vmlinux-32)
-        +@$(call makeboot,$@)
-
-vmlinux.ecoff: $(vmlinux-32)
-        +@$(call makeboot,$@)
-
-vmlinux.srec: $(vmlinux-32)
-        +@$(call makeboot,$@)
-
-CLEAN_FILES += vmlinux.ecoff \
-               vmlinux.srec
+CLEAN_FILES += vmlinux.32 vmlinux.64
 
 archprepare:
 ifdef CONFIG_MIPS32_N32
@@ -780,9 +302,9 @@ install:
         $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
 
 archclean:
-        @$(MAKE) $(clean)=arch/mips/boot
-        @$(MAKE) $(clean)=arch/mips/boot/compressed
-        @$(MAKE) $(clean)=arch/mips/lasat
+        $(Q)$(MAKE) $(clean)=arch/mips/boot
+        $(Q)$(MAKE) $(clean)=arch/mips/boot/compressed
+        $(Q)$(MAKE) $(clean)=arch/mips/lasat
 
 define archhelp
         echo '  install              - install kernel into $(INSTALL_PATH)'
@@ -796,11 +318,3 @@ define archhelp
         echo
         echo '  These will be default as apropriate for a configured platform.'
 endef
-
-CLEAN_FILES += vmlinux.32 \
-               vmlinux.64 \
-               vmlinux.ecoff \
-               vmlinuz \
-               vmlinuz.ecoff \
-               vmlinuz.bin \
-               vmlinuz.srec
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index df3b1a7eb15d..2ccfd4a135bc 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -11,7 +11,7 @@ config ALCHEMY_GPIO_INDIRECT
 
 choice
         prompt "Machine type"
-        depends on MACH_ALCHEMY
+        depends on MIPS_ALCHEMY
         default MIPS_DB1000
 
 config MIPS_MTX1
@@ -128,41 +128,33 @@ config MIPS_XXS1500
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
+config MIPS_GPR
+        bool "Trapeze ITS GPR board"
+        select SOC_AU1550
+        select HW_HAS_PCI
+        select DMA_NONCOHERENT
+        select MIPS_DISABLE_OBSOLETE_IDE
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
+
 endchoice
 
 config SOC_AU1000
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1100
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1500
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1550
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1200
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1X00
-        bool
-        select 64BIT_PHYS_ADDR
-        select CEVT_R4K_LIB
-        select CSRC_R4K_LIB
-        select IRQ_CPU
-        select SYS_HAS_CPU_MIPS32_R1
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_APM_EMULATION
-        select GENERIC_GPIO
-        select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
new file mode 100644
index 000000000000..96e9e41f1b2a
--- /dev/null
+++ b/arch/mips/alchemy/Platform
@@ -0,0 +1,114 @@
+#
+# Core Alchemy code
+#
+platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
+
+
+#
+# AMD Alchemy Pb1000 eval board
+#
+platform-$(CONFIG_MIPS_PB1000)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1000)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1000)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1100 eval board
+#
+platform-$(CONFIG_MIPS_PB1100)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1100)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1100)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1500 eval board
+#
+platform-$(CONFIG_MIPS_PB1500)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1500)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1500)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1550 eval board
+#
+platform-$(CONFIG_MIPS_PB1550)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1550)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1550)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1200 eval board
+#
+platform-$(CONFIG_MIPS_PB1200)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1200)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1200)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1000 eval board
+#
+platform-$(CONFIG_MIPS_DB1000)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1000)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1000)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1100 eval board
+#
+platform-$(CONFIG_MIPS_DB1100)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1100)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1100)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1500 eval board
+#
+platform-$(CONFIG_MIPS_DB1500)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1500)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1500)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1550 eval board
+#
+platform-$(CONFIG_MIPS_DB1550)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1550)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1550)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1200 eval board
+#
+platform-$(CONFIG_MIPS_DB1200)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1200)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1200)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Bosporus eval board
+#
+platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_BOSPORUS)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_BOSPORUS)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Mirage eval board
+#
+platform-$(CONFIG_MIPS_MIRAGE)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_MIRAGE)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_MIRAGE)      += 0xffffffff80100000
+
+#
+# 4G-Systems eval board
+#
+platform-$(CONFIG_MIPS_MTX1)    += alchemy/mtx-1/
+load-$(CONFIG_MIPS_MTX1)        += 0xffffffff80100000
+
+#
+# MyCable eval board
+#
+platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/
+load-$(CONFIG_MIPS_XXS1500)     += 0xffffffff80100000
+
+#
+# Trapeze ITS GRP board
+#
+platform-$(CONFIG_MIPS_GPR)     += alchemy/gpr/
+load-$(CONFIG_MIPS_GPR)         += 0xffffffff80100000
+
+# boards can specify their own <gpio.h> in one of their include dirs.
+# If they do, placing this line here at the end will make sure the
+# compiler picks the board one.  If they don't, it will make sure
+# the alchemy generic gpio header is picked up.
+
+cflags-$(CONFIG_MIPS_ALCHEMY)   += -I$(srctree)/arch/mips/include/asm/mach-au1x00
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 06c0e65a54b5..27811fe341d6 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -18,5 +18,3 @@ ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
 endif
 
 obj-$(CONFIG_PCI)               += pci.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 460c6285c1bb..af0fe41055af 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -89,11 +89,7 @@ unsigned long au1xxx_calc_clock(void)
          * over backwards trying to determine the frequency.
          */
         if (au1xxx_cpu_has_pll_wo())
-#ifdef CONFIG_SOC_AU1000_FREQUENCY
-                cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
-#else
                 cpu_speed = 396000000;
-#endif
         else
                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
 
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index f9e5622ebc95..1dc55ee2681b 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/dma-mapping.h>
+#include <linux/etherdevice.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/init.h>
@@ -21,6 +22,8 @@
 #include <asm/mach-au1x00/au1100_mmc.h>
 #include <asm/mach-au1x00/au1xxx_eth.h>
 
+#include <prom.h>
+
 #define PORT(_base, _irq)                                       \
         {                                                       \
                 .mapbase        = _base,                        \
@@ -33,7 +36,6 @@
         }
 
 static struct plat_serial8250_port au1x00_uart_data[] = {
-#if defined(CONFIG_SERIAL_8250_AU1X00)
 #if defined(CONFIG_SOC_AU1000)
         PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
         PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
@@ -54,7 +56,6 @@ static struct plat_serial8250_port au1x00_uart_data[] = {
         PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
         PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
 #endif
-#endif  /* CONFIG_SERIAL_8250_AU1X00 */
         { },
 };
 
@@ -436,17 +437,27 @@ static int __init au1xxx_platform_init(void)
 {
         unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
         int err, i;
+        unsigned char ethaddr[6];
 
         /* Fill up uartclk. */
         for (i = 0; au1x00_uart_data[i].flags; i++)
                 au1x00_uart_data[i].uartclk = uartclk;
 
+        /* use firmware-provided mac addr if available and necessary */
+        i = prom_get_ethernet_addr(ethaddr);
+        if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
+                memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
+
         err = platform_add_devices(au1xxx_platform_devices,
                                    ARRAY_SIZE(au1xxx_platform_devices));
 #ifndef CONFIG_SOC_AU1100
+        ethaddr[5] += 1;        /* next addr for 2nd MAC */
+        if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
+                memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
+
         /* Register second MAC if enabled in pinfunc */
         if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
-                platform_device_register(&au1xxx_eth1_device);
+                err = platform_device_register(&au1xxx_eth1_device);
 #endif
 
         return err;
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index ecbd37f9ee87..826449c817c3 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -16,5 +16,3 @@ obj-$(CONFIG_MIPS_DB1500)	+= db1x00/
 obj-$(CONFIG_MIPS_DB1550)       += db1x00/
 obj-$(CONFIG_MIPS_BOSPORUS)     += db1x00/
 obj-$(CONFIG_MIPS_MIRAGE)       += db1x00/
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 3cb95a98ab31..3fa34c3abc04 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -216,14 +216,14 @@ static struct resource db1200_ide_res[] = {
         }
 };
 
-static u64 ide_dmamask = DMA_32BIT_MASK;
+static u64 ide_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device db1200_ide_dev = {
         .name           = "au1200-ide",
         .id             = 0,
         .dev = {
                 .dma_mask               = &ide_dmamask,
-                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(db1200_ide_res),
         .resource       = db1200_ide_res,
@@ -385,12 +385,12 @@ static struct au1550_spi_info db1200_spi_platdata = {
         .activate_cs    = db1200_spi_cs_en,
 };
 
-static u64 spi_dmamask = DMA_32BIT_MASK;
+static u64 spi_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device db1200_spi_dev = {
         .dev    = {
                 .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
                 .platform_data          = &db1200_spi_platdata,
         },
         .name           = "au1550-spi",
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 50c9bef99daa..9e45971343ed 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -79,7 +79,6 @@ static struct au1000_eth_platform_data eth0_pdata = {
 
 static void bosporus_power_off(void)
 {
-        printk(KERN_INFO "It's now safe to turn off power\n");
         while (1)
                 asm volatile (".set mips3 ; wait ; .set mips0");
 }
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index 4ef50d86b181..f6540ec47a64 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -47,9 +47,11 @@ static void board_reset(char *c)
 
 static void board_power_off(void)
 {
-        printk(KERN_ALERT "It's now safe to remove power\n");
         while (1)
-                asm volatile (".set mips3 ; wait ; .set mips1");
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
index 2ea9b02ef09f..18c1bd53e4c0 100644
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y := board_setup.o platform.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
new file mode 100644
index 000000000000..cb73fe256dce
--- /dev/null
+++ b/arch/mips/alchemy/gpr/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2003 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for Trapeze ITS GPR board.
+#
+
+obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
new file mode 100644
index 000000000000..ad2e3f137933
--- /dev/null
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2000-2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+#define UART1_ADDR      KSEG1ADDR(UART1_PHYS_ADDR)
+#define UART3_ADDR      KSEG1ADDR(UART3_PHYS_ADDR)
+
+char irq_tab_alchemy[][5] __initdata = {
+        [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
+};
+
+static void gpr_reset(char *c)
+{
+        /* switch System-LED to orange (red# and green# on) */
+        alchemy_gpio_direction_output(4, 0);
+        alchemy_gpio_direction_output(5, 0);
+
+        /* trigger watchdog to reset board in 200ms */
+        printk(KERN_EMERG "Triggering watchdog soft reset...\n");
+        raw_local_irq_disable();
+        alchemy_gpio_direction_output(1, 0);
+        udelay(1);
+        alchemy_gpio_set_value(1, 1);
+        while (1)
+                cpu_wait();
+}
+
+static void gpr_power_off(void)
+{
+        while (1)
+                cpu_wait();
+}
+
+void __init board_setup(void)
+{
+        printk(KERN_INFO "Tarpeze ITS GPR board\n");
+
+        pm_power_off = gpr_power_off;
+        _machine_halt = gpr_power_off;
+        _machine_restart = gpr_reset;
+
+        /* Enable UART3 */
+        au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */
+        au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
+        /* Enable UART1 */
+        au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
+        au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
+
+        /* Take away Reset of UMTS-card */
+        alchemy_gpio_direction_output(215, 1);
+
+#ifdef CONFIG_PCI
+#if defined(__MIPSEB__)
+        au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
+#else
+        au_writel(0xf, Au1500_PCI_CFG);
+#endif
+#endif
+}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
new file mode 100644
index 000000000000..f044f4c541d7
--- /dev/null
+++ b/arch/mips/alchemy/gpr/init.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "GPR";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str)
+                memsize = 0x04000000;
+        else
+                strict_strtoul(memsize_str, 0, &memsize);
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
new file mode 100644
index 000000000000..14b46629cfc8
--- /dev/null
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -0,0 +1,183 @@
+/*
+ * GPR board platform device registration
+ *
+ * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+/*
+ * Watchdog
+ */
+static struct resource gpr_wdt_resource[] = {
+        [0] = {
+                .start  = 1,
+                .end    = 1,
+                .name   = "gpr-adm6320-wdt",
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device gpr_wdt_device = {
+        .name = "adm6320-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(gpr_wdt_resource),
+        .resource = gpr_wdt_resource,
+};
+
+/*
+ * FLASH
+ *
+ * 0x00000000-0x00200000 : "kernel"
+ * 0x00200000-0x00a00000 : "rootfs"
+ * 0x01d00000-0x01f00000 : "config"
+ * 0x01c00000-0x01d00000 : "yamon"
+ * 0x01d00000-0x01d40000 : "yamon env vars"
+ * 0x00000000-0x00a00000 : "kernel+rootfs"
+ */
+static struct mtd_partition gpr_mtd_partitions[] = {
+        {
+                .name   = "kernel",
+                .size   = 0x00200000,
+                .offset = 0,
+        },
+        {
+                .name   = "rootfs",
+                .size   = 0x00800000,
+                .offset = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        {
+                .name   = "config",
+                .size   = 0x00200000,
+                .offset = 0x01d00000,
+        },
+        {
+                .name   = "yamon",
+                .size   = 0x00100000,
+                .offset = 0x01c00000,
+        },
+        {
+                .name   = "yamon env vars",
+                .size   = 0x00040000,
+                .offset = MTDPART_OFS_APPEND,
+        },
+        {
+                .name   = "kernel+rootfs",
+                .size   = 0x00a00000,
+                .offset = 0,
+        },
+};
+
+static struct physmap_flash_data gpr_flash_data = {
+        .width          = 4,
+        .nr_parts       = ARRAY_SIZE(gpr_mtd_partitions),
+        .parts          = gpr_mtd_partitions,
+};
+
+static struct resource gpr_mtd_resource = {
+        .start  = 0x1e000000,
+        .end    = 0x1fffffff,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device gpr_mtd_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &gpr_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &gpr_mtd_resource,
+};
+
+/*
+ * LEDs
+ */
+static struct gpio_led gpr_gpio_leds[] = {
+        {       /* green */
+                .name                   = "gpr:green",
+                .gpio                   = 4,
+                .active_low             = 1,
+        },
+        {       /* red */
+                .name                   = "gpr:red",
+                .gpio                   = 5,
+                .active_low             = 1,
+        }
+};
+
+static struct gpio_led_platform_data gpr_led_data = {
+        .num_leds = ARRAY_SIZE(gpr_gpio_leds),
+        .leds = gpr_gpio_leds,
+};
+
+static struct platform_device gpr_led_devices = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &gpr_led_data,
+        }
+};
+
+/*
+ * I2C
+ */
+static struct i2c_gpio_platform_data gpr_i2c_data = {
+        .sda_pin                = 209,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = 210,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+        .timeout                = HZ,
+ };
+
+static struct platform_device gpr_i2c_device = {
+        .name                   = "i2c-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &gpr_i2c_data,
+};
+
+static struct i2c_board_info gpr_i2c_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("lm83", 0x18),
+                .type = "lm83"
+        }
+};
+
+static struct platform_device *gpr_devices[] __initdata = {
+        &gpr_wdt_device,
+        &gpr_mtd_device,
+        &gpr_i2c_device,
+        &gpr_led_devices,
+};
+
+static int __init gpr_dev_init(void)
+{
+        i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
+
+        return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
+}
+device_initcall(gpr_dev_init);
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
index 4a53815b3c6c..81b540ceaf88 100644
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ b/arch/mips/alchemy/mtx-1/Makefile
@@ -6,7 +6,4 @@
 # Makefile for 4G Systems MTX-1 board.
 #
 
-lib-y := init.o board_setup.o
-obj-y := platform.o
-
-EXTRA_CFLAGS += -Werror
+obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 52d883d37dd7..6398fa95905c 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -60,9 +60,11 @@ static void mtx1_reset(char *c)
 
 static void mtx1_power_off(void)
 {
-        printk(KERN_ALERT "It's now safe to remove power\n");
         while (1)
-                asm volatile (".set mips3 ; wait ; .set mips1");
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
@@ -105,14 +107,10 @@ void __init board_setup(void)
 int
 mtx1_pci_idsel(unsigned int devsel, int assert)
 {
-#define MTX_IDSEL_ONLY_0_AND_3 0
-#if MTX_IDSEL_ONLY_0_AND_3
-        if (devsel != 0 && devsel != 3) {
-                printk(KERN_ERR "*** not 0 or 3\n");
-                return 0;
-        }
-#endif
-
+        /* This function is only necessary to support a proprietary Cardbus
+         * adapter on the mtx-1 "singleboard" variant. It triggers a custom
+         * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
+         */
         if (assert && devsel != 0)
                 /* Suppress signal to Cardbus */
                 alchemy_gpio_set_value(1, 0);   /* set EXT_IO3 OFF */
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
index 4dc81d794cb8..91defcf4f335 100644
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ b/arch/mips/alchemy/xxs1500/Makefile
@@ -5,6 +5,4 @@
 # Makefile for MyCable XXS1500 board.
 #
 
-lib-y := init.o board_setup.o platform.o
-
-EXTRA_CFLAGS += -Werror
+obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 47b42927607b..b43c918925d3 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -42,9 +42,11 @@ static void xxs1500_reset(char *c)
 
 static void xxs1500_power_off(void)
 {
-        printk(KERN_ALERT "It's now safe to remove power\n");
         while (1)
-                asm volatile (".set mips3 ; wait ; .set mips1");
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
diff --git a/arch/mips/ar7/Makefile b/arch/mips/ar7/Makefile
index 26bc5da18997..7435e44b3964 100644
--- a/arch/mips/ar7/Makefile
+++ b/arch/mips/ar7/Makefile
@@ -8,4 +8,3 @@ obj-y := \
         platform.o \
         gpio.o \
         clock.o
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ar7/Platform b/arch/mips/ar7/Platform
new file mode 100644
index 000000000000..0bf85c416c6c
--- /dev/null
+++ b/arch/mips/ar7/Platform
@@ -0,0 +1,6 @@
+#
+# Texas Instruments AR7
+#
+platform-$(CONFIG_AR7)          += ar7/
+cflags-$(CONFIG_AR7)            += -I$(srctree)/arch/mips/include/asm/mach-ar7
+load-$(CONFIG_AR7)              += 0xffffffff94100000
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 8f31d1d59683..0da5b2b8dd88 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -292,40 +292,28 @@ static struct platform_device cpmac_high = {
         .num_resources  = ARRAY_SIZE(cpmac_high_res),
 };
 
-static inline unsigned char char2hex(char h)
+static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
 {
-        switch (h) {
-        case '0': case '1': case '2': case '3': case '4':
-        case '5': case '6': case '7': case '8': case '9':
-                return h - '0';
-        case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
-                return h - 'A' + 10;
-        case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
-                return h - 'a' + 10;
-        default:
-                return 0;
-        }
-}
-
-static void cpmac_get_mac(int instance, unsigned char *dev_addr)
-{
-        int i;
-        char name[5], default_mac[ETH_ALEN], *mac;
+        char name[5], *mac;
 
-        mac = NULL;
         sprintf(name, "mac%c", 'a' + instance);
         mac = prom_getenv(name);
-        if (!mac) {
+        if (!mac && instance) {
                 sprintf(name, "mac%c", 'a');
                 mac = prom_getenv(name);
         }
-        if (!mac) {
-                random_ether_addr(default_mac);
-                mac = default_mac;
-        }
-        for (i = 0; i < 6; i++)
-                dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
-                        char2hex(mac[i * 3 + 1]);
+
+        if (mac) {
+                if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
+                                        &dev_addr[0], &dev_addr[1],
+                                        &dev_addr[2], &dev_addr[3],
+                                        &dev_addr[4], &dev_addr[5]) != 6) {
+                        pr_warning("cannot parse mac address, "
+                                        "using random address\n");
+                        random_ether_addr(dev_addr);
+                }
+        } else
+                random_ether_addr(dev_addr);
 }
 
 /*****************************************************************************
diff --git a/arch/mips/bcm47xx/Platform b/arch/mips/bcm47xx/Platform
new file mode 100644
index 000000000000..874b7ca4cd11
--- /dev/null
+++ b/arch/mips/bcm47xx/Platform
@@ -0,0 +1,7 @@
+#
+# Broadcom BCM47XX boards
+#
+platform-$(CONFIG_BCM47XX)      += bcm47xx/
+cflags-$(CONFIG_BCM47XX)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
+load-$(CONFIG_BCM47XX)          := 0xffffffff80001000
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index 06e03b222f6d..e5b6615731e5 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -69,7 +69,7 @@ int nvram_getenv(char *name, char *val, size_t val_len)
         char *var, *value, *end, *eq;
 
         if (!name)
-                return 1;
+                return NVRAM_ERR_INV_PARAM;
 
         if (!nvram_buf[0])
                 early_nvram_init();
@@ -89,6 +89,6 @@ int nvram_getenv(char *name, char *val, size_t val_len)
                         return 0;
                 }
         }
-        return 1;
+        return NVRAM_ERR_ENVNOTFOUND;
 }
 EXPORT_SYMBOL(nvram_getenv);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 0fa646c5a844..f6e9063cc4c2 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -126,6 +126,7 @@ static __init void prom_init_cmdline(void)
 static __init void prom_init_mem(void)
 {
         unsigned long mem;
+        unsigned long max;
 
         /* Figure out memory size by finding aliases.
          *
@@ -134,21 +135,26 @@ static __init void prom_init_mem(void)
          * want to reuse the memory used by CFE (around 4MB). That means cfe_*
          * functions stop to work at some point during the boot, we should only
          * call them at the beginning of the boot.
+         *
+         * BCM47XX uses 128MB for addressing the ram, if the system contains
+         * less that that amount of ram it remaps the ram more often into the
+         * available space.
+         * Accessing memory after 128MB will cause an exception.
+         * max contains the biggest possible address supported by the platform.
+         * If the method wants to try something above we assume 128MB ram.
          */
+        max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
         for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
+                if (((unsigned long)(prom_init) + mem) > max) {
+                        mem = (128 << 20);
+                        printk(KERN_DEBUG "assume 128MB RAM\n");
+                        break;
+                }
                 if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
                     *(unsigned long *)(prom_init))
                         break;
         }
 
-        /* Ignoring the last page when ddr size is 128M. Cached
-         * accesses to last page is causing the processor to prefetch
-         * using address above 128M stepping out of the ddr address
-         * space.
-         */
-        if (mem == 0x8000000)
-                mem -= 0x1000;
-
         add_memory_region(0, mem, BOOT_MEM_RAM);
 }
 
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 00064b660809..6dfdc69928ac 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -3,5 +3,3 @@ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-y           += boards/
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/Platform b/arch/mips/bcm63xx/Platform
new file mode 100644
index 000000000000..5f86b2fff6de
--- /dev/null
+++ b/arch/mips/bcm63xx/Platform
@@ -0,0 +1,7 @@
+#
+# Broadcom BCM63XX boards
+#
+platform-$(CONFIG_BCM63XX)      += bcm63xx/
+cflags-$(CONFIG_BCM63XX)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
+load-$(CONFIG_BCM63XX)          := 0xffffffff80010000
diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore
index 4667a5f9280b..f210b09ececc 100644
--- a/arch/mips/boot/.gitignore
+++ b/arch/mips/boot/.gitignore
@@ -3,3 +3,4 @@ elf2ecoff
 vmlinux.*
 zImage
 zImage.tmp
+calc_vmlinuz_load_addr
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index e39a08edcaaa..85bcb5adc7cb 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -11,35 +11,32 @@
 # Some DECstations need all possible sections of an ECOFF executable
 #
 ifdef CONFIG_MACH_DECSTATION
-  E2EFLAGS = -a
-else
-  E2EFLAGS =
+  e2eflag := -a
 endif
 
 #
 # Drop some uninteresting sections in the kernel.
 # This is only relevant for ELF kernels but doesn't hurt a.out
 #
-drop-sections   = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
-strip-flags     = $(addprefix --remove-section=,$(drop-sections))
-
-VMLINUX = vmlinux
-
-all: vmlinux.ecoff vmlinux.srec
-
-vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
-        $(obj)/elf2ecoff $(VMLINUX) $(obj)/vmlinux.ecoff $(E2EFLAGS)
-
-$(obj)/elf2ecoff: $(obj)/elf2ecoff.c
-        $(HOSTCC) -o $@ $^
-
-vmlinux.bin: $(VMLINUX)
-        $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $(obj)/vmlinux.bin
-
-vmlinux.srec: $(VMLINUX)
-        $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
-
-clean-files += elf2ecoff \
-               vmlinux.bin \
-               vmlinux.ecoff \
-               vmlinux.srec
+drop-sections := .reginfo .mdebug .comment .note .pdr .options .MIPS.options
+strip-flags   := $(addprefix --remove-section=,$(drop-sections))
+
+hostprogs-y := elf2ecoff
+
+targets := vmlinux.ecoff
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
+$(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
+        $(call if_changed,ecoff)
+
+targets += vmlinux.bin
+quiet_cmd_bin = OBJCOPY $@
+      cmd_bin = $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.bin: $(VMLINUX) FORCE
+        $(call if_changed,bin)
+
+targets += vmlinux.srec
+quiet_cmd_srec = OBJCOPY $@
+      cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.srec: $(VMLINUX) FORCE
+        $(call if_changed,srec)
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 790ddd397620..ed9bb709c9a3 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -12,14 +12,6 @@
 # Author: Wu Zhangjin <wuzhangjin@gmail.com>
 #
 
-# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
-VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
-VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo -n $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
-# VMLINUZ_LOAD_ADDRESS = concat "high32 of VMLINUX_LOAD_ADDRESS" and "(low32 of VMLINUX_LOAD_ADDRESS) + VMLINUX_SIZE"
-HIGH32 := $(shell A=$(VMLINUX_LOAD_ADDRESS); [ $${\#A} -gt 10 ] && expr substr "$(VMLINUX_LOAD_ADDRESS)" 3 $$(($${\#A} - 10)))
-LOW32 := $(shell [ -n "$(HIGH32)" ] && A=11 || A=3; expr substr "$(VMLINUX_LOAD_ADDRESS)" $${A} 8)
-VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" -a -n "$(LOW32)" ] && printf "$(HIGH32)%08x" $$(($(VMLINUX_SIZE) + 0x$(LOW32))))
-
 # set the default size of the mallocing area for decompressing
 BOOT_HEAP_SIZE := 0x400000
 
@@ -33,49 +25,61 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
         -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
         -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
 
-obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
+targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
+
+# decompressor objects (linked with vmlinuz)
+vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
 
 ifdef CONFIG_DEBUG_ZBOOT
-obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
-obj-$(CONFIG_MACH_ALCHEMY)                 += $(obj)/uart-alchemy.o
+vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY)                 += $(obj)/uart-alchemy.o
 endif
 
+targets += vmlinux.bin
 OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
-$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
+$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
         $(call if_changed,objcopy)
 
-suffix_$(CONFIG_KERNEL_GZIP)  = gz
-suffix_$(CONFIG_KERNEL_BZIP2) = bz2
-suffix_$(CONFIG_KERNEL_LZMA)  = lzma
-suffix_$(CONFIG_KERNEL_LZO)   = lzo
 tool_$(CONFIG_KERNEL_GZIP)    = gzip
 tool_$(CONFIG_KERNEL_BZIP2)   = bzip2
 tool_$(CONFIG_KERNEL_LZMA)    = lzma
 tool_$(CONFIG_KERNEL_LZO)     = lzo
-$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
+
+targets += vmlinux.bin.z
+$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
         $(call if_changed,$(tool_y))
 
-$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
-        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
-                --add-section=.image=$< \
-                --set-section-flags=.image=contents,alloc,load,readonly,data \
-                $(obj)/dummy.o $@
+targets += piggy.o
+OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
+                        --set-section-flags=.image=contents,alloc,load,readonly,data
+$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
+        $(call if_changed,objcopy)
+
+# Calculate the load address of the compressed kernel image
+hostprogs-y := calc_vmlinuz_load_addr
+
+VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
+                $(objtree)/$(KBUILD_IMAGE) $(VMLINUX_LOAD_ADDRESS))
 
-LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
-vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
-        $(call if_changed,ld)
-        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) $@
+vmlinuzobjs-y += $(obj)/piggy.o
+
+quiet_cmd_zld = LD      $@
+      cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
+quiet_cmd_strip = STRIP   $@
+      cmd_strip = $(STRIP) -s $@
+vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
+        $(call cmd,zld)
+        $(call cmd,strip)
 
 #
 # Some DECstations need all possible sections of an ECOFF executable
 #
 ifdef CONFIG_MACH_DECSTATION
-  E2EFLAGS = -a
-else
-  E2EFLAGS =
+  e2eflag := -a
 endif
 
 # elf2ecoff can only handle 32bit image
+hostprogs-y += ../elf2ecoff
 
 ifdef CONFIG_32BIT
         VMLINUZ = vmlinuz
@@ -83,23 +87,22 @@ else
         VMLINUZ = vmlinuz.32
 endif
 
+quiet_cmd_32 = OBJCOPY $@
+      cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 vmlinuz.32: vmlinuz
-        $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
+        $(call cmd,32)
 
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
 vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
-        $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
-
-$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
-        $(Q)$(HOSTCC) -o $@ $^
+        $(call cmd,ecoff)
 
 OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
 vmlinuz.bin: vmlinuz
-        $(call if_changed,objcopy)
+        $(call cmd,objcopy)
 
 OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
 vmlinuz.srec: vmlinuz
-        $(call if_changed,objcopy)
+        $(call cmd,objcopy)
 
-clean:
-clean-files += *.o \
-               vmlinu*
+clean-files := $(objtree)/vmlinuz.*
diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
new file mode 100644
index 000000000000..88c9d963be88
--- /dev/null
+++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char *argv[])
+{
+        struct stat sb;
+        uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
+
+        if (argc != 3) {
+                fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
+                                argv[0]);
+                return EXIT_FAILURE;
+        }
+
+        if (stat(argv[1], &sb) == -1) {
+                perror("stat");
+                return EXIT_FAILURE;
+        }
+
+        /* Convert hex characters to dec number */
+        errno = 0;
+        if (sscanf(argv[2], "%llx", &vmlinux_load_addr) != 1) {
+                if (errno != 0)
+                        perror("sscanf");
+                else
+                        fprintf(stderr, "No matching characters\n");
+
+                return EXIT_FAILURE;
+        }
+
+        vmlinux_size = (uint64_t)sb.st_size;
+        vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
+
+        /*
+         * Align with 16 bytes: "greater than that used for any standard data
+         * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition).
+         */
+
+        vmlinuz_load_addr += (16 - vmlinux_size % 16);
+
+        printf("0x%llx\n", vmlinuz_load_addr);
+
+        return EXIT_SUCCESS;
+}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index 5db43c58b1bf..5cad0faefa17 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -1,9 +1,6 @@
 /*
- * Misc. bootloader code for many machines.
- *
  * Copyright 2001 MontaVista Software Inc.
- * Author: Matt Porter <mporter@mvista.com> Derived from
- * arch/ppc/boot/prep/misc.c
+ * Author: Matt Porter <mporter@mvista.com>
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
@@ -19,12 +16,12 @@
 
 #include <asm/addrspace.h>
 
-/* These two variables specify the free mem region
+/*
+ * These two variables specify the free mem region
  * that can be used for temporary malloc area
  */
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
-char *zimage_start;
 
 /* The linker tells us where the image is. */
 extern unsigned char __image_begin, __image_end;
@@ -83,38 +80,31 @@ void *memset(void *s, int c, size_t n)
 
 void decompress_kernel(unsigned long boot_heap_start)
 {
-        int zimage_size;
-
-        /*
-         * We link ourself to an arbitrary low address.  When we run, we
-         * relocate outself to that address.  __image_beign points to
-         * the part of the image where the zImage is. -- Tom
-         */
-        zimage_start = (char *)(unsigned long)(&__image_begin);
+        unsigned long zimage_start, zimage_size;
+
+        zimage_start = (unsigned long)(&__image_begin);
         zimage_size = (unsigned long)(&__image_end) -
             (unsigned long)(&__image_begin);
 
-        /*
-         * The zImage and initrd will be between start and _end, so they've
-         * already been moved once.  We're good to go now. -- Tom
-         */
         puts("zimage at:     ");
-        puthex((unsigned long)zimage_start);
+        puthex(zimage_start);
         puts(" ");
-        puthex((unsigned long)(zimage_size + zimage_start));
+        puthex(zimage_size + zimage_start);
         puts("\n");
 
-        /* this area are prepared for mallocing when decompressing */
+        /* This area are prepared for mallocing when decompressing */
         free_mem_ptr = boot_heap_start;
         free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
 
-        /* Display standard Linux/MIPS boot prompt for kernel args */
+        /* Display standard Linux/MIPS boot prompt */
         puts("Uncompressing Linux at load address ");
         puthex(VMLINUX_LOAD_ADDRESS_ULL);
         puts("\n");
+
         /* Decompress the kernel with according algorithm */
-        decompress(zimage_start, zimage_size, 0, 0,
+        decompress((char *)zimage_start, zimage_size, 0, 0,
                    (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
-        /* FIXME: is there a need to flush cache here? */
+
+        /* FIXME: should we flush cache here? */
         puts("Now, booting the kernel...\n");
 }
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
index 613a35b02f50..8e6b07ca2f5e 100644
--- a/arch/mips/boot/compressed/ld.script
+++ b/arch/mips/boot/compressed/ld.script
@@ -2,61 +2,44 @@
  * ld.script for compressed kernel support of MIPS
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhanjing@gmail.com>
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhanjing@gmail.com>
  */
 
 OUTPUT_ARCH(mips)
 ENTRY(start)
 SECTIONS
 {
-        /* . = VMLINUZ_LOAD_ADDRESS */
-        /* read-only */
-        _text = .;      /* Text and read-only data */
-        .text   : {
-                _ftext = . ;
+        /* Text and read-only data */
+        /* . = VMLINUZ_LOAD_ADDRESS; */
+        .text : {
                 *(.text)
                 *(.rodata)
-        } = 0
-        _etext = .;     /* End of text section */
+        }
+        /* End of text section */
 
-        /* writable */
-        .data   : {     /* Data */
-                _fdata = . ;
+        /* Writable data */
+        .data : {
                 *(.data)
-                /* Put the compressed image here, so bss is on the end. */
+                /* Put the compressed image here */
                 __image_begin = .;
                 *(.image)
                 __image_end = .;
                 CONSTRUCTORS
         }
-        .sdata  : { *(.sdata) }
-        . = ALIGN(4);
-        _edata  =  .;   /* End of data section */
+        . = ALIGN(16);
+        _edata = .;
+        /* End of data section */
 
         /* BSS */
-        __bss_start = .;
-        _fbss = .;
-        .sbss   : { *(.sbss) *(.scommon) }
-        .bss    : {
-                *(.dynbss)
+        .bss : {
                 *(.bss)
-                *(COMMON)
         }
-        .  = ALIGN(4);
-        _end = . ;
-
-        /* These are needed for ELF backends which have not yet been converted
-         * to the new style linker.  */
-
-        .stab 0 : { *(.stab) }
-        .stabstr 0 : { *(.stabstr) }
-
-        /* These must appear regardless of  .  */
-        .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
-        .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+        . = ALIGN(16);
+        _end = .;
 
         /* Sections to be discarded */
-        /DISCARD/       : {
+        /DISCARD/ : {
                 *(.MIPS.options)
                 *(.options)
                 *(.pdr)
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 3e9876317e61..19eb0434269f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,6 @@
 obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
+obj-y += executive/
 
 obj-$(CONFIG_SMP)                     += smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
new file mode 100644
index 000000000000..1e43ccf1a792
--- /dev/null
+++ b/arch/mips/cavium-octeon/Platform
@@ -0,0 +1,11 @@
+#
+# Cavium Octeon
+#
+platform-$(CONFIG_CPU_CAVIUM_OCTEON)    += cavium-octeon/
+cflags-$(CONFIG_CPU_CAVIUM_OCTEON)      +=                              \
+                -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
+ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff84100000
+else
+load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff81100000
+endif
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
index b6df5387e855..c664c8cc2b42 100644
--- a/arch/mips/cavium-octeon/cpu.c
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -41,12 +41,8 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
         return NOTIFY_OK;               /* Let default notifier send signals */
 }
 
-static struct notifier_block cnmips_cu2_notifier = {
-        .notifier_call = cnmips_cu2_call,
-};
-
 static int cnmips_cu2_setup(void)
 {
-        return register_cu2_notifier(&cnmips_cu2_notifier);
+        return cu2_notifier(cnmips_cu2_call, 0);
 }
 early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 0bf4bbe04ae2..b6847c8e0ddd 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
 unsigned long long notrace sched_clock(void)
 {
         /* 64-bit arithmatic can overflow, so use 128-bit.  */
-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
         u64 t1, t2, t3;
         unsigned long long rv;
         u64 mult = clocksource_mips.mult;
@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
                 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
                 : "hi", "lo");
         return rv;
-#else
-        /* GCC > 4.3 do it the easy way.  */
-        unsigned int __attribute__((mode(TI))) t;
-        t = read_c0_cvmcount();
-        t = t * clocksource_mips.mult;
-        return (unsigned long long)(t >> clocksource_mips.shift);
-#endif
 }
 
 void __init plat_time_init(void)
@@ -88,3 +80,58 @@ void __init plat_time_init(void)
         clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
         clocksource_register(&clocksource_mips);
 }
+
+static u64 octeon_udelay_factor;
+static u64 octeon_ndelay_factor;
+
+void __init octeon_setup_delays(void)
+{
+        octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
+        /*
+         * For __ndelay we divide by 2^16, so the factor is multiplied
+         * by the same amount.
+         */
+        octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
+
+        preset_lpj = octeon_get_clock_rate() / HZ;
+}
+
+void __udelay(unsigned long us)
+{
+        u64 cur, end, inc;
+
+        cur = read_c0_cvmcount();
+
+        inc = us * octeon_udelay_factor;
+        end = cur + inc;
+
+        while (end > cur)
+                cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__udelay);
+
+void __ndelay(unsigned long ns)
+{
+        u64 cur, end, inc;
+
+        cur = read_c0_cvmcount();
+
+        inc = ((ns * octeon_ndelay_factor) >> 16);
+        end = cur + inc;
+
+        while (end > cur)
+                cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__ndelay);
+
+void __delay(unsigned long loops)
+{
+        u64 cur, end;
+
+        cur = read_c0_cvmcount();
+        end = cur + loops;
+
+        while (end > cur)
+                cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__delay);
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index be531ec1f206..d22b5a2d64f4 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -99,13 +99,16 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
                         panic("dma_map_single: "
                               "Attempt to map illegal memory address 0x%llx\n",
                               physical);
-                else if ((physical + size >=
-                          (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
-                         && physical < (4ull<<30))
-                        pr_warning("dma_map_single: Warning: "
-                                   "Mapping memory address that might "
-                                   "conflict with devices 0x%llx-0x%llx\n",
-                                   physical, physical+size-1);
+                else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
+                         physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
+                        result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+
+                        if (((result+size-1) & dma_mask) != result+size-1)
+                                panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
+                                      physical, physical+size-1, dma_mask);
+                        goto done;
+                }
+
                 /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
                 if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
                         result = physical - 0x400000000ull;
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index c424cd158dc6..ce7500cdf5b7 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,15 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  */
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
 #include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-pexp-defs.h>
-#include <asm/octeon/cvmx-npi-defs.h>
 
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
@@ -41,14 +39,14 @@ static void octeon_irq_core_ack(unsigned int irq)
 
 static void octeon_irq_core_eoi(unsigned int irq)
 {
-        struct irq_desc *desc = irq_desc + irq;
+        struct irq_desc *desc = irq_to_desc(irq);
         unsigned int bit = irq - OCTEON_IRQ_SW0;
         /*
          * If an IRQ is being processed while we are disabling it the
          * handler will attempt to unmask the interrupt after it has
          * been disabled.
          */
-        if (desc->status & IRQ_DISABLED)
+        if ((unlikely(desc->status & IRQ_DISABLED)))
                 return;
         /*
          * We don't need to disable IRQs to make these atomic since
@@ -106,6 +104,29 @@ static struct irq_chip octeon_irq_chip_core = {
 
 static void octeon_irq_ciu0_ack(unsigned int irq)
 {
+        switch (irq) {
+        case OCTEON_IRQ_GMX_DRP0:
+        case OCTEON_IRQ_GMX_DRP1:
+        case OCTEON_IRQ_IPD_DRP:
+        case OCTEON_IRQ_KEY_ZERO:
+        case OCTEON_IRQ_TIMER0:
+        case OCTEON_IRQ_TIMER1:
+        case OCTEON_IRQ_TIMER2:
+        case OCTEON_IRQ_TIMER3:
+        {
+                int index = cvmx_get_core_num() * 2;
+                u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+                /*
+                 * CIU timer type interrupts must be acknoleged by
+                 * writing a '1' bit to their sum0 bit.
+                 */
+                cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+                break;
+        }
+        default:
+                break;
+        }
+
         /*
          * In order to avoid any locking accessing the CIU, we
          * acknowledge CIU interrupts by disabling all of them.  This
@@ -130,8 +151,54 @@ static void octeon_irq_ciu0_eoi(unsigned int irq)
         set_c0_status(0x100 << 2);
 }
 
+static int next_coreid_for_irq(struct irq_desc *desc)
+{
+
+#ifdef CONFIG_SMP
+        int coreid;
+        int weight = cpumask_weight(desc->affinity);
+
+        if (weight > 1) {
+                int cpu = smp_processor_id();
+                for (;;) {
+                        cpu = cpumask_next(cpu, desc->affinity);
+                        if (cpu >= nr_cpu_ids) {
+                                cpu = -1;
+                                continue;
+                        } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
+                                break;
+                        }
+                }
+                coreid = octeon_coreid_for_cpu(cpu);
+        } else if (weight == 1) {
+                coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
+        } else {
+                coreid = cvmx_get_core_num();
+        }
+        return coreid;
+#else
+        return cvmx_get_core_num();
+#endif
+}
+
 static void octeon_irq_ciu0_enable(unsigned int irq)
 {
+        struct irq_desc *desc = irq_to_desc(irq);
+        int coreid = next_coreid_for_irq(desc);
+        unsigned long flags;
+        uint64_t en0;
+        int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
+
+        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+        en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+        en0 |= 1ull << bit;
+        cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+        cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+}
+
+static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
+{
         int coreid = cvmx_get_core_num();
         unsigned long flags;
         uint64_t en0;
@@ -167,63 +234,76 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
 }
 
 /*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the next core in the affinity set for chips that
+ * have the EN*_W1{S,C} registers.
  */
 static void octeon_irq_ciu0_enable_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2;
+        int index;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+        struct irq_desc *desc = irq_to_desc(irq);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        if ((desc->status & IRQ_DISABLED) == 0) {
+                index = next_coreid_for_irq(desc) * 2;
+                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        }
 }
 
 /*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the current CPU for chips that
+ * have the EN*_W1{S,C} registers.
  */
-static void octeon_irq_ciu0_ack_v2(unsigned int irq)
+static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2;
+        int index;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+        index = cvmx_get_core_num() * 2;
+        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
 }
 
 /*
- * CIU timer type interrupts must be acknoleged by writing a '1' bit
- * to their sum0 bit.
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
  */
-static void octeon_irq_ciu0_timer_ack(unsigned int irq)
+static void octeon_irq_ciu0_ack_v2(unsigned int irq)
 {
         int index = cvmx_get_core_num() * 2;
-        uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-        cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
-}
+        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq)
-{
-        octeon_irq_ciu0_timer_ack(irq);
-        octeon_irq_ciu0_ack(irq);
-}
+        switch (irq) {
+        case OCTEON_IRQ_GMX_DRP0:
+        case OCTEON_IRQ_GMX_DRP1:
+        case OCTEON_IRQ_IPD_DRP:
+        case OCTEON_IRQ_KEY_ZERO:
+        case OCTEON_IRQ_TIMER0:
+        case OCTEON_IRQ_TIMER1:
+        case OCTEON_IRQ_TIMER2:
+        case OCTEON_IRQ_TIMER3:
+                /*
+                 * CIU timer type interrupts must be acknoleged by
+                 * writing a '1' bit to their sum0 bit.
+                 */
+                cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+                break;
+        default:
+                break;
+        }
 
-static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq)
-{
-        octeon_irq_ciu0_timer_ack(irq);
-        octeon_irq_ciu0_ack_v2(irq);
+        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
 }
 
 /*
  * Enable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu0_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
 {
-        struct irq_desc *desc = irq_desc + irq;
+        struct irq_desc *desc = irq_to_desc(irq);
         int index = cvmx_get_core_num() * 2;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-        if ((desc->status & IRQ_DISABLED) == 0)
+        if (likely((desc->status & IRQ_DISABLED) == 0))
                 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
 }
 
@@ -246,18 +326,30 @@ static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
 static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
 {
         int cpu;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         unsigned long flags;
         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
 
+        /*
+         * For non-v2 CIU, we will allow only single CPU affinity.
+         * This removes the need to do locking in the .ack/.eoi
+         * functions.
+         */
+        if (cpumask_weight(dest) != 1)
+                return -EINVAL;
+
         raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 uint64_t en0 =
                         cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-                if (cpumask_test_cpu(cpu, dest))
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         en0 |= 1ull << bit;
-                else
+                } else {
                         en0 &= ~(1ull << bit);
+                }
                 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
         }
         /*
@@ -279,13 +371,18 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
 {
         int cpu;
         int index;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+
         for_each_online_cpu(cpu) {
                 index = octeon_coreid_for_cpu(cpu) * 2;
-                if (cpumask_test_cpu(cpu, dest))
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
-                else
+                } else {
                         cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+                }
         }
         return 0;
 }
@@ -298,8 +395,7 @@ static struct irq_chip octeon_irq_chip_ciu0_v2 = {
         .name = "CIU0",
         .enable = octeon_irq_ciu0_enable_v2,
         .disable = octeon_irq_ciu0_disable_all_v2,
-        .ack = octeon_irq_ciu0_ack_v2,
-        .eoi = octeon_irq_ciu0_eoi_v2,
+        .eoi = octeon_irq_ciu0_enable_v2,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu0_set_affinity_v2,
 #endif
@@ -309,36 +405,27 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
         .name = "CIU0",
         .enable = octeon_irq_ciu0_enable,
         .disable = octeon_irq_ciu0_disable,
-        .ack = octeon_irq_ciu0_ack,
         .eoi = octeon_irq_ciu0_eoi,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu0_set_affinity,
 #endif
 };
 
-static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = {
-        .name = "CIU0-T",
-        .enable = octeon_irq_ciu0_enable_v2,
-        .disable = octeon_irq_ciu0_disable_all_v2,
-        .ack = octeon_irq_ciu0_timer_ack_v2,
-        .eoi = octeon_irq_ciu0_eoi_v2,
-#ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu0_set_affinity_v2,
-#endif
+/* The mbox versions don't do any affinity or round-robin. */
+static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
+        .name = "CIU0-M",
+        .enable = octeon_irq_ciu0_enable_mbox_v2,
+        .disable = octeon_irq_ciu0_disable,
+        .eoi = octeon_irq_ciu0_eoi_mbox_v2,
 };
 
-static struct irq_chip octeon_irq_chip_ciu0_timer = {
-        .name = "CIU0-T",
-        .enable = octeon_irq_ciu0_enable,
+static struct irq_chip octeon_irq_chip_ciu0_mbox = {
+        .name = "CIU0-M",
+        .enable = octeon_irq_ciu0_enable_mbox,
         .disable = octeon_irq_ciu0_disable,
-        .ack = octeon_irq_ciu0_timer_ack_v1,
         .eoi = octeon_irq_ciu0_eoi,
-#ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu0_set_affinity,
-#endif
 };
 
-
 static void octeon_irq_ciu1_ack(unsigned int irq)
 {
         /*
@@ -365,10 +452,30 @@ static void octeon_irq_ciu1_eoi(unsigned int irq)
 
 static void octeon_irq_ciu1_enable(unsigned int irq)
 {
-        int coreid = cvmx_get_core_num();
+        struct irq_desc *desc = irq_to_desc(irq);
+        int coreid = next_coreid_for_irq(desc);
+        unsigned long flags;
+        uint64_t en1;
+        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+
+        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+        en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+        en1 |= 1ull << bit;
+        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+        cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+}
+
+/*
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
+ */
+static void octeon_irq_ciu1_wd_enable(unsigned int irq)
+{
         unsigned long flags;
         uint64_t en1;
         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+        int coreid = bit;
 
         raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
         en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
@@ -405,36 +512,43 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
  */
 static void octeon_irq_ciu1_enable_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2 + 1;
+        int index;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+        struct irq_desc *desc = irq_to_desc(irq);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        if ((desc->status & IRQ_DISABLED) == 0) {
+                index = next_coreid_for_irq(desc) * 2 + 1;
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        }
 }
 
 /*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
  */
-static void octeon_irq_ciu1_ack_v2(unsigned int irq)
+static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2 + 1;
+        int index;
+        int coreid = irq - OCTEON_IRQ_WDOG0;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+        struct irq_desc *desc = irq_to_desc(irq);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+        if ((desc->status & IRQ_DISABLED) == 0) {
+                index = coreid * 2 + 1;
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        }
 }
 
 /*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu1_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu1_ack_v2(unsigned int irq)
 {
-        struct irq_desc *desc = irq_desc + irq;
         int index = cvmx_get_core_num() * 2 + 1;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
 
-        if ((desc->status & IRQ_DISABLED) == 0)
-                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
 }
 
 /*
@@ -457,19 +571,30 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
                                         const struct cpumask *dest)
 {
         int cpu;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         unsigned long flags;
         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
 
+        /*
+         * For non-v2 CIU, we will allow only single CPU affinity.
+         * This removes the need to do locking in the .ack/.eoi
+         * functions.
+         */
+        if (cpumask_weight(dest) != 1)
+                return -EINVAL;
+
         raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 uint64_t en1 =
-                        cvmx_read_csr(CVMX_CIU_INTX_EN1
-                                (coreid * 2 + 1));
-                if (cpumask_test_cpu(cpu, dest))
+                        cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         en1 |= 1ull << bit;
-                else
+                } else {
                         en1 &= ~(1ull << bit);
+                }
                 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
         }
         /*
@@ -491,13 +616,17 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
 {
         int cpu;
         int index;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
         for_each_online_cpu(cpu) {
                 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
-                if (cpumask_test_cpu(cpu, dest))
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
-                else
+                } else {
                         cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+                }
         }
         return 0;
 }
@@ -507,11 +636,10 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
  * Newer octeon chips have support for lockless CIU operation.
  */
 static struct irq_chip octeon_irq_chip_ciu1_v2 = {
-        .name = "CIU0",
+        .name = "CIU1",
         .enable = octeon_irq_ciu1_enable_v2,
         .disable = octeon_irq_ciu1_disable_all_v2,
-        .ack = octeon_irq_ciu1_ack_v2,
-        .eoi = octeon_irq_ciu1_eoi_v2,
+        .eoi = octeon_irq_ciu1_enable_v2,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu1_set_affinity_v2,
 #endif
@@ -521,103 +649,36 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
         .name = "CIU1",
         .enable = octeon_irq_ciu1_enable,
         .disable = octeon_irq_ciu1_disable,
-        .ack = octeon_irq_ciu1_ack,
         .eoi = octeon_irq_ciu1_eoi,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu1_set_affinity,
 #endif
 };
 
-#ifdef CONFIG_PCI_MSI
-
-static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
-
-static void octeon_irq_msi_ack(unsigned int irq)
-{
-        if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                /* These chips have PCI */
-                cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
-                               1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-        } else {
-                /*
-                 * These chips have PCIe. Thankfully the ACK doesn't
-                 * need any locking.
-                 */
-                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
-                               1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-        }
-}
-
-static void octeon_irq_msi_eoi(unsigned int irq)
-{
-        /* Nothing needed */
-}
-
-static void octeon_irq_msi_enable(unsigned int irq)
-{
-        if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                /*
-                 * Octeon PCI doesn't have the ability to mask/unmask
-                 * MSI interrupts individually.  Instead of
-                 * masking/unmasking them in groups of 16, we simple
-                 * assume MSI devices are well behaved.  MSI
-                 * interrupts are always enable and the ACK is assumed
-                 * to be enough.
-                 */
-        } else {
-                /* These chips have PCIe.  Note that we only support
-                 * the first 64 MSI interrupts.  Unfortunately all the
-                 * MSI enables are in the same register.  We use
-                 * MSI0's lock to control access to them all.
-                 */
-                uint64_t en;
-                unsigned long flags;
-                raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
-                en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
-                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
-                cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
-        }
-}
-
-static void octeon_irq_msi_disable(unsigned int irq)
-{
-        if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                /* See comment in enable */
-        } else {
-                /*
-                 * These chips have PCIe.  Note that we only support
-                 * the first 64 MSI interrupts.  Unfortunately all the
-                 * MSI enables are in the same register.  We use
-                 * MSI0's lock to control access to them all.
-                 */
-                uint64_t en;
-                unsigned long flags;
-                raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
-                en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
-                cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
-        }
-}
+static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
+        .name = "CIU1-W",
+        .enable = octeon_irq_ciu1_wd_enable_v2,
+        .disable = octeon_irq_ciu1_disable_all_v2,
+        .eoi = octeon_irq_ciu1_wd_enable_v2,
+};
 
-static struct irq_chip octeon_irq_chip_msi = {
-        .name = "MSI",
-        .enable = octeon_irq_msi_enable,
-        .disable = octeon_irq_msi_disable,
-        .ack = octeon_irq_msi_ack,
-        .eoi = octeon_irq_msi_eoi,
+static struct irq_chip octeon_irq_chip_ciu1_wd = {
+        .name = "CIU1-W",
+        .enable = octeon_irq_ciu1_wd_enable,
+        .disable = octeon_irq_ciu1_disable,
+        .eoi = octeon_irq_ciu1_eoi,
 };
-#endif
+
+static void (*octeon_ciu0_ack)(unsigned int);
+static void (*octeon_ciu1_ack)(unsigned int);
 
 void __init arch_init_irq(void)
 {
-        int irq;
+        unsigned int irq;
         struct irq_chip *chip0;
-        struct irq_chip *chip0_timer;
+        struct irq_chip *chip0_mbox;
         struct irq_chip *chip1;
+        struct irq_chip *chip1_wd;
 
 #ifdef CONFIG_SMP
         /* Set the default affinity to the boot cpu. */
@@ -631,13 +692,19 @@ void __init arch_init_irq(void)
         if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
             OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
+                octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
+                octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
                 chip0 = &octeon_irq_chip_ciu0_v2;
-                chip0_timer = &octeon_irq_chip_ciu0_timer_v2;
+                chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
                 chip1 = &octeon_irq_chip_ciu1_v2;
+                chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
         } else {
+                octeon_ciu0_ack = octeon_irq_ciu0_ack;
+                octeon_ciu1_ack = octeon_irq_ciu1_ack;
                 chip0 = &octeon_irq_chip_ciu0;
-                chip0_timer = &octeon_irq_chip_ciu0_timer;
+                chip0_mbox = &octeon_irq_chip_ciu0_mbox;
                 chip1 = &octeon_irq_chip_ciu1;
+                chip1_wd = &octeon_irq_chip_ciu1_wd;
         }
 
         /* 0 - 15 reserved for i8259 master and slave controller. */
@@ -651,34 +718,23 @@ void __init arch_init_irq(void)
         /* 24 - 87 CIU_INT_SUM0 */
         for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
                 switch (irq) {
-                case OCTEON_IRQ_GMX_DRP0:
-                case OCTEON_IRQ_GMX_DRP1:
-                case OCTEON_IRQ_IPD_DRP:
-                case OCTEON_IRQ_KEY_ZERO:
-                case OCTEON_IRQ_TIMER0:
-                case OCTEON_IRQ_TIMER1:
-                case OCTEON_IRQ_TIMER2:
-                case OCTEON_IRQ_TIMER3:
-                        set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
+                case OCTEON_IRQ_MBOX0:
+                case OCTEON_IRQ_MBOX1:
+                        set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
                         break;
                 default:
-                        set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
+                        set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
                         break;
                 }
         }
 
         /* 88 - 151 CIU_INT_SUM1 */
-        for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
-                set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
-        }
+        for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
+                set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
+
+        for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
+                set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
 
-#ifdef CONFIG_PCI_MSI
-        /* 152 - 215 PCI/PCIe MSI interrupts */
-        for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
-                set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
-                                         handle_percpu_irq);
-        }
-#endif
         set_c0_status(0x300 << 2);
 }
 
@@ -693,6 +749,7 @@ asmlinkage void plat_irq_dispatch(void)
         unsigned long cop0_status;
         uint64_t ciu_en;
         uint64_t ciu_sum;
+        unsigned int irq;
 
         while (1) {
                 cop0_cause = read_c0_cause();
@@ -704,18 +761,24 @@ asmlinkage void plat_irq_dispatch(void)
                         ciu_sum = cvmx_read_csr(ciu_sum0_address);
                         ciu_en = cvmx_read_csr(ciu_en0_address);
                         ciu_sum &= ciu_en;
-                        if (likely(ciu_sum))
-                                do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
-                        else
+                        if (likely(ciu_sum)) {
+                                irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
+                                octeon_ciu0_ack(irq);
+                                do_IRQ(irq);
+                        } else {
                                 spurious_interrupt();
+                        }
                 } else if (unlikely(cop0_cause & STATUSF_IP3)) {
                         ciu_sum = cvmx_read_csr(ciu_sum1_address);
                         ciu_en = cvmx_read_csr(ciu_en1_address);
                         ciu_sum &= ciu_en;
-                        if (likely(ciu_sum))
-                                do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
-                        else
+                        if (likely(ciu_sum)) {
+                                irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
+                                octeon_ciu1_ack(irq);
+                                do_IRQ(irq);
+                        } else {
                                 spurious_interrupt();
+                        }
                 } else if (likely(cop0_cause)) {
                         do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
                 } else {
@@ -725,54 +788,84 @@ asmlinkage void plat_irq_dispatch(void)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
-{
-        unsigned int isset;
-        int coreid = octeon_coreid_for_cpu(cpu);
-        int bit = (irq < OCTEON_IRQ_WDOG0) ?
-                   irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
-       if (irq < 64) {
-                isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
-                        (1ull << bit)) >> bit;
-       } else {
-               isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
-                        (1ull << bit)) >> bit;
-       }
-       return isset;
-}
 
 void fixup_irqs(void)
 {
-       int irq;
+        int irq;
+        struct irq_desc *desc;
+        cpumask_t new_affinity;
+        unsigned long flags;
+        int do_set_affinity;
+        int cpu;
+
+        cpu = smp_processor_id();
 
         for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
                 octeon_irq_core_disable_local(irq);
 
-        for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
-                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                        /* ciu irq migrates to next cpu */
-                        octeon_irq_chip_ciu0.disable(irq);
-                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
-                }
-        }
-
-#if 0
-        for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
-                octeon_irq_mailbox_mask(irq);
-#endif
-        for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
-                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                        /* ciu irq migrates to next cpu */
-                        octeon_irq_chip_ciu0.disable(irq);
-                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
-                }
-        }
+        for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
+                desc = irq_to_desc(irq);
+                switch (irq) {
+                case OCTEON_IRQ_MBOX0:
+                case OCTEON_IRQ_MBOX1:
+                        /* The eoi function will disable them on this CPU. */
+                        desc->chip->eoi(irq);
+                        break;
+                case OCTEON_IRQ_WDOG0:
+                case OCTEON_IRQ_WDOG1:
+                case OCTEON_IRQ_WDOG2:
+                case OCTEON_IRQ_WDOG3:
+                case OCTEON_IRQ_WDOG4:
+                case OCTEON_IRQ_WDOG5:
+                case OCTEON_IRQ_WDOG6:
+                case OCTEON_IRQ_WDOG7:
+                case OCTEON_IRQ_WDOG8:
+                case OCTEON_IRQ_WDOG9:
+                case OCTEON_IRQ_WDOG10:
+                case OCTEON_IRQ_WDOG11:
+                case OCTEON_IRQ_WDOG12:
+                case OCTEON_IRQ_WDOG13:
+                case OCTEON_IRQ_WDOG14:
+                case OCTEON_IRQ_WDOG15:
+                        /*
+                         * These have special per CPU semantics and
+                         * are handled in the watchdog driver.
+                         */
+                        break;
+                default:
+                        raw_spin_lock_irqsave(&desc->lock, flags);
+                        /*
+                         * If this irq has an action, it is in use and
+                         * must be migrated if it has affinity to this
+                         * cpu.
+                         */
+                        if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
+                                if (cpumask_weight(desc->affinity) > 1) {
+                                        /*
+                                         * It has multi CPU affinity,
+                                         * just remove this CPU from
+                                         * the affinity set.
+                                         */
+                                        cpumask_copy(&new_affinity, desc->affinity);
+                                        cpumask_clear_cpu(cpu, &new_affinity);
+                                } else {
+                                        /*
+                                         * Otherwise, put it on lowest
+                                         * numbered online CPU.
+                                         */
+                                        cpumask_clear(&new_affinity);
+                                        cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
+                                }
+                                do_set_affinity = 1;
+                        } else {
+                                do_set_affinity = 0;
+                        }
+                        raw_spin_unlock_irqrestore(&desc->lock, flags);
+
+                        if (do_set_affinity)
+                                irq_set_affinity(irq, &new_affinity);
 
-        for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
-                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                        /* ciu irq migrates to next cpu */
-                        octeon_irq_chip_ciu1.disable(irq);
-                        octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
+                        break;
                 }
         }
 }
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 0f7f84accf9a..428864b2ba41 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -23,14 +23,16 @@
 #include <linux/types.h>
 
 struct boot_init_vector {
-        uint32_t stack_addr;
-        uint32_t code_addr;
+        /* First stage address - in ram instead of flash */
+        uint64_t code_addr;
+        /* Setup code for application, NOT application entry point */
         uint32_t app_start_func_addr;
+        /* k0 is used for global data - needs to be passed to other cores */
         uint32_t k0_val;
-        uint32_t flags;
-        uint32_t boot_info_addr;
+        /* Address of boot info block structure */
+        uint64_t boot_info_addr;
+        uint32_t flags;         /* flags */
         uint32_t pad;
-        uint32_t pad2;
 };
 
 /* similar to bootloader's linux_app_boot_info but without global data */
@@ -40,7 +42,7 @@ struct linux_app_boot_info {
         uint32_t avail_coremask;
         uint32_t pci_console_active;
         uint32_t icache_prefetch_disable;
-        uint32_t InitTLBStart_addr;
+        uint64_t InitTLBStart_addr;
         uint32_t start_app_addr;
         uint32_t cur_exception_base;
         uint32_t no_mark_private_data;
@@ -58,7 +60,7 @@ struct linux_app_boot_info {
 
 #define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
 
-#define LABI_SIGNATURE 0xAABBCCDD
+#define LABI_SIGNATURE 0xAABBCC01
 
 /*  from uboot-headers/octeon_mem_map.h */
 #define EXCEPTION_BASE_INCR     (4 * 1024)
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 83eac37a1ff9..638adab02842 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -18,11 +18,7 @@
 
 #include <asm/octeon/octeon.h>
 
-#ifdef CONFIG_GDB_CONSOLE
-#define DEBUG_UART 0
-#else
 #define DEBUG_UART 1
-#endif
 
 unsigned int octeon_serial_in(struct uart_port *up, int offset)
 {
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d1b5ffaf0281..69197cb6c7ea 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -32,6 +32,7 @@
 #include <asm/time.h>
 
 #include <asm/octeon/octeon.h>
+#include <asm/octeon/pci-octeon.h>
 
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 extern void cvmx_interrupt_rsl_decode(void);
@@ -578,9 +579,6 @@ void __init prom_init(void)
         }
 
         if (strstr(arcs_cmdline, "console=") == NULL) {
-#ifdef CONFIG_GDB_CONSOLE
-                strcat(arcs_cmdline, " console=gdb");
-#else
 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
                 strcat(arcs_cmdline, " console=ttyS0,115200");
 #else
@@ -589,7 +587,6 @@ void __init prom_init(void)
                 else
                         strcat(arcs_cmdline, " console=ttyS0,115200");
 #endif
-#endif
         }
 
         if (octeon_is_simulation()) {
@@ -598,13 +595,13 @@ void __init prom_init(void)
                  * the filesystem. Also specify the calibration delay
                  * to avoid calculating it every time.
                  */
-                strcat(arcs_cmdline, " rw root=1f00"
-                       " lpj=60176 slram=root,0x40000000,+1073741824");
+                strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
         }
 
         mips_hpt_frequency = octeon_get_clock_rate();
 
         octeon_init_cvmcount();
+        octeon_setup_delays();
 
         _machine_restart = octeon_restart;
         _machine_halt = octeon_halt;
@@ -613,6 +610,22 @@ void __init prom_init(void)
         register_smp_ops(&octeon_smp_ops);
 }
 
+/* Exclude a single page from the regions obtained in plat_mem_setup. */
+static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
+{
+        if (addr > *mem && addr < *mem + *size) {
+                u64 inc = addr - *mem;
+                add_memory_region(*mem, inc, BOOT_MEM_RAM);
+                *mem += inc;
+                *size -= inc;
+        }
+
+        if (addr == *mem && *size > PAGE_SIZE) {
+                *mem += PAGE_SIZE;
+                *size -= PAGE_SIZE;
+        }
+}
+
 void __init plat_mem_setup(void)
 {
         uint64_t mem_alloc_size;
@@ -663,12 +676,27 @@ void __init plat_mem_setup(void)
                                                 CVMX_BOOTMEM_FLAG_NO_LOCKING);
 #endif
                 if (memory >= 0) {
+                        u64 size = mem_alloc_size;
+
+                        /*
+                         * exclude a page at the beginning and end of
+                         * the 256MB PCIe 'hole' so the kernel will not
+                         * try to allocate multi-page buffers that
+                         * span the discontinuity.
+                         */
+                        memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
+                                            &memory, &size);
+                        memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
+                                            CVMX_PCIE_BAR1_PHYS_SIZE,
+                                            &memory, &size);
+
                         /*
                          * This function automatically merges address
                          * regions next to each other if they are
                          * received in incrementing order.
                          */
-                        add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
+                        if (size)
+                                add_memory_region(memory, size, BOOT_MEM_RAM);
                         total += mem_alloc_size;
                 } else {
                         break;
@@ -691,7 +719,10 @@ void __init plat_mem_setup(void)
                       "cvmx_bootmem_phy_alloc\n");
 }
 
-
+/*
+ * Emit one character to the boot UART.  Exported for use by the
+ * watchdog timer.
+ */
 int prom_putchar(char c)
 {
         uint64_t lsrval;
@@ -705,6 +736,7 @@ int prom_putchar(char c)
         cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
         return 1;
 }
+EXPORT_SYMBOL(prom_putchar);
 
 void prom_free_prom_memory(void)
 {
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 6d99b9d8887d..391cefe556b3 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  */
 #include <linux/cpu.h>
 #include <linux/init.h>
@@ -27,7 +27,8 @@ volatile unsigned long octeon_processor_sp;
 volatile unsigned long octeon_processor_gp;
 
 #ifdef CONFIG_HOTPLUG_CPU
-static unsigned int InitTLBStart_addr;
+uint64_t octeon_bootloader_entry_addr;
+EXPORT_SYMBOL(octeon_bootloader_entry_addr);
 #endif
 
 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
@@ -80,20 +81,13 @@ static inline void octeon_send_ipi_mask(const struct cpumask *mask,
 static void octeon_smp_hotplug_setup(void)
 {
 #ifdef CONFIG_HOTPLUG_CPU
-        uint32_t labi_signature;
-
-        labi_signature =
-                cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                        LABI_ADDR_IN_BOOTLOADER +
-                                        offsetof(struct linux_app_boot_info,
-                                                    labi_signature)));
-        if (labi_signature != LABI_SIGNATURE)
-                pr_err("The bootloader version on this board is incorrect\n");
-        InitTLBStart_addr =
-                cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                   LABI_ADDR_IN_BOOTLOADER +
-                                           offsetof(struct linux_app_boot_info,
-                                                    InitTLBStart_addr)));
+        struct linux_app_boot_info *labi;
+
+        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+        if (labi->labi_signature != LABI_SIGNATURE)
+                panic("The bootloader version on this board is incorrect.");
+
+        octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
 #endif
 }
 
@@ -102,24 +96,47 @@ static void octeon_smp_setup(void)
         const int coreid = cvmx_get_core_num();
         int cpus;
         int id;
-
         int core_mask = octeon_get_boot_coremask();
+#ifdef CONFIG_HOTPLUG_CPU
+        unsigned int num_cores = cvmx_octeon_num_cores();
+#endif
+
+        /* The present CPUs are initially just the boot cpu (CPU 0). */
+        for (id = 0; id < NR_CPUS; id++) {
+                set_cpu_possible(id, id == 0);
+                set_cpu_present(id, id == 0);
+        }
 
-        cpus_clear(cpu_possible_map);
         __cpu_number_map[coreid] = 0;
         __cpu_logical_map[0] = coreid;
-        cpu_set(0, cpu_possible_map);
 
+        /* The present CPUs get the lowest CPU numbers. */
         cpus = 1;
-        for (id = 0; id < 16; id++) {
+        for (id = 0; id < NR_CPUS; id++) {
                 if ((id != coreid) && (core_mask & (1 << id))) {
-                        cpu_set(cpus, cpu_possible_map);
+                        set_cpu_possible(cpus, true);
+                        set_cpu_present(cpus, true);
                         __cpu_number_map[id] = cpus;
                         __cpu_logical_map[cpus] = id;
                         cpus++;
                 }
         }
-        cpu_present_map = cpu_possible_map;
+
+#ifdef CONFIG_HOTPLUG_CPU
+        /*
+         * The possible CPUs are all those present on the chip.  We
+         * will assign CPU numbers for possible cores as well.  Cores
+         * are always consecutively numberd from 0.
+         */
+        for (id = 0; id < num_cores && id < NR_CPUS; id++) {
+                if (!(core_mask & (1 << id))) {
+                        set_cpu_possible(cpus, true);
+                        __cpu_number_map[id] = cpus;
+                        __cpu_logical_map[cpus] = id;
+                        cpus++;
+                }
+        }
+#endif
 
         octeon_smp_hotplug_setup();
 }
@@ -158,18 +175,21 @@ static void octeon_init_secondary(void)
 {
         const int coreid = cvmx_get_core_num();
         union cvmx_ciu_intx_sum0 interrupt_enable;
+        unsigned int sr;
 
 #ifdef CONFIG_HOTPLUG_CPU
-        unsigned int cur_exception_base;
-
-        cur_exception_base = cvmx_read64_uint32(
-                CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                             LABI_ADDR_IN_BOOTLOADER +
-                             offsetof(struct linux_app_boot_info,
-                                      cur_exception_base)));
-        /* cur_exception_base is incremented in bootloader after setting */
-        write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
+        struct linux_app_boot_info *labi;
+
+        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+        if (labi->labi_signature != LABI_SIGNATURE)
+                panic("The bootloader version on this board is incorrect.");
 #endif
+
+        sr = set_c0_status(ST0_BEV);
+        write_c0_ebase((u32)ebase);
+        write_c0_status(sr);
+
         octeon_check_cpu_bist();
         octeon_init_cvmcount();
         /*
@@ -276,8 +296,8 @@ static int octeon_cpu_disable(void)
 static void octeon_cpu_die(unsigned int cpu)
 {
         int coreid = cpu_logical_map(cpu);
-        uint32_t avail_coremask;
-        struct cvmx_bootmem_named_block_desc *block_desc;
+        uint32_t mask, new_mask;
+        const struct cvmx_bootmem_named_block_desc *block_desc;
 
         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
                 cpu_relax();
@@ -286,52 +306,40 @@ static void octeon_cpu_die(unsigned int cpu)
          * This is a bit complicated strategics of getting/settig available
          * cores mask, copied from bootloader
          */
+
+        mask = 1 << coreid;
         /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 
         if (!block_desc) {
-                avail_coremask =
-                        cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                   LABI_ADDR_IN_BOOTLOADER +
-                                                   offsetof
-                                                   (struct linux_app_boot_info,
-                                                    avail_coremask)));
-        } else {                       /* alternative, already initialized */
-               avail_coremask =
-                   cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                   block_desc->base_addr +
-                                                  AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
-        }
+                struct linux_app_boot_info *labi;
 
-        avail_coremask |= 1 << coreid;
+                labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 
-        /* Setting avail_coremask for bootoct binary */
-        if (!block_desc) {
-                cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                LABI_ADDR_IN_BOOTLOADER +
-                                                offsetof(struct linux_app_boot_info,
-                                                         avail_coremask)),
-                                   avail_coremask);
-        } else {
-                cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                block_desc->base_addr +
-                                                AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
-                                   avail_coremask);
+                labi->avail_coremask |= mask;
+                new_mask = labi->avail_coremask;
+        } else {                       /* alternative, already initialized */
+                uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
+                                                               AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
+                *p |= mask;
+                new_mask = *p;
         }
 
-        pr_info("Reset core %d. Available Coremask = %x\n", coreid,
-                avail_coremask);
+        pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
+        mb();
         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 }
 
 void play_dead(void)
 {
-        int coreid = cvmx_get_core_num();
+        int cpu = cpu_number_map(cvmx_get_core_num());
 
         idle_task_exit();
         octeon_processor_boot = 0xff;
-        per_cpu(cpu_state, coreid) = CPU_DEAD;
+        per_cpu(cpu_state, cpu) = CPU_DEAD;
+
+        mb();
 
         while (1)       /* core will be reset here */
                 ;
@@ -344,29 +352,27 @@ static void start_after_reset(void)
         kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
 }
 
-int octeon_update_boot_vector(unsigned int cpu)
+static int octeon_update_boot_vector(unsigned int cpu)
 {
 
         int coreid = cpu_logical_map(cpu);
-        unsigned int avail_coremask;
-        struct cvmx_bootmem_named_block_desc *block_desc;
+        uint32_t avail_coremask;
+        const struct cvmx_bootmem_named_block_desc *block_desc;
         struct boot_init_vector *boot_vect =
-                (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
-                                                  BOOTLOADER_BOOT_VECTOR);
+                (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
 
         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 
         if (!block_desc) {
-                avail_coremask =
-                        cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                           LABI_ADDR_IN_BOOTLOADER +
-                                                offsetof(struct linux_app_boot_info,
-                                                avail_coremask)));
+                struct linux_app_boot_info *labi;
+
+                labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+                avail_coremask = labi->avail_coremask;
+                labi->avail_coremask &= ~(1 << coreid);
         } else {                       /* alternative, already initialized */
-               avail_coremask =
-                   cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                   block_desc->base_addr +
-                                                   AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
+                avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
+                        block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
         }
 
         if (!(avail_coremask & (1 << coreid))) {
@@ -377,9 +383,9 @@ int octeon_update_boot_vector(unsigned int cpu)
 
         boot_vect[coreid].app_start_func_addr =
                 (uint32_t) (unsigned long) start_after_reset;
-        boot_vect[coreid].code_addr = InitTLBStart_addr;
+        boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
 
-        CVMX_SYNC;
+        mb();
 
         cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
 
@@ -405,17 +411,11 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
-        .notifier_call = octeon_cpu_callback,
-};
-
 static int __cpuinit register_cavium_notifier(void)
 {
-        register_hotcpu_notifier(&octeon_cpu_notifier);
-
+        hotcpu_notifier(octeon_cpu_callback, 0);
         return 0;
 }
-
 late_initcall(register_cavium_notifier);
 
 #endif  /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index 237926288d6d..61a334ac43ac 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -7,5 +7,3 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
 obj-$(CONFIG_PCI)               += pci.o
 obj-$(CONFIG_EARLY_PRINTK)      += console.o
 obj-$(CONFIG_MTD_PHYSMAP)       += mtd.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cobalt/Platform b/arch/mips/cobalt/Platform
new file mode 100644
index 000000000000..34123efd6dfe
--- /dev/null
+++ b/arch/mips/cobalt/Platform
@@ -0,0 +1,6 @@
+#
+# Cobalt Server
+#
+platform-$(CONFIG_MIPS_COBALT)  += cobalt/
+cflags-$(CONFIG_MIPS_COBALT)    += -I$(srctree)/arch/mips/include/asm/mach-cobalt
+load-$(CONFIG_MIPS_COBALT)      += 0xffffffff80080000
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index f66d406aadce..3a9ec6ccd40d 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1000=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index abb9a5805adc..4589b84301f3 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 991c20adf471..9950f2aabd31 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1200=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1200=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 5424c9167bf2..346ae631d1ef 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 949b6dcf634b..10eafb942af3 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1550=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
new file mode 100644
index 000000000000..17e2e624d03f
--- /dev/null
+++ b/arch/mips/configs/gpr_defconfig
@@ -0,0 +1,2060 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.35-rc6
+# Fri Jul 23 19:28:52 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+CONFIG_MIPS_ALCHEMY=y
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_MIPS_GPR=y
+CONFIG_SOC_AU1550=y
+CONFIG_LOONGSON_UART_BASE=y
+# CONFIG_LOONGSON_MC146818 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+CONFIG_NETFILTER_XT_MATCH_HL=m
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+# CONFIG_IP_VS_PROTO_SCTP is not set
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DECnet: Netfilter Configuration
+#
+CONFIG_DECNET_NF_GRABULATOR=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+# CONFIG_BRIDGE_EBT_NFLOG is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=y
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=y
+CONFIG_ATM_CLIP=y
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+CONFIG_DECNET=m
+# CONFIG_DECNET_ROUTER is not set
+CONFIG_LLC=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPDDP_DECAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_ECONET=m
+CONFIG_ECONET_AUNUDP=y
+CONFIG_ECONET_NATIVE=y
+CONFIG_WAN_ROUTER=m
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_MULTIQ is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+# CONFIG_NET_SCH_DRR is not set
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+CONFIG_AX25=m
+# CONFIG_AX25_DAMA_SLAVE is not set
+CONFIG_NETROM=m
+CONFIG_ROSE=m
+
+#
+# AX.25 network device drivers
+#
+CONFIG_MKISS=m
+CONFIG_6PACK=m
+CONFIG_BPQETHER=m
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+CONFIG_YAM=m
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=m
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_GPIO_ADDR is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+CONFIG_TIFM_CORE=m
+CONFIG_TIFM_7XX1=m
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# The newer stack is recommended.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=y
+CONFIG_ATH_DEBUG=y
+CONFIG_ATH5K=y
+CONFIG_ATH5K_DEBUG=y
+# CONFIG_ATH9K is not set
+# CONFIG_ATH9K_HTC is not set
+# CONFIG_AR9170_USB is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
+CONFIG_WAN=y
+CONFIG_LANMEDIA=m
+CONFIG_HDLC=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_X25=m
+CONFIG_PCI200SYN=m
+CONFIG_WANXL=m
+# CONFIG_PC300TOO is not set
+CONFIG_FARSYNC=m
+CONFIG_DSCC4=m
+CONFIG_DSCC4_PCISYNC=y
+CONFIG_DSCC4_PCI_RST=y
+CONFIG_DLCI=m
+CONFIG_DLCI_MAX=8
+CONFIG_WAN_ROUTER_DRIVERS=m
+CONFIG_CYCLADES_SYNC=m
+CONFIG_CYCLOMX_X25=y
+CONFIG_LAPBETHER=m
+CONFIG_X25_ASY=m
+CONFIG_ATM_DRIVERS=y
+# CONFIG_ATM_DUMMY is not set
+CONFIG_ATM_TCP=m
+CONFIG_ATM_LANAI=m
+CONFIG_ATM_ENI=m
+# CONFIG_ATM_ENI_DEBUG is not set
+# CONFIG_ATM_ENI_TUNE_BURST is not set
+CONFIG_ATM_FIRESTREAM=m
+CONFIG_ATM_ZATM=m
+# CONFIG_ATM_ZATM_DEBUG is not set
+CONFIG_ATM_NICSTAR=m
+# CONFIG_ATM_NICSTAR_USE_SUNI is not set
+# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
+CONFIG_ATM_IDT77252=m
+# CONFIG_ATM_IDT77252_DEBUG is not set
+# CONFIG_ATM_IDT77252_RCV_ALL is not set
+CONFIG_ATM_IDT77252_USE_SUNI=y
+CONFIG_ATM_AMBASSADOR=m
+# CONFIG_ATM_AMBASSADOR_DEBUG is not set
+CONFIG_ATM_HORIZON=m
+# CONFIG_ATM_HORIZON_DEBUG is not set
+CONFIG_ATM_IA=m
+# CONFIG_ATM_IA_DEBUG is not set
+CONFIG_ATM_FORE200E=m
+# CONFIG_ATM_FORE200E_USE_TASKLET is not set
+CONFIG_ATM_FORE200E_TX_RETRY=16
+CONFIG_ATM_FORE200E_DEBUG=0
+CONFIG_ATM_HE=m
+CONFIG_ATM_HE_USE_SUNI=y
+# CONFIG_ATM_SOLOS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOATM=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_NET_FC=y
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_AU1550 is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_SCH is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_CS5535 is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_LANGWELL is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+CONFIG_SENSORS_LM83=y
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TC35892 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=y
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ATM is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FSNOTIFY is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_LKDTM is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto"
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_SPINLOCK_TEST is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index cff8f4c0e57c..10d20aa731d3 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_MTX1=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 97382b698b9b..778f726af8e0 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
index e9ad77320f16..0f908c692111 100644
--- a/arch/mips/configs/pb1200_defconfig
+++ b/arch/mips/configs/pb1200_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1200=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1200=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 7497d3306b91..1c5fe6f06c0e 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index aa526f53cb1b..49494b01138b 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_ALCHEMY_GPIOINT_AU1000=y
 CONFIG_MIPS_PB1550=y
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
index 7291633d81cc..af0ab73bfce8 100644
--- a/arch/mips/configs/powertv_defconfig
+++ b/arch/mips/configs/powertv_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc5
-# Fri Aug 28 14:49:33 2009
+# Linux kernel version: 2.6.35-rc3
+# Thu Jul  1 11:03:28 2010
 #
 CONFIG_MIPS=y
 
@@ -11,11 +11,12 @@ CONFIG_MIPS=y
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
 # CONFIG_LASAT is not set
-# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_NEC_MARKEINS is not set
@@ -50,7 +51,6 @@ CONFIG_POWERTV=y
 # CONFIG_MIN_RUNTIME_RESOURCES is not set
 # CONFIG_BOOTLOADER_DRIVER is not set
 CONFIG_BOOTLOADER_FAMILY="R2"
-CONFIG_CSRC_POWERTV=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -65,9 +65,9 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_CEVT_R4K_LIB=y
 CONFIG_CEVT_R4K=y
+CONFIG_CSRC_POWERTV=y
 CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_SYS_HAS_EARLY_PRINTK=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_CPU_BIG_ENDIAN=y
@@ -79,7 +79,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
 #
 # CPU selection
 #
-# CONFIG_CPU_LOONGSON2 is not set
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 # CONFIG_CPU_MIPS32_R1 is not set
 CONFIG_CPU_MIPS32_R2=y
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -122,7 +123,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-CONFIG_CPU_HAS_LLSC=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
 CONFIG_CPU_MIPSR2_IRQ_VI=y
 CONFIG_CPU_MIPSR2_IRQ_EI=y
 CONFIG_CPU_HAS_SYNC=y
@@ -144,8 +145,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
@@ -177,6 +177,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="mips-linux-"
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
@@ -190,19 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=16
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 CONFIG_RELAY=y
 # CONFIG_NAMESPACES is not set
@@ -211,6 +208,7 @@ CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_RD_GZIP is not set
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -234,18 +232,16 @@ CONFIG_SHMEM=y
 CONFIG_AIO=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
 # CONFIG_VM_EVENT_COUNTERS is not set
 CONFIG_PCI_QUIRKS=y
 # CONFIG_SLUB_DEBUG is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 
 #
@@ -253,7 +249,7 @@ CONFIG_HAVE_OPROFILE=y
 #
 # CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
@@ -271,15 +267,41 @@ CONFIG_LBDAF=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
-# CONFIG_PROBE_INITRD_HEADER is not set
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -289,7 +311,6 @@ CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCI_IOV is not set
@@ -318,7 +339,6 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
@@ -390,12 +410,26 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_NETFILTER_NETLINK_LOG is not set
 # CONFIG_NF_CONNTRACK is not set
 CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+
+#
+# Xtables targets
+#
 # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
 # CONFIG_NETFILTER_XT_TARGET_MARK is not set
 # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
 # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
 # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
 # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
 # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
 # CONFIG_NETFILTER_XT_MATCH_DCCP is not set
 # CONFIG_NETFILTER_XT_MATCH_DSCP is not set
@@ -465,10 +499,13 @@ CONFIG_IP6_NF_FILTER=y
 # CONFIG_IP6_NF_RAW is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+# CONFIG_L2TP is not set
 CONFIG_STP=y
 CONFIG_BRIDGE=y
+CONFIG_BRIDGE_IGMP_SNOOPING=y
 # CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
@@ -526,10 +563,21 @@ CONFIG_NET_SCH_FIFO=y
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_WIRELESS is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+
+#
+# Some wireless drivers require a rate control algorithm
+#
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
 
 #
 # Device Drivers
@@ -539,6 +587,7 @@ CONFIG_NET_SCH_FIFO=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
@@ -550,9 +599,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
@@ -568,6 +617,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
 # CONFIG_MTD_OOPS is not set
 
 #
@@ -611,11 +661,16 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_SM_COMMON is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_DENALI is not set
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
 CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_RICOH is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_CAFE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
@@ -641,6 +696,10 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_UB is not set
@@ -658,6 +717,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -693,64 +753,95 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
 CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
 # CONFIG_SATA_SIL24 is not set
 CONFIG_ATA_SFF=y
-# CONFIG_SATA_SVW is not set
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
 # CONFIG_SATA_NV is not set
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
 # CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
 # CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
 # CONFIG_SATA_VITESSE is not set
-# CONFIG_SATA_INIC162X is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
 # CONFIG_PATA_ALI is not set
 # CONFIG_PATA_AMD is not set
 # CONFIG_PATA_ARTOP is not set
 # CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_ATP867X is not set
 # CONFIG_PATA_CMD64X is not set
 # CONFIG_PATA_CS5520 is not set
 # CONFIG_PATA_CS5530 is not set
 # CONFIG_PATA_CYPRESS is not set
 # CONFIG_PATA_EFAR is not set
-# CONFIG_ATA_GENERIC is not set
 # CONFIG_PATA_HPT366 is not set
 # CONFIG_PATA_HPT37X is not set
 # CONFIG_PATA_HPT3X2N is not set
 # CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IT821X is not set
 # CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
 # CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
 # CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87410 is not set
 # CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
 # CONFIG_PATA_PDC_OLD is not set
 # CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_RDC is not set
 # CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
 # CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_PDC2027X is not set
 # CONFIG_PATA_SIL680 is not set
 # CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
 # CONFIG_PATA_PLATFORM is not set
-# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
@@ -763,7 +854,7 @@ CONFIG_ATA_SFF=y
 #
 
 #
-# See the help texts for more information.
+# The newer stack is recommended.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -787,6 +878,7 @@ CONFIG_MII=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
@@ -800,6 +892,7 @@ CONFIG_MII=y
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_ATL2 is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
@@ -829,6 +922,8 @@ CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_CHELSIO_T3 is not set
+CONFIG_CHELSIO_T4_DEPENDS=y
+# CONFIG_CHELSIO_T4 is not set
 # CONFIG_ENIC is not set
 # CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
@@ -841,16 +936,12 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
+# CONFIG_QLCNIC is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
 # CONFIG_BE2NET is not set
 # CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+# CONFIG_WLAN is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -864,6 +955,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_USB_PEGASUS is not set
 CONFIG_USB_RTL8150=y
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
@@ -873,6 +965,7 @@ CONFIG_USB_RTL8150=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
@@ -882,6 +975,7 @@ CONFIG_USB_RTL8150=y
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -913,6 +1007,7 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
 # CONFIG_NOZOMI is not set
 
 #
@@ -924,6 +1019,9 @@ CONFIG_INPUT_EVDEV=y
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -934,6 +1032,7 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
 
@@ -945,7 +1044,6 @@ CONFIG_DEVPORT=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -953,20 +1051,14 @@ CONFIG_SSB_POSSIBLE=y
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_SUPPORT is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGA_ARB is not set
 # CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
@@ -980,7 +1072,6 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
 
 #
@@ -993,31 +1084,43 @@ CONFIG_USB_HIDDEV=y
 #
 # Special HID drivers
 #
+# CONFIG_HID_3M_PCT is not set
 # CONFIG_HID_A4TECH is not set
 # CONFIG_HID_APPLE is not set
 # CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
 # CONFIG_HID_CHERRY is not set
 # CONFIG_HID_CHICONY is not set
 # CONFIG_HID_CYPRESS is not set
 # CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
 # CONFIG_HID_EZKEY is not set
 # CONFIG_HID_KYE is not set
 # CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
 # CONFIG_HID_KENSINGTON is not set
 # CONFIG_HID_LOGITECH is not set
 # CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
 # CONFIG_HID_MONTEREY is not set
 # CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
 # CONFIG_HID_PANTHERLORD is not set
 # CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
 # CONFIG_HID_SAMSUNG is not set
 # CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
 # CONFIG_HID_SUNPLUS is not set
 # CONFIG_HID_GREENASIA is not set
 # CONFIG_HID_SMARTJOYPLUS is not set
 # CONFIG_HID_TOPSEED is not set
 # CONFIG_HID_THRUSTMASTER is not set
 # CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1032,7 +1135,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_MON is not set
@@ -1050,6 +1152,7 @@ CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1133,6 +1236,7 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
 # CONFIG_USB_SERIAL_QUALCOMM is not set
 # CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
@@ -1146,6 +1250,8 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 # CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
 # CONFIG_USB_SERIAL_DEBUG is not set
 
 #
@@ -1158,7 +1264,6 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -1171,7 +1276,6 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 
 #
@@ -1189,10 +1293,6 @@ CONFIG_RTC_LIB=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
 # CONFIG_STAGING is not set
 
 #
@@ -1214,6 +1314,7 @@ CONFIG_JBD=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
@@ -1274,6 +1375,7 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1284,7 +1386,6 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1299,6 +1400,7 @@ CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
@@ -1360,6 +1462,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1393,15 +1496,25 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
 # CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_TRACING_SUPPORT=y
 CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_PREEMPT_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
@@ -1410,19 +1523,22 @@ CONFIG_FTRACE=y
 CONFIG_BRANCH_PROFILE_NONE=y
 # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
 # CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
-# CONFIG_KMEMCHECK is not set
+# CONFIG_EARLY_PRINTK is not set
 CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
+CONFIG_CMDLINE=""
 # CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
+# CONFIG_SPINLOCK_TEST is not set
 
 #
 # Security options
@@ -1430,13 +1546,16 @@ CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
@@ -1479,11 +1598,13 @@ CONFIG_CRYPTO_CBC=y
 #
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile
index c530208ee154..9eb2f9c036aa 100644
--- a/arch/mips/dec/Makefile
+++ b/arch/mips/dec/Makefile
@@ -8,5 +8,3 @@ obj-y		:= ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
 obj-$(CONFIG_PROM_CONSOLE)      += promcon.o
 obj-$(CONFIG_TC)                += tc.o
 obj-$(CONFIG_CPU_HAS_WB)        += wbflush.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/dec/Platform b/arch/mips/dec/Platform
new file mode 100644
index 000000000000..3adbcbd95db1
--- /dev/null
+++ b/arch/mips/dec/Platform
@@ -0,0 +1,8 @@
+#
+# DECstation family
+#
+platform-$(CONFIG_MACH_DECSTATION)      = dec/
+cflags-$(CONFIG_MACH_DECSTATION)        += \
+                        -I$(srctree)/arch/mips/include/asm/mach-dec
+libs-$(CONFIG_MACH_DECSTATION)          += arch/mips/dec/prom/
+load-$(CONFIG_MACH_DECSTATION)          += 0xffffffff80040000
diff --git a/arch/mips/dec/promcon.c b/arch/mips/dec/promcon.c
index 9f0972f5a702..c239c25b79ff 100644
--- a/arch/mips/dec/promcon.c
+++ b/arch/mips/dec/promcon.c
@@ -33,8 +33,7 @@ static int __init prom_console_setup(struct console *co, char *options)
         return 0;
 }
 
-static struct console sercons =
-{
+static struct console sercons = {
         .name   = "ttyS",
         .write  = prom_console_write,
         .setup  = prom_console_setup,
diff --git a/arch/mips/emma/Makefile b/arch/mips/emma/Makefile
new file mode 100644
index 000000000000..4254a31edb09
--- /dev/null
+++ b/arch/mips/emma/Makefile
@@ -0,0 +1,6 @@
+obj-$(CONFIG_SOC_EMMA2RH)       += common/
+
+#
+# NEC EMMA2RH Mark-eins
+#
+obj-$(CONFIG_NEC_MARKEINS)      += markeins/
diff --git a/arch/mips/emma/Platform b/arch/mips/emma/Platform
new file mode 100644
index 000000000000..0282f7f99b88
--- /dev/null
+++ b/arch/mips/emma/Platform
@@ -0,0 +1,4 @@
+platform-$(CONFIG_SOC_EMMA2RH)  += emma/
+cflags-$(CONFIG_SOC_EMMA2RH)    +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-emma2rh
+load-$(CONFIG_NEC_MARKEINS)     += 0xffffffff88100000
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9504b7ee0b7c..3a96799eb65f 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
         /* setup cascade interrupts */
         setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
         setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
-        setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+        setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
 }
 
 asmlinkage void plat_irq_dispatch(void)
@@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP7)
-                do_IRQ(CPU_IRQ_BASE + 7);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & STATUSF_IP2)
                 emma2rh_irq_dispatch();
         else if (pending & STATUSF_IP1)
-                do_IRQ(CPU_IRQ_BASE + 1);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 1);
         else if (pending & STATUSF_IP0)
-                do_IRQ(CPU_IRQ_BASE + 0);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 0);
         else
                 spurious_interrupt();
 }
diff --git a/arch/mips/emma/markeins/setup.c b/arch/mips/emma/markeins/setup.c
index 9b3f51e5f140..feceebcfff42 100644
--- a/arch/mips/emma/markeins/setup.c
+++ b/arch/mips/emma/markeins/setup.c
@@ -52,7 +52,6 @@ static void markeins_machine_halt(void)
 
 static void markeins_machine_power_off(void)
 {
-        printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
         markeins_led("poweroff.");
         while (1) ;
 }
diff --git a/arch/mips/include/asm/arch_hweight.h b/arch/mips/include/asm/arch_hweight.h
new file mode 100644
index 000000000000..712a7445ee93
--- /dev/null
+++ b/arch/mips/include/asm/arch_hweight.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef _ASM_ARCH_HWEIGHT_H
+#define _ASM_ARCH_HWEIGHT_H
+
+#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
+
+#include <asm/types.h>
+
+static inline unsigned int __arch_hweight32(unsigned int w)
+{
+        return __builtin_popcount(w);
+}
+
+static inline unsigned int __arch_hweight16(unsigned int w)
+{
+        return __builtin_popcount(w & 0xffff);
+}
+
+static inline unsigned int __arch_hweight8(unsigned int w)
+{
+        return __builtin_popcount(w & 0xff);
+}
+
+static inline unsigned long __arch_hweight64(__u64 w)
+{
+        return __builtin_popcountll(w);
+}
+
+#else
+#include <asm-generic/bitops/arch_hweight.h>
+#endif
+
+#endif /* _ASM_ARCH_HWEIGHT_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 9255cfbee459..b0ce7ca2851f 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -700,7 +700,10 @@ static inline int ffs(int word)
 #ifdef __KERNEL__
 
 #include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
+
+#include <asm/arch_hweight.h>
+#include <asm-generic/bitops/const_hweight.h>
+
 #include <asm-generic/bitops/ext2-non-atomic.h>
 #include <asm-generic/bitops/ext2-atomic.h>
 #include <asm-generic/bitops/minix.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 09eee09780f2..15a8ef0707c6 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -71,6 +71,12 @@
 #define MACH_LEMOTE_LL2F       7
 #define MACH_LOONGSON_END      8
 
+/*
+ * Valid machtype for group INGENIC
+ */
+#define  MACH_INGENIC_JZ4730    0       /* JZ4730 SOC           */
+#define  MACH_INGENIC_JZ4740    1       /* JZ4740 SOC           */
+
 extern char *system_type;
 const char *get_system_type(void);
 
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 44437ed765e8..9161e684cb4c 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -30,6 +30,8 @@
 #define BRK_BUG         512     /* Used by BUG() */
 #define BRK_KDB         513     /* Used in KDB_ENTER() */
 #define BRK_MEMU        514     /* Used by FPU emulator */
+#define BRK_KPROBE_BP   515     /* Kprobe break */
+#define BRK_KPROBE_SSTEPBP 516  /* Kprobe single step software implementation */
 #define BRK_MULOVF      1023    /* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 256ad2cc6eb8..8f99c11ab665 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -62,6 +62,8 @@
  * RM7000-specific cacheops
  */
 #define Page_Invalidate_T       0x16
+#define Index_Store_Tag_T       0x0a
+#define Index_Load_Tag_T        0x06
 
 /*
  * R10000-specific cacheops
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 6b04c98b7fad..2cb2f0c2c4f8 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_COP2_H
 #define __ASM_COP2_H
 
+#include <linux/notifier.h>
+
 enum cu2_ops {
         CU2_EXCEPTION,
         CU2_LWC2_OP,
@@ -20,4 +22,14 @@ enum cu2_ops {
 extern int register_cu2_notifier(struct notifier_block *nb);
 extern int cu2_notifier_call_chain(unsigned long val, void *v);
 
+#define cu2_notifier(fn, pri)                                           \
+({                                                                      \
+        static struct notifier_block fn##_nb __cpuinitdata = {          \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_cu2_notifier(&fn##_nb);                                \
+})
+
 #endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index ac73cede3a0a..ca400f7c3f59 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -159,7 +159,8 @@
 
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
- * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels
+ * pre-MIPS32/MIPS53 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
+ * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */
 # ifndef cpu_has_clo_clz
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index a5acda416946..b201a8f5b127 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -34,7 +34,7 @@
 #define PRID_COMP_LSI           0x080000
 #define PRID_COMP_LEXRA         0x0b0000
 #define PRID_COMP_CAVIUM        0x0d0000
-
+#define PRID_COMP_INGENIC       0xd00000
 
 /*
  * Assigned values for the product ID register.  In order to detect a
@@ -133,6 +133,12 @@
 #define PRID_IMP_CAVIUM_CN52XX 0x0700
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
+ */
+
+#define PRID_IMP_JZRISC        0x0200
+
+/*
  * Definitions for 7:0 on legacy processors
  */
 
@@ -219,6 +225,7 @@ enum cpu_type_enum {
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
         CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
+        CPU_JZRISC,
 
         /*
          * MIPS64 class processors
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index ea77a42c5f8c..fd1d39eb7431 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -372,4 +372,9 @@ extern const char *__elf_platform;
 struct linux_binprm;
 extern int arch_setup_additional_pages(struct linux_binprm *bprm,
                                        int uses_interp);
+
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 2afb2fe11b30..c1449d20ef0e 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -99,88 +99,22 @@
 #define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
 #define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
 
-#define NUM_CPU_IRQ             8
 #define NUM_EMMA2RH_IRQ         96
 
-#define CPU_EMMA2RH_CASCADE     2
-#define CPU_IRQ_BASE            MIPS_CPU_IRQ_BASE
-#define EMMA2RH_IRQ_BASE        (CPU_IRQ_BASE + NUM_CPU_IRQ)
+#define EMMA2RH_IRQ_BASE        (MIPS_CPU_IRQ_BASE + 8)
 
 /*
  * emma2rh irq defs
  */
 
-#define EMMA2RH_IRQ_INT0        (0 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT1        (1 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT2        (2 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT3        (3 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT4        (4 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT5        (5 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT6        (6 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT7        (7 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT8        (8 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT9        (9 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT10       (10 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT11       (11 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT12       (12 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT13       (13 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT14       (14 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT15       (15 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT16       (16 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT17       (17 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT18       (18 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT19       (19 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT20       (20 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT21       (21 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT22       (22 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT23       (23 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT24       (24 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT25       (25 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT26       (26 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT27       (27 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT28       (28 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT29       (29 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT30       (30 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT31       (31 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT32       (32 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT33       (33 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT34       (34 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT35       (35 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT36       (36 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT37       (37 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT38       (38 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT39       (39 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT40       (40 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT41       (41 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT42       (42 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT43       (43 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT44       (44 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT45       (45 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT46       (46 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT47       (47 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT48       (48 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT49       (49 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT50       (50 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT51       (51 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT52       (52 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT53       (53 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT54       (54 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT55       (55 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT56       (56 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT57       (57 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT58       (58 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT59       (59 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT60       (60 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT61       (61 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT62       (62 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT63       (63 + EMMA2RH_IRQ_BASE)
-
-#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT49
-#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT50
-#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT51
-#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT56
-#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT57
-#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT58
+#define EMMA2RH_IRQ_INT(n)      (EMMA2RH_IRQ_BASE + (n))
+
+#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT(49)
+#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT(50)
+#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT(51)
+#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT(56)
+#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT(57)
+#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT(58)
 
 /*
  *  EMMA2RH Register Access
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 2618bf230248..bf2d229c2dae 100644
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -25,44 +25,13 @@
 #define NUM_EMMA2RH_IRQ_SW      32
 #define NUM_EMMA2RH_IRQ_GPIO    32
 
-#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
-#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
+#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
+#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
 
 #define EMMA2RH_SW_IRQ_BASE     (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
 #define EMMA2RH_GPIO_IRQ_BASE   (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
 
-#define EMMA2RH_SW_IRQ_INT0     (0+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT1     (1+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT2     (2+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT3     (3+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT4     (4+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT5     (5+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT6     (6+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT7     (7+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT8     (8+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT9     (9+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT10    (10+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT11    (11+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT12    (12+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT13    (13+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT14    (14+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT15    (15+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT16    (16+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT17    (17+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT18    (18+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT19    (19+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT20    (20+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT21    (21+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT22    (22+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT23    (23+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT24    (24+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT25    (25+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT26    (26+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT27    (27+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT28    (28+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT29    (29+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT30    (30+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT31    (31+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT(n)   (EMMA2RH_SW_IRQ_BASE + (n))
 
 #define MARKEINS_PCI_IRQ_INTA   EMMA2RH_GPIO_IRQ_BASE+15
 #define MARKEINS_PCI_IRQ_INTB   EMMA2RH_GPIO_IRQ_BASE+16
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 0eaf77ffbc4f..4e332165d7b7 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do {									\
         : "=r" (tmp));                                                  \
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -138,7 +138,7 @@ do {									\
                 __instruction_hazard();                                 \
 } while (0)
 
-#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
       defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
       defined(CONFIG_CPU_R5500)
 
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 6489f00731ca..444ff71aa0e8 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -247,6 +247,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
         unsigned int fmt : 2;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+        unsigned int opcode:6;
+        unsigned int code:20;
+        unsigned int func:6;
+};
+
 #elif defined(__MIPSEL__)
 
 struct j_format {       /* Jump format */
@@ -314,6 +320,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
         unsigned int opcode : 6;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+        unsigned int func:6;
+        unsigned int code:20;
+        unsigned int opcode:6;
+};
+
 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
 #endif
@@ -328,7 +340,8 @@ union mips_instruction {
         struct c_format c_format;
         struct r_format r_format;
         struct f_format f_format;
-        struct ma_format ma_format;
+        struct ma_format ma_format;
+        struct b_format b_format;
 };
 
 /* HACHACHAHCAHC ...  */
diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h
index 5bf62aafc890..6a9af5fcb5d7 100644
--- a/arch/mips/include/asm/kdebug.h
+++ b/arch/mips/include/asm/kdebug.h
@@ -8,6 +8,9 @@ enum die_val {
         DIE_FP,
         DIE_TRAP,
         DIE_RI,
+        DIE_PAGE_FAULT,
+        DIE_BREAK,
+        DIE_SSTEPBP
 };
 
 #endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/arch/mips/include/asm/kgdb.h b/arch/mips/include/asm/kgdb.h
index 19002d605ac4..e6c0b0e14ccb 100644
--- a/arch/mips/include/asm/kgdb.h
+++ b/arch/mips/include/asm/kgdb.h
@@ -8,28 +8,27 @@
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
         (_MIPS_ISA == _MIPS_ISA_MIPS32)
 
-#define KGDB_GDB_REG_SIZE 32
+#define KGDB_GDB_REG_SIZE       32
+#define GDB_SIZEOF_REG          sizeof(u32)
 
 #elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
         (_MIPS_ISA == _MIPS_ISA_MIPS64)
 
 #ifdef CONFIG_32BIT
-#define KGDB_GDB_REG_SIZE 32
+#define KGDB_GDB_REG_SIZE       32
+#define GDB_SIZEOF_REG          sizeof(u32)
 #else /* CONFIG_CPU_32BIT */
-#define KGDB_GDB_REG_SIZE 64
+#define KGDB_GDB_REG_SIZE       64
+#define GDB_SIZEOF_REG          sizeof(u64)
 #endif
 #else
 #error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
 #endif /* _MIPS_ISA */
 
 #define BUFMAX                  2048
-#if (KGDB_GDB_REG_SIZE == 32)
-#define NUMREGBYTES             (90*sizeof(u32))
-#define NUMCRITREGBYTES         (12*sizeof(u32))
-#else
-#define NUMREGBYTES             (90*sizeof(u64))
-#define NUMCRITREGBYTES         (12*sizeof(u64))
-#endif
+#define DBG_MAX_REG_NUM         72
+#define NUMREGBYTES             (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG))
+#define NUMCRITREGBYTES         (12 * sizeof(GDB_SIZEOF_REG))
 #define BREAK_INSTR_SIZE        4
 #define CACHE_FLUSH_IS_SAFE     0
 
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
new file mode 100644
index 000000000000..e6ea4d4d7205
--- /dev/null
+++ b/arch/mips/include/asm/kprobes.h
@@ -0,0 +1,92 @@
+/*
+ *  Kernel Probes (KProbes)
+ *  include/asm-mips/kprobes.h
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+
+#include <linux/ptrace.h>
+#include <linux/types.h>
+
+#include <asm/cacheflush.h>
+#include <asm/kdebug.h>
+#include <asm/inst.h>
+
+#define  __ARCH_WANT_KPROBES_INSN_SLOT
+
+struct kprobe;
+struct pt_regs;
+
+typedef union mips_instruction kprobe_opcode_t;
+
+#define MAX_INSN_SIZE 2
+
+#define flush_insn_slot(p)                                              \
+do {                                                                    \
+        flush_icache_range((unsigned long)p->addr,                      \
+                           (unsigned long)p->addr +                     \
+                           (MAX_INSN_SIZE * sizeof(kprobe_opcode_t)));  \
+} while (0)
+
+
+#define kretprobe_blacklist_size 0
+
+void arch_remove_kprobe(struct kprobe *p);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the original instruction */
+        kprobe_opcode_t *insn;
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+        unsigned long old_SR;
+        unsigned long saved_SR;
+        unsigned long saved_epc;
+};
+
+#define MAX_JPROBES_STACK_SIZE 128
+#define MAX_JPROBES_STACK_ADDR \
+        (((unsigned long)current_thread_info()) + THREAD_SIZE - 32 - sizeof(struct pt_regs))
+
+#define MIN_JPROBES_STACK_SIZE(ADDR)                                    \
+        ((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR)   \
+                ? MAX_JPROBES_STACK_ADDR - (ADDR)                       \
+                : MAX_JPROBES_STACK_SIZE)
+
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long kprobe_old_SR;
+        unsigned long kprobe_saved_SR;
+        unsigned long kprobe_saved_epc;
+        unsigned long jprobe_saved_sp;
+        struct pt_regs jprobe_saved_regs;
+        u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
+        struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+
+#endif                          /* _ASM_KPROBES_H */
diff --git a/arch/mips/include/asm/local64.h b/arch/mips/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/mips/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
index bae9b758fcde..49dc8d9db186 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -9,6 +9,7 @@ struct au1000_eth_platform_data {
         int phy_addr;
         int phy_busid;
         int phy_irq;
+        char mac[6];
 };
 
 void __init au1xxx_override_eth_cfg(unsigned port,
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index 0d8cc146f7a4..c58ebd8bc155 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -31,6 +31,9 @@ struct nvram_header {
 #define NVRAM_MAX_VALUE_LEN 255
 #define NVRAM_MAX_PARAM_LEN 64
 
+#define NVRAM_ERR_INV_PARAM     -8
+#define NVRAM_ERR_ENVNOTFOUND   -9
+
 extern int nvram_getenv(char *name, char *val, size_t val_len);
 
 #endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bbf054042395..b952fc7215e2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -61,21 +61,18 @@
 
 #define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
 
-#define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
 #define spin_lock_prefetch(x) prefetch(x)
 #define PREFETCH_STRIDE 128
 
-static inline int read_current_timer(unsigned long *result)
-{
-        asm volatile ("rdhwr %0,$31\n"
-#ifndef CONFIG_64BIT
-                      "\tsll %0, 0"
+#ifdef __OCTEON__
+/*
+ * All gcc versions that have OCTEON support define __OCTEON__ and have the
+ *  __builtin_popcount support.
+ */
+#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
 #endif
-                      : "=r" (*result));
-        return 0;
-}
 
 static inline int octeon_has_saa(void)
 {
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index d32220fbf4f1..6ddab8aef644 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,71 +172,9 @@
 #ifdef CONFIG_PCI_MSI
 /* 152 - 215 represent the MSI interrupts 0-63 */
 #define OCTEON_IRQ_MSI_BIT0     152
-#define OCTEON_IRQ_MSI_BIT1     153
-#define OCTEON_IRQ_MSI_BIT2     154
-#define OCTEON_IRQ_MSI_BIT3     155
-#define OCTEON_IRQ_MSI_BIT4     156
-#define OCTEON_IRQ_MSI_BIT5     157
-#define OCTEON_IRQ_MSI_BIT6     158
-#define OCTEON_IRQ_MSI_BIT7     159
-#define OCTEON_IRQ_MSI_BIT8     160
-#define OCTEON_IRQ_MSI_BIT9     161
-#define OCTEON_IRQ_MSI_BIT10    162
-#define OCTEON_IRQ_MSI_BIT11    163
-#define OCTEON_IRQ_MSI_BIT12    164
-#define OCTEON_IRQ_MSI_BIT13    165
-#define OCTEON_IRQ_MSI_BIT14    166
-#define OCTEON_IRQ_MSI_BIT15    167
-#define OCTEON_IRQ_MSI_BIT16    168
-#define OCTEON_IRQ_MSI_BIT17    169
-#define OCTEON_IRQ_MSI_BIT18    170
-#define OCTEON_IRQ_MSI_BIT19    171
-#define OCTEON_IRQ_MSI_BIT20    172
-#define OCTEON_IRQ_MSI_BIT21    173
-#define OCTEON_IRQ_MSI_BIT22    174
-#define OCTEON_IRQ_MSI_BIT23    175
-#define OCTEON_IRQ_MSI_BIT24    176
-#define OCTEON_IRQ_MSI_BIT25    177
-#define OCTEON_IRQ_MSI_BIT26    178
-#define OCTEON_IRQ_MSI_BIT27    179
-#define OCTEON_IRQ_MSI_BIT28    180
-#define OCTEON_IRQ_MSI_BIT29    181
-#define OCTEON_IRQ_MSI_BIT30    182
-#define OCTEON_IRQ_MSI_BIT31    183
-#define OCTEON_IRQ_MSI_BIT32    184
-#define OCTEON_IRQ_MSI_BIT33    185
-#define OCTEON_IRQ_MSI_BIT34    186
-#define OCTEON_IRQ_MSI_BIT35    187
-#define OCTEON_IRQ_MSI_BIT36    188
-#define OCTEON_IRQ_MSI_BIT37    189
-#define OCTEON_IRQ_MSI_BIT38    190
-#define OCTEON_IRQ_MSI_BIT39    191
-#define OCTEON_IRQ_MSI_BIT40    192
-#define OCTEON_IRQ_MSI_BIT41    193
-#define OCTEON_IRQ_MSI_BIT42    194
-#define OCTEON_IRQ_MSI_BIT43    195
-#define OCTEON_IRQ_MSI_BIT44    196
-#define OCTEON_IRQ_MSI_BIT45    197
-#define OCTEON_IRQ_MSI_BIT46    198
-#define OCTEON_IRQ_MSI_BIT47    199
-#define OCTEON_IRQ_MSI_BIT48    200
-#define OCTEON_IRQ_MSI_BIT49    201
-#define OCTEON_IRQ_MSI_BIT50    202
-#define OCTEON_IRQ_MSI_BIT51    203
-#define OCTEON_IRQ_MSI_BIT52    204
-#define OCTEON_IRQ_MSI_BIT53    205
-#define OCTEON_IRQ_MSI_BIT54    206
-#define OCTEON_IRQ_MSI_BIT55    207
-#define OCTEON_IRQ_MSI_BIT56    208
-#define OCTEON_IRQ_MSI_BIT57    209
-#define OCTEON_IRQ_MSI_BIT58    210
-#define OCTEON_IRQ_MSI_BIT59    211
-#define OCTEON_IRQ_MSI_BIT60    212
-#define OCTEON_IRQ_MSI_BIT61    213
-#define OCTEON_IRQ_MSI_BIT62    214
-#define OCTEON_IRQ_MSI_BIT63    215
+#define OCTEON_IRQ_MSI_LAST     (OCTEON_IRQ_MSI_BIT0 + 255)
 
-#define OCTEON_IRQ_LAST         216
+#define OCTEON_IRQ_LAST         (OCTEON_IRQ_MSI_LAST + 1)
 #else
 #define OCTEON_IRQ_LAST         152
 #endif
diff --git a/arch/mips/include/asm/mach-jz4740/base.h b/arch/mips/include/asm/mach-jz4740/base.h
new file mode 100644
index 000000000000..f37318605452
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/base.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_MACH_JZ4740_BASE_H__
+#define __ASM_MACH_JZ4740_BASE_H__
+
+#define JZ4740_CPM_BASE_ADDR    0x10000000
+#define JZ4740_INTC_BASE_ADDR   0x10001000
+#define JZ4740_WDT_BASE_ADDR    0x10002000
+#define JZ4740_TCU_BASE_ADDR    0x10002010
+#define JZ4740_RTC_BASE_ADDR    0x10003000
+#define JZ4740_GPIO_BASE_ADDR   0x10010000
+#define JZ4740_AIC_BASE_ADDR    0x10020000
+#define JZ4740_MSC_BASE_ADDR    0x10021000
+#define JZ4740_UART0_BASE_ADDR  0x10030000
+#define JZ4740_UART1_BASE_ADDR  0x10031000
+#define JZ4740_I2C_BASE_ADDR    0x10042000
+#define JZ4740_SSI_BASE_ADDR    0x10043000
+#define JZ4740_SADC_BASE_ADDR   0x10070000
+#define JZ4740_EMC_BASE_ADDR    0x13010000
+#define JZ4740_DMAC_BASE_ADDR   0x13020000
+#define JZ4740_UHC_BASE_ADDR    0x13030000
+#define JZ4740_UDC_BASE_ADDR    0x13040000
+#define JZ4740_LCD_BASE_ADDR    0x13050000
+#define JZ4740_SLCD_BASE_ADDR   0x13050000
+#define JZ4740_CIM_BASE_ADDR    0x13060000
+#define JZ4740_IPU_BASE_ADDR    0x13080000
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
new file mode 100644
index 000000000000..1b7408dd0e23
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/clock.h
@@ -0,0 +1,28 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_JZ4740_CLOCK_H__
+#define __ASM_JZ4740_CLOCK_H__
+
+enum jz4740_wait_mode {
+        JZ4740_WAIT_MODE_IDLE,
+        JZ4740_WAIT_MODE_SLEEP,
+};
+
+void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
+
+void jz4740_clock_udc_enable_auto_suspend(void);
+void jz4740_clock_udc_disable_auto_suspend(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
new file mode 100644
index 000000000000..d12e5c6477b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr   0
+#define cpu_has_counter         0
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc            1
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define kernel_uses_llsc        1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_pindexed_dcache 0
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_has_nofpuex 0
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_inclusive_pcaches 0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
new file mode 100644
index 000000000000..a3be12183599
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -0,0 +1,90 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ7420/JZ4740 DMA definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_DMA_H__
+#define __ASM_MACH_JZ4740_DMA_H__
+
+struct jz4740_dma_chan;
+
+enum jz4740_dma_request_type {
+        JZ4740_DMA_TYPE_AUTO_REQUEST    = 8,
+        JZ4740_DMA_TYPE_UART_TRANSMIT   = 20,
+        JZ4740_DMA_TYPE_UART_RECEIVE    = 21,
+        JZ4740_DMA_TYPE_SPI_TRANSMIT    = 22,
+        JZ4740_DMA_TYPE_SPI_RECEIVE     = 23,
+        JZ4740_DMA_TYPE_AIC_TRANSMIT    = 24,
+        JZ4740_DMA_TYPE_AIC_RECEIVE     = 25,
+        JZ4740_DMA_TYPE_MMC_TRANSMIT    = 26,
+        JZ4740_DMA_TYPE_MMC_RECEIVE     = 27,
+        JZ4740_DMA_TYPE_TCU             = 28,
+        JZ4740_DMA_TYPE_SADC            = 29,
+        JZ4740_DMA_TYPE_SLCD            = 30,
+};
+
+enum jz4740_dma_width {
+        JZ4740_DMA_WIDTH_32BIT  = 0,
+        JZ4740_DMA_WIDTH_8BIT   = 1,
+        JZ4740_DMA_WIDTH_16BIT  = 2,
+};
+
+enum jz4740_dma_transfer_size {
+        JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
+        JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
+        JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
+        JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
+        JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
+};
+
+enum jz4740_dma_flags {
+        JZ4740_DMA_SRC_AUTOINC = 0x2,
+        JZ4740_DMA_DST_AUTOINC = 0x1,
+};
+
+enum jz4740_dma_mode {
+        JZ4740_DMA_MODE_SINGLE  = 0,
+        JZ4740_DMA_MODE_BLOCK   = 1,
+};
+
+struct jz4740_dma_config {
+        enum jz4740_dma_width src_width;
+        enum jz4740_dma_width dst_width;
+        enum jz4740_dma_transfer_size transfer_size;
+        enum jz4740_dma_request_type request_type;
+        enum jz4740_dma_flags flags;
+        enum jz4740_dma_mode mode;
+};
+
+typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
+
+struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
+void jz4740_dma_free(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_configure(struct jz4740_dma_chan *dma,
+        const struct jz4740_dma_config *config);
+
+
+void jz4740_dma_enable(struct jz4740_dma_chan *dma);
+void jz4740_dma_disable(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
+
+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
+        jz4740_dma_complete_callback_t cb);
+
+#endif  /* __ASM_JZ4740_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
new file mode 100644
index 000000000000..7b74703745bb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/gpio.h
@@ -0,0 +1,398 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 GPIO pin definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _JZ_GPIO_H
+#define _JZ_GPIO_H
+
+#include <linux/types.h>
+
+enum jz_gpio_function {
+    JZ_GPIO_FUNC_NONE,
+    JZ_GPIO_FUNC1,
+    JZ_GPIO_FUNC2,
+    JZ_GPIO_FUNC3,
+};
+
+
+/*
+ Usually a driver for a SoC component has to request several gpio pins and
+ configure them as funcion pins.
+ jz_gpio_bulk_request can be used to ease this process.
+ Usually one would do something like:
+
+ const static struct jz_gpio_bulk_request i2c_pins[] = {
+        JZ_GPIO_BULK_PIN(I2C_SDA),
+        JZ_GPIO_BULK_PIN(I2C_SCK),
+ };
+
+ inside the probe function:
+
+    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
+    if (ret) {
+        ...
+
+ inside the remove function:
+
+    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
+
+
+*/
+struct jz_gpio_bulk_request {
+        int gpio;
+        const char *name;
+        enum jz_gpio_function function;
+};
+
+#define JZ_GPIO_BULK_PIN(pin) { \
+    .gpio = JZ_GPIO_ ## pin, \
+    .name = #pin, \
+    .function = JZ_GPIO_FUNC_ ## pin \
+}
+
+int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_enable_pullup(unsigned gpio);
+void jz_gpio_disable_pullup(unsigned gpio);
+int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
+
+int jz_gpio_port_direction_input(int port, uint32_t mask);
+int jz_gpio_port_direction_output(int port, uint32_t mask);
+void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
+uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
+
+#include <asm/mach-generic/gpio.h>
+
+#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
+#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
+#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
+#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
+
+/* Port A function pins */
+#define JZ_GPIO_MEM_DATA0               JZ_GPIO_PORTA(0)
+#define JZ_GPIO_MEM_DATA1               JZ_GPIO_PORTA(1)
+#define JZ_GPIO_MEM_DATA2               JZ_GPIO_PORTA(2)
+#define JZ_GPIO_MEM_DATA3               JZ_GPIO_PORTA(3)
+#define JZ_GPIO_MEM_DATA4               JZ_GPIO_PORTA(4)
+#define JZ_GPIO_MEM_DATA5               JZ_GPIO_PORTA(5)
+#define JZ_GPIO_MEM_DATA6               JZ_GPIO_PORTA(6)
+#define JZ_GPIO_MEM_DATA7               JZ_GPIO_PORTA(7)
+#define JZ_GPIO_MEM_DATA8               JZ_GPIO_PORTA(8)
+#define JZ_GPIO_MEM_DATA9               JZ_GPIO_PORTA(9)
+#define JZ_GPIO_MEM_DATA10              JZ_GPIO_PORTA(10)
+#define JZ_GPIO_MEM_DATA11              JZ_GPIO_PORTA(11)
+#define JZ_GPIO_MEM_DATA12              JZ_GPIO_PORTA(12)
+#define JZ_GPIO_MEM_DATA13              JZ_GPIO_PORTA(13)
+#define JZ_GPIO_MEM_DATA14              JZ_GPIO_PORTA(14)
+#define JZ_GPIO_MEM_DATA15              JZ_GPIO_PORTA(15)
+#define JZ_GPIO_MEM_DATA16              JZ_GPIO_PORTA(16)
+#define JZ_GPIO_MEM_DATA17              JZ_GPIO_PORTA(17)
+#define JZ_GPIO_MEM_DATA18              JZ_GPIO_PORTA(18)
+#define JZ_GPIO_MEM_DATA19              JZ_GPIO_PORTA(19)
+#define JZ_GPIO_MEM_DATA20              JZ_GPIO_PORTA(20)
+#define JZ_GPIO_MEM_DATA21              JZ_GPIO_PORTA(21)
+#define JZ_GPIO_MEM_DATA22              JZ_GPIO_PORTA(22)
+#define JZ_GPIO_MEM_DATA23              JZ_GPIO_PORTA(23)
+#define JZ_GPIO_MEM_DATA24              JZ_GPIO_PORTA(24)
+#define JZ_GPIO_MEM_DATA25              JZ_GPIO_PORTA(25)
+#define JZ_GPIO_MEM_DATA26              JZ_GPIO_PORTA(26)
+#define JZ_GPIO_MEM_DATA27              JZ_GPIO_PORTA(27)
+#define JZ_GPIO_MEM_DATA28              JZ_GPIO_PORTA(28)
+#define JZ_GPIO_MEM_DATA29              JZ_GPIO_PORTA(29)
+#define JZ_GPIO_MEM_DATA30              JZ_GPIO_PORTA(30)
+#define JZ_GPIO_MEM_DATA31              JZ_GPIO_PORTA(31)
+
+#define JZ_GPIO_FUNC_MEM_DATA0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA17         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA18         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA19         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA20         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA21         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA22         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA23         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA24         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA25         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA26         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA27         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA28         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA29         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA30         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA31         JZ_GPIO_FUNC1
+
+/* Port B function pins */
+#define JZ_GPIO_MEM_ADDR0               JZ_GPIO_PORTB(0)
+#define JZ_GPIO_MEM_ADDR1               JZ_GPIO_PORTB(1)
+#define JZ_GPIO_MEM_ADDR2               JZ_GPIO_PORTB(2)
+#define JZ_GPIO_MEM_ADDR3               JZ_GPIO_PORTB(3)
+#define JZ_GPIO_MEM_ADDR4               JZ_GPIO_PORTB(4)
+#define JZ_GPIO_MEM_ADDR5               JZ_GPIO_PORTB(5)
+#define JZ_GPIO_MEM_ADDR6               JZ_GPIO_PORTB(6)
+#define JZ_GPIO_MEM_ADDR7               JZ_GPIO_PORTB(7)
+#define JZ_GPIO_MEM_ADDR8               JZ_GPIO_PORTB(8)
+#define JZ_GPIO_MEM_ADDR9               JZ_GPIO_PORTB(9)
+#define JZ_GPIO_MEM_ADDR10              JZ_GPIO_PORTB(10)
+#define JZ_GPIO_MEM_ADDR11              JZ_GPIO_PORTB(11)
+#define JZ_GPIO_MEM_ADDR12              JZ_GPIO_PORTB(12)
+#define JZ_GPIO_MEM_ADDR13              JZ_GPIO_PORTB(13)
+#define JZ_GPIO_MEM_ADDR14              JZ_GPIO_PORTB(14)
+#define JZ_GPIO_MEM_ADDR15              JZ_GPIO_PORTB(15)
+#define JZ_GPIO_MEM_ADDR16              JZ_GPIO_PORTB(16)
+#define JZ_GPIO_LCD_CLS                 JZ_GPIO_PORTB(17)
+#define JZ_GPIO_LCD_SPL                 JZ_GPIO_PORTB(18)
+#define JZ_GPIO_MEM_DCS                 JZ_GPIO_PORTB(19)
+#define JZ_GPIO_MEM_RAS                 JZ_GPIO_PORTB(20)
+#define JZ_GPIO_MEM_CAS                 JZ_GPIO_PORTB(21)
+#define JZ_GPIO_MEM_SDWE                JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_CKE                 JZ_GPIO_PORTB(23)
+#define JZ_GPIO_MEM_CKO                 JZ_GPIO_PORTB(24)
+#define JZ_GPIO_MEM_CS0                 JZ_GPIO_PORTB(25)
+#define JZ_GPIO_MEM_CS1                 JZ_GPIO_PORTB(26)
+#define JZ_GPIO_MEM_CS2                 JZ_GPIO_PORTB(27)
+#define JZ_GPIO_MEM_CS3                 JZ_GPIO_PORTB(28)
+#define JZ_GPIO_MEM_RD                  JZ_GPIO_PORTB(29)
+#define JZ_GPIO_MEM_WR                  JZ_GPIO_PORTB(30)
+#define JZ_GPIO_MEM_WE0                 JZ_GPIO_PORTB(31)
+
+#define JZ_GPIO_FUNC_MEM_ADDR0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_CLS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_SPL            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DCS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RAS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CAS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_SDWE           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKE            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKO            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS0            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS1            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS2            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS3            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RD             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WR             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE0            JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR21              JZ_GPIO_PORTB(17)
+#define JZ_GPIO_MEM_ADDR22              JZ_GPIO_PORTB(18)
+
+#define JZ_GPIO_FUNC_MEM_ADDR21         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR22         JZ_GPIO_FUNC2
+
+/* Port C function pins */
+#define JZ_GPIO_LCD_DATA0               JZ_GPIO_PORTC(0)
+#define JZ_GPIO_LCD_DATA1               JZ_GPIO_PORTC(1)
+#define JZ_GPIO_LCD_DATA2               JZ_GPIO_PORTC(2)
+#define JZ_GPIO_LCD_DATA3               JZ_GPIO_PORTC(3)
+#define JZ_GPIO_LCD_DATA4               JZ_GPIO_PORTC(4)
+#define JZ_GPIO_LCD_DATA5               JZ_GPIO_PORTC(5)
+#define JZ_GPIO_LCD_DATA6               JZ_GPIO_PORTC(6)
+#define JZ_GPIO_LCD_DATA7               JZ_GPIO_PORTC(7)
+#define JZ_GPIO_LCD_DATA8               JZ_GPIO_PORTC(8)
+#define JZ_GPIO_LCD_DATA9               JZ_GPIO_PORTC(9)
+#define JZ_GPIO_LCD_DATA10              JZ_GPIO_PORTC(10)
+#define JZ_GPIO_LCD_DATA11              JZ_GPIO_PORTC(11)
+#define JZ_GPIO_LCD_DATA12              JZ_GPIO_PORTC(12)
+#define JZ_GPIO_LCD_DATA13              JZ_GPIO_PORTC(13)
+#define JZ_GPIO_LCD_DATA14              JZ_GPIO_PORTC(14)
+#define JZ_GPIO_LCD_DATA15              JZ_GPIO_PORTC(15)
+#define JZ_GPIO_LCD_DATA16              JZ_GPIO_PORTC(16)
+#define JZ_GPIO_LCD_DATA17              JZ_GPIO_PORTC(17)
+#define JZ_GPIO_LCD_PCLK                JZ_GPIO_PORTC(18)
+#define JZ_GPIO_LCD_HSYNC               JZ_GPIO_PORTC(19)
+#define JZ_GPIO_LCD_VSYNC               JZ_GPIO_PORTC(20)
+#define JZ_GPIO_LCD_DE                  JZ_GPIO_PORTC(21)
+#define JZ_GPIO_LCD_PS                  JZ_GPIO_PORTC(22)
+#define JZ_GPIO_LCD_REV                 JZ_GPIO_PORTC(23)
+#define JZ_GPIO_MEM_WE1                 JZ_GPIO_PORTC(24)
+#define JZ_GPIO_MEM_WE2                 JZ_GPIO_PORTC(25)
+#define JZ_GPIO_MEM_WE3                 JZ_GPIO_PORTC(26)
+#define JZ_GPIO_MEM_WAIT                JZ_GPIO_PORTC(27)
+#define JZ_GPIO_MEM_FRE                 JZ_GPIO_PORTC(28)
+#define JZ_GPIO_MEM_FWE                 JZ_GPIO_PORTC(29)
+
+#define JZ_GPIO_FUNC_LCD_DATA0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA17         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_VSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_HSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DE             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PS             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_REV            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE1            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE2            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE3            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WAIT           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FRE            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FWE            JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR19              JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_ADDR20              JZ_GPIO_PORTB(23)
+
+#define JZ_GPIO_FUNC_MEM_ADDR19         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR20         JZ_GPIO_FUNC2
+
+/* Port D function pins */
+#define JZ_GPIO_CIM_DATA0               JZ_GPIO_PORTD(0)
+#define JZ_GPIO_CIM_DATA1               JZ_GPIO_PORTD(1)
+#define JZ_GPIO_CIM_DATA2               JZ_GPIO_PORTD(2)
+#define JZ_GPIO_CIM_DATA3               JZ_GPIO_PORTD(3)
+#define JZ_GPIO_CIM_DATA4               JZ_GPIO_PORTD(4)
+#define JZ_GPIO_CIM_DATA5               JZ_GPIO_PORTD(5)
+#define JZ_GPIO_CIM_DATA6               JZ_GPIO_PORTD(6)
+#define JZ_GPIO_CIM_DATA7               JZ_GPIO_PORTD(7)
+#define JZ_GPIO_MSC_CMD                 JZ_GPIO_PORTD(8)
+#define JZ_GPIO_MSC_CLK                 JZ_GPIO_PORTD(9)
+#define JZ_GPIO_MSC_DATA0               JZ_GPIO_PORTD(10)
+#define JZ_GPIO_MSC_DATA1               JZ_GPIO_PORTD(11)
+#define JZ_GPIO_MSC_DATA2               JZ_GPIO_PORTD(12)
+#define JZ_GPIO_MSC_DATA3               JZ_GPIO_PORTD(13)
+#define JZ_GPIO_CIM_MCLK                JZ_GPIO_PORTD(14)
+#define JZ_GPIO_CIM_PCLK                JZ_GPIO_PORTD(15)
+#define JZ_GPIO_CIM_VSYNC               JZ_GPIO_PORTD(16)
+#define JZ_GPIO_CIM_HSYNC               JZ_GPIO_PORTD(17)
+#define JZ_GPIO_SPI_CLK                 JZ_GPIO_PORTD(18)
+#define JZ_GPIO_SPI_CE0                 JZ_GPIO_PORTD(19)
+#define JZ_GPIO_SPI_DT                  JZ_GPIO_PORTD(20)
+#define JZ_GPIO_SPI_DR                  JZ_GPIO_PORTD(21)
+#define JZ_GPIO_SPI_CE1                 JZ_GPIO_PORTD(22)
+#define JZ_GPIO_PWM0                    JZ_GPIO_PORTD(23)
+#define JZ_GPIO_PWM1                    JZ_GPIO_PORTD(24)
+#define JZ_GPIO_PWM2                    JZ_GPIO_PORTD(25)
+#define JZ_GPIO_PWM3                    JZ_GPIO_PORTD(26)
+#define JZ_GPIO_PWM4                    JZ_GPIO_PORTD(27)
+#define JZ_GPIO_PWM5                    JZ_GPIO_PORTD(28)
+#define JZ_GPIO_PWM6                    JZ_GPIO_PORTD(30)
+#define JZ_GPIO_PWM7                    JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_CIM_DATA           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA0          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA1          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA2          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA3          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA4          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA5          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA6          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA7          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_MSC_CMD            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_CLK            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA0          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA1          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA2          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA3          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_CIM_MCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_PCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_VSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_HSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CLK            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE0            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DT             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DR             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE1            JZ_GPIO_FUNC1
+
+#define JZ_GPIO_FUNC_PWM                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM0               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM1               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM2               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM3               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM4               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM5               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM6               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM7               JZ_GPIO_FUNC_PWM
+
+#define JZ_GPIO_MEM_SCLK_RSTN           JZ_GPIO_PORTD(18)
+#define JZ_GPIO_MEM_BCLK                JZ_GPIO_PORTD(19)
+#define JZ_GPIO_MEM_SDATO               JZ_GPIO_PORTD(20)
+#define JZ_GPIO_MEM_SDATI               JZ_GPIO_PORTD(21)
+#define JZ_GPIO_MEM_SYNC                JZ_GPIO_PORTD(22)
+#define JZ_GPIO_I2C_SDA                 JZ_GPIO_PORTD(23)
+#define JZ_GPIO_I2C_SCK                 JZ_GPIO_PORTD(24)
+#define JZ_GPIO_UART0_TXD               JZ_GPIO_PORTD(25)
+#define JZ_GPIO_UART0_RXD               JZ_GPIO_PORTD(26)
+#define JZ_GPIO_MEM_ADDR17              JZ_GPIO_PORTD(27)
+#define JZ_GPIO_MEM_ADDR18              JZ_GPIO_PORTD(28)
+#define JZ_GPIO_UART0_CTS               JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART0_RTS               JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_MEM_SCLK_RSTN      JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_BCLK           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATO          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATI          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SYNC           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SDA            JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SCK            JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_TXD          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RXD          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR17         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR18         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_CTS          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RTS          JZ_GPIO_FUNC2
+
+#define JZ_GPIO_UART1_RXD               JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART1_TXD               JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_UART1_RXD          JZ_GPIO_FUNC3
+#define JZ_GPIO_FUNC_UART1_TXD          JZ_GPIO_FUNC3
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
new file mode 100644
index 000000000000..a865c983c70a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -0,0 +1,57 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 IRQ definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_IRQ_H__
+#define __ASM_MACH_JZ4740_IRQ_H__
+
+#define MIPS_CPU_IRQ_BASE 0
+#define JZ4740_IRQ_BASE 8
+
+/* 1st-level interrupts */
+#define JZ4740_IRQ(x)           (JZ4740_IRQ_BASE + (x))
+#define JZ4740_IRQ_I2C          JZ4740_IRQ(1)
+#define JZ4740_IRQ_UHC          JZ4740_IRQ(3)
+#define JZ4740_IRQ_UART1        JZ4740_IRQ(8)
+#define JZ4740_IRQ_UART0        JZ4740_IRQ(9)
+#define JZ4740_IRQ_SADC         JZ4740_IRQ(12)
+#define JZ4740_IRQ_MSC          JZ4740_IRQ(14)
+#define JZ4740_IRQ_RTC          JZ4740_IRQ(15)
+#define JZ4740_IRQ_SSI          JZ4740_IRQ(16)
+#define JZ4740_IRQ_CIM          JZ4740_IRQ(17)
+#define JZ4740_IRQ_AIC          JZ4740_IRQ(18)
+#define JZ4740_IRQ_ETH          JZ4740_IRQ(19)
+#define JZ4740_IRQ_DMAC         JZ4740_IRQ(20)
+#define JZ4740_IRQ_TCU2         JZ4740_IRQ(21)
+#define JZ4740_IRQ_TCU1         JZ4740_IRQ(22)
+#define JZ4740_IRQ_TCU0         JZ4740_IRQ(23)
+#define JZ4740_IRQ_UDC          JZ4740_IRQ(24)
+#define JZ4740_IRQ_GPIO3        JZ4740_IRQ(25)
+#define JZ4740_IRQ_GPIO2        JZ4740_IRQ(26)
+#define JZ4740_IRQ_GPIO1        JZ4740_IRQ(27)
+#define JZ4740_IRQ_GPIO0        JZ4740_IRQ(28)
+#define JZ4740_IRQ_IPU          JZ4740_IRQ(29)
+#define JZ4740_IRQ_LCD          JZ4740_IRQ(30)
+
+/* 2nd-level interrupts */
+#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (X))
+
+#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
+#define JZ4740_IRQ_GPIO(x)      (JZ4740_IRQ(48) + (x))
+
+#define JZ4740_IRQ_ADC_BASE     JZ4740_IRQ(176)
+
+#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_fb.h b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
new file mode 100644
index 000000000000..6a50e6f7a21a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
@@ -0,0 +1,67 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
+#define __ASM_MACH_JZ4740_JZ4740_FB_H__
+
+#include <linux/fb.h>
+
+enum jz4740_fb_lcd_type {
+        JZ_LCD_TYPE_GENERIC_16_BIT = 0,
+        JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
+        JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
+        JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
+        JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
+        JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
+        JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
+        JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
+        JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
+        JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
+        JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
+        JZ_LCD_TYPE_8BIT_SERIAL = 12,
+};
+
+#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
+
+/*
+* width: width of the lcd display in mm
+* height: height of the lcd display in mm
+* num_modes: size of modes
+* modes: list of valid video modes
+* bpp: bits per pixel for the lcd
+* lcd_type: lcd type
+*/
+
+struct jz4740_fb_platform_data {
+        unsigned int width;
+        unsigned int height;
+
+        size_t num_modes;
+        struct fb_videomode *modes;
+
+        unsigned int bpp;
+        enum jz4740_fb_lcd_type lcd_type;
+
+        struct {
+                uint32_t spl;
+                uint32_t cls;
+                uint32_t ps;
+                uint32_t rev;
+        } special_tft_config;
+
+        unsigned pixclk_falling_edge:1;
+        unsigned date_enable_active_low:1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
new file mode 100644
index 000000000000..8543f432b4b3
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
@@ -0,0 +1,15 @@
+#ifndef __LINUX_MMC_JZ4740_MMC
+#define __LINUX_MMC_JZ4740_MMC
+
+struct jz4740_mmc_platform_data {
+        int gpio_power;
+        int gpio_card_detect;
+        int gpio_read_only;
+        unsigned card_detect_active_low:1;
+        unsigned read_only_active_low:1;
+        unsigned power_active_low:1;
+
+        unsigned data_1bit:1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
new file mode 100644
index 000000000000..bb5b9a4e29c8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC NAND controller driver
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
+#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
+
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+struct jz_nand_platform_data {
+        int                     num_partitions;
+        struct mtd_partition    *partitions;
+
+        struct nand_ecclayout   *ecc_layout;
+
+        unsigned int busy_gpio;
+
+        void (*ident_callback)(struct platform_device *, struct nand_chip *,
+                                struct mtd_partition **, int *num_partitions);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
new file mode 100644
index 000000000000..8987a76e9676
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform device definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+
+#ifndef __JZ4740_PLATFORM_H
+#define __JZ4740_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device jz4740_usb_ohci_device;
+extern struct platform_device jz4740_udc_device;
+extern struct platform_device jz4740_mmc_device;
+extern struct platform_device jz4740_rtc_device;
+extern struct platform_device jz4740_i2c_device;
+extern struct platform_device jz4740_nand_device;
+extern struct platform_device jz4740_framebuffer_device;
+extern struct platform_device jz4740_i2s_device;
+extern struct platform_device jz4740_pcm_device;
+extern struct platform_device jz4740_codec_device;
+extern struct platform_device jz4740_adc_device;
+
+void jz4740_serial_device_register(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
new file mode 100644
index 000000000000..9baa03ce748c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/timer.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_TIMER
+#define __ASM_MACH_JZ4740_TIMER
+
+void jz4740_timer_enable_watchdog(void);
+void jz4740_timer_disable_watchdog(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
new file mode 100644
index 000000000000..3a5bc17e28fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
+#define __ASM_MIPS_MACH_JZ4740_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index fcdbe3a4ce1f..cb6985f24303 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -45,7 +45,6 @@ static inline void prom_init_uart_base(void)
 /* irq operation functions */
 extern void bonito_irqdispatch(void);
 extern void __init bonito_irq_init(void);
-extern void __init set_irq_trigger_mode(void);
 extern void __init mach_init_irq(void);
 extern void mach_irq_dispatch(unsigned int pending);
 extern int mach_i8259_irq(void);
@@ -63,6 +62,14 @@ extern int mach_i8259_irq(void);
 #define LOONGSON_IRQ_BASE       32
 #define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
 
+#include <linux/interrupt.h>
+static inline void do_perfcnt_IRQ(void)
+{
+#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
+        do_IRQ(LOONGSON2_PERFCNT_IRQ);
+#endif
+}
+
 #define LOONGSON_FLASH_BASE     0x1c000000
 #define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
 #define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 58796410bd6e..fc4d766641ce 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,14 +40,6 @@
 #define SMBUS_PSC_BASE          PSC2_BASE_ADDR
 #define I2S_PSC_BASE            PSC3_BASE_ADDR
 
-#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOTH_BANKS
-#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOOT_ONLY
-#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_USER_ONLY
-#endif
-
 /*
  * Timing values as described in databook, * ns value stripped of
  * lower 2 bits.
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
index bcad43a93ebf..c7077a64b9a7 100644
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -20,6 +20,7 @@
 #define _ASM_MACH_POWERTV_ASIC_H
 
 #include <linux/ioport.h>
+#include <linux/platform_device.h>
 #include <asm/mach-powertv/asic_regs.h>
 
 #define DVR_CAPABLE     (1<<0)
@@ -40,19 +41,23 @@ enum family_type {
         FAMILY_8600VZB,
         FAMILY_1500VZE,
         FAMILY_1500VZF,
+        FAMILY_8700,
         FAMILIES
 };
 
 /* Register maps for each ASIC */
 extern const struct register_map calliope_register_map;
 extern const struct register_map cronus_register_map;
+extern const struct register_map gaia_register_map;
 extern const struct register_map zeus_register_map;
 
 extern struct resource dvr_cronus_resources[];
+extern struct resource dvr_gaia_resources[];
 extern struct resource dvr_zeus_resources[];
 extern struct resource non_dvr_calliope_resources[];
 extern struct resource non_dvr_cronus_resources[];
 extern struct resource non_dvr_cronuslite_resources[];
+extern struct resource non_dvr_gaia_resources[];
 extern struct resource non_dvr_vz_calliope_resources[];
 extern struct resource non_dvr_vze_calliope_resources[];
 extern struct resource non_dvr_vzf_calliope_resources[];
@@ -67,16 +72,24 @@ extern int platform_supports_ffs(void);
 extern int platform_supports_pcie(void);
 extern int platform_supports_display(void);
 extern void configure_platform(void);
-extern void platform_configure_usb_ehci(void);
-extern void platform_unconfigure_usb_ehci(void);
-extern void platform_configure_usb_ohci(void);
-extern void platform_unconfigure_usb_ohci(void);
 
 /* Platform Resources */
 #define ASIC_RESOURCE_GET_EXISTS 1
 extern struct resource *asic_resource_get(const char *name);
 extern void platform_release_memory(void *baddr, int size);
 
+/* USB configuration */
+struct usb_hcd;                 /* Forward reference */
+extern void platform_configure_usb_ehci(void);
+extern void platform_unconfigure_usb_ehci(void);
+extern void platform_configure_usb_ohci(void);
+extern void platform_unconfigure_usb_ohci(void);
+
+/* Resource for ASIC registers */
+extern struct resource asic_resource;
+extern int platform_usb_devices_init(struct platform_device **echi_dev,
+        struct platform_device **ohci_dev);
+
 /* Reboot Cause */
 extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
 extern void set_locked_reboot_cause(char code, unsigned int data,
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
index 6f26cb09828e..20348e817b09 100644
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
@@ -64,7 +64,7 @@ REGISTER_MAP_ELEMENT(int_level_0_1)
 REGISTER_MAP_ELEMENT(int_level_0_0)
 REGISTER_MAP_ELEMENT(int_docsis_en)
 REGISTER_MAP_ELEMENT(mips_pll_setup)
-REGISTER_MAP_ELEMENT(usb_fs)
+REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
 REGISTER_MAP_ELEMENT(test_bus)
 REGISTER_MAP_ELEMENT(crt_spare)
 REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
index 1e11236c6dbc..deecb26a077e 100644
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -27,7 +27,8 @@ enum asic_type {
         ASIC_CALLIOPE,
         ASIC_CRONUS,
         ASIC_CRONUSLITE,
-        ASICS
+        ASIC_GAIA,
+        ASICS                   /* Number of supported ASICs */
 };
 
 /* hardcoded values read from Chip Version registers */
@@ -37,6 +38,7 @@ enum asic_type {
 
 #define NAND_FLASH_BASE         0x03000000
 #define CALLIOPE_IO_BASE        0x08000000
+#define GAIA_IO_BASE            0x09000000
 #define CRONUS_IO_BASE          0x09000000
 #define ZEUS_IO_BASE            0x09000000
 
@@ -99,6 +101,7 @@ static inline void register_map_virtualize(struct register_map *map)
 }
 
 extern struct register_map _asic_register_map;
+extern unsigned long asic_phy_base;
 
 /*
  * Macros to interface to registers through their ioremapped address
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index 5b8d5ebeb838..f76029c2406e 100644
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -65,21 +65,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         size_t size)
 {
         if (is_kseg2(addr))
-                return phys_to_bus(virt_to_phys_from_pte(addr));
+                return phys_to_dma(virt_to_phys_from_pte(addr));
         else
-                return phys_to_bus(virt_to_phys(addr));
+                return phys_to_dma(virt_to_phys(addr));
 }
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         struct page *page)
 {
-        return phys_to_bus(page_to_phys(page));
+        return phys_to_dma(page_to_phys(page));
 }
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
-        return bus_to_phys(dma_addr);
+        return dma_to_phys(dma_addr);
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
index e6276d5146e8..076f2eeaa575 100644
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -10,64 +10,101 @@
 #define __ASM_MACH_POWERTV_IOREMAP_H
 
 #include <linux/types.h>
+#include <linux/log2.h>
+#include <linux/compiler.h>
 
-#define LOW_MEM_BOUNDARY_PHYS   0x20000000
-#define LOW_MEM_BOUNDARY_MASK   (~(LOW_MEM_BOUNDARY_PHYS - 1))
+#include <asm/pgtable-bits.h>
+#include <asm/addrspace.h>
+
+/* We're going to mess with bits, so get sizes */
+#define IOR_BPC                 8                       /* Bits per char */
+#define IOR_PHYS_BITS           (IOR_BPC * sizeof(phys_addr_t))
+#define IOR_DMA_BITS            (IOR_BPC * sizeof(dma_addr_t))
 
 /*
- * The bus addresses are different than the physical addresses that
- * the processor sees by an offset. This offset varies by ASIC
- * version. Define a variable to hold the offset and some macros to
- * make the conversion simpler. */
-extern unsigned long phys_to_bus_offset;
-
-#ifdef CONFIG_HIGHMEM
-#define MEM_GAP_PHYS            0x60000000
+ * Define the granularity of physical/DMA mapping in terms of the number
+ * of bits that defines the offset within a grain. These will be the
+ * least significant bits of the address. The rest of a physical or DMA
+ * address will be used to index into an appropriate table to find the
+ * offset to add to the address to yield the corresponding DMA or physical
+ * address, respectively.
+ */
+#define IOR_LSBITS              22                      /* Bits in a grain */
+
 /*
- * TODO: We will use the hard code for conversion between physical and
- * bus until the bootloader releases their device tree to us.
+ * Compute the number of most significant address bits after removing those
+ * used for the offset within a grain and then compute the number of table
+ * entries for the conversion.
  */
-#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
-        ((x) + phys_to_bus_offset) : (x))
-#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
-        ((x) - phys_to_bus_offset) : (x))
-#else
-#define phys_to_bus(x) ((x) + phys_to_bus_offset)
-#define bus_to_phys(x) ((x) - phys_to_bus_offset)
-#endif
+#define IOR_PHYS_MSBITS         (IOR_PHYS_BITS - IOR_LSBITS)
+#define IOR_NUM_PHYS_TO_DMA     ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
+
+#define IOR_DMA_MSBITS          (IOR_DMA_BITS - IOR_LSBITS)
+#define IOR_NUM_DMA_TO_PHYS     ((dma_addr_t) 1 << IOR_DMA_MSBITS)
 
 /*
- * Determine whether the address we are given is for an ASIC device
- * Params:  addr    Address to check
- * Returns: Zero if the address is not for ASIC devices, non-zero
- *      if it is.
+ * Define data structures used as elements in the arrays for the conversion
+ * between physical and DMA addresses. We do some slightly fancy math to
+ * compute the width of the offset element of the conversion tables so
+ * that we can have the smallest conversion tables. Next, round up the
+ * sizes to the next higher power of two, i.e. the offset element will have
+ * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
+ * bits.  Finally, we compute a shift value that puts the most significant
+ * bits of the offset into the most significant bits of the offset element.
+ * This makes it more efficient on processors without barrel shifters and
+ * easier to see the values if the conversion table is dumped in binary.
  */
-static inline int asic_is_device_addr(phys_t addr)
+#define _IOR_OFFSET_WIDTH(n)    (1 << order_base_2(n))
+#define IOR_OFFSET_WIDTH(n) \
+        (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
+
+#define IOR_PHYS_OFFSET_BITS    IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
+#define IOR_PHYS_SHIFT          (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
+
+#define IOR_DMA_OFFSET_BITS     IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
+#define IOR_DMA_SHIFT           (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
+
+struct ior_phys_to_dma {
+        dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
+                __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
+};
+
+struct ior_dma_to_phys {
+        dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
+                __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
+};
+
+extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
+extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
+
+static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
 {
-        return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
+        return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
 }
 
-/*
- * Determine whether the address we are given is external RAM mappable
- * into KSEG1.
- * Params:  addr    Address to check
- * Returns: Zero if the address is not for external RAM and
- */
-static inline int asic_is_lowmem_ram_addr(phys_t addr)
+static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
 {
-        /*
-         * The RAM always starts at the following address in the processor's
-         * physical address space
-         */
-        static const phys_t phys_ram_base = 0x10000000;
-        phys_t bus_ram_base;
+        return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
+}
 
-        bus_ram_base = phys_to_bus_offset + phys_ram_base;
+/* These are not portable and should not be used in drivers. Drivers should
+ * be using ioremap() and friends to map physical addreses to virtual
+ * addresses and dma_map*() and friends to map virtual addresses into DMA
+ * addresses and back.
+ */
+static inline dma_addr_t phys_to_dma(phys_addr_t phys)
+{
+        return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
+}
 
-        return addr >= bus_ram_base &&
-                addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
+static inline phys_addr_t dma_to_phys(dma_addr_t dma)
+{
+        return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
 }
 
+extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
+        dma_addr_t size);
+
 /*
  * Allow physical addresses to be fixed up to help peripherals located
  * outside the low 32-bit range -- generic pass-through version.
@@ -77,10 +114,50 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
         return phys_addr;
 }
 
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+/*
+ * Handle the special case of addresses the area aliased into the first
+ * 512 MiB of the processor's physical address space. These turn into either
+ * kseg0 or kseg1 addresses, depending on flags.
+ */
+static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
         unsigned long flags)
 {
-        return NULL;
+        phys_addr_t start_offset;
+        void __iomem *result = NULL;
+
+        /* Start by checking to see whether this is an aliased address */
+        start_offset = _dma_to_phys_offset_raw(start);
+
+        /*
+         * If:
+         * o    the memory is aliased into the first 512 MiB, and
+         * o    the start and end are in the same RAM bank, and
+         * o    we don't have a zero size or wrap around, and
+         * o    we are supposed to create an uncached mapping,
+         *      handle this is a kseg0 or kseg1 address
+         */
+        if (start_offset != 0) {
+                phys_addr_t last;
+                dma_addr_t dma_to_phys_offset;
+
+                last = start + size - 1;
+                dma_to_phys_offset =
+                        _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
+
+                if (dma_to_phys_offset == start_offset &&
+                        size != 0 && start <= last) {
+                        phys_t adjusted_start;
+                        adjusted_start = start + start_offset;
+                        if (flags == _CACHE_UNCACHED)
+                                result = (void __iomem *) (unsigned long)
+                                        CKSEG1ADDR(adjusted_start);
+                        else
+                                result = (void __iomem *) (unsigned long)
+                                        CKSEG0ADDR(adjusted_start);
+                }
+        }
+
+        return result;
 }
 
 static inline int plat_iounmap(const volatile void __iomem *addr)
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
index 913ff196259d..b74caf65482b 100644
--- a/arch/mips/include/asm/mach-tx49xx/kmalloc.h
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_MACH_TX49XX_KMALLOC_H
 #define __ASM_MACH_TX49XX_KMALLOC_H
 
-/*
- * All happy, no need to define ARCH_KMALLOC_MINALIGN
- */
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
 
 #endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c6e3c93ce7c7..335474c155f6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -408,6 +408,7 @@
 #define  STATUSB_IP15           7
 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 #define ST0_CH                  0x00040000
+#define ST0_NMI                 0x00080000
 #define ST0_SR                  0x00100000
 #define ST0_TS                  0x00200000
 #define ST0_BEV                 0x00400000
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index ca6214b5ccb9..917a6c413b1a 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -50,6 +50,7 @@ extern void octeon_crypto_disable(struct octeon_cop2_state *state,
 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
 
 extern void octeon_init_cvmcount(void);
+extern void octeon_setup_delays(void);
 
 #define OCTEON_ARGV_MAX_ARGS    64
 #define OCTOEN_SERIAL_LEN       20
@@ -253,4 +254,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
 
 extern struct cvmx_bootinfo *octeon_bootinfo;
 
+extern uint64_t octeon_bootloader_entry_addr;
+
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index 6ac5d3e3398e..ece78043acf6 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -15,6 +15,19 @@
 #define PCI_CONFIG_SPACE_DELAY 10000
 
 /*
+ * The physical memory base mapped by BAR1.  256MB at the end of the
+ * first 4GB.
+ */
+#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
+#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
+
+/*
+ * The RC base of BAR1.  gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
+ * place BAR1 so it is the same for both.
+ */
+#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
+
+/*
  * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
  * call the Octeon specific version pointed to by this variable. This
  * function needs to change for PCI or PCIe based hosts.
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 3beea1479b43..576397c69920 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -140,6 +140,11 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+/* MSI arch hook for OCTEON */
+#define arch_setup_msi_irqs arch_setup_msi_irqs
+#endif
+
 extern int pci_probe_only;
 
 extern char * (*pcibios_plat_setup)(char *str);
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 54ef1a96d7ce..786d82daf8d6 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -124,10 +124,6 @@ extern void prom_meminit(void);
 extern void prom_fixup_mem_map(unsigned long start_mem,
                                unsigned long end_mem);
 
-#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
-extern bool get_ramroot(void **start, unsigned long *size);
-#endif
-
 extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
 extern unsigned long get_deviceid(void);
 extern char identify_enet(unsigned long interface_num);
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 5d33b727acf5..0d629bb93cbe 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -34,6 +34,11 @@ extern void (*cpu_wait)(void);
 extern unsigned int vced_count, vcei_count;
 
 /*
+ * MIPS does have an arch_pick_mmap_layout()
+ */
+#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
+
+/*
  * A special page (the vdso) is mapped into all processes at the very
  * top of the virtual memory space.
  */
@@ -52,6 +57,9 @@ extern unsigned int vced_count, vcei_count;
  * space during mmap's.
  */
 #define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+
+#define TASK_IS_32BIT_ADDR 1
+
 #endif
 
 #ifdef CONFIG_64BIT
@@ -77,6 +85,9 @@ extern unsigned int vced_count, vcei_count;
                 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
 #define TASK_SIZE_OF(tsk)                                               \
         (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+
+#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
+
 #endif
 
 #ifdef __KERNEL__
@@ -218,7 +229,6 @@ struct thread_struct {
         unsigned long cp0_badvaddr;     /* Last user fault */
         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
         unsigned long error_code;
-        unsigned long trap_no;
         unsigned long irix_trampoline;  /* Wheee... */
         unsigned long irix_oldctx;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
@@ -290,7 +300,6 @@ struct thread_struct {
         .cp0_badvaddr           = 0,                            \
         .cp0_baduaddr           = 0,                            \
         .error_code             = 0,                            \
-        .trap_no                = 0,                            \
         .irix_trampoline        = 0,                            \
         .irix_oldctx            = 0,                            \
         /*                                                      \
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index cdc6a46efd98..9f1b8dba2c81 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -137,6 +137,7 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
  */
 #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
 
+#define regs_return_value(_regs) ((_regs)->regs[2])
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 #define profile_pc(regs) instruction_pointer(regs)
 
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
index ac4ea85c3a5c..dc81114d4742 100644
--- a/arch/mips/include/asm/sn/agent.h
+++ b/arch/mips/include/asm/sn/agent.h
@@ -11,7 +11,6 @@
 #ifndef _ASM_SGI_SN_AGENT_H
 #define _ASM_SGI_SN_AGENT_H
 
-#include <linux/topology.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/arch.h>
 
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 697e40c06497..892062d6d748 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -10,44 +10,55 @@
 
 #include <linux/types.h>
 
+#ifdef CONFIG_EXPORT_UASM
+#include <linux/module.h>
+#define __uasminit
+#define __uasminitdata
+#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
+#else
+#define __uasminit __cpuinit
+#define __uasminitdata __cpuinitdata
+#define UASM_EXPORT_SYMBOL(sym)
+#endif
+
 #define Ip_u1u2u3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u2u1u3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u3u1u2(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u1u2s3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2s3u1(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
 
 #define Ip_u2u1s3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2u1msbu3(op)                                                \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c,   \
            unsigned int d)
 
 #define Ip_u1u2(op)                                                     \
-void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
+void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
 
 #define Ip_u1s2(op)                                                     \
-void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b)
+void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
 
-#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a)
+#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a)
 
-#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf)
+#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf)
 
 Ip_u2u1s3(_addiu);
 Ip_u3u1u2(_addu);
@@ -71,6 +82,7 @@ Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
 Ip_u2u1u3(_drotr);
+Ip_u2u1u3(_drotr32);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u1(_j);
@@ -111,7 +123,7 @@ struct uasm_label {
         int lab;
 };
 
-void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
+void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
 #ifdef CONFIG_64BIT
 int uasm_in_compat_space_p(long addr);
 #endif
@@ -121,7 +133,7 @@ void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
 void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
 
 #define UASM_L_LA(lb)                                                   \
-static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
+static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 {                                                                       \
         uasm_build_label(lab, addr, label##lb);                         \
 }
@@ -176,6 +188,15 @@ static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
                 uasm_i_dsrl32(p, a1, a2, a3 - 32);
 }
 
+static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
+                                     unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_drotr(p, a1, a2, a3);
+        else
+                uasm_i_drotr32(p, a1, a2, a3 - 32);
+}
+
 static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
                                     unsigned int a2, unsigned int a3)
 {
@@ -213,3 +234,7 @@ void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
+void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile
index 5aee0c266d18..dd9d99bfcf7a 100644
--- a/arch/mips/jazz/Makefile
+++ b/arch/mips/jazz/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y           := irq.o jazzdma.o reset.o setup.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/jazz/Platform b/arch/mips/jazz/Platform
new file mode 100644
index 000000000000..3373788acca1
--- /dev/null
+++ b/arch/mips/jazz/Platform
@@ -0,0 +1,6 @@
+#
+# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
+#
+platform-$(CONFIG_MACH_JAZZ)    += jazz/
+cflags-$(CONFIG_MACH_JAZZ)      += -I$(srctree)/arch/mips/include/asm/mach-jazz
+load-$(CONFIG_MACH_JAZZ)        += 0xffffffff80080000
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
new file mode 100644
index 000000000000..3e7141f0746c
--- /dev/null
+++ b/arch/mips/jz4740/Kconfig
@@ -0,0 +1,12 @@
+choice
+        prompt "Machine type"
+        depends on MACH_JZ4740
+        default JZ4740_QI_LB60
+
+config JZ4740_QI_LB60
+        bool "Qi Hardware Ben NanoNote"
+
+endchoice
+
+config HAVE_PWM
+        bool
diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
new file mode 100644
index 000000000000..a604eaeb6c08
--- /dev/null
+++ b/arch/mips/jz4740/Makefile
@@ -0,0 +1,20 @@
+#
+# Makefile for the Ingenic JZ4740.
+#
+
+# Object file lists.
+
+obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
+        gpio.o clock.o platform.o timer.o pwm.o serial.o
+
+obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
+
+# board specific support
+
+obj-$(CONFIG_JZ4740_QI_LB60)    += board-qi_lb60.o
+
+# PM support
+
+obj-$(CONFIG_PM) += pm.o
+
+EXTRA_CFLAGS += -Werror -Wall
diff --git a/arch/mips/jz4740/Platform b/arch/mips/jz4740/Platform
new file mode 100644
index 000000000000..6a97230e3d05
--- /dev/null
+++ b/arch/mips/jz4740/Platform
@@ -0,0 +1,3 @@
+core-$(CONFIG_MACH_JZ4740)      += arch/mips/jz4740/
+cflags-$(CONFIG_MACH_JZ4740)    += -I$(srctree)/arch/mips/include/asm/mach-jz4740
+load-$(CONFIG_MACH_JZ4740)      += 0xffffffff80010000
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
new file mode 100644
index 000000000000..5742bb4d78f4
--- /dev/null
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -0,0 +1,471 @@
+/*
+ * linux/arch/mips/jz4740/board-qi_lb60.c
+ *
+ * QI_LB60 board support
+ *
+ * Copyright (c) 2009 Qi Hardware inc.,
+ * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
+ * Copyright 2010, Lars-Petrer Clausen <lars@metafoo.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/power_supply.h>
+#include <linux/power/jz4740-battery.h>
+
+#include <asm/mach-jz4740/jz4740_fb.h>
+#include <asm/mach-jz4740/jz4740_mmc.h>
+#include <asm/mach-jz4740/jz4740_nand.h>
+
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+
+#include <linux/leds_pwm.h>
+
+#include <asm/mach-jz4740/platform.h>
+
+#include "clock.h"
+
+static bool is_avt2;
+
+/* GPIOs */
+#define QI_LB60_GPIO_SD_CD              JZ_GPIO_PORTD(0)
+#define QI_LB60_GPIO_SD_VCC_EN_N        JZ_GPIO_PORTD(2)
+
+#define QI_LB60_GPIO_KEYOUT(x)          (JZ_GPIO_PORTC(10) + (x))
+#define QI_LB60_GPIO_KEYIN(x)           (JZ_GPIO_PORTD(18) + (x))
+#define QI_LB60_GPIO_KEYIN8             JZ_GPIO_PORTD(26)
+
+/* NAND */
+static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
+/*      .eccbytes = 36,
+        .eccpos = {
+                6,  7,  8,  9,  10, 11, 12, 13,
+                14, 15, 16, 17, 18, 19, 20, 21,
+                22, 23, 24, 25, 26, 27, 28, 29,
+                30, 31, 32, 33, 34, 35, 36, 37,
+                38, 39, 40, 41
+        },*/
+        .oobfree = {
+                { .offset = 2, .length = 4 },
+                { .offset = 42, .length = 22 }
+        },
+};
+
+/* Early prototypes of the QI LB60 had only 1GB of NAND.
+ * In order to support these devices aswell the partition and ecc layout is
+ * initalized depending on the NAND size */
+static struct mtd_partition qi_lb60_partitions_1gb[] = {
+        {
+                .name = "NAND BOOT partition",
+                .offset = 0 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND KERNEL partition",
+                .offset = 4 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND ROOTFS partition",
+                .offset = 8 * 0x100000,
+                .size = (504 + 512) * 0x100000,
+        },
+};
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+/*      .eccbytes = 72,
+        .eccpos = {
+                12, 13, 14, 15, 16, 17, 18, 19,
+                20, 21, 22, 23, 24, 25, 26, 27,
+                28, 29, 30, 31, 32, 33, 34, 35,
+                36, 37, 38, 39, 40, 41, 42, 43,
+                44, 45, 46, 47, 48, 49, 50, 51,
+                52, 53, 54, 55, 56, 57, 58, 59,
+                60, 61, 62, 63, 64, 65, 66, 67,
+                68, 69, 70, 71, 72, 73, 74, 75,
+                76, 77, 78, 79, 80, 81, 82, 83
+        },*/
+        .oobfree = {
+                { .offset = 2, .length = 10 },
+                { .offset = 84, .length = 44 },
+        },
+};
+
+static struct mtd_partition qi_lb60_partitions_2gb[] = {
+        {
+                .name = "NAND BOOT partition",
+                .offset = 0 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND KERNEL partition",
+                .offset = 4 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND ROOTFS partition",
+                .offset = 8 * 0x100000,
+                .size = (504 + 512 + 1024) * 0x100000,
+        },
+};
+
+static void qi_lb60_nand_ident(struct platform_device *pdev,
+                struct nand_chip *chip, struct mtd_partition **partitions,
+                int *num_partitions)
+{
+        if (chip->page_shift == 12) {
+                chip->ecc.layout = &qi_lb60_ecclayout_2gb;
+                *partitions = qi_lb60_partitions_2gb;
+                *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
+        } else {
+                chip->ecc.layout = &qi_lb60_ecclayout_1gb;
+                *partitions = qi_lb60_partitions_1gb;
+                *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
+        }
+}
+
+static struct jz_nand_platform_data qi_lb60_nand_pdata = {
+        .ident_callback = qi_lb60_nand_ident,
+        .busy_gpio = 94,
+};
+
+/* Keyboard*/
+
+#define KEY_QI_QI       KEY_F13
+#define KEY_QI_UPRED    KEY_RIGHTALT
+#define KEY_QI_VOLUP    KEY_VOLUMEUP
+#define KEY_QI_VOLDOWN  KEY_VOLUMEDOWN
+#define KEY_QI_FN       KEY_LEFTCTRL
+
+static const uint32_t qi_lb60_keymap[] = {
+        KEY(0, 0, KEY_F1),      /* S2 */
+        KEY(0, 1, KEY_F2),      /* S3 */
+        KEY(0, 2, KEY_F3),      /* S4 */
+        KEY(0, 3, KEY_F4),      /* S5 */
+        KEY(0, 4, KEY_F5),      /* S6 */
+        KEY(0, 5, KEY_F6),      /* S7 */
+        KEY(0, 6, KEY_F7),      /* S8 */
+
+        KEY(1, 0, KEY_Q),       /* S10 */
+        KEY(1, 1, KEY_W),       /* S11 */
+        KEY(1, 2, KEY_E),       /* S12 */
+        KEY(1, 3, KEY_R),       /* S13 */
+        KEY(1, 4, KEY_T),       /* S14 */
+        KEY(1, 5, KEY_Y),       /* S15 */
+        KEY(1, 6, KEY_U),       /* S16 */
+        KEY(1, 7, KEY_I),       /* S17 */
+        KEY(2, 0, KEY_A),       /* S18 */
+        KEY(2, 1, KEY_S),       /* S19 */
+        KEY(2, 2, KEY_D),       /* S20 */
+        KEY(2, 3, KEY_F),       /* S21 */
+        KEY(2, 4, KEY_G),       /* S22 */
+        KEY(2, 5, KEY_H),       /* S23 */
+        KEY(2, 6, KEY_J),       /* S24 */
+        KEY(2, 7, KEY_K),       /* S25 */
+        KEY(3, 0, KEY_ESC),     /* S26 */
+        KEY(3, 1, KEY_Z),       /* S27 */
+        KEY(3, 2, KEY_X),       /* S28 */
+        KEY(3, 3, KEY_C),       /* S29 */
+        KEY(3, 4, KEY_V),       /* S30 */
+        KEY(3, 5, KEY_B),       /* S31 */
+        KEY(3, 6, KEY_N),       /* S32 */
+        KEY(3, 7, KEY_M),       /* S33 */
+        KEY(4, 0, KEY_TAB),     /* S34 */
+        KEY(4, 1, KEY_CAPSLOCK),        /* S35 */
+        KEY(4, 2, KEY_BACKSLASH),       /* S36 */
+        KEY(4, 3, KEY_APOSTROPHE),      /* S37 */
+        KEY(4, 4, KEY_COMMA),   /* S38 */
+        KEY(4, 5, KEY_DOT),     /* S39 */
+        KEY(4, 6, KEY_SLASH),   /* S40 */
+        KEY(4, 7, KEY_UP),      /* S41 */
+        KEY(5, 0, KEY_O),       /* S42 */
+        KEY(5, 1, KEY_L),       /* S43 */
+        KEY(5, 2, KEY_EQUAL),   /* S44 */
+        KEY(5, 3, KEY_QI_UPRED),        /* S45 */
+        KEY(5, 4, KEY_SPACE),   /* S46 */
+        KEY(5, 5, KEY_QI_QI),   /* S47 */
+        KEY(5, 6, KEY_RIGHTCTRL),       /* S48 */
+        KEY(5, 7, KEY_LEFT),    /* S49 */
+        KEY(6, 0, KEY_F8),      /* S50 */
+        KEY(6, 1, KEY_P),       /* S51 */
+        KEY(6, 2, KEY_BACKSPACE),/* S52 */
+        KEY(6, 3, KEY_ENTER),   /* S53 */
+        KEY(6, 4, KEY_QI_VOLUP),        /* S54 */
+        KEY(6, 5, KEY_QI_VOLDOWN),      /* S55 */
+        KEY(6, 6, KEY_DOWN),    /* S56 */
+        KEY(6, 7, KEY_RIGHT),   /* S57 */
+
+        KEY(7, 0, KEY_LEFTSHIFT),       /* S58 */
+        KEY(7, 1, KEY_LEFTALT), /* S59 */
+        KEY(7, 2, KEY_QI_FN),   /* S60 */
+};
+
+static const struct matrix_keymap_data qi_lb60_keymap_data = {
+        .keymap         = qi_lb60_keymap,
+        .keymap_size    = ARRAY_SIZE(qi_lb60_keymap),
+};
+
+static const unsigned int qi_lb60_keypad_cols[] = {
+        QI_LB60_GPIO_KEYOUT(0),
+        QI_LB60_GPIO_KEYOUT(1),
+        QI_LB60_GPIO_KEYOUT(2),
+        QI_LB60_GPIO_KEYOUT(3),
+        QI_LB60_GPIO_KEYOUT(4),
+        QI_LB60_GPIO_KEYOUT(5),
+        QI_LB60_GPIO_KEYOUT(6),
+        QI_LB60_GPIO_KEYOUT(7),
+};
+
+static const unsigned int qi_lb60_keypad_rows[] = {
+        QI_LB60_GPIO_KEYIN(0),
+        QI_LB60_GPIO_KEYIN(1),
+        QI_LB60_GPIO_KEYIN(2),
+        QI_LB60_GPIO_KEYIN(3),
+        QI_LB60_GPIO_KEYIN(4),
+        QI_LB60_GPIO_KEYIN(5),
+        QI_LB60_GPIO_KEYIN(7),
+        QI_LB60_GPIO_KEYIN8,
+};
+
+static struct matrix_keypad_platform_data qi_lb60_pdata = {
+        .keymap_data = &qi_lb60_keymap_data,
+        .col_gpios      = qi_lb60_keypad_cols,
+        .row_gpios      = qi_lb60_keypad_rows,
+        .num_col_gpios  = ARRAY_SIZE(qi_lb60_keypad_cols),
+        .num_row_gpios  = ARRAY_SIZE(qi_lb60_keypad_rows),
+        .col_scan_delay_us      = 10,
+        .debounce_ms            = 10,
+        .wakeup                 = 1,
+        .active_low             = 1,
+};
+
+static struct platform_device qi_lb60_keypad = {
+        .name           = "matrix-keypad",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &qi_lb60_pdata,
+        },
+};
+
+/* Display */
+static struct fb_videomode qi_lb60_video_modes[] = {
+        {
+                .name = "320x240",
+                .xres = 320,
+                .yres = 240,
+                .refresh = 30,
+                .left_margin = 140,
+                .right_margin = 273,
+                .upper_margin = 20,
+                .lower_margin = 2,
+                .hsync_len = 1,
+                .vsync_len = 1,
+                .sync = 0,
+                .vmode = FB_VMODE_NONINTERLACED,
+        },
+};
+
+static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
+        .width          = 60,
+        .height         = 45,
+        .num_modes      = ARRAY_SIZE(qi_lb60_video_modes),
+        .modes          = qi_lb60_video_modes,
+        .bpp            = 24,
+        .lcd_type       = JZ_LCD_TYPE_8BIT_SERIAL,
+        .pixclk_falling_edge = 1,
+};
+
+struct spi_gpio_platform_data spigpio_platform_data = {
+        .sck = JZ_GPIO_PORTC(23),
+        .mosi = JZ_GPIO_PORTC(22),
+        .miso = -1,
+        .num_chipselect = 1,
+};
+
+static struct platform_device spigpio_device = {
+        .name = "spi_gpio",
+        .id   = 1,
+        .dev = {
+                .platform_data = &spigpio_platform_data,
+        },
+};
+
+static struct spi_board_info qi_lb60_spi_board_info[] = {
+        {
+                .modalias = "ili8960",
+                .controller_data = (void *)JZ_GPIO_PORTC(21),
+                .chip_select = 0,
+                .bus_num = 1,
+                .max_speed_hz = 30 * 1000,
+                .mode = SPI_3WIRE,
+        },
+};
+
+/* Battery */
+static struct jz_battery_platform_data qi_lb60_battery_pdata = {
+        .gpio_charge =  JZ_GPIO_PORTC(27),
+        .gpio_charge_active_low = 1,
+        .info = {
+                .name = "battery",
+                .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
+                .voltage_max_design = 4200000,
+                .voltage_min_design = 3600000,
+        },
+};
+
+/* GPIO Key: power */
+static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
+        [0] = {
+                .code           = KEY_POWER,
+                .gpio           = JZ_GPIO_PORTD(29),
+                .active_low     = 1,
+                .desc           = "Power",
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
+        .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
+        .buttons = qi_lb60_gpio_keys_buttons,
+};
+
+static struct platform_device qi_lb60_gpio_keys = {
+        .name = "gpio-keys",
+        .id =   -1,
+        .dev = {
+                .platform_data = &qi_lb60_gpio_keys_data,
+        }
+};
+
+static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
+        .gpio_card_detect       = QI_LB60_GPIO_SD_CD,
+        .gpio_read_only         = -1,
+        .gpio_power             = QI_LB60_GPIO_SD_VCC_EN_N,
+        .power_active_low       = 1,
+};
+
+/* OHCI */
+static struct regulator_consumer_supply avt2_usb_regulator_consumer =
+        REGULATOR_SUPPLY("vbus", "jz4740-ohci");
+
+static struct regulator_init_data avt2_usb_regulator_init_data = {
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &avt2_usb_regulator_consumer,
+        .constraints = {
+                .name = "USB power",
+                .min_uV = 5000000,
+                .max_uV = 5000000,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct fixed_voltage_config avt2_usb_regulator_data = {
+        .supply_name = "USB power",
+        .microvolts = 5000000,
+        .gpio = JZ_GPIO_PORTB(17),
+        .init_data = &avt2_usb_regulator_init_data,
+};
+
+static struct platform_device avt2_usb_regulator_device = {
+        .name = "reg-fixed-voltage",
+        .id = -1,
+        .dev = {
+                .platform_data = &avt2_usb_regulator_data,
+        }
+};
+
+/* beeper */
+static struct platform_device qi_lb60_pwm_beeper = {
+        .name = "pwm-beeper",
+        .id = -1,
+        .dev = {
+                .platform_data = (void *)4,
+        },
+};
+
+static struct platform_device *jz_platform_devices[] __initdata = {
+        &jz4740_udc_device,
+        &jz4740_mmc_device,
+        &jz4740_nand_device,
+        &qi_lb60_keypad,
+        &spigpio_device,
+        &jz4740_framebuffer_device,
+        &jz4740_pcm_device,
+        &jz4740_i2s_device,
+        &jz4740_codec_device,
+        &jz4740_rtc_device,
+        &jz4740_adc_device,
+        &qi_lb60_gpio_keys,
+        &qi_lb60_pwm_beeper,
+};
+
+static void __init board_gpio_setup(void)
+{
+        /* We only need to enable/disable pullup here for pins used in generic
+         * drivers. Everything else is done by the drivers themselfs. */
+        jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
+        jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
+}
+
+static int __init qi_lb60_init_platform_devices(void)
+{
+        jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
+        jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
+        jz4740_adc_device.dev.platform_data = &qi_lb60_battery_pdata;
+        jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;
+
+        jz4740_serial_device_register();
+
+        spi_register_board_info(qi_lb60_spi_board_info,
+                                ARRAY_SIZE(qi_lb60_spi_board_info));
+
+        if (is_avt2) {
+                platform_device_register(&avt2_usb_regulator_device);
+                platform_device_register(&jz4740_usb_ohci_device);
+        }
+
+        return platform_add_devices(jz_platform_devices,
+                                        ARRAY_SIZE(jz_platform_devices));
+
+}
+
+struct jz4740_clock_board_data jz4740_clock_bdata = {
+        .ext_rate = 12000000,
+        .rtc_rate = 32768,
+};
+
+static __init int board_avt2(char *str)
+{
+        qi_lb60_mmc_pdata.card_detect_active_low = 1;
+        is_avt2 = true;
+
+        return 1;
+}
+__setup("avt2", board_avt2);
+
+static int __init qi_lb60_board_setup(void)
+{
+        printk(KERN_INFO "Qi Hardware JZ4740 QI %s setup\n",
+                is_avt2 ? "AVT2" : "LB60");
+
+        board_gpio_setup();
+
+        if (qi_lb60_init_platform_devices())
+                panic("Failed to initalize platform devices\n");
+
+        return 0;
+}
+arch_initcall(qi_lb60_board_setup);
diff --git a/arch/mips/jz4740/clock-debugfs.c b/arch/mips/jz4740/clock-debugfs.c
new file mode 100644
index 000000000000..330a0f2bf17b
--- /dev/null
+++ b/arch/mips/jz4740/clock-debugfs.c
@@ -0,0 +1,109 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC clock support debugfs entries
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#include <asm/mach-jz4740/clock.h>
+#include "clock.h"
+
+static struct dentry *jz4740_clock_debugfs;
+
+static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value)
+{
+        struct clk *clk = data;
+        *value = clk_is_enabled(clk);
+
+        return 0;
+}
+
+static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value)
+{
+        struct clk *clk = data;
+
+        if (value)
+                return clk_enable(clk);
+        else
+                clk_disable(clk);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled,
+        jz4740_clock_debugfs_show_enabled,
+        jz4740_clock_debugfs_set_enabled,
+        "%llu\n");
+
+static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value)
+{
+        struct clk *clk = data;
+        *value = clk_get_rate(clk);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate,
+        jz4740_clock_debugfs_show_rate,
+        NULL,
+        "%llu\n");
+
+void jz4740_clock_debugfs_add_clk(struct clk *clk)
+{
+        if (!jz4740_clock_debugfs)
+                return;
+
+        clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs);
+        debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
+                                &jz4740_clock_debugfs_ops_rate);
+        debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
+                                &jz4740_clock_debugfs_ops_enabled);
+
+        if (clk->parent) {
+                char parent_path[100];
+                snprintf(parent_path, 100, "../%s", clk->parent->name);
+                clk->debugfs_parent_entry = debugfs_create_symlink("parent",
+                                                clk->debugfs_entry,
+                                                parent_path);
+        }
+}
+
+/* TODO: Locking */
+void jz4740_clock_debugfs_update_parent(struct clk *clk)
+{
+        if (clk->debugfs_parent_entry)
+                debugfs_remove(clk->debugfs_parent_entry);
+
+        if (clk->parent) {
+                char parent_path[100];
+                snprintf(parent_path, 100, "../%s", clk->parent->name);
+                clk->debugfs_parent_entry = debugfs_create_symlink("parent",
+                                                clk->debugfs_entry,
+                                                parent_path);
+        } else {
+                clk->debugfs_parent_entry = NULL;
+        }
+}
+
+void jz4740_clock_debugfs_init(void)
+{
+        jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL);
+        if (IS_ERR(jz4740_clock_debugfs))
+                jz4740_clock_debugfs = NULL;
+}
diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c
new file mode 100644
index 000000000000..118a8a5562dd
--- /dev/null
+++ b/arch/mips/jz4740/clock.c
@@ -0,0 +1,924 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC clock support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+
+#include <asm/mach-jz4740/clock.h>
+#include <asm/mach-jz4740/base.h>
+
+#include "clock.h"
+
+#define JZ_REG_CLOCK_CTRL       0x00
+#define JZ_REG_CLOCK_LOW_POWER  0x04
+#define JZ_REG_CLOCK_PLL        0x10
+#define JZ_REG_CLOCK_GATE       0x20
+#define JZ_REG_CLOCK_SLEEP_CTRL 0x24
+#define JZ_REG_CLOCK_I2S        0x60
+#define JZ_REG_CLOCK_LCD        0x64
+#define JZ_REG_CLOCK_MMC        0x68
+#define JZ_REG_CLOCK_UHC        0x6C
+#define JZ_REG_CLOCK_SPI        0x74
+
+#define JZ_CLOCK_CTRL_I2S_SRC_PLL       BIT(31)
+#define JZ_CLOCK_CTRL_KO_ENABLE         BIT(30)
+#define JZ_CLOCK_CTRL_UDC_SRC_PLL       BIT(29)
+#define JZ_CLOCK_CTRL_UDIV_MASK         0x1f800000
+#define JZ_CLOCK_CTRL_CHANGE_ENABLE     BIT(22)
+#define JZ_CLOCK_CTRL_PLL_HALF          BIT(21)
+#define JZ_CLOCK_CTRL_LDIV_MASK         0x001f0000
+#define JZ_CLOCK_CTRL_UDIV_OFFSET       23
+#define JZ_CLOCK_CTRL_LDIV_OFFSET       16
+#define JZ_CLOCK_CTRL_MDIV_OFFSET       12
+#define JZ_CLOCK_CTRL_PDIV_OFFSET        8
+#define JZ_CLOCK_CTRL_HDIV_OFFSET        4
+#define JZ_CLOCK_CTRL_CDIV_OFFSET        0
+
+#define JZ_CLOCK_GATE_UART0     BIT(0)
+#define JZ_CLOCK_GATE_TCU       BIT(1)
+#define JZ_CLOCK_GATE_RTC       BIT(2)
+#define JZ_CLOCK_GATE_I2C       BIT(3)
+#define JZ_CLOCK_GATE_SPI       BIT(4)
+#define JZ_CLOCK_GATE_AIC       BIT(5)
+#define JZ_CLOCK_GATE_I2S       BIT(6)
+#define JZ_CLOCK_GATE_MMC       BIT(7)
+#define JZ_CLOCK_GATE_ADC       BIT(8)
+#define JZ_CLOCK_GATE_CIM       BIT(9)
+#define JZ_CLOCK_GATE_LCD       BIT(10)
+#define JZ_CLOCK_GATE_UDC       BIT(11)
+#define JZ_CLOCK_GATE_DMAC      BIT(12)
+#define JZ_CLOCK_GATE_IPU       BIT(13)
+#define JZ_CLOCK_GATE_UHC       BIT(14)
+#define JZ_CLOCK_GATE_UART1     BIT(15)
+
+#define JZ_CLOCK_I2S_DIV_MASK           0x01ff
+
+#define JZ_CLOCK_LCD_DIV_MASK           0x01ff
+
+#define JZ_CLOCK_MMC_DIV_MASK           0x001f
+
+#define JZ_CLOCK_UHC_DIV_MASK           0x000f
+
+#define JZ_CLOCK_SPI_SRC_PLL            BIT(31)
+#define JZ_CLOCK_SPI_DIV_MASK           0x000f
+
+#define JZ_CLOCK_PLL_M_MASK             0x01ff
+#define JZ_CLOCK_PLL_N_MASK             0x001f
+#define JZ_CLOCK_PLL_OD_MASK            0x0003
+#define JZ_CLOCK_PLL_STABLE             BIT(10)
+#define JZ_CLOCK_PLL_BYPASS             BIT(9)
+#define JZ_CLOCK_PLL_ENABLED            BIT(8)
+#define JZ_CLOCK_PLL_STABLIZE_MASK      0x000f
+#define JZ_CLOCK_PLL_M_OFFSET           23
+#define JZ_CLOCK_PLL_N_OFFSET           18
+#define JZ_CLOCK_PLL_OD_OFFSET          16
+
+#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
+#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
+
+#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
+#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
+
+static void __iomem *jz_clock_base;
+static spinlock_t jz_clock_lock;
+static LIST_HEAD(jz_clocks);
+
+struct main_clk {
+        struct clk clk;
+        uint32_t div_offset;
+};
+
+struct divided_clk {
+        struct clk clk;
+        uint32_t reg;
+        uint32_t mask;
+};
+
+struct static_clk {
+        struct clk clk;
+        unsigned long rate;
+};
+
+static uint32_t jz_clk_reg_read(int reg)
+{
+        return readl(jz_clock_base + reg);
+}
+
+static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
+{
+        uint32_t val2;
+
+        spin_lock(&jz_clock_lock);
+        val2 = readl(jz_clock_base + reg);
+        val2 &= ~mask;
+        val2 |= val;
+        writel(val2, jz_clock_base + reg);
+        spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_set_bits(int reg, uint32_t mask)
+{
+        uint32_t val;
+
+        spin_lock(&jz_clock_lock);
+        val = readl(jz_clock_base + reg);
+        val |= mask;
+        writel(val, jz_clock_base + reg);
+        spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
+{
+        uint32_t val;
+
+        spin_lock(&jz_clock_lock);
+        val = readl(jz_clock_base + reg);
+        val &= ~mask;
+        writel(val, jz_clock_base + reg);
+        spin_unlock(&jz_clock_lock);
+}
+
+static int jz_clk_enable_gating(struct clk *clk)
+{
+        if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+                return -EINVAL;
+
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+        return 0;
+}
+
+static int jz_clk_disable_gating(struct clk *clk)
+{
+        if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+                return -EINVAL;
+
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+        return 0;
+}
+
+static int jz_clk_is_enabled_gating(struct clk *clk)
+{
+        if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+                return 1;
+
+        return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
+}
+
+static unsigned long jz_clk_static_get_rate(struct clk *clk)
+{
+        return ((struct static_clk *)clk)->rate;
+}
+
+static int jz_clk_ko_enable(struct clk *clk)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+        return 0;
+}
+
+static int jz_clk_ko_disable(struct clk *clk)
+{
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+        return 0;
+}
+
+static int jz_clk_ko_is_enabled(struct clk *clk)
+{
+        return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
+}
+
+static const int pllno[] = {1, 2, 2, 4};
+
+static unsigned long jz_clk_pll_get_rate(struct clk *clk)
+{
+        uint32_t val;
+        int m;
+        int n;
+        int od;
+
+        val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
+
+        if (val & JZ_CLOCK_PLL_BYPASS)
+                return clk_get_rate(clk->parent);
+
+        m = ((val >> 23) & 0x1ff) + 2;
+        n = ((val >> 18) & 0x1f) + 2;
+        od = (val >> 16) & 0x3;
+
+        return ((clk_get_rate(clk->parent) / n) * m) / pllno[od];
+}
+
+static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
+{
+        uint32_t reg;
+
+        reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+        if (reg & JZ_CLOCK_CTRL_PLL_HALF)
+                return jz_clk_pll_get_rate(clk->parent);
+        return jz_clk_pll_get_rate(clk->parent) >> 1;
+}
+
+static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+        int div;
+
+        div = parent_rate / rate;
+        if (div > 32)
+                return parent_rate / 32;
+        else if (div < 1)
+                return parent_rate;
+
+        div &= (0x3 << (ffs(div) - 1));
+
+        return parent_rate / div;
+}
+
+static unsigned long jz_clk_main_get_rate(struct clk *clk)
+{
+        struct main_clk *mclk = (struct main_clk *)clk;
+        uint32_t div;
+
+        div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+        div >>= mclk->div_offset;
+        div &= 0xf;
+
+        if (div >= ARRAY_SIZE(jz_clk_main_divs))
+                div = ARRAY_SIZE(jz_clk_main_divs) - 1;
+
+        return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
+}
+
+static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct main_clk *mclk = (struct main_clk *)clk;
+        int i;
+        int div;
+        unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+
+        rate = jz_clk_main_round_rate(clk, rate);
+
+        div = parent_rate / rate;
+
+        i = (ffs(div) - 1) << 1;
+        if (i > 0 && !(div & BIT(i-1)))
+                i -= 1;
+
+        jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
+                                0xf << mclk->div_offset);
+
+        return 0;
+}
+
+static struct clk_ops jz_clk_static_ops = {
+        .get_rate = jz_clk_static_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct static_clk jz_clk_ext = {
+        .clk = {
+                .name = "ext",
+                .gate_bit = JZ4740_CLK_NOT_GATED,
+                .ops = &jz_clk_static_ops,
+        },
+};
+
+static struct clk_ops jz_clk_pll_ops = {
+        .get_rate = jz_clk_pll_get_rate,
+};
+
+static struct clk jz_clk_pll = {
+        .name = "pll",
+        .parent = &jz_clk_ext.clk,
+        .ops = &jz_clk_pll_ops,
+};
+
+static struct clk_ops jz_clk_pll_half_ops = {
+        .get_rate = jz_clk_pll_half_get_rate,
+};
+
+static struct clk jz_clk_pll_half = {
+        .name = "pll half",
+        .parent = &jz_clk_pll,
+        .ops = &jz_clk_pll_half_ops,
+};
+
+static const struct clk_ops jz_clk_main_ops = {
+        .get_rate = jz_clk_main_get_rate,
+        .set_rate = jz_clk_main_set_rate,
+        .round_rate = jz_clk_main_round_rate,
+};
+
+static struct main_clk jz_clk_cpu = {
+        .clk = {
+                .name = "cclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_memory = {
+        .clk = {
+                .name = "mclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_high_speed_peripheral = {
+        .clk = {
+                .name = "hclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
+};
+
+
+static struct main_clk jz_clk_low_speed_peripheral = {
+        .clk = {
+                .name = "pclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
+};
+
+static const struct clk_ops jz_clk_ko_ops = {
+        .enable = jz_clk_ko_enable,
+        .disable = jz_clk_ko_disable,
+        .is_enabled = jz_clk_ko_is_enabled,
+};
+
+static struct clk jz_clk_ko = {
+        .name = "cko",
+        .parent = &jz_clk_memory.clk,
+        .ops = &jz_clk_ko_ops,
+};
+
+static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
+{
+        if (parent == &jz_clk_pll)
+                jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
+        else if (parent == &jz_clk_ext.clk)
+                jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        return 0;
+}
+
+static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
+{
+        if (parent == &jz_clk_pll_half)
+                jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
+        else if (parent == &jz_clk_ext.clk)
+                jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        return 0;
+}
+
+static int jz_clk_udc_enable(struct clk *clk)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
+                        JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
+
+        return 0;
+}
+
+static int jz_clk_udc_disable(struct clk *clk)
+{
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
+                        JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
+
+        return 0;
+}
+
+static int jz_clk_udc_is_enabled(struct clk *clk)
+{
+        return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
+                        JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
+}
+
+static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
+{
+        if (parent == &jz_clk_pll_half)
+                jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
+        else if (parent == &jz_clk_ext.clk)
+                jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        return 0;
+}
+
+static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return -EINVAL;
+
+        div = clk_get_rate(clk->parent) / rate - 1;
+
+        if (div < 0)
+                div = 0;
+        else if (div > 63)
+                div = 63;
+
+        jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
+                                JZ_CLOCK_CTRL_UDIV_MASK);
+        return 0;
+}
+
+static unsigned long jz_clk_udc_get_rate(struct clk *clk)
+{
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return clk_get_rate(clk->parent);
+
+        div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
+        div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
+        div += 1;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long jz_clk_divided_get_rate(struct clk *clk)
+{
+        struct divided_clk *dclk = (struct divided_clk *)clk;
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return clk_get_rate(clk->parent);
+
+        div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct divided_clk *dclk = (struct divided_clk *)clk;
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return -EINVAL;
+
+        div = clk_get_rate(clk->parent) / rate - 1;
+
+        if (div < 0)
+                div = 0;
+        else if (div > dclk->mask)
+                div = dclk->mask;
+
+        jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
+
+        return 0;
+}
+
+static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+        unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
+
+        if (rate > 150000000)
+                return 150000000;
+
+        div = parent_rate / rate;
+        if (div < 1)
+                div = 1;
+        else if (div > 32)
+                div = 32;
+
+        return parent_rate / div;
+}
+
+static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+
+        if (rate > 150000000)
+                return -EINVAL;
+
+        div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
+        if (div < 0)
+                div = 0;
+        else if (div > 31)
+                div = 31;
+
+        jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
+                                JZ_CLOCK_CTRL_LDIV_MASK);
+
+        return 0;
+}
+
+static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
+{
+        int div;
+
+        div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
+        div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
+
+        return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
+}
+
+static const struct clk_ops jz_clk_ops_ld = {
+        .set_rate = jz_clk_ldclk_set_rate,
+        .get_rate = jz_clk_ldclk_get_rate,
+        .round_rate = jz_clk_ldclk_round_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct clk jz_clk_ld = {
+        .name = "lcd",
+        .gate_bit = JZ_CLOCK_GATE_LCD,
+        .parent = &jz_clk_pll_half,
+        .ops = &jz_clk_ops_ld,
+};
+
+static const struct clk_ops jz_clk_i2s_ops = {
+        .set_rate = jz_clk_divided_set_rate,
+        .get_rate = jz_clk_divided_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+        .set_parent = jz_clk_i2s_set_parent,
+};
+
+static const struct clk_ops jz_clk_spi_ops = {
+        .set_rate = jz_clk_divided_set_rate,
+        .get_rate = jz_clk_divided_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+        .set_parent = jz_clk_spi_set_parent,
+};
+
+static const struct clk_ops jz_clk_divided_ops = {
+        .set_rate = jz_clk_divided_set_rate,
+        .get_rate = jz_clk_divided_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct divided_clk jz4740_clock_divided_clks[] = {
+        [0] = {
+                .clk = {
+                        .name = "i2s",
+                        .parent = &jz_clk_ext.clk,
+                        .gate_bit = JZ_CLOCK_GATE_I2S,
+                        .ops = &jz_clk_i2s_ops,
+                },
+                .reg = JZ_REG_CLOCK_I2S,
+                .mask = JZ_CLOCK_I2S_DIV_MASK,
+        },
+        [1] = {
+                .clk = {
+                        .name = "spi",
+                        .parent = &jz_clk_ext.clk,
+                        .gate_bit = JZ_CLOCK_GATE_SPI,
+                        .ops = &jz_clk_spi_ops,
+                },
+                .reg = JZ_REG_CLOCK_SPI,
+                .mask = JZ_CLOCK_SPI_DIV_MASK,
+        },
+        [2] = {
+                .clk = {
+                        .name = "lcd_pclk",
+                        .parent = &jz_clk_pll_half,
+                        .gate_bit = JZ4740_CLK_NOT_GATED,
+                        .ops = &jz_clk_divided_ops,
+                },
+                .reg = JZ_REG_CLOCK_LCD,
+                .mask = JZ_CLOCK_LCD_DIV_MASK,
+        },
+        [3] = {
+                .clk = {
+                        .name = "mmc",
+                        .parent = &jz_clk_pll_half,
+                        .gate_bit = JZ_CLOCK_GATE_MMC,
+                        .ops = &jz_clk_divided_ops,
+                },
+                .reg = JZ_REG_CLOCK_MMC,
+                .mask = JZ_CLOCK_MMC_DIV_MASK,
+        },
+        [4] = {
+                .clk = {
+                        .name = "uhc",
+                        .parent = &jz_clk_pll_half,
+                        .gate_bit = JZ_CLOCK_GATE_UHC,
+                        .ops = &jz_clk_divided_ops,
+                },
+                .reg = JZ_REG_CLOCK_UHC,
+                .mask = JZ_CLOCK_UHC_DIV_MASK,
+        },
+};
+
+static const struct clk_ops jz_clk_udc_ops = {
+        .set_parent = jz_clk_udc_set_parent,
+        .set_rate = jz_clk_udc_set_rate,
+        .get_rate = jz_clk_udc_get_rate,
+        .enable = jz_clk_udc_enable,
+        .disable = jz_clk_udc_disable,
+        .is_enabled = jz_clk_udc_is_enabled,
+};
+
+static const struct clk_ops jz_clk_simple_ops = {
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct clk jz4740_clock_simple_clks[] = {
+        [0] = {
+                .name = "udc",
+                .parent = &jz_clk_ext.clk,
+                .ops = &jz_clk_udc_ops,
+        },
+        [1] = {
+                .name = "uart0",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_UART0,
+                .ops = &jz_clk_simple_ops,
+        },
+        [2] = {
+                .name = "uart1",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_UART1,
+                .ops = &jz_clk_simple_ops,
+        },
+        [3] = {
+                .name = "dma",
+                .parent = &jz_clk_high_speed_peripheral.clk,
+                .gate_bit = JZ_CLOCK_GATE_UART0,
+                .ops = &jz_clk_simple_ops,
+        },
+        [4] = {
+                .name = "ipu",
+                .parent = &jz_clk_high_speed_peripheral.clk,
+                .gate_bit = JZ_CLOCK_GATE_IPU,
+                .ops = &jz_clk_simple_ops,
+        },
+        [5] = {
+                .name = "adc",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_ADC,
+                .ops = &jz_clk_simple_ops,
+        },
+        [6] = {
+                .name = "i2c",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_I2C,
+                .ops = &jz_clk_simple_ops,
+        },
+        [7] = {
+                .name = "aic",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_AIC,
+                .ops = &jz_clk_simple_ops,
+        },
+};
+
+static struct static_clk jz_clk_rtc = {
+        .clk = {
+                .name = "rtc",
+                .gate_bit = JZ_CLOCK_GATE_RTC,
+                .ops = &jz_clk_static_ops,
+        },
+        .rate = 32768,
+};
+
+int clk_enable(struct clk *clk)
+{
+        if (!clk->ops->enable)
+                return -EINVAL;
+
+        return clk->ops->enable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        if (clk->ops->disable)
+                clk->ops->disable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+int clk_is_enabled(struct clk *clk)
+{
+        if (clk->ops->is_enabled)
+                return clk->ops->is_enabled(clk);
+
+        return 1;
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk->ops->get_rate)
+                return clk->ops->get_rate(clk);
+        if (clk->parent)
+                return clk_get_rate(clk->parent);
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (!clk->ops->set_rate)
+                return -EINVAL;
+        return clk->ops->set_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk->ops->round_rate)
+                return clk->ops->round_rate(clk, rate);
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret;
+        int enabled;
+
+        if (!clk->ops->set_parent)
+                return -EINVAL;
+
+        enabled = clk_is_enabled(clk);
+        if (enabled)
+                clk_disable(clk);
+        ret = clk->ops->set_parent(clk, parent);
+        if (enabled)
+                clk_enable(clk);
+
+        jz4740_clock_debugfs_update_parent(clk);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+struct clk *clk_get(struct device *dev, const char *name)
+{
+        struct clk *clk;
+
+        list_for_each_entry(clk, &jz_clocks, list) {
+                if (strcmp(clk->name, name) == 0)
+                        return clk;
+        }
+        return ERR_PTR(-ENXIO);
+}
+EXPORT_SYMBOL_GPL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL_GPL(clk_put);
+
+static inline void clk_add(struct clk *clk)
+{
+        list_add_tail(&clk->list, &jz_clocks);
+
+        jz4740_clock_debugfs_add_clk(clk);
+}
+
+static void clk_register_clks(void)
+{
+        size_t i;
+
+        clk_add(&jz_clk_ext.clk);
+        clk_add(&jz_clk_pll);
+        clk_add(&jz_clk_pll_half);
+        clk_add(&jz_clk_cpu.clk);
+        clk_add(&jz_clk_high_speed_peripheral.clk);
+        clk_add(&jz_clk_low_speed_peripheral.clk);
+        clk_add(&jz_clk_ko);
+        clk_add(&jz_clk_ld);
+        clk_add(&jz_clk_rtc.clk);
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
+                clk_add(&jz4740_clock_divided_clks[i].clk);
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
+                clk_add(&jz4740_clock_simple_clks[i]);
+}
+
+void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
+{
+        switch (mode) {
+        case JZ4740_WAIT_MODE_IDLE:
+                jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
+                break;
+        case JZ4740_WAIT_MODE_SLEEP:
+                jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
+                break;
+        }
+}
+
+void jz4740_clock_udc_disable_auto_suspend(void)
+{
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
+}
+EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
+
+void jz4740_clock_udc_enable_auto_suspend(void)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
+}
+EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
+
+void jz4740_clock_suspend(void)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
+                JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+}
+
+void jz4740_clock_resume(void)
+{
+        uint32_t pll;
+
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+
+        do {
+                pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
+        } while (!(pll & JZ_CLOCK_PLL_STABLE));
+
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
+                JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+}
+
+static int jz4740_clock_init(void)
+{
+        uint32_t val;
+
+        jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
+        if (!jz_clock_base)
+                return -EBUSY;
+
+        spin_lock_init(&jz_clock_lock);
+
+        jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
+        jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
+
+        val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
+
+        if (val & JZ_CLOCK_SPI_SRC_PLL)
+                jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
+
+        val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+        if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
+                jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
+
+        if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
+                jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
+
+        jz4740_clock_debugfs_init();
+
+        clk_register_clks();
+
+        return 0;
+}
+arch_initcall(jz4740_clock_init);
diff --git a/arch/mips/jz4740/clock.h b/arch/mips/jz4740/clock.h
new file mode 100644
index 000000000000..5d07499d7461
--- /dev/null
+++ b/arch/mips/jz4740/clock.h
@@ -0,0 +1,76 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC clock support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_CLOCK_H__
+#define __MIPS_JZ4740_CLOCK_H__
+
+#include <linux/list.h>
+
+struct jz4740_clock_board_data {
+        unsigned long ext_rate;
+        unsigned long rtc_rate;
+};
+
+extern struct jz4740_clock_board_data jz4740_clock_bdata;
+
+void jz4740_clock_suspend(void);
+void jz4740_clock_resume(void);
+
+struct clk;
+
+struct clk_ops {
+        unsigned long (*get_rate)(struct clk *clk);
+        unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+        int (*set_rate)(struct clk *clk, unsigned long rate);
+        int (*enable)(struct clk *clk);
+        int (*disable)(struct clk *clk);
+        int (*is_enabled)(struct clk *clk);
+
+        int (*set_parent)(struct clk *clk, struct clk *parent);
+
+};
+
+struct clk {
+        const char *name;
+        struct clk *parent;
+
+        uint32_t gate_bit;
+
+        const struct clk_ops *ops;
+
+        struct list_head list;
+
+#ifdef CONFIG_DEBUG_FS
+        struct dentry *debugfs_entry;
+        struct dentry *debugfs_parent_entry;
+#endif
+
+};
+
+#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
+
+int clk_is_enabled(struct clk *clk);
+
+#ifdef CONFIG_DEBUG_FS
+void jz4740_clock_debugfs_init(void);
+void jz4740_clock_debugfs_add_clk(struct clk *clk);
+void jz4740_clock_debugfs_update_parent(struct clk *clk);
+#else
+static inline void jz4740_clock_debugfs_init(void) {};
+static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {};
+static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {};
+#endif
+
+#endif
diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c
new file mode 100644
index 000000000000..5ebe75a68350
--- /dev/null
+++ b/arch/mips/jz4740/dma.c
@@ -0,0 +1,289 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC DMA support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+
+#include <linux/dma-mapping.h>
+#include <asm/mach-jz4740/dma.h>
+#include <asm/mach-jz4740/base.h>
+
+#define JZ_REG_DMA_SRC_ADDR(x)          (0x00 + (x) * 0x20)
+#define JZ_REG_DMA_DST_ADDR(x)          (0x04 + (x) * 0x20)
+#define JZ_REG_DMA_TRANSFER_COUNT(x)    (0x08 + (x) * 0x20)
+#define JZ_REG_DMA_REQ_TYPE(x)          (0x0C + (x) * 0x20)
+#define JZ_REG_DMA_STATUS_CTRL(x)       (0x10 + (x) * 0x20)
+#define JZ_REG_DMA_CMD(x)               (0x14 + (x) * 0x20)
+#define JZ_REG_DMA_DESC_ADDR(x)         (0x18 + (x) * 0x20)
+
+#define JZ_REG_DMA_CTRL                 0x300
+#define JZ_REG_DMA_IRQ                  0x304
+#define JZ_REG_DMA_DOORBELL             0x308
+#define JZ_REG_DMA_DOORBELL_SET         0x30C
+
+#define JZ_DMA_STATUS_CTRL_NO_DESC              BIT(31)
+#define JZ_DMA_STATUS_CTRL_DESC_INV             BIT(6)
+#define JZ_DMA_STATUS_CTRL_ADDR_ERR             BIT(4)
+#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE        BIT(3)
+#define JZ_DMA_STATUS_CTRL_HALT                 BIT(2)
+#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE      BIT(1)
+#define JZ_DMA_STATUS_CTRL_ENABLE               BIT(0)
+
+#define JZ_DMA_CMD_SRC_INC                      BIT(23)
+#define JZ_DMA_CMD_DST_INC                      BIT(22)
+#define JZ_DMA_CMD_RDIL_MASK                    (0xf << 16)
+#define JZ_DMA_CMD_SRC_WIDTH_MASK               (0x3 << 14)
+#define JZ_DMA_CMD_DST_WIDTH_MASK               (0x3 << 12)
+#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK         (0x7 << 8)
+#define JZ_DMA_CMD_BLOCK_MODE                   BIT(7)
+#define JZ_DMA_CMD_DESC_VALID                   BIT(4)
+#define JZ_DMA_CMD_DESC_VALID_MODE              BIT(3)
+#define JZ_DMA_CMD_VALID_IRQ_ENABLE             BIT(2)
+#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE          BIT(1)
+#define JZ_DMA_CMD_LINK_ENABLE                  BIT(0)
+
+#define JZ_DMA_CMD_FLAGS_OFFSET 22
+#define JZ_DMA_CMD_RDIL_OFFSET 16
+#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
+#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
+#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
+#define JZ_DMA_CMD_MODE_OFFSET 7
+
+#define JZ_DMA_CTRL_PRIORITY_MASK       (0x3 << 8)
+#define JZ_DMA_CTRL_HALT                BIT(3)
+#define JZ_DMA_CTRL_ADDRESS_ERROR       BIT(2)
+#define JZ_DMA_CTRL_ENABLE              BIT(0)
+
+
+static void __iomem *jz4740_dma_base;
+static spinlock_t jz4740_dma_lock;
+
+static inline uint32_t jz4740_dma_read(size_t reg)
+{
+        return readl(jz4740_dma_base + reg);
+}
+
+static inline void jz4740_dma_write(size_t reg, uint32_t val)
+{
+        writel(val, jz4740_dma_base + reg);
+}
+
+static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
+{
+        uint32_t val2;
+        val2 = jz4740_dma_read(reg);
+        val2 &= ~mask;
+        val2 |= val;
+        jz4740_dma_write(reg, val2);
+}
+
+struct jz4740_dma_chan {
+        unsigned int id;
+        void *dev;
+        const char *name;
+
+        enum jz4740_dma_flags flags;
+        uint32_t transfer_shift;
+
+        jz4740_dma_complete_callback_t complete_cb;
+
+        unsigned used:1;
+};
+
+#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
+
+struct jz4740_dma_chan jz4740_dma_channels[] = {
+        JZ4740_DMA_CHANNEL(0),
+        JZ4740_DMA_CHANNEL(1),
+        JZ4740_DMA_CHANNEL(2),
+        JZ4740_DMA_CHANNEL(3),
+        JZ4740_DMA_CHANNEL(4),
+        JZ4740_DMA_CHANNEL(5),
+};
+
+struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
+{
+        unsigned int i;
+        struct jz4740_dma_chan *dma = NULL;
+
+        spin_lock(&jz4740_dma_lock);
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
+                if (!jz4740_dma_channels[i].used) {
+                        dma = &jz4740_dma_channels[i];
+                        dma->used = 1;
+                        break;
+                }
+        }
+
+        spin_unlock(&jz4740_dma_lock);
+
+        if (!dma)
+                return NULL;
+
+        dma->dev = dev;
+        dma->name = name;
+
+        return dma;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_request);
+
+void jz4740_dma_configure(struct jz4740_dma_chan *dma,
+        const struct jz4740_dma_config *config)
+{
+        uint32_t cmd;
+
+        switch (config->transfer_size) {
+        case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
+                dma->transfer_shift = 1;
+                break;
+        case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
+                dma->transfer_shift = 2;
+                break;
+        case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
+                dma->transfer_shift = 4;
+                break;
+        case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
+                dma->transfer_shift = 5;
+                break;
+        default:
+                dma->transfer_shift = 0;
+                break;
+        }
+
+        cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
+        cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
+        cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
+        cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
+        cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
+        cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
+
+        jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
+        jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
+        jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_configure);
+
+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
+{
+        jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
+
+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
+{
+        jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
+
+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
+{
+        count >>= dma->transfer_shift;
+        jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
+
+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
+        jz4740_dma_complete_callback_t cb)
+{
+        dma->complete_cb = cb;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
+
+void jz4740_dma_free(struct jz4740_dma_chan *dma)
+{
+        dma->dev = NULL;
+        dma->complete_cb = NULL;
+        dma->used = 0;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_free);
+
+void jz4740_dma_enable(struct jz4740_dma_chan *dma)
+{
+        jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
+                        JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
+                        JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
+                        JZ_DMA_STATUS_CTRL_ENABLE);
+
+        jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
+                        JZ_DMA_CTRL_ENABLE,
+                        JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_enable);
+
+void jz4740_dma_disable(struct jz4740_dma_chan *dma)
+{
+        jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
+                        JZ_DMA_STATUS_CTRL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_disable);
+
+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
+{
+        uint32_t residue;
+        residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
+        return residue << dma->transfer_shift;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
+
+static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
+{
+        uint32_t status;
+
+        status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
+
+        jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
+                JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
+
+        if (dma->complete_cb)
+                dma->complete_cb(dma, 0, dma->dev);
+}
+
+static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
+{
+        uint32_t irq_status;
+        unsigned int i;
+
+        irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
+
+        for (i = 0; i < 6; ++i) {
+                if (irq_status & (1 << i))
+                        jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int jz4740_dma_init(void)
+{
+        unsigned int ret;
+
+        jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
+
+        if (!jz4740_dma_base)
+                return -EBUSY;
+
+        spin_lock_init(&jz4740_dma_lock);
+
+        ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
+
+        if (ret)
+                printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
+
+        return ret;
+}
+arch_initcall(jz4740_dma_init);
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
new file mode 100644
index 000000000000..38f60f35156c
--- /dev/null
+++ b/arch/mips/jz4740/gpio.c
@@ -0,0 +1,604 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform GPIO support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/spinlock.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include <asm/mach-jz4740/base.h>
+
+#define JZ4740_GPIO_BASE_A (32*0)
+#define JZ4740_GPIO_BASE_B (32*1)
+#define JZ4740_GPIO_BASE_C (32*2)
+#define JZ4740_GPIO_BASE_D (32*3)
+
+#define JZ4740_GPIO_NUM_A 32
+#define JZ4740_GPIO_NUM_B 32
+#define JZ4740_GPIO_NUM_C 31
+#define JZ4740_GPIO_NUM_D 32
+
+#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
+#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
+#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
+#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
+
+#define JZ_REG_GPIO_PIN                 0x00
+#define JZ_REG_GPIO_DATA                0x10
+#define JZ_REG_GPIO_DATA_SET            0x14
+#define JZ_REG_GPIO_DATA_CLEAR          0x18
+#define JZ_REG_GPIO_MASK                0x20
+#define JZ_REG_GPIO_MASK_SET            0x24
+#define JZ_REG_GPIO_MASK_CLEAR          0x28
+#define JZ_REG_GPIO_PULL                0x30
+#define JZ_REG_GPIO_PULL_SET            0x34
+#define JZ_REG_GPIO_PULL_CLEAR          0x38
+#define JZ_REG_GPIO_FUNC                0x40
+#define JZ_REG_GPIO_FUNC_SET            0x44
+#define JZ_REG_GPIO_FUNC_CLEAR          0x48
+#define JZ_REG_GPIO_SELECT              0x50
+#define JZ_REG_GPIO_SELECT_SET          0x54
+#define JZ_REG_GPIO_SELECT_CLEAR        0x58
+#define JZ_REG_GPIO_DIRECTION           0x60
+#define JZ_REG_GPIO_DIRECTION_SET       0x64
+#define JZ_REG_GPIO_DIRECTION_CLEAR     0x68
+#define JZ_REG_GPIO_TRIGGER             0x70
+#define JZ_REG_GPIO_TRIGGER_SET         0x74
+#define JZ_REG_GPIO_TRIGGER_CLEAR       0x78
+#define JZ_REG_GPIO_FLAG                0x80
+#define JZ_REG_GPIO_FLAG_CLEAR          0x14
+
+#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
+#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
+#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
+
+struct jz_gpio_chip {
+        unsigned int irq;
+        unsigned int irq_base;
+        uint32_t wakeup;
+        uint32_t suspend_mask;
+        uint32_t edge_trigger_both;
+
+        void __iomem *base;
+
+        spinlock_t lock;
+
+        struct gpio_chip gpio_chip;
+        struct irq_chip irq_chip;
+        struct sys_device sysdev;
+};
+
+static struct jz_gpio_chip jz4740_gpio_chips[];
+
+static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
+{
+        return &jz4740_gpio_chips[gpio >> 5];
+}
+
+static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
+{
+        return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
+}
+
+static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq)
+{
+        return get_irq_chip_data(irq);
+}
+
+static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
+{
+        writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
+}
+
+int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
+{
+        if (function == JZ_GPIO_FUNC_NONE) {
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
+        } else {
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
+                switch (function) {
+                case JZ_GPIO_FUNC1:
+                        jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
+                        break;
+                case JZ_GPIO_FUNC3:
+                        jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
+                case JZ_GPIO_FUNC2: /* Falltrough */
+                        jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
+                        break;
+                default:
+                        BUG();
+                        break;
+                }
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(jz_gpio_set_function);
+
+int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+        int ret;
+
+        for (i = 0; i < num; ++i, ++request) {
+                ret = gpio_request(request->gpio, request->name);
+                if (ret)
+                        goto err;
+                jz_gpio_set_function(request->gpio, request->function);
+        }
+
+        return 0;
+
+err:
+        for (--request; i > 0; --i, --request) {
+                gpio_free(request->gpio);
+                jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
+
+void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+
+        for (i = 0; i < num; ++i, ++request) {
+                gpio_free(request->gpio);
+                jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+        }
+
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
+
+void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+
+        for (i = 0; i < num; ++i, ++request) {
+                jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+                jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
+        }
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
+
+void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+
+        for (i = 0; i < num; ++i, ++request)
+                jz_gpio_set_function(request->gpio, request->function);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
+
+void jz_gpio_enable_pullup(unsigned gpio)
+{
+        jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
+
+void jz_gpio_disable_pullup(unsigned gpio)
+{
+        jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
+
+static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
+}
+
+static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+        uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
+        reg += !value;
+        writel(BIT(gpio), reg);
+}
+
+static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
+        int value)
+{
+        writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
+        jz_gpio_set_value(chip, gpio, value);
+
+        return 0;
+}
+
+static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
+
+        return 0;
+}
+
+int jz_gpio_port_direction_input(int port, uint32_t mask)
+{
+        writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
+
+        return 0;
+}
+EXPORT_SYMBOL(jz_gpio_port_direction_input);
+
+int jz_gpio_port_direction_output(int port, uint32_t mask)
+{
+        writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
+
+        return 0;
+}
+EXPORT_SYMBOL(jz_gpio_port_direction_output);
+
+void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
+{
+        writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
+        writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
+}
+EXPORT_SYMBOL(jz_gpio_port_set_value);
+
+uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
+{
+        uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
+
+        return value & mask;
+}
+EXPORT_SYMBOL(jz_gpio_port_get_value);
+
+int gpio_to_irq(unsigned gpio)
+{
+        return JZ4740_IRQ_GPIO(0) + gpio;
+}
+EXPORT_SYMBOL_GPL(gpio_to_irq);
+
+int irq_to_gpio(unsigned irq)
+{
+        return irq - JZ4740_IRQ_GPIO(0);
+}
+EXPORT_SYMBOL_GPL(irq_to_gpio);
+
+#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
+
+static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
+{
+        uint32_t value;
+        void __iomem *reg;
+        uint32_t mask = IRQ_TO_BIT(irq);
+
+        if (!(chip->edge_trigger_both & mask))
+                return;
+
+        reg = chip->base;
+
+        value = readl(chip->base + JZ_REG_GPIO_PIN);
+        if (value & mask)
+                reg += JZ_REG_GPIO_DIRECTION_CLEAR;
+        else
+                reg += JZ_REG_GPIO_DIRECTION_SET;
+
+        writel(mask, reg);
+}
+
+static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+        uint32_t flag;
+        unsigned int gpio_irq;
+        unsigned int gpio_bank;
+        struct jz_gpio_chip *chip = get_irq_desc_data(desc);
+
+        gpio_bank = JZ4740_IRQ_GPIO0 - irq;
+
+        flag = readl(chip->base + JZ_REG_GPIO_FLAG);
+
+        if (!flag)
+                return;
+
+        gpio_irq = __fls(flag);
+
+        jz_gpio_check_trigger_both(chip, irq);
+
+        gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
+
+        generic_handle_irq(gpio_irq);
+};
+
+static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        writel(IRQ_TO_BIT(irq), chip->base + reg);
+}
+
+static void jz_gpio_irq_mask(unsigned int irq)
+{
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
+};
+
+static void jz_gpio_irq_unmask(unsigned int irq)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+
+        jz_gpio_check_trigger_both(chip, irq);
+
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
+};
+
+/* TODO: Check if function is gpio */
+static unsigned int jz_gpio_irq_startup(unsigned int irq)
+{
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
+
+        desc->status &= ~IRQ_MASKED;
+        jz_gpio_irq_unmask(irq);
+
+        return 0;
+}
+
+static void jz_gpio_irq_shutdown(unsigned int irq)
+{
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        jz_gpio_irq_mask(irq);
+        desc->status |= IRQ_MASKED;
+
+        /* Set direction to input */
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
+}
+
+static void jz_gpio_irq_ack(unsigned int irq)
+{
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
+};
+
+static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        jz_gpio_irq_mask(irq);
+
+        if (flow_type == IRQ_TYPE_EDGE_BOTH) {
+                uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
+                if (value & IRQ_TO_BIT(irq))
+                        flow_type = IRQ_TYPE_EDGE_FALLING;
+                else
+                        flow_type = IRQ_TYPE_EDGE_RISING;
+                chip->edge_trigger_both |= IRQ_TO_BIT(irq);
+        } else {
+                chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
+        }
+
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_RISING:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (!(desc->status & IRQ_MASKED))
+                jz_gpio_irq_unmask(irq);
+
+        return 0;
+}
+
+static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        spin_lock(&chip->lock);
+        if (on)
+                chip->wakeup |= IRQ_TO_BIT(irq);
+        else
+                chip->wakeup &= ~IRQ_TO_BIT(irq);
+        spin_unlock(&chip->lock);
+
+        set_irq_wake(chip->irq, on);
+        return 0;
+}
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
+#define JZ4740_GPIO_CHIP(_bank) { \
+        .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
+        .gpio_chip = { \
+                .label = "Bank " # _bank, \
+                .owner = THIS_MODULE, \
+                .set = jz_gpio_set_value, \
+                .get = jz_gpio_get_value, \
+                .direction_output = jz_gpio_direction_output, \
+                .direction_input = jz_gpio_direction_input, \
+                .base = JZ4740_GPIO_BASE_ ## _bank, \
+                .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
+        }, \
+        .irq_chip =  { \
+                .name = "GPIO Bank " # _bank, \
+                .mask = jz_gpio_irq_mask, \
+                .unmask = jz_gpio_irq_unmask, \
+                .ack = jz_gpio_irq_ack, \
+                .startup = jz_gpio_irq_startup, \
+                .shutdown = jz_gpio_irq_shutdown, \
+                .set_type = jz_gpio_irq_set_type, \
+                .set_wake = jz_gpio_irq_set_wake, \
+        }, \
+}
+
+static struct jz_gpio_chip jz4740_gpio_chips[] = {
+        JZ4740_GPIO_CHIP(A),
+        JZ4740_GPIO_CHIP(B),
+        JZ4740_GPIO_CHIP(C),
+        JZ4740_GPIO_CHIP(D),
+};
+
+static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
+{
+        return container_of(dev, struct jz_gpio_chip, sysdev);
+}
+
+static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+        struct jz_gpio_chip *chip = sysdev_to_chip(dev);
+
+        chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
+        writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
+        writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+
+        return 0;
+}
+
+static int jz4740_gpio_resume(struct sys_device *dev)
+{
+        struct jz_gpio_chip *chip = sysdev_to_chip(dev);
+        uint32_t mask = chip->suspend_mask;
+
+        writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+        writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
+
+        return 0;
+}
+
+static struct sysdev_class jz4740_gpio_sysdev_class = {
+        .name = "gpio",
+        .suspend = jz4740_gpio_suspend,
+        .resume = jz4740_gpio_resume,
+};
+
+static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
+{
+        int ret, irq;
+
+        chip->sysdev.id = id;
+        chip->sysdev.cls = &jz4740_gpio_sysdev_class;
+        ret = sysdev_register(&chip->sysdev);
+
+        if (ret)
+                return ret;
+
+        spin_lock_init(&chip->lock);
+
+        chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
+
+        gpiochip_add(&chip->gpio_chip);
+
+        chip->irq = JZ4740_IRQ_INTC_GPIO(id);
+        set_irq_data(chip->irq, chip);
+        set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
+
+        for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
+                lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
+                set_irq_chip_data(irq, chip);
+                set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
+        }
+
+        return 0;
+}
+
+static int __init jz4740_gpio_init(void)
+{
+        unsigned int i;
+        int ret;
+
+        ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
+                jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
+
+        printk(KERN_INFO "JZ4740 GPIO initalized\n");
+
+        return 0;
+}
+arch_initcall(jz4740_gpio_init);
+
+#ifdef CONFIG_DEBUG_FS
+
+static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
+        const char *name, unsigned int reg)
+{
+        seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
+}
+
+static int gpio_regs_show(struct seq_file *s, void *unused)
+{
+        struct jz_gpio_chip *chip = jz4740_gpio_chips;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
+                seq_printf(s, "==GPIO %d==\n", i);
+                gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
+                gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
+                gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
+                gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
+                gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
+                gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
+                gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
+                gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
+                gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
+        }
+
+        return 0;
+}
+
+static int gpio_regs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, gpio_regs_show, NULL);
+}
+
+static const struct file_operations gpio_regs_operations = {
+        .open           = gpio_regs_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init gpio_debugfs_init(void)
+{
+        (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
+                                NULL, NULL, &gpio_regs_operations);
+        return 0;
+}
+subsys_initcall(gpio_debugfs_init);
+
+#endif
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
new file mode 100644
index 000000000000..7d33ff83580f
--- /dev/null
+++ b/arch/mips/jz4740/irq.c
@@ -0,0 +1,167 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform IRQ support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/irq_cpu.h>
+
+#include <asm/mach-jz4740/base.h>
+
+static void __iomem *jz_intc_base;
+static uint32_t jz_intc_wakeup;
+static uint32_t jz_intc_saved;
+
+#define JZ_REG_INTC_STATUS      0x00
+#define JZ_REG_INTC_MASK        0x04
+#define JZ_REG_INTC_SET_MASK    0x08
+#define JZ_REG_INTC_CLEAR_MASK  0x0c
+#define JZ_REG_INTC_PENDING     0x10
+
+#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
+
+static void intc_irq_unmask(unsigned int irq)
+{
+        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+}
+
+static void intc_irq_mask(unsigned int irq)
+{
+        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+static int intc_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        if (on)
+                jz_intc_wakeup |= IRQ_BIT(irq);
+        else
+                jz_intc_wakeup &= ~IRQ_BIT(irq);
+
+        return 0;
+}
+
+static struct irq_chip intc_irq_type = {
+        .name =         "INTC",
+        .mask =         intc_irq_mask,
+        .mask_ack =     intc_irq_mask,
+        .unmask =       intc_irq_unmask,
+        .set_wake =     intc_irq_set_wake,
+};
+
+static irqreturn_t jz4740_cascade(int irq, void *data)
+{
+        uint32_t irq_reg;
+
+        irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
+
+        if (irq_reg)
+                generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction jz4740_cascade_action = {
+        .handler = jz4740_cascade,
+        .name = "JZ4740 cascade interrupt",
+};
+
+void __init arch_init_irq(void)
+{
+        int i;
+        mips_cpu_irq_init();
+
+        jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
+
+        for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
+                intc_irq_mask(i);
+                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+        }
+
+        setup_irq(2, &jz4740_cascade_action);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+        if (pending & STATUSF_IP2)
+                do_IRQ(2);
+        else if (pending & STATUSF_IP3)
+                do_IRQ(3);
+        else
+                spurious_interrupt();
+}
+
+void jz4740_intc_suspend(void)
+{
+        jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
+        writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
+        writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+}
+
+void jz4740_intc_resume(void)
+{
+        writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+        writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static inline void intc_seq_reg(struct seq_file *s, const char *name,
+        unsigned int reg)
+{
+        seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
+}
+
+static int intc_regs_show(struct seq_file *s, void *unused)
+{
+        intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
+        intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
+        intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
+
+        return 0;
+}
+
+static int intc_regs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, intc_regs_show, NULL);
+}
+
+static const struct file_operations intc_regs_operations = {
+        .open           = intc_regs_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init intc_debugfs_init(void)
+{
+        (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
+                                NULL, NULL, &intc_regs_operations);
+        return 0;
+}
+subsys_initcall(intc_debugfs_init);
+
+#endif
diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h
new file mode 100644
index 000000000000..56b5eadd1fa2
--- /dev/null
+++ b/arch/mips/jz4740/irq.h
@@ -0,0 +1,21 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_IRQ_H__
+#define __MIPS_JZ4740_IRQ_H__
+
+extern void jz4740_intc_suspend(void);
+extern void jz4740_intc_resume(void);
+
+#endif
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
new file mode 100644
index 000000000000..95bc2b5b14f1
--- /dev/null
+++ b/arch/mips/jz4740/platform.c
@@ -0,0 +1,291 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform devices
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-jz4740/platform.h>
+#include <asm/mach-jz4740/base.h>
+#include <asm/mach-jz4740/irq.h>
+
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include "serial.h"
+#include "clock.h"
+
+/* OHCI controller */
+static struct resource jz4740_usb_ohci_resources[] = {
+        {
+                .start  = JZ4740_UHC_BASE_ADDR,
+                .end    = JZ4740_UHC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_UHC,
+                .end    = JZ4740_IRQ_UHC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_usb_ohci_device = {
+        .name           = "jz4740-ohci",
+        .id             = -1,
+        .dev = {
+                .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(jz4740_usb_ohci_resources),
+        .resource       = jz4740_usb_ohci_resources,
+};
+
+/* UDC (USB gadget controller) */
+static struct resource jz4740_usb_gdt_resources[] = {
+        {
+                .start  = JZ4740_UDC_BASE_ADDR,
+                .end    = JZ4740_UDC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_UDC,
+                .end    = JZ4740_IRQ_UDC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_udc_device = {
+        .name           = "jz-udc",
+        .id             = -1,
+        .dev = {
+                .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(jz4740_usb_gdt_resources),
+        .resource       = jz4740_usb_gdt_resources,
+};
+
+/* MMC/SD controller */
+static struct resource jz4740_mmc_resources[] = {
+        {
+                .start  = JZ4740_MSC_BASE_ADDR,
+                .end    = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_MSC,
+                .end    = JZ4740_IRQ_MSC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device jz4740_mmc_device = {
+        .name           = "jz4740-mmc",
+        .id             = 0,
+        .dev = {
+                .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(jz4740_mmc_resources),
+        .resource       = jz4740_mmc_resources,
+};
+
+/* RTC controller */
+static struct resource jz4740_rtc_resources[] = {
+        {
+                .start  = JZ4740_RTC_BASE_ADDR,
+                .end    = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_RTC,
+                .end    = JZ4740_IRQ_RTC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_rtc_device = {
+        .name           = "jz4740-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_rtc_resources),
+        .resource       = jz4740_rtc_resources,
+};
+
+/* I2C controller */
+static struct resource jz4740_i2c_resources[] = {
+        {
+                .start  = JZ4740_I2C_BASE_ADDR,
+                .end    = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_I2C,
+                .end    = JZ4740_IRQ_I2C,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device jz4740_i2c_device = {
+        .name           = "jz4740-i2c",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(jz4740_i2c_resources),
+        .resource       = jz4740_i2c_resources,
+};
+
+/* NAND controller */
+static struct resource jz4740_nand_resources[] = {
+        {
+                .name   = "mmio",
+                .start  = JZ4740_EMC_BASE_ADDR,
+                .end    = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "bank",
+                .start  = 0x18000000,
+                .end    = 0x180C0000 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_nand_device = {
+        .name = "jz4740-nand",
+        .num_resources = ARRAY_SIZE(jz4740_nand_resources),
+        .resource = jz4740_nand_resources,
+};
+
+/* LCD controller */
+static struct resource jz4740_framebuffer_resources[] = {
+        {
+                .start  = JZ4740_LCD_BASE_ADDR,
+                .end    = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_framebuffer_device = {
+        .name           = "jz4740-fb",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_framebuffer_resources),
+        .resource       = jz4740_framebuffer_resources,
+        .dev = {
+                .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+/* I2S controller */
+static struct resource jz4740_i2s_resources[] = {
+        {
+                .start  = JZ4740_AIC_BASE_ADDR,
+                .end    = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_i2s_device = {
+        .name           = "jz4740-i2s",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_i2s_resources),
+        .resource       = jz4740_i2s_resources,
+};
+
+/* PCM */
+struct platform_device jz4740_pcm_device = {
+        .name           = "jz4740-pcm",
+        .id             = -1,
+};
+
+/* Codec */
+static struct resource jz4740_codec_resources[] = {
+        {
+                .start  = JZ4740_AIC_BASE_ADDR + 0x80,
+                .end    = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_codec_device = {
+        .name           = "jz4740-codec",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_codec_resources),
+        .resource       = jz4740_codec_resources,
+};
+
+/* ADC controller */
+static struct resource jz4740_adc_resources[] = {
+        {
+                .start  = JZ4740_SADC_BASE_ADDR,
+                .end    = JZ4740_SADC_BASE_ADDR + 0x30,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_SADC,
+                .end    = JZ4740_IRQ_SADC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = JZ4740_IRQ_ADC_BASE,
+                .end    = JZ4740_IRQ_ADC_BASE,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_adc_device = {
+        .name           = "jz4740-adc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_adc_resources),
+        .resource       = jz4740_adc_resources,
+};
+
+/* Serial */
+#define JZ4740_UART_DATA(_id) \
+        { \
+                .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
+                .iotype = UPIO_MEM, \
+                .regshift = 2, \
+                .serial_out = jz4740_serial_out, \
+                .type = PORT_16550, \
+                .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
+                .irq = JZ4740_IRQ_UART ## _id, \
+        }
+
+static struct plat_serial8250_port jz4740_uart_data[] = {
+        JZ4740_UART_DATA(0),
+        JZ4740_UART_DATA(1),
+        {},
+};
+
+static struct platform_device jz4740_uart_device = {
+        .name = "serial8250",
+        .id = 0,
+        .dev = {
+                .platform_data = jz4740_uart_data,
+        },
+};
+
+void jz4740_serial_device_register(void)
+{
+        struct plat_serial8250_port *p;
+
+        for (p = jz4740_uart_data; p->flags != 0; ++p)
+                p->uartclk = jz4740_clock_bdata.ext_rate;
+
+        platform_device_register(&jz4740_uart_device);
+}
diff --git a/arch/mips/jz4740/pm.c b/arch/mips/jz4740/pm.c
new file mode 100644
index 000000000000..a9994585424d
--- /dev/null
+++ b/arch/mips/jz4740/pm.c
@@ -0,0 +1,56 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *      JZ4740 SoC power management support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+
+#include <asm/mach-jz4740/clock.h>
+
+#include "clock.h"
+#include "irq.h"
+
+static int jz4740_pm_enter(suspend_state_t state)
+{
+        jz4740_intc_suspend();
+        jz4740_clock_suspend();
+
+        jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
+
+        __asm__(".set\tmips3\n\t"
+                "wait\n\t"
+                ".set\tmips0");
+
+        jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
+
+        jz4740_clock_resume();
+        jz4740_intc_resume();
+
+        return 0;
+}
+
+static struct platform_suspend_ops jz4740_pm_ops = {
+        .valid          = suspend_valid_only_mem,
+        .enter          = jz4740_pm_enter,
+};
+
+static int __init jz4740_pm_init(void)
+{
+        suspend_set_ops(&jz4740_pm_ops);
+        return 0;
+
+}
+late_initcall(jz4740_pm_init);
diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c
new file mode 100644
index 000000000000..cfeac15eb2e4
--- /dev/null
+++ b/arch/mips/jz4740/prom.c
@@ -0,0 +1,68 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC prom code
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <linux/serial_reg.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-jz4740/base.h>
+
+void jz4740_init_cmdline(int argc, char *argv[])
+{
+        unsigned int count = COMMAND_LINE_SIZE - 1;
+        int i;
+        char *dst = &(arcs_cmdline[0]);
+        char *src;
+
+        for (i = 1; i < argc && count; ++i) {
+                src = argv[i];
+                while (*src && count) {
+                        *dst++ = *src++;
+                        --count;
+                }
+                *dst++ = ' ';
+        }
+        if (i > 1)
+                --dst;
+
+        *dst = 0;
+}
+
+void __init prom_init(void)
+{
+        jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1);
+        mips_machtype = MACH_INGENIC_JZ4740;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
+
+void prom_putchar(char c)
+{
+        uint8_t lsr;
+
+        do {
+                lsr = readb(UART_REG(UART_LSR));
+        } while ((lsr & UART_LSR_TEMT) == 0);
+
+        writeb(c, UART_REG(UART_TX));
+}
diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c
new file mode 100644
index 000000000000..a26a6faec9a6
--- /dev/null
+++ b/arch/mips/jz4740/pwm.c
@@ -0,0 +1,177 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform PWM support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-jz4740/gpio.h>
+#include "timer.h"
+
+static struct clk *jz4740_pwm_clk;
+
+DEFINE_MUTEX(jz4740_pwm_mutex);
+
+struct pwm_device {
+        unsigned int id;
+        unsigned int gpio;
+        bool used;
+};
+
+static struct pwm_device jz4740_pwm_list[] = {
+        { 2, JZ_GPIO_PWM2, false },
+        { 3, JZ_GPIO_PWM3, false },
+        { 4, JZ_GPIO_PWM4, false },
+        { 5, JZ_GPIO_PWM5, false },
+        { 6, JZ_GPIO_PWM6, false },
+        { 7, JZ_GPIO_PWM7, false },
+};
+
+struct pwm_device *pwm_request(int id, const char *label)
+{
+        int ret = 0;
+        struct pwm_device *pwm;
+
+        if (id < 2 || id > 7 || !jz4740_pwm_clk)
+                return ERR_PTR(-ENODEV);
+
+        mutex_lock(&jz4740_pwm_mutex);
+
+        pwm = &jz4740_pwm_list[id - 2];
+        if (pwm->used)
+                ret = -EBUSY;
+        else
+                pwm->used = true;
+
+        mutex_unlock(&jz4740_pwm_mutex);
+
+        if (ret)
+                return ERR_PTR(ret);
+
+        ret = gpio_request(pwm->gpio, label);
+
+        if (ret) {
+                printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret);
+                pwm->used = false;
+                return ERR_PTR(ret);
+        }
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
+
+        jz4740_timer_start(id);
+
+        return pwm;
+}
+
+void pwm_free(struct pwm_device *pwm)
+{
+        pwm_disable(pwm);
+        jz4740_timer_set_ctrl(pwm->id, 0);
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
+        gpio_free(pwm->gpio);
+
+        jz4740_timer_stop(pwm->id);
+
+        pwm->used = false;
+}
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long tmp;
+        unsigned long period, duty;
+        unsigned int prescaler = 0;
+        unsigned int id = pwm->id;
+        uint16_t ctrl;
+        bool is_enabled;
+
+        if (duty_ns < 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
+        do_div(tmp, 1000000000);
+        period = tmp;
+
+        while (period > 0xffff && prescaler < 6) {
+                period >>= 2;
+                ++prescaler;
+        }
+
+        if (prescaler == 6)
+                return -EINVAL;
+
+        tmp = (unsigned long long)period * duty_ns;
+        do_div(tmp, period_ns);
+        duty = period - tmp;
+
+        if (duty >= period)
+                duty = period - 1;
+
+        is_enabled = jz4740_timer_is_enabled(id);
+        if (is_enabled)
+                pwm_disable(pwm);
+
+        jz4740_timer_set_count(id, 0);
+        jz4740_timer_set_duty(id, duty);
+        jz4740_timer_set_period(id, period);
+
+        ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
+                JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
+
+        jz4740_timer_set_ctrl(id, ctrl);
+
+        if (is_enabled)
+                pwm_enable(pwm);
+
+        return 0;
+}
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+        jz4740_timer_enable(pwm->id);
+
+        return 0;
+}
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_disable(pwm->id);
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+}
+
+static int __init jz4740_pwm_init(void)
+{
+        int ret = 0;
+
+        jz4740_pwm_clk = clk_get(NULL, "ext");
+
+        if (IS_ERR(jz4740_pwm_clk)) {
+                ret = PTR_ERR(jz4740_pwm_clk);
+                jz4740_pwm_clk = NULL;
+        }
+
+        return ret;
+}
+subsys_initcall(jz4740_pwm_init);
diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
new file mode 100644
index 000000000000..5f1fb95c0d0d
--- /dev/null
+++ b/arch/mips/jz4740/reset.c
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+
+#include <asm/mach-jz4740/base.h>
+#include <asm/mach-jz4740/timer.h>
+
+static void jz4740_halt(void)
+{
+        while (1) {
+                __asm__(".set push;\n"
+                        ".set mips3;\n"
+                        "wait;\n"
+                        ".set pop;\n"
+                );
+        }
+}
+
+#define JZ_REG_WDT_DATA 0x00
+#define JZ_REG_WDT_COUNTER_ENABLE 0x04
+#define JZ_REG_WDT_COUNTER 0x08
+#define JZ_REG_WDT_CTRL 0x0c
+
+static void jz4740_restart(char *command)
+{
+        void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
+
+        jz4740_timer_enable_watchdog();
+
+        writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
+
+        writew(0, wdt_base + JZ_REG_WDT_COUNTER);
+        writew(0, wdt_base + JZ_REG_WDT_DATA);
+        writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
+
+        writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
+        jz4740_halt();
+}
+
+#define JZ_REG_RTC_CTRL         0x00
+#define JZ_REG_RTC_HIBERNATE    0x20
+
+#define JZ_RTC_CTRL_WRDY        BIT(7)
+
+static void jz4740_power_off(void)
+{
+        void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
+        uint32_t ctrl;
+
+        do {
+                ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
+        } while (!(ctrl & JZ_RTC_CTRL_WRDY));
+
+        writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
+        jz4740_halt();
+}
+
+void jz4740_reset_init(void)
+{
+        _machine_restart = jz4740_restart;
+        _machine_halt = jz4740_halt;
+        pm_power_off = jz4740_power_off;
+}
diff --git a/arch/mips/jz4740/reset.h b/arch/mips/jz4740/reset.h
new file mode 100644
index 000000000000..5202ab4ad9db
--- /dev/null
+++ b/arch/mips/jz4740/reset.h
@@ -0,0 +1,6 @@
+#ifndef __MIPS_JZ4740_RESET_H__
+#define __MIPS_JZ4740_RESET_H__
+
+extern void jz4740_reset_init(void);
+
+#endif
diff --git a/arch/mips/jz4740/serial.c b/arch/mips/jz4740/serial.c
new file mode 100644
index 000000000000..d23de45826d1
--- /dev/null
+++ b/arch/mips/jz4740/serial.c
@@ -0,0 +1,33 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 serial support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+
+void jz4740_serial_out(struct uart_port *p, int offset, int value)
+{
+        switch (offset) {
+        case UART_FCR:
+                value |= 0x10; /* Enable uart module */
+                break;
+        case UART_IER:
+                value |= (value & 0x4) << 2;
+                break;
+        default:
+                break;
+        }
+        writeb(value, p->membase + (offset << p->regshift));
+}
diff --git a/arch/mips/jz4740/serial.h b/arch/mips/jz4740/serial.h
new file mode 100644
index 000000000000..b9fe3ade0289
--- /dev/null
+++ b/arch/mips/jz4740/serial.h
@@ -0,0 +1,20 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 serial support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_SERIAL_H__
+
+void jz4740_serial_out(struct uart_port *p, int offset, int value);
+
+#endif
diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
new file mode 100644
index 000000000000..6a9e14dab91e
--- /dev/null
+++ b/arch/mips/jz4740/setup.c
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 setup code
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include "reset.h"
+
+void __init plat_mem_setup(void)
+{
+        jz4740_reset_init();
+}
+
+const char *get_system_type(void)
+{
+        return "JZ4740";
+}
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
new file mode 100644
index 000000000000..fe01678d94fd
--- /dev/null
+++ b/arch/mips/jz4740/time.c
@@ -0,0 +1,144 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform time support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+
+#include <linux/clockchips.h>
+
+#include <asm/mach-jz4740/irq.h>
+#include <asm/time.h>
+
+#include "clock.h"
+#include "timer.h"
+
+#define TIMER_CLOCKEVENT 0
+#define TIMER_CLOCKSOURCE 1
+
+static uint16_t jz4740_jiffies_per_tick;
+
+static cycle_t jz4740_clocksource_read(struct clocksource *cs)
+{
+        return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
+}
+
+static struct clocksource jz4740_clocksource = {
+        .name = "jz4740-timer",
+        .rating = 200,
+        .read = jz4740_clocksource_read,
+        .mask = CLOCKSOURCE_MASK(16),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
+{
+        struct clock_event_device *cd = devid;
+
+        jz4740_timer_ack_full(TIMER_CLOCKEVENT);
+
+        if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
+                jz4740_timer_disable(TIMER_CLOCKEVENT);
+
+        cd->event_handler(cd);
+
+        return IRQ_HANDLED;
+}
+
+static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
+        struct clock_event_device *cd)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
+                jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
+        case CLOCK_EVT_MODE_RESUME:
+                jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
+                jz4740_timer_enable(TIMER_CLOCKEVENT);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                jz4740_timer_disable(TIMER_CLOCKEVENT);
+                break;
+        default:
+                break;
+        }
+}
+
+static int jz4740_clockevent_set_next(unsigned long evt,
+        struct clock_event_device *cd)
+{
+        jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
+        jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
+        jz4740_timer_enable(TIMER_CLOCKEVENT);
+
+        return 0;
+}
+
+static struct clock_event_device jz4740_clockevent = {
+        .name = "jz4740-timer",
+        .features = CLOCK_EVT_FEAT_PERIODIC,
+        .set_next_event = jz4740_clockevent_set_next,
+        .set_mode = jz4740_clockevent_set_mode,
+        .rating = 200,
+        .irq = JZ4740_IRQ_TCU0,
+};
+
+static struct irqaction timer_irqaction = {
+        .handler        = jz4740_clockevent_irq,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
+        .name           = "jz4740-timerirq",
+        .dev_id         = &jz4740_clockevent,
+};
+
+void __init plat_time_init(void)
+{
+        int ret;
+        uint32_t clk_rate;
+        uint16_t ctrl;
+
+        jz4740_timer_init();
+
+        clk_rate = jz4740_clock_bdata.ext_rate >> 4;
+        jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
+
+        clockevent_set_clock(&jz4740_clockevent, clk_rate);
+        jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
+        jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
+        jz4740_clockevent.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&jz4740_clockevent);
+
+        clocksource_set_clock(&jz4740_clocksource, clk_rate);
+        ret = clocksource_register(&jz4740_clocksource);
+
+        if (ret)
+                printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
+
+        setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
+
+        ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
+
+        jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
+        jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
+
+        jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
+        jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
+
+        jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
+
+        jz4740_timer_enable(TIMER_CLOCKEVENT);
+        jz4740_timer_enable(TIMER_CLOCKSOURCE);
+}
diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c
new file mode 100644
index 000000000000..b2c015129055
--- /dev/null
+++ b/arch/mips/jz4740/timer.c
@@ -0,0 +1,48 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "timer.h"
+
+#include <asm/mach-jz4740/base.h>
+
+void __iomem *jz4740_timer_base;
+
+void jz4740_timer_enable_watchdog(void)
+{
+        writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+void jz4740_timer_disable_watchdog(void)
+{
+        writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+void __init jz4740_timer_init(void)
+{
+        jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
+
+        if (!jz4740_timer_base)
+                panic("Failed to ioremap timer registers");
+
+        /* Disable all timer clocks except for those used as system timers */
+        writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+
+        /* Timer irqs are unmasked by default, mask them */
+        writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h
new file mode 100644
index 000000000000..fca3994f2e6d
--- /dev/null
+++ b/arch/mips/jz4740/timer.h
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_TIMER_H__
+#define __MIPS_JZ4740_TIMER_H__
+
+#include <linux/module.h>
+#include <linux/io.h>
+
+#define JZ_REG_TIMER_STOP               0x0C
+#define JZ_REG_TIMER_STOP_SET           0x1C
+#define JZ_REG_TIMER_STOP_CLEAR         0x2C
+#define JZ_REG_TIMER_ENABLE             0x00
+#define JZ_REG_TIMER_ENABLE_SET         0x04
+#define JZ_REG_TIMER_ENABLE_CLEAR       0x08
+#define JZ_REG_TIMER_FLAG               0x10
+#define JZ_REG_TIMER_FLAG_SET           0x14
+#define JZ_REG_TIMER_FLAG_CLEAR         0x18
+#define JZ_REG_TIMER_MASK               0x20
+#define JZ_REG_TIMER_MASK_SET           0x24
+#define JZ_REG_TIMER_MASK_CLEAR         0x28
+
+#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
+#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
+#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
+#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
+
+#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
+#define JZ_TIMER_IRQ_FULL(x) BIT(x)
+
+#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN      BIT(9)
+#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW            BIT(8)
+#define JZ_TIMER_CTRL_PWM_ENABLE                BIT(7)
+#define JZ_TIMER_CTRL_PRESCALE_MASK             0x1c
+#define JZ_TIMER_CTRL_PRESCALE_OFFSET           0x3
+#define JZ_TIMER_CTRL_PRESCALE_1                (0 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_4                (1 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_16               (2 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_64               (3 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_256              (4 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_1024             (5 << 3)
+
+#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
+
+#define JZ_TIMER_CTRL_SRC_EXT           BIT(2)
+#define JZ_TIMER_CTRL_SRC_RTC           BIT(1)
+#define JZ_TIMER_CTRL_SRC_PCLK          BIT(0)
+
+extern void __iomem *jz4740_timer_base;
+void __init jz4740_timer_init(void);
+
+static inline void jz4740_timer_stop(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+static inline void jz4740_timer_start(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+static inline bool jz4740_timer_is_enabled(unsigned int timer)
+{
+        return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
+}
+
+static inline void jz4740_timer_enable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
+}
+
+static inline void jz4740_timer_disable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+}
+
+
+static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
+{
+        writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
+}
+
+static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
+{
+        writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
+}
+
+static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
+{
+        writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline uint16_t jz4740_timer_get_count(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline void jz4740_timer_ack_full(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_enable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_disable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
+
+static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
+{
+        writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+#endif
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 7a6ac501cbb5..06f848299785 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_IRQ_TXX9)		+= irq_txx9.o
 obj-$(CONFIG_IRQ_GT641XX)       += irq-gt641xx.o
 obj-$(CONFIG_IRQ_GIC)           += irq-gic.o
 
+obj-$(CONFIG_KPROBES)           += kprobes.o
 obj-$(CONFIG_32BIT)             += scall32-o32.o
 obj-$(CONFIG_64BIT)             += scall64-64.o
 obj-$(CONFIG_MIPS32_COMPAT)     += linux32.o ptrace32.o signal32.o
@@ -101,6 +102,4 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
 
 obj-$(CONFIG_MIPS_CPUFREQ)      += cpufreq/
 
-EXTRA_CFLAGS += -Werror
-
 CPPFLAGS_vmlinux.lds            := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index ca6c83218caa..6b30fb2caa67 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -126,7 +126,6 @@ void output_thread_defines(void)
                thread.cp0_baduaddr);
         OFFSET(THREAD_ECODE, task_struct, \
                thread.error_code);
-        OFFSET(THREAD_TRAPNO, task_struct, thread.trap_no);
         OFFSET(THREAD_TRAMP, task_struct, \
                thread.irix_trampoline);
         OFFSET(THREAD_OLDCTX, task_struct, \
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 0b2450ceb13f..2a4d50ff5e2c 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -163,7 +163,6 @@ int c0_compare_int_usable(void)
 
 int __cpuinit r4k_clockevent_init(void)
 {
-        uint64_t mips_freq = mips_hpt_frequency;
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *cd;
         unsigned int irq;
@@ -188,9 +187,9 @@ int __cpuinit r4k_clockevent_init(void)
         cd->name                = "MIPS";
         cd->features            = CLOCK_EVT_FEAT_ONESHOT;
 
+        clockevent_set_clock(cd, mips_hpt_frequency);
+
         /* Calculate the min / max delta */
-        cd->mult        = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
-        cd->shift               = 32;
         cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
         cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
 
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 408d0a07b3a3..b8bb8ba60869 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -239,7 +239,7 @@ static inline void check_daddi(void)
         panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
 }
 
-int daddiu_bug __cpuinitdata = -1;
+int daddiu_bug  = -1;
 
 static inline void check_daddiu(void)
 {
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3562b854f2cd..b1b304ea2128 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -187,6 +187,7 @@ void __init check_wait(void)
         case CPU_BCM6358:
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
+        case CPU_JZRISC:
                 cpu_wait = r4k_wait;
                 break;
 
@@ -760,6 +761,9 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
                 ok = decode_config4(c);
 
         mips_probe_watch_registers(c);
+
+        if (cpu_has_mips_r2)
+                c->core = read_c0_ebase() & 0x3ff;
 }
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
@@ -956,6 +960,22 @@ platform:
         }
 }
 
+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
+{
+        decode_configs(c);
+        /* JZRISC does not implement the CP0 counter. */
+        c->options &= ~MIPS_CPU_COUNTER;
+        switch (c->processor_id & 0xff00) {
+        case PRID_IMP_JZRISC:
+                c->cputype = CPU_JZRISC;
+                __cpu_name[cpu] = "Ingenic JZRISC";
+                break;
+        default:
+                panic("Unknown Ingenic Processor ID!");
+                break;
+        }
+}
+
 const char *__cpu_name[NR_CPUS];
 const char *__elf_platform;
 
@@ -994,6 +1014,9 @@ __cpuinit void cpu_probe(void)
         case PRID_COMP_CAVIUM:
                 cpu_probe_cavium(c, cpu);
                 break;
+        case PRID_COMP_INGENIC:
+                cpu_probe_ingenic(c, cpu);
+                break;
         }
 
         BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index 9b78ff6e9b84..1f4e2fa64140 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -50,6 +50,151 @@ static struct hard_trap_info {
         { 0, 0}                 /* Must be last */
 };
 
+struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
+{
+        { "zero", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[0]) },
+        { "at", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[1]) },
+        { "v0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[2]) },
+        { "v1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[3]) },
+        { "a0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[4]) },
+        { "a1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[5]) },
+        { "a2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[6]) },
+        { "a3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[7]) },
+        { "t0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[8]) },
+        { "t1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[9]) },
+        { "t2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[10]) },
+        { "t3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[11]) },
+        { "t4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[12]) },
+        { "t5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[13]) },
+        { "t6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[14]) },
+        { "t7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[15]) },
+        { "s0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[16]) },
+        { "s1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[17]) },
+        { "s2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[18]) },
+        { "s3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[19]) },
+        { "s4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[20]) },
+        { "s5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[21]) },
+        { "s6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[22]) },
+        { "s7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[23]) },
+        { "t8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[24]) },
+        { "t9", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[25]) },
+        { "k0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[26]) },
+        { "k1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[27]) },
+        { "gp", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[28]) },
+        { "sp", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[29]) },
+        { "s8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[30]) },
+        { "ra", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[31]) },
+        { "sr", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_status) },
+        { "lo", GDB_SIZEOF_REG, offsetof(struct pt_regs, lo) },
+        { "hi", GDB_SIZEOF_REG, offsetof(struct pt_regs, hi) },
+        { "bad", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_badvaddr) },
+        { "cause", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_cause) },
+        { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, cp0_epc) },
+        { "f0", GDB_SIZEOF_REG, 0 },
+        { "f1", GDB_SIZEOF_REG, 1 },
+        { "f2", GDB_SIZEOF_REG, 2 },
+        { "f3", GDB_SIZEOF_REG, 3 },
+        { "f4", GDB_SIZEOF_REG, 4 },
+        { "f5", GDB_SIZEOF_REG, 5 },
+        { "f6", GDB_SIZEOF_REG, 6 },
+        { "f7", GDB_SIZEOF_REG, 7 },
+        { "f8", GDB_SIZEOF_REG, 8 },
+        { "f9", GDB_SIZEOF_REG, 9 },
+        { "f10", GDB_SIZEOF_REG, 10 },
+        { "f11", GDB_SIZEOF_REG, 11 },
+        { "f12", GDB_SIZEOF_REG, 12 },
+        { "f13", GDB_SIZEOF_REG, 13 },
+        { "f14", GDB_SIZEOF_REG, 14 },
+        { "f15", GDB_SIZEOF_REG, 15 },
+        { "f16", GDB_SIZEOF_REG, 16 },
+        { "f17", GDB_SIZEOF_REG, 17 },
+        { "f18", GDB_SIZEOF_REG, 18 },
+        { "f19", GDB_SIZEOF_REG, 19 },
+        { "f20", GDB_SIZEOF_REG, 20 },
+        { "f21", GDB_SIZEOF_REG, 21 },
+        { "f22", GDB_SIZEOF_REG, 22 },
+        { "f23", GDB_SIZEOF_REG, 23 },
+        { "f24", GDB_SIZEOF_REG, 24 },
+        { "f25", GDB_SIZEOF_REG, 25 },
+        { "f26", GDB_SIZEOF_REG, 26 },
+        { "f27", GDB_SIZEOF_REG, 27 },
+        { "f28", GDB_SIZEOF_REG, 28 },
+        { "f29", GDB_SIZEOF_REG, 29 },
+        { "f30", GDB_SIZEOF_REG, 30 },
+        { "f31", GDB_SIZEOF_REG, 31 },
+        { "fsr", GDB_SIZEOF_REG, 0 },
+        { "fir", GDB_SIZEOF_REG, 0 },
+};
+
+int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
+{
+        int fp_reg;
+
+        if (regno < 0 || regno >= DBG_MAX_REG_NUM)
+                return -EINVAL;
+
+        if (dbg_reg_def[regno].offset != -1 && regno < 38) {
+                memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
+                       dbg_reg_def[regno].size);
+        } else if (current && dbg_reg_def[regno].offset != -1 && regno < 72) {
+                /* FP registers 38 -> 69 */
+                if (!(regs->cp0_status & ST0_CU1))
+                        return 0;
+                if (regno == 70) {
+                        /* Process the fcr31/fsr (register 70) */
+                        memcpy((void *)&current->thread.fpu.fcr31, mem,
+                               dbg_reg_def[regno].size);
+                        goto out_save;
+                } else if (regno == 71) {
+                        /* Ignore the fir (register 71) */
+                        goto out_save;
+                }
+                fp_reg = dbg_reg_def[regno].offset;
+                memcpy((void *)&current->thread.fpu.fpr[fp_reg], mem,
+                       dbg_reg_def[regno].size);
+out_save:
+                restore_fp(current);
+        }
+
+        return 0;
+}
+
+char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
+{
+        int fp_reg;
+
+        if (regno >= DBG_MAX_REG_NUM || regno < 0)
+                return NULL;
+
+        if (dbg_reg_def[regno].offset != -1 && regno < 38) {
+                /* First 38 registers */
+                memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
+                       dbg_reg_def[regno].size);
+        } else if (current && dbg_reg_def[regno].offset != -1 && regno < 72) {
+                /* FP registers 38 -> 69 */
+                if (!(regs->cp0_status & ST0_CU1))
+                        goto out;
+                save_fp(current);
+                if (regno == 70) {
+                        /* Process the fcr31/fsr (register 70) */
+                        memcpy(mem, (void *)&current->thread.fpu.fcr31,
+                               dbg_reg_def[regno].size);
+                        goto out;
+                } else if (regno == 71) {
+                        /* Ignore the fir (register 71) */
+                        memset(mem, 0, dbg_reg_def[regno].size);
+                        goto out;
+                }
+                fp_reg = dbg_reg_def[regno].offset;
+                memcpy(mem, (void *)&current->thread.fpu.fpr[fp_reg],
+                       dbg_reg_def[regno].size);
+        }
+
+out:
+        return dbg_reg_def[regno].name;
+
+}
+
 void arch_kgdb_breakpoint(void)
 {
         __asm__ __volatile__(
@@ -84,64 +229,6 @@ static int compute_signal(int tt)
         return SIGHUP;          /* default for things we don't know about */
 }
 
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
-        int reg;
-
-#if (KGDB_GDB_REG_SIZE == 32)
-        u32 *ptr = (u32 *)gdb_regs;
-#else
-        u64 *ptr = (u64 *)gdb_regs;
-#endif
-
-        for (reg = 0; reg < 32; reg++)
-                *(ptr++) = regs->regs[reg];
-
-        *(ptr++) = regs->cp0_status;
-        *(ptr++) = regs->lo;
-        *(ptr++) = regs->hi;
-        *(ptr++) = regs->cp0_badvaddr;
-        *(ptr++) = regs->cp0_cause;
-        *(ptr++) = regs->cp0_epc;
-
-        /* FP REGS */
-        if (!(current && (regs->cp0_status & ST0_CU1)))
-                return;
-
-        save_fp(current);
-        for (reg = 0; reg < 32; reg++)
-                *(ptr++) = current->thread.fpu.fpr[reg];
-}
-
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
-        int reg;
-
-#if (KGDB_GDB_REG_SIZE == 32)
-        const u32 *ptr = (u32 *)gdb_regs;
-#else
-        const u64 *ptr = (u64 *)gdb_regs;
-#endif
-
-        for (reg = 0; reg < 32; reg++)
-                regs->regs[reg] = *(ptr++);
-
-        regs->cp0_status = *(ptr++);
-        regs->lo = *(ptr++);
-        regs->hi = *(ptr++);
-        regs->cp0_badvaddr = *(ptr++);
-        regs->cp0_cause = *(ptr++);
-        regs->cp0_epc = *(ptr++);
-
-        /* FP REGS from current */
-        if (!(current && (regs->cp0_status & ST0_CU1)))
-                return;
-
-        for (reg = 0; reg < 32; reg++)
-                current->thread.fpu.fpr[reg] = *(ptr++);
-        restore_fp(current);
-}
-
 /*
  * Similar to regs_to_gdb_regs() except that process is sleeping and so
  * we may not be able to get all the info.
@@ -242,7 +329,7 @@ static struct notifier_block kgdb_notifier = {
 };
 
 /*
- * Handle the 's' and 'c' commands
+ * Handle the 'c' command
  */
 int kgdb_arch_handle_exception(int vector, int signo, int err_code,
                                char *remcom_in_buffer, char *remcom_out_buffer,
@@ -250,20 +337,14 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code,
 {
         char *ptr;
         unsigned long address;
-        int cpu = smp_processor_id();
 
         switch (remcom_in_buffer[0]) {
-        case 's':
         case 'c':
                 /* handle the optional parameter */
                 ptr = &remcom_in_buffer[1];
                 if (kgdb_hex2long(&ptr, &address))
                         regs->cp0_epc = address;
 
-                atomic_set(&kgdb_cpu_doing_single_step, -1);
-                if (remcom_in_buffer[0] == 's')
-                        atomic_set(&kgdb_cpu_doing_single_step, cpu);
-
                 return 0;
         }
 
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
new file mode 100644
index 000000000000..ee28683fc2ac
--- /dev/null
+++ b/arch/mips/kernel/kprobes.c
@@ -0,0 +1,557 @@
+/*
+ *  Kernel Probes (KProbes)
+ *  arch/mips/kernel/kprobes.c
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ *
+ *  Some portions copied from the powerpc version.
+ *
+ *   Copyright (C) IBM Corporation, 2002, 2004
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kprobes.h>
+#include <linux/preempt.h>
+#include <linux/kdebug.h>
+#include <linux/slab.h>
+
+#include <asm/ptrace.h>
+#include <asm/break.h>
+#include <asm/inst.h>
+
+static const union mips_instruction breakpoint_insn = {
+        .b_format = {
+                .opcode = spec_op,
+                .code = BRK_KPROBE_BP,
+                .func = break_op
+        }
+};
+
+static const union mips_instruction breakpoint2_insn = {
+        .b_format = {
+                .opcode = spec_op,
+                .code = BRK_KPROBE_SSTEPBP,
+                .func = break_op
+        }
+};
+
+DEFINE_PER_CPU(struct kprobe *, current_kprobe);
+DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
+
+static int __kprobes insn_has_delayslot(union mips_instruction insn)
+{
+        switch (insn.i_format.opcode) {
+
+                /*
+                 * This group contains:
+                 * jr and jalr are in r_format format.
+                 */
+        case spec_op:
+                switch (insn.r_format.func) {
+                case jr_op:
+                case jalr_op:
+                        break;
+                default:
+                        goto insn_ok;
+                }
+
+                /*
+                 * This group contains:
+                 * bltz_op, bgez_op, bltzl_op, bgezl_op,
+                 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
+                 */
+        case bcond_op:
+
+                /*
+                 * These are unconditional and in j_format.
+                 */
+        case jal_op:
+        case j_op:
+
+                /*
+                 * These are conditional and in i_format.
+                 */
+        case beq_op:
+        case beql_op:
+        case bne_op:
+        case bnel_op:
+        case blez_op:
+        case blezl_op:
+        case bgtz_op:
+        case bgtzl_op:
+
+                /*
+                 * These are the FPA/cp1 branch instructions.
+                 */
+        case cop1_op:
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        case lwc2_op: /* This is bbit0 on Octeon */
+        case ldc2_op: /* This is bbit032 on Octeon */
+        case swc2_op: /* This is bbit1 on Octeon */
+        case sdc2_op: /* This is bbit132 on Octeon */
+#endif
+                return 1;
+        default:
+                break;
+        }
+insn_ok:
+        return 0;
+}
+
+int __kprobes arch_prepare_kprobe(struct kprobe *p)
+{
+        union mips_instruction insn;
+        union mips_instruction prev_insn;
+        int ret = 0;
+
+        prev_insn = p->addr[-1];
+        insn = p->addr[0];
+
+        if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) {
+                pr_notice("Kprobes for branch and jump instructions are not supported\n");
+                ret = -EINVAL;
+                goto out;
+        }
+
+        /* insn: must be on special executable page on mips. */
+        p->ainsn.insn = get_insn_slot();
+        if (!p->ainsn.insn) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        /*
+         * In the kprobe->ainsn.insn[] array we store the original
+         * instruction at index zero and a break trap instruction at
+         * index one.
+         */
+
+        memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
+        p->ainsn.insn[1] = breakpoint2_insn;
+        p->opcode = *p->addr;
+
+out:
+        return ret;
+}
+
+void __kprobes arch_arm_kprobe(struct kprobe *p)
+{
+        *p->addr = breakpoint_insn;
+        flush_insn_slot(p);
+}
+
+void __kprobes arch_disarm_kprobe(struct kprobe *p)
+{
+        *p->addr = p->opcode;
+        flush_insn_slot(p);
+}
+
+void __kprobes arch_remove_kprobe(struct kprobe *p)
+{
+        free_insn_slot(p->ainsn.insn, 0);
+}
+
+static void save_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+        kcb->prev_kprobe.kp = kprobe_running();
+        kcb->prev_kprobe.status = kcb->kprobe_status;
+        kcb->prev_kprobe.old_SR = kcb->kprobe_old_SR;
+        kcb->prev_kprobe.saved_SR = kcb->kprobe_saved_SR;
+        kcb->prev_kprobe.saved_epc = kcb->kprobe_saved_epc;
+}
+
+static void restore_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+        __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
+        kcb->kprobe_status = kcb->prev_kprobe.status;
+        kcb->kprobe_old_SR = kcb->prev_kprobe.old_SR;
+        kcb->kprobe_saved_SR = kcb->prev_kprobe.saved_SR;
+        kcb->kprobe_saved_epc = kcb->prev_kprobe.saved_epc;
+}
+
+static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
+                               struct kprobe_ctlblk *kcb)
+{
+        __get_cpu_var(current_kprobe) = p;
+        kcb->kprobe_saved_SR = kcb->kprobe_old_SR = (regs->cp0_status & ST0_IE);
+        kcb->kprobe_saved_epc = regs->cp0_epc;
+}
+
+static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+{
+        regs->cp0_status &= ~ST0_IE;
+
+        /* single step inline if the instruction is a break */
+        if (p->opcode.word == breakpoint_insn.word ||
+            p->opcode.word == breakpoint2_insn.word)
+                regs->cp0_epc = (unsigned long)p->addr;
+        else
+                regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
+}
+
+static int __kprobes kprobe_handler(struct pt_regs *regs)
+{
+        struct kprobe *p;
+        int ret = 0;
+        kprobe_opcode_t *addr;
+        struct kprobe_ctlblk *kcb;
+
+        addr = (kprobe_opcode_t *) regs->cp0_epc;
+
+        /*
+         * We don't want to be preempted for the entire
+         * duration of kprobe processing
+         */
+        preempt_disable();
+        kcb = get_kprobe_ctlblk();
+
+        /* Check we're not actually recursing */
+        if (kprobe_running()) {
+                p = get_kprobe(addr);
+                if (p) {
+                        if (kcb->kprobe_status == KPROBE_HIT_SS &&
+                            p->ainsn.insn->word == breakpoint_insn.word) {
+                                regs->cp0_status &= ~ST0_IE;
+                                regs->cp0_status |= kcb->kprobe_saved_SR;
+                                goto no_kprobe;
+                        }
+                        /*
+                         * We have reentered the kprobe_handler(), since
+                         * another probe was hit while within the handler.
+                         * We here save the original kprobes variables and
+                         * just single step on the instruction of the new probe
+                         * without calling any user handlers.
+                         */
+                        save_previous_kprobe(kcb);
+                        set_current_kprobe(p, regs, kcb);
+                        kprobes_inc_nmissed_count(p);
+                        prepare_singlestep(p, regs);
+                        kcb->kprobe_status = KPROBE_REENTER;
+                        return 1;
+                } else {
+                        if (addr->word != breakpoint_insn.word) {
+                                /*
+                                 * The breakpoint instruction was removed by
+                                 * another cpu right after we hit, no further
+                                 * handling of this interrupt is appropriate
+                                 */
+                                ret = 1;
+                                goto no_kprobe;
+                        }
+                        p = __get_cpu_var(current_kprobe);
+                        if (p->break_handler && p->break_handler(p, regs))
+                                goto ss_probe;
+                }
+                goto no_kprobe;
+        }
+
+        p = get_kprobe(addr);
+        if (!p) {
+                if (addr->word != breakpoint_insn.word) {
+                        /*
+                         * The breakpoint instruction was removed right
+                         * after we hit it.  Another cpu has removed
+                         * either a probepoint or a debugger breakpoint
+                         * at this address.  In either case, no further
+                         * handling of this interrupt is appropriate.
+                         */
+                        ret = 1;
+                }
+                /* Not one of ours: let kernel handle it */
+                goto no_kprobe;
+        }
+
+        set_current_kprobe(p, regs, kcb);
+        kcb->kprobe_status = KPROBE_HIT_ACTIVE;
+
+        if (p->pre_handler && p->pre_handler(p, regs)) {
+                /* handler has already set things up, so skip ss setup */
+                return 1;
+        }
+
+ss_probe:
+        prepare_singlestep(p, regs);
+        kcb->kprobe_status = KPROBE_HIT_SS;
+        return 1;
+
+no_kprobe:
+        preempt_enable_no_resched();
+        return ret;
+
+}
+
+/*
+ * Called after single-stepping.  p->addr is the address of the
+ * instruction whose first byte has been replaced by the "break 0"
+ * instruction.  To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction.  The address of this
+ * copy is p->ainsn.insn.
+ *
+ * This function prepares to return from the post-single-step
+ * breakpoint trap.
+ */
+static void __kprobes resume_execution(struct kprobe *p,
+                                       struct pt_regs *regs,
+                                       struct kprobe_ctlblk *kcb)
+{
+        unsigned long orig_epc = kcb->kprobe_saved_epc;
+        regs->cp0_epc = orig_epc + 4;
+}
+
+static inline int post_kprobe_handler(struct pt_regs *regs)
+{
+        struct kprobe *cur = kprobe_running();
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        if (!cur)
+                return 0;
+
+        if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
+                kcb->kprobe_status = KPROBE_HIT_SSDONE;
+                cur->post_handler(cur, regs, 0);
+        }
+
+        resume_execution(cur, regs, kcb);
+
+        regs->cp0_status |= kcb->kprobe_saved_SR;
+
+        /* Restore back the original saved kprobes variables and continue. */
+        if (kcb->kprobe_status == KPROBE_REENTER) {
+                restore_previous_kprobe(kcb);
+                goto out;
+        }
+        reset_current_kprobe();
+out:
+        preempt_enable_no_resched();
+
+        return 1;
+}
+
+static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
+{
+        struct kprobe *cur = kprobe_running();
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
+                return 1;
+
+        if (kcb->kprobe_status & KPROBE_HIT_SS) {
+                resume_execution(cur, regs, kcb);
+                regs->cp0_status |= kcb->kprobe_old_SR;
+
+                reset_current_kprobe();
+                preempt_enable_no_resched();
+        }
+        return 0;
+}
+
+/*
+ * Wrapper routine for handling exceptions.
+ */
+int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
+                                       unsigned long val, void *data)
+{
+
+        struct die_args *args = (struct die_args *)data;
+        int ret = NOTIFY_DONE;
+
+        switch (val) {
+        case DIE_BREAK:
+                if (kprobe_handler(args->regs))
+                        ret = NOTIFY_STOP;
+                break;
+        case DIE_SSTEPBP:
+                if (post_kprobe_handler(args->regs))
+                        ret = NOTIFY_STOP;
+                break;
+
+        case DIE_PAGE_FAULT:
+                /* kprobe_running() needs smp_processor_id() */
+                preempt_disable();
+
+                if (kprobe_running()
+                    && kprobe_fault_handler(args->regs, args->trapnr))
+                        ret = NOTIFY_STOP;
+                preempt_enable();
+                break;
+        default:
+                break;
+        }
+        return ret;
+}
+
+int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        struct jprobe *jp = container_of(p, struct jprobe, kp);
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        kcb->jprobe_saved_regs = *regs;
+        kcb->jprobe_saved_sp = regs->regs[29];
+
+        memcpy(kcb->jprobes_stack, (void *)kcb->jprobe_saved_sp,
+               MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
+
+        regs->cp0_epc = (unsigned long)(jp->entry);
+
+        return 1;
+}
+
+/* Defined in the inline asm below. */
+void jprobe_return_end(void);
+
+void __kprobes jprobe_return(void)
+{
+        /* Assembler quirk necessitates this '0,code' business.  */
+        asm volatile(
+                "break 0,%0\n\t"
+                ".globl jprobe_return_end\n"
+                "jprobe_return_end:\n"
+                : : "n" (BRK_KPROBE_BP) : "memory");
+}
+
+int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        if (regs->cp0_epc >= (unsigned long)jprobe_return &&
+            regs->cp0_epc <= (unsigned long)jprobe_return_end) {
+                *regs = kcb->jprobe_saved_regs;
+                memcpy((void *)kcb->jprobe_saved_sp, kcb->jprobes_stack,
+                       MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
+                preempt_enable_no_resched();
+
+                return 1;
+        }
+        return 0;
+}
+
+/*
+ * Function return probe trampoline:
+ *      - init_kprobes() establishes a probepoint here
+ *      - When the probed function returns, this probe causes the
+ *        handlers to fire
+ */
+static void __used kretprobe_trampoline_holder(void)
+{
+        asm volatile(
+                ".set push\n\t"
+                /* Keep the assembler from reordering and placing JR here. */
+                ".set noreorder\n\t"
+                "nop\n\t"
+                ".global kretprobe_trampoline\n"
+                "kretprobe_trampoline:\n\t"
+                "nop\n\t"
+                ".set pop"
+                : : : "memory");
+}
+
+void kretprobe_trampoline(void);
+
+void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
+                                      struct pt_regs *regs)
+{
+        ri->ret_addr = (kprobe_opcode_t *) regs->regs[31];
+
+        /* Replace the return addr with trampoline addr */
+        regs->regs[31] = (unsigned long)kretprobe_trampoline;
+}
+
+/*
+ * Called when the probe at kretprobe trampoline is hit
+ */
+static int __kprobes trampoline_probe_handler(struct kprobe *p,
+                                                struct pt_regs *regs)
+{
+        struct kretprobe_instance *ri = NULL;
+        struct hlist_head *head, empty_rp;
+        struct hlist_node *node, *tmp;
+        unsigned long flags, orig_ret_address = 0;
+        unsigned long trampoline_address = (unsigned long)kretprobe_trampoline;
+
+        INIT_HLIST_HEAD(&empty_rp);
+        kretprobe_hash_lock(current, &head, &flags);
+
+        /*
+         * It is possible to have multiple instances associated with a given
+         * task either because an multiple functions in the call path
+         * have a return probe installed on them, and/or more than one return
+         * return probe was registered for a target function.
+         *
+         * We can handle this because:
+         *     - instances are always inserted at the head of the list
+         *     - when multiple return probes are registered for the same
+         *       function, the first instance's ret_addr will point to the
+         *       real return address, and all the rest will point to
+         *       kretprobe_trampoline
+         */
+        hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
+                if (ri->task != current)
+                        /* another task is sharing our hash bucket */
+                        continue;
+
+                if (ri->rp && ri->rp->handler)
+                        ri->rp->handler(ri, regs);
+
+                orig_ret_address = (unsigned long)ri->ret_addr;
+                recycle_rp_inst(ri, &empty_rp);
+
+                if (orig_ret_address != trampoline_address)
+                        /*
+                         * This is the real return address. Any other
+                         * instances associated with this task are for
+                         * other calls deeper on the call stack
+                         */
+                        break;
+        }
+
+        kretprobe_assert(ri, orig_ret_address, trampoline_address);
+        instruction_pointer(regs) = orig_ret_address;
+
+        reset_current_kprobe();
+        kretprobe_hash_unlock(current, &flags);
+        preempt_enable_no_resched();
+
+        hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) {
+                hlist_del(&ri->hlist);
+                kfree(ri);
+        }
+        /*
+         * By returning a non-zero value, we are telling
+         * kprobe_handler() that we don't want the post_handler
+         * to run (and have re-enabled preemption)
+         */
+        return 1;
+}
+
+int __kprobes arch_trampoline_kprobe(struct kprobe *p)
+{
+        if (p->addr == (kprobe_opcode_t *)kretprobe_trampoline)
+                return 1;
+
+        return 0;
+}
+
+static struct kprobe trampoline_p = {
+        .addr = (kprobe_opcode_t *)kretprobe_trampoline,
+        .pre_handler = trampoline_probe_handler
+};
+
+int __init arch_init_kprobes(void)
+{
+        return register_kprobe(&trampoline_p);
+}
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 6bfcb7a00ec6..4c968e7efb74 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -165,12 +165,12 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra)
 
         /* arg3: Get frame pointer of current stack */
 #ifdef CONFIG_FRAME_POINTER
-         move   a2, fp
+        move    a2, fp
 #else /* ! CONFIG_FRAME_POINTER */
 #ifdef CONFIG_64BIT
-         PTR_LA a2, PT_SIZE(sp)
+        PTR_LA  a2, PT_SIZE(sp)
 #else
-         PTR_LA a2, (PT_SIZE+8)(sp)
+        PTR_LA  a2, (PT_SIZE+8)(sp)
 #endif
 #endif
 
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index a4faceea9d88..a3d66137731a 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -400,22 +400,22 @@ EXPORT(sysn32_call_table)
         PTR     sys_ioprio_set
         PTR     sys_ioprio_get
         PTR     compat_sys_utimensat
-        PTR     compat_sys_signalfd             /* 5280 */
+        PTR     compat_sys_signalfd             /* 6280 */
         PTR     sys_ni_syscall
         PTR     sys_eventfd
         PTR     sys_fallocate
         PTR     sys_timerfd_create
-        PTR     compat_sys_timerfd_gettime      /* 5285 */
+        PTR     compat_sys_timerfd_gettime      /* 6285 */
         PTR     compat_sys_timerfd_settime
         PTR     sys_signalfd4
         PTR     sys_eventfd2
         PTR     sys_epoll_create1
-        PTR     sys_dup3                        /* 5290 */
+        PTR     sys_dup3                        /* 6290 */
         PTR     sys_pipe2
         PTR     sys_inotify_init1
         PTR     sys_preadv
         PTR     sys_pwritev
-        PTR     compat_sys_rt_tgsigqueueinfo    /* 5295 */
+        PTR     compat_sys_rt_tgsigqueueinfo    /* 6295 */
         PTR     sys_perf_event_open
         PTR     sys_accept4
         PTR     compat_sys_recvmmsg
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 6cdca1956b77..383aeb95cb49 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -47,8 +47,12 @@
 #endif /* CONFIG_MIPS_MT_SMTC */
 
 volatile cpumask_t cpu_callin_map;      /* Bitmask of started secondaries */
+
 int __cpu_number_map[NR_CPUS];          /* Map physical to logical */
+EXPORT_SYMBOL(__cpu_number_map);
+
 int __cpu_logical_map[NR_CPUS];         /* Map logical to physical */
+EXPORT_SYMBOL(__cpu_logical_map);
 
 /* Number of TCs (or siblings in Intel speak) per CPU core */
 int smp_num_siblings = 1;
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a95dea5459c4..cfeb2c155896 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -975,8 +975,7 @@ void ipi_decode(struct smtc_ipi *pipi)
                         ipi_call_interrupt();
                         break;
                 default:
-                        printk("Impossible SMTC IPI Argument 0x%x\n",
-                                (int)arg_copy);
+                        printk("Impossible SMTC IPI Argument %p\n", arg_copy);
                         break;
                 }
                 break;
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index dd81b0f87518..58bab2ef257f 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -29,6 +29,8 @@
 #include <linux/ipc.h>
 #include <linux/uaccess.h>
 #include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/elf.h>
 
 #include <asm/asm.h>
 #include <asm/branch.h>
@@ -116,7 +118,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
                     (!vmm || addr + len <= vmm->vm_start))
                         return addr;
         }
-        addr = TASK_UNMAPPED_BASE;
+        addr = current->mm->mmap_base;
         if (do_color_align)
                 addr = COLOUR_ALIGN(addr, pgoff);
         else
@@ -134,6 +136,51 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
         }
 }
 
+void arch_pick_mmap_layout(struct mm_struct *mm)
+{
+        unsigned long random_factor = 0UL;
+
+        if (current->flags & PF_RANDOMIZE) {
+                random_factor = get_random_int();
+                random_factor = random_factor << PAGE_SHIFT;
+                if (TASK_IS_32BIT_ADDR)
+                        random_factor &= 0xfffffful;
+                else
+                        random_factor &= 0xffffffful;
+        }
+
+        mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
+        mm->get_unmapped_area = arch_get_unmapped_area;
+        mm->unmap_area = arch_unmap_area;
+}
+
+static inline unsigned long brk_rnd(void)
+{
+        unsigned long rnd = get_random_int();
+
+        rnd = rnd << PAGE_SHIFT;
+        /* 8MB for 32bit, 256MB for 64bit */
+        if (TASK_IS_32BIT_ADDR)
+                rnd = rnd & 0x7ffffful;
+        else
+                rnd = rnd & 0xffffffful;
+
+        return rnd;
+}
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+        unsigned long base = mm->brk;
+        unsigned long ret;
+
+        ret = PAGE_ALIGN(base + brk_rnd());
+
+        if (ret < mm->brk)
+                return mm->brk;
+
+        return ret;
+}
+
 SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
         unsigned long, prot, unsigned long, flags, unsigned long,
         fd, off_t, offset)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 852780868fb4..03ec0019032b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -25,6 +25,7 @@
 #include <linux/ptrace.h>
 #include <linux/kgdb.h>
 #include <linux/kdebug.h>
+#include <linux/kprobes.h>
 #include <linux/notifier.h>
 #include <linux/kdb.h>
 
@@ -334,7 +335,7 @@ void show_regs(struct pt_regs *regs)
         __show_regs((struct pt_regs *)regs);
 }
 
-void show_registers(const struct pt_regs *regs)
+void show_registers(struct pt_regs *regs)
 {
         const int field = 2 * sizeof(unsigned long);
 
@@ -356,9 +357,14 @@ void show_registers(const struct pt_regs *regs)
         printk("\n");
 }
 
+static int regs_to_trapnr(struct pt_regs *regs)
+{
+        return (regs->cp0_cause >> 2) & 0x1f;
+}
+
 static DEFINE_SPINLOCK(die_lock);
 
-void __noreturn die(const char * str, struct pt_regs * regs)
+void __noreturn die(const char *str, struct pt_regs *regs)
 {
         static int die_counter;
         int sig = SIGSEGV;
@@ -366,7 +372,7 @@ void __noreturn die(const char * str, struct pt_regs * regs)
         unsigned long dvpret = dvpe();
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-        notify_die(DIE_OOPS, str, (struct pt_regs *)regs, SIGSEGV, 0, 0);
+        notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV);
 
         console_verbose();
         spin_lock_irq(&die_lock);
@@ -375,7 +381,7 @@ void __noreturn die(const char * str, struct pt_regs * regs)
         mips_mt_regdump(dvpret);
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-        if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP)
+        if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
                 sig = 0;
 
         printk("%s[#%d]:\n", str, ++die_counter);
@@ -449,7 +455,7 @@ asmlinkage void do_be(struct pt_regs *regs)
         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
                data ? "Data" : "Instruction",
                field, regs->cp0_epc, field, regs->regs[31]);
-        if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
+        if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
             == NOTIFY_STOP)
                 return;
 
@@ -650,7 +656,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 {
         siginfo_t info;
 
-        if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
+        if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
             == NOTIFY_STOP)
                 return;
         die_if_kernel("FP exception in kernel code", regs);
@@ -713,11 +719,11 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
         char b[40];
 
 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
-        if (kgdb_ll_trap(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
+        if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
                 return;
 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
 
-        if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
+        if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
                 return;
 
         /*
@@ -783,6 +789,25 @@ asmlinkage void do_bp(struct pt_regs *regs)
         if (bcode >= (1 << 10))
                 bcode >>= 10;
 
+        /*
+         * notify the kprobe handlers, if instruction is likely to
+         * pertain to them.
+         */
+        switch (bcode) {
+        case BRK_KPROBE_BP:
+                if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
+                        return;
+                else
+                        break;
+        case BRK_KPROBE_SSTEPBP:
+                if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
+                        return;
+                else
+                        break;
+        default:
+                break;
+        }
+
         do_trap_or_bp(regs, bcode, "Break");
         return;
 
@@ -815,7 +840,7 @@ asmlinkage void do_ri(struct pt_regs *regs)
         unsigned int opcode = 0;
         int status = -1;
 
-        if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
+        if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
             == NOTIFY_STOP)
                 return;
 
@@ -907,11 +932,6 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
         return NOTIFY_OK;
 }
 
-static struct notifier_block default_cu2_notifier = {
-        .notifier_call  = default_cu2_call,
-        .priority       = 0x80000000,           /* Run last  */
-};
-
 asmlinkage void do_cpu(struct pt_regs *regs)
 {
         unsigned int __user *epc;
@@ -1734,5 +1754,5 @@ void __init trap_init(void)
 
         sort_extable(__start___dbe_table, __stop___dbe_table);
 
-        register_cu2_notifier(&default_cu2_notifier);
+        cu2_notifier(default_cu2_call, 0x80000000);     /* Run last  */
 }
diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile
index 33791609fe99..9cc4e4db8b99 100644
--- a/arch/mips/lasat/Makefile
+++ b/arch/mips/lasat/Makefile
@@ -12,5 +12,3 @@ obj-$(CONFIG_PICVUE_PROC)	+= picvue_proc.o
 
 clean:
         make -C image clean
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lasat/Platform b/arch/mips/lasat/Platform
new file mode 100644
index 000000000000..760252828bf1
--- /dev/null
+++ b/arch/mips/lasat/Platform
@@ -0,0 +1,7 @@
+#
+# LASAT platforms
+#
+platform-$(CONFIG_LASAT)        += lasat/
+cflags-$(CONFIG_LASAT)          +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-lasat
+load-$(CONFIG_LASAT)            += 0xffffffff80000000
diff --git a/arch/mips/loongson/Platform b/arch/mips/loongson/Platform
new file mode 100644
index 000000000000..29692e5433b1
--- /dev/null
+++ b/arch/mips/loongson/Platform
@@ -0,0 +1,32 @@
+#
+# Loongson Processors' Support
+#
+
+# Only gcc >= 4.4 have Loongson specific support
+cflags-$(CONFIG_CPU_LOONGSON2)  += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2E) += \
+        $(call cc-option,-march=loongson2e,-march=r4600)
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+        $(call cc-option,-march=loongson2f,-march=r4600)
+# Enable the workarounds for Loongson2f
+ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
+  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
+    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
+  else
+    cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
+  endif
+  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
+    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
+  else
+    cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
+  endif
+endif
+
+#
+# Loongson Machines' Support
+#
+
+platform-$(CONFIG_MACH_LOONGSON) += loongson/
+cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely
+load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
+load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
index 510d4cdc2378..f12e64007347 100644
--- a/arch/mips/loongson/common/cs5536/Makefile
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -9,5 +9,3 @@ obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
 # Enable cs5536 mfgpt Timer
 #
 obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index 20e732831978..5897471dedca 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -21,19 +21,16 @@ void bonito_irqdispatch(void)
 
         /* workaround the IO dma problem: let cpu looping to allow DMA finish */
         int_status = LOONGSON_INTISR;
-        if (int_status & (1 << 10)) {
-                while (int_status & (1 << 10)) {
-                        udelay(1);
-                        int_status = LOONGSON_INTISR;
-                }
+        while (int_status & (1 << 10)) {
+                udelay(1);
+                int_status = LOONGSON_INTISR;
         }
 
         /* Get pending sources, masked by current enables */
         int_status = LOONGSON_INTISR & LOONGSON_INTEN;
 
-        if (int_status != 0) {
+        if (int_status) {
                 i = __ffs(int_status);
-                int_status &= ~(1 << i);
                 do_IRQ(LOONGSON_IRQ_BASE + i);
         }
 }
@@ -56,9 +53,6 @@ void __init arch_init_irq(void)
          */
         clear_c0_status(ST0_IM | ST0_BEV);
 
-        /* setting irq trigger mode */
-        set_irq_trigger_mode();
-
         /* no steer */
         LOONGSON_INTSTEER = 0;
 
diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile
index 3aba5fcc09dc..b7622720c1ad 100644
--- a/arch/mips/loongson/fuloong-2e/Makefile
+++ b/arch/mips/loongson/fuloong-2e/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y += irq.o reset.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 320e9379bdd7..d61a04222b87 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -30,7 +30,7 @@ asmlinkage void mach_irq_dispatch(unsigned int pending)
         if (pending & CAUSEF_IP7)
                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & CAUSEF_IP6) /* perf counter loverflow */
-                do_IRQ(LOONGSON2_PERFCNT_IRQ);
+                do_perfcnt_IRQ();
         else if (pending & CAUSEF_IP5)
                 i8259_irqdispatch();
         else if (pending & CAUSEF_IP2)
@@ -44,13 +44,6 @@ static struct irqaction cascade_irqaction = {
         .name = "cascade",
 };
 
-void __init set_irq_trigger_mode(void)
-{
-        /* most bonito irq should be level triggered */
-        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
-            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
-}
-
 void __init mach_init_irq(void)
 {
         /* init all controller
@@ -59,6 +52,10 @@ void __init mach_init_irq(void)
          *   32-63        ------> bonito irq
          */
 
+        /* most bonito irq should be level triggered */
+        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
+
         /* Sets the first-level interrupt dispatcher. */
         mips_cpu_irq_init();
         init_i8259_irqs();
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
index 1d8b4d28a058..081db102bb98 100644
--- a/arch/mips/loongson/lemote-2f/irq.c
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -19,7 +19,6 @@
 #include <machine.h>
 
 #define LOONGSON_TIMER_IRQ      (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
-#define LOONGSON_PERFCNT_IRQ    (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
 #define LOONGSON_NORTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 6) /* bonito */
 #define LOONGSON_UART_IRQ       (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
 #define LOONGSON_SOUTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
@@ -79,9 +78,7 @@ void mach_irq_dispatch(unsigned int pending)
         if (pending & CAUSEF_IP7)
                 do_IRQ(LOONGSON_TIMER_IRQ);
         else if (pending & CAUSEF_IP6) {        /* North Bridge, Perf counter */
-#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
-                do_IRQ(LOONGSON2_PERFCNT_IRQ);
-#endif
+                do_perfcnt_IRQ();
                 bonito_irqdispatch();
         } else if (pending & CAUSEF_IP3)        /* CPU UART */
                 do_IRQ(LOONGSON_UART_IRQ);
@@ -91,13 +88,6 @@ void mach_irq_dispatch(unsigned int pending)
                 spurious_interrupt();
 }
 
-void __init set_irq_trigger_mode(void)
-{
-        /* setup cs5536 as high level trigger */
-        LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
-        LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
-}
-
 static irqreturn_t ip6_action(int cpl, void *dev_id)
 {
         return IRQ_HANDLED;
@@ -122,6 +112,10 @@ void __init mach_init_irq(void)
          *   32-63        ------> bonito irq
          */
 
+        /* setup cs5536 as high level trigger */
+        LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
+        LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
+
         /* Sets the first-level interrupt dispatcher. */
         mips_cpu_irq_init();
         init_i8259_irqs();
diff --git a/arch/mips/math-emu/Makefile b/arch/mips/math-emu/Makefile
index d547efdeedc2..96607230d9ea 100644
--- a/arch/mips/math-emu/Makefile
+++ b/arch/mips/math-emu/Makefile
@@ -10,4 +10,3 @@ obj-y	:= cp1emu.o ieee754m.o ieee754d.o ieee754dp.o ieee754sp.o ieee754.o \
            sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \
            dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o
 
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/math-emu/dp_modf.c b/arch/mips/math-emu/dp_modf.c
index 25861a42c36f..a8570e5c3efc 100644
--- a/arch/mips/math-emu/dp_modf.c
+++ b/arch/mips/math-emu/dp_modf.c
@@ -29,7 +29,7 @@
 
 /* modf function is always exact for a finite number
 */
-ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp * ip)
+ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp *ip)
 {
         COMPXDP;
 
diff --git a/arch/mips/math-emu/dp_tint.c b/arch/mips/math-emu/dp_tint.c
index 77b2b7ccf28a..24478623c117 100644
--- a/arch/mips/math-emu/dp_tint.c
+++ b/arch/mips/math-emu/dp_tint.c
@@ -69,8 +69,7 @@ int ieee754dp_tint(ieee754dp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         residue = xm << (64 - DP_MBITS + xe);
                         round = (residue >> 63) != 0;
                         sticky = (residue << 1) != 0;
diff --git a/arch/mips/math-emu/dp_tlong.c b/arch/mips/math-emu/dp_tlong.c
index d71113e07164..0f07ec2be3f9 100644
--- a/arch/mips/math-emu/dp_tlong.c
+++ b/arch/mips/math-emu/dp_tlong.c
@@ -71,8 +71,7 @@ s64 ieee754dp_tlong(ieee754dp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         /* Shifting a u64 64 times does not work,
                         * so we do it in two steps. Be aware that xe
                         * may be -1 */
diff --git a/arch/mips/math-emu/sp_modf.c b/arch/mips/math-emu/sp_modf.c
index 4b1dbac796f8..76568946b4c0 100644
--- a/arch/mips/math-emu/sp_modf.c
+++ b/arch/mips/math-emu/sp_modf.c
@@ -29,7 +29,7 @@
 
 /* modf function is always exact for a finite number
 */
-ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp * ip)
+ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp *ip)
 {
         COMPXSP;
 
diff --git a/arch/mips/math-emu/sp_tint.c b/arch/mips/math-emu/sp_tint.c
index 1d73d2abe0b5..352dc3a5f1af 100644
--- a/arch/mips/math-emu/sp_tint.c
+++ b/arch/mips/math-emu/sp_tint.c
@@ -72,8 +72,7 @@ int ieee754sp_tint(ieee754sp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         /* Shifting a u32 32 times does not work,
                         * so we do it in two steps. Be aware that xe
                         * may be -1 */
diff --git a/arch/mips/math-emu/sp_tlong.c b/arch/mips/math-emu/sp_tlong.c
index 4be21aa81fbf..92cd9c511a10 100644
--- a/arch/mips/math-emu/sp_tlong.c
+++ b/arch/mips/math-emu/sp_tlong.c
@@ -71,8 +71,7 @@ s64 ieee754sp_tlong(ieee754sp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         residue = xm << (32 - SP_MBITS + xe);
                         round = (residue >> 31) != 0;
                         sticky = (residue << 1) != 0;
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 41b96571315e..01410a3f1729 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -21,5 +21,3 @@ obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
 
 obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
 obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mipssim/Platform b/arch/mips/mipssim/Platform
new file mode 100644
index 000000000000..3df60b8a12ef
--- /dev/null
+++ b/arch/mips/mipssim/Platform
@@ -0,0 +1,6 @@
+#
+# MIPS SIM
+#
+platform-$(CONFIG_MIPS_SIM)     += mipssim/
+cflags-$(CONFIG_MIPS_SIM)       += -I$(srctree)/arch/mips/include/asm/mach-mipssim
+load-$(CONFIG_MIPS_SIM)         += 0x80100000
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index f0e435599707..d679c772d082 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -34,5 +34,3 @@ obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
 obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
 obj-$(CONFIG_MIPS_CPU_SCACHE)   += sc-mips.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index b78f7d913ca4..783ad0065fdf 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -16,8 +16,8 @@
 #include <linux/mman.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
-#include <linux/vt_kern.h>              /* For unblank_screen() */
 #include <linux/module.h>
+#include <linux/kprobes.h>
 
 #include <asm/branch.h>
 #include <asm/mmu_context.h>
@@ -25,13 +25,14 @@
 #include <asm/uaccess.h>
 #include <asm/ptrace.h>
 #include <asm/highmem.h>                /* For VMALLOC_END */
+#include <linux/kdebug.h>
 
 /*
  * This routine handles page faults.  It determines the address,
  * and the problem, and then passes it off to one of the appropriate
  * routines.
  */
-asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
+asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write,
                               unsigned long address)
 {
         struct vm_area_struct * vma = NULL;
@@ -47,6 +48,17 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
                field, regs->cp0_epc);
 #endif
 
+#ifdef CONFIG_KPROBES
+        /*
+         * This is to notify the fault handler of the kprobes.  The
+         * exception code is redundant as it is also carried in REGS,
+         * but we pass it anyhow.
+         */
+        if (notify_die(DIE_PAGE_FAULT, "page fault", regs, -1,
+                       (regs->cp0_cause >> 2) & 0x1f, SIGSEGV) == NOTIFY_STOP)
+                return;
+#endif
+
         info.si_code = SEGV_MAPERR;
 
         /*
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index de69bfbf506e..1ef75cd80a0d 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -16,6 +16,7 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 #include <asm/processor.h>
+#include <asm/sections.h>
 #include <asm/cacheflush.h> /* for run_uncached() */
 
 /* Primary cache parameters. */
@@ -25,11 +26,15 @@
 /* Secondary cache parameters. */
 #define scache_size     (256*1024)      /* Fixed to 256KiB on RM7000 */
 
+/* Tertiary cache parameters */
+#define tc_lsize        32
+
 extern unsigned long icache_way_size, dcache_way_size;
+unsigned long tcache_size;
 
 #include <asm/r4kcache.h>
 
-static int rm7k_tcache_enabled;
+static int rm7k_tcache_init;
 
 /*
  * Writeback and invalidate the primary cache dcache before DMA.
@@ -46,7 +51,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
 
         blast_scache_range(addr, addr + size);
 
-        if (!rm7k_tcache_enabled)
+        if (!rm7k_tcache_init)
                 return;
 
         a = addr & ~(tc_pagesize - 1);
@@ -70,7 +75,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
 
         blast_inv_scache_range(addr, addr + size);
 
-        if (!rm7k_tcache_enabled)
+        if (!rm7k_tcache_init)
                 return;
 
         a = addr & ~(tc_pagesize - 1);
@@ -83,6 +88,45 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
         }
 }
 
+static void blast_rm7k_tcache(void)
+{
+        unsigned long start = CKSEG0ADDR(0);
+        unsigned long end = start + tcache_size;
+
+        write_c0_taglo(0);
+
+        while (start < end) {
+                cache_op(Page_Invalidate_T, start);
+                start += tc_pagesize;
+        }
+}
+
+/*
+ * This function is executed in uncached address space.
+ */
+static __cpuinit void __rm7k_tc_enable(void)
+{
+        int i;
+
+        set_c0_config(RM7K_CONF_TE);
+
+        write_c0_taglo(0);
+        write_c0_taghi(0);
+
+        for (i = 0; i < tcache_size; i += tc_lsize)
+                cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
+}
+
+static __cpuinit void rm7k_tc_enable(void)
+{
+        if (read_c0_config() & RM7K_CONF_TE)
+                return;
+
+        BUG_ON(tcache_size == 0);
+
+        run_uncached(__rm7k_tc_enable);
+}
+
 /*
  * This function is executed in uncached address space.
  */
@@ -95,16 +139,8 @@ static __cpuinit void __rm7k_sc_enable(void)
         write_c0_taglo(0);
         write_c0_taghi(0);
 
-        for (i = 0; i < scache_size; i += sc_lsize) {
-                __asm__ __volatile__ (
-                      ".set noreorder\n\t"
-                      ".set mips3\n\t"
-                      "cache %1, (%0)\n\t"
-                      ".set mips0\n\t"
-                      ".set reorder"
-                      :
-                      : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
-        }
+        for (i = 0; i < scache_size; i += sc_lsize)
+                cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
 }
 
 static __cpuinit void rm7k_sc_enable(void)
@@ -112,13 +148,29 @@ static __cpuinit void rm7k_sc_enable(void)
         if (read_c0_config() & RM7K_CONF_SE)
                 return;
 
-        printk(KERN_INFO "Enabling secondary cache...\n");
+        pr_info("Enabling secondary cache...\n");
         run_uncached(__rm7k_sc_enable);
+
+        if (rm7k_tcache_init)
+                rm7k_tc_enable();
+}
+
+static void rm7k_tc_disable(void)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        blast_rm7k_tcache();
+        clear_c0_config(RM7K_CONF_TE);
+        local_irq_save(flags);
 }
 
 static void rm7k_sc_disable(void)
 {
         clear_c0_config(RM7K_CONF_SE);
+
+        if (rm7k_tcache_init)
+                rm7k_tc_disable();
 }
 
 static struct bcache_ops rm7k_sc_ops = {
@@ -128,6 +180,52 @@ static struct bcache_ops rm7k_sc_ops = {
         .bc_inv = rm7k_sc_inv
 };
 
+/*
+ * This is a probing function like the one found in c-r4k.c, we look for the
+ * wrap around point with different addresses.
+ */
+static __cpuinit void __probe_tcache(void)
+{
+        unsigned long flags, addr, begin, end, pow2;
+
+        begin = (unsigned long) &_stext;
+        begin  &= ~((8 * 1024 * 1024) - 1);
+        end = begin + (8 * 1024 * 1024);
+
+        local_irq_save(flags);
+
+        set_c0_config(RM7K_CONF_TE);
+
+        /* Fill size-multiple lines with a valid tag */
+        pow2 = (256 * 1024);
+        for (addr = begin; addr <= end; addr = (begin + pow2)) {
+                unsigned long *p = (unsigned long *) addr;
+                __asm__ __volatile__("nop" : : "r" (*p));
+                pow2 <<= 1;
+        }
+
+        /* Load first line with a 0 tag, to check after */
+        write_c0_taglo(0);
+        write_c0_taghi(0);
+        cache_op(Index_Store_Tag_T, begin);
+
+        /* Look for the wrap-around */
+        pow2 = (512 * 1024);
+        for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
+                cache_op(Index_Load_Tag_T, addr);
+                if (!read_c0_taglo())
+                        break;
+                pow2 <<= 1;
+        }
+
+        addr -= begin;
+        tcache_size = addr;
+
+        clear_c0_config(RM7K_CONF_TE);
+
+        local_irq_restore(flags);
+}
+
 void __cpuinit rm7k_sc_init(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
@@ -147,27 +245,26 @@ void __cpuinit rm7k_sc_init(void)
         if (!(config & RM7K_CONF_SE))
                 rm7k_sc_enable();
 
+        bcops = &rm7k_sc_ops;
+
         /*
          * While we're at it let's deal with the tertiary cache.
          */
-        if (!(config & RM7K_CONF_TC)) {
-
-                /*
-                 * We can't enable the L3 cache yet. There may be board-specific
-                 * magic necessary to turn it on, and blindly asking the CPU to
-                 * start using it would may give cache errors.
-                 *
-                 * Also, board-specific knowledge may allow us to use the
-                 * CACHE Flash_Invalidate_T instruction if the tag RAM supports
-                 * it, and may specify the size of the L3 cache so we don't have
-                 * to probe it.
-                 */
-                printk(KERN_INFO "Tertiary cache present, %s enabled\n",
-                       (config & RM7K_CONF_TE) ? "already" : "not (yet)");
-
-                if ((config & RM7K_CONF_TE))
-                        rm7k_tcache_enabled = 1;
-        }
 
-        bcops = &rm7k_sc_ops;
+        rm7k_tcache_init = 0;
+        tcache_size = 0;
+
+        if (config & RM7K_CONF_TC)
+                return;
+
+        /*
+         * No efficient way to ask the hardware for the size of the tcache,
+         * so must probe for it.
+         */
+        run_uncached(__probe_tcache);
+        rm7k_tc_enable();
+        rm7k_tcache_init = 1;
+        c->tcache.linesz = tc_lsize;
+        c->tcache.ways = 1;
+        pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
 }
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 86f004dc8355..4510e61883eb 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
                 tlbw(p);
                 break;
 
+        case CPU_JZRISC:
+                tlbw(p);
+                uasm_i_nop(p);
+                break;
+
         default:
                 panic("No TLB refill handler yet (CPU type: %d)",
                       current_cpu_data.cputype);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 611d564fdcf1..d2647a4e012b 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -62,12 +62,13 @@ enum opcode {
         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
         insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
         insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
-        insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
-        insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
-        insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
-        insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
-        insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
-        insn_dins, insn_syscall
+        insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
+        insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
+        insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
+        insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
+        insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
+        insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
+        insn_dins, insn_syscall, insn_bbit0, insn_bbit1
 };
 
 struct insn {
@@ -85,7 +86,7 @@ struct insn {
          | (e) << RE_SH                                         \
          | (f) << FUNC_SH)
 
-static struct insn insn_table[] __cpuinitdata = {
+static struct insn insn_table[] __uasminitdata = {
         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
         { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
@@ -108,6 +109,7 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
         { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
+        { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
@@ -141,12 +143,14 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
         { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
         { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
+        { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_invalid, 0, 0 }
 };
 
 #undef M
 
-static inline __cpuinit u32 build_rs(u32 arg)
+static inline __uasminit u32 build_rs(u32 arg)
 {
         if (arg & ~RS_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -154,7 +158,7 @@ static inline __cpuinit u32 build_rs(u32 arg)
         return (arg & RS_MASK) << RS_SH;
 }
 
-static inline __cpuinit u32 build_rt(u32 arg)
+static inline __uasminit u32 build_rt(u32 arg)
 {
         if (arg & ~RT_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -162,7 +166,7 @@ static inline __cpuinit u32 build_rt(u32 arg)
         return (arg & RT_MASK) << RT_SH;
 }
 
-static inline __cpuinit u32 build_rd(u32 arg)
+static inline __uasminit u32 build_rd(u32 arg)
 {
         if (arg & ~RD_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -170,7 +174,7 @@ static inline __cpuinit u32 build_rd(u32 arg)
         return (arg & RD_MASK) << RD_SH;
 }
 
-static inline __cpuinit u32 build_re(u32 arg)
+static inline __uasminit u32 build_re(u32 arg)
 {
         if (arg & ~RE_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -178,7 +182,7 @@ static inline __cpuinit u32 build_re(u32 arg)
         return (arg & RE_MASK) << RE_SH;
 }
 
-static inline __cpuinit u32 build_simm(s32 arg)
+static inline __uasminit u32 build_simm(s32 arg)
 {
         if (arg > 0x7fff || arg < -0x8000)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -186,7 +190,7 @@ static inline __cpuinit u32 build_simm(s32 arg)
         return arg & 0xffff;
 }
 
-static inline __cpuinit u32 build_uimm(u32 arg)
+static inline __uasminit u32 build_uimm(u32 arg)
 {
         if (arg & ~IMM_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -194,7 +198,7 @@ static inline __cpuinit u32 build_uimm(u32 arg)
         return arg & IMM_MASK;
 }
 
-static inline __cpuinit u32 build_bimm(s32 arg)
+static inline __uasminit u32 build_bimm(s32 arg)
 {
         if (arg > 0x1ffff || arg < -0x20000)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -205,7 +209,7 @@ static inline __cpuinit u32 build_bimm(s32 arg)
         return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
 }
 
-static inline __cpuinit u32 build_jimm(u32 arg)
+static inline __uasminit u32 build_jimm(u32 arg)
 {
         if (arg & ~((JIMM_MASK) << 2))
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -213,7 +217,7 @@ static inline __cpuinit u32 build_jimm(u32 arg)
         return (arg >> 2) & JIMM_MASK;
 }
 
-static inline __cpuinit u32 build_scimm(u32 arg)
+static inline __uasminit u32 build_scimm(u32 arg)
 {
         if (arg & ~SCIMM_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -221,7 +225,7 @@ static inline __cpuinit u32 build_scimm(u32 arg)
         return (arg & SCIMM_MASK) << SCIMM_SH;
 }
 
-static inline __cpuinit u32 build_func(u32 arg)
+static inline __uasminit u32 build_func(u32 arg)
 {
         if (arg & ~FUNC_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -229,7 +233,7 @@ static inline __cpuinit u32 build_func(u32 arg)
         return arg & FUNC_MASK;
 }
 
-static inline __cpuinit u32 build_set(u32 arg)
+static inline __uasminit u32 build_set(u32 arg)
 {
         if (arg & ~SET_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -241,7 +245,7 @@ static inline __cpuinit u32 build_set(u32 arg)
  * The order of opcode arguments is implicitly left to right,
  * starting with RS and ending with FUNC or IMM.
  */
-static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
+static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
 {
         struct insn *ip = NULL;
         unsigned int i;
@@ -291,67 +295,78 @@ static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
 Ip_u1u2u3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, a, b, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2u1u3(op)                                    \
 Ip_u2u1u3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, b, a, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u3u1u2(op)                                    \
 Ip_u3u1u2(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, b, c, a);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1u2s3(op)                                    \
 Ip_u1u2s3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, a, b, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2s3u1(op)                                    \
 Ip_u2s3u1(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, c, a, b);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2u1s3(op)                                    \
 Ip_u2u1s3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, b, a, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2u1msbu3(op)                                 \
 Ip_u2u1msbu3(op)                                        \
 {                                                       \
         build_insn(buf, insn##op, b, a, c+d-1, c);      \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1u2(op)                                      \
 Ip_u1u2(op)                                             \
 {                                                       \
         build_insn(buf, insn##op, a, b);                \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1s2(op)                                      \
 Ip_u1s2(op)                                             \
 {                                                       \
         build_insn(buf, insn##op, a, b);                \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1(op)                                        \
 Ip_u1(op)                                               \
 {                                                       \
         build_insn(buf, insn##op, a);                   \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_0(op)                                         \
 Ip_0(op)                                                \
 {                                                       \
         build_insn(buf, insn##op);                      \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 I_u2u1s3(_addiu)
 I_u3u1u2(_addu)
@@ -375,6 +390,7 @@ I_u2u1u3(_dsra)
 I_u2u1u3(_dsrl)
 I_u2u1u3(_dsrl32)
 I_u2u1u3(_drotr)
+I_u2u1u3(_drotr32)
 I_u3u1u2(_dsubu)
 I_0(_eret)
 I_u1(_j)
@@ -408,16 +424,19 @@ I_u3u1u2(_xor)
 I_u2u1u3(_xori)
 I_u2u1msbu3(_dins);
 I_u1(_syscall);
+I_u1u2s3(_bbit0);
+I_u1u2s3(_bbit1);
 
 /* Handle labels. */
-void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
+void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 {
         (*lab)->addr = addr;
         (*lab)->lab = lid;
         (*lab)++;
 }
+UASM_EXPORT_SYMBOL(uasm_build_label);
 
-int __cpuinit uasm_in_compat_space_p(long addr)
+int __uasminit uasm_in_compat_space_p(long addr)
 {
         /* Is this address in 32bit compat space? */
 #ifdef CONFIG_64BIT
@@ -426,8 +445,9 @@ int __cpuinit uasm_in_compat_space_p(long addr)
         return 1;
 #endif
 }
+UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
 
-static int __cpuinit uasm_rel_highest(long val)
+static int __uasminit uasm_rel_highest(long val)
 {
 #ifdef CONFIG_64BIT
         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
@@ -436,7 +456,7 @@ static int __cpuinit uasm_rel_highest(long val)
 #endif
 }
 
-static int __cpuinit uasm_rel_higher(long val)
+static int __uasminit uasm_rel_higher(long val)
 {
 #ifdef CONFIG_64BIT
         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
@@ -445,17 +465,19 @@ static int __cpuinit uasm_rel_higher(long val)
 #endif
 }
 
-int __cpuinit uasm_rel_hi(long val)
+int __uasminit uasm_rel_hi(long val)
 {
         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 }
+UASM_EXPORT_SYMBOL(uasm_rel_hi);
 
-int __cpuinit uasm_rel_lo(long val)
+int __uasminit uasm_rel_lo(long val)
 {
         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 }
+UASM_EXPORT_SYMBOL(uasm_rel_lo);
 
-void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
+void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 {
         if (!uasm_in_compat_space_p(addr)) {
                 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
@@ -470,8 +492,9 @@ void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
         } else
                 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
 }
+UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
 
-void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
+void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
 {
         UASM_i_LA_mostly(buf, rs, addr);
         if (uasm_rel_lo(addr)) {
@@ -481,9 +504,10 @@ void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
                         uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
         }
 }
+UASM_EXPORT_SYMBOL(UASM_i_LA);
 
 /* Handle relocations. */
-void __cpuinit
+void __uasminit
 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
 {
         (*rel)->addr = addr;
@@ -491,8 +515,9 @@ uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
         (*rel)->lab = lid;
         (*rel)++;
 }
+UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
 
-static inline void __cpuinit
+static inline void __uasminit
 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 {
         long laddr = (long)lab->addr;
@@ -509,7 +534,7 @@ __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
         }
 }
 
-void __cpuinit
+void __uasminit
 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 {
         struct uasm_label *l;
@@ -519,24 +544,27 @@ uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
                         if (rel->lab == l->lab)
                                 __resolve_relocs(rel, l);
 }
+UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
 
-void __cpuinit
+void __uasminit
 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
 {
         for (; rel->lab != UASM_LABEL_INVALID; rel++)
                 if (rel->addr >= first && rel->addr < end)
                         rel->addr += off;
 }
+UASM_EXPORT_SYMBOL(uasm_move_relocs);
 
-void __cpuinit
+void __uasminit
 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
 {
         for (; lab->lab != UASM_LABEL_INVALID; lab++)
                 if (lab->addr >= first && lab->addr < end)
                         lab->addr += off;
 }
+UASM_EXPORT_SYMBOL(uasm_move_labels);
 
-void __cpuinit
+void __uasminit
 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
                   u32 *end, u32 *target)
 {
@@ -547,8 +575,9 @@ uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
         uasm_move_relocs(rel, first, end, off);
         uasm_move_labels(lab, first, end, off);
 }
+UASM_EXPORT_SYMBOL(uasm_copy_handler);
 
-int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
+int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 {
         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
                 if (rel->addr == addr
@@ -559,61 +588,88 @@ int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 
         return 0;
 }
+UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
 
 /* Convenience functions for labeled branches. */
-void __cpuinit
+void __uasminit
 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bltz(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bltz);
 
-void __cpuinit
+void __uasminit
 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_b(p, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_b);
 
-void __cpuinit
+void __uasminit
 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_beqz(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_beqz);
 
-void __cpuinit
+void __uasminit
 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_beqzl(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_beqzl);
 
-void __cpuinit
+void __uasminit
 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
         unsigned int reg2, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bne(p, reg1, reg2, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bne);
 
-void __cpuinit
+void __uasminit
 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bnez(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bnez);
 
-void __cpuinit
+void __uasminit
 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bgezl(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bgezl);
 
-void __cpuinit
+void __uasminit
 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bgez(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bgez);
+
+void __uasminit
+uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+              unsigned int bit, int lid)
+{
+        uasm_r_mips_pc16(r, *p, lid);
+        uasm_i_bbit0(p, reg, bit, 0);
+}
+UASM_EXPORT_SYMBOL(uasm_il_bbit0);
+
+void __uasminit
+uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+              unsigned int bit, int lid)
+{
+        uasm_r_mips_pc16(r, *p, lid);
+        uasm_i_bbit1(p, reg, bit, 0);
+}
+UASM_EXPORT_SYMBOL(uasm_il_bbit1);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 32e847808df1..6079ef33b5f0 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -15,5 +15,3 @@ obj-$(CONFIG_PCI)		+= malta-pci.o
 
 # FIXME FIXME FIXME
 obj-$(CONFIG_MIPS_MT_SMTC)      += malta-smtc.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mti-malta/Platform b/arch/mips/mti-malta/Platform
new file mode 100644
index 000000000000..5b548b5a4fcf
--- /dev/null
+++ b/arch/mips/mti-malta/Platform
@@ -0,0 +1,7 @@
+#
+# MIPS Malta board
+#
+platform-$(CONFIG_MIPS_MALTA)   += mti-malta/
+cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
+load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
+all-$(CONFIG_MIPS_MALTA)        := $(COMPRESSION_FNAME).bin
diff --git a/arch/mips/nxp/pnx833x/stb22x/Makefile b/arch/mips/nxp/pnx833x/stb22x/Makefile
deleted file mode 100644
index f81c5801f455..000000000000
--- a/arch/mips/nxp/pnx833x/stb22x/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-lib-y := board.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/jbs/Makefile b/arch/mips/nxp/pnx8550/jbs/Makefile
deleted file mode 100644
index ad6a8ca7d8ce..000000000000
--- a/arch/mips/nxp/pnx8550/jbs/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-# Makefile for the NXP JBS Board.
-
-lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/stb810/Makefile b/arch/mips/nxp/pnx8550/stb810/Makefile
deleted file mode 100644
index ab91d72c5664..000000000000
--- a/arch/mips/nxp/pnx8550/stb810/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-# Makefile for the NXP STB810 Board.
-
-lib-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 03742e647657..d8080499872a 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2005-2009 Cavium Networks
+ * Copyright (C) 2005-2009, 2010 Cavium Networks
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -22,7 +22,7 @@
  * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
  * in use.
  */
-static uint64_t msi_free_irq_bitmask;
+static u64 msi_free_irq_bitmask[4];
 
 /*
  * Each bit in msi_multiple_irq_bitmask tells that the device using
@@ -30,7 +30,7 @@ static uint64_t msi_free_irq_bitmask;
  * is used so we can disable all of the MSI interrupts when a device
  * uses multiple.
  */
-static uint64_t msi_multiple_irq_bitmask;
+static u64 msi_multiple_irq_bitmask[4];
 
 /*
  * This lock controls updates to msi_free_irq_bitmask and
@@ -38,6 +38,11 @@ static uint64_t msi_multiple_irq_bitmask;
  */
 static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
 
+/*
+ * Number of MSI IRQs used. This variable is set up in
+ * the module init time.
+ */
+static int msi_irq_size;
 
 /**
  * Called when a driver request MSI interrupts instead of the
@@ -54,12 +59,13 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
 {
         struct msi_msg msg;
-        uint16_t control;
+        u16 control;
         int configured_private_bits;
         int request_private_bits;
-        int irq;
+        int irq = 0;
         int irq_step;
-        uint64_t search_mask;
+        u64 search_mask;
+        int index;
 
         /*
          * Read the MSI config to figure out how many IRQs this device
@@ -111,29 +117,31 @@ try_only_one:
          * use.
          */
         spin_lock(&msi_free_irq_bitmask_lock);
-        for (irq = 0; irq < 64; irq += irq_step) {
-                if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
-                        msi_free_irq_bitmask |= search_mask << irq;
-                        msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
-                        break;
+        for (index = 0; index < msi_irq_size/64; index++) {
+                for (irq = 0; irq < 64; irq += irq_step) {
+                        if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
+                                msi_free_irq_bitmask[index] |= search_mask << irq;
+                                msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
+                                goto msi_irq_allocated;
+                        }
                 }
         }
+msi_irq_allocated:
         spin_unlock(&msi_free_irq_bitmask_lock);
 
         /* Make sure the search for available interrupts didn't fail */
         if (irq >= 64) {
                 if (request_private_bits) {
-                        pr_err("arch_setup_msi_irq: Unable to find %d free "
-                               "interrupts, trying just one",
+                        pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
                                1 << request_private_bits);
                         request_private_bits = 0;
                         goto try_only_one;
                 } else
-                        panic("arch_setup_msi_irq: Unable to find a free MSI "
-                              "interrupt");
+                        panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
         }
 
         /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
+        irq += index*64;
         irq += OCTEON_IRQ_MSI_BIT0;
 
         switch (octeon_dma_bar_type) {
@@ -169,6 +177,34 @@ try_only_one:
         return 0;
 }
 
+int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        struct msi_desc *entry;
+        int ret;
+
+        /*
+         * MSI-X is not supported.
+         */
+        if (type == PCI_CAP_ID_MSIX)
+                return -EINVAL;
+
+        /*
+         * If an architecture wants to support multiple MSI, it needs to
+         * override arch_setup_msi_irqs()
+         */
+        if (type == PCI_CAP_ID_MSI && nvec > 1)
+                return 1;
+
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                ret = arch_setup_msi_irq(dev, entry);
+                if (ret < 0)
+                        return ret;
+                if (ret > 0)
+                        return -ENOSPC;
+        }
+
+        return 0;
+}
 
 /**
  * Called when a device no longer needs its MSI interrupts. All
@@ -179,12 +215,18 @@ try_only_one:
 void arch_teardown_msi_irq(unsigned int irq)
 {
         int number_irqs;
-        uint64_t bitmask;
+        u64 bitmask;
+        int index = 0;
+        int irq0;
 
-        if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
+        if ((irq < OCTEON_IRQ_MSI_BIT0)
+                || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
                 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
                       "MSI interrupt (%d)", irq);
+
         irq -= OCTEON_IRQ_MSI_BIT0;
+        index = irq / 64;
+        irq0 = irq % 64;
 
         /*
          * Count the number of IRQs we need to free by looking at the
@@ -192,97 +234,198 @@ void arch_teardown_msi_irq(unsigned int irq)
          * IRQ is also owned by this device.
          */
         number_irqs = 0;
-        while ((irq+number_irqs < 64) &&
-               (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
+        while ((irq0 + number_irqs < 64) &&
+               (msi_multiple_irq_bitmask[index]
+                & (1ull << (irq0 + number_irqs))))
                 number_irqs++;
         number_irqs++;
         /* Mask with one bit for each IRQ */
         bitmask = (1 << number_irqs) - 1;
         /* Shift the mask to the correct bit location */
-        bitmask <<= irq;
-        if ((msi_free_irq_bitmask & bitmask) != bitmask)
+        bitmask <<= irq0;
+        if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
                 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
                       "interrupt (%d) not in use", irq);
 
         /* Checks are done, update the in use bitmask */
         spin_lock(&msi_free_irq_bitmask_lock);
-        msi_free_irq_bitmask &= ~bitmask;
-        msi_multiple_irq_bitmask &= ~bitmask;
+        msi_free_irq_bitmask[index] &= ~bitmask;
+        msi_multiple_irq_bitmask[index] &= ~bitmask;
         spin_unlock(&msi_free_irq_bitmask_lock);
 }
 
+static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
+
+static u64 msi_rcv_reg[4];
+static u64 mis_ena_reg[4];
+
+static void octeon_irq_msi_enable_pcie(unsigned int irq)
+{
+        u64 en;
+        unsigned long flags;
+        int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
+        int irq_index = msi_number >> 6;
+        int irq_bit = msi_number & 0x3f;
+
+        raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+        en = cvmx_read_csr(mis_ena_reg[irq_index]);
+        en |= 1ull << irq_bit;
+        cvmx_write_csr(mis_ena_reg[irq_index], en);
+        cvmx_read_csr(mis_ena_reg[irq_index]);
+        raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+}
+
+static void octeon_irq_msi_disable_pcie(unsigned int irq)
+{
+        u64 en;
+        unsigned long flags;
+        int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
+        int irq_index = msi_number >> 6;
+        int irq_bit = msi_number & 0x3f;
+
+        raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+        en = cvmx_read_csr(mis_ena_reg[irq_index]);
+        en &= ~(1ull << irq_bit);
+        cvmx_write_csr(mis_ena_reg[irq_index], en);
+        cvmx_read_csr(mis_ena_reg[irq_index]);
+        raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+}
+
+static struct irq_chip octeon_irq_chip_msi_pcie = {
+        .name = "MSI",
+        .enable = octeon_irq_msi_enable_pcie,
+        .disable = octeon_irq_msi_disable_pcie,
+};
+
+static void octeon_irq_msi_enable_pci(unsigned int irq)
+{
+        /*
+         * Octeon PCI doesn't have the ability to mask/unmask MSI
+         * interrupts individually. Instead of masking/unmasking them
+         * in groups of 16, we simple assume MSI devices are well
+         * behaved. MSI interrupts are always enable and the ACK is
+         * assumed to be enough
+         */
+}
+
+static void octeon_irq_msi_disable_pci(unsigned int irq)
+{
+        /* See comment in enable */
+}
+
+static struct irq_chip octeon_irq_chip_msi_pci = {
+        .name = "MSI",
+        .enable = octeon_irq_msi_enable_pci,
+        .disable = octeon_irq_msi_disable_pci,
+};
 
 /*
  * Called by the interrupt handling code when an MSI interrupt
  * occurs.
  */
-static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
+static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
 {
-        uint64_t msi_bits;
         int irq;
+        int bit;
 
-        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
-                msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
-        else
-                msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
-        irq = fls64(msi_bits);
-        if (irq) {
-                irq += OCTEON_IRQ_MSI_BIT0 - 1;
-                if (irq_desc[irq].action) {
-                        do_IRQ(irq);
-                        return IRQ_HANDLED;
-                } else {
-                        pr_err("Spurious MSI interrupt %d\n", irq);
-                        if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                                /* These chips have PCIe */
-                                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
-                                               1ull << (irq -
-                                                        OCTEON_IRQ_MSI_BIT0));
-                        } else {
-                                /* These chips have PCI */
-                                cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
-                                               1ull << (irq -
-                                                        OCTEON_IRQ_MSI_BIT0));
-                        }
-                }
+        bit = fls64(msi_bits);
+        if (bit) {
+                bit--;
+                /* Acknowledge it first. */
+                cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
+
+                irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
+                do_IRQ(irq);
+                return IRQ_HANDLED;
         }
         return IRQ_NONE;
 }
 
+#define OCTEON_MSI_INT_HANDLER_X(x)                                     \
+static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id)       \
+{                                                                       \
+        u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]);                 \
+        return __octeon_msi_do_interrupt((x), msi_bits);                \
+}
+
+/*
+ * Create octeon_msi_interrupt{0-3} function body
+ */
+OCTEON_MSI_INT_HANDLER_X(0);
+OCTEON_MSI_INT_HANDLER_X(1);
+OCTEON_MSI_INT_HANDLER_X(2);
+OCTEON_MSI_INT_HANDLER_X(3);
 
 /*
  * Initializes the MSI interrupt handling code
  */
-int octeon_msi_initialize(void)
+int __init octeon_msi_initialize(void)
 {
+        int irq;
+        struct irq_chip *msi;
+
+        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
+                msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
+                msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
+                msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
+                msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
+                mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
+                mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
+                mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
+                mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
+                msi = &octeon_irq_chip_msi_pcie;
+        } else {
+                msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
+#define INVALID_GENERATE_ADE 0x8700000000000000ULL;
+                msi_rcv_reg[1] = INVALID_GENERATE_ADE;
+                msi_rcv_reg[2] = INVALID_GENERATE_ADE;
+                msi_rcv_reg[3] = INVALID_GENERATE_ADE;
+                mis_ena_reg[0] = INVALID_GENERATE_ADE;
+                mis_ena_reg[1] = INVALID_GENERATE_ADE;
+                mis_ena_reg[2] = INVALID_GENERATE_ADE;
+                mis_ena_reg[3] = INVALID_GENERATE_ADE;
+                msi = &octeon_irq_chip_msi_pci;
+        }
+
+        for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
+                set_irq_chip_and_handler(irq, msi, handle_simple_irq);
+
         if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[0:63]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
+                                0, "MSI[0:63]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
+
+                if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
+                                0, "MSI[64:127]", octeon_msi_interrupt1))
+                        panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
+
+                if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
+                                0, "MSI[127:191]", octeon_msi_interrupt2))
+                        panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
+
+                if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
+                                0, "MSI[192:255]", octeon_msi_interrupt3))
+                        panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
+
+                msi_irq_size = 256;
         } else if (octeon_is_pci_host()) {
-                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[0:15]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
+                                0, "MSI[0:15]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
 
-                if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[16:31]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
+                                0, "MSI[16:31]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
 
-                if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[32:47]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
+                                0, "MSI[32:47]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
 
-                if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[48:63]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
+                                0, "MSI[48:63]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
-
+                msi_irq_size = 64;
         }
         return 0;
 }
-
 subsys_initcall(octeon_msi_initialize);
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
index 749c1922d420..57d54adc9e20 100644
--- a/arch/mips/pci/ops-titan-ht.c
+++ b/arch/mips/pci/ops-titan-ht.c
@@ -32,7 +32,7 @@
 #include <asm/titan_dep.h>
 
 static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
-        int offset, u32 * val)
+        int offset, u32 *val)
 {
         volatile uint32_t address;
         int busno;
@@ -64,7 +64,7 @@ static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
 }
 
 static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn,
-        int offset, int size, u32 * val)
+        int offset, int size, u32 *val)
 {
         uint32_t dword;
 
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 6aa5c542d52d..861361e0c9af 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -402,6 +402,10 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         npei_ctl_status2.s.mps = 0;
         /* Max read request size = 128 bytes for best Octeon DMA performance */
         npei_ctl_status2.s.mrrs = 0;
+        if (pcie_port)
+                npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
+        else
+                npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
         cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
 
         /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
@@ -666,6 +670,8 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
 static int cvmx_pcie_rc_initialize(int pcie_port)
 {
         int i;
+        int base;
+        u64 addr_swizzle;
         union cvmx_ciu_soft_prst ciu_soft_prst;
         union cvmx_pescx_bist_status pescx_bist_status;
         union cvmx_pescx_bist_status2 pescx_bist_status2;
@@ -674,6 +680,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         union cvmx_npei_mem_access_subidx mem_access_subid;
         union cvmx_npei_dbg_data npei_dbg_data;
         union cvmx_pescx_ctl_status2 pescx_ctl_status2;
+        union cvmx_npei_bar1_indexx bar1_index;
 
         /*
          * Make sure we aren't trying to setup a target mode interface
@@ -918,12 +925,30 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
         cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
 
-        /*
-         * Disable Octeon's BAR1. It isn't needed in RC mode since
-         * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
-         * the 2nd 256MB of memory.
-         */
-        cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
+        /* BAR1 follows BAR2 with a gap. */
+        cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
+
+        bar1_index.u32 = 0;
+        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
+        bar1_index.s.ca = 1;       /* Not Cached */
+        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
+        bar1_index.s.addr_v = 1;   /* Valid entry */
+
+        base = pcie_port ? 16 : 0;
+
+        /* Big endian swizzle for 32-bit PEXP_NCB register. */
+#ifdef __MIPSEB__
+        addr_swizzle = 4;
+#else
+        addr_swizzle = 0;
+#endif
+        for (i = 0; i < 16; i++) {
+                cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
+                                    bar1_index.u32);
+                base++;
+                /* 256MB / 16 >> 22 == 4 */
+                bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
+        }
 
         /*
          * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
diff --git a/arch/mips/pmc-sierra/Platform b/arch/mips/pmc-sierra/Platform
new file mode 100644
index 000000000000..f092f2524c5f
--- /dev/null
+++ b/arch/mips/pmc-sierra/Platform
@@ -0,0 +1,14 @@
+#
+# PMC-Sierra MSP SOCs
+#
+platform-$(CONFIG_PMC_MSP)      += pmc-sierra/msp71xx/
+cflags-$(CONFIG_PMC_MSP)        += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
+                                        -mno-branch-likely
+load-$(CONFIG_PMC_MSP)          += 0xffffffff80100000
+
+#
+# PMC-Sierra Yosemite
+#
+platform-$(CONFIG_PMC_YOSEMITE) += pmc-sierra/yosemite/
+cflags-$(CONFIG_PMC_YOSEMITE)   += -I$(srctree)/arch/mips/include/asm/mach-yosemite
+load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
index 11769b55438c..c841f083a7f5 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -32,9 +32,6 @@
 #include <msp_int.h>
 #include <msp_regs.h>
 #include <msp_regops.h>
-#ifdef CONFIG_PMCTWILED
-#include <msp_led_macros.h>
-#endif
 
 /* For hwbutton_interrupt->initial_state */
 #define HWBUTTON_HI     0x1
@@ -82,10 +79,6 @@ static void standby_on(void *data)
         printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n");
 
         /* TODO: Put board in standby mode */
-#ifdef CONFIG_PMCTWILED
-        msp_led_turn_off(MSP_LED_PWRSTANDBY_GREEN);
-        msp_led_turn_on(MSP_LED_PWRSTANDBY_RED);
-#endif
 }
 
 static void standby_off(void *data)
@@ -94,10 +87,6 @@ static void standby_off(void *data)
                 "STANDBY switch was set to OFF (not implemented)\n");
 
         /* TODO: Take out of standby mode */
-#ifdef CONFIG_PMCTWILED
-        msp_led_turn_on(MSP_LED_PWRSTANDBY_GREEN);
-        msp_led_turn_off(MSP_LED_PWRSTANDBY_RED);
-#endif
 }
 
 static struct hwbutton_interrupt softreset_sw = {
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
index 5aec4057314e..86b98e98fb4f 100644
--- a/arch/mips/pmc-sierra/yosemite/ht-irq.c
+++ b/arch/mips/pmc-sierra/yosemite/ht-irq.c
@@ -35,18 +35,17 @@
  */
 void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
 {
-        struct pci_bus *current_bus = bus;
-        struct pci_dev *devices;
-        struct list_head *devices_link;
+        struct pci_bus *current_bus = bus;
+        struct pci_dev *devices;
+        struct list_head *devices_link;
 
         list_for_each(devices_link, &(current_bus->devices)) {
-                devices = pci_dev_b(devices_link);
-                if (devices == NULL)
-                        continue;
+                devices = pci_dev_b(devices_link);
+                if (devices == NULL)
+                        continue;
         }
 
         /*
          * PLX and SPKT related changes go here
          */
-
 }
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index 51021cfd04bc..25bbbf428be9 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -150,8 +150,4 @@ void __init arch_init_irq(void)
         mips_cpu_irq_init();
         rm7k_cpu_irq_init();
         rm9k_cpu_irq_init();
-
-#ifdef CONFIG_GDB_CONSOLE
-        register_gdb_console();
-#endif
 }
diff --git a/arch/mips/pnx833x/Makefile b/arch/mips/pnx833x/Makefile
new file mode 100644
index 000000000000..02c4698cab05
--- /dev/null
+++ b/arch/mips/pnx833x/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_SOC_PNX833X)       += common/
+obj-$(CONFIG_NXP_STB220)        += stb22x/
+obj-$(CONFIG_NXP_STB225)        += stb22x/
diff --git a/arch/mips/pnx833x/Platform b/arch/mips/pnx833x/Platform
new file mode 100644
index 000000000000..7e6ec4dbc8dd
--- /dev/null
+++ b/arch/mips/pnx833x/Platform
@@ -0,0 +1,5 @@
+# NXP STB225
+platform-$(CONFIG_SOC_PNX833X)  += pnx833x/
+cflags-$(CONFIG_SOC_PNX833X)    += -Iarch/mips/include/asm/mach-pnx833x
+load-$(CONFIG_NXP_STB220)       += 0xffffffff80001000
+load-$(CONFIG_NXP_STB225)       += 0xffffffff80001000
diff --git a/arch/mips/nxp/pnx833x/common/Makefile b/arch/mips/pnx833x/common/Makefile
index 4a16f3b503b5..1a46dd291b16 100644
--- a/arch/mips/nxp/pnx833x/common/Makefile
+++ b/arch/mips/pnx833x/common/Makefile
@@ -1,3 +1 @@
 obj-y := interrupts.o platform.o prom.o setup.o reset.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index 941916f8aaff..941916f8aaff 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/pnx833x/common/platform.c
index 01f8345a2069..01f8345a2069 100644
--- a/arch/mips/nxp/pnx833x/common/platform.c
+++ b/arch/mips/pnx833x/common/platform.c
diff --git a/arch/mips/nxp/pnx833x/common/prom.c b/arch/mips/pnx833x/common/prom.c
index 29969f90a6b0..29969f90a6b0 100644
--- a/arch/mips/nxp/pnx833x/common/prom.c
+++ b/arch/mips/pnx833x/common/prom.c
diff --git a/arch/mips/nxp/pnx833x/common/reset.c b/arch/mips/pnx833x/common/reset.c
index e0ea96d29fde..e0ea96d29fde 100644
--- a/arch/mips/nxp/pnx833x/common/reset.c
+++ b/arch/mips/pnx833x/common/reset.c
diff --git a/arch/mips/nxp/pnx833x/common/setup.c b/arch/mips/pnx833x/common/setup.c
index e51fbc4b644d..e51fbc4b644d 100644
--- a/arch/mips/nxp/pnx833x/common/setup.c
+++ b/arch/mips/pnx833x/common/setup.c
diff --git a/arch/mips/pnx833x/stb22x/Makefile b/arch/mips/pnx833x/stb22x/Makefile
new file mode 100644
index 000000000000..7b580060de50
--- /dev/null
+++ b/arch/mips/pnx833x/stb22x/Makefile
@@ -0,0 +1 @@
+obj-y := board.o
diff --git a/arch/mips/nxp/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c
index 644eb7c3210f..644eb7c3210f 100644
--- a/arch/mips/nxp/pnx833x/stb22x/board.c
+++ b/arch/mips/pnx833x/stb22x/board.c
diff --git a/arch/mips/pnx8550/Makefile b/arch/mips/pnx8550/Makefile
new file mode 100644
index 000000000000..3f7e8561437b
--- /dev/null
+++ b/arch/mips/pnx8550/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_SOC_PNX8550)       += common/
+obj-$(CONFIG_PNX8550_JBS)       += jbs/
+obj-$(CONFIG_PNX8550_STB810)    += stb810/
diff --git a/arch/mips/pnx8550/Platform b/arch/mips/pnx8550/Platform
new file mode 100644
index 000000000000..0e7fbde768d5
--- /dev/null
+++ b/arch/mips/pnx8550/Platform
@@ -0,0 +1,7 @@
+platform-$(CONFIG_SOC_PNX8550)  += pnx8550/
+
+cflags-$(CONFIG_SOC_PNX8550)    +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-pnx8550
+
+load-$(CONFIG_PNX8550_JBS)      += 0xffffffff80060000
+load-$(CONFIG_PNX8550_STB810)   += 0xffffffff80060000
diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/pnx8550/common/Makefile
index dd9e7b1f7fd3..f8ce695dc54f 100644
--- a/arch/mips/nxp/pnx8550/common/Makefile
+++ b/arch/mips/pnx8550/common/Makefile
@@ -24,5 +24,3 @@
 
 obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
 obj-$(CONFIG_PCI) += pci.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index cfed5051dc6d..cfed5051dc6d 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
diff --git a/arch/mips/pnx8550/common/pci.c b/arch/mips/pnx8550/common/pci.c
new file mode 100644
index 000000000000..98e86ddb86cc
--- /dev/null
+++ b/arch/mips/pnx8550/common/pci.c
@@ -0,0 +1,134 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <pci.h>
+#include <glb.h>
+#include <nand.h>
+
+static struct resource pci_io_resource = {
+        .start  = PNX8550_PCIIO + 0x1000,       /* reserve regacy I/O space */
+        .end    = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
+        .name   = "pci IO space",
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+        .start  = PNX8550_PCIMEM,
+        .end    = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
+        .name   = "pci memory space",
+        .flags  = IORESOURCE_MEM
+};
+
+extern struct pci_ops pnx8550_pci_ops;
+
+static struct pci_controller pnx8550_controller = {
+        .pci_ops        = &pnx8550_pci_ops,
+        .io_map_base    = PNX8550_PORT_BASE,
+        .io_resource    = &pci_io_resource,
+        .mem_resource   = &pci_mem_resource,
+};
+
+/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
+static inline unsigned long get_system_mem_size(void)
+{
+        /* Read IP2031_RANK0_ADDR_LO */
+        unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+        /* Read IP2031_RANK1_ADDR_HI */
+        unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+
+        return dram_r1_hi - dram_r0_lo + 1;
+}
+
+static int __init pnx8550_pci_setup(void)
+{
+        int pci_mem_code;
+        int mem_size = get_system_mem_size() >> 20;
+
+        /* Clear the Global 2 Register, PCI Inta Output Enable Registers
+           Bit 1:Enable DAC Powerdown
+          -> 0:DACs are enabled and are working normally
+             1:DACs are powerdown
+           Bit 0:Enable of PCI inta output
+          -> 0 = Disable PCI inta output
+             1 = Enable PCI inta output
+        */
+        PNX8550_GLB2_ENAB_INTA_O = 0;
+
+        /* Calc the PCI mem size code */
+        if (mem_size >= 128)
+                pci_mem_code = SIZE_128M;
+        else if (mem_size >= 64)
+                pci_mem_code = SIZE_64M;
+        else if (mem_size >= 32)
+                pci_mem_code = SIZE_32M;
+        else
+                pci_mem_code = SIZE_16M;
+
+        /* Set PCI_XIO registers */
+        outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
+        outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
+        outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
+        outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
+
+        /* Send memory transaction via PCI_BASE2 */
+        outl(0x00000001, PCI_BASE | PCI_IO);
+
+        /* Unlock the setup register */
+        outl(0xca, PCI_BASE | PCI_UNLOCKREG);
+
+        /*
+         * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
+         * to work, and in order for bus_to_baddr to work without any
+         * hacks.
+         */
+        outl(0x00000000, PCI_BASE | PCI_BASE10);
+
+        /*
+         *These two bars are set by default or the boot code.
+         * However, it's safer to set them here so we're not boot
+         * code dependent.
+         */
+        outl(0x1be00000, PCI_BASE | PCI_BASE14);  /* PNX MMIO */
+        outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18);  /* XIO      */
+
+        outl(PCI_EN_TA |
+             PCI_EN_PCI2MMI |
+             PCI_EN_XIO |
+             PCI_SETUP_BASE18_SIZE(SIZE_32M) |
+             PCI_SETUP_BASE18_EN |
+             PCI_SETUP_BASE14_EN |
+             PCI_SETUP_BASE10_PREF |
+             PCI_SETUP_BASE10_SIZE(pci_mem_code) |
+             PCI_SETUP_CFGMANAGE_EN |
+             PCI_SETUP_PCIARB_EN,
+             PCI_BASE |
+             PCI_SETUP);        /* PCI_SETUP */
+        outl(0x00000000, PCI_BASE | PCI_CTRL);  /* PCI_CONTROL */
+
+        register_pci_controller(&pnx8550_controller);
+
+        return 0;
+}
+
+arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/pnx8550/common/platform.c
index 5264cc09a27b..5264cc09a27b 100644
--- a/arch/mips/nxp/pnx8550/common/platform.c
+++ b/arch/mips/pnx8550/common/platform.c
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/pnx8550/common/proc.c
index 3bba5ec828e8..3bba5ec828e8 100644
--- a/arch/mips/nxp/pnx8550/common/proc.c
+++ b/arch/mips/pnx8550/common/proc.c
diff --git a/arch/mips/nxp/pnx8550/common/prom.c b/arch/mips/pnx8550/common/prom.c
index 32f70097c3c7..32f70097c3c7 100644
--- a/arch/mips/nxp/pnx8550/common/prom.c
+++ b/arch/mips/pnx8550/common/prom.c
diff --git a/arch/mips/nxp/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c
index fadd8744a6bc..fadd8744a6bc 100644
--- a/arch/mips/nxp/pnx8550/common/reset.c
+++ b/arch/mips/pnx8550/common/reset.c
diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c
new file mode 100644
index 000000000000..64246c9c875c
--- /dev/null
+++ b/arch/mips/pnx8550/common/setup.c
@@ -0,0 +1,145 @@
+/*
+ *
+ * 2.6 port, Embedded Alley Solutions, Inc
+ *
+ *  Based on Per Hallsmark, per.hallsmark@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/serial_pnx8xxx.h>
+#include <linux/pm.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/time.h>
+
+#include <glb.h>
+#include <int.h>
+#include <pci.h>
+#include <uart.h>
+#include <nand.h>
+
+extern void __init board_setup(void);
+extern void pnx8550_machine_restart(char *);
+extern void pnx8550_machine_halt(void);
+extern void pnx8550_machine_power_off(void);
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
+extern char *prom_getcmdline(void);
+
+struct resource standard_io_resources[] = {
+        {
+                .start  = 0x00,
+                .end    = 0x1f,
+                .name   = "dma1",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0x40,
+                .end    = 0x5f,
+                .name   = "timer",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0x80,
+                .end    = 0x8f,
+                .name   = "dma page reg",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0xc0,
+                .end    = 0xdf,
+                .name   = "dma2",
+                .flags  = IORESOURCE_BUSY
+        },
+};
+
+#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
+
+extern struct resource pci_io_resource;
+extern struct resource pci_mem_resource;
+
+/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
+unsigned long get_system_mem_size(void)
+{
+        /* Read IP2031_RANK0_ADDR_LO */
+        unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+        /* Read IP2031_RANK1_ADDR_HI */
+        unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+
+        return dram_r1_hi - dram_r0_lo + 1;
+}
+
+int pnx8550_console_port = -1;
+
+void __init plat_mem_setup(void)
+{
+        int i;
+        char* argptr;
+
+        board_setup();  /* board specific setup */
+
+        _machine_restart = pnx8550_machine_restart;
+        _machine_halt = pnx8550_machine_halt;
+        pm_power_off = pnx8550_machine_power_off;
+
+        /* Clear the Global 2 Register, PCI Inta Output Enable Registers
+           Bit 1:Enable DAC Powerdown
+          -> 0:DACs are enabled and are working normally
+             1:DACs are powerdown
+           Bit 0:Enable of PCI inta output
+          -> 0 = Disable PCI inta output
+             1 = Enable PCI inta output
+        */
+        PNX8550_GLB2_ENAB_INTA_O = 0;
+
+        /* IO/MEM resources. */
+        set_io_port_base(PNX8550_PORT_BASE);
+        ioport_resource.start = 0;
+        ioport_resource.end = ~0;
+        iomem_resource.start = 0;
+        iomem_resource.end = ~0;
+
+        /* Request I/O space for devices on this board */
+        for (i = 0; i < STANDARD_IO_RESOURCES; i++)
+                request_resource(&ioport_resource, standard_io_resources + i);
+
+        /* Place the Mode Control bit for GPIO pin 16 in primary function */
+        /* Pin 16 is used by UART1, UA1_TX                                */
+        outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
+                        (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
+                        PNX8550_GPIO_MC1);
+
+        argptr = prom_getcmdline();
+        if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
+                argptr += strlen("console=ttyS");
+                pnx8550_console_port = *argptr == '0' ? 0 : 1;
+
+                /* We must initialize the UART (console) before early printk */
+                /* Set LCR to 8-bit and BAUD to 38400 (no 5)                */
+                ip3106_lcr(UART_BASE, pnx8550_console_port) =
+                        PNX8XXX_UART_LCR_8BIT;
+                ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
+        }
+
+        return;
+}
diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c
index 8836c6203df0..8836c6203df0 100644
--- a/arch/mips/nxp/pnx8550/common/time.c
+++ b/arch/mips/pnx8550/common/time.c
diff --git a/arch/mips/pnx8550/jbs/Makefile b/arch/mips/pnx8550/jbs/Makefile
new file mode 100644
index 000000000000..c4dc3d53eb5c
--- /dev/null
+++ b/arch/mips/pnx8550/jbs/Makefile
@@ -0,0 +1,4 @@
+
+# Makefile for the NXP JBS Board.
+
+obj-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/pnx8550/jbs/board_setup.c
index 57dd903ca408..57dd903ca408 100644
--- a/arch/mips/nxp/pnx8550/jbs/board_setup.c
+++ b/arch/mips/pnx8550/jbs/board_setup.c
diff --git a/arch/mips/nxp/pnx8550/jbs/init.c b/arch/mips/pnx8550/jbs/init.c
index d59b4a4e5e8b..d59b4a4e5e8b 100644
--- a/arch/mips/nxp/pnx8550/jbs/init.c
+++ b/arch/mips/pnx8550/jbs/init.c
diff --git a/arch/mips/nxp/pnx8550/jbs/irqmap.c b/arch/mips/pnx8550/jbs/irqmap.c
index 7fc89842002c..7fc89842002c 100644
--- a/arch/mips/nxp/pnx8550/jbs/irqmap.c
+++ b/arch/mips/pnx8550/jbs/irqmap.c
diff --git a/arch/mips/pnx8550/stb810/Makefile b/arch/mips/pnx8550/stb810/Makefile
new file mode 100644
index 000000000000..cb4ff022f1fb
--- /dev/null
+++ b/arch/mips/pnx8550/stb810/Makefile
@@ -0,0 +1,4 @@
+
+# Makefile for the NXP STB810 Board.
+
+obj-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/pnx8550/stb810/board_setup.c
index af2a55e0b4e9..af2a55e0b4e9 100644
--- a/arch/mips/nxp/pnx8550/stb810/board_setup.c
+++ b/arch/mips/pnx8550/stb810/board_setup.c
diff --git a/arch/mips/nxp/pnx8550/stb810/irqmap.c b/arch/mips/pnx8550/stb810/irqmap.c
index 8c034963ddcd..8c034963ddcd 100644
--- a/arch/mips/nxp/pnx8550/stb810/irqmap.c
+++ b/arch/mips/pnx8550/stb810/irqmap.c
diff --git a/arch/mips/nxp/pnx8550/stb810/prom_init.c b/arch/mips/pnx8550/stb810/prom_init.c
index ca7f4ada0640..ca7f4ada0640 100644
--- a/arch/mips/nxp/pnx8550/stb810/prom_init.c
+++ b/arch/mips/pnx8550/stb810/prom_init.c
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
index 0a0d73c0564f..baf6e9092a9f 100644
--- a/arch/mips/powertv/Makefile
+++ b/arch/mips/powertv/Makefile
@@ -23,6 +23,9 @@
 # under Linux.
 #
 
-obj-y += init.o memory.o reset.o time.o powertv_setup.o asic/ pci/
+obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \
+        asic/ pci/
 
-EXTRA_CFLAGS += -Wall -Werror
+obj-$(CONFIG_USB) += powertv-usb.o
+
+EXTRA_CFLAGS += -Wall
diff --git a/arch/mips/powertv/Platform b/arch/mips/powertv/Platform
new file mode 100644
index 000000000000..4eb5af1d8eea
--- /dev/null
+++ b/arch/mips/powertv/Platform
@@ -0,0 +1,7 @@
+#
+# Cisco PowerTV Platform
+#
+platform-$(CONFIG_POWERTV)      += powertv/
+cflags-$(CONFIG_POWERTV)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-powertv
+load-$(CONFIG_POWERTV)          += 0xffffffff90800000
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
index bebfdcff0443..f0e95dc0ac97 100644
--- a/arch/mips/powertv/asic/Makefile
+++ b/arch/mips/powertv/asic/Makefile
@@ -16,8 +16,8 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 #
 
-obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \
-         irq_asic.o prealloc-calliope.o prealloc-cronus.o \
-         prealloc-cronuslite.o prealloc-zeus.o
+obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \
+        asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \
+        prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o
 
 EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 1ae6623444b2..0a170e0ffeaa 100644
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -77,7 +77,7 @@ const struct register_map calliope_register_map __initdata = {
         .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
 
         .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
-        .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
+        .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)},
         .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
         .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
         .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index 5bb64bfb508b..bbc0c122be5e 100644
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -77,13 +77,13 @@ const struct register_map cronus_register_map __initdata = {
         .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
 
         .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
-        .usb_fs = {.phys = CRONUS_ADDR(0x1C0018)},
+        .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)},
         .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
         .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
         .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
         .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
         .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
-        .ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)},
+        .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)},
         .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
         .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
         .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c
new file mode 100644
index 000000000000..91dda682752c
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-gaia.c
@@ -0,0 +1,96 @@
+/*
+ * Locations of devices in the Gaia ASIC
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       David VomLehn
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map gaia_register_map __initdata = {
+        .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000},
+        .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038},
+        .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
+
+        .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800},
+        .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804},
+        .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808},
+        .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C},
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800},
+        .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804},
+        .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808},
+        .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C},
+        .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810},
+        .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814},
+        .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818},
+        .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C},
+
+        .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800},
+        .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804},
+        .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808},
+        .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C},
+        .int_config = {.phys = GAIA_IO_BASE + 0x2A2810},
+        .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818},
+        .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830},
+        .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834},
+        .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838},
+        .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C},
+        .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880},
+        .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884},
+        .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888},
+        .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C},
+        .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890},
+        .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894},
+        .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898},
+        .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C},
+        .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0},
+        .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4},
+        .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8},
+        .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC},
+        .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0},
+        .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4},
+        .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8},
+        .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC},
+        .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4},
+
+        .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000},
+        .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024},
+        .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC},
+        .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108},
+        .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C},
+        .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014},
+        .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00},
+        .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00},
+        .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004},
+        .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C},
+        .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00},
+        .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04},
+        .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08},
+
+        .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000},
+        .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10},
+        .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14},
+        .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20},
+        .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24},
+        .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C},
+        .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30},
+        .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800},
+};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
index 095cbe10ebb9..4a05bb096476 100644
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -77,7 +77,7 @@ const struct register_map zeus_register_map __initdata = {
         .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
 
         .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
-        .usb_fs = {.phys = ZEUS_ADDR(0x1a0018)},
+        .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)},
         .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
         .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
         .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index 9ec523e4dd06..e56fa61b3991 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -1,7 +1,6 @@
 /*
- *                   ASIC Device List Intialization
  *
- * Description:  Defines the platform resources for the SA settop.
+ * Description:  Defines the platform resources for Gaia-based settops.
  *
  * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  *
@@ -19,11 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
- *
- * Description:  Defines the platform resources for the SA settop.
- *
  * NOTE: The bootloader allocates persistent memory at an address which is
  * 16 MiB below the end of the highest address in KSEG0. All fixed
  * address memory reservations must avoid this region.
@@ -39,7 +33,6 @@
 #include <linux/mm.h>
 #include <linux/platform_device.h>
 #include <linux/module.h>
-#include <linux/gfp.h>
 #include <asm/page.h>
 #include <linux/swap.h>
 #include <linux/highmem.h>
@@ -74,14 +67,13 @@ unsigned long asic_phy_base;
 unsigned long asic_base;
 EXPORT_SYMBOL(asic_base);                       /* Exported for testing */
 struct resource *gp_resources;
-static bool usb_configured;
 
 /*
  * Don't recommend to use it directly, it is usually used by kernel internally.
  * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
  */
-unsigned long phys_to_bus_offset;
-EXPORT_SYMBOL(phys_to_bus_offset);
+unsigned long phys_to_dma_offset;
+EXPORT_SYMBOL(phys_to_dma_offset);
 
 /*
  *
@@ -97,101 +89,19 @@ struct resource asic_resource = {
 };
 
 /*
- *
- * USB Host Resource Definition
- *
- */
-
-static struct resource ehci_resources[] = {
-        {
-                .parent = &asic_resource,
-                .start  = 0,
-                .end    = 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = irq_usbehci,
-                .end    = irq_usbehci,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device ehci_device = {
-        .name = "powertv-ehci",
-        .id = 0,
-        .num_resources = 2,
-        .resource = ehci_resources,
-        .dev = {
-                .dma_mask = &ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource ohci_resources[] = {
-        {
-                .parent = &asic_resource,
-                .start  = 0,
-                .end    = 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = irq_usbohci,
-                .end    = irq_usbohci,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device ohci_device = {
-        .name = "powertv-ohci",
-        .id = 0,
-        .num_resources = 2,
-        .resource = ohci_resources,
-        .dev = {
-                .dma_mask = &ohci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct platform_device *platform_devices[] = {
-        &ehci_device,
-        &ohci_device,
-};
-
-/*
- *
- * Platform Configuration and Device Initialization
- *
- */
-static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
-{
-        int en_prg, byp, pwr, nsb, val;
-        int sout;
-
-        sout = 1;
-        en_prg = 1;
-        byp = 0;
-        nsb = 1;
-        pwr = 1;
-
-        val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
-                (nsb<<1) | (disable_div_by_3<<5));
-
-        asic_write(val, usb_fs);
-        asic_write(val | (en_prg<<4), usb_fs);
-        asic_write(val | (en_prg<<4) | pwr, usb_fs);
-}
-
-/*
  * Allow override of bootloader-specified model
+ * Returns zero on success, a negative errno value on failure.  This parameter
+ * allows overriding of the bootloader-specified model.
  */
 static char __initdata cmdline[COMMAND_LINE_SIZE];
 
 #define FORCEFAMILY_PARAM       "forcefamily"
 
+/*
+ * check_forcefamily - check for, and parse, forcefamily command line parameter
+ * @forced_family:      Pointer to two-character array in which to store the
+ *                      value of the forcedfamily parameter, if any.
+ */
 static __init int check_forcefamily(unsigned char forced_family[2])
 {
         const char *p;
@@ -231,14 +141,10 @@ static __init int check_forcefamily(unsigned char forced_family[2])
  */
 static __init noinline void platform_set_family(void)
 {
-#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
-
         unsigned char forced_family[2];
         unsigned short bootldr_family;
 
-        check_forcefamily(forced_family);
-
-        if (forced_family[0] != '\0' && forced_family[1] != '\0')
+        if (check_forcefamily(forced_family) == 0)
                 bootldr_family = BOOTLDRFAMILY(forced_family[0],
                         forced_family[1]);
         else {
@@ -289,6 +195,9 @@ static __init noinline void platform_set_family(void)
         case BOOTLDRFAMILY('F', '1'):
                 platform_family = FAMILY_1500VZF;
                 break;
+        case BOOTLDRFAMILY('8', '7'):
+                platform_family = FAMILY_8700;
+                break;
         default:
                 platform_family = -1;
         }
@@ -301,24 +210,9 @@ unsigned int platform_get_family(void)
 EXPORT_SYMBOL(platform_get_family);
 
 /*
- * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
- *
- * \param     unsigned int value saved to the register.
- *
- * \return    none
- *
- */
-static void __init usb_eye_configure(unsigned int value)
-{
-        asic_write(asic_read(crt_spare) | value, crt_spare);
-}
-
-/*
  * platform_get_asic - determine the ASIC type.
  *
- * \param     none
- *
- * \return    ASIC type; ASIC_UNKNOWN if none
+ * Returns the ASIC type, or ASIC_UNKNOWN if unknown
  *
  */
 enum asic_type platform_get_asic(void)
@@ -328,93 +222,10 @@ enum asic_type platform_get_asic(void)
 EXPORT_SYMBOL(platform_get_asic);
 
 /*
- * platform_configure_usb - usb configuration based on platform type.
- * @bcm1_usb2_ctl:      value for the BCM1_USB2_CTL register, which is
- *                      quirky
- */
-static void __init platform_configure_usb(void)
-{
-        u32 bcm1_usb2_ctl;
-
-        if (usb_configured)
-                return;
-
-        switch (asic) {
-        case ASIC_ZEUS:
-        case ASIC_CRONUS:
-        case ASIC_CRONUSLITE:
-                fs_update(0x0000, 0x11, 0x02, 0);
-                bcm1_usb2_ctl = 0x803;
-                break;
-
-        case ASIC_CALLIOPE:
-                fs_update(0x0000, 0x11, 0x02, 1);
-
-                switch (platform_family) {
-                case FAMILY_1500VZE:
-                        break;
-
-                case FAMILY_1500VZF:
-                        usb_eye_configure(0x003c0000);
-                        break;
-
-                default:
-                        usb_eye_configure(0x00300000);
-                        break;
-                }
-
-                bcm1_usb2_ctl = 0x803;
-                break;
-
-        default:
-                pr_err("Unknown ASIC type: %d\n", asic);
-                break;
-        }
-
-        /* turn on USB power */
-        asic_write(0, usb2_strap);
-        /* Enable all OHCI interrupts */
-        asic_write(bcm1_usb2_ctl, usb2_control);
-        /* USB2_STBUS_OBC store32/load32 */
-        asic_write(3, usb2_stbus_obc);
-        /* USB2_STBUS_MESS_SIZE 2 packets */
-        asic_write(1, usb2_stbus_mess_size);
-        /* USB2_STBUS_CHUNK_SIZE 2 packets */
-        asic_write(1, usb2_stbus_chunk_size);
-
-        usb_configured = true;
-}
-
-/*
- * Set up the USB EHCI interface
+ * set_register_map - set ASIC register configuration
+ * @phys_base:  Physical address of the base of the ASIC registers
+ * @map:        Description of key ASIC registers
  */
-void platform_configure_usb_ehci()
-{
-        platform_configure_usb();
-}
-
-/*
- * Set up the USB OHCI interface
- */
-void platform_configure_usb_ohci()
-{
-        platform_configure_usb();
-}
-
-/*
- * Shut the USB EHCI interface down--currently a NOP
- */
-void platform_unconfigure_usb_ehci()
-{
-}
-
-/*
- * Shut the USB OHCI interface down--currently a NOP
- */
-void platform_unconfigure_usb_ohci()
-{
-}
-
 static void __init set_register_map(unsigned long phys_base,
         const struct register_map *map)
 {
@@ -526,6 +337,15 @@ void __init configure_platform(void)
                         "DVR_CAPABLE\n");
                 break;
 
+        case FAMILY_8700:
+                platform_features = FFS_CAPABLE | PCIE_CAPABLE;
+                asic = ASIC_GAIA;
+                set_register_map(GAIA_IO_BASE, &gaia_register_map);
+                gp_resources = dvr_gaia_resources;
+
+                pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n");
+                break;
+
         default:
                 pr_crit("Platform:  UNKNOWN PLATFORM\n");
                 break;
@@ -533,10 +353,10 @@ void __init configure_platform(void)
 
         switch (asic) {
         case ASIC_ZEUS:
-                phys_to_bus_offset = 0x30000000;
+                phys_to_dma_offset = 0x30000000;
                 break;
         case ASIC_CALLIOPE:
-                phys_to_bus_offset = 0x10000000;
+                phys_to_dma_offset = 0x10000000;
                 break;
         case ASIC_CRONUSLITE:
                 /* Fall through */
@@ -546,42 +366,16 @@ void __init configure_platform(void)
                  * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
                  * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
                  */
-                phys_to_bus_offset = 0x10000000;
+                phys_to_dma_offset = 0x10000000;
                 break;
         default:
-                phys_to_bus_offset = 0x00000000;
+                phys_to_dma_offset = 0x00000000;
                 break;
         }
 }
 
-/**
- * platform_devices_init - sets up USB device resourse.
- */
-static int __init platform_devices_init(void)
-{
-        pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
-
-        asic_resource.start = asic_phy_base;
-        asic_resource.end += asic_resource.start;
-
-        ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
-        ehci_resources[0].end += ehci_resources[0].start;
-
-        ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
-        ohci_resources[0].end += ohci_resources[0].start;
-
-        set_io_port_base(0);
-
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
-        return 0;
-}
-
-arch_initcall(platform_devices_init);
-
 /*
- *
- * BOOTMEM ALLOCATION
+ * RESOURCE ALLOCATION
  *
  */
 /*
@@ -603,7 +397,7 @@ void __init platform_alloc_bootmem(void)
                 int size = gp_resources[i].end - gp_resources[i].start + 1;
                 if ((gp_resources[i].start != 0) &&
                         ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
-                        reserve_bootmem(bus_to_phys(gp_resources[i].start),
+                        reserve_bootmem(dma_to_phys(gp_resources[i].start),
                                 size, 0);
                         total += gp_resources[i].end -
                                 gp_resources[i].start + 1;
@@ -627,7 +421,7 @@ void __init platform_alloc_bootmem(void)
 
                         else {
                                 gp_resources[i].start =
-                                        phys_to_bus(virt_to_phys(mem));
+                                        phys_to_dma(virt_to_phys(mem));
                                 gp_resources[i].end =
                                         gp_resources[i].start + size - 1;
                                 total += size;
@@ -691,7 +485,7 @@ static void __init pmem_setup_resource(void)
         if (resource && pmemaddr && pmemlen) {
                 /* The address provided by bootloader is in kseg0. Convert to
                  * a bus address. */
-                resource->start = phys_to_bus(pmemaddr - 0x80000000);
+                resource->start = phys_to_dma(pmemaddr - 0x80000000);
                 resource->end = resource->start + pmemlen - 1;
 
                 pr_info("persistent memory: start=0x%x  end=0x%x\n",
diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c
new file mode 100644
index 000000000000..8ac8c7aeb986
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-gaia.c
@@ -0,0 +1,589 @@
+/*
+ * Memory pre-allocations for Gaia boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       David VomLehn
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * DVR_CAPABLE GAIA RESOURCES
+ */
+struct resource dvr_gaia_resources[] __initdata = {
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * ITFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "ITFS",
+                .start  = 0x64180000,
+                /* 815,104 bytes each for 2 ITFS partitions. */
+                .end    = 0x6430DFFF,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
+                .end    = 0x64AD0000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "AvfsFileSys",
+                .start  = 0x64AD0000,
+                .end    = 0x64AD1000 - 1,  /* 4K */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+/*
+ * NON_DVR_CAPABLE GAIA RESOURCES
+ */
+struct resource non_dvr_gaia_resources[] __initdata = {
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                .end    = 0x645D2C00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        { },
+};
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
index 0afe227f1d0a..83552288e802 100644
--- a/arch/mips/powertv/init.c
+++ b/arch/mips/powertv/init.c
@@ -117,8 +117,10 @@ void __init prom_init(void)
         board_nmi_handler_setup = mips_nmi_setup;
         board_ejtag_handler_setup = mips_ejtag_setup;
 
-        if (prom_argc == 1)
+        if (prom_argc == 1) {
+                strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
                 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
+        }
 
         configure_platform();
         prom_meminit();
diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c
new file mode 100644
index 000000000000..a77c6f62fe23
--- /dev/null
+++ b/arch/mips/powertv/ioremap.c
@@ -0,0 +1,136 @@
+/*
+ *                      ioremap.c
+ *
+ * Support for mapping between dma_addr_t values a phys_addr_t values.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       David VomLehn <dvomlehn@cisco.com>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ *
+ * NOTE: The bootloader allocates persistent memory at an address which is
+ * 16 MiB below the end of the highest address in KSEG0. All fixed
+ * address memory reservations must avoid this region.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/mach-powertv/ioremap.h>
+
+/*
+ * Define the sizes of and masks for grains in physical and DMA space. The
+ * values are the same but the types are not.
+ */
+#define IOR_PHYS_GRAIN          ((phys_addr_t) 1 << IOR_LSBITS)
+#define IOR_PHYS_GRAIN_MASK     (IOR_PHYS_GRAIN - 1)
+
+#define IOR_DMA_GRAIN           ((dma_addr_t) 1 << IOR_LSBITS)
+#define IOR_DMA_GRAIN_MASK      (IOR_DMA_GRAIN - 1)
+
+/*
+ * Values that, when accessed by an index derived from a phys_addr_t and
+ * added to phys_addr_t value, yield a DMA address
+ */
+struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
+EXPORT_SYMBOL(_ior_phys_to_dma);
+
+/*
+ * Values that, when accessed by an index derived from a dma_addr_t and
+ * added to that dma_addr_t value, yield a physical address
+ */
+struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
+EXPORT_SYMBOL(_ior_dma_to_phys);
+
+/**
+ * setup_dma_to_phys - set up conversion from DMA to physical addresses
+ * @dma_idx:    Top IOR_LSBITS bits of the DMA address, i.e. an index
+ *              into the array _dma_to_phys.
+ * @delta:      Value that, when added to the DMA address, will yield the
+ *              physical address
+ * @s:          Number of bytes in the section of memory with the given delta
+ *              between DMA and physical addresses.
+ */
+static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s)
+{
+        int dma_idx, first_idx, last_idx;
+        phys_addr_t first, last;
+
+        /*
+         * Calculate the first and last indices, rounding the first up and
+         * the second down.
+         */
+        first = dma & ~IOR_DMA_GRAIN_MASK;
+        last = (dma + s - 1) & ~IOR_DMA_GRAIN_MASK;
+        first_idx = first >> IOR_LSBITS;                /* Convert to indices */
+        last_idx = last >> IOR_LSBITS;
+
+        for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++)
+                _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT;
+}
+
+/**
+ * setup_phys_to_dma - set up conversion from DMA to physical addresses
+ * @phys_idx:   Top IOR_LSBITS bits of the DMA address, i.e. an index
+ *              into the array _phys_to_dma.
+ * @delta:      Value that, when added to the DMA address, will yield the
+ *              physical address
+ * @s:          Number of bytes in the section of memory with the given delta
+ *              between DMA and physical addresses.
+ */
+static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s)
+{
+        int phys_idx, first_idx, last_idx;
+        phys_addr_t first, last;
+
+        /*
+         * Calculate the first and last indices, rounding the first up and
+         * the second down.
+         */
+        first = phys & ~IOR_PHYS_GRAIN_MASK;
+        last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK;
+        first_idx = first >> IOR_LSBITS;                /* Convert to indices */
+        last_idx = last >> IOR_LSBITS;
+
+        for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++)
+                _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT;
+}
+
+/**
+ * ioremap_add_map - add to the physical and DMA address conversion arrays
+ * @phys:       Process's view of the address of the start of the memory chunk
+ * @dma:        DMA address of the start of the memory chunk
+ * @size:       Size, in bytes, of the chunk of memory
+ *
+ * NOTE: It might be obvious, but the assumption is that all @size bytes have
+ * the same offset between the physical address and the DMA address.
+ */
+void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size)
+{
+        if (size == 0)
+                return;
+
+        if ((dma & IOR_DMA_GRAIN_MASK) != 0 ||
+                (phys & IOR_PHYS_GRAIN_MASK) != 0 ||
+                (size & IOR_PHYS_GRAIN_MASK) != 0)
+                pr_crit("Memory allocation must be in chunks of 0x%x bytes\n",
+                        IOR_PHYS_GRAIN);
+
+        setup_dma_to_phys(dma, phys - dma, size);
+        setup_phys_to_dma(phys, dma - phys, size);
+}
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
index f49eb3d0358b..73880ad29bc2 100644
--- a/arch/mips/powertv/memory.c
+++ b/arch/mips/powertv/memory.c
@@ -30,28 +30,141 @@
 #include <asm/sections.h>
 
 #include <asm/mips-boards/prom.h>
+#include <asm/mach-powertv/asic.h>
+#include <asm/mach-powertv/ioremap.h>
 
 #include "init.h"
 
 /* Memory constants */
 #define KIBIBYTE(n)             ((n) * 1024)    /* Number of kibibytes */
 #define MEBIBYTE(n)             ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
-#define DEFAULT_MEMSIZE         MEBIBYTE(256)   /* If no memsize provided */
-#define LOW_MEM_MAX             MEBIBYTE(252)   /* Max usable low mem */
-#define RES_BOOTLDR_MEMSIZE     MEBIBYTE(1)     /* Memory reserved for bldr */
-#define BOOT_MEM_SIZE           KIBIBYTE(256)   /* Memory reserved for bldr */
-#define PHYS_MEM_START          0x10000000      /* Start of physical memory */
+#define DEFAULT_MEMSIZE         MEBIBYTE(128)   /* If no memsize provided */
 
-char __initdata cmdline[COMMAND_LINE_SIZE];
+#define BLDR_SIZE       KIBIBYTE(256)           /* Memory reserved for bldr */
+#define RV_SIZE         MEBIBYTE(4)             /* Size of reset vector */
 
-void __init prom_meminit(void)
+#define LOW_MEM_END     0x20000000              /* Highest low memory address */
+#define BLDR_ALIAS      0x10000000              /* Bootloader address */
+#define RV_PHYS         0x1fc00000              /* Reset vector address */
+#define LOW_RAM_END     RV_PHYS                 /* End of real RAM in low mem */
+
+/*
+ * Very low-level conversion from processor physical address to device
+ * DMA address for the first bank of memory.
+ */
+#define PHYS_TO_DMA(paddr)      ((paddr) + (CONFIG_LOW_RAM_DMA - LOW_RAM_ALIAS))
+
+unsigned long ptv_memsize;
+
+/*
+ * struct low_mem_reserved - Items in low memmory that are reserved
+ * @start:      Physical address of item
+ * @size:       Size, in bytes, of this item
+ * @is_aliased: True if this is RAM aliased from another location. If false,
+ *              it is something other than aliased RAM and the RAM in the
+ *              unaliased address is still visible outside of low memory.
+ */
+struct low_mem_reserved {
+        phys_addr_t     start;
+        phys_addr_t     size;
+        bool            is_aliased;
+};
+
+/*
+ * Must be in ascending address order
+ */
+struct low_mem_reserved low_mem_reserved[] = {
+        {BLDR_ALIAS, BLDR_SIZE, true},  /* Bootloader RAM */
+        {RV_PHYS, RV_SIZE, false},      /* Reset vector */
+};
+
+/*
+ * struct mem_layout - layout of a piece of the system RAM
+ * @phys:       Physical address of the start of this piece of RAM. This is the
+ *              address at which both the processor and I/O devices see the
+ *              RAM.
+ * @alias:      Alias of this piece of memory in order to make it appear in
+ *              the low memory part of the processor's address space. I/O
+ *              devices don't see anything here.
+ * @size:       Size, in bytes, of this piece of RAM
+ */
+struct mem_layout {
+        phys_addr_t     phys;
+        phys_addr_t     alias;
+        phys_addr_t     size;
+};
+
+/*
+ * struct mem_layout_list - list descriptor for layouts of system RAM pieces
+ * @family:     Specifies the family being described
+ * @n:          Number of &struct mem_layout elements
+ * @layout:     Pointer to the list of &mem_layout structures
+ */
+struct mem_layout_list {
+        enum family_type        family;
+        size_t                  n;
+        struct mem_layout       *layout;
+};
+
+static struct mem_layout f1500_layout[] = {
+        {0x20000000, 0x10000000, MEBIBYTE(256)},
+};
+
+static struct mem_layout f4500_layout[] = {
+        {0x40000000, 0x10000000, MEBIBYTE(256)},
+        {0x20000000, 0x20000000, MEBIBYTE(32)},
+};
+
+static struct mem_layout f8500_layout[] = {
+        {0x40000000, 0x10000000, MEBIBYTE(256)},
+        {0x20000000, 0x20000000, MEBIBYTE(32)},
+        {0x30000000, 0x30000000, MEBIBYTE(32)},
+};
+
+static struct mem_layout fx600_layout[] = {
+        {0x20000000, 0x10000000, MEBIBYTE(256)},
+        {0x60000000, 0x60000000, MEBIBYTE(128)},
+};
+
+static struct mem_layout_list layout_list[] = {
+        {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout},
+        {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout},
+        {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout},
+        {FAMILY_4500, ARRAY_SIZE(f4500_layout), f4500_layout},
+        {FAMILY_8500, ARRAY_SIZE(f8500_layout), f8500_layout},
+        {FAMILY_8500RNG, ARRAY_SIZE(f8500_layout), f8500_layout},
+        {FAMILY_4600, ARRAY_SIZE(fx600_layout), fx600_layout},
+        {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout},
+        {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout},
+        {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout},
+};
+
+/* If we can't determine the layout, use this */
+static struct mem_layout default_layout[] = {
+        {0x20000000, 0x10000000, MEBIBYTE(128)},
+};
+
+/**
+ * register_non_ram - register low memory not available for RAM usage
+ */
+static __init void register_non_ram(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++)
+                add_memory_region(low_mem_reserved[i].start,
+                        low_mem_reserved[i].size, BOOT_MEM_RESERVED);
+}
+
+/**
+ * get_memsize - get the size of memory as a single bank
+ */
+static phys_addr_t get_memsize(void)
 {
+        static char cmdline[COMMAND_LINE_SIZE] __initdata;
+        phys_addr_t memsize = 0;
         char *memsize_str;
-        unsigned long memsize = 0;
-        unsigned int physend;
         char *ptr;
-        int low_mem;
-        int high_mem;
 
         /* Check the command line first for a memsize directive */
         strcpy(cmdline, arcs_cmdline);
@@ -73,96 +186,156 @@ void __init prom_meminit(void)
                 if (memsize == 0) {
                         if (_prom_memsize != 0) {
                                 memsize = _prom_memsize;
-                                pr_info("_prom_memsize = 0x%lx\n", memsize);
+                                pr_info("_prom_memsize = 0x%x\n", memsize);
                                 /* add in memory that the bootloader doesn't
                                  * report */
-                                memsize += BOOT_MEM_SIZE;
+                                memsize += BLDR_SIZE;
                         } else {
                                 memsize = DEFAULT_MEMSIZE;
                                 pr_info("Memsize not passed by bootloader, "
-                                        "defaulting to 0x%lx\n", memsize);
+                                        "defaulting to 0x%x\n", memsize);
                         }
                 }
         }
 
-        physend = PFN_ALIGN(&_end) - 0x80000000;
-        if (memsize > LOW_MEM_MAX) {
-                low_mem = LOW_MEM_MAX;
-                high_mem = memsize - low_mem;
-        } else {
-                low_mem = memsize;
-                high_mem = 0;
+        return memsize;
+}
+
+/**
+ * register_low_ram - register an aliased section of RAM
+ * @p:          Alias address of memory
+ * @n:          Number of bytes in this section of memory
+ *
+ * Returns the number of bytes registered
+ *
+ */
+static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n)
+{
+        phys_addr_t s;
+        int i;
+        phys_addr_t orig_n;
+
+        orig_n = n;
+
+        BUG_ON(p + n > RV_PHYS);
+
+        for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) {
+                phys_addr_t start;
+                phys_addr_t size;
+
+                start = low_mem_reserved[i].start;
+                size = low_mem_reserved[i].size;
+
+                /* Handle memory before this low memory section */
+                if (p < start) {
+                        phys_addr_t s;
+                        s = min(n, start - p);
+                        add_memory_region(p, s, BOOT_MEM_RAM);
+                        p += s;
+                        n -= s;
+                }
+
+                /* Handle the low memory section itself. If it's aliased,
+                 * we reduce the number of byes left, but if not, the RAM
+                 * is available elsewhere and we don't reduce the number of
+                 * bytes remaining. */
+                if (p == start) {
+                        if (low_mem_reserved[i].is_aliased) {
+                                s = min(n, size);
+                                n -= s;
+                                p += s;
+                        } else
+                                p += n;
+                }
         }
 
+        return orig_n - n;
+}
+
 /*
- * TODO: We will use the hard code for memory configuration until
- * the bootloader releases their device tree to us.
+ * register_ram - register real RAM
+ * @p:  Address of memory as seen by devices
+ * @alias:      If the memory is seen at an additional address by the processor,
+ *              this will be the address, otherwise it is the same as @p.
+ * @n:          Number of bytes in this section of memory
  */
+static __init void register_ram(phys_addr_t p, phys_addr_t alias,
+        phys_addr_t n)
+{
         /*
-         * Add the memory reserved for use by the bootloader to the
-         * memory map.
-         */
-        add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE,
-                BOOT_MEM_RESERVED);
-#ifdef CONFIG_HIGHMEM_256_128
-        /*
-         * Add memory in low for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         */
-        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
-                LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
-        /*
-         * Add the memory reserved for reset vector.
-         */
-        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
-        /*
-         * Add the memory reserved.
-         */
-        add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED);
-        /*
-         * Add memory in high for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         *
-         * 75MB is reserved for devices which are using the memory in high.
-         */
-        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
-                BOOT_MEM_RAM);
-#elif defined CONFIG_HIGHMEM_128_128
-        /*
-         * Add memory in low for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         */
-        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
-                MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
-        /*
-         * Add the memory reserved.
-         */
-        add_memory_region(PHYS_MEM_START + MEBIBYTE(128),
-                MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED);
-        /*
-         * Add memory in high for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         *
-         * 75MB is reserved for devices which are using the memory in high.
-         */
-        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
-                BOOT_MEM_RAM);
-#else
-        /* Add low memory regions for either:
-         *   - no-highmemory configuration case -OR-
-         *   - highmemory "HIGHMEM_LOWBANK_ONLY" case
-         */
-        /*
-         * Add memory for general use by the kernel and its friends
-         * (like drivers, applications, etc).
+         * If some or all of this memory has an alias, break it into the
+         * aliased and non-aliased portion.
          */
-        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
-                low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        if (p != alias) {
+                phys_addr_t alias_size;
+                phys_addr_t registered;
+
+                alias_size = min(n, LOW_RAM_END - alias);
+                registered = register_low_ram(alias, alias_size);
+                ioremap_add_map(alias, p, n);
+                n -= registered;
+                p += registered;
+        }
+
+#ifdef CONFIG_HIGHMEM
+        if (n != 0) {
+                add_memory_region(p, n, BOOT_MEM_RAM);
+                ioremap_add_map(p, p, n);
+        }
+#endif
+}
+
+/**
+ * register_address_space - register things in the address space
+ * @memsize:    Number of bytes of RAM installed
+ *
+ * Takes the given number of bytes of RAM and registers as many of the regions,
+ * or partial regions, as it can. So, the default configuration might have
+ * two regions with 256 MiB each. If the memsize passed in on the command line
+ * is 384 MiB, it will register the first region with 256 MiB and the second
+ * with 128 MiB.
+ */
+static __init void register_address_space(phys_addr_t memsize)
+{
+        int i;
+        phys_addr_t size;
+        size_t n;
+        struct mem_layout *layout;
+        enum family_type family;
+
         /*
-         * Add the memory reserved for reset vector.
+         * Register all of the things that aren't available to the kernel as
+         * memory.
          */
-        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
-#endif
+        register_non_ram();
+
+        /* Find the appropriate memory description */
+        family = platform_get_family();
+
+        for (i = 0; i < ARRAY_SIZE(layout_list); i++) {
+                if (layout_list[i].family == family)
+                        break;
+        }
+
+        if (i == ARRAY_SIZE(layout_list)) {
+                n = ARRAY_SIZE(default_layout);
+                layout = default_layout;
+        } else {
+                n = layout_list[i].n;
+                layout = layout_list[i].layout;
+        }
+
+        for (i = 0; memsize != 0 && i < n; i++) {
+                size = min(memsize, layout[i].size);
+                register_ram(layout[i].phys, layout[i].alias, size);
+                memsize -= size;
+        }
+}
+
+void __init prom_meminit(void)
+{
+        ptv_memsize = get_memsize();
+        register_address_space(ptv_memsize);
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c
new file mode 100644
index 000000000000..6ac85cf7aa20
--- /dev/null
+++ b/arch/mips/powertv/powertv-usb.c
@@ -0,0 +1,403 @@
+/*
+ *                              powertv-usb.c
+ *
+ * Description:  ASIC-specific USB device setup and shutdown
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ * Copyright (C) 2009 Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * NOTE: The bootloader allocates persistent memory at an address which is
+ * 16 MiB below the end of the highest address in KSEG0. All fixed
+ * address memory reservations must avoid this region.
+ */
+
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <asm/mach-powertv/asic.h>
+#include <asm/mach-powertv/interrupts.h>
+
+/* misc_clk_ctl1 values */
+#define MCC1_30MHZ_POWERUP_SELECT       (1 << 14)
+#define MCC1_DIV9                       (1 << 13)
+#define MCC1_ETHMIPS_POWERUP_SELECT     (1 << 11)
+#define MCC1_USB_POWERUP_SELECT         (1 << 1)
+#define MCC1_CLOCK108_POWERUP_SELECT    (1 << 0)
+
+/* Possible values for clock select */
+#define MCC1_USB_CLOCK_HIGH_Z           (0 << 4)
+#define MCC1_USB_CLOCK_48MHZ            (1 << 4)
+#define MCC1_USB_CLOCK_24MHZ            (2 << 4)
+#define MCC1_USB_CLOCK_6MHZ             (3 << 4)
+
+#define MCC1_CONFIG     (MCC1_30MHZ_POWERUP_SELECT |            \
+                         MCC1_DIV9 |                            \
+                         MCC1_ETHMIPS_POWERUP_SELECT |          \
+                         MCC1_USB_POWERUP_SELECT |              \
+                         MCC1_CLOCK108_POWERUP_SELECT)
+
+/* misc_clk_ctl2 values */
+#define MCC2_GMII_GCLK_TO_PAD           (1 << 31)
+#define MCC2_ETHER125_0_CLOCK_SELECT    (1 << 29)
+#define MCC2_RMII_0_CLOCK_SELECT        (1 << 28)
+#define MCC2_GMII_TX0_CLOCK_SELECT      (1 << 27)
+#define MCC2_GMII_RX0_CLOCK_SELECT      (1 << 26)
+#define MCC2_ETHER125_1_CLOCK_SELECT    (1 << 24)
+#define MCC2_RMII_1_CLOCK_SELECT        (1 << 23)
+#define MCC2_GMII_TX1_CLOCK_SELECT      (1 << 22)
+#define MCC2_GMII_RX1_CLOCK_SELECT      (1 << 21)
+#define MCC2_ETHER125_2_CLOCK_SELECT    (1 << 19)
+#define MCC2_RMII_2_CLOCK_SELECT        (1 << 18)
+#define MCC2_GMII_TX2_CLOCK_SELECT      (1 << 17)
+#define MCC2_GMII_RX2_CLOCK_SELECT      (1 << 16)
+
+#define ETHER_CLK_CONFIG        (MCC2_GMII_GCLK_TO_PAD |        \
+                                 MCC2_ETHER125_0_CLOCK_SELECT | \
+                                 MCC2_RMII_0_CLOCK_SELECT |     \
+                                 MCC2_GMII_TX0_CLOCK_SELECT |   \
+                                 MCC2_GMII_RX0_CLOCK_SELECT |   \
+                                 MCC2_ETHER125_1_CLOCK_SELECT | \
+                                 MCC2_RMII_1_CLOCK_SELECT |     \
+                                 MCC2_GMII_TX1_CLOCK_SELECT |   \
+                                 MCC2_GMII_RX1_CLOCK_SELECT |   \
+                                 MCC2_ETHER125_2_CLOCK_SELECT | \
+                                 MCC2_RMII_2_CLOCK_SELECT |     \
+                                 MCC2_GMII_TX2_CLOCK_SELECT |   \
+                                 MCC2_GMII_RX2_CLOCK_SELECT)
+
+/* misc_clk_ctl2 definitions for Gaia */
+#define FSX4A_REF_SELECT                (1 << 16)
+#define FSX4B_REF_SELECT                (1 << 17)
+#define FSX4C_REF_SELECT                (1 << 18)
+#define DDR_PLL_REF_SELECT              (1 << 19)
+#define MIPS_PLL_REF_SELECT             (1 << 20)
+
+/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
+#define QAM_FS_SDIV_SHIFT               29
+#define QAM_FS_MD_SHIFT                 24
+#define QAM_FS_MD_MASK                  0x1f    /* Cut down to 5 bits */
+#define QAM_FS_PE_SHIFT                 8
+
+#define QAM_FS_DISABLE_DIVIDE_BY_3              (1 << 5)
+#define QAM_FS_ENABLE_PROGRAM                   (1 << 4)
+#define QAM_FS_ENABLE_OUTPUT                    (1 << 3)
+#define QAM_FS_SELECT_TEST_BYPASS               (1 << 2)
+#define QAM_FS_DISABLE_DIGITAL_STANDBY          (1 << 1)
+#define QAM_FS_CHOOSE_FS                        (1 << 0)
+
+/* Definitions for fs432x4a_ctl register */
+#define QAM_FS_NSDIV_54MHZ                      (1 << 2)
+
+/* Definitions for bcm1_usb2_ctl register */
+#define BCM1_USB2_CTL_BISTOK                            (1 << 11)
+#define BCM1_USB2_CTL_PORT2_SHIFT_JK                    (1 << 7)
+#define BCM1_USB2_CTL_PORT1_SHIFT_JK                    (1 << 6)
+#define BCM1_USB2_CTL_PORT2_FAST_EDGE                   (1 << 5)
+#define BCM1_USB2_CTL_PORT1_FAST_EDGE                   (1 << 4)
+#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH          (1 << 1)
+#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH     (1 << 0)
+
+/* Definitions for crt_spare register */
+#define CRT_SPARE_PORT2_SHIFT_JK                        (1 << 21)
+#define CRT_SPARE_PORT1_SHIFT_JK                        (1 << 20)
+#define CRT_SPARE_PORT2_FAST_EDGE                       (1 << 19)
+#define CRT_SPARE_PORT1_FAST_EDGE                       (1 << 18)
+#define CRT_SPARE_DIVIDE_BY_9_FROM_432                  (1 << 17)
+#define CRT_SPARE_USB_DIVIDE_BY_9                       (1 << 16)
+
+/* Definitions for usb2_stbus_obc register */
+#define USB_STBUS_OBC_STORE32_LOAD32                    0x3
+
+/* Definitions for usb2_stbus_mess_size register */
+#define USB2_STBUS_MESS_SIZE_2                          0x1     /* 2 packets */
+
+/* Definitions for usb2_stbus_chunk_size register */
+#define USB2_STBUS_CHUNK_SIZE_2                         0x1     /* 2 packets */
+
+/* Definitions for usb2_strap register */
+#define USB2_STRAP_HFREQ_SELECT                         0x1
+
+/*
+ * USB Host Resource Definition
+ */
+
+static struct resource ehci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbehci,
+                .end    = irq_usbehci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ehci_dmamask = 0xffffffffULL;
+
+static struct platform_device ehci_device = {
+        .name = "powertv-ehci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ehci_resources,
+        .dev = {
+                .dma_mask = &ehci_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
+
+static struct resource ohci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbohci,
+                .end    = irq_usbohci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ohci_dmamask = 0xffffffffULL;
+
+static struct platform_device ohci_device = {
+        .name = "powertv-ohci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ohci_resources,
+        .dev = {
+                .dma_mask = &ohci_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
+
+static unsigned usb_users;
+static DEFINE_SPINLOCK(usb_regs_lock);
+
+/*
+ *
+ * fs_update - set frequency synthesizer for USB
+ * @pe_bits             Phase tap setting
+ * @md_bits             Coarse selector bus for algorithm of phase tap
+ * @sdiv_bits           Output divider setting
+ * @disable_div_by_3    Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
+ * @standby             Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
+ *
+ * QAM frequency selection code, which affects the frequency at which USB
+ * runs. The frequency is calculated as:
+ *                             2^15 * ndiv * Fin
+ * Fout = ------------------------------------------------------------
+ *        (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
+ * where:
+ * Fin          54 MHz
+ * ndiv         QAM_FS_NSDIV_54MHZ ? 8 : 16
+ * sdiv         1 << (sdiv_bits + 1)
+ * ipe          Same as pe_bits
+ * md           A five-bit, two's-complement integer (range [-16, 15]), which
+ *              is the lower 5 bits of md_bits.
+ */
+static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
+        u32 disable_div_by_3, u32 standby)
+{
+        u32 val;
+
+        val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
+                ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
+                (pe_bits << QAM_FS_PE_SHIFT) |
+                QAM_FS_ENABLE_OUTPUT |
+                standby |
+                disable_div_by_3);
+        asic_write(val, fs432x4b4_usb_ctl);
+        asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
+        asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
+                fs432x4b4_usb_ctl);
+}
+
+/*
+ * usb_eye_configure - for optimizing the shape USB eye waveform
+ * @set:        Bits to set in the register
+ * @clear:      Bits to clear in the register; each bit with a one will
+ *              be set in the register, zero bits will not be modified
+ */
+static void usb_eye_configure(u32 set, u32 clear)
+{
+        u32 old;
+
+        old = asic_read(crt_spare);
+        old |= set;
+        old &= ~clear;
+        asic_write(old, crt_spare);
+}
+
+/*
+ * platform_configure_usb - usb configuration based on platform type.
+ */
+static void platform_configure_usb(void)
+{
+        u32 bcm1_usb2_ctl_value;
+        enum asic_type asic_type;
+        unsigned long flags;
+
+        spin_lock_irqsave(&usb_regs_lock, flags);
+        usb_users++;
+
+        if (usb_users != 1) {
+                spin_unlock_irqrestore(&usb_regs_lock, flags);
+                return;
+        }
+
+        asic_type = platform_get_asic();
+
+        switch (asic_type) {
+        case ASIC_ZEUS:
+                fs_update(0x0000, -15, 0x02, 0, 0);
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        case ASIC_CRONUS:
+        case ASIC_CRONUSLITE:
+                usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
+                fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
+                        QAM_FS_DISABLE_DIGITAL_STANDBY);
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        case ASIC_CALLIOPE:
+                fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
+                        QAM_FS_DISABLE_DIGITAL_STANDBY);
+
+                switch (platform_get_family()) {
+                case FAMILY_1500VZE:
+                        break;
+
+                case FAMILY_1500VZF:
+                        usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
+                                CRT_SPARE_PORT1_SHIFT_JK |
+                                CRT_SPARE_PORT2_FAST_EDGE |
+                                CRT_SPARE_PORT1_FAST_EDGE, 0);
+                        break;
+
+                default:
+                        usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
+                                CRT_SPARE_PORT1_SHIFT_JK, 0);
+                        break;
+                }
+
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
+                        BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        case ASIC_GAIA:
+                fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
+                        QAM_FS_DISABLE_DIGITAL_STANDBY);
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
+                        BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        default:
+                pr_err("Unknown ASIC type: %d\n", asic_type);
+                bcm1_usb2_ctl_value = 0;
+                break;
+        }
+
+        /* turn on USB power */
+        asic_write(0, usb2_strap);
+        /* Enable all OHCI interrupts */
+        asic_write(bcm1_usb2_ctl_value, usb2_control);
+        /* usb2_stbus_obc store32/load32 */
+        asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
+        /* usb2_stbus_mess_size 2 packets */
+        asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
+        /* usb2_stbus_chunk_size 2 packets */
+        asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
+        spin_unlock_irqrestore(&usb_regs_lock, flags);
+}
+
+static void platform_unconfigure_usb(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&usb_regs_lock, flags);
+        usb_users--;
+        if (usb_users == 0)
+                asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
+        spin_unlock_irqrestore(&usb_regs_lock, flags);
+}
+
+/*
+ * Set up the USB EHCI interface
+ */
+void platform_configure_usb_ehci()
+{
+        platform_configure_usb();
+}
+EXPORT_SYMBOL(platform_configure_usb_ehci);
+
+/*
+ * Set up the USB OHCI interface
+ */
+void platform_configure_usb_ohci()
+{
+        platform_configure_usb();
+}
+EXPORT_SYMBOL(platform_configure_usb_ohci);
+
+/*
+ * Shut the USB EHCI interface down
+ */
+void platform_unconfigure_usb_ehci()
+{
+        platform_unconfigure_usb();
+}
+EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
+
+/*
+ * Shut the USB OHCI interface down
+ */
+void platform_unconfigure_usb_ohci()
+{
+        platform_unconfigure_usb();
+}
+EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
+
+/**
+ * platform_devices_init - sets up USB device resourse.
+ */
+int __init platform_usb_devices_init(struct platform_device **ehci_dev,
+        struct platform_device **ohci_dev)
+{
+        *ehci_dev = &ehci_device;
+        ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
+        ehci_resources[0].end += ehci_resources[0].start;
+
+        *ohci_dev = &ohci_device;
+        ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
+        ohci_resources[0].end += ohci_resources[0].start;
+
+        return 0;
+}
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
index af2cae0a5ab3..3933c373a438 100644
--- a/arch/mips/powertv/powertv_setup.c
+++ b/arch/mips/powertv/powertv_setup.c
@@ -199,14 +199,8 @@ static int panic_handler(struct notifier_block *notifier_block,
                 my_regs.cp0_status = read_c0_status();
         }
 
-#ifdef CONFIG_DIAGNOSTICS
-        failure_report((char *) cause_string,
-                have_die_regs ? &die_regs : &my_regs);
-        have_die_regs = false;
-#else
         pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
                 "zzzz... \n");
-#endif
 
         return NOTIFY_DONE;
 }
diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile
index 8f0b6b6a1625..efdecdb6e3ea 100644
--- a/arch/mips/rb532/Makefile
+++ b/arch/mips/rb532/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y    += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/rb532/Platform b/arch/mips/rb532/Platform
new file mode 100644
index 000000000000..aeec45a7cbb3
--- /dev/null
+++ b/arch/mips/rb532/Platform
@@ -0,0 +1,7 @@
+#
+# Routerboard 532
+#
+platform-$(CONFIG_MIKROTIK_RB532)       += rb532/
+cflags-$(CONFIG_MIKROTIK_RB532)         +=                              \
+                -I$(srctree)/arch/mips/include/asm/mach-rc32434
+load-$(CONFIG_MIKROTIK_RB532)           += 0xffffffff80101000
diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile
index 416b18f9fa72..cc538493cae1 100644
--- a/arch/mips/sgi-ip22/Makefile
+++ b/arch/mips/sgi-ip22/Makefile
@@ -9,5 +9,3 @@ obj-y	+= ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \
 obj-$(CONFIG_SGI_IP22) += ip22-berr.o
 obj-$(CONFIG_SGI_IP28) += ip28-berr.o
 obj-$(CONFIG_EISA)      += ip22-eisa.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip22/Platform b/arch/mips/sgi-ip22/Platform
new file mode 100644
index 000000000000..b7a4b7e04c38
--- /dev/null
+++ b/arch/mips/sgi-ip22/Platform
@@ -0,0 +1,34 @@
+#
+# SGI IP22 (Indy/Indigo2)
+#
+# Set the load address to >= 0xffffffff88069000 if you want to leave space for
+# symmon, 0xffffffff80002000 for production kernels.  Note that the value must
+# be aligned to a multiple of the kernel stack size or the handling of the
+# current variable will break so for 64-bit kernels we have to raise the start
+# address by 8kb.
+#
+platform-$(CONFIG_SGI_IP22)             += sgi-ip22/
+cflags-$(CONFIG_SGI_IP22)       += -I$(srctree)/arch/mips/include/asm/mach-ip22
+ifdef CONFIG_32BIT
+load-$(CONFIG_SGI_IP22)         += 0xffffffff88002000
+endif
+ifdef CONFIG_64BIT
+load-$(CONFIG_SGI_IP22)         += 0xffffffff88004000
+endif
+
+#
+# SGI IP28 (Indigo2 R10k)
+#
+# Set the load address to >= 0xa800000020080000 if you want to leave space for
+# symmon, 0xa800000020004000 for production kernels ?  Note that the value must
+# be 16kb aligned or the handling of the current variable will break.
+# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
+#
+ifdef CONFIG_SGI_IP28
+  ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
+      $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
+  endif
+endif
+platform-$(CONFIG_SGI_IP28)             += sgi-ip22/
+cflags-$(CONFIG_SGI_IP28)       += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
+load-$(CONFIG_SGI_IP28)         += 0xa800000020004000
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index 31f4931b8484..1f29e761d691 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -8,5 +8,3 @@ obj-y	:= ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
 
 obj-$(CONFIG_EARLY_PRINTK)      += ip27-console.o
 obj-$(CONFIG_SMP)               += ip27-smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip27/Platform b/arch/mips/sgi-ip27/Platform
new file mode 100644
index 000000000000..1fb9c2ea7c8f
--- /dev/null
+++ b/arch/mips/sgi-ip27/Platform
@@ -0,0 +1,19 @@
+#
+# SGI-IP27 (Origin200/2000)
+#
+# Set the load address to >= 0xc000000000300000 if you want to leave space for
+# symmon, 0xc00000000001c000 for production kernels.  Note that the value must
+# be 16kb aligned or the handling of the current variable will break.
+#
+ifdef CONFIG_SGI_IP27
+platform-$(CONFIG_SGI_IP27)     += sgi-ip27/
+cflags-$(CONFIG_SGI_IP27)       += -I$(srctree)/arch/mips/include/asm/mach-ip27
+ifdef CONFIG_MAPPED_KERNEL
+load-$(CONFIG_SGI_IP27)         += 0xc00000004001c000
+OBJCOPYFLAGS                    := --change-addresses=0x3fffffff80000000
+dataoffset-$(CONFIG_SGI_IP27)   += 0x01000000
+else
+load-$(CONFIG_SGI_IP27)         += 0xa80000000001c000
+OBJCOPYFLAGS                    := --change-addresses=0x57ffffff80000000
+endif
+endif
diff --git a/arch/mips/sgi-ip27/ip27-klconfig.c b/arch/mips/sgi-ip27/ip27-klconfig.c
index dd830b3670d1..7afe14688003 100644
--- a/arch/mips/sgi-ip27/ip27-klconfig.c
+++ b/arch/mips/sgi-ip27/ip27-klconfig.c
@@ -48,7 +48,7 @@ klinfo_t *find_first_component(lboard_t *brd, unsigned char struct_type)
         return find_component(brd, (klinfo_t *)NULL, struct_type);
 }
 
-lboard_t * find_lboard(lboard_t *start, unsigned char brd_type)
+lboard_t *find_lboard(lboard_t *start, unsigned char brd_type)
 {
         /* Search all boards stored on this node. */
         while (start) {
@@ -60,7 +60,7 @@ lboard_t * find_lboard(lboard_t *start, unsigned char brd_type)
         return (lboard_t *)NULL;
 }
 
-lboard_t * find_lboard_class(lboard_t *start, unsigned char brd_type)
+lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_type)
 {
         /* Search all boards stored on this node. */
         while (start) {
@@ -78,7 +78,7 @@ cnodeid_t get_cpu_cnode(cpuid_t cpu)
         return CPUID_TO_COMPACT_NODEID(cpu);
 }
 
-klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
+klcpu_t *nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
 {
         lboard_t *brd;
         klcpu_t *acpu;
@@ -97,7 +97,7 @@ klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
         return (klcpu_t *)NULL;
 }
 
-klcpu_t * sn_get_cpuinfo(cpuid_t cpu)
+klcpu_t *sn_get_cpuinfo(cpuid_t cpu)
 {
         nasid_t nasid;
         int slice;
diff --git a/arch/mips/sgi-ip32/Makefile b/arch/mips/sgi-ip32/Makefile
index 31c9aa1bcb40..60f0227425e7 100644
--- a/arch/mips/sgi-ip32/Makefile
+++ b/arch/mips/sgi-ip32/Makefile
@@ -5,5 +5,3 @@
 
 obj-y   += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \
            crime.o ip32-memory.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip32/Platform b/arch/mips/sgi-ip32/Platform
new file mode 100644
index 000000000000..0fea556f3641
--- /dev/null
+++ b/arch/mips/sgi-ip32/Platform
@@ -0,0 +1,11 @@
+#
+# SGI-IP32 (O2)
+#
+# Set the load address to >= 80069000 if you want to leave space for symmon,
+# 0xffffffff80004000 for production kernels.  Note that the value must be aligned to
+# a multiple of the kernel stack size or the handling of the current variable
+# will break.
+#
+platform-$(CONFIG_SGI_IP32)     += sgi-ip32/
+cflags-$(CONFIG_SGI_IP32)       += -I$(srctree)/arch/mips/include/asm/mach-ip32
+load-$(CONFIG_SGI_IP32)         += 0xffffffff80004000
diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile
new file mode 100644
index 000000000000..c8ed2c807e69
--- /dev/null
+++ b/arch/mips/sibyte/Makefile
@@ -0,0 +1,27 @@
+#
+# Sibyte SB1250 / BCM1480 family of SOCs
+#
+obj-$(CONFIG_SIBYTE_BCM112X)    += sb1250/
+obj-$(CONFIG_SIBYTE_BCM112X)    += common/
+obj-$(CONFIG_SIBYTE_SB1250)     += sb1250/
+obj-$(CONFIG_SIBYTE_SB1250)     += common/
+obj-$(CONFIG_SIBYTE_BCM1x55)    += bcm1480/
+obj-$(CONFIG_SIBYTE_BCM1x55)    += common/
+obj-$(CONFIG_SIBYTE_BCM1x80)    += bcm1480/
+obj-$(CONFIG_SIBYTE_BCM1x80)    += common/
+
+#
+# Sibyte BCM91120x (Carmel) board
+# Sibyte BCM91120C (CRhine) board
+# Sibyte BCM91125C (CRhone) board
+# Sibyte BCM91125E (Rhone) board
+# Sibyte SWARM board
+# Sibyte BCM91x80 (BigSur) board
+#
+obj-$(CONFIG_SIBYTE_CARMEL)     += swarm/
+obj-$(CONFIG_SIBYTE_CRHINE)     += swarm/
+obj-$(CONFIG_SIBYTE_CRHONE)     += swarm/
+obj-$(CONFIG_SIBYTE_RHONE)      += swarm/
+obj-$(CONFIG_SIBYTE_SENTOSA)    += swarm/
+obj-$(CONFIG_SIBYTE_SWARM)      += swarm/
+obj-$(CONFIG_SIBYTE_BIGSUR)     += swarm/
diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform
new file mode 100644
index 000000000000..911dfe39c631
--- /dev/null
+++ b/arch/mips/sibyte/Platform
@@ -0,0 +1,43 @@
+#
+# These are all rather similar so we consider them a single platform
+#
+platform-$(CONFIG_SIBYTE_BCM112X)       += sibyte/
+platform-$(CONFIG_SIBYTE_SB1250)        += sibyte/
+platform-$(CONFIG_SIBYTE_BCM1x55)       += sibyte/
+platform-$(CONFIG_SIBYTE_BCM1x80)       += sibyte/
+
+#
+# Sibyte SB1250 / BCM1480 family of SOCs
+#
+cflags-$(CONFIG_SIBYTE_BCM112X) +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
+
+platform-$(CONFIG_SIBYTE_SB1250)        += sibyte/
+cflags-$(CONFIG_SIBYTE_SB1250)  +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
+
+cflags-$(CONFIG_SIBYTE_BCM1x55) +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
+
+cflags-$(CONFIG_SIBYTE_BCM1x80) +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
+
+#
+# Sibyte BCM91120x (Carmel) board
+# Sibyte BCM91120C (CRhine) board
+# Sibyte BCM91125C (CRhone) board
+# Sibyte BCM91125E (Rhone) board
+# Sibyte SWARM board
+# Sibyte BCM91x80 (BigSur) board
+#
+load-$(CONFIG_SIBYTE_CARMEL)    := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_CRHINE)    := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_CRHONE)    := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_RHONE)     := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_SENTOSA)   := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_SWARM)     := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_BIGSUR)    := 0xffffffff80100000
diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile
index f292f7df0cfb..cdc4c56c3e29 100644
--- a/arch/mips/sibyte/bcm1480/Makefile
+++ b/arch/mips/sibyte/bcm1480/Makefile
@@ -1,5 +1,3 @@
 obj-y := setup.o irq.o time.o
 
 obj-$(CONFIG_SMP)                       += smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index 4f659837c7c6..36aa700cc40c 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -1,5 +1,3 @@
 obj-y := cfe.o
 obj-$(CONFIG_SIBYTE_CFE_CONSOLE)        += cfe_console.o
 obj-$(CONFIG_SIBYTE_TBPROF)             += sb_tbprof.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index 1896f4e77a30..d3d969de407b 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -2,5 +2,3 @@ obj-y := setup.o irq.o time.o
 
 obj-$(CONFIG_SMP)                       += smp.o
 obj-$(CONFIG_SIBYTE_BUS_WATCHER)        += bus_watcher.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index a7dbeebe7fe6..9d3bad3200ce 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -4,5 +4,3 @@
 
 obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o
 obj-$(CONFIG_EISA) += eisa.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/Platform b/arch/mips/sni/Platform
new file mode 100644
index 000000000000..2644a9d63c0f
--- /dev/null
+++ b/arch/mips/sni/Platform
@@ -0,0 +1,11 @@
+#
+# SNI RM
+#
+platform-$(CONFIG_SNI_RM)               += sni/
+cflags-$(CONFIG_SNI_RM)         += -I$(srctree)/arch/mips/include/asm/mach-rm
+ifdef CONFIG_CPU_LITTLE_ENDIAN
+load-$(CONFIG_SNI_RM)           += 0xffffffff80600000
+else
+load-$(CONFIG_SNI_RM)           += 0xffffffff80030000
+endif
+all-$(CONFIG_SNI_RM)            := $(COMPRESSION_FNAME).ecoff
diff --git a/arch/mips/txx9/Makefile b/arch/mips/txx9/Makefile
new file mode 100644
index 000000000000..34787dabff06
--- /dev/null
+++ b/arch/mips/txx9/Makefile
@@ -0,0 +1,17 @@
+#
+# Common TXx9
+#
+obj-$(CONFIG_MACH_TX39XX)      += generic/
+obj-$(CONFIG_MACH_TX49XX)      += generic/
+
+#
+# Toshiba JMR-TX3927 board
+#
+obj-$(CONFIG_TOSHIBA_JMR3927)  += jmr3927/
+
+#
+# Toshiba RBTX49XX boards
+#
+obj-$(CONFIG_TOSHIBA_RBTX4927) += rbtx4927/
+obj-$(CONFIG_TOSHIBA_RBTX4938) += rbtx4938/
+obj-$(CONFIG_TOSHIBA_RBTX4939) += rbtx4939/
diff --git a/arch/mips/txx9/Platform b/arch/mips/txx9/Platform
new file mode 100644
index 000000000000..a801abbe138b
--- /dev/null
+++ b/arch/mips/txx9/Platform
@@ -0,0 +1,10 @@
+platform-$(CONFIG_MACH_TX39XX)  += txx9/
+platform-$(CONFIG_MACH_TX49XX)  += txx9/
+
+cflags-$(CONFIG_MACH_TX39XX)    +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-tx39xx
+cflags-$(CONFIG_MACH_TX49XX)    +=                                      \
+                 -I$(srctree)/arch/mips/include/asm/mach-tx49xx
+
+load-$(CONFIG_MACH_TX39XX)      += 0xffffffff80050000
+load-$(CONFIG_MACH_TX49XX)      += 0xffffffff80100000
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index f2579ce054a1..1863c167e66e 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -11,5 +11,3 @@ obj-$(CONFIG_SOC_TX4939)	+= setup_tx4939.o irq_tx4939.o
 obj-$(CONFIG_TOSHIBA_FPCIB0)    += smsc_fdc37m81x.o
 obj-$(CONFIG_SPI)               += spi_eeprom.o
 obj-$(CONFIG_TXX9_7SEGLED)      += 7segled.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile
index 20d61ac543e5..9f5d5b623839 100644
--- a/arch/mips/txx9/jmr3927/Makefile
+++ b/arch/mips/txx9/jmr3927/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y   += prom.o irq.o setup.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4927/Makefile b/arch/mips/txx9/rbtx4927/Makefile
index f3e1f597b4f1..60b24c8f7e63 100644
--- a/arch/mips/txx9/rbtx4927/Makefile
+++ b/arch/mips/txx9/rbtx4927/Makefile
@@ -1,3 +1 @@
 obj-y   += prom.o setup.o irq.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile
index f3e1f597b4f1..60b24c8f7e63 100644
--- a/arch/mips/txx9/rbtx4938/Makefile
+++ b/arch/mips/txx9/rbtx4938/Makefile
@@ -1,3 +1 @@
 obj-y   += prom.o setup.o irq.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
index 3232cd03a7d6..5c84625a3f1c 100644
--- a/arch/mips/txx9/rbtx4939/Makefile
+++ b/arch/mips/txx9/rbtx4939/Makefile
@@ -1,3 +1 @@
 obj-y    += irq.o setup.o prom.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/vr41xx/Platform b/arch/mips/vr41xx/Platform
new file mode 100644
index 000000000000..b6c8d5c08ddb
--- /dev/null
+++ b/arch/mips/vr41xx/Platform
@@ -0,0 +1,32 @@
+#
+# NEC VR4100 series based machines
+#
+platform-$(CONFIG_MACH_VR41XX)  += vr41xx/common/
+cflags-$(CONFIG_MACH_VR41XX)    += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
+
+#
+# CASIO CASSIPEIA E-55/65 (VR4111)
+#
+platform-$(CONFIG_CASIO_E55)    += vr41xx/casio-e55/
+load-$(CONFIG_CASIO_E55)        += 0xffffffff80004000
+
+#
+# IBM WorkPad z50 (VR4121)
+#
+platform-$(CONFIG_IBM_WORKPAD)  += vr41xx/ibm-workpad/
+load-$(CONFIG_IBM_WORKPAD)      += 0xffffffff80004000
+
+#
+# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
+#
+load-$(CONFIG_TANBAC_TB022X)    += 0xffffffff80000000
+
+#
+# Victor MP-C303/304 (VR4122)
+#
+load-$(CONFIG_VICTOR_MPC30X)    += 0xffffffff80001000
+
+#
+# ZAO Networks Capcella (VR4131)
+#
+load-$(CONFIG_ZAO_CAPCELLA)     += 0xffffffff80000000
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile
index 7d5d83b8c582..d0d84ec8d63d 100644
--- a/arch/mips/vr41xx/common/Makefile
+++ b/arch/mips/vr41xx/common/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y   += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/wrppmc/Makefile
index b49d282bee8a..307cc6920ce6 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/wrppmc/Makefile
@@ -6,9 +6,7 @@
 # Copyright 2006 Wind River System, Inc.
 # Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
 #
-# Makefile for the Wind River MIPS 4KC PPMC Eval Board
+# Makefile for the Wind River MIPS 4Kc PPMC Eval Board
 #
 
 obj-y += irq.o pci.o reset.o serial.o setup.o time.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/wrppmc/Platform b/arch/mips/wrppmc/Platform
new file mode 100644
index 000000000000..e758645e9681
--- /dev/null
+++ b/arch/mips/wrppmc/Platform
@@ -0,0 +1,7 @@
+#
+# Wind River PPMC Board (4KC + GT64120)
+#
+platform-$(CONFIG_WR_PPMC)      += wrppmc/
+cflags-$(CONFIG_WR_PPMC)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-wrppmc
+load-$(CONFIG_WR_PPMC)          += 0xffffffff80100000
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/wrppmc/irq.c
index c6e706274db4..c6e706274db4 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/wrppmc/irq.c
diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/wrppmc/pci.c
index d06192faeb7c..d06192faeb7c 100644
--- a/arch/mips/gt64120/wrppmc/pci.c
+++ b/arch/mips/wrppmc/pci.c
diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/wrppmc/reset.c
index cc5474b24f06..cc5474b24f06 100644
--- a/arch/mips/gt64120/wrppmc/reset.c
+++ b/arch/mips/wrppmc/reset.c
diff --git a/arch/mips/gt64120/wrppmc/serial.c b/arch/mips/wrppmc/serial.c
index 6f9d0858f596..6f9d0858f596 100644
--- a/arch/mips/gt64120/wrppmc/serial.c
+++ b/arch/mips/wrppmc/serial.c
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/wrppmc/setup.c
index ca65c84031a7..ca65c84031a7 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/wrppmc/setup.c
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/wrppmc/time.c
index 668dbd5f12c5..668dbd5f12c5 100644
--- a/arch/mips/gt64120/wrppmc/time.c
+++ b/arch/mips/wrppmc/time.c
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 1c4565a9102b..444b9f918fdf 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -46,9 +46,6 @@ config GENERIC_FIND_NEXT_BIT
 config GENERIC_HWEIGHT
         def_bool y
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_BUG
         def_bool y
 
diff --git a/arch/mn10300/include/asm/local64.h b/arch/mn10300/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/mn10300/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 05a366a5c4d5..907417d187e1 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -66,10 +66,6 @@ config GENERIC_CALIBRATE_DELAY
         bool
         default y
 
-config GENERIC_TIME
-        bool
-        default y
-
 config TIME_LOW_RES
         bool
         depends on SMP
diff --git a/arch/parisc/include/asm/local64.h b/arch/parisc/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/parisc/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/parisc/kernel/firmware.c b/arch/parisc/kernel/firmware.c
index 4c247e02d9b1..df971fa0c32f 100644
--- a/arch/parisc/kernel/firmware.c
+++ b/arch/parisc/kernel/firmware.c
@@ -1123,7 +1123,6 @@ static char __attribute__((aligned(64))) iodc_dbuf[4096];
  */
 int pdc_iodc_print(const unsigned char *str, unsigned count)
 {
-        static int posx;        /* for simple TAB-Simulation... */
         unsigned int i;
         unsigned long flags;
 
@@ -1133,19 +1132,12 @@ int pdc_iodc_print(const unsigned char *str, unsigned count)
                         iodc_dbuf[i+0] = '\r';
                         iodc_dbuf[i+1] = '\n';
                         i += 2;
-                        posx = 0;
                         goto print;
-                case '\t':
-                        while (posx & 7) {
-                                iodc_dbuf[i] = ' ';
-                                i++, posx++;
-                        }
-                        break;
                 case '\b':      /* BS */
-                        posx -= 2;
+                        i--; /* overwrite last */
                 default:
                         iodc_dbuf[i] = str[i];
-                        i++, posx++;
+                        i++;
                         break;
                 }
         }
diff --git a/arch/parisc/kernel/ftrace.c b/arch/parisc/kernel/ftrace.c
index 9877372ffdba..5beb97bafbb1 100644
--- a/arch/parisc/kernel/ftrace.c
+++ b/arch/parisc/kernel/ftrace.c
@@ -82,7 +82,7 @@ unsigned long ftrace_return_to_handler(unsigned long retval0,
         unsigned long ret;
 
         pop_return_trace(&trace, &ret);
-        trace.rettime = cpu_clock(raw_smp_processor_id());
+        trace.rettime = local_clock();
         ftrace_graph_return(&trace);
 
         if (unlikely(!ret)) {
@@ -126,7 +126,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
                 return;
         }
 
-        calltime = cpu_clock(raw_smp_processor_id());
+        calltime = local_clock();
 
         if (push_return_trace(old, calltime,
                                 self_addr, &trace.depth) == -EBUSY) {
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2031a2846865..631e5a0fb6ab 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -29,9 +29,6 @@ config MMU
 config GENERIC_CMOS_UPDATE
         def_bool y
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_TIME_VSYSCALL
         def_bool y
 
@@ -120,6 +117,8 @@ config ARCH_NO_VIRT_TO_BUS
 config PPC
         bool
         default y
+        select OF
+        select OF_FLATTREE
         select HAVE_FTRACE_MCOUNT_RECORD
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FUNCTION_TRACER
@@ -141,6 +140,7 @@ config PPC
         select GENERIC_ATOMIC64 if PPC32
         select HAVE_PERF_EVENTS
         select HAVE_REGS_AND_STACK_ACCESS_API
+        select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
 
 config EARLY_PRINTK
         bool
@@ -172,10 +172,6 @@ config ARCH_MAY_HAVE_PC_FDC
 config PPC_OF
         def_bool y
 
-config OF
-        def_bool y
-        select OF_FLATTREE
-
 config PPC_UDBG_16550
         bool
         default n
@@ -198,10 +194,6 @@ config SYS_SUPPORTS_APM_EMULATION
         default y if PMAC_APM_EMU
         bool
 
-config DTC
-       bool
-       default y
-
 config DEFAULT_UIMAGE
         bool
         help
@@ -218,7 +210,7 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
         depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
-                   PPC_85xx || PPC_86xx
+                   PPC_85xx || PPC_86xx || PPC_PSERIES
 
 config PPC_DCR_NATIVE
         bool
@@ -351,7 +343,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
 
 config KEXEC
         bool "kexec system call (EXPERIMENTAL)"
-        depends on (PPC_BOOK3S || (FSL_BOOKE && !SMP)) && EXPERIMENTAL
+        depends on (PPC_BOOK3S || FSL_BOOKE) && EXPERIMENTAL
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
@@ -368,8 +360,8 @@ config KEXEC
 
 config CRASH_DUMP
         bool "Build a kdump crash kernel"
-        depends on PPC64 || 6xx
-        select RELOCATABLE if PPC64
+        depends on PPC64 || 6xx || FSL_BOOKE
+        select RELOCATABLE if PPC64 || FSL_BOOKE
         help
           Build a kernel suitable for use as a kdump capture kernel.
           The same kernel binary can be used as production kernel and dump
@@ -578,14 +570,6 @@ config SCHED_SMT
           when dealing with POWER5 cpus at a cost of slightly increased
           overhead in some places. If unsure say N here.
 
-config PROC_DEVICETREE
-        bool "Support for device tree in /proc"
-        depends on PROC_FS
-        help
-          This option adds a device-tree directory under /proc which contains
-          an image of the device tree that the kernel copies from Open
-          Firmware or other boot firmware. If unsure, say Y here.
-
 config CMDLINE_BOOL
         bool "Default bootloader kernel arguments"
 
@@ -668,7 +652,7 @@ config NEED_SG_DMA_LENGTH
 
 config GENERIC_ISA_DMA
         bool
-        depends on PPC64 || POWER4 || 6xx && !CPM2
+        depends on ISA_DMA_API
         default y
 
 config PPC_INDIRECT_PCI
@@ -897,7 +881,7 @@ config KERNEL_START_BOOL
 config KERNEL_START
         hex "Virtual address of kernel base" if KERNEL_START_BOOL
         default PAGE_OFFSET if PAGE_OFFSET_BOOL
-        default "0xc2000000" if CRASH_DUMP
+        default "0xc2000000" if CRASH_DUMP && !RELOCATABLE
         default "0xc0000000"
 
 config PHYSICAL_START_BOOL
@@ -910,7 +894,7 @@ config PHYSICAL_START_BOOL
 
 config PHYSICAL_START
         hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
-        default "0x02000000" if PPC_STD_MMU && CRASH_DUMP
+        default "0x02000000" if PPC_STD_MMU && CRASH_DUMP && !RELOCATABLE
         default "0x00000000"
 
 config PHYSICAL_ALIGN
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 77cfe7a29e25..5d42f5eae70f 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -94,7 +94,7 @@ else
 endif
 endif
 
-LDFLAGS_MODULE  += arch/powerpc/lib/crtsavres.o
+KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
 
 ifeq ($(CONFIG_TUNE_CELL),y)
         KBUILD_CFLAGS += $(call cc-option,-mtune=cell)
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index cd56bb5b347b..5806ef0b860b 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -270,7 +270,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1d 0x4>;
+                                interrupts = <28 0x4>;
                         };
 
                         UART3: serial@ef600600 {
@@ -281,7 +281,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1e 0x4>;
+                                interrupts = <29 0x4>;
                         };
 
                         IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index d62a4fb6f93c..e618fc4cbc9e 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -259,7 +259,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1d 0x4>;
+                                interrupts = <28 0x4>;
                         };
 
                         UART3: serial@ef600600 {
@@ -270,7 +270,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1e 0x4>;
+                                interrupts = <29 0x4>;
                         };
 
                         IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
new file mode 100644
index 000000000000..a97eb2db5a18
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -0,0 +1,303 @@
+/*
+ * MPC8308RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "fsl,mpc8308rdb";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8308@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <16384>;
+                        i-cache-size = <16384>;
+                        timebase-frequency = <0>;       // from bootloader
+                        bus-frequency = <0>;            // from bootloader
+                        clock-frequency = <0>;          // from bootloader
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;  // 128MB at 0
+        };
+
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xe0005000 0x1000>;
+                interrupts = <77 0x8>;
+                interrupt-parent = <&ipic>;
+
+                // CS0 and CS1 are swapped when
+                // booting from nand, but the
+                // addresses are the same.
+                ranges = <0x0 0x0 0xfe000000 0x00800000
+                          0x1 0x0 0xe0600000 0x00002000
+                          0x2 0x0 0xf0000000 0x00020000
+                          0x3 0x0 0xfa000000 0x00008000>;
+
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x800000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        u-boot@0 {
+                                reg = <0x0 0x60000>;
+                                read-only;
+                        };
+                        env@60000 {
+                                reg = <0x60000 0x10000>;
+                        };
+                        env1@70000 {
+                                reg = <0x70000 0x10000>;
+                        };
+                        kernel@80000 {
+                                reg = <0x80000 0x200000>;
+                        };
+                        dtb@280000 {
+                                reg = <0x280000 0x10000>;
+                        };
+                        ramdisk@290000 {
+                                reg = <0x290000 0x570000>;
+                        };
+                };
+
+                nand@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8315-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x1 0x0 0x2000>;
+
+                        jffs2@0 {
+                                reg = <0x0 0x2000000>;
+                        };
+                };
+        };
+
+        immr@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,mpc8315-immr", "simple-bus";
+                ranges = <0 0xe0000000 0x00100000>;
+                reg = <0xe0000000 0x00000200>;
+                bus-frequency = <0>;
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <14 0x8>;
+                        interrupt-parent = <&ipic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds1339";
+                                reg = <0x68>;
+                        };
+                };
+
+                usb@23000 {
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x23000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <38 0x8>;
+                        dr_mode = "peripheral";
+                        phy_type = "ulpi";
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x24000 0x1000>;
+
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <32 0x8 33 0x8 34 0x8>;
+                        interrupt-parent = <&ipic>;
+                        tbi-handle = < &tbi0 >;
+                        phy-handle = < &phy2 >;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+                                phy2: ethernet-phy@2 {
+                                        interrupt-parent = <&ipic>;
+                                        interrupts = <17 0x8>;
+                                        reg = <0x2>;
+                                        device_type = "ethernet-phy";
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 0x8 36 0x8 37 0x8>;
+                        interrupt-parent = <&ipic>;
+                        tbi-handle = < &tbi1 >;
+                        /* Vitesse 7385 isn't on the MDIO bus */
+                        fixed-link = <1 1 1000 0 0>;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <133333333>;
+                        interrupts = <9 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <133333333>;
+                        interrupts = <10 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                gpio@c00 {
+                        #gpio-cells = <2>;
+                        device_type = "gpio";
+                        compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
+                        reg = <0xc00 0x18>;
+                        interrupts = <74 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
+                /* IPIC
+                 * interrupts cell = <intr #, sense>
+                 * sense values match linux IORESOURCE_IRQ_* defines:
+                 * sense == 8: Level, low assertion
+                 * sense == 2: Edge, high-to-low change
+                 */
+                ipic: interrupt-controller@700 {
+                        compatible = "fsl,ipic";
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x700 0x100>;
+                        device_type = "ipic";
+                };
+
+                ipic-msi@7c0 {
+                        compatible = "fsl,ipic-msi";
+                        reg = <0x7c0 0x40>;
+                        msi-available-ranges = <0x0 0x100>;
+                        interrupts = < 0x43 0x8
+                                        0x4  0x8
+                                        0x51 0x8
+                                        0x52 0x8
+                                        0x56 0x8
+                                        0x57 0x8
+                                        0x58 0x8
+                                        0x59 0x8 >;
+                        interrupt-parent = < &ipic >;
+                };
+
+        };
+
+        pci0: pcie@e0009000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                device_type = "pci";
+                compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
+                reg = <0xe0009000 0x00001000
+                        0xb0000000 0x01000000>;
+                ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
+                bus-range = <0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <0 0 0 1 &ipic 1 8
+                                 0 0 0 2 &ipic 1 8
+                                 0 0 0 3 &ipic 1 8
+                                 0 0 0 4 &ipic 1 8>;
+                interrupts = <0x1 0x8>;
+                interrupt-parent = <&ipic>;
+                clock-frequency = <0>;
+
+                pcie@0 {
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        reg = <0 0 0 0 0>;
+                        ranges = <0x02000000 0 0xa0000000
+                                  0x02000000 0 0xa0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00800000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 9dc292962a9a..8d1bf0fd9268 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8540-memory-controller";
+                        compatible = "fsl,mpc8540-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8540-l2-cache-controller";
+                        compatible = "fsl,mpc8540-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 9a3ad311aedf..87ff96549fac 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8541-memory-controller";
+                        compatible = "fsl,mpc8541-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8541-l2-cache-controller";
+                        compatible = "fsl,mpc8541-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 98e94b465662..d793968743c9 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -73,14 +73,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8544-memory-controller";
+                        compatible = "fsl,mpc8544-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8544-l2-cache-controller";
+                        compatible = "fsl,mpc8544-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 0f5262452682..a17a5572fb73 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -74,14 +74,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8548-memory-controller";
+                        compatible = "fsl,mpc8548-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8548-l2-cache-controller";
+                        compatible = "fsl,mpc8548-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 065b2f093de2..5c5614f9eb17 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8555-memory-controller";
+                        compatible = "fsl,mpc8555-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8555-l2-cache-controller";
+                        compatible = "fsl,mpc8555-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index a5bb1ec70a5a..6e85e1ba0851 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8540-memory-controller";
+                        compatible = "fsl,mpc8540-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8540-l2-cache-controller";
+                        compatible = "fsl,mpc8540-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 92fb17876e7d..30cf0e098bb9 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -124,14 +124,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8568-memory-controller";
+                        compatible = "fsl,mpc8568-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8568-l2-cache-controller";
+                        compatible = "fsl,mpc8568-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index 7fad2df25981..ad5b85269004 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -617,6 +617,7 @@
                 bus-frequency = <0>;
                 fsl,qe-num-riscs = <1>;
                 fsl,qe-num-snums = <28>;
+                status = "disabled"; /* no firmware loaded */
 
                 qeic: interrupt-controller@80 {
                         interrupt-controller;
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
new file mode 100644
index 000000000000..8bcb10b92677
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -0,0 +1,633 @@
+/*
+ * P1022 DS 36Bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/ {
+        model = "fsl,P1022";
+        compatible = "fsl,P1022DS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,P1022@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+
+                PowerPC,P1022@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        localbus@fffe05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
+                reg = <0 0xffe05000 0 0x1000>;
+                interrupts = <19 2>;
+
+                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
+                          0x1 0x0 0xf 0xe0000000 0x08000000
+                          0x2 0x0 0x0 0xffa00000 0x00040000
+                          0x3 0x0 0xf 0xffdf0000 0x00008000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                reg = <0x0 0x03000000>;
+                                label = "ramdisk-nor";
+                                read-only;
+                        };
+
+                        partition@3000000 {
+                                reg = <0x03000000 0x00e00000>;
+                                label = "diagnostic-nor";
+                                read-only;
+                        };
+
+                        partition@3e00000 {
+                                reg = <0x03e00000 0x00200000>;
+                                label = "dink-nor";
+                                read-only;
+                        };
+
+                        partition@4000000 {
+                                reg = <0x04000000 0x00400000>;
+                                label = "kernel-nor";
+                                read-only;
+                        };
+
+                        partition@4400000 {
+                                reg = <0x04400000 0x03b00000>;
+                                label = "jffs2-nor";
+                        };
+
+                        partition@7f00000 {
+                                reg = <0x07f00000 0x00080000>;
+                                label = "dtb-nor";
+                                read-only;
+                        };
+
+                        partition@7f80000 {
+                                reg = <0x07f80000 0x00080000>;
+                                label = "u-boot-nor";
+                                read-only;
+                        };
+                };
+
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x2 0x0 0x40000>;
+
+                        partition@0 {
+                                reg = <0x0 0x02000000>;
+                                label = "u-boot-nand";
+                                read-only;
+                        };
+
+                        partition@2000000 {
+                                reg = <0x02000000 0x10000000>;
+                                label = "jffs2-nand";
+                        };
+
+                        partition@12000000 {
+                                reg = <0x12000000 0x10000000>;
+                                label = "ramdisk-nand";
+                                read-only;
+                        };
+
+                        partition@22000000 {
+                                reg = <0x22000000 0x04000000>;
+                                label = "kernel-nand";
+                        };
+
+                        partition@26000000 {
+                                reg = <0x26000000 0x01000000>;
+                                label = "dtb-nand";
+                                read-only;
+                        };
+
+                        partition@27000000 {
+                                reg = <0x27000000 0x19000000>;
+                                label = "reserved-nand";
+                        };
+                };
+        };
+
+        soc@fffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,p1022-immr", "simple-bus";
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,p1022-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <16 2>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,p1022-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupts = <16 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        dfsrr;
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        dfsrr;
+
+                        wm8776:codec@1a {
+                                compatible = "wlf,wm8776";
+                                reg = <0x1a>;
+                                /* MCLK source is a stand-alone oscillator */
+                                clock-frequency = <12288000>;
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                };
+
+                spi@7000 {
+                        cell-index = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,espi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <59 0x2>;
+                        espi,num-ss-bits = <4>;
+                        mode = "cpu";
+
+                        fsl_m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,espi-flash";
+                                reg = <0>;
+                                linux,modalias = "fsl_m25p80";
+                                spi-max-frequency = <40000000>; /* input clock */
+                                partition@0 {
+                                        label = "u-boot-spi";
+                                        reg = <0x00000000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@100000 {
+                                        label = "kernel-spi";
+                                        reg = <0x00100000 0x00500000>;
+                                        read-only;
+                                };
+                                partition@600000 {
+                                        label = "dtb-spi";
+                                        reg = <0x00600000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@700000 {
+                                        label = "file system-spi";
+                                        reg = <0x00700000 0x00900000>;
+                                };
+                        };
+                };
+
+                ssi@15000 {
+                        compatible = "fsl,mpc8610-ssi";
+                        cell-index = <0>;
+                        reg = <0x15000 0x100>;
+                        interrupts = <75 2>;
+                        fsl,mode = "i2s-slave";
+                        codec-handle = <&wm8776>;
+                        fsl,playback-dma = <&dma00>;
+                        fsl,capture-dma = <&dma01>;
+                        fsl,fifo-depth = <16>;
+                };
+
+                dma@c300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0xc300 0x4>;
+                        ranges = <0x0 0xc100 0x200>;
+                        cell-index = <1>;
+                        dma00: dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupts = <76 2>;
+                        };
+                        dma01: dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupts = <77 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupts = <78 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupts = <79 2>;
+                        };
+                };
+
+                gpio: gpio-controller@f000 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8572-gpio";
+                        reg = <0xf000 0x100>;
+                        interrupts = <47 0x2>;
+                        gpio-controller;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,p1022-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
+                        interrupts = <16 2>;
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                usb@22000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x22000 0x1000>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                mdio@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,etsec2-mdio";
+                        reg = <0x24000 0x1000 0xb0030 0x4>;
+
+                        phy0: ethernet-phy@0 {
+                                interrupts = <3 1>;
+                                reg = <0x1>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupts = <9 1>;
+                                reg = <0x2>;
+                        };
+                };
+
+                mdio@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,etsec2-mdio";
+                        reg = <0x25000 0x1000 0xb1030 0x4>;
+                };
+
+                enet0: ethernet@B0000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "fsl,etsec2";
+                        fsl,num_rx_queues = <0x8>;
+                        fsl,num_tx_queues = <0x8>;
+                        fsl,magic-packet;
+                        fsl,wake-on-filer;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        fixed-link = <1 1 1000 0 0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                        queue-group@0{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB0000 0x1000>;
+                                interrupts = <29 2 30 2 34 2>;
+                        };
+                        queue-group@1{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB4000 0x1000>;
+                                interrupts = <17 2 18 2 24 2>;
+                        };
+                };
+
+                enet1: ethernet@B1000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "fsl,etsec2";
+                        fsl,num_rx_queues = <0x8>;
+                        fsl,num_tx_queues = <0x8>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        fixed-link = <1 1 1000 0 0>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                        queue-group@0{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB1000 0x1000>;
+                                interrupts = <35 2 36 2 40 2>;
+                        };
+                        queue-group@1{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB5000 0x1000>;
+                                interrupts = <51 2 52 2 67 2>;
+                        };
+                };
+
+                sdhci@2e000 {
+                        compatible = "fsl,p1022-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        fsl,sdhci-auto-cmd12;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
+                                     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
+                                     "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x97c>;
+                        fsl,descriptor-types-mask = <0x3a30abf>;
+                };
+
+                sata@18000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x18000 0x1000>;
+                        cell-index = <1>;
+                        interrupts = <74 0x2>;
+                };
+
+                sata@19000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x19000 0x1000>;
+                        cell-index = <2>;
+                        interrupts = <41 0x2>;
+                };
+
+                power@e0070{
+                        compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
+                        reg = <0xe0070 0x20>;
+                };
+
+                display@10000 {
+                        compatible = "fsl,diu", "fsl,p1022-diu";
+                        reg = <0x10000 1000>;
+                        interrupts = <64 2>;
+                };
+
+                timer@41100 {
+                        compatible = "fsl,mpic-global-timer";
+                        reg = <0x41100 0x204>;
+                        interrupts = <0xf7 0x2>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+
+                msi@41600 {
+                        compatible = "fsl,p1022-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,p1022-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+
+        pci0: pcie@fffe09000 {
+                compatible = "fsl,p1022-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe09000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 4 1
+                        0000 0 0 2 &mpic 5 1
+                        0000 0 0 3 &mpic 6 1
+                        0000 0 0 4 &mpic 7 1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                compatible = "fsl,p1022-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 0 1
+                        0000 0 0 2 &mpic 1 1
+                        0000 0 0 3 &mpic 2 1
+                        0000 0 0 4 &mpic 3 1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+
+        pci2: pcie@fffe0b000 {
+                compatible = "fsl,p1022-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0b000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 8 1
+                        0000 0 0 2 &mpic 9 1
+                        0000 0 0 3 &mpic 10 1
+                        0000 0 0 4 &mpic 11 1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
new file mode 100644
index 000000000000..94dfa5c9a7f9
--- /dev/null
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -0,0 +1,410 @@
+/*
+ * Device Tree Source for IFM PDM360NG.
+ *
+ * Copyright 2009 - 2010 DENX Software Engineering.
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * Based on MPC5121E ADS dts.
+ * Copyright 2008 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "pdm360ng";
+        compatible = "ifm,pdm360ng";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&ipic>;
+
+        aliases {
+                ethernet0 = &eth0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,5121@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <0x20>;     // 32 bytes
+                        i-cache-line-size = <0x20>;     // 32 bytes
+                        d-cache-size = <0x8000>;        // L1, 32K
+                        i-cache-size = <0x8000>;        // L1, 32K
+                        timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
+                        bus-frequency = <198000000>;    // 198 MHz csb bus
+                        clock-frequency = <396000000>;  // 396 MHz ppc core
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;  // 512MB at 0
+        };
+
+        nfc@40000000 {
+                compatible = "fsl,mpc5121-nfc";
+                reg = <0x40000000 0x100000>;
+                interrupts = <0x6 0x8>;
+                #address-cells = <0x1>;
+                #size-cells = <0x1>;
+                bank-width = <0x1>;
+                chips = <0x1>;
+
+                partition@0 {
+                        label = "nand0";
+                        reg = <0x0 0x40000000>;
+                };
+        };
+
+        sram@50000000 {
+                compatible = "fsl,mpc5121-sram";
+                reg = <0x50000000 0x20000>;     // 128K at 0x50000000
+        };
+
+        localbus@80000020 {
+                compatible = "fsl,mpc5121-localbus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0x80000020 0x40>;
+
+                ranges = <0x0 0x0 0xf0000000 0x10000000   /* Flash */
+                          0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
+
+                flash@0,0 {
+                        compatible = "amd,s29gl01gp", "cfi-flash";
+                        reg = <0 0x00000000 0x08000000
+                               0 0x08000000 0x08000000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <4>;
+                        device-width = <2>;
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x00000000 0x00080000>;
+                                read-only;
+                        };
+                        partition@80000 {
+                                label = "environment";
+                                reg = <0x00080000 0x00080000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "splash-image";
+                                reg = <0x00100000 0x00080000>;
+                                read-only;
+                        };
+                        partition@180000 {
+                                label = "device-tree";
+                                reg = <0x00180000 0x00040000>;
+                        };
+                        partition@1c0000 {
+                                label = "kernel";
+                                reg = <0x001c0000 0x00500000>;
+                        };
+                        partition@6c0000 {
+                                label = "filesystem";
+                                reg = <0x006c0000 0x07940000>;
+                        };
+                };
+
+                mram0@2,0 {
+                        compatible = "mtd-ram";
+                        reg = <2 0x00000 0x10000>;
+                        bank-width = <2>;
+                };
+
+                mram1@2,10000 {
+                        compatible = "mtd-ram";
+                        reg = <2 0x010000 0x10000>;
+                        bank-width = <2>;
+                };
+        };
+
+        soc@80000000 {
+                compatible = "fsl,mpc5121-immr";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                #interrupt-cells = <2>;
+                ranges = <0x0 0x80000000 0x400000>;
+                reg = <0x80000000 0x400000>;
+                bus-frequency = <66000000>;     // 66 MHz ips bus
+
+                // IPIC
+                // interrupts cell = <intr #, sense>
+                // sense values match linux IORESOURCE_IRQ_* defines:
+                // sense == 8: Level, low assertion
+                // sense == 2: Edge, high-to-low change
+                //
+                ipic: interrupt-controller@c00 {
+                        compatible = "fsl,mpc5121-ipic", "fsl,ipic";
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0xc00 0x100>;
+                };
+
+                rtc@a00 {       // Real time clock
+                        compatible = "fsl,mpc5121-rtc";
+                        reg = <0xa00 0x100>;
+                        interrupts = <79 0x8 80 0x8>;
+                };
+
+                reset@e00 {     // Reset module
+                        compatible = "fsl,mpc5121-reset";
+                        reg = <0xe00 0x100>;
+                };
+
+                clock@f00 {     // Clock control
+                        compatible = "fsl,mpc5121-clock";
+                        reg = <0xf00 0x100>;
+                };
+
+                pmc@1000{       //Power Management Controller
+                        compatible = "fsl,mpc5121-pmc";
+                        reg = <0x1000 0x100>;
+                        interrupts = <83 0x2>;
+                };
+
+                gpio@1100 {
+                        compatible = "fsl,mpc5121-gpio";
+                        reg = <0x1100 0x100>;
+                        interrupts = <78 0x8>;
+                };
+
+                can@1300 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <12 0x8>;
+                        reg = <0x1300 0x80>;
+                };
+
+                can@1380 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <13 0x8>;
+                        reg = <0x1380 0x80>;
+                };
+
+                i2c@1700 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5121-i2c";
+                        reg = <0x1700 0x20>;
+                        interrupts = <0x9 0x8>;
+                        fsl,preserve-clocking;
+
+                        eeprom@50 {
+                                compatible = "at,24c01";
+                                reg = <0x50>;
+                        };
+
+                        rtc@68 {
+                                compatible = "stm,m41t00";
+                                reg = <0x68>;
+                        };
+                };
+
+                i2c@1740 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5121-i2c";
+                        reg = <0x1740 0x20>;
+                        interrupts = <0xb 0x8>;
+                        fsl,preserve-clocking;
+                };
+
+                i2ccontrol@1760 {
+                        compatible = "fsl,mpc5121-i2c-ctrl";
+                        reg = <0x1760 0x8>;
+                };
+
+                axe@2000 {
+                        compatible = "fsl,mpc5121-axe";
+                        reg = <0x2000 0x100>;
+                        interrupts = <42 0x8>;
+                };
+
+                display@2100 {
+                        compatible = "fsl,mpc5121-diu";
+                        reg = <0x2100 0x100>;
+                        interrupts = <64 0x8>;
+                };
+
+                can@2300 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <90 0x8>;
+                        reg = <0x2300 0x80>;
+                };
+
+                can@2380 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <91 0x8>;
+                        reg = <0x2380 0x80>;
+                };
+
+                viu@2400 {
+                        compatible = "fsl,mpc5121-viu";
+                        reg = <0x2400 0x400>;
+                        interrupts = <67 0x8>;
+                };
+
+                mdio@2800 {
+                        compatible = "fsl,mpc5121-fec-mdio";
+                        reg = <0x2800 0x200>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy: ethernet-phy@0 {
+                                compatible = "smsc,lan8700";
+                                reg = <0x1f>;
+                        };
+                };
+
+                eth0: ethernet@2800 {
+                        compatible = "fsl,mpc5121-fec";
+                        reg = <0x2800 0x200>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <4 0x8>;
+                        phy-handle = < &phy >;
+                };
+
+                // USB1 using external ULPI PHY
+                usb@3000 {
+                        compatible = "fsl,mpc5121-usb2-dr";
+                        reg = <0x3000 0x600>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <43 0x8>;
+                        dr_mode = "host";
+                        phy_type = "ulpi";
+                };
+
+                // USB0 using internal UTMI PHY
+                usb@4000 {
+                        compatible = "fsl,mpc5121-usb2-dr";
+                        reg = <0x4000 0x600>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <44 0x8>;
+                        dr_mode = "otg";
+                        phy_type = "utmi_wide";
+                        fsl,invert-pwr-fault;
+                };
+
+                // IO control
+                ioctl@a000 {
+                        compatible = "fsl,mpc5121-ioctl";
+                        reg = <0xA000 0x1000>;
+                };
+
+                // 512x PSCs are not 52xx PSCs compatible
+                serial@11000 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <0>;
+                        reg = <0x11000 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11100 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <1>;
+                        reg = <0x11100 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11200 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <2>;
+                        reg = <0x11200 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11300 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <3>;
+                        reg = <0x11300 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11400 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <4>;
+                        reg = <0x11400 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11600 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <6>;
+                        reg = <0x11600 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11800 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <8>;
+                        reg = <0x11800 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11B00 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <11>;
+                        reg = <0x11B00 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                pscfifo@11f00 {
+                        compatible = "fsl,mpc5121-psc-fifo";
+                        reg = <0x11f00 0x100>;
+                        interrupts = <40 0x8>;
+                };
+
+                spi@11900 {
+                        compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
+                        cell-index = <9>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11900 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+
+                        // 7845 touch screen controller
+                        ts@0 {
+                                compatible = "ti,ads7846";
+                                reg = <0x0>;
+                                spi-max-frequency = <3000000>;
+                                // pen irq is GPIO25
+                                interrupts = <78 0x8>;
+                        };
+                };
+
+                dma@14000 {
+                        compatible = "fsl,mpc5121-dma";
+                        reg = <0x14000 0x1800>;
+                        interrupts = <65 0x8>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
new file mode 100644
index 000000000000..49efd44057d7
--- /dev/null
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -0,0 +1,380 @@
+/*
+ * MPC8555-based STx GP3 Device Tree Source
+ *
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
+ *
+ * Copyright 2010 Silicon Turnkey Express LLC.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "stx,gp3";
+        compatible = "stx,gp3-8560", "stx,gp3";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8555@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
+                        timebase-frequency = <0>;       //  33 MHz, from uboot
+                        bus-frequency = <0>;    // 166 MHz
+                        clock-frequency = <0>;  // 825 MHz, from uboot
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        soc8555@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x0 0xe0000000 0x100000>;
+                bus-frequency = <0>;
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,mpc8555-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,mpc8555-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+
+                                phy0: ethernet-phy@2 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <5 1>;
+                                        reg = <0x2>;
+                                        device_type = "ethernet-phy";
+                                };
+                                phy1: ethernet-phy@4 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <5 1>;
+                                        reg = <0x4>;
+                                        device_type = "ethernet-phy";
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy1>;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;   // reg base, size
+                        clock-frequency = <0>;  // should we fill in in uboot?
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;   // reg base, size
+                        clock-frequency = <0>;  // should we fill in in uboot?
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x7e>;
+                        fsl,descriptor-types-mask = <0x01010ebf>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+
+                cpm@919c0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
+                        reg = <0x919c0 0x30>;
+                        ranges;
+
+                        muram@80000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x0 0x80000 0x10000>;
+
+                                data@0 {
+                                        compatible = "fsl,cpm-muram-data";
+                                        reg = <0x0 0x2000 0x9000 0x1000>;
+                                };
+                        };
+
+                        brg@919f0 {
+                                compatible = "fsl,mpc8555-brg",
+                                             "fsl,cpm2-brg",
+                                             "fsl,cpm-brg";
+                                reg = <0x919f0 0x10 0x915f0 0x10>;
+                        };
+
+                        cpmpic: pic@90c00 {
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <2>;
+                                interrupts = <46 2>;
+                                interrupt-parent = <&mpic>;
+                                reg = <0x90c00 0x80>;
+                                compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
+                        };
+                };
+        };
+
+        pci0: pci@e0008000 {
+                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x10 */
+                        0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+                        /* IDSEL 0x11 */
+                        0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
+
+                        /* IDSEL 0x12 (Slot 1) */
+                        0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+                        /* IDSEL 0x13 (Slot 2) */
+                        0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
+
+                        /* IDSEL 0x14 (Slot 3) */
+                        0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x15 (Slot 4) */
+                        0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* Bus 1 (Tundra Bridge) */
+                        /* IDSEL 0x12 (ISA bridge) */
+                        0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+                interrupt-parent = <&mpic>;
+                interrupts = <24 2>;
+                bus-range = <0 0>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe0008000 0x1000>;
+                compatible = "fsl,mpc8540-pci";
+                device_type = "pci";
+
+                i8259@19000 {
+                        interrupt-controller;
+                        device_type = "interrupt-controller";
+                        reg = <0x19000 0x0 0x0 0x0 0x1>;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        compatible = "chrp,iic";
+                        interrupts = <1>;
+                        interrupt-parent = <&pci0>;
+                };
+        };
+
+        pci1: pci@e0009000 {
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x15 */
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                bus-range = <0 0>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe0009000 0x1000>;
+                compatible = "fsl,mpc8540-pci";
+                device_type = "pci";
+        };
+};
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 71347537b83e..15ca731bc24e 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -289,7 +289,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index b30f63753d41..f49d09181312 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -311,7 +311,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 61f25e15fd66..5dbb36edb038 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -442,7 +442,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 025759c7c955..a050ae427108 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -442,7 +442,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 95e287381836..81bad8cd3756 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -311,7 +311,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index ff70580a8f4c..22ec39b5beeb 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -382,7 +382,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8xx.dts b/arch/powerpc/boot/dts/tqm8xx.dts
new file mode 100644
index 000000000000..f6da7ec49a8e
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8xx.dts
@@ -0,0 +1,172 @@
+/*
+ * TQM8XX Device Tree Source
+ *
+ * Heiko Schocher <hs@denx.de>
+ * 2010 DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "TQM8xx";
+        compatible = "tqc,tqm8xx";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &eth0;
+                ethernet1 = &eth1;
+                mdio1 = &phy1;
+                serial0 = &smc1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,860@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <16>;       // 16 bytes
+                        i-cache-line-size = <16>;       // 16 bytes
+                        d-cache-size = <0x1000>;                // L1, 4K
+                        i-cache-size = <0x1000>;                // L1, 4K
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                        interrupts = <15 2>;    // decrementer interrupt
+                        interrupt-parent = <&PIC>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        localbus@fff00100 {
+                compatible = "fsl,mpc860-localbus", "fsl,pq1-localbus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0xfff00100 0x40>;
+
+                ranges = <
+                        0x0 0x0 0x40000000 0x800000
+                >;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x800000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <4>;
+                        device-width = <2>;
+                };
+        };
+
+        soc@fff00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                ranges = <0x0 0xfff00000 0x00004000>;
+
+                phy1: mdio@e00 {
+                        compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
+                        reg = <0xe00 0x188>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        PHY: ethernet-phy@f {
+                                reg = <0xf>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+
+                eth1: ethernet@e00 {
+                        device_type = "network";
+                        compatible = "fsl,mpc866-fec-enet",
+                                     "fsl,pq1-fec-enet";
+                        reg = <0xe00 0x188>;
+                        interrupts = <3 1>;
+                        interrupt-parent = <&PIC>;
+                        phy-handle = <&PHY>;
+                        linux,network-index = <1>;
+                };
+
+                PIC: pic@0 {
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        reg = <0x0 0x24>;
+                        compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
+                };
+
+                cpm@9c0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc860-cpm", "fsl,cpm1";
+                        ranges;
+                        reg = <0x9c0 0x40>;
+                        brg-frequency = <0>;
+                        interrupts = <0 2>;     // cpm error interrupt
+                        interrupt-parent = <&CPM_PIC>;
+
+                        muram@2000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x0 0x2000 0x2000>;
+
+                                data@0 {
+                                        compatible = "fsl,cpm-muram-data";
+                                        reg = <0x0 0x2000>;
+                                };
+                        };
+
+                        brg@9f0 {
+                                compatible = "fsl,mpc860-brg",
+                                             "fsl,cpm1-brg",
+                                             "fsl,cpm-brg";
+                                reg = <0x9f0 0x10>;
+                                clock-frequency = <0>;
+                        };
+
+                        CPM_PIC: pic@930 {
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <1>;
+                                interrupts = <5 2 0 2>;
+                                interrupt-parent = <&PIC>;
+                                reg = <0x930 0x20>;
+                                compatible = "fsl,mpc860-cpm-pic",
+                                             "fsl,cpm1-pic";
+                        };
+
+
+                        smc1: serial@a80 {
+                                device_type = "serial";
+                                compatible = "fsl,mpc860-smc-uart",
+                                             "fsl,cpm1-smc-uart";
+                                reg = <0xa80 0x10 0x3e80 0x40>;
+                                interrupts = <4>;
+                                interrupt-parent = <&CPM_PIC>;
+                                fsl,cpm-brg = <1>;
+                                fsl,cpm-command = <0x90>;
+                        };
+
+                        eth0: ethernet@a00 {
+                                device_type = "network";
+                                compatible = "fsl,mpc860-scc-enet",
+                                             "fsl,cpm1-scc-enet";
+                                reg = <0xa00 0x18 0x3c00 0x100>;
+                                interrupts = <30>;
+                                interrupt-parent = <&CPM_PIC>;
+                                fsl,cpm-command = <0000>;
+                                linux,network-index = <0>;
+                                fixed-link = <0 0 10 0 0>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cfebef9f9123..d32f31a03f58 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -19,7 +19,8 @@ CONFIG_E500=y
 CONFIG_FSL_EMB_PERFMON=y
 CONFIG_BOOKE=y
 CONFIG_FSL_BOOKE=y
-# CONFIG_PHYS_64BIT is not set
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
 CONFIG_SPE=y
 CONFIG_PPC_MMU_NOHASH=y
 CONFIG_PPC_MMU_NOHASH_32=y
@@ -28,7 +29,7 @@ CONFIG_PPC_BOOK3E_MMU=y
 # CONFIG_SMP is not set
 CONFIG_PPC32=y
 CONFIG_WORD_SIZE=32
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_MMU=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_TIME=y
@@ -239,6 +240,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_P1022_DS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
 CONFIG_XES_MPC85xx=y
@@ -311,7 +313,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
@@ -321,7 +323,7 @@ CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
 # CONFIG_PPC_256K_PAGES is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_FORCE_MAX_ZONEORDER=12
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 CONFIG_EXTRA_TARGETS=""
@@ -1122,16 +1124,13 @@ CONFIG_VGA_CONSOLE=y
 # CONFIG_VGACON_SOFT_SCROLLBACK is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_SOUND_OSS_CORE is not set
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
 # CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
 # CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
@@ -1145,12 +1144,7 @@ CONFIG_SND_VMASTER=y
 # CONFIG_SND_SBAWE_SEQ is not set
 # CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_AC97_CODEC=y
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
+# CONFIG_SND_DRIVERS is not set
 CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
@@ -1218,12 +1212,8 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
-CONFIG_SND_PPC=y
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_UA101 is not set
-# CONFIG_SND_USB_USX2Y is not set
-# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_PPC is not set
+# CONFIG_SND_USB is not set
 # CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index f5451d80f19b..f93de10adcda 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -19,7 +19,8 @@ CONFIG_E500=y
 CONFIG_FSL_EMB_PERFMON=y
 CONFIG_BOOKE=y
 CONFIG_FSL_BOOKE=y
-# CONFIG_PHYS_64BIT is not set
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
 CONFIG_SPE=y
 CONFIG_PPC_MMU_NOHASH=y
 CONFIG_PPC_MMU_NOHASH_32=y
@@ -29,7 +30,7 @@ CONFIG_SMP=y
 CONFIG_NR_CPUS=8
 CONFIG_PPC32=y
 CONFIG_WORD_SIZE=32
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_MMU=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_TIME=y
@@ -243,6 +244,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_P1022_DS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
 CONFIG_XES_MPC85xx=y
@@ -316,7 +318,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
@@ -326,7 +328,7 @@ CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
 # CONFIG_PPC_256K_PAGES is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_FORCE_MAX_ZONEORDER=12
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 CONFIG_EXTRA_TARGETS=""
@@ -1127,16 +1129,13 @@ CONFIG_VGA_CONSOLE=y
 # CONFIG_VGACON_SOFT_SCROLLBACK is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_SOUND_OSS_CORE is not set
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
 # CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
 # CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
@@ -1150,12 +1149,7 @@ CONFIG_SND_VMASTER=y
 # CONFIG_SND_SBAWE_SEQ is not set
 # CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_AC97_CODEC=y
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
+# CONFIG_SND_DRIVERS is not set
 CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
@@ -1223,12 +1217,8 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
-CONFIG_SND_PPC=y
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_UA101 is not set
-# CONFIG_SND_USB_USX2Y is not set
-# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_PPC is not set
+# CONFIG_SND_USB is not set
 # CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=y
diff --git a/arch/powerpc/configs/tqm8xx_defconfig b/arch/powerpc/configs/tqm8xx_defconfig
new file mode 100644
index 000000000000..85e654b64874
--- /dev/null
+++ b/arch/powerpc/configs/tqm8xx_defconfig
@@ -0,0 +1,934 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.34-rc1
+# Tue Mar 23 08:22:15 2010
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_PPC_BOOK3S_32 is not set
+# CONFIG_PPC_85xx is not set
+CONFIG_PPC_8xx=y
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_8xx=y
+CONFIG_PPC_MMU_NOHASH=y
+CONFIG_PPC_MMU_NOHASH_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_NR_IRQS=512
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+CONFIG_CPM1=y
+# CONFIG_MPC8XXFADS is not set
+# CONFIG_MPC86XADS is not set
+# CONFIG_MPC885ADS is not set
+# CONFIG_PPC_EP88XC is not set
+# CONFIG_PPC_ADDER875 is not set
+# CONFIG_PPC_MGSUVD is not set
+CONFIG_TQM8XX=y
+
+#
+# MPC8xx CPM Options
+#
+
+#
+# Generic MPC8xx Options
+#
+CONFIG_8xx_COPYBACK=y
+# CONFIG_8xx_GPIO is not set
+# CONFIG_8xx_CPU6 is not set
+# CONFIG_8xx_CPU15 is not set
+CONFIG_NO_UCODE_PATCH=y
+# CONFIG_USB_SOF_UCODE_PATCH is not set
+# CONFIG_I2C_SPI_UCODE_PATCH is not set
+# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_CPM=y
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+CONFIG_8XX_MINIMAL_FPEMU=y
+# CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_MAX_ACTIVE_REGIONS=32
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FSL_SOC=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_PCI_QSPAN is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_MDIO=y
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+CONFIG_DAVICOM_PHY=y
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_XILINX_EMACLITE is not set
+CONFIG_FS_ENET=y
+CONFIG_FS_ENET_HAS_SCC=y
+CONFIG_FS_ENET_HAS_FEC=y
+CONFIG_FS_ENET_MDIO_FEC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CPM=y
+CONFIG_SERIAL_CPM_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_CODE_PATCHING_SELFTEST is not set
+# CONFIG_FTR_FIXUP_SELFTEST is not set
+# CONFIG_MSI_BITMAP_SELFTEST is not set
+# CONFIG_XMON is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+CONFIG_PPC_CLOCK=y
+CONFIG_PPC_LIB_RHEAP=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/include/asm/abs_addr.h b/arch/powerpc/include/asm/abs_addr.h
index 9a846efe6382..5ab0b71531be 100644
--- a/arch/powerpc/include/asm/abs_addr.h
+++ b/arch/powerpc/include/asm/abs_addr.h
@@ -69,7 +69,7 @@ static inline unsigned long phys_to_abs(unsigned long pa)
  * Legacy iSeries Hypervisor calls
  */
 #define iseries_hv_addr(virtaddr)       \
-        (0x8000000000000000 | virt_to_abs(virtaddr))
+        (0x8000000000000000UL | virt_to_abs(virtaddr))
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
index 2048a6aeea91..decad950f11a 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -30,6 +30,7 @@
 #define PPC_STLCX       stringify_in_c(stdcx.)
 #define PPC_CNTLZL      stringify_in_c(cntlzd)
 #define PPC_LR_STKOFF   16
+#define PPC_MIN_STKFRM  112
 
 /* Move to CR, single-entry optimized version. Only available
  * on POWER4 and later.
@@ -55,6 +56,7 @@
 #define PPC_CNTLZL      stringify_in_c(cntlzw)
 #define PPC_MTOCRF      stringify_in_c(mtcrf)
 #define PPC_LR_STKOFF   4
+#define PPC_MIN_STKFRM  16
 
 #endif
 
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index b0b21134f61a..3a40a992e594 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -197,6 +197,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_SAO                     LONG_ASM_CONST(0x0020000000000000)
 #define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0040000000000000)
 #define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0080000000000000)
+#define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0100000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -412,7 +413,7 @@ extern const char *powerpc_base_platform;
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-            CPU_FTR_DSCR | CPU_FTR_SAO)
+            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT)
 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -517,6 +518,10 @@ static inline int cpu_has_feature(unsigned long feature)
                 & feature);
 }
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+#define HBP_NUM 1
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h
index 501189a543d1..0893ab9343a6 100644
--- a/arch/powerpc/include/asm/dbell.h
+++ b/arch/powerpc/include/asm/dbell.h
@@ -27,10 +27,10 @@ enum ppc_dbell {
         PPC_G_DBELL_MC = 4,     /* guest mcheck doorbell */
 };
 
-#ifdef CONFIG_SMP
-extern unsigned long dbell_smp_message[NR_CPUS];
-extern void smp_dbell_message_pass(int target, int msg);
-#endif
+extern void doorbell_message_pass(int target, int msg);
+extern void doorbell_exception(struct pt_regs *regs);
+extern void doorbell_check_self(void);
+extern void doorbell_setup_this_cpu(void);
 
 static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
 {
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 5119b7db3142..de03ca58db5d 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -74,6 +74,7 @@
 #define H_NOT_ENOUGH_RESOURCES -44
 #define H_R_STATE       -45
 #define H_RESCINDEND    -46
+#define H_MULTI_THREADS_ACTIVE -9005
 
 
 /* Long Busy is a condition that can be returned by the firmware
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h b/arch/powerpc/include/asm/hw_breakpoint.h
new file mode 100644
index 000000000000..1c33ec17ca36
--- /dev/null
+++ b/arch/powerpc/include/asm/hw_breakpoint.h
@@ -0,0 +1,74 @@
+/*
+ * PowerPC BookIII S hardware breakpoint definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010, IBM Corporation.
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
+#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
+
+#ifdef  __KERNEL__
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+
+struct arch_hw_breakpoint {
+        bool            extraneous_interrupt;
+        u8              len; /* length of the target data symbol */
+        int             type;
+        unsigned long   address;
+};
+
+#include <linux/kdebug.h>
+#include <asm/reg.h>
+#include <asm/system.h>
+
+struct perf_event;
+struct pmu;
+struct perf_sample_data;
+
+#define HW_BREAKPOINT_ALIGN 0x7
+/* Maximum permissible length of any HW Breakpoint */
+#define HW_BREAKPOINT_LEN 0x8
+
+extern int hw_breakpoint_slots(int type);
+extern int arch_bp_generic_fields(int type, int *gen_bp_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+                                                unsigned long val, void *data);
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
+
+extern struct pmu perf_ops_bp;
+extern void ptrace_triggered(struct perf_event *bp, int nmi,
+                        struct perf_sample_data *data, struct pt_regs *regs);
+static inline void hw_breakpoint_disable(void)
+{
+        set_dabr(0);
+}
+extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
+
+#else   /* CONFIG_HAVE_HW_BREAKPOINT */
+static inline void hw_breakpoint_disable(void) { }
+static inline void thread_change_pc(struct task_struct *tsk,
+                                        struct pt_regs *regs) { }
+#endif  /* CONFIG_HAVE_HW_BREAKPOINT */
+#endif  /* __KERNEL__ */
+#endif  /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index ecba37a91749..67ab5fb7d153 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -300,34 +300,6 @@ extern unsigned int irq_alloc_virt(struct irq_host *host,
  */
 extern void irq_free_virt(unsigned int virq, unsigned int count);
 
-
-/* -- OF helpers -- */
-
-/**
- * irq_create_of_mapping - Map a hardware interrupt into linux virq space
- * @controller: Device node of the interrupt controller
- * @inspec: Interrupt specifier from the device-tree
- * @intsize: Size of the interrupt specifier from the device-tree
- *
- * This function is identical to irq_create_mapping except that it takes
- * as input informations straight from the device-tree (typically the results
- * of the of_irq_map_*() functions.
- */
-extern unsigned int irq_create_of_mapping(struct device_node *controller,
-                                          const u32 *intspec, unsigned int intsize);
-
-/**
- * irq_of_parse_and_map - Parse and Map an interrupt into linux virq space
- * @device: Device node of the device whose interrupt is to be mapped
- * @index: Index of the interrupt to map
- *
- * This function is a wrapper that chains of_irq_map_one() and
- * irq_create_of_mapping() to make things easier to callers
- */
-extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
-
-/* -- End OF helpers -- */
-
 /**
  * irq_early_init - Init irq remapping subsystem
  */
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 6f74d93725a0..8274a2d43925 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -115,7 +115,15 @@ extern void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu);
 extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte);
 extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr);
 extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu);
-extern struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data);
+
+extern void kvmppc_mmu_hpte_cache_map(struct kvm_vcpu *vcpu, struct hpte_cache *pte);
+extern struct hpte_cache *kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu);
+extern void kvmppc_mmu_hpte_destroy(struct kvm_vcpu *vcpu);
+extern int kvmppc_mmu_hpte_init(struct kvm_vcpu *vcpu);
+extern void kvmppc_mmu_invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte);
+extern int kvmppc_mmu_hpte_sysinit(void);
+extern void kvmppc_mmu_hpte_sysexit(void);
+
 extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data);
 extern int kvmppc_st(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data);
 extern void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec);
diff --git a/arch/powerpc/include/asm/kvm_fpu.h b/arch/powerpc/include/asm/kvm_fpu.h
index 94f05de9ad04..c3d4f0518a67 100644
--- a/arch/powerpc/include/asm/kvm_fpu.h
+++ b/arch/powerpc/include/asm/kvm_fpu.h
@@ -22,24 +22,24 @@
 
 #include <linux/types.h>
 
-extern void fps_fres(struct thread_struct *t, u32 *dst, u32 *src1);
-extern void fps_frsqrte(struct thread_struct *t, u32 *dst, u32 *src1);
-extern void fps_fsqrts(struct thread_struct *t, u32 *dst, u32 *src1);
+extern void fps_fres(u64 *fpscr, u32 *dst, u32 *src1);
+extern void fps_frsqrte(u64 *fpscr, u32 *dst, u32 *src1);
+extern void fps_fsqrts(u64 *fpscr, u32 *dst, u32 *src1);
 
-extern void fps_fadds(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2);
-extern void fps_fdivs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2);
-extern void fps_fmuls(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2);
-extern void fps_fsubs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2);
+extern void fps_fadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
+extern void fps_fdivs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
+extern void fps_fmuls(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
+extern void fps_fsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
 
-extern void fps_fmadds(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2,
+extern void fps_fmadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
                        u32 *src3);
-extern void fps_fmsubs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2,
+extern void fps_fmsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
                        u32 *src3);
-extern void fps_fnmadds(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2,
+extern void fps_fnmadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
                         u32 *src3);
-extern void fps_fnmsubs(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2,
+extern void fps_fnmsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
                         u32 *src3);
-extern void fps_fsel(struct thread_struct *t, u32 *dst, u32 *src1, u32 *src2,
+extern void fps_fsel(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
                      u32 *src3);
 
 #define FPD_ONE_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \
@@ -82,4 +82,7 @@ FPD_THREE_IN(fmadd)
 FPD_THREE_IN(fnmsub)
 FPD_THREE_IN(fnmadd)
 
+extern void kvm_cvt_fd(u32 *from, u64 *to, u64 *fpscr);
+extern void kvm_cvt_df(u64 *from, u32 *to, u64 *fpscr);
+
 #endif
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 0c9ad869decd..b0b23c007d6e 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -35,10 +35,17 @@
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
 
 /* We don't currently support large pages. */
+#define KVM_HPAGE_GFN_SHIFT(x)  0
 #define KVM_NR_PAGE_SIZES       1
 #define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
 
-#define HPTEG_CACHE_NUM 1024
+#define HPTEG_CACHE_NUM                 (1 << 15)
+#define HPTEG_HASH_BITS_PTE             13
+#define HPTEG_HASH_BITS_VPTE            13
+#define HPTEG_HASH_BITS_VPTE_LONG       5
+#define HPTEG_HASH_NUM_PTE              (1 << HPTEG_HASH_BITS_PTE)
+#define HPTEG_HASH_NUM_VPTE             (1 << HPTEG_HASH_BITS_VPTE)
+#define HPTEG_HASH_NUM_VPTE_LONG        (1 << HPTEG_HASH_BITS_VPTE_LONG)
 
 struct kvm;
 struct kvm_run;
@@ -151,6 +158,9 @@ struct kvmppc_mmu {
 };
 
 struct hpte_cache {
+        struct hlist_node list_pte;
+        struct hlist_node list_vpte;
+        struct hlist_node list_vpte_long;
         u64 host_va;
         u64 pfn;
         ulong slot;
@@ -282,8 +292,10 @@ struct kvm_vcpu_arch {
         unsigned long pending_exceptions;
 
 #ifdef CONFIG_PPC_BOOK3S
-        struct hpte_cache hpte_cache[HPTEG_CACHE_NUM];
-        int hpte_cache_offset;
+        struct hlist_head hpte_hash_pte[HPTEG_HASH_NUM_PTE];
+        struct hlist_head hpte_hash_vpte[HPTEG_HASH_NUM_VPTE];
+        struct hlist_head hpte_hash_vpte_long[HPTEG_HASH_NUM_VPTE_LONG];
+        int hpte_cache_count;
 #endif
 };
 
diff --git a/arch/powerpc/include/asm/local64.h b/arch/powerpc/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/powerpc/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 9f0fc9e6ce0d..adc8e6cdf339 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -266,6 +266,7 @@ struct machdep_calls {
         void (*suspend_disable_irqs)(void);
         void (*suspend_enable_irqs)(void);
 #endif
+        int (*suspend_disable_cpu)(void);
 
 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
         ssize_t (*cpu_probe)(const char *, size_t);
@@ -277,6 +278,7 @@ extern void e500_idle(void);
 extern void power4_idle(void);
 extern void power4_cpu_offline_powersave(void);
 extern void ppc6xx_idle(void);
+extern void book3e_idle(void);
 
 /*
  * ppc_md contains a copy of the machine description structure for the
@@ -366,8 +368,5 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
 #define machine_late_initcall(mach,fn)          __define_machine_initcall(mach,"7",fn,7)
 #define machine_late_initcall_sync(mach,fn)     __define_machine_initcall(mach,"7s",fn,7s)
 
-void generic_suspend_disable_irqs(void);
-void generic_suspend_enable_irqs(void);
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/arch/powerpc/include/asm/macio.h b/arch/powerpc/include/asm/macio.h
index 675e159b5ef4..7ab82c825a03 100644
--- a/arch/powerpc/include/asm/macio.h
+++ b/arch/powerpc/include/asm/macio.h
@@ -38,7 +38,7 @@ struct macio_dev
 {
         struct macio_bus        *bus;           /* macio bus this device is on */
         struct macio_dev        *media_bay;     /* Device is part of a media bay */
-        struct of_device        ofdev;
+        struct platform_device  ofdev;
         struct device_dma_parameters dma_parms; /* ide needs that */
         int                     n_resources;
         struct resource         resource[MACIO_DEV_COUNT_RESOURCES];
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 74695816205c..87a1d787c5b6 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -193,6 +193,10 @@ struct mmu_psize_def
 {
         unsigned int    shift;  /* number of bits */
         unsigned int    enc;    /* PTE encoding */
+        unsigned int    ind;    /* Corresponding indirect page size shift */
+        unsigned int    flags;
+#define MMU_PAGE_SIZE_DIRECT    0x1     /* Supported as a direct size */
+#define MMU_PAGE_SIZE_INDIRECT  0x2     /* Supported as an indirect size */
 };
 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index e6a30bb1d16a..8c0ab2ca689c 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -21,4 +21,36 @@ struct mpc512x_reset_module {
         u32     rcer;   /* Reset Control Enable Register */
 };
 
+/*
+ * Clock Control Module
+ */
+struct mpc512x_ccm {
+        u32     spmr;   /* System PLL Mode Register */
+        u32     sccr1;  /* System Clock Control Register 1 */
+        u32     sccr2;  /* System Clock Control Register 2 */
+        u32     scfr1;  /* System Clock Frequency Register 1 */
+        u32     scfr2;  /* System Clock Frequency Register 2 */
+        u32     scfr2s; /* System Clock Frequency Shadow Register 2 */
+        u32     bcr;    /* Bread Crumb Register */
+        u32     p0ccr;  /* PSC0 Clock Control Register */
+        u32     p1ccr;  /* PSC1 CCR */
+        u32     p2ccr;  /* PSC2 CCR */
+        u32     p3ccr;  /* PSC3 CCR */
+        u32     p4ccr;  /* PSC4 CCR */
+        u32     p5ccr;  /* PSC5 CCR */
+        u32     p6ccr;  /* PSC6 CCR */
+        u32     p7ccr;  /* PSC7 CCR */
+        u32     p8ccr;  /* PSC8 CCR */
+        u32     p9ccr;  /* PSC9 CCR */
+        u32     p10ccr; /* PSC10 CCR */
+        u32     p11ccr; /* PSC11 CCR */
+        u32     spccr;  /* SPDIF Clock Control Register */
+        u32     cccr;   /* CFM Clock Control Register */
+        u32     dccr;   /* DIU Clock Control Register */
+        u32     m1ccr;  /* MSCAN1 CCR */
+        u32     m2ccr;  /* MSCAN2 CCR */
+        u32     m3ccr;  /* MSCAN3 CCR */
+        u32     m4ccr;  /* MSCAN4 CCR */
+        u8      res[0x98]; /* Reserved */
+};
 #endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/include/asm/of_device.h b/arch/powerpc/include/asm/of_device.h
deleted file mode 100644
index 444e97e2982e..000000000000
--- a/arch/powerpc/include/asm/of_device.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _ASM_POWERPC_OF_DEVICE_H
-#define _ASM_POWERPC_OF_DEVICE_H
-#ifdef __KERNEL__
-
-#include <linux/device.h>
-#include <linux/of.h>
-
-/*
- * The of_device is a kind of "base class" that is a superset of
- * struct device for use by devices attached to an OF node and
- * probed using OF properties.
- */
-struct of_device
-{
-        struct device           dev;            /* Generic device interface */
-        struct pdev_archdata    archdata;
-};
-
-extern struct of_device *of_device_alloc(struct device_node *np,
-                                         const char *bus_id,
-                                         struct device *parent);
-
-extern int of_device_uevent(struct device *dev,
-                            struct kobj_uevent_env *env);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_OF_DEVICE_H */
diff --git a/arch/powerpc/include/asm/of_platform.h b/arch/powerpc/include/asm/of_platform.h
deleted file mode 100644
index d4aaa3489440..000000000000
--- a/arch/powerpc/include/asm/of_platform.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef _ASM_POWERPC_OF_PLATFORM_H
-#define _ASM_POWERPC_OF_PLATFORM_H
-/*
- *    Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
- *                       <benh@kernel.crashing.org>
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- *
- */
-
-/* Platform devices and busses creation */
-extern struct of_device *of_platform_device_create(struct device_node *np,
-                                                   const char *bus_id,
-                                                   struct device *parent);
-/* pseudo "matches" value to not do deep probe */
-#define OF_NO_DEEP_PROBE ((struct of_device_id *)-1)
-
-extern int of_platform_bus_probe(struct device_node *root,
-                                 const struct of_device_id *matches,
-                                 struct device *parent);
-
-extern struct of_device *of_find_device_by_phandle(phandle ph);
-
-extern void of_instantiate_rtc(void);
-
-#endif  /* _ASM_POWERPC_OF_PLATFORM_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 8ce7963ad41d..1ff6662f7faf 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -146,7 +146,7 @@ struct paca_struct {
 extern struct paca_struct *paca;
 extern __initdata struct paca_struct boot_paca;
 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
-
+extern void setup_paca(struct paca_struct *new_paca);
 extern void allocate_pacas(void);
 extern void free_unused_pacas(void);
 
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 76e1f313a58e..51e9e6f90d12 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -303,13 +303,8 @@ extern void pcibios_free_controller(struct pci_controller *phb);
 extern void pcibios_setup_phb_resources(struct pci_controller *hose);
 
 #ifdef CONFIG_PCI
-extern unsigned long pci_address_to_pio(phys_addr_t address);
 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 #else
-static inline unsigned long pci_address_to_pio(phys_addr_t address)
-{
-        return (unsigned long)-1;
-}
 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 {
         return 0;
diff --git a/arch/powerpc/include/asm/percpu.h b/arch/powerpc/include/asm/percpu.h
index f879252b7ea6..2cedefddba37 100644
--- a/arch/powerpc/include/asm/percpu.h
+++ b/arch/powerpc/include/asm/percpu.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_POWERPC_PERCPU_H_
 #define _ASM_POWERPC_PERCPU_H_
 #ifdef __powerpc64__
-#include <linux/compiler.h>
 
 /*
  * Same as asm-generic/percpu.h, except that we store the per cpu offset
@@ -12,9 +11,7 @@
 
 #include <asm/paca.h>
 
-#define __per_cpu_offset(cpu) (paca[cpu].data_offset)
 #define __my_cpu_offset local_paca->data_offset
-#define per_cpu_offset(x) (__per_cpu_offset(x))
 
 #endif /* CONFIG_SMP */
 #endif /* __powerpc64__ */
diff --git a/arch/powerpc/include/asm/perf_event.h b/arch/powerpc/include/asm/perf_event.h
index e6d4ce69b126..5c16b891d501 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -21,3 +21,15 @@
 #ifdef CONFIG_FSL_EMB_PERF_EVENT
 #include <asm/perf_event_fsl_emb.h>
 #endif
+
+#ifdef CONFIG_PERF_EVENTS
+#include <asm/ptrace.h>
+#include <asm/reg.h>
+
+#define perf_arch_fetch_caller_regs(regs, __ip)                 \
+        do {                                                    \
+                (regs)->nip = __ip;                             \
+                (regs)->gpr[1] = *(unsigned long *)__get_SP();  \
+                asm volatile("mfmsr %0" : "=r" ((regs)->msr));  \
+        } while (0)
+#endif
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index d553bbeb726c..43adc8b819ed 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -52,13 +52,17 @@
 #define PPC_INST_WAIT                   0x7c00007c
 #define PPC_INST_TLBIVAX                0x7c000624
 #define PPC_INST_TLBSRX_DOT             0x7c0006a5
+#define PPC_INST_XXLOR                  0xf0000510
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
 #define __PPC_RB(b)     (((b) & 0x1f) << 11)
 #define __PPC_RS(s)     (((s) & 0x1f) << 21)
 #define __PPC_RT(s)     __PPC_RS(s)
+#define __PPC_XA(a)     ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
+#define __PPC_XB(b)     ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
 #define __PPC_XS(s)     ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
+#define __PPC_XT(s)     __PPC_XS(s)
 #define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
 #define __PPC_WC(w)     (((w) & 0x3) << 21)
 /*
@@ -106,9 +110,12 @@
  * the 128 bit load store instructions based on that.
  */
 #define VSX_XX1(s, a, b)        (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
+#define VSX_XX3(t, a, b)        (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
 #define STXVD2X(s, a, b)        stringify_in_c(.long PPC_INST_STXVD2X | \
                                                VSX_XX1((s), (a), (b)))
 #define LXVD2X(s, a, b)         stringify_in_c(.long PPC_INST_LXVD2X | \
                                                VSX_XX1((s), (a), (b)))
+#define XXLOR(t, a, b)          stringify_in_c(.long PPC_INST_XXLOR | \
+                                               VSX_XX3((t), (a), (b)))
 
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 7492fe8ad6e4..19c05b0f74be 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -209,6 +209,14 @@ struct thread_struct {
 #ifdef CONFIG_PPC64
         unsigned long   start_tb;       /* Start purr when proc switched in */
         unsigned long   accum_tb;       /* Total accumilated purr for process */
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        struct perf_event *ptrace_bps[HBP_NUM];
+        /*
+         * Helps identify source of single-step exception and subsequent
+         * hw-breakpoint enablement
+         */
+        struct perf_event *last_hit_ubp;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
         unsigned long   dabr;           /* Data address breakpoint register */
 #ifdef CONFIG_ALTIVEC
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index ddd408a93b5a..ae26f2efd089 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -17,9 +17,6 @@
  * 2 of the License, or (at your option) any later version.
  */
 #include <linux/types.h>
-#include <linux/of_fdt.h>
-#include <linux/proc_fs.h>
-#include <linux/platform_device.h>
 #include <asm/irq.h>
 #include <asm/atomic.h>
 
@@ -43,49 +40,14 @@ extern void pci_create_OF_bus_map(void);
  * OF address retreival & translation
  */
 
-/* Translate an OF address block into a CPU physical address
- */
-extern u64 of_translate_address(struct device_node *np, const u32 *addr);
-
 /* Translate a DMA address from device space to CPU space */
 extern u64 of_translate_dma_address(struct device_node *dev,
                                     const u32 *in_addr);
 
-/* Extract an address from a device, returns the region size and
- * the address space flags too. The PCI version uses a BAR number
- * instead of an absolute index
- */
-extern const u32 *of_get_address(struct device_node *dev, int index,
-                           u64 *size, unsigned int *flags);
 #ifdef CONFIG_PCI
-extern const u32 *of_get_pci_address(struct device_node *dev, int bar_no,
-                               u64 *size, unsigned int *flags);
-#else
-static inline const u32 *of_get_pci_address(struct device_node *dev,
-                int bar_no, u64 *size, unsigned int *flags)
-{
-        return NULL;
-}
-#endif /* CONFIG_PCI */
-
-/* Get an address as a resource. Note that if your address is
- * a PIO address, the conversion will fail if the physical address
- * can't be internally converted to an IO token with
- * pci_address_to_pio(), that is because it's either called to early
- * or it can't be matched to any host bridge IO space
- */
-extern int of_address_to_resource(struct device_node *dev, int index,
-                                  struct resource *r);
-#ifdef CONFIG_PCI
-extern int of_pci_address_to_resource(struct device_node *dev, int bar,
-                                      struct resource *r);
-#else
-static inline int of_pci_address_to_resource(struct device_node *dev, int bar,
-                struct resource *r)
-{
-        return -ENOSYS;
-}
-#endif /* CONFIG_PCI */
+extern unsigned long pci_address_to_pio(phys_addr_t address);
+#define pci_address_to_pio pci_address_to_pio
+#endif  /* CONFIG_PCI */
 
 /* Parse the ibm,dma-window property of an OF node into the busno, phys and
  * size parameters.
@@ -104,69 +66,12 @@ struct device_node *of_find_next_cache_node(struct device_node *np);
 /* Get the MAC address */
 extern const void *of_get_mac_address(struct device_node *np);
 
-/*
- * OF interrupt mapping
- */
-
-/* This structure is returned when an interrupt is mapped. The controller
- * field needs to be put() after use
- */
-
-#define OF_MAX_IRQ_SPEC          4 /* We handle specifiers of at most 4 cells */
-
-struct of_irq {
-        struct device_node *controller; /* Interrupt controller node */
-        u32 size;                       /* Specifier size */
-        u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
-};
-
-/**
- * of_irq_map_init - Initialize the irq remapper
- * @flags:      flags defining workarounds to enable
- *
- * Some machines have bugs in the device-tree which require certain workarounds
- * to be applied. Call this before any interrupt mapping attempts to enable
- * those workarounds.
- */
-#define OF_IMAP_OLDWORLD_MAC    0x00000001
-#define OF_IMAP_NO_PHANDLE      0x00000002
-
-extern void of_irq_map_init(unsigned int flags);
-
-/**
- * of_irq_map_raw - Low level interrupt tree parsing
- * @parent:     the device interrupt parent
- * @intspec:    interrupt specifier ("interrupts" property of the device)
- * @ointsize:   size of the passed in interrupt specifier
- * @addr:       address specifier (start of "reg" property of the device)
- * @out_irq:    structure of_irq filled by this function
- *
- * Returns 0 on success and a negative number on error
- *
- * This function is a low-level interrupt tree walking function. It
- * can be used to do a partial walk with synthetized reg and interrupts
- * properties, for example when resolving PCI interrupts when no device
- * node exist for the parent.
- *
- */
-
-extern int of_irq_map_raw(struct device_node *parent, const u32 *intspec,
-                          u32 ointsize, const u32 *addr,
-                          struct of_irq *out_irq);
-
-
-/**
- * of_irq_map_one - Resolve an interrupt for a device
- * @device:     the device whose interrupt is to be resolved
- * @index:      index of the interrupt to resolve
- * @out_irq:    structure of_irq filled by this function
- *
- * This function resolves an interrupt, walking the tree, for a given
- * device-tree node. It's the high level pendant to of_irq_map_raw().
- * It also implements the workarounds for OldWolrd Macs.
- */
-extern int of_irq_map_one(struct device_node *device, int index,
-                          struct of_irq *out_irq);
+#ifdef CONFIG_NUMA
+extern int of_node_to_nid(struct device_node *device);
+#else
+static inline int of_node_to_nid(struct device_node *device) { return 0; }
+#endif
+#define of_node_to_nid of_node_to_nid
 
 /**
  * of_irq_map_pci - Resolve the interrupt for a PCI device
@@ -180,19 +85,19 @@ extern int of_irq_map_one(struct device_node *device, int index,
  * resolving using the OF tree walking.
  */
 struct pci_dev;
+struct of_irq;
 extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
 
-extern int of_irq_to_resource(struct device_node *dev, int index,
-                        struct resource *r);
+extern void of_instantiate_rtc(void);
 
-/**
- * of_iomap - Maps the memory mapped IO for a given device_node
- * @device:     the device whose io range will be mapped
- * @index:      index of the io range
- *
- * Returns a pointer to the mapped memory
- */
-extern void __iomem *of_iomap(struct device_node *device, int index);
+/* These includes are put at the bottom because they may contain things
+ * that are overridden by this file.  Ideally they shouldn't be included
+ * by this file, but there are a bunch of .c files that currently depend
+ * on it.  Eventually they will be cleaned up. */
+#include <linux/of_fdt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
 
 #endif /* __KERNEL__ */
 #endif /* _POWERPC_PROM_H */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index d62fdf4e504b..d8be016d2ede 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -890,7 +890,7 @@
 #ifndef __ASSEMBLY__
 #define mfmsr()         ({unsigned long rval; \
                         asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 #define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
                                      : : "r" (v) : "memory")
 #define mtmsrd(v)       __mtmsrd((v), 0)
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 2360317179a9..667a498eaee1 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -29,8 +29,8 @@
 #if defined(CONFIG_PPC_BOOK3E_64)
 #define MSR_            MSR_ME | MSR_CE
 #define MSR_KERNEL      MSR_ | MSR_CM
-#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64      MSR_USER32 | MSR_CM
+#define MSR_USER32      MSR_ | MSR_PR | MSR_EE | MSR_DE
+#define MSR_USER64      MSR_USER32 | MSR_CM | MSR_DE
 #elif defined (CONFIG_40x)
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
@@ -62,6 +62,7 @@
 #define SPRN_TLB0PS     0x158   /* TLB 0 Page Size Register */
 #define SPRN_MAS5_MAS6  0x15c   /* MMU Assist Register 5 || 6 */
 #define SPRN_MAS8_MAS1  0x15d   /* MMU Assist Register 8 || 1 */
+#define SPRN_EPTCFG     0x15e   /* Embedded Page Table Config */
 #define SPRN_MAS7_MAS3  0x174   /* MMU Assist Register 7 || 3 */
 #define SPRN_MAS0_MAS1  0x175   /* MMU Assist Register 0 || 1 */
 #define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 20de73c36682..3d35f8ae377e 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -63,6 +63,14 @@ struct rtas_t {
         struct device_node *dev;        /* virtual address pointer */
 };
 
+struct rtas_suspend_me_data {
+        atomic_t working; /* number of cpus accessing this struct */
+        atomic_t done;
+        int token; /* ibm,suspend-me */
+        atomic_t error;
+        struct completion *complete; /* wait on this until working == 0 */
+};
+
 /* RTAS event classes */
 #define RTAS_INTERNAL_ERROR             0x80000000 /* set bit 0 */
 #define RTAS_EPOW_WARNING               0x40000000 /* set bit 1 */
@@ -137,6 +145,9 @@ struct rtas_t {
 #define RTAS_TYPE_PMGM_CONFIG_CHANGE    0x70
 #define RTAS_TYPE_PMGM_SERVICE_PROC     0x71
 
+/* RTAS check-exception vector offset */
+#define RTAS_VECTOR_EXTERNAL_INTERRUPT  0x500
+
 struct rtas_error_log {
         unsigned long version:8;                /* Architectural version */
         unsigned long severity:3;               /* Severity level of error */
@@ -174,6 +185,8 @@ extern int rtas_set_indicator(int indicator, int index, int new_value);
 extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
 extern void rtas_progress(char *s, unsigned short hex);
 extern void rtas_initialize(void);
+extern int rtas_suspend_cpu(struct rtas_suspend_me_data *data);
+extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data);
 
 struct rtc_time;
 extern unsigned long rtas_get_boot_time(void);
diff --git a/arch/powerpc/include/asm/smu.h b/arch/powerpc/include/asm/smu.h
index 7ae2753da565..e3bdada8c542 100644
--- a/arch/powerpc/include/asm/smu.h
+++ b/arch/powerpc/include/asm/smu.h
@@ -457,8 +457,8 @@ extern void smu_poll(void);
  */
 extern int smu_init(void);
 extern int smu_present(void);
-struct of_device;
-extern struct of_device *smu_get_ofdev(void);
+struct platform_device;
+extern struct platform_device *smu_get_ofdev(void);
 
 
 /*
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index a6297c67c3d6..6c294acac848 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -515,11 +515,8 @@ __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
  * powers of 2 writes until it reaches sufficient alignment).
  *
  * Based on this we disable the IP header alignment in network drivers.
- * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
- * cacheline alignment of buffers.
  */
 #define NET_IP_ALIGN    0
-#define NET_SKB_PAD     L1_CACHE_BYTES
 
 #define cmpxchg64(ptr, o, n)                                            \
   ({                                                                    \
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 27ccb764fdab..dc779dfcf258 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -28,16 +28,12 @@
 extern unsigned long tb_ticks_per_jiffy;
 extern unsigned long tb_ticks_per_usec;
 extern unsigned long tb_ticks_per_sec;
-extern u64 tb_to_xs;
-extern unsigned      tb_to_us;
 
 struct rtc_time;
 extern void to_tm(int tim, struct rtc_time * tm);
 extern void GregorianDay(struct rtc_time *tm);
-extern time_t last_rtc_update;
 
 extern void generic_calibrate_decr(void);
-extern void wakeup_decrementer(void);
 extern void snapshot_timebase(void);
 
 extern void set_dec_cpu6(unsigned int val);
@@ -204,9 +200,6 @@ static inline unsigned long tb_ticks_since(unsigned long tstamp)
 extern u64 mulhdu(u64, u64);
 #endif
 
-extern void smp_space_timers(unsigned int);
-
-extern unsigned mulhwu_scale_factor(unsigned, unsigned);
 extern void div128_by_32(u64 dividend_high, u64 dividend_low,
                          unsigned divisor, struct div_result *dr);
 
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 32adf7280720..afe4aaa65c3b 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -41,8 +41,6 @@ static inline int cpu_to_node(int cpu)
                                cpu_all_mask :                           \
                                node_to_cpumask_map[node])
 
-int of_node_to_nid(struct device_node *device);
-
 struct pci_bus;
 #ifdef CONFIG_PCI
 extern int pcibus_to_node(struct pci_bus *bus);
@@ -87,6 +85,9 @@ static inline int pcibus_to_node(struct pci_bus *bus)
         .balance_interval       = 1,                                    \
 }
 
+extern int __node_distance(int, int);
+#define node_distance(a, b) __node_distance(a, b)
+
 extern void __init dump_numa_cpu_topology(void);
 
 extern int sysfs_add_device_to_node(struct sys_device *dev, int nid);
@@ -94,11 +95,6 @@ extern void sysfs_remove_device_from_node(struct sys_device *dev, int nid);
 
 #else
 
-static inline int of_node_to_nid(struct device_node *device)
-{
-        return 0;
-}
-
 static inline void dump_numa_cpu_topology(void) {}
 
 static inline int sysfs_add_device_to_node(struct sys_device *dev, int nid)
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
index 13c2c283e178..08679c5319b8 100644
--- a/arch/powerpc/include/asm/vdso_datapage.h
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -85,6 +85,7 @@ struct vdso_data {
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         struct timespec stamp_xtime;    /* xtime as at tb_orig_stamp */
+        __u32 stamp_sec_fraction;       /* fractional seconds of stamp_xtime */
         __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls  */
         __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
 };
@@ -105,6 +106,7 @@ struct vdso_data {
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         struct timespec stamp_xtime;    /* xtime as at tb_orig_stamp */
+        __u32 stamp_sec_fraction;       /* fractional seconds of stamp_xtime */
         __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
         __u32 dcache_block_size;        /* L1 d-cache block size     */
         __u32 icache_block_size;        /* L1 i-cache block size     */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 58d0572de6f9..1dda70129141 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -34,13 +34,14 @@ obj-y				+= vdso32/
 obj-$(CONFIG_PPC64)             += setup_64.o sys_ppc32.o \
                                    signal_64.o ptrace32.o \
                                    paca.o nvram_64.o firmware.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += hw_breakpoint.o
 obj-$(CONFIG_PPC_BOOK3S_64)     += cpu_setup_ppc970.o cpu_setup_pa6t.o
 obj64-$(CONFIG_RELOCATABLE)     += reloc_64.o
-obj-$(CONFIG_PPC_BOOK3E_64)     += exceptions-64e.o
+obj-$(CONFIG_PPC_BOOK3E_64)     += exceptions-64e.o idle_book3e.o
 obj-$(CONFIG_PPC64)             += vdso64/
 obj-$(CONFIG_ALTIVEC)           += vecemu.o
 obj-$(CONFIG_PPC_970_NAP)       += idle_power4.o
-obj-$(CONFIG_PPC_OF)            += of_device.o of_platform.o prom_parse.o
+obj-$(CONFIG_PPC_OF)            += of_platform.o prom_parse.o
 obj-$(CONFIG_PPC_CLOCK)         += clock.o
 procfs-y                        := proc_powerpc.o
 obj-$(CONFIG_PROC_FS)           += $(procfs-y)
@@ -67,6 +68,7 @@ obj64-$(CONFIG_HIBERNATION)	+= swsusp_asm64.o
 obj-$(CONFIG_MODULES)           += module.o module_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_44x)               += cpu_setup_44x.o
 obj-$(CONFIG_FSL_BOOKE)         += cpu_setup_fsl_booke.o dbell.o
+obj-$(CONFIG_PPC_BOOK3E_64)     += dbell.o
 
 extra-y                         := head_$(CONFIG_WORD_SIZE).o
 extra-$(CONFIG_PPC_BOOK3E_32)   := head_new_booke.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 496cc5b3984f..1c0607ddccc0 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -194,7 +194,6 @@ int main(void)
         DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr));
         DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
         DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
-        DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset));
         DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
         DEFINE(PACA_KVM_SVCPU, offsetof(struct paca_struct, shadow_vcpu));
@@ -342,6 +341,7 @@ int main(void)
         DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
         DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
         DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
+        DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
         DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
         DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
         DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 87aa0f3c6047..65e2b4e10f97 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1364,10 +1364,10 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_4xx,
                 .platform               = "ppc405",
         },
-        {       /* 405EX */
-                .pvr_mask               = 0xffff0004,
-                .pvr_value              = 0x12910004,
-                .cpu_name               = "405EX",
+        {       /* 405EX Rev. A/B with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910007,
+                .cpu_name               = "405EX Rev. A/B",
                 .cpu_features           = CPU_FTRS_40X,
                 .cpu_user_features      = PPC_FEATURE_32 |
                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
@@ -1377,10 +1377,114 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_4xx,
                 .platform               = "ppc405",
         },
-        {       /* 405EXr */
-                .pvr_mask               = 0xffff0004,
+        {       /* 405EX Rev. C without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x1291000d,
+                .cpu_name               = "405EX Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EX Rev. C with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x1291000f,
+                .cpu_name               = "405EX Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EX Rev. D without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910003,
+                .cpu_name               = "405EX Rev. D",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EX Rev. D with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910005,
+                .cpu_name               = "405EX Rev. D",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. A/B without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910001,
+                .cpu_name               = "405EXr Rev. A/B",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. C without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910009,
+                .cpu_name               = "405EXr Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. C with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x1291000b,
+                .cpu_name               = "405EXr Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. D without Security */
+                .pvr_mask               = 0xffff000f,
                 .pvr_value              = 0x12910000,
-                .cpu_name               = "405EXr",
+                .cpu_name               = "405EXr Rev. D",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. D with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910002,
+                .cpu_name               = "405EXr Rev. D",
                 .cpu_features           = CPU_FTRS_40X,
                 .cpu_user_features      = PPC_FEATURE_32 |
                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 40f524643ba6..8e05c16344e4 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -128,9 +128,9 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
         if (!csize)
                 return 0;
 
-        csize = min(csize, PAGE_SIZE);
+        csize = min_t(size_t, csize, PAGE_SIZE);
 
-        if (pfn < max_pfn) {
+        if ((min_low_pfn < pfn) && (pfn < max_pfn)) {
                 vaddr = __va(pfn << PAGE_SHIFT);
                 csize = copy_oldmem_vaddr(vaddr, buf, csize, offset, userbuf);
         } else {
diff --git a/arch/powerpc/kernel/dbell.c b/arch/powerpc/kernel/dbell.c
index 1493734cd871..3307a52d797f 100644
--- a/arch/powerpc/kernel/dbell.c
+++ b/arch/powerpc/kernel/dbell.c
@@ -13,32 +13,88 @@
 #include <linux/kernel.h>
 #include <linux/smp.h>
 #include <linux/threads.h>
+#include <linux/percpu.h>
 
 #include <asm/dbell.h>
+#include <asm/irq_regs.h>
 
 #ifdef CONFIG_SMP
-unsigned long dbell_smp_message[NR_CPUS];
+struct doorbell_cpu_info {
+        unsigned long   messages;       /* current messages bits */
+        unsigned int    tag;            /* tag value */
+};
 
-void smp_dbell_message_pass(int target, int msg)
+static DEFINE_PER_CPU(struct doorbell_cpu_info, doorbell_cpu_info);
+
+void doorbell_setup_this_cpu(void)
+{
+        struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
+
+        info->messages = 0;
+        info->tag = mfspr(SPRN_PIR) & 0x3fff;
+}
+
+void doorbell_message_pass(int target, int msg)
 {
+        struct doorbell_cpu_info *info;
         int i;
 
-        if(target < NR_CPUS) {
-                set_bit(msg, &dbell_smp_message[target]);
-                ppc_msgsnd(PPC_DBELL, 0, target);
+        if (target < NR_CPUS) {
+                info = &per_cpu(doorbell_cpu_info, target);
+                set_bit(msg, &info->messages);
+                ppc_msgsnd(PPC_DBELL, 0, info->tag);
         }
-        else if(target == MSG_ALL_BUT_SELF) {
+        else if (target == MSG_ALL_BUT_SELF) {
                 for_each_online_cpu(i) {
                         if (i == smp_processor_id())
                                 continue;
-                        set_bit(msg, &dbell_smp_message[i]);
-                        ppc_msgsnd(PPC_DBELL, 0, i);
+                        info = &per_cpu(doorbell_cpu_info, i);
+                        set_bit(msg, &info->messages);
+                        ppc_msgsnd(PPC_DBELL, 0, info->tag);
                 }
         }
         else { /* target == MSG_ALL */
-                for_each_online_cpu(i)
-                        set_bit(msg, &dbell_smp_message[i]);
+                for_each_online_cpu(i) {
+                        info = &per_cpu(doorbell_cpu_info, i);
+                        set_bit(msg, &info->messages);
+                }
                 ppc_msgsnd(PPC_DBELL, PPC_DBELL_MSG_BRDCAST, 0);
         }
 }
-#endif
+
+void doorbell_exception(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+        struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
+        int msg;
+
+        /* Warning: regs can be NULL when called from irq enable */
+
+        if (!info->messages || (num_online_cpus() < 2))
+                goto out;
+
+        for (msg = 0; msg < 4; msg++)
+                if (test_and_clear_bit(msg, &info->messages))
+                        smp_message_recv(msg);
+
+out:
+        set_irq_regs(old_regs);
+}
+
+void doorbell_check_self(void)
+{
+        struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
+
+        if (!info->messages)
+                return;
+
+        ppc_msgsnd(PPC_DBELL, 0, info->tag);
+}
+
+#else /* CONFIG_SMP */
+void doorbell_exception(struct pt_regs *regs)
+{
+        printk(KERN_WARNING "Received doorbell on non-smp system\n");
+}
+#endif /* CONFIG_SMP */
+
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 02f724f36753..4295e0b94b2d 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -82,17 +82,9 @@ static struct notifier_block ppc_swiotlb_plat_bus_notifier = {
         .priority = 0,
 };
 
-static struct notifier_block ppc_swiotlb_of_bus_notifier = {
-        .notifier_call = ppc_swiotlb_bus_notify,
-        .priority = 0,
-};
-
 int __init swiotlb_setup_bus_notifier(void)
 {
         bus_register_notifier(&platform_bus_type,
                               &ppc_swiotlb_plat_bus_notifier);
-        bus_register_notifier(&of_platform_bus_type,
-                              &ppc_swiotlb_of_bus_notifier);
-
         return 0;
 }
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 24dcc0ecf246..5c43063d2506 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -191,6 +191,12 @@ exc_##n##_bad_stack:							    \
         sth     r1,PACA_TRAP_SAVE(r13); /* store trap */                    \
         b       bad_stack_book3e;       /* bad stack error */
 
+/* WARNING: If you change the layout of this stub, make sure you chcek
+        *   the debug exception handler which handles single stepping
+        *   into exceptions from userspace, and the MM code in
+        *   arch/powerpc/mm/tlb_nohash.c which patches the branch here
+        *   and would need to be updated if that branch is moved
+        */
 #define EXCEPTION_STUB(loc, label)                                      \
         . = interrupt_base_book3e + loc;                                \
         nop;    /* To make debug interrupts happy */                    \
@@ -204,11 +210,30 @@ exc_##n##_bad_stack:							    \
         lis     r,TSR_FIS@h;                                            \
         mtspr   SPRN_TSR,r
 
+/* Used by asynchronous interrupt that may happen in the idle loop.
+ *
+ * This check if the thread was in the idle loop, and if yes, returns
+ * to the caller rather than the PC. This is to avoid a race if
+ * interrupts happen before the wait instruction.
+ */
+#define CHECK_NAPPING()                                                 \
+        clrrdi  r11,r1,THREAD_SHIFT;                                    \
+        ld      r10,TI_LOCAL_FLAGS(r11);                                \
+        andi.   r9,r10,_TLF_NAPPING;                                    \
+        beq+    1f;                                                     \
+        ld      r8,_LINK(r1);                                           \
+        rlwinm  r7,r10,0,~_TLF_NAPPING;                                 \
+        std     r8,_NIP(r1);                                            \
+        std     r7,TI_LOCAL_FLAGS(r11);                                 \
+1:
+
+
 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)                   \
         START_EXCEPTION(label);                                         \
         NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)      \
         EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL)         \
         ack(r8);                                                        \
+        CHECK_NAPPING();                                                \
         addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
         bl      hdlr;                                                   \
         b       .ret_from_except_lite;
@@ -246,11 +271,9 @@ interrupt_base_book3e:					/* fake trap */
         EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
         EXCEPTION_STUB(0x1c0, data_tlb_miss)
         EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
+        EXCEPTION_STUB(0x280, doorbell)
+        EXCEPTION_STUB(0x2a0, doorbell_crit)
 
-#if 0
-        EXCEPTION_STUB(0x280, processor_doorbell)
-        EXCEPTION_STUB(0x220, processor_doorbell_crit)
-#endif
         .globl interrupt_end_book3e
 interrupt_end_book3e:
 
@@ -259,6 +282,7 @@ interrupt_end_book3e:
         CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
 //      bl      special_reg_save_crit
+//      CHECK_NAPPING();
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
 //      bl      .critical_exception
 //      b       ret_from_crit_except
@@ -270,6 +294,7 @@ interrupt_end_book3e:
 //      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
 //      bl      special_reg_save_mc
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      CHECK_NAPPING();
 //      bl      .machine_check_exception
 //      b       ret_from_mc_except
         b       .
@@ -340,6 +365,7 @@ interrupt_end_book3e:
         CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
 //      bl      special_reg_save_crit
+//      CHECK_NAPPING();
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
 //      bl      .unknown_exception
 //      b       ret_from_crit_except
@@ -428,6 +454,20 @@ interrupt_end_book3e:
 kernel_dbg_exc:
         b       .       /* NYI */
 
+/* Doorbell interrupt */
+        MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
+
+/* Doorbell critical Interrupt */
+        START_EXCEPTION(doorbell_crit);
+        CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      bl      special_reg_save_crit
+//      CHECK_NAPPING();
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .doorbell_critical_exception
+//      b       ret_from_crit_except
+        b       .
+
 
 /*
  * An interrupt came in while soft-disabled; clear EE in SRR1,
@@ -563,6 +603,8 @@ BAD_STACK_TRAMPOLINE(0xd00)
 BAD_STACK_TRAMPOLINE(0xe00)
 BAD_STACK_TRAMPOLINE(0xf00)
 BAD_STACK_TRAMPOLINE(0xf20)
+BAD_STACK_TRAMPOLINE(0x2070)
+BAD_STACK_TRAMPOLINE(0x2080)
 
         .globl  bad_stack_book3e
 bad_stack_book3e:
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 3e423fbad6bc..f53029a01554 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -828,6 +828,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
 
 /* We have a data breakpoint exception - handle it */
 handle_dabr_fault:
+        bl      .save_nvgprs
         ld      r4,_DAR(r1)
         ld      r5,_DSISR(r1)
         addi    r3,r1,STACK_FRAME_OVERHEAD
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
new file mode 100644
index 000000000000..5ecd0401cdb1
--- /dev/null
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -0,0 +1,364 @@
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers. Derived from
+ * "arch/x86/kernel/hw_breakpoint.c"
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010 IBM Corporation
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#include <linux/hw_breakpoint.h>
+#include <linux/notifier.h>
+#include <linux/kprobes.h>
+#include <linux/percpu.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/hw_breakpoint.h>
+#include <asm/processor.h>
+#include <asm/sstep.h>
+#include <asm/uaccess.h>
+
+/*
+ * Stores the breakpoints currently in use on each breakpoint address
+ * register for every cpu
+ */
+static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
+
+/*
+ * Returns total number of data or instruction breakpoints available.
+ */
+int hw_breakpoint_slots(int type)
+{
+        if (type == TYPE_DATA)
+                return HBP_NUM;
+        return 0;               /* no instruction breakpoints available */
+}
+
+/*
+ * Install a perf counter breakpoint.
+ *
+ * We seek a free debug address register and use it for this
+ * breakpoint.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+        *slot = bp;
+
+        /*
+         * Do not install DABR values if the instruction must be single-stepped.
+         * If so, DABR will be populated in single_step_dabr_instruction().
+         */
+        if (current->thread.last_hit_ubp != bp)
+                set_dabr(info->address | info->type | DABR_TRANSLATION);
+
+        return 0;
+}
+
+/*
+ * Uninstall the breakpoint contained in the given counter.
+ *
+ * First we search the debug address register it uses and then we disable
+ * it.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+        struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+        if (*slot != bp) {
+                WARN_ONCE(1, "Can't find the breakpoint");
+                return;
+        }
+
+        *slot = NULL;
+        set_dabr(0);
+}
+
+/*
+ * Perform cleanup of arch-specific counters during unregistration
+ * of the perf-event
+ */
+void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+        /*
+         * If the breakpoint is unregistered between a hw_breakpoint_handler()
+         * and the single_step_dabr_instruction(), then cleanup the breakpoint
+         * restoration variables to prevent dangling pointers.
+         */
+        if (bp->ctx->task)
+                bp->ctx->task->thread.last_hit_ubp = NULL;
+}
+
+/*
+ * Check for virtual address in kernel space.
+ */
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        return is_kernel_addr(info->address);
+}
+
+int arch_bp_generic_fields(int type, int *gen_bp_type)
+{
+        switch (type) {
+        case DABR_DATA_READ:
+                *gen_bp_type = HW_BREAKPOINT_R;
+                break;
+        case DABR_DATA_WRITE:
+                *gen_bp_type = HW_BREAKPOINT_W;
+                break;
+        case (DABR_DATA_WRITE | DABR_DATA_READ):
+                *gen_bp_type = (HW_BREAKPOINT_W | HW_BREAKPOINT_R);
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
+{
+        int ret = -EINVAL;
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        if (!bp)
+                return ret;
+
+        switch (bp->attr.bp_type) {
+        case HW_BREAKPOINT_R:
+                info->type = DABR_DATA_READ;
+                break;
+        case HW_BREAKPOINT_W:
+                info->type = DABR_DATA_WRITE;
+                break;
+        case HW_BREAKPOINT_R | HW_BREAKPOINT_W:
+                info->type = (DABR_DATA_READ | DABR_DATA_WRITE);
+                break;
+        default:
+                return ret;
+        }
+
+        info->address = bp->attr.bp_addr;
+        info->len = bp->attr.bp_len;
+
+        /*
+         * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
+         * and breakpoint addresses are aligned to nearest double-word
+         * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
+         * 'symbolsize' should satisfy the check below.
+         */
+        if (info->len >
+            (HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
+                return -EINVAL;
+        return 0;
+}
+
+/*
+ * Restores the breakpoint on the debug registers.
+ * Invoke this function if it is known that the execution context is
+ * about to change to cause loss of MSR_SE settings.
+ */
+void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
+{
+        struct arch_hw_breakpoint *info;
+
+        if (likely(!tsk->thread.last_hit_ubp))
+                return;
+
+        info = counter_arch_bp(tsk->thread.last_hit_ubp);
+        regs->msr &= ~MSR_SE;
+        set_dabr(info->address | info->type | DABR_TRANSLATION);
+        tsk->thread.last_hit_ubp = NULL;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_handler(struct die_args *args)
+{
+        int rc = NOTIFY_STOP;
+        struct perf_event *bp;
+        struct pt_regs *regs = args->regs;
+        int stepped = 1;
+        struct arch_hw_breakpoint *info;
+        unsigned int instr;
+        unsigned long dar = regs->dar;
+
+        /* Disable breakpoints during exception handling */
+        set_dabr(0);
+
+        /*
+         * The counter may be concurrently released but that can only
+         * occur from a call_rcu() path. We can then safely fetch
+         * the breakpoint, use its callback, touch its counter
+         * while we are in an rcu_read_lock() path.
+         */
+        rcu_read_lock();
+
+        bp = __get_cpu_var(bp_per_reg);
+        if (!bp)
+                goto out;
+        info = counter_arch_bp(bp);
+
+        /*
+         * Return early after invoking user-callback function without restoring
+         * DABR if the breakpoint is from ptrace which always operates in
+         * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
+         * generated in do_dabr().
+         */
+        if (bp->overflow_handler == ptrace_triggered) {
+                perf_bp_event(bp, regs);
+                rc = NOTIFY_DONE;
+                goto out;
+        }
+
+        /*
+         * Verify if dar lies within the address range occupied by the symbol
+         * being watched to filter extraneous exceptions.  If it doesn't,
+         * we still need to single-step the instruction, but we don't
+         * generate an event.
+         */
+        info->extraneous_interrupt = !((bp->attr.bp_addr <= dar) &&
+                        (dar - bp->attr.bp_addr < bp->attr.bp_len));
+
+        /* Do not emulate user-space instructions, instead single-step them */
+        if (user_mode(regs)) {
+                bp->ctx->task->thread.last_hit_ubp = bp;
+                regs->msr |= MSR_SE;
+                goto out;
+        }
+
+        stepped = 0;
+        instr = 0;
+        if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
+                stepped = emulate_step(regs, instr);
+
+        /*
+         * emulate_step() could not execute it. We've failed in reliably
+         * handling the hw-breakpoint. Unregister it and throw a warning
+         * message to let the user know about it.
+         */
+        if (!stepped) {
+                WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
+                        "0x%lx will be disabled.", info->address);
+                perf_event_disable(bp);
+                goto out;
+        }
+        /*
+         * As a policy, the callback is invoked in a 'trigger-after-execute'
+         * fashion
+         */
+        if (!info->extraneous_interrupt)
+                perf_bp_event(bp, regs);
+
+        set_dabr(info->address | info->type | DABR_TRANSLATION);
+out:
+        rcu_read_unlock();
+        return rc;
+}
+
+/*
+ * Handle single-step exceptions following a DABR hit.
+ */
+int __kprobes single_step_dabr_instruction(struct die_args *args)
+{
+        struct pt_regs *regs = args->regs;
+        struct perf_event *bp = NULL;
+        struct arch_hw_breakpoint *bp_info;
+
+        bp = current->thread.last_hit_ubp;
+        /*
+         * Check if we are single-stepping as a result of a
+         * previous HW Breakpoint exception
+         */
+        if (!bp)
+                return NOTIFY_DONE;
+
+        bp_info = counter_arch_bp(bp);
+
+        /*
+         * We shall invoke the user-defined callback function in the single
+         * stepping handler to confirm to 'trigger-after-execute' semantics
+         */
+        if (!bp_info->extraneous_interrupt)
+                perf_bp_event(bp, regs);
+
+        set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
+        current->thread.last_hit_ubp = NULL;
+
+        /*
+         * If the process was being single-stepped by ptrace, let the
+         * other single-step actions occur (e.g. generate SIGTRAP).
+         */
+        if (test_thread_flag(TIF_SINGLESTEP))
+                return NOTIFY_DONE;
+
+        return NOTIFY_STOP;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_exceptions_notify(
+                struct notifier_block *unused, unsigned long val, void *data)
+{
+        int ret = NOTIFY_DONE;
+
+        switch (val) {
+        case DIE_DABR_MATCH:
+                ret = hw_breakpoint_handler(data);
+                break;
+        case DIE_SSTEP:
+                ret = single_step_dabr_instruction(data);
+                break;
+        }
+
+        return ret;
+}
+
+/*
+ * Release the user breakpoints used by ptrace
+ */
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+        struct thread_struct *t = &tsk->thread;
+
+        unregister_hw_breakpoint(t->ptrace_bps[0]);
+        t->ptrace_bps[0] = NULL;
+}
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+        /* TODO */
+}
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index 21266abfbda6..9b626cfffce1 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -140,19 +140,19 @@ static struct dma_map_ops ibmebus_dma_ops = {
 
 static int ibmebus_match_path(struct device *dev, void *data)
 {
-        struct device_node *dn = to_of_device(dev)->dev.of_node;
+        struct device_node *dn = to_platform_device(dev)->dev.of_node;
         return (dn->full_name &&
                 (strcasecmp((char *)data, dn->full_name) == 0));
 }
 
 static int ibmebus_match_node(struct device *dev, void *data)
 {
-        return to_of_device(dev)->dev.of_node == data;
+        return to_platform_device(dev)->dev.of_node == data;
 }
 
 static int ibmebus_create_device(struct device_node *dn)
 {
-        struct of_device *dev;
+        struct platform_device *dev;
         int ret;
 
         dev = of_device_alloc(dn, NULL, &ibmebus_bus_device);
@@ -298,7 +298,7 @@ static ssize_t ibmebus_store_remove(struct bus_type *bus,
 
         if ((dev = bus_find_device(&ibmebus_bus_type, NULL, path,
                                    ibmebus_match_path))) {
-                of_device_unregister(to_of_device(dev));
+                of_device_unregister(to_platform_device(dev));
 
                 kfree(path);
                 return count;
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
new file mode 100644
index 000000000000..16c002d6bdf1
--- /dev/null
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2010 IBM Corp, Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
+ * Generic idle routine for Book3E processors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/threads.h>
+#include <asm/reg.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/ppc-opcode.h>
+#include <asm/processor.h>
+#include <asm/thread_info.h>
+
+/* 64-bit version only for now */
+#ifdef CONFIG_PPC64
+
+_GLOBAL(book3e_idle)
+        /* Save LR for later */
+        mflr    r0
+        std     r0,16(r1)
+
+        /* Hard disable interrupts */
+        wrteei  0
+
+        /* Now check if an interrupt came in while we were soft disabled
+         * since we may otherwise lose it (doorbells etc...). We know
+         * that since PACAHARDIRQEN will have been cleared in that case.
+         */
+        lbz     r3,PACAHARDIRQEN(r13)
+        cmpwi   cr0,r3,0
+        beqlr
+
+        /* Now we are going to mark ourselves as soft and hard enables in
+         * order to be able to take interrupts while asleep. We inform lockdep
+         * of that. We don't actually turn interrupts on just yet tho.
+         */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        stdu    r1,-128(r1)
+        bl      .trace_hardirqs_on
+#endif
+        li      r0,1
+        stb     r0,PACASOFTIRQEN(r13)
+        stb     r0,PACAHARDIRQEN(r13)
+        
+        /* Interrupts will make use return to LR, so get something we want
+         * in there
+         */
+        bl      1f
+
+        /* Hard disable interrupts again */
+        wrteei  0
+
+        /* Mark them off again in the PACA as well */
+        li      r0,0
+        stb     r0,PACASOFTIRQEN(r13)
+        stb     r0,PACAHARDIRQEN(r13)
+
+        /* Tell lockdep about it */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        bl      .trace_hardirqs_off
+        addi    r1,r1,128
+#endif
+        ld      r0,16(r1)
+        mtlr    r0
+        blr
+
+1:      /* Let's set the _TLF_NAPPING flag so interrupts make us return
+         * to the right spot
+        */
+        clrrdi  r11,r1,THREAD_SHIFT
+        ld      r10,TI_LOCAL_FLAGS(r11)
+        ori     r10,r10,_TLF_NAPPING
+        std     r10,TI_LOCAL_FLAGS(r11)
+
+        /* We can now re-enable hard interrupts and go to sleep */
+        wrteei  1
+1:      PPC_WAIT(0)
+        b       1b
+
+#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 77be3d058a65..d3ce67cf03be 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -53,6 +53,8 @@
 #include <linux/bootmem.h>
 #include <linux/pci.h>
 #include <linux/debugfs.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/uaccess.h>
 #include <asm/system.h>
@@ -64,6 +66,8 @@
 #include <asm/ptrace.h>
 #include <asm/machdep.h>
 #include <asm/udbg.h>
+#include <asm/dbell.h>
+
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
 #include <asm/firmware.h>
@@ -153,14 +157,28 @@ notrace void raw_local_irq_restore(unsigned long en)
         if (get_hard_enabled())
                 return;
 
+#if defined(CONFIG_BOOKE) && defined(CONFIG_SMP)
+        /* Check for pending doorbell interrupts and resend to ourself */
+        doorbell_check_self();
+#endif
+
         /*
          * Need to hard-enable interrupts here.  Since currently disabled,
          * no need to take further asm precautions against preemption; but
          * use local_paca instead of get_paca() to avoid preemption checking.
          */
         local_paca->hard_enabled = en;
+
+#ifndef CONFIG_BOOKE
+        /* On server, re-trigger the decrementer if it went negative since
+         * some processors only trigger on edge transitions of the sign bit.
+         *
+         * BookE has a level sensitive decrementer (latches in TSR) so we
+         * don't need that
+         */
         if ((int)mfspr(SPRN_DEC) < 0)
                 mtspr(SPRN_DEC, 1);
+#endif /* CONFIG_BOOKE */
 
         /*
          * Force the delivery of pending soft-disabled interrupts on PS3.
@@ -804,18 +822,6 @@ unsigned int irq_create_of_mapping(struct device_node *controller,
 }
 EXPORT_SYMBOL_GPL(irq_create_of_mapping);
 
-unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
-{
-        struct of_irq oirq;
-
-        if (of_irq_map_one(dev, index, &oirq))
-                return NO_IRQ;
-
-        return irq_create_of_mapping(oirq.controller, oirq.specifier,
-                                     oirq.size);
-}
-EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
-
 void irq_dispose_mapping(unsigned int virq)
 {
         struct irq_host *host;
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index 82a7b228c81a..7f61a3ac787c 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -129,7 +129,7 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs)
                 return 0;
 
         if (*(u32 *) (regs->nip) == *(u32 *) (&arch_kgdb_ops.gdb_bpt_instr))
-                regs->nip += 4;
+                regs->nip += BREAK_INSTR_SIZE;
 
         return 1;
 }
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index 035ada5443ee..c1fd0f9658fd 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -4,6 +4,7 @@
 #include <linux/serial_core.h>
 #include <linux/console.h>
 #include <linux/pci.h>
+#include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index 89f005116aac..dd6c141f1662 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -45,6 +45,18 @@ void machine_kexec_cleanup(struct kimage *image)
                 ppc_md.machine_kexec_cleanup(image);
 }
 
+void arch_crash_save_vmcoreinfo(void)
+{
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+        VMCOREINFO_SYMBOL(node_data);
+        VMCOREINFO_LENGTH(node_data, MAX_NUMNODES);
+#endif
+#ifndef CONFIG_NEED_MULTIPLE_NODES
+        VMCOREINFO_SYMBOL(contig_page_data);
+#endif
+}
+
 /*
  * Do not allocate memory (or fail in any way) in machine_kexec().
  * We are past the point of no return, committed to rebooting now.
@@ -144,24 +156,24 @@ int overlaps_crashkernel(unsigned long start, unsigned long size)
 }
 
 /* Values we need to export to the second kernel via the device tree. */
-static unsigned long kernel_end;
-static unsigned long crashk_size;
+static phys_addr_t kernel_end;
+static phys_addr_t crashk_size;
 
 static struct property kernel_end_prop = {
         .name = "linux,kernel-end",
-        .length = sizeof(unsigned long),
+        .length = sizeof(phys_addr_t),
         .value = &kernel_end,
 };
 
 static struct property crashk_base_prop = {
         .name = "linux,crashkernel-base",
-        .length = sizeof(unsigned long),
+        .length = sizeof(phys_addr_t),
         .value = &crashk_res.start,
 };
 
 static struct property crashk_size_prop = {
         .name = "linux,crashkernel-size",
-        .length = sizeof(unsigned long),
+        .length = sizeof(phys_addr_t),
         .value = &crashk_size,
 };
 
diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index ed31a29c4ff7..583af70c4b14 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -15,6 +15,8 @@
 #include <linux/thread_info.h>
 #include <linux/init_task.h>
 #include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/cpu.h>
 
 #include <asm/page.h>
 #include <asm/current.h>
@@ -25,6 +27,7 @@
 #include <asm/sections.h>       /* _end */
 #include <asm/prom.h>
 #include <asm/smp.h>
+#include <asm/hw_breakpoint.h>
 
 int default_machine_kexec_prepare(struct kimage *image)
 {
@@ -165,6 +168,7 @@ static void kexec_smp_down(void *arg)
         while(kexec_all_irq_disabled == 0)
                 cpu_relax();
         mb(); /* make sure all irqs are disabled before this */
+        hw_breakpoint_disable();
         /*
          * Now every CPU has IRQs off, we can clear out any pending
          * IPIs and be sure that no more will come in after this.
@@ -180,8 +184,22 @@ static void kexec_prepare_cpus_wait(int wait_state)
 {
         int my_cpu, i, notified=-1;
 
+        hw_breakpoint_disable();
         my_cpu = get_cpu();
-        /* Make sure each CPU has atleast made it to the state we need */
+        /* Make sure each CPU has at least made it to the state we need.
+         *
+         * FIXME: There is a (slim) chance of a problem if not all of the CPUs
+         * are correctly onlined.  If somehow we start a CPU on boot with RTAS
+         * start-cpu, but somehow that CPU doesn't write callin_cpu_map[] in
+         * time, the boot CPU will timeout.  If it does eventually execute
+         * stuff, the secondary will start up (paca[].cpu_start was written) and
+         * get into a peculiar state.  If the platform supports
+         * smp_ops->take_timebase(), the secondary CPU will probably be spinning
+         * in there.  If not (i.e. pseries), the secondary will continue on and
+         * try to online itself/idle/etc. If it survives that, we need to find
+         * these possible-but-not-online-but-should-be CPUs and chaperone them
+         * into kexec_smp_wait().
+         */
         for_each_online_cpu(i) {
                 if (i == my_cpu)
                         continue;
@@ -189,9 +207,9 @@ static void kexec_prepare_cpus_wait(int wait_state)
                 while (paca[i].kexec_state < wait_state) {
                         barrier();
                         if (i != notified) {
-                                printk( "kexec: waiting for cpu %d (physical"
-                                                " %d) to enter %i state\n",
-                                        i, paca[i].hw_cpu_id, wait_state);
+                                printk(KERN_INFO "kexec: waiting for cpu %d "
+                                       "(physical %d) to enter %i state\n",
+                                       i, paca[i].hw_cpu_id, wait_state);
                                 notified = i;
                         }
                 }
@@ -199,9 +217,32 @@ static void kexec_prepare_cpus_wait(int wait_state)
         mb();
 }
 
-static void kexec_prepare_cpus(void)
+/*
+ * We need to make sure each present CPU is online.  The next kernel will scan
+ * the device tree and assume primary threads are online and query secondary
+ * threads via RTAS to online them if required.  If we don't online primary
+ * threads, they will be stuck.  However, we also online secondary threads as we
+ * may be using 'cede offline'.  In this case RTAS doesn't see the secondary
+ * threads as offline -- and again, these CPUs will be stuck.
+ *
+ * So, we online all CPUs that should be running, including secondary threads.
+ */
+static void wake_offline_cpus(void)
 {
+        int cpu = 0;
 
+        for_each_present_cpu(cpu) {
+                if (!cpu_online(cpu)) {
+                        printk(KERN_INFO "kexec: Waking offline cpu %d.\n",
+                               cpu);
+                        cpu_up(cpu);
+                }
+        }
+}
+
+static void kexec_prepare_cpus(void)
+{
+        wake_offline_cpus();
         smp_call_function(kexec_smp_down, NULL, /* wait */0);
         local_irq_disable();
         mb(); /* make sure IRQs are disabled before we say they are */
@@ -215,7 +256,10 @@ static void kexec_prepare_cpus(void)
         if (ppc_md.kexec_cpu_down)
                 ppc_md.kexec_cpu_down(0, 0);
 
-        /* Before removing MMU mapings make sure all CPUs have entered real mode */
+        /*
+         * Before removing MMU mappings make sure all CPUs have entered real
+         * mode:
+         */
         kexec_prepare_cpus_wait(KEXEC_STATE_REAL_MODE);
 
         put_cpu();
@@ -257,6 +301,12 @@ static void kexec_prepare_cpus(void)
 static union thread_union kexec_stack __init_task_data =
         { };
 
+/*
+ * For similar reasons to the stack above, the kexecing CPU needs to be on a
+ * static PACA; we switch to kexec_paca.
+ */
+struct paca_struct kexec_paca;
+
 /* Our assembly helper, in kexec_stub.S */
 extern NORET_TYPE void kexec_sequence(void *newstack, unsigned long start,
                                         void *image, void *control,
@@ -278,12 +328,28 @@ void default_machine_kexec(struct kimage *image)
         if (crashing_cpu == -1)
                 kexec_prepare_cpus();
 
+        pr_debug("kexec: Starting switchover sequence.\n");
+
         /* switch to a staticly allocated stack.  Based on irq stack code.
          * XXX: the task struct will likely be invalid once we do the copy!
          */
         kexec_stack.thread_info.task = current_thread_info()->task;
         kexec_stack.thread_info.flags = 0;
 
+        /* We need a static PACA, too; copy this CPU's PACA over and switch to
+         * it.  Also poison per_cpu_offset to catch anyone using non-static
+         * data.
+         */
+        memcpy(&kexec_paca, get_paca(), sizeof(struct paca_struct));
+        kexec_paca.data_offset = 0xedeaddeadeeeeeeeUL;
+        paca = (struct paca_struct *)RELOC_HIDE(&kexec_paca, 0) -
+                kexec_paca.paca_index;
+        setup_paca(&kexec_paca);
+
+        /* XXX: If anyone does 'dynamic lppacas' this will also need to be
+         * switched to a static version!
+         */
+
         /* Some things are best done in assembly.  Finding globals with
          * a toc is easier in C, so pass in what we can.
          */
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
index 22e507c8a556..2d29752cbe16 100644
--- a/arch/powerpc/kernel/misc.S
+++ b/arch/powerpc/kernel/misc.S
@@ -127,29 +127,3 @@ _GLOBAL(__setup_cpu_power7)
 _GLOBAL(__restore_cpu_power7)
         /* place holder */
         blr
-
-/*
- * Get a minimal set of registers for our caller's nth caller.
- * r3 = regs pointer, r5 = n.
- *
- * We only get R1 (stack pointer), NIP (next instruction pointer)
- * and LR (link register).  These are all we can get in the
- * general case without doing complicated stack unwinding, but
- * fortunately they are enough to do a stack backtrace, which
- * is all we need them for.
- */
-_GLOBAL(perf_arch_fetch_caller_regs)
-        mr      r6,r1
-        cmpwi   r5,0
-        mflr    r4
-        ble     2f
-        mtctr   r5
-1:      PPC_LL  r6,0(r6)
-        bdnz    1b
-        PPC_LL  r4,PPC_LR_STKOFF(r6)
-2:      PPC_LL  r7,0(r6)
-        PPC_LL  r7,PPC_LR_STKOFF(r7)
-        PPC_STL r6,GPR1-STACK_FRAME_OVERHEAD(r3)
-        PPC_STL r4,_NIP-STACK_FRAME_OVERHEAD(r3)
-        PPC_STL r7,_LINK-STACK_FRAME_OVERHEAD(r3)
-        blr
diff --git a/arch/powerpc/kernel/of_device.c b/arch/powerpc/kernel/of_device.c
deleted file mode 100644
index df78e0236a02..000000000000
--- a/arch/powerpc/kernel/of_device.c
+++ /dev/null
@@ -1,133 +0,0 @@
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/slab.h>
-#include <linux/of_device.h>
-
-#include <asm/errno.h>
-#include <asm/dcr.h>
-
-static void of_device_make_bus_id(struct of_device *dev)
-{
-        static atomic_t bus_no_reg_magic;
-        struct device_node *node = dev->dev.of_node;
-        const u32 *reg;
-        u64 addr;
-        int magic;
-
-        /*
-         * If it's a DCR based device, use 'd' for native DCRs
-         * and 'D' for MMIO DCRs.
-         */
-#ifdef CONFIG_PPC_DCR
-        reg = of_get_property(node, "dcr-reg", NULL);
-        if (reg) {
-#ifdef CONFIG_PPC_DCR_NATIVE
-                dev_set_name(&dev->dev, "d%x.%s", *reg, node->name);
-#else /* CONFIG_PPC_DCR_NATIVE */
-                addr = of_translate_dcr_address(node, *reg, NULL);
-                if (addr != OF_BAD_ADDR) {
-                        dev_set_name(&dev->dev, "D%llx.%s",
-                                     (unsigned long long)addr, node->name);
-                        return;
-                }
-#endif /* !CONFIG_PPC_DCR_NATIVE */
-        }
-#endif /* CONFIG_PPC_DCR */
-
-        /*
-         * For MMIO, get the physical address
-         */
-        reg = of_get_property(node, "reg", NULL);
-        if (reg) {
-                addr = of_translate_address(node, reg);
-                if (addr != OF_BAD_ADDR) {
-                        dev_set_name(&dev->dev, "%llx.%s",
-                                     (unsigned long long)addr, node->name);
-                        return;
-                }
-        }
-
-        /*
-         * No BusID, use the node name and add a globally incremented
-         * counter (and pray...)
-         */
-        magic = atomic_add_return(1, &bus_no_reg_magic);
-        dev_set_name(&dev->dev, "%s.%d", node->name, magic - 1);
-}
-
-struct of_device *of_device_alloc(struct device_node *np,
-                                  const char *bus_id,
-                                  struct device *parent)
-{
-        struct of_device *dev;
-
-        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-        if (!dev)
-                return NULL;
-
-        dev->dev.of_node = of_node_get(np);
-        dev->dev.dma_mask = &dev->archdata.dma_mask;
-        dev->dev.parent = parent;
-        dev->dev.release = of_release_dev;
-
-        if (bus_id)
-                dev_set_name(&dev->dev, "%s", bus_id);
-        else
-                of_device_make_bus_id(dev);
-
-        return dev;
-}
-EXPORT_SYMBOL(of_device_alloc);
-
-int of_device_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
-        struct of_device *ofdev;
-        const char *compat;
-        int seen = 0, cplen, sl;
-
-        if (!dev)
-                return -ENODEV;
-
-        ofdev = to_of_device(dev);
-
-        if (add_uevent_var(env, "OF_NAME=%s", ofdev->dev.of_node->name))
-                return -ENOMEM;
-
-        if (add_uevent_var(env, "OF_TYPE=%s", ofdev->dev.of_node->type))
-                return -ENOMEM;
-
-        /* Since the compatible field can contain pretty much anything
-         * it's not really legal to split it out with commas. We split it
-         * up using a number of environment variables instead. */
-
-        compat = of_get_property(ofdev->dev.of_node, "compatible", &cplen);
-        while (compat && *compat && cplen > 0) {
-                if (add_uevent_var(env, "OF_COMPATIBLE_%d=%s", seen, compat))
-                        return -ENOMEM;
-
-                sl = strlen (compat) + 1;
-                compat += sl;
-                cplen -= sl;
-                seen++;
-        }
-
-        if (add_uevent_var(env, "OF_COMPATIBLE_N=%d", seen))
-                return -ENOMEM;
-
-        /* modalias is trickier, we add it in 2 steps */
-        if (add_uevent_var(env, "MODALIAS="))
-                return -ENOMEM;
-        sl = of_device_get_modalias(ofdev, &env->buf[env->buflen-1],
-                                    sizeof(env->buf) - env->buflen);
-        if (sl >= (sizeof(env->buf) - env->buflen))
-                return -ENOMEM;
-        env->buflen += sl;
-
-        return 0;
-}
-EXPORT_SYMBOL(of_device_uevent);
-EXPORT_SYMBOL(of_device_get_modalias);
diff --git a/arch/powerpc/kernel/of_platform.c b/arch/powerpc/kernel/of_platform.c
index 487a98851ba6..b2c363ef38ad 100644
--- a/arch/powerpc/kernel/of_platform.c
+++ b/arch/powerpc/kernel/of_platform.c
@@ -28,207 +28,6 @@
 #include <asm/ppc-pci.h>
 #include <asm/atomic.h>
 
-/*
- * The list of OF IDs below is used for matching bus types in the
- * system whose devices are to be exposed as of_platform_devices.
- *
- * This is the default list valid for most platforms. This file provides
- * functions who can take an explicit list if necessary though
- *
- * The search is always performed recursively looking for children of
- * the provided device_node and recursively if such a children matches
- * a bus type in the list
- */
-
-static const struct of_device_id of_default_bus_ids[] = {
-        { .type = "soc", },
-        { .compatible = "soc", },
-        { .type = "spider", },
-        { .type = "axon", },
-        { .type = "plb5", },
-        { .type = "plb4", },
-        { .type = "opb", },
-        { .type = "ebc", },
-        {},
-};
-
-struct bus_type of_platform_bus_type = {
-       .uevent  = of_device_uevent,
-};
-EXPORT_SYMBOL(of_platform_bus_type);
-
-static int __init of_bus_driver_init(void)
-{
-        return of_bus_type_init(&of_platform_bus_type, "of_platform");
-}
-
-postcore_initcall(of_bus_driver_init);
-
-struct of_device* of_platform_device_create(struct device_node *np,
-                                            const char *bus_id,
-                                            struct device *parent)
-{
-        struct of_device *dev;
-
-        dev = of_device_alloc(np, bus_id, parent);
-        if (!dev)
-                return NULL;
-
-        dev->archdata.dma_mask = 0xffffffffUL;
-        dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
-        dev->dev.bus = &of_platform_bus_type;
-
-        /* We do not fill the DMA ops for platform devices by default.
-         * This is currently the responsibility of the platform code
-         * to do such, possibly using a device notifier
-         */
-
-        if (of_device_register(dev) != 0) {
-                of_device_free(dev);
-                return NULL;
-        }
-
-        return dev;
-}
-EXPORT_SYMBOL(of_platform_device_create);
-
-
-
-/**
- * of_platform_bus_create - Create an OF device for a bus node and all its
- * children. Optionally recursively instanciate matching busses.
- * @bus: device node of the bus to instanciate
- * @matches: match table, NULL to use the default, OF_NO_DEEP_PROBE to
- * disallow recursive creation of child busses
- */
-static int of_platform_bus_create(const struct device_node *bus,
-                                  const struct of_device_id *matches,
-                                  struct device *parent)
-{
-        struct device_node *child;
-        struct of_device *dev;
-        int rc = 0;
-
-        for_each_child_of_node(bus, child) {
-                pr_debug("   create child: %s\n", child->full_name);
-                dev = of_platform_device_create(child, NULL, parent);
-                if (dev == NULL)
-                        rc = -ENOMEM;
-                else if (!of_match_node(matches, child))
-                        continue;
-                if (rc == 0) {
-                        pr_debug("   and sub busses\n");
-                        rc = of_platform_bus_create(child, matches, &dev->dev);
-                } if (rc) {
-                        of_node_put(child);
-                        break;
-                }
-        }
-        return rc;
-}
-
-/**
- * of_platform_bus_probe - Probe the device-tree for platform busses
- * @root: parent of the first level to probe or NULL for the root of the tree
- * @matches: match table, NULL to use the default
- * @parent: parent to hook devices from, NULL for toplevel
- *
- * Note that children of the provided root are not instanciated as devices
- * unless the specified root itself matches the bus list and is not NULL.
- */
-
-int of_platform_bus_probe(struct device_node *root,
-                          const struct of_device_id *matches,
-                          struct device *parent)
-{
-        struct device_node *child;
-        struct of_device *dev;
-        int rc = 0;
-
-        if (matches == NULL)
-                matches = of_default_bus_ids;
-        if (matches == OF_NO_DEEP_PROBE)
-                return -EINVAL;
-        if (root == NULL)
-                root = of_find_node_by_path("/");
-        else
-                of_node_get(root);
-
-        pr_debug("of_platform_bus_probe()\n");
-        pr_debug(" starting at: %s\n", root->full_name);
-
-        /* Do a self check of bus type, if there's a match, create
-         * children
-         */
-        if (of_match_node(matches, root)) {
-                pr_debug(" root match, create all sub devices\n");
-                dev = of_platform_device_create(root, NULL, parent);
-                if (dev == NULL) {
-                        rc = -ENOMEM;
-                        goto bail;
-                }
-                pr_debug(" create all sub busses\n");
-                rc = of_platform_bus_create(root, matches, &dev->dev);
-                goto bail;
-        }
-        for_each_child_of_node(root, child) {
-                if (!of_match_node(matches, child))
-                        continue;
-
-                pr_debug("  match: %s\n", child->full_name);
-                dev = of_platform_device_create(child, NULL, parent);
-                if (dev == NULL)
-                        rc = -ENOMEM;
-                else
-                        rc = of_platform_bus_create(child, matches, &dev->dev);
-                if (rc) {
-                        of_node_put(child);
-                        break;
-                }
-        }
- bail:
-        of_node_put(root);
-        return rc;
-}
-EXPORT_SYMBOL(of_platform_bus_probe);
-
-static int of_dev_node_match(struct device *dev, void *data)
-{
-        return to_of_device(dev)->dev.of_node == data;
-}
-
-struct of_device *of_find_device_by_node(struct device_node *np)
-{
-        struct device *dev;
-
-        dev = bus_find_device(&of_platform_bus_type,
-                              NULL, np, of_dev_node_match);
-        if (dev)
-                return to_of_device(dev);
-        return NULL;
-}
-EXPORT_SYMBOL(of_find_device_by_node);
-
-static int of_dev_phandle_match(struct device *dev, void *data)
-{
-        phandle *ph = data;
-        return to_of_device(dev)->dev.of_node->phandle == *ph;
-}
-
-struct of_device *of_find_device_by_phandle(phandle ph)
-{
-        struct device *dev;
-
-        dev = bus_find_device(&of_platform_bus_type,
-                              NULL, &ph, of_dev_phandle_match);
-        if (dev)
-                return to_of_device(dev);
-        return NULL;
-}
-EXPORT_SYMBOL(of_find_device_by_phandle);
-
-
 #ifdef CONFIG_PPC_OF_PLATFORM_PCI
 
 /* The probing of PCI controllers from of_platform is currently
@@ -237,7 +36,7 @@ EXPORT_SYMBOL(of_find_device_by_phandle);
  * lacking some bits needed here.
  */
 
-static int __devinit of_pci_phb_probe(struct of_device *dev,
+static int __devinit of_pci_phb_probe(struct platform_device *dev,
                                       const struct of_device_id *match)
 {
         struct pci_controller *phb;
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 139a773853f4..d0a26f1770fe 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -105,6 +105,16 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
 #endif /* CONFIG_PPC_STD_MMU_64 */
 }
 
+/* Put the paca pointer into r13 and SPRG_PACA */
+void setup_paca(struct paca_struct *new_paca)
+{
+        local_paca = new_paca;
+        mtspr(SPRN_SPRG_PACA, local_paca);
+#ifdef CONFIG_PPC_BOOK3E
+        mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
+#endif
+}
+
 static int __initdata paca_size;
 
 void __init allocate_pacas(void)
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 5b38f6ae2b29..9021c4ad4bbd 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -21,6 +21,7 @@
 #include <linux/string.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
+#include <linux/of_address.h>
 #include <linux/mm.h>
 #include <linux/list.h>
 #include <linux/syscalls.h>
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 5c14ffe51258..d301a30445e0 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -410,15 +410,15 @@ static void power_pmu_read(struct perf_event *event)
          * Therefore we treat them like NMIs.
          */
         do {
-                prev = atomic64_read(&event->hw.prev_count);
+                prev = local64_read(&event->hw.prev_count);
                 barrier();
                 val = read_pmc(event->hw.idx);
-        } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
+        } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
 
         /* The counters are only 32 bits wide */
         delta = (val - prev) & 0xfffffffful;
-        atomic64_add(delta, &event->count);
-        atomic64_sub(delta, &event->hw.period_left);
+        local64_add(delta, &event->count);
+        local64_sub(delta, &event->hw.period_left);
 }
 
 /*
@@ -444,10 +444,10 @@ static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
                 if (!event->hw.idx)
                         continue;
                 val = (event->hw.idx == 5) ? pmc5 : pmc6;
-                prev = atomic64_read(&event->hw.prev_count);
+                prev = local64_read(&event->hw.prev_count);
                 event->hw.idx = 0;
                 delta = (val - prev) & 0xfffffffful;
-                atomic64_add(delta, &event->count);
+                local64_add(delta, &event->count);
         }
 }
 
@@ -462,7 +462,7 @@ static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
                 event = cpuhw->limited_counter[i];
                 event->hw.idx = cpuhw->limited_hwidx[i];
                 val = (event->hw.idx == 5) ? pmc5 : pmc6;
-                atomic64_set(&event->hw.prev_count, val);
+                local64_set(&event->hw.prev_count, val);
                 perf_event_update_userpage(event);
         }
 }
@@ -666,11 +666,11 @@ void hw_perf_enable(void)
                 }
                 val = 0;
                 if (event->hw.sample_period) {
-                        left = atomic64_read(&event->hw.period_left);
+                        left = local64_read(&event->hw.period_left);
                         if (left < 0x80000000L)
                                 val = 0x80000000L - left;
                 }
-                atomic64_set(&event->hw.prev_count, val);
+                local64_set(&event->hw.prev_count, val);
                 event->hw.idx = idx;
                 write_pmc(idx, val);
                 perf_event_update_userpage(event);
@@ -754,7 +754,7 @@ static int power_pmu_enable(struct perf_event *event)
          * skip the schedulability test here, it will be peformed
          * at commit time(->commit_txn) as a whole
          */
-        if (cpuhw->group_flag & PERF_EVENT_TXN_STARTED)
+        if (cpuhw->group_flag & PERF_EVENT_TXN)
                 goto nocheck;
 
         if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
@@ -845,8 +845,8 @@ static void power_pmu_unthrottle(struct perf_event *event)
         if (left < 0x80000000L)
                 val = 0x80000000L - left;
         write_pmc(event->hw.idx, val);
-        atomic64_set(&event->hw.prev_count, val);
-        atomic64_set(&event->hw.period_left, left);
+        local64_set(&event->hw.prev_count, val);
+        local64_set(&event->hw.period_left, left);
         perf_event_update_userpage(event);
         perf_enable();
         local_irq_restore(flags);
@@ -861,7 +861,7 @@ void power_pmu_start_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 
-        cpuhw->group_flag |= PERF_EVENT_TXN_STARTED;
+        cpuhw->group_flag |= PERF_EVENT_TXN;
         cpuhw->n_txn_start = cpuhw->n_events;
 }
 
@@ -874,7 +874,7 @@ void power_pmu_cancel_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 
-        cpuhw->group_flag &= ~PERF_EVENT_TXN_STARTED;
+        cpuhw->group_flag &= ~PERF_EVENT_TXN;
 }
 
 /*
@@ -900,6 +900,7 @@ int power_pmu_commit_txn(const struct pmu *pmu)
         for (i = cpuhw->n_txn_start; i < n; ++i)
                 cpuhw->event[i]->hw.config = cpuhw->events[i];
 
+        cpuhw->group_flag &= ~PERF_EVENT_TXN;
         return 0;
 }
 
@@ -1111,7 +1112,7 @@ const struct pmu *hw_perf_event_init(struct perf_event *event)
         event->hw.config = events[n];
         event->hw.event_base = cflags[n];
         event->hw.last_period = event->hw.sample_period;
-        atomic64_set(&event->hw.period_left, event->hw.last_period);
+        local64_set(&event->hw.period_left, event->hw.last_period);
 
         /*
          * See if we need to reserve the PMU.
@@ -1149,16 +1150,16 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
         int record = 0;
 
         /* we don't have to worry about interrupts here */
-        prev = atomic64_read(&event->hw.prev_count);
+        prev = local64_read(&event->hw.prev_count);
         delta = (val - prev) & 0xfffffffful;
-        atomic64_add(delta, &event->count);
+        local64_add(delta, &event->count);
 
         /*
          * See if the total period for this event has expired,
          * and update for the next period.
          */
         val = 0;
-        left = atomic64_read(&event->hw.period_left) - delta;
+        left = local64_read(&event->hw.period_left) - delta;
         if (period) {
                 if (left <= 0) {
                         left += period;
@@ -1196,8 +1197,8 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
         }
 
         write_pmc(event->hw.idx, val);
-        atomic64_set(&event->hw.prev_count, val);
-        atomic64_set(&event->hw.period_left, left);
+        local64_set(&event->hw.prev_count, val);
+        local64_set(&event->hw.period_left, left);
         perf_event_update_userpage(event);
 }
 
diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c
index 369872f6cf78..1ba45471ae43 100644
--- a/arch/powerpc/kernel/perf_event_fsl_emb.c
+++ b/arch/powerpc/kernel/perf_event_fsl_emb.c
@@ -162,15 +162,15 @@ static void fsl_emb_pmu_read(struct perf_event *event)
          * Therefore we treat them like NMIs.
          */
         do {
-                prev = atomic64_read(&event->hw.prev_count);
+                prev = local64_read(&event->hw.prev_count);
                 barrier();
                 val = read_pmc(event->hw.idx);
-        } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
+        } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
 
         /* The counters are only 32 bits wide */
         delta = (val - prev) & 0xfffffffful;
-        atomic64_add(delta, &event->count);
-        atomic64_sub(delta, &event->hw.period_left);
+        local64_add(delta, &event->count);
+        local64_sub(delta, &event->hw.period_left);
 }
 
 /*
@@ -296,11 +296,11 @@ static int fsl_emb_pmu_enable(struct perf_event *event)
 
         val = 0;
         if (event->hw.sample_period) {
-                s64 left = atomic64_read(&event->hw.period_left);
+                s64 left = local64_read(&event->hw.period_left);
                 if (left < 0x80000000L)
                         val = 0x80000000L - left;
         }
-        atomic64_set(&event->hw.prev_count, val);
+        local64_set(&event->hw.prev_count, val);
         write_pmc(i, val);
         perf_event_update_userpage(event);
 
@@ -371,8 +371,8 @@ static void fsl_emb_pmu_unthrottle(struct perf_event *event)
         if (left < 0x80000000L)
                 val = 0x80000000L - left;
         write_pmc(event->hw.idx, val);
-        atomic64_set(&event->hw.prev_count, val);
-        atomic64_set(&event->hw.period_left, left);
+        local64_set(&event->hw.prev_count, val);
+        local64_set(&event->hw.period_left, left);
         perf_event_update_userpage(event);
         perf_enable();
         local_irq_restore(flags);
@@ -500,7 +500,7 @@ const struct pmu *hw_perf_event_init(struct perf_event *event)
                 return ERR_PTR(-ENOTSUPP);
 
         event->hw.last_period = event->hw.sample_period;
-        atomic64_set(&event->hw.period_left, event->hw.last_period);
+        local64_set(&event->hw.period_left, event->hw.last_period);
 
         /*
          * See if we need to reserve the PMU.
@@ -541,16 +541,16 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
         int record = 0;
 
         /* we don't have to worry about interrupts here */
-        prev = atomic64_read(&event->hw.prev_count);
+        prev = local64_read(&event->hw.prev_count);
         delta = (val - prev) & 0xfffffffful;
-        atomic64_add(delta, &event->count);
+        local64_add(delta, &event->count);
 
         /*
          * See if the total period for this event has expired,
          * and update for the next period.
          */
         val = 0;
-        left = atomic64_read(&event->hw.period_left) - delta;
+        left = local64_read(&event->hw.period_left) - delta;
         if (period) {
                 if (left <= 0) {
                         left += period;
@@ -566,9 +566,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
          * Finally record data if requested.
          */
         if (record) {
-                struct perf_sample_data data = {
-                        .period = event->hw.last_period,
-                };
+                struct perf_sample_data data;
+
+                perf_sample_data_init(&data, 0);
+                data.period = event->hw.last_period;
 
                 if (perf_event_overflow(event, nmi, &data, regs)) {
                         /*
@@ -584,8 +585,8 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
         }
 
         write_pmc(event->hw.idx, val);
-        atomic64_set(&event->hw.prev_count, val);
-        atomic64_set(&event->hw.period_left, left);
+        local64_set(&event->hw.prev_count, val);
+        local64_set(&event->hw.period_left, left);
         perf_event_update_userpage(event);
 }
 
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 3b4dcc82a4c1..ab3e392ac63c 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -101,10 +101,6 @@ EXPORT_SYMBOL(pci_dram_offset);
 EXPORT_SYMBOL(start_thread);
 EXPORT_SYMBOL(kernel_thread);
 
-#ifdef CONFIG_PPC_FPU
-EXPORT_SYMBOL_GPL(cvt_df);
-EXPORT_SYMBOL_GPL(cvt_fd);
-#endif
 EXPORT_SYMBOL(giveup_fpu);
 #ifdef CONFIG_ALTIVEC
 EXPORT_SYMBOL(giveup_altivec);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 773424df828a..e78a5add7f15 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -37,6 +37,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/personality.h>
 #include <linux/random.h>
+#include <linux/hw_breakpoint.h>
 
 #include <asm/pgtable.h>
 #include <asm/uaccess.h>
@@ -462,14 +463,42 @@ struct task_struct *__switch_to(struct task_struct *prev,
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
         switch_booke_debug_regs(&new->thread);
 #else
+/*
+ * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
+ * schedule DABR
+ */
+#ifndef CONFIG_HAVE_HW_BREAKPOINT
         if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
                 set_dabr(new->thread.dabr);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
 
 
         new_thread = &new->thread;
         old_thread = &current->thread;
 
+#if defined(CONFIG_PPC_BOOK3E_64)
+        /* XXX Current Book3E code doesn't deal with kernel side DBCR0,
+         * we always hold the user values, so we set it now.
+         *
+         * However, we ensure the kernel MSR:DE is appropriately cleared too
+         * to avoid spurrious single step exceptions in the kernel.
+         *
+         * This will have to change to merge with the ppc32 code at some point,
+         * but I don't like much what ppc32 is doing today so there's some
+         * thinking needed there
+         */
+        if ((new_thread->dbcr0 | old_thread->dbcr0) & DBCR0_IDM) {
+                u32 dbcr0;
+
+                mtmsr(mfmsr() & ~MSR_DE);
+                isync();
+                dbcr0 = mfspr(SPRN_DBCR0);
+                dbcr0 = (dbcr0 & DBCR0_EDM) | new_thread->dbcr0;
+                mtspr(SPRN_DBCR0, dbcr0);
+        }
+#endif /* CONFIG_PPC64_BOOK3E */
+
 #ifdef CONFIG_PPC64
         /*
          * Collect processor utilization data per process
@@ -642,7 +671,11 @@ void flush_thread(void)
 {
         discard_lazy_cpu_state();
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINTS
+        flush_ptrace_hw_breakpoint(current);
+#else /* CONFIG_HAVE_HW_BREAKPOINTS */
         set_debug_reg_defaults(&current->thread);
+#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
 }
 
 void
@@ -660,6 +693,9 @@ void prepare_to_copy(struct task_struct *tsk)
         flush_altivec_to_thread(current);
         flush_vsx_to_thread(current);
         flush_spe_to_thread(current);
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        flush_ptrace_hw_breakpoint(tsk);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 }
 
 /*
@@ -1263,3 +1299,14 @@ unsigned long randomize_et_dyn(unsigned long base)
 
         return ret;
 }
+
+#ifdef CONFIG_SMP
+int arch_sd_sibling_asym_packing(void)
+{
+        if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
+                printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
+                return SD_ASYM_PACKING;
+        }
+        return 0;
+}
+#endif
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 3b6f8ae9b8cc..941ff4dbc567 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -311,6 +311,24 @@ static void __init prom_print_hex(unsigned long val)
         call_prom("write", 3, 1, _prom->stdout, buf, nibbles);
 }
 
+/* max number of decimal digits in an unsigned long */
+#define UL_DIGITS 21
+static void __init prom_print_dec(unsigned long val)
+{
+        int i, size;
+        char buf[UL_DIGITS+1];
+        struct prom_t *_prom = &RELOC(prom);
+
+        for (i = UL_DIGITS-1; i >= 0;  i--) {
+                buf[i] = (val % 10) + '0';
+                val = val/10;
+                if (val == 0)
+                        break;
+        }
+        /* shift stuff down */
+        size = UL_DIGITS - i;
+        call_prom("write", 3, 1, _prom->stdout, buf+i, size);
+}
 
 static void __init prom_printf(const char *format, ...)
 {
@@ -350,6 +368,14 @@ static void __init prom_printf(const char *format, ...)
                         v = va_arg(args, unsigned long);
                         prom_print_hex(v);
                         break;
+                case 'l':
+                        ++q;
+                        if (*q == 'u') { /* '%lu' */
+                                ++q;
+                                v = va_arg(args, unsigned long);
+                                prom_print_dec(v);
+                        }
+                        break;
                 }
         }
 }
@@ -835,11 +861,11 @@ static int __init prom_count_smt_threads(void)
                 if (plen == PROM_ERROR)
                         break;
                 plen >>= 2;
-                prom_debug("Found 0x%x smt threads per core\n", (unsigned long)plen);
+                prom_debug("Found %lu smt threads per core\n", (unsigned long)plen);
 
                 /* Sanity check */
                 if (plen < 1 || plen > 64) {
-                        prom_printf("Threads per core 0x%x out of bounds, assuming 1\n",
+                        prom_printf("Threads per core %lu out of bounds, assuming 1\n",
                                     (unsigned long)plen);
                         return 1;
                 }
@@ -869,12 +895,12 @@ static void __init prom_send_capabilities(void)
                 cores = (u32 *)PTRRELOC(&ibm_architecture_vec[IBM_ARCH_VEC_NRCORES_OFFSET]);
                 if (*cores != NR_CPUS) {
                         prom_printf("WARNING ! "
-                                    "ibm_architecture_vec structure inconsistent: 0x%x !\n",
+                                    "ibm_architecture_vec structure inconsistent: %lu!\n",
                                     *cores);
                 } else {
                         *cores = DIV_ROUND_UP(NR_CPUS, prom_count_smt_threads());
-                        prom_printf("Max number of cores passed to firmware: 0x%x\n",
-                                    (unsigned long)*cores);
+                        prom_printf("Max number of cores passed to firmware: %lu (NR_CPUS = %lu)\n",
+                                    *cores, NR_CPUS);
                 }
 
                 /* try calling the ibm,client-architecture-support method */
@@ -1482,7 +1508,7 @@ static void __init prom_hold_cpus(void)
                 reg = -1;
                 prom_getprop(node, "reg", &reg, sizeof(reg));
 
-                prom_debug("cpu hw idx   = 0x%x\n", reg);
+                prom_debug("cpu hw idx   = %lu\n", reg);
 
                 /* Init the acknowledge var which will be reset by
                  * the secondary cpu when it awakens from its OF
@@ -1492,7 +1518,7 @@ static void __init prom_hold_cpus(void)
 
                 if (reg != _prom->cpu) {
                         /* Primary Thread of non-boot cpu */
-                        prom_printf("starting cpu hw idx %x... ", reg);
+                        prom_printf("starting cpu hw idx %lu... ", reg);
                         call_prom("start-cpu", 3, 0, node,
                                   secondary_hold, reg);
 
@@ -1507,7 +1533,7 @@ static void __init prom_hold_cpus(void)
                 }
 #ifdef CONFIG_SMP
                 else
-                        prom_printf("boot cpu hw idx %x\n", reg);
+                        prom_printf("boot cpu hw idx %lu\n", reg);
 #endif /* CONFIG_SMP */
         }
 
@@ -2420,7 +2446,7 @@ static void __init prom_find_boot_cpu(void)
         prom_getprop(cpu_pkg, "reg", &getprop_rval, sizeof(getprop_rval));
         _prom->cpu = getprop_rval;
 
-        prom_debug("Booting CPU hw index = 0x%x\n", _prom->cpu);
+        prom_debug("Booting CPU hw index = %lu\n", _prom->cpu);
 }
 
 static void __init prom_check_initrd(unsigned long r3, unsigned long r4)
diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c
index 8362620c9e6f..88334af038e5 100644
--- a/arch/powerpc/kernel/prom_parse.c
+++ b/arch/powerpc/kernel/prom_parse.c
@@ -6,232 +6,11 @@
 #include <linux/module.h>
 #include <linux/ioport.h>
 #include <linux/etherdevice.h>
+#include <linux/of_address.h>
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 
-#ifdef DEBUG
-#define DBG(fmt...) do { printk(fmt); } while(0)
-#else
-#define DBG(fmt...) do { } while(0)
-#endif
-
-#ifdef CONFIG_PPC64
-#define PRu64   "%lx"
-#else
-#define PRu64   "%llx"
-#endif
-
-/* Max address size we deal with */
-#define OF_MAX_ADDR_CELLS       4
-#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
-                        (ns) > 0)
-
-static struct of_bus *of_match_bus(struct device_node *np);
-static int __of_address_to_resource(struct device_node *dev,
-                const u32 *addrp, u64 size, unsigned int flags,
-                struct resource *r);
-
-
-/* Debug utility */
-#ifdef DEBUG
-static void of_dump_addr(const char *s, const u32 *addr, int na)
-{
-        printk("%s", s);
-        while(na--)
-                printk(" %08x", *(addr++));
-        printk("\n");
-}
-#else
-static void of_dump_addr(const char *s, const u32 *addr, int na) { }
-#endif
-
-
-/* Callbacks for bus specific translators */
-struct of_bus {
-        const char      *name;
-        const char      *addresses;
-        int             (*match)(struct device_node *parent);
-        void            (*count_cells)(struct device_node *child,
-                                       int *addrc, int *sizec);
-        u64             (*map)(u32 *addr, const u32 *range,
-                                int na, int ns, int pna);
-        int             (*translate)(u32 *addr, u64 offset, int na);
-        unsigned int    (*get_flags)(const u32 *addr);
-};
-
-
-/*
- * Default translator (generic bus)
- */
-
-static void of_bus_default_count_cells(struct device_node *dev,
-                                       int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = of_n_addr_cells(dev);
-        if (sizec)
-                *sizec = of_n_size_cells(dev);
-}
-
-static u64 of_bus_default_map(u32 *addr, const u32 *range,
-                int na, int ns, int pna)
-{
-        u64 cp, s, da;
-
-        cp = of_read_number(range, na);
-        s  = of_read_number(range + na + pna, ns);
-        da = of_read_number(addr, na);
-
-        DBG("OF: default map, cp="PRu64", s="PRu64", da="PRu64"\n",
-            cp, s, da);
-
-        if (da < cp || da >= (cp + s))
-                return OF_BAD_ADDR;
-        return da - cp;
-}
-
-static int of_bus_default_translate(u32 *addr, u64 offset, int na)
-{
-        u64 a = of_read_number(addr, na);
-        memset(addr, 0, na * 4);
-        a += offset;
-        if (na > 1)
-                addr[na - 2] = a >> 32;
-        addr[na - 1] = a & 0xffffffffu;
-
-        return 0;
-}
-
-static unsigned int of_bus_default_get_flags(const u32 *addr)
-{
-        return IORESOURCE_MEM;
-}
-
-
 #ifdef CONFIG_PCI
-/*
- * PCI bus specific translator
- */
-
-static int of_bus_pci_match(struct device_node *np)
-{
-        /* "vci" is for the /chaos bridge on 1st-gen PCI powermacs */
-        return !strcmp(np->type, "pci") || !strcmp(np->type, "vci");
-}
-
-static void of_bus_pci_count_cells(struct device_node *np,
-                                   int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = 3;
-        if (sizec)
-                *sizec = 2;
-}
-
-static unsigned int of_bus_pci_get_flags(const u32 *addr)
-{
-        unsigned int flags = 0;
-        u32 w = addr[0];
-
-        switch((w >> 24) & 0x03) {
-        case 0x01:
-                flags |= IORESOURCE_IO;
-                break;
-        case 0x02: /* 32 bits */
-        case 0x03: /* 64 bits */
-                flags |= IORESOURCE_MEM;
-                break;
-        }
-        if (w & 0x40000000)
-                flags |= IORESOURCE_PREFETCH;
-        return flags;
-}
-
-static u64 of_bus_pci_map(u32 *addr, const u32 *range, int na, int ns, int pna)
-{
-        u64 cp, s, da;
-        unsigned int af, rf;
-
-        af = of_bus_pci_get_flags(addr);
-        rf = of_bus_pci_get_flags(range);
-
-        /* Check address type match */
-        if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO))
-                return OF_BAD_ADDR;
-
-        /* Read address values, skipping high cell */
-        cp = of_read_number(range + 1, na - 1);
-        s  = of_read_number(range + na + pna, ns);
-        da = of_read_number(addr + 1, na - 1);
-
-        DBG("OF: PCI map, cp="PRu64", s="PRu64", da="PRu64"\n", cp, s, da);
-
-        if (da < cp || da >= (cp + s))
-                return OF_BAD_ADDR;
-        return da - cp;
-}
-
-static int of_bus_pci_translate(u32 *addr, u64 offset, int na)
-{
-        return of_bus_default_translate(addr + 1, offset, na - 1);
-}
-
-const u32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size,
-                        unsigned int *flags)
-{
-        const u32 *prop;
-        unsigned int psize;
-        struct device_node *parent;
-        struct of_bus *bus;
-        int onesize, i, na, ns;
-
-        /* Get parent & match bus type */
-        parent = of_get_parent(dev);
-        if (parent == NULL)
-                return NULL;
-        bus = of_match_bus(parent);
-        if (strcmp(bus->name, "pci")) {
-                of_node_put(parent);
-                return NULL;
-        }
-        bus->count_cells(dev, &na, &ns);
-        of_node_put(parent);
-        if (!OF_CHECK_COUNTS(na, ns))
-                return NULL;
-
-        /* Get "reg" or "assigned-addresses" property */
-        prop = of_get_property(dev, bus->addresses, &psize);
-        if (prop == NULL)
-                return NULL;
-        psize /= 4;
-
-        onesize = na + ns;
-        for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++)
-                if ((prop[0] & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0)) {
-                        if (size)
-                                *size = of_read_number(prop + na, ns);
-                        if (flags)
-                                *flags = bus->get_flags(prop);
-                        return prop;
-                }
-        return NULL;
-}
-EXPORT_SYMBOL(of_get_pci_address);
-
-int of_pci_address_to_resource(struct device_node *dev, int bar,
-                               struct resource *r)
-{
-        const u32       *addrp;
-        u64             size;
-        unsigned int    flags;
-
-        addrp = of_get_pci_address(dev, bar, &size, &flags);
-        if (addrp == NULL)
-                return -EINVAL;
-        return __of_address_to_resource(dev, addrp, size, flags, r);
-}
-EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
-
 int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
 {
         struct device_node *dn, *ppnode;
@@ -313,345 +92,6 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
 EXPORT_SYMBOL_GPL(of_irq_map_pci);
 #endif /* CONFIG_PCI */
 
-/*
- * ISA bus specific translator
- */
-
-static int of_bus_isa_match(struct device_node *np)
-{
-        return !strcmp(np->name, "isa");
-}
-
-static void of_bus_isa_count_cells(struct device_node *child,
-                                   int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = 2;
-        if (sizec)
-                *sizec = 1;
-}
-
-static u64 of_bus_isa_map(u32 *addr, const u32 *range, int na, int ns, int pna)
-{
-        u64 cp, s, da;
-
-        /* Check address type match */
-        if ((addr[0] ^ range[0]) & 0x00000001)
-                return OF_BAD_ADDR;
-
-        /* Read address values, skipping high cell */
-        cp = of_read_number(range + 1, na - 1);
-        s  = of_read_number(range + na + pna, ns);
-        da = of_read_number(addr + 1, na - 1);
-
-        DBG("OF: ISA map, cp="PRu64", s="PRu64", da="PRu64"\n", cp, s, da);
-
-        if (da < cp || da >= (cp + s))
-                return OF_BAD_ADDR;
-        return da - cp;
-}
-
-static int of_bus_isa_translate(u32 *addr, u64 offset, int na)
-{
-        return of_bus_default_translate(addr + 1, offset, na - 1);
-}
-
-static unsigned int of_bus_isa_get_flags(const u32 *addr)
-{
-        unsigned int flags = 0;
-        u32 w = addr[0];
-
-        if (w & 1)
-                flags |= IORESOURCE_IO;
-        else
-                flags |= IORESOURCE_MEM;
-        return flags;
-}
-
-
-/*
- * Array of bus specific translators
- */
-
-static struct of_bus of_busses[] = {
-#ifdef CONFIG_PCI
-        /* PCI */
-        {
-                .name = "pci",
-                .addresses = "assigned-addresses",
-                .match = of_bus_pci_match,
-                .count_cells = of_bus_pci_count_cells,
-                .map = of_bus_pci_map,
-                .translate = of_bus_pci_translate,
-                .get_flags = of_bus_pci_get_flags,
-        },
-#endif /* CONFIG_PCI */
-        /* ISA */
-        {
-                .name = "isa",
-                .addresses = "reg",
-                .match = of_bus_isa_match,
-                .count_cells = of_bus_isa_count_cells,
-                .map = of_bus_isa_map,
-                .translate = of_bus_isa_translate,
-                .get_flags = of_bus_isa_get_flags,
-        },
-        /* Default */
-        {
-                .name = "default",
-                .addresses = "reg",
-                .match = NULL,
-                .count_cells = of_bus_default_count_cells,
-                .map = of_bus_default_map,
-                .translate = of_bus_default_translate,
-                .get_flags = of_bus_default_get_flags,
-        },
-};
-
-static struct of_bus *of_match_bus(struct device_node *np)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(of_busses); i ++)
-                if (!of_busses[i].match || of_busses[i].match(np))
-                        return &of_busses[i];
-        BUG();
-        return NULL;
-}
-
-static int of_translate_one(struct device_node *parent, struct of_bus *bus,
-                            struct of_bus *pbus, u32 *addr,
-                            int na, int ns, int pna, const char *rprop)
-{
-        const u32 *ranges;
-        unsigned int rlen;
-        int rone;
-        u64 offset = OF_BAD_ADDR;
-
-        /* Normally, an absence of a "ranges" property means we are
-         * crossing a non-translatable boundary, and thus the addresses
-         * below the current not cannot be converted to CPU physical ones.
-         * Unfortunately, while this is very clear in the spec, it's not
-         * what Apple understood, and they do have things like /uni-n or
-         * /ht nodes with no "ranges" property and a lot of perfectly
-         * useable mapped devices below them. Thus we treat the absence of
-         * "ranges" as equivalent to an empty "ranges" property which means
-         * a 1:1 translation at that level. It's up to the caller not to try
-         * to translate addresses that aren't supposed to be translated in
-         * the first place. --BenH.
-         */
-        ranges = of_get_property(parent, rprop, &rlen);
-        if (ranges == NULL || rlen == 0) {
-                offset = of_read_number(addr, na);
-                memset(addr, 0, pna * 4);
-                DBG("OF: no ranges, 1:1 translation\n");
-                goto finish;
-        }
-
-        DBG("OF: walking ranges...\n");
-
-        /* Now walk through the ranges */
-        rlen /= 4;
-        rone = na + pna + ns;
-        for (; rlen >= rone; rlen -= rone, ranges += rone) {
-                offset = bus->map(addr, ranges, na, ns, pna);
-                if (offset != OF_BAD_ADDR)
-                        break;
-        }
-        if (offset == OF_BAD_ADDR) {
-                DBG("OF: not found !\n");
-                return 1;
-        }
-        memcpy(addr, ranges + na, 4 * pna);
-
- finish:
-        of_dump_addr("OF: parent translation for:", addr, pna);
-        DBG("OF: with offset: "PRu64"\n", offset);
-
-        /* Translate it into parent bus space */
-        return pbus->translate(addr, offset, pna);
-}
-
-
-/*
- * Translate an address from the device-tree into a CPU physical address,
- * this walks up the tree and applies the various bus mappings on the
- * way.
- *
- * Note: We consider that crossing any level with #size-cells == 0 to mean
- * that translation is impossible (that is we are not dealing with a value
- * that can be mapped to a cpu physical address). This is not really specified
- * that way, but this is traditionally the way IBM at least do things
- */
-u64 __of_translate_address(struct device_node *dev, const u32 *in_addr,
-                           const char *rprop)
-{
-        struct device_node *parent = NULL;
-        struct of_bus *bus, *pbus;
-        u32 addr[OF_MAX_ADDR_CELLS];
-        int na, ns, pna, pns;
-        u64 result = OF_BAD_ADDR;
-
-        DBG("OF: ** translation for device %s **\n", dev->full_name);
-
-        /* Increase refcount at current level */
-        of_node_get(dev);
-
-        /* Get parent & match bus type */
-        parent = of_get_parent(dev);
-        if (parent == NULL)
-                goto bail;
-        bus = of_match_bus(parent);
-
-        /* Cound address cells & copy address locally */
-        bus->count_cells(dev, &na, &ns);
-        if (!OF_CHECK_COUNTS(na, ns)) {
-                printk(KERN_ERR "prom_parse: Bad cell count for %s\n",
-                       dev->full_name);
-                goto bail;
-        }
-        memcpy(addr, in_addr, na * 4);
-
-        DBG("OF: bus is %s (na=%d, ns=%d) on %s\n",
-            bus->name, na, ns, parent->full_name);
-        of_dump_addr("OF: translating address:", addr, na);
-
-        /* Translate */
-        for (;;) {
-                /* Switch to parent bus */
-                of_node_put(dev);
-                dev = parent;
-                parent = of_get_parent(dev);
-
-                /* If root, we have finished */
-                if (parent == NULL) {
-                        DBG("OF: reached root node\n");
-                        result = of_read_number(addr, na);
-                        break;
-                }
-
-                /* Get new parent bus and counts */
-                pbus = of_match_bus(parent);
-                pbus->count_cells(dev, &pna, &pns);
-                if (!OF_CHECK_COUNTS(pna, pns)) {
-                        printk(KERN_ERR "prom_parse: Bad cell count for %s\n",
-                               dev->full_name);
-                        break;
-                }
-
-                DBG("OF: parent bus is %s (na=%d, ns=%d) on %s\n",
-                    pbus->name, pna, pns, parent->full_name);
-
-                /* Apply bus translation */
-                if (of_translate_one(dev, bus, pbus, addr, na, ns, pna, rprop))
-                        break;
-
-                /* Complete the move up one level */
-                na = pna;
-                ns = pns;
-                bus = pbus;
-
-                of_dump_addr("OF: one level translation:", addr, na);
-        }
- bail:
-        of_node_put(parent);
-        of_node_put(dev);
-
-        return result;
-}
-
-u64 of_translate_address(struct device_node *dev, const u32 *in_addr)
-{
-        return __of_translate_address(dev, in_addr, "ranges");
-}
-EXPORT_SYMBOL(of_translate_address);
-
-u64 of_translate_dma_address(struct device_node *dev, const u32 *in_addr)
-{
-        return __of_translate_address(dev, in_addr, "dma-ranges");
-}
-EXPORT_SYMBOL(of_translate_dma_address);
-
-const u32 *of_get_address(struct device_node *dev, int index, u64 *size,
-                    unsigned int *flags)
-{
-        const u32 *prop;
-        unsigned int psize;
-        struct device_node *parent;
-        struct of_bus *bus;
-        int onesize, i, na, ns;
-
-        /* Get parent & match bus type */
-        parent = of_get_parent(dev);
-        if (parent == NULL)
-                return NULL;
-        bus = of_match_bus(parent);
-        bus->count_cells(dev, &na, &ns);
-        of_node_put(parent);
-        if (!OF_CHECK_COUNTS(na, ns))
-                return NULL;
-
-        /* Get "reg" or "assigned-addresses" property */
-        prop = of_get_property(dev, bus->addresses, &psize);
-        if (prop == NULL)
-                return NULL;
-        psize /= 4;
-
-        onesize = na + ns;
-        for (i = 0; psize >= onesize; psize -= onesize, prop += onesize, i++)
-                if (i == index) {
-                        if (size)
-                                *size = of_read_number(prop + na, ns);
-                        if (flags)
-                                *flags = bus->get_flags(prop);
-                        return prop;
-                }
-        return NULL;
-}
-EXPORT_SYMBOL(of_get_address);
-
-static int __of_address_to_resource(struct device_node *dev, const u32 *addrp,
-                                    u64 size, unsigned int flags,
-                                    struct resource *r)
-{
-        u64 taddr;
-
-        if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
-                return -EINVAL;
-        taddr = of_translate_address(dev, addrp);
-        if (taddr == OF_BAD_ADDR)
-                return -EINVAL;
-        memset(r, 0, sizeof(struct resource));
-        if (flags & IORESOURCE_IO) {
-                unsigned long port;
-                port = pci_address_to_pio(taddr);
-                if (port == (unsigned long)-1)
-                        return -EINVAL;
-                r->start = port;
-                r->end = port + size - 1;
-        } else {
-                r->start = taddr;
-                r->end = taddr + size - 1;
-        }
-        r->flags = flags;
-        r->name = dev->name;
-        return 0;
-}
-
-int of_address_to_resource(struct device_node *dev, int index,
-                           struct resource *r)
-{
-        const u32       *addrp;
-        u64             size;
-        unsigned int    flags;
-
-        addrp = of_get_address(dev, index, &size, &flags);
-        if (addrp == NULL)
-                return -EINVAL;
-        return __of_address_to_resource(dev, addrp, size, flags, r);
-}
-EXPORT_SYMBOL_GPL(of_address_to_resource);
-
 void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
                 unsigned long *busno, unsigned long *phys, unsigned long *size)
 {
@@ -678,342 +118,6 @@ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
         *size = of_read_number(dma_window, cells);
 }
 
-/*
- * Interrupt remapper
- */
-
-static unsigned int of_irq_workarounds;
-static struct device_node *of_irq_dflt_pic;
-
-static struct device_node *of_irq_find_parent(struct device_node *child)
-{
-        struct device_node *p;
-        const phandle *parp;
-
-        if (!of_node_get(child))
-                return NULL;
-
-        do {
-                parp = of_get_property(child, "interrupt-parent", NULL);
-                if (parp == NULL)
-                        p = of_get_parent(child);
-                else {
-                        if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
-                                p = of_node_get(of_irq_dflt_pic);
-                        else
-                                p = of_find_node_by_phandle(*parp);
-                }
-                of_node_put(child);
-                child = p;
-        } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
-
-        return p;
-}
-
-/* This doesn't need to be called if you don't have any special workaround
- * flags to pass
- */
-void of_irq_map_init(unsigned int flags)
-{
-        of_irq_workarounds = flags;
-
-        /* OldWorld, don't bother looking at other things */
-        if (flags & OF_IMAP_OLDWORLD_MAC)
-                return;
-
-        /* If we don't have phandles, let's try to locate a default interrupt
-         * controller (happens when booting with BootX). We do a first match
-         * here, hopefully, that only ever happens on machines with one
-         * controller.
-         */
-        if (flags & OF_IMAP_NO_PHANDLE) {
-                struct device_node *np;
-
-                for_each_node_with_property(np, "interrupt-controller") {
-                        /* Skip /chosen/interrupt-controller */
-                        if (strcmp(np->name, "chosen") == 0)
-                                continue;
-                        /* It seems like at least one person on this planet wants
-                         * to use BootX on a machine with an AppleKiwi controller
-                         * which happens to pretend to be an interrupt
-                         * controller too.
-                         */
-                        if (strcmp(np->name, "AppleKiwi") == 0)
-                                continue;
-                        /* I think we found one ! */
-                        of_irq_dflt_pic = np;
-                        break;
-                }
-        }
-
-}
-
-int of_irq_map_raw(struct device_node *parent, const u32 *intspec, u32 ointsize,
-                const u32 *addr, struct of_irq *out_irq)
-{
-        struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
-        const u32 *tmp, *imap, *imask;
-        u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
-        int imaplen, match, i;
-
-        DBG("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
-            parent->full_name, intspec[0], intspec[1], ointsize);
-
-        ipar = of_node_get(parent);
-
-        /* First get the #interrupt-cells property of the current cursor
-         * that tells us how to interpret the passed-in intspec. If there
-         * is none, we are nice and just walk up the tree
-         */
-        do {
-                tmp = of_get_property(ipar, "#interrupt-cells", NULL);
-                if (tmp != NULL) {
-                        intsize = *tmp;
-                        break;
-                }
-                tnode = ipar;
-                ipar = of_irq_find_parent(ipar);
-                of_node_put(tnode);
-        } while (ipar);
-        if (ipar == NULL) {
-                DBG(" -> no parent found !\n");
-                goto fail;
-        }
-
-        DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize);
-
-        if (ointsize != intsize)
-                return -EINVAL;
-
-        /* Look for this #address-cells. We have to implement the old linux
-         * trick of looking for the parent here as some device-trees rely on it
-         */
-        old = of_node_get(ipar);
-        do {
-                tmp = of_get_property(old, "#address-cells", NULL);
-                tnode = of_get_parent(old);
-                of_node_put(old);
-                old = tnode;
-        } while(old && tmp == NULL);
-        of_node_put(old);
-        old = NULL;
-        addrsize = (tmp == NULL) ? 2 : *tmp;
-
-        DBG(" -> addrsize=%d\n", addrsize);
-
-        /* Now start the actual "proper" walk of the interrupt tree */
-        while (ipar != NULL) {
-                /* Now check if cursor is an interrupt-controller and if it is
-                 * then we are done
-                 */
-                if (of_get_property(ipar, "interrupt-controller", NULL) !=
-                                NULL) {
-                        DBG(" -> got it !\n");
-                        memcpy(out_irq->specifier, intspec,
-                               intsize * sizeof(u32));
-                        out_irq->size = intsize;
-                        out_irq->controller = ipar;
-                        of_node_put(old);
-                        return 0;
-                }
-
-                /* Now look for an interrupt-map */
-                imap = of_get_property(ipar, "interrupt-map", &imaplen);
-                /* No interrupt map, check for an interrupt parent */
-                if (imap == NULL) {
-                        DBG(" -> no map, getting parent\n");
-                        newpar = of_irq_find_parent(ipar);
-                        goto skiplevel;
-                }
-                imaplen /= sizeof(u32);
-
-                /* Look for a mask */
-                imask = of_get_property(ipar, "interrupt-map-mask", NULL);
-
-                /* If we were passed no "reg" property and we attempt to parse
-                 * an interrupt-map, then #address-cells must be 0.
-                 * Fail if it's not.
-                 */
-                if (addr == NULL && addrsize != 0) {
-                        DBG(" -> no reg passed in when needed !\n");
-                        goto fail;
-                }
-
-                /* Parse interrupt-map */
-                match = 0;
-                while (imaplen > (addrsize + intsize + 1) && !match) {
-                        /* Compare specifiers */
-                        match = 1;
-                        for (i = 0; i < addrsize && match; ++i) {
-                                u32 mask = imask ? imask[i] : 0xffffffffu;
-                                match = ((addr[i] ^ imap[i]) & mask) == 0;
-                        }
-                        for (; i < (addrsize + intsize) && match; ++i) {
-                                u32 mask = imask ? imask[i] : 0xffffffffu;
-                                match =
-                                   ((intspec[i-addrsize] ^ imap[i]) & mask) == 0;
-                        }
-                        imap += addrsize + intsize;
-                        imaplen -= addrsize + intsize;
-
-                        DBG(" -> match=%d (imaplen=%d)\n", match, imaplen);
-
-                        /* Get the interrupt parent */
-                        if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
-                                newpar = of_node_get(of_irq_dflt_pic);
-                        else
-                                newpar = of_find_node_by_phandle((phandle)*imap);
-                        imap++;
-                        --imaplen;
-
-                        /* Check if not found */
-                        if (newpar == NULL) {
-                                DBG(" -> imap parent not found !\n");
-                                goto fail;
-                        }
-
-                        /* Get #interrupt-cells and #address-cells of new
-                         * parent
-                         */
-                        tmp = of_get_property(newpar, "#interrupt-cells", NULL);
-                        if (tmp == NULL) {
-                                DBG(" -> parent lacks #interrupt-cells !\n");
-                                goto fail;
-                        }
-                        newintsize = *tmp;
-                        tmp = of_get_property(newpar, "#address-cells", NULL);
-                        newaddrsize = (tmp == NULL) ? 0 : *tmp;
-
-                        DBG(" -> newintsize=%d, newaddrsize=%d\n",
-                            newintsize, newaddrsize);
-
-                        /* Check for malformed properties */
-                        if (imaplen < (newaddrsize + newintsize))
-                                goto fail;
-
-                        imap += newaddrsize + newintsize;
-                        imaplen -= newaddrsize + newintsize;
-
-                        DBG(" -> imaplen=%d\n", imaplen);
-                }
-                if (!match)
-                        goto fail;
-
-                of_node_put(old);
-                old = of_node_get(newpar);
-                addrsize = newaddrsize;
-                intsize = newintsize;
-                intspec = imap - intsize;
-                addr = intspec - addrsize;
-
-        skiplevel:
-                /* Iterate again with new parent */
-                DBG(" -> new parent: %s\n", newpar ? newpar->full_name : "<>");
-                of_node_put(ipar);
-                ipar = newpar;
-                newpar = NULL;
-        }
- fail:
-        of_node_put(ipar);
-        of_node_put(old);
-        of_node_put(newpar);
-
-        return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(of_irq_map_raw);
-
-#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
-static int of_irq_map_oldworld(struct device_node *device, int index,
-                               struct of_irq *out_irq)
-{
-        const u32 *ints = NULL;
-        int intlen;
-
-        /*
-         * Old machines just have a list of interrupt numbers
-         * and no interrupt-controller nodes. We also have dodgy
-         * cases where the APPL,interrupts property is completely
-         * missing behind pci-pci bridges and we have to get it
-         * from the parent (the bridge itself, as apple just wired
-         * everything together on these)
-         */
-        while (device) {
-                ints = of_get_property(device, "AAPL,interrupts", &intlen);
-                if (ints != NULL)
-                        break;
-                device = device->parent;
-                if (device && strcmp(device->type, "pci") != 0)
-                        break;
-        }
-        if (ints == NULL)
-                return -EINVAL;
-        intlen /= sizeof(u32);
-
-        if (index >= intlen)
-                return -EINVAL;
-
-        out_irq->controller = NULL;
-        out_irq->specifier[0] = ints[index];
-        out_irq->size = 1;
-
-        return 0;
-}
-#else /* defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) */
-static int of_irq_map_oldworld(struct device_node *device, int index,
-                               struct of_irq *out_irq)
-{
-        return -EINVAL;
-}
-#endif /* !(defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)) */
-
-int of_irq_map_one(struct device_node *device, int index, struct of_irq *out_irq)
-{
-        struct device_node *p;
-        const u32 *intspec, *tmp, *addr;
-        u32 intsize, intlen;
-        int res = -EINVAL;
-
-        DBG("of_irq_map_one: dev=%s, index=%d\n", device->full_name, index);
-
-        /* OldWorld mac stuff is "special", handle out of line */
-        if (of_irq_workarounds & OF_IMAP_OLDWORLD_MAC)
-                return of_irq_map_oldworld(device, index, out_irq);
-
-        /* Get the interrupts property */
-        intspec = of_get_property(device, "interrupts", &intlen);
-        if (intspec == NULL)
-                return -EINVAL;
-        intlen /= sizeof(u32);
-
-        /* Get the reg property (if any) */
-        addr = of_get_property(device, "reg", NULL);
-
-        /* Look for the interrupt parent. */
-        p = of_irq_find_parent(device);
-        if (p == NULL)
-                return -EINVAL;
-
-        /* Get size of interrupt specifier */
-        tmp = of_get_property(p, "#interrupt-cells", NULL);
-        if (tmp == NULL)
-                goto out;
-        intsize = *tmp;
-
-        DBG(" intsize=%d intlen=%d\n", intsize, intlen);
-
-        /* Check index */
-        if ((index + 1) * intsize > intlen)
-                goto out;
-
-        /* Get new specifier and map it */
-        res = of_irq_map_raw(p, intspec + index * intsize, intsize,
-                             addr, out_irq);
-out:
-        of_node_put(p);
-        return res;
-}
-EXPORT_SYMBOL_GPL(of_irq_map_one);
-
 /**
  * Search the device tree for the best MAC address to use.  'mac-address' is
  * checked first, because that is supposed to contain to "most recent" MAC
@@ -1051,29 +155,3 @@ const void *of_get_mac_address(struct device_node *np)
         return NULL;
 }
 EXPORT_SYMBOL(of_get_mac_address);
-
-int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
-{
-        int irq = irq_of_parse_and_map(dev, index);
-
-        /* Only dereference the resource if both the
-         * resource and the irq are valid. */
-        if (r && irq != NO_IRQ) {
-                r->start = r->end = irq;
-                r->flags = IORESOURCE_IRQ;
-        }
-
-        return irq;
-}
-EXPORT_SYMBOL_GPL(of_irq_to_resource);
-
-void __iomem *of_iomap(struct device_node *np, int index)
-{
-        struct resource res;
-
-        if (of_address_to_resource(np, index, &res))
-                return NULL;
-
-        return ioremap(res.start, 1 + res.end - res.start);
-}
-EXPORT_SYMBOL(of_iomap);
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 7a0c0199ea28..11f3cd9c832f 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -32,6 +32,8 @@
 #ifdef CONFIG_PPC32
 #include <linux/module.h>
 #endif
+#include <linux/hw_breakpoint.h>
+#include <linux/perf_event.h>
 
 #include <asm/uaccess.h>
 #include <asm/page.h>
@@ -866,9 +868,34 @@ void user_disable_single_step(struct task_struct *task)
         clear_tsk_thread_flag(task, TIF_SINGLESTEP);
 }
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+void ptrace_triggered(struct perf_event *bp, int nmi,
+                      struct perf_sample_data *data, struct pt_regs *regs)
+{
+        struct perf_event_attr attr;
+
+        /*
+         * Disable the breakpoint request here since ptrace has defined a
+         * one-shot behaviour for breakpoint exceptions in PPC64.
+         * The SIGTRAP signal is generated automatically for us in do_dabr().
+         * We don't have to do anything about that here
+         */
+        attr = bp->attr;
+        attr.disabled = true;
+        modify_user_hw_breakpoint(bp, &attr);
+}
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
 int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
                                unsigned long data)
 {
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        int ret;
+        struct thread_struct *thread = &(task->thread);
+        struct perf_event *bp;
+        struct perf_event_attr attr;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
         /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
          *  For embedded processors we support one DAC and no IAC's at the
          *  moment.
@@ -896,6 +923,43 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
         /* Ensure breakpoint translation bit is set */
         if (data && !(data & DABR_TRANSLATION))
                 return -EIO;
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        bp = thread->ptrace_bps[0];
+        if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
+                if (bp) {
+                        unregister_hw_breakpoint(bp);
+                        thread->ptrace_bps[0] = NULL;
+                }
+                return 0;
+        }
+        if (bp) {
+                attr = bp->attr;
+                attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+                arch_bp_generic_fields(data &
+                                        (DABR_DATA_WRITE | DABR_DATA_READ),
+                                                        &attr.bp_type);
+                ret =  modify_user_hw_breakpoint(bp, &attr);
+                if (ret)
+                        return ret;
+                thread->ptrace_bps[0] = bp;
+                thread->dabr = data;
+                return 0;
+        }
+
+        /* Create a new breakpoint request if one doesn't exist already */
+        hw_breakpoint_init(&attr);
+        attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+        arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
+                                                                &attr.bp_type);
+
+        thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
+                                                        ptrace_triggered, task);
+        if (IS_ERR(bp)) {
+                thread->ptrace_bps[0] = NULL;
+                return PTR_ERR(bp);
+        }
+
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 
         /* Move contents to the DABR register */
         task->thread.dabr = data;
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index d0516dbee762..41048de3c6c3 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -47,14 +47,6 @@ struct rtas_t rtas = {
 };
 EXPORT_SYMBOL(rtas);
 
-struct rtas_suspend_me_data {
-        atomic_t working; /* number of cpus accessing this struct */
-        atomic_t done;
-        int token; /* ibm,suspend-me */
-        int error;
-        struct completion *complete; /* wait on this until working == 0 */
-};
-
 DEFINE_SPINLOCK(rtas_data_buf_lock);
 EXPORT_SYMBOL(rtas_data_buf_lock);
 
@@ -714,14 +706,53 @@ void rtas_os_term(char *str)
 
 static int ibm_suspend_me_token = RTAS_UNKNOWN_SERVICE;
 #ifdef CONFIG_PPC_PSERIES
-static void rtas_percpu_suspend_me(void *info)
+static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_when_done)
+{
+        u16 slb_size = mmu_slb_size;
+        int rc = H_MULTI_THREADS_ACTIVE;
+        int cpu;
+
+        slb_set_size(SLB_MIN_SIZE);
+        printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n", smp_processor_id());
+
+        while (rc == H_MULTI_THREADS_ACTIVE && !atomic_read(&data->done) &&
+               !atomic_read(&data->error))
+                rc = rtas_call(data->token, 0, 1, NULL);
+
+        if (rc || atomic_read(&data->error)) {
+                printk(KERN_DEBUG "ibm,suspend-me returned %d\n", rc);
+                slb_set_size(slb_size);
+        }
+
+        if (atomic_read(&data->error))
+                rc = atomic_read(&data->error);
+
+        atomic_set(&data->error, rc);
+
+        if (wake_when_done) {
+                atomic_set(&data->done, 1);
+
+                for_each_online_cpu(cpu)
+                        plpar_hcall_norets(H_PROD, get_hard_smp_processor_id(cpu));
+        }
+
+        if (atomic_dec_return(&data->working) == 0)
+                complete(data->complete);
+
+        return rc;
+}
+
+int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data)
+{
+        atomic_inc(&data->working);
+        return __rtas_suspend_last_cpu(data, 0);
+}
+
+static int __rtas_suspend_cpu(struct rtas_suspend_me_data *data, int wake_when_done)
 {
         long rc = H_SUCCESS;
         unsigned long msr_save;
-        u16 slb_size = mmu_slb_size;
         int cpu;
-        struct rtas_suspend_me_data *data =
-                (struct rtas_suspend_me_data *)info;
 
         atomic_inc(&data->working);
 
@@ -729,7 +760,7 @@ static void rtas_percpu_suspend_me(void *info)
         msr_save = mfmsr();
         mtmsr(msr_save & ~(MSR_EE));
 
-        while (rc == H_SUCCESS && !atomic_read(&data->done))
+        while (rc == H_SUCCESS && !atomic_read(&data->done) && !atomic_read(&data->error))
                 rc = plpar_hcall_norets(H_JOIN);
 
         mtmsr(msr_save);
@@ -741,33 +772,37 @@ static void rtas_percpu_suspend_me(void *info)
                 /* All other cpus are in H_JOIN, this cpu does
                  * the suspend.
                  */
-                slb_set_size(SLB_MIN_SIZE);
-                printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n",
-                       smp_processor_id());
-                data->error = rtas_call(data->token, 0, 1, NULL);
-
-                if (data->error) {
-                        printk(KERN_DEBUG "ibm,suspend-me returned %d\n",
-                               data->error);
-                        slb_set_size(slb_size);
-                }
+                return __rtas_suspend_last_cpu(data, wake_when_done);
         } else {
                 printk(KERN_ERR "H_JOIN on cpu %i failed with rc = %ld\n",
                        smp_processor_id(), rc);
-                data->error = rc;
+                atomic_set(&data->error, rc);
         }
 
-        atomic_set(&data->done, 1);
+        if (wake_when_done) {
+                atomic_set(&data->done, 1);
 
-        /* This cpu did the suspend or got an error; in either case,
-         * we need to prod all other other cpus out of join state.
-         * Extra prods are harmless.
-         */
-        for_each_online_cpu(cpu)
-                plpar_hcall_norets(H_PROD, get_hard_smp_processor_id(cpu));
+                /* This cpu did the suspend or got an error; in either case,
+                 * we need to prod all other other cpus out of join state.
+                 * Extra prods are harmless.
+                 */
+                for_each_online_cpu(cpu)
+                        plpar_hcall_norets(H_PROD, get_hard_smp_processor_id(cpu));
+        }
 out:
         if (atomic_dec_return(&data->working) == 0)
                 complete(data->complete);
+        return rc;
+}
+
+int rtas_suspend_cpu(struct rtas_suspend_me_data *data)
+{
+        return __rtas_suspend_cpu(data, 0);
+}
+
+static void rtas_percpu_suspend_me(void *info)
+{
+        __rtas_suspend_cpu((struct rtas_suspend_me_data *)info, 1);
 }
 
 static int rtas_ibm_suspend_me(struct rtas_args *args)
@@ -802,22 +837,22 @@ static int rtas_ibm_suspend_me(struct rtas_args *args)
 
         atomic_set(&data.working, 0);
         atomic_set(&data.done, 0);
+        atomic_set(&data.error, 0);
         data.token = rtas_token("ibm,suspend-me");
-        data.error = 0;
         data.complete = &done;
 
         /* Call function on all CPUs.  One of us will make the
          * rtas call
          */
         if (on_each_cpu(rtas_percpu_suspend_me, &data, 0))
-                data.error = -EINVAL;
+                atomic_set(&data.error, -EINVAL);
 
         wait_for_completion(&done);
 
-        if (data.error != 0)
+        if (atomic_read(&data.error) != 0)
                 printk(KERN_ERR "Error doing global join\n");
 
-        return data.error;
+        return atomic_read(&data.error);
 }
 #else /* CONFIG_PPC_PSERIES */
 static int rtas_ibm_suspend_me(struct rtas_args *args)
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index b7e6c7e193ae..15ade0d7bbb2 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
         .orig_video_points = 16
 };
 
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
 #ifdef __DO_IRQ_CANON
 /* XXX should go elsewhere eventually */
 int ppc_do_canonicalize_irqs;
@@ -575,6 +579,15 @@ int check_legacy_ioport(unsigned long base_port)
                         np = of_find_compatible_node(NULL, NULL, "pnpPNP,f03");
                 if (np) {
                         parent = of_get_parent(np);
+
+                        of_i8042_kbd_irq = irq_of_parse_and_map(parent, 0);
+                        if (!of_i8042_kbd_irq)
+                                of_i8042_kbd_irq = 1;
+
+                        of_i8042_aux_irq = irq_of_parse_and_map(parent, 1);
+                        if (!of_i8042_aux_irq)
+                                of_i8042_aux_irq = 12;
+
                         of_node_put(np);
                         np = parent;
                         break;
@@ -701,16 +714,9 @@ static struct notifier_block ppc_dflt_plat_bus_notifier = {
         .priority = INT_MAX,
 };
 
-static struct notifier_block ppc_dflt_of_bus_notifier = {
-        .notifier_call = ppc_dflt_bus_notify,
-        .priority = INT_MAX,
-};
-
 static int __init setup_bus_notifier(void)
 {
         bus_register_notifier(&platform_bus_type, &ppc_dflt_plat_bus_notifier);
-        bus_register_notifier(&of_platform_bus_type, &ppc_dflt_of_bus_notifier);
-
         return 0;
 }
 
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index d135f93cb0f6..1bee4b68fa45 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -142,16 +142,6 @@ early_param("smt-enabled", early_smt_enabled);
 #define check_smt_enabled()
 #endif /* CONFIG_SMP */
 
-/* Put the paca pointer into r13 and SPRG_PACA */
-static void __init setup_paca(struct paca_struct *new_paca)
-{
-        local_paca = new_paca;
-        mtspr(SPRN_SPRG_PACA, local_paca);
-#ifdef CONFIG_PPC_BOOK3E
-        mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
-#endif
-}
-
 /*
  * Early initialization entry point. This is called by head.S
  * with MMU translation disabled. We rely on the "feature" of
@@ -600,6 +590,9 @@ static int pcpu_cpu_distance(unsigned int from, unsigned int to)
                 return REMOTE_DISTANCE;
 }
 
+unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
+EXPORT_SYMBOL(__per_cpu_offset);
+
 void __init setup_per_cpu_areas(void)
 {
         const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
@@ -624,8 +617,10 @@ void __init setup_per_cpu_areas(void)
                 panic("cannot initialize percpu area (err=%d)", rc);
 
         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
-        for_each_possible_cpu(cpu)
-                paca[cpu].data_offset = delta + pcpu_unit_offsets[cpu];
+        for_each_possible_cpu(cpu) {
+                __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
+                paca[cpu].data_offset = __per_cpu_offset[cpu];
+        }
 }
 #endif
 
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index a0afb555a7c9..7109f5b1baa8 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -11,6 +11,7 @@
 
 #include <linux/tracehook.h>
 #include <linux/signal.h>
+#include <asm/hw_breakpoint.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
 
@@ -149,6 +150,8 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
         if (current->thread.dabr)
                 set_dabr(current->thread.dabr);
 #endif
+        /* Re-enable the breakpoints for the signal stack */
+        thread_change_pc(current, regs);
 
         if (is32) {
                 if (ka.sa.sa_flags & SA_SIGINFO)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 5c196d1086d9..a61b3ddd7bb3 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -288,8 +288,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                         max_cpus = NR_CPUS;
         else
                 max_cpus = 1;
- 
-        smp_space_timers(max_cpus);
 
         for_each_possible_cpu(cpu)
                 if (cpu != boot_cpuid)
@@ -501,14 +499,6 @@ int __devinit start_secondary(void *unused)
         current->active_mm = &init_mm;
 
         smp_store_cpu_info(cpu);
-
-#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
-        /* Clear any pending timer interrupts */
-        mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
-
-        /* Enable decrementer interrupt */
-        mtspr(SPRN_TCR, TCR_DIE);
-#endif
         set_dec(tb_ticks_per_jiffy);
         preempt_disable();
         cpu_callin_map[cpu] = 1;
diff --git a/arch/powerpc/kernel/suspend.c b/arch/powerpc/kernel/suspend.c
index 6fc6328dc626..0167d53da30c 100644
--- a/arch/powerpc/kernel/suspend.c
+++ b/arch/powerpc/kernel/suspend.c
@@ -3,7 +3,7 @@
  *
  * Distribute under GPLv2
  *
- * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
+ * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
  */
 
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 0441bbdadbd1..ce53dfa7130d 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -149,16 +149,6 @@ unsigned long tb_ticks_per_usec = 100; /* sane default */
 EXPORT_SYMBOL(tb_ticks_per_usec);
 unsigned long tb_ticks_per_sec;
 EXPORT_SYMBOL(tb_ticks_per_sec);        /* for cputime_t conversions */
-u64 tb_to_xs;
-unsigned tb_to_us;
-
-#define TICKLEN_SCALE   NTP_SCALE_SHIFT
-static u64 last_tick_len;       /* units are ns / 2^TICKLEN_SCALE */
-static u64 ticklen_to_xs;       /* 0.64 fraction */
-
-/* If last_tick_len corresponds to about 1/HZ seconds, then
-   last_tick_len << TICKLEN_SHIFT will be about 2^63. */
-#define TICKLEN_SHIFT   (63 - 30 - TICKLEN_SCALE + SHIFT_HZ)
 
 DEFINE_SPINLOCK(rtc_lock);
 EXPORT_SYMBOL_GPL(rtc_lock);
@@ -174,7 +164,6 @@ unsigned long ppc_proc_freq;
 EXPORT_SYMBOL(ppc_proc_freq);
 unsigned long ppc_tb_freq;
 
-static u64 tb_last_jiffy __cacheline_aligned_in_smp;
 static DEFINE_PER_CPU(u64, last_jiffy);
 
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
@@ -423,30 +412,6 @@ void udelay(unsigned long usecs)
 }
 EXPORT_SYMBOL(udelay);
 
-static inline void update_gtod(u64 new_tb_stamp, u64 new_stamp_xsec,
-                               u64 new_tb_to_xs)
-{
-        /*
-         * tb_update_count is used to allow the userspace gettimeofday code
-         * to assure itself that it sees a consistent view of the tb_to_xs and
-         * stamp_xsec variables.  It reads the tb_update_count, then reads
-         * tb_to_xs and stamp_xsec and then reads tb_update_count again.  If
-         * the two values of tb_update_count match and are even then the
-         * tb_to_xs and stamp_xsec values are consistent.  If not, then it
-         * loops back and reads them again until this criteria is met.
-         * We expect the caller to have done the first increment of
-         * vdso_data->tb_update_count already.
-         */
-        vdso_data->tb_orig_stamp = new_tb_stamp;
-        vdso_data->stamp_xsec = new_stamp_xsec;
-        vdso_data->tb_to_xs = new_tb_to_xs;
-        vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec;
-        vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec;
-        vdso_data->stamp_xtime = xtime;
-        smp_wmb();
-        ++(vdso_data->tb_update_count);
-}
-
 #ifdef CONFIG_SMP
 unsigned long profile_pc(struct pt_regs *regs)
 {
@@ -470,7 +435,6 @@ EXPORT_SYMBOL(profile_pc);
 
 static int __init iSeries_tb_recal(void)
 {
-        struct div_result divres;
         unsigned long titan, tb;
 
         /* Make sure we only run on iSeries */
@@ -501,10 +465,7 @@ static int __init iSeries_tb_recal(void)
                                 tb_ticks_per_jiffy = new_tb_ticks_per_jiffy;
                                 tb_ticks_per_sec   = new_tb_ticks_per_sec;
                                 calc_cputime_factors();
-                                div128_by_32( XSEC_PER_SEC, 0, tb_ticks_per_sec, &divres );
-                                tb_to_xs = divres.result_low;
                                 vdso_data->tb_ticks_per_sec = tb_ticks_per_sec;
-                                vdso_data->tb_to_xs = tb_to_xs;
                                 setup_cputime_one_jiffy();
                         }
                         else {
@@ -667,27 +628,9 @@ void timer_interrupt(struct pt_regs * regs)
         trace_timer_interrupt_exit(regs);
 }
 
-void wakeup_decrementer(void)
-{
-        unsigned long ticks;
-
-        /*
-         * The timebase gets saved on sleep and restored on wakeup,
-         * so all we need to do is to reset the decrementer.
-         */
-        ticks = tb_ticks_since(__get_cpu_var(last_jiffy));
-        if (ticks < tb_ticks_per_jiffy)
-                ticks = tb_ticks_per_jiffy - ticks;
-        else
-                ticks = 1;
-        set_dec(ticks);
-}
-
 #ifdef CONFIG_SUSPEND
-void generic_suspend_disable_irqs(void)
+static void generic_suspend_disable_irqs(void)
 {
-        preempt_disable();
-
         /* Disable the decrementer, so that it doesn't interfere
          * with suspending.
          */
@@ -697,12 +640,9 @@ void generic_suspend_disable_irqs(void)
         set_dec(0x7fffffff);
 }
 
-void generic_suspend_enable_irqs(void)
+static void generic_suspend_enable_irqs(void)
 {
-        wakeup_decrementer();
-
         local_irq_enable();
-        preempt_enable();
 }
 
 /* Overrides the weak version in kernel/power/main.c */
@@ -722,23 +662,6 @@ void arch_suspend_enable_irqs(void)
 }
 #endif
 
-#ifdef CONFIG_SMP
-void __init smp_space_timers(unsigned int max_cpus)
-{
-        int i;
-        u64 previous_tb = per_cpu(last_jiffy, boot_cpuid);
-
-        /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */
-        previous_tb -= tb_ticks_per_jiffy;
-
-        for_each_possible_cpu(i) {
-                if (i == boot_cpuid)
-                        continue;
-                per_cpu(last_jiffy, i) = previous_tb;
-        }
-}
-#endif
-
 /*
  * Scheduler clock - returns current time in nanosec units.
  *
@@ -873,10 +796,11 @@ static cycle_t timebase_read(struct clocksource *cs)
         return (cycle_t)get_tb();
 }
 
-void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
-                     u32 mult)
+void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
+                        struct clocksource *clock, u32 mult)
 {
-        u64 t2x, stamp_xsec;
+        u64 new_tb_to_xs, new_stamp_xsec;
+        u32 frac_sec;
 
         if (clock != &clocksource_timebase)
                 return;
@@ -887,11 +811,35 @@ void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
 
         /* XXX this assumes clock->shift == 22 */
         /* 4611686018 ~= 2^(20+64-22) / 1e9 */
-        t2x = (u64) mult * 4611686018ULL;
-        stamp_xsec = (u64) xtime.tv_nsec * XSEC_PER_SEC;
-        do_div(stamp_xsec, 1000000000);
-        stamp_xsec += (u64) xtime.tv_sec * XSEC_PER_SEC;
-        update_gtod(clock->cycle_last, stamp_xsec, t2x);
+        new_tb_to_xs = (u64) mult * 4611686018ULL;
+        new_stamp_xsec = (u64) wall_time->tv_nsec * XSEC_PER_SEC;
+        do_div(new_stamp_xsec, 1000000000);
+        new_stamp_xsec += (u64) wall_time->tv_sec * XSEC_PER_SEC;
+
+        BUG_ON(wall_time->tv_nsec >= NSEC_PER_SEC);
+        /* this is tv_nsec / 1e9 as a 0.32 fraction */
+        frac_sec = ((u64) wall_time->tv_nsec * 18446744073ULL) >> 32;
+
+        /*
+         * tb_update_count is used to allow the userspace gettimeofday code
+         * to assure itself that it sees a consistent view of the tb_to_xs and
+         * stamp_xsec variables.  It reads the tb_update_count, then reads
+         * tb_to_xs and stamp_xsec and then reads tb_update_count again.  If
+         * the two values of tb_update_count match and are even then the
+         * tb_to_xs and stamp_xsec values are consistent.  If not, then it
+         * loops back and reads them again until this criteria is met.
+         * We expect the caller to have done the first increment of
+         * vdso_data->tb_update_count already.
+         */
+        vdso_data->tb_orig_stamp = clock->cycle_last;
+        vdso_data->stamp_xsec = new_stamp_xsec;
+        vdso_data->tb_to_xs = new_tb_to_xs;
+        vdso_data->wtom_clock_sec = wtm->tv_sec;
+        vdso_data->wtom_clock_nsec = wtm->tv_nsec;
+        vdso_data->stamp_xtime = *wall_time;
+        vdso_data->stamp_sec_fraction = frac_sec;
+        smp_wmb();
+        ++(vdso_data->tb_update_count);
 }
 
 void update_vsyscall_tz(void)
@@ -1007,15 +955,13 @@ void secondary_cpu_time_init(void)
 /* This function is only called on the boot processor */
 void __init time_init(void)
 {
-        unsigned long flags;
         struct div_result res;
-        u64 scale, x;
+        u64 scale;
         unsigned shift;
 
         if (__USE_RTC()) {
                 /* 601 processor: dec counts down by 128 every 128ns */
                 ppc_tb_freq = 1000000000;
-                tb_last_jiffy = get_rtcl();
         } else {
                 /* Normal PowerPC with timebase register */
                 ppc_md.calibrate_decr();
@@ -1023,50 +969,15 @@ void __init time_init(void)
                        ppc_tb_freq / 1000000, ppc_tb_freq % 1000000);
                 printk(KERN_DEBUG "time_init: processor frequency   = %lu.%.6lu MHz\n",
                        ppc_proc_freq / 1000000, ppc_proc_freq % 1000000);
-                tb_last_jiffy = get_tb();
         }
 
         tb_ticks_per_jiffy = ppc_tb_freq / HZ;
         tb_ticks_per_sec = ppc_tb_freq;
         tb_ticks_per_usec = ppc_tb_freq / 1000000;
-        tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
         calc_cputime_factors();
         setup_cputime_one_jiffy();
 
         /*
-         * Calculate the length of each tick in ns.  It will not be
-         * exactly 1e9/HZ unless ppc_tb_freq is divisible by HZ.
-         * We compute 1e9 * tb_ticks_per_jiffy / ppc_tb_freq,
-         * rounded up.
-         */
-        x = (u64) NSEC_PER_SEC * tb_ticks_per_jiffy + ppc_tb_freq - 1;
-        do_div(x, ppc_tb_freq);
-        tick_nsec = x;
-        last_tick_len = x << TICKLEN_SCALE;
-
-        /*
-         * Compute ticklen_to_xs, which is a factor which gets multiplied
-         * by (last_tick_len << TICKLEN_SHIFT) to get a tb_to_xs value.
-         * It is computed as:
-         * ticklen_to_xs = 2^N / (tb_ticks_per_jiffy * 1e9)
-         * where N = 64 + 20 - TICKLEN_SCALE - TICKLEN_SHIFT
-         * which turns out to be N = 51 - SHIFT_HZ.
-         * This gives the result as a 0.64 fixed-point fraction.
-         * That value is reduced by an offset amounting to 1 xsec per
-         * 2^31 timebase ticks to avoid problems with time going backwards
-         * by 1 xsec when we do timer_recalc_offset due to losing the
-         * fractional xsec.  That offset is equal to ppc_tb_freq/2^51
-         * since there are 2^20 xsec in a second.
-         */
-        div128_by_32((1ULL << 51) - ppc_tb_freq, 0,
-                     tb_ticks_per_jiffy << SHIFT_HZ, &res);
-        div128_by_32(res.result_high, res.result_low, NSEC_PER_SEC, &res);
-        ticklen_to_xs = res.result_low;
-
-        /* Compute tb_to_xs from tick_nsec */
-        tb_to_xs = mulhdu(last_tick_len << TICKLEN_SHIFT, ticklen_to_xs);
-
-        /*
          * Compute scale factor for sched_clock.
          * The calibrate_decr() function has set tb_ticks_per_sec,
          * which is the timebase frequency.
@@ -1087,21 +998,14 @@ void __init time_init(void)
         /* Save the current timebase to pretty up CONFIG_PRINTK_TIME */
         boot_tb = get_tb_or_rtc();
 
-        write_seqlock_irqsave(&xtime_lock, flags);
-
         /* If platform provided a timezone (pmac), we correct the time */
         if (timezone_offset) {
                 sys_tz.tz_minuteswest = -timezone_offset / 60;
                 sys_tz.tz_dsttime = 0;
         }
 
-        vdso_data->tb_orig_stamp = tb_last_jiffy;
         vdso_data->tb_update_count = 0;
         vdso_data->tb_ticks_per_sec = tb_ticks_per_sec;
-        vdso_data->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC;
-        vdso_data->tb_to_xs = tb_to_xs;
-
-        write_sequnlock_irqrestore(&xtime_lock, flags);
 
         /* Start the decrementer on CPUs that have manual control
          * such as BookE
@@ -1195,39 +1099,6 @@ void to_tm(int tim, struct rtc_time * tm)
         GregorianDay(tm);
 }
 
-/* Auxiliary function to compute scaling factors */
-/* Actually the choice of a timebase running at 1/4 the of the bus
- * frequency giving resolution of a few tens of nanoseconds is quite nice.
- * It makes this computation very precise (27-28 bits typically) which
- * is optimistic considering the stability of most processor clock
- * oscillators and the precision with which the timebase frequency
- * is measured but does not harm.
- */
-unsigned mulhwu_scale_factor(unsigned inscale, unsigned outscale)
-{
-        unsigned mlt=0, tmp, err;
-        /* No concern for performance, it's done once: use a stupid
-         * but safe and compact method to find the multiplier.
-         */
-  
-        for (tmp = 1U<<31; tmp != 0; tmp >>= 1) {
-                if (mulhwu(inscale, mlt|tmp) < outscale)
-                        mlt |= tmp;
-        }
-  
-        /* We might still be off by 1 for the best approximation.
-         * A side effect of this is that if outscale is too large
-         * the returned value will be zero.
-         * Many corner cases have been checked and seem to work,
-         * some might have been forgotten in the test however.
-         */
-  
-        err = inscale * (mlt+1);
-        if (err <= inscale/2)
-                mlt++;
-        return mlt;
-}
-
 /*
  * Divide a 128-bit dividend by a 32-bit divisor, leaving a 128 bit
  * result.
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 25fc33984c2b..a45a63c3a0c7 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -55,9 +55,6 @@
 #endif
 #include <asm/kexec.h>
 #include <asm/ppc-opcode.h>
-#ifdef CONFIG_FSL_BOOKE
-#include <asm/dbell.h>
-#endif
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -688,7 +685,7 @@ void RunModeException(struct pt_regs *regs)
 
 void __kprobes single_step_exception(struct pt_regs *regs)
 {
-        regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
+        clear_single_step(regs);
 
         if (notify_die(DIE_SSTEP, "single_step", regs, 5,
                                         5, SIGTRAP) == NOTIFY_STOP)
@@ -707,10 +704,8 @@ void __kprobes single_step_exception(struct pt_regs *regs)
  */
 static void emulate_single_step(struct pt_regs *regs)
 {
-        if (single_stepping(regs)) {
-                clear_single_step(regs);
-                _exception(SIGTRAP, regs, TRAP_TRACE, 0);
-        }
+        if (single_stepping(regs))
+                single_step_exception(regs);
 }
 
 static inline int __parse_fpscr(unsigned long fpscr)
@@ -1344,24 +1339,6 @@ void vsx_assist_exception(struct pt_regs *regs)
 #endif /* CONFIG_VSX */
 
 #ifdef CONFIG_FSL_BOOKE
-
-void doorbell_exception(struct pt_regs *regs)
-{
-#ifdef CONFIG_SMP
-        int cpu = smp_processor_id();
-        int msg;
-
-        if (num_online_cpus() < 2)
-                return;
-
-        for (msg = 0; msg < 4; msg++)
-                if (test_and_clear_bit(msg, &dbell_smp_message[cpu]))
-                        smp_message_recv(msg);
-#else
-        printk(KERN_WARNING "Received doorbell on non-smp system\n");
-#endif
-}
-
 void CacheLockingException(struct pt_regs *regs, unsigned long address,
                            unsigned long error_code)
 {
diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S
index ee038d4bf252..4ee09ee2e836 100644
--- a/arch/powerpc/kernel/vdso32/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso32/gettimeofday.S
@@ -19,8 +19,10 @@
 /* Offset for the low 32-bit part of a field of long type */
 #ifdef CONFIG_PPC64
 #define LOPART  4
+#define TSPEC_TV_SEC    TSPC64_TV_SEC+LOPART
 #else
 #define LOPART  0
+#define TSPEC_TV_SEC    TSPC32_TV_SEC
 #endif
 
         .text
@@ -41,23 +43,11 @@ V_FUNCTION_BEGIN(__kernel_gettimeofday)
         mr      r9, r3                  /* datapage ptr in r9 */
         cmplwi  r10,0                   /* check if tv is NULL */
         beq     3f
-        bl      __do_get_xsec@local     /* get xsec from tb & kernel */
-        bne-    2f                      /* out of line -> do syscall */
-
-        /* seconds are xsec >> 20 */
-        rlwinm  r5,r4,12,20,31
-        rlwimi  r5,r3,12,0,19
-        stw     r5,TVAL32_TV_SEC(r10)
-
-        /* get remaining xsec and convert to usec. we scale
-         * up remaining xsec by 12 bits and get the top 32 bits
-         * of the multiplication
-         */
-        rlwinm  r5,r4,12,0,19
-        lis     r6,1000000@h
-        ori     r6,r6,1000000@l
-        mulhwu  r5,r5,r6
-        stw     r5,TVAL32_TV_USEC(r10)
+        lis     r7,1000000@ha           /* load up USEC_PER_SEC */
+        addi    r7,r7,1000000@l         /* so we get microseconds in r4 */
+        bl      __do_get_tspec@local    /* get sec/usec from tb & kernel */
+        stw     r3,TVAL32_TV_SEC(r10)
+        stw     r4,TVAL32_TV_USEC(r10)
 
 3:      cmplwi  r11,0                   /* check if tz is NULL */
         beq     1f
@@ -70,14 +60,6 @@ V_FUNCTION_BEGIN(__kernel_gettimeofday)
         crclr   cr0*4+so
         li      r3,0
         blr
-
-2:
-        mtlr    r12
-        mr      r3,r10
-        mr      r4,r11
-        li      r0,__NR_gettimeofday
-        sc
-        blr
   .cfi_endproc
 V_FUNCTION_END(__kernel_gettimeofday)
 
@@ -100,7 +82,8 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime)
         mr      r11,r4                  /* r11 saves tp */
         bl      __get_datapage@local    /* get data page */
         mr      r9,r3                   /* datapage ptr in r9 */
-
+        lis     r7,NSEC_PER_SEC@h       /* want nanoseconds */
+        ori     r7,r7,NSEC_PER_SEC@l
 50:     bl      __do_get_tspec@local    /* get sec/nsec from tb & kernel */
         bne     cr1,80f                 /* not monotonic -> all done */
 
@@ -198,83 +181,12 @@ V_FUNCTION_END(__kernel_clock_getres)
 
 
 /*
- * This is the core of gettimeofday() & friends, it returns the xsec
- * value in r3 & r4 and expects the datapage ptr (non clobbered)
- * in r9. clobbers r0,r4,r5,r6,r7,r8.
- * When returning, r8 contains the counter value that can be reused
- * by the monotonic clock implementation
- */
-__do_get_xsec:
-  .cfi_startproc
-        /* Check for update count & load values. We use the low
-         * order 32 bits of the update count
-         */
-1:      lwz     r8,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
-        andi.   r0,r8,1                 /* pending update ? loop */
-        bne-    1b
-        xor     r0,r8,r8                /* create dependency */
-        add     r9,r9,r0
-
-        /* Load orig stamp (offset to TB) */
-        lwz     r5,CFG_TB_ORIG_STAMP(r9)
-        lwz     r6,(CFG_TB_ORIG_STAMP+4)(r9)
-
-        /* Get a stable TB value */
-2:      mftbu   r3
-        mftbl   r4
-        mftbu   r0
-        cmpl    cr0,r3,r0
-        bne-    2b
-
-        /* Substract tb orig stamp. If the high part is non-zero, we jump to
-         * the slow path which call the syscall.
-         * If it's ok, then we have our 32 bits tb_ticks value in r7
-         */
-        subfc   r7,r6,r4
-        subfe.  r0,r5,r3
-        bne-    3f
-
-        /* Load scale factor & do multiplication */
-        lwz     r5,CFG_TB_TO_XS(r9)     /* load values */
-        lwz     r6,(CFG_TB_TO_XS+4)(r9)
-        mulhwu  r4,r7,r5
-        mulhwu  r6,r7,r6
-        mullw   r0,r7,r5
-        addc    r6,r6,r0
-
-        /* At this point, we have the scaled xsec value in r4 + XER:CA
-         * we load & add the stamp since epoch
-         */
-        lwz     r5,CFG_STAMP_XSEC(r9)
-        lwz     r6,(CFG_STAMP_XSEC+4)(r9)
-        adde    r4,r4,r6
-        addze   r3,r5
-
-        /* We now have our result in r3,r4. We create a fake dependency
-         * on that result and re-check the counter
-         */
-        or      r6,r4,r3
-        xor     r0,r6,r6
-        add     r9,r9,r0
-        lwz     r0,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
-        cmpl    cr0,r8,r0               /* check if updated */
-        bne-    1b
-
-        /* Warning ! The caller expects CR:EQ to be set to indicate a
-         * successful calculation (so it won't fallback to the syscall
-         * method). We have overriden that CR bit in the counter check,
-         * but fortunately, the loop exit condition _is_ CR:EQ set, so
-         * we can exit safely here. If you change this code, be careful
-         * of that side effect.
-         */
-3:      blr
-  .cfi_endproc
-
-/*
- * This is the core of clock_gettime(), it returns the current
- * time in seconds and nanoseconds in r3 and r4.
+ * This is the core of clock_gettime() and gettimeofday(),
+ * it returns the current time in r3 (seconds) and r4.
+ * On entry, r7 gives the resolution of r4, either USEC_PER_SEC
+ * or NSEC_PER_SEC, giving r4 in microseconds or nanoseconds.
  * It expects the datapage ptr in r9 and doesn't clobber it.
- * It clobbers r0, r5, r6, r10 and returns NSEC_PER_SEC in r7.
+ * It clobbers r0, r5 and r6.
  * On return, r8 contains the counter value that can be reused.
  * This clobbers cr0 but not any other cr field.
  */
@@ -297,70 +209,58 @@ __do_get_tspec:
 2:      mftbu   r3
         mftbl   r4
         mftbu   r0
-        cmpl    cr0,r3,r0
+        cmplw   cr0,r3,r0
         bne-    2b
 
         /* Subtract tb orig stamp and shift left 12 bits.
          */
-        subfc   r7,r6,r4
+        subfc   r4,r6,r4
         subfe   r0,r5,r3
         slwi    r0,r0,12
-        rlwimi. r0,r7,12,20,31
-        slwi    r7,r7,12
+        rlwimi. r0,r4,12,20,31
+        slwi    r4,r4,12
 
-        /* Load scale factor & do multiplication */
+        /*
+         * Load scale factor & do multiplication.
+         * We only use the high 32 bits of the tb_to_xs value.
+         * Even with a 1GHz timebase clock, the high 32 bits of
+         * tb_to_xs will be at least 4 million, so the error from
+         * ignoring the low 32 bits will be no more than 0.25ppm.
+         * The error will just make the clock run very very slightly
+         * slow until the next time the kernel updates the VDSO data,
+         * at which point the clock will catch up to the kernel's value,
+         * so there is no long-term error accumulation.
+         */
         lwz     r5,CFG_TB_TO_XS(r9)     /* load values */
-        lwz     r6,(CFG_TB_TO_XS+4)(r9)
-        mulhwu  r3,r7,r6
-        mullw   r10,r7,r5
-        mulhwu  r4,r7,r5
-        addc    r10,r3,r10
+        mulhwu  r4,r4,r5
         li      r3,0
 
         beq+    4f                      /* skip high part computation if 0 */
         mulhwu  r3,r0,r5
-        mullw   r7,r0,r5
-        mulhwu  r5,r0,r6
-        mullw   r6,r0,r6
-        adde    r4,r4,r7
-        addze   r3,r3
+        mullw   r5,r0,r5
         addc    r4,r4,r5
         addze   r3,r3
-        addc    r10,r10,r6
-
-4:      addze   r4,r4                   /* add in carry */
-        lis     r7,NSEC_PER_SEC@h
-        ori     r7,r7,NSEC_PER_SEC@l
-        mulhwu  r4,r4,r7                /* convert to nanoseconds */
-
-        /* At this point, we have seconds & nanoseconds since the xtime
-         * stamp in r3+CA and r4.  Load & add the xtime stamp.
+4:
+        /* At this point, we have seconds since the xtime stamp
+         * as a 32.32 fixed-point number in r3 and r4.
+         * Load & add the xtime stamp.
          */
-#ifdef CONFIG_PPC64
-        lwz     r5,STAMP_XTIME+TSPC64_TV_SEC+LOPART(r9)
-        lwz     r6,STAMP_XTIME+TSPC64_TV_NSEC+LOPART(r9)
-#else
-        lwz     r5,STAMP_XTIME+TSPC32_TV_SEC(r9)
-        lwz     r6,STAMP_XTIME+TSPC32_TV_NSEC(r9)
-#endif
-        add     r4,r4,r6
+        lwz     r5,STAMP_XTIME+TSPEC_TV_SEC(r9)
+        lwz     r6,STAMP_SEC_FRAC(r9)
+        addc    r4,r4,r6
         adde    r3,r3,r5
 
-        /* We now have our result in r3,r4. We create a fake dependency
-         * on that result and re-check the counter
+        /* We create a fake dependency on the result in r3/r4
+         * and re-check the counter
          */
         or      r6,r4,r3
         xor     r0,r6,r6
         add     r9,r9,r0
         lwz     r0,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
-        cmpl    cr0,r8,r0               /* check if updated */
+        cmplw   cr0,r8,r0               /* check if updated */
         bne-    1b
 
-        /* check for nanosecond overflow and adjust if necessary */
-        cmpw    r4,r7
-        bltlr                           /* all done if no overflow */
-        subf    r4,r7,r4                /* adjust if overflow */
-        addi    r3,r3,1
+        mulhwu  r4,r4,r7                /* convert to micro or nanoseconds */
 
         blr
   .cfi_endproc
diff --git a/arch/powerpc/kernel/vdso64/gettimeofday.S b/arch/powerpc/kernel/vdso64/gettimeofday.S
index 262cd5857a56..e97a9a0dc4ac 100644
--- a/arch/powerpc/kernel/vdso64/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso64/gettimeofday.S
@@ -33,18 +33,11 @@ V_FUNCTION_BEGIN(__kernel_gettimeofday)
         bl      V_LOCAL_FUNC(__get_datapage)    /* get data page */
         cmpldi  r11,0                   /* check if tv is NULL */
         beq     2f
-        bl      V_LOCAL_FUNC(__do_get_xsec)     /* get xsec from tb & kernel */
-        lis     r7,15                   /* r7 = 1000000 = USEC_PER_SEC */
-        ori     r7,r7,16960
-        rldicl  r5,r4,44,20             /* r5 = sec = xsec / XSEC_PER_SEC */
-        rldicr  r6,r5,20,43             /* r6 = sec * XSEC_PER_SEC */
-        std     r5,TVAL64_TV_SEC(r11)   /* store sec in tv */
-        subf    r0,r6,r4                /* r0 = xsec = (xsec - r6) */
-        mulld   r0,r0,r7                /* usec = (xsec * USEC_PER_SEC) /
-                                         * XSEC_PER_SEC
-                                         */
-        rldicl  r0,r0,44,20
-        std     r0,TVAL64_TV_USEC(r11)  /* store usec in tv */
+        lis     r7,1000000@ha           /* load up USEC_PER_SEC */
+        addi    r7,r7,1000000@l
+        bl      V_LOCAL_FUNC(__do_get_tspec) /* get sec/us from tb & kernel */
+        std     r4,TVAL64_TV_SEC(r11)   /* store sec in tv */
+        std     r5,TVAL64_TV_USEC(r11)  /* store usec in tv */
 2:      cmpldi  r10,0                   /* check if tz is NULL */
         beq     1f
         lwz     r4,CFG_TZ_MINUTEWEST(r3)/* fill tz */
@@ -77,6 +70,8 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime)
   .cfi_register lr,r12
         mr      r11,r4                  /* r11 saves tp */
         bl      V_LOCAL_FUNC(__get_datapage)    /* get data page */
+        lis     r7,NSEC_PER_SEC@h       /* want nanoseconds */
+        ori     r7,r7,NSEC_PER_SEC@l
 50:     bl      V_LOCAL_FUNC(__do_get_tspec)    /* get time from tb & kernel */
         bne     cr1,80f                 /* if not monotonic, all done */
 
@@ -171,49 +166,12 @@ V_FUNCTION_END(__kernel_clock_getres)
 
 
 /*
- * This is the core of gettimeofday(), it returns the xsec
- * value in r4 and expects the datapage ptr (non clobbered)
- * in r3. clobbers r0,r4,r5,r6,r7,r8
- * When returning, r8 contains the counter value that can be reused
- */
-V_FUNCTION_BEGIN(__do_get_xsec)
-  .cfi_startproc
-        /* check for update count & load values */
-1:      ld      r8,CFG_TB_UPDATE_COUNT(r3)
-        andi.   r0,r8,1                 /* pending update ? loop */
-        bne-    1b
-        xor     r0,r8,r8                /* create dependency */
-        add     r3,r3,r0
-
-        /* Get TB & offset it. We use the MFTB macro which will generate
-         * workaround code for Cell.
-         */
-        MFTB(r7)
-        ld      r9,CFG_TB_ORIG_STAMP(r3)
-        subf    r7,r9,r7
-
-        /* Scale result */
-        ld      r5,CFG_TB_TO_XS(r3)
-        mulhdu  r7,r7,r5
-
-        /* Add stamp since epoch */
-        ld      r6,CFG_STAMP_XSEC(r3)
-        add     r4,r6,r7
-
-        xor     r0,r4,r4
-        add     r3,r3,r0
-        ld      r0,CFG_TB_UPDATE_COUNT(r3)
-        cmpld   cr0,r0,r8               /* check if updated */
-        bne-    1b
-        blr
-  .cfi_endproc
-V_FUNCTION_END(__do_get_xsec)
-
-/*
- * This is the core of clock_gettime(), it returns the current
- * time in seconds and nanoseconds in r4 and r5.
+ * This is the core of clock_gettime() and gettimeofday(),
+ * it returns the current time in r4 (seconds) and r5.
+ * On entry, r7 gives the resolution of r5, either USEC_PER_SEC
+ * or NSEC_PER_SEC, giving r5 in microseconds or nanoseconds.
  * It expects the datapage ptr in r3 and doesn't clobber it.
- * It clobbers r0 and r6 and returns NSEC_PER_SEC in r7.
+ * It clobbers r0, r6 and r9.
  * On return, r8 contains the counter value that can be reused.
  * This clobbers cr0 but not any other cr field.
  */
@@ -229,18 +187,18 @@ V_FUNCTION_BEGIN(__do_get_tspec)
         /* Get TB & offset it. We use the MFTB macro which will generate
          * workaround code for Cell.
          */
-        MFTB(r7)
+        MFTB(r6)
         ld      r9,CFG_TB_ORIG_STAMP(r3)
-        subf    r7,r9,r7
+        subf    r6,r9,r6
 
         /* Scale result */
         ld      r5,CFG_TB_TO_XS(r3)
-        sldi    r7,r7,12                /* compute time since stamp_xtime */
-        mulhdu  r6,r7,r5                /* in units of 2^-32 seconds */
+        sldi    r6,r6,12                /* compute time since stamp_xtime */
+        mulhdu  r6,r6,r5                /* in units of 2^-32 seconds */
 
         /* Add stamp since epoch */
         ld      r4,STAMP_XTIME+TSPC64_TV_SEC(r3)
-        ld      r5,STAMP_XTIME+TSPC64_TV_NSEC(r3)
+        lwz     r5,STAMP_SEC_FRAC(r3)
         or      r0,r4,r5
         or      r0,r0,r6
         xor     r0,r0,r0
@@ -250,17 +208,11 @@ V_FUNCTION_BEGIN(__do_get_tspec)
         bne-    1b                      /* reload if so */
 
         /* convert to seconds & nanoseconds and add to stamp */
-        lis     r7,NSEC_PER_SEC@h
-        ori     r7,r7,NSEC_PER_SEC@l
-        mulhwu  r0,r6,r7                /* compute nanoseconds and */
+        add     r6,r6,r5                /* add on fractional seconds of xtime */
+        mulhwu  r5,r6,r7                /* compute micro or nanoseconds and */
         srdi    r6,r6,32                /* seconds since stamp_xtime */
-        clrldi  r0,r0,32
-        add     r5,r5,r0                /* add nanoseconds together */
-        cmpd    r5,r7                   /* overflow? */
+        clrldi  r5,r5,32
         add     r4,r4,r6
-        bltlr                           /* all done if no overflow */
-        subf    r5,r7,r5                /* if overflow, adjust */
-        addi    r4,r4,1
         blr
   .cfi_endproc
 V_FUNCTION_END(__do_get_tspec)
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 812312542e50..9b9b5cdea840 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -316,7 +316,8 @@ void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gpa_t gpaddr,
         gfn = gpaddr >> PAGE_SHIFT;
         new_page = gfn_to_page(vcpu->kvm, gfn);
         if (is_error_page(new_page)) {
-                printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
+                printk(KERN_ERR "Couldn't get guest page for gfn %llx!\n",
+                        (unsigned long long)gfn);
                 kvm_release_page_clean(new_page);
                 return;
         }
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index ff436066bf77..d45c818a384c 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -45,6 +45,7 @@ kvm-book3s_64-objs := \
         book3s.o \
         book3s_emulate.o \
         book3s_interrupts.o \
+        book3s_mmu_hpte.o \
         book3s_64_mmu_host.o \
         book3s_64_mmu.o \
         book3s_32_mmu.o
@@ -57,6 +58,7 @@ kvm-book3s_32-objs := \
         book3s.o \
         book3s_emulate.o \
         book3s_interrupts.o \
+        book3s_mmu_hpte.o \
         book3s_32_mmu_host.o \
         book3s_32_mmu.o
 kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index b998abf1a63d..a3cef30d1d42 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -1047,8 +1047,6 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
         int i;
 
-        vcpu_load(vcpu);
-
         regs->pc = kvmppc_get_pc(vcpu);
         regs->cr = kvmppc_get_cr(vcpu);
         regs->ctr = kvmppc_get_ctr(vcpu);
@@ -1069,8 +1067,6 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -1078,8 +1074,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
         int i;
 
-        vcpu_load(vcpu);
-
         kvmppc_set_pc(vcpu, regs->pc);
         kvmppc_set_cr(vcpu, regs->cr);
         kvmppc_set_ctr(vcpu, regs->ctr);
@@ -1099,8 +1093,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -1110,8 +1102,6 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
         struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
         int i;
 
-        vcpu_load(vcpu);
-
         sregs->pvr = vcpu->arch.pvr;
 
         sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1;
@@ -1131,8 +1121,6 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
                 }
         }
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -1142,8 +1130,6 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
         int i;
 
-        vcpu_load(vcpu);
-
         kvmppc_set_pvr(vcpu, sregs->pvr);
 
         vcpu3s->sdr1 = sregs->u.s.sdr1;
@@ -1171,8 +1157,6 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         /* Flush the MMU after messing with the segments */
         kvmppc_mmu_pte_flush(vcpu, 0, 0);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -1309,12 +1293,17 @@ extern int __kvmppc_vcpu_entry(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
 int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 {
         int ret;
-        struct thread_struct ext_bkp;
+        double fpr[32][TS_FPRWIDTH];
+        unsigned int fpscr;
+        int fpexc_mode;
 #ifdef CONFIG_ALTIVEC
-        bool save_vec = current->thread.used_vr;
+        vector128 vr[32];
+        vector128 vscr;
+        unsigned long uninitialized_var(vrsave);
+        int used_vr;
 #endif
 #ifdef CONFIG_VSX
-        bool save_vsx = current->thread.used_vsr;
+        int used_vsr;
 #endif
         ulong ext_msr;
 
@@ -1327,27 +1316,27 @@ int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         /* Save FPU state in stack */
         if (current->thread.regs->msr & MSR_FP)
                 giveup_fpu(current);
-        memcpy(ext_bkp.fpr, current->thread.fpr, sizeof(current->thread.fpr));
-        ext_bkp.fpscr = current->thread.fpscr;
-        ext_bkp.fpexc_mode = current->thread.fpexc_mode;
+        memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr));
+        fpscr = current->thread.fpscr.val;
+        fpexc_mode = current->thread.fpexc_mode;
 
 #ifdef CONFIG_ALTIVEC
         /* Save Altivec state in stack */
-        if (save_vec) {
+        used_vr = current->thread.used_vr;
+        if (used_vr) {
                 if (current->thread.regs->msr & MSR_VEC)
                         giveup_altivec(current);
-                memcpy(ext_bkp.vr, current->thread.vr, sizeof(ext_bkp.vr));
-                ext_bkp.vscr = current->thread.vscr;
-                ext_bkp.vrsave = current->thread.vrsave;
+                memcpy(vr, current->thread.vr, sizeof(current->thread.vr));
+                vscr = current->thread.vscr;
+                vrsave = current->thread.vrsave;
         }
-        ext_bkp.used_vr = current->thread.used_vr;
 #endif
 
 #ifdef CONFIG_VSX
         /* Save VSX state in stack */
-        if (save_vsx && (current->thread.regs->msr & MSR_VSX))
+        used_vsr = current->thread.used_vsr;
+        if (used_vsr && (current->thread.regs->msr & MSR_VSX))
                         __giveup_vsx(current);
-        ext_bkp.used_vsr = current->thread.used_vsr;
 #endif
 
         /* Remember the MSR with disabled extensions */
@@ -1372,22 +1361,22 @@ int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         kvmppc_giveup_ext(vcpu, MSR_VSX);
 
         /* Restore FPU state from stack */
-        memcpy(current->thread.fpr, ext_bkp.fpr, sizeof(ext_bkp.fpr));
-        current->thread.fpscr = ext_bkp.fpscr;
-        current->thread.fpexc_mode = ext_bkp.fpexc_mode;
+        memcpy(current->thread.fpr, fpr, sizeof(current->thread.fpr));
+        current->thread.fpscr.val = fpscr;
+        current->thread.fpexc_mode = fpexc_mode;
 
 #ifdef CONFIG_ALTIVEC
         /* Restore Altivec state from stack */
-        if (save_vec && current->thread.used_vr) {
-                memcpy(current->thread.vr, ext_bkp.vr, sizeof(ext_bkp.vr));
-                current->thread.vscr = ext_bkp.vscr;
-                current->thread.vrsave= ext_bkp.vrsave;
+        if (used_vr && current->thread.used_vr) {
+                memcpy(current->thread.vr, vr, sizeof(current->thread.vr));
+                current->thread.vscr = vscr;
+                current->thread.vrsave = vrsave;
         }
-        current->thread.used_vr = ext_bkp.used_vr;
+        current->thread.used_vr = used_vr;
 #endif
 
 #ifdef CONFIG_VSX
-        current->thread.used_vsr = ext_bkp.used_vsr;
+        current->thread.used_vsr = used_vsr;
 #endif
 
         return ret;
@@ -1395,12 +1384,22 @@ int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 
 static int kvmppc_book3s_init(void)
 {
-        return kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), 0,
-                        THIS_MODULE);
+        int r;
+
+        r = kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), 0,
+                     THIS_MODULE);
+
+        if (r)
+                return r;
+
+        r = kvmppc_mmu_hpte_sysinit();
+
+        return r;
 }
 
 static void kvmppc_book3s_exit(void)
 {
+        kvmppc_mmu_hpte_sysexit();
         kvm_exit();
 }
 
diff --git a/arch/powerpc/kvm/book3s_32_mmu.c b/arch/powerpc/kvm/book3s_32_mmu.c
index 0b10503c8a4a..3292d76101d2 100644
--- a/arch/powerpc/kvm/book3s_32_mmu.c
+++ b/arch/powerpc/kvm/book3s_32_mmu.c
@@ -354,10 +354,10 @@ static int kvmppc_mmu_book3s_32_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid,
                 *vsid = VSID_REAL_DR | gvsid;
                 break;
         case MSR_DR|MSR_IR:
-                if (!sr->valid)
-                        return -1;
-
-                *vsid = sr->vsid;
+                if (sr->valid)
+                        *vsid = sr->vsid;
+                else
+                        *vsid = VSID_BAT | gvsid;
                 break;
         default:
                 BUG();
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c
index 0bb66005338f..0b51ef872c1e 100644
--- a/arch/powerpc/kvm/book3s_32_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_32_mmu_host.c
@@ -19,6 +19,7 @@
  */
 
 #include <linux/kvm_host.h>
+#include <linux/hash.h>
 
 #include <asm/kvm_ppc.h>
 #include <asm/kvm_book3s.h>
@@ -57,139 +58,26 @@
 static ulong htab;
 static u32 htabmask;
 
-static void invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
+void kvmppc_mmu_invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
 {
         volatile u32 *pteg;
 
-        dprintk_mmu("KVM: Flushing SPTE: 0x%llx (0x%llx) -> 0x%llx\n",
-                    pte->pte.eaddr, pte->pte.vpage, pte->host_va);
-
+        /* Remove from host HTAB */
         pteg = (u32*)pte->slot;
-
         pteg[0] = 0;
+
+        /* And make sure it's gone from the TLB too */
         asm volatile ("sync");
         asm volatile ("tlbie %0" : : "r" (pte->pte.eaddr) : "memory");
         asm volatile ("sync");
         asm volatile ("tlbsync");
-
-        pte->host_va = 0;
-
-        if (pte->pte.may_write)
-                kvm_release_pfn_dirty(pte->pfn);
-        else
-                kvm_release_pfn_clean(pte->pfn);
-}
-
-void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong guest_ea, ulong ea_mask)
-{
-        int i;
-
-        dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%x & 0x%x\n",
-                    vcpu->arch.hpte_cache_offset, guest_ea, ea_mask);
-        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
-
-        guest_ea &= ea_mask;
-        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if ((pte->pte.eaddr & ea_mask) == guest_ea) {
-                        invalidate_pte(vcpu, pte);
-                }
-        }
-
-        /* Doing a complete flush -> start from scratch */
-        if (!ea_mask)
-                vcpu->arch.hpte_cache_offset = 0;
-}
-
-void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask)
-{
-        int i;
-
-        dprintk_mmu("KVM: Flushing %d Shadow vPTEs: 0x%llx & 0x%llx\n",
-                    vcpu->arch.hpte_cache_offset, guest_vp, vp_mask);
-        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
-
-        guest_vp &= vp_mask;
-        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if ((pte->pte.vpage & vp_mask) == guest_vp) {
-                        invalidate_pte(vcpu, pte);
-                }
-        }
-}
-
-void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end)
-{
-        int i;
-
-        dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%llx & 0x%llx\n",
-                    vcpu->arch.hpte_cache_offset, pa_start, pa_end);
-        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
-
-        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if ((pte->pte.raddr >= pa_start) &&
-                    (pte->pte.raddr < pa_end)) {
-                        invalidate_pte(vcpu, pte);
-                }
-        }
-}
-
-struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data)
-{
-        int i;
-        u64 guest_vp;
-
-        guest_vp = vcpu->arch.mmu.ea_to_vp(vcpu, ea, false);
-        for (i=0; i<vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if (pte->pte.vpage == guest_vp)
-                        return &pte->pte;
-        }
-
-        return NULL;
-}
-
-static int kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu)
-{
-        if (vcpu->arch.hpte_cache_offset == HPTEG_CACHE_NUM)
-                kvmppc_mmu_pte_flush(vcpu, 0, 0);
-
-        return vcpu->arch.hpte_cache_offset++;
 }
 
 /* We keep 512 gvsid->hvsid entries, mapping the guest ones to the array using
  * a hash, so we don't waste cycles on looping */
 static u16 kvmppc_sid_hash(struct kvm_vcpu *vcpu, u64 gvsid)
 {
-        return (u16)(((gvsid >> (SID_MAP_BITS * 7)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 6)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 5)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 4)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 3)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 2)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 1)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 0)) & SID_MAP_MASK));
+        return hash_64(gvsid, SID_MAP_BITS);
 }
 
 
@@ -256,7 +144,6 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
         register int rr = 0;
         bool primary = false;
         bool evict = false;
-        int hpte_id;
         struct hpte_cache *pte;
 
         /* Get host physical address for gpa */
@@ -341,8 +228,7 @@ next_pteg:
 
         /* Now tell our Shadow PTE code about the new page */
 
-        hpte_id = kvmppc_mmu_hpte_cache_next(vcpu);
-        pte = &vcpu->arch.hpte_cache[hpte_id];
+        pte = kvmppc_mmu_hpte_cache_next(vcpu);
 
         dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%llx (0x%llx) -> %lx\n",
                     orig_pte->may_write ? 'w' : '-',
@@ -355,6 +241,8 @@ next_pteg:
         pte->pte = *orig_pte;
         pte->pfn = hpaddr >> PAGE_SHIFT;
 
+        kvmppc_mmu_hpte_cache_map(vcpu, pte);
+
         return 0;
 }
 
@@ -439,7 +327,7 @@ void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu)
 
 void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
 {
-        kvmppc_mmu_pte_flush(vcpu, 0, 0);
+        kvmppc_mmu_hpte_destroy(vcpu);
         preempt_disable();
         __destroy_context(to_book3s(vcpu)->context_id);
         preempt_enable();
@@ -479,5 +367,7 @@ int kvmppc_mmu_init(struct kvm_vcpu *vcpu)
         htabmask = ((sdr1 & 0x1FF) << 16) | 0xFFC0;
         htab = (ulong)__va(sdr1 & 0xffff0000);
 
+        kvmppc_mmu_hpte_init(vcpu);
+
         return 0;
 }
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index e4b5744977f6..384179a5002b 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -20,6 +20,7 @@
  */
 
 #include <linux/kvm_host.h>
+#include <linux/hash.h>
 
 #include <asm/kvm_ppc.h>
 #include <asm/kvm_book3s.h>
@@ -46,135 +47,20 @@
 #define dprintk_slb(a, ...) do { } while(0)
 #endif
 
-static void invalidate_pte(struct hpte_cache *pte)
+void kvmppc_mmu_invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
 {
-        dprintk_mmu("KVM: Flushing SPT: 0x%lx (0x%llx) -> 0x%llx\n",
-                    pte->pte.eaddr, pte->pte.vpage, pte->host_va);
-
         ppc_md.hpte_invalidate(pte->slot, pte->host_va,
                                MMU_PAGE_4K, MMU_SEGSIZE_256M,
                                false);
-        pte->host_va = 0;
-
-        if (pte->pte.may_write)
-                kvm_release_pfn_dirty(pte->pfn);
-        else
-                kvm_release_pfn_clean(pte->pfn);
-}
-
-void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong guest_ea, ulong ea_mask)
-{
-        int i;
-
-        dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%lx & 0x%lx\n",
-                    vcpu->arch.hpte_cache_offset, guest_ea, ea_mask);
-        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
-
-        guest_ea &= ea_mask;
-        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if ((pte->pte.eaddr & ea_mask) == guest_ea) {
-                        invalidate_pte(pte);
-                }
-        }
-
-        /* Doing a complete flush -> start from scratch */
-        if (!ea_mask)
-                vcpu->arch.hpte_cache_offset = 0;
-}
-
-void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask)
-{
-        int i;
-
-        dprintk_mmu("KVM: Flushing %d Shadow vPTEs: 0x%llx & 0x%llx\n",
-                    vcpu->arch.hpte_cache_offset, guest_vp, vp_mask);
-        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
-
-        guest_vp &= vp_mask;
-        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if ((pte->pte.vpage & vp_mask) == guest_vp) {
-                        invalidate_pte(pte);
-                }
-        }
-}
-
-void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end)
-{
-        int i;
-
-        dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%lx & 0x%lx\n",
-                    vcpu->arch.hpte_cache_offset, pa_start, pa_end);
-        BUG_ON(vcpu->arch.hpte_cache_offset > HPTEG_CACHE_NUM);
-
-        for (i = 0; i < vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if ((pte->pte.raddr >= pa_start) &&
-                    (pte->pte.raddr < pa_end)) {
-                        invalidate_pte(pte);
-                }
-        }
-}
-
-struct kvmppc_pte *kvmppc_mmu_find_pte(struct kvm_vcpu *vcpu, u64 ea, bool data)
-{
-        int i;
-        u64 guest_vp;
-
-        guest_vp = vcpu->arch.mmu.ea_to_vp(vcpu, ea, false);
-        for (i=0; i<vcpu->arch.hpte_cache_offset; i++) {
-                struct hpte_cache *pte;
-
-                pte = &vcpu->arch.hpte_cache[i];
-                if (!pte->host_va)
-                        continue;
-
-                if (pte->pte.vpage == guest_vp)
-                        return &pte->pte;
-        }
-
-        return NULL;
-}
-
-static int kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu)
-{
-        if (vcpu->arch.hpte_cache_offset == HPTEG_CACHE_NUM)
-                kvmppc_mmu_pte_flush(vcpu, 0, 0);
-
-        return vcpu->arch.hpte_cache_offset++;
 }
 
 /* We keep 512 gvsid->hvsid entries, mapping the guest ones to the array using
  * a hash, so we don't waste cycles on looping */
 static u16 kvmppc_sid_hash(struct kvm_vcpu *vcpu, u64 gvsid)
 {
-        return (u16)(((gvsid >> (SID_MAP_BITS * 7)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 6)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 5)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 4)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 3)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 2)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 1)) & SID_MAP_MASK) ^
-                     ((gvsid >> (SID_MAP_BITS * 0)) & SID_MAP_MASK));
+        return hash_64(gvsid, SID_MAP_BITS);
 }
 
-
 static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid)
 {
         struct kvmppc_sid_map *map;
@@ -273,8 +159,7 @@ map_again:
                 attempt++;
                 goto map_again;
         } else {
-                int hpte_id = kvmppc_mmu_hpte_cache_next(vcpu);
-                struct hpte_cache *pte = &vcpu->arch.hpte_cache[hpte_id];
+                struct hpte_cache *pte = kvmppc_mmu_hpte_cache_next(vcpu);
 
                 dprintk_mmu("KVM: %c%c Map 0x%lx: [%lx] 0x%lx (0x%llx) -> %lx\n",
                             ((rflags & HPTE_R_PP) == 3) ? '-' : 'w',
@@ -292,6 +177,8 @@ map_again:
                 pte->host_va = va;
                 pte->pte = *orig_pte;
                 pte->pfn = hpaddr >> PAGE_SHIFT;
+
+                kvmppc_mmu_hpte_cache_map(vcpu, pte);
         }
 
         return 0;
@@ -418,7 +305,7 @@ void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu)
 
 void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
 {
-        kvmppc_mmu_pte_flush(vcpu, 0, 0);
+        kvmppc_mmu_hpte_destroy(vcpu);
         __destroy_context(to_book3s(vcpu)->context_id);
 }
 
@@ -436,5 +323,7 @@ int kvmppc_mmu_init(struct kvm_vcpu *vcpu)
         vcpu3s->vsid_first = vcpu3s->context_id << USER_ESID_BITS;
         vcpu3s->vsid_next = vcpu3s->vsid_first;
 
+        kvmppc_mmu_hpte_init(vcpu);
+
         return 0;
 }
diff --git a/arch/powerpc/kvm/book3s_mmu_hpte.c b/arch/powerpc/kvm/book3s_mmu_hpte.c
new file mode 100644
index 000000000000..4868d4a7ebc5
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_mmu_hpte.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2010 SUSE Linux Products GmbH. All rights reserved.
+ *
+ * Authors:
+ *     Alexander Graf <agraf@suse.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kvm_host.h>
+#include <linux/hash.h>
+#include <linux/slab.h>
+
+#include <asm/kvm_ppc.h>
+#include <asm/kvm_book3s.h>
+#include <asm/machdep.h>
+#include <asm/mmu_context.h>
+#include <asm/hw_irq.h>
+
+#define PTE_SIZE        12
+
+/* #define DEBUG_MMU */
+
+#ifdef DEBUG_MMU
+#define dprintk_mmu(a, ...) printk(KERN_INFO a, __VA_ARGS__)
+#else
+#define dprintk_mmu(a, ...) do { } while(0)
+#endif
+
+static struct kmem_cache *hpte_cache;
+
+static inline u64 kvmppc_mmu_hash_pte(u64 eaddr)
+{
+        return hash_64(eaddr >> PTE_SIZE, HPTEG_HASH_BITS_PTE);
+}
+
+static inline u64 kvmppc_mmu_hash_vpte(u64 vpage)
+{
+        return hash_64(vpage & 0xfffffffffULL, HPTEG_HASH_BITS_VPTE);
+}
+
+static inline u64 kvmppc_mmu_hash_vpte_long(u64 vpage)
+{
+        return hash_64((vpage & 0xffffff000ULL) >> 12,
+                       HPTEG_HASH_BITS_VPTE_LONG);
+}
+
+void kvmppc_mmu_hpte_cache_map(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
+{
+        u64 index;
+
+        /* Add to ePTE list */
+        index = kvmppc_mmu_hash_pte(pte->pte.eaddr);
+        hlist_add_head(&pte->list_pte, &vcpu->arch.hpte_hash_pte[index]);
+
+        /* Add to vPTE list */
+        index = kvmppc_mmu_hash_vpte(pte->pte.vpage);
+        hlist_add_head(&pte->list_vpte, &vcpu->arch.hpte_hash_vpte[index]);
+
+        /* Add to vPTE_long list */
+        index = kvmppc_mmu_hash_vpte_long(pte->pte.vpage);
+        hlist_add_head(&pte->list_vpte_long,
+                       &vcpu->arch.hpte_hash_vpte_long[index]);
+}
+
+static void invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
+{
+        dprintk_mmu("KVM: Flushing SPT: 0x%lx (0x%llx) -> 0x%llx\n",
+                    pte->pte.eaddr, pte->pte.vpage, pte->host_va);
+
+        /* Different for 32 and 64 bit */
+        kvmppc_mmu_invalidate_pte(vcpu, pte);
+
+        if (pte->pte.may_write)
+                kvm_release_pfn_dirty(pte->pfn);
+        else
+                kvm_release_pfn_clean(pte->pfn);
+
+        hlist_del(&pte->list_pte);
+        hlist_del(&pte->list_vpte);
+        hlist_del(&pte->list_vpte_long);
+
+        vcpu->arch.hpte_cache_count--;
+        kmem_cache_free(hpte_cache, pte);
+}
+
+static void kvmppc_mmu_pte_flush_all(struct kvm_vcpu *vcpu)
+{
+        struct hpte_cache *pte;
+        struct hlist_node *node, *tmp;
+        int i;
+
+        for (i = 0; i < HPTEG_HASH_NUM_VPTE_LONG; i++) {
+                struct hlist_head *list = &vcpu->arch.hpte_hash_vpte_long[i];
+
+                hlist_for_each_entry_safe(pte, node, tmp, list, list_vpte_long)
+                        invalidate_pte(vcpu, pte);
+        }
+}
+
+static void kvmppc_mmu_pte_flush_page(struct kvm_vcpu *vcpu, ulong guest_ea)
+{
+        struct hlist_head *list;
+        struct hlist_node *node, *tmp;
+        struct hpte_cache *pte;
+
+        /* Find the list of entries in the map */
+        list = &vcpu->arch.hpte_hash_pte[kvmppc_mmu_hash_pte(guest_ea)];
+
+        /* Check the list for matching entries and invalidate */
+        hlist_for_each_entry_safe(pte, node, tmp, list, list_pte)
+                if ((pte->pte.eaddr & ~0xfffUL) == guest_ea)
+                        invalidate_pte(vcpu, pte);
+}
+
+void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong guest_ea, ulong ea_mask)
+{
+        u64 i;
+
+        dprintk_mmu("KVM: Flushing %d Shadow PTEs: 0x%lx & 0x%lx\n",
+                    vcpu->arch.hpte_cache_count, guest_ea, ea_mask);
+
+        guest_ea &= ea_mask;
+
+        switch (ea_mask) {
+        case ~0xfffUL:
+                kvmppc_mmu_pte_flush_page(vcpu, guest_ea);
+                break;
+        case 0x0ffff000:
+                /* 32-bit flush w/o segment, go through all possible segments */
+                for (i = 0; i < 0x100000000ULL; i += 0x10000000ULL)
+                        kvmppc_mmu_pte_flush(vcpu, guest_ea | i, ~0xfffUL);
+                break;
+        case 0:
+                /* Doing a complete flush -> start from scratch */
+                kvmppc_mmu_pte_flush_all(vcpu);
+                break;
+        default:
+                WARN_ON(1);
+                break;
+        }
+}
+
+/* Flush with mask 0xfffffffff */
+static void kvmppc_mmu_pte_vflush_short(struct kvm_vcpu *vcpu, u64 guest_vp)
+{
+        struct hlist_head *list;
+        struct hlist_node *node, *tmp;
+        struct hpte_cache *pte;
+        u64 vp_mask = 0xfffffffffULL;
+
+        list = &vcpu->arch.hpte_hash_vpte[kvmppc_mmu_hash_vpte(guest_vp)];
+
+        /* Check the list for matching entries and invalidate */
+        hlist_for_each_entry_safe(pte, node, tmp, list, list_vpte)
+                if ((pte->pte.vpage & vp_mask) == guest_vp)
+                        invalidate_pte(vcpu, pte);
+}
+
+/* Flush with mask 0xffffff000 */
+static void kvmppc_mmu_pte_vflush_long(struct kvm_vcpu *vcpu, u64 guest_vp)
+{
+        struct hlist_head *list;
+        struct hlist_node *node, *tmp;
+        struct hpte_cache *pte;
+        u64 vp_mask = 0xffffff000ULL;
+
+        list = &vcpu->arch.hpte_hash_vpte_long[
+                kvmppc_mmu_hash_vpte_long(guest_vp)];
+
+        /* Check the list for matching entries and invalidate */
+        hlist_for_each_entry_safe(pte, node, tmp, list, list_vpte_long)
+                if ((pte->pte.vpage & vp_mask) == guest_vp)
+                        invalidate_pte(vcpu, pte);
+}
+
+void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 guest_vp, u64 vp_mask)
+{
+        dprintk_mmu("KVM: Flushing %d Shadow vPTEs: 0x%llx & 0x%llx\n",
+                    vcpu->arch.hpte_cache_count, guest_vp, vp_mask);
+        guest_vp &= vp_mask;
+
+        switch(vp_mask) {
+        case 0xfffffffffULL:
+                kvmppc_mmu_pte_vflush_short(vcpu, guest_vp);
+                break;
+        case 0xffffff000ULL:
+                kvmppc_mmu_pte_vflush_long(vcpu, guest_vp);
+                break;
+        default:
+                WARN_ON(1);
+                return;
+        }
+}
+
+void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end)
+{
+        struct hlist_node *node, *tmp;
+        struct hpte_cache *pte;
+        int i;
+
+        dprintk_mmu("KVM: Flushing %d Shadow pPTEs: 0x%lx - 0x%lx\n",
+                    vcpu->arch.hpte_cache_count, pa_start, pa_end);
+
+        for (i = 0; i < HPTEG_HASH_NUM_VPTE_LONG; i++) {
+                struct hlist_head *list = &vcpu->arch.hpte_hash_vpte_long[i];
+
+                hlist_for_each_entry_safe(pte, node, tmp, list, list_vpte_long)
+                        if ((pte->pte.raddr >= pa_start) &&
+                            (pte->pte.raddr < pa_end))
+                                invalidate_pte(vcpu, pte);
+        }
+}
+
+struct hpte_cache *kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu)
+{
+        struct hpte_cache *pte;
+
+        pte = kmem_cache_zalloc(hpte_cache, GFP_KERNEL);
+        vcpu->arch.hpte_cache_count++;
+
+        if (vcpu->arch.hpte_cache_count == HPTEG_CACHE_NUM)
+                kvmppc_mmu_pte_flush_all(vcpu);
+
+        return pte;
+}
+
+void kvmppc_mmu_hpte_destroy(struct kvm_vcpu *vcpu)
+{
+        kvmppc_mmu_pte_flush(vcpu, 0, 0);
+}
+
+static void kvmppc_mmu_hpte_init_hash(struct hlist_head *hash_list, int len)
+{
+        int i;
+
+        for (i = 0; i < len; i++)
+                INIT_HLIST_HEAD(&hash_list[i]);
+}
+
+int kvmppc_mmu_hpte_init(struct kvm_vcpu *vcpu)
+{
+        /* init hpte lookup hashes */
+        kvmppc_mmu_hpte_init_hash(vcpu->arch.hpte_hash_pte,
+                                  ARRAY_SIZE(vcpu->arch.hpte_hash_pte));
+        kvmppc_mmu_hpte_init_hash(vcpu->arch.hpte_hash_vpte,
+                                  ARRAY_SIZE(vcpu->arch.hpte_hash_vpte));
+        kvmppc_mmu_hpte_init_hash(vcpu->arch.hpte_hash_vpte_long,
+                                  ARRAY_SIZE(vcpu->arch.hpte_hash_vpte_long));
+
+        return 0;
+}
+
+int kvmppc_mmu_hpte_sysinit(void)
+{
+        /* init hpte slab cache */
+        hpte_cache = kmem_cache_create("kvm-spt", sizeof(struct hpte_cache),
+                                       sizeof(struct hpte_cache), 0, NULL);
+
+        return 0;
+}
+
+void kvmppc_mmu_hpte_sysexit(void)
+{
+        kmem_cache_destroy(hpte_cache);
+}
diff --git a/arch/powerpc/kvm/book3s_paired_singles.c b/arch/powerpc/kvm/book3s_paired_singles.c
index a9f66abafcb3..474f2e24050a 100644
--- a/arch/powerpc/kvm/book3s_paired_singles.c
+++ b/arch/powerpc/kvm/book3s_paired_singles.c
@@ -159,10 +159,7 @@
 
 static inline void kvmppc_sync_qpr(struct kvm_vcpu *vcpu, int rt)
 {
-        struct thread_struct t;
-
-        t.fpscr.val = vcpu->arch.fpscr;
-        cvt_df((double*)&vcpu->arch.fpr[rt], (float*)&vcpu->arch.qpr[rt], &t);
+        kvm_cvt_df(&vcpu->arch.fpr[rt], &vcpu->arch.qpr[rt], &vcpu->arch.fpscr);
 }
 
 static void kvmppc_inject_pf(struct kvm_vcpu *vcpu, ulong eaddr, bool is_store)
@@ -183,7 +180,6 @@ static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                    int rs, ulong addr, int ls_type)
 {
         int emulated = EMULATE_FAIL;
-        struct thread_struct t;
         int r;
         char tmp[8];
         int len = sizeof(u32);
@@ -191,8 +187,6 @@ static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
         if (ls_type == FPU_LS_DOUBLE)
                 len = sizeof(u64);
 
-        t.fpscr.val = vcpu->arch.fpscr;
-
         /* read from memory */
         r = kvmppc_ld(vcpu, &addr, len, tmp, true);
         vcpu->arch.paddr_accessed = addr;
@@ -210,7 +204,7 @@ static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
         /* put in registers */
         switch (ls_type) {
         case FPU_LS_SINGLE:
-                cvt_fd((float*)tmp, (double*)&vcpu->arch.fpr[rs], &t);
+                kvm_cvt_fd((u32*)tmp, &vcpu->arch.fpr[rs], &vcpu->arch.fpscr);
                 vcpu->arch.qpr[rs] = *((u32*)tmp);
                 break;
         case FPU_LS_DOUBLE:
@@ -229,17 +223,14 @@ static int kvmppc_emulate_fpr_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                     int rs, ulong addr, int ls_type)
 {
         int emulated = EMULATE_FAIL;
-        struct thread_struct t;
         int r;
         char tmp[8];
         u64 val;
         int len;
 
-        t.fpscr.val = vcpu->arch.fpscr;
-
         switch (ls_type) {
         case FPU_LS_SINGLE:
-                cvt_df((double*)&vcpu->arch.fpr[rs], (float*)tmp, &t);
+                kvm_cvt_df(&vcpu->arch.fpr[rs], (u32*)tmp, &vcpu->arch.fpscr);
                 val = *((u32*)tmp);
                 len = sizeof(u32);
                 break;
@@ -278,13 +269,10 @@ static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                    int rs, ulong addr, bool w, int i)
 {
         int emulated = EMULATE_FAIL;
-        struct thread_struct t;
         int r;
         float one = 1.0;
         u32 tmp[2];
 
-        t.fpscr.val = vcpu->arch.fpscr;
-
         /* read from memory */
         if (w) {
                 r = kvmppc_ld(vcpu, &addr, sizeof(u32), tmp, true);
@@ -308,7 +296,7 @@ static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
         emulated = EMULATE_DONE;
 
         /* put in registers */
-        cvt_fd((float*)&tmp[0], (double*)&vcpu->arch.fpr[rs], &t);
+        kvm_cvt_fd(&tmp[0], &vcpu->arch.fpr[rs], &vcpu->arch.fpscr);
         vcpu->arch.qpr[rs] = tmp[1];
 
         dprintk(KERN_INFO "KVM: PSQ_LD [0x%x, 0x%x] at 0x%lx (%d)\n", tmp[0],
@@ -322,14 +310,11 @@ static int kvmppc_emulate_psq_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                     int rs, ulong addr, bool w, int i)
 {
         int emulated = EMULATE_FAIL;
-        struct thread_struct t;
         int r;
         u32 tmp[2];
         int len = w ? sizeof(u32) : sizeof(u64);
 
-        t.fpscr.val = vcpu->arch.fpscr;
-
-        cvt_df((double*)&vcpu->arch.fpr[rs], (float*)&tmp[0], &t);
+        kvm_cvt_df(&vcpu->arch.fpr[rs], &tmp[0], &vcpu->arch.fpscr);
         tmp[1] = vcpu->arch.qpr[rs];
 
         r = kvmppc_st(vcpu, &addr, len, tmp, true);
@@ -517,7 +502,7 @@ static int get_d_signext(u32 inst)
 static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
                                       int reg_out, int reg_in1, int reg_in2,
                                       int reg_in3, int scalar,
-                                      void (*func)(struct thread_struct *t,
+                                      void (*func)(u64 *fpscr,
                                                  u32 *dst, u32 *src1,
                                                  u32 *src2, u32 *src3))
 {
@@ -526,27 +511,25 @@ static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
         u32 ps0_out;
         u32 ps0_in1, ps0_in2, ps0_in3;
         u32 ps1_in1, ps1_in2, ps1_in3;
-        struct thread_struct t;
-        t.fpscr.val = vcpu->arch.fpscr;
 
         /* RC */
         WARN_ON(rc);
 
         /* PS0 */
-        cvt_df((double*)&fpr[reg_in1], (float*)&ps0_in1, &t);
-        cvt_df((double*)&fpr[reg_in2], (float*)&ps0_in2, &t);
-        cvt_df((double*)&fpr[reg_in3], (float*)&ps0_in3, &t);
+        kvm_cvt_df(&fpr[reg_in1], &ps0_in1, &vcpu->arch.fpscr);
+        kvm_cvt_df(&fpr[reg_in2], &ps0_in2, &vcpu->arch.fpscr);
+        kvm_cvt_df(&fpr[reg_in3], &ps0_in3, &vcpu->arch.fpscr);
 
         if (scalar & SCALAR_LOW)
                 ps0_in2 = qpr[reg_in2];
 
-        func(&t, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3);
+        func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3);
 
         dprintk(KERN_INFO "PS3 ps0 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
                           ps0_in1, ps0_in2, ps0_in3, ps0_out);
 
         if (!(scalar & SCALAR_NO_PS0))
-                cvt_fd((float*)&ps0_out, (double*)&fpr[reg_out], &t);
+                kvm_cvt_fd(&ps0_out, &fpr[reg_out], &vcpu->arch.fpscr);
 
         /* PS1 */
         ps1_in1 = qpr[reg_in1];
@@ -557,7 +540,7 @@ static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
                 ps1_in2 = ps0_in2;
 
         if (!(scalar & SCALAR_NO_PS1))
-                func(&t, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3);
+                func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3);
 
         dprintk(KERN_INFO "PS3 ps1 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
                           ps1_in1, ps1_in2, ps1_in3, qpr[reg_out]);
@@ -568,7 +551,7 @@ static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
 static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
                                     int reg_out, int reg_in1, int reg_in2,
                                     int scalar,
-                                    void (*func)(struct thread_struct *t,
+                                    void (*func)(u64 *fpscr,
                                                  u32 *dst, u32 *src1,
                                                  u32 *src2))
 {
@@ -578,27 +561,25 @@ static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
         u32 ps0_in1, ps0_in2;
         u32 ps1_out;
         u32 ps1_in1, ps1_in2;
-        struct thread_struct t;
-        t.fpscr.val = vcpu->arch.fpscr;
 
         /* RC */
         WARN_ON(rc);
 
         /* PS0 */
-        cvt_df((double*)&fpr[reg_in1], (float*)&ps0_in1, &t);
+        kvm_cvt_df(&fpr[reg_in1], &ps0_in1, &vcpu->arch.fpscr);
 
         if (scalar & SCALAR_LOW)
                 ps0_in2 = qpr[reg_in2];
         else
-                cvt_df((double*)&fpr[reg_in2], (float*)&ps0_in2, &t);
+                kvm_cvt_df(&fpr[reg_in2], &ps0_in2, &vcpu->arch.fpscr);
 
-        func(&t, &ps0_out, &ps0_in1, &ps0_in2);
+        func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2);
 
         if (!(scalar & SCALAR_NO_PS0)) {
                 dprintk(KERN_INFO "PS2 ps0 -> f(0x%x, 0x%x) = 0x%x\n",
                                   ps0_in1, ps0_in2, ps0_out);
 
-                cvt_fd((float*)&ps0_out, (double*)&fpr[reg_out], &t);
+                kvm_cvt_fd(&ps0_out, &fpr[reg_out], &vcpu->arch.fpscr);
         }
 
         /* PS1 */
@@ -608,7 +589,7 @@ static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
         if (scalar & SCALAR_HIGH)
                 ps1_in2 = ps0_in2;
 
-        func(&t, &ps1_out, &ps1_in1, &ps1_in2);
+        func(&vcpu->arch.fpscr, &ps1_out, &ps1_in1, &ps1_in2);
 
         if (!(scalar & SCALAR_NO_PS1)) {
                 qpr[reg_out] = ps1_out;
@@ -622,31 +603,29 @@ static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
 
 static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc,
                                     int reg_out, int reg_in,
-                                    void (*func)(struct thread_struct *t,
+                                    void (*func)(u64 *t,
                                                  u32 *dst, u32 *src1))
 {
         u32 *qpr = vcpu->arch.qpr;
         u64 *fpr = vcpu->arch.fpr;
         u32 ps0_out, ps0_in;
         u32 ps1_in;
-        struct thread_struct t;
-        t.fpscr.val = vcpu->arch.fpscr;
 
         /* RC */
         WARN_ON(rc);
 
         /* PS0 */
-        cvt_df((double*)&fpr[reg_in], (float*)&ps0_in, &t);
-        func(&t, &ps0_out, &ps0_in);
+        kvm_cvt_df(&fpr[reg_in], &ps0_in, &vcpu->arch.fpscr);
+        func(&vcpu->arch.fpscr, &ps0_out, &ps0_in);
 
         dprintk(KERN_INFO "PS1 ps0 -> f(0x%x) = 0x%x\n",
                           ps0_in, ps0_out);
 
-        cvt_fd((float*)&ps0_out, (double*)&fpr[reg_out], &t);
+        kvm_cvt_fd(&ps0_out, &fpr[reg_out], &vcpu->arch.fpscr);
 
         /* PS1 */
         ps1_in = qpr[reg_in];
-        func(&t, &qpr[reg_out], &ps1_in);
+        func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in);
 
         dprintk(KERN_INFO "PS1 ps1 -> f(0x%x) = 0x%x\n",
                           ps1_in, qpr[reg_out]);
@@ -672,13 +651,10 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
 
         bool rcomp = (inst & 1) ? true : false;
         u32 cr = kvmppc_get_cr(vcpu);
-        struct thread_struct t;
 #ifdef DEBUG
         int i;
 #endif
 
-        t.fpscr.val = vcpu->arch.fpscr;
-
         if (!kvmppc_inst_is_paired_single(vcpu, inst))
                 return EMULATE_FAIL;
 
@@ -695,7 +671,7 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
 #ifdef DEBUG
         for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
                 u32 f;
-                cvt_df((double*)&vcpu->arch.fpr[i], (float*)&f, &t);
+                kvm_cvt_df(&vcpu->arch.fpr[i], &f, &vcpu->arch.fpscr);
                 dprintk(KERN_INFO "FPR[%d] = 0x%x / 0x%llx    QPR[%d] = 0x%x\n",
                         i, f, vcpu->arch.fpr[i], i, vcpu->arch.qpr[i]);
         }
@@ -819,8 +795,9 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         WARN_ON(rcomp);
                         vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra];
                         /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
-                        cvt_df((double*)&vcpu->arch.fpr[ax_rb],
-                               (float*)&vcpu->arch.qpr[ax_rd], &t);
+                        kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
+                                   &vcpu->arch.qpr[ax_rd],
+                                   &vcpu->arch.fpscr);
                         break;
                 case OP_4X_PS_MERGE01:
                         WARN_ON(rcomp);
@@ -830,17 +807,20 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 case OP_4X_PS_MERGE10:
                         WARN_ON(rcomp);
                         /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
-                        cvt_fd((float*)&vcpu->arch.qpr[ax_ra],
-                               (double*)&vcpu->arch.fpr[ax_rd], &t);
+                        kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
+                                   &vcpu->arch.fpr[ax_rd],
+                                   &vcpu->arch.fpscr);
                         /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
-                        cvt_df((double*)&vcpu->arch.fpr[ax_rb],
-                               (float*)&vcpu->arch.qpr[ax_rd], &t);
+                        kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
+                                   &vcpu->arch.qpr[ax_rd],
+                                   &vcpu->arch.fpscr);
                         break;
                 case OP_4X_PS_MERGE11:
                         WARN_ON(rcomp);
                         /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
-                        cvt_fd((float*)&vcpu->arch.qpr[ax_ra],
-                               (double*)&vcpu->arch.fpr[ax_rd], &t);
+                        kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
+                                   &vcpu->arch.fpr[ax_rd],
+                                   &vcpu->arch.fpscr);
                         vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
                         break;
                 }
@@ -1275,7 +1255,7 @@ int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
 #ifdef DEBUG
         for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
                 u32 f;
-                cvt_df((double*)&vcpu->arch.fpr[i], (float*)&f, &t);
+                kvm_cvt_df(&vcpu->arch.fpr[i], &f, &vcpu->arch.fpscr);
                 dprintk(KERN_INFO "FPR[%d] = 0x%x\n", i, f);
         }
 #endif
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index a33ab8cc2ccc..8d4e35f5372c 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -144,7 +144,7 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
                                         unsigned int priority)
 {
         int allowed = 0;
-        ulong msr_mask;
+        ulong uninitialized_var(msr_mask);
         bool update_esr = false, update_dear = false;
 
         switch (priority) {
@@ -485,8 +485,6 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
         int i;
 
-        vcpu_load(vcpu);
-
         regs->pc = vcpu->arch.pc;
         regs->cr = kvmppc_get_cr(vcpu);
         regs->ctr = vcpu->arch.ctr;
@@ -507,8 +505,6 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -516,8 +512,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
         int i;
 
-        vcpu_load(vcpu);
-
         vcpu->arch.pc = regs->pc;
         kvmppc_set_cr(vcpu, regs->cr);
         vcpu->arch.ctr = regs->ctr;
@@ -537,8 +531,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
                 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -569,9 +561,7 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
 {
         int r;
 
-        vcpu_load(vcpu);
         r = kvmppc_core_vcpu_translate(vcpu, tr);
-        vcpu_put(vcpu);
         return r;
 }
 
diff --git a/arch/powerpc/kvm/fpu.S b/arch/powerpc/kvm/fpu.S
index 2b340a3eee90..cb34bbe16113 100644
--- a/arch/powerpc/kvm/fpu.S
+++ b/arch/powerpc/kvm/fpu.S
@@ -271,3 +271,21 @@ FPD_THREE_IN(fmsub)
 FPD_THREE_IN(fmadd)
 FPD_THREE_IN(fnmsub)
 FPD_THREE_IN(fnmadd)
+
+_GLOBAL(kvm_cvt_fd)
+        lfd     0,0(r5)                 /* load up fpscr value */
+        MTFSF_L(0)
+        lfs     0,0(r3)
+        stfd    0,0(r4)
+        mffs    0
+        stfd    0,0(r5)                 /* save new fpscr value */
+        blr
+
+_GLOBAL(kvm_cvt_df)
+        lfd     0,0(r5)                 /* load up fpscr value */
+        MTFSF_L(0)
+        lfd     0,0(r3)
+        stfs    0,0(r4)
+        mffs    0
+        stfd    0,0(r5)                 /* save new fpscr value */
+        blr
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 9b8683f39e05..72a4ad86ee91 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -36,11 +36,6 @@
 #define CREATE_TRACE_POINTS
 #include "trace.h"
 
-gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
-{
-        return gfn;
-}
-
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
 {
         return !(v->arch.msr & MSR_WE) || !!(v->arch.pending_exceptions);
@@ -287,7 +282,7 @@ static void kvmppc_complete_dcr_load(struct kvm_vcpu *vcpu,
 static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu,
                                       struct kvm_run *run)
 {
-        u64 gpr;
+        u64 uninitialized_var(gpr);
 
         if (run->mmio.len > sizeof(gpr)) {
                 printk(KERN_ERR "bad MMIO length: %d\n", run->mmio.len);
@@ -423,8 +418,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
         int r;
         sigset_t sigsaved;
 
-        vcpu_load(vcpu);
-
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 
@@ -456,8 +449,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 
-        vcpu_put(vcpu);
-
         return r;
 }
 
@@ -523,8 +514,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 if (copy_from_user(&irq, argp, sizeof(irq)))
                         goto out;
                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
-                break;
+                goto out;
         }
+
         case KVM_ENABLE_CAP:
         {
                 struct kvm_enable_cap cap;
diff --git a/arch/powerpc/kvm/timing.c b/arch/powerpc/kvm/timing.c
index 70378551c0cc..46fa04f12a9b 100644
--- a/arch/powerpc/kvm/timing.c
+++ b/arch/powerpc/kvm/timing.c
@@ -182,7 +182,7 @@ static ssize_t kvmppc_exit_timing_write(struct file *file,
         }
 
         if (c == 'c') {
-                struct seq_file *seqf = (struct seq_file *)file->private_data;
+                struct seq_file *seqf = file->private_data;
                 struct kvm_vcpu *vcpu = seqf->private;
                 /* Write does not affect our buffers previously generated with
                  * show. seq_file is locked here to prevent races of init with
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 111da1c03a11..5bb89c828070 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -18,8 +18,9 @@ obj-$(CONFIG_HAS_IOMEM)	+= devres.o
 
 obj-$(CONFIG_PPC64)     += copypage_64.o copyuser_64.o \
                            memcpy_64.o usercopy_64.o mem_64.o string.o
-obj-$(CONFIG_XMON)      += sstep.o
-obj-$(CONFIG_KPROBES)   += sstep.o
+obj-$(CONFIG_XMON)      += sstep.o ldstfp.o
+obj-$(CONFIG_KPROBES)   += sstep.o ldstfp.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += sstep.o ldstfp.o
 
 ifeq ($(CONFIG_PPC64),y)
 obj-$(CONFIG_SMP)       += locks.o
diff --git a/arch/powerpc/lib/ldstfp.S b/arch/powerpc/lib/ldstfp.S
new file mode 100644
index 000000000000..f6448636baf5
--- /dev/null
+++ b/arch/powerpc/lib/ldstfp.S
@@ -0,0 +1,375 @@
+/*
+ * Floating-point, VMX/Altivec and VSX loads and stores
+ * for use in instruction emulation.
+ *
+ * Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/processor.h>
+#include <asm/ppc_asm.h>
+#include <asm/ppc-opcode.h>
+#include <asm/reg.h>
+#include <asm/asm-offsets.h>
+#include <linux/errno.h>
+
+#define STKFRM  (PPC_MIN_STKFRM + 16)
+
+        .macro  extab   instr,handler
+        .section __ex_table,"a"
+        PPC_LONG \instr,\handler
+        .previous
+        .endm
+
+        .macro  inst32  op
+reg = 0
+        .rept   32
+20:     \op     reg,0,r4
+        b       3f
+        extab   20b,99f
+reg = reg + 1
+        .endr
+        .endm
+
+/* Get the contents of frN into fr0; N is in r3. */
+_GLOBAL(get_fpr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* fr0 is already in fr0 */
+        nop
+reg = 1
+        .rept   31
+        fmr     fr0,reg
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Put the contents of fr0 into frN; N is in r3. */
+_GLOBAL(put_fpr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* fr0 is already in fr0 */
+        nop
+reg = 1
+        .rept   31
+        fmr     reg,fr0
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Load FP reg N from float at *p.  N is in r3, p in r4. */
+_GLOBAL(do_lfs)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+1:      li      r9,-EFAULT
+2:      lfs     fr0,0(r4)
+        li      r9,0
+3:      bl      put_fpr
+        beq     cr7,4f
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Load FP reg N from double at *p.  N is in r3, p in r4. */
+_GLOBAL(do_lfd)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+1:      li      r9,-EFAULT
+2:      lfd     fr0,0(r4)
+        li      r9,0
+3:      beq     cr7,4f
+        bl      put_fpr
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store FP reg N to float at *p.  N is in r3, p in r4. */
+_GLOBAL(do_stfs)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+        bl      get_fpr
+1:      li      r9,-EFAULT
+2:      stfs    fr0,0(r4)
+        li      r9,0
+3:      beq     cr7,4f
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store FP reg N to double at *p.  N is in r3, p in r4. */
+_GLOBAL(do_stfd)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+        bl      get_fpr
+1:      li      r9,-EFAULT
+2:      stfd    fr0,0(r4)
+        li      r9,0
+3:      beq     cr7,4f
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+#ifdef CONFIG_ALTIVEC
+/* Get the contents of vrN into vr0; N is in r3. */
+_GLOBAL(get_vr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* vr0 is already in vr0 */
+        nop
+reg = 1
+        .rept   31
+        vor     vr0,reg,reg     /* assembler doesn't know vmr? */
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Put the contents of vr0 into vrN; N is in r3. */
+_GLOBAL(put_vr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* vr0 is already in vr0 */
+        nop
+reg = 1
+        .rept   31
+        vor     reg,vr0,vr0
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Load vector reg N from *p.  N is in r3, p in r4. */
+_GLOBAL(do_lvx)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VEC@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stvx    vr0,r1,r8
+1:      li      r9,-EFAULT
+2:      lvx     vr0,0,r4
+        li      r9,0
+3:      beq     cr7,4f
+        bl      put_vr
+        lvx     vr0,r1,r8
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store vector reg N to *p.  N is in r3, p in r4. */
+_GLOBAL(do_stvx)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VEC@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stvx    vr0,r1,r8
+        bl      get_vr
+1:      li      r9,-EFAULT
+2:      stvx    vr0,0,r4
+        li      r9,0
+3:      beq     cr7,4f
+        lvx     vr0,r1,r8
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef CONFIG_VSX
+/* Get the contents of vsrN into vsr0; N is in r3. */
+_GLOBAL(get_vsr)
+        mflr    r0
+        rlwinm  r3,r3,3,0x1f8
+        bcl     20,31,1f
+        blr                     /* vsr0 is already in vsr0 */
+        nop
+reg = 1
+        .rept   63
+        XXLOR(0,reg,reg)
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Put the contents of vsr0 into vsrN; N is in r3. */
+_GLOBAL(put_vsr)
+        mflr    r0
+        rlwinm  r3,r3,3,0x1f8
+        bcl     20,31,1f
+        blr                     /* vr0 is already in vr0 */
+        nop
+reg = 1
+        .rept   63
+        XXLOR(reg,0,0)
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Load VSX reg N from vector doubleword *p.  N is in r3, p in r4. */
+_GLOBAL(do_lxvd2x)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VSX@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        STXVD2X(0,r1,r8)
+1:      li      r9,-EFAULT
+2:      LXVD2X(0,0,r4)
+        li      r9,0
+3:      beq     cr7,4f
+        bl      put_vsr
+        LXVD2X(0,r1,r8)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store VSX reg N to vector doubleword *p.  N is in r3, p in r4. */
+_GLOBAL(do_stxvd2x)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VSX@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        STXVD2X(0,r1,r8)
+        bl      get_vsr
+1:      li      r9,-EFAULT
+2:      STXVD2X(0,0,r4)
+        li      r9,0
+3:      beq     cr7,4f
+        LXVD2X(0,r1,r8)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+#endif /* CONFIG_VSX */
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 13b7d54f185b..e0a9858d537e 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -13,6 +13,8 @@
 #include <linux/ptrace.h>
 #include <asm/sstep.h>
 #include <asm/processor.h>
+#include <asm/uaccess.h>
+#include <asm/cputable.h>
 
 extern char system_call_common[];
 
@@ -23,6 +25,23 @@ extern char system_call_common[];
 #define MSR_MASK        0x87c0ffff
 #endif
 
+/* Bits in XER */
+#define XER_SO          0x80000000U
+#define XER_OV          0x40000000U
+#define XER_CA          0x20000000U
+
+/*
+ * Functions in ldstfp.S
+ */
+extern int do_lfs(int rn, unsigned long ea);
+extern int do_lfd(int rn, unsigned long ea);
+extern int do_stfs(int rn, unsigned long ea);
+extern int do_stfd(int rn, unsigned long ea);
+extern int do_lvx(int rn, unsigned long ea);
+extern int do_stvx(int rn, unsigned long ea);
+extern int do_lxvd2x(int rn, unsigned long ea);
+extern int do_stxvd2x(int rn, unsigned long ea);
+
 /*
  * Determine whether a conditional branch instruction would branch.
  */
@@ -46,16 +65,499 @@ static int __kprobes branch_taken(unsigned int instr, struct pt_regs *regs)
         return 1;
 }
 
+
+static long __kprobes address_ok(struct pt_regs *regs, unsigned long ea, int nb)
+{
+        if (!user_mode(regs))
+                return 1;
+        return __access_ok(ea, nb, USER_DS);
+}
+
+/*
+ * Calculate effective address for a D-form instruction
+ */
+static unsigned long __kprobes dform_ea(unsigned int instr, struct pt_regs *regs)
+{
+        int ra;
+        unsigned long ea;
+
+        ra = (instr >> 16) & 0x1f;
+        ea = (signed short) instr;              /* sign-extend */
+        if (ra) {
+                ea += regs->gpr[ra];
+                if (instr & 0x04000000)         /* update forms */
+                        regs->gpr[ra] = ea;
+        }
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF))
+                ea &= 0xffffffffUL;
+#endif
+        return ea;
+}
+
+#ifdef __powerpc64__
+/*
+ * Calculate effective address for a DS-form instruction
+ */
+static unsigned long __kprobes dsform_ea(unsigned int instr, struct pt_regs *regs)
+{
+        int ra;
+        unsigned long ea;
+
+        ra = (instr >> 16) & 0x1f;
+        ea = (signed short) (instr & ~3);       /* sign-extend */
+        if (ra) {
+                ea += regs->gpr[ra];
+                if ((instr & 3) == 1)           /* update forms */
+                        regs->gpr[ra] = ea;
+        }
+        if (!(regs->msr & MSR_SF))
+                ea &= 0xffffffffUL;
+        return ea;
+}
+#endif /* __powerpc64 */
+
+/*
+ * Calculate effective address for an X-form instruction
+ */
+static unsigned long __kprobes xform_ea(unsigned int instr, struct pt_regs *regs,
+                                     int do_update)
+{
+        int ra, rb;
+        unsigned long ea;
+
+        ra = (instr >> 16) & 0x1f;
+        rb = (instr >> 11) & 0x1f;
+        ea = regs->gpr[rb];
+        if (ra) {
+                ea += regs->gpr[ra];
+                if (do_update)          /* update forms */
+                        regs->gpr[ra] = ea;
+        }
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF))
+                ea &= 0xffffffffUL;
+#endif
+        return ea;
+}
+
+/*
+ * Return the largest power of 2, not greater than sizeof(unsigned long),
+ * such that x is a multiple of it.
+ */
+static inline unsigned long max_align(unsigned long x)
+{
+        x |= sizeof(unsigned long);
+        return x & -x;          /* isolates rightmost bit */
+}
+
+
+static inline unsigned long byterev_2(unsigned long x)
+{
+        return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
+}
+
+static inline unsigned long byterev_4(unsigned long x)
+{
+        return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
+                ((x & 0xff00) << 8) | ((x & 0xff) << 24);
+}
+
+#ifdef __powerpc64__
+static inline unsigned long byterev_8(unsigned long x)
+{
+        return (byterev_4(x) << 32) | byterev_4(x >> 32);
+}
+#endif
+
+static int __kprobes read_mem_aligned(unsigned long *dest, unsigned long ea,
+                                      int nb)
+{
+        int err = 0;
+        unsigned long x = 0;
+
+        switch (nb) {
+        case 1:
+                err = __get_user(x, (unsigned char __user *) ea);
+                break;
+        case 2:
+                err = __get_user(x, (unsigned short __user *) ea);
+                break;
+        case 4:
+                err = __get_user(x, (unsigned int __user *) ea);
+                break;
+#ifdef __powerpc64__
+        case 8:
+                err = __get_user(x, (unsigned long __user *) ea);
+                break;
+#endif
+        }
+        if (!err)
+                *dest = x;
+        return err;
+}
+
+static int __kprobes read_mem_unaligned(unsigned long *dest, unsigned long ea,
+                                        int nb, struct pt_regs *regs)
+{
+        int err;
+        unsigned long x, b, c;
+
+        /* unaligned, do this in pieces */
+        x = 0;
+        for (; nb > 0; nb -= c) {
+                c = max_align(ea);
+                if (c > nb)
+                        c = max_align(nb);
+                err = read_mem_aligned(&b, ea, c);
+                if (err)
+                        return err;
+                x = (x << (8 * c)) + b;
+                ea += c;
+        }
+        *dest = x;
+        return 0;
+}
+
+/*
+ * Read memory at address ea for nb bytes, return 0 for success
+ * or -EFAULT if an error occurred.
+ */
+static int __kprobes read_mem(unsigned long *dest, unsigned long ea, int nb,
+                              struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & (nb - 1)) == 0)
+                return read_mem_aligned(dest, ea, nb);
+        return read_mem_unaligned(dest, ea, nb, regs);
+}
+
+static int __kprobes write_mem_aligned(unsigned long val, unsigned long ea,
+                                       int nb)
+{
+        int err = 0;
+
+        switch (nb) {
+        case 1:
+                err = __put_user(val, (unsigned char __user *) ea);
+                break;
+        case 2:
+                err = __put_user(val, (unsigned short __user *) ea);
+                break;
+        case 4:
+                err = __put_user(val, (unsigned int __user *) ea);
+                break;
+#ifdef __powerpc64__
+        case 8:
+                err = __put_user(val, (unsigned long __user *) ea);
+                break;
+#endif
+        }
+        return err;
+}
+
+static int __kprobes write_mem_unaligned(unsigned long val, unsigned long ea,
+                                         int nb, struct pt_regs *regs)
+{
+        int err;
+        unsigned long c;
+
+        /* unaligned or little-endian, do this in pieces */
+        for (; nb > 0; nb -= c) {
+                c = max_align(ea);
+                if (c > nb)
+                        c = max_align(nb);
+                err = write_mem_aligned(val >> (nb - c) * 8, ea, c);
+                if (err)
+                        return err;
+                ++ea;
+        }
+        return 0;
+}
+
+/*
+ * Write memory at address ea for nb bytes, return 0 for success
+ * or -EFAULT if an error occurred.
+ */
+static int __kprobes write_mem(unsigned long val, unsigned long ea, int nb,
+                               struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & (nb - 1)) == 0)
+                return write_mem_aligned(val, ea, nb);
+        return write_mem_unaligned(val, ea, nb, regs);
+}
+
 /*
- * Emulate instructions that cause a transfer of control.
+ * Check the address and alignment, and call func to do the actual
+ * load or store.
+ */
+static int __kprobes do_fp_load(int rn, int (*func)(int, unsigned long),
+                                unsigned long ea, int nb,
+                                struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[sizeof(double) / sizeof(long)];
+        unsigned long ptr;
+
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        ptr = (unsigned long) &val[0];
+        if (sizeof(unsigned long) == 8 || nb == 4) {
+                err = read_mem_unaligned(&val[0], ea, nb, regs);
+                ptr += sizeof(unsigned long) - nb;
+        } else {
+                /* reading a double on 32-bit */
+                err = read_mem_unaligned(&val[0], ea, 4, regs);
+                if (!err)
+                        err = read_mem_unaligned(&val[1], ea + 4, 4, regs);
+        }
+        if (err)
+                return err;
+        return (*func)(rn, ptr);
+}
+
+static int __kprobes do_fp_store(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, int nb,
+                                 struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[sizeof(double) / sizeof(long)];
+        unsigned long ptr;
+
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        ptr = (unsigned long) &val[0];
+        if (sizeof(unsigned long) == 8 || nb == 4) {
+                ptr += sizeof(unsigned long) - nb;
+                err = (*func)(rn, ptr);
+                if (err)
+                        return err;
+                err = write_mem_unaligned(val[0], ea, nb, regs);
+        } else {
+                /* writing a double on 32-bit */
+                err = (*func)(rn, ptr);
+                if (err)
+                        return err;
+                err = write_mem_unaligned(val[0], ea, 4, regs);
+                if (!err)
+                        err = write_mem_unaligned(val[1], ea + 4, 4, regs);
+        }
+        return err;
+}
+
+#ifdef CONFIG_ALTIVEC
+/* For Altivec/VMX, no need to worry about alignment */
+static int __kprobes do_vec_load(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea & ~0xfUL, 16))
+                return -EFAULT;
+        return (*func)(rn, ea);
+}
+
+static int __kprobes do_vec_store(int rn, int (*func)(int, unsigned long),
+                                  unsigned long ea, struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea & ~0xfUL, 16))
+                return -EFAULT;
+        return (*func)(rn, ea);
+}
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef CONFIG_VSX
+static int __kprobes do_vsx_load(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[2];
+
+        if (!address_ok(regs, ea, 16))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        err = read_mem_unaligned(&val[0], ea, 8, regs);
+        if (!err)
+                err = read_mem_unaligned(&val[1], ea + 8, 8, regs);
+        if (!err)
+                err = (*func)(rn, (unsigned long) &val[0]);
+        return err;
+}
+
+static int __kprobes do_vsx_store(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[2];
+
+        if (!address_ok(regs, ea, 16))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        err = (*func)(rn, (unsigned long) &val[0]);
+        if (err)
+                return err;
+        err = write_mem_unaligned(val[0], ea, 8, regs);
+        if (!err)
+                err = write_mem_unaligned(val[1], ea + 8, 8, regs);
+        return err;
+}
+#endif /* CONFIG_VSX */
+
+#define __put_user_asmx(x, addr, err, op, cr)           \
+        __asm__ __volatile__(                           \
+                "1:     " op " %2,0,%3\n"               \
+                "       mfcr    %1\n"                   \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li      %0,%4\n"                \
+                "       b       2b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
+                ".previous"                             \
+                : "=r" (err), "=r" (cr)                 \
+                : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __get_user_asmx(x, addr, err, op)               \
+        __asm__ __volatile__(                           \
+                "1:     "op" %1,0,%2\n"                 \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li      %0,%3\n"                \
+                "       b       2b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
+                ".previous"                             \
+                : "=r" (err), "=r" (x)                  \
+                : "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __cacheop_user_asmx(addr, err, op)              \
+        __asm__ __volatile__(                           \
+                "1:     "op" 0,%1\n"                    \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li      %0,%3\n"                \
+                "       b       2b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
+                ".previous"                             \
+                : "=r" (err)                            \
+                : "r" (addr), "i" (-EFAULT), "0" (err))
+
+static void __kprobes set_cr0(struct pt_regs *regs, int rd)
+{
+        long val = regs->gpr[rd];
+
+        regs->ccr = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF))
+                val = (int) val;
+#endif
+        if (val < 0)
+                regs->ccr |= 0x80000000;
+        else if (val > 0)
+                regs->ccr |= 0x40000000;
+        else
+                regs->ccr |= 0x20000000;
+}
+
+static void __kprobes add_with_carry(struct pt_regs *regs, int rd,
+                                     unsigned long val1, unsigned long val2,
+                                     unsigned long carry_in)
+{
+        unsigned long val = val1 + val2;
+
+        if (carry_in)
+                ++val;
+        regs->gpr[rd] = val;
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF)) {
+                val = (unsigned int) val;
+                val1 = (unsigned int) val1;
+        }
+#endif
+        if (val < val1 || (carry_in && val == val1))
+                regs->xer |= XER_CA;
+        else
+                regs->xer &= ~XER_CA;
+}
+
+static void __kprobes do_cmp_signed(struct pt_regs *regs, long v1, long v2,
+                                    int crfld)
+{
+        unsigned int crval, shift;
+
+        crval = (regs->xer >> 31) & 1;          /* get SO bit */
+        if (v1 < v2)
+                crval |= 8;
+        else if (v1 > v2)
+                crval |= 4;
+        else
+                crval |= 2;
+        shift = (7 - crfld) * 4;
+        regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
+}
+
+static void __kprobes do_cmp_unsigned(struct pt_regs *regs, unsigned long v1,
+                                      unsigned long v2, int crfld)
+{
+        unsigned int crval, shift;
+
+        crval = (regs->xer >> 31) & 1;          /* get SO bit */
+        if (v1 < v2)
+                crval |= 8;
+        else if (v1 > v2)
+                crval |= 4;
+        else
+                crval |= 2;
+        shift = (7 - crfld) * 4;
+        regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
+}
+
+/*
+ * Elements of 32-bit rotate and mask instructions.
+ */
+#define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
+                         ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
+#ifdef __powerpc64__
+#define MASK64_L(mb)    (~0UL >> (mb))
+#define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
+#define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
+#define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
+#else
+#define DATA32(x)       (x)
+#endif
+#define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
+
+/*
+ * Emulate instructions that cause a transfer of control,
+ * loads and stores, and a few other instructions.
  * Returns 1 if the step was emulated, 0 if not,
  * or -1 if the instruction is one that should not be stepped,
  * such as an rfid, or a mtmsrd that would clear MSR_RI.
  */
 int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
 {
-        unsigned int opcode, rs, rb, rd, spr;
+        unsigned int opcode, ra, rb, rd, spr, u;
         unsigned long int imm;
+        unsigned long int val, val2;
+        unsigned long int ea;
+        unsigned int cr, mb, me, sh;
+        int err;
+        unsigned long old_ra;
+        long ival;
 
         opcode = instr >> 26;
         switch (opcode) {
@@ -78,7 +580,13 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                  * entry code works.  If that is changed, this will
                  * need to be changed also.
                  */
+                if (regs->gpr[0] == 0x1ebe &&
+                    cpu_has_feature(CPU_FTR_REAL_LE)) {
+                        regs->msr ^= MSR_LE;
+                        goto instr_done;
+                }
                 regs->gpr[9] = regs->gpr[13];
+                regs->gpr[10] = MSR_KERNEL;
                 regs->gpr[11] = regs->nip + 4;
                 regs->gpr[12] = regs->msr & MSR_MASK;
                 regs->gpr[13] = (unsigned long) get_paca();
@@ -102,9 +610,9 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                 regs->nip = imm;
                 return 1;
         case 19:
-                switch (instr & 0x7fe) {
-                case 0x20:      /* bclr */
-                case 0x420:     /* bcctr */
+                switch ((instr >> 1) & 0x3ff) {
+                case 16:        /* bclr */
+                case 528:       /* bcctr */
                         imm = (instr & 0x400)? regs->ctr: regs->link;
                         regs->nip += 4;
                         if ((regs->msr & MSR_SF) == 0) {
@@ -116,30 +624,233 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                         if (branch_taken(instr, regs))
                                 regs->nip = imm;
                         return 1;
-                case 0x24:      /* rfid, scary */
+
+                case 18:        /* rfid, scary */
                         return -1;
+
+                case 150:       /* isync */
+                        isync();
+                        goto instr_done;
+
+                case 33:        /* crnor */
+                case 129:       /* crandc */
+                case 193:       /* crxor */
+                case 225:       /* crnand */
+                case 257:       /* crand */
+                case 289:       /* creqv */
+                case 417:       /* crorc */
+                case 449:       /* cror */
+                        ra = (instr >> 16) & 0x1f;
+                        rb = (instr >> 11) & 0x1f;
+                        rd = (instr >> 21) & 0x1f;
+                        ra = (regs->ccr >> (31 - ra)) & 1;
+                        rb = (regs->ccr >> (31 - rb)) & 1;
+                        val = (instr >> (6 + ra * 2 + rb)) & 1;
+                        regs->ccr = (regs->ccr & ~(1UL << (31 - rd))) |
+                                (val << (31 - rd));
+                        goto instr_done;
+                }
+                break;
+        case 31:
+                switch ((instr >> 1) & 0x3ff) {
+                case 598:       /* sync */
+#ifdef __powerpc64__
+                        switch ((instr >> 21) & 3) {
+                        case 1:         /* lwsync */
+                                asm volatile("lwsync" : : : "memory");
+                                goto instr_done;
+                        case 2:         /* ptesync */
+                                asm volatile("ptesync" : : : "memory");
+                                goto instr_done;
+                        }
+#endif
+                        mb();
+                        goto instr_done;
+
+                case 854:       /* eieio */
+                        eieio();
+                        goto instr_done;
+                }
+                break;
+        }
+
+        /* Following cases refer to regs->gpr[], so we need all regs */
+        if (!FULL_REGS(regs))
+                return 0;
+
+        rd = (instr >> 21) & 0x1f;
+        ra = (instr >> 16) & 0x1f;
+        rb = (instr >> 11) & 0x1f;
+
+        switch (opcode) {
+        case 7:         /* mulli */
+                regs->gpr[rd] = regs->gpr[ra] * (short) instr;
+                goto instr_done;
+
+        case 8:         /* subfic */
+                imm = (short) instr;
+                add_with_carry(regs, rd, ~regs->gpr[ra], imm, 1);
+                goto instr_done;
+
+        case 10:        /* cmpli */
+                imm = (unsigned short) instr;
+                val = regs->gpr[ra];
+#ifdef __powerpc64__
+                if ((rd & 1) == 0)
+                        val = (unsigned int) val;
+#endif
+                do_cmp_unsigned(regs, val, imm, rd >> 2);
+                goto instr_done;
+
+        case 11:        /* cmpi */
+                imm = (short) instr;
+                val = regs->gpr[ra];
+#ifdef __powerpc64__
+                if ((rd & 1) == 0)
+                        val = (int) val;
+#endif
+                do_cmp_signed(regs, val, imm, rd >> 2);
+                goto instr_done;
+
+        case 12:        /* addic */
+                imm = (short) instr;
+                add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
+                goto instr_done;
+
+        case 13:        /* addic. */
+                imm = (short) instr;
+                add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
+                set_cr0(regs, rd);
+                goto instr_done;
+
+        case 14:        /* addi */
+                imm = (short) instr;
+                if (ra)
+                        imm += regs->gpr[ra];
+                regs->gpr[rd] = imm;
+                goto instr_done;
+
+        case 15:        /* addis */
+                imm = ((short) instr) << 16;
+                if (ra)
+                        imm += regs->gpr[ra];
+                regs->gpr[rd] = imm;
+                goto instr_done;
+
+        case 20:        /* rlwimi */
+                mb = (instr >> 6) & 0x1f;
+                me = (instr >> 1) & 0x1f;
+                val = DATA32(regs->gpr[rd]);
+                imm = MASK32(mb, me);
+                regs->gpr[ra] = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
+                goto logical_done;
+
+        case 21:        /* rlwinm */
+                mb = (instr >> 6) & 0x1f;
+                me = (instr >> 1) & 0x1f;
+                val = DATA32(regs->gpr[rd]);
+                regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
+                goto logical_done;
+
+        case 23:        /* rlwnm */
+                mb = (instr >> 6) & 0x1f;
+                me = (instr >> 1) & 0x1f;
+                rb = regs->gpr[rb] & 0x1f;
+                val = DATA32(regs->gpr[rd]);
+                regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
+                goto logical_done;
+
+        case 24:        /* ori */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] | imm;
+                goto instr_done;
+
+        case 25:        /* oris */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] | (imm << 16);
+                goto instr_done;
+
+        case 26:        /* xori */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] ^ imm;
+                goto instr_done;
+
+        case 27:        /* xoris */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] ^ (imm << 16);
+                goto instr_done;
+
+        case 28:        /* andi. */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] & imm;
+                set_cr0(regs, ra);
+                goto instr_done;
+
+        case 29:        /* andis. */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] & (imm << 16);
+                set_cr0(regs, ra);
+                goto instr_done;
+
+#ifdef __powerpc64__
+        case 30:        /* rld* */
+                mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
+                val = regs->gpr[rd];
+                if ((instr & 0x10) == 0) {
+                        sh = rb | ((instr & 2) << 4);
+                        val = ROTATE(val, sh);
+                        switch ((instr >> 2) & 3) {
+                        case 0:         /* rldicl */
+                                regs->gpr[ra] = val & MASK64_L(mb);
+                                goto logical_done;
+                        case 1:         /* rldicr */
+                                regs->gpr[ra] = val & MASK64_R(mb);
+                                goto logical_done;
+                        case 2:         /* rldic */
+                                regs->gpr[ra] = val & MASK64(mb, 63 - sh);
+                                goto logical_done;
+                        case 3:         /* rldimi */
+                                imm = MASK64(mb, 63 - sh);
+                                regs->gpr[ra] = (regs->gpr[ra] & ~imm) |
+                                        (val & imm);
+                                goto logical_done;
+                        }
+                } else {
+                        sh = regs->gpr[rb] & 0x3f;
+                        val = ROTATE(val, sh);
+                        switch ((instr >> 1) & 7) {
+                        case 0:         /* rldcl */
+                                regs->gpr[ra] = val & MASK64_L(mb);
+                                goto logical_done;
+                        case 1:         /* rldcr */
+                                regs->gpr[ra] = val & MASK64_R(mb);
+                                goto logical_done;
+                        }
                 }
+#endif
+
         case 31:
-                rd = (instr >> 21) & 0x1f;
-                switch (instr & 0x7fe) {
-                case 0xa6:      /* mfmsr */
+                switch ((instr >> 1) & 0x3ff) {
+                case 83:        /* mfmsr */
+                        if (regs->msr & MSR_PR)
+                                break;
                         regs->gpr[rd] = regs->msr & MSR_MASK;
-                        regs->nip += 4;
-                        if ((regs->msr & MSR_SF) == 0)
-                                regs->nip &= 0xffffffffUL;
-                        return 1;
-                case 0x124:     /* mtmsr */
+                        goto instr_done;
+                case 146:       /* mtmsr */
+                        if (regs->msr & MSR_PR)
+                                break;
                         imm = regs->gpr[rd];
                         if ((imm & MSR_RI) == 0)
                                 /* can't step mtmsr that would clear MSR_RI */
                                 return -1;
                         regs->msr = imm;
-                        regs->nip += 4;
-                        return 1;
+                        goto instr_done;
 #ifdef CONFIG_PPC64
-                case 0x164:     /* mtmsrd */
+                case 178:       /* mtmsrd */
                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
                         /* mtmsrd doesn't change MSR_HV and MSR_ME */
+                        if (regs->msr & MSR_PR)
+                                break;
                         imm = (instr & 0x10000)? 0x8002: 0xefffffffffffefffUL;
                         imm = (regs->msr & MSR_MASK & ~imm)
                                 | (regs->gpr[rd] & imm);
@@ -147,57 +858,770 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                                 /* can't step mtmsrd that would clear MSR_RI */
                                 return -1;
                         regs->msr = imm;
-                        regs->nip += 4;
-                        if ((imm & MSR_SF) == 0)
-                                regs->nip &= 0xffffffffUL;
-                        return 1;
+                        goto instr_done;
 #endif
-                case 0x26:      /* mfcr */
+                case 19:        /* mfcr */
                         regs->gpr[rd] = regs->ccr;
                         regs->gpr[rd] &= 0xffffffffUL;
-                        goto mtspr_out;
-                case 0x2a6:     /* mfspr */
+                        goto instr_done;
+
+                case 144:       /* mtcrf */
+                        imm = 0xf0000000UL;
+                        val = regs->gpr[rd];
+                        for (sh = 0; sh < 8; ++sh) {
+                                if (instr & (0x80000 >> sh))
+                                        regs->ccr = (regs->ccr & ~imm) |
+                                                (val & imm);
+                                imm >>= 4;
+                        }
+                        goto instr_done;
+
+                case 339:       /* mfspr */
                         spr = (instr >> 11) & 0x3ff;
                         switch (spr) {
                         case 0x20:      /* mfxer */
                                 regs->gpr[rd] = regs->xer;
                                 regs->gpr[rd] &= 0xffffffffUL;
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x100:     /* mflr */
                                 regs->gpr[rd] = regs->link;
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x120:     /* mfctr */
                                 regs->gpr[rd] = regs->ctr;
-                                goto mtspr_out;
-                        }
-                        break;
-                case 0x378:     /* orx */
-                        if (instr & 1)
-                                break;
-                        rs = (instr >> 21) & 0x1f;
-                        rb = (instr >> 11) & 0x1f;
-                        if (rs == rb) {         /* mr */
-                                rd = (instr >> 16) & 0x1f;
-                                regs->gpr[rd] = regs->gpr[rs];
-                                goto mtspr_out;
+                                goto instr_done;
                         }
                         break;
-                case 0x3a6:     /* mtspr */
+
+                case 467:       /* mtspr */
                         spr = (instr >> 11) & 0x3ff;
                         switch (spr) {
                         case 0x20:      /* mtxer */
                                 regs->xer = (regs->gpr[rd] & 0xffffffffUL);
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x100:     /* mtlr */
                                 regs->link = regs->gpr[rd];
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x120:     /* mtctr */
                                 regs->ctr = regs->gpr[rd];
-mtspr_out:
-                                regs->nip += 4;
-                                return 1;
+                                goto instr_done;
                         }
+                        break;
+
+/*
+ * Compare instructions
+ */
+                case 0: /* cmp */
+                        val = regs->gpr[ra];
+                        val2 = regs->gpr[rb];
+#ifdef __powerpc64__
+                        if ((rd & 1) == 0) {
+                                /* word (32-bit) compare */
+                                val = (int) val;
+                                val2 = (int) val2;
+                        }
+#endif
+                        do_cmp_signed(regs, val, val2, rd >> 2);
+                        goto instr_done;
+
+                case 32:        /* cmpl */
+                        val = regs->gpr[ra];
+                        val2 = regs->gpr[rb];
+#ifdef __powerpc64__
+                        if ((rd & 1) == 0) {
+                                /* word (32-bit) compare */
+                                val = (unsigned int) val;
+                                val2 = (unsigned int) val2;
+                        }
+#endif
+                        do_cmp_unsigned(regs, val, val2, rd >> 2);
+                        goto instr_done;
+
+/*
+ * Arithmetic instructions
+ */
+                case 8: /* subfc */
+                        add_with_carry(regs, rd, ~regs->gpr[ra],
+                                       regs->gpr[rb], 1);
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 9: /* mulhdu */
+                        asm("mulhdu %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+#endif
+                case 10:        /* addc */
+                        add_with_carry(regs, rd, regs->gpr[ra],
+                                       regs->gpr[rb], 0);
+                        goto arith_done;
+
+                case 11:        /* mulhwu */
+                        asm("mulhwu %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+
+                case 40:        /* subf */
+                        regs->gpr[rd] = regs->gpr[rb] - regs->gpr[ra];
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 73:        /* mulhd */
+                        asm("mulhd %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+#endif
+                case 75:        /* mulhw */
+                        asm("mulhw %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+
+                case 104:       /* neg */
+                        regs->gpr[rd] = -regs->gpr[ra];
+                        goto arith_done;
+
+                case 136:       /* subfe */
+                        add_with_carry(regs, rd, ~regs->gpr[ra], regs->gpr[rb],
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 138:       /* adde */
+                        add_with_carry(regs, rd, regs->gpr[ra], regs->gpr[rb],
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 200:       /* subfze */
+                        add_with_carry(regs, rd, ~regs->gpr[ra], 0L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 202:       /* addze */
+                        add_with_carry(regs, rd, regs->gpr[ra], 0L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 232:       /* subfme */
+                        add_with_carry(regs, rd, ~regs->gpr[ra], -1L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 233:       /* mulld */
+                        regs->gpr[rd] = regs->gpr[ra] * regs->gpr[rb];
+                        goto arith_done;
+#endif
+                case 234:       /* addme */
+                        add_with_carry(regs, rd, regs->gpr[ra], -1L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 235:       /* mullw */
+                        regs->gpr[rd] = (unsigned int) regs->gpr[ra] *
+                                (unsigned int) regs->gpr[rb];
+                        goto arith_done;
+
+                case 266:       /* add */
+                        regs->gpr[rd] = regs->gpr[ra] + regs->gpr[rb];
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 457:       /* divdu */
+                        regs->gpr[rd] = regs->gpr[ra] / regs->gpr[rb];
+                        goto arith_done;
+#endif
+                case 459:       /* divwu */
+                        regs->gpr[rd] = (unsigned int) regs->gpr[ra] /
+                                (unsigned int) regs->gpr[rb];
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 489:       /* divd */
+                        regs->gpr[rd] = (long int) regs->gpr[ra] /
+                                (long int) regs->gpr[rb];
+                        goto arith_done;
+#endif
+                case 491:       /* divw */
+                        regs->gpr[rd] = (int) regs->gpr[ra] /
+                                (int) regs->gpr[rb];
+                        goto arith_done;
+
+
+/*
+ * Logical instructions
+ */
+                case 26:        /* cntlzw */
+                        asm("cntlzw %0,%1" : "=r" (regs->gpr[ra]) :
+                            "r" (regs->gpr[rd]));
+                        goto logical_done;
+#ifdef __powerpc64__
+                case 58:        /* cntlzd */
+                        asm("cntlzd %0,%1" : "=r" (regs->gpr[ra]) :
+                            "r" (regs->gpr[rd]));
+                        goto logical_done;
+#endif
+                case 28:        /* and */
+                        regs->gpr[ra] = regs->gpr[rd] & regs->gpr[rb];
+                        goto logical_done;
+
+                case 60:        /* andc */
+                        regs->gpr[ra] = regs->gpr[rd] & ~regs->gpr[rb];
+                        goto logical_done;
+
+                case 124:       /* nor */
+                        regs->gpr[ra] = ~(regs->gpr[rd] | regs->gpr[rb]);
+                        goto logical_done;
+
+                case 284:       /* xor */
+                        regs->gpr[ra] = ~(regs->gpr[rd] ^ regs->gpr[rb]);
+                        goto logical_done;
+
+                case 316:       /* xor */
+                        regs->gpr[ra] = regs->gpr[rd] ^ regs->gpr[rb];
+                        goto logical_done;
+
+                case 412:       /* orc */
+                        regs->gpr[ra] = regs->gpr[rd] | ~regs->gpr[rb];
+                        goto logical_done;
+
+                case 444:       /* or */
+                        regs->gpr[ra] = regs->gpr[rd] | regs->gpr[rb];
+                        goto logical_done;
+
+                case 476:       /* nand */
+                        regs->gpr[ra] = ~(regs->gpr[rd] & regs->gpr[rb]);
+                        goto logical_done;
+
+                case 922:       /* extsh */
+                        regs->gpr[ra] = (signed short) regs->gpr[rd];
+                        goto logical_done;
+
+                case 954:       /* extsb */
+                        regs->gpr[ra] = (signed char) regs->gpr[rd];
+                        goto logical_done;
+#ifdef __powerpc64__
+                case 986:       /* extsw */
+                        regs->gpr[ra] = (signed int) regs->gpr[rd];
+                        goto logical_done;
+#endif
+
+/*
+ * Shift instructions
+ */
+                case 24:        /* slw */
+                        sh = regs->gpr[rb] & 0x3f;
+                        if (sh < 32)
+                                regs->gpr[ra] = (regs->gpr[rd] << sh) & 0xffffffffUL;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 536:       /* srw */
+                        sh = regs->gpr[rb] & 0x3f;
+                        if (sh < 32)
+                                regs->gpr[ra] = (regs->gpr[rd] & 0xffffffffUL) >> sh;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 792:       /* sraw */
+                        sh = regs->gpr[rb] & 0x3f;
+                        ival = (signed int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> (sh < 32 ? sh : 31);
+                        if (ival < 0 && (sh >= 32 || (ival & ((1 << sh) - 1)) != 0))
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+
+                case 824:       /* srawi */
+                        sh = rb;
+                        ival = (signed int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> sh;
+                        if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+
+#ifdef __powerpc64__
+                case 27:        /* sld */
+                        sh = regs->gpr[rd] & 0x7f;
+                        if (sh < 64)
+                                regs->gpr[ra] = regs->gpr[rd] << sh;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 539:       /* srd */
+                        sh = regs->gpr[rb] & 0x7f;
+                        if (sh < 64)
+                                regs->gpr[ra] = regs->gpr[rd] >> sh;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 794:       /* srad */
+                        sh = regs->gpr[rb] & 0x7f;
+                        ival = (signed long int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> (sh < 64 ? sh : 63);
+                        if (ival < 0 && (sh >= 64 || (ival & ((1 << sh) - 1)) != 0))
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+
+                case 826:       /* sradi with sh_5 = 0 */
+                case 827:       /* sradi with sh_5 = 1 */
+                        sh = rb | ((instr & 2) << 4);
+                        ival = (signed long int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> sh;
+                        if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+#endif /* __powerpc64__ */
+
+/*
+ * Cache instructions
+ */
+                case 54:        /* dcbst */
+                        ea = xform_ea(instr, regs, 0);
+                        if (!address_ok(regs, ea, 8))
+                                return 0;
+                        err = 0;
+                        __cacheop_user_asmx(ea, err, "dcbst");
+                        if (err)
+                                return 0;
+                        goto instr_done;
+
+                case 86:        /* dcbf */
+                        ea = xform_ea(instr, regs, 0);
+                        if (!address_ok(regs, ea, 8))
+                                return 0;
+                        err = 0;
+                        __cacheop_user_asmx(ea, err, "dcbf");
+                        if (err)
+                                return 0;
+                        goto instr_done;
+
+                case 246:       /* dcbtst */
+                        if (rd == 0) {
+                                ea = xform_ea(instr, regs, 0);
+                                prefetchw((void *) ea);
+                        }
+                        goto instr_done;
+
+                case 278:       /* dcbt */
+                        if (rd == 0) {
+                                ea = xform_ea(instr, regs, 0);
+                                prefetch((void *) ea);
+                        }
+                        goto instr_done;
+
                 }
+                break;
         }
-        return 0;
+
+        /*
+         * Following cases are for loads and stores, so bail out
+         * if we're in little-endian mode.
+         */
+        if (regs->msr & MSR_LE)
+                return 0;
+
+        /*
+         * Save register RA in case it's an update form load or store
+         * and the access faults.
+         */
+        old_ra = regs->gpr[ra];
+
+        switch (opcode) {
+        case 31:
+                u = instr & 0x40;
+                switch ((instr >> 1) & 0x3ff) {
+                case 20:        /* lwarx */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 3)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 4))
+                                goto ldst_done;
+                        err = 0;
+                        __get_user_asmx(val, ea, err, "lwarx");
+                        if (!err)
+                                regs->gpr[rd] = val;
+                        goto ldst_done;
+
+                case 150:       /* stwcx. */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 3)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 4))
+                                goto ldst_done;
+                        err = 0;
+                        __put_user_asmx(regs->gpr[rd], ea, err, "stwcx.", cr);
+                        if (!err)
+                                regs->ccr = (regs->ccr & 0x0fffffff) |
+                                        (cr & 0xe0000000) |
+                                        ((regs->xer >> 3) & 0x10000000);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 84:        /* ldarx */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 7)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 8))
+                                goto ldst_done;
+                        err = 0;
+                        __get_user_asmx(val, ea, err, "ldarx");
+                        if (!err)
+                                regs->gpr[rd] = val;
+                        goto ldst_done;
+
+                case 214:       /* stdcx. */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 7)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 8))
+                                goto ldst_done;
+                        err = 0;
+                        __put_user_asmx(regs->gpr[rd], ea, err, "stdcx.", cr);
+                        if (!err)
+                                regs->ccr = (regs->ccr & 0x0fffffff) |
+                                        (cr & 0xe0000000) |
+                                        ((regs->xer >> 3) & 0x10000000);
+                        goto ldst_done;
+
+                case 21:        /* ldx */
+                case 53:        /* ldux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       8, regs);
+                        goto ldst_done;
+#endif
+
+                case 23:        /* lwzx */
+                case 55:        /* lwzux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       4, regs);
+                        goto ldst_done;
+
+                case 87:        /* lbzx */
+                case 119:       /* lbzux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       1, regs);
+                        goto ldst_done;
+
+#ifdef CONFIG_ALTIVEC
+                case 103:       /* lvx */
+                case 359:       /* lvxl */
+                        if (!(regs->msr & MSR_VEC))
+                                break;
+                        ea = xform_ea(instr, regs, 0);
+                        err = do_vec_load(rd, do_lvx, ea, regs);
+                        goto ldst_done;
+
+                case 231:       /* stvx */
+                case 487:       /* stvxl */
+                        if (!(regs->msr & MSR_VEC))
+                                break;
+                        ea = xform_ea(instr, regs, 0);
+                        err = do_vec_store(rd, do_stvx, ea, regs);
+                        goto ldst_done;
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef __powerpc64__
+                case 149:       /* stdx */
+                case 181:       /* stdux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 8, regs);
+                        goto ldst_done;
+#endif
+
+                case 151:       /* stwx */
+                case 183:       /* stwux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 4, regs);
+                        goto ldst_done;
+
+                case 215:       /* stbx */
+                case 247:       /* stbux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 1, regs);
+                        goto ldst_done;
+
+                case 279:       /* lhzx */
+                case 311:       /* lhzux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       2, regs);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 341:       /* lwax */
+                case 373:       /* lwaux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       4, regs);
+                        if (!err)
+                                regs->gpr[rd] = (signed int) regs->gpr[rd];
+                        goto ldst_done;
+#endif
+
+                case 343:       /* lhax */
+                case 375:       /* lhaux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       2, regs);
+                        if (!err)
+                                regs->gpr[rd] = (signed short) regs->gpr[rd];
+                        goto ldst_done;
+
+                case 407:       /* sthx */
+                case 439:       /* sthux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 2, regs);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 532:       /* ldbrx */
+                        err = read_mem(&val, xform_ea(instr, regs, 0), 8, regs);
+                        if (!err)
+                                regs->gpr[rd] = byterev_8(val);
+                        goto ldst_done;
+
+#endif
+
+                case 534:       /* lwbrx */
+                        err = read_mem(&val, xform_ea(instr, regs, 0), 4, regs);
+                        if (!err)
+                                regs->gpr[rd] = byterev_4(val);
+                        goto ldst_done;
+
+                case 535:       /* lfsx */
+                case 567:       /* lfsux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_load(rd, do_lfs, ea, 4, regs);
+                        goto ldst_done;
+
+                case 599:       /* lfdx */
+                case 631:       /* lfdux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_load(rd, do_lfd, ea, 8, regs);
+                        goto ldst_done;
+
+                case 663:       /* stfsx */
+                case 695:       /* stfsux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_store(rd, do_stfs, ea, 4, regs);
+                        goto ldst_done;
+
+                case 727:       /* stfdx */
+                case 759:       /* stfdux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_store(rd, do_stfd, ea, 8, regs);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 660:       /* stdbrx */
+                        val = byterev_8(regs->gpr[rd]);
+                        err = write_mem(val, xform_ea(instr, regs, 0), 8, regs);
+                        goto ldst_done;
+
+#endif
+                case 662:       /* stwbrx */
+                        val = byterev_4(regs->gpr[rd]);
+                        err = write_mem(val, xform_ea(instr, regs, 0), 4, regs);
+                        goto ldst_done;
+
+                case 790:       /* lhbrx */
+                        err = read_mem(&val, xform_ea(instr, regs, 0), 2, regs);
+                        if (!err)
+                                regs->gpr[rd] = byterev_2(val);
+                        goto ldst_done;
+
+                case 918:       /* sthbrx */
+                        val = byterev_2(regs->gpr[rd]);
+                        err = write_mem(val, xform_ea(instr, regs, 0), 2, regs);
+                        goto ldst_done;
+
+#ifdef CONFIG_VSX
+                case 844:       /* lxvd2x */
+                case 876:       /* lxvd2ux */
+                        if (!(regs->msr & MSR_VSX))
+                                break;
+                        rd |= (instr & 1) << 5;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_vsx_load(rd, do_lxvd2x, ea, regs);
+                        goto ldst_done;
+
+                case 972:       /* stxvd2x */
+                case 1004:      /* stxvd2ux */
+                        if (!(regs->msr & MSR_VSX))
+                                break;
+                        rd |= (instr & 1) << 5;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_vsx_store(rd, do_stxvd2x, ea, regs);
+                        goto ldst_done;
+
+#endif /* CONFIG_VSX */
+                }
+                break;
+
+        case 32:        /* lwz */
+        case 33:        /* lwzu */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 4, regs);
+                goto ldst_done;
+
+        case 34:        /* lbz */
+        case 35:        /* lbzu */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 1, regs);
+                goto ldst_done;
+
+        case 36:        /* stw */
+        case 37:        /* stwu */
+                val = regs->gpr[rd];
+                err = write_mem(val, dform_ea(instr, regs), 4, regs);
+                goto ldst_done;
+
+        case 38:        /* stb */
+        case 39:        /* stbu */
+                val = regs->gpr[rd];
+                err = write_mem(val, dform_ea(instr, regs), 1, regs);
+                goto ldst_done;
+
+        case 40:        /* lhz */
+        case 41:        /* lhzu */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 2, regs);
+                goto ldst_done;
+
+        case 42:        /* lha */
+        case 43:        /* lhau */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 2, regs);
+                if (!err)
+                        regs->gpr[rd] = (signed short) regs->gpr[rd];
+                goto ldst_done;
+
+        case 44:        /* sth */
+        case 45:        /* sthu */
+                val = regs->gpr[rd];
+                err = write_mem(val, dform_ea(instr, regs), 2, regs);
+                goto ldst_done;
+
+        case 46:        /* lmw */
+                ra = (instr >> 16) & 0x1f;
+                if (ra >= rd)
+                        break;          /* invalid form, ra in range to load */
+                ea = dform_ea(instr, regs);
+                do {
+                        err = read_mem(&regs->gpr[rd], ea, 4, regs);
+                        if (err)
+                                return 0;
+                        ea += 4;
+                } while (++rd < 32);
+                goto instr_done;
+
+        case 47:        /* stmw */
+                ea = dform_ea(instr, regs);
+                do {
+                        err = write_mem(regs->gpr[rd], ea, 4, regs);
+                        if (err)
+                                return 0;
+                        ea += 4;
+                } while (++rd < 32);
+                goto instr_done;
+
+        case 48:        /* lfs */
+        case 49:        /* lfsu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_load(rd, do_lfs, ea, 4, regs);
+                goto ldst_done;
+
+        case 50:        /* lfd */
+        case 51:        /* lfdu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_load(rd, do_lfd, ea, 8, regs);
+                goto ldst_done;
+
+        case 52:        /* stfs */
+        case 53:        /* stfsu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_store(rd, do_stfs, ea, 4, regs);
+                goto ldst_done;
+
+        case 54:        /* stfd */
+        case 55:        /* stfdu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_store(rd, do_stfd, ea, 8, regs);
+                goto ldst_done;
+
+#ifdef __powerpc64__
+        case 58:        /* ld[u], lwa */
+                switch (instr & 3) {
+                case 0:         /* ld */
+                        err = read_mem(&regs->gpr[rd], dsform_ea(instr, regs),
+                                       8, regs);
+                        goto ldst_done;
+                case 1:         /* ldu */
+                        err = read_mem(&regs->gpr[rd], dsform_ea(instr, regs),
+                                       8, regs);
+                        goto ldst_done;
+                case 2:         /* lwa */
+                        err = read_mem(&regs->gpr[rd], dsform_ea(instr, regs),
+                                       4, regs);
+                        if (!err)
+                                regs->gpr[rd] = (signed int) regs->gpr[rd];
+                        goto ldst_done;
+                }
+                break;
+
+        case 62:        /* std[u] */
+                val = regs->gpr[rd];
+                switch (instr & 3) {
+                case 0:         /* std */
+                        err = write_mem(val, dsform_ea(instr, regs), 8, regs);
+                        goto ldst_done;
+                case 1:         /* stdu */
+                        err = write_mem(val, dsform_ea(instr, regs), 8, regs);
+                        goto ldst_done;
+                }
+                break;
+#endif /* __powerpc64__ */
+
+        }
+        err = -EINVAL;
+
+ ldst_done:
+        if (err) {
+                regs->gpr[ra] = old_ra;
+                return 0;       /* invoke DSI if -EFAULT? */
+        }
+ instr_done:
+        regs->nip += 4;
+#ifdef __powerpc64__
+        if ((regs->msr & MSR_SF) == 0)
+                regs->nip &= 0xffffffffUL;
+#endif
+        return 1;
+
+ logical_done:
+        if (instr & 1)
+                set_cr0(regs, ra);
+        goto instr_done;
+
+ arith_done:
+        if (instr & 1)
+                set_cr0(regs, rd);
+        goto instr_done;
 }
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index cdc7526e9c93..4b66a1ece6d8 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -104,9 +104,10 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
 }
 
 /*
- * Set up one of the I/D BAT (block address translation) register pairs.
- * The parameters are not checked; in particular size must be a power
- * of 4 between 4k and 256M.
+ * Set up a variable-size TLB entry (tlbcam). The parameters are not checked;
+ * in particular size must be a power of 4 between 4k and 256M (or 1G, for cpus
+ * that support extended page sizes).  Note that while some cpus support a
+ * page size of 4G, we don't allow its use here.
  */
 static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
                 unsigned long size, unsigned long flags, unsigned int pid)
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index aa731af720c0..002878ccf90b 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -42,6 +42,12 @@ EXPORT_SYMBOL(node_data);
 
 static int min_common_depth;
 static int n_mem_addr_cells, n_mem_size_cells;
+static int form1_affinity;
+
+#define MAX_DISTANCE_REF_POINTS 4
+static int distance_ref_points_depth;
+static const unsigned int *distance_ref_points;
+static int distance_lookup_table[MAX_NUMNODES][MAX_DISTANCE_REF_POINTS];
 
 /*
  * Allocate node_to_cpumask_map based on number of available nodes
@@ -204,6 +210,39 @@ static const u32 *of_get_usable_memory(struct device_node *memory)
         return prop;
 }
 
+int __node_distance(int a, int b)
+{
+        int i;
+        int distance = LOCAL_DISTANCE;
+
+        if (!form1_affinity)
+                return distance;
+
+        for (i = 0; i < distance_ref_points_depth; i++) {
+                if (distance_lookup_table[a][i] == distance_lookup_table[b][i])
+                        break;
+
+                /* Double the distance for each NUMA level */
+                distance *= 2;
+        }
+
+        return distance;
+}
+
+static void initialize_distance_lookup_table(int nid,
+                const unsigned int *associativity)
+{
+        int i;
+
+        if (!form1_affinity)
+                return;
+
+        for (i = 0; i < distance_ref_points_depth; i++) {
+                distance_lookup_table[nid][i] =
+                        associativity[distance_ref_points[i]];
+        }
+}
+
 /* Returns nid in the range [0..MAX_NUMNODES-1], or -1 if no useful numa
  * info is found.
  */
@@ -225,6 +264,10 @@ static int of_node_to_nid_single(struct device_node *device)
         /* POWER4 LPAR uses 0xffff as invalid node */
         if (nid == 0xffff || nid >= MAX_NUMNODES)
                 nid = -1;
+
+        if (nid > 0 && tmp[0] >= distance_ref_points_depth)
+                initialize_distance_lookup_table(nid, tmp);
+
 out:
         return nid;
 }
@@ -251,26 +294,10 @@ int of_node_to_nid(struct device_node *device)
 }
 EXPORT_SYMBOL_GPL(of_node_to_nid);
 
-/*
- * In theory, the "ibm,associativity" property may contain multiple
- * associativity lists because a resource may be multiply connected
- * into the machine.  This resource then has different associativity
- * characteristics relative to its multiple connections.  We ignore
- * this for now.  We also assume that all cpu and memory sets have
- * their distances represented at a common level.  This won't be
- * true for hierarchical NUMA.
- *
- * In any case the ibm,associativity-reference-points should give
- * the correct depth for a normal NUMA system.
- *
- * - Dave Hansen <haveblue@us.ibm.com>
- */
 static int __init find_min_common_depth(void)
 {
-        int depth, index;
-        const unsigned int *ref_points;
+        int depth;
         struct device_node *rtas_root;
-        unsigned int len;
         struct device_node *chosen;
         const char *vec5;
 
@@ -280,18 +307,28 @@ static int __init find_min_common_depth(void)
                 return -1;
 
         /*
-         * this property is 2 32-bit integers, each representing a level of
-         * depth in the associativity nodes.  The first is for an SMP
-         * configuration (should be all 0's) and the second is for a normal
-         * NUMA configuration.
+         * This property is a set of 32-bit integers, each representing
+         * an index into the ibm,associativity nodes.
+         *
+         * With form 0 affinity the first integer is for an SMP configuration
+         * (should be all 0's) and the second is for a normal NUMA
+         * configuration. We have only one level of NUMA.
+         *
+         * With form 1 affinity the first integer is the most significant
+         * NUMA boundary and the following are progressively less significant
+         * boundaries. There can be more than one level of NUMA.
          */
-        index = 1;
-        ref_points = of_get_property(rtas_root,
-                        "ibm,associativity-reference-points", &len);
+        distance_ref_points = of_get_property(rtas_root,
+                                        "ibm,associativity-reference-points",
+                                        &distance_ref_points_depth);
+
+        if (!distance_ref_points) {
+                dbg("NUMA: ibm,associativity-reference-points not found.\n");
+                goto err;
+        }
+
+        distance_ref_points_depth /= sizeof(int);
 
-        /*
-         * For form 1 affinity information we want the first field
-         */
 #define VEC5_AFFINITY_BYTE      5
 #define VEC5_AFFINITY           0x80
         chosen = of_find_node_by_path("/chosen");
@@ -299,19 +336,38 @@ static int __init find_min_common_depth(void)
                 vec5 = of_get_property(chosen, "ibm,architecture-vec-5", NULL);
                 if (vec5 && (vec5[VEC5_AFFINITY_BYTE] & VEC5_AFFINITY)) {
                         dbg("Using form 1 affinity\n");
-                        index = 0;
+                        form1_affinity = 1;
                 }
         }
 
-        if ((len >= 2 * sizeof(unsigned int)) && ref_points) {
-                depth = ref_points[index];
+        if (form1_affinity) {
+                depth = distance_ref_points[0];
         } else {
-                dbg("NUMA: ibm,associativity-reference-points not found.\n");
-                depth = -1;
+                if (distance_ref_points_depth < 2) {
+                        printk(KERN_WARNING "NUMA: "
+                                "short ibm,associativity-reference-points\n");
+                        goto err;
+                }
+
+                depth = distance_ref_points[1];
         }
-        of_node_put(rtas_root);
 
+        /*
+         * Warn and cap if the hardware supports more than
+         * MAX_DISTANCE_REF_POINTS domains.
+         */
+        if (distance_ref_points_depth > MAX_DISTANCE_REF_POINTS) {
+                printk(KERN_WARNING "NUMA: distance array capped at "
+                        "%d entries\n", MAX_DISTANCE_REF_POINTS);
+                distance_ref_points_depth = MAX_DISTANCE_REF_POINTS;
+        }
+
+        of_node_put(rtas_root);
         return depth;
+
+err:
+        of_node_put(rtas_root);
+        return -1;
 }
 
 static void __init get_n_mem_cells(int *n_addr_cells, int *n_size_cells)
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index ebc2f38eb381..2c7e801ab20b 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -92,7 +92,6 @@ static void pte_free_rcu_callback(struct rcu_head *head)
 
 static void pte_free_submit(struct pte_freelist_batch *batch)
 {
-        INIT_RCU_HEAD(&batch->rcu);
         call_rcu(&batch->rcu, pte_free_rcu_callback);
 }
 
diff --git a/arch/powerpc/mm/tlb_hash32.c b/arch/powerpc/mm/tlb_hash32.c
index 8aaa8b7eb324..690566b66e8e 100644
--- a/arch/powerpc/mm/tlb_hash32.c
+++ b/arch/powerpc/mm/tlb_hash32.c
@@ -89,17 +89,6 @@ void tlb_flush(struct mmu_gather *tlb)
  *    -- Cort
  */
 
-/*
- * 750 SMP is a Bad Idea because the 750 doesn't broadcast all
- * the cache operations on the bus.  Hence we need to use an IPI
- * to get the other CPU(s) to invalidate their TLBs.
- */
-#ifdef CONFIG_SMP_750
-#define FINISH_FLUSH    smp_send_tlb_invalidate(0)
-#else
-#define FINISH_FLUSH    do { } while (0)
-#endif
-
 static void flush_range(struct mm_struct *mm, unsigned long start,
                         unsigned long end)
 {
@@ -138,7 +127,6 @@ static void flush_range(struct mm_struct *mm, unsigned long start,
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 {
         flush_range(&init_mm, start, end);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_kernel_range);
 
@@ -162,7 +150,6 @@ void flush_tlb_mm(struct mm_struct *mm)
          */
         for (mp = mm->mmap; mp != NULL; mp = mp->vm_next)
                 flush_range(mp->vm_mm, mp->vm_start, mp->vm_end);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_mm);
 
@@ -179,7 +166,6 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
         pmd = pmd_offset(pud_offset(pgd_offset(mm, vmaddr), vmaddr), vmaddr);
         if (!pmd_none(*pmd))
                 flush_hash_pages(mm->context.id, vmaddr, pmd_val(*pmd), 1);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_page);
 
@@ -192,6 +178,5 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                      unsigned long end)
 {
         flush_range(vma->vm_mm, start, end);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_range);
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index d8695b02a968..fe391e942521 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -46,6 +46,7 @@
 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
         [MMU_PAGE_4K] = {
                 .shift  = 12,
+                .ind    = 20,
                 .enc    = BOOK3E_PAGESZ_4K,
         },
         [MMU_PAGE_16K] = {
@@ -54,6 +55,7 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
         },
         [MMU_PAGE_64K] = {
                 .shift  = 16,
+                .ind    = 28,
                 .enc    = BOOK3E_PAGESZ_64K,
         },
         [MMU_PAGE_1M] = {
@@ -62,6 +64,7 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
         },
         [MMU_PAGE_16M] = {
                 .shift  = 24,
+                .ind    = 36,
                 .enc    = BOOK3E_PAGESZ_16M,
         },
         [MMU_PAGE_256M] = {
@@ -344,16 +347,108 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
         }
 }
 
-/*
- * Early initialization of the MMU TLB code
- */
-static void __early_init_mmu(int boot_cpu)
+static void setup_page_sizes(void)
+{
+        unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+        unsigned int tlb0ps = mfspr(SPRN_TLB0PS);
+        unsigned int eptcfg = mfspr(SPRN_EPTCFG);
+        int i, psize;
+
+        /* Look for supported direct sizes */
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+                struct mmu_psize_def *def = &mmu_psize_defs[psize];
+
+                if (tlb0ps & (1U << (def->shift - 10)))
+                        def->flags |= MMU_PAGE_SIZE_DIRECT;
+        }
+
+        /* Indirect page sizes supported ? */
+        if ((tlb0cfg & TLBnCFG_IND) == 0)
+                goto no_indirect;
+
+        /* Now, we only deal with one IND page size for each
+         * direct size. Hopefully all implementations today are
+         * unambiguous, but we might want to be careful in the
+         * future.
+         */
+        for (i = 0; i < 3; i++) {
+                unsigned int ps, sps;
+
+                sps = eptcfg & 0x1f;
+                eptcfg >>= 5;
+                ps = eptcfg & 0x1f;
+                eptcfg >>= 5;
+                if (!ps || !sps)
+                        continue;
+                for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
+                        struct mmu_psize_def *def = &mmu_psize_defs[psize];
+
+                        if (ps == (def->shift - 10))
+                                def->flags |= MMU_PAGE_SIZE_INDIRECT;
+                        if (sps == (def->shift - 10))
+                                def->ind = ps + 10;
+                }
+        }
+ no_indirect:
+
+        /* Cleanup array and print summary */
+        pr_info("MMU: Supported page sizes\n");
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+                struct mmu_psize_def *def = &mmu_psize_defs[psize];
+                const char *__page_type_names[] = {
+                        "unsupported",
+                        "direct",
+                        "indirect",
+                        "direct & indirect"
+                };
+                if (def->flags == 0) {
+                        def->shift = 0; 
+                        continue;
+                }
+                pr_info("  %8ld KB as %s\n", 1ul << (def->shift - 10),
+                        __page_type_names[def->flags & 0x3]);
+        }
+}
+
+static void setup_mmu_htw(void)
 {
         extern unsigned int interrupt_base_book3e;
         extern unsigned int exc_data_tlb_miss_htw_book3e;
         extern unsigned int exc_instruction_tlb_miss_htw_book3e;
 
         unsigned int *ibase = &interrupt_base_book3e;
+
+        /* Check if HW tablewalk is present, and if yes, enable it by:
+         *
+         * - patching the TLB miss handlers to branch to the
+         *   one dedicates to it
+         *
+         * - setting the global book3e_htw_enabled
+         */
+        unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+
+        if ((tlb0cfg & TLBnCFG_IND) &&
+            (tlb0cfg & TLBnCFG_PT)) {
+                /* Our exceptions vectors start with a NOP and -then- a branch
+                 * to deal with single stepping from userspace which stops on
+                 * the second instruction. Thus we need to patch the second
+                 * instruction of the exception, not the first one
+                 */
+                patch_branch(ibase + (0x1c0 / 4) + 1,
+                             (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
+                patch_branch(ibase + (0x1e0 / 4) + 1,
+                             (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
+                book3e_htw_enabled = 1;
+        }
+        pr_info("MMU: Book3E Page Tables %s\n",
+                book3e_htw_enabled ? "Enabled" : "Disabled");
+}
+
+/*
+ * Early initialization of the MMU TLB code
+ */
+static void __early_init_mmu(int boot_cpu)
+{
         unsigned int mas4;
 
         /* XXX This will have to be decided at runtime, but right
@@ -370,35 +465,17 @@ static void __early_init_mmu(int boot_cpu)
          */
         mmu_vmemmap_psize = MMU_PAGE_16M;
 
-        /* Check if HW tablewalk is present, and if yes, enable it by:
-         *
-         * - patching the TLB miss handlers to branch to the
-         *   one dedicates to it
-         *
-         * - setting the global book3e_htw_enabled
-         *
-         * - Set MAS4:INDD and default page size
-         */
-
         /* XXX This code only checks for TLB 0 capabilities and doesn't
          *     check what page size combos are supported by the HW. It
          *     also doesn't handle the case where a separate array holds
          *     the IND entries from the array loaded by the PT.
          */
         if (boot_cpu) {
-                unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+                /* Look for supported page sizes */
+                setup_page_sizes();
 
-                /* Check if HW loader is supported */
-                if ((tlb0cfg & TLBnCFG_IND) &&
-                    (tlb0cfg & TLBnCFG_PT)) {
-                        patch_branch(ibase + (0x1c0 / 4),
-                             (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
-                        patch_branch(ibase + (0x1e0 / 4),
-                             (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
-                        book3e_htw_enabled = 1;
-                }
-                pr_info("MMU: Book3E Page Tables %s\n",
-                        book3e_htw_enabled ? "Enabled" : "Disabled");
+                /* Look for HW tablewalk support */
+                setup_mmu_htw();
         }
 
         /* Set MAS4 based on page table setting */
diff --git a/arch/powerpc/oprofile/Makefile b/arch/powerpc/oprofile/Makefile
index 73e1c2ca0552..e219ca43962d 100644
--- a/arch/powerpc/oprofile/Makefile
+++ b/arch/powerpc/oprofile/Makefile
@@ -16,6 +16,6 @@ oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
 oprofile-$(CONFIG_OPROFILE_CELL) += op_model_cell.o \
                 cell/spu_profiler.o cell/vma_map.o \
                 cell/spu_task_sync.o
-oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
+oprofile-$(CONFIG_PPC_BOOK3S_64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
 oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o
 oprofile-$(CONFIG_6xx) += op_model_7450.o
diff --git a/arch/powerpc/oprofile/common.c b/arch/powerpc/oprofile/common.c
index 21f16edf6c8d..d65e68f3cb25 100644
--- a/arch/powerpc/oprofile/common.c
+++ b/arch/powerpc/oprofile/common.c
@@ -199,7 +199,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
                 return -ENODEV;
 
         switch (cur_cpu_spec->oprofile_type) {
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 #ifdef CONFIG_OPROFILE_CELL
                 case PPC_OPROFILE_CELL:
                         if (firmware_has_feature(FW_FEATURE_LPAR))
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index ec64264f7a50..b72176434ebe 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -71,22 +71,6 @@ config MAKALU
         help
           This option enables support for the AMCC PPC405EX board.
 
-#config REDWOOD_5
-#       bool "Redwood-5"
-#       depends on 40x
-#       default n
-#       select STB03xxx
-#       help
-#         This option enables support for the IBM STB04 evaluation board.
-
-#config REDWOOD_6
-#       bool "Redwood-6"
-#       depends on 40x
-#       default n
-#       select STB03xxx
-#       help
-#         This option enables support for the IBM STBx25xx evaluation board.
-
 #config SYCAMORE
 #       bool "Sycamore"
 #       depends on 40x
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index 4dac9b0525a4..27b0651221d1 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,32 +1,34 @@
 config PPC_MPC512x
-        bool
+        bool "512x-based boards"
+        depends on 6xx
         select FSL_SOC
         select IPIC
         select PPC_CLOCK
         select PPC_PCI_CHOICE
         select FSL_PCI if PCI
 
-config PPC_MPC5121
-        bool
-        select PPC_MPC512x
-
 config MPC5121_ADS
         bool "Freescale MPC5121E ADS"
-        depends on 6xx
+        depends on PPC_MPC512x
         select DEFAULT_UIMAGE
-        select PPC_MPC5121
         select MPC5121_ADS_CPLD
         help
           This option enables support for the MPC5121E ADS board.
 
 config MPC5121_GENERIC
         bool "Generic support for simple MPC5121 based boards"
-        depends on 6xx
+        depends on PPC_MPC512x
         select DEFAULT_UIMAGE
-        select PPC_MPC5121
         help
           This option enables support for simple MPC5121 based boards
           which do not need custom platform specific setup.
 
           Compatible boards include:  Protonic LVT base boards (ZANMCU
           and VICVT2).
+
+config PDM360NG
+        bool "ifm PDM360NG board"
+        depends on PPC_MPC512x
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the PDM360NG board.
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 90be2f5717e6..4efc1c4b6fb5 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -4,3 +4,4 @@
 obj-y                           += clock.o mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)       += mpc5121_ads.o mpc5121_ads_cpld.o
 obj-$(CONFIG_MPC5121_GENERIC)   += mpc5121_generic.o
+obj-$(CONFIG_PDM360NG)          += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 4c42246b86a7..5b243bd3eb3b 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -292,6 +292,15 @@ static void diu_clk_calc(struct clk *clk)
         clk->rate = rate;
 }
 
+static void viu_clk_calc(struct clk *clk)
+{
+        unsigned long rate;
+
+        rate = sys_clk.rate;
+        rate /= 2;
+        clk->rate = rate;
+}
+
 static void half_clk_calc(struct clk *clk)
 {
         clk->rate = clk->parent->rate / 2;
@@ -412,6 +421,14 @@ static struct clk diu_clk = {
         .calc = diu_clk_calc,
 };
 
+static struct clk viu_clk = {
+        .name = "viu_clk",
+        .flags = CLK_HAS_CTRL,
+        .reg = 1,
+        .bit = 18,
+        .calc = viu_clk_calc,
+};
+
 static struct clk axe_clk = {
         .name = "axe_clk",
         .flags = CLK_HAS_CTRL,
@@ -535,6 +552,7 @@ struct clk *rate_clks[] = {
         &ref_clk,
         &sys_clk,
         &diu_clk,
+        &viu_clk,
         &csb_clk,
         &e300_clk,
         &ips_clk,
@@ -660,7 +678,7 @@ static void psc_clks_init(void)
 {
         struct device_node *np;
         const u32 *cell_index;
-        struct of_device *ofdev;
+        struct platform_device *ofdev;
 
         for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
                 cell_index = of_get_property(np, "cell-index", NULL);
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c
index ee6ae129c25c..dcef6ade48e1 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
@@ -42,6 +42,7 @@ static void __init mpc5121_ads_setup_arch(void)
         for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
                 mpc83xx_add_bridge(np);
 #endif
+        mpc512x_setup_diu();
 }
 
 static void __init mpc5121_ads_init_IRQ(void)
@@ -65,6 +66,7 @@ define_machine(mpc5121_ads) {
         .probe                  = mpc5121_ads_probe,
         .setup_arch             = mpc5121_ads_setup_arch,
         .init                   = mpc512x_init,
+        .init_early             = mpc512x_init_diu,
         .init_IRQ               = mpc5121_ads_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/512x/mpc5121_generic.c b/arch/powerpc/platforms/512x/mpc5121_generic.c
index a6c0e3a2615d..e487eb06ec6b 100644
--- a/arch/powerpc/platforms/512x/mpc5121_generic.c
+++ b/arch/powerpc/platforms/512x/mpc5121_generic.c
@@ -52,6 +52,8 @@ define_machine(mpc5121_generic) {
         .name                   = "MPC5121 generic",
         .probe                  = mpc5121_generic_probe,
         .init                   = mpc512x_init,
+        .init_early             = mpc512x_init_diu,
+        .setup_arch             = mpc512x_setup_diu,
         .init_IRQ               = mpc512x_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index b2daca0d1488..1ab6d11d0b19 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -16,4 +16,6 @@ extern void __init mpc512x_init(void);
 extern int __init mpc5121_clk_init(void);
 void __init mpc512x_declare_of_platform_devices(void);
 extern void mpc512x_restart(char *cmd);
+extern void mpc512x_init_diu(void);
+extern void mpc512x_setup_diu(void);
 #endif                          /* __MPC512X_H__ */
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 707e572b7c40..e41ebbdb3e12 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -16,7 +16,11 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/of_platform.h>
+#include <linux/fsl-diu-fb.h>
+#include <linux/bootmem.h>
+#include <sysdev/fsl_soc.h>
 
+#include <asm/cacheflush.h>
 #include <asm/machdep.h>
 #include <asm/ipic.h>
 #include <asm/prom.h>
@@ -54,6 +58,286 @@ void mpc512x_restart(char *cmd)
                 ;
 }
 
+struct fsl_diu_shared_fb {
+        u8              gamma[0x300];   /* 32-bit aligned! */
+        struct diu_ad   ad0;            /* 32-bit aligned! */
+        phys_addr_t     fb_phys;
+        size_t          fb_len;
+        bool            in_use;
+};
+
+unsigned int mpc512x_get_pixel_format(unsigned int bits_per_pixel,
+                                      int monitor_port)
+{
+        switch (bits_per_pixel) {
+        case 32:
+                return 0x88883316;
+        case 24:
+                return 0x88082219;
+        case 16:
+                return 0x65053118;
+        }
+        return 0x00000400;
+}
+
+void mpc512x_set_gamma_table(int monitor_port, char *gamma_table_base)
+{
+}
+
+void mpc512x_set_monitor_port(int monitor_port)
+{
+}
+
+#define DIU_DIV_MASK    0x000000ff
+void mpc512x_set_pixel_clock(unsigned int pixclock)
+{
+        unsigned long bestval, bestfreq, speed, busfreq;
+        unsigned long minpixclock, maxpixclock, pixval;
+        struct mpc512x_ccm __iomem *ccm;
+        struct device_node *np;
+        u32 temp;
+        long err;
+        int i;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+        if (!np) {
+                pr_err("Can't find clock control module.\n");
+                return;
+        }
+
+        ccm = of_iomap(np, 0);
+        of_node_put(np);
+        if (!ccm) {
+                pr_err("Can't map clock control module reg.\n");
+                return;
+        }
+
+        np = of_find_node_by_type(NULL, "cpu");
+        if (np) {
+                const unsigned int *prop =
+                        of_get_property(np, "bus-frequency", NULL);
+
+                of_node_put(np);
+                if (prop) {
+                        busfreq = *prop;
+                } else {
+                        pr_err("Can't get bus-frequency property\n");
+                        return;
+                }
+        } else {
+                pr_err("Can't find 'cpu' node.\n");
+                return;
+        }
+
+        /* Pixel Clock configuration */
+        pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
+        speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
+
+        /* Calculate the pixel clock with the smallest error */
+        /* calculate the following in steps to avoid overflow */
+        pr_debug("DIU pixclock in ps - %d\n", pixclock);
+        temp = (1000000000 / pixclock) * 1000;
+        pixclock = temp;
+        pr_debug("DIU pixclock freq - %u\n", pixclock);
+
+        temp = temp / 20; /* pixclock * 0.05 */
+        pr_debug("deviation = %d\n", temp);
+        minpixclock = pixclock - temp;
+        maxpixclock = pixclock + temp;
+        pr_debug("DIU minpixclock - %lu\n", minpixclock);
+        pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+        pixval = speed/pixclock;
+        pr_debug("DIU pixval = %lu\n", pixval);
+
+        err = LONG_MAX;
+        bestval = pixval;
+        pr_debug("DIU bestval = %lu\n", bestval);
+
+        bestfreq = 0;
+        for (i = -1; i <= 1; i++) {
+                temp = speed / (pixval+i);
+                pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
+                        i, pixval, temp);
+                if ((temp < minpixclock) || (temp > maxpixclock))
+                        pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
+                                minpixclock, maxpixclock);
+                else if (abs(temp - pixclock) < err) {
+                        pr_debug("Entered the else if block %d\n", i);
+                        err = abs(temp - pixclock);
+                        bestval = pixval + i;
+                        bestfreq = temp;
+                }
+        }
+
+        pr_debug("DIU chose = %lx\n", bestval);
+        pr_debug("DIU error = %ld\n NomPixClk ", err);
+        pr_debug("DIU: Best Freq = %lx\n", bestfreq);
+        /* Modify DIU_DIV in CCM SCFR1 */
+        temp = in_be32(&ccm->scfr1);
+        pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
+        temp &= ~DIU_DIV_MASK;
+        temp |= (bestval & DIU_DIV_MASK);
+        out_be32(&ccm->scfr1, temp);
+        pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
+        iounmap(ccm);
+}
+
+ssize_t mpc512x_show_monitor_port(int monitor_port, char *buf)
+{
+        return sprintf(buf, "0 - 5121 LCD\n");
+}
+
+int mpc512x_set_sysfs_monitor_port(int val)
+{
+        return 0;
+}
+
+static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
+
+#if defined(CONFIG_FB_FSL_DIU) || \
+    defined(CONFIG_FB_FSL_DIU_MODULE)
+static inline void mpc512x_free_bootmem(struct page *page)
+{
+        __ClearPageReserved(page);
+        BUG_ON(PageTail(page));
+        BUG_ON(atomic_read(&page->_count) > 1);
+        atomic_set(&page->_count, 1);
+        __free_page(page);
+        totalram_pages++;
+}
+
+void mpc512x_release_bootmem(void)
+{
+        unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK;
+        unsigned long size = diu_shared_fb.fb_len;
+        unsigned long start, end;
+
+        if (diu_shared_fb.in_use) {
+                start = PFN_UP(addr);
+                end = PFN_DOWN(addr + size);
+
+                for (; start < end; start++)
+                        mpc512x_free_bootmem(pfn_to_page(start));
+
+                diu_shared_fb.in_use = false;
+        }
+        diu_ops.release_bootmem = NULL;
+}
+#endif
+
+/*
+ * Check if DIU was pre-initialized. If so, perform steps
+ * needed to continue displaying through the whole boot process.
+ * Move area descriptor and gamma table elsewhere, they are
+ * destroyed by bootmem allocator otherwise. The frame buffer
+ * address range will be reserved in setup_arch() after bootmem
+ * allocator is up.
+ */
+void __init mpc512x_init_diu(void)
+{
+        struct device_node *np;
+        struct diu __iomem *diu_reg;
+        phys_addr_t desc;
+        void __iomem *vaddr;
+        unsigned long mode, pix_fmt, res, bpp;
+        unsigned long dst;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
+        if (!np) {
+                pr_err("No DIU node\n");
+                return;
+        }
+
+        diu_reg = of_iomap(np, 0);
+        of_node_put(np);
+        if (!diu_reg) {
+                pr_err("Can't map DIU\n");
+                return;
+        }
+
+        mode = in_be32(&diu_reg->diu_mode);
+        if (mode != MFB_MODE1) {
+                pr_info("%s: DIU OFF\n", __func__);
+                goto out;
+        }
+
+        desc = in_be32(&diu_reg->desc[0]);
+        vaddr = ioremap(desc, sizeof(struct diu_ad));
+        if (!vaddr) {
+                pr_err("Can't map DIU area desc.\n");
+                goto out;
+        }
+        memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad));
+        /* flush fb area descriptor */
+        dst = (unsigned long)&diu_shared_fb.ad0;
+        flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1);
+
+        res = in_be32(&diu_reg->disp_size);
+        pix_fmt = in_le32(vaddr);
+        bpp = ((pix_fmt >> 16) & 0x3) + 1;
+        diu_shared_fb.fb_phys = in_le32(vaddr + 4);
+        diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp;
+        diu_shared_fb.in_use = true;
+        iounmap(vaddr);
+
+        desc = in_be32(&diu_reg->gamma);
+        vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma));
+        if (!vaddr) {
+                pr_err("Can't map DIU area desc.\n");
+                diu_shared_fb.in_use = false;
+                goto out;
+        }
+        memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma));
+        /* flush gamma table */
+        dst = (unsigned long)&diu_shared_fb.gamma;
+        flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1);
+
+        iounmap(vaddr);
+        out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma));
+        out_be32(&diu_reg->desc[1], 0);
+        out_be32(&diu_reg->desc[2], 0);
+        out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0));
+
+out:
+        iounmap(diu_reg);
+}
+
+void __init mpc512x_setup_diu(void)
+{
+        int ret;
+
+        /*
+         * We do not allocate and configure new area for bitmap buffer
+         * because it would requere copying bitmap data (splash image)
+         * and so negatively affect boot time. Instead we reserve the
+         * already configured frame buffer area so that it won't be
+         * destroyed. The starting address of the area to reserve and
+         * also it's length is passed to reserve_bootmem(). It will be
+         * freed later on first open of fbdev, when splash image is not
+         * needed any more.
+         */
+        if (diu_shared_fb.in_use) {
+                ret = reserve_bootmem(diu_shared_fb.fb_phys,
+                                      diu_shared_fb.fb_len,
+                                      BOOTMEM_EXCLUSIVE);
+                if (ret) {
+                        pr_err("%s: reserve bootmem failed\n", __func__);
+                        diu_shared_fb.in_use = false;
+                }
+        }
+
+#if defined(CONFIG_FB_FSL_DIU) || \
+    defined(CONFIG_FB_FSL_DIU_MODULE)
+        diu_ops.get_pixel_format        = mpc512x_get_pixel_format;
+        diu_ops.set_gamma_table         = mpc512x_set_gamma_table;
+        diu_ops.set_monitor_port        = mpc512x_set_monitor_port;
+        diu_ops.set_pixel_clock         = mpc512x_set_pixel_clock;
+        diu_ops.show_monitor_port       = mpc512x_show_monitor_port;
+        diu_ops.set_sysfs_monitor_port  = mpc512x_set_sysfs_monitor_port;
+        diu_ops.release_bootmem         = mpc512x_release_bootmem;
+#endif
+}
+
 void __init mpc512x_init_IRQ(void)
 {
         struct device_node *np;
diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c
new file mode 100644
index 000000000000..0575e858291c
--- /dev/null
+++ b/arch/powerpc/platforms/512x/pdm360ng.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2010 DENX Software Engineering
+ *
+ * Anatolij Gustschin, <agust@denx.de>
+ *
+ * PDM360NG board setup
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+
+#include "mpc512x.h"
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
+    defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+#include <linux/interrupt.h>
+#include <linux/spi/ads7846.h>
+#include <linux/spi/spi.h>
+#include <linux/notifier.h>
+
+static void *pdm360ng_gpio_base;
+
+static int pdm360ng_get_pendown_state(void)
+{
+        u32 reg;
+
+        reg = in_be32(pdm360ng_gpio_base + 0xc);
+        if (reg & 0x40)
+                setbits32(pdm360ng_gpio_base + 0xc, 0x40);
+
+        reg = in_be32(pdm360ng_gpio_base + 0x8);
+
+        /* return 1 if pen is down */
+        return (reg & 0x40) == 0;
+}
+
+static struct ads7846_platform_data pdm360ng_ads7846_pdata = {
+        .model                  = 7845,
+        .get_pendown_state      = pdm360ng_get_pendown_state,
+        .irq_flags              = IRQF_TRIGGER_LOW,
+};
+
+static int __init pdm360ng_penirq_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-gpio");
+        if (!np) {
+                pr_err("%s: Can't find 'mpc5121-gpio' node\n", __func__);
+                return -ENODEV;
+        }
+
+        pdm360ng_gpio_base = of_iomap(np, 0);
+        of_node_put(np);
+        if (!pdm360ng_gpio_base) {
+                pr_err("%s: Can't map gpio regs.\n", __func__);
+                return -ENODEV;
+        }
+        out_be32(pdm360ng_gpio_base + 0xc, 0xffffffff);
+        setbits32(pdm360ng_gpio_base + 0x18, 0x2000);
+        setbits32(pdm360ng_gpio_base + 0x10, 0x40);
+
+        return 0;
+}
+
+static int pdm360ng_touchscreen_notifier_call(struct notifier_block *nb,
+                                        unsigned long event, void *__dev)
+{
+        struct device *dev = __dev;
+
+        if ((event == BUS_NOTIFY_ADD_DEVICE) &&
+            of_device_is_compatible(dev->of_node, "ti,ads7846")) {
+                dev->platform_data = &pdm360ng_ads7846_pdata;
+                return NOTIFY_OK;
+        }
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block pdm360ng_touchscreen_nb = {
+        .notifier_call = pdm360ng_touchscreen_notifier_call,
+};
+
+static void __init pdm360ng_touchscreen_init(void)
+{
+        if (pdm360ng_penirq_init())
+                return;
+
+        bus_register_notifier(&spi_bus_type, &pdm360ng_touchscreen_nb);
+}
+#else
+static inline void __init pdm360ng_touchscreen_init(void)
+{
+}
+#endif /* CONFIG_TOUCHSCREEN_ADS7846 */
+
+void __init pdm360ng_init(void)
+{
+        mpc512x_init();
+        pdm360ng_touchscreen_init();
+}
+
+static int __init pdm360ng_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "ifm,pdm360ng");
+}
+
+define_machine(pdm360ng) {
+        .name                   = "PDM360NG",
+        .probe                  = pdm360ng_probe,
+        .setup_arch             = mpc512x_setup_diu,
+        .init                   = pdm360ng_init,
+        .init_early             = mpc512x_init_diu,
+        .init_IRQ               = mpc512x_init_IRQ,
+        .get_irq                = ipic_get_irq,
+        .calibrate_decr         = generic_calibrate_decr,
+        .restart                = mpc512x_restart,
+};
diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c
index 6d584f4e3c9a..de55bc0584b5 100644
--- a/arch/powerpc/platforms/52xx/lite5200.c
+++ b/arch/powerpc/platforms/52xx/lite5200.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/root_dev.h>
 #include <linux/initrd.h>
 #include <asm/time.h>
diff --git a/arch/powerpc/platforms/52xx/lite5200_pm.c b/arch/powerpc/platforms/52xx/lite5200_pm.c
index b5c753db125e..80234e5921f5 100644
--- a/arch/powerpc/platforms/52xx/lite5200_pm.c
+++ b/arch/powerpc/platforms/52xx/lite5200_pm.c
@@ -216,9 +216,6 @@ static int lite5200_pm_enter(suspend_state_t state)
 
         lite5200_restore_regs();
 
-        /* restart jiffies */
-        wakeup_decrementer();
-
         iounmap(mbar);
         return 0;
 }
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
index ca5305a5bd61..0dad9a935eb5 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
@@ -147,26 +147,25 @@ mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
         return 0;
 }
 
-static int __devinit mpc52xx_wkup_gpiochip_probe(struct of_device *ofdev,
+static int __devinit mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev,
                                         const struct of_device_id *match)
 {
         struct mpc52xx_gpiochip *chip;
         struct mpc52xx_gpio_wkup __iomem *regs;
-        struct of_gpio_chip *ofchip;
+        struct gpio_chip *gc;
         int ret;
 
         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
         if (!chip)
                 return -ENOMEM;
 
-        ofchip = &chip->mmchip.of_gc;
+        gc = &chip->mmchip.gc;
 
-        ofchip->gpio_cells          = 2;
-        ofchip->gc.ngpio            = 8;
-        ofchip->gc.direction_input  = mpc52xx_wkup_gpio_dir_in;
-        ofchip->gc.direction_output = mpc52xx_wkup_gpio_dir_out;
-        ofchip->gc.get              = mpc52xx_wkup_gpio_get;
-        ofchip->gc.set              = mpc52xx_wkup_gpio_set;
+        gc->ngpio            = 8;
+        gc->direction_input  = mpc52xx_wkup_gpio_dir_in;
+        gc->direction_output = mpc52xx_wkup_gpio_dir_out;
+        gc->get              = mpc52xx_wkup_gpio_get;
+        gc->set              = mpc52xx_wkup_gpio_set;
 
         ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip);
         if (ret)
@@ -180,7 +179,7 @@ static int __devinit mpc52xx_wkup_gpiochip_probe(struct of_device *ofdev,
         return 0;
 }
 
-static int mpc52xx_gpiochip_remove(struct of_device *ofdev)
+static int mpc52xx_gpiochip_remove(struct platform_device *ofdev)
 {
         return -EBUSY;
 }
@@ -311,11 +310,11 @@ mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
         return 0;
 }
 
-static int __devinit mpc52xx_simple_gpiochip_probe(struct of_device *ofdev,
+static int __devinit mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev,
                                         const struct of_device_id *match)
 {
         struct mpc52xx_gpiochip *chip;
-        struct of_gpio_chip *ofchip;
+        struct gpio_chip *gc;
         struct mpc52xx_gpio __iomem *regs;
         int ret;
 
@@ -323,14 +322,13 @@ static int __devinit mpc52xx_simple_gpiochip_probe(struct of_device *ofdev,
         if (!chip)
                 return -ENOMEM;
 
-        ofchip = &chip->mmchip.of_gc;
+        gc = &chip->mmchip.gc;
 
-        ofchip->gpio_cells          = 2;
-        ofchip->gc.ngpio            = 32;
-        ofchip->gc.direction_input  = mpc52xx_simple_gpio_dir_in;
-        ofchip->gc.direction_output = mpc52xx_simple_gpio_dir_out;
-        ofchip->gc.get              = mpc52xx_simple_gpio_get;
-        ofchip->gc.set              = mpc52xx_simple_gpio_set;
+        gc->ngpio            = 32;
+        gc->direction_input  = mpc52xx_simple_gpio_dir_in;
+        gc->direction_output = mpc52xx_simple_gpio_dir_out;
+        gc->get              = mpc52xx_simple_gpio_get;
+        gc->set              = mpc52xx_simple_gpio_set;
 
         ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip);
         if (ret)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 46c93578cbf0..fea833e18ad5 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -78,7 +78,7 @@ MODULE_LICENSE("GPL");
  * @dev: pointer to device structure
  * @regs: virtual address of GPT registers
  * @lock: spinlock to coordinate between different functions.
- * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
+ * @gc: gpio_chip instance structure; used when GPIO is enabled
  * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
  * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
  *   if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
@@ -94,7 +94,7 @@ struct mpc52xx_gpt_priv {
         u8 wdt_mode;
 
 #if defined(CONFIG_GPIOLIB)
-        struct of_gpio_chip of_gc;
+        struct gpio_chip gc;
 #endif
 };
 
@@ -280,7 +280,7 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
 #if defined(CONFIG_GPIOLIB)
 static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
 {
-        return container_of(to_of_gpio_chip(gc), struct mpc52xx_gpt_priv,of_gc);
+        return container_of(gc, struct mpc52xx_gpt_priv, gc);
 }
 
 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -336,28 +336,25 @@ mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
         if (!of_find_property(node, "gpio-controller", NULL))
                 return;
 
-        gpt->of_gc.gc.label = kstrdup(node->full_name, GFP_KERNEL);
-        if (!gpt->of_gc.gc.label) {
+        gpt->gc.label = kstrdup(node->full_name, GFP_KERNEL);
+        if (!gpt->gc.label) {
                 dev_err(gpt->dev, "out of memory\n");
                 return;
         }
 
-        gpt->of_gc.gpio_cells = 2;
-        gpt->of_gc.gc.ngpio = 1;
-        gpt->of_gc.gc.direction_input  = mpc52xx_gpt_gpio_dir_in;
-        gpt->of_gc.gc.direction_output = mpc52xx_gpt_gpio_dir_out;
-        gpt->of_gc.gc.get = mpc52xx_gpt_gpio_get;
-        gpt->of_gc.gc.set = mpc52xx_gpt_gpio_set;
-        gpt->of_gc.gc.base = -1;
-        gpt->of_gc.xlate = of_gpio_simple_xlate;
-        node->data = &gpt->of_gc;
-        of_node_get(node);
+        gpt->gc.ngpio = 1;
+        gpt->gc.direction_input  = mpc52xx_gpt_gpio_dir_in;
+        gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
+        gpt->gc.get = mpc52xx_gpt_gpio_get;
+        gpt->gc.set = mpc52xx_gpt_gpio_set;
+        gpt->gc.base = -1;
+        gpt->gc.of_node = node;
 
         /* Setup external pin in GPIO mode */
         clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
                         MPC52xx_GPT_MODE_MS_GPIO);
 
-        rc = gpiochip_add(&gpt->of_gc.gc);
+        rc = gpiochip_add(&gpt->gc);
         if (rc)
                 dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
 
@@ -723,7 +720,7 @@ static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
 /* ---------------------------------------------------------------------
  * of_platform bus binding code
  */
-static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
+static int __devinit mpc52xx_gpt_probe(struct platform_device *ofdev,
                                        const struct of_device_id *match)
 {
         struct mpc52xx_gpt_priv *gpt;
@@ -769,7 +766,7 @@ static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
         return 0;
 }
 
-static int mpc52xx_gpt_remove(struct of_device *ofdev)
+static int mpc52xx_gpt_remove(struct platform_device *ofdev)
 {
         return -EBUSY;
 }
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
index e86aec644501..f4ac213c89c0 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c
@@ -436,8 +436,8 @@ void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req)
 }
 EXPORT_SYMBOL(mpc52xx_lpbfifo_abort);
 
-static int __devinit
-mpc52xx_lpbfifo_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit mpc52xx_lpbfifo_probe(struct platform_device *op,
+                                           const struct of_device_id *match)
 {
         struct resource res;
         int rc = -ENOMEM;
@@ -507,7 +507,7 @@ mpc52xx_lpbfifo_probe(struct of_device *op, const struct of_device_id *match)
 }
 
 
-static int __devexit mpc52xx_lpbfifo_remove(struct of_device *op)
+static int __devexit mpc52xx_lpbfifo_remove(struct platform_device *op)
 {
         if (lpbfifo.dev != &op->dev)
                 return 0;
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pm.c b/arch/powerpc/platforms/52xx/mpc52xx_pm.c
index 76722532bd95..568cef636275 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pm.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pm.c
@@ -171,9 +171,6 @@ int mpc52xx_pm_enter(suspend_state_t state)
         /* restore SRAM */
         memcpy(sram, saved_sram, sram_size);
 
-        /* restart jiffies */
-        wakeup_decrementer();
-
         /* reenable interrupts in PIC */
         out_be32(&intr->main_mask, intr_main_mask);
 
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 9f2e52b36f91..1565e0446dc8 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -111,7 +111,7 @@ static struct mdiobb_ctrl ep8248e_mdio_ctrl = {
         .ops = &ep8248e_mdio_ops,
 };
 
-static int __devinit ep8248e_mdio_probe(struct of_device *ofdev,
+static int __devinit ep8248e_mdio_probe(struct platform_device *ofdev,
                                         const struct of_device_id *match)
 {
         struct mii_bus *bus;
@@ -154,7 +154,7 @@ err_free_bus:
         return ret;
 }
 
-static int ep8248e_mdio_remove(struct of_device *ofdev)
+static int ep8248e_mdio_remove(struct platform_device *ofdev)
 {
         BUG();
         return 0;
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index f49a2548c5ff..021763a32c2f 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -9,6 +9,14 @@ menuconfig PPC_83xx
 
 if PPC_83xx
 
+config MPC830x_RDB
+        bool "Freescale MPC830x RDB"
+        select DEFAULT_UIMAGE
+        select PPC_MPC831x
+        select FSL_GTM
+        help
+          This option enables support for the MPC8308 RDB board.
+
 config MPC831x_RDB
         bool "Freescale MPC831x RDB"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index e139c36572ec..6e8bbbbcfdf8 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -4,6 +4,7 @@
 obj-y                           := misc.o usb.o
 obj-$(CONFIG_SUSPEND)           += suspend.o suspend-asm.o
 obj-$(CONFIG_MCU_MPC8349EMITX)  += mcu_mpc8349emitx.o
+obj-$(CONFIG_MPC830x_RDB)       += mpc830x_rdb.o
 obj-$(CONFIG_MPC831x_RDB)       += mpc831x_rdb.o
 obj-$(CONFIG_MPC832x_RDB)       += mpc832x_rdb.o
 obj-$(CONFIG_MPC834x_MDS)       += mpc834x_mds.o
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index d119a7c1c17a..70798ac911ef 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -35,9 +35,8 @@
 
 struct mcu {
         struct mutex lock;
-        struct device_node *np;
         struct i2c_client *client;
-        struct of_gpio_chip of_gc;
+        struct gpio_chip gc;
         u8 reg_ctrl;
 };
 
@@ -56,8 +55,7 @@ static void mcu_power_off(void)
 
 static void mcu_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 {
-        struct of_gpio_chip *of_gc = to_of_gpio_chip(gc);
-        struct mcu *mcu = container_of(of_gc, struct mcu, of_gc);
+        struct mcu *mcu = container_of(gc, struct mcu, gc);
         u8 bit = 1 << (4 + gpio);
 
         mutex_lock(&mcu->lock);
@@ -79,9 +77,7 @@ static int mcu_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 static int mcu_gpiochip_add(struct mcu *mcu)
 {
         struct device_node *np;
-        struct of_gpio_chip *of_gc = &mcu->of_gc;
-        struct gpio_chip *gc = &of_gc->gc;
-        int ret;
+        struct gpio_chip *gc = &mcu->gc;
 
         np = of_find_compatible_node(NULL, NULL, "fsl,mcu-mpc8349emitx");
         if (!np)
@@ -94,32 +90,14 @@ static int mcu_gpiochip_add(struct mcu *mcu)
         gc->base = -1;
         gc->set = mcu_gpio_set;
         gc->direction_output = mcu_gpio_dir_out;
-        of_gc->gpio_cells = 2;
-        of_gc->xlate = of_gpio_simple_xlate;
+        gc->of_node = np;
 
-        np->data = of_gc;
-        mcu->np = np;
-
-        /*
-         * We don't want to lose the node, its ->data and ->full_name...
-         * So, if succeeded, we don't put the node here.
-         */
-        ret = gpiochip_add(gc);
-        if (ret)
-                of_node_put(np);
-        return ret;
+        return gpiochip_add(gc);
 }
 
 static int mcu_gpiochip_remove(struct mcu *mcu)
 {
-        int ret;
-
-        ret = gpiochip_remove(&mcu->of_gc.gc);
-        if (ret)
-                return ret;
-        of_node_put(mcu->np);
-
-        return 0;
+        return gpiochip_remove(&mcu->gc);
 }
 
 static int __devinit mcu_probe(struct i2c_client *client,
@@ -182,10 +160,16 @@ static const struct i2c_device_id mcu_ids[] = {
 };
 MODULE_DEVICE_TABLE(i2c, mcu_ids);
 
+static struct of_device_id mcu_of_match_table[] __devinitdata = {
+        { .compatible = "fsl,mcu-mpc8349emitx", },
+        { },
+};
+
 static struct i2c_driver mcu_driver = {
         .driver = {
                 .name = "mcu-mpc8349emitx",
                 .owner = THIS_MODULE,
+                .of_match_table = mcu_of_match_table,
         },
         .probe = mcu_probe,
         .remove = __devexit_p(mcu_remove),
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
new file mode 100644
index 000000000000..ac102ee9abe8
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -0,0 +1,94 @@
+/*
+ * arch/powerpc/platforms/83xx/mpc830x_rdb.c
+ *
+ * Description: MPC830x RDB board specific routines.
+ * This file is based on mpc831x_rdb.c
+ *
+ * Copyright (C) Freescale Semiconductor, Inc. 2009. All rights reserved.
+ * Copyright (C) 2010. Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <asm/time.h>
+#include <asm/ipic.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_pci.h>
+#include <sysdev/fsl_soc.h>
+#include "mpc83xx.h"
+
+/*
+ * Setup the architecture
+ */
+static void __init mpc830x_rdb_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc830x_rdb_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,mpc8308-pcie")
+                mpc83xx_add_bridge(np);
+#endif
+        mpc831x_usb_cfg();
+}
+
+static void __init mpc830x_rdb_init_IRQ(void)
+{
+        struct device_node *np;
+
+        np = of_find_node_by_type(NULL, "ipic");
+        if (!np)
+                return;
+
+        ipic_init(np, 0);
+
+        /* Initialize the default interrupt mapping priorities,
+         * in case the boot rom changed something on us.
+         */
+        ipic_set_default_priority();
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc830x_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "MPC8308RDB") ||
+               of_flat_dt_is_compatible(root, "fsl,mpc8308rdb");
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .compatible = "simple-bus" },
+        { .compatible = "gianfar" },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+        return 0;
+}
+machine_device_initcall(mpc830x_rdb, declare_of_platform_devices);
+
+define_machine(mpc830x_rdb) {
+        .name                   = "MPC830x RDB",
+        .probe                  = mpc830x_rdb_probe,
+        .setup_arch             = mpc830x_rdb_setup_arch,
+        .init_IRQ               = mpc830x_rdb_init_IRQ,
+        .get_irq                = ipic_get_irq,
+        .restart                = mpc83xx_restart,
+        .time_init              = mpc83xx_time_init,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/83xx/suspend.c b/arch/powerpc/platforms/83xx/suspend.c
index ebe6c3537209..75ae77f1af6a 100644
--- a/arch/powerpc/platforms/83xx/suspend.c
+++ b/arch/powerpc/platforms/83xx/suspend.c
@@ -99,7 +99,7 @@ struct pmc_type {
         int has_deep_sleep;
 };
 
-static struct of_device *pmc_dev;
+static struct platform_device *pmc_dev;
 static int has_deep_sleep, deep_sleeping;
 static int pmc_irq;
 static struct mpc83xx_pmc __iomem *pmc_regs;
@@ -318,7 +318,7 @@ static struct platform_suspend_ops mpc83xx_suspend_ops = {
         .end = mpc83xx_suspend_end,
 };
 
-static int pmc_probe(struct of_device *ofdev,
+static int pmc_probe(struct platform_device *ofdev,
                      const struct of_device_id *match)
 {
         struct device_node *np = ofdev->dev.of_node;
@@ -396,7 +396,7 @@ out:
         return ret;
 }
 
-static int pmc_remove(struct of_device *ofdev)
+static int pmc_remove(struct platform_device *ofdev)
 {
         return -EPERM;
 };
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 3a2ade2e443f..bea1f5905ad4 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -65,6 +65,14 @@ config MPC85xx_RDB
         help
           This option enables support for the MPC85xx RDB (P2020 RDB) board
 
+config P1022_DS
+        bool "Freescale P1022 DS"
+        select DEFAULT_UIMAGE
+        select CONFIG_PHYS_64BIT        # The DTS has 36-bit addresses
+        select SWIOTLB
+        help
+          This option enables support for the Freescale P1022DS reference board.
+
 config SOCRATES
         bool "Socrates"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 387c128f2c8c..a2ec3f8f4d06 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.o
 obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
 obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
 obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
+obj-$(CONFIG_P1022_DS)    += p1022_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 494513682d70..da64be19d099 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -158,51 +158,108 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
 extern void __init mpc85xx_smp_init(void);
 #endif
 
-static void __init mpc85xx_mds_setup_arch(void)
+#ifdef CONFIG_QUICC_ENGINE
+static struct of_device_id mpc85xx_qe_ids[] __initdata = {
+        { .type = "qe", },
+        { .compatible = "fsl,qe", },
+        { },
+};
+
+static void __init mpc85xx_publish_qe_devices(void)
 {
         struct device_node *np;
-        static u8 __iomem *bcsr_regs = NULL;
-#ifdef CONFIG_PCI
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
 
-        if (ppc_md.progress)
-                ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
+        of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
+}
+
+static void __init mpc85xx_mds_reset_ucc_phys(void)
+{
+        struct device_node *np;
+        static u8 __iomem *bcsr_regs;
 
         /* Map BCSR area */
         np = of_find_node_by_name(NULL, "bcsr");
-        if (np != NULL) {
-                struct resource res;
+        if (!np)
+                return;
 
-                of_address_to_resource(np, 0, &res);
-                bcsr_regs = ioremap(res.start, res.end - res.start +1);
-                of_node_put(np);
-        }
+        bcsr_regs = of_iomap(np, 0);
+        of_node_put(np);
+        if (!bcsr_regs)
+                return;
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0x8000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
+        if (machine_is(mpc8568_mds)) {
+#define BCSR_UCC1_GETH_EN       (0x1 << 7)
+#define BCSR_UCC2_GETH_EN       (0x1 << 7)
+#define BCSR_UCC1_MODE_MSK      (0x3 << 4)
+#define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
+                /* Turn off UCC1 & UCC2 */
+                clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+
+                /* Mode is RGMII, all bits clear */
+                clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+                                         BCSR_UCC2_MODE_MSK);
+
+                /* Turn UCC1 & UCC2 on */
+                setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+        } else if (machine_is(mpc8569_mds)) {
+#define BCSR7_UCC12_GETHnRST    (0x1 << 2)
+#define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
+#define BCSR_UCC_RGMII          (0x1 << 6)
+#define BCSR_UCC_RTBI           (0x1 << 5)
+                /*
+                 * U-Boot mangles interrupt polarity for Marvell PHYs,
+                 * so reset built-in and UEM Marvell PHYs, this puts
+                 * the PHYs into their normal state.
+                 */
+                clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+                setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+                setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+                clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+                for (np = NULL; (np = of_find_compatible_node(np,
+                                                "network",
+                                                "ucc_geth")) != NULL;) {
+                        const unsigned int *prop;
+                        int ucc_num;
+
+                        prop = of_get_property(np, "cell-index", NULL);
+                        if (prop == NULL)
+                                continue;
+
+                        ucc_num = *prop - 1;
+
+                        prop = of_get_property(np, "phy-connection-type", NULL);
+                        if (prop == NULL)
+                                continue;
+
+                        if (strcmp("rtbi", (const char *)prop) == 0)
+                                clrsetbits_8(&bcsr_regs[7 + ucc_num],
+                                        BCSR_UCC_RGMII, BCSR_UCC_RTBI);
                 }
+        } else if (machine_is(p1021_mds)) {
+#define BCSR11_ENET_MICRST     (0x1 << 5)
+                /* Reset Micrel PHY */
+                clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
+                setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
         }
-#endif
 
-#ifdef CONFIG_SMP
-        mpc85xx_smp_init();
-#endif
+        iounmap(bcsr_regs);
+}
+
+static void __init mpc85xx_mds_qe_init(void)
+{
+        struct device_node *np;
 
-#ifdef CONFIG_QUICC_ENGINE
         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
         if (!np) {
                 np = of_find_node_by_name(NULL, "qe");
@@ -210,6 +267,11 @@ static void __init mpc85xx_mds_setup_arch(void)
                         return;
         }
 
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
         qe_reset();
         of_node_put(np);
 
@@ -224,70 +286,7 @@ static void __init mpc85xx_mds_setup_arch(void)
                         par_io_of_config(ucc);
         }
 
-        if (bcsr_regs) {
-                if (machine_is(mpc8568_mds)) {
-#define BCSR_UCC1_GETH_EN       (0x1 << 7)
-#define BCSR_UCC2_GETH_EN       (0x1 << 7)
-#define BCSR_UCC1_MODE_MSK      (0x3 << 4)
-#define BCSR_UCC2_MODE_MSK      (0x3 << 0)
-
-                        /* Turn off UCC1 & UCC2 */
-                        clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                        clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
-
-                        /* Mode is RGMII, all bits clear */
-                        clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
-                                                 BCSR_UCC2_MODE_MSK);
-
-                        /* Turn UCC1 & UCC2 on */
-                        setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                        setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
-                } else if (machine_is(mpc8569_mds)) {
-#define BCSR7_UCC12_GETHnRST    (0x1 << 2)
-#define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
-#define BCSR_UCC_RGMII          (0x1 << 6)
-#define BCSR_UCC_RTBI           (0x1 << 5)
-                        /*
-                         * U-Boot mangles interrupt polarity for Marvell PHYs,
-                         * so reset built-in and UEM Marvell PHYs, this puts
-                         * the PHYs into their normal state.
-                         */
-                        clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
-                        setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
-
-                        setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
-                        clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
-
-                        for (np = NULL; (np = of_find_compatible_node(np,
-                                                        "network",
-                                                        "ucc_geth")) != NULL;) {
-                                const unsigned int *prop;
-                                int ucc_num;
-
-                                prop = of_get_property(np, "cell-index", NULL);
-                                if (prop == NULL)
-                                        continue;
-
-                                ucc_num = *prop - 1;
-
-                                prop = of_get_property(np, "phy-connection-type", NULL);
-                                if (prop == NULL)
-                                        continue;
-
-                                if (strcmp("rtbi", (const char *)prop) == 0)
-                                        clrsetbits_8(&bcsr_regs[7 + ucc_num],
-                                                BCSR_UCC_RGMII, BCSR_UCC_RTBI);
-                        }
-
-                } else if (machine_is(p1021_mds)) {
-#define BCSR11_ENET_MICRST     (0x1 << 5)
-                        /* Reset Micrel PHY */
-                        clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
-                        setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
-                }
-
-                iounmap(bcsr_regs);
-        }
+        mpc85xx_mds_reset_ucc_phys();
 
         if (machine_is(p1021_mds)) {
 #define MPC85xx_PMUXCR_OFFSET           0x60
@@ -322,8 +321,72 @@ static void __init mpc85xx_mds_setup_arch(void)
                 }
 
         }
+}
+
+static void __init mpc85xx_mds_qeic_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (!np) {
+                np = of_find_node_by_type(NULL, "qeic");
+                if (!np)
+                        return;
+        }
+
+        if (machine_is(p1021_mds))
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+        else
+                qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+        of_node_put(np);
+}
+#else
+static void __init mpc85xx_publish_qe_devices(void) { }
+static void __init mpc85xx_mds_qe_init(void) { }
+static void __init mpc85xx_mds_qeic_init(void) { }
 #endif  /* CONFIG_QUICC_ENGINE */
 
+static void __init mpc85xx_mds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct pci_controller *hose;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_node_by_type(np, "pci") {
+                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
+                        struct resource rsrc;
+                        of_address_to_resource(np, 0, &rsrc);
+                        if ((rsrc.start & 0xfffff) == 0x8000)
+                                fsl_add_bridge(np, 1);
+                        else
+                                fsl_add_bridge(np, 0);
+
+                        hose = pci_find_hose_for_OF_device(np);
+                        max = min(max, hose->dma_window_base_cur +
+                                        hose->dma_window_size);
+                }
+        }
+#endif
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+        mpc85xx_mds_qe_init();
+
 #ifdef CONFIG_SWIOTLB
         if (memblock_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
@@ -369,8 +432,6 @@ static struct of_device_id mpc85xx_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
         { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
         { .compatible = "gianfar", },
         { .compatible = "fsl,rapidio-delta", },
         { .compatible = "fsl,mpc8548-guts", },
@@ -382,8 +443,6 @@ static struct of_device_id p1021_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
         { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
         { .compatible = "gianfar", },
         {},
 };
@@ -395,16 +454,16 @@ static int __init mpc85xx_publish_devices(void)
         if (machine_is(mpc8569_mds))
                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
-        /* Publish the QE devices */
         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
+        mpc85xx_publish_qe_devices();
 
         return 0;
 }
 
 static int __init p1021_publish_devices(void)
 {
-        /* Publish the QE devices */
         of_platform_bus_probe(NULL, p1021_ids, NULL);
+        mpc85xx_publish_qe_devices();
 
         return 0;
 }
@@ -441,21 +500,7 @@ static void __init mpc85xx_mds_pic_init(void)
         of_node_put(np);
 
         mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "qeic");
-                if (!np)
-                        return;
-        }
-        if (machine_is(p1021_mds))
-                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-                                qe_ic_cascade_high_mpic);
-        else
-                qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
-        of_node_put(np);
-#endif                          /* CONFIG_QUICC_ENGINE */
+        mpc85xx_mds_qeic_init();
 }
 
 static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
new file mode 100644
index 000000000000..e1467c937450
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -0,0 +1,148 @@
+/*
+ * P1022DS board specific routines
+ *
+ * Authors: Travis Wheatley <travis.wheatley@freescale.com>
+ *          Dave Liu <daveliu@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is taken from the Freescale P1022DS BSP, with modifications:
+ * 1) No DIU support (pending rewrite of DIU code)
+ * 2) No AMP support
+ * 3) No PCI endpoint support
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <linux/lmb.h>
+
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+void __init p1022_ds_pic_init(void)
+{
+        struct mpic *mpic;
+        struct resource r;
+        struct device_node *np;
+
+        np = of_find_node_by_type(NULL, "open-pic");
+        if (!np) {
+                pr_err("Could not find open-pic node\n");
+                return;
+        }
+
+        if (of_address_to_resource(np, 0, &r)) {
+                pr_err("Failed to map mpic register space\n");
+                of_node_put(np);
+                return;
+        }
+
+        mpic = mpic_alloc(np, r.start,
+                MPIC_PRIMARY | MPIC_WANTS_RESET |
+                MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                MPIC_SINGLE_DEST_CPU,
+                0, 256, " OpenPIC  ");
+
+        BUG_ON(mpic == NULL);
+        of_node_put(np);
+
+        mpic_init(mpic);
+}
+
+#ifdef CONFIG_SMP
+void __init mpc85xx_smp_init(void);
+#endif
+
+/*
+ * Setup the architecture
+ */
+static void __init p1022_ds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("p1022_ds_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
+                struct resource rsrc;
+                struct pci_controller *hose;
+
+                of_address_to_resource(np, 0, &rsrc);
+
+                if ((rsrc.start & 0xfffff) == 0x8000)
+                        fsl_add_bridge(np, 1);
+                else
+                        fsl_add_bridge(np, 0);
+
+                hose = pci_find_hose_for_OF_device(np);
+                max = min(max, hose->dma_window_base_cur +
+                          hose->dma_window_size);
+        }
+#endif
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+#ifdef CONFIG_SWIOTLB
+        if (lmb_end_of_DRAM() > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+
+        pr_info("Freescale P1022 DS reference board\n");
+}
+
+static struct of_device_id __initdata p1022_ds_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .compatible = "simple-bus", },
+        { .compatible = "gianfar", },
+        {},
+};
+
+static int __init p1022_ds_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
+}
+machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
+
+machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p1022_ds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,p1022ds");
+}
+
+define_machine(p1022_ds) {
+        .name                   = "P1022 DS",
+        .probe                  = p1022_ds_probe,
+        .setup_arch             = p1022_ds_setup_arch,
+        .init_IRQ               = p1022_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index a15f582300d8..a6b106557be4 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/of.h>
+#include <linux/kexec.h>
 
 #include <asm/machdep.h>
 #include <asm/pgtable.h>
@@ -24,6 +25,7 @@
 #include <asm/dbell.h>
 
 #include <sysdev/fsl_soc.h>
+#include <sysdev/mpic.h>
 
 extern void __early_start(void);
 
@@ -99,12 +101,70 @@ static void __init
 smp_85xx_setup_cpu(int cpu_nr)
 {
         mpic_setup_this_cpu();
+        if (cpu_has_feature(CPU_FTR_DBELL))
+                doorbell_setup_this_cpu();
 }
 
 struct smp_ops_t smp_85xx_ops = {
         .kick_cpu = smp_85xx_kick_cpu,
+#ifdef CONFIG_KEXEC
+        .give_timebase  = smp_generic_give_timebase,
+        .take_timebase  = smp_generic_take_timebase,
+#endif
 };
 
+#ifdef CONFIG_KEXEC
+static int kexec_down_cpus = 0;
+
+void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
+{
+        mpic_teardown_this_cpu(1);
+
+        /* When crashing, this gets called on all CPU's we only
+         * take down the non-boot cpus */
+        if (smp_processor_id() != boot_cpuid)
+        {
+                local_irq_disable();
+                kexec_down_cpus++;
+
+                while (1);
+        }
+}
+
+static void mpc85xx_smp_kexec_down(void *arg)
+{
+        if (ppc_md.kexec_cpu_down)
+                ppc_md.kexec_cpu_down(0,1);
+}
+
+static void mpc85xx_smp_machine_kexec(struct kimage *image)
+{
+        int timeout = 2000;
+        int i;
+
+        set_cpus_allowed(current, cpumask_of_cpu(boot_cpuid));
+
+        smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
+
+        while ( (kexec_down_cpus != (num_online_cpus() - 1)) &&
+                ( timeout > 0 ) )
+        {
+                timeout--;
+        }
+
+        if ( !timeout )
+                printk(KERN_ERR "Unable to bring down secondary cpu(s)");
+
+        for (i = 0; i < num_present_cpus(); i++)
+        {
+                if ( i == smp_processor_id() ) continue;
+                mpic_reset_core(i);
+        }
+
+        default_machine_kexec(image);
+}
+#endif /* CONFIG_KEXEC */
+
 void __init mpc85xx_smp_init(void)
 {
         struct device_node *np;
@@ -117,9 +177,14 @@ void __init mpc85xx_smp_init(void)
         }
 
         if (cpu_has_feature(CPU_FTR_DBELL))
-                smp_85xx_ops.message_pass = smp_dbell_message_pass;
+                smp_85xx_ops.message_pass = doorbell_message_pass;
 
         BUG_ON(!smp_85xx_ops.message_pass);
 
         smp_ops = &smp_85xx_ops;
+
+#ifdef CONFIG_KEXEC
+        ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
+        ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
+#endif
 }
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 5b0ab9966e90..8f29bbce5360 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -151,6 +151,27 @@ static void tqm85xx_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
 
+static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev)
+{
+        unsigned int val;
+
+        /* Do not do the fixup on other platforms! */
+        if (!machine_is(tqm85xx))
+                return;
+
+        dev_info(&pdev->dev, "Using TI 1520 fixup on TQM85xx\n");
+
+        /*
+         * Enable P2CCLK bit in system control register
+         * to enable CLOCK output to power chip
+         */
+        pci_read_config_dword(pdev, 0x80, &val);
+        pci_write_config_dword(pdev, 0x80, val | (1 << 27));
+
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
+                tqm85xx_ti1520_fixup);
+
 static struct of_device_id __initdata of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c b/arch/powerpc/platforms/86xx/gef_gpio.c
index b8cb08dbd89c..4ff7b1e7bbad 100644
--- a/arch/powerpc/platforms/86xx/gef_gpio.c
+++ b/arch/powerpc/platforms/86xx/gef_gpio.c
@@ -118,12 +118,12 @@ static int __init gef_gpio_init(void)
                 }
 
                 /* Setup pointers to chip functions */
-                gef_gpio_chip->of_gc.gpio_cells = 2;
-                gef_gpio_chip->of_gc.gc.ngpio = 19;
-                gef_gpio_chip->of_gc.gc.direction_input = gef_gpio_dir_in;
-                gef_gpio_chip->of_gc.gc.direction_output = gef_gpio_dir_out;
-                gef_gpio_chip->of_gc.gc.get = gef_gpio_get;
-                gef_gpio_chip->of_gc.gc.set = gef_gpio_set;
+                gef_gpio_chip->gc.of_gpio_n_cells = 2;
+                gef_gpio_chip->gc.ngpio = 19;
+                gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
+                gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
+                gef_gpio_chip->gc.get = gef_gpio_get;
+                gef_gpio_chip->gc.set = gef_gpio_set;
 
                 /* This function adds a memory mapped GPIO chip */
                 retval = of_mm_gpiochip_add(np, gef_gpio_chip);
@@ -146,12 +146,12 @@ static int __init gef_gpio_init(void)
                 }
 
                 /* Setup pointers to chip functions */
-                gef_gpio_chip->of_gc.gpio_cells = 2;
-                gef_gpio_chip->of_gc.gc.ngpio = 6;
-                gef_gpio_chip->of_gc.gc.direction_input = gef_gpio_dir_in;
-                gef_gpio_chip->of_gc.gc.direction_output = gef_gpio_dir_out;
-                gef_gpio_chip->of_gc.gc.get = gef_gpio_get;
-                gef_gpio_chip->of_gc.gc.set = gef_gpio_set;
+                gef_gpio_chip->gc.of_gpio_n_cells = 2;
+                gef_gpio_chip->gc.ngpio = 6;
+                gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
+                gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
+                gef_gpio_chip->gc.get = gef_gpio_get;
+                gef_gpio_chip->gc.set = gef_gpio_set;
 
                 /* This function adds a memory mapped GPIO chip */
                 retval = of_mm_gpiochip_add(np, gef_gpio_chip);
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 48a920a98e7b..dd35ce081cff 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -55,6 +55,12 @@ config PPC_MGSUVD
         help
           This enables support for the Keymile MGSUVD board.
 
+config TQM8XX
+        bool "TQM8XX"
+        select CPM1
+        help
+          support for the mpc8xx based boards from TQM.
+
 endchoice
 
 menu "Freescale Ethernet driver platform-specific options"
diff --git a/arch/powerpc/platforms/8xx/Makefile b/arch/powerpc/platforms/8xx/Makefile
index bdbfd7496018..a491fe6b94fc 100644
--- a/arch/powerpc/platforms/8xx/Makefile
+++ b/arch/powerpc/platforms/8xx/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_MPC86XADS)   += mpc86xads_setup.o
 obj-$(CONFIG_PPC_EP88XC)  += ep88xc.o
 obj-$(CONFIG_PPC_ADDER875) += adder875.o
 obj-$(CONFIG_PPC_MGSUVD) += mgsuvd.o
+obj-$(CONFIG_TQM8XX)      += tqm8xx_setup.o
diff --git a/arch/powerpc/platforms/8xx/tqm8xx_setup.c b/arch/powerpc/platforms/8xx/tqm8xx_setup.c
new file mode 100644
index 000000000000..b71c650fbb11
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/tqm8xx_setup.c
@@ -0,0 +1,156 @@
+/*
+ * Platform setup for the MPC8xx based boards from TQM.
+ *
+ * Heiko Schocher <hs@denx.de>
+ * Copyright 2010 DENX Software Engineering GmbH
+ *
+ * based on:
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * Heavily modified by Scott Wood <scottwood@freescale.com>
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <linux/fs_enet_pd.h>
+#include <linux/fs_uart_pd.h>
+#include <linux/fsl_devices.h>
+#include <linux/mii.h>
+#include <linux/of_platform.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <asm/cpm1.h>
+#include <asm/fs_pd.h>
+#include <asm/udbg.h>
+
+#include "mpc8xx.h"
+
+struct cpm_pin {
+        int port, pin, flags;
+};
+
+static struct __initdata cpm_pin tqm8xx_pins[] = {
+        /* SMC1 */
+        {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
+        {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
+
+        /* SCC1 */
+        {CPM_PORTA, 5, CPM_PIN_INPUT}, /* CLK1 */
+        {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
+        {CPM_PORTA, 14, CPM_PIN_INPUT}, /* TX */
+        {CPM_PORTA, 15, CPM_PIN_INPUT}, /* RX */
+        {CPM_PORTC, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
+        {CPM_PORTC, 10, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
+        {CPM_PORTC, 11, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
+};
+
+static struct __initdata cpm_pin tqm8xx_fec_pins[] = {
+        /* MII */
+        {CPM_PORTD, 3, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 4, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 5, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 6, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 7, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 8, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 9, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 10, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 11, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 12, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 13, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 14, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 15, CPM_PIN_OUTPUT},
+};
+
+static void __init init_pins(int n, struct cpm_pin *pin)
+{
+        int i;
+
+        for (i = 0; i < n; i++) {
+                cpm1_set_pin(pin->port, pin->pin, pin->flags);
+                pin++;
+        }
+}
+
+static void __init init_ioports(void)
+{
+        struct device_node *dnode;
+        struct property *prop;
+        int     len;
+
+        init_pins(ARRAY_SIZE(tqm8xx_pins), &tqm8xx_pins[0]);
+
+        cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
+
+        dnode = of_find_node_by_name(NULL, "aliases");
+        if (dnode == NULL)
+                return;
+        prop = of_find_property(dnode, "ethernet1", &len);
+        if (prop == NULL)
+                return;
+
+        /* init FEC pins */
+        init_pins(ARRAY_SIZE(tqm8xx_fec_pins), &tqm8xx_fec_pins[0]);
+}
+
+static void __init tqm8xx_setup_arch(void)
+{
+        cpm_reset();
+        init_ioports();
+}
+
+static int __init tqm8xx_probe(void)
+{
+        unsigned long node = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(node, "tqc,tqm8xx");
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .name = "soc", },
+        { .name = "cpm", },
+        { .name = "localbus", },
+        { .compatible = "simple-bus" },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+        return 0;
+}
+machine_device_initcall(tqm8xx, declare_of_platform_devices);
+
+define_machine(tqm8xx) {
+        .name                   = "TQM8xx",
+        .probe                  = tqm8xx_probe,
+        .setup_arch             = tqm8xx_setup_arch,
+        .init_IRQ               = mpc8xx_pics_init,
+        .get_irq                = mpc8xx_get_irq,
+        .restart                = mpc8xx_restart,
+        .calibrate_decr         = mpc8xx_calibrate_decr,
+        .set_rtc_time           = mpc8xx_set_rtc_time,
+        .get_rtc_time           = mpc8xx_get_rtc_time,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/amigaone/setup.c b/arch/powerpc/platforms/amigaone/setup.c
index fb4eb0df054c..03aabc0e16ac 100644
--- a/arch/powerpc/platforms/amigaone/setup.c
+++ b/arch/powerpc/platforms/amigaone/setup.c
@@ -13,12 +13,13 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/seq_file.h>
 #include <generated/utsrelease.h>
 
 #include <asm/machdep.h>
 #include <asm/cputable.h>
-#include <asm/prom.h>
 #include <asm/pci-bridge.h>
 #include <asm/i8259.h>
 #include <asm/time.h>
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index 6257e5378615..97085530aa63 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -328,7 +328,7 @@ static struct irq_host_ops msic_host_ops = {
         .map    = msic_host_map,
 };
 
-static int axon_msi_shutdown(struct of_device *device)
+static int axon_msi_shutdown(struct platform_device *device)
 {
         struct axon_msic *msic = dev_get_drvdata(&device->dev);
         u32 tmp;
@@ -342,7 +342,7 @@ static int axon_msi_shutdown(struct of_device *device)
         return 0;
 }
 
-static int axon_msi_probe(struct of_device *device,
+static int axon_msi_probe(struct platform_device *device,
                           const struct of_device_id *device_id)
 {
         struct device_node *dn = device->dev.of_node;
diff --git a/arch/powerpc/platforms/cell/beat_iommu.c b/arch/powerpc/platforms/cell/beat_iommu.c
index 39d361c5c6d2..beec405eb6f8 100644
--- a/arch/powerpc/platforms/cell/beat_iommu.c
+++ b/arch/powerpc/platforms/cell/beat_iommu.c
@@ -108,7 +108,7 @@ static int __init celleb_init_iommu(void)
         celleb_init_direct_mapping();
         set_pci_dma_ops(&dma_direct_ops);
         ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup;
-        bus_register_notifier(&of_platform_bus_type, &celleb_of_bus_notifier);
+        bus_register_notifier(&platform_bus_type, &celleb_of_bus_notifier);
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index 3712900471ba..58b13ce3847e 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -1204,7 +1204,7 @@ static int __init cell_iommu_init(void)
         /* Register callbacks on OF platform device addition/removal
          * to handle linking them to the right DMA operations
          */
-        bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier);
+        bus_register_notifier(&platform_bus_type, &cell_of_bus_notifier);
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/cell/qpace_setup.c b/arch/powerpc/platforms/cell/qpace_setup.c
index c5ce02e84c8e..1b5749042756 100644
--- a/arch/powerpc/platforms/cell/qpace_setup.c
+++ b/arch/powerpc/platforms/cell/qpace_setup.c
@@ -61,12 +61,24 @@ static void qpace_progress(char *s, unsigned short hex)
         printk("*** %04x : %s\n", hex, s ? s : "");
 }
 
+static const struct of_device_id qpace_bus_ids[] __initdata = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .type = "spider", },
+        { .type = "axon", },
+        { .type = "plb5", },
+        { .type = "plb4", },
+        { .type = "opb", },
+        { .type = "ebc", },
+        {},
+};
+
 static int __init qpace_publish_devices(void)
 {
         int node;
 
         /* Publish OF platform devices for southbridge IOs */
-        of_platform_bus_probe(NULL, NULL, NULL);
+        of_platform_bus_probe(NULL, qpace_bus_ids, NULL);
 
         /* There is no device for the MIC memory controller, thus we create
          * a platform device for it to attach the EDAC driver to.
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index 50385db586bd..691995761b3d 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -141,6 +141,18 @@ static int __devinit cell_setup_phb(struct pci_controller *phb)
         return 0;
 }
 
+static const struct of_device_id cell_bus_ids[] __initdata = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .type = "spider", },
+        { .type = "axon", },
+        { .type = "plb5", },
+        { .type = "plb4", },
+        { .type = "opb", },
+        { .type = "ebc", },
+        {},
+};
+
 static int __init cell_publish_devices(void)
 {
         struct device_node *root = of_find_node_by_path("/");
@@ -148,7 +160,7 @@ static int __init cell_publish_devices(void)
         int node;
 
         /* Publish OF platform devices for southbridge IOs */
-        of_platform_bus_probe(NULL, NULL, NULL);
+        of_platform_bus_probe(NULL, cell_bus_ids, NULL);
 
         /* On spider based blades, we need to manually create the OF
          * platform devices for the PCI host bridges
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c
index d2c1d497846e..33e5fc7334fc 100644
--- a/arch/powerpc/platforms/iseries/mf.c
+++ b/arch/powerpc/platforms/iseries/mf.c
@@ -30,6 +30,7 @@
 #include <linux/init.h>
 #include <linux/completion.h>
 #include <linux/delay.h>
+#include <linux/proc_fs.h>
 #include <linux/dma-mapping.h>
 #include <linux/bcd.h>
 #include <linux/rtc.h>
diff --git a/arch/powerpc/platforms/iseries/vio.c b/arch/powerpc/platforms/iseries/vio.c
index 00b6730bc48f..b6db7cef83b4 100644
--- a/arch/powerpc/platforms/iseries/vio.c
+++ b/arch/powerpc/platforms/iseries/vio.c
@@ -87,12 +87,11 @@ static struct device_node *new_node(const char *path,
 
         if (!np)
                 return NULL;
-        np->full_name = kmalloc(strlen(path) + 1, GFP_KERNEL);
+        np->full_name = kstrdup(path, GFP_KERNEL);
         if (!np->full_name) {
                 kfree(np);
                 return NULL;
         }
-        strcpy(np->full_name, path);
         of_node_set_flag(np, OF_DYNAMIC);
         kref_init(&np->kref);
         np->parent = of_node_get(parent);
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
index 627ee089e75d..a5d907b5a4c2 100644
--- a/arch/powerpc/platforms/pasemi/gpio_mdio.c
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -216,7 +216,7 @@ static int gpio_mdio_reset(struct mii_bus *bus)
 }
 
 
-static int __devinit gpio_mdio_probe(struct of_device *ofdev,
+static int __devinit gpio_mdio_probe(struct platform_device *ofdev,
                                      const struct of_device_id *match)
 {
         struct device *dev = &ofdev->dev;
@@ -275,7 +275,7 @@ out:
 }
 
 
-static int gpio_mdio_remove(struct of_device *dev)
+static int gpio_mdio_remove(struct platform_device *dev)
 {
         struct mii_bus *bus = dev_get_drvdata(&dev->dev);
 
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
index 1e9eba175ff0..415ca6d6b273 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_32.c
@@ -310,8 +310,12 @@ static int pmu_set_cpu_speed(int low_speed)
         /* Restore low level PMU operations */
         pmu_unlock();
 
-        /* Restore decrementer */
-        wakeup_decrementer();
+        /*
+         * Restore decrementer; we'll take a decrementer interrupt
+         * as soon as interrupts are re-enabled and the generic
+         * clockevents code will reprogram it with the right value.
+         */
+        set_dec(1);
 
         /* Restore interrupts */
         mpic_cpu_set_priority(pic_prio);
diff --git a/arch/powerpc/platforms/powermac/feature.c b/arch/powerpc/platforms/powermac/feature.c
index 9e1b9fd75206..39df6ab1735a 100644
--- a/arch/powerpc/platforms/powermac/feature.c
+++ b/arch/powerpc/platforms/powermac/feature.c
@@ -21,6 +21,8 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/spinlock.h>
 #include <linux/adb.h>
 #include <linux/pmu.h>
@@ -2191,7 +2193,11 @@ static struct pmac_mb_def pmac_mb_defs[] = {
                 PMAC_TYPE_UNKNOWN_INTREPID,     intrepid_features,
                 PMAC_MB_MAY_SLEEP,
         },
-        {       "iMac,1",                       "iMac (first generation)",
+        {       "PowerMac10,2",                 "Mac mini (Late 2005)",
+                PMAC_TYPE_UNKNOWN_INTREPID,     intrepid_features,
+                PMAC_MB_MAY_SLEEP,
+        },
+        {       "iMac,1",                       "iMac (first generation)",
                 PMAC_TYPE_ORIG_IMAC,            paddington_features,
                 0
         },
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 630a533d0e59..890d5f72b198 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -46,6 +46,10 @@ struct pmac_irq_hw {
         unsigned int    level;
 };
 
+/* Workaround flags for 32bit powermac machines */
+unsigned int of_irq_workarounds;
+struct device_node *of_irq_dflt_pic;
+
 /* Default addresses */
 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
 
@@ -428,6 +432,42 @@ static void __init pmac_pic_probe_oldstyle(void)
         setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
 #endif
 }
+
+int of_irq_map_oldworld(struct device_node *device, int index,
+                        struct of_irq *out_irq)
+{
+        const u32 *ints = NULL;
+        int intlen;
+
+        /*
+         * Old machines just have a list of interrupt numbers
+         * and no interrupt-controller nodes. We also have dodgy
+         * cases where the APPL,interrupts property is completely
+         * missing behind pci-pci bridges and we have to get it
+         * from the parent (the bridge itself, as apple just wired
+         * everything together on these)
+         */
+        while (device) {
+                ints = of_get_property(device, "AAPL,interrupts", &intlen);
+                if (ints != NULL)
+                        break;
+                device = device->parent;
+                if (device && strcmp(device->type, "pci") != 0)
+                        break;
+        }
+        if (ints == NULL)
+                return -EINVAL;
+        intlen /= sizeof(u32);
+
+        if (index >= intlen)
+                return -EINVAL;
+
+        out_irq->controller = NULL;
+        out_irq->specifier[0] = ints[index];
+        out_irq->size = 1;
+
+        return 0;
+}
 #endif /* CONFIG_PPC32 */
 
 static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
@@ -559,19 +599,39 @@ static int __init pmac_pic_probe_mpic(void)
 
 void __init pmac_pic_init(void)
 {
-        unsigned int flags = 0;
-
         /* We configure the OF parsing based on our oldworld vs. newworld
          * platform type and wether we were booted by BootX.
          */
 #ifdef CONFIG_PPC32
         if (!pmac_newworld)
-                flags |= OF_IMAP_OLDWORLD_MAC;
+                of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
         if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
-                flags |= OF_IMAP_NO_PHANDLE;
-#endif /* CONFIG_PPC_32 */
+                of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
 
-        of_irq_map_init(flags);
+        /* If we don't have phandles on a newworld, then try to locate a
+         * default interrupt controller (happens when booting with BootX).
+         * We do a first match here, hopefully, that only ever happens on
+         * machines with one controller.
+         */
+        if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
+                struct device_node *np;
+
+                for_each_node_with_property(np, "interrupt-controller") {
+                        /* Skip /chosen/interrupt-controller */
+                        if (strcmp(np->name, "chosen") == 0)
+                                continue;
+                        /* It seems like at least one person wants
+                         * to use BootX on a machine with an AppleKiwi
+                         * controller which happens to pretend to be an
+                         * interrupt controller too. */
+                        if (strcmp(np->name, "AppleKiwi") == 0)
+                                continue;
+                        /* I think we found one ! */
+                        of_irq_dflt_pic = np;
+                        break;
+                }
+        }
+#endif /* CONFIG_PPC32 */
 
         /* We first try to detect Apple's new Core99 chipset, since mac-io
          * is quite different on those machines and contains an IBM MPIC2.
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 2c0ed87f2024..3124cf791ebb 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -136,7 +136,7 @@ static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
          * As lv1_read_htab_entries() does not give us the RPN, we can
          * not synthesize the new hpte_r value here, and therefore can
          * not update the hpte with lv1_insert_htab_entry(), so we
-         * insted invalidate it and ask the caller to update it via
+         * instead invalidate it and ask the caller to update it via
          * ps3_hpte_insert() by returning a -1 value.
          */
         if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 3dbef309bc8d..046ace9c4381 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -26,3 +26,7 @@ obj-$(CONFIG_HCALL_STATS)	+= hvCall_inst.o
 obj-$(CONFIG_PHYP_DUMP) += phyp_dump.o
 obj-$(CONFIG_CMM)               += cmm.o
 obj-$(CONFIG_DTL)               += dtl.o
+
+ifeq ($(CONFIG_PPC_PSERIES),y)
+obj-$(CONFIG_SUSPEND)           += suspend.o
+endif
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index d71e58584086..227c1c3d585e 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -463,6 +463,7 @@ static int dlpar_offline_cpu(struct device_node *dn)
                                 break;
 
                         if (get_cpu_current_state(cpu) == CPU_STATE_ONLINE) {
+                                set_preferred_offline_state(cpu, CPU_STATE_OFFLINE);
                                 cpu_maps_update_done();
                                 rc = cpu_down(cpu);
                                 if (rc)
diff --git a/arch/powerpc/platforms/pseries/eeh_cache.c b/arch/powerpc/platforms/pseries/eeh_cache.c
index 30b987b73c20..8ed0d2d0e1b5 100644
--- a/arch/powerpc/platforms/pseries/eeh_cache.c
+++ b/arch/powerpc/platforms/pseries/eeh_cache.c
@@ -288,8 +288,7 @@ void __init pci_addr_cache_build(void)
 
         spin_lock_init(&pci_io_addr_cache_root.piar_lock);
 
-        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-
+        for_each_pci_dev(dev) {
                 pci_addr_cache_insert_device(dev);
 
                 dn = pci_device_to_OF_node(dev);
diff --git a/arch/powerpc/platforms/pseries/event_sources.c b/arch/powerpc/platforms/pseries/event_sources.c
index e889c9d9586a..2605c310166a 100644
--- a/arch/powerpc/platforms/pseries/event_sources.c
+++ b/arch/powerpc/platforms/pseries/event_sources.c
@@ -41,9 +41,12 @@ void request_event_sources_irqs(struct device_node *np,
                         if (count > 15)
                                 break;
                         virqs[count] = irq_create_mapping(NULL, *(opicprop++));
-                        if (virqs[count] == NO_IRQ)
-                                printk(KERN_ERR "Unable to allocate interrupt "
-                                       "number for %s\n", np->full_name);
+                        if (virqs[count] == NO_IRQ) {
+                                pr_err("event-sources: Unable to allocate "
+                                       "interrupt number for %s\n",
+                                       np->full_name);
+                                WARN_ON(1);
+                        }
                         else
                                 count++;
 
@@ -59,9 +62,12 @@ void request_event_sources_irqs(struct device_node *np,
                         virqs[count] = irq_create_of_mapping(oirq.controller,
                                                             oirq.specifier,
                                                             oirq.size);
-                        if (virqs[count] == NO_IRQ)
-                                printk(KERN_ERR "Unable to allocate interrupt "
-                                       "number for %s\n", np->full_name);
+                        if (virqs[count] == NO_IRQ) {
+                                pr_err("event-sources: Unable to allocate "
+                                       "interrupt number for %s\n",
+                                       np->full_name);
+                                WARN_ON(1);
+                        }
                         else
                                 count++;
                 }
@@ -70,8 +76,9 @@ void request_event_sources_irqs(struct device_node *np,
         /* Now request them */
         for (i = 0; i < count; i++) {
                 if (request_irq(virqs[i], handler, 0, name, NULL)) {
-                        printk(KERN_ERR "Unable to request interrupt %d for "
-                               "%s\n", virqs[i], np->full_name);
+                        pr_err("event-sources: Unable to request interrupt "
+                               "%d for %s\n", virqs[i], np->full_name);
+                        WARN_ON(1);
                         return;
                 }
         }
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 8f85f399ab9f..fd50ccd4bac1 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -116,6 +116,9 @@ static void pseries_mach_cpu_die(void)
 
         if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) {
                 set_cpu_current_state(cpu, CPU_STATE_INACTIVE);
+                if (ppc_md.suspend_disable_cpu)
+                        ppc_md.suspend_disable_cpu();
+
                 cede_latency_hint = 2;
 
                 get_lppaca()->idle = 1;
@@ -190,12 +193,12 @@ static void pseries_cpu_die(unsigned int cpu)
 
         if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) {
                 cpu_status = 1;
-                for (tries = 0; tries < 1000; tries++) {
+                for (tries = 0; tries < 5000; tries++) {
                         if (get_cpu_current_state(cpu) == CPU_STATE_INACTIVE) {
                                 cpu_status = 0;
                                 break;
                         }
-                        cpu_relax();
+                        msleep(1);
                 }
         } else if (get_preferred_offline_state(cpu) == CPU_STATE_OFFLINE) {
 
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 41a3e9a039ed..a4fc6da87c2e 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -61,7 +61,6 @@ static int ras_check_exception_token;
 
 #define EPOW_SENSOR_TOKEN       9
 #define EPOW_SENSOR_INDEX       0
-#define RAS_VECTOR_OFFSET       0x500
 
 static irqreturn_t ras_epow_interrupt(int irq, void *dev_id);
 static irqreturn_t ras_error_interrupt(int irq, void *dev_id);
@@ -121,7 +120,7 @@ static irqreturn_t ras_epow_interrupt(int irq, void *dev_id)
         spin_lock(&ras_log_buf_lock);
 
         status = rtas_call(ras_check_exception_token, 6, 1, NULL,
-                           RAS_VECTOR_OFFSET,
+                           RTAS_VECTOR_EXTERNAL_INTERRUPT,
                            irq_map[irq].hwirq,
                            RTAS_EPOW_WARNING | RTAS_POWERMGM_EVENTS,
                            critical, __pa(&ras_log_buf),
@@ -156,7 +155,7 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id)
         spin_lock(&ras_log_buf_lock);
 
         status = rtas_call(ras_check_exception_token, 6, 1, NULL,
-                           RAS_VECTOR_OFFSET,
+                           RTAS_VECTOR_EXTERNAL_INTERRUPT,
                            irq_map[irq].hwirq,
                            RTAS_INTERNAL_ERROR, 1 /*Time Critical */,
                            __pa(&ras_log_buf),
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index 1a58637bcea5..57ddbb43b33a 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -118,12 +118,10 @@ static int pSeries_reconfig_add_node(const char *path, struct property *proplist
         if (!np)
                 goto out_err;
 
-        np->full_name = kmalloc(strlen(path) + 1, GFP_KERNEL);
+        np->full_name = kstrdup(path, GFP_KERNEL);
         if (!np->full_name)
                 goto out_err;
 
-        strcpy(np->full_name, path);
-
         np->properties = proplist;
         of_node_set_flag(np, OF_DYNAMIC);
         kref_init(&np->kref);
diff --git a/arch/powerpc/platforms/pseries/suspend.c b/arch/powerpc/platforms/pseries/suspend.c
new file mode 100644
index 000000000000..ed72098bb4e3
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/suspend.c
@@ -0,0 +1,214 @@
+/*
+  * Copyright (C) 2010 Brian King IBM Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+  */
+
+#include <linux/delay.h>
+#include <linux/suspend.h>
+#include <asm/firmware.h>
+#include <asm/hvcall.h>
+#include <asm/machdep.h>
+#include <asm/mmu.h>
+#include <asm/rtas.h>
+
+static u64 stream_id;
+static struct sys_device suspend_sysdev;
+static DECLARE_COMPLETION(suspend_work);
+static struct rtas_suspend_me_data suspend_data;
+static atomic_t suspending;
+
+/**
+ * pseries_suspend_begin - First phase of hibernation
+ *
+ * Check to ensure we are in a valid state to hibernate
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_suspend_begin(suspend_state_t state)
+{
+        long vasi_state, rc;
+        unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
+
+        /* Make sure the state is valid */
+        rc = plpar_hcall(H_VASI_STATE, retbuf, stream_id);
+
+        vasi_state = retbuf[0];
+
+        if (rc) {
+                pr_err("pseries_suspend_begin: vasi_state returned %ld\n",rc);
+                return rc;
+        } else if (vasi_state == H_VASI_ENABLED) {
+                return -EAGAIN;
+        } else if (vasi_state != H_VASI_SUSPENDING) {
+                pr_err("pseries_suspend_begin: vasi_state returned state %ld\n",
+                       vasi_state);
+                return -EIO;
+        }
+
+        return 0;
+}
+
+/**
+ * pseries_suspend_cpu - Suspend a single CPU
+ *
+ * Makes the H_JOIN call to suspend the CPU
+ *
+ **/
+static int pseries_suspend_cpu(void)
+{
+        if (atomic_read(&suspending))
+                return rtas_suspend_cpu(&suspend_data);
+        return 0;
+}
+
+/**
+ * pseries_suspend_enter - Final phase of hibernation
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_suspend_enter(suspend_state_t state)
+{
+        int rc = rtas_suspend_last_cpu(&suspend_data);
+
+        atomic_set(&suspending, 0);
+        atomic_set(&suspend_data.done, 1);
+        return rc;
+}
+
+/**
+ * pseries_prepare_late - Prepare to suspend all other CPUs
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_prepare_late(void)
+{
+        atomic_set(&suspending, 1);
+        atomic_set(&suspend_data.working, 0);
+        atomic_set(&suspend_data.done, 0);
+        atomic_set(&suspend_data.error, 0);
+        suspend_data.complete = &suspend_work;
+        INIT_COMPLETION(suspend_work);
+        return 0;
+}
+
+/**
+ * store_hibernate - Initiate partition hibernation
+ * @classdev:   sysdev class struct
+ * @attr:               class device attribute struct
+ * @buf:                buffer
+ * @count:              buffer size
+ *
+ * Write the stream ID received from the HMC to this file
+ * to trigger hibernating the partition
+ *
+ * Return value:
+ *      number of bytes printed to buffer / other on failure
+ **/
+static ssize_t store_hibernate(struct sysdev_class *classdev,
+                               struct sysdev_class_attribute *attr,
+                               const char *buf, size_t count)
+{
+        int rc;
+
+        if (!capable(CAP_SYS_ADMIN))
+                return -EPERM;
+
+        stream_id = simple_strtoul(buf, NULL, 16);
+
+        do {
+                rc = pseries_suspend_begin(PM_SUSPEND_MEM);
+                if (rc == -EAGAIN)
+                        ssleep(1);
+        } while (rc == -EAGAIN);
+
+        if (!rc)
+                rc = pm_suspend(PM_SUSPEND_MEM);
+
+        stream_id = 0;
+
+        if (!rc)
+                rc = count;
+        return rc;
+}
+
+static SYSDEV_CLASS_ATTR(hibernate, S_IWUSR, NULL, store_hibernate);
+
+static struct sysdev_class suspend_sysdev_class = {
+        .name = "power",
+};
+
+static struct platform_suspend_ops pseries_suspend_ops = {
+        .valid          = suspend_valid_only_mem,
+        .begin          = pseries_suspend_begin,
+        .prepare_late   = pseries_prepare_late,
+        .enter          = pseries_suspend_enter,
+};
+
+/**
+ * pseries_suspend_sysfs_register - Register with sysfs
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_suspend_sysfs_register(struct sys_device *sysdev)
+{
+        int rc;
+
+        if ((rc = sysdev_class_register(&suspend_sysdev_class)))
+                return rc;
+
+        sysdev->id = 0;
+        sysdev->cls = &suspend_sysdev_class;
+
+        if ((rc = sysdev_class_create_file(&suspend_sysdev_class, &attr_hibernate)))
+                goto class_unregister;
+
+        return 0;
+
+class_unregister:
+        sysdev_class_unregister(&suspend_sysdev_class);
+        return rc;
+}
+
+/**
+ * pseries_suspend_init - initcall for pSeries suspend
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int __init pseries_suspend_init(void)
+{
+        int rc;
+
+        if (!machine_is(pseries) || !firmware_has_feature(FW_FEATURE_LPAR))
+                return 0;
+
+        suspend_data.token = rtas_token("ibm,suspend-me");
+        if (suspend_data.token == RTAS_UNKNOWN_SERVICE)
+                return 0;
+
+        if ((rc = pseries_suspend_sysfs_register(&suspend_sysdev)))
+                return rc;
+
+        ppc_md.suspend_disable_cpu = pseries_suspend_cpu;
+        suspend_set_ops(&pseries_suspend_ops);
+        return 0;
+}
+
+__initcall(pseries_suspend_init);
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index f19d19468393..5b22b07c8f67 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -549,8 +549,6 @@ static irqreturn_t xics_ipi_dispatch(int cpu)
 {
         unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
 
-        WARN_ON(cpu_is_offline(cpu));
-
         mb();   /* order mmio clearing qirr */
         while (*tgt) {
                 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
diff --git a/arch/powerpc/sysdev/axonram.c b/arch/powerpc/sysdev/axonram.c
index 402d2212162f..2659a60bd7b8 100644
--- a/arch/powerpc/sysdev/axonram.c
+++ b/arch/powerpc/sysdev/axonram.c
@@ -60,7 +60,7 @@
 static int azfs_major, azfs_minor;
 
 struct axon_ram_bank {
-        struct of_device        *device;
+        struct platform_device  *device;
         struct gendisk          *disk;
         unsigned int            irq_id;
         unsigned long           ph_addr;
@@ -72,7 +72,7 @@ struct axon_ram_bank {
 static ssize_t
 axon_ram_sysfs_ecc(struct device *dev, struct device_attribute *attr, char *buf)
 {
-        struct of_device *device = to_of_device(dev);
+        struct platform_device *device = to_platform_device(dev);
         struct axon_ram_bank *bank = device->dev.platform_data;
 
         BUG_ON(!bank);
@@ -90,7 +90,7 @@ static DEVICE_ATTR(ecc, S_IRUGO, axon_ram_sysfs_ecc, NULL);
 static irqreturn_t
 axon_ram_irq_handler(int irq, void *dev)
 {
-        struct of_device *device = dev;
+        struct platform_device *device = dev;
         struct axon_ram_bank *bank = device->dev.platform_data;
 
         BUG_ON(!bank);
@@ -174,8 +174,8 @@ static const struct block_device_operations axon_ram_devops = {
  * axon_ram_probe - probe() method for platform driver
  * @device, @device_id: see of_platform_driver method
  */
-static int
-axon_ram_probe(struct of_device *device, const struct of_device_id *device_id)
+static int axon_ram_probe(struct platform_device *device,
+                          const struct of_device_id *device_id)
 {
         static int axon_ram_bank_id = -1;
         struct axon_ram_bank *bank;
@@ -304,7 +304,7 @@ failed:
  * @device: see of_platform_driver method
  */
 static int
-axon_ram_remove(struct of_device *device)
+axon_ram_remove(struct platform_device *device)
 {
         struct axon_ram_bank *bank = device->dev.platform_data;
 
diff --git a/arch/powerpc/sysdev/bestcomm/bestcomm.c b/arch/powerpc/sysdev/bestcomm/bestcomm.c
index a7c5c470af14..650256115064 100644
--- a/arch/powerpc/sysdev/bestcomm/bestcomm.c
+++ b/arch/powerpc/sysdev/bestcomm/bestcomm.c
@@ -365,8 +365,8 @@ bcom_engine_cleanup(void)
 /* OF platform driver                                                       */
 /* ======================================================================== */
 
-static int __devinit
-mpc52xx_bcom_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit mpc52xx_bcom_probe(struct platform_device *op,
+                                        const struct of_device_id *match)
 {
         struct device_node *ofn_sram;
         struct resource res_bcom;
@@ -461,8 +461,7 @@ error_ofput:
 }
 
 
-static int
-mpc52xx_bcom_remove(struct of_device *op)
+static int mpc52xx_bcom_remove(struct platform_device *op)
 {
         /* Clean up the engine */
         bcom_engine_cleanup();
diff --git a/arch/powerpc/sysdev/bestcomm/sram.c b/arch/powerpc/sysdev/bestcomm/sram.c
index 5d74ef7a651f..1225012a681a 100644
--- a/arch/powerpc/sysdev/bestcomm/sram.c
+++ b/arch/powerpc/sysdev/bestcomm/sram.c
@@ -11,6 +11,7 @@
  * kind, whether express or implied.
  */
 
+#include <linux/err.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/slab.h>
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 8d103ca6d6ab..00852124ff4a 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -621,7 +621,6 @@ int cpm1_gpiochip_add16(struct device_node *np)
 {
         struct cpm1_gpio16_chip *cpm1_gc;
         struct of_mm_gpio_chip *mm_gc;
-        struct of_gpio_chip *of_gc;
         struct gpio_chip *gc;
 
         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
@@ -631,11 +630,9 @@ int cpm1_gpiochip_add16(struct device_node *np)
         spin_lock_init(&cpm1_gc->lock);
 
         mm_gc = &cpm1_gc->mm_gc;
-        of_gc = &mm_gc->of_gc;
-        gc = &of_gc->gc;
+        gc = &mm_gc->gc;
 
         mm_gc->save_regs = cpm1_gpio16_save_regs;
-        of_gc->gpio_cells = 2;
         gc->ngpio = 16;
         gc->direction_input = cpm1_gpio16_dir_in;
         gc->direction_output = cpm1_gpio16_dir_out;
@@ -745,7 +742,6 @@ int cpm1_gpiochip_add32(struct device_node *np)
 {
         struct cpm1_gpio32_chip *cpm1_gc;
         struct of_mm_gpio_chip *mm_gc;
-        struct of_gpio_chip *of_gc;
         struct gpio_chip *gc;
 
         cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
@@ -755,11 +751,9 @@ int cpm1_gpiochip_add32(struct device_node *np)
         spin_lock_init(&cpm1_gc->lock);
 
         mm_gc = &cpm1_gc->mm_gc;
-        of_gc = &mm_gc->of_gc;
-        gc = &of_gc->gc;
+        gc = &mm_gc->gc;
 
         mm_gc->save_regs = cpm1_gpio32_save_regs;
-        of_gc->gpio_cells = 2;
         gc->ngpio = 32;
         gc->direction_input = cpm1_gpio32_dir_in;
         gc->direction_output = cpm1_gpio32_dir_out;
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index 88b9812c854f..2b69aa0315b3 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -325,7 +325,6 @@ int cpm2_gpiochip_add32(struct device_node *np)
 {
         struct cpm2_gpio32_chip *cpm2_gc;
         struct of_mm_gpio_chip *mm_gc;
-        struct of_gpio_chip *of_gc;
         struct gpio_chip *gc;
 
         cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
@@ -335,11 +334,9 @@ int cpm2_gpiochip_add32(struct device_node *np)
         spin_lock_init(&cpm2_gc->lock);
 
         mm_gc = &cpm2_gc->mm_gc;
-        of_gc = &mm_gc->of_gc;
-        gc = &of_gc->gc;
+        gc = &mm_gc->gc;
 
         mm_gc->save_regs = cpm2_gpio32_save_regs;
-        of_gc->gpio_cells = 2;
         gc->ngpio = 32;
         gc->direction_input = cpm2_gpio32_dir_in;
         gc->direction_output = cpm2_gpio32_dir_out;
diff --git a/arch/powerpc/sysdev/fsl_gtm.c b/arch/powerpc/sysdev/fsl_gtm.c
index eca4545dd52e..7dd2885321ad 100644
--- a/arch/powerpc/sysdev/fsl_gtm.c
+++ b/arch/powerpc/sysdev/fsl_gtm.c
@@ -14,6 +14,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/list.h>
 #include <linux/io.h>
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 962c2d8dd8d9..87991d3abbab 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -250,7 +250,7 @@ unlock:
         raw_spin_unlock(&desc->lock);
 }
 
-static int fsl_of_msi_remove(struct of_device *ofdev)
+static int fsl_of_msi_remove(struct platform_device *ofdev)
 {
         struct fsl_msi *msi = ofdev->dev.platform_data;
         int virq, i;
@@ -274,7 +274,7 @@ static int fsl_of_msi_remove(struct of_device *ofdev)
         return 0;
 }
 
-static int __devinit fsl_of_msi_probe(struct of_device *dev,
+static int __devinit fsl_of_msi_probe(struct platform_device *dev,
                                 const struct of_device_id *match)
 {
         struct fsl_msi *msi;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 356c6a0e1b23..209384b6e039 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -412,6 +412,7 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
 
 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 9082eb921ad9..44de8559c975 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -58,7 +58,8 @@ static struct platform_suspend_ops pmc_suspend_ops = {
         .enter = pmc_suspend_enter,
 };
 
-static int pmc_probe(struct of_device *ofdev, const struct of_device_id *id)
+static int pmc_probe(struct platform_device *ofdev,
+                     const struct of_device_id *id)
 {
         pmc_regs = of_iomap(ofdev->dev.of_node, 0);
         if (!pmc_regs)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 30e1626b2e85..8bd86530ee25 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1338,7 +1338,7 @@ static inline void fsl_rio_info(struct device *dev, u32 ccsr)
  * master port with system-specific info, and registers the
  * master port with the RapidIO subsystem.
  */
-int fsl_rio_setup(struct of_device *dev)
+int fsl_rio_setup(struct platform_device *dev)
 {
         struct rio_ops *ops;
         struct rio_mport *port;
@@ -1536,7 +1536,7 @@ err_ops:
 
 /* The probe function for RapidIO peer-to-peer network.
  */
-static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev,
+static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev,
                                      const struct of_device_id *match)
 {
         int rc;
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 42381bb6cd51..53609489a62b 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -30,6 +30,7 @@ struct platform_diu_data_ops {
         void (*set_pixel_clock) (unsigned int pixclock);
         ssize_t (*show_monitor_port) (int monitor_port, char *buf);
         int (*set_sysfs_monitor_port) (int val);
+        void (*release_bootmem) (void);
 };
 
 extern struct platform_diu_data_ops diu_ops;
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index 83f519655fac..2b69084d0f0c 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -257,7 +257,6 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
 {
         struct mpc8xxx_gpio_chip *mpc8xxx_gc;
         struct of_mm_gpio_chip *mm_gc;
-        struct of_gpio_chip *of_gc;
         struct gpio_chip *gc;
         unsigned hwirq;
         int ret;
@@ -271,11 +270,9 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
         spin_lock_init(&mpc8xxx_gc->lock);
 
         mm_gc = &mpc8xxx_gc->mm_gc;
-        of_gc = &mm_gc->of_gc;
-        gc = &of_gc->gc;
+        gc = &mm_gc->gc;
 
         mm_gc->save_regs = mpc8xxx_gpio_save_regs;
-        of_gc->gpio_cells = 2;
         gc->ngpio = MPC8XXX_GPIO_PINS;
         gc->direction_input = mpc8xxx_gpio_dir_in;
         gc->direction_output = mpc8xxx_gpio_dir_out;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 20b73c025a45..7c1342618a30 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1636,6 +1636,24 @@ void __devinit smp_mpic_setup_cpu(int cpu)
 {
         mpic_setup_this_cpu();
 }
+
+void mpic_reset_core(int cpu)
+{
+        struct mpic *mpic = mpic_primary;
+        u32 pir;
+        int cpuid = get_hard_smp_processor_id(cpu);
+
+        /* Set target bit for core reset */
+        pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+        pir |= (1 << cpuid);
+        mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
+        mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+
+        /* Restore target bit after reset complete */
+        pir &= ~(1 << cpuid);
+        mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
+        mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+}
 #endif /* CONFIG_SMP */
 
 #ifdef CONFIG_PM
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index eff433c322a0..e4a6df77b8d7 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -37,5 +37,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
 extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type);
 extern void mpic_set_vector(unsigned int virq, unsigned int vector);
 extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask);
+extern void mpic_reset_core(int cpu);
 
 #endif /* _POWERPC_SYSDEV_MPIC_H */
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index 31acd3b1718b..1398bc454999 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -20,12 +20,7 @@
 
 #include <asm/prom.h>
 
-/*
- * These functions provide the necessary setup for the mv64x60 drivers.
- * These drivers are unusual in that they work on both the MIPS and PowerPC
- * architectures.  Because of that, the drivers do not support the normal
- * PowerPC of_platform_bus_type.  They support platform_bus_type instead.
- */
+/* These functions provide the necessary setup for the mv64x60 drivers. */
 
 static struct of_device_id __initdata of_mv64x60_devices[] = {
         { .compatible = "marvell,mv64306-devctrl", },
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index 198f288570cc..77bb3f4d530a 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -73,7 +73,6 @@ static struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */
         .attr = {
                 .name = "hs_reg",
                 .mode = S_IRUGO | S_IWUSR,
-                .owner = THIS_MODULE,
         },
         .size  = MV64X60_VAL_LEN_MAX,
         .read  = mv64x60_hs_reg_read,
diff --git a/arch/powerpc/sysdev/pmi.c b/arch/powerpc/sysdev/pmi.c
index d07137a07d75..24a0bb955b18 100644
--- a/arch/powerpc/sysdev/pmi.c
+++ b/arch/powerpc/sysdev/pmi.c
@@ -43,7 +43,7 @@ struct pmi_data {
         struct mutex            msg_mutex;
         pmi_message_t           msg;
         struct completion       *completion;
-        struct of_device        *dev;
+        struct platform_device  *dev;
         int                     irq;
         u8 __iomem              *pmi_reg;
         struct work_struct      work;
@@ -121,7 +121,7 @@ static void pmi_notify_handlers(struct work_struct *work)
         spin_unlock(&data->handler_spinlock);
 }
 
-static int pmi_of_probe(struct of_device *dev,
+static int pmi_of_probe(struct platform_device *dev,
                         const struct of_device_id *match)
 {
         struct device_node *np = dev->dev.of_node;
@@ -185,7 +185,7 @@ out:
         return rc;
 }
 
-static int pmi_of_remove(struct of_device *dev)
+static int pmi_of_remove(struct platform_device *dev)
 {
         struct pmi_handler *handler, *tmp;
 
diff --git a/arch/powerpc/sysdev/ppc4xx_gpio.c b/arch/powerpc/sysdev/ppc4xx_gpio.c
index 3812fc366bec..fc65ad1b3293 100644
--- a/arch/powerpc/sysdev/ppc4xx_gpio.c
+++ b/arch/powerpc/sysdev/ppc4xx_gpio.c
@@ -181,7 +181,6 @@ static int __init ppc4xx_add_gpiochips(void)
                 int ret;
                 struct ppc4xx_gpio_chip *ppc4xx_gc;
                 struct of_mm_gpio_chip *mm_gc;
-                struct of_gpio_chip *of_gc;
                 struct gpio_chip *gc;
 
                 ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
@@ -193,10 +192,8 @@ static int __init ppc4xx_add_gpiochips(void)
                 spin_lock_init(&ppc4xx_gc->lock);
 
                 mm_gc = &ppc4xx_gc->mm_gc;
-                of_gc = &mm_gc->of_gc;
-                gc = &of_gc->gc;
+                gc = &mm_gc->gc;
 
-                of_gc->gpio_cells = 2;
                 gc->ngpio = 32;
                 gc->direction_input = ppc4xx_gpio_dir_in;
                 gc->direction_output = ppc4xx_gpio_dir_out;
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
index dc8f8d618074..36bf845df127 100644
--- a/arch/powerpc/sysdev/qe_lib/gpio.c
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -138,8 +138,8 @@ struct qe_pin {
 struct qe_pin *qe_pin_request(struct device_node *np, int index)
 {
         struct qe_pin *qe_pin;
-        struct device_node *gc;
-        struct of_gpio_chip *of_gc = NULL;
+        struct device_node *gpio_np;
+        struct gpio_chip *gc;
         struct of_mm_gpio_chip *mm_gc;
         struct qe_gpio_chip *qe_gc;
         int err;
@@ -155,40 +155,40 @@ struct qe_pin *qe_pin_request(struct device_node *np, int index)
         }
 
         err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
-                                          &gc, &gpio_spec);
+                                          &gpio_np, &gpio_spec);
         if (err) {
                 pr_debug("%s: can't parse gpios property\n", __func__);
                 goto err0;
         }
 
-        if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
+        if (!of_device_is_compatible(gpio_np, "fsl,mpc8323-qe-pario-bank")) {
                 pr_debug("%s: tried to get a non-qe pin\n", __func__);
                 err = -EINVAL;
                 goto err1;
         }
 
-        of_gc = gc->data;
-        if (!of_gc) {
+        gc = of_node_to_gpiochip(gpio_np);
+        if (!gc) {
                 pr_debug("%s: gpio controller %s isn't registered\n",
-                         np->full_name, gc->full_name);
+                         np->full_name, gpio_np->full_name);
                 err = -ENODEV;
                 goto err1;
         }
 
-        gpio_cells = of_get_property(gc, "#gpio-cells", &size);
+        gpio_cells = of_get_property(gpio_np, "#gpio-cells", &size);
         if (!gpio_cells || size != sizeof(*gpio_cells) ||
-                        *gpio_cells != of_gc->gpio_cells) {
+                        *gpio_cells != gc->of_gpio_n_cells) {
                 pr_debug("%s: wrong #gpio-cells for %s\n",
-                         np->full_name, gc->full_name);
+                         np->full_name, gpio_np->full_name);
                 err = -EINVAL;
                 goto err1;
         }
 
-        err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
+        err = gc->of_xlate(gc, np, gpio_spec, NULL);
         if (err < 0)
                 goto err1;
 
-        mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
+        mm_gc = to_of_mm_gpio_chip(gc);
         qe_gc = to_qe_gpio_chip(mm_gc);
 
         spin_lock_irqsave(&qe_gc->lock, flags);
@@ -206,7 +206,7 @@ struct qe_pin *qe_pin_request(struct device_node *np, int index)
         if (!err)
                 return qe_pin;
 err1:
-        of_node_put(gc);
+        of_node_put(gpio_np);
 err0:
         kfree(qe_pin);
         pr_debug("%s failed with status %d\n", __func__, err);
@@ -307,7 +307,6 @@ static int __init qe_add_gpiochips(void)
                 int ret;
                 struct qe_gpio_chip *qe_gc;
                 struct of_mm_gpio_chip *mm_gc;
-                struct of_gpio_chip *of_gc;
                 struct gpio_chip *gc;
 
                 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
@@ -319,11 +318,9 @@ static int __init qe_add_gpiochips(void)
                 spin_lock_init(&qe_gc->lock);
 
                 mm_gc = &qe_gc->mm_gc;
-                of_gc = &mm_gc->of_gc;
-                gc = &of_gc->gc;
+                gc = &mm_gc->gc;
 
                 mm_gc->save_regs = qe_gpio_save_regs;
-                of_gc->gpio_cells = 2;
                 gc->ngpio = QE_PIO_PINS;
                 gc->direction_input = qe_gpio_dir_in;
                 gc->direction_output = qe_gpio_dir_out;
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 093e0ae1a941..3da8014931c9 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -651,14 +651,15 @@ unsigned int qe_get_num_of_snums(void)
 EXPORT_SYMBOL(qe_get_num_of_snums);
 
 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
-static int qe_resume(struct of_device *ofdev)
+static int qe_resume(struct platform_device *ofdev)
 {
         if (!qe_alive_during_sleep())
                 qe_reset();
         return 0;
 }
 
-static int qe_probe(struct of_device *ofdev, const struct of_device_id *id)
+static int qe_probe(struct platform_device *ofdev,
+                    const struct of_device_id *id)
 {
         return 0;
 }
diff --git a/arch/powerpc/sysdev/simple_gpio.c b/arch/powerpc/sysdev/simple_gpio.c
index d5fb173e588c..b6defda5ccc9 100644
--- a/arch/powerpc/sysdev/simple_gpio.c
+++ b/arch/powerpc/sysdev/simple_gpio.c
@@ -91,7 +91,6 @@ static int __init u8_simple_gpiochip_add(struct device_node *np)
         int ret;
         struct u8_gpio_chip *u8_gc;
         struct of_mm_gpio_chip *mm_gc;
-        struct of_gpio_chip *of_gc;
         struct gpio_chip *gc;
 
         u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
@@ -101,11 +100,9 @@ static int __init u8_simple_gpiochip_add(struct device_node *np)
         spin_lock_init(&u8_gc->lock);
 
         mm_gc = &u8_gc->mm_gc;
-        of_gc = &mm_gc->of_gc;
-        gc = &of_gc->gc;
+        gc = &mm_gc->gc;
 
         mm_gc->save_regs = u8_gpio_save_regs;
-        of_gc->gpio_cells = 2;
         gc->ngpio = 8;
         gc->direction_input = u8_gpio_dir_in;
         gc->direction_output = u8_gpio_dir_out;
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 8bad7d5f32af..0554445200bf 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -155,6 +155,9 @@ static int do_spu_cmd(void);
 #ifdef CONFIG_44x
 static void dump_tlb_44x(void);
 #endif
+#ifdef CONFIG_PPC_BOOK3E
+static void dump_tlb_book3e(void);
+#endif
 
 static int xmon_no_auto_backtrace;
 
@@ -888,6 +891,11 @@ cmds(struct pt_regs *excp)
                         dump_tlb_44x();
                         break;
 #endif
+#ifdef CONFIG_PPC_BOOK3E
+                case 'u':
+                        dump_tlb_book3e();
+                        break;
+#endif
                 default:
                         printf("Unrecognized command: ");
                         do {
@@ -2701,6 +2709,150 @@ static void dump_tlb_44x(void)
 }
 #endif /* CONFIG_44x */
 
+#ifdef CONFIG_PPC_BOOK3E
+static void dump_tlb_book3e(void)
+{
+        u32 mmucfg, pidmask, lpidmask;
+        u64 ramask;
+        int i, tlb, ntlbs, pidsz, lpidsz, rasz, lrat = 0;
+        int mmu_version;
+        static const char *pgsz_names[] = {
+                "  1K",
+                "  2K",
+                "  4K",
+                "  8K",
+                " 16K",
+                " 32K",
+                " 64K",
+                "128K",
+                "256K",
+                "512K",
+                "  1M",
+                "  2M",
+                "  4M",
+                "  8M",
+                " 16M",
+                " 32M",
+                " 64M",
+                "128M",
+                "256M",
+                "512M",
+                "  1G",
+                "  2G",
+                "  4G",
+                "  8G",
+                " 16G",
+                " 32G",
+                " 64G",
+                "128G",
+                "256G",
+                "512G",
+                "  1T",
+                "  2T",
+        };
+
+        /* Gather some infos about the MMU */
+        mmucfg = mfspr(SPRN_MMUCFG);
+        mmu_version = (mmucfg & 3) + 1;
+        ntlbs = ((mmucfg >> 2) & 3) + 1;
+        pidsz = ((mmucfg >> 6) & 0x1f) + 1;
+        lpidsz = (mmucfg >> 24) & 0xf;
+        rasz = (mmucfg >> 16) & 0x7f;
+        if ((mmu_version > 1) && (mmucfg & 0x10000))
+                lrat = 1;
+        printf("Book3E MMU MAV=%d.0,%d TLBs,%d-bit PID,%d-bit LPID,%d-bit RA\n",
+               mmu_version, ntlbs, pidsz, lpidsz, rasz);
+        pidmask = (1ul << pidsz) - 1;
+        lpidmask = (1ul << lpidsz) - 1;
+        ramask = (1ull << rasz) - 1;
+
+        for (tlb = 0; tlb < ntlbs; tlb++) {
+                u32 tlbcfg;
+                int nent, assoc, new_cc = 1;
+                printf("TLB %d:\n------\n", tlb);
+                switch(tlb) {
+                case 0:
+                        tlbcfg = mfspr(SPRN_TLB0CFG);
+                        break;
+                case 1:
+                        tlbcfg = mfspr(SPRN_TLB1CFG);
+                        break;
+                case 2:
+                        tlbcfg = mfspr(SPRN_TLB2CFG);
+                        break;
+                case 3:
+                        tlbcfg = mfspr(SPRN_TLB3CFG);
+                        break;
+                default:
+                        printf("Unsupported TLB number !\n");
+                        continue;
+                }
+                nent = tlbcfg & 0xfff;
+                assoc = (tlbcfg >> 24) & 0xff;
+                for (i = 0; i < nent; i++) {
+                        u32 mas0 = MAS0_TLBSEL(tlb);
+                        u32 mas1 = MAS1_TSIZE(BOOK3E_PAGESZ_4K);
+                        u64 mas2 = 0;
+                        u64 mas7_mas3;
+                        int esel = i, cc = i;
+
+                        if (assoc != 0) {
+                                cc = i / assoc;
+                                esel = i % assoc;
+                                mas2 = cc * 0x1000;
+                        }
+
+                        mas0 |= MAS0_ESEL(esel);
+                        mtspr(SPRN_MAS0, mas0);
+                        mtspr(SPRN_MAS1, mas1);
+                        mtspr(SPRN_MAS2, mas2);
+                        asm volatile("tlbre  0,0,0" : : : "memory");
+                        mas1 = mfspr(SPRN_MAS1);
+                        mas2 = mfspr(SPRN_MAS2);
+                        mas7_mas3 = mfspr(SPRN_MAS7_MAS3);
+                        if (assoc && (i % assoc) == 0)
+                                new_cc = 1;
+                        if (!(mas1 & MAS1_VALID))
+                                continue;
+                        if (assoc == 0)
+                                printf("%04x- ", i);
+                        else if (new_cc)
+                                printf("%04x-%c", cc, 'A' + esel);
+                        else
+                                printf("    |%c", 'A' + esel);
+                        new_cc = 0;
+                        printf(" %016llx %04x %s %c%c AS%c",
+                               mas2 & ~0x3ffull,
+                               (mas1 >> 16) & 0x3fff,
+                               pgsz_names[(mas1 >> 7) & 0x1f],
+                               mas1 & MAS1_IND ? 'I' : ' ',
+                               mas1 & MAS1_IPROT ? 'P' : ' ',
+                               mas1 & MAS1_TS ? '1' : '0');
+                        printf(" %c%c%c%c%c%c%c",
+                               mas2 & MAS2_X0 ? 'a' : ' ',
+                               mas2 & MAS2_X1 ? 'v' : ' ',
+                               mas2 & MAS2_W  ? 'w' : ' ',
+                               mas2 & MAS2_I  ? 'i' : ' ',
+                               mas2 & MAS2_M  ? 'm' : ' ',
+                               mas2 & MAS2_G  ? 'g' : ' ',
+                               mas2 & MAS2_E  ? 'e' : ' ');
+                        printf(" %016llx", mas7_mas3 & ramask & ~0x7ffull);
+                        if (mas1 & MAS1_IND)
+                                printf(" %s\n",
+                                       pgsz_names[(mas7_mas3 >> 1) & 0x1f]);
+                        else
+                                printf(" U%c%c%c S%c%c%c\n",
+                                       mas7_mas3 & MAS3_UX ? 'x' : ' ',
+                                       mas7_mas3 & MAS3_UW ? 'w' : ' ',
+                                       mas7_mas3 & MAS3_UR ? 'r' : ' ',
+                                       mas7_mas3 & MAS3_SX ? 'x' : ' ',
+                                       mas7_mas3 & MAS3_SW ? 'w' : ' ',
+                                       mas7_mas3 & MAS3_SR ? 'r' : ' ');
+                }
+        }
+}
+#endif /* CONFIG_PPC_BOOK3E */
+
 static void xmon_init(int enable)
 {
 #ifdef CONFIG_PPC_ISERIES
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index bee1c0f794cf..f0777a47e3a5 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -40,9 +40,6 @@ config ARCH_HAS_ILOG2_U64
 config GENERIC_HWEIGHT
         def_bool y
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_TIME_VSYSCALL
         def_bool y
 
diff --git a/arch/s390/Makefile b/arch/s390/Makefile
index 30c5f01f93b0..0c9e6c6d2a64 100644
--- a/arch/s390/Makefile
+++ b/arch/s390/Makefile
@@ -24,7 +24,8 @@ CHECKFLAGS	+= -D__s390__ -msize-long
 else
 LD_BFD          := elf64-s390
 LDFLAGS         := -m elf64_s390
-MODFLAGS        += -fpic -D__PIC__
+KBUILD_AFLAGS_MODULE += -fpic -D__PIC__
+KBUILD_CFLAGS_MODULE += -fpic -D__PIC__
 KBUILD_CFLAGS   += -m64
 KBUILD_AFLAGS   += -m64
 UTS_MACHINE     := s390x
diff --git a/arch/s390/appldata/appldata_net_sum.c b/arch/s390/appldata/appldata_net_sum.c
index 9a9586f4103f..f02e89ce4df1 100644
--- a/arch/s390/appldata/appldata_net_sum.c
+++ b/arch/s390/appldata/appldata_net_sum.c
@@ -85,7 +85,8 @@ static void appldata_get_net_sum_data(void *data)
 
         rcu_read_lock();
         for_each_netdev_rcu(&init_net, dev) {
-                const struct net_device_stats *stats = dev_get_stats(dev);
+                struct rtnl_link_stats64 temp;
+                const struct net_device_stats *stats = dev_get_stats(dev, &temp);
 
                 rx_packets += stats->rx_packets;
                 tx_packets += stats->tx_packets;
diff --git a/arch/s390/crypto/Makefile b/arch/s390/crypto/Makefile
index 6a1157fa4f98..1cf81d77c5a5 100644
--- a/arch/s390/crypto/Makefile
+++ b/arch/s390/crypto/Makefile
@@ -5,6 +5,6 @@
 obj-$(CONFIG_CRYPTO_SHA1_S390) += sha1_s390.o sha_common.o
 obj-$(CONFIG_CRYPTO_SHA256_S390) += sha256_s390.o sha_common.o
 obj-$(CONFIG_CRYPTO_SHA512_S390) += sha512_s390.o sha_common.o
-obj-$(CONFIG_CRYPTO_DES_S390) += des_s390.o des_check_key.o
+obj-$(CONFIG_CRYPTO_DES_S390) += des_s390.o
 obj-$(CONFIG_CRYPTO_AES_S390) += aes_s390.o
 obj-$(CONFIG_S390_PRNG) += prng.o
diff --git a/arch/s390/crypto/crypto_des.h b/arch/s390/crypto/crypto_des.h
index c964b64111dd..6210457ceebb 100644
--- a/arch/s390/crypto/crypto_des.h
+++ b/arch/s390/crypto/crypto_des.h
@@ -15,4 +15,4 @@
 
 extern int crypto_des_check_key(const u8*, unsigned int, u32*);
 
-#endif //__CRYPTO_DES_H__
+#endif /*__CRYPTO_DES_H__*/
diff --git a/arch/s390/crypto/des_s390.c b/arch/s390/crypto/des_s390.c
index 2bc479ab3a66..cc5420118393 100644
--- a/arch/s390/crypto/des_s390.c
+++ b/arch/s390/crypto/des_s390.c
@@ -14,32 +14,21 @@
  *
  */
 
-#include <crypto/algapi.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/crypto.h>
+#include <crypto/algapi.h>
+#include <crypto/des.h>
 
 #include "crypt_s390.h"
-#include "crypto_des.h"
-
-#define DES_BLOCK_SIZE 8
-#define DES_KEY_SIZE 8
-
-#define DES3_128_KEY_SIZE       (2 * DES_KEY_SIZE)
-#define DES3_128_BLOCK_SIZE     DES_BLOCK_SIZE
 
 #define DES3_192_KEY_SIZE       (3 * DES_KEY_SIZE)
-#define DES3_192_BLOCK_SIZE     DES_BLOCK_SIZE
 
 struct crypt_s390_des_ctx {
         u8 iv[DES_BLOCK_SIZE];
         u8 key[DES_KEY_SIZE];
 };
 
-struct crypt_s390_des3_128_ctx {
-        u8 iv[DES_BLOCK_SIZE];
-        u8 key[DES3_128_KEY_SIZE];
-};
-
 struct crypt_s390_des3_192_ctx {
         u8 iv[DES_BLOCK_SIZE];
         u8 key[DES3_192_KEY_SIZE];
@@ -50,13 +39,16 @@ static int des_setkey(struct crypto_tfm *tfm, const u8 *key,
 {
         struct crypt_s390_des_ctx *dctx = crypto_tfm_ctx(tfm);
         u32 *flags = &tfm->crt_flags;
-        int ret;
+        u32 tmp[DES_EXPKEY_WORDS];
 
-        /* test if key is valid (not a weak key) */
-        ret = crypto_des_check_key(key, keylen, flags);
-        if (ret == 0)
-                memcpy(dctx->key, key, keylen);
-        return ret;
+        /* check for weak keys */
+        if (!des_ekey(tmp, key) && (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
+                *flags |= CRYPTO_TFM_RES_WEAK_KEY;
+                return -EINVAL;
+        }
+
+        memcpy(dctx->key, key, keylen);
+        return 0;
 }
 
 static void des_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
@@ -237,165 +229,6 @@ static struct crypto_alg cbc_des_alg = {
  *   complementation keys.  Any weakness is obviated by the use of
  *   multiple keys.
  *
- *   However, if the two  independent 64-bit keys are equal,
- *   then the DES3 operation is simply the same as DES.
- *   Implementers MUST reject keys that exhibit this property.
- *
- */
-static int des3_128_setkey(struct crypto_tfm *tfm, const u8 *key,
-                           unsigned int keylen)
-{
-        int i, ret;
-        struct crypt_s390_des3_128_ctx *dctx = crypto_tfm_ctx(tfm);
-        const u8 *temp_key = key;
-        u32 *flags = &tfm->crt_flags;
-
-        if (!(memcmp(key, &key[DES_KEY_SIZE], DES_KEY_SIZE)) &&
-            (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
-                *flags |= CRYPTO_TFM_RES_WEAK_KEY;
-                return -EINVAL;
-        }
-        for (i = 0; i < 2; i++, temp_key += DES_KEY_SIZE) {
-                ret = crypto_des_check_key(temp_key, DES_KEY_SIZE, flags);
-                if (ret < 0)
-                        return ret;
-        }
-        memcpy(dctx->key, key, keylen);
-        return 0;
-}
-
-static void des3_128_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
-{
-        struct crypt_s390_des3_128_ctx *dctx = crypto_tfm_ctx(tfm);
-
-        crypt_s390_km(KM_TDEA_128_ENCRYPT, dctx->key, dst, (void*)src,
-                      DES3_128_BLOCK_SIZE);
-}
-
-static void des3_128_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
-{
-        struct crypt_s390_des3_128_ctx *dctx = crypto_tfm_ctx(tfm);
-
-        crypt_s390_km(KM_TDEA_128_DECRYPT, dctx->key, dst, (void*)src,
-                      DES3_128_BLOCK_SIZE);
-}
-
-static struct crypto_alg des3_128_alg = {
-        .cra_name               =       "des3_ede128",
-        .cra_driver_name        =       "des3_ede128-s390",
-        .cra_priority           =       CRYPT_S390_PRIORITY,
-        .cra_flags              =       CRYPTO_ALG_TYPE_CIPHER,
-        .cra_blocksize          =       DES3_128_BLOCK_SIZE,
-        .cra_ctxsize            =       sizeof(struct crypt_s390_des3_128_ctx),
-        .cra_module             =       THIS_MODULE,
-        .cra_list               =       LIST_HEAD_INIT(des3_128_alg.cra_list),
-        .cra_u                  =       {
-                .cipher = {
-                        .cia_min_keysize        =       DES3_128_KEY_SIZE,
-                        .cia_max_keysize        =       DES3_128_KEY_SIZE,
-                        .cia_setkey             =       des3_128_setkey,
-                        .cia_encrypt            =       des3_128_encrypt,
-                        .cia_decrypt            =       des3_128_decrypt,
-                }
-        }
-};
-
-static int ecb_des3_128_encrypt(struct blkcipher_desc *desc,
-                                struct scatterlist *dst,
-                                struct scatterlist *src, unsigned int nbytes)
-{
-        struct crypt_s390_des3_128_ctx *sctx = crypto_blkcipher_ctx(desc->tfm);
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_desall_crypt(desc, KM_TDEA_128_ENCRYPT, sctx->key, &walk);
-}
-
-static int ecb_des3_128_decrypt(struct blkcipher_desc *desc,
-                                struct scatterlist *dst,
-                                struct scatterlist *src, unsigned int nbytes)
-{
-        struct crypt_s390_des3_128_ctx *sctx = crypto_blkcipher_ctx(desc->tfm);
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_desall_crypt(desc, KM_TDEA_128_DECRYPT, sctx->key, &walk);
-}
-
-static struct crypto_alg ecb_des3_128_alg = {
-        .cra_name               =       "ecb(des3_ede128)",
-        .cra_driver_name        =       "ecb-des3_ede128-s390",
-        .cra_priority           =       CRYPT_S390_COMPOSITE_PRIORITY,
-        .cra_flags              =       CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          =       DES3_128_BLOCK_SIZE,
-        .cra_ctxsize            =       sizeof(struct crypt_s390_des3_128_ctx),
-        .cra_type               =       &crypto_blkcipher_type,
-        .cra_module             =       THIS_MODULE,
-        .cra_list               =       LIST_HEAD_INIT(
-                                                ecb_des3_128_alg.cra_list),
-        .cra_u                  =       {
-                .blkcipher = {
-                        .min_keysize            =       DES3_128_KEY_SIZE,
-                        .max_keysize            =       DES3_128_KEY_SIZE,
-                        .setkey                 =       des3_128_setkey,
-                        .encrypt                =       ecb_des3_128_encrypt,
-                        .decrypt                =       ecb_des3_128_decrypt,
-                }
-        }
-};
-
-static int cbc_des3_128_encrypt(struct blkcipher_desc *desc,
-                                struct scatterlist *dst,
-                                struct scatterlist *src, unsigned int nbytes)
-{
-        struct crypt_s390_des3_128_ctx *sctx = crypto_blkcipher_ctx(desc->tfm);
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return cbc_desall_crypt(desc, KMC_TDEA_128_ENCRYPT, sctx->iv, &walk);
-}
-
-static int cbc_des3_128_decrypt(struct blkcipher_desc *desc,
-                                struct scatterlist *dst,
-                                struct scatterlist *src, unsigned int nbytes)
-{
-        struct crypt_s390_des3_128_ctx *sctx = crypto_blkcipher_ctx(desc->tfm);
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return cbc_desall_crypt(desc, KMC_TDEA_128_DECRYPT, sctx->iv, &walk);
-}
-
-static struct crypto_alg cbc_des3_128_alg = {
-        .cra_name               =       "cbc(des3_ede128)",
-        .cra_driver_name        =       "cbc-des3_ede128-s390",
-        .cra_priority           =       CRYPT_S390_COMPOSITE_PRIORITY,
-        .cra_flags              =       CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          =       DES3_128_BLOCK_SIZE,
-        .cra_ctxsize            =       sizeof(struct crypt_s390_des3_128_ctx),
-        .cra_type               =       &crypto_blkcipher_type,
-        .cra_module             =       THIS_MODULE,
-        .cra_list               =       LIST_HEAD_INIT(
-                                                cbc_des3_128_alg.cra_list),
-        .cra_u                  =       {
-                .blkcipher = {
-                        .min_keysize            =       DES3_128_KEY_SIZE,
-                        .max_keysize            =       DES3_128_KEY_SIZE,
-                        .ivsize                 =       DES3_128_BLOCK_SIZE,
-                        .setkey                 =       des3_128_setkey,
-                        .encrypt                =       cbc_des3_128_encrypt,
-                        .decrypt                =       cbc_des3_128_decrypt,
-                }
-        }
-};
-
-/*
- * RFC2451:
- *
- *   For DES-EDE3, there is no known need to reject weak or
- *   complementation keys.  Any weakness is obviated by the use of
- *   multiple keys.
- *
  *   However, if the first two or last two independent 64-bit keys are
  *   equal (k1 == k2 or k2 == k3), then the DES3 operation is simply the
  *   same as DES.  Implementers MUST reject keys that exhibit this
@@ -405,9 +238,7 @@ static struct crypto_alg cbc_des3_128_alg = {
 static int des3_192_setkey(struct crypto_tfm *tfm, const u8 *key,
                            unsigned int keylen)
 {
-        int i, ret;
         struct crypt_s390_des3_192_ctx *dctx = crypto_tfm_ctx(tfm);
-        const u8 *temp_key = key;
         u32 *flags = &tfm->crt_flags;
 
         if (!(memcmp(key, &key[DES_KEY_SIZE], DES_KEY_SIZE) &&
@@ -417,11 +248,6 @@ static int des3_192_setkey(struct crypto_tfm *tfm, const u8 *key,
                 *flags |= CRYPTO_TFM_RES_WEAK_KEY;
                 return -EINVAL;
         }
-        for (i = 0; i < 3; i++, temp_key += DES_KEY_SIZE) {
-                ret = crypto_des_check_key(temp_key, DES_KEY_SIZE, flags);
-                if (ret < 0)
-                        return ret;
-        }
         memcpy(dctx->key, key, keylen);
         return 0;
 }
@@ -431,7 +257,7 @@ static void des3_192_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
         struct crypt_s390_des3_192_ctx *dctx = crypto_tfm_ctx(tfm);
 
         crypt_s390_km(KM_TDEA_192_ENCRYPT, dctx->key, dst, (void*)src,
-                      DES3_192_BLOCK_SIZE);
+                      DES_BLOCK_SIZE);
 }
 
 static void des3_192_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
@@ -439,7 +265,7 @@ static void des3_192_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
         struct crypt_s390_des3_192_ctx *dctx = crypto_tfm_ctx(tfm);
 
         crypt_s390_km(KM_TDEA_192_DECRYPT, dctx->key, dst, (void*)src,
-                      DES3_192_BLOCK_SIZE);
+                      DES_BLOCK_SIZE);
 }
 
 static struct crypto_alg des3_192_alg = {
@@ -447,7 +273,7 @@ static struct crypto_alg des3_192_alg = {
         .cra_driver_name        =       "des3_ede-s390",
         .cra_priority           =       CRYPT_S390_PRIORITY,
         .cra_flags              =       CRYPTO_ALG_TYPE_CIPHER,
-        .cra_blocksize          =       DES3_192_BLOCK_SIZE,
+        .cra_blocksize          =       DES_BLOCK_SIZE,
         .cra_ctxsize            =       sizeof(struct crypt_s390_des3_192_ctx),
         .cra_module             =       THIS_MODULE,
         .cra_list               =       LIST_HEAD_INIT(des3_192_alg.cra_list),
@@ -489,7 +315,7 @@ static struct crypto_alg ecb_des3_192_alg = {
         .cra_driver_name        =       "ecb-des3_ede-s390",
         .cra_priority           =       CRYPT_S390_COMPOSITE_PRIORITY,
         .cra_flags              =       CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          =       DES3_192_BLOCK_SIZE,
+        .cra_blocksize          =       DES_BLOCK_SIZE,
         .cra_ctxsize            =       sizeof(struct crypt_s390_des3_192_ctx),
         .cra_type               =       &crypto_blkcipher_type,
         .cra_module             =       THIS_MODULE,
@@ -533,7 +359,7 @@ static struct crypto_alg cbc_des3_192_alg = {
         .cra_driver_name        =       "cbc-des3_ede-s390",
         .cra_priority           =       CRYPT_S390_COMPOSITE_PRIORITY,
         .cra_flags              =       CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          =       DES3_192_BLOCK_SIZE,
+        .cra_blocksize          =       DES_BLOCK_SIZE,
         .cra_ctxsize            =       sizeof(struct crypt_s390_des3_192_ctx),
         .cra_type               =       &crypto_blkcipher_type,
         .cra_module             =       THIS_MODULE,
@@ -543,7 +369,7 @@ static struct crypto_alg cbc_des3_192_alg = {
                 .blkcipher = {
                         .min_keysize            =       DES3_192_KEY_SIZE,
                         .max_keysize            =       DES3_192_KEY_SIZE,
-                        .ivsize                 =       DES3_192_BLOCK_SIZE,
+                        .ivsize                 =       DES_BLOCK_SIZE,
                         .setkey                 =       des3_192_setkey,
                         .encrypt                =       cbc_des3_192_encrypt,
                         .decrypt                =       cbc_des3_192_decrypt,
@@ -553,10 +379,9 @@ static struct crypto_alg cbc_des3_192_alg = {
 
 static int des_s390_init(void)
 {
-        int ret = 0;
+        int ret;
 
         if (!crypt_s390_func_available(KM_DEA_ENCRYPT) ||
-            !crypt_s390_func_available(KM_TDEA_128_ENCRYPT) ||
             !crypt_s390_func_available(KM_TDEA_192_ENCRYPT))
                 return -EOPNOTSUPP;
 
@@ -569,17 +394,6 @@ static int des_s390_init(void)
         ret = crypto_register_alg(&cbc_des_alg);
         if (ret)
                 goto cbc_des_err;
-
-        ret = crypto_register_alg(&des3_128_alg);
-        if (ret)
-                goto des3_128_err;
-        ret = crypto_register_alg(&ecb_des3_128_alg);
-        if (ret)
-                goto ecb_des3_128_err;
-        ret = crypto_register_alg(&cbc_des3_128_alg);
-        if (ret)
-                goto cbc_des3_128_err;
-
         ret = crypto_register_alg(&des3_192_alg);
         if (ret)
                 goto des3_192_err;
@@ -589,7 +403,6 @@ static int des_s390_init(void)
         ret = crypto_register_alg(&cbc_des3_192_alg);
         if (ret)
                 goto cbc_des3_192_err;
-
 out:
         return ret;
 
@@ -598,12 +411,6 @@ cbc_des3_192_err:
 ecb_des3_192_err:
         crypto_unregister_alg(&des3_192_alg);
 des3_192_err:
-        crypto_unregister_alg(&cbc_des3_128_alg);
-cbc_des3_128_err:
-        crypto_unregister_alg(&ecb_des3_128_alg);
-ecb_des3_128_err:
-        crypto_unregister_alg(&des3_128_alg);
-des3_128_err:
         crypto_unregister_alg(&cbc_des_alg);
 cbc_des_err:
         crypto_unregister_alg(&ecb_des_alg);
@@ -613,21 +420,18 @@ des_err:
         goto out;
 }
 
-static void __exit des_s390_fini(void)
+static void __exit des_s390_exit(void)
 {
         crypto_unregister_alg(&cbc_des3_192_alg);
         crypto_unregister_alg(&ecb_des3_192_alg);
         crypto_unregister_alg(&des3_192_alg);
-        crypto_unregister_alg(&cbc_des3_128_alg);
-        crypto_unregister_alg(&ecb_des3_128_alg);
-        crypto_unregister_alg(&des3_128_alg);
         crypto_unregister_alg(&cbc_des_alg);
         crypto_unregister_alg(&ecb_des_alg);
         crypto_unregister_alg(&des_alg);
 }
 
 module_init(des_s390_init);
-module_exit(des_s390_fini);
+module_exit(des_s390_exit);
 
 MODULE_ALIAS("des");
 MODULE_ALIAS("des3_ede");
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index 27605b62b980..cef7dbf69dfc 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -26,7 +26,7 @@
 
 struct sca_entry {
         atomic_t scn;
-        __u64   reserved;
+        __u32   reserved;
         __u64   sda;
         __u64   reserved2[2];
 } __attribute__((packed));
@@ -41,7 +41,8 @@ struct sca_block {
 } __attribute__((packed));
 
 #define KVM_NR_PAGE_SIZES 2
-#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + ((x) - 1) * 8)
+#define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 8)
+#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
 #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
 #define KVM_HPAGE_MASK(x)       (~(KVM_HPAGE_SIZE(x) - 1))
 #define KVM_PAGES_PER_HPAGE(x)  (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
diff --git a/arch/s390/include/asm/local64.h b/arch/s390/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/s390/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index 0eaae6260274..2ba630276295 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -84,6 +84,7 @@ struct qdr {
 
 #define QIB_AC_OUTBOUND_PCI_SUPPORTED   0x40
 #define QIB_RFLAGS_ENABLE_QEBSM         0x80
+#define QIB_RFLAGS_ENABLE_DATA_DIV      0x02
 
 /**
  * struct qib - queue information block (QIB)
@@ -284,6 +285,9 @@ struct slsb {
         u8 val[QDIO_MAX_BUFFERS_PER_Q];
 } __attribute__ ((packed, aligned(256)));
 
+#define CHSC_AC2_DATA_DIV_AVAILABLE     0x0010
+#define CHSC_AC2_DATA_DIV_ENABLED       0x0002
+
 struct qdio_ssqd_desc {
         u8 flags;
         u8:8;
@@ -332,6 +336,7 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
  * @adapter_name: name for the adapter
  * @qib_param_field_format: format for qib_parm_field
  * @qib_param_field: pointer to 128 bytes or NULL, if no param field
+ * @qib_rflags: rflags to set
  * @input_slib_elements: pointer to no_input_qs * 128 words of data or NULL
  * @output_slib_elements: pointer to no_output_qs * 128 words of data or NULL
  * @no_input_qs: number of input queues
@@ -348,6 +353,7 @@ struct qdio_initialize {
         unsigned char adapter_name[8];
         unsigned int qib_param_field_format;
         unsigned char *qib_param_field;
+        unsigned char qib_rflags;
         unsigned long *input_slib_elements;
         unsigned long *output_slib_elements;
         unsigned int no_input_qs;
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index d5e3e6007447..bea9ee37ac9d 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -535,8 +535,16 @@ pgm_no_vtime2:
         l       %r3,__LC_PGM_ILC        # load program interruption code
         la      %r8,0x7f
         nr      %r8,%r3                 # clear per-event-bit and ilc
-        be      BASED(pgm_exit)         # only per or per+check ?
-        b       BASED(pgm_do_call)
+        be      BASED(pgm_exit2)        # only per or per+check ?
+        l       %r7,BASED(.Ljump_table)
+        sll     %r8,2
+        l       %r7,0(%r8,%r7)          # load address of handler routine
+        la      %r2,SP_PTREGS(%r15)     # address of register-save area
+        basr    %r14,%r7                # branch to interrupt-handler
+pgm_exit2:
+        TRACE_IRQS_ON
+        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        b       BASED(sysc_return)
 
 #
 # it was a single stepped SVC that is causing all the trouble
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index e7192e1cb678..8bccec15ea90 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -544,8 +544,16 @@ pgm_no_vtime2:
         lgf     %r3,__LC_PGM_ILC        # load program interruption code
         lghi    %r8,0x7f
         ngr     %r8,%r3                 # clear per-event-bit and ilc
-        je      pgm_exit
-        j       pgm_do_call
+        je      pgm_exit2
+        sll     %r8,3
+        larl    %r1,pgm_check_table
+        lg      %r1,0(%r8,%r1)          # load address of handler routine
+        la      %r2,SP_PTREGS(%r15)     # address of register-save area
+        basr    %r14,%r1                # branch to interrupt-handler
+pgm_exit2:
+        TRACE_IRQS_ON
+        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        j       sysc_return
 
 #
 # it was a single stepped SVC that is causing all the trouble
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index a2163c95eb98..2896cac9c14a 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -207,8 +207,8 @@ struct clocksource * __init clocksource_default_clock(void)
         return &clocksource_tod;
 }
 
-void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
-                     u32 mult)
+void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
+                        struct clocksource *clock, u32 mult)
 {
         if (clock != &clocksource_tod)
                 return;
@@ -219,8 +219,8 @@ void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
         vdso_data->xtime_tod_stamp = clock->cycle_last;
         vdso_data->xtime_clock_sec = wall_time->tv_sec;
         vdso_data->xtime_clock_nsec = wall_time->tv_nsec;
-        vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec;
-        vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec;
+        vdso_data->wtom_clock_sec = wtm->tv_sec;
+        vdso_data->wtom_clock_nsec = wtm->tv_nsec;
         vdso_data->ntp_mult = mult;
         smp_wmb();
         ++vdso_data->tb_update_count;
@@ -524,8 +524,11 @@ void etr_switch_to_local(void)
         if (!etr_eacr.sl)
                 return;
         disable_sync_clock(NULL);
-        set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
-        queue_work(time_sync_wq, &etr_work);
+        if (!test_and_set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) {
+                etr_eacr.es = etr_eacr.sl = 0;
+                etr_setr(&etr_eacr);
+                queue_work(time_sync_wq, &etr_work);
+        }
 }
 
 /*
@@ -539,8 +542,11 @@ void etr_sync_check(void)
         if (!etr_eacr.es)
                 return;
         disable_sync_clock(NULL);
-        set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
-        queue_work(time_sync_wq, &etr_work);
+        if (!test_and_set_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) {
+                etr_eacr.es = 0;
+                etr_setr(&etr_eacr);
+                queue_work(time_sync_wq, &etr_work);
+        }
 }
 
 /*
@@ -902,7 +908,7 @@ static struct etr_eacr etr_handle_update(struct etr_aib *aib,
          * Do not try to get the alternate port aib if the clock
          * is not in sync yet.
          */
-        if (!check_sync_clock())
+        if (!eacr.es || !check_sync_clock())
                 return eacr;
 
         /*
@@ -1064,7 +1070,7 @@ static void etr_work_fn(struct work_struct *work)
          * If the clock is in sync just update the eacr and return.
          * If there is no valid sync port wait for a port update.
          */
-        if (check_sync_clock() || sync_port < 0) {
+        if ((eacr.es && check_sync_clock()) || sync_port < 0) {
                 etr_update_eacr(eacr);
                 etr_set_tolec_timeout(now);
                 goto out_unlock;
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 3ddc30895e31..f7b6df45d8be 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -135,7 +135,7 @@ static int handle_stop(struct kvm_vcpu *vcpu)
         spin_lock_bh(&vcpu->arch.local_int.lock);
         if (vcpu->arch.local_int.action_bits & ACTION_STORE_ON_STOP) {
                 vcpu->arch.local_int.action_bits &= ~ACTION_STORE_ON_STOP;
-                rc = __kvm_s390_vcpu_store_status(vcpu,
+                rc = kvm_s390_vcpu_store_status(vcpu,
                                                   KVM_S390_STORE_STATUS_NOADDR);
                 if (rc >= 0)
                         rc = -EOPNOTSUPP;
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index ae3705816878..4fe68650535c 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -207,6 +207,7 @@ out_nokvm:
 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 {
         VCPU_EVENT(vcpu, 3, "%s", "free cpu");
+        clear_bit(63 - vcpu->vcpu_id, (unsigned long *) &vcpu->kvm->arch.sca->mcn);
         if (vcpu->kvm->arch.sca->cpu[vcpu->vcpu_id].sda ==
                 (__u64) vcpu->arch.sie_block)
                 vcpu->kvm->arch.sca->cpu[vcpu->vcpu_id].sda = 0;
@@ -296,7 +297,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
 {
         atomic_set(&vcpu->arch.sie_block->cpuflags, CPUSTAT_ZARCH);
         set_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests);
-        vcpu->arch.sie_block->ecb   = 2;
+        vcpu->arch.sie_block->ecb   = 6;
         vcpu->arch.sie_block->eca   = 0xC1002001U;
         vcpu->arch.sie_block->fac   = (int) (long) facilities;
         hrtimer_init(&vcpu->arch.ckc_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS);
@@ -329,6 +330,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
                 kvm->arch.sca->cpu[id].sda = (__u64) vcpu->arch.sie_block;
         vcpu->arch.sie_block->scaoh = (__u32)(((__u64)kvm->arch.sca) >> 32);
         vcpu->arch.sie_block->scaol = (__u32)(__u64)kvm->arch.sca;
+        set_bit(63 - id, (unsigned long *) &kvm->arch.sca->mcn);
 
         spin_lock_init(&vcpu->arch.local_int.lock);
         INIT_LIST_HEAD(&vcpu->arch.local_int.list);
@@ -363,63 +365,49 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 
 static int kvm_arch_vcpu_ioctl_initial_reset(struct kvm_vcpu *vcpu)
 {
-        vcpu_load(vcpu);
         kvm_s390_vcpu_initial_reset(vcpu);
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
-        vcpu_load(vcpu);
         memcpy(&vcpu->arch.guest_gprs, &regs->gprs, sizeof(regs->gprs));
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
-        vcpu_load(vcpu);
         memcpy(&regs->gprs, &vcpu->arch.guest_gprs, sizeof(regs->gprs));
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
                                   struct kvm_sregs *sregs)
 {
-        vcpu_load(vcpu);
         memcpy(&vcpu->arch.guest_acrs, &sregs->acrs, sizeof(sregs->acrs));
         memcpy(&vcpu->arch.sie_block->gcr, &sregs->crs, sizeof(sregs->crs));
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
                                   struct kvm_sregs *sregs)
 {
-        vcpu_load(vcpu);
         memcpy(&sregs->acrs, &vcpu->arch.guest_acrs, sizeof(sregs->acrs));
         memcpy(&sregs->crs, &vcpu->arch.sie_block->gcr, sizeof(sregs->crs));
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
-        vcpu_load(vcpu);
         memcpy(&vcpu->arch.guest_fpregs.fprs, &fpu->fprs, sizeof(fpu->fprs));
         vcpu->arch.guest_fpregs.fpc = fpu->fpc;
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
-        vcpu_load(vcpu);
         memcpy(&fpu->fprs, &vcpu->arch.guest_fpregs.fprs, sizeof(fpu->fprs));
         fpu->fpc = vcpu->arch.guest_fpregs.fpc;
-        vcpu_put(vcpu);
         return 0;
 }
 
@@ -427,14 +415,12 @@ static int kvm_arch_vcpu_ioctl_set_initial_psw(struct kvm_vcpu *vcpu, psw_t psw)
 {
         int rc = 0;
 
-        vcpu_load(vcpu);
         if (atomic_read(&vcpu->arch.sie_block->cpuflags) & CPUSTAT_RUNNING)
                 rc = -EBUSY;
         else {
                 vcpu->run->psw_mask = psw.mask;
                 vcpu->run->psw_addr = psw.addr;
         }
-        vcpu_put(vcpu);
         return rc;
 }
 
@@ -498,8 +484,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
         int rc;
         sigset_t sigsaved;
 
-        vcpu_load(vcpu);
-
 rerun_vcpu:
         if (vcpu->requests)
                 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
@@ -568,8 +552,6 @@ rerun_vcpu:
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 
-        vcpu_put(vcpu);
-
         vcpu->stat.exit_userspace++;
         return rc;
 }
@@ -589,7 +571,7 @@ static int __guestcopy(struct kvm_vcpu *vcpu, u64 guestdest, const void *from,
  * KVM_S390_STORE_STATUS_NOADDR: -> 0x1200 on 64 bit
  * KVM_S390_STORE_STATUS_PREFIXED: -> prefix
  */
-int __kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
+int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
 {
         const unsigned char archmode = 1;
         int prefix;
@@ -651,45 +633,42 @@ int __kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
         return 0;
 }
 
-static int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
-{
-        int rc;
-
-        vcpu_load(vcpu);
-        rc = __kvm_s390_vcpu_store_status(vcpu, addr);
-        vcpu_put(vcpu);
-        return rc;
-}
-
 long kvm_arch_vcpu_ioctl(struct file *filp,
                          unsigned int ioctl, unsigned long arg)
 {
         struct kvm_vcpu *vcpu = filp->private_data;
         void __user *argp = (void __user *)arg;
+        long r;
 
         switch (ioctl) {
         case KVM_S390_INTERRUPT: {
                 struct kvm_s390_interrupt s390int;
 
+                r = -EFAULT;
                 if (copy_from_user(&s390int, argp, sizeof(s390int)))
-                        return -EFAULT;
-                return kvm_s390_inject_vcpu(vcpu, &s390int);
+                        break;
+                r = kvm_s390_inject_vcpu(vcpu, &s390int);
+                break;
         }
         case KVM_S390_STORE_STATUS:
-                return kvm_s390_vcpu_store_status(vcpu, arg);
+                r = kvm_s390_vcpu_store_status(vcpu, arg);
+                break;
         case KVM_S390_SET_INITIAL_PSW: {
                 psw_t psw;
 
+                r = -EFAULT;
                 if (copy_from_user(&psw, argp, sizeof(psw)))
-                        return -EFAULT;
-                return kvm_arch_vcpu_ioctl_set_initial_psw(vcpu, psw);
+                        break;
+                r = kvm_arch_vcpu_ioctl_set_initial_psw(vcpu, psw);
+                break;
         }
         case KVM_S390_INITIAL_RESET:
-                return kvm_arch_vcpu_ioctl_initial_reset(vcpu);
+                r = kvm_arch_vcpu_ioctl_initial_reset(vcpu);
+                break;
         default:
-                ;
+                r = -EINVAL;
         }
-        return -EINVAL;
+        return r;
 }
 
 /* Section: memory related */
@@ -744,11 +723,6 @@ void kvm_arch_flush_shadow(struct kvm *kvm)
 {
 }
 
-gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
-{
-        return gfn;
-}
-
 static int __init kvm_s390_init(void)
 {
         int ret;
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index cfa9d1777457..a7b7586626db 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -92,7 +92,7 @@ int kvm_s390_handle_b2(struct kvm_vcpu *vcpu);
 int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu);
 
 /* implemented in kvm-s390.c */
-int __kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu,
+int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu,
                                  unsigned long addr);
 /* implemented in diag.c */
 int kvm_s390_handle_diag(struct kvm_vcpu *vcpu);
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 55d413e6dcf2..be4a15584751 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -55,9 +55,6 @@ config GENERIC_CALIBRATE_DELAY
 config GENERIC_CLOCKEVENTS
         def_bool y
 
-config GENERIC_TIME
-        def_bool y
-
 config SCHED_NO_NO_OMIT_FRAME_POINTER
         def_bool y
 
diff --git a/arch/score/Makefile b/arch/score/Makefile
index 68e0cd06d5c9..d77dc639d8e3 100644
--- a/arch/score/Makefile
+++ b/arch/score/Makefile
@@ -20,7 +20,8 @@ cflags-y += -G0 -pipe -mel -mnhwloop -D__SCOREEL__ \
 #
 KBUILD_AFLAGS += $(cflags-y)
 KBUILD_CFLAGS += $(cflags-y)
-MODFLAGS += -mlong-calls
+KBUILD_AFLAGS_MODULE += -mlong-calls
+KBUILD_CFLAGS_MODULE += -mlong-calls
 LDFLAGS += --oformat elf32-littlescore
 LDFLAGS_vmlinux += -G0 -static -nostdlib
 
diff --git a/arch/score/include/asm/local64.h b/arch/score/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/score/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 82868fee21fd..33990fa95af0 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -98,9 +98,6 @@ config GENERIC_CALIBRATE_DELAY
 config GENERIC_IOMAP
         bool
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_CLOCKEVENTS
         def_bool y
 
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 3a170bd3f3d0..de375b64e410 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -316,7 +316,7 @@ static struct soc_camera_platform_info camera_info = {
         .format_name = "UYVY",
         .format_depth = 16,
         .format = {
-                .code = V4L2_MBUS_FMT_YUYV8_2X8_BE,
+                .code = V4L2_MBUS_FMT_UYVY8_2X8,
                 .colorspace = V4L2_COLORSPACE_SMPTE170M,
                 .field = V4L2_FIELD_NONE,
                 .width = 640,
diff --git a/arch/sh/include/asm/local64.h b/arch/sh/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/sh/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/sh/kernel/clkdev.c b/arch/sh/kernel/clkdev.c
index defdd6e30908..befc255830a4 100644
--- a/arch/sh/kernel/clkdev.c
+++ b/arch/sh/kernel/clkdev.c
@@ -36,7 +36,7 @@ static DEFINE_MUTEX(clocks_mutex);
  *  If an entry has a device ID, it must match
  *  If an entry has a connection ID, it must match
  * Then we take the most specific entry - with the following
- * order of precidence: dev+con > dev only > con only.
+ * order of precedence: dev+con > dev only > con only.
  */
 static struct clk *clk_find(const char *dev_id, const char *con_id)
 {
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 81b6de41ae5d..7a3dc3567258 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -185,10 +185,10 @@ static void sh_perf_event_update(struct perf_event *event,
          * this is the simplest approach for maintaining consistency.
          */
 again:
-        prev_raw_count = atomic64_read(&hwc->prev_count);
+        prev_raw_count = local64_read(&hwc->prev_count);
         new_raw_count = sh_pmu->read(idx);
 
-        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
                              new_raw_count) != prev_raw_count)
                 goto again;
 
@@ -203,7 +203,7 @@ again:
         delta = (new_raw_count << shift) - (prev_raw_count << shift);
         delta >>= shift;
 
-        atomic64_add(delta, &event->count);
+        local64_add(delta, &event->count);
 }
 
 static void sh_pmu_disable(struct perf_event *event)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index c0015db247ba..491e9d6de191 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -18,6 +18,7 @@ config 64BIT
 config SPARC
         bool
         default y
+        select OF
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_ARCH_KGDB if !SMP || SPARC64
@@ -66,9 +67,6 @@ config BITS
         default 32 if SPARC32
         default 64 if SPARC64
 
-config GENERIC_TIME
-        def_bool y
-
 config ARCH_USES_GETTIMEOFFSET
         bool
         default y if SPARC32
@@ -148,9 +146,6 @@ config GENERIC_GPIO
 config ARCH_NO_VIRT_TO_BUS
         def_bool y
 
-config OF
-        def_bool y
-
 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
         def_bool y if SPARC64
 
diff --git a/arch/sparc/boot/btfixupprep.c b/arch/sparc/boot/btfixupprep.c
index e7f2940bd270..da031159e2b7 100644
--- a/arch/sparc/boot/btfixupprep.c
+++ b/arch/sparc/boot/btfixupprep.c
@@ -216,7 +216,7 @@ main1:
                 switch (buffer[nbase+3]) {
                 case 'f':
                         if (initval) {
-                                fprintf(stderr, "Cannot use pre-initalized fixups for calls\n%s\n", buffer);
+                                fprintf(stderr, "Cannot use pre-initialized fixups for calls\n%s\n", buffer);
                                 exit(1);
                         }
                         if (!strcmp (sect, "__ksymtab")) {
@@ -273,7 +273,7 @@ main1:
                         break;
                 case 'i':
                         if (initval) {
-                                fprintf(stderr, "Cannot use pre-initalized fixups for INT\n%s\n", buffer);
+                                fprintf(stderr, "Cannot use pre-initialized fixups for INT\n%s\n", buffer);
                                 exit(1);
                         }
                         if (strncmp (buffer + mode+9, "HI22      ", 10) && strncmp (buffer + mode+9, "LO10      ", 10)) {
diff --git a/arch/sparc/include/asm/device.h b/arch/sparc/include/asm/device.h
index d4c452147412..daa6a8a5e9cd 100644
--- a/arch/sparc/include/asm/device.h
+++ b/arch/sparc/include/asm/device.h
@@ -6,18 +6,25 @@
 #ifndef _ASM_SPARC_DEVICE_H
 #define _ASM_SPARC_DEVICE_H
 
+#include <asm/openprom.h>
+
 struct device_node;
-struct of_device;
+struct platform_device;
 
 struct dev_archdata {
         void                    *iommu;
         void                    *stc;
         void                    *host_controller;
-        struct of_device        *op;
+        struct platform_device  *op;
         int                     numa_node;
 };
 
+extern void of_propagate_archdata(struct platform_device *bus);
+
 struct pdev_archdata {
+        struct resource         resource[PROMREG_MAX];
+        unsigned int            irqs[PROMINTR_MAX];
+        int                     num_irqs;
 };
 
 #endif /* _ASM_SPARC_DEVICE_H */
diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h
index 8fac3ab22f36..6597ce874d78 100644
--- a/arch/sparc/include/asm/floppy_64.h
+++ b/arch/sparc/include/asm/floppy_64.h
@@ -43,7 +43,7 @@ struct sun_flpy_controller {
 /* You'll only ever find one controller on an Ultra anyways. */
 static struct sun_flpy_controller *sun_fdc = (struct sun_flpy_controller *)-1;
 unsigned long fdc_status;
-static struct of_device *floppy_op = NULL;
+static struct platform_device *floppy_op = NULL;
 
 struct sun_floppy_ops {
         unsigned char   (*fd_inb) (unsigned long port);
@@ -548,7 +548,7 @@ static unsigned long __init sun_floppy_init(void)
 {
         static int initialized = 0;
         struct device_node *dp;
-        struct of_device *op;
+        struct platform_device *op;
         const char *prop;
         char state[128];
 
@@ -567,7 +567,7 @@ static unsigned long __init sun_floppy_init(void)
         }
         if (op) {
                 floppy_op = op;
-                FLOPPY_IRQ = op->irqs[0];
+                FLOPPY_IRQ = op->archdata.irqs[0];
         } else {
                 struct device_node *ebus_dp;
                 void __iomem *auxio_reg;
@@ -593,7 +593,7 @@ static unsigned long __init sun_floppy_init(void)
                 if (state_prop && !strncmp(state_prop, "disabled", 8))
                         return 0;
 
-                FLOPPY_IRQ = op->irqs[0];
+                FLOPPY_IRQ = op->archdata.irqs[0];
 
                 /* Make sure the high density bit is set, some systems
                  * (most notably Ultra5/Ultra10) come up with it clear.
@@ -661,7 +661,7 @@ static unsigned long __init sun_floppy_init(void)
                 config = 0;
                 for (dp = ebus_dp->child; dp; dp = dp->sibling) {
                         if (!strcmp(dp->name, "ecpp")) {
-                                struct of_device *ecpp_op;
+                                struct platform_device *ecpp_op;
 
                                 ecpp_op = of_find_device_by_node(dp);
                                 if (ecpp_op)
diff --git a/arch/sparc/include/asm/local64.h b/arch/sparc/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/sparc/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/sparc/include/asm/of_device.h b/arch/sparc/include/asm/of_device.h
deleted file mode 100644
index f320246a0586..000000000000
--- a/arch/sparc/include/asm/of_device.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef _ASM_SPARC_OF_DEVICE_H
-#define _ASM_SPARC_OF_DEVICE_H
-#ifdef __KERNEL__
-
-#include <linux/device.h>
-#include <linux/of.h>
-#include <linux/mod_devicetable.h>
-#include <asm/openprom.h>
-
-/*
- * The of_device is a kind of "base class" that is a superset of
- * struct device for use by devices attached to an OF node and
- * probed using OF properties.
- */
-struct of_device
-{
-        struct device                   dev;
-        struct resource                 resource[PROMREG_MAX];
-        unsigned int                    irqs[PROMINTR_MAX];
-        int                             num_irqs;
-
-        void                            *sysdata;
-
-        int                             slot;
-        int                             portid;
-        int                             clock_freq;
-};
-
-extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
-extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
-
-extern void of_propagate_archdata(struct of_device *bus);
-
-/* This is just here during the transition */
-#include <linux/of_platform.h>
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_SPARC_OF_DEVICE_H */
diff --git a/arch/sparc/include/asm/of_platform.h b/arch/sparc/include/asm/of_platform.h
deleted file mode 100644
index 90da99059f83..000000000000
--- a/arch/sparc/include/asm/of_platform.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef ___ASM_SPARC_OF_PLATFORM_H
-#define ___ASM_SPARC_OF_PLATFORM_H
-/*
- *    Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corp.
- *                       <benh@kernel.crashing.org>
- *    Modified for Sparc by merging parts of asm/of_device.h
- *              by Stephen Rothwell
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- *
- */
-
-#define of_bus_type     of_platform_bus_type    /* for compatibility */
-
-#endif
diff --git a/arch/sparc/include/asm/parport.h b/arch/sparc/include/asm/parport.h
index c333b8d0949b..4f7afa01b2ae 100644
--- a/arch/sparc/include/asm/parport.h
+++ b/arch/sparc/include/asm/parport.h
@@ -103,7 +103,7 @@ static inline unsigned int get_dma_residue(unsigned int dmanr)
         return ebus_dma_residue(&sparc_ebus_dmas[dmanr].info);
 }
 
-static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit ecpp_probe(struct platform_device *op, const struct of_device_id *match)
 {
         unsigned long base = op->resource[0].start;
         unsigned long config = op->resource[1].start;
@@ -116,7 +116,7 @@ static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id
         parent = op->dev.of_node->parent;
         if (!strcmp(parent->name, "dma")) {
                 p = parport_pc_probe_port(base, base + 0x400,
-                                          op->irqs[0], PARPORT_DMA_NOFIFO,
+                                          op->archdata.irqs[0], PARPORT_DMA_NOFIFO,
                                           op->dev.parent->parent, 0);
                 if (!p)
                         return -ENOMEM;
@@ -166,7 +166,7 @@ static int __devinit ecpp_probe(struct of_device *op, const struct of_device_id
                        0, PTR_LPT_REG_DIR);
 
         p = parport_pc_probe_port(base, base + 0x400,
-                                  op->irqs[0],
+                                  op->archdata.irqs[0],
                                   slot,
                                   op->dev.parent,
                                   0);
@@ -192,7 +192,7 @@ out_err:
         return err;
 }
 
-static int __devexit ecpp_remove(struct of_device *op)
+static int __devexit ecpp_remove(struct platform_device *op)
 {
         struct parport *p = dev_get_drvdata(&op->dev);
         int slot = p->dma;
@@ -243,9 +243,7 @@ static struct of_platform_driver ecpp_driver = {
 
 static int parport_pc_find_nonpci_ports(int autoirq, int autodma)
 {
-        of_register_driver(&ecpp_driver, &of_bus_type);
-
-        return 0;
+        return of_register_platform_driver(&ecpp_driver);
 }
 
 #endif /* !(_ASM_SPARC64_PARPORT_H */
diff --git a/arch/sparc/include/asm/perf_event.h b/arch/sparc/include/asm/perf_event.h
index 7e2669894ce8..74c4e0cd889c 100644
--- a/arch/sparc/include/asm/perf_event.h
+++ b/arch/sparc/include/asm/perf_event.h
@@ -6,7 +6,15 @@ extern void set_perf_event_pending(void);
 #define PERF_EVENT_INDEX_OFFSET 0
 
 #ifdef CONFIG_PERF_EVENTS
+#include <asm/ptrace.h>
+
 extern void init_hw_perf_events(void);
+
+extern void
+__perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip);
+
+#define perf_arch_fetch_caller_regs(pt_regs, ip)        \
+        __perf_arch_fetch_caller_regs(pt_regs, ip, 1);
 #else
 static inline void init_hw_perf_events(void)    { }
 #endif
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
index f845828ca4c6..291f12575edd 100644
--- a/arch/sparc/include/asm/prom.h
+++ b/arch/sparc/include/asm/prom.h
@@ -43,20 +43,22 @@ extern int of_getintprop_default(struct device_node *np,
 extern int of_find_in_proplist(const char *list, const char *match, int len);
 #ifdef CONFIG_NUMA
 extern int of_node_to_nid(struct device_node *dp);
-#else
-#define of_node_to_nid(dp)      (-1)
+#define of_node_to_nid of_node_to_nid
 #endif
 
 extern void prom_build_devicetree(void);
 extern void of_populate_present_mask(void);
 extern void of_fill_in_cpu_data(void);
 
+struct resource;
+extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
+extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
+
 /* These routines are here to provide compatibility with how powerpc
  * handles IRQ mapping for OF device nodes.  We precompute and permanently
- * register them in the of_device objects, whereas powerpc computes them
+ * register them in the platform_device objects, whereas powerpc computes them
  * on request.
  */
-extern unsigned int irq_of_parse_and_map(struct device_node *node, int index);
 static inline void irq_dispose_mapping(unsigned int virq)
 {
 }
diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c
index b27476caa133..2c0046ecc715 100644
--- a/arch/sparc/kernel/apc.c
+++ b/arch/sparc/kernel/apc.c
@@ -68,7 +68,7 @@ static void apc_swift_idle(void)
 #endif
 } 
 
-static inline void apc_free(struct of_device *op)
+static inline void apc_free(struct platform_device *op)
 {
         of_iounmap(&op->resource[0], regs, resource_size(&op->resource[0]));
 }
@@ -136,7 +136,7 @@ static const struct file_operations apc_fops = {
 
 static struct miscdevice apc_miscdev = { APC_MINOR, APC_DEVNAME, &apc_fops };
 
-static int __devinit apc_probe(struct of_device *op,
+static int __devinit apc_probe(struct platform_device *op,
                                const struct of_device_id *match)
 {
         int err;
@@ -184,7 +184,7 @@ static struct of_platform_driver apc_driver = {
 
 static int __init apc_init(void)
 {
-        return of_register_driver(&apc_driver, &of_bus_type);
+        return of_register_platform_driver(&apc_driver);
 }
 
 /* This driver is not critical to the boot process
diff --git a/arch/sparc/kernel/auxio_64.c b/arch/sparc/kernel/auxio_64.c
index ddc84128b3c2..3efd3c5af6a9 100644
--- a/arch/sparc/kernel/auxio_64.c
+++ b/arch/sparc/kernel/auxio_64.c
@@ -102,7 +102,8 @@ static struct of_device_id __initdata auxio_match[] = {
 
 MODULE_DEVICE_TABLE(of, auxio_match);
 
-static int __devinit auxio_probe(struct of_device *dev, const struct of_device_id *match)
+static int __devinit auxio_probe(struct platform_device *dev,
+                                 const struct of_device_id *match)
 {
         struct device_node *dp = dev->dev.of_node;
         unsigned long size;
@@ -142,7 +143,7 @@ static struct of_platform_driver auxio_driver = {
 
 static int __init auxio_init(void)
 {
-        return of_register_driver(&auxio_driver, &of_platform_bus_type);
+        return of_register_platform_driver(&auxio_driver);
 }
 
 /* Must be after subsys_initcall() so that busses are probed.  Must
diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c
index 434335f65823..cfa2624c5332 100644
--- a/arch/sparc/kernel/central.c
+++ b/arch/sparc/kernel/central.c
@@ -59,7 +59,7 @@ static int __devinit clock_board_calc_nslots(struct clock_board *p)
         }
 }
 
-static int __devinit clock_board_probe(struct of_device *op,
+static int __devinit clock_board_probe(struct platform_device *op,
                                        const struct of_device_id *match)
 {
         struct clock_board *p = kzalloc(sizeof(*p), GFP_KERNEL);
@@ -157,7 +157,7 @@ static struct of_platform_driver clock_board_driver = {
         },
 };
 
-static int __devinit fhc_probe(struct of_device *op,
+static int __devinit fhc_probe(struct platform_device *op,
                                const struct of_device_id *match)
 {
         struct fhc *p = kzalloc(sizeof(*p), GFP_KERNEL);
@@ -265,8 +265,8 @@ static struct of_platform_driver fhc_driver = {
 
 static int __init sunfire_init(void)
 {
-        (void) of_register_driver(&fhc_driver, &of_platform_bus_type);
-        (void) of_register_driver(&clock_board_driver, &of_platform_bus_type);
+        (void) of_register_platform_driver(&fhc_driver);
+        (void) of_register_platform_driver(&clock_board_driver);
         return 0;
 }
 
diff --git a/arch/sparc/kernel/chmc.c b/arch/sparc/kernel/chmc.c
index 870cb65b3f21..08c466ebb32b 100644
--- a/arch/sparc/kernel/chmc.c
+++ b/arch/sparc/kernel/chmc.c
@@ -392,7 +392,7 @@ static void __devinit jbusmc_construct_dimm_groups(struct jbusmc *p,
         }
 }
 
-static int __devinit jbusmc_probe(struct of_device *op,
+static int __devinit jbusmc_probe(struct platform_device *op,
                                   const struct of_device_id *match)
 {
         const struct linux_prom64_registers *mem_regs;
@@ -690,7 +690,7 @@ static void chmc_fetch_decode_regs(struct chmc *p)
                                       chmc_read_mcreg(p, CHMCTRL_DECODE4));
 }
 
-static int __devinit chmc_probe(struct of_device *op,
+static int __devinit chmc_probe(struct platform_device *op,
                                 const struct of_device_id *match)
 {
         struct device_node *dp = op->dev.of_node;
@@ -765,7 +765,7 @@ out_free:
         goto out;
 }
 
-static int __devinit us3mc_probe(struct of_device *op,
+static int __devinit us3mc_probe(struct platform_device *op,
                                 const struct of_device_id *match)
 {
         if (mc_type == MC_TYPE_SAFARI)
@@ -775,21 +775,21 @@ static int __devinit us3mc_probe(struct of_device *op,
         return -ENODEV;
 }
 
-static void __devexit chmc_destroy(struct of_device *op, struct chmc *p)
+static void __devexit chmc_destroy(struct platform_device *op, struct chmc *p)
 {
         list_del(&p->list);
         of_iounmap(&op->resource[0], p->regs, 0x48);
         kfree(p);
 }
 
-static void __devexit jbusmc_destroy(struct of_device *op, struct jbusmc *p)
+static void __devexit jbusmc_destroy(struct platform_device *op, struct jbusmc *p)
 {
         mc_list_del(&p->list);
         of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
         kfree(p);
 }
 
-static int __devexit us3mc_remove(struct of_device *op)
+static int __devexit us3mc_remove(struct platform_device *op)
 {
         void *p = dev_get_drvdata(&op->dev);
 
@@ -848,7 +848,7 @@ static int __init us3mc_init(void)
         ret = register_dimm_printer(us3mc_dimm_printer);
 
         if (!ret) {
-                ret = of_register_driver(&us3mc_driver, &of_bus_type);
+                ret = of_register_platform_driver(&us3mc_driver);
                 if (ret)
                         unregister_dimm_printer(us3mc_dimm_printer);
         }
@@ -859,7 +859,7 @@ static void __exit us3mc_cleanup(void)
 {
         if (us3mc_platform()) {
                 unregister_dimm_printer(us3mc_dimm_printer);
-                of_unregister_driver(&us3mc_driver);
+                of_unregister_platform_driver(&us3mc_driver);
         }
 }
 
diff --git a/arch/sparc/kernel/helpers.S b/arch/sparc/kernel/helpers.S
index 92090cc9e829..682fee06a16b 100644
--- a/arch/sparc/kernel/helpers.S
+++ b/arch/sparc/kernel/helpers.S
@@ -47,9 +47,9 @@ stack_trace_flush:
         .size           stack_trace_flush,.-stack_trace_flush
 
 #ifdef CONFIG_PERF_EVENTS
-        .globl          perf_arch_fetch_caller_regs
-        .type           perf_arch_fetch_caller_regs,#function
-perf_arch_fetch_caller_regs:
+        .globl          __perf_arch_fetch_caller_regs
+        .type           __perf_arch_fetch_caller_regs,#function
+__perf_arch_fetch_caller_regs:
         /* We always read the %pstate into %o5 since we will use
          * that to construct a fake %tstate to store into the regs.
          */
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 703e4aa9bc38..41f7e4e0f72a 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -253,7 +253,7 @@ EXPORT_SYMBOL(sbus_set_sbus64);
 static void *sbus_alloc_coherent(struct device *dev, size_t len,
                                  dma_addr_t *dma_addrp, gfp_t gfp)
 {
-        struct of_device *op = to_of_device(dev);
+        struct platform_device *op = to_platform_device(dev);
         unsigned long len_total = (len + PAGE_SIZE-1) & PAGE_MASK;
         unsigned long va;
         struct resource *res;
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index 47e63f1e719c..2d055a1e9cc2 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -241,10 +241,10 @@ static int __init use_1to1_mapping(struct device_node *pp)
 
 static int of_resource_verbose;
 
-static void __init build_device_resources(struct of_device *op,
+static void __init build_device_resources(struct platform_device *op,
                                           struct device *parent)
 {
-        struct of_device *p_op;
+        struct platform_device *p_op;
         struct of_bus *bus;
         int na, ns;
         int index, num_reg;
@@ -253,7 +253,7 @@ static void __init build_device_resources(struct of_device *op,
         if (!parent)
                 return;
 
-        p_op = to_of_device(parent);
+        p_op = to_platform_device(parent);
         bus = of_match_bus(p_op->dev.of_node);
         bus->count_cells(op->dev.of_node, &na, &ns);
 
@@ -267,6 +267,8 @@ static void __init build_device_resources(struct of_device *op,
         /* Conver to num-entries.  */
         num_reg /= na + ns;
 
+        op->resource = op->archdata.resource;
+        op->num_resources = num_reg;
         for (index = 0; index < num_reg; index++) {
                 struct resource *r = &op->resource[index];
                 u32 addr[OF_MAX_ADDR_CELLS];
@@ -333,10 +335,10 @@ static void __init build_device_resources(struct of_device *op,
         }
 }
 
-static struct of_device * __init scan_one_device(struct device_node *dp,
+static struct platform_device * __init scan_one_device(struct device_node *dp,
                                                  struct device *parent)
 {
-        struct of_device *op = kzalloc(sizeof(*op), GFP_KERNEL);
+        struct platform_device *op = kzalloc(sizeof(*op), GFP_KERNEL);
         const struct linux_prom_irqs *intr;
         struct dev_archdata *sd;
         int len, i;
@@ -349,27 +351,21 @@ static struct of_device * __init scan_one_device(struct device_node *dp,
 
         op->dev.of_node = dp;
 
-        op->clock_freq = of_getintprop_default(dp, "clock-frequency",
-                                               (25*1000*1000));
-        op->portid = of_getintprop_default(dp, "upa-portid", -1);
-        if (op->portid == -1)
-                op->portid = of_getintprop_default(dp, "portid", -1);
-
         intr = of_get_property(dp, "intr", &len);
         if (intr) {
-                op->num_irqs = len / sizeof(struct linux_prom_irqs);
-                for (i = 0; i < op->num_irqs; i++)
-                        op->irqs[i] = intr[i].pri;
+                op->archdata.num_irqs = len / sizeof(struct linux_prom_irqs);
+                for (i = 0; i < op->archdata.num_irqs; i++)
+                        op->archdata.irqs[i] = intr[i].pri;
         } else {
                 const unsigned int *irq =
                         of_get_property(dp, "interrupts", &len);
 
                 if (irq) {
-                        op->num_irqs = len / sizeof(unsigned int);
-                        for (i = 0; i < op->num_irqs; i++)
-                                op->irqs[i] = irq[i];
+                        op->archdata.num_irqs = len / sizeof(unsigned int);
+                        for (i = 0; i < op->archdata.num_irqs; i++)
+                                op->archdata.irqs[i] = irq[i];
                 } else {
-                        op->num_irqs = 0;
+                        op->archdata.num_irqs = 0;
                 }
         }
         if (sparc_cpu_model == sun4d) {
@@ -411,8 +407,8 @@ static struct of_device * __init scan_one_device(struct device_node *dp,
                         goto build_resources;
                 }
 
-                for (i = 0; i < op->num_irqs; i++) {
-                        int this_irq = op->irqs[i];
+                for (i = 0; i < op->archdata.num_irqs; i++) {
+                        int this_irq = op->archdata.irqs[i];
                         int sbusl = pil_to_sbus[this_irq];
 
                         if (sbusl)
@@ -420,7 +416,7 @@ static struct of_device * __init scan_one_device(struct device_node *dp,
                                             (sbusl << 2) +
                                             slot);
 
-                        op->irqs[i] = this_irq;
+                        op->archdata.irqs[i] = this_irq;
                 }
         }
 
@@ -428,7 +424,7 @@ build_resources:
         build_device_resources(op, parent);
 
         op->dev.parent = parent;
-        op->dev.bus = &of_platform_bus_type;
+        op->dev.bus = &platform_bus_type;
         if (!parent)
                 dev_set_name(&op->dev, "root");
         else
@@ -447,7 +443,7 @@ build_resources:
 static void __init scan_tree(struct device_node *dp, struct device *parent)
 {
         while (dp) {
-                struct of_device *op = scan_one_device(dp, parent);
+                struct platform_device *op = scan_one_device(dp, parent);
 
                 if (op)
                         scan_tree(dp->child, &op->dev);
@@ -456,30 +452,19 @@ static void __init scan_tree(struct device_node *dp, struct device *parent)
         }
 }
 
-static void __init scan_of_devices(void)
+static int __init scan_of_devices(void)
 {
         struct device_node *root = of_find_node_by_path("/");
-        struct of_device *parent;
+        struct platform_device *parent;
 
         parent = scan_one_device(root, NULL);
         if (!parent)
-                return;
+                return 0;
 
         scan_tree(root->child, &parent->dev);
+        return 0;
 }
-
-static int __init of_bus_driver_init(void)
-{
-        int err;
-
-        err = of_bus_type_init(&of_platform_bus_type, "of");
-        if (!err)
-                scan_of_devices();
-
-        return err;
-}
-
-postcore_initcall(of_bus_driver_init);
+postcore_initcall(scan_of_devices);
 
 static int __init of_debug(char *str)
 {
diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c
index 1dae8079f728..63cd4e5d47c2 100644
--- a/arch/sparc/kernel/of_device_64.c
+++ b/arch/sparc/kernel/of_device_64.c
@@ -310,10 +310,10 @@ static int __init use_1to1_mapping(struct device_node *pp)
 
 static int of_resource_verbose;
 
-static void __init build_device_resources(struct of_device *op,
+static void __init build_device_resources(struct platform_device *op,
                                           struct device *parent)
 {
-        struct of_device *p_op;
+        struct platform_device *p_op;
         struct of_bus *bus;
         int na, ns;
         int index, num_reg;
@@ -322,7 +322,7 @@ static void __init build_device_resources(struct of_device *op,
         if (!parent)
                 return;
 
-        p_op = to_of_device(parent);
+        p_op = to_platform_device(parent);
         bus = of_match_bus(p_op->dev.of_node);
         bus->count_cells(op->dev.of_node, &na, &ns);
 
@@ -344,6 +344,8 @@ static void __init build_device_resources(struct of_device *op,
                 num_reg = PROMREG_MAX;
         }
 
+        op->resource = op->archdata.resource;
+        op->num_resources = num_reg;
         for (index = 0; index < num_reg; index++) {
                 struct resource *r = &op->resource[index];
                 u32 addr[OF_MAX_ADDR_CELLS];
@@ -526,7 +528,7 @@ static unsigned int __init pci_irq_swizzle(struct device_node *dp,
 
 static int of_irq_verbose;
 
-static unsigned int __init build_one_device_irq(struct of_device *op,
+static unsigned int __init build_one_device_irq(struct platform_device *op,
                                                 struct device *parent,
                                                 unsigned int irq)
 {
@@ -628,10 +630,10 @@ out:
         return irq;
 }
 
-static struct of_device * __init scan_one_device(struct device_node *dp,
+static struct platform_device * __init scan_one_device(struct device_node *dp,
                                                  struct device *parent)
 {
-        struct of_device *op = kzalloc(sizeof(*op), GFP_KERNEL);
+        struct platform_device *op = kzalloc(sizeof(*op), GFP_KERNEL);
         const unsigned int *irq;
         struct dev_archdata *sd;
         int len, i;
@@ -644,34 +646,28 @@ static struct of_device * __init scan_one_device(struct device_node *dp,
 
         op->dev.of_node = dp;
 
-        op->clock_freq = of_getintprop_default(dp, "clock-frequency",
-                                               (25*1000*1000));
-        op->portid = of_getintprop_default(dp, "upa-portid", -1);
-        if (op->portid == -1)
-                op->portid = of_getintprop_default(dp, "portid", -1);
-
         irq = of_get_property(dp, "interrupts", &len);
         if (irq) {
-                op->num_irqs = len / 4;
+                op->archdata.num_irqs = len / 4;
 
                 /* Prevent overrunning the op->irqs[] array.  */
-                if (op->num_irqs > PROMINTR_MAX) {
+                if (op->archdata.num_irqs > PROMINTR_MAX) {
                         printk(KERN_WARNING "%s: Too many irqs (%d), "
                                "limiting to %d.\n",
-                               dp->full_name, op->num_irqs, PROMINTR_MAX);
-                        op->num_irqs = PROMINTR_MAX;
+                               dp->full_name, op->archdata.num_irqs, PROMINTR_MAX);
+                        op->archdata.num_irqs = PROMINTR_MAX;
                 }
-                memcpy(op->irqs, irq, op->num_irqs * 4);
+                memcpy(op->archdata.irqs, irq, op->archdata.num_irqs * 4);
         } else {
-                op->num_irqs = 0;
+                op->archdata.num_irqs = 0;
         }
 
         build_device_resources(op, parent);
-        for (i = 0; i < op->num_irqs; i++)
-                op->irqs[i] = build_one_device_irq(op, parent, op->irqs[i]);
+        for (i = 0; i < op->archdata.num_irqs; i++)
+                op->archdata.irqs[i] = build_one_device_irq(op, parent, op->archdata.irqs[i]);
 
         op->dev.parent = parent;
-        op->dev.bus = &of_platform_bus_type;
+        op->dev.bus = &platform_bus_type;
         if (!parent)
                 dev_set_name(&op->dev, "root");
         else
@@ -690,7 +686,7 @@ static struct of_device * __init scan_one_device(struct device_node *dp,
 static void __init scan_tree(struct device_node *dp, struct device *parent)
 {
         while (dp) {
-                struct of_device *op = scan_one_device(dp, parent);
+                struct platform_device *op = scan_one_device(dp, parent);
 
                 if (op)
                         scan_tree(dp->child, &op->dev);
@@ -699,30 +695,19 @@ static void __init scan_tree(struct device_node *dp, struct device *parent)
         }
 }
 
-static void __init scan_of_devices(void)
+static int __init scan_of_devices(void)
 {
         struct device_node *root = of_find_node_by_path("/");
-        struct of_device *parent;
+        struct platform_device *parent;
 
         parent = scan_one_device(root, NULL);
         if (!parent)
-                return;
+                return 0;
 
         scan_tree(root->child, &parent->dev);
+        return 0;
 }
-
-static int __init of_bus_driver_init(void)
-{
-        int err;
-
-        err = of_bus_type_init(&of_platform_bus_type, "of");
-        if (!err)
-                scan_of_devices();
-
-        return err;
-}
-
-postcore_initcall(of_bus_driver_init);
+postcore_initcall(scan_of_devices);
 
 static int __init of_debug(char *str)
 {
diff --git a/arch/sparc/kernel/of_device_common.c b/arch/sparc/kernel/of_device_common.c
index 10c6c36a6e75..49ddff56cb04 100644
--- a/arch/sparc/kernel/of_device_common.c
+++ b/arch/sparc/kernel/of_device_common.c
@@ -11,48 +11,28 @@
 
 #include "of_device_common.h"
 
-static int node_match(struct device *dev, void *data)
-{
-        struct of_device *op = to_of_device(dev);
-        struct device_node *dp = data;
-
-        return (op->dev.of_node == dp);
-}
-
-struct of_device *of_find_device_by_node(struct device_node *dp)
-{
-        struct device *dev = bus_find_device(&of_platform_bus_type, NULL,
-                                             dp, node_match);
-
-        if (dev)
-                return to_of_device(dev);
-
-        return NULL;
-}
-EXPORT_SYMBOL(of_find_device_by_node);
-
 unsigned int irq_of_parse_and_map(struct device_node *node, int index)
 {
-        struct of_device *op = of_find_device_by_node(node);
+        struct platform_device *op = of_find_device_by_node(node);
 
-        if (!op || index >= op->num_irqs)
+        if (!op || index >= op->archdata.num_irqs)
                 return 0;
 
-        return op->irqs[index];
+        return op->archdata.irqs[index];
 }
 EXPORT_SYMBOL(irq_of_parse_and_map);
 
 /* Take the archdata values for IOMMU, STC, and HOSTDATA found in
- * BUS and propagate to all child of_device objects.
+ * BUS and propagate to all child platform_device objects.
  */
-void of_propagate_archdata(struct of_device *bus)
+void of_propagate_archdata(struct platform_device *bus)
 {
         struct dev_archdata *bus_sd = &bus->dev.archdata;
         struct device_node *bus_dp = bus->dev.of_node;
         struct device_node *dp;
 
         for (dp = bus_dp->child; dp; dp = dp->sibling) {
-                struct of_device *op = of_find_device_by_node(dp);
+                struct platform_device *op = of_find_device_by_node(dp);
 
                 op->dev.archdata.iommu = bus_sd->iommu;
                 op->dev.archdata.stc = bus_sd->stc;
@@ -64,9 +44,6 @@ void of_propagate_archdata(struct of_device *bus)
         }
 }
 
-struct bus_type of_platform_bus_type;
-EXPORT_SYMBOL(of_platform_bus_type);
-
 static void get_cells(struct device_node *dp, int *addrc, int *sizec)
 {
         if (addrc)
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 8a8363adb8bd..4137579d9adc 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -198,7 +198,7 @@ static unsigned long pci_parse_of_flags(u32 addr0)
  * into physical address resources, we only have to figure out the register
  * mapping.
  */
-static void pci_parse_of_addrs(struct of_device *op,
+static void pci_parse_of_addrs(struct platform_device *op,
                                struct device_node *node,
                                struct pci_dev *dev)
 {
@@ -248,7 +248,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 {
         struct dev_archdata *sd;
         struct pci_slot *slot;
-        struct of_device *op;
+        struct platform_device *op;
         struct pci_dev *dev;
         const char *type;
         u32 class;
@@ -340,7 +340,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
                 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
                 dev->rom_base_reg = PCI_ROM_ADDRESS;
 
-                dev->irq = sd->op->irqs[0];
+                dev->irq = sd->op->archdata.irqs[0];
                 if (dev->irq == 0xffffffff)
                         dev->irq = PCI_IRQ_NONE;
         }
diff --git a/arch/sparc/kernel/pci_fire.c b/arch/sparc/kernel/pci_fire.c
index 51cfa09e392a..efb896d68754 100644
--- a/arch/sparc/kernel/pci_fire.c
+++ b/arch/sparc/kernel/pci_fire.c
@@ -410,7 +410,7 @@ static void pci_fire_hw_init(struct pci_pbm_info *pbm)
 }
 
 static int __devinit pci_fire_pbm_init(struct pci_pbm_info *pbm,
-                                       struct of_device *op, u32 portid)
+                                       struct platform_device *op, u32 portid)
 {
         const struct linux_prom64_registers *regs;
         struct device_node *dp = op->dev.of_node;
@@ -455,7 +455,7 @@ static int __devinit pci_fire_pbm_init(struct pci_pbm_info *pbm,
         return 0;
 }
 
-static int __devinit fire_probe(struct of_device *op,
+static int __devinit fire_probe(struct platform_device *op,
                                 const struct of_device_id *match)
 {
         struct device_node *dp = op->dev.of_node;
@@ -518,7 +518,7 @@ static struct of_platform_driver fire_driver = {
 
 static int __init fire_init(void)
 {
-        return of_register_driver(&fire_driver, &of_bus_type);
+        return of_register_platform_driver(&fire_driver);
 }
 
 subsys_initcall(fire_init);
diff --git a/arch/sparc/kernel/pci_impl.h b/arch/sparc/kernel/pci_impl.h
index 03186824327e..e20ed5f06e9c 100644
--- a/arch/sparc/kernel/pci_impl.h
+++ b/arch/sparc/kernel/pci_impl.h
@@ -91,7 +91,7 @@ struct pci_pbm_info {
         char                            *name;
 
         /* OBP specific information. */
-        struct of_device                *op;
+        struct platform_device          *op;
         u64                             ino_bitmap;
 
         /* PBM I/O and Memory space resources. */
diff --git a/arch/sparc/kernel/pci_psycho.c b/arch/sparc/kernel/pci_psycho.c
index 558a70512824..22eab7cf3b11 100644
--- a/arch/sparc/kernel/pci_psycho.c
+++ b/arch/sparc/kernel/pci_psycho.c
@@ -285,7 +285,7 @@ static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
 #define  PSYCHO_ECCCTRL_CE       0x2000000000000000UL /* Enable CE INterrupts */
 static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
 {
-        struct of_device *op = of_find_device_by_node(pbm->op->dev.of_node);
+        struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
         unsigned long base = pbm->controller_regs;
         u64 tmp;
         int err;
@@ -302,23 +302,23 @@ static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
          * 5: POWER MANAGEMENT
          */
 
-        if (op->num_irqs < 6)
+        if (op->archdata.num_irqs < 6)
                 return;
 
         /* We really mean to ignore the return result here.  Two
          * PCI controller share the same interrupt numbers and
          * drive the same front-end hardware.
          */
-        err = request_irq(op->irqs[1], psycho_ue_intr, IRQF_SHARED,
+        err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED,
                           "PSYCHO_UE", pbm);
-        err = request_irq(op->irqs[2], psycho_ce_intr, IRQF_SHARED,
+        err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED,
                           "PSYCHO_CE", pbm);
 
         /* This one, however, ought not to fail.  We can just warn
          * about it since the system can still operate properly even
          * if this fails.
          */
-        err = request_irq(op->irqs[0], psycho_pcierr_intr, IRQF_SHARED,
+        err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED,
                           "PSYCHO_PCIERR", pbm);
         if (err)
                 printk(KERN_WARNING "%s: Could not register PCIERR, "
@@ -483,7 +483,7 @@ static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
 #define PSYCHO_MEMSPACE_SIZE    0x07fffffffUL
 
 static void __devinit psycho_pbm_init(struct pci_pbm_info *pbm,
-                                      struct of_device *op, int is_pbm_a)
+                                      struct platform_device *op, int is_pbm_a)
 {
         psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
         psycho_pbm_strbuf_init(pbm, is_pbm_a);
@@ -503,7 +503,7 @@ static struct pci_pbm_info * __devinit psycho_find_sibling(u32 upa_portid)
 
 #define PSYCHO_CONFIGSPACE      0x001000000UL
 
-static int __devinit psycho_probe(struct of_device *op,
+static int __devinit psycho_probe(struct platform_device *op,
                                   const struct of_device_id *match)
 {
         const struct linux_prom64_registers *pr_regs;
@@ -612,7 +612,7 @@ static struct of_platform_driver psycho_driver = {
 
 static int __init psycho_init(void)
 {
-        return of_register_driver(&psycho_driver, &of_bus_type);
+        return of_register_platform_driver(&psycho_driver);
 }
 
 subsys_initcall(psycho_init);
diff --git a/arch/sparc/kernel/pci_sabre.c b/arch/sparc/kernel/pci_sabre.c
index 6dad8e3b7506..5c3f5ec4cabc 100644
--- a/arch/sparc/kernel/pci_sabre.c
+++ b/arch/sparc/kernel/pci_sabre.c
@@ -311,7 +311,7 @@ static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
 {
         struct device_node *dp = pbm->op->dev.of_node;
-        struct of_device *op;
+        struct platform_device *op;
         unsigned long base = pbm->controller_regs;
         u64 tmp;
         int err;
@@ -329,7 +329,7 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
          * 2: CE ERR
          * 3: POWER FAIL
          */
-        if (op->num_irqs < 4)
+        if (op->archdata.num_irqs < 4)
                 return;
 
         /* We clear the error bits in the appropriate AFSR before
@@ -341,7 +341,7 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
                     SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE),
                    base + SABRE_UE_AFSR);
 
-        err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
+        err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
         if (err)
                 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
                        pbm->name, err);
@@ -351,11 +351,11 @@ static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
                    base + SABRE_CE_AFSR);
 
 
-        err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
+        err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
         if (err)
                 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
                        pbm->name, err);
-        err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
+        err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0,
                           "SABRE_PCIERR", pbm);
         if (err)
                 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
@@ -443,7 +443,7 @@ static void __devinit sabre_scan_bus(struct pci_pbm_info *pbm,
 }
 
 static void __devinit sabre_pbm_init(struct pci_pbm_info *pbm,
-                                     struct of_device *op)
+                                     struct platform_device *op)
 {
         psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
         pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
@@ -452,7 +452,7 @@ static void __devinit sabre_pbm_init(struct pci_pbm_info *pbm,
         sabre_scan_bus(pbm, &op->dev);
 }
 
-static int __devinit sabre_probe(struct of_device *op,
+static int __devinit sabre_probe(struct platform_device *op,
                                  const struct of_device_id *match)
 {
         const struct linux_prom64_registers *pr_regs;
@@ -606,7 +606,7 @@ static struct of_platform_driver sabre_driver = {
 
 static int __init sabre_init(void)
 {
-        return of_register_driver(&sabre_driver, &of_bus_type);
+        return of_register_platform_driver(&sabre_driver);
 }
 
 subsys_initcall(sabre_init);
diff --git a/arch/sparc/kernel/pci_schizo.c b/arch/sparc/kernel/pci_schizo.c
index 97a1ae2e1c02..445a47a2fb3d 100644
--- a/arch/sparc/kernel/pci_schizo.c
+++ b/arch/sparc/kernel/pci_schizo.c
@@ -844,7 +844,7 @@ static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
  */
 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
 {
-        struct of_device *op = of_find_device_by_node(pbm->op->dev.of_node);
+        struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
         u64 tmp, err_mask, err_no_mask;
         int err;
 
@@ -857,14 +857,14 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
          */
 
         if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
-                err = request_irq(op->irqs[1], schizo_ue_intr, 0,
+                err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
                                   "TOMATILLO_UE", pbm);
                 if (err)
                         printk(KERN_WARNING "%s: Could not register UE, "
                                "err=%d\n", pbm->name, err);
         }
         if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
-                err = request_irq(op->irqs[2], schizo_ce_intr, 0,
+                err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
                                   "TOMATILLO_CE", pbm);
                 if (err)
                         printk(KERN_WARNING "%s: Could not register CE, "
@@ -872,10 +872,10 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
         }
         err = 0;
         if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
-                err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
+                err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
                                   "TOMATILLO_PCIERR", pbm);
         } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
-                err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
+                err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
                                   "TOMATILLO_PCIERR", pbm);
         }
         if (err)
@@ -883,7 +883,7 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
                        "err=%d\n", pbm->name, err);
 
         if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
-                err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
+                err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
                                   "TOMATILLO_SERR", pbm);
                 if (err)
                         printk(KERN_WARNING "%s: Could not register SERR, "
@@ -939,7 +939,7 @@ static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
 
 static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
 {
-        struct of_device *op = of_find_device_by_node(pbm->op->dev.of_node);
+        struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
         u64 tmp, err_mask, err_no_mask;
         int err;
 
@@ -952,14 +952,14 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
          */
 
         if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
-                err = request_irq(op->irqs[1], schizo_ue_intr, 0,
+                err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
                                   "SCHIZO_UE", pbm);
                 if (err)
                         printk(KERN_WARNING "%s: Could not register UE, "
                                "err=%d\n", pbm->name, err);
         }
         if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
-                err = request_irq(op->irqs[2], schizo_ce_intr, 0,
+                err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
                                   "SCHIZO_CE", pbm);
                 if (err)
                         printk(KERN_WARNING "%s: Could not register CE, "
@@ -967,10 +967,10 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
         }
         err = 0;
         if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
-                err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
+                err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
                                   "SCHIZO_PCIERR", pbm);
         } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
-                err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
+                err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
                                   "SCHIZO_PCIERR", pbm);
         }
         if (err)
@@ -978,7 +978,7 @@ static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
                        "err=%d\n", pbm->name, err);
 
         if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
-                err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
+                err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
                                   "SCHIZO_SERR", pbm);
                 if (err)
                         printk(KERN_WARNING "%s: Could not register SERR, "
@@ -1307,7 +1307,7 @@ static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
 }
 
 static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm,
-                                     struct of_device *op, u32 portid,
+                                     struct platform_device *op, u32 portid,
                                      int chip_type)
 {
         const struct linux_prom64_registers *regs;
@@ -1413,7 +1413,7 @@ static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid,
         return NULL;
 }
 
-static int __devinit __schizo_init(struct of_device *op, unsigned long chip_type)
+static int __devinit __schizo_init(struct platform_device *op, unsigned long chip_type)
 {
         struct device_node *dp = op->dev.of_node;
         struct pci_pbm_info *pbm;
@@ -1460,7 +1460,7 @@ out_err:
         return err;
 }
 
-static int __devinit schizo_probe(struct of_device *op,
+static int __devinit schizo_probe(struct platform_device *op,
                                   const struct of_device_id *match)
 {
         return __schizo_init(op, (unsigned long) match->data);
@@ -1501,7 +1501,7 @@ static struct of_platform_driver schizo_driver = {
 
 static int __init schizo_init(void)
 {
-        return of_register_driver(&schizo_driver, &of_bus_type);
+        return of_register_platform_driver(&schizo_driver);
 }
 
 subsys_initcall(schizo_init);
diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c
index a24af6f7e17f..743344aa6d8a 100644
--- a/arch/sparc/kernel/pci_sun4v.c
+++ b/arch/sparc/kernel/pci_sun4v.c
@@ -879,7 +879,7 @@ static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
 #endif /* !(CONFIG_PCI_MSI) */
 
 static int __devinit pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
-                                        struct of_device *op, u32 devhandle)
+                                        struct platform_device *op, u32 devhandle)
 {
         struct device_node *dp = op->dev.of_node;
         int err;
@@ -918,7 +918,7 @@ static int __devinit pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
         return 0;
 }
 
-static int __devinit pci_sun4v_probe(struct of_device *op,
+static int __devinit pci_sun4v_probe(struct platform_device *op,
                                      const struct of_device_id *match)
 {
         const struct linux_prom64_registers *regs;
@@ -1019,7 +1019,7 @@ static struct of_platform_driver pci_sun4v_driver = {
 
 static int __init pci_sun4v_init(void)
 {
-        return of_register_driver(&pci_sun4v_driver, &of_bus_type);
+        return of_register_platform_driver(&pci_sun4v_driver);
 }
 
 subsys_initcall(pci_sun4v_init);
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 44faabc3c02c..357ced3c33ff 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -572,18 +572,18 @@ static u64 sparc_perf_event_update(struct perf_event *event,
         s64 delta;
 
 again:
-        prev_raw_count = atomic64_read(&hwc->prev_count);
+        prev_raw_count = local64_read(&hwc->prev_count);
         new_raw_count = read_pmc(idx);
 
-        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
                              new_raw_count) != prev_raw_count)
                 goto again;
 
         delta = (new_raw_count << shift) - (prev_raw_count << shift);
         delta >>= shift;
 
-        atomic64_add(delta, &event->count);
-        atomic64_sub(delta, &hwc->period_left);
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
 
         return new_raw_count;
 }
@@ -591,27 +591,27 @@ again:
 static int sparc_perf_event_set_period(struct perf_event *event,
                                        struct hw_perf_event *hwc, int idx)
 {
-        s64 left = atomic64_read(&hwc->period_left);
+        s64 left = local64_read(&hwc->period_left);
         s64 period = hwc->sample_period;
         int ret = 0;
 
         if (unlikely(left <= -period)) {
                 left = period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
 
         if (unlikely(left <= 0)) {
                 left += period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
         if (left > MAX_PERIOD)
                 left = MAX_PERIOD;
 
-        atomic64_set(&hwc->prev_count, (u64)-left);
+        local64_set(&hwc->prev_count, (u64)-left);
 
         write_pmc(idx, (u64)(-left) & 0xffffffff);
 
@@ -1006,7 +1006,7 @@ static int sparc_pmu_enable(struct perf_event *event)
          * skip the schedulability test here, it will be peformed
          * at commit time(->commit_txn) as a whole
          */
-        if (cpuc->group_flag & PERF_EVENT_TXN_STARTED)
+        if (cpuc->group_flag & PERF_EVENT_TXN)
                 goto nocheck;
 
         if (check_excludes(cpuc->event, n0, 1))
@@ -1088,7 +1088,7 @@ static int __hw_perf_event_init(struct perf_event *event)
         if (!hwc->sample_period) {
                 hwc->sample_period = MAX_PERIOD;
                 hwc->last_period = hwc->sample_period;
-                atomic64_set(&hwc->period_left, hwc->sample_period);
+                local64_set(&hwc->period_left, hwc->sample_period);
         }
 
         return 0;
@@ -1103,7 +1103,7 @@ static void sparc_pmu_start_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 
-        cpuhw->group_flag |= PERF_EVENT_TXN_STARTED;
+        cpuhw->group_flag |= PERF_EVENT_TXN;
 }
 
 /*
@@ -1115,7 +1115,7 @@ static void sparc_pmu_cancel_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 
-        cpuhw->group_flag &= ~PERF_EVENT_TXN_STARTED;
+        cpuhw->group_flag &= ~PERF_EVENT_TXN;
 }
 
 /*
@@ -1138,6 +1138,7 @@ static int sparc_pmu_commit_txn(const struct pmu *pmu)
         if (sparc_check_constraints(cpuc->event, cpuc->events, n))
                 return -EAGAIN;
 
+        cpuc->group_flag &= ~PERF_EVENT_TXN;
         return 0;
 }
 
diff --git a/arch/sparc/kernel/pmc.c b/arch/sparc/kernel/pmc.c
index 9589d8b9b0c1..94536a85f161 100644
--- a/arch/sparc/kernel/pmc.c
+++ b/arch/sparc/kernel/pmc.c
@@ -51,7 +51,7 @@ static void pmc_swift_idle(void)
 #endif
 }
 
-static int __devinit pmc_probe(struct of_device *op,
+static int __devinit pmc_probe(struct platform_device *op,
                                const struct of_device_id *match)
 {
         regs = of_ioremap(&op->resource[0], 0,
@@ -89,7 +89,7 @@ static struct of_platform_driver pmc_driver = {
 
 static int __init pmc_init(void)
 {
-        return of_register_driver(&pmc_driver, &of_bus_type);
+        return of_register_platform_driver(&pmc_driver);
 }
 
 /* This driver is not critical to the boot process
diff --git a/arch/sparc/kernel/power.c b/arch/sparc/kernel/power.c
index 168d4cb63f5b..2c59f4d387dd 100644
--- a/arch/sparc/kernel/power.c
+++ b/arch/sparc/kernel/power.c
@@ -33,10 +33,10 @@ static int __devinit has_button_interrupt(unsigned int irq, struct device_node *
         return 1;
 }
 
-static int __devinit power_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit power_probe(struct platform_device *op, const struct of_device_id *match)
 {
         struct resource *res = &op->resource[0];
-        unsigned int irq= op->irqs[0];
+        unsigned int irq = op->archdata.irqs[0];
 
         power_reg = of_ioremap(res, 0, 0x4, "power");
 
@@ -70,7 +70,7 @@ static struct of_platform_driver power_driver = {
 
 static int __init power_init(void)
 {
-        return of_register_driver(&power_driver, &of_platform_bus_type);
+        return of_register_platform_driver(&power_driver);
 }
 
 device_initcall(power_init);
diff --git a/arch/sparc/kernel/prom.h b/arch/sparc/kernel/prom.h
index a8591ef2636d..eeb04a782ec8 100644
--- a/arch/sparc/kernel/prom.h
+++ b/arch/sparc/kernel/prom.h
@@ -9,14 +9,6 @@ extern void irq_trans_init(struct device_node *dp);
 
 extern unsigned int prom_unique_id;
 
-static inline int is_root_node(const struct device_node *dp)
-{
-        if (!dp)
-                return 0;
-
-        return (dp->parent == NULL);
-}
-
 extern char *build_path_component(struct device_node *dp);
 extern void of_console_init(void);
 
diff --git a/arch/sparc/kernel/prom_64.c b/arch/sparc/kernel/prom_64.c
index 466a32763ea8..86597d9867fd 100644
--- a/arch/sparc/kernel/prom_64.c
+++ b/arch/sparc/kernel/prom_64.c
@@ -21,7 +21,7 @@
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/memblock.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
 
 #include <asm/prom.h>
 #include <asm/oplib.h>
@@ -81,7 +81,7 @@ static void __init sun4v_path_component(struct device_node *dp, char *tmp_buf)
                 return;
 
         regs = rprop->value;
-        if (!is_root_node(dp->parent)) {
+        if (!of_node_is_root(dp->parent)) {
                 sprintf(tmp_buf, "%s@%x,%x",
                         dp->name,
                         (unsigned int) (regs->phys_addr >> 32UL),
@@ -121,7 +121,7 @@ static void __init sun4u_path_component(struct device_node *dp, char *tmp_buf)
                 return;
 
         regs = prop->value;
-        if (!is_root_node(dp->parent)) {
+        if (!of_node_is_root(dp->parent)) {
                 sprintf(tmp_buf, "%s@%x,%x",
                         dp->name,
                         (unsigned int) (regs->phys_addr >> 32UL),
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 57ac9e28be0c..1f830da2ddf2 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -244,7 +244,7 @@ char * __init build_full_name(struct device_node *dp)
 
         n = prom_early_alloc(len);
         strcpy(n, dp->parent->full_name);
-        if (!is_root_node(dp->parent)) {
+        if (!of_node_is_root(dp->parent)) {
                 strcpy(n + plen, "/");
                 plen++;
         }
diff --git a/arch/sparc/kernel/prom_irqtrans.c b/arch/sparc/kernel/prom_irqtrans.c
index 5702ad4710cb..ce651147fabc 100644
--- a/arch/sparc/kernel/prom_irqtrans.c
+++ b/arch/sparc/kernel/prom_irqtrans.c
@@ -719,7 +719,7 @@ static unsigned int central_build_irq(struct device_node *dp,
                                       void *_data)
 {
         struct device_node *central_dp = _data;
-        struct of_device *central_op = of_find_device_by_node(central_dp);
+        struct platform_device *central_op = of_find_device_by_node(central_dp);
         struct resource *res;
         unsigned long imap, iclr;
         u32 tmp;
diff --git a/arch/sparc/kernel/psycho_common.c b/arch/sparc/kernel/psycho_common.c
index 3f34ac853931..fe2af66bb198 100644
--- a/arch/sparc/kernel/psycho_common.c
+++ b/arch/sparc/kernel/psycho_common.c
@@ -447,7 +447,7 @@ int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
 
 }
 
-void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct of_device *op,
+void psycho_pbm_init_common(struct pci_pbm_info *pbm, struct platform_device *op,
                             const char *chip_name, int chip_type)
 {
         struct device_node *dp = op->dev.of_node;
diff --git a/arch/sparc/kernel/psycho_common.h b/arch/sparc/kernel/psycho_common.h
index 092c278ef28d..590b4ed8ab5e 100644
--- a/arch/sparc/kernel/psycho_common.h
+++ b/arch/sparc/kernel/psycho_common.h
@@ -42,7 +42,7 @@ extern int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize,
                              unsigned long write_complete_offset);
 
 extern void psycho_pbm_init_common(struct pci_pbm_info *pbm,
-                                   struct of_device *op,
+                                   struct platform_device *op,
                                    const char *chip_name, int chip_type);
 
 #endif /* _PSYCHO_COMMON_H */
diff --git a/arch/sparc/kernel/sbus.c b/arch/sparc/kernel/sbus.c
index cfeaf04b9cdf..2ca32d13abcf 100644
--- a/arch/sparc/kernel/sbus.c
+++ b/arch/sparc/kernel/sbus.c
@@ -57,7 +57,7 @@
 void sbus_set_sbus64(struct device *dev, int bursts)
 {
         struct iommu *iommu = dev->archdata.iommu;
-        struct of_device *op = to_of_device(dev);
+        struct platform_device *op = to_platform_device(dev);
         const struct linux_prom_registers *regs;
         unsigned long cfg_reg;
         int slot;
@@ -204,7 +204,7 @@ static unsigned long sysio_imap_to_iclr(unsigned long imap)
         return imap + diff;
 }
 
-static unsigned int sbus_build_irq(struct of_device *op, unsigned int ino)
+static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino)
 {
         struct iommu *iommu = op->dev.archdata.iommu;
         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
@@ -267,7 +267,7 @@ static unsigned int sbus_build_irq(struct of_device *op, unsigned int ino)
 #define  SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
 static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
 {
-        struct of_device *op = dev_id;
+        struct platform_device *op = dev_id;
         struct iommu *iommu = op->dev.archdata.iommu;
         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
         unsigned long afsr_reg, afar_reg;
@@ -341,7 +341,7 @@ static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
 #define  SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
 static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
 {
-        struct of_device *op = dev_id;
+        struct platform_device *op = dev_id;
         struct iommu *iommu = op->dev.archdata.iommu;
         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
         unsigned long afsr_reg, afar_reg;
@@ -420,7 +420,7 @@ static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
 #define  SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved                  */
 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
 {
-        struct of_device *op = dev_id;
+        struct platform_device *op = dev_id;
         struct iommu *iommu = op->dev.archdata.iommu;
         unsigned long afsr_reg, afar_reg, reg_base;
         unsigned long afsr, afar, error_bits;
@@ -488,7 +488,7 @@ static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
 #define SYSIO_CE_INO            0x35
 #define SYSIO_SBUSERR_INO       0x36
 
-static void __init sysio_register_error_handlers(struct of_device *op)
+static void __init sysio_register_error_handlers(struct platform_device *op)
 {
         struct iommu *iommu = op->dev.archdata.iommu;
         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
@@ -534,7 +534,7 @@ static void __init sysio_register_error_handlers(struct of_device *op)
 }
 
 /* Boot time initialization. */
-static void __init sbus_iommu_init(struct of_device *op)
+static void __init sbus_iommu_init(struct platform_device *op)
 {
         const struct linux_prom64_registers *pr;
         struct device_node *dp = op->dev.of_node;
@@ -663,7 +663,7 @@ static int __init sbus_init(void)
         struct device_node *dp;
 
         for_each_node_by_name(dp, "sbus") {
-                struct of_device *op = of_find_device_by_node(dp);
+                struct platform_device *op = of_find_device_by_node(dp);
 
                 sbus_iommu_init(op);
                 of_propagate_archdata(op);
diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c
index e404b063be2c..9c743b1886ff 100644
--- a/arch/sparc/kernel/time_32.c
+++ b/arch/sparc/kernel/time_32.c
@@ -142,7 +142,7 @@ static struct platform_device m48t59_rtc = {
         },
 };
 
-static int __devinit clock_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit clock_probe(struct platform_device *op, const struct of_device_id *match)
 {
         struct device_node *dp = op->dev.of_node;
         const char *model = of_get_property(dp, "model", NULL);
@@ -189,7 +189,7 @@ static struct of_platform_driver clock_driver = {
 /* Probe for the mostek real time clock chip. */
 static int __init clock_init(void)
 {
-        return of_register_driver(&clock_driver, &of_platform_bus_type);
+        return of_register_platform_driver(&clock_driver);
 }
 /* Must be after subsys_initcall() so that busses are probed.  Must
  * be before device_initcall() because things like the RTC driver
diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c
index 21e9fcae0668..3bc9c9979b92 100644
--- a/arch/sparc/kernel/time_64.c
+++ b/arch/sparc/kernel/time_64.c
@@ -419,7 +419,7 @@ static struct platform_device rtc_cmos_device = {
         .num_resources  = 1,
 };
 
-static int __devinit rtc_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit rtc_probe(struct platform_device *op, const struct of_device_id *match)
 {
         struct resource *r;
 
@@ -477,7 +477,7 @@ static struct platform_device rtc_bq4802_device = {
         .num_resources  = 1,
 };
 
-static int __devinit bq4802_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit bq4802_probe(struct platform_device *op, const struct of_device_id *match)
 {
 
         printk(KERN_INFO "%s: BQ4802 regs at 0x%llx\n",
@@ -534,7 +534,7 @@ static struct platform_device m48t59_rtc = {
         },
 };
 
-static int __devinit mostek_probe(struct of_device *op, const struct of_device_id *match)
+static int __devinit mostek_probe(struct platform_device *op, const struct of_device_id *match)
 {
         struct device_node *dp = op->dev.of_node;
 
@@ -586,9 +586,9 @@ static int __init clock_init(void)
         if (tlb_type == hypervisor)
                 return platform_device_register(&rtc_sun4v_device);
 
-        (void) of_register_driver(&rtc_driver, &of_platform_bus_type);
-        (void) of_register_driver(&mostek_driver, &of_platform_bus_type);
-        (void) of_register_driver(&bq4802_driver, &of_platform_bus_type);
+        (void) of_register_platform_driver(&rtc_driver);
+        (void) of_register_platform_driver(&mostek_driver);
+        (void) of_register_platform_driver(&bq4802_driver);
 
         return 0;
 }
diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c
index 005e758a4db7..fc58c3e917df 100644
--- a/arch/sparc/mm/io-unit.c
+++ b/arch/sparc/mm/io-unit.c
@@ -35,7 +35,7 @@
 #define IOPERM        (IOUPTE_CACHE | IOUPTE_WRITE | IOUPTE_VALID)
 #define MKIOPTE(phys) __iopte((((phys)>>4) & IOUPTE_PAGE) | IOPERM)
 
-static void __init iounit_iommu_init(struct of_device *op)
+static void __init iounit_iommu_init(struct platform_device *op)
 {
         struct iounit_struct *iounit;
         iopte_t *xpt, *xptend;
@@ -74,7 +74,7 @@ static int __init iounit_init(void)
         struct device_node *dp;
 
         for_each_node_by_name(dp, "sbi") {
-                struct of_device *op = of_find_device_by_node(dp);
+                struct platform_device *op = of_find_device_by_node(dp);
 
                 iounit_iommu_init(op);
                 of_propagate_archdata(op);
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
index b2e6e73888b5..07fc6a65d9b6 100644
--- a/arch/sparc/mm/iommu.c
+++ b/arch/sparc/mm/iommu.c
@@ -56,14 +56,14 @@ static pgprot_t dvma_prot;		/* Consistent mapping pte flags */
 #define IOPERM        (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
 #define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
 
-static void __init sbus_iommu_init(struct of_device *op)
+static void __init sbus_iommu_init(struct platform_device *op)
 {
         struct iommu_struct *iommu;
         unsigned int impl, vers;
         unsigned long *bitmap;
         unsigned long tmp;
 
-        iommu = kmalloc(sizeof(struct iommu_struct), GFP_ATOMIC);
+        iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
         if (!iommu) {
                 prom_printf("Unable to allocate iommu structure\n");
                 prom_halt();
@@ -132,7 +132,7 @@ static int __init iommu_init(void)
         struct device_node *dp;
 
         for_each_node_by_name(dp, "iommu") {
-                struct of_device *op = of_find_device_by_node(dp);
+                struct platform_device *op = of_find_device_by_node(dp);
 
                 sbus_iommu_init(op);
                 of_propagate_archdata(op);
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index 0d207e73a758..7c8e277f6d34 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -55,10 +55,6 @@ config GENERIC_BUG
         default y
         depends on BUG
 
-config GENERIC_TIME
-        bool
-        default y
-
 config GENERIC_CLOCKEVENTS
         bool
         default y
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index f05372694233..2ab233ba32c1 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -25,11 +25,6 @@
 #include "net_kern.h"
 #include "net_user.h"
 
-static inline void set_ether_mac(struct net_device *dev, unsigned char *addr)
-{
-        memcpy(dev->dev_addr, addr, ETH_ALEN);
-}
-
 #define DRIVER_NAME "uml-netdev"
 
 static DEFINE_SPINLOCK(opened_lock);
@@ -266,7 +261,7 @@ static int uml_net_set_mac(struct net_device *dev, void *addr)
         struct sockaddr *hwaddr = addr;
 
         spin_lock_irq(&lp->lock);
-        set_ether_mac(dev, hwaddr->sa_data);
+        eth_mac_addr(dev, hwaddr->sa_data);
         spin_unlock_irq(&lp->lock);
 
         return 0;
@@ -380,7 +375,6 @@ static const struct net_device_ops uml_netdev_ops = {
         .ndo_tx_timeout         = uml_net_tx_timeout,
         .ndo_set_mac_address    = uml_net_set_mac,
         .ndo_change_mtu         = uml_net_change_mtu,
-        .ndo_set_mac_address    = eth_mac_addr,
         .ndo_validate_addr      = eth_validate_addr,
 };
 
@@ -478,7 +472,7 @@ static void eth_configure(int n, void *init, char *mac,
             ((*transport->user->init)(&lp->user, dev) != 0))
                 goto out_unregister;
 
-        set_ether_mac(dev, device->mac);
+        eth_mac_addr(dev, device->mac);
         dev->mtu = transport->user->mtu;
         dev->netdev_ops = &uml_netdev_ops;
         dev->ethtool_ops = &uml_net_ethtool_ops;
diff --git a/arch/um/include/asm/pgtable-3level.h b/arch/um/include/asm/pgtable-3level.h
index 084de4a9fc70..0032f9212e74 100644
--- a/arch/um/include/asm/pgtable-3level.h
+++ b/arch/um/include/asm/pgtable-3level.h
@@ -60,7 +60,7 @@
         set_pud(pud, __pud(_PAGE_TABLE + __pa(pmd)))
 
 #ifdef CONFIG_64BIT
-#define set_pud(pudptr, pudval) set_64bit((phys_t *) (pudptr), pud_val(pudval))
+#define set_pud(pudptr, pudval) set_64bit((u64 *) (pudptr), pud_val(pudval))
 #else
 #define set_pud(pudptr, pudval) (*(pudptr) = (pudval))
 #endif
@@ -73,7 +73,7 @@ static inline int pgd_newpage(pgd_t pgd)
 static inline void pgd_mkuptodate(pgd_t pgd) { pgd_val(pgd) &= ~_PAGE_NEWPAGE; }
 
 #ifdef CONFIG_64BIT
-#define set_pmd(pmdptr, pmdval) set_64bit((phys_t *) (pmdptr), pmd_val(pmdval))
+#define set_pmd(pmdptr, pmdval) set_64bit((u64 *) (pmdptr), pmd_val(pmdval))
 #else
 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
 #endif
diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c
index c8b9c469fcd7..a08d9fab81f2 100644
--- a/arch/um/kernel/time.c
+++ b/arch/um/kernel/time.c
@@ -102,16 +102,16 @@ static void __init setup_itimer(void)
         clockevents_register_device(&itimer_clockevent);
 }
 
-void __init time_init(void)
+void read_persistent_clock(struct timespec *ts)
 {
-        long long nsecs;
-
-        timer_init();
+        long long nsecs = os_nsecs();
 
-        nsecs = os_nsecs();
-        set_normalized_timespec(&wall_to_monotonic, -nsecs / NSEC_PER_SEC,
-                                -nsecs % NSEC_PER_SEC);
-        set_normalized_timespec(&xtime, nsecs / NSEC_PER_SEC,
+        set_normalized_timespec(ts, nsecs / NSEC_PER_SEC,
                                 nsecs % NSEC_PER_SEC);
+}
+
+void __init time_init(void)
+{
+        timer_init();
         late_time_init = setup_itimer;
 }
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index dcb0593b4a66..baa34e510222 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -55,6 +55,7 @@ config X86
         select HAVE_HW_BREAKPOINT
         select HAVE_MIXED_BREAKPOINTS_REGS
         select PERF_EVENTS
+        select HAVE_PERF_EVENTS_NMI
         select ANON_INODES
         select HAVE_ARCH_KMEMCHECK
         select HAVE_USER_RETURN_NOTIFIER
@@ -72,9 +73,6 @@ config ARCH_DEFCONFIG
         default "arch/x86/configs/i386_defconfig" if X86_32
         default "arch/x86/configs/x86_64_defconfig" if X86_64
 
-config GENERIC_TIME
-        def_bool y
-
 config GENERIC_CMOS_UPDATE
         def_bool y
 
@@ -2046,7 +2044,7 @@ config SCx200
 
 config SCx200HR_TIMER
         tristate "NatSemi SCx200 27MHz High-Resolution Timer Support"
-        depends on SCx200 && GENERIC_TIME
+        depends on SCx200
         default y
         ---help---
           This driver provides a clocksource built upon the on-chip
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index ec749c2bfdd7..f7cb086b4add 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -26,10 +26,10 @@ targets		:= vmlinux.bin setup.bin setup.elf bzImage
 targets         += fdimage fdimage144 fdimage288 image.iso mtools.conf
 subdir-         := compressed
 
-setup-y         += a20.o bioscall.o cmdline.o copy.o cpu.o cpucheck.o edd.o
-setup-y         += header.o main.o mca.o memory.o pm.o pmjump.o
-setup-y         += printf.o regs.o string.o tty.o video.o video-mode.o
-setup-y         += version.o
+setup-y         += a20.o bioscall.o cmdline.o copy.o cpu.o cpucheck.o
+setup-y         += early_serial_console.o edd.o header.o main.o mca.o memory.o
+setup-y         += pm.o pmjump.o printf.o regs.o string.o tty.o video.o
+setup-y         += video-mode.o version.o
 setup-$(CONFIG_X86_APM_BOOT) += apm.o
 
 # The link order of the video-*.o modules can matter.  In particular,
diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h
index 98239d2658f2..c7093bd9f2d3 100644
--- a/arch/x86/boot/boot.h
+++ b/arch/x86/boot/boot.h
@@ -28,6 +28,7 @@
 #include "bitops.h"
 #include <asm/cpufeature.h>
 #include <asm/processor-flags.h>
+#include "ctype.h"
 
 /* Useful macros */
 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
@@ -37,6 +38,8 @@
 extern struct setup_header hdr;
 extern struct boot_params boot_params;
 
+#define cpu_relax()     asm volatile("rep; nop")
+
 /* Basic port I/O */
 static inline void outb(u8 v, u16 port)
 {
@@ -198,11 +201,6 @@ static inline int memcmp_gs(const void *s1, addr_t s2, size_t len)
         return diff;
 }
 
-static inline int isdigit(int ch)
-{
-        return (ch >= '0') && (ch <= '9');
-}
-
 /* Heap -- available for dynamic lists. */
 extern char _end[];
 extern char *HEAP;
@@ -287,8 +285,18 @@ struct biosregs {
 void intcall(u8 int_no, const struct biosregs *ireg, struct biosregs *oreg);
 
 /* cmdline.c */
-int cmdline_find_option(const char *option, char *buffer, int bufsize);
-int cmdline_find_option_bool(const char *option);
+int __cmdline_find_option(u32 cmdline_ptr, const char *option, char *buffer, int bufsize);
+int __cmdline_find_option_bool(u32 cmdline_ptr, const char *option);
+static inline int cmdline_find_option(const char *option, char *buffer, int bufsize)
+{
+        return __cmdline_find_option(boot_params.hdr.cmd_line_ptr, option, buffer, bufsize);
+}
+
+static inline int cmdline_find_option_bool(const char *option)
+{
+        return __cmdline_find_option_bool(boot_params.hdr.cmd_line_ptr, option);
+}
+
 
 /* cpu.c, cpucheck.c */
 struct cpu_features {
@@ -300,6 +308,10 @@ extern struct cpu_features cpu;
 int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr);
 int validate_cpu(void);
 
+/* early_serial_console.c */
+extern int early_serial_base;
+void console_init(void);
+
 /* edd.c */
 void query_edd(void);
 
@@ -329,8 +341,10 @@ void initregs(struct biosregs *regs);
 
 /* string.c */
 int strcmp(const char *str1, const char *str2);
+int strncmp(const char *cs, const char *ct, size_t count);
 size_t strnlen(const char *s, size_t maxlen);
 unsigned int atou(const char *s);
+unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base);
 
 /* tty.c */
 void puts(const char *);
diff --git a/arch/x86/boot/cmdline.c b/arch/x86/boot/cmdline.c
index a1d35634bce0..6b3b6f708c04 100644
--- a/arch/x86/boot/cmdline.c
+++ b/arch/x86/boot/cmdline.c
@@ -27,9 +27,8 @@ static inline int myisspace(u8 c)
  * Returns the length of the argument (regardless of if it was
  * truncated to fit in the buffer), or -1 on not found.
  */
-int cmdline_find_option(const char *option, char *buffer, int bufsize)
+int __cmdline_find_option(u32 cmdline_ptr, const char *option, char *buffer, int bufsize)
 {
-        u32 cmdline_ptr = boot_params.hdr.cmd_line_ptr;
         addr_t cptr;
         char c;
         int len = -1;
@@ -100,9 +99,8 @@ int cmdline_find_option(const char *option, char *buffer, int bufsize)
  * Returns the position of that option (starts counting with 1)
  * or 0 on not found
  */
-int cmdline_find_option_bool(const char *option)
+int __cmdline_find_option_bool(u32 cmdline_ptr, const char *option)
 {
-        u32 cmdline_ptr = boot_params.hdr.cmd_line_ptr;
         addr_t cptr;
         char c;
         int pos = 0, wstart = 0;
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index fbb47daf2459..0c229551eead 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -4,7 +4,7 @@
 # create a compressed vmlinux image from the original vmlinux
 #
 
-targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo head_$(BITS).o misc.o piggy.o
+targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo head_$(BITS).o misc.o string.o cmdline.o early_serial_console.o piggy.o
 
 KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2
 KBUILD_CFLAGS += -fno-strict-aliasing -fPIC
@@ -23,7 +23,7 @@ LDFLAGS_vmlinux := -T
 
 hostprogs-y     := mkpiggy
 
-$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/piggy.o FORCE
+$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o $(obj)/piggy.o FORCE
         $(call if_changed,ld)
         @:
 
diff --git a/arch/x86/boot/compressed/cmdline.c b/arch/x86/boot/compressed/cmdline.c
new file mode 100644
index 000000000000..cb62f786990d
--- /dev/null
+++ b/arch/x86/boot/compressed/cmdline.c
@@ -0,0 +1,21 @@
+#include "misc.h"
+
+static unsigned long fs;
+static inline void set_fs(unsigned long seg)
+{
+        fs = seg << 4;  /* shift it back */
+}
+typedef unsigned long addr_t;
+static inline char rdfs8(addr_t addr)
+{
+        return *((char *)(fs + addr));
+}
+#include "../cmdline.c"
+int cmdline_find_option(const char *option, char *buffer, int bufsize)
+{
+        return __cmdline_find_option(real_mode->hdr.cmd_line_ptr, option, buffer, bufsize);
+}
+int cmdline_find_option_bool(const char *option)
+{
+        return __cmdline_find_option_bool(real_mode->hdr.cmd_line_ptr, option);
+}
diff --git a/arch/x86/boot/compressed/early_serial_console.c b/arch/x86/boot/compressed/early_serial_console.c
new file mode 100644
index 000000000000..261e81fb9582
--- /dev/null
+++ b/arch/x86/boot/compressed/early_serial_console.c
@@ -0,0 +1,5 @@
+#include "misc.h"
+
+int early_serial_base;
+
+#include "../early_serial_console.c"
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index f543b70ffae2..67a655a39ce4 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -124,6 +124,19 @@ relocated:
         rep     stosl
 
 /*
+ * Adjust our own GOT
+ */
+        leal    _got(%ebx), %edx
+        leal    _egot(%ebx), %ecx
+1:
+        cmpl    %ecx, %edx
+        jae     2f
+        addl    %ebx, (%edx)
+        addl    $4, %edx
+        jmp     1b
+2:
+
+/*
  * Do the decompression, and jump to the new kernel..
  */
         leal    z_extract_offset_negative(%ebx), %ebp
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index faff0dc9c06a..52f85a196fa0 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -280,6 +280,19 @@ relocated:
         rep     stosq
 
 /*
+ * Adjust our own GOT
+ */
+        leaq    _got(%rip), %rdx
+        leaq    _egot(%rip), %rcx
+1:
+        cmpq    %rcx, %rdx
+        jae     2f
+        addq    %rbx, (%rdx)
+        addq    $8, %rdx
+        jmp     1b
+2:
+        
+/*
  * Do the decompression, and jump to the new kernel..
  */
         pushq   %rsi                    /* Save the real mode argument */
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 51e240779a44..8f7bef8e9fff 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -9,23 +9,7 @@
  * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
  */
 
-/*
- * we have to be careful, because no indirections are allowed here, and
- * paravirt_ops is a kind of one. As it will only run in baremetal anyway,
- * we just keep it from happening
- */
-#undef CONFIG_PARAVIRT
-#ifdef CONFIG_X86_32
-#define _ASM_X86_DESC_H 1
-#endif
-
-#include <linux/linkage.h>
-#include <linux/screen_info.h>
-#include <linux/elf.h>
-#include <linux/io.h>
-#include <asm/page.h>
-#include <asm/boot.h>
-#include <asm/bootparam.h>
+#include "misc.h"
 
 /* WARNING!!
  * This code is compiled with -fPIC and it is relocated dynamically
@@ -123,15 +107,13 @@ static void error(char *m);
 /*
  * This is set up by the setup-routine at boot-time
  */
-static struct boot_params *real_mode;           /* Pointer to real-mode data */
+struct boot_params *real_mode;          /* Pointer to real-mode data */
 static int quiet;
+static int debug;
 
 void *memset(void *s, int c, size_t n);
 void *memcpy(void *dest, const void *src, size_t n);
 
-static void __putstr(int, const char *);
-#define putstr(__x)  __putstr(0, __x)
-
 #ifdef CONFIG_X86_64
 #define memptr long
 #else
@@ -170,7 +152,21 @@ static void scroll(void)
                 vidmem[i] = ' ';
 }
 
-static void __putstr(int error, const char *s)
+#define XMTRDY          0x20
+
+#define TXR             0       /*  Transmit register (WRITE) */
+#define LSR             5       /*  Line Status               */
+static void serial_putchar(int ch)
+{
+        unsigned timeout = 0xffff;
+
+        while ((inb(early_serial_base + LSR) & XMTRDY) == 0 && --timeout)
+                cpu_relax();
+
+        outb(ch, early_serial_base + TXR);
+}
+
+void __putstr(int error, const char *s)
 {
         int x, y, pos;
         char c;
@@ -179,6 +175,14 @@ static void __putstr(int error, const char *s)
         if (!error)
                 return;
 #endif
+        if (early_serial_base) {
+                const char *str = s;
+                while (*str) {
+                        if (*str == '\n')
+                                serial_putchar('\r');
+                        serial_putchar(*str++);
+                }
+        }
 
         if (real_mode->screen_info.orig_video_mode == 0 &&
             lines == 0 && cols == 0)
@@ -305,8 +309,10 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
 {
         real_mode = rmode;
 
-        if (real_mode->hdr.loadflags & QUIET_FLAG)
+        if (cmdline_find_option_bool("quiet"))
                 quiet = 1;
+        if (cmdline_find_option_bool("debug"))
+                debug = 1;
 
         if (real_mode->screen_info.orig_video_mode == 7) {
                 vidmem = (char *) 0xb0000;
@@ -319,6 +325,10 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
         lines = real_mode->screen_info.orig_video_lines;
         cols = real_mode->screen_info.orig_video_cols;
 
+        console_init();
+        if (debug)
+                putstr("early console in decompress_kernel\n");
+
         free_mem_ptr     = heap;        /* Heap */
         free_mem_end_ptr = heap + BOOT_HEAP_SIZE;
 
diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h
new file mode 100644
index 000000000000..3f19c81a6203
--- /dev/null
+++ b/arch/x86/boot/compressed/misc.h
@@ -0,0 +1,39 @@
+#ifndef BOOT_COMPRESSED_MISC_H
+#define BOOT_COMPRESSED_MISC_H
+
+/*
+ * we have to be careful, because no indirections are allowed here, and
+ * paravirt_ops is a kind of one. As it will only run in baremetal anyway,
+ * we just keep it from happening
+ */
+#undef CONFIG_PARAVIRT
+#ifdef CONFIG_X86_32
+#define _ASM_X86_DESC_H 1
+#endif
+
+#include <linux/linkage.h>
+#include <linux/screen_info.h>
+#include <linux/elf.h>
+#include <linux/io.h>
+#include <asm/page.h>
+#include <asm/boot.h>
+#include <asm/bootparam.h>
+
+#define BOOT_BOOT_H
+#include "../ctype.h"
+
+/* misc.c */
+extern struct boot_params *real_mode;           /* Pointer to real-mode data */
+void __putstr(int error, const char *s);
+#define putstr(__x)  __putstr(0, __x)
+#define puts(__x)  __putstr(0, __x)
+
+/* cmdline.c */
+int cmdline_find_option(const char *option, char *buffer, int bufsize);
+int cmdline_find_option_bool(const char *option);
+
+/* early_serial_console.c */
+extern int early_serial_base;
+void console_init(void);
+
+#endif
diff --git a/arch/x86/boot/compressed/string.c b/arch/x86/boot/compressed/string.c
new file mode 100644
index 000000000000..19b3e693cd72
--- /dev/null
+++ b/arch/x86/boot/compressed/string.c
@@ -0,0 +1,2 @@
+#include "misc.h"
+#include "../string.c"
diff --git a/arch/x86/boot/compressed/vmlinux.lds.S b/arch/x86/boot/compressed/vmlinux.lds.S
index 5ddabceee124..34d047c98284 100644
--- a/arch/x86/boot/compressed/vmlinux.lds.S
+++ b/arch/x86/boot/compressed/vmlinux.lds.S
@@ -41,6 +41,12 @@ SECTIONS
                 *(.rodata.*)
                 _erodata = . ;
         }
+        .got : {
+                _got = .;
+                KEEP(*(.got.plt))
+                KEEP(*(.got))
+                _egot = .;
+        }
         .data : {
                 _data = . ;
                 *(.data)
diff --git a/arch/x86/boot/ctype.h b/arch/x86/boot/ctype.h
new file mode 100644
index 000000000000..25e13403193c
--- /dev/null
+++ b/arch/x86/boot/ctype.h
@@ -0,0 +1,21 @@
+#ifndef BOOT_ISDIGIT_H
+
+#define BOOT_ISDIGIT_H
+
+static inline int isdigit(int ch)
+{
+        return (ch >= '0') && (ch <= '9');
+}
+
+static inline int isxdigit(int ch)
+{
+        if (isdigit(ch))
+                return true;
+
+        if ((ch >= 'a') && (ch <= 'f'))
+                return true;
+
+        return (ch >= 'A') && (ch <= 'F');
+}
+
+#endif
diff --git a/arch/x86/boot/early_serial_console.c b/arch/x86/boot/early_serial_console.c
new file mode 100644
index 000000000000..030f4b93e255
--- /dev/null
+++ b/arch/x86/boot/early_serial_console.c
@@ -0,0 +1,139 @@
+#include "boot.h"
+
+#define DEFAULT_SERIAL_PORT 0x3f8 /* ttyS0 */
+
+#define XMTRDY          0x20
+
+#define DLAB            0x80
+
+#define TXR             0       /*  Transmit register (WRITE) */
+#define RXR             0       /*  Receive register  (READ)  */
+#define IER             1       /*  Interrupt Enable          */
+#define IIR             2       /*  Interrupt ID              */
+#define FCR             2       /*  FIFO control              */
+#define LCR             3       /*  Line control              */
+#define MCR             4       /*  Modem control             */
+#define LSR             5       /*  Line Status               */
+#define MSR             6       /*  Modem Status              */
+#define DLL             0       /*  Divisor Latch Low         */
+#define DLH             1       /*  Divisor latch High        */
+
+#define DEFAULT_BAUD 9600
+
+static void early_serial_init(int port, int baud)
+{
+        unsigned char c;
+        unsigned divisor;
+
+        outb(0x3, port + LCR);  /* 8n1 */
+        outb(0, port + IER);    /* no interrupt */
+        outb(0, port + FCR);    /* no fifo */
+        outb(0x3, port + MCR);  /* DTR + RTS */
+
+        divisor = 115200 / baud;
+        c = inb(port + LCR);
+        outb(c | DLAB, port + LCR);
+        outb(divisor & 0xff, port + DLL);
+        outb((divisor >> 8) & 0xff, port + DLH);
+        outb(c & ~DLAB, port + LCR);
+
+        early_serial_base = port;
+}
+
+static void parse_earlyprintk(void)
+{
+        int baud = DEFAULT_BAUD;
+        char arg[32];
+        int pos = 0;
+        int port = 0;
+
+        if (cmdline_find_option("earlyprintk", arg, sizeof arg) > 0) {
+                char *e;
+
+                if (!strncmp(arg, "serial", 6)) {
+                        port = DEFAULT_SERIAL_PORT;
+                        pos += 6;
+                }
+
+                if (arg[pos] == ',')
+                        pos++;
+
+                if (!strncmp(arg, "ttyS", 4)) {
+                        static const int bases[] = { 0x3f8, 0x2f8 };
+                        int idx = 0;
+
+                        if (!strncmp(arg + pos, "ttyS", 4))
+                                pos += 4;
+
+                        if (arg[pos++] == '1')
+                                idx = 1;
+
+                        port = bases[idx];
+                }
+
+                if (arg[pos] == ',')
+                        pos++;
+
+                baud = simple_strtoull(arg + pos, &e, 0);
+                if (baud == 0 || arg + pos == e)
+                        baud = DEFAULT_BAUD;
+        }
+
+        if (port)
+                early_serial_init(port, baud);
+}
+
+#define BASE_BAUD (1843200/16)
+static unsigned int probe_baud(int port)
+{
+        unsigned char lcr, dll, dlh;
+        unsigned int quot;
+
+        lcr = inb(port + LCR);
+        outb(lcr | DLAB, port + LCR);
+        dll = inb(port + DLL);
+        dlh = inb(port + DLH);
+        outb(lcr, port + LCR);
+        quot = (dlh << 8) | dll;
+
+        return BASE_BAUD / quot;
+}
+
+static void parse_console_uart8250(void)
+{
+        char optstr[64], *options;
+        int baud = DEFAULT_BAUD;
+        int port = 0;
+
+        /*
+         * console=uart8250,io,0x3f8,115200n8
+         * need to make sure it is last one console !
+         */
+        if (cmdline_find_option("console", optstr, sizeof optstr) <= 0)
+                return;
+
+        options = optstr;
+
+        if (!strncmp(options, "uart8250,io,", 12))
+                port = simple_strtoull(options + 12, &options, 0);
+        else if (!strncmp(options, "uart,io,", 8))
+                port = simple_strtoull(options + 8, &options, 0);
+        else
+                return;
+
+        if (options && (options[0] == ','))
+                baud = simple_strtoull(options + 1, &options, 0);
+        else
+                baud = probe_baud(port);
+
+        if (port)
+                early_serial_init(port, baud);
+}
+
+void console_init(void)
+{
+        parse_earlyprintk();
+
+        if (!early_serial_base)
+                parse_console_uart8250();
+}
diff --git a/arch/x86/boot/main.c b/arch/x86/boot/main.c
index 140172b895bd..40358c8905be 100644
--- a/arch/x86/boot/main.c
+++ b/arch/x86/boot/main.c
@@ -130,6 +130,11 @@ void main(void)
         /* First, copy the boot header into the "zeropage" */
         copy_boot_params();
 
+        /* Initialize the early-boot console */
+        console_init();
+        if (cmdline_find_option_bool("debug"))
+                puts("early console in setup code\n");
+
         /* End of heap check */
         init_heap();
 
@@ -168,10 +173,6 @@ void main(void)
         /* Set the video mode */
         set_video();
 
-        /* Parse command line for 'quiet' and pass it to decompressor. */
-        if (cmdline_find_option_bool("quiet"))
-                boot_params.hdr.loadflags |= QUIET_FLAG;
-
         /* Do the last things and invoke protected mode */
         go_to_protected_mode();
 }
diff --git a/arch/x86/boot/printf.c b/arch/x86/boot/printf.c
index 50e47cdbdddd..cdac91ca55d3 100644
--- a/arch/x86/boot/printf.c
+++ b/arch/x86/boot/printf.c
@@ -34,7 +34,7 @@ static int skip_atoi(const char **s)
 #define SMALL   32              /* Must be 32 == 0x20 */
 #define SPECIAL 64              /* 0x */
 
-#define do_div(n,base) ({ \
+#define __do_div(n, base) ({ \
 int __res; \
 __res = ((unsigned long) n) % (unsigned) base; \
 n = ((unsigned long) n) / (unsigned) base; \
@@ -83,7 +83,7 @@ static char *number(char *str, long num, int base, int size, int precision,
                 tmp[i++] = '0';
         else
                 while (num != 0)
-                        tmp[i++] = (digits[do_div(num, base)] | locase);
+                        tmp[i++] = (digits[__do_div(num, base)] | locase);
         if (i > precision)
                 precision = i;
         size -= precision;
diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c
index f94b7a0c2abf..3cbc4058dd26 100644
--- a/arch/x86/boot/string.c
+++ b/arch/x86/boot/string.c
@@ -30,6 +30,22 @@ int strcmp(const char *str1, const char *str2)
         return 0;
 }
 
+int strncmp(const char *cs, const char *ct, size_t count)
+{
+        unsigned char c1, c2;
+
+        while (count) {
+                c1 = *cs++;
+                c2 = *ct++;
+                if (c1 != c2)
+                        return c1 < c2 ? -1 : 1;
+                if (!c1)
+                        break;
+                count--;
+        }
+        return 0;
+}
+
 size_t strnlen(const char *s, size_t maxlen)
 {
         const char *es = s;
@@ -48,3 +64,50 @@ unsigned int atou(const char *s)
                 i = i * 10 + (*s++ - '0');
         return i;
 }
+
+/* Works only for digits and letters, but small and fast */
+#define TOLOWER(x) ((x) | 0x20)
+
+static unsigned int simple_guess_base(const char *cp)
+{
+        if (cp[0] == '0') {
+                if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2]))
+                        return 16;
+                else
+                        return 8;
+        } else {
+                return 10;
+        }
+}
+
+/**
+ * simple_strtoull - convert a string to an unsigned long long
+ * @cp: The start of the string
+ * @endp: A pointer to the end of the parsed string will be placed here
+ * @base: The number base to use
+ */
+
+unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base)
+{
+        unsigned long long result = 0;
+
+        if (!base)
+                base = simple_guess_base(cp);
+
+        if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
+                cp += 2;
+
+        while (isxdigit(*cp)) {
+                unsigned int value;
+
+                value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10;
+                if (value >= base)
+                        break;
+                result = result * base + value;
+                cp++;
+        }
+        if (endp)
+                *endp = (char *)cp;
+
+        return result;
+}
diff --git a/arch/x86/boot/tty.c b/arch/x86/boot/tty.c
index 01ec69c901c7..def2451f46ae 100644
--- a/arch/x86/boot/tty.c
+++ b/arch/x86/boot/tty.c
@@ -10,23 +10,36 @@
  * ----------------------------------------------------------------------- */
 
 /*
- * Very simple screen I/O
- * XXX: Probably should add very simple serial I/O?
+ * Very simple screen and serial I/O
  */
 
 #include "boot.h"
 
+int early_serial_base;
+
+#define XMTRDY          0x20
+
+#define TXR             0       /*  Transmit register (WRITE) */
+#define LSR             5       /*  Line Status               */
+
 /*
  * These functions are in .inittext so they can be used to signal
  * error during initialization.
  */
 
-void __attribute__((section(".inittext"))) putchar(int ch)
+static void __attribute__((section(".inittext"))) serial_putchar(int ch)
 {
-        struct biosregs ireg;
+        unsigned timeout = 0xffff;
 
-        if (ch == '\n')
-                putchar('\r');  /* \n -> \r\n */
+        while ((inb(early_serial_base + LSR) & XMTRDY) == 0 && --timeout)
+                cpu_relax();
+
+        outb(ch, early_serial_base + TXR);
+}
+
+static void __attribute__((section(".inittext"))) bios_putchar(int ch)
+{
+        struct biosregs ireg;
 
         initregs(&ireg);
         ireg.bx = 0x0007;
@@ -36,6 +49,17 @@ void __attribute__((section(".inittext"))) putchar(int ch)
         intcall(0x10, &ireg, NULL);
 }
 
+void __attribute__((section(".inittext"))) putchar(int ch)
+{
+        if (ch == '\n')
+                putchar('\r');  /* \n -> \r\n */
+
+        bios_putchar(ch);
+
+        if (early_serial_base != 0)
+                serial_putchar(ch);
+}
+
 void __attribute__((section(".inittext"))) puts(const char *str)
 {
         while (*str)
@@ -112,3 +136,4 @@ int getchar_timeout(void)
 
         return 0;               /* Timeout! */
 }
+
diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig
index d28fad19654a..e3a32431ca1e 100644
--- a/arch/x86/configs/i386_defconfig
+++ b/arch/x86/configs/i386_defconfig
@@ -1471,6 +1471,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_CORETEMP is not set
+# CONFIG_SENSORS_PKGTEMP is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM63 is not set
 # CONFIG_SENSORS_LM75 is not set
diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig
index 6c86acd847a4..4251f8372050 100644
--- a/arch/x86/configs/x86_64_defconfig
+++ b/arch/x86/configs/x86_64_defconfig
@@ -1456,6 +1456,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_CORETEMP is not set
+# CONFIG_SENSORS_PKGTEMP is not set
 # CONFIG_SENSORS_IT87 is not set
 # CONFIG_SENSORS_LM63 is not set
 # CONFIG_SENSORS_LM75 is not set
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index aa2c39d968fc..92091de11113 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -134,7 +134,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
             boot_cpu_data.x86_model <= 0x05 &&
             boot_cpu_data.x86_mask < 0x0A)
                 return 1;
-        else if (boot_cpu_has(X86_FEATURE_AMDC1E))
+        else if (c1e_detected)
                 return 1;
         else
                 return max_cstate;
diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index c74a2eebe570..a69b1ac9eaf8 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -55,7 +55,6 @@ extern unsigned long apbt_quick_calibrate(void);
 extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
 extern void apbt_setup_secondary_clock(void);
 extern unsigned int boot_cpu_id;
-extern int disable_apbt_percpu;
 
 extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
 extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index 8859e12dd3cf..284a6e8f7ce1 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -11,38 +11,42 @@
 extern void __xchg_wrong_size(void);
 
 /*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *        but generally the primitive is invalid, *ptr is output argument. --ANK
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway.
+ * Since this is generally used to protect other memory information, we
+ * use "asm volatile" and "memory" clobbers to prevent gcc from moving
+ * information around.
  */
-
-struct __xchg_dummy {
-        unsigned long a[100];
-};
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
 #define __xchg(x, ptr, size)                                            \
 ({                                                                      \
         __typeof(*(ptr)) __x = (x);                                     \
         switch (size) {                                                 \
         case 1:                                                         \
-                asm volatile("xchgb %b0,%1"                             \
-                             : "=q" (__x)                               \
-                             : "m" (*__xg(ptr)), "0" (__x)              \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile("xchgb %0,%1"                              \
+                             : "=q" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 2:                                                         \
-                asm volatile("xchgw %w0,%1"                             \
-                             : "=r" (__x)                               \
-                             : "m" (*__xg(ptr)), "0" (__x)              \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile("xchgw %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 4:                                                         \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
                 asm volatile("xchgl %0,%1"                              \
-                             : "=r" (__x)                               \
-                             : "m" (*__xg(ptr)), "0" (__x)              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         default:                                                        \
                 __xchg_wrong_size();                                    \
         }                                                               \
@@ -53,60 +57,33 @@ struct __xchg_dummy {
         __xchg((v), (ptr), sizeof(*ptr))
 
 /*
- * The semantics of XCHGCMP8B are a bit strange, this is why
- * there is a loop and the loading of %%eax and %%edx has to
- * be inside. This inlines well in most cases, the cached
- * cost is around ~38 cycles. (in the future we might want
- * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
- * might have an implicit FPU-save as a cost, so it's not
- * clear which path to go.)
+ * CMPXCHG8B only writes to the target if we had the previous
+ * value in registers, otherwise it acts as a read and gives us the
+ * "new previous" value.  That is why there is a loop.  Preloading
+ * EDX:EAX is a performance optimization: in the common case it means
+ * we need only one locked operation.
  *
- * cmpxchg8b must be used with the lock prefix here to allow
- * the instruction to be executed atomically, see page 3-102
- * of the instruction set reference 24319102.pdf. We need
- * the reader side to see the coherent 64bit value.
+ * A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very
+ * least an FPU save and/or %cr0.ts manipulation.
+ *
+ * cmpxchg8b must be used with the lock prefix here to allow the
+ * instruction to be executed atomically.  We need to have the reader
+ * side to see the coherent 64bit value.
  */
-static inline void __set_64bit(unsigned long long *ptr,
-                               unsigned int low, unsigned int high)
+static inline void set_64bit(volatile u64 *ptr, u64 value)
 {
+        u32 low  = value;
+        u32 high = value >> 32;
+        u64 prev = *ptr;
+
         asm volatile("\n1:\t"
-                     "movl (%0), %%eax\n\t"
-                     "movl 4(%0), %%edx\n\t"
-                     LOCK_PREFIX "cmpxchg8b (%0)\n\t"
+                     LOCK_PREFIX "cmpxchg8b %0\n\t"
                      "jnz 1b"
-                     : /* no outputs */
-                     : "D"(ptr),
-                       "b"(low),
-                       "c"(high)
-                     : "ax", "dx", "memory");
-}
-
-static inline void __set_64bit_constant(unsigned long long *ptr,
-                                        unsigned long long value)
-{
-        __set_64bit(ptr, (unsigned int)value, (unsigned int)(value >> 32));
-}
-
-#define ll_low(x)       *(((unsigned int *)&(x)) + 0)
-#define ll_high(x)      *(((unsigned int *)&(x)) + 1)
-
-static inline void __set_64bit_var(unsigned long long *ptr,
-                                   unsigned long long value)
-{
-        __set_64bit(ptr, ll_low(value), ll_high(value));
+                     : "=m" (*ptr), "+A" (prev)
+                     : "b" (low), "c" (high)
+                     : "memory");
 }
 
-#define set_64bit(ptr, value)                   \
-        (__builtin_constant_p((value))          \
-         ? __set_64bit_constant((ptr), (value)) \
-         : __set_64bit_var((ptr), (value)))
-
-#define _set_64bit(ptr, value)                                          \
-        (__builtin_constant_p(value)                                    \
-         ? __set_64bit(ptr, (unsigned int)(value),                      \
-                       (unsigned int)((value) >> 32))                   \
-         : __set_64bit(ptr, ll_low((value)), ll_high((value))))
-
 extern void __cmpxchg_wrong_size(void);
 
 /*
@@ -121,23 +98,32 @@ extern void __cmpxchg_wrong_size(void);
         __typeof__(*(ptr)) __new = (new);                               \
         switch (size) {                                                 \
         case 1:                                                         \
-                asm volatile(lock "cmpxchgb %b1,%2"                     \
-                             : "=a"(__ret)                              \
-                             : "q"(__new), "m"(*__xg(ptr)), "0"(__old)  \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile(lock "cmpxchgb %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "q" (__new), "0" (__old)                 \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 2:                                                         \
-                asm volatile(lock "cmpxchgw %w1,%2"                     \
-                             : "=a"(__ret)                              \
-                             : "r"(__new), "m"(*__xg(ptr)), "0"(__old)  \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile(lock "cmpxchgw %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 4:                                                         \
-                asm volatile(lock "cmpxchgl %1,%2"                      \
-                             : "=a"(__ret)                              \
-                             : "r"(__new), "m"(*__xg(ptr)), "0"(__old)  \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
+                asm volatile(lock "cmpxchgl %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         default:                                                        \
                 __cmpxchg_wrong_size();                                 \
         }                                                               \
@@ -175,32 +161,28 @@ extern void __cmpxchg_wrong_size(void);
                                                (unsigned long long)(n)))
 #endif
 
-static inline unsigned long long __cmpxchg64(volatile void *ptr,
-                                             unsigned long long old,
-                                             unsigned long long new)
+static inline u64 __cmpxchg64(volatile u64 *ptr, u64 old, u64 new)
 {
-        unsigned long long prev;
-        asm volatile(LOCK_PREFIX "cmpxchg8b %3"
-                     : "=A"(prev)
-                     : "b"((unsigned long)new),
-                       "c"((unsigned long)(new >> 32)),
-                       "m"(*__xg(ptr)),
-                       "0"(old)
+        u64 prev;
+        asm volatile(LOCK_PREFIX "cmpxchg8b %1"
+                     : "=A" (prev),
+                       "+m" (*ptr)
+                     : "b" ((u32)new),
+                       "c" ((u32)(new >> 32)),
+                       "0" (old)
                      : "memory");
         return prev;
 }
 
-static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
-                                                   unsigned long long old,
-                                                   unsigned long long new)
+static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
 {
-        unsigned long long prev;
-        asm volatile("cmpxchg8b %3"
-                     : "=A"(prev)
-                     : "b"((unsigned long)new),
-                       "c"((unsigned long)(new >> 32)),
-                       "m"(*__xg(ptr)),
-                       "0"(old)
+        u64 prev;
+        asm volatile("cmpxchg8b %1"
+                     : "=A" (prev),
+                       "+m" (*ptr)
+                     : "b" ((u32)new),
+                       "c" ((u32)(new >> 32)),
+                       "0" (old)
                      : "memory");
         return prev;
 }
@@ -264,8 +246,6 @@ static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
  * to simulate the cmpxchg8b on the 80386 and 80486 CPU.
  */
 
-extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64);
-
 #define cmpxchg64(ptr, o, n)                                    \
 ({                                                              \
         __typeof__(*(ptr)) __ret;                               \
@@ -283,20 +263,20 @@ extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64);
         __ret; })
 
 
-
-#define cmpxchg64_local(ptr, o, n)                                      \
-({                                                                      \
-        __typeof__(*(ptr)) __ret;                                       \
-        if (likely(boot_cpu_data.x86 > 4))                              \
-                __ret = (__typeof__(*(ptr)))__cmpxchg64_local((ptr),    \
-                                (unsigned long long)(o),                \
-                                (unsigned long long)(n));               \
-        else                                                            \
-                __ret = (__typeof__(*(ptr)))cmpxchg_486_u64((ptr),      \
-                                (unsigned long long)(o),                \
-                                (unsigned long long)(n));               \
-        __ret;                                                          \
-})
+#define cmpxchg64_local(ptr, o, n)                              \
+({                                                              \
+        __typeof__(*(ptr)) __ret;                               \
+        __typeof__(*(ptr)) __old = (o);                         \
+        __typeof__(*(ptr)) __new = (n);                         \
+        alternative_io("call cmpxchg8b_emu",                    \
+                       "cmpxchg8b (%%esi)" ,                    \
+                       X86_FEATURE_CX8,                         \
+                       "=A" (__ret),                            \
+                       "S" ((ptr)), "0" (__old),                \
+                       "b" ((unsigned int)__new),               \
+                       "c" ((unsigned int)(__new>>32))          \
+                       : "memory");                             \
+        __ret; })
 
 #endif
 
diff --git a/arch/x86/include/asm/cmpxchg_64.h b/arch/x86/include/asm/cmpxchg_64.h
index 485ae415faec..423ae58aa020 100644
--- a/arch/x86/include/asm/cmpxchg_64.h
+++ b/arch/x86/include/asm/cmpxchg_64.h
@@ -3,51 +3,60 @@
 
 #include <asm/alternative.h> /* Provides LOCK_PREFIX */
 
-#define __xg(x) ((volatile long *)(x))
-
-static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
+static inline void set_64bit(volatile u64 *ptr, u64 val)
 {
         *ptr = val;
 }
 
-#define _set_64bit set_64bit
-
 extern void __xchg_wrong_size(void);
 extern void __cmpxchg_wrong_size(void);
 
 /*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *        but generally the primitive is invalid, *ptr is output argument. --ANK
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway.
+ * Since this is generally used to protect other memory information, we
+ * use "asm volatile" and "memory" clobbers to prevent gcc from moving
+ * information around.
  */
 #define __xchg(x, ptr, size)                                            \
 ({                                                                      \
         __typeof(*(ptr)) __x = (x);                                     \
         switch (size) {                                                 \
         case 1:                                                         \
-                asm volatile("xchgb %b0,%1"                             \
-                             : "=q" (__x)                               \
-                             : "m" (*__xg(ptr)), "0" (__x)              \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile("xchgb %0,%1"                              \
+                             : "=q" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 2:                                                         \
-                asm volatile("xchgw %w0,%1"                             \
-                             : "=r" (__x)                               \
-                             : "m" (*__xg(ptr)), "0" (__x)              \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile("xchgw %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 4:                                                         \
-                asm volatile("xchgl %k0,%1"                             \
-                             : "=r" (__x)                               \
-                             : "m" (*__xg(ptr)), "0" (__x)              \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
+                asm volatile("xchgl %0,%1"                              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 8:                                                         \
+        {                                                               \
+                volatile u64 *__ptr = (volatile u64 *)(ptr);            \
                 asm volatile("xchgq %0,%1"                              \
-                             : "=r" (__x)                               \
-                             : "m" (*__xg(ptr)), "0" (__x)              \
+                             : "=r" (__x), "+m" (*__ptr)                \
+                             : "0" (__x)                                \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         default:                                                        \
                 __xchg_wrong_size();                                    \
         }                                                               \
@@ -71,29 +80,41 @@ extern void __cmpxchg_wrong_size(void);
         __typeof__(*(ptr)) __new = (new);                               \
         switch (size) {                                                 \
         case 1:                                                         \
-                asm volatile(lock "cmpxchgb %b1,%2"                     \
-                             : "=a"(__ret)                              \
-                             : "q"(__new), "m"(*__xg(ptr)), "0"(__old)  \
+        {                                                               \
+                volatile u8 *__ptr = (volatile u8 *)(ptr);              \
+                asm volatile(lock "cmpxchgb %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "q" (__new), "0" (__old)                 \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 2:                                                         \
-                asm volatile(lock "cmpxchgw %w1,%2"                     \
-                             : "=a"(__ret)                              \
-                             : "r"(__new), "m"(*__xg(ptr)), "0"(__old)  \
+        {                                                               \
+                volatile u16 *__ptr = (volatile u16 *)(ptr);            \
+                asm volatile(lock "cmpxchgw %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 4:                                                         \
-                asm volatile(lock "cmpxchgl %k1,%2"                     \
-                             : "=a"(__ret)                              \
-                             : "r"(__new), "m"(*__xg(ptr)), "0"(__old)  \
+        {                                                               \
+                volatile u32 *__ptr = (volatile u32 *)(ptr);            \
+                asm volatile(lock "cmpxchgl %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         case 8:                                                         \
-                asm volatile(lock "cmpxchgq %1,%2"                      \
-                             : "=a"(__ret)                              \
-                             : "r"(__new), "m"(*__xg(ptr)), "0"(__old)  \
+        {                                                               \
+                volatile u64 *__ptr = (volatile u64 *)(ptr);            \
+                asm volatile(lock "cmpxchgq %2,%1"                      \
+                             : "=a" (__ret), "+m" (*__ptr)              \
+                             : "r" (__new), "0" (__old)                 \
                              : "memory");                               \
                 break;                                                  \
+        }                                                               \
         default:                                                        \
                 __cmpxchg_wrong_size();                                 \
         }                                                               \
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 468145914389..0b205b8a4308 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -6,7 +6,7 @@
 
 #include <asm/required-features.h>
 
-#define NCAPINTS        9       /* N 32-bit words worth of info */
+#define NCAPINTS        10      /* N 32-bit words worth of info */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -89,7 +89,7 @@
 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
 #define X86_FEATURE_11AP        (3*32+19) /* "" Bad local APIC aka 11AP */
 #define X86_FEATURE_NOPL        (3*32+20) /* The NOPL (0F 1F) instructions */
-#define X86_FEATURE_AMDC1E      (3*32+21) /* AMD C1E detected */
+                                          /* 21 available, was AMD_C1E */
 #define X86_FEATURE_XTOPOLOGY   (3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
@@ -124,6 +124,8 @@
 #define X86_FEATURE_XSAVE       (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
 #define X86_FEATURE_OSXSAVE     (4*32+27) /* "" XSAVE enabled in the OS */
 #define X86_FEATURE_AVX         (4*32+28) /* Advanced Vector Extensions */
+#define X86_FEATURE_F16C        (4*32+29) /* 16-bit fp conversions */
+#define X86_FEATURE_RDRND       (4*32+30) /* The RDRAND instruction */
 #define X86_FEATURE_HYPERVISOR  (4*32+31) /* Running on a hypervisor */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
@@ -157,22 +159,29 @@
 
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
- * CPUID levels like 0x6, 0xA etc
+ * CPUID levels like 0x6, 0xA etc, word 7
  */
 #define X86_FEATURE_IDA         (7*32+ 0) /* Intel Dynamic Acceleration */
 #define X86_FEATURE_ARAT        (7*32+ 1) /* Always Running APIC Timer */
 #define X86_FEATURE_CPB         (7*32+ 2) /* AMD Core Performance Boost */
+#define X86_FEATURE_EPB         (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
+#define X86_FEATURE_XSAVEOPT    (7*32+ 4) /* Optimized Xsave */
+#define X86_FEATURE_PLN         (7*32+ 5) /* Intel Power Limit Notification */
+#define X86_FEATURE_PTS         (7*32+ 6) /* Intel Package Thermal Status */
 
-/* Virtualization flags: Linux defined */
+/* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
 #define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
 #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
-#define X86_FEATURE_NPT         (8*32+5)  /* AMD Nested Page Table support */
-#define X86_FEATURE_LBRV        (8*32+6)  /* AMD LBR Virtualization support */
-#define X86_FEATURE_SVML        (8*32+7)  /* "svm_lock" AMD SVM locking MSR */
-#define X86_FEATURE_NRIPS       (8*32+8)  /* "nrip_save" AMD SVM next_rip save */
+#define X86_FEATURE_NPT         (8*32+ 5) /* AMD Nested Page Table support */
+#define X86_FEATURE_LBRV        (8*32+ 6) /* AMD LBR Virtualization support */
+#define X86_FEATURE_SVML        (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
+#define X86_FEATURE_NRIPS       (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
+
+/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
+#define X86_FEATURE_FSGSBASE    (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
@@ -194,7 +203,9 @@ extern const char * const x86_power_flags[32];
            (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||     \
            (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||     \
            (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||     \
-           (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) )      \
+           (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||     \
+           (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||     \
+           (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )      \
           ? 1 :                                                         \
          test_cpu_cap(c, bit))
 
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index 942255310e6a..528a11e8d3e3 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h
@@ -20,10 +20,10 @@ struct arch_hw_breakpoint {
 #include <linux/list.h>
 
 /* Available HW breakpoint length encodings */
+#define X86_BREAKPOINT_LEN_X            0x00
 #define X86_BREAKPOINT_LEN_1            0x40
 #define X86_BREAKPOINT_LEN_2            0x44
 #define X86_BREAKPOINT_LEN_4            0x4c
-#define X86_BREAKPOINT_LEN_EXECUTE      0x40
 
 #ifdef CONFIG_X86_64
 #define X86_BREAKPOINT_LEN_8            0x48
diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h
index 70abda7058c8..ff2546ce7178 100644
--- a/arch/x86/include/asm/hypervisor.h
+++ b/arch/x86/include/asm/hypervisor.h
@@ -45,5 +45,6 @@ extern const struct hypervisor_x86 *x86_hyper;
 /* Recognized hypervisors */
 extern const struct hypervisor_x86 x86_hyper_vmware;
 extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
+extern const struct hypervisor_x86 x86_hyper_xen_hvm;
 
 #endif
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index c991b3a7b904..815c5b2b9f57 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -482,6 +482,8 @@ static inline void fpu_copy(struct fpu *dst, struct fpu *src)
         memcpy(dst->state, src->state, xstate_size);
 }
 
+extern void fpu_finit(struct fpu *fpu);
+
 #endif /* __ASSEMBLY__ */
 
 #define PSHUFB_XMM5_XMM0 .byte 0x66, 0x0f, 0x38, 0x00, 0xc5
diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h
index 4470c9ad4a3e..29f66793cc55 100644
--- a/arch/x86/include/asm/intel_scu_ipc.h
+++ b/arch/x86/include/asm/intel_scu_ipc.h
@@ -1,6 +1,12 @@
 #ifndef _ASM_X86_INTEL_SCU_IPC_H_
 #define  _ASM_X86_INTEL_SCU_IPC_H_
 
+#define IPCMSG_VRTC     0xFA     /* Set vRTC device */
+
+/* Command id associated with message IPCMSG_VRTC */
+#define IPC_CMD_VRTC_SETTIME      1 /* Set time */
+#define IPC_CMD_VRTC_SETALARM     2 /* Set alarm */
+
 /* Read single register */
 int intel_scu_ipc_ioread8(u16 addr, u8 *data);
 
@@ -28,20 +34,6 @@ int intel_scu_ipc_writev(u16 *addr, u8 *data, int len);
 /* Update single register based on the mask */
 int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask);
 
-/*
- * Indirect register read
- * Can be used when SCCB(System Controller Configuration Block) register
- * HRIM(Honor Restricted IPC Messages) is set (bit 23)
- */
-int intel_scu_ipc_register_read(u32 addr, u32 *data);
-
-/*
- * Indirect register write
- * Can be used when SCCB(System Controller Configuration Block) register
- * HRIM(Honor Restricted IPC Messages) is set (bit 23)
- */
-int intel_scu_ipc_register_write(u32 addr, u32 data);
-
 /* Issue commands to the SCU with or without data */
 int intel_scu_ipc_simple_command(int cmd, int sub);
 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 8767d99c4f64..e2ca30092557 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -125,6 +125,9 @@
  */
 #define MCE_SELF_VECTOR                 0xeb
 
+/* Xen vector callback to receive events in a HVM domain */
+#define XEN_HVM_EVTCHN_CALLBACK         0xe9
+
 #define NR_VECTORS                       256
 
 #define FPU_IRQ                           13
diff --git a/arch/x86/include/asm/kgdb.h b/arch/x86/include/asm/kgdb.h
index 006da3687cdc..396f5b5fc4d7 100644
--- a/arch/x86/include/asm/kgdb.h
+++ b/arch/x86/include/asm/kgdb.h
@@ -39,9 +39,11 @@ enum regnames {
         GDB_FS,                 /* 14 */
         GDB_GS,                 /* 15 */
 };
+#define GDB_ORIG_AX             41
+#define DBG_MAX_REG_NUM         16
 #define NUMREGBYTES             ((GDB_GS+1)*4)
 #else /* ! CONFIG_X86_32 */
-enum regnames64 {
+enum regnames {
         GDB_AX,                 /* 0 */
         GDB_BX,                 /* 1 */
         GDB_CX,                 /* 2 */
@@ -59,15 +61,15 @@ enum regnames64 {
         GDB_R14,                /* 14 */
         GDB_R15,                /* 15 */
         GDB_PC,                 /* 16 */
+        GDB_PS,                 /* 17 */
+        GDB_CS,                 /* 18 */
+        GDB_SS,                 /* 19 */
 };
-
-enum regnames32 {
-        GDB_PS = 34,
-        GDB_CS,
-        GDB_SS,
-};
-#define NUMREGBYTES             ((GDB_SS+1)*4)
-#endif /* CONFIG_X86_32 */
+#define GDB_ORIG_AX             57
+#define DBG_MAX_REG_NUM         20
+/* 17 64 bit regs and 3 32 bit regs */
+#define NUMREGBYTES             ((17 * 8) + (3 * 4))
+#endif /* ! CONFIG_X86_32 */
 
 static inline void arch_kgdb_breakpoint(void)
 {
diff --git a/arch/x86/include/asm/kvm.h b/arch/x86/include/asm/kvm.h
index ff90055c7f0b..4d8dcbdfc120 100644
--- a/arch/x86/include/asm/kvm.h
+++ b/arch/x86/include/asm/kvm.h
@@ -22,6 +22,8 @@
 #define __KVM_HAVE_XEN_HVM
 #define __KVM_HAVE_VCPU_EVENTS
 #define __KVM_HAVE_DEBUGREGS
+#define __KVM_HAVE_XSAVE
+#define __KVM_HAVE_XCRS
 
 /* Architectural interrupt line count. */
 #define KVM_NR_INTERRUPTS 256
@@ -299,4 +301,24 @@ struct kvm_debugregs {
         __u64 reserved[9];
 };
 
+/* for KVM_CAP_XSAVE */
+struct kvm_xsave {
+        __u32 region[1024];
+};
+
+#define KVM_MAX_XCRS    16
+
+struct kvm_xcr {
+        __u32 xcr;
+        __u32 reserved;
+        __u64 value;
+};
+
+struct kvm_xcrs {
+        __u32 nr_xcrs;
+        __u32 flags;
+        struct kvm_xcr xcrs[KVM_MAX_XCRS];
+        __u64 padding[16];
+};
+
 #endif /* _ASM_X86_KVM_H */
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index 0b2729bf2070..51cfd730ac5d 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -51,8 +51,10 @@ struct x86_emulate_ctxt;
 #define X86EMUL_UNHANDLEABLE    1
 /* Terminate emulation but return success to the caller. */
 #define X86EMUL_PROPAGATE_FAULT 2 /* propagate a generated fault to guest */
-#define X86EMUL_RETRY_INSTR     2 /* retry the instruction for some reason */
-#define X86EMUL_CMPXCHG_FAILED  2 /* cmpxchg did not see expected value */
+#define X86EMUL_RETRY_INSTR     3 /* retry the instruction for some reason */
+#define X86EMUL_CMPXCHG_FAILED  4 /* cmpxchg did not see expected value */
+#define X86EMUL_IO_NEEDED       5 /* IO is needed to complete emulation */
+
 struct x86_emulate_ops {
         /*
          * read_std: Read bytes of standard (non-emulated/special) memory.
@@ -92,6 +94,7 @@ struct x86_emulate_ops {
         int (*read_emulated)(unsigned long addr,
                              void *val,
                              unsigned int bytes,
+                             unsigned int *error,
                              struct kvm_vcpu *vcpu);
 
         /*
@@ -104,6 +107,7 @@ struct x86_emulate_ops {
         int (*write_emulated)(unsigned long addr,
                               const void *val,
                               unsigned int bytes,
+                              unsigned int *error,
                               struct kvm_vcpu *vcpu);
 
         /*
@@ -118,6 +122,7 @@ struct x86_emulate_ops {
                                 const void *old,
                                 const void *new,
                                 unsigned int bytes,
+                                unsigned int *error,
                                 struct kvm_vcpu *vcpu);
 
         int (*pio_in_emulated)(int size, unsigned short port, void *val,
@@ -132,18 +137,26 @@ struct x86_emulate_ops {
                                       int seg, struct kvm_vcpu *vcpu);
         u16 (*get_segment_selector)(int seg, struct kvm_vcpu *vcpu);
         void (*set_segment_selector)(u16 sel, int seg, struct kvm_vcpu *vcpu);
+        unsigned long (*get_cached_segment_base)(int seg, struct kvm_vcpu *vcpu);
         void (*get_gdt)(struct desc_ptr *dt, struct kvm_vcpu *vcpu);
         ulong (*get_cr)(int cr, struct kvm_vcpu *vcpu);
-        void (*set_cr)(int cr, ulong val, struct kvm_vcpu *vcpu);
+        int (*set_cr)(int cr, ulong val, struct kvm_vcpu *vcpu);
         int (*cpl)(struct kvm_vcpu *vcpu);
-        void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
+        int (*get_dr)(int dr, unsigned long *dest, struct kvm_vcpu *vcpu);
+        int (*set_dr)(int dr, unsigned long value, struct kvm_vcpu *vcpu);
+        int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
+        int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
 };
 
 /* Type, address-of, and value of an instruction's operand. */
 struct operand {
         enum { OP_REG, OP_MEM, OP_IMM, OP_NONE } type;
         unsigned int bytes;
-        unsigned long val, orig_val, *ptr;
+        unsigned long orig_val, *ptr;
+        union {
+                unsigned long val;
+                char valptr[sizeof(unsigned long) + 2];
+        };
 };
 
 struct fetch_cache {
@@ -186,6 +199,7 @@ struct decode_cache {
         unsigned long modrm_val;
         struct fetch_cache fetch;
         struct read_cache io_read;
+        struct read_cache mem_read;
 };
 
 struct x86_emulate_ctxt {
@@ -202,6 +216,12 @@ struct x86_emulate_ctxt {
         int interruptibility;
 
         bool restart; /* restart string instruction after writeback */
+
+        int exception; /* exception that happens during emulation or -1 */
+        u32 error_code; /* error code for exception */
+        bool error_code_valid;
+        unsigned long cr2; /* faulted address in case of #PF */
+
         /* decode cache */
         struct decode_cache decode;
 };
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 76f5483cffec..502e53f999cf 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -15,6 +15,7 @@
 #include <linux/mm.h>
 #include <linux/mmu_notifier.h>
 #include <linux/tracepoint.h>
+#include <linux/cpumask.h>
 
 #include <linux/kvm.h>
 #include <linux/kvm_para.h>
@@ -39,11 +40,14 @@
                                   0xFFFFFF0000000000ULL)
 
 #define INVALID_PAGE (~(hpa_t)0)
+#define VALID_PAGE(x) ((x) != INVALID_PAGE)
+
 #define UNMAPPED_GVA (~(gpa_t)0)
 
 /* KVM Hugepage definitions for x86 */
 #define KVM_NR_PAGE_SIZES       3
-#define KVM_HPAGE_SHIFT(x)      (PAGE_SHIFT + (((x) - 1) * 9))
+#define KVM_HPAGE_GFN_SHIFT(x)  (((x) - 1) * 9)
+#define KVM_HPAGE_SHIFT(x)      (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
 #define KVM_HPAGE_SIZE(x)       (1UL << KVM_HPAGE_SHIFT(x))
 #define KVM_HPAGE_MASK(x)       (~(KVM_HPAGE_SIZE(x) - 1))
 #define KVM_PAGES_PER_HPAGE(x)  (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
@@ -69,8 +73,6 @@
 
 #define IOPL_SHIFT 12
 
-#define KVM_ALIAS_SLOTS 4
-
 #define KVM_PERMILLE_MMU_PAGES 20
 #define KVM_MIN_ALLOC_MMU_PAGES 64
 #define KVM_MMU_HASH_SHIFT 10
@@ -241,7 +243,7 @@ struct kvm_mmu {
         void (*prefetch_page)(struct kvm_vcpu *vcpu,
                               struct kvm_mmu_page *page);
         int (*sync_page)(struct kvm_vcpu *vcpu,
-                         struct kvm_mmu_page *sp);
+                         struct kvm_mmu_page *sp, bool clear_unsync);
         void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva);
         hpa_t root_hpa;
         int root_level;
@@ -301,8 +303,8 @@ struct kvm_vcpu_arch {
                 unsigned long mmu_seq;
         } update_pte;
 
-        struct i387_fxsave_struct host_fx_image;
-        struct i387_fxsave_struct guest_fx_image;
+        struct fpu guest_fpu;
+        u64 xcr0;
 
         gva_t mmio_fault_cr2;
         struct kvm_pio_request pio;
@@ -360,26 +362,11 @@ struct kvm_vcpu_arch {
 
         /* fields used by HYPER-V emulation */
         u64 hv_vapic;
-};
-
-struct kvm_mem_alias {
-        gfn_t base_gfn;
-        unsigned long npages;
-        gfn_t target_gfn;
-#define KVM_ALIAS_INVALID     1UL
-        unsigned long flags;
-};
 
-#define KVM_ARCH_HAS_UNALIAS_INSTANTIATION
-
-struct kvm_mem_aliases {
-        struct kvm_mem_alias aliases[KVM_ALIAS_SLOTS];
-        int naliases;
+        cpumask_var_t wbinvd_dirty_mask;
 };
 
 struct kvm_arch {
-        struct kvm_mem_aliases *aliases;
-
         unsigned int n_free_mmu_pages;
         unsigned int n_requested_mmu_pages;
         unsigned int n_alloc_mmu_pages;
@@ -533,6 +520,8 @@ struct kvm_x86_ops {
 
         void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry);
 
+        bool (*has_wbinvd_exit)(void);
+
         const struct trace_print_flags *exit_reasons_str;
 };
 
@@ -576,7 +565,6 @@ enum emulation_result {
 #define EMULTYPE_SKIP               (1 << 2)
 int emulate_instruction(struct kvm_vcpu *vcpu,
                         unsigned long cr2, u16 error_code, int emulation_type);
-void kvm_report_emulation_failure(struct kvm_vcpu *cvpu, const char *context);
 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
 void realmode_lidt(struct kvm_vcpu *vcpu, u16 size, unsigned long address);
 
@@ -591,10 +579,7 @@ void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
 int kvm_emulate_halt(struct kvm_vcpu *vcpu);
 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address);
 int emulate_clts(struct kvm_vcpu *vcpu);
-int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
-                    unsigned long *dest);
-int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
-                    unsigned long value);
+int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
 
 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
@@ -602,15 +587,16 @@ int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
                     bool has_error_code, u32 error_code);
 
-void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
-void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
-void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
+int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
+int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
+int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
+int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr);
 
 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data);
@@ -630,12 +616,7 @@ int kvm_pic_set_irq(void *opaque, int irq, int level);
 
 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
 
-void fx_init(struct kvm_vcpu *vcpu);
-
-int emulator_write_emulated(unsigned long addr,
-                            const void *val,
-                            unsigned int bytes,
-                            struct kvm_vcpu *vcpu);
+int fx_init(struct kvm_vcpu *vcpu);
 
 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu);
 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
@@ -664,8 +645,6 @@ void kvm_disable_tdp(void);
 int complete_pio(struct kvm_vcpu *vcpu);
 bool kvm_check_iopl(struct kvm_vcpu *vcpu);
 
-struct kvm_memory_slot *gfn_to_memslot_unaliased(struct kvm *kvm, gfn_t gfn);
-
 static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
 {
         struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
@@ -719,21 +698,6 @@ static inline unsigned long read_msr(unsigned long msr)
 }
 #endif
 
-static inline void kvm_fx_save(struct i387_fxsave_struct *image)
-{
-        asm("fxsave (%0)":: "r" (image));
-}
-
-static inline void kvm_fx_restore(struct i387_fxsave_struct *image)
-{
-        asm("fxrstor (%0)":: "r" (image));
-}
-
-static inline void kvm_fx_finit(void)
-{
-        asm("finit");
-}
-
 static inline u32 get_rdx_init_val(void)
 {
         return 0x600; /* P6 family */
diff --git a/arch/x86/include/asm/local64.h b/arch/x86/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/x86/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index 451d30e7f62d..16350740edf6 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -13,6 +13,32 @@
 extern int pci_mrst_init(void);
 int __init sfi_parse_mrtc(struct sfi_table_header *table);
 
+/*
+ * Medfield is the follow-up of Moorestown, it combines two chip solution into
+ * one. Other than that it also added always-on and constant tsc and lapic
+ * timers. Medfield is the platform name, and the chip name is called Penwell
+ * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
+ * identified via MSRs.
+ */
+enum mrst_cpu_type {
+        MRST_CPU_CHIP_LINCROFT = 1,
+        MRST_CPU_CHIP_PENWELL,
+};
+
+extern enum mrst_cpu_type __mrst_cpu_chip;
+static enum mrst_cpu_type mrst_identify_cpu(void)
+{
+        return __mrst_cpu_chip;
+}
+
+enum mrst_timer_options {
+        MRST_TIMER_DEFAULT,
+        MRST_TIMER_APBT_ONLY,
+        MRST_TIMER_LAPIC_APBT,
+};
+
+extern enum mrst_timer_options mrst_timer_options;
+
 #define SFI_MTMR_MAX_NUM 8
 #define SFI_MRTC_MAX    8
 
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 8c7ae4318629..65bbec2093aa 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -20,6 +20,7 @@
 #define _EFER_LMA               10 /* Long mode active (read-only) */
 #define _EFER_NX                11 /* No execute enable */
 #define _EFER_SVME              12 /* Enable virtualization */
+#define _EFER_LMSLE             13 /* Long Mode Segment Limit Enable */
 #define _EFER_FFXSR             14 /* Enable Fast FXSAVE/FXRSTOR */
 
 #define EFER_SCE                (1<<_EFER_SCE)
@@ -27,6 +28,7 @@
 #define EFER_LMA                (1<<_EFER_LMA)
 #define EFER_NX                 (1<<_EFER_NX)
 #define EFER_SVME               (1<<_EFER_SVME)
+#define EFER_LMSLE              (1<<_EFER_LMSLE)
 #define EFER_FFXSR              (1<<_EFER_FFXSR)
 
 /* Intel MSRs. Some also available on other CPUs */
@@ -159,8 +161,6 @@
 #define MSR_K7_FID_VID_STATUS           0xc0010042
 
 /* K6 MSRs */
-#define MSR_K6_EFER                     0xc0000080
-#define MSR_K6_STAR                     0xc0000081
 #define MSR_K6_WHCR                     0xc0000082
 #define MSR_K6_UWCCR                    0xc0000085
 #define MSR_K6_EPMR                     0xc0000086
@@ -224,12 +224,14 @@
 #define MSR_IA32_THERM_CONTROL          0x0000019a
 #define MSR_IA32_THERM_INTERRUPT        0x0000019b
 
-#define THERM_INT_LOW_ENABLE            (1 << 0)
-#define THERM_INT_HIGH_ENABLE           (1 << 1)
+#define THERM_INT_HIGH_ENABLE           (1 << 0)
+#define THERM_INT_LOW_ENABLE            (1 << 1)
+#define THERM_INT_PLN_ENABLE            (1 << 24)
 
 #define MSR_IA32_THERM_STATUS           0x0000019c
 
 #define THERM_STATUS_PROCHOT            (1 << 0)
+#define THERM_STATUS_POWER_LIMIT        (1 << 10)
 
 #define MSR_THERM2_CTL                  0x0000019d
 
@@ -239,6 +241,19 @@
 
 #define MSR_IA32_TEMPERATURE_TARGET     0x000001a2
 
+#define MSR_IA32_ENERGY_PERF_BIAS       0x000001b0
+
+#define MSR_IA32_PACKAGE_THERM_STATUS           0x000001b1
+
+#define PACKAGE_THERM_STATUS_PROCHOT            (1 << 0)
+#define PACKAGE_THERM_STATUS_POWER_LIMIT        (1 << 10)
+
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT        0x000001b2
+
+#define PACKAGE_THERM_INT_HIGH_ENABLE           (1 << 0)
+#define PACKAGE_THERM_INT_LOW_ENABLE            (1 << 1)
+#define PACKAGE_THERM_INT_PLN_ENABLE            (1 << 24)
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING        (1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC                (1ULL << 1)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index c5bc4c2d33f5..084ef95274cd 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -148,8 +148,8 @@ static inline unsigned long long native_read_pmc(int counter)
 #define rdmsr(msr, val1, val2)                                  \
 do {                                                            \
         u64 __val = native_read_msr((msr));                     \
-        (val1) = (u32)__val;                                    \
-        (val2) = (u32)(__val >> 32);                            \
+        (void)((val1) = (u32)__val);                            \
+        (void)((val2) = (u32)(__val >> 32));                    \
 } while (0)
 
 static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index 93da9c3f3341..932f0f86b4b7 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -17,7 +17,9 @@ int do_nmi_callback(struct pt_regs *regs, int cpu);
 
 extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
 extern int check_nmi_watchdog(void);
+#if !defined(CONFIG_LOCKUP_DETECTOR)
 extern int nmi_watchdog_enabled;
+#endif
 extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);
 extern int reserve_perfctr_nmi(unsigned int);
 extern void release_perfctr_nmi(unsigned int);
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index cd2a31dc5fb8..49c7219826f9 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -30,6 +30,7 @@
 #define PCI_HAS_IO_ECS          0x40000
 #define PCI_NOASSIGN_ROMS       0x80000
 #define PCI_ROOT_NO_CRS         0x100000
+#define PCI_NOASSIGN_BARS       0x200000
 
 extern unsigned int pci_probe;
 extern unsigned long pirq_table_addr;
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 254883d0c7e0..6e742cc4251b 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -68,8 +68,9 @@ union cpuid10_eax {
 
 union cpuid10_edx {
         struct {
-                unsigned int num_counters_fixed:4;
-                unsigned int reserved:28;
+                unsigned int num_counters_fixed:5;
+                unsigned int bit_width_fixed:8;
+                unsigned int reserved:19;
         } split;
         unsigned int full;
 };
@@ -140,6 +141,19 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 extern unsigned long perf_misc_flags(struct pt_regs *regs);
 #define perf_misc_flags(regs)   perf_misc_flags(regs)
 
+#include <asm/stacktrace.h>
+
+/*
+ * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
+ * and the comment with PERF_EFLAGS_EXACT.
+ */
+#define perf_arch_fetch_caller_regs(regs, __ip)         {       \
+        (regs)->ip = (__ip);                                    \
+        (regs)->bp = caller_frame_pointer();                    \
+        (regs)->cs = __KERNEL_CS;                               \
+        regs->flags = 0;                                        \
+}
+
 #else
 static inline void init_hw_perf_events(void)            { }
 static inline void perf_events_lapic_init(void) { }
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 64a8ebff06fc..def500776b16 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -19,7 +19,6 @@
 #define ARCH_P4_RESERVED_ESCR   (2) /* IQ_ESCR(0,1) not always present */
 #define ARCH_P4_MAX_ESCR        (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
 #define ARCH_P4_MAX_CCCR        (18)
-#define ARCH_P4_MAX_COUNTER     (ARCH_P4_MAX_CCCR / 2)
 
 #define P4_ESCR_EVENT_MASK      0x7e000000U
 #define P4_ESCR_EVENT_SHIFT     25
@@ -71,10 +70,6 @@
 #define P4_CCCR_THRESHOLD(v)            ((v) << P4_CCCR_THRESHOLD_SHIFT)
 #define P4_CCCR_ESEL(v)                 ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
 
-/* Custom bits in reerved CCCR area */
-#define P4_CCCR_CACHE_OPS_MASK          0x0000003fU
-
-
 /* Non HT mask */
 #define P4_CCCR_MASK                            \
         (P4_CCCR_OVF                    |       \
@@ -106,8 +101,7 @@
  * ESCR and CCCR but rather an only packed value should
  * be unpacked and written to a proper addresses
  *
- * the base idea is to pack as much info as
- * possible
+ * the base idea is to pack as much info as possible
  */
 #define p4_config_pack_escr(v)          (((u64)(v)) << 32)
 #define p4_config_pack_cccr(v)          (((u64)(v)) & 0xffffffffULL)
@@ -130,8 +124,6 @@
                 t;                                      \
         })
 
-#define p4_config_unpack_cache_event(v) (((u64)(v)) & P4_CCCR_CACHE_OPS_MASK)
-
 #define P4_CONFIG_HT_SHIFT              63
 #define P4_CONFIG_HT                    (1ULL << P4_CONFIG_HT_SHIFT)
 
@@ -214,6 +206,12 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
         return escr;
 }
 
+/*
+ * This are the events which should be used in "Event Select"
+ * field of ESCR register, they are like unique keys which allow
+ * the kernel to determinate which CCCR and COUNTER should be
+ * used to track an event
+ */
 enum P4_EVENTS {
         P4_EVENT_TC_DELIVER_MODE,
         P4_EVENT_BPU_FETCH_REQUEST,
@@ -561,7 +559,7 @@ enum P4_EVENT_OPCODES {
  * a caller should use P4_ESCR_EMASK_NAME helper to
  * pick the EventMask needed, for example
  *
- *      P4_ESCR_EMASK_NAME(P4_EVENT_TC_DELIVER_MODE, DD)
+ *      P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD)
  */
 enum P4_ESCR_EMASKS {
         P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
@@ -753,43 +751,50 @@ enum P4_ESCR_EMASKS {
         P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
 };
 
-/* P4 PEBS: stale for a while */
-#define P4_PEBS_METRIC_MASK     0x00001fffU
-#define P4_PEBS_UOB_TAG         0x01000000U
-#define P4_PEBS_ENABLE          0x02000000U
-
-/* Replay metrics for MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT */
-#define P4_PEBS__1stl_cache_load_miss_retired   0x3000001
-#define P4_PEBS__2ndl_cache_load_miss_retired   0x3000002
-#define P4_PEBS__dtlb_load_miss_retired         0x3000004
-#define P4_PEBS__dtlb_store_miss_retired        0x3000004
-#define P4_PEBS__dtlb_all_miss_retired          0x3000004
-#define P4_PEBS__tagged_mispred_branch          0x3018000
-#define P4_PEBS__mob_load_replay_retired        0x3000200
-#define P4_PEBS__split_load_retired             0x3000400
-#define P4_PEBS__split_store_retired            0x3000400
-
-#define P4_VERT__1stl_cache_load_miss_retired   0x0000001
-#define P4_VERT__2ndl_cache_load_miss_retired   0x0000001
-#define P4_VERT__dtlb_load_miss_retired         0x0000001
-#define P4_VERT__dtlb_store_miss_retired        0x0000002
-#define P4_VERT__dtlb_all_miss_retired          0x0000003
-#define P4_VERT__tagged_mispred_branch          0x0000010
-#define P4_VERT__mob_load_replay_retired        0x0000001
-#define P4_VERT__split_load_retired             0x0000001
-#define P4_VERT__split_store_retired            0x0000002
-
-enum P4_CACHE_EVENTS {
-        P4_CACHE__NONE,
-
-        P4_CACHE__1stl_cache_load_miss_retired,
-        P4_CACHE__2ndl_cache_load_miss_retired,
-        P4_CACHE__dtlb_load_miss_retired,
-        P4_CACHE__dtlb_store_miss_retired,
-        P4_CACHE__itlb_reference_hit,
-        P4_CACHE__itlb_reference_miss,
-
-        P4_CACHE__MAX
+/*
+ * P4 PEBS specifics (Replay Event only)
+ *
+ * Format (bits):
+ *   0-6: metric from P4_PEBS_METRIC enum
+ *    7 : reserved
+ *    8 : reserved
+ * 9-11 : reserved
+ *
+ * Note we have UOP and PEBS bits reserved for now
+ * just in case if we will need them once
+ */
+#define P4_PEBS_CONFIG_ENABLE           (1 << 7)
+#define P4_PEBS_CONFIG_UOP_TAG          (1 << 8)
+#define P4_PEBS_CONFIG_METRIC_MASK      0x3f
+#define P4_PEBS_CONFIG_MASK             0xff
+
+/*
+ * mem: Only counters MSR_IQ_COUNTER4 (16) and
+ * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
+ */
+#define P4_PEBS_ENABLE                  0x02000000U
+#define P4_PEBS_ENABLE_UOP_TAG          0x01000000U
+
+#define p4_config_unpack_metric(v)      (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
+#define p4_config_unpack_pebs(v)        (((u64)(v)) & P4_PEBS_CONFIG_MASK)
+
+#define p4_config_pebs_has(v, mask)     (p4_config_unpack_pebs(v) & (mask))
+
+enum P4_PEBS_METRIC {
+        P4_PEBS_METRIC__none,
+
+        P4_PEBS_METRIC__1stl_cache_load_miss_retired,
+        P4_PEBS_METRIC__2ndl_cache_load_miss_retired,
+        P4_PEBS_METRIC__dtlb_load_miss_retired,
+        P4_PEBS_METRIC__dtlb_store_miss_retired,
+        P4_PEBS_METRIC__dtlb_all_miss_retired,
+        P4_PEBS_METRIC__tagged_mispred_branch,
+        P4_PEBS_METRIC__mob_load_replay_retired,
+        P4_PEBS_METRIC__split_load_retired,
+        P4_PEBS_METRIC__split_store_retired,
+
+        P4_PEBS_METRIC__max
 };
 
 #endif /* PERF_EVENT_P4_H */
+
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 7e5c6a60b8ee..325b7bdbebaa 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -762,6 +762,7 @@ extern void init_c1e_mask(void);
 extern unsigned long            boot_option_idle_override;
 extern unsigned long            idle_halt;
 extern unsigned long            idle_nomwait;
+extern bool                     c1e_detected;
 
 /*
  * on systems with caches, caches must be flashed as the absolute
@@ -1025,4 +1026,24 @@ unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
         return ratio;
 }
 
+/*
+ * AMD errata checking
+ */
+#ifdef CONFIG_CPU_SUP_AMD
+extern const int amd_erratum_383[];
+extern const int amd_erratum_400[];
+extern bool cpu_has_amd_erratum(const int *);
+
+#define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
+#define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
+        ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
+#define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
+#define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
+#define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
+
+#else
+#define cpu_has_amd_erratum(x)  (false)
+#endif /* CONFIG_CPU_SUP_AMD */
+
 #endif /* _ASM_X86_PROCESSOR_H */
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index 64cf2d24fad1..6c7fc25f2c34 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -84,5 +84,7 @@
 #define REQUIRED_MASK5  0
 #define REQUIRED_MASK6  0
 #define REQUIRED_MASK7  0
+#define REQUIRED_MASK8  0
+#define REQUIRED_MASK9  0
 
 #endif /* _ASM_X86_REQUIRED_FEATURES_H */
diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
index 606ede126972..d1e41b0f9b60 100644
--- a/arch/x86/include/asm/rwsem.h
+++ b/arch/x86/include/asm/rwsem.h
@@ -118,7 +118,7 @@ static inline void __down_read(struct rw_semaphore *sem)
 {
         asm volatile("# beginning down_read\n\t"
                      LOCK_PREFIX _ASM_INC "(%1)\n\t"
-                     /* adds 0x00000001, returns the old value */
+                     /* adds 0x00000001 */
                      "  jns        1f\n"
                      "  call call_rwsem_down_read_failed\n"
                      "1:\n\t"
@@ -156,11 +156,9 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
 static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
 {
         rwsem_count_t tmp;
-
-        tmp = RWSEM_ACTIVE_WRITE_BIAS;
         asm volatile("# beginning down_write\n\t"
                      LOCK_PREFIX "  xadd      %1,(%2)\n\t"
-                     /* subtract 0x0000ffff, returns the old value */
+                     /* adds 0xffff0001, returns the old value */
                      "  test      %1,%1\n\t"
                      /* was the count 0 before? */
                      "  jz        1f\n"
@@ -168,7 +166,7 @@ static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
                      "1:\n"
                      "# ending down_write"
                      : "+m" (sem->count), "=d" (tmp)
-                     : "a" (sem), "1" (tmp)
+                     : "a" (sem), "1" (RWSEM_ACTIVE_WRITE_BIAS)
                      : "memory", "cc");
 }
 
@@ -195,16 +193,16 @@ static inline int __down_write_trylock(struct rw_semaphore *sem)
  */
 static inline void __up_read(struct rw_semaphore *sem)
 {
-        rwsem_count_t tmp = -RWSEM_ACTIVE_READ_BIAS;
+        rwsem_count_t tmp;
         asm volatile("# beginning __up_read\n\t"
                      LOCK_PREFIX "  xadd      %1,(%2)\n\t"
                      /* subtracts 1, returns the old value */
                      "  jns        1f\n\t"
-                     "  call call_rwsem_wake\n"
+                     "  call call_rwsem_wake\n" /* expects old value in %edx */
                      "1:\n"
                      "# ending __up_read\n"
                      : "+m" (sem->count), "=d" (tmp)
-                     : "a" (sem), "1" (tmp)
+                     : "a" (sem), "1" (-RWSEM_ACTIVE_READ_BIAS)
                      : "memory", "cc");
 }
 
@@ -216,10 +214,9 @@ static inline void __up_write(struct rw_semaphore *sem)
         rwsem_count_t tmp;
         asm volatile("# beginning __up_write\n\t"
                      LOCK_PREFIX "  xadd      %1,(%2)\n\t"
-                     /* tries to transition
-                        0xffff0001 -> 0x00000000 */
-                     "  jz       1f\n"
-                     "  call call_rwsem_wake\n"
+                     /* subtracts 0xffff0001, returns the old value */
+                     "  jns        1f\n\t"
+                     "  call call_rwsem_wake\n" /* expects old value in %edx */
                      "1:\n\t"
                      "# ending __up_write\n"
                      : "+m" (sem->count), "=d" (tmp)
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index 86b1506f4179..ef292c792d74 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -82,7 +82,7 @@ void *extend_brk(size_t size, size_t align);
  * executable.)
  */
 #define RESERVE_BRK(name,sz)                                            \
-        static void __section(.discard) __used                          \
+        static void __section(.discard.text) __used                     \
         __brk_reservation_fn_##name##__(void) {                         \
                 asm volatile (                                          \
                         ".pushsection .brk_reservation,\"aw\",@nobits;" \
diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h
index 4dab78edbad9..2b16a2ad23dc 100644
--- a/arch/x86/include/asm/stacktrace.h
+++ b/arch/x86/include/asm/stacktrace.h
@@ -1,6 +1,13 @@
+/*
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *  Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
+ */
+
 #ifndef _ASM_X86_STACKTRACE_H
 #define _ASM_X86_STACKTRACE_H
 
+#include <linux/uaccess.h>
+
 extern int kstack_depth_to_print;
 
 struct thread_info;
@@ -42,4 +49,46 @@ void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp,
                 const struct stacktrace_ops *ops, void *data);
 
+#ifdef CONFIG_X86_32
+#define STACKSLOTS_PER_LINE 8
+#define get_bp(bp) asm("movl %%ebp, %0" : "=r" (bp) :)
+#else
+#define STACKSLOTS_PER_LINE 4
+#define get_bp(bp) asm("movq %%rbp, %0" : "=r" (bp) :)
+#endif
+
+extern void
+show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
+                unsigned long *stack, unsigned long bp, char *log_lvl);
+
+extern void
+show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
+                unsigned long *sp, unsigned long bp, char *log_lvl);
+
+extern unsigned int code_bytes;
+
+/* The form of the top of the frame on the stack */
+struct stack_frame {
+        struct stack_frame *next_frame;
+        unsigned long return_address;
+};
+
+struct stack_frame_ia32 {
+    u32 next_frame;
+    u32 return_address;
+};
+
+static inline unsigned long caller_frame_pointer(void)
+{
+        struct stack_frame *frame;
+
+        get_bp(frame);
+
+#ifdef CONFIG_FRAME_POINTER
+        frame = frame->next_frame;
+#endif
+
+        return (unsigned long)frame;
+}
+
 #endif /* _ASM_X86_STACKTRACE_H */
diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h
index e7f4d33c55ed..33ecc3ea8782 100644
--- a/arch/x86/include/asm/system.h
+++ b/arch/x86/include/asm/system.h
@@ -457,4 +457,11 @@ static __always_inline void rdtsc_barrier(void)
         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 }
 
+/*
+ * We handle most unaligned accesses in hardware.  On the other hand
+ * unaligned DMA can be quite expensive on some Nehalem processors.
+ *
+ * Based on this we disable the IP header alignment in network drivers.
+ */
+#define NET_IP_ALIGN    0
 #endif /* _ASM_X86_SYSTEM_H */
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 9e6779f7cf2d..9f0cbd987d50 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -257,6 +257,7 @@ enum vmcs_field {
 #define EXIT_REASON_IO_INSTRUCTION      30
 #define EXIT_REASON_MSR_READ            31
 #define EXIT_REASON_MSR_WRITE           32
+#define EXIT_REASON_INVALID_STATE       33
 #define EXIT_REASON_MWAIT_INSTRUCTION   36
 #define EXIT_REASON_MONITOR_INSTRUCTION 39
 #define EXIT_REASON_PAUSE_INSTRUCTION   40
@@ -266,6 +267,7 @@ enum vmcs_field {
 #define EXIT_REASON_EPT_VIOLATION       48
 #define EXIT_REASON_EPT_MISCONFIG       49
 #define EXIT_REASON_WBINVD              54
+#define EXIT_REASON_XSETBV              55
 
 /*
  * Interruption-information format
@@ -375,6 +377,9 @@ enum vmcs_field {
 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 
+#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
+#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
+
 #define VMX_EPT_DEFAULT_GAW                     3
 #define VMX_EPT_MAX_GAW                         0x4
 #define VMX_EPT_MT_EPTE_SHIFT                   3
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index 9c371e4a9fa6..7fda040a76cd 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -417,6 +417,12 @@ HYPERVISOR_nmi_op(unsigned long op, unsigned long arg)
         return _hypercall2(int, nmi_op, op, arg);
 }
 
+static inline unsigned long __must_check
+HYPERVISOR_hvm_op(int op, void *arg)
+{
+       return _hypercall2(unsigned long, hvm_op, op, arg);
+}
+
 static inline void
 MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set)
 {
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 2c4390cae228..32c36668fa7b 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -13,6 +13,12 @@
 
 #define FXSAVE_SIZE     512
 
+#define XSAVE_HDR_SIZE      64
+#define XSAVE_HDR_OFFSET    FXSAVE_SIZE
+
+#define XSAVE_YMM_SIZE      256
+#define XSAVE_YMM_OFFSET    (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
+
 /*
  * These are the features that the OS can handle currently.
  */
diff --git a/arch/x86/kernel/acpi/realmode/wakeup.S b/arch/x86/kernel/acpi/realmode/wakeup.S
index 580b4e296010..28595d6df47c 100644
--- a/arch/x86/kernel/acpi/realmode/wakeup.S
+++ b/arch/x86/kernel/acpi/realmode/wakeup.S
@@ -104,7 +104,7 @@ _start:
         movl    %eax, %ecx
         orl     %edx, %ecx
         jz      1f
-        movl    $0xc0000080, %ecx
+        movl    $MSR_EFER, %ecx
         wrmsr
 1:
 
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index fcc3c61fdecc..33cec152070d 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -2,7 +2,7 @@
  * sleep.c - x86-specific ACPI sleep support.
  *
  *  Copyright (C) 2001-2003 Patrick Mochel
- *  Copyright (C) 2001-2003 Pavel Machek <pavel@suse.cz>
+ *  Copyright (C) 2001-2003 Pavel Machek <pavel@ucw.cz>
  */
 
 #include <linux/acpi.h>
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 0d20286d78c6..fa044e1e30a2 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -2572,6 +2572,11 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
                                     unsigned long cap)
 {
+        switch (cap) {
+        case IOMMU_CAP_CACHE_COHERENCY:
+                return 1;
+        }
+
         return 0;
 }
 
@@ -2609,8 +2614,7 @@ int __init amd_iommu_init_passthrough(void)
 
         pt_domain->mode |= PAGE_MODE_NONE;
 
-        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-
+        for_each_pci_dev(dev) {
                 if (!check_device(&dev->dev))
                         continue;
 
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index a35347501d36..8dd77800ff5d 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -43,10 +43,11 @@
 
 #include <asm/fixmap.h>
 #include <asm/apb_timer.h>
+#include <asm/mrst.h>
 
 #define APBT_MASK                       CLOCKSOURCE_MASK(32)
 #define APBT_SHIFT                      22
-#define APBT_CLOCKEVENT_RATING          150
+#define APBT_CLOCKEVENT_RATING          110
 #define APBT_CLOCKSOURCE_RATING         250
 #define APBT_MIN_DELTA_USEC             200
 
@@ -83,8 +84,6 @@ struct apbt_dev {
         char name[10];
 };
 
-int disable_apbt_percpu __cpuinitdata;
-
 static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
 
 #ifdef CONFIG_SMP
@@ -195,29 +194,6 @@ static struct clock_event_device apbt_clockevent = {
 };
 
 /*
- * if user does not want to use per CPU apb timer, just give it a lower rating
- * than local apic timer and skip the late per cpu timer init.
- */
-static inline int __init setup_x86_mrst_timer(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-
-        if (strcmp("apbt_only", arg) == 0)
-                disable_apbt_percpu = 0;
-        else if (strcmp("lapic_and_apbt", arg) == 0)
-                disable_apbt_percpu = 1;
-        else {
-                pr_warning("X86 MRST timer option %s not recognised"
-                           " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
-                           arg);
-                return -EINVAL;
-        }
-        return 0;
-}
-__setup("x86_mrst_timer=", setup_x86_mrst_timer);
-
-/*
  * start count down from 0xffff_ffff. this is done by toggling the enable bit
  * then load initial load count to ~0.
  */
@@ -335,7 +311,7 @@ static int __init apbt_clockevent_register(void)
         adev->num = smp_processor_id();
         memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
 
-        if (disable_apbt_percpu) {
+        if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
                 apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
                 global_clock_event = &adev->evt;
                 printk(KERN_DEBUG "%s clockevent registered as global\n",
@@ -429,7 +405,8 @@ static int apbt_cpuhp_notify(struct notifier_block *n,
 
 static __init int apbt_late_init(void)
 {
-        if (disable_apbt_percpu || !apb_timer_block_enabled)
+        if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
+                !apb_timer_block_enabled)
                 return 0;
         /* This notifier should be called after workqueue is ready */
         hotcpu_notifier(apbt_cpuhp_notify, -20);
@@ -450,6 +427,8 @@ static void apbt_set_mode(enum clock_event_mode mode,
         int timer_num;
         struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
 
+        BUG_ON(!apbt_virt_address);
+
         timer_num = adev->num;
         pr_debug("%s CPU %d timer %d mode=%d\n",
                  __func__, first_cpu(*evt->cpumask), timer_num, mode);
@@ -676,7 +655,7 @@ void __init apbt_time_init(void)
         }
 #ifdef CONFIG_SMP
         /* kernel cmdline disable apb timer, so we will use lapic timers */
-        if (disable_apbt_percpu) {
+        if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
                 printk(KERN_INFO "apbt: disabled per cpu timer\n");
                 return;
         }
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index b5d8b0bcf235..a2e0caf26e17 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -280,7 +280,7 @@ void __init early_gart_iommu_check(void)
          * or BIOS forget to put that in reserved.
          * try to update e820 to make that region as reserved.
          */
-        u32 agp_aper_base = 0, agp_aper_order = 0;
+        u32 agp_aper_order = 0;
         int i, fix, slot, valid_agp = 0;
         u32 ctl;
         u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
@@ -291,7 +291,7 @@ void __init early_gart_iommu_check(void)
                 return;
 
         /* This is mostly duplicate of iommu_hole_init */
-        agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
+        search_agp_bridge(&agp_aper_order, &valid_agp);
 
         fix = 0;
         for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
index 565c1bfc507d..910f20b457c4 100644
--- a/arch/x86/kernel/apic/Makefile
+++ b/arch/x86/kernel/apic/Makefile
@@ -2,7 +2,12 @@
 # Makefile for local APIC drivers and for the IO-APIC code
 #
 
-obj-$(CONFIG_X86_LOCAL_APIC)    += apic.o apic_noop.o probe_$(BITS).o ipi.o nmi.o
+obj-$(CONFIG_X86_LOCAL_APIC)    += apic.o apic_noop.o probe_$(BITS).o ipi.o
+ifneq ($(CONFIG_HARDLOCKUP_DETECTOR),y)
+obj-$(CONFIG_X86_LOCAL_APIC)    += nmi.o
+endif
+obj-$(CONFIG_HARDLOCKUP_DETECTOR)       += hw_nmi.o
+
 obj-$(CONFIG_X86_IO_APIC)       += io_apic.o
 obj-$(CONFIG_SMP)               += ipi.o
 
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index a96489ee6cab..980508c79082 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -460,7 +460,7 @@ static void lapic_timer_broadcast(const struct cpumask *mask)
 }
 
 /*
- * Setup the local APIC timer for this CPU. Copy the initilized values
+ * Setup the local APIC timer for this CPU. Copy the initialized values
  * of the boot CPU and register the clock event in the framework.
  */
 static void __cpuinit setup_APIC_timer(void)
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
new file mode 100644
index 000000000000..cefd6942f0e9
--- /dev/null
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -0,0 +1,107 @@
+/*
+ *  HW NMI watchdog support
+ *
+ *  started by Don Zickus, Copyright (C) 2010 Red Hat, Inc.
+ *
+ *  Arch specific calls to support NMI watchdog
+ *
+ *  Bits copied from original nmi.c file
+ *
+ */
+#include <asm/apic.h>
+
+#include <linux/cpumask.h>
+#include <linux/kdebug.h>
+#include <linux/notifier.h>
+#include <linux/kprobes.h>
+#include <linux/nmi.h>
+#include <linux/module.h>
+
+/* For reliability, we're prepared to waste bits here. */
+static DECLARE_BITMAP(backtrace_mask, NR_CPUS) __read_mostly;
+
+u64 hw_nmi_get_sample_period(void)
+{
+        return (u64)(cpu_khz) * 1000 * 60;
+}
+
+#ifdef ARCH_HAS_NMI_WATCHDOG
+void arch_trigger_all_cpu_backtrace(void)
+{
+        int i;
+
+        cpumask_copy(to_cpumask(backtrace_mask), cpu_online_mask);
+
+        printk(KERN_INFO "sending NMI to all CPUs:\n");
+        apic->send_IPI_all(NMI_VECTOR);
+
+        /* Wait for up to 10 seconds for all CPUs to do the backtrace */
+        for (i = 0; i < 10 * 1000; i++) {
+                if (cpumask_empty(to_cpumask(backtrace_mask)))
+                        break;
+                mdelay(1);
+        }
+}
+
+static int __kprobes
+arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self,
+                         unsigned long cmd, void *__args)
+{
+        struct die_args *args = __args;
+        struct pt_regs *regs;
+        int cpu = smp_processor_id();
+
+        switch (cmd) {
+        case DIE_NMI:
+        case DIE_NMI_IPI:
+                break;
+
+        default:
+                return NOTIFY_DONE;
+        }
+
+        regs = args->regs;
+
+        if (cpumask_test_cpu(cpu, to_cpumask(backtrace_mask))) {
+                static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+                arch_spin_lock(&lock);
+                printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu);
+                show_regs(regs);
+                dump_stack();
+                arch_spin_unlock(&lock);
+                cpumask_clear_cpu(cpu, to_cpumask(backtrace_mask));
+                return NOTIFY_STOP;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static __read_mostly struct notifier_block backtrace_notifier = {
+        .notifier_call          = arch_trigger_all_cpu_backtrace_handler,
+        .next                   = NULL,
+        .priority               = 1
+};
+
+static int __init register_trigger_all_cpu_backtrace(void)
+{
+        register_die_notifier(&backtrace_notifier);
+        return 0;
+}
+early_initcall(register_trigger_all_cpu_backtrace);
+#endif
+
+/* STUB calls to mimic old nmi_watchdog behaviour */
+#if defined(CONFIG_X86_LOCAL_APIC)
+unsigned int nmi_watchdog = NMI_NONE;
+EXPORT_SYMBOL(nmi_watchdog);
+void acpi_nmi_enable(void) { return; }
+void acpi_nmi_disable(void) { return; }
+#endif
+atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
+EXPORT_SYMBOL(nmi_active);
+int unknown_nmi_panic;
+void cpu_nmi_set_wd_enabled(void) { return; }
+void stop_apic_nmi_watchdog(void *unused) { return; }
+void setup_apic_nmi_watchdog(void *unused) { return; }
+int __init check_nmi_watchdog(void) { return 0; }
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index e41ed24ab26d..4dc0084ec1b1 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -3397,7 +3397,7 @@ static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
 
         cfg = desc->chip_data;
 
-        read_msi_msg_desc(desc, &msg);
+        get_cached_msi_msg_desc(desc, &msg);
 
         msg.data &= ~MSI_DATA_VECTOR_MASK;
         msg.data |= MSI_DATA_VECTOR(cfg->vector);
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c
index 1edaf15c0b8e..a43f71cb30f8 100644
--- a/arch/x86/kernel/apic/nmi.c
+++ b/arch/x86/kernel/apic/nmi.c
@@ -401,13 +401,6 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
         int cpu = smp_processor_id();
         int rc = 0;
 
-        /* check for other users first */
-        if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
-                        == NOTIFY_STOP) {
-                rc = 1;
-                touched = 1;
-        }
-
         sum = get_timer_irqs(cpu);
 
         if (__get_cpu_var(nmi_touch)) {
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index c4f9182ca3ac..4c9c67bf09b7 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -140,7 +140,7 @@
  *         is now the way life works).
  *         Fix thinko in suspend() (wrong return).
  *         Notify drivers on critical suspend.
- *         Make kapmd absorb more idle time (Pavel Machek <pavel@suse.cz>
+ *         Make kapmd absorb more idle time (Pavel Machek <pavel@ucw.cz>
  *         modified by sfr).
  *         Disable interrupts while we are suspended (Andy Henroid
  *         <andy_henroid@yahoo.com> fixed by sfr).
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 3a785da34b6f..3f0ebe429a01 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -12,11 +12,11 @@ endif
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_common.o         := $(nostackp)
 
-obj-y                   := intel_cacheinfo.o addon_cpuid_features.o
+obj-y                   := intel_cacheinfo.o scattered.o topology.o
 obj-y                   += proc.o capflags.o powerflags.o common.o
 obj-y                   += vmware.o hypervisor.o sched.o mshyperv.o
 
-obj-$(CONFIG_X86_32)    += bugs.o cmpxchg.o
+obj-$(CONFIG_X86_32)    += bugs.o
 obj-$(CONFIG_X86_64)    += bugs_64.o
 
 obj-$(CONFIG_CPU_SUP_INTEL)             += intel.o
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index e485825130d2..60a57b13082d 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -466,7 +466,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 }
 
         }
-        if (c->x86 == 0x10 || c->x86 == 0x11)
+        if (c->x86 >= 0x10)
                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 
         /* get apicid instead of initial apic id from cpuid */
@@ -529,7 +529,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                         num_cache_leaves = 3;
         }
 
-        if (c->x86 >= 0xf && c->x86 <= 0x11)
+        if (c->x86 >= 0xf)
                 set_cpu_cap(c, X86_FEATURE_K8);
 
         if (cpu_has_xmm2) {
@@ -546,7 +546,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 fam10h_check_enable_mmcfg();
         }
 
-        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
+        if (c == &boot_cpu_data && c->x86 >= 0xf) {
                 unsigned long long tseg;
 
                 /*
@@ -609,3 +609,74 @@ static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
 };
 
 cpu_dev_register(amd_cpu_dev);
+
+/*
+ * AMD errata checking
+ *
+ * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
+ * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
+ * have an OSVW id assigned, which it takes as first argument. Both take a
+ * variable number of family-specific model-stepping ranges created by
+ * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
+ * int[] in arch/x86/include/asm/processor.h.
+ *
+ * Example:
+ *
+ * const int amd_erratum_319[] =
+ *      AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
+ *                         AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
+ *                         AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
+ */
+
+const int amd_erratum_400[] =
+        AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
+                            AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
+EXPORT_SYMBOL_GPL(amd_erratum_400);
+
+const int amd_erratum_383[] =
+        AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
+EXPORT_SYMBOL_GPL(amd_erratum_383);
+
+bool cpu_has_amd_erratum(const int *erratum)
+{
+        struct cpuinfo_x86 *cpu = &current_cpu_data;
+        int osvw_id = *erratum++;
+        u32 range;
+        u32 ms;
+
+        /*
+         * If called early enough that current_cpu_data hasn't been initialized
+         * yet, fall back to boot_cpu_data.
+         */
+        if (cpu->x86 == 0)
+                cpu = &boot_cpu_data;
+
+        if (cpu->x86_vendor != X86_VENDOR_AMD)
+                return false;
+
+        if (osvw_id >= 0 && osvw_id < 65536 &&
+            cpu_has(cpu, X86_FEATURE_OSVW)) {
+                u64 osvw_len;
+
+                rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
+                if (osvw_id < osvw_len) {
+                        u64 osvw_bits;
+
+                        rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
+                            osvw_bits);
+                        return osvw_bits & (1ULL << (osvw_id & 0x3f));
+                }
+        }
+
+        /* OSVW unavailable or ID unknown, match family-model-stepping range */
+        ms = (cpu->x86_model << 8) | cpu->x86_mask;
+        while ((range = *erratum++))
+                if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
+                    (ms >= AMD_MODEL_RANGE_START(range)) &&
+                    (ms <= AMD_MODEL_RANGE_END(range)))
+                        return true;
+
+        return false;
+}
+
+EXPORT_SYMBOL_GPL(cpu_has_amd_erratum);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 68e4a6f2211e..f10273138382 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -551,6 +551,16 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
                 c->x86_capability[4] = excap;
         }
 
+        /* Additional Intel-defined flags: level 0x00000007 */
+        if (c->cpuid_level >= 0x00000007) {
+                u32 eax, ebx, ecx, edx;
+
+                cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
+
+                if (eax > 0)
+                        c->x86_capability[9] = ebx;
+        }
+
         /* AMD-defined flags: level 0x80000001 */
         xlvl = cpuid_eax(0x80000000);
         c->extended_cpuid_level = xlvl;
@@ -576,6 +586,7 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
         if (c->extended_cpuid_level >= 0x80000007)
                 c->x86_power = cpuid_edx(0x80000007);
 
+        init_scattered_cpuid_features(c);
 }
 
 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
@@ -731,7 +742,6 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 
         get_model_name(c); /* Default name */
 
-        init_scattered_cpuid_features(c);
         detect_nopl(c);
 }
 
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index 1d3cddaa40ee..246cd3afbb5f 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -34,7 +34,6 @@
 #include <linux/compiler.h>
 #include <linux/dmi.h>
 #include <linux/slab.h>
-#include <trace/events/power.h>
 
 #include <linux/acpi.h>
 #include <linux/io.h>
@@ -324,8 +323,6 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
                 }
         }
 
-        trace_power_frequency(POWER_PSTATE, data->freq_table[next_state].frequency);
-
         switch (data->cpu_feature) {
         case SYSTEM_INTEL_MSR_CAPABLE:
                 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
@@ -351,7 +348,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
 
         freqs.old = perf->states[perf->state].core_frequency * 1000;
         freqs.new = data->freq_table[next_state].frequency;
-        for_each_cpu(i, cmd.mask) {
+        for_each_cpu(i, policy->cpus) {
                 freqs.cpu = i;
                 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
         }
@@ -367,7 +364,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
                 }
         }
 
-        for_each_cpu(i, cmd.mask) {
+        for_each_cpu(i, policy->cpus) {
                 freqs.cpu = i;
                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
         }
diff --git a/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c b/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
index 16e3483be9e3..32974cf84232 100644
--- a/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
@@ -169,12 +169,9 @@ static int gx_freq_mult[16] = {
  *      Low Level chipset interface                             *
  ****************************************************************/
 static struct pci_device_id gx_chipset_tbl[] __initdata = {
-        { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
-                PCI_ANY_ID, PCI_ANY_ID },
-        { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520,
-                PCI_ANY_ID, PCI_ANY_ID },
-        { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510,
-                PCI_ANY_ID, PCI_ANY_ID },
+        { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY), },
+        { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
+        { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
         { 0, },
 };
 
@@ -199,7 +196,7 @@ static __init struct pci_dev *gx_detect_chipset(void)
         }
 
         /* detect which companion chip is used */
-        while ((gx_pci = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, gx_pci)) != NULL) {
+        for_each_pci_dev(gx_pci) {
                 if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
                         return gx_pci;
         }
diff --git a/arch/x86/kernel/cpu/cpufreq/longhaul.c b/arch/x86/kernel/cpu/cpufreq/longhaul.c
index 7e7eea4f8261..03162dac6271 100644
--- a/arch/x86/kernel/cpu/cpufreq/longhaul.c
+++ b/arch/x86/kernel/cpu/cpufreq/longhaul.c
@@ -426,7 +426,7 @@ static int guess_fsb(int mult)
 }
 
 
-static int __init longhaul_get_ranges(void)
+static int __cpuinit longhaul_get_ranges(void)
 {
         unsigned int i, j, k = 0;
         unsigned int ratio;
@@ -530,7 +530,7 @@ static int __init longhaul_get_ranges(void)
 }
 
 
-static void __init longhaul_setup_voltagescaling(void)
+static void __cpuinit longhaul_setup_voltagescaling(void)
 {
         union msr_longhaul longhaul;
         struct mV_pos minvid, maxvid, vid;
@@ -784,7 +784,7 @@ static int longhaul_setup_southbridge(void)
         return 0;
 }
 
-static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
+static int __cpuinit longhaul_cpu_init(struct cpufreq_policy *policy)
 {
         struct cpuinfo_x86 *c = &cpu_data(0);
         char *cpuname = NULL;
diff --git a/arch/x86/kernel/cpu/cpufreq/longhaul.h b/arch/x86/kernel/cpu/cpufreq/longhaul.h
index e2360a469f79..cbf48fbca881 100644
--- a/arch/x86/kernel/cpu/cpufreq/longhaul.h
+++ b/arch/x86/kernel/cpu/cpufreq/longhaul.h
@@ -56,7 +56,7 @@ union msr_longhaul {
 /*
  * VIA C3 Samuel 1  & Samuel 2 (stepping 0)
  */
-static const int __initdata samuel1_mults[16] = {
+static const int __cpuinitdata samuel1_mults[16] = {
         -1, /* 0000 -> RESERVED */
         30, /* 0001 ->  3.0x */
         40, /* 0010 ->  4.0x */
@@ -75,7 +75,7 @@ static const int __initdata samuel1_mults[16] = {
         -1, /* 1111 -> RESERVED */
 };
 
-static const int __initdata samuel1_eblcr[16] = {
+static const int __cpuinitdata samuel1_eblcr[16] = {
         50, /* 0000 -> RESERVED */
         30, /* 0001 ->  3.0x */
         40, /* 0010 ->  4.0x */
@@ -97,7 +97,7 @@ static const int __initdata samuel1_eblcr[16] = {
 /*
  * VIA C3 Samuel2 Stepping 1->15
  */
-static const int __initdata samuel2_eblcr[16] = {
+static const int __cpuinitdata samuel2_eblcr[16] = {
         50,  /* 0000 ->  5.0x */
         30,  /* 0001 ->  3.0x */
         40,  /* 0010 ->  4.0x */
@@ -119,7 +119,7 @@ static const int __initdata samuel2_eblcr[16] = {
 /*
  * VIA C3 Ezra
  */
-static const int __initdata ezra_mults[16] = {
+static const int __cpuinitdata ezra_mults[16] = {
         100, /* 0000 -> 10.0x */
         30,  /* 0001 ->  3.0x */
         40,  /* 0010 ->  4.0x */
@@ -138,7 +138,7 @@ static const int __initdata ezra_mults[16] = {
         120, /* 1111 -> 12.0x */
 };
 
-static const int __initdata ezra_eblcr[16] = {
+static const int __cpuinitdata ezra_eblcr[16] = {
         50,  /* 0000 ->  5.0x */
         30,  /* 0001 ->  3.0x */
         40,  /* 0010 ->  4.0x */
@@ -160,7 +160,7 @@ static const int __initdata ezra_eblcr[16] = {
 /*
  * VIA C3 (Ezra-T) [C5M].
  */
-static const int __initdata ezrat_mults[32] = {
+static const int __cpuinitdata ezrat_mults[32] = {
         100, /* 0000 -> 10.0x */
         30,  /* 0001 ->  3.0x */
         40,  /* 0010 ->  4.0x */
@@ -196,7 +196,7 @@ static const int __initdata ezrat_mults[32] = {
         -1,  /* 1111 -> RESERVED (12.0x) */
 };
 
-static const int __initdata ezrat_eblcr[32] = {
+static const int __cpuinitdata ezrat_eblcr[32] = {
         50,  /* 0000 ->  5.0x */
         30,  /* 0001 ->  3.0x */
         40,  /* 0010 ->  4.0x */
@@ -235,7 +235,7 @@ static const int __initdata ezrat_eblcr[32] = {
 /*
  * VIA C3 Nehemiah */
 
-static const int __initdata  nehemiah_mults[32] = {
+static const int __cpuinitdata nehemiah_mults[32] = {
         100, /* 0000 -> 10.0x */
         -1, /* 0001 -> 16.0x */
         40,  /* 0010 ->  4.0x */
@@ -270,7 +270,7 @@ static const int __initdata  nehemiah_mults[32] = {
         -1, /* 1111 -> 12.0x */
 };
 
-static const int __initdata nehemiah_eblcr[32] = {
+static const int __cpuinitdata nehemiah_eblcr[32] = {
         50,  /* 0000 ->  5.0x */
         160, /* 0001 -> 16.0x */
         40,  /* 0010 ->  4.0x */
@@ -315,7 +315,7 @@ struct mV_pos {
         unsigned short pos;
 };
 
-static const struct mV_pos __initdata vrm85_mV[32] = {
+static const struct mV_pos __cpuinitdata vrm85_mV[32] = {
         {1250, 8},      {1200, 6},      {1150, 4},      {1100, 2},
         {1050, 0},      {1800, 30},     {1750, 28},     {1700, 26},
         {1650, 24},     {1600, 22},     {1550, 20},     {1500, 18},
@@ -326,14 +326,14 @@ static const struct mV_pos __initdata vrm85_mV[32] = {
         {1475, 17},     {1425, 15},     {1375, 13},     {1325, 11}
 };
 
-static const unsigned char __initdata mV_vrm85[32] = {
+static const unsigned char __cpuinitdata mV_vrm85[32] = {
         0x04,   0x14,   0x03,   0x13,   0x02,   0x12,   0x01,   0x11,
         0x00,   0x10,   0x0f,   0x1f,   0x0e,   0x1e,   0x0d,   0x1d,
         0x0c,   0x1c,   0x0b,   0x1b,   0x0a,   0x1a,   0x09,   0x19,
         0x08,   0x18,   0x07,   0x17,   0x06,   0x16,   0x05,   0x15
 };
 
-static const struct mV_pos __initdata mobilevrm_mV[32] = {
+static const struct mV_pos __cpuinitdata mobilevrm_mV[32] = {
         {1750, 31},     {1700, 30},     {1650, 29},     {1600, 28},
         {1550, 27},     {1500, 26},     {1450, 25},     {1400, 24},
         {1350, 23},     {1300, 22},     {1250, 21},     {1200, 20},
@@ -344,7 +344,7 @@ static const struct mV_pos __initdata mobilevrm_mV[32] = {
         {675, 3},       {650, 2},       {625, 1},       {600, 0}
 };
 
-static const unsigned char __initdata mV_mobilevrm[32] = {
+static const unsigned char __cpuinitdata mV_mobilevrm[32] = {
         0x1f,   0x1e,   0x1d,   0x1c,   0x1b,   0x1a,   0x19,   0x18,
         0x17,   0x16,   0x15,   0x14,   0x13,   0x12,   0x11,   0x10,
         0x0f,   0x0e,   0x0d,   0x0c,   0x0b,   0x0a,   0x09,   0x08,
diff --git a/arch/x86/kernel/cpu/cpufreq/longrun.c b/arch/x86/kernel/cpu/cpufreq/longrun.c
index e7b559d74c52..fc09f142d94d 100644
--- a/arch/x86/kernel/cpu/cpufreq/longrun.c
+++ b/arch/x86/kernel/cpu/cpufreq/longrun.c
@@ -165,8 +165,8 @@ static unsigned int longrun_get(unsigned int cpu)
  * TMTA rules:
  * performance_pctg = (target_freq - low_freq)/(high_freq - low_freq)
  */
-static unsigned int __init longrun_determine_freqs(unsigned int *low_freq,
-                                                   unsigned int *high_freq)
+static unsigned int __cpuinit longrun_determine_freqs(unsigned int *low_freq,
+                                                      unsigned int *high_freq)
 {
         u32 msr_lo, msr_hi;
         u32 save_lo, save_hi;
@@ -258,7 +258,7 @@ static unsigned int __init longrun_determine_freqs(unsigned int *low_freq,
 }
 
 
-static int __init longrun_cpu_init(struct cpufreq_policy *policy)
+static int __cpuinit longrun_cpu_init(struct cpufreq_policy *policy)
 {
         int result = 0;
 
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index 7b8a8ba67b07..bd1cac747f67 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -178,13 +178,8 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
                 }
         }
 
-        if (c->x86 != 0xF) {
-                if (!cpu_has(c, X86_FEATURE_EST))
-                        printk(KERN_WARNING PFX "Unknown CPU. "
-                                "Please send an e-mail to "
-                                "<cpufreq@vger.kernel.org>\n");
+        if (c->x86 != 0xF)
                 return 0;
-        }
 
         /* on P-4s, the TSC runs with constant frequency independent whether
          * throttling is active or not. */
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
index 9a97116f89e5..4a45fd6e41ba 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k7.c
@@ -569,7 +569,7 @@ static int powernow_verify(struct cpufreq_policy *policy)
  * We will then get the same kind of behaviour already tested under
  * the "well-known" other OS.
  */
-static int __init fixup_sgtc(void)
+static int __cpuinit fixup_sgtc(void)
 {
         unsigned int sgtc;
         unsigned int m;
@@ -603,7 +603,7 @@ static unsigned int powernow_get(unsigned int cpu)
 }
 
 
-static int __init acer_cpufreq_pst(const struct dmi_system_id *d)
+static int __cpuinit acer_cpufreq_pst(const struct dmi_system_id *d)
 {
         printk(KERN_WARNING PFX
                 "%s laptop with broken PST tables in BIOS detected.\n",
@@ -621,7 +621,7 @@ static int __init acer_cpufreq_pst(const struct dmi_system_id *d)
  * A BIOS update is all that can save them.
  * Mention this, and disable cpufreq.
  */
-static struct dmi_system_id __initdata powernow_dmi_table[] = {
+static struct dmi_system_id __cpuinitdata powernow_dmi_table[] = {
         {
                 .callback = acer_cpufreq_pst,
                 .ident = "Acer Aspire",
@@ -633,7 +633,7 @@ static struct dmi_system_id __initdata powernow_dmi_table[] = {
         { }
 };
 
-static int __init powernow_cpu_init(struct cpufreq_policy *policy)
+static int __cpuinit powernow_cpu_init(struct cpufreq_policy *policy)
 {
         union msr_fidvidstatus fidvidstatus;
         int result;
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 3e90cce3dc8b..491977baf6c0 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -9,7 +9,7 @@
  *  Based on the powernow-k7.c module written by Dave Jones.
  *  (C) 2003 Dave Jones on behalf of SuSE Labs
  *  (C) 2004 Dominik Brodowski <linux@brodo.de>
- *  (C) 2004 Pavel Machek <pavel@suse.cz>
+ *  (C) 2004 Pavel Machek <pavel@ucw.cz>
  *  Licensed under the terms of the GNU GPL License version 2.
  *  Based upon datasheets & sample CPUs kindly provided by AMD.
  *
@@ -806,6 +806,8 @@ static int find_psb_table(struct powernow_k8_data *data)
          * www.amd.com
          */
         printk(KERN_ERR FW_BUG PFX "No PSB or ACPI _PSS objects\n");
+        printk(KERN_ERR PFX "Make sure that your BIOS is up to date"
+                " and Cool'N'Quiet support is enabled in BIOS setup\n");
         return -ENODEV;
 }
 
@@ -910,8 +912,8 @@ static int fill_powernow_table_pstate(struct powernow_k8_data *data,
 {
         int i;
         u32 hi = 0, lo = 0;
-        rdmsr(MSR_PSTATE_CUR_LIMIT, hi, lo);
-        data->max_hw_pstate = (hi & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT;
+        rdmsr(MSR_PSTATE_CUR_LIMIT, lo, hi);
+        data->max_hw_pstate = (lo & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT;
 
         for (i = 0; i < data->acpi_data.state_count; i++) {
                 u32 index;
diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c
index dd531cc56a8f..8095f8611f8a 100644
--- a/arch/x86/kernel/cpu/hypervisor.c
+++ b/arch/x86/kernel/cpu/hypervisor.c
@@ -34,6 +34,9 @@ static const __initconst struct hypervisor_x86 * const hypervisors[] =
 {
         &x86_hyper_vmware,
         &x86_hyper_ms_hyperv,
+#ifdef CONFIG_XEN_PVHVM
+        &x86_hyper_xen_hvm,
+#endif
 };
 
 const struct hypervisor_x86 *x86_hyper;
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 33eae2062cf5..898c2f4eab88 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -347,8 +347,8 @@ static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
         return l3;
 }
 
-static void __cpuinit
-amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
+static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
+                                           int index)
 {
         int node;
 
@@ -396,20 +396,39 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
         this_leaf->l3 = l3_caches[node];
 }
 
+/*
+ * check whether a slot used for disabling an L3 index is occupied.
+ * @l3: L3 cache descriptor
+ * @slot: slot number (0..1)
+ *
+ * @returns: the disabled index if used or negative value if slot free.
+ */
+int amd_get_l3_disable_slot(struct amd_l3_cache *l3, unsigned slot)
+{
+        unsigned int reg = 0;
+
+        pci_read_config_dword(l3->dev, 0x1BC + slot * 4, &reg);
+
+        /* check whether this slot is activated already */
+        if (reg & (3UL << 30))
+                return reg & 0xfff;
+
+        return -1;
+}
+
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
                                   unsigned int slot)
 {
-        struct pci_dev *dev = this_leaf->l3->dev;
-        unsigned int reg = 0;
+        int index;
 
         if (!this_leaf->l3 || !this_leaf->l3->can_disable)
                 return -EINVAL;
 
-        if (!dev)
-                return -EINVAL;
+        index = amd_get_l3_disable_slot(this_leaf->l3, slot);
+        if (index >= 0)
+                return sprintf(buf, "%d\n", index);
 
-        pci_read_config_dword(dev, 0x1BC + slot * 4, &reg);
-        return sprintf(buf, "0x%08x\n", reg);
+        return sprintf(buf, "FREE\n");
 }
 
 #define SHOW_CACHE_DISABLE(slot)                                        \
@@ -451,37 +470,74 @@ static void amd_l3_disable_index(struct amd_l3_cache *l3, int cpu,
         }
 }
 
-
-static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
-                                   const char *buf, size_t count,
-                                   unsigned int slot)
+/*
+ * disable a L3 cache index by using a disable-slot
+ *
+ * @l3:    L3 cache descriptor
+ * @cpu:   A CPU on the node containing the L3 cache
+ * @slot:  slot number (0..1)
+ * @index: index to disable
+ *
+ * @return: 0 on success, error status on failure
+ */
+int amd_set_l3_disable_slot(struct amd_l3_cache *l3, int cpu, unsigned slot,
+                            unsigned long index)
 {
-        struct pci_dev *dev = this_leaf->l3->dev;
-        int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
-        unsigned long val = 0;
+        int ret = 0;
 
 #define SUBCACHE_MASK   (3UL << 20)
 #define SUBCACHE_INDEX  0xfff
 
-        if (!this_leaf->l3 || !this_leaf->l3->can_disable)
+        /*
+         * check whether this slot is already used or
+         * the index is already disabled
+         */
+        ret = amd_get_l3_disable_slot(l3, slot);
+        if (ret >= 0)
                 return -EINVAL;
 
+        /*
+         * check whether the other slot has disabled the
+         * same index already
+         */
+        if (index == amd_get_l3_disable_slot(l3, !slot))
+                return -EINVAL;
+
+        /* do not allow writes outside of allowed bits */
+        if ((index & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
+            ((index & SUBCACHE_INDEX) > l3->indices))
+                return -EINVAL;
+
+        amd_l3_disable_index(l3, cpu, slot, index);
+
+        return 0;
+}
+
+static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
+                                  const char *buf, size_t count,
+                                  unsigned int slot)
+{
+        unsigned long val = 0;
+        int cpu, err = 0;
+
         if (!capable(CAP_SYS_ADMIN))
                 return -EPERM;
 
-        if (!dev)
+        if (!this_leaf->l3 || !this_leaf->l3->can_disable)
                 return -EINVAL;
 
-        if (strict_strtoul(buf, 10, &val) < 0)
-                return -EINVAL;
+        cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
 
-        /* do not allow writes outside of allowed bits */
-        if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
-            ((val & SUBCACHE_INDEX) > this_leaf->l3->indices))
+        if (strict_strtoul(buf, 10, &val) < 0)
                 return -EINVAL;
 
-        amd_l3_disable_index(this_leaf->l3, cpu, slot, val);
-
+        err = amd_set_l3_disable_slot(this_leaf->l3, cpu, slot, val);
+        if (err) {
+                if (err == -EEXIST)
+                        printk(KERN_WARNING "L3 disable slot %d in use!\n",
+                                            slot);
+                return err;
+        }
         return count;
 }
 
@@ -502,7 +558,7 @@ static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
 
 #else   /* CONFIG_CPU_SUP_AMD */
 static void __cpuinit
-amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
+amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
 {
 };
 #endif /* CONFIG_CPU_SUP_AMD */
@@ -518,7 +574,7 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
 
         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
                 amd_cpuid4(index, &eax, &ebx, &ecx);
-                amd_check_l3_disable(index, this_leaf);
+                amd_check_l3_disable(this_leaf, index);
         } else {
                 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
         }
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 18cc42562250..e1269d62c569 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -51,7 +51,7 @@
 static DEFINE_MUTEX(mce_read_mutex);
 
 #define rcu_dereference_check_mce(p) \
-        rcu_dereference_check((p), \
+        rcu_dereference_index_check((p), \
                               rcu_read_lock_sched_held() || \
                               lockdep_is_held(&mce_read_mutex))
 
@@ -600,6 +600,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                  */
                 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
                         mce_log(&m);
+                        atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
                         add_taint(TAINT_MACHINE_CHECK);
                 }
 
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index e1a0a3bf9716..c2a8b26d4fea 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -34,15 +34,25 @@
 /* How long to wait between reporting thermal events */
 #define CHECK_INTERVAL          (300 * HZ)
 
+#define THERMAL_THROTTLING_EVENT        0
+#define POWER_LIMIT_EVENT               1
+
 /*
- * Current thermal throttling state:
+ * Current thermal event state:
  */
-struct thermal_state {
-        bool                    is_throttled;
-
+struct _thermal_state {
+        bool                    new_event;
+        int                     event;
         u64                     next_check;
-        unsigned long           throttle_count;
-        unsigned long           last_throttle_count;
+        unsigned long           count;
+        unsigned long           last_count;
+};
+
+struct thermal_state {
+        struct _thermal_state core_throttle;
+        struct _thermal_state core_power_limit;
+        struct _thermal_state package_throttle;
+        struct _thermal_state package_power_limit;
 };
 
 static DEFINE_PER_CPU(struct thermal_state, thermal_state);
@@ -53,11 +63,13 @@ static u32 lvtthmr_init __read_mostly;
 
 #ifdef CONFIG_SYSFS
 #define define_therm_throt_sysdev_one_ro(_name)                         \
-        static SYSDEV_ATTR(_name, 0444, therm_throt_sysdev_show_##_name, NULL)
+        static SYSDEV_ATTR(_name, 0444,                                 \
+                           therm_throt_sysdev_show_##_name,             \
+                                   NULL)                                \
 
-#define define_therm_throt_sysdev_show_func(name)                       \
+#define define_therm_throt_sysdev_show_func(event, name)                \
                                                                         \
-static ssize_t therm_throt_sysdev_show_##name(                          \
+static ssize_t therm_throt_sysdev_show_##event##_##name(                \
                         struct sys_device *dev,                         \
                         struct sysdev_attribute *attr,                  \
                         char *buf)                                      \
@@ -66,30 +78,42 @@ static ssize_t therm_throt_sysdev_show_##name(				\
         ssize_t ret;                                                    \
                                                                         \
         preempt_disable();      /* CPU hotplug */                       \
-        if (cpu_online(cpu))                                            \
+        if (cpu_online(cpu)) {                                          \
                 ret = sprintf(buf, "%lu\n",                             \
-                              per_cpu(thermal_state, cpu).name);        \
-        else                                                            \
+                              per_cpu(thermal_state, cpu).event.name);  \
+        } else                                                          \
                 ret = 0;                                                \
         preempt_enable();                                               \
                                                                         \
         return ret;                                                     \
 }
 
-define_therm_throt_sysdev_show_func(throttle_count);
-define_therm_throt_sysdev_one_ro(throttle_count);
+define_therm_throt_sysdev_show_func(core_throttle, count);
+define_therm_throt_sysdev_one_ro(core_throttle_count);
+
+define_therm_throt_sysdev_show_func(core_power_limit, count);
+define_therm_throt_sysdev_one_ro(core_power_limit_count);
+
+define_therm_throt_sysdev_show_func(package_throttle, count);
+define_therm_throt_sysdev_one_ro(package_throttle_count);
+
+define_therm_throt_sysdev_show_func(package_power_limit, count);
+define_therm_throt_sysdev_one_ro(package_power_limit_count);
 
 static struct attribute *thermal_throttle_attrs[] = {
-        &attr_throttle_count.attr,
+        &attr_core_throttle_count.attr,
         NULL
 };
 
-static struct attribute_group thermal_throttle_attr_group = {
+static struct attribute_group thermal_attr_group = {
         .attrs  = thermal_throttle_attrs,
         .name   = "thermal_throttle"
 };
 #endif /* CONFIG_SYSFS */
 
+#define CORE_LEVEL      0
+#define PACKAGE_LEVEL   1
+
 /***
  * therm_throt_process - Process thermal throttling event from interrupt
  * @curr: Whether the condition is current or not (boolean), since the
@@ -106,39 +130,70 @@ static struct attribute_group thermal_throttle_attr_group = {
  *          1 : Event should be logged further, and a message has been
  *              printed to the syslog.
  */
-static int therm_throt_process(bool is_throttled)
+static int therm_throt_process(bool new_event, int event, int level)
 {
-        struct thermal_state *state;
-        unsigned int this_cpu;
-        bool was_throttled;
+        struct _thermal_state *state;
+        unsigned int this_cpu = smp_processor_id();
+        bool old_event;
         u64 now;
+        struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
 
-        this_cpu = smp_processor_id();
         now = get_jiffies_64();
-        state = &per_cpu(thermal_state, this_cpu);
+        if (level == CORE_LEVEL) {
+                if (event == THERMAL_THROTTLING_EVENT)
+                        state = &pstate->core_throttle;
+                else if (event == POWER_LIMIT_EVENT)
+                        state = &pstate->core_power_limit;
+                else
+                         return 0;
+        } else if (level == PACKAGE_LEVEL) {
+                if (event == THERMAL_THROTTLING_EVENT)
+                        state = &pstate->package_throttle;
+                else if (event == POWER_LIMIT_EVENT)
+                        state = &pstate->package_power_limit;
+                else
+                        return 0;
+        } else
+                return 0;
 
-        was_throttled = state->is_throttled;
-        state->is_throttled = is_throttled;
+        old_event = state->new_event;
+        state->new_event = new_event;
 
-        if (is_throttled)
-                state->throttle_count++;
+        if (new_event)
+                state->count++;
 
         if (time_before64(now, state->next_check) &&
-                        state->throttle_count != state->last_throttle_count)
+                        state->count != state->last_count)
                 return 0;
 
         state->next_check = now + CHECK_INTERVAL;
-        state->last_throttle_count = state->throttle_count;
+        state->last_count = state->count;
 
         /* if we just entered the thermal event */
-        if (is_throttled) {
-                printk(KERN_CRIT "CPU%d: Temperature above threshold, cpu clock throttled (total events = %lu)\n", this_cpu, state->throttle_count);
+        if (new_event) {
+                if (event == THERMAL_THROTTLING_EVENT)
+                        printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
+                                this_cpu,
+                                level == CORE_LEVEL ? "Core" : "Package",
+                                state->count);
+                else
+                        printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n",
+                                this_cpu,
+                                level == CORE_LEVEL ? "Core" : "Package",
+                                state->count);
 
                 add_taint(TAINT_MACHINE_CHECK);
                 return 1;
         }
-        if (was_throttled) {
-                printk(KERN_INFO "CPU%d: Temperature/speed normal\n", this_cpu);
+        if (old_event) {
+                if (event == THERMAL_THROTTLING_EVENT)
+                        printk(KERN_INFO "CPU%d: %s temperature/speed normal\n",
+                                this_cpu,
+                                level == CORE_LEVEL ? "Core" : "Package");
+                else
+                        printk(KERN_INFO "CPU%d: %s power limit normal\n",
+                                this_cpu,
+                                level == CORE_LEVEL ? "Core" : "Package");
                 return 1;
         }
 
@@ -149,13 +204,32 @@ static int therm_throt_process(bool is_throttled)
 /* Add/Remove thermal_throttle interface for CPU device: */
 static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev)
 {
-        return sysfs_create_group(&sys_dev->kobj,
-                                  &thermal_throttle_attr_group);
+        int err;
+        struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
+
+        err = sysfs_create_group(&sys_dev->kobj, &thermal_attr_group);
+        if (err)
+                return err;
+
+        if (cpu_has(c, X86_FEATURE_PLN))
+                err = sysfs_add_file_to_group(&sys_dev->kobj,
+                                              &attr_core_power_limit_count.attr,
+                                              thermal_attr_group.name);
+        if (cpu_has(c, X86_FEATURE_PTS))
+                err = sysfs_add_file_to_group(&sys_dev->kobj,
+                                              &attr_package_throttle_count.attr,
+                                              thermal_attr_group.name);
+                if (cpu_has(c, X86_FEATURE_PLN))
+                        err = sysfs_add_file_to_group(&sys_dev->kobj,
+                                        &attr_package_power_limit_count.attr,
+                                        thermal_attr_group.name);
+
+        return err;
 }
 
 static __cpuinit void thermal_throttle_remove_dev(struct sys_device *sys_dev)
 {
-        sysfs_remove_group(&sys_dev->kobj, &thermal_throttle_attr_group);
+        sysfs_remove_group(&sys_dev->kobj, &thermal_attr_group);
 }
 
 /* Mutex protecting device creation against CPU hotplug: */
@@ -226,14 +300,50 @@ device_initcall(thermal_throttle_init_device);
 
 #endif /* CONFIG_SYSFS */
 
+/*
+ * Set up the most two significant bit to notify mce log that this thermal
+ * event type.
+ * This is a temp solution. May be changed in the future with mce log
+ * infrasture.
+ */
+#define CORE_THROTTLED          (0)
+#define CORE_POWER_LIMIT        ((__u64)1 << 62)
+#define PACKAGE_THROTTLED       ((__u64)2 << 62)
+#define PACKAGE_POWER_LIMIT     ((__u64)3 << 62)
+
 /* Thermal transition interrupt handler */
 static void intel_thermal_interrupt(void)
 {
         __u64 msr_val;
+        struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
 
         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
-        if (therm_throt_process((msr_val & THERM_STATUS_PROCHOT) != 0))
-                mce_log_therm_throt_event(msr_val);
+
+        if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
+                                THERMAL_THROTTLING_EVENT,
+                                CORE_LEVEL) != 0)
+                mce_log_therm_throt_event(CORE_THROTTLED | msr_val);
+
+        if (cpu_has(c, X86_FEATURE_PLN))
+                if (therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
+                                        POWER_LIMIT_EVENT,
+                                        CORE_LEVEL) != 0)
+                        mce_log_therm_throt_event(CORE_POWER_LIMIT | msr_val);
+
+        if (cpu_has(c, X86_FEATURE_PTS)) {
+                rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
+                if (therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
+                                        THERMAL_THROTTLING_EVENT,
+                                        PACKAGE_LEVEL) != 0)
+                        mce_log_therm_throt_event(PACKAGE_THROTTLED | msr_val);
+                if (cpu_has(c, X86_FEATURE_PLN))
+                        if (therm_throt_process(msr_val &
+                                        PACKAGE_THERM_STATUS_POWER_LIMIT,
+                                        POWER_LIMIT_EVENT,
+                                        PACKAGE_LEVEL) != 0)
+                                mce_log_therm_throt_event(PACKAGE_POWER_LIMIT
+                                                          | msr_val);
+        }
 }
 
 static void unexpected_thermal_interrupt(void)
@@ -335,8 +445,26 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
         apic_write(APIC_LVTTHMR, h);
 
         rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
-        wrmsr(MSR_IA32_THERM_INTERRUPT,
-                l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
+        if (cpu_has(c, X86_FEATURE_PLN))
+                wrmsr(MSR_IA32_THERM_INTERRUPT,
+                      l | (THERM_INT_LOW_ENABLE
+                        | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
+        else
+                wrmsr(MSR_IA32_THERM_INTERRUPT,
+                      l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
+
+        if (cpu_has(c, X86_FEATURE_PTS)) {
+                rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
+                if (cpu_has(c, X86_FEATURE_PLN))
+                        wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
+                              l | (PACKAGE_THERM_INT_LOW_ENABLE
+                                | PACKAGE_THERM_INT_HIGH_ENABLE
+                                | PACKAGE_THERM_INT_PLN_ENABLE), h);
+                else
+                        wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
+                              l | (PACKAGE_THERM_INT_LOW_ENABLE
+                                | PACKAGE_THERM_INT_HIGH_ENABLE), h);
+        }
 
         smp_thermal_vector = intel_thermal_interrupt;
 
diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
index 16f41bbe46b6..d944bf6c50e9 100644
--- a/arch/x86/kernel/cpu/mshyperv.c
+++ b/arch/x86/kernel/cpu/mshyperv.c
@@ -18,6 +18,7 @@
 #include <asm/mshyperv.h>
 
 struct ms_hyperv_info ms_hyperv;
+EXPORT_SYMBOL_GPL(ms_hyperv);
 
 static bool __init ms_hyperv_platform(void)
 {
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index fd31a441c61c..7d28d7d03885 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -433,13 +433,12 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
 {
         unsigned int mask_lo, mask_hi, base_lo, base_hi;
         unsigned int tmp, hi;
-        int cpu;
 
         /*
          * get_mtrr doesn't need to update mtrr_state, also it could be called
          * from any cpu, so try to print it out directly.
          */
-        cpu = get_cpu();
+        get_cpu();
 
         rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
 
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 5db5b7d65a18..f2da20fda02d 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -220,6 +220,7 @@ struct x86_pmu {
                                                  struct perf_event *event);
         struct event_constraint *event_constraints;
         void            (*quirks)(void);
+        int             perfctr_second_write;
 
         int             (*cpu_prepare)(int cpu);
         void            (*cpu_starting)(int cpu);
@@ -295,10 +296,10 @@ x86_perf_event_update(struct perf_event *event)
          * count to the generic event atomically:
          */
 again:
-        prev_raw_count = atomic64_read(&hwc->prev_count);
+        prev_raw_count = local64_read(&hwc->prev_count);
         rdmsrl(hwc->event_base + idx, new_raw_count);
 
-        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
                                         new_raw_count) != prev_raw_count)
                 goto again;
 
@@ -313,8 +314,8 @@ again:
         delta = (new_raw_count << shift) - (prev_raw_count << shift);
         delta >>= shift;
 
-        atomic64_add(delta, &event->count);
-        atomic64_sub(delta, &hwc->period_left);
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
 
         return new_raw_count;
 }
@@ -438,7 +439,7 @@ static int x86_setup_perfctr(struct perf_event *event)
         if (!hwc->sample_period) {
                 hwc->sample_period = x86_pmu.max_period;
                 hwc->last_period = hwc->sample_period;
-                atomic64_set(&hwc->period_left, hwc->sample_period);
+                local64_set(&hwc->period_left, hwc->sample_period);
         } else {
                 /*
                  * If we have a PMU initialized but no APIC
@@ -885,7 +886,7 @@ static int
 x86_perf_event_set_period(struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
-        s64 left = atomic64_read(&hwc->period_left);
+        s64 left = local64_read(&hwc->period_left);
         s64 period = hwc->sample_period;
         int ret = 0, idx = hwc->idx;
 
@@ -897,14 +898,14 @@ x86_perf_event_set_period(struct perf_event *event)
          */
         if (unlikely(left <= -period)) {
                 left = period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
 
         if (unlikely(left <= 0)) {
                 left += period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
@@ -923,10 +924,19 @@ x86_perf_event_set_period(struct perf_event *event)
          * The hw event starts counting from this event offset,
          * mark it to be able to extra future deltas:
          */
-        atomic64_set(&hwc->prev_count, (u64)-left);
+        local64_set(&hwc->prev_count, (u64)-left);
 
-        wrmsrl(hwc->event_base + idx,
+        wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
+
+        /*
+         * Due to erratum on certan cpu we need
+         * a second write to be sure the register
+         * is updated properly
+         */
+        if (x86_pmu.perfctr_second_write) {
+                wrmsrl(hwc->event_base + idx,
                         (u64)(-left) & x86_pmu.cntval_mask);
+        }
 
         perf_event_update_userpage(event);
 
@@ -969,7 +979,7 @@ static int x86_pmu_enable(struct perf_event *event)
          * skip the schedulability test here, it will be peformed
          * at commit time(->commit_txn) as a whole
          */
-        if (cpuc->group_flag & PERF_EVENT_TXN_STARTED)
+        if (cpuc->group_flag & PERF_EVENT_TXN)
                 goto out;
 
         ret = x86_pmu.schedule_events(cpuc, n, assign);
@@ -1096,7 +1106,7 @@ static void x86_pmu_disable(struct perf_event *event)
          * The events never got scheduled and ->cancel_txn will truncate
          * the event_list.
          */
-        if (cpuc->group_flag & PERF_EVENT_TXN_STARTED)
+        if (cpuc->group_flag & PERF_EVENT_TXN)
                 return;
 
         x86_pmu_stop(event);
@@ -1388,7 +1398,7 @@ static void x86_pmu_start_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        cpuc->group_flag |= PERF_EVENT_TXN_STARTED;
+        cpuc->group_flag |= PERF_EVENT_TXN;
         cpuc->n_txn = 0;
 }
 
@@ -1401,7 +1411,7 @@ static void x86_pmu_cancel_txn(const struct pmu *pmu)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        cpuc->group_flag &= ~PERF_EVENT_TXN_STARTED;
+        cpuc->group_flag &= ~PERF_EVENT_TXN;
         /*
          * Truncate the collected events.
          */
@@ -1435,11 +1445,7 @@ static int x86_pmu_commit_txn(const struct pmu *pmu)
          */
         memcpy(cpuc->assign, assign, n*sizeof(int));
 
-        /*
-         * Clear out the txn count so that ->cancel_txn() which gets
-         * run after ->commit_txn() doesn't undo things.
-         */
-        cpuc->n_txn = 0;
+        cpuc->group_flag &= ~PERF_EVENT_TXN;
 
         return 0;
 }
@@ -1607,8 +1613,6 @@ static const struct stacktrace_ops backtrace_ops = {
         .walk_stack             = print_context_stack_bp,
 };
 
-#include "../dumpstack.h"
-
 static void
 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
 {
@@ -1730,22 +1734,6 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
         return entry;
 }
 
-void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
-{
-        regs->ip = ip;
-        /*
-         * perf_arch_fetch_caller_regs adds another call, we need to increment
-         * the skip level
-         */
-        regs->bp = rewind_frame_pointer(skip + 1);
-        regs->cs = __KERNEL_CS;
-        /*
-         * We abuse bit 3 to pass exact information, see perf_misc_flags
-         * and the comment with PERF_EFLAGS_EXACT.
-         */
-        regs->flags = 0;
-}
-
 unsigned long perf_instruction_pointer(struct pt_regs *regs)
 {
         unsigned long ip;
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index ae85d69644d1..107711bf0ee8 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -21,22 +21,36 @@ struct p4_event_bind {
         char cntr[2][P4_CNTR_LIMIT];            /* counter index (offset), -1 on abscence */
 };
 
-struct p4_cache_event_bind {
+struct p4_pebs_bind {
         unsigned int metric_pebs;
         unsigned int metric_vert;
 };
 
-#define P4_GEN_CACHE_EVENT_BIND(name)           \
-        [P4_CACHE__##name] = {                  \
-                .metric_pebs = P4_PEBS__##name, \
-                .metric_vert = P4_VERT__##name, \
+/* it sets P4_PEBS_ENABLE_UOP_TAG as well */
+#define P4_GEN_PEBS_BIND(name, pebs, vert)                      \
+        [P4_PEBS_METRIC__##name] = {                            \
+                .metric_pebs = pebs | P4_PEBS_ENABLE_UOP_TAG,   \
+                .metric_vert = vert,                            \
         }
 
-static struct p4_cache_event_bind p4_cache_event_bind_map[] = {
-        P4_GEN_CACHE_EVENT_BIND(1stl_cache_load_miss_retired),
-        P4_GEN_CACHE_EVENT_BIND(2ndl_cache_load_miss_retired),
-        P4_GEN_CACHE_EVENT_BIND(dtlb_load_miss_retired),
-        P4_GEN_CACHE_EVENT_BIND(dtlb_store_miss_retired),
+/*
+ * note we have P4_PEBS_ENABLE_UOP_TAG always set here
+ *
+ * it's needed for mapping P4_PEBS_CONFIG_METRIC_MASK bits of
+ * event configuration to find out which values are to be
+ * written into MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT
+ * resgisters
+ */
+static struct p4_pebs_bind p4_pebs_bind_map[] = {
+        P4_GEN_PEBS_BIND(1stl_cache_load_miss_retired,  0x0000001, 0x0000001),
+        P4_GEN_PEBS_BIND(2ndl_cache_load_miss_retired,  0x0000002, 0x0000001),
+        P4_GEN_PEBS_BIND(dtlb_load_miss_retired,        0x0000004, 0x0000001),
+        P4_GEN_PEBS_BIND(dtlb_store_miss_retired,       0x0000004, 0x0000002),
+        P4_GEN_PEBS_BIND(dtlb_all_miss_retired,         0x0000004, 0x0000003),
+        P4_GEN_PEBS_BIND(tagged_mispred_branch,         0x0018000, 0x0000010),
+        P4_GEN_PEBS_BIND(mob_load_replay_retired,       0x0000200, 0x0000001),
+        P4_GEN_PEBS_BIND(split_load_retired,            0x0000400, 0x0000001),
+        P4_GEN_PEBS_BIND(split_store_retired,           0x0000400, 0x0000002),
 };
 
 /*
@@ -281,10 +295,10 @@ static struct p4_event_bind p4_event_bind_map[] = {
         },
 };
 
-#define P4_GEN_CACHE_EVENT(event, bit, cache_event)                       \
+#define P4_GEN_CACHE_EVENT(event, bit, metric)                            \
         p4_config_pack_escr(P4_ESCR_EVENT(event)                        | \
                             P4_ESCR_EMASK_BIT(event, bit))              | \
-        p4_config_pack_cccr(cache_event                                 | \
+        p4_config_pack_cccr(metric                                      | \
                             P4_CCCR_ESEL(P4_OPCODE_ESEL(P4_OPCODE(event))))
 
 static __initconst const u64 p4_hw_cache_event_ids
@@ -296,34 +310,34 @@ static __initconst const u64 p4_hw_cache_event_ids
         [ C(OP_READ) ] = {
                 [ C(RESULT_ACCESS) ] = 0x0,
                 [ C(RESULT_MISS)   ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
-                                                P4_CACHE__1stl_cache_load_miss_retired),
+                                                P4_PEBS_METRIC__1stl_cache_load_miss_retired),
         },
  },
  [ C(LL  ) ] = {
         [ C(OP_READ) ] = {
                 [ C(RESULT_ACCESS) ] = 0x0,
                 [ C(RESULT_MISS)   ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
-                                                P4_CACHE__2ndl_cache_load_miss_retired),
+                                                P4_PEBS_METRIC__2ndl_cache_load_miss_retired),
         },
 },
  [ C(DTLB) ] = {
         [ C(OP_READ) ] = {
                 [ C(RESULT_ACCESS) ] = 0x0,
                 [ C(RESULT_MISS)   ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
-                                                P4_CACHE__dtlb_load_miss_retired),
+                                                P4_PEBS_METRIC__dtlb_load_miss_retired),
         },
         [ C(OP_WRITE) ] = {
                 [ C(RESULT_ACCESS) ] = 0x0,
                 [ C(RESULT_MISS)   ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
-                                                P4_CACHE__dtlb_store_miss_retired),
+                                                P4_PEBS_METRIC__dtlb_store_miss_retired),
         },
  },
  [ C(ITLB) ] = {
         [ C(OP_READ) ] = {
                 [ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT,
-                                                P4_CACHE__itlb_reference_hit),
+                                                P4_PEBS_METRIC__none),
                 [ C(RESULT_MISS)   ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,
-                                                P4_CACHE__itlb_reference_miss),
+                                                P4_PEBS_METRIC__none),
         },
         [ C(OP_WRITE) ] = {
                 [ C(RESULT_ACCESS) ] = -1,
@@ -414,11 +428,37 @@ static u64 p4_pmu_event_map(int hw_event)
         return config;
 }
 
+static int p4_validate_raw_event(struct perf_event *event)
+{
+        unsigned int v;
+
+        /* user data may have out-of-bound event index */
+        v = p4_config_unpack_event(event->attr.config);
+        if (v >= ARRAY_SIZE(p4_event_bind_map)) {
+                pr_warning("P4 PMU: Unknown event code: %d\n", v);
+                return -EINVAL;
+        }
+
+        /*
+         * it may have some screwed PEBS bits
+         */
+        if (p4_config_pebs_has(event->attr.config, P4_PEBS_CONFIG_ENABLE)) {
+                pr_warning("P4 PMU: PEBS are not supported yet\n");
+                return -EINVAL;
+        }
+        v = p4_config_unpack_metric(event->attr.config);
+        if (v >= ARRAY_SIZE(p4_pebs_bind_map)) {
+                pr_warning("P4 PMU: Unknown metric code: %d\n", v);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
 static int p4_hw_config(struct perf_event *event)
 {
         int cpu = get_cpu();
         int rc = 0;
-        unsigned int evnt;
         u32 escr, cccr;
 
         /*
@@ -438,12 +478,9 @@ static int p4_hw_config(struct perf_event *event)
 
         if (event->attr.type == PERF_TYPE_RAW) {
 
-                /* user data may have out-of-bound event index */
-                evnt = p4_config_unpack_event(event->attr.config);
-                if (evnt >= ARRAY_SIZE(p4_event_bind_map)) {
-                        rc = -EINVAL;
+                rc = p4_validate_raw_event(event);
+                if (rc)
                         goto out;
-                }
 
                 /*
                  * We don't control raw events so it's up to the caller
@@ -451,12 +488,15 @@ static int p4_hw_config(struct perf_event *event)
                  * on HT machine but allow HT-compatible specifics to be
                  * passed on)
                  *
+                 * Note that for RAW events we allow user to use P4_CCCR_RESERVED
+                 * bits since we keep additional info here (for cache events and etc)
+                 *
                  * XXX: HT wide things should check perf_paranoid_cpu() &&
                  *      CAP_SYS_ADMIN
                  */
                 event->hw.config |= event->attr.config &
                         (p4_config_pack_escr(P4_ESCR_MASK_HT) |
-                         p4_config_pack_cccr(P4_CCCR_MASK_HT));
+                         p4_config_pack_cccr(P4_CCCR_MASK_HT | P4_CCCR_RESERVED));
         }
 
         rc = x86_setup_perfctr(event);
@@ -482,6 +522,29 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
         return overflow;
 }
 
+static void p4_pmu_disable_pebs(void)
+{
+        /*
+         * FIXME
+         *
+         * It's still allowed that two threads setup same cache
+         * events so we can't simply clear metrics until we knew
+         * noone is depending on us, so we need kind of counter
+         * for "ReplayEvent" users.
+         *
+         * What is more complex -- RAW events, if user (for some
+         * reason) will pass some cache event metric with improper
+         * event opcode -- it's fine from hardware point of view
+         * but completely nonsence from "meaning" of such action.
+         *
+         * So at moment let leave metrics turned on forever -- it's
+         * ok for now but need to be revisited!
+         *
+         * (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)0);
+         * (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
+         */
+}
+
 static inline void p4_pmu_disable_event(struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
@@ -507,6 +570,26 @@ static void p4_pmu_disable_all(void)
                         continue;
                 p4_pmu_disable_event(event);
         }
+
+        p4_pmu_disable_pebs();
+}
+
+/* configuration must be valid */
+static void p4_pmu_enable_pebs(u64 config)
+{
+        struct p4_pebs_bind *bind;
+        unsigned int idx;
+
+        BUILD_BUG_ON(P4_PEBS_METRIC__max > P4_PEBS_CONFIG_METRIC_MASK);
+
+        idx = p4_config_unpack_metric(config);
+        if (idx == P4_PEBS_METRIC__none)
+                return;
+
+        bind = &p4_pebs_bind_map[idx];
+
+        (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE,     (u64)bind->metric_pebs);
+        (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT,  (u64)bind->metric_vert);
 }
 
 static void p4_pmu_enable_event(struct perf_event *event)
@@ -515,9 +598,7 @@ static void p4_pmu_enable_event(struct perf_event *event)
         int thread = p4_ht_config_thread(hwc->config);
         u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config));
         unsigned int idx = p4_config_unpack_event(hwc->config);
-        unsigned int idx_cache = p4_config_unpack_cache_event(hwc->config);
         struct p4_event_bind *bind;
-        struct p4_cache_event_bind *bind_cache;
         u64 escr_addr, cccr;
 
         bind = &p4_event_bind_map[idx];
@@ -537,16 +618,10 @@ static void p4_pmu_enable_event(struct perf_event *event)
         cccr = p4_config_unpack_cccr(hwc->config);
 
         /*
-         * it could be Cache event so that we need to
-         * set metrics into additional MSRs
+         * it could be Cache event so we need to write metrics
+         * into additional MSRs
          */
-        BUILD_BUG_ON(P4_CACHE__MAX > P4_CCCR_CACHE_OPS_MASK);
-        if (idx_cache > P4_CACHE__NONE &&
-                idx_cache < ARRAY_SIZE(p4_cache_event_bind_map)) {
-                bind_cache = &p4_cache_event_bind_map[idx_cache];
-                (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)bind_cache->metric_pebs);
-                (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)bind_cache->metric_vert);
-        }
+        p4_pmu_enable_pebs(hwc->config);
 
         (void)checking_wrmsrl(escr_addr, escr_conf);
         (void)checking_wrmsrl(hwc->config_base + hwc->idx,
@@ -829,6 +904,15 @@ static __initconst const struct x86_pmu p4_pmu = {
         .max_period             = (1ULL << 39) - 1,
         .hw_config              = p4_hw_config,
         .schedule_events        = p4_pmu_schedule_events,
+        /*
+         * This handles erratum N15 in intel doc 249199-029,
+         * the counter may not be updated correctly on write
+         * so we need a second write operation to do the trick
+         * (the official workaround didn't work)
+         *
+         * the former idea is taken from OProfile code
+         */
+        .perfctr_second_write   = 1,
 };
 
 static __init int p4_pmu_init(void)
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
new file mode 100644
index 000000000000..34b4dad6f0b8
--- /dev/null
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -0,0 +1,63 @@
+/*
+ *      Routines to indentify additional cpu features that are scattered in
+ *      cpuid space.
+ */
+#include <linux/cpu.h>
+
+#include <asm/pat.h>
+#include <asm/processor.h>
+
+#include <asm/apic.h>
+
+struct cpuid_bit {
+        u16 feature;
+        u8 reg;
+        u8 bit;
+        u32 level;
+        u32 sub_leaf;
+};
+
+enum cpuid_regs {
+        CR_EAX = 0,
+        CR_ECX,
+        CR_EDX,
+        CR_EBX
+};
+
+void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
+{
+        u32 max_level;
+        u32 regs[4];
+        const struct cpuid_bit *cb;
+
+        static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
+                { X86_FEATURE_IDA,              CR_EAX, 1, 0x00000006, 0 },
+                { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006, 0 },
+                { X86_FEATURE_PLN,              CR_EAX, 4, 0x00000006, 0 },
+                { X86_FEATURE_PTS,              CR_EAX, 6, 0x00000006, 0 },
+                { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
+                { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
+                { X86_FEATURE_XSAVEOPT,         CR_EAX, 0, 0x0000000d, 1 },
+                { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007, 0 },
+                { X86_FEATURE_NPT,              CR_EDX, 0, 0x8000000a, 0 },
+                { X86_FEATURE_LBRV,             CR_EDX, 1, 0x8000000a, 0 },
+                { X86_FEATURE_SVML,             CR_EDX, 2, 0x8000000a, 0 },
+                { X86_FEATURE_NRIPS,            CR_EDX, 3, 0x8000000a, 0 },
+                { 0, 0, 0, 0, 0 }
+        };
+
+        for (cb = cpuid_bits; cb->feature; cb++) {
+
+                /* Verify that the level is valid */
+                max_level = cpuid_eax(cb->level & 0xffff0000);
+                if (max_level < cb->level ||
+                    max_level > (cb->level | 0xffff))
+                        continue;
+
+                cpuid_count(cb->level, cb->sub_leaf, &regs[CR_EAX],
+                            &regs[CR_EBX], &regs[CR_ECX], &regs[CR_EDX]);
+
+                if (regs[cb->reg] & (1 << cb->bit))
+                        set_cpu_cap(c, cb->feature);
+        }
+}
diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/topology.c
index 10fa5684a662..4397e987a1cf 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/topology.c
@@ -1,62 +1,14 @@
 /*
- *      Routines to indentify additional cpu features that are scattered in
- *      cpuid space.
+ * Check for extended topology enumeration cpuid leaf 0xb and if it
+ * exists, use it for populating initial_apicid and cpu topology
+ * detection.
  */
-#include <linux/cpu.h>
 
+#include <linux/cpu.h>
+#include <asm/apic.h>
 #include <asm/pat.h>
 #include <asm/processor.h>
 
-#include <asm/apic.h>
-
-struct cpuid_bit {
-        u16 feature;
-        u8 reg;
-        u8 bit;
-        u32 level;
-};
-
-enum cpuid_regs {
-        CR_EAX = 0,
-        CR_ECX,
-        CR_EDX,
-        CR_EBX
-};
-
-void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
-{
-        u32 max_level;
-        u32 regs[4];
-        const struct cpuid_bit *cb;
-
-        static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
-                { X86_FEATURE_IDA,              CR_EAX, 1, 0x00000006 },
-                { X86_FEATURE_ARAT,             CR_EAX, 2, 0x00000006 },
-                { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006 },
-                { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007 },
-                { X86_FEATURE_NPT,              CR_EDX, 0, 0x8000000a },
-                { X86_FEATURE_LBRV,             CR_EDX, 1, 0x8000000a },
-                { X86_FEATURE_SVML,             CR_EDX, 2, 0x8000000a },
-                { X86_FEATURE_NRIPS,            CR_EDX, 3, 0x8000000a },
-                { 0, 0, 0, 0 }
-        };
-
-        for (cb = cpuid_bits; cb->feature; cb++) {
-
-                /* Verify that the level is valid */
-                max_level = cpuid_eax(cb->level & 0xffff0000);
-                if (max_level < cb->level ||
-                    max_level > (cb->level | 0xffff))
-                        continue;
-
-                cpuid(cb->level, &regs[CR_EAX], &regs[CR_EBX],
-                        &regs[CR_ECX], &regs[CR_EDX]);
-
-                if (regs[cb->reg] & (1 << cb->bit))
-                        set_cpu_cap(c, cb->feature);
-        }
-}
-
 /* leaf 0xb SMT level */
 #define SMT_LEVEL       0
 
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index c89a386930b7..6e8752c1bd52 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -18,7 +18,6 @@
 
 #include <asm/stacktrace.h>
 
-#include "dumpstack.h"
 
 int panic_on_unrecovered_nmi;
 int panic_on_io_nmi;
diff --git a/arch/x86/kernel/dumpstack.h b/arch/x86/kernel/dumpstack.h
deleted file mode 100644
index e1a93be4fd44..000000000000
--- a/arch/x86/kernel/dumpstack.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *  Copyright (C) 1991, 1992  Linus Torvalds
- *  Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
- */
-
-#ifndef DUMPSTACK_H
-#define DUMPSTACK_H
-
-#ifdef CONFIG_X86_32
-#define STACKSLOTS_PER_LINE 8
-#define get_bp(bp) asm("movl %%ebp, %0" : "=r" (bp) :)
-#else
-#define STACKSLOTS_PER_LINE 4
-#define get_bp(bp) asm("movq %%rbp, %0" : "=r" (bp) :)
-#endif
-
-#include <linux/uaccess.h>
-
-extern void
-show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *stack, unsigned long bp, char *log_lvl);
-
-extern void
-show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *sp, unsigned long bp, char *log_lvl);
-
-extern unsigned int code_bytes;
-
-/* The form of the top of the frame on the stack */
-struct stack_frame {
-        struct stack_frame *next_frame;
-        unsigned long return_address;
-};
-
-struct stack_frame_ia32 {
-    u32 next_frame;
-    u32 return_address;
-};
-
-static inline unsigned long rewind_frame_pointer(int n)
-{
-        struct stack_frame *frame;
-
-        get_bp(frame);
-
-#ifdef CONFIG_FRAME_POINTER
-        while (n--) {
-                if (probe_kernel_address(&frame->next_frame, frame))
-                        break;
-        }
-#endif
-
-        return (unsigned long)frame;
-}
-
-#endif /* DUMPSTACK_H */
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index 11540a189d93..0f6376ffa2d9 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -16,8 +16,6 @@
 
 #include <asm/stacktrace.h>
 
-#include "dumpstack.h"
-
 
 void dump_trace(struct task_struct *task, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp,
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 272c9f1f05f3..57a21f11c791 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -16,7 +16,6 @@
 
 #include <asm/stacktrace.h>
 
-#include "dumpstack.h"
 
 #define N_EXCEPTION_STACKS_END \
                 (N_EXCEPTION_STACKS + DEBUG_STKSZ/EXCEPTION_STKSZ - 2)
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index cd49141cf153..258e93fa2630 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -611,14 +611,14 @@ ldt_ss:
  * compensating for the offset by changing to the ESPFIX segment with
  * a base address that matches for the difference.
  */
+#define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8)
         mov %esp, %edx                  /* load kernel esp */
         mov PT_OLDESP(%esp), %eax       /* load userspace esp */
         mov %dx, %ax                    /* eax: new kernel esp */
         sub %eax, %edx                  /* offset (low word is 0) */
-        PER_CPU(gdt_page, %ebx)
         shr $16, %edx
-        mov %dl, GDT_ENTRY_ESPFIX_SS * 8 + 4(%ebx) /* bits 16..23 */
-        mov %dh, GDT_ENTRY_ESPFIX_SS * 8 + 7(%ebx) /* bits 24..31 */
+        mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
+        mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
         pushl $__ESPFIX_SS
         CFI_ADJUST_CFA_OFFSET 4
         push %eax                       /* new kernel esp */
@@ -791,9 +791,8 @@ ptregs_clone:
  * normal stack and adjusts ESP with the matching offset.
  */
         /* fixup the stack */
-        PER_CPU(gdt_page, %ebx)
-        mov GDT_ENTRY_ESPFIX_SS * 8 + 4(%ebx), %al /* bits 16..23 */
-        mov GDT_ENTRY_ESPFIX_SS * 8 + 7(%ebx), %ah /* bits 24..31 */
+        mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */
+        mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */
         shl $16, %eax
         addl %esp, %eax                 /* the adjusted stack pointer */
         pushl $__KERNEL_DS
@@ -1166,6 +1165,9 @@ ENTRY(xen_failsafe_callback)
 .previous
 ENDPROC(xen_failsafe_callback)
 
+BUILD_INTERRUPT3(xen_hvm_callback_vector, XEN_HVM_EVTCHN_CALLBACK,
+                xen_evtchn_do_upcall)
+
 #endif  /* CONFIG_XEN */
 
 #ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 4db7c4d12ffa..c5ea5cdbe7b3 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1065,6 +1065,7 @@ ENTRY(\sym)
 END(\sym)
 .endm
 
+#define INIT_TSS_IST(x) PER_CPU_VAR(init_tss) + (TSS_ist + ((x) - 1) * 8)
 .macro paranoidzeroentry_ist sym do_sym ist
 ENTRY(\sym)
         INTR_FRAME
@@ -1076,10 +1077,9 @@ ENTRY(\sym)
         TRACE_IRQS_OFF
         movq %rsp,%rdi          /* pt_regs pointer */
         xorl %esi,%esi          /* no error code */
-        PER_CPU(init_tss, %r12)
-        subq $EXCEPTION_STKSZ, TSS_ist + (\ist - 1) * 8(%r12)
+        subq $EXCEPTION_STKSZ, INIT_TSS_IST(\ist)
         call \do_sym
-        addq $EXCEPTION_STKSZ, TSS_ist + (\ist - 1) * 8(%r12)
+        addq $EXCEPTION_STKSZ, INIT_TSS_IST(\ist)
         jmp paranoid_exit       /* %ebx: no swapgs flag */
         CFI_ENDPROC
 END(\sym)
@@ -1329,6 +1329,9 @@ ENTRY(xen_failsafe_callback)
         CFI_ENDPROC
 END(xen_failsafe_callback)
 
+apicinterrupt XEN_HVM_EVTCHN_CALLBACK \
+        xen_hvm_callback_vector xen_evtchn_do_upcall
+
 #endif /* CONFIG_XEN */
 
 /*
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index b2e246037392..784360c0625c 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -20,7 +20,7 @@
 
 static void __init i386_default_early_setup(void)
 {
-        /* Initilize 32bit specific setup functions */
+        /* Initialize 32bit specific setup functions */
         x86_init.resources.probe_roms = probe_roms;
         x86_init.resources.reserve_resources = i386_reserve_resources;
         x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc;
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 3d1e6f16b7a6..239046bd447f 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -234,9 +234,8 @@ ENTRY(secondary_startup_64)
          * init data section till per cpu areas are set up.
          */
         movl    $MSR_GS_BASE,%ecx
-        movq    initial_gs(%rip),%rax
-        movq    %rax,%rdx
-        shrq    $32,%rdx
+        movl    initial_gs(%rip),%eax
+        movl    initial_gs+4(%rip),%edx
         wrmsr   
 
         /* esi is pointer to real mode structure with interesting info.
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index ba390d731175..33dbcc4ec5ff 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -16,7 +16,6 @@
 #include <asm/hpet.h>
 
 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
-#define HPET_SHIFT                      22
 
 /* FSEC = 10^-15
    NSEC = 10^-9 */
@@ -787,7 +786,6 @@ static struct clocksource clocksource_hpet = {
         .rating         = 250,
         .read           = read_hpet,
         .mask           = HPET_MASK,
-        .shift          = HPET_SHIFT,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
         .resume         = hpet_resume_counter,
 #ifdef CONFIG_X86_64
@@ -798,6 +796,7 @@ static struct clocksource clocksource_hpet = {
 static int hpet_clocksource_register(void)
 {
         u64 start, now;
+        u64 hpet_freq;
         cycle_t t1;
 
         /* Start the counter */
@@ -832,9 +831,15 @@ static int hpet_clocksource_register(void)
          *  mult = (hpet_period * 2^shift)/10^6
          *  mult = (hpet_period << shift)/FSEC_PER_NSEC
          */
-        clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
 
-        clocksource_register(&clocksource_hpet);
+        /* Need to convert hpet_period (fsec/cyc) to cyc/sec:
+         *
+         * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc)
+         * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period
+         */
+        hpet_freq = FSEC_PER_NSEC * NSEC_PER_SEC;
+        do_div(hpet_freq, hpet_period);
+        clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 
         return 0;
 }
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index a8f1b803d2fd..a474ec37c32f 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -208,6 +208,9 @@ int arch_bp_generic_fields(int x86_len, int x86_type,
 {
         /* Len */
         switch (x86_len) {
+        case X86_BREAKPOINT_LEN_X:
+                *gen_len = sizeof(long);
+                break;
         case X86_BREAKPOINT_LEN_1:
                 *gen_len = HW_BREAKPOINT_LEN_1;
                 break;
@@ -251,6 +254,29 @@ static int arch_build_bp_info(struct perf_event *bp)
 
         info->address = bp->attr.bp_addr;
 
+        /* Type */
+        switch (bp->attr.bp_type) {
+        case HW_BREAKPOINT_W:
+                info->type = X86_BREAKPOINT_WRITE;
+                break;
+        case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
+                info->type = X86_BREAKPOINT_RW;
+                break;
+        case HW_BREAKPOINT_X:
+                info->type = X86_BREAKPOINT_EXECUTE;
+                /*
+                 * x86 inst breakpoints need to have a specific undefined len.
+                 * But we still need to check userspace is not trying to setup
+                 * an unsupported length, to get a range breakpoint for example.
+                 */
+                if (bp->attr.bp_len == sizeof(long)) {
+                        info->len = X86_BREAKPOINT_LEN_X;
+                        return 0;
+                }
+        default:
+                return -EINVAL;
+        }
+
         /* Len */
         switch (bp->attr.bp_len) {
         case HW_BREAKPOINT_LEN_1:
@@ -271,21 +297,6 @@ static int arch_build_bp_info(struct perf_event *bp)
                 return -EINVAL;
         }
 
-        /* Type */
-        switch (bp->attr.bp_type) {
-        case HW_BREAKPOINT_W:
-                info->type = X86_BREAKPOINT_WRITE;
-                break;
-        case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
-                info->type = X86_BREAKPOINT_RW;
-                break;
-        case HW_BREAKPOINT_X:
-                info->type = X86_BREAKPOINT_EXECUTE;
-                break;
-        default:
-                return -EINVAL;
-        }
-
         return 0;
 }
 /*
@@ -305,6 +316,9 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
         ret = -EINVAL;
 
         switch (info->len) {
+        case X86_BREAKPOINT_LEN_X:
+                align = sizeof(long) -1;
+                break;
         case X86_BREAKPOINT_LEN_1:
                 align = 0;
                 break;
@@ -466,6 +480,13 @@ static int __kprobes hw_breakpoint_handler(struct die_args *args)
 
                 perf_bp_event(bp, args->regs);
 
+                /*
+                 * Set up resume flag to avoid breakpoint recursion when
+                 * returning back to origin.
+                 */
+                if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
+                        args->regs->flags |= X86_EFLAGS_RF;
+
                 rcu_read_unlock();
         }
         /*
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 86cef6b32253..c4444bce8469 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -107,7 +107,7 @@ void __cpuinit fpu_init(void)
 }
 #endif  /* CONFIG_X86_64 */
 
-static void fpu_finit(struct fpu *fpu)
+void fpu_finit(struct fpu *fpu)
 {
 #ifdef CONFIG_X86_32
         if (!HAVE_HWFP) {
@@ -132,6 +132,7 @@ static void fpu_finit(struct fpu *fpu)
                 fp->fos = 0xffff0000u;
         }
 }
+EXPORT_SYMBOL_GPL(fpu_finit);
 
 /*
  * The _current_ task is using the FPU for the first time
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 4f4af75b9482..ef10940e1af0 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -49,55 +49,94 @@
 #include <asm/system.h>
 #include <asm/apic.h>
 
-/**
- *      pt_regs_to_gdb_regs - Convert ptrace regs to GDB regs
- *      @gdb_regs: A pointer to hold the registers in the order GDB wants.
- *      @regs: The &struct pt_regs of the current process.
- *
- *      Convert the pt_regs in @regs into the format for registers that
- *      GDB expects, stored in @gdb_regs.
- */
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
 {
-#ifndef CONFIG_X86_32
-        u32 *gdb_regs32 = (u32 *)gdb_regs;
+#ifdef CONFIG_X86_32
+        { "ax", 4, offsetof(struct pt_regs, ax) },
+        { "cx", 4, offsetof(struct pt_regs, cx) },
+        { "dx", 4, offsetof(struct pt_regs, dx) },
+        { "bx", 4, offsetof(struct pt_regs, bx) },
+        { "sp", 4, offsetof(struct pt_regs, sp) },
+        { "bp", 4, offsetof(struct pt_regs, bp) },
+        { "si", 4, offsetof(struct pt_regs, si) },
+        { "di", 4, offsetof(struct pt_regs, di) },
+        { "ip", 4, offsetof(struct pt_regs, ip) },
+        { "flags", 4, offsetof(struct pt_regs, flags) },
+        { "cs", 4, offsetof(struct pt_regs, cs) },
+        { "ss", 4, offsetof(struct pt_regs, ss) },
+        { "ds", 4, offsetof(struct pt_regs, ds) },
+        { "es", 4, offsetof(struct pt_regs, es) },
+        { "fs", 4, -1 },
+        { "gs", 4, -1 },
+#else
+        { "ax", 8, offsetof(struct pt_regs, ax) },
+        { "bx", 8, offsetof(struct pt_regs, bx) },
+        { "cx", 8, offsetof(struct pt_regs, cx) },
+        { "dx", 8, offsetof(struct pt_regs, dx) },
+        { "si", 8, offsetof(struct pt_regs, dx) },
+        { "di", 8, offsetof(struct pt_regs, di) },
+        { "bp", 8, offsetof(struct pt_regs, bp) },
+        { "sp", 8, offsetof(struct pt_regs, sp) },
+        { "r8", 8, offsetof(struct pt_regs, r8) },
+        { "r9", 8, offsetof(struct pt_regs, r9) },
+        { "r10", 8, offsetof(struct pt_regs, r10) },
+        { "r11", 8, offsetof(struct pt_regs, r11) },
+        { "r12", 8, offsetof(struct pt_regs, r12) },
+        { "r13", 8, offsetof(struct pt_regs, r13) },
+        { "r14", 8, offsetof(struct pt_regs, r14) },
+        { "r15", 8, offsetof(struct pt_regs, r15) },
+        { "ip", 8, offsetof(struct pt_regs, ip) },
+        { "flags", 4, offsetof(struct pt_regs, flags) },
+        { "cs", 4, offsetof(struct pt_regs, cs) },
+        { "ss", 4, offsetof(struct pt_regs, ss) },
 #endif
-        gdb_regs[GDB_AX]        = regs->ax;
-        gdb_regs[GDB_BX]        = regs->bx;
-        gdb_regs[GDB_CX]        = regs->cx;
-        gdb_regs[GDB_DX]        = regs->dx;
-        gdb_regs[GDB_SI]        = regs->si;
-        gdb_regs[GDB_DI]        = regs->di;
-        gdb_regs[GDB_BP]        = regs->bp;
-        gdb_regs[GDB_PC]        = regs->ip;
+};
+
+int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
+{
+        if (
 #ifdef CONFIG_X86_32
-        gdb_regs[GDB_PS]        = regs->flags;
-        gdb_regs[GDB_DS]        = regs->ds;
-        gdb_regs[GDB_ES]        = regs->es;
-        gdb_regs[GDB_CS]        = regs->cs;
-        gdb_regs[GDB_FS]        = 0xFFFF;
-        gdb_regs[GDB_GS]        = 0xFFFF;
-        if (user_mode_vm(regs)) {
-                gdb_regs[GDB_SS] = regs->ss;
-                gdb_regs[GDB_SP] = regs->sp;
-        } else {
-                gdb_regs[GDB_SS] = __KERNEL_DS;
-                gdb_regs[GDB_SP] = kernel_stack_pointer(regs);
+            regno == GDB_SS || regno == GDB_FS || regno == GDB_GS ||
+#endif
+            regno == GDB_SP || regno == GDB_ORIG_AX)
+                return 0;
+
+        if (dbg_reg_def[regno].offset != -1)
+                memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
+                       dbg_reg_def[regno].size);
+        return 0;
+}
+
+char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
+{
+        if (regno == GDB_ORIG_AX) {
+                memcpy(mem, &regs->orig_ax, sizeof(regs->orig_ax));
+                return "orig_ax";
         }
-#else
-        gdb_regs[GDB_R8]        = regs->r8;
-        gdb_regs[GDB_R9]        = regs->r9;
-        gdb_regs[GDB_R10]       = regs->r10;
-        gdb_regs[GDB_R11]       = regs->r11;
-        gdb_regs[GDB_R12]       = regs->r12;
-        gdb_regs[GDB_R13]       = regs->r13;
-        gdb_regs[GDB_R14]       = regs->r14;
-        gdb_regs[GDB_R15]       = regs->r15;
-        gdb_regs32[GDB_PS]      = regs->flags;
-        gdb_regs32[GDB_CS]      = regs->cs;
-        gdb_regs32[GDB_SS]      = regs->ss;
-        gdb_regs[GDB_SP]        = kernel_stack_pointer(regs);
+        if (regno >= DBG_MAX_REG_NUM || regno < 0)
+                return NULL;
+
+        if (dbg_reg_def[regno].offset != -1)
+                memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
+                       dbg_reg_def[regno].size);
+
+        switch (regno) {
+#ifdef CONFIG_X86_32
+        case GDB_SS:
+                if (!user_mode_vm(regs))
+                        *(unsigned long *)mem = __KERNEL_DS;
+                break;
+        case GDB_SP:
+                if (!user_mode_vm(regs))
+                        *(unsigned long *)mem = kernel_stack_pointer(regs);
+                break;
+        case GDB_GS:
+        case GDB_FS:
+                *(unsigned long *)mem = 0xFFFF;
+                break;
 #endif
+        }
+        return dbg_reg_def[regno].name;
 }
 
 /**
@@ -150,54 +189,13 @@ void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
         gdb_regs[GDB_SP]        = p->thread.sp;
 }
 
-/**
- *      gdb_regs_to_pt_regs - Convert GDB regs to ptrace regs.
- *      @gdb_regs: A pointer to hold the registers we've received from GDB.
- *      @regs: A pointer to a &struct pt_regs to hold these values in.
- *
- *      Convert the GDB regs in @gdb_regs into the pt_regs, and store them
- *      in @regs.
- */
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
-#ifndef CONFIG_X86_32
-        u32 *gdb_regs32 = (u32 *)gdb_regs;
-#endif
-        regs->ax                = gdb_regs[GDB_AX];
-        regs->bx                = gdb_regs[GDB_BX];
-        regs->cx                = gdb_regs[GDB_CX];
-        regs->dx                = gdb_regs[GDB_DX];
-        regs->si                = gdb_regs[GDB_SI];
-        regs->di                = gdb_regs[GDB_DI];
-        regs->bp                = gdb_regs[GDB_BP];
-        regs->ip                = gdb_regs[GDB_PC];
-#ifdef CONFIG_X86_32
-        regs->flags             = gdb_regs[GDB_PS];
-        regs->ds                = gdb_regs[GDB_DS];
-        regs->es                = gdb_regs[GDB_ES];
-        regs->cs                = gdb_regs[GDB_CS];
-#else
-        regs->r8                = gdb_regs[GDB_R8];
-        regs->r9                = gdb_regs[GDB_R9];
-        regs->r10               = gdb_regs[GDB_R10];
-        regs->r11               = gdb_regs[GDB_R11];
-        regs->r12               = gdb_regs[GDB_R12];
-        regs->r13               = gdb_regs[GDB_R13];
-        regs->r14               = gdb_regs[GDB_R14];
-        regs->r15               = gdb_regs[GDB_R15];
-        regs->flags             = gdb_regs32[GDB_PS];
-        regs->cs                = gdb_regs32[GDB_CS];
-        regs->ss                = gdb_regs32[GDB_SS];
-#endif
-}
-
 static struct hw_breakpoint {
         unsigned                enabled;
         unsigned long           addr;
         int                     len;
         int                     type;
         struct perf_event       **pev;
-} breakinfo[4];
+} breakinfo[HBP_NUM];
 
 static unsigned long early_dr7;
 
@@ -205,7 +203,7 @@ static void kgdb_correct_hw_break(void)
 {
         int breakno;
 
-        for (breakno = 0; breakno < 4; breakno++) {
+        for (breakno = 0; breakno < HBP_NUM; breakno++) {
                 struct perf_event *bp;
                 struct arch_hw_breakpoint *info;
                 int val;
@@ -292,10 +290,10 @@ kgdb_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype bptype)
 {
         int i;
 
-        for (i = 0; i < 4; i++)
+        for (i = 0; i < HBP_NUM; i++)
                 if (breakinfo[i].addr == addr && breakinfo[i].enabled)
                         break;
-        if (i == 4)
+        if (i == HBP_NUM)
                 return -1;
 
         if (hw_break_release_slot(i)) {
@@ -313,7 +311,7 @@ static void kgdb_remove_all_hw_break(void)
         int cpu = raw_smp_processor_id();
         struct perf_event *bp;
 
-        for (i = 0; i < 4; i++) {
+        for (i = 0; i < HBP_NUM; i++) {
                 if (!breakinfo[i].enabled)
                         continue;
                 bp = *per_cpu_ptr(breakinfo[i].pev, cpu);
@@ -333,10 +331,10 @@ kgdb_set_hw_break(unsigned long addr, int len, enum kgdb_bptype bptype)
 {
         int i;
 
-        for (i = 0; i < 4; i++)
+        for (i = 0; i < HBP_NUM; i++)
                 if (!breakinfo[i].enabled)
                         break;
-        if (i == 4)
+        if (i == HBP_NUM)
                 return -1;
 
         switch (bptype) {
@@ -397,7 +395,7 @@ void kgdb_disable_hw_debug(struct pt_regs *regs)
 
         /* Disable hardware debugging while we are in kgdb: */
         set_debugreg(0UL, 7);
-        for (i = 0; i < 4; i++) {
+        for (i = 0; i < HBP_NUM; i++) {
                 if (!breakinfo[i].enabled)
                         continue;
                 if (dbg_is_early) {
@@ -458,7 +456,6 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
 {
         unsigned long addr;
         char *ptr;
-        int newPC;
 
         switch (remcomInBuffer[0]) {
         case 'c':
@@ -469,8 +466,6 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
                         linux_regs->ip = addr;
         case 'D':
         case 'k':
-                newPC = linux_regs->ip;
-
                 /* clear the trace bit */
                 linux_regs->flags &= ~X86_EFLAGS_TF;
                 atomic_set(&kgdb_cpu_doing_single_step, -1);
@@ -572,7 +567,6 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd)
         return NOTIFY_STOP;
 }
 
-#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
 int kgdb_ll_trap(int cmd, const char *str,
                  struct pt_regs *regs, long err, int trap, int sig)
 {
@@ -590,7 +584,6 @@ int kgdb_ll_trap(int cmd, const char *str,
 
         return __kgdb_notify(&args, cmd);
 }
-#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
 
 static int
 kgdb_notify(struct notifier_block *self, unsigned long cmd, void *ptr)
@@ -625,6 +618,12 @@ int kgdb_arch_init(void)
         return register_die_notifier(&kgdb_notifier);
 }
 
+static void kgdb_hw_overflow_handler(struct perf_event *event, int nmi,
+                struct perf_sample_data *data, struct pt_regs *regs)
+{
+        kgdb_ll_trap(DIE_DEBUG, "debug", regs, 0, 0, SIGTRAP);
+}
+
 void kgdb_arch_late(void)
 {
         int i, cpu;
@@ -641,7 +640,7 @@ void kgdb_arch_late(void)
         attr.bp_len = HW_BREAKPOINT_LEN_1;
         attr.bp_type = HW_BREAKPOINT_W;
         attr.disabled = 1;
-        for (i = 0; i < 4; i++) {
+        for (i = 0; i < HBP_NUM; i++) {
                 if (breakinfo[i].pev)
                         continue;
                 breakinfo[i].pev = register_wide_hw_breakpoint(&attr, NULL);
@@ -655,6 +654,7 @@ void kgdb_arch_late(void)
                 for_each_online_cpu(cpu) {
                         pevent = per_cpu_ptr(breakinfo[i].pev, cpu);
                         pevent[0]->hw.sample_period = 1;
+                        pevent[0]->overflow_handler = kgdb_hw_overflow_handler;
                         if (pevent[0]->destroy != NULL) {
                                 pevent[0]->destroy = NULL;
                                 release_bp_slot(*pevent);
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c
index 675879b65ce6..1bfb6cf4dd55 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes.c
@@ -126,16 +126,22 @@ static void __kprobes synthesize_reljump(void *from, void *to)
 }
 
 /*
- * Check for the REX prefix which can only exist on X86_64
- * X86_32 always returns 0
+ * Skip the prefixes of the instruction.
  */
-static int __kprobes is_REX_prefix(kprobe_opcode_t *insn)
+static kprobe_opcode_t *__kprobes skip_prefixes(kprobe_opcode_t *insn)
 {
+        insn_attr_t attr;
+
+        attr = inat_get_opcode_attribute((insn_byte_t)*insn);
+        while (inat_is_legacy_prefix(attr)) {
+                insn++;
+                attr = inat_get_opcode_attribute((insn_byte_t)*insn);
+        }
 #ifdef CONFIG_X86_64
-        if ((*insn & 0xf0) == 0x40)
-                return 1;
+        if (inat_is_rex_prefix(attr))
+                insn++;
 #endif
-        return 0;
+        return insn;
 }
 
 /*
@@ -272,6 +278,9 @@ static int __kprobes can_probe(unsigned long paddr)
  */
 static int __kprobes is_IF_modifier(kprobe_opcode_t *insn)
 {
+        /* Skip prefixes */
+        insn = skip_prefixes(insn);
+
         switch (*insn) {
         case 0xfa:              /* cli */
         case 0xfb:              /* sti */
@@ -280,13 +289,6 @@ static int __kprobes is_IF_modifier(kprobe_opcode_t *insn)
                 return 1;
         }
 
-        /*
-         * on X86_64, 0x40-0x4f are REX prefixes so we need to look
-         * at the next byte instead.. but of course not recurse infinitely
-         */
-        if (is_REX_prefix(insn))
-                return is_IF_modifier(++insn);
-
         return 0;
 }
 
@@ -803,9 +805,8 @@ static void __kprobes resume_execution(struct kprobe *p,
         unsigned long orig_ip = (unsigned long)p->addr;
         kprobe_opcode_t *insn = p->ainsn.insn;
 
-        /*skip the REX prefix*/
-        if (is_REX_prefix(insn))
-                insn++;
+        /* Skip prefixes */
+        insn = skip_prefixes(insn);
 
         regs->flags &= ~X86_EFLAGS_TF;
         switch (*insn) {
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/kernel/mrst.c
index 5915e0b33303..79ae68154e87 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/kernel/mrst.c
@@ -25,8 +25,34 @@
 #include <asm/i8259.h>
 #include <asm/apb_timer.h>
 
+/*
+ * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
+ * cmdline option x86_mrst_timer can be used to override the configuration
+ * to prefer one or the other.
+ * at runtime, there are basically three timer configurations:
+ * 1. per cpu apbt clock only
+ * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
+ * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
+ *
+ * by default (without cmdline option), platform code first detects cpu type
+ * to see if we are on lincroft or penwell, then set up both lapic or apbt
+ * clocks accordingly.
+ * i.e. by default, medfield uses configuration #2, moorestown uses #1.
+ * config #3 is supported but not recommended on medfield.
+ *
+ * rating and feature summary:
+ * lapic (with C3STOP) --------- 100
+ * apbt (always-on) ------------ 110
+ * lapic (always-on,ARAT) ------ 150
+ */
+
+__cpuinitdata enum mrst_timer_options mrst_timer_options;
+
 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
+enum mrst_cpu_type __mrst_cpu_chip;
+EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
+
 int sfi_mtimer_num;
 
 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
@@ -167,18 +193,6 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
         return 0;
 }
 
-/*
- * the secondary clock in Moorestown can be APBT or LAPIC clock, default to
- * APBT but cmdline option can also override it.
- */
-static void __cpuinit mrst_setup_secondary_clock(void)
-{
-        /* restore default lapic clock if disabled by cmdline */
-        if (disable_apbt_percpu)
-                return setup_secondary_APIC_clock();
-        apbt_setup_secondary_clock();
-}
-
 static unsigned long __init mrst_calibrate_tsc(void)
 {
         unsigned long flags, fast_calibrate;
@@ -195,6 +209,21 @@ static unsigned long __init mrst_calibrate_tsc(void)
 
 void __init mrst_time_init(void)
 {
+        switch (mrst_timer_options) {
+        case MRST_TIMER_APBT_ONLY:
+                break;
+        case MRST_TIMER_LAPIC_APBT:
+                x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
+                x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
+                break;
+        default:
+                if (!boot_cpu_has(X86_FEATURE_ARAT))
+                        break;
+                x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
+                x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
+                return;
+        }
+        /* we need at least one APB timer */
         sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
         pre_init_apic_IRQ0();
         apbt_time_init();
@@ -205,16 +234,21 @@ void __init mrst_rtc_init(void)
         sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
 }
 
-/*
- * if we use per cpu apb timer, the bootclock already setup. if we use lapic
- * timer and one apbt timer for broadcast, we need to set up lapic boot clock.
- */
-static void __init mrst_setup_boot_clock(void)
+void __cpuinit mrst_arch_setup(void)
 {
-        pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
-        if (disable_apbt_percpu)
-                setup_boot_APIC_clock();
-};
+        if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
+                __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
+        else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
+                __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+        else {
+                pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
+                        boot_cpu_data.x86, boot_cpu_data.x86_model);
+                __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+        }
+        pr_debug("Moorestown CPU %s identified\n",
+                (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
+                "Lincroft" : "Penwell");
+}
 
 /* MID systems don't have i8042 controller */
 static int mrst_i8042_detect(void)
@@ -232,11 +266,13 @@ void __init x86_mrst_early_setup(void)
         x86_init.resources.reserve_resources = x86_init_noop;
 
         x86_init.timers.timer_init = mrst_time_init;
-        x86_init.timers.setup_percpu_clockev = mrst_setup_boot_clock;
+        x86_init.timers.setup_percpu_clockev = x86_init_noop;
 
         x86_init.irqs.pre_vector_init = x86_init_noop;
 
-        x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
+        x86_init.oem.arch_setup = mrst_arch_setup;
+
+        x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
 
         x86_platform.calibrate_tsc = mrst_calibrate_tsc;
         x86_platform.i8042_detect = mrst_i8042_detect;
@@ -250,3 +286,26 @@ void __init x86_mrst_early_setup(void)
         x86_init.mpparse.get_smp_config = x86_init_uint_noop;
 
 }
+
+/*
+ * if user does not want to use per CPU apb timer, just give it a lower rating
+ * than local apic timer and skip the late per cpu timer init.
+ */
+static inline int __init setup_x86_mrst_timer(char *arg)
+{
+        if (!arg)
+                return -EINVAL;
+
+        if (strcmp("apbt_only", arg) == 0)
+                mrst_timer_options = MRST_TIMER_APBT_ONLY;
+        else if (strcmp("lapic_and_apbt", arg) == 0)
+                mrst_timer_options = MRST_TIMER_LAPIC_APBT;
+        else {
+                pr_warning("X86 MRST timer option %s not recognised"
+                           " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
+                           arg);
+                return -EINVAL;
+        }
+        return 0;
+}
+__setup("x86_mrst_timer=", setup_x86_mrst_timer);
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index e7e35219b32f..d401f1d2d06e 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -28,6 +28,7 @@ unsigned long idle_nomwait;
 EXPORT_SYMBOL(idle_nomwait);
 
 struct kmem_cache *task_xstate_cachep;
+EXPORT_SYMBOL_GPL(task_xstate_cachep);
 
 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
 {
@@ -371,7 +372,7 @@ static inline int hlt_use_halt(void)
 void default_idle(void)
 {
         if (hlt_use_halt()) {
-                trace_power_start(POWER_CSTATE, 1);
+                trace_power_start(POWER_CSTATE, 1, smp_processor_id());
                 current_thread_info()->status &= ~TS_POLLING;
                 /*
                  * TS_POLLING-cleared state must be visible before we
@@ -441,7 +442,7 @@ EXPORT_SYMBOL_GPL(cpu_idle_wait);
  */
 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 {
-        trace_power_start(POWER_CSTATE, (ax>>4)+1);
+        trace_power_start(POWER_CSTATE, (ax>>4)+1, smp_processor_id());
         if (!need_resched()) {
                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
                         clflush((void *)&current_thread_info()->flags);
@@ -457,7 +458,7 @@ void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 static void mwait_idle(void)
 {
         if (!need_resched()) {
-                trace_power_start(POWER_CSTATE, 1);
+                trace_power_start(POWER_CSTATE, 1, smp_processor_id());
                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
                         clflush((void *)&current_thread_info()->flags);
 
@@ -478,7 +479,7 @@ static void mwait_idle(void)
  */
 static void poll_idle(void)
 {
-        trace_power_start(POWER_CSTATE, 0);
+        trace_power_start(POWER_CSTATE, 0, smp_processor_id());
         local_irq_enable();
         while (!need_resched())
                 cpu_relax();
@@ -525,44 +526,10 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
         return (edx & MWAIT_EDX_C1);
 }
 
-/*
- * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e.
- * For more information see
- * - Erratum #400 for NPT family 0xf and family 0x10 CPUs
- * - Erratum #365 for family 0x11 (not affected because C1e not in use)
- */
-static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
-{
-        u64 val;
-        if (c->x86_vendor != X86_VENDOR_AMD)
-                goto no_c1e_idle;
-
-        /* Family 0x0f models < rev F do not have C1E */
-        if (c->x86 == 0x0F && c->x86_model >= 0x40)
-                return 1;
-
-        if (c->x86 == 0x10) {
-                /*
-                 * check OSVW bit for CPUs that are not affected
-                 * by erratum #400
-                 */
-                if (cpu_has(c, X86_FEATURE_OSVW)) {
-                        rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
-                        if (val >= 2) {
-                                rdmsrl(MSR_AMD64_OSVW_STATUS, val);
-                                if (!(val & BIT(1)))
-                                        goto no_c1e_idle;
-                        }
-                }
-                return 1;
-        }
-
-no_c1e_idle:
-        return 0;
-}
+bool c1e_detected;
+EXPORT_SYMBOL(c1e_detected);
 
 static cpumask_var_t c1e_mask;
-static int c1e_detected;
 
 void c1e_remove_cpu(int cpu)
 {
@@ -584,12 +551,12 @@ static void c1e_idle(void)
                 u32 lo, hi;
 
                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
+
                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
-                        c1e_detected = 1;
+                        c1e_detected = true;
                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
                                 mark_tsc_unstable("TSC halt in AMD C1E");
                         printk(KERN_INFO "System has AMD C1E enabled\n");
-                        set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
                 }
         }
 
@@ -638,7 +605,8 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
                  */
                 printk(KERN_INFO "using mwait in idle threads.\n");
                 pm_idle = mwait_idle;
-        } else if (check_c1e_idle(c)) {
+        } else if (cpu_has_amd_erratum(amd_erratum_400)) {
+                /* E400: APIC timer interrupt does not wake up CPU from C1e */
                 printk(KERN_INFO "using C1E aware idle routine\n");
                 pm_idle = c1e_idle;
         } else
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 8d128783af47..96586c3cbbbf 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -57,6 +57,8 @@
 #include <asm/syscalls.h>
 #include <asm/debugreg.h>
 
+#include <trace/events/power.h>
+
 asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
 
 /*
@@ -111,6 +113,8 @@ void cpu_idle(void)
                         stop_critical_timings();
                         pm_idle();
                         start_critical_timings();
+
+                        trace_power_end(smp_processor_id());
                 }
                 tick_nohz_restart_sched_tick();
                 preempt_enable_no_resched();
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 3c2422a99f1f..3d9ea531ddd1 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -51,6 +51,8 @@
 #include <asm/syscalls.h>
 #include <asm/debugreg.h>
 
+#include <trace/events/power.h>
+
 asmlinkage extern void ret_from_fork(void);
 
 DEFINE_PER_CPU(unsigned long, old_rsp);
@@ -138,6 +140,9 @@ void cpu_idle(void)
                         stop_critical_timings();
                         pm_idle();
                         start_critical_timings();
+
+                        trace_power_end(smp_processor_id());
+
                         /* In many cases the interrupt that ended idle
                            has already called exit_idle. But some idle
                            loops can be woken up without interrupt. */
diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c
index 922eefbb3f6c..b53c525368a7 100644
--- a/arch/x86/kernel/stacktrace.c
+++ b/arch/x86/kernel/stacktrace.c
@@ -23,11 +23,16 @@ static int save_stack_stack(void *data, char *name)
         return 0;
 }
 
-static void save_stack_address(void *data, unsigned long addr, int reliable)
+static void
+__save_stack_address(void *data, unsigned long addr, bool reliable, bool nosched)
 {
         struct stack_trace *trace = data;
+#ifdef CONFIG_FRAME_POINTER
         if (!reliable)
                 return;
+#endif
+        if (nosched && in_sched_functions(addr))
+                return;
         if (trace->skip > 0) {
                 trace->skip--;
                 return;
@@ -36,20 +41,15 @@ static void save_stack_address(void *data, unsigned long addr, int reliable)
                 trace->entries[trace->nr_entries++] = addr;
 }
 
+static void save_stack_address(void *data, unsigned long addr, int reliable)
+{
+        return __save_stack_address(data, addr, reliable, false);
+}
+
 static void
 save_stack_address_nosched(void *data, unsigned long addr, int reliable)
 {
-        struct stack_trace *trace = (struct stack_trace *)data;
-        if (!reliable)
-                return;
-        if (in_sched_functions(addr))
-                return;
-        if (trace->skip > 0) {
-                trace->skip--;
-                return;
-        }
-        if (trace->nr_entries < trace->max_entries)
-                trace->entries[trace->nr_entries++] = addr;
+        return __save_stack_address(data, addr, reliable, true);
 }
 
 static const struct stacktrace_ops save_stack_ops = {
@@ -96,12 +96,13 @@ EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
 
 /* Userspace stacktrace - based on kernel/trace/trace_sysprof.c */
 
-struct stack_frame {
+struct stack_frame_user {
         const void __user       *next_fp;
         unsigned long           ret_addr;
 };
 
-static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
+static int
+copy_stack_frame(const void __user *fp, struct stack_frame_user *frame)
 {
         int ret;
 
@@ -126,7 +127,7 @@ static inline void __save_stack_trace_user(struct stack_trace *trace)
                 trace->entries[trace->nr_entries++] = regs->ip;
 
         while (trace->nr_entries < trace->max_entries) {
-                struct stack_frame frame;
+                struct stack_frame_user frame;
 
                 frame.next_fp = NULL;
                 frame.ret_addr = 0;
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 725ef4d17cd5..60788dee0f8a 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -392,7 +392,13 @@ static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
                 if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT)
                                                                 == NOTIFY_STOP)
                         return;
+
 #ifdef CONFIG_X86_LOCAL_APIC
+                if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
+                                                        == NOTIFY_STOP)
+                        return;
+
+#ifndef CONFIG_LOCKUP_DETECTOR
                 /*
                  * Ok, so this is none of the documented NMI sources,
                  * so it must be the NMI watchdog.
@@ -400,6 +406,7 @@ static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
                 if (nmi_watchdog_tick(regs, reason))
                         return;
                 if (!do_nmi_callback(regs, cpu))
+#endif /* !CONFIG_LOCKUP_DETECTOR */
                         unknown_nmi_error(reason, regs);
 #else
                 unknown_nmi_error(reason, regs);
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 9faf91ae1841..ce8e50239332 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -751,7 +751,6 @@ static struct clocksource clocksource_tsc = {
         .read                   = read_tsc,
         .resume                 = resume_tsc,
         .mask                   = CLOCKSOURCE_MASK(64),
-        .shift                  = 22,
         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
                                   CLOCK_SOURCE_MUST_VERIFY,
 #ifdef CONFIG_X86_64
@@ -845,8 +844,6 @@ __cpuinit int unsynchronized_tsc(void)
 
 static void __init init_tsc_clocksource(void)
 {
-        clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
-                        clocksource_tsc.shift);
         if (tsc_clocksource_reliable)
                 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
         /* lower the rating if we already know its unstable: */
@@ -854,7 +851,7 @@ static void __init init_tsc_clocksource(void)
                 clocksource_tsc.rating = 0;
                 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
         }
-        clocksource_register(&clocksource_tsc);
+        clocksource_register_khz(&clocksource_tsc, tsc_khz);
 }
 
 #ifdef CONFIG_X86_64
diff --git a/arch/x86/kernel/verify_cpu_64.S b/arch/x86/kernel/verify_cpu_64.S
index 45b6f8a975a1..56a8c2a867d9 100644
--- a/arch/x86/kernel/verify_cpu_64.S
+++ b/arch/x86/kernel/verify_cpu_64.S
@@ -31,6 +31,7 @@
  */
 
 #include <asm/cpufeature.h>
+#include <asm/msr-index.h>
 
 verify_cpu:
         pushfl                          # Save caller passed flags
@@ -88,7 +89,7 @@ verify_cpu_sse_test:
         je      verify_cpu_sse_ok
         test    %di,%di
         jz      verify_cpu_no_longmode  # only try to force SSE on AMD
-        movl    $0xc0010015,%ecx        # HWCR
+        movl    $MSR_K7_HWCR,%ecx
         rdmsr
         btr     $15,%eax                # enable SSE
         wrmsr
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index 1c0c6ab9c60f..dcbb28c4b694 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -73,8 +73,8 @@ void update_vsyscall_tz(void)
         write_sequnlock_irqrestore(&vsyscall_gtod_data.lock, flags);
 }
 
-void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
-                     u32 mult)
+void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
+                        struct clocksource *clock, u32 mult)
 {
         unsigned long flags;
 
@@ -87,7 +87,7 @@ void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
         vsyscall_gtod_data.clock.shift = clock->shift;
         vsyscall_gtod_data.wall_time_sec = wall_time->tv_sec;
         vsyscall_gtod_data.wall_time_nsec = wall_time->tv_nsec;
-        vsyscall_gtod_data.wall_to_monotonic = wall_to_monotonic;
+        vsyscall_gtod_data.wall_to_monotonic = *wtm;
         vsyscall_gtod_data.wall_time_coarse = __current_kernel_time();
         write_sequnlock_irqrestore(&vsyscall_gtod_data.lock, flags);
 }
@@ -169,13 +169,18 @@ int __vsyscall(0) vgettimeofday(struct timeval * tv, struct timezone * tz)
  * unlikely */
 time_t __vsyscall(1) vtime(time_t *t)
 {
-        struct timeval tv;
+        unsigned seq;
         time_t result;
         if (unlikely(!__vsyscall_gtod_data.sysctl_enabled))
                 return time_syscall(t);
 
-        vgettimeofday(&tv, NULL);
-        result = tv.tv_sec;
+        do {
+                seq = read_seqbegin(&__vsyscall_gtod_data.lock);
+
+                result = __vsyscall_gtod_data.wall_time_sec;
+
+        } while (read_seqretry(&__vsyscall_gtod_data.lock, seq));
+
         if (t)
                 *t = result;
         return result;
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
index 37e68fc5e24a..980149867a19 100644
--- a/arch/x86/kernel/xsave.c
+++ b/arch/x86/kernel/xsave.c
@@ -36,15 +36,14 @@ int check_for_xstate(struct i387_fxsave_struct __user *buf,
 
         err = __copy_from_user(fx_sw_user, &buf->sw_reserved[0],
                                sizeof(struct _fpx_sw_bytes));
-
         if (err)
-                return err;
+                return -EFAULT;
 
         /*
          * First Magic check failed.
          */
         if (fx_sw_user->magic1 != FP_XSTATE_MAGIC1)
-                return -1;
+                return -EINVAL;
 
         /*
          * Check for error scenarios.
@@ -52,19 +51,21 @@ int check_for_xstate(struct i387_fxsave_struct __user *buf,
         if (fx_sw_user->xstate_size < min_xstate_size ||
             fx_sw_user->xstate_size > xstate_size ||
             fx_sw_user->xstate_size > fx_sw_user->extended_size)
-                return -1;
+                return -EINVAL;
 
         err = __get_user(magic2, (__u32 *) (((void *)fpstate) +
                                             fx_sw_user->extended_size -
                                             FP_XSTATE_MAGIC2_SIZE));
+        if (err)
+                return err;
         /*
          * Check for the presence of second magic word at the end of memory
          * layout. This detects the case where the user just copied the legacy
          * fpstate layout with out copying the extended state information
          * in the memory layout.
          */
-        if (err || magic2 != FP_XSTATE_MAGIC2)
-                return -1;
+        if (magic2 != FP_XSTATE_MAGIC2)
+                return -EFAULT;
 
         return 0;
 }
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 5ac0bb465ed6..b38bd8b92aa6 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -9,6 +9,7 @@
  * privileged instructions:
  *
  * Copyright (C) 2006 Qumranet
+ * Copyright 2010 Red Hat, Inc. and/or its affilates.
  *
  *   Avi Kivity <avi@qumranet.com>
  *   Yaniv Kamay <yaniv@qumranet.com>
@@ -67,6 +68,9 @@
 #define SrcImmUByte (8<<4)      /* 8-bit unsigned immediate operand. */
 #define SrcImmU     (9<<4)      /* Immediate operand, unsigned */
 #define SrcSI       (0xa<<4)    /* Source is in the DS:RSI */
+#define SrcImmFAddr (0xb<<4)    /* Source is immediate far address */
+#define SrcMemFAddr (0xc<<4)    /* Source is far address in memory */
+#define SrcAcc      (0xd<<4)    /* Source Accumulator */
 #define SrcMask     (0xf<<4)
 /* Generic ModRM decode. */
 #define ModRM       (1<<8)
@@ -88,10 +92,6 @@
 #define Src2CL      (1<<29)
 #define Src2ImmByte (2<<29)
 #define Src2One     (3<<29)
-#define Src2Imm16   (4<<29)
-#define Src2Mem16   (5<<29) /* Used for Ep encoding. First argument has to be
-                               in memory and second argument is located
-                               immediately after the first one in memory. */
 #define Src2Mask    (7<<29)
 
 enum {
@@ -124,15 +124,15 @@ static u32 opcode_table[256] = {
         /* 0x20 - 0x27 */
         ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
-        DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
+        ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
         /* 0x28 - 0x2F */
         ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
-        0, 0, 0, 0,
+        ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
         /* 0x30 - 0x37 */
         ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
-        0, 0, 0, 0,
+        ByteOp | DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
         /* 0x38 - 0x3F */
         ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
         ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
@@ -170,20 +170,20 @@ static u32 opcode_table[256] = {
         /* 0x88 - 0x8F */
         ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
         ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
-        DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
-        DstReg | SrcMem | ModRM | Mov, Group | Group1A,
+        DstMem | SrcNone | ModRM | Mov, ModRM | DstReg,
+        ImplicitOps | SrcMem16 | ModRM, Group | Group1A,
         /* 0x90 - 0x97 */
         DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
         /* 0x98 - 0x9F */
-        0, 0, SrcImm | Src2Imm16 | No64, 0,
+        0, 0, SrcImmFAddr | No64, 0,
         ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
         /* 0xA0 - 0xA7 */
-        ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
-        ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
+        ByteOp | DstAcc | SrcMem | Mov | MemAbs, DstAcc | SrcMem | Mov | MemAbs,
+        ByteOp | DstMem | SrcAcc | Mov | MemAbs, DstMem | SrcAcc | Mov | MemAbs,
         ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
         ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
         /* 0xA8 - 0xAF */
-        0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
+        DstAcc | SrcImmByte | ByteOp, DstAcc | SrcImm, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
         ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
         ByteOp | DstDI | String, DstDI | String,
         /* 0xB0 - 0xB7 */
@@ -215,7 +215,7 @@ static u32 opcode_table[256] = {
         ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
         /* 0xE8 - 0xEF */
         SrcImm | Stack, SrcImm | ImplicitOps,
-        SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
+        SrcImmFAddr | No64, SrcImmByte | ImplicitOps,
         SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
         SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
         /* 0xF0 - 0xF7 */
@@ -337,20 +337,20 @@ static u32 group_table[] = {
         [Group1A*8] =
         DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
         [Group3_Byte*8] =
-        ByteOp | SrcImm | DstMem | ModRM, 0,
+        ByteOp | SrcImm | DstMem | ModRM, ByteOp | SrcImm | DstMem | ModRM,
         ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
         0, 0, 0, 0,
         [Group3*8] =
-        DstMem | SrcImm | ModRM, 0,
+        DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
         DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
         0, 0, 0, 0,
         [Group4*8] =
-        ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
+        ByteOp | DstMem | SrcNone | ModRM | Lock, ByteOp | DstMem | SrcNone | ModRM | Lock,
         0, 0, 0, 0, 0, 0,
         [Group5*8] =
-        DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
+        DstMem | SrcNone | ModRM | Lock, DstMem | SrcNone | ModRM | Lock,
         SrcMem | ModRM | Stack, 0,
-        SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps,
+        SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps,
         SrcMem | ModRM | Stack, 0,
         [Group7*8] =
         0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
@@ -576,6 +576,13 @@ static u32 group2_table[] = {
         (_type)_x;                                                      \
 })
 
+#define insn_fetch_arr(_arr, _size, _eip)                                \
+({      rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size));           \
+        if (rc != X86EMUL_CONTINUE)                                     \
+                goto done;                                              \
+        (_eip) += (_size);                                              \
+})
+
 static inline unsigned long ad_mask(struct decode_cache *c)
 {
         return (1UL << (c->ad_bytes << 3)) - 1;
@@ -617,31 +624,66 @@ static void set_seg_override(struct decode_cache *c, int seg)
         c->seg_override = seg;
 }
 
-static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
+static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
+                              struct x86_emulate_ops *ops, int seg)
 {
         if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
                 return 0;
 
-        return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
+        return ops->get_cached_segment_base(seg, ctxt->vcpu);
 }
 
 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
+                                       struct x86_emulate_ops *ops,
                                        struct decode_cache *c)
 {
         if (!c->has_seg_override)
                 return 0;
 
-        return seg_base(ctxt, c->seg_override);
+        return seg_base(ctxt, ops, c->seg_override);
+}
+
+static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
+                             struct x86_emulate_ops *ops)
+{
+        return seg_base(ctxt, ops, VCPU_SREG_ES);
+}
+
+static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
+                             struct x86_emulate_ops *ops)
+{
+        return seg_base(ctxt, ops, VCPU_SREG_SS);
+}
+
+static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
+                                      u32 error, bool valid)
+{
+        ctxt->exception = vec;
+        ctxt->error_code = error;
+        ctxt->error_code_valid = valid;
+        ctxt->restart = false;
+}
+
+static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
+{
+        emulate_exception(ctxt, GP_VECTOR, err, true);
 }
 
-static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
+static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
+                       int err)
 {
-        return seg_base(ctxt, VCPU_SREG_ES);
+        ctxt->cr2 = addr;
+        emulate_exception(ctxt, PF_VECTOR, err, true);
 }
 
-static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
+static void emulate_ud(struct x86_emulate_ctxt *ctxt)
 {
-        return seg_base(ctxt, VCPU_SREG_SS);
+        emulate_exception(ctxt, UD_VECTOR, 0, false);
+}
+
+static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
+{
+        emulate_exception(ctxt, TS_VECTOR, err, true);
 }
 
 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
@@ -932,12 +974,9 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
         /* we cannot decode insn before we complete previous rep insn */
         WARN_ON(ctxt->restart);
 
-        /* Shadow copy of register state. Committed on successful emulation. */
-        memset(c, 0, sizeof(struct decode_cache));
         c->eip = ctxt->eip;
         c->fetch.start = c->fetch.end = c->eip;
-        ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
-        memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
+        ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
 
         switch (mode) {
         case X86EMUL_MODE_REAL:
@@ -1060,7 +1099,7 @@ done_prefixes:
                 set_seg_override(c, VCPU_SREG_DS);
 
         if (!(!c->twobyte && c->b == 0x8d))
-                c->modrm_ea += seg_override_base(ctxt, c);
+                c->modrm_ea += seg_override_base(ctxt, ops, c);
 
         if (c->ad_bytes != 8)
                 c->modrm_ea = (u32)c->modrm_ea;
@@ -1148,6 +1187,25 @@ done_prefixes:
                 else
                         c->src.val = insn_fetch(u8, 1, c->eip);
                 break;
+        case SrcAcc:
+                c->src.type = OP_REG;
+                c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
+                c->src.ptr = &c->regs[VCPU_REGS_RAX];
+                switch (c->src.bytes) {
+                        case 1:
+                                c->src.val = *(u8 *)c->src.ptr;
+                                break;
+                        case 2:
+                                c->src.val = *(u16 *)c->src.ptr;
+                                break;
+                        case 4:
+                                c->src.val = *(u32 *)c->src.ptr;
+                                break;
+                        case 8:
+                                c->src.val = *(u64 *)c->src.ptr;
+                                break;
+                }
+                break;
         case SrcOne:
                 c->src.bytes = 1;
                 c->src.val = 1;
@@ -1156,10 +1214,21 @@ done_prefixes:
                 c->src.type = OP_MEM;
                 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
                 c->src.ptr = (unsigned long *)
-                        register_address(c,  seg_override_base(ctxt, c),
+                        register_address(c,  seg_override_base(ctxt, ops, c),
                                          c->regs[VCPU_REGS_RSI]);
                 c->src.val = 0;
                 break;
+        case SrcImmFAddr:
+                c->src.type = OP_IMM;
+                c->src.ptr = (unsigned long *)c->eip;
+                c->src.bytes = c->op_bytes + 2;
+                insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
+                break;
+        case SrcMemFAddr:
+                c->src.type = OP_MEM;
+                c->src.ptr = (unsigned long *)c->modrm_ea;
+                c->src.bytes = c->op_bytes + 2;
+                break;
         }
 
         /*
@@ -1179,22 +1248,10 @@ done_prefixes:
                 c->src2.bytes = 1;
                 c->src2.val = insn_fetch(u8, 1, c->eip);
                 break;
-        case Src2Imm16:
-                c->src2.type = OP_IMM;
-                c->src2.ptr = (unsigned long *)c->eip;
-                c->src2.bytes = 2;
-                c->src2.val = insn_fetch(u16, 2, c->eip);
-                break;
         case Src2One:
                 c->src2.bytes = 1;
                 c->src2.val = 1;
                 break;
-        case Src2Mem16:
-                c->src2.type = OP_MEM;
-                c->src2.bytes = 2;
-                c->src2.ptr = (unsigned long *)(c->modrm_ea + c->src.bytes);
-                c->src2.val = 0;
-                break;
         }
 
         /* Decode and fetch the destination operand: register or memory. */
@@ -1253,7 +1310,7 @@ done_prefixes:
                 c->dst.type = OP_MEM;
                 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
                 c->dst.ptr = (unsigned long *)
-                        register_address(c, es_base(ctxt),
+                        register_address(c, es_base(ctxt, ops),
                                          c->regs[VCPU_REGS_RDI]);
                 c->dst.val = 0;
                 break;
@@ -1263,6 +1320,37 @@ done:
         return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
 }
 
+static int read_emulated(struct x86_emulate_ctxt *ctxt,
+                         struct x86_emulate_ops *ops,
+                         unsigned long addr, void *dest, unsigned size)
+{
+        int rc;
+        struct read_cache *mc = &ctxt->decode.mem_read;
+        u32 err;
+
+        while (size) {
+                int n = min(size, 8u);
+                size -= n;
+                if (mc->pos < mc->end)
+                        goto read_cached;
+
+                rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
+                                        ctxt->vcpu);
+                if (rc == X86EMUL_PROPAGATE_FAULT)
+                        emulate_pf(ctxt, addr, err);
+                if (rc != X86EMUL_CONTINUE)
+                        return rc;
+                mc->end += n;
+
+        read_cached:
+                memcpy(dest, mc->data + mc->pos, n);
+                mc->pos += n;
+                dest += n;
+                addr += n;
+        }
+        return X86EMUL_CONTINUE;
+}
+
 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
                            struct x86_emulate_ops *ops,
                            unsigned int size, unsigned short port,
@@ -1330,13 +1418,13 @@ static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
         get_descriptor_table_ptr(ctxt, ops, selector, &dt);
 
         if (dt.size < index * 8 + 7) {
-                kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
+                emulate_gp(ctxt, selector & 0xfffc);
                 return X86EMUL_PROPAGATE_FAULT;
         }
         addr = dt.address + index * 8;
         ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,  &err);
         if (ret == X86EMUL_PROPAGATE_FAULT)
-                kvm_inject_page_fault(ctxt->vcpu, addr, err);
+                emulate_pf(ctxt, addr, err);
 
        return ret;
 }
@@ -1355,14 +1443,14 @@ static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
         get_descriptor_table_ptr(ctxt, ops, selector, &dt);
 
         if (dt.size < index * 8 + 7) {
-                kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
+                emulate_gp(ctxt, selector & 0xfffc);
                 return X86EMUL_PROPAGATE_FAULT;
         }
 
         addr = dt.address + index * 8;
         ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
         if (ret == X86EMUL_PROPAGATE_FAULT)
-                kvm_inject_page_fault(ctxt->vcpu, addr, err);
+                emulate_pf(ctxt, addr, err);
 
         return ret;
 }
@@ -1481,11 +1569,70 @@ load:
         ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
         return X86EMUL_CONTINUE;
 exception:
-        kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
+        emulate_exception(ctxt, err_vec, err_code, true);
         return X86EMUL_PROPAGATE_FAULT;
 }
 
-static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
+static inline int writeback(struct x86_emulate_ctxt *ctxt,
+                            struct x86_emulate_ops *ops)
+{
+        int rc;
+        struct decode_cache *c = &ctxt->decode;
+        u32 err;
+
+        switch (c->dst.type) {
+        case OP_REG:
+                /* The 4-byte case *is* correct:
+                 * in 64-bit mode we zero-extend.
+                 */
+                switch (c->dst.bytes) {
+                case 1:
+                        *(u8 *)c->dst.ptr = (u8)c->dst.val;
+                        break;
+                case 2:
+                        *(u16 *)c->dst.ptr = (u16)c->dst.val;
+                        break;
+                case 4:
+                        *c->dst.ptr = (u32)c->dst.val;
+                        break;  /* 64b: zero-ext */
+                case 8:
+                        *c->dst.ptr = c->dst.val;
+                        break;
+                }
+                break;
+        case OP_MEM:
+                if (c->lock_prefix)
+                        rc = ops->cmpxchg_emulated(
+                                        (unsigned long)c->dst.ptr,
+                                        &c->dst.orig_val,
+                                        &c->dst.val,
+                                        c->dst.bytes,
+                                        &err,
+                                        ctxt->vcpu);
+                else
+                        rc = ops->write_emulated(
+                                        (unsigned long)c->dst.ptr,
+                                        &c->dst.val,
+                                        c->dst.bytes,
+                                        &err,
+                                        ctxt->vcpu);
+                if (rc == X86EMUL_PROPAGATE_FAULT)
+                        emulate_pf(ctxt,
+                                              (unsigned long)c->dst.ptr, err);
+                if (rc != X86EMUL_CONTINUE)
+                        return rc;
+                break;
+        case OP_NONE:
+                /* no writeback */
+                break;
+        default:
+                break;
+        }
+        return X86EMUL_CONTINUE;
+}
+
+static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
+                                struct x86_emulate_ops *ops)
 {
         struct decode_cache *c = &ctxt->decode;
 
@@ -1493,7 +1640,7 @@ static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
         c->dst.bytes = c->op_bytes;
         c->dst.val = c->src.val;
         register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
-        c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
+        c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
                                                c->regs[VCPU_REGS_RSP]);
 }
 
@@ -1504,9 +1651,9 @@ static int emulate_pop(struct x86_emulate_ctxt *ctxt,
         struct decode_cache *c = &ctxt->decode;
         int rc;
 
-        rc = ops->read_emulated(register_address(c, ss_base(ctxt),
-                                                 c->regs[VCPU_REGS_RSP]),
-                                dest, len, ctxt->vcpu);
+        rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
+                                                       c->regs[VCPU_REGS_RSP]),
+                           dest, len);
         if (rc != X86EMUL_CONTINUE)
                 return rc;
 
@@ -1541,7 +1688,7 @@ static int emulate_popf(struct x86_emulate_ctxt *ctxt,
                 break;
         case X86EMUL_MODE_VM86:
                 if (iopl < 3) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         return X86EMUL_PROPAGATE_FAULT;
                 }
                 change_mask |= EFLG_IF;
@@ -1557,15 +1704,14 @@ static int emulate_popf(struct x86_emulate_ctxt *ctxt,
         return rc;
 }
 
-static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
+static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
+                              struct x86_emulate_ops *ops, int seg)
 {
         struct decode_cache *c = &ctxt->decode;
-        struct kvm_segment segment;
 
-        kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
+        c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
 
-        c->src.val = segment.selector;
-        emulate_push(ctxt);
+        emulate_push(ctxt, ops);
 }
 
 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
@@ -1583,19 +1729,31 @@ static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
         return rc;
 }
 
-static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
+static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
+                          struct x86_emulate_ops *ops)
 {
         struct decode_cache *c = &ctxt->decode;
         unsigned long old_esp = c->regs[VCPU_REGS_RSP];
+        int rc = X86EMUL_CONTINUE;
         int reg = VCPU_REGS_RAX;
 
         while (reg <= VCPU_REGS_RDI) {
                 (reg == VCPU_REGS_RSP) ?
                 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
 
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
+
+                rc = writeback(ctxt, ops);
+                if (rc != X86EMUL_CONTINUE)
+                        return rc;
+
                 ++reg;
         }
+
+        /* Disable writeback. */
+        c->dst.type = OP_NONE;
+
+        return rc;
 }
 
 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
@@ -1695,14 +1853,14 @@ static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
                 old_eip = c->eip;
                 c->eip = c->src.val;
                 c->src.val = old_eip;
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
                 break;
         }
         case 4: /* jmp abs */
                 c->eip = c->src.val;
                 break;
         case 6: /* push */
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
                 break;
         }
         return X86EMUL_CONTINUE;
@@ -1748,145 +1906,82 @@ static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
         return rc;
 }
 
-static inline int writeback(struct x86_emulate_ctxt *ctxt,
-                            struct x86_emulate_ops *ops)
-{
-        int rc;
-        struct decode_cache *c = &ctxt->decode;
-
-        switch (c->dst.type) {
-        case OP_REG:
-                /* The 4-byte case *is* correct:
-                 * in 64-bit mode we zero-extend.
-                 */
-                switch (c->dst.bytes) {
-                case 1:
-                        *(u8 *)c->dst.ptr = (u8)c->dst.val;
-                        break;
-                case 2:
-                        *(u16 *)c->dst.ptr = (u16)c->dst.val;
-                        break;
-                case 4:
-                        *c->dst.ptr = (u32)c->dst.val;
-                        break;  /* 64b: zero-ext */
-                case 8:
-                        *c->dst.ptr = c->dst.val;
-                        break;
-                }
-                break;
-        case OP_MEM:
-                if (c->lock_prefix)
-                        rc = ops->cmpxchg_emulated(
-                                        (unsigned long)c->dst.ptr,
-                                        &c->dst.orig_val,
-                                        &c->dst.val,
-                                        c->dst.bytes,
-                                        ctxt->vcpu);
-                else
-                        rc = ops->write_emulated(
-                                        (unsigned long)c->dst.ptr,
-                                        &c->dst.val,
-                                        c->dst.bytes,
-                                        ctxt->vcpu);
-                if (rc != X86EMUL_CONTINUE)
-                        return rc;
-                break;
-        case OP_NONE:
-                /* no writeback */
-                break;
-        default:
-                break;
-        }
-        return X86EMUL_CONTINUE;
-}
-
-static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
-{
-        u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
-        /*
-         * an sti; sti; sequence only disable interrupts for the first
-         * instruction. So, if the last instruction, be it emulated or
-         * not, left the system with the INT_STI flag enabled, it
-         * means that the last instruction is an sti. We should not
-         * leave the flag on in this case. The same goes for mov ss
-         */
-        if (!(int_shadow & mask))
-                ctxt->interruptibility = mask;
-}
-
 static inline void
 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
-        struct kvm_segment *cs, struct kvm_segment *ss)
+                        struct x86_emulate_ops *ops, struct desc_struct *cs,
+                        struct desc_struct *ss)
 {
-        memset(cs, 0, sizeof(struct kvm_segment));
-        kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
-        memset(ss, 0, sizeof(struct kvm_segment));
+        memset(cs, 0, sizeof(struct desc_struct));
+        ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
+        memset(ss, 0, sizeof(struct desc_struct));
 
         cs->l = 0;              /* will be adjusted later */
-        cs->base = 0;           /* flat segment */
+        set_desc_base(cs, 0);   /* flat segment */
         cs->g = 1;              /* 4kb granularity */
-        cs->limit = 0xffffffff; /* 4GB limit */
+        set_desc_limit(cs, 0xfffff);    /* 4GB limit */
         cs->type = 0x0b;        /* Read, Execute, Accessed */
         cs->s = 1;
         cs->dpl = 0;            /* will be adjusted later */
-        cs->present = 1;
-        cs->db = 1;
+        cs->p = 1;
+        cs->d = 1;
 
-        ss->unusable = 0;
-        ss->base = 0;           /* flat segment */
-        ss->limit = 0xffffffff; /* 4GB limit */
+        set_desc_base(ss, 0);   /* flat segment */
+        set_desc_limit(ss, 0xfffff);    /* 4GB limit */
         ss->g = 1;              /* 4kb granularity */
         ss->s = 1;
         ss->type = 0x03;        /* Read/Write, Accessed */
-        ss->db = 1;             /* 32bit stack segment */
+        ss->d = 1;              /* 32bit stack segment */
         ss->dpl = 0;
-        ss->present = 1;
+        ss->p = 1;
 }
 
 static int
-emulate_syscall(struct x86_emulate_ctxt *ctxt)
+emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 {
         struct decode_cache *c = &ctxt->decode;
-        struct kvm_segment cs, ss;
+        struct desc_struct cs, ss;
         u64 msr_data;
+        u16 cs_sel, ss_sel;
 
         /* syscall is not available in real mode */
         if (ctxt->mode == X86EMUL_MODE_REAL ||
             ctxt->mode == X86EMUL_MODE_VM86) {
-                kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                emulate_ud(ctxt);
                 return X86EMUL_PROPAGATE_FAULT;
         }
 
-        setup_syscalls_segments(ctxt, &cs, &ss);
+        setup_syscalls_segments(ctxt, ops, &cs, &ss);
 
-        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
+        ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
         msr_data >>= 32;
-        cs.selector = (u16)(msr_data & 0xfffc);
-        ss.selector = (u16)(msr_data + 8);
+        cs_sel = (u16)(msr_data & 0xfffc);
+        ss_sel = (u16)(msr_data + 8);
 
         if (is_long_mode(ctxt->vcpu)) {
-                cs.db = 0;
+                cs.d = 0;
                 cs.l = 1;
         }
-        kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
-        kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
+        ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
+        ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
+        ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
+        ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
 
         c->regs[VCPU_REGS_RCX] = c->eip;
         if (is_long_mode(ctxt->vcpu)) {
 #ifdef CONFIG_X86_64
                 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
 
-                kvm_x86_ops->get_msr(ctxt->vcpu,
-                        ctxt->mode == X86EMUL_MODE_PROT64 ?
-                        MSR_LSTAR : MSR_CSTAR, &msr_data);
+                ops->get_msr(ctxt->vcpu,
+                             ctxt->mode == X86EMUL_MODE_PROT64 ?
+                             MSR_LSTAR : MSR_CSTAR, &msr_data);
                 c->eip = msr_data;
 
-                kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
+                ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
                 ctxt->eflags &= ~(msr_data | EFLG_RF);
 #endif
         } else {
                 /* legacy mode */
-                kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
+                ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
                 c->eip = (u32)msr_data;
 
                 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
@@ -1896,15 +1991,16 @@ emulate_syscall(struct x86_emulate_ctxt *ctxt)
 }
 
 static int
-emulate_sysenter(struct x86_emulate_ctxt *ctxt)
+emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 {
         struct decode_cache *c = &ctxt->decode;
-        struct kvm_segment cs, ss;
+        struct desc_struct cs, ss;
         u64 msr_data;
+        u16 cs_sel, ss_sel;
 
         /* inject #GP if in real mode */
         if (ctxt->mode == X86EMUL_MODE_REAL) {
-                kvm_inject_gp(ctxt->vcpu, 0);
+                emulate_gp(ctxt, 0);
                 return X86EMUL_PROPAGATE_FAULT;
         }
 
@@ -1912,67 +2008,70 @@ emulate_sysenter(struct x86_emulate_ctxt *ctxt)
         * Therefore, we inject an #UD.
         */
         if (ctxt->mode == X86EMUL_MODE_PROT64) {
-                kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                emulate_ud(ctxt);
                 return X86EMUL_PROPAGATE_FAULT;
         }
 
-        setup_syscalls_segments(ctxt, &cs, &ss);
+        setup_syscalls_segments(ctxt, ops, &cs, &ss);
 
-        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
+        ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
         switch (ctxt->mode) {
         case X86EMUL_MODE_PROT32:
                 if ((msr_data & 0xfffc) == 0x0) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         return X86EMUL_PROPAGATE_FAULT;
                 }
                 break;
         case X86EMUL_MODE_PROT64:
                 if (msr_data == 0x0) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         return X86EMUL_PROPAGATE_FAULT;
                 }
                 break;
         }
 
         ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
-        cs.selector = (u16)msr_data;
-        cs.selector &= ~SELECTOR_RPL_MASK;
-        ss.selector = cs.selector + 8;
-        ss.selector &= ~SELECTOR_RPL_MASK;
+        cs_sel = (u16)msr_data;
+        cs_sel &= ~SELECTOR_RPL_MASK;
+        ss_sel = cs_sel + 8;
+        ss_sel &= ~SELECTOR_RPL_MASK;
         if (ctxt->mode == X86EMUL_MODE_PROT64
                 || is_long_mode(ctxt->vcpu)) {
-                cs.db = 0;
+                cs.d = 0;
                 cs.l = 1;
         }
 
-        kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
-        kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
+        ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
+        ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
+        ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
+        ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
 
-        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
+        ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
         c->eip = msr_data;
 
-        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
+        ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
         c->regs[VCPU_REGS_RSP] = msr_data;
 
         return X86EMUL_CONTINUE;
 }
 
 static int
-emulate_sysexit(struct x86_emulate_ctxt *ctxt)
+emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 {
         struct decode_cache *c = &ctxt->decode;
-        struct kvm_segment cs, ss;
+        struct desc_struct cs, ss;
         u64 msr_data;
         int usermode;
+        u16 cs_sel, ss_sel;
 
         /* inject #GP if in real mode or Virtual 8086 mode */
         if (ctxt->mode == X86EMUL_MODE_REAL ||
             ctxt->mode == X86EMUL_MODE_VM86) {
-                kvm_inject_gp(ctxt->vcpu, 0);
+                emulate_gp(ctxt, 0);
                 return X86EMUL_PROPAGATE_FAULT;
         }
 
-        setup_syscalls_segments(ctxt, &cs, &ss);
+        setup_syscalls_segments(ctxt, ops, &cs, &ss);
 
         if ((c->rex_prefix & 0x8) != 0x0)
                 usermode = X86EMUL_MODE_PROT64;
@@ -1981,35 +2080,37 @@ emulate_sysexit(struct x86_emulate_ctxt *ctxt)
 
         cs.dpl = 3;
         ss.dpl = 3;
-        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
+        ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
         switch (usermode) {
         case X86EMUL_MODE_PROT32:
-                cs.selector = (u16)(msr_data + 16);
+                cs_sel = (u16)(msr_data + 16);
                 if ((msr_data & 0xfffc) == 0x0) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         return X86EMUL_PROPAGATE_FAULT;
                 }
-                ss.selector = (u16)(msr_data + 24);
+                ss_sel = (u16)(msr_data + 24);
                 break;
         case X86EMUL_MODE_PROT64:
-                cs.selector = (u16)(msr_data + 32);
+                cs_sel = (u16)(msr_data + 32);
                 if (msr_data == 0x0) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         return X86EMUL_PROPAGATE_FAULT;
                 }
-                ss.selector = cs.selector + 8;
-                cs.db = 0;
+                ss_sel = cs_sel + 8;
+                cs.d = 0;
                 cs.l = 1;
                 break;
         }
-        cs.selector |= SELECTOR_RPL_MASK;
-        ss.selector |= SELECTOR_RPL_MASK;
+        cs_sel |= SELECTOR_RPL_MASK;
+        ss_sel |= SELECTOR_RPL_MASK;
 
-        kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
-        kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
+        ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
+        ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
+        ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
+        ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
 
-        c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
-        c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
+        c->eip = c->regs[VCPU_REGS_RDX];
+        c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
 
         return X86EMUL_CONTINUE;
 }
@@ -2030,25 +2131,25 @@ static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
                                             struct x86_emulate_ops *ops,
                                             u16 port, u16 len)
 {
-        struct kvm_segment tr_seg;
+        struct desc_struct tr_seg;
         int r;
         u16 io_bitmap_ptr;
         u8 perm, bit_idx = port & 0x7;
         unsigned mask = (1 << len) - 1;
 
-        kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
-        if (tr_seg.unusable)
+        ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
+        if (!tr_seg.p)
                 return false;
-        if (tr_seg.limit < 103)
+        if (desc_limit_scaled(&tr_seg) < 103)
                 return false;
-        r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
-                          NULL);
+        r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
+                          ctxt->vcpu, NULL);
         if (r != X86EMUL_CONTINUE)
                 return false;
-        if (io_bitmap_ptr + port/8 > tr_seg.limit)
+        if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
                 return false;
-        r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
-                          ctxt->vcpu, NULL);
+        r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
+                          &perm, 1, ctxt->vcpu, NULL);
         if (r != X86EMUL_CONTINUE)
                 return false;
         if ((perm >> bit_idx) & mask)
@@ -2066,17 +2167,6 @@ static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
         return true;
 }
 
-static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt,
-                                      struct x86_emulate_ops *ops,
-                                      int seg)
-{
-        struct desc_struct desc;
-        if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu))
-                return get_desc_base(&desc);
-        else
-                return ~0;
-}
-
 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
                                 struct x86_emulate_ops *ops,
                                 struct tss_segment_16 *tss)
@@ -2165,7 +2255,7 @@ static int task_switch_16(struct x86_emulate_ctxt *ctxt,
                             &err);
         if (ret == X86EMUL_PROPAGATE_FAULT) {
                 /* FIXME: need to provide precise fault address */
-                kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
+                emulate_pf(ctxt, old_tss_base, err);
                 return ret;
         }
 
@@ -2175,7 +2265,7 @@ static int task_switch_16(struct x86_emulate_ctxt *ctxt,
                              &err);
         if (ret == X86EMUL_PROPAGATE_FAULT) {
                 /* FIXME: need to provide precise fault address */
-                kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
+                emulate_pf(ctxt, old_tss_base, err);
                 return ret;
         }
 
@@ -2183,7 +2273,7 @@ static int task_switch_16(struct x86_emulate_ctxt *ctxt,
                             &err);
         if (ret == X86EMUL_PROPAGATE_FAULT) {
                 /* FIXME: need to provide precise fault address */
-                kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
+                emulate_pf(ctxt, new_tss_base, err);
                 return ret;
         }
 
@@ -2196,7 +2286,7 @@ static int task_switch_16(struct x86_emulate_ctxt *ctxt,
                                      ctxt->vcpu, &err);
                 if (ret == X86EMUL_PROPAGATE_FAULT) {
                         /* FIXME: need to provide precise fault address */
-                        kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
+                        emulate_pf(ctxt, new_tss_base, err);
                         return ret;
                 }
         }
@@ -2238,7 +2328,10 @@ static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
         struct decode_cache *c = &ctxt->decode;
         int ret;
 
-        ops->set_cr(3, tss->cr3, ctxt->vcpu);
+        if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
+                emulate_gp(ctxt, 0);
+                return X86EMUL_PROPAGATE_FAULT;
+        }
         c->eip = tss->eip;
         ctxt->eflags = tss->eflags | 2;
         c->regs[VCPU_REGS_RAX] = tss->eax;
@@ -2304,7 +2397,7 @@ static int task_switch_32(struct x86_emulate_ctxt *ctxt,
                             &err);
         if (ret == X86EMUL_PROPAGATE_FAULT) {
                 /* FIXME: need to provide precise fault address */
-                kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
+                emulate_pf(ctxt, old_tss_base, err);
                 return ret;
         }
 
@@ -2314,7 +2407,7 @@ static int task_switch_32(struct x86_emulate_ctxt *ctxt,
                              &err);
         if (ret == X86EMUL_PROPAGATE_FAULT) {
                 /* FIXME: need to provide precise fault address */
-                kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
+                emulate_pf(ctxt, old_tss_base, err);
                 return ret;
         }
 
@@ -2322,7 +2415,7 @@ static int task_switch_32(struct x86_emulate_ctxt *ctxt,
                             &err);
         if (ret == X86EMUL_PROPAGATE_FAULT) {
                 /* FIXME: need to provide precise fault address */
-                kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
+                emulate_pf(ctxt, new_tss_base, err);
                 return ret;
         }
 
@@ -2335,7 +2428,7 @@ static int task_switch_32(struct x86_emulate_ctxt *ctxt,
                                      ctxt->vcpu, &err);
                 if (ret == X86EMUL_PROPAGATE_FAULT) {
                         /* FIXME: need to provide precise fault address */
-                        kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
+                        emulate_pf(ctxt, new_tss_base, err);
                         return ret;
                 }
         }
@@ -2352,7 +2445,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
         int ret;
         u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
         ulong old_tss_base =
-                get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR);
+                ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
         u32 desc_limit;
 
         /* FIXME: old_tss_base == ~0 ? */
@@ -2369,7 +2462,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
         if (reason != TASK_SWITCH_IRET) {
                 if ((tss_selector & 3) > next_tss_desc.dpl ||
                     ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         return X86EMUL_PROPAGATE_FAULT;
                 }
         }
@@ -2378,8 +2471,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
         if (!next_tss_desc.p ||
             ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
              desc_limit < 0x2b)) {
-                kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
-                                      tss_selector & 0xfffc);
+                emulate_ts(ctxt, tss_selector & 0xfffc);
                 return X86EMUL_PROPAGATE_FAULT;
         }
 
@@ -2425,7 +2517,7 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
                 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
                 c->lock_prefix = 0;
                 c->src.val = (unsigned long) error_code;
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
         }
 
         return ret;
@@ -2439,18 +2531,16 @@ int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
         struct decode_cache *c = &ctxt->decode;
         int rc;
 
-        memset(c, 0, sizeof(struct decode_cache));
         c->eip = ctxt->eip;
-        memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
         c->dst.type = OP_NONE;
 
         rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
                                      has_error_code, error_code);
 
         if (rc == X86EMUL_CONTINUE) {
-                memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
-                kvm_rip_write(ctxt->vcpu, c->eip);
                 rc = writeback(ctxt, ops);
+                if (rc == X86EMUL_CONTINUE)
+                        ctxt->eip = c->eip;
         }
 
         return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
@@ -2474,29 +2564,22 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
         int rc = X86EMUL_CONTINUE;
         int saved_dst_type = c->dst.type;
 
-        ctxt->interruptibility = 0;
-
-        /* Shadow copy of register state. Committed on successful emulation.
-         * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
-         * modify them.
-         */
-
-        memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
+        ctxt->decode.mem_read.pos = 0;
 
         if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
-                kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                emulate_ud(ctxt);
                 goto done;
         }
 
         /* LOCK prefix is allowed only with some instructions */
         if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
-                kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                emulate_ud(ctxt);
                 goto done;
         }
 
         /* Privileged instruction can be executed only in CPL=0 */
         if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
-                kvm_inject_gp(ctxt->vcpu, 0);
+                emulate_gp(ctxt, 0);
                 goto done;
         }
 
@@ -2506,7 +2589,7 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
                 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
                 string_done:
                         ctxt->restart = false;
-                        kvm_rip_write(ctxt->vcpu, c->eip);
+                        ctxt->eip = c->eip;
                         goto done;
                 }
                 /* The second termination condition only applies for REPE
@@ -2529,20 +2612,16 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
         }
 
         if (c->src.type == OP_MEM) {
-                rc = ops->read_emulated((unsigned long)c->src.ptr,
-                                        &c->src.val,
-                                        c->src.bytes,
-                                        ctxt->vcpu);
+                rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
+                                        c->src.valptr, c->src.bytes);
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
                 c->src.orig_val = c->src.val;
         }
 
         if (c->src2.type == OP_MEM) {
-                rc = ops->read_emulated((unsigned long)c->src2.ptr,
-                                        &c->src2.val,
-                                        c->src2.bytes,
-                                        ctxt->vcpu);
+                rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
+                                        &c->src2.val, c->src2.bytes);
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
         }
@@ -2553,8 +2632,8 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 
         if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
                 /* optimisation - avoid slow emulated read if Mov */
-                rc = ops->read_emulated((unsigned long)c->dst.ptr, &c->dst.val,
-                                        c->dst.bytes, ctxt->vcpu);
+                rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
+                                   &c->dst.val, c->dst.bytes);
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
         }
@@ -2571,7 +2650,7 @@ special_insn:
                 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
                 break;
         case 0x06:              /* push es */
-                emulate_push_sreg(ctxt, VCPU_SREG_ES);
+                emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
                 break;
         case 0x07:              /* pop es */
                 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
@@ -2583,14 +2662,14 @@ special_insn:
                 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
                 break;
         case 0x0e:              /* push cs */
-                emulate_push_sreg(ctxt, VCPU_SREG_CS);
+                emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
                 break;
         case 0x10 ... 0x15:
               adc:              /* adc */
                 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
                 break;
         case 0x16:              /* push ss */
-                emulate_push_sreg(ctxt, VCPU_SREG_SS);
+                emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
                 break;
         case 0x17:              /* pop ss */
                 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
@@ -2602,7 +2681,7 @@ special_insn:
                 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
                 break;
         case 0x1e:              /* push ds */
-                emulate_push_sreg(ctxt, VCPU_SREG_DS);
+                emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
                 break;
         case 0x1f:              /* pop ds */
                 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
@@ -2632,7 +2711,7 @@ special_insn:
                 emulate_1op("dec", c->dst, ctxt->eflags);
                 break;
         case 0x50 ... 0x57:  /* push reg */
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
                 break;
         case 0x58 ... 0x5f: /* pop reg */
         pop_instruction:
@@ -2641,7 +2720,9 @@ special_insn:
                         goto done;
                 break;
         case 0x60:      /* pusha */
-                emulate_pusha(ctxt);
+                rc = emulate_pusha(ctxt, ops);
+                if (rc != X86EMUL_CONTINUE)
+                        goto done;
                 break;
         case 0x61:      /* popa */
                 rc = emulate_popa(ctxt, ops);
@@ -2655,14 +2736,14 @@ special_insn:
                 break;
         case 0x68: /* push imm */
         case 0x6a: /* push imm8 */
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
                 break;
         case 0x6c:              /* insb */
         case 0x6d:              /* insw/insd */
                 c->dst.bytes = min(c->dst.bytes, 4u);
                 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
                                           c->dst.bytes)) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         goto done;
                 }
                 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
@@ -2674,7 +2755,7 @@ special_insn:
                 c->src.bytes = min(c->src.bytes, 4u);
                 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
                                           c->src.bytes)) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         goto done;
                 }
                 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
@@ -2707,6 +2788,7 @@ special_insn:
                 }
                 break;
         case 0x84 ... 0x85:
+        test:
                 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
                 break;
         case 0x86 ... 0x87:     /* xchg */
@@ -2735,18 +2817,13 @@ special_insn:
                 break;
         case 0x88 ... 0x8b:     /* mov */
                 goto mov;
-        case 0x8c: { /* mov r/m, sreg */
-                struct kvm_segment segreg;
-
-                if (c->modrm_reg <= VCPU_SREG_GS)
-                        kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
-                else {
-                        kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+        case 0x8c:  /* mov r/m, sreg */
+                if (c->modrm_reg > VCPU_SREG_GS) {
+                        emulate_ud(ctxt);
                         goto done;
                 }
-                c->dst.val = segreg.selector;
+                c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
                 break;
-        }
         case 0x8d: /* lea r16/r32, m */
                 c->dst.val = c->modrm_ea;
                 break;
@@ -2757,12 +2834,12 @@ special_insn:
 
                 if (c->modrm_reg == VCPU_SREG_CS ||
                     c->modrm_reg > VCPU_SREG_GS) {
-                        kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                        emulate_ud(ctxt);
                         goto done;
                 }
 
                 if (c->modrm_reg == VCPU_SREG_SS)
-                        toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS);
+                        ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
 
                 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
 
@@ -2775,19 +2852,19 @@ special_insn:
                         goto done;
                 break;
         case 0x90: /* nop / xchg r8,rax */
-                if (!(c->rex_prefix & 1)) { /* nop */
-                        c->dst.type = OP_NONE;
+                if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
+                        c->dst.type = OP_NONE;  /* nop */
                         break;
                 }
         case 0x91 ... 0x97: /* xchg reg,rax */
-                c->src.type = c->dst.type = OP_REG;
-                c->src.bytes = c->dst.bytes = c->op_bytes;
+                c->src.type = OP_REG;
+                c->src.bytes = c->op_bytes;
                 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
                 c->src.val = *(c->src.ptr);
                 goto xchg;
         case 0x9c: /* pushf */
                 c->src.val =  (unsigned long) ctxt->eflags;
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
                 break;
         case 0x9d: /* popf */
                 c->dst.type = OP_REG;
@@ -2797,19 +2874,15 @@ special_insn:
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
                 break;
-        case 0xa0 ... 0xa1:     /* mov */
-                c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
-                c->dst.val = c->src.val;
-                break;
-        case 0xa2 ... 0xa3:     /* mov */
-                c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
-                break;
+        case 0xa0 ... 0xa3:     /* mov */
         case 0xa4 ... 0xa5:     /* movs */
                 goto mov;
         case 0xa6 ... 0xa7:     /* cmps */
                 c->dst.type = OP_NONE; /* Disable writeback. */
                 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
                 goto cmp;
+        case 0xa8 ... 0xa9:     /* test ax, imm */
+                goto test;
         case 0xaa ... 0xab:     /* stos */
                 c->dst.val = c->regs[VCPU_REGS_RAX];
                 break;
@@ -2855,19 +2928,23 @@ special_insn:
                 long int rel = c->src.val;
                 c->src.val = (unsigned long) c->eip;
                 jmp_rel(c, rel);
-                emulate_push(ctxt);
+                emulate_push(ctxt, ops);
                 break;
         }
         case 0xe9: /* jmp rel */
                 goto jmp;
-        case 0xea: /* jmp far */
+        case 0xea: { /* jmp far */
+                unsigned short sel;
         jump_far:
-                if (load_segment_descriptor(ctxt, ops, c->src2.val,
-                                            VCPU_SREG_CS))
+                memcpy(&sel, c->src.valptr + c->op_bytes, 2);
+
+                if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
                         goto done;
 
-                c->eip = c->src.val;
+                c->eip = 0;
+                memcpy(&c->eip, c->src.valptr, c->op_bytes);
                 break;
+        }
         case 0xeb:
               jmp:              /* jmp rel short */
                 jmp_rel(c, c->src.val);
@@ -2879,20 +2956,20 @@ special_insn:
         do_io_in:
                 c->dst.bytes = min(c->dst.bytes, 4u);
                 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         goto done;
                 }
                 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
                                      &c->dst.val))
                         goto done; /* IO is needed */
                 break;
-        case 0xee: /* out al,dx */
-        case 0xef: /* out (e/r)ax,dx */
+        case 0xee: /* out dx,al */
+        case 0xef: /* out dx,(e/r)ax */
                 c->src.val = c->regs[VCPU_REGS_RDX];
         do_io_out:
                 c->dst.bytes = min(c->dst.bytes, 4u);
                 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                        emulate_gp(ctxt, 0);
                         goto done;
                 }
                 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
@@ -2916,18 +2993,20 @@ special_insn:
                 c->dst.type = OP_NONE;  /* Disable writeback. */
                 break;
         case 0xfa: /* cli */
-                if (emulator_bad_iopl(ctxt, ops))
-                        kvm_inject_gp(ctxt->vcpu, 0);
-                else {
+                if (emulator_bad_iopl(ctxt, ops)) {
+                        emulate_gp(ctxt, 0);
+                        goto done;
+                } else {
                         ctxt->eflags &= ~X86_EFLAGS_IF;
                         c->dst.type = OP_NONE;  /* Disable writeback. */
                 }
                 break;
         case 0xfb: /* sti */
-                if (emulator_bad_iopl(ctxt, ops))
-                        kvm_inject_gp(ctxt->vcpu, 0);
-                else {
-                        toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI);
+                if (emulator_bad_iopl(ctxt, ops)) {
+                        emulate_gp(ctxt, 0);
+                        goto done;
+                } else {
+                        ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
                         ctxt->eflags |= X86_EFLAGS_IF;
                         c->dst.type = OP_NONE;  /* Disable writeback. */
                 }
@@ -2964,11 +3043,12 @@ writeback:
         c->dst.type = saved_dst_type;
 
         if ((c->d & SrcMask) == SrcSI)
-                string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI,
-                                &c->src);
+                string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
+                                VCPU_REGS_RSI, &c->src);
 
         if ((c->d & DstMask) == DstDI)
-                string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst);
+                string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
+                                &c->dst);
 
         if (c->rep_prefix && (c->d & String)) {
                 struct read_cache *rc = &ctxt->decode.io_read;
@@ -2981,11 +3061,12 @@ writeback:
                     (rc->end != 0 && rc->end == rc->pos))
                         ctxt->restart = false;
         }
-
-        /* Commit shadow register state. */
-        memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
-        kvm_rip_write(ctxt->vcpu, c->eip);
-        ops->set_rflags(ctxt->vcpu, ctxt->eflags);
+        /*
+         * reset read cache here in case string instruction is restared
+         * without decoding
+         */
+        ctxt->decode.mem_read.end = 0;
+        ctxt->eip = c->eip;
 
 done:
         return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
@@ -3051,7 +3132,7 @@ twobyte_insn:
                         c->dst.type = OP_NONE;
                         break;
                 case 5: /* not defined */
-                        kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                        emulate_ud(ctxt);
                         goto done;
                 case 7: /* invlpg*/
                         emulate_invlpg(ctxt->vcpu, c->modrm_ea);
@@ -3063,7 +3144,7 @@ twobyte_insn:
                 }
                 break;
         case 0x05:              /* syscall */
-                rc = emulate_syscall(ctxt);
+                rc = emulate_syscall(ctxt, ops);
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
                 else
@@ -3073,8 +3154,11 @@ twobyte_insn:
                 emulate_clts(ctxt->vcpu);
                 c->dst.type = OP_NONE;
                 break;
-        case 0x08:              /* invd */
         case 0x09:              /* wbinvd */
+                kvm_emulate_wbinvd(ctxt->vcpu);
+                c->dst.type = OP_NONE;
+                break;
+        case 0x08:              /* invd */
         case 0x0d:              /* GrpP (prefetch) */
         case 0x18:              /* Grp16 (prefetch/nop) */
                 c->dst.type = OP_NONE;
@@ -3084,7 +3168,7 @@ twobyte_insn:
                 case 1:
                 case 5 ... 7:
                 case 9 ... 15:
-                        kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                        emulate_ud(ctxt);
                         goto done;
                 }
                 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
@@ -3093,31 +3177,42 @@ twobyte_insn:
         case 0x21: /* mov from dr to reg */
                 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
                     (c->modrm_reg == 4 || c->modrm_reg == 5)) {
-                        kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                        emulate_ud(ctxt);
                         goto done;
                 }
-                emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
+                ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
                 c->dst.type = OP_NONE;  /* no writeback */
                 break;
         case 0x22: /* mov reg, cr */
-                ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu);
+                if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
+                        emulate_gp(ctxt, 0);
+                        goto done;
+                }
                 c->dst.type = OP_NONE;
                 break;
         case 0x23: /* mov from reg to dr */
                 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
                     (c->modrm_reg == 4 || c->modrm_reg == 5)) {
-                        kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
+                        emulate_ud(ctxt);
+                        goto done;
+                }
+
+                if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
+                                ((ctxt->mode == X86EMUL_MODE_PROT64) ?
+                                 ~0ULL : ~0U), ctxt->vcpu) < 0) {
+                        /* #UD condition is already handled by the code above */
+                        emulate_gp(ctxt, 0);
                         goto done;
                 }
-                emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]);
+
                 c->dst.type = OP_NONE;  /* no writeback */
                 break;
         case 0x30:
                 /* wrmsr */
                 msr_data = (u32)c->regs[VCPU_REGS_RAX]
                         | ((u64)c->regs[VCPU_REGS_RDX] << 32);
-                if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
+                        emulate_gp(ctxt, 0);
                         goto done;
                 }
                 rc = X86EMUL_CONTINUE;
@@ -3125,8 +3220,8 @@ twobyte_insn:
                 break;
         case 0x32:
                 /* rdmsr */
-                if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
-                        kvm_inject_gp(ctxt->vcpu, 0);
+                if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
+                        emulate_gp(ctxt, 0);
                         goto done;
                 } else {
                         c->regs[VCPU_REGS_RAX] = (u32)msr_data;
@@ -3136,14 +3231,14 @@ twobyte_insn:
                 c->dst.type = OP_NONE;
                 break;
         case 0x34:              /* sysenter */
-                rc = emulate_sysenter(ctxt);
+                rc = emulate_sysenter(ctxt, ops);
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
                 else
                         goto writeback;
                 break;
         case 0x35:              /* sysexit */
-                rc = emulate_sysexit(ctxt);
+                rc = emulate_sysexit(ctxt, ops);
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
                 else
@@ -3160,7 +3255,7 @@ twobyte_insn:
                 c->dst.type = OP_NONE;
                 break;
         case 0xa0:        /* push fs */
-                emulate_push_sreg(ctxt, VCPU_SREG_FS);
+                emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
                 break;
         case 0xa1:       /* pop fs */
                 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
@@ -3179,7 +3274,7 @@ twobyte_insn:
                 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
                 break;
         case 0xa8:      /* push gs */
-                emulate_push_sreg(ctxt, VCPU_SREG_GS);
+                emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
                 break;
         case 0xa9:      /* pop gs */
                 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 0150affad25d..0fd6378981f4 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -5,6 +5,7 @@
  * Copyright (c) 2006 Intel Corporation
  * Copyright (c) 2007 Keir Fraser, XenSource Inc
  * Copyright (c) 2008 Intel Corporation
+ * Copyright 2009 Red Hat, Inc. and/or its affilates.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -33,6 +34,7 @@
 
 #include <linux/kvm_host.h>
 #include <linux/slab.h>
+#include <linux/workqueue.h>
 
 #include "irq.h"
 #include "i8254.h"
@@ -243,11 +245,22 @@ static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
 {
         struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
                                                  irq_ack_notifier);
-        raw_spin_lock(&ps->inject_lock);
-        if (atomic_dec_return(&ps->pit_timer.pending) < 0)
+        int value;
+
+        spin_lock(&ps->inject_lock);
+        value = atomic_dec_return(&ps->pit_timer.pending);
+        if (value < 0)
+                /* spurious acks can be generated if, for example, the
+                 * PIC is being reset.  Handle it gracefully here
+                 */
                 atomic_inc(&ps->pit_timer.pending);
+        else if (value > 0)
+                /* in this case, we had multiple outstanding pit interrupts
+                 * that we needed to inject.  Reinject
+                 */
+                queue_work(ps->pit->wq, &ps->pit->expired);
         ps->irq_ack = 1;
-        raw_spin_unlock(&ps->inject_lock);
+        spin_unlock(&ps->inject_lock);
 }
 
 void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
@@ -263,10 +276,10 @@ void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
 }
 
-static void destroy_pit_timer(struct kvm_timer *pt)
+static void destroy_pit_timer(struct kvm_pit *pit)
 {
-        pr_debug("execute del timer!\n");
-        hrtimer_cancel(&pt->timer);
+        hrtimer_cancel(&pit->pit_state.pit_timer.timer);
+        cancel_work_sync(&pit->expired);
 }
 
 static bool kpit_is_periodic(struct kvm_timer *ktimer)
@@ -280,6 +293,60 @@ static struct kvm_timer_ops kpit_ops = {
         .is_periodic = kpit_is_periodic,
 };
 
+static void pit_do_work(struct work_struct *work)
+{
+        struct kvm_pit *pit = container_of(work, struct kvm_pit, expired);
+        struct kvm *kvm = pit->kvm;
+        struct kvm_vcpu *vcpu;
+        int i;
+        struct kvm_kpit_state *ps = &pit->pit_state;
+        int inject = 0;
+
+        /* Try to inject pending interrupts when
+         * last one has been acked.
+         */
+        spin_lock(&ps->inject_lock);
+        if (ps->irq_ack) {
+                ps->irq_ack = 0;
+                inject = 1;
+        }
+        spin_unlock(&ps->inject_lock);
+        if (inject) {
+                kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
+                kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
+
+                /*
+                 * Provides NMI watchdog support via Virtual Wire mode.
+                 * The route is: PIT -> PIC -> LVT0 in NMI mode.
+                 *
+                 * Note: Our Virtual Wire implementation is simplified, only
+                 * propagating PIT interrupts to all VCPUs when they have set
+                 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
+                 * VCPU0, and only if its LVT0 is in EXTINT mode.
+                 */
+                if (kvm->arch.vapics_in_nmi_mode > 0)
+                        kvm_for_each_vcpu(i, vcpu, kvm)
+                                kvm_apic_nmi_wd_deliver(vcpu);
+        }
+}
+
+static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
+{
+        struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
+        struct kvm_pit *pt = ktimer->kvm->arch.vpit;
+
+        if (ktimer->reinject || !atomic_read(&ktimer->pending)) {
+                atomic_inc(&ktimer->pending);
+                queue_work(pt->wq, &pt->expired);
+        }
+
+        if (ktimer->t_ops->is_periodic(ktimer)) {
+                hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
+                return HRTIMER_RESTART;
+        } else
+                return HRTIMER_NORESTART;
+}
+
 static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
 {
         struct kvm_timer *pt = &ps->pit_timer;
@@ -291,13 +358,13 @@ static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
 
         /* TODO The new value only affected after the retriggered */
         hrtimer_cancel(&pt->timer);
+        cancel_work_sync(&ps->pit->expired);
         pt->period = interval;
         ps->is_periodic = is_period;
 
-        pt->timer.function = kvm_timer_fn;
+        pt->timer.function = pit_timer_fn;
         pt->t_ops = &kpit_ops;
         pt->kvm = ps->pit->kvm;
-        pt->vcpu = pt->kvm->bsp_vcpu;
 
         atomic_set(&pt->pending, 0);
         ps->irq_ack = 1;
@@ -346,7 +413,7 @@ static void pit_load_count(struct kvm *kvm, int channel, u32 val)
                 }
                 break;
         default:
-                destroy_pit_timer(&ps->pit_timer);
+                destroy_pit_timer(kvm->arch.vpit);
         }
 }
 
@@ -625,7 +692,15 @@ struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags)
 
         mutex_init(&pit->pit_state.lock);
         mutex_lock(&pit->pit_state.lock);
-        raw_spin_lock_init(&pit->pit_state.inject_lock);
+        spin_lock_init(&pit->pit_state.inject_lock);
+
+        pit->wq = create_singlethread_workqueue("kvm-pit-wq");
+        if (!pit->wq) {
+                mutex_unlock(&pit->pit_state.lock);
+                kfree(pit);
+                return NULL;
+        }
+        INIT_WORK(&pit->expired, pit_do_work);
 
         kvm->arch.vpit = pit;
         pit->kvm = kvm;
@@ -677,6 +752,9 @@ void kvm_free_pit(struct kvm *kvm)
         struct hrtimer *timer;
 
         if (kvm->arch.vpit) {
+                kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &kvm->arch.vpit->dev);
+                kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
+                                              &kvm->arch.vpit->speaker_dev);
                 kvm_unregister_irq_mask_notifier(kvm, 0,
                                                &kvm->arch.vpit->mask_notifier);
                 kvm_unregister_irq_ack_notifier(kvm,
@@ -684,54 +762,10 @@ void kvm_free_pit(struct kvm *kvm)
                 mutex_lock(&kvm->arch.vpit->pit_state.lock);
                 timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
                 hrtimer_cancel(timer);
+                cancel_work_sync(&kvm->arch.vpit->expired);
                 kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
                 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
+                destroy_workqueue(kvm->arch.vpit->wq);
                 kfree(kvm->arch.vpit);
         }
 }
-
-static void __inject_pit_timer_intr(struct kvm *kvm)
-{
-        struct kvm_vcpu *vcpu;
-        int i;
-
-        kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
-        kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
-
-        /*
-         * Provides NMI watchdog support via Virtual Wire mode.
-         * The route is: PIT -> PIC -> LVT0 in NMI mode.
-         *
-         * Note: Our Virtual Wire implementation is simplified, only
-         * propagating PIT interrupts to all VCPUs when they have set
-         * LVT0 to NMI delivery. Other PIC interrupts are just sent to
-         * VCPU0, and only if its LVT0 is in EXTINT mode.
-         */
-        if (kvm->arch.vapics_in_nmi_mode > 0)
-                kvm_for_each_vcpu(i, vcpu, kvm)
-                        kvm_apic_nmi_wd_deliver(vcpu);
-}
-
-void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
-{
-        struct kvm_pit *pit = vcpu->kvm->arch.vpit;
-        struct kvm *kvm = vcpu->kvm;
-        struct kvm_kpit_state *ps;
-
-        if (pit) {
-                int inject = 0;
-                ps = &pit->pit_state;
-
-                /* Try to inject pending interrupts when
-                 * last one has been acked.
-                 */
-                raw_spin_lock(&ps->inject_lock);
-                if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
-                        ps->irq_ack = 0;
-                        inject = 1;
-                }
-                raw_spin_unlock(&ps->inject_lock);
-                if (inject)
-                        __inject_pit_timer_intr(kvm);
-        }
-}
diff --git a/arch/x86/kvm/i8254.h b/arch/x86/kvm/i8254.h
index 900d6b0ba7c2..46d08ca0b48f 100644
--- a/arch/x86/kvm/i8254.h
+++ b/arch/x86/kvm/i8254.h
@@ -27,7 +27,7 @@ struct kvm_kpit_state {
         u32    speaker_data_on;
         struct mutex lock;
         struct kvm_pit *pit;
-        raw_spinlock_t inject_lock;
+        spinlock_t inject_lock;
         unsigned long irq_ack;
         struct kvm_irq_ack_notifier irq_ack_notifier;
 };
@@ -40,6 +40,8 @@ struct kvm_pit {
         struct kvm_kpit_state pit_state;
         int irq_source_id;
         struct kvm_irq_mask_notifier mask_notifier;
+        struct workqueue_struct *wq;
+        struct work_struct expired;
 };
 
 #define KVM_PIT_BASE_ADDRESS        0x40
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index 93825ff3338f..8d10c063d7f2 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -3,6 +3,7 @@
  *
  * Copyright (c) 2003-2004 Fabrice Bellard
  * Copyright (c) 2007 Intel Corporation
+ * Copyright 2009 Red Hat, Inc. and/or its affilates.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -33,6 +34,8 @@
 #include <linux/kvm_host.h>
 #include "trace.h"
 
+static void pic_irq_request(struct kvm *kvm, int level);
+
 static void pic_lock(struct kvm_pic *s)
         __acquires(&s->lock)
 {
@@ -43,16 +46,25 @@ static void pic_unlock(struct kvm_pic *s)
         __releases(&s->lock)
 {
         bool wakeup = s->wakeup_needed;
-        struct kvm_vcpu *vcpu;
+        struct kvm_vcpu *vcpu, *found = NULL;
+        int i;
 
         s->wakeup_needed = false;
 
         raw_spin_unlock(&s->lock);
 
         if (wakeup) {
-                vcpu = s->kvm->bsp_vcpu;
-                if (vcpu)
-                        kvm_vcpu_kick(vcpu);
+                kvm_for_each_vcpu(i, vcpu, s->kvm) {
+                        if (kvm_apic_accept_pic_intr(vcpu)) {
+                                found = vcpu;
+                                break;
+                        }
+                }
+
+                if (!found)
+                        found = s->kvm->bsp_vcpu;
+
+                kvm_vcpu_kick(found);
         }
 }
 
@@ -173,10 +185,7 @@ static void pic_update_irq(struct kvm_pic *s)
                 pic_set_irq1(&s->pics[0], 2, 0);
         }
         irq = pic_get_irq(&s->pics[0]);
-        if (irq >= 0)
-                s->irq_request(s->irq_request_opaque, 1);
-        else
-                s->irq_request(s->irq_request_opaque, 0);
+        pic_irq_request(s->kvm, irq >= 0);
 }
 
 void kvm_pic_update_irq(struct kvm_pic *s)
@@ -261,8 +270,7 @@ int kvm_pic_read_irq(struct kvm *kvm)
 void kvm_pic_reset(struct kvm_kpic_state *s)
 {
         int irq;
-        struct kvm *kvm = s->pics_state->irq_request_opaque;
-        struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu;
+        struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
         u8 irr = s->irr, isr = s->imr;
 
         s->last_irr = 0;
@@ -301,8 +309,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
                         /*
                          * deassert a pending interrupt
                          */
-                        s->pics_state->irq_request(s->pics_state->
-                                                   irq_request_opaque, 0);
+                        pic_irq_request(s->pics_state->kvm, 0);
                         s->init_state = 1;
                         s->init4 = val & 1;
                         if (val & 0x02)
@@ -356,10 +363,20 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
                 }
         } else
                 switch (s->init_state) {
-                case 0:         /* normal mode */
+                case 0: { /* normal mode */
+                        u8 imr_diff = s->imr ^ val,
+                                off = (s == &s->pics_state->pics[0]) ? 0 : 8;
                         s->imr = val;
+                        for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
+                                if (imr_diff & (1 << irq))
+                                        kvm_fire_mask_notifiers(
+                                                s->pics_state->kvm,
+                                                SELECT_PIC(irq + off),
+                                                irq + off,
+                                                !!(s->imr & (1 << irq)));
                         pic_update_irq(s->pics_state);
                         break;
+                }
                 case 1:
                         s->irq_base = val & 0xf8;
                         s->init_state = 2;
@@ -518,9 +535,8 @@ static int picdev_read(struct kvm_io_device *this,
 /*
  * callback when PIC0 irq status changed
  */
-static void pic_irq_request(void *opaque, int level)
+static void pic_irq_request(struct kvm *kvm, int level)
 {
-        struct kvm *kvm = opaque;
         struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
         struct kvm_pic *s = pic_irqchip(kvm);
         int irq = pic_get_irq(&s->pics[0]);
@@ -549,8 +565,6 @@ struct kvm_pic *kvm_create_pic(struct kvm *kvm)
         s->kvm = kvm;
         s->pics[0].elcr_mask = 0xf8;
         s->pics[1].elcr_mask = 0xde;
-        s->irq_request = pic_irq_request;
-        s->irq_request_opaque = kvm;
         s->pics[0].pics_state = s;
         s->pics[1].pics_state = s;
 
diff --git a/arch/x86/kvm/irq.c b/arch/x86/kvm/irq.c
index 96dfbb6ad2a9..2095a049835e 100644
--- a/arch/x86/kvm/irq.c
+++ b/arch/x86/kvm/irq.c
@@ -1,6 +1,7 @@
 /*
  * irq.c: API for in kernel interrupt controller
  * Copyright (c) 2007, Intel Corporation.
+ * Copyright 2009 Red Hat, Inc. and/or its affilates.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -89,7 +90,6 @@ EXPORT_SYMBOL_GPL(kvm_cpu_get_interrupt);
 void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu)
 {
         kvm_inject_apic_timer_irqs(vcpu);
-        kvm_inject_pit_timer_irqs(vcpu);
         /* TODO: PIT, RTC etc. */
 }
 EXPORT_SYMBOL_GPL(kvm_inject_pending_timer_irqs);
diff --git a/arch/x86/kvm/irq.h b/arch/x86/kvm/irq.h
index cd1f362f413d..ffed06871c5c 100644
--- a/arch/x86/kvm/irq.h
+++ b/arch/x86/kvm/irq.h
@@ -38,8 +38,6 @@
 struct kvm;
 struct kvm_vcpu;
 
-typedef void irq_request_func(void *opaque, int level);
-
 struct kvm_kpic_state {
         u8 last_irr;    /* edge detection */
         u8 irr;         /* interrupt request register */
@@ -67,8 +65,6 @@ struct kvm_pic {
         unsigned pending_acks;
         struct kvm *kvm;
         struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
-        irq_request_func *irq_request;
-        void *irq_request_opaque;
         int output;             /* intr from master PIC */
         struct kvm_io_device dev;
         void (*ack_notifier)(void *opaque, int irq);
diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h
index cff851cf5322..6491ac8e755b 100644
--- a/arch/x86/kvm/kvm_cache_regs.h
+++ b/arch/x86/kvm/kvm_cache_regs.h
@@ -36,6 +36,8 @@ static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val)
 
 static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index)
 {
+        might_sleep();  /* on svm */
+
         if (!test_bit(VCPU_EXREG_PDPTR,
                       (unsigned long *)&vcpu->arch.regs_avail))
                 kvm_x86_ops->cache_reg(vcpu, VCPU_EXREG_PDPTR);
@@ -69,4 +71,10 @@ static inline ulong kvm_read_cr4(struct kvm_vcpu *vcpu)
         return kvm_read_cr4_bits(vcpu, ~0UL);
 }
 
+static inline u64 kvm_read_edx_eax(struct kvm_vcpu *vcpu)
+{
+        return (kvm_register_read(vcpu, VCPU_REGS_RAX) & -1u)
+                | ((u64)(kvm_register_read(vcpu, VCPU_REGS_RDX) & -1u) << 32);
+}
+
 #endif
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 1eb7a4ae0c9c..77d8c0f4817d 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2006 Qumranet, Inc.
  * Copyright (C) 2007 Novell
  * Copyright (C) 2007 Intel
+ * Copyright 2009 Red Hat, Inc. and/or its affilates.
  *
  * Authors:
  *   Dor Laor <dor.laor@qumranet.com>
@@ -328,7 +329,7 @@ int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
                    "dest_mode 0x%x, short_hand 0x%x\n",
                    target, source, dest, dest_mode, short_hand);
 
-        ASSERT(!target);
+        ASSERT(target);
         switch (short_hand) {
         case APIC_DEST_NOSHORT:
                 if (dest_mode == 0)
@@ -533,7 +534,7 @@ static void __report_tpr_access(struct kvm_lapic *apic, bool write)
         struct kvm_vcpu *vcpu = apic->vcpu;
         struct kvm_run *run = vcpu->run;
 
-        set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
+        kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
         run->tpr_access.rip = kvm_rip_read(vcpu);
         run->tpr_access.is_write = write;
 }
@@ -1106,13 +1107,11 @@ int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
         int r = 0;
 
-        if (kvm_vcpu_is_bsp(vcpu)) {
-                if (!apic_hw_enabled(vcpu->arch.apic))
-                        r = 1;
-                if ((lvt0 & APIC_LVT_MASKED) == 0 &&
-                    GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
-                        r = 1;
-        }
+        if (!apic_hw_enabled(vcpu->arch.apic))
+                r = 1;
+        if ((lvt0 & APIC_LVT_MASKED) == 0 &&
+            GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
+                r = 1;
         return r;
 }
 
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index b1ed0a1a5913..311f6dad8951 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -7,6 +7,7 @@
  * MMU support
  *
  * Copyright (C) 2006 Qumranet, Inc.
+ * Copyright 2010 Red Hat, Inc. and/or its affilates.
  *
  * Authors:
  *   Yaniv Kamay  <yaniv@qumranet.com>
@@ -32,6 +33,7 @@
 #include <linux/compiler.h>
 #include <linux/srcu.h>
 #include <linux/slab.h>
+#include <linux/uaccess.h>
 
 #include <asm/page.h>
 #include <asm/cmpxchg.h>
@@ -90,8 +92,6 @@ module_param(oos_shadow, bool, 0644);
 #define PT_FIRST_AVAIL_BITS_SHIFT 9
 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 
-#define VALID_PAGE(x) ((x) != INVALID_PAGE)
-
 #define PT64_LEVEL_BITS 9
 
 #define PT64_LEVEL_SHIFT(level) \
@@ -173,7 +173,7 @@ struct kvm_shadow_walk_iterator {
              shadow_walk_okay(&(_walker));                      \
              shadow_walk_next(&(_walker)))
 
-typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp);
+typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte);
 
 static struct kmem_cache *pte_chain_cache;
 static struct kmem_cache *rmap_desc_cache;
@@ -281,13 +281,38 @@ static gfn_t pse36_gfn_delta(u32 gpte)
 
 static void __set_spte(u64 *sptep, u64 spte)
 {
+        set_64bit(sptep, spte);
+}
+
+static u64 __xchg_spte(u64 *sptep, u64 new_spte)
+{
 #ifdef CONFIG_X86_64
-        set_64bit((unsigned long *)sptep, spte);
+        return xchg(sptep, new_spte);
 #else
-        set_64bit((unsigned long long *)sptep, spte);
+        u64 old_spte;
+
+        do {
+                old_spte = *sptep;
+        } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte);
+
+        return old_spte;
 #endif
 }
 
+static void update_spte(u64 *sptep, u64 new_spte)
+{
+        u64 old_spte;
+
+        if (!shadow_accessed_mask || (new_spte & shadow_accessed_mask) ||
+              !is_rmap_spte(*sptep))
+                __set_spte(sptep, new_spte);
+        else {
+                old_spte = __xchg_spte(sptep, new_spte);
+                if (old_spte & shadow_accessed_mask)
+                        mark_page_accessed(pfn_to_page(spte_to_pfn(old_spte)));
+        }
+}
+
 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
                                   struct kmem_cache *base_cache, int min)
 {
@@ -304,10 +329,11 @@ static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
         return 0;
 }
 
-static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
+static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
+                                  struct kmem_cache *cache)
 {
         while (mc->nobjs)
-                kfree(mc->objects[--mc->nobjs]);
+                kmem_cache_free(cache, mc->objects[--mc->nobjs]);
 }
 
 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
@@ -355,10 +381,11 @@ out:
 
 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
 {
-        mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
-        mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
+        mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
+        mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
-        mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
+        mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
+                                mmu_page_header_cache);
 }
 
 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
@@ -379,7 +406,7 @@ static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
 
 static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
 {
-        kfree(pc);
+        kmem_cache_free(pte_chain_cache, pc);
 }
 
 static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
@@ -390,7 +417,23 @@ static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
 
 static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
 {
-        kfree(rd);
+        kmem_cache_free(rmap_desc_cache, rd);
+}
+
+static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
+{
+        if (!sp->role.direct)
+                return sp->gfns[index];
+
+        return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
+}
+
+static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
+{
+        if (sp->role.direct)
+                BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
+        else
+                sp->gfns[index] = gfn;
 }
 
 /*
@@ -403,8 +446,8 @@ static int *slot_largepage_idx(gfn_t gfn,
 {
         unsigned long idx;
 
-        idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
-              (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
+        idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
+              (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
         return &slot->lpage_info[level - 2][idx].write_count;
 }
 
@@ -414,9 +457,7 @@ static void account_shadowed(struct kvm *kvm, gfn_t gfn)
         int *write_count;
         int i;
 
-        gfn = unalias_gfn(kvm, gfn);
-
-        slot = gfn_to_memslot_unaliased(kvm, gfn);
+        slot = gfn_to_memslot(kvm, gfn);
         for (i = PT_DIRECTORY_LEVEL;
              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
                 write_count   = slot_largepage_idx(gfn, slot, i);
@@ -430,8 +471,7 @@ static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
         int *write_count;
         int i;
 
-        gfn = unalias_gfn(kvm, gfn);
-        slot = gfn_to_memslot_unaliased(kvm, gfn);
+        slot = gfn_to_memslot(kvm, gfn);
         for (i = PT_DIRECTORY_LEVEL;
              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
                 write_count   = slot_largepage_idx(gfn, slot, i);
@@ -447,8 +487,7 @@ static int has_wrprotected_page(struct kvm *kvm,
         struct kvm_memory_slot *slot;
         int *largepage_idx;
 
-        gfn = unalias_gfn(kvm, gfn);
-        slot = gfn_to_memslot_unaliased(kvm, gfn);
+        slot = gfn_to_memslot(kvm, gfn);
         if (slot) {
                 largepage_idx = slot_largepage_idx(gfn, slot, level);
                 return *largepage_idx;
@@ -501,7 +540,6 @@ static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 
 /*
  * Take gfn and return the reverse mapping to it.
- * Note: gfn must be unaliased before this function get called
  */
 
 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
@@ -513,8 +551,8 @@ static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
         if (likely(level == PT_PAGE_TABLE_LEVEL))
                 return &slot->rmap[gfn - slot->base_gfn];
 
-        idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
-                (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
+        idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
+                (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
 
         return &slot->lpage_info[level - 2][idx].rmap_pde;
 }
@@ -541,9 +579,8 @@ static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 
         if (!is_rmap_spte(*spte))
                 return count;
-        gfn = unalias_gfn(vcpu->kvm, gfn);
         sp = page_header(__pa(spte));
-        sp->gfns[spte - sp->spt] = gfn;
+        kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
         if (!*rmapp) {
                 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
@@ -600,19 +637,13 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
         struct kvm_rmap_desc *desc;
         struct kvm_rmap_desc *prev_desc;
         struct kvm_mmu_page *sp;
-        pfn_t pfn;
+        gfn_t gfn;
         unsigned long *rmapp;
         int i;
 
-        if (!is_rmap_spte(*spte))
-                return;
         sp = page_header(__pa(spte));
-        pfn = spte_to_pfn(*spte);
-        if (*spte & shadow_accessed_mask)
-                kvm_set_pfn_accessed(pfn);
-        if (is_writable_pte(*spte))
-                kvm_set_pfn_dirty(pfn);
-        rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
+        gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
+        rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
         if (!*rmapp) {
                 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
                 BUG();
@@ -644,6 +675,32 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
         }
 }
 
+static void set_spte_track_bits(u64 *sptep, u64 new_spte)
+{
+        pfn_t pfn;
+        u64 old_spte = *sptep;
+
+        if (!shadow_accessed_mask || !is_shadow_present_pte(old_spte) ||
+              old_spte & shadow_accessed_mask) {
+                __set_spte(sptep, new_spte);
+        } else
+                old_spte = __xchg_spte(sptep, new_spte);
+
+        if (!is_rmap_spte(old_spte))
+                return;
+        pfn = spte_to_pfn(old_spte);
+        if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
+                kvm_set_pfn_accessed(pfn);
+        if (is_writable_pte(old_spte))
+                kvm_set_pfn_dirty(pfn);
+}
+
+static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
+{
+        set_spte_track_bits(sptep, new_spte);
+        rmap_remove(kvm, sptep);
+}
+
 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
 {
         struct kvm_rmap_desc *desc;
@@ -676,7 +733,6 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
         u64 *spte;
         int i, write_protected = 0;
 
-        gfn = unalias_gfn(kvm, gfn);
         rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
 
         spte = rmap_next(kvm, rmapp, NULL);
@@ -685,7 +741,7 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
                 BUG_ON(!(*spte & PT_PRESENT_MASK));
                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
                 if (is_writable_pte(*spte)) {
-                        __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
+                        update_spte(spte, *spte & ~PT_WRITABLE_MASK);
                         write_protected = 1;
                 }
                 spte = rmap_next(kvm, rmapp, spte);
@@ -709,9 +765,9 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
                         BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
                         pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
                         if (is_writable_pte(*spte)) {
-                                rmap_remove(kvm, spte);
+                                drop_spte(kvm, spte,
+                                          shadow_trap_nonpresent_pte);
                                 --kvm->stat.lpages;
-                                __set_spte(spte, shadow_trap_nonpresent_pte);
                                 spte = NULL;
                                 write_protected = 1;
                         }
@@ -731,8 +787,7 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
         while ((spte = rmap_next(kvm, rmapp, NULL))) {
                 BUG_ON(!(*spte & PT_PRESENT_MASK));
                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
-                rmap_remove(kvm, spte);
-                __set_spte(spte, shadow_trap_nonpresent_pte);
+                drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
                 need_tlb_flush = 1;
         }
         return need_tlb_flush;
@@ -754,8 +809,7 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
                 need_flush = 1;
                 if (pte_write(*ptep)) {
-                        rmap_remove(kvm, spte);
-                        __set_spte(spte, shadow_trap_nonpresent_pte);
+                        drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
                         spte = rmap_next(kvm, rmapp, NULL);
                 } else {
                         new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
@@ -763,9 +817,8 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
 
                         new_spte &= ~PT_WRITABLE_MASK;
                         new_spte &= ~SPTE_HOST_WRITEABLE;
-                        if (is_writable_pte(*spte))
-                                kvm_set_pfn_dirty(spte_to_pfn(*spte));
-                        __set_spte(spte, new_spte);
+                        new_spte &= ~shadow_accessed_mask;
+                        set_spte_track_bits(spte, new_spte);
                         spte = rmap_next(kvm, rmapp, spte);
                 }
         }
@@ -799,8 +852,12 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
                         ret = handler(kvm, &memslot->rmap[gfn_offset], data);
 
                         for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
-                                int idx = gfn_offset;
-                                idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
+                                unsigned long idx;
+                                int sh;
+
+                                sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j);
+                                idx = ((memslot->base_gfn+gfn_offset) >> sh) -
+                                        (memslot->base_gfn >> sh);
                                 ret |= handler(kvm,
                                         &memslot->lpage_info[j][idx].rmap_pde,
                                         data);
@@ -863,7 +920,6 @@ static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 
         sp = page_header(__pa(spte));
 
-        gfn = unalias_gfn(vcpu->kvm, gfn);
         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
 
         kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
@@ -894,10 +950,12 @@ static int is_empty_shadow_page(u64 *spt)
 static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
 {
         ASSERT(is_empty_shadow_page(sp->spt));
+        hlist_del(&sp->hash_link);
         list_del(&sp->link);
         __free_page(virt_to_page(sp->spt));
-        __free_page(virt_to_page(sp->gfns));
-        kfree(sp);
+        if (!sp->role.direct)
+                __free_page(virt_to_page(sp->gfns));
+        kmem_cache_free(mmu_page_header_cache, sp);
         ++kvm->arch.n_free_mmu_pages;
 }
 
@@ -907,13 +965,15 @@ static unsigned kvm_page_table_hashfn(gfn_t gfn)
 }
 
 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
-                                               u64 *parent_pte)
+                                               u64 *parent_pte, int direct)
 {
         struct kvm_mmu_page *sp;
 
         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
-        sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
+        if (!direct)
+                sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
+                                                  PAGE_SIZE);
         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
         bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
@@ -998,7 +1058,6 @@ static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
         BUG();
 }
 
-
 static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
 {
         struct kvm_pte_chain *pte_chain;
@@ -1008,63 +1067,37 @@ static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
 
         if (!sp->multimapped && sp->parent_pte) {
                 parent_sp = page_header(__pa(sp->parent_pte));
-                fn(parent_sp);
-                mmu_parent_walk(parent_sp, fn);
+                fn(parent_sp, sp->parent_pte);
                 return;
         }
+
         hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
                 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
-                        if (!pte_chain->parent_ptes[i])
+                        u64 *spte = pte_chain->parent_ptes[i];
+
+                        if (!spte)
                                 break;
-                        parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
-                        fn(parent_sp);
-                        mmu_parent_walk(parent_sp, fn);
+                        parent_sp = page_header(__pa(spte));
+                        fn(parent_sp, spte);
                 }
 }
 
-static void kvm_mmu_update_unsync_bitmap(u64 *spte)
+static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte);
+static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
 {
-        unsigned int index;
-        struct kvm_mmu_page *sp = page_header(__pa(spte));
-
-        index = spte - sp->spt;
-        if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
-                sp->unsync_children++;
-        WARN_ON(!sp->unsync_children);
+        mmu_parent_walk(sp, mark_unsync);
 }
 
-static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
+static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte)
 {
-        struct kvm_pte_chain *pte_chain;
-        struct hlist_node *node;
-        int i;
+        unsigned int index;
 
-        if (!sp->parent_pte)
+        index = spte - sp->spt;
+        if (__test_and_set_bit(index, sp->unsync_child_bitmap))
                 return;
-
-        if (!sp->multimapped) {
-                kvm_mmu_update_unsync_bitmap(sp->parent_pte);
+        if (sp->unsync_children++)
                 return;
-        }
-
-        hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
-                for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
-                        if (!pte_chain->parent_ptes[i])
-                                break;
-                        kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
-                }
-}
-
-static int unsync_walk_fn(struct kvm_mmu_page *sp)
-{
-        kvm_mmu_update_parents_unsync(sp);
-        return 1;
-}
-
-static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
-{
-        mmu_parent_walk(sp, unsync_walk_fn);
-        kvm_mmu_update_parents_unsync(sp);
+        kvm_mmu_mark_parents_unsync(sp);
 }
 
 static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
@@ -1077,7 +1110,7 @@ static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
 }
 
 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
-                               struct kvm_mmu_page *sp)
+                               struct kvm_mmu_page *sp, bool clear_unsync)
 {
         return 1;
 }
@@ -1123,35 +1156,40 @@ static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
         int i, ret, nr_unsync_leaf = 0;
 
         for_each_unsync_children(sp->unsync_child_bitmap, i) {
+                struct kvm_mmu_page *child;
                 u64 ent = sp->spt[i];
 
-                if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
-                        struct kvm_mmu_page *child;
-                        child = page_header(ent & PT64_BASE_ADDR_MASK);
-
-                        if (child->unsync_children) {
-                                if (mmu_pages_add(pvec, child, i))
-                                        return -ENOSPC;
-
-                                ret = __mmu_unsync_walk(child, pvec);
-                                if (!ret)
-                                        __clear_bit(i, sp->unsync_child_bitmap);
-                                else if (ret > 0)
-                                        nr_unsync_leaf += ret;
-                                else
-                                        return ret;
-                        }
+                if (!is_shadow_present_pte(ent) || is_large_pte(ent))
+                        goto clear_child_bitmap;
+
+                child = page_header(ent & PT64_BASE_ADDR_MASK);
+
+                if (child->unsync_children) {
+                        if (mmu_pages_add(pvec, child, i))
+                                return -ENOSPC;
+
+                        ret = __mmu_unsync_walk(child, pvec);
+                        if (!ret)
+                                goto clear_child_bitmap;
+                        else if (ret > 0)
+                                nr_unsync_leaf += ret;
+                        else
+                                return ret;
+                } else if (child->unsync) {
+                        nr_unsync_leaf++;
+                        if (mmu_pages_add(pvec, child, i))
+                                return -ENOSPC;
+                } else
+                         goto clear_child_bitmap;
 
-                        if (child->unsync) {
-                                nr_unsync_leaf++;
-                                if (mmu_pages_add(pvec, child, i))
-                                        return -ENOSPC;
-                        }
-                }
+                continue;
+
+clear_child_bitmap:
+                __clear_bit(i, sp->unsync_child_bitmap);
+                sp->unsync_children--;
+                WARN_ON((int)sp->unsync_children < 0);
         }
 
-        if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
-                sp->unsync_children = 0;
 
         return nr_unsync_leaf;
 }
@@ -1166,26 +1204,6 @@ static int mmu_unsync_walk(struct kvm_mmu_page *sp,
         return __mmu_unsync_walk(sp, pvec);
 }
 
-static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
-{
-        unsigned index;
-        struct hlist_head *bucket;
-        struct kvm_mmu_page *sp;
-        struct hlist_node *node;
-
-        pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
-        index = kvm_page_table_hashfn(gfn);
-        bucket = &kvm->arch.mmu_page_hash[index];
-        hlist_for_each_entry(sp, node, bucket, hash_link)
-                if (sp->gfn == gfn && !sp->role.direct
-                    && !sp->role.invalid) {
-                        pgprintk("%s: found role %x\n",
-                                 __func__, sp->role.word);
-                        return sp;
-                }
-        return NULL;
-}
-
 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
 {
         WARN_ON(!sp->unsync);
@@ -1194,20 +1212,36 @@ static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
         --kvm->stat.mmu_unsync;
 }
 
-static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
+static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
+                                    struct list_head *invalid_list);
+static void kvm_mmu_commit_zap_page(struct kvm *kvm,
+                                    struct list_head *invalid_list);
 
-static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
+#define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
+  hlist_for_each_entry(sp, pos,                                         \
+   &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
+        if ((sp)->gfn != (gfn)) {} else
+
+#define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
+  hlist_for_each_entry(sp, pos,                                         \
+   &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
+                if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
+                        (sp)->role.invalid) {} else
+
+/* @sp->gfn should be write-protected at the call site */
+static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
+                           struct list_head *invalid_list, bool clear_unsync)
 {
         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
-                kvm_mmu_zap_page(vcpu->kvm, sp);
+                kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
                 return 1;
         }
 
-        if (rmap_write_protect(vcpu->kvm, sp->gfn))
-                kvm_flush_remote_tlbs(vcpu->kvm);
-        kvm_unlink_unsync_page(vcpu->kvm, sp);
-        if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
-                kvm_mmu_zap_page(vcpu->kvm, sp);
+        if (clear_unsync)
+                kvm_unlink_unsync_page(vcpu->kvm, sp);
+
+        if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) {
+                kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
                 return 1;
         }
 
@@ -1215,6 +1249,52 @@ static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
         return 0;
 }
 
+static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
+                                   struct kvm_mmu_page *sp)
+{
+        LIST_HEAD(invalid_list);
+        int ret;
+
+        ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
+        if (ret)
+                kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
+
+        return ret;
+}
+
+static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
+                         struct list_head *invalid_list)
+{
+        return __kvm_sync_page(vcpu, sp, invalid_list, true);
+}
+
+/* @gfn should be write-protected at the call site */
+static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
+{
+        struct kvm_mmu_page *s;
+        struct hlist_node *node;
+        LIST_HEAD(invalid_list);
+        bool flush = false;
+
+        for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
+                if (!s->unsync)
+                        continue;
+
+                WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
+                if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
+                        (vcpu->arch.mmu.sync_page(vcpu, s, true))) {
+                        kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
+                        continue;
+                }
+                kvm_unlink_unsync_page(vcpu->kvm, s);
+                flush = true;
+        }
+
+        kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
+        if (flush)
+                kvm_mmu_flush_tlb(vcpu);
+}
+
 struct mmu_page_path {
         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
         unsigned int idx[PT64_ROOT_LEVEL-1];
@@ -1281,6 +1361,7 @@ static void mmu_sync_children(struct kvm_vcpu *vcpu,
         struct kvm_mmu_page *sp;
         struct mmu_page_path parents;
         struct kvm_mmu_pages pages;
+        LIST_HEAD(invalid_list);
 
         kvm_mmu_pages_init(parent, &parents, &pages);
         while (mmu_unsync_walk(parent, &pages)) {
@@ -1293,9 +1374,10 @@ static void mmu_sync_children(struct kvm_vcpu *vcpu,
                         kvm_flush_remote_tlbs(vcpu->kvm);
 
                 for_each_sp(pages, sp, parents, i) {
-                        kvm_sync_page(vcpu, sp);
+                        kvm_sync_page(vcpu, sp, &invalid_list);
                         mmu_pages_clear_parents(&parents);
                 }
+                kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
                 cond_resched_lock(&vcpu->kvm->mmu_lock);
                 kvm_mmu_pages_init(parent, &parents, &pages);
         }
@@ -1310,11 +1392,10 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                                              u64 *parent_pte)
 {
         union kvm_mmu_page_role role;
-        unsigned index;
         unsigned quadrant;
-        struct hlist_head *bucket;
         struct kvm_mmu_page *sp;
-        struct hlist_node *node, *tmp;
+        struct hlist_node *node;
+        bool need_sync = false;
 
         role = vcpu->arch.mmu.base_role;
         role.level = level;
@@ -1322,40 +1403,45 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
         if (role.direct)
                 role.cr4_pae = 0;
         role.access = access;
-        if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
+        if (!tdp_enabled && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
                 role.quadrant = quadrant;
         }
-        index = kvm_page_table_hashfn(gfn);
-        bucket = &vcpu->kvm->arch.mmu_page_hash[index];
-        hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
-                if (sp->gfn == gfn) {
-                        if (sp->unsync)
-                                if (kvm_sync_page(vcpu, sp))
-                                        continue;
+        for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
+                if (!need_sync && sp->unsync)
+                        need_sync = true;
 
-                        if (sp->role.word != role.word)
-                                continue;
+                if (sp->role.word != role.word)
+                        continue;
 
-                        mmu_page_add_parent_pte(vcpu, sp, parent_pte);
-                        if (sp->unsync_children) {
-                                set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
-                                kvm_mmu_mark_parents_unsync(sp);
-                        }
-                        trace_kvm_mmu_get_page(sp, false);
-                        return sp;
-                }
+                if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
+                        break;
+
+                mmu_page_add_parent_pte(vcpu, sp, parent_pte);
+                if (sp->unsync_children) {
+                        kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
+                        kvm_mmu_mark_parents_unsync(sp);
+                } else if (sp->unsync)
+                        kvm_mmu_mark_parents_unsync(sp);
+
+                trace_kvm_mmu_get_page(sp, false);
+                return sp;
+        }
         ++vcpu->kvm->stat.mmu_cache_miss;
-        sp = kvm_mmu_alloc_page(vcpu, parent_pte);
+        sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
         if (!sp)
                 return sp;
         sp->gfn = gfn;
         sp->role = role;
-        hlist_add_head(&sp->hash_link, bucket);
+        hlist_add_head(&sp->hash_link,
+                &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
         if (!direct) {
                 if (rmap_write_protect(vcpu->kvm, gfn))
                         kvm_flush_remote_tlbs(vcpu->kvm);
+                if (level > PT_PAGE_TABLE_LEVEL && need_sync)
+                        kvm_sync_pages(vcpu, gfn);
+
                 account_shadowed(vcpu->kvm, gfn);
         }
         if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
@@ -1402,6 +1488,47 @@ static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
         --iterator->level;
 }
 
+static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
+{
+        u64 spte;
+
+        spte = __pa(sp->spt)
+                | PT_PRESENT_MASK | PT_ACCESSED_MASK
+                | PT_WRITABLE_MASK | PT_USER_MASK;
+        __set_spte(sptep, spte);
+}
+
+static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
+{
+        if (is_large_pte(*sptep)) {
+                drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
+                kvm_flush_remote_tlbs(vcpu->kvm);
+        }
+}
+
+static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
+                                   unsigned direct_access)
+{
+        if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
+                struct kvm_mmu_page *child;
+
+                /*
+                 * For the direct sp, if the guest pte's dirty bit
+                 * changed form clean to dirty, it will corrupt the
+                 * sp's access: allow writable in the read-only sp,
+                 * so we should update the spte at this point to get
+                 * a new sp with the correct access.
+                 */
+                child = page_header(*sptep & PT64_BASE_ADDR_MASK);
+                if (child->role.access == direct_access)
+                        return;
+
+                mmu_page_remove_parent_pte(child, sptep);
+                __set_spte(sptep, shadow_trap_nonpresent_pte);
+                kvm_flush_remote_tlbs(vcpu->kvm);
+        }
+}
+
 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
                                          struct kvm_mmu_page *sp)
 {
@@ -1422,7 +1549,8 @@ static void kvm_mmu_page_unlink_children(struct kvm *kvm,
                         } else {
                                 if (is_large_pte(ent))
                                         --kvm->stat.lpages;
-                                rmap_remove(kvm, &pt[i]);
+                                drop_spte(kvm, &pt[i],
+                                          shadow_trap_nonpresent_pte);
                         }
                 }
                 pt[i] = shadow_trap_nonpresent_pte;
@@ -1464,7 +1592,8 @@ static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
 }
 
 static int mmu_zap_unsync_children(struct kvm *kvm,
-                                   struct kvm_mmu_page *parent)
+                                   struct kvm_mmu_page *parent,
+                                   struct list_head *invalid_list)
 {
         int i, zapped = 0;
         struct mmu_page_path parents;
@@ -1478,7 +1607,7 @@ static int mmu_zap_unsync_children(struct kvm *kvm,
                 struct kvm_mmu_page *sp;
 
                 for_each_sp(pages, sp, parents, i) {
-                        kvm_mmu_zap_page(kvm, sp);
+                        kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
                         mmu_pages_clear_parents(&parents);
                         zapped++;
                 }
@@ -1488,32 +1617,52 @@ static int mmu_zap_unsync_children(struct kvm *kvm,
         return zapped;
 }
 
-static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
+static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
+                                    struct list_head *invalid_list)
 {
         int ret;
 
-        trace_kvm_mmu_zap_page(sp);
+        trace_kvm_mmu_prepare_zap_page(sp);
         ++kvm->stat.mmu_shadow_zapped;
-        ret = mmu_zap_unsync_children(kvm, sp);
+        ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
         kvm_mmu_page_unlink_children(kvm, sp);
         kvm_mmu_unlink_parents(kvm, sp);
-        kvm_flush_remote_tlbs(kvm);
         if (!sp->role.invalid && !sp->role.direct)
                 unaccount_shadowed(kvm, sp->gfn);
         if (sp->unsync)
                 kvm_unlink_unsync_page(kvm, sp);
         if (!sp->root_count) {
-                hlist_del(&sp->hash_link);
-                kvm_mmu_free_page(kvm, sp);
+                /* Count self */
+                ret++;
+                list_move(&sp->link, invalid_list);
         } else {
-                sp->role.invalid = 1;
                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
                 kvm_reload_remote_mmus(kvm);
         }
+
+        sp->role.invalid = 1;
         kvm_mmu_reset_last_pte_updated(kvm);
         return ret;
 }
 
+static void kvm_mmu_commit_zap_page(struct kvm *kvm,
+                                    struct list_head *invalid_list)
+{
+        struct kvm_mmu_page *sp;
+
+        if (list_empty(invalid_list))
+                return;
+
+        kvm_flush_remote_tlbs(kvm);
+
+        do {
+                sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
+                WARN_ON(!sp->role.invalid || sp->root_count);
+                kvm_mmu_free_page(kvm, sp);
+        } while (!list_empty(invalid_list));
+
+}
+
 /*
  * Changing the number of mmu pages allocated to the vm
  * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
@@ -1521,6 +1670,7 @@ static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
 {
         int used_pages;
+        LIST_HEAD(invalid_list);
 
         used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
         used_pages = max(0, used_pages);
@@ -1538,9 +1688,10 @@ void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
 
                         page = container_of(kvm->arch.active_mmu_pages.prev,
                                             struct kvm_mmu_page, link);
-                        used_pages -= kvm_mmu_zap_page(kvm, page);
-                        used_pages--;
+                        used_pages -= kvm_mmu_prepare_zap_page(kvm, page,
+                                                               &invalid_list);
                 }
+                kvm_mmu_commit_zap_page(kvm, &invalid_list);
                 kvm_nr_mmu_pages = used_pages;
                 kvm->arch.n_free_mmu_pages = 0;
         }
@@ -1553,47 +1704,36 @@ void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
 
 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
 {
-        unsigned index;
-        struct hlist_head *bucket;
         struct kvm_mmu_page *sp;
-        struct hlist_node *node, *n;
+        struct hlist_node *node;
+        LIST_HEAD(invalid_list);
         int r;
 
         pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
         r = 0;
-        index = kvm_page_table_hashfn(gfn);
-        bucket = &kvm->arch.mmu_page_hash[index];
-restart:
-        hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
-                if (sp->gfn == gfn && !sp->role.direct) {
-                        pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
-                                 sp->role.word);
-                        r = 1;
-                        if (kvm_mmu_zap_page(kvm, sp))
-                                goto restart;
-                }
+
+        for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
+                pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
+                         sp->role.word);
+                r = 1;
+                kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
+        }
+        kvm_mmu_commit_zap_page(kvm, &invalid_list);
         return r;
 }
 
 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
 {
-        unsigned index;
-        struct hlist_head *bucket;
         struct kvm_mmu_page *sp;
-        struct hlist_node *node, *nn;
+        struct hlist_node *node;
+        LIST_HEAD(invalid_list);
 
-        index = kvm_page_table_hashfn(gfn);
-        bucket = &kvm->arch.mmu_page_hash[index];
-restart:
-        hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
-                if (sp->gfn == gfn && !sp->role.direct
-                    && !sp->role.invalid) {
-                        pgprintk("%s: zap %lx %x\n",
-                                 __func__, gfn, sp->role.word);
-                        if (kvm_mmu_zap_page(kvm, sp))
-                                goto restart;
-                }
+        for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
+                pgprintk("%s: zap %lx %x\n",
+                         __func__, gfn, sp->role.word);
+                kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
         }
+        kvm_mmu_commit_zap_page(kvm, &invalid_list);
 }
 
 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
@@ -1723,47 +1863,51 @@ u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
 }
 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
 
-static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
+static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 {
-        unsigned index;
-        struct hlist_head *bucket;
-        struct kvm_mmu_page *s;
-        struct hlist_node *node, *n;
-
-        index = kvm_page_table_hashfn(sp->gfn);
-        bucket = &vcpu->kvm->arch.mmu_page_hash[index];
-        /* don't unsync if pagetable is shadowed with multiple roles */
-        hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
-                if (s->gfn != sp->gfn || s->role.direct)
-                        continue;
-                if (s->role.word != sp->role.word)
-                        return 1;
-        }
         trace_kvm_mmu_unsync_page(sp);
         ++vcpu->kvm->stat.mmu_unsync;
         sp->unsync = 1;
 
         kvm_mmu_mark_parents_unsync(sp);
-
         mmu_convert_notrap(sp);
-        return 0;
+}
+
+static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
+{
+        struct kvm_mmu_page *s;
+        struct hlist_node *node;
+
+        for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
+                if (s->unsync)
+                        continue;
+                WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
+                __kvm_unsync_page(vcpu, s);
+        }
 }
 
 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
                                   bool can_unsync)
 {
-        struct kvm_mmu_page *shadow;
+        struct kvm_mmu_page *s;
+        struct hlist_node *node;
+        bool need_unsync = false;
 
-        shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
-        if (shadow) {
-                if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
+        for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
+                if (!can_unsync)
                         return 1;
-                if (shadow->unsync)
-                        return 0;
-                if (can_unsync && oos_shadow)
-                        return kvm_unsync_page(vcpu, shadow);
-                return 1;
+
+                if (s->role.level != PT_PAGE_TABLE_LEVEL)
+                        return 1;
+
+                if (!need_unsync && !s->unsync) {
+                        if (!oos_shadow)
+                                return 1;
+                        need_unsync = true;
+                }
         }
+        if (need_unsync)
+                kvm_unsync_pages(vcpu, gfn);
         return 0;
 }
 
@@ -1804,13 +1948,14 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
         spte |= (u64)pfn << PAGE_SHIFT;
 
         if ((pte_access & ACC_WRITE_MASK)
-            || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
+            || (!tdp_enabled && write_fault && !is_write_protection(vcpu)
+                && !user_fault)) {
 
                 if (level > PT_PAGE_TABLE_LEVEL &&
                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
                         ret = 1;
-                        spte = shadow_trap_nonpresent_pte;
-                        goto set_pte;
+                        drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
+                        goto done;
                 }
 
                 spte |= PT_WRITABLE_MASK;
@@ -1841,7 +1986,10 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                 mark_page_dirty(vcpu->kvm, gfn);
 
 set_pte:
-        __set_spte(sptep, spte);
+        if (is_writable_pte(*sptep) && !is_writable_pte(spte))
+                kvm_set_pfn_dirty(pfn);
+        update_spte(sptep, spte);
+done:
         return ret;
 }
 
@@ -1853,7 +2001,6 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                          bool reset_host_protection)
 {
         int was_rmapped = 0;
-        int was_writable = is_writable_pte(*sptep);
         int rmap_count;
 
         pgprintk("%s: spte %llx access %x write_fault %d"
@@ -1878,8 +2025,7 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                 } else if (pfn != spte_to_pfn(*sptep)) {
                         pgprintk("hfn old %lx new %lx\n",
                                  spte_to_pfn(*sptep), pfn);
-                        rmap_remove(vcpu->kvm, sptep);
-                        __set_spte(sptep, shadow_trap_nonpresent_pte);
+                        drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
                         kvm_flush_remote_tlbs(vcpu->kvm);
                 } else
                         was_rmapped = 1;
@@ -1890,7 +2036,7 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                       reset_host_protection)) {
                 if (write_fault)
                         *ptwrite = 1;
-                kvm_x86_ops->tlb_flush(vcpu);
+                kvm_mmu_flush_tlb(vcpu);
         }
 
         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
@@ -1904,15 +2050,10 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
         page_header_update_slot(vcpu->kvm, sptep, gfn);
         if (!was_rmapped) {
                 rmap_count = rmap_add(vcpu, sptep, gfn);
-                kvm_release_pfn_clean(pfn);
                 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
                         rmap_recycle(vcpu, sptep, gfn);
-        } else {
-                if (was_writable)
-                        kvm_release_pfn_dirty(pfn);
-                else
-                        kvm_release_pfn_clean(pfn);
         }
+        kvm_release_pfn_clean(pfn);
         if (speculative) {
                 vcpu->arch.last_pte_updated = sptep;
                 vcpu->arch.last_pte_gfn = gfn;
@@ -1941,7 +2082,10 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
                 }
 
                 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
-                        pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
+                        u64 base_addr = iterator.addr;
+
+                        base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
+                        pseudo_gfn = base_addr >> PAGE_SHIFT;
                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
                                               iterator.level - 1,
                                               1, ACC_ALL, iterator.sptep);
@@ -1960,6 +2104,29 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
         return pt_write;
 }
 
+static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
+{
+        char buf[1];
+        void __user *hva;
+        int r;
+
+        /* Touch the page, so send SIGBUS */
+        hva = (void __user *)gfn_to_hva(kvm, gfn);
+        r = copy_from_user(buf, hva, 1);
+}
+
+static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
+{
+        kvm_release_pfn_clean(pfn);
+        if (is_hwpoison_pfn(pfn)) {
+                kvm_send_hwpoison_signal(kvm, gfn);
+                return 0;
+        } else if (is_fault_pfn(pfn))
+                return -EFAULT;
+
+        return 1;
+}
+
 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
 {
         int r;
@@ -1983,10 +2150,8 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
         pfn = gfn_to_pfn(vcpu->kvm, gfn);
 
         /* mmio */
-        if (is_error_pfn(pfn)) {
-                kvm_release_pfn_clean(pfn);
-                return 1;
-        }
+        if (is_error_pfn(pfn))
+                return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
 
         spin_lock(&vcpu->kvm->mmu_lock);
         if (mmu_notifier_retry(vcpu, mmu_seq))
@@ -2009,6 +2174,7 @@ static void mmu_free_roots(struct kvm_vcpu *vcpu)
 {
         int i;
         struct kvm_mmu_page *sp;
+        LIST_HEAD(invalid_list);
 
         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
                 return;
@@ -2018,8 +2184,10 @@ static void mmu_free_roots(struct kvm_vcpu *vcpu)
 
                 sp = page_header(root);
                 --sp->root_count;
-                if (!sp->root_count && sp->role.invalid)
-                        kvm_mmu_zap_page(vcpu->kvm, sp);
+                if (!sp->root_count && sp->role.invalid) {
+                        kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
+                        kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
+                }
                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
                 spin_unlock(&vcpu->kvm->mmu_lock);
                 return;
@@ -2032,10 +2200,12 @@ static void mmu_free_roots(struct kvm_vcpu *vcpu)
                         sp = page_header(root);
                         --sp->root_count;
                         if (!sp->root_count && sp->role.invalid)
-                                kvm_mmu_zap_page(vcpu->kvm, sp);
+                                kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
+                                                         &invalid_list);
                 }
                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
         }
+        kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
         spin_unlock(&vcpu->kvm->mmu_lock);
         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
 }
@@ -2045,7 +2215,7 @@ static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
         int ret = 0;
 
         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
-                set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
+                kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
                 ret = 1;
         }
 
@@ -2073,6 +2243,7 @@ static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
                         root_gfn = 0;
                 }
                 spin_lock(&vcpu->kvm->mmu_lock);
+                kvm_mmu_free_some_pages(vcpu);
                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
                                       PT64_ROOT_LEVEL, direct,
                                       ACC_ALL, NULL);
@@ -2103,6 +2274,7 @@ static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
                         root_gfn = i << 30;
                 }
                 spin_lock(&vcpu->kvm->mmu_lock);
+                kvm_mmu_free_some_pages(vcpu);
                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
                                       PT32_ROOT_LEVEL, direct,
                                       ACC_ALL, NULL);
@@ -2198,10 +2370,8 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
         mmu_seq = vcpu->kvm->mmu_notifier_seq;
         smp_rmb();
         pfn = gfn_to_pfn(vcpu->kvm, gfn);
-        if (is_error_pfn(pfn)) {
-                kvm_release_pfn_clean(pfn);
-                return 1;
-        }
+        if (is_error_pfn(pfn))
+                return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
         spin_lock(&vcpu->kvm->mmu_lock);
         if (mmu_notifier_retry(vcpu, mmu_seq))
                 goto out_unlock;
@@ -2243,7 +2413,7 @@ static int nonpaging_init_context(struct kvm_vcpu *vcpu)
 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
 {
         ++vcpu->stat.tlb_flush;
-        kvm_x86_ops->tlb_flush(vcpu);
+        kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 }
 
 static void paging_new_cr3(struct kvm_vcpu *vcpu)
@@ -2457,10 +2627,9 @@ static int init_kvm_mmu(struct kvm_vcpu *vcpu)
 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
 {
         ASSERT(vcpu);
-        if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
+        if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                /* mmu.free() should set root_hpa = INVALID_PAGE */
                 vcpu->arch.mmu.free(vcpu);
-                vcpu->arch.mmu.root_hpa = INVALID_PAGE;
-        }
 }
 
 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
@@ -2477,9 +2646,6 @@ int kvm_mmu_load(struct kvm_vcpu *vcpu)
         r = mmu_topup_memory_caches(vcpu);
         if (r)
                 goto out;
-        spin_lock(&vcpu->kvm->mmu_lock);
-        kvm_mmu_free_some_pages(vcpu);
-        spin_unlock(&vcpu->kvm->mmu_lock);
         r = mmu_alloc_roots(vcpu);
         spin_lock(&vcpu->kvm->mmu_lock);
         mmu_sync_roots(vcpu);
@@ -2508,7 +2674,7 @@ static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
         pte = *spte;
         if (is_shadow_present_pte(pte)) {
                 if (is_last_spte(pte, sp->role.level))
-                        rmap_remove(vcpu->kvm, spte);
+                        drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte);
                 else {
                         child = page_header(pte & PT64_BASE_ADDR_MASK);
                         mmu_page_remove_parent_pte(child, spte);
@@ -2529,6 +2695,9 @@ static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
                 return;
         }
 
+        if (is_rsvd_bits_set(vcpu, *(u64 *)new, PT_PAGE_TABLE_LEVEL))
+                return;
+
         ++vcpu->kvm->stat.mmu_pte_updated;
         if (!sp->role.cr4_pae)
                 paging32_update_pte(vcpu, sp, spte, new);
@@ -2549,11 +2718,15 @@ static bool need_remote_flush(u64 old, u64 new)
         return (old & ~new & PT64_PERM_MASK) != 0;
 }
 
-static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
+static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
+                                    bool remote_flush, bool local_flush)
 {
-        if (need_remote_flush(old, new))
+        if (zap_page)
+                return;
+
+        if (remote_flush)
                 kvm_flush_remote_tlbs(vcpu->kvm);
-        else
+        else if (local_flush)
                 kvm_mmu_flush_tlb(vcpu);
 }
 
@@ -2603,10 +2776,10 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
                        bool guest_initiated)
 {
         gfn_t gfn = gpa >> PAGE_SHIFT;
+        union kvm_mmu_page_role mask = { .word = 0 };
         struct kvm_mmu_page *sp;
-        struct hlist_node *node, *n;
-        struct hlist_head *bucket;
-        unsigned index;
+        struct hlist_node *node;
+        LIST_HEAD(invalid_list);
         u64 entry, gentry;
         u64 *spte;
         unsigned offset = offset_in_page(gpa);
@@ -2619,6 +2792,9 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
         int npte;
         int r;
         int invlpg_counter;
+        bool remote_flush, local_flush, zap_page;
+
+        zap_page = remote_flush = local_flush = false;
 
         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
 
@@ -2674,13 +2850,9 @@ void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
                         vcpu->arch.last_pte_updated = NULL;
                 }
         }
-        index = kvm_page_table_hashfn(gfn);
-        bucket = &vcpu->kvm->arch.mmu_page_hash[index];
 
-restart:
-        hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
-                if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
-                        continue;
+        mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
+        for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
                 pte_size = sp->role.cr4_pae ? 8 : 4;
                 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
                 misaligned |= bytes < 4;
@@ -2697,8 +2869,8 @@ restart:
                          */
                         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
                                  gpa, bytes, sp->role.word);
-                        if (kvm_mmu_zap_page(vcpu->kvm, sp))
-                                goto restart;
+                        zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
+                                                     &invalid_list);
                         ++vcpu->kvm->stat.mmu_flooded;
                         continue;
                 }
@@ -2722,16 +2894,22 @@ restart:
                         if (quadrant != sp->role.quadrant)
                                 continue;
                 }
+                local_flush = true;
                 spte = &sp->spt[page_offset / sizeof(*spte)];
                 while (npte--) {
                         entry = *spte;
                         mmu_pte_write_zap_pte(vcpu, sp, spte);
-                        if (gentry)
+                        if (gentry &&
+                              !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
+                              & mask.word))
                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
-                        mmu_pte_write_flush_tlb(vcpu, entry, *spte);
+                        if (!remote_flush && need_remote_flush(entry, *spte))
+                                remote_flush = true;
                         ++spte;
                 }
         }
+        mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
+        kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
         kvm_mmu_audit(vcpu, "post pte write");
         spin_unlock(&vcpu->kvm->mmu_lock);
         if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
@@ -2759,15 +2937,21 @@ EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
 
 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
 {
-        while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
+        int free_pages;
+        LIST_HEAD(invalid_list);
+
+        free_pages = vcpu->kvm->arch.n_free_mmu_pages;
+        while (free_pages < KVM_REFILL_PAGES &&
                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
                 struct kvm_mmu_page *sp;
 
                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
                                   struct kvm_mmu_page, link);
-                kvm_mmu_zap_page(vcpu->kvm, sp);
+                free_pages += kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
+                                                       &invalid_list);
                 ++vcpu->kvm->stat.mmu_recycled;
         }
+        kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
 }
 
 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
@@ -2795,11 +2979,8 @@ int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
                 return 1;
         case EMULATE_DO_MMIO:
                 ++vcpu->stat.mmio_exits;
-                return 0;
+                /* fall through */
         case EMULATE_FAIL:
-                vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
-                vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
-                vcpu->run->internal.ndata = 0;
                 return 0;
         default:
                 BUG();
@@ -2896,7 +3077,7 @@ void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
                 pt = sp->spt;
                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
                         /* avoid RMW */
-                        if (pt[i] & PT_WRITABLE_MASK)
+                        if (is_writable_pte(pt[i]))
                                 pt[i] &= ~PT_WRITABLE_MASK;
         }
         kvm_flush_remote_tlbs(kvm);
@@ -2905,25 +3086,26 @@ void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
 void kvm_mmu_zap_all(struct kvm *kvm)
 {
         struct kvm_mmu_page *sp, *node;
+        LIST_HEAD(invalid_list);
 
         spin_lock(&kvm->mmu_lock);
 restart:
         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
-                if (kvm_mmu_zap_page(kvm, sp))
+                if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
                         goto restart;
 
+        kvm_mmu_commit_zap_page(kvm, &invalid_list);
         spin_unlock(&kvm->mmu_lock);
-
-        kvm_flush_remote_tlbs(kvm);
 }
 
-static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
+static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
+                                               struct list_head *invalid_list)
 {
         struct kvm_mmu_page *page;
 
         page = container_of(kvm->arch.active_mmu_pages.prev,
                             struct kvm_mmu_page, link);
-        return kvm_mmu_zap_page(kvm, page) + 1;
+        return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
 }
 
 static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
@@ -2936,6 +3118,7 @@ static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
 
         list_for_each_entry(kvm, &vm_list, vm_list) {
                 int npages, idx, freed_pages;
+                LIST_HEAD(invalid_list);
 
                 idx = srcu_read_lock(&kvm->srcu);
                 spin_lock(&kvm->mmu_lock);
@@ -2943,12 +3126,14 @@ static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
                          kvm->arch.n_free_mmu_pages;
                 cache_count += npages;
                 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
-                        freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm);
+                        freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
+                                                          &invalid_list);
                         cache_count -= freed_pages;
                         kvm_freed = kvm;
                 }
                 nr_to_scan--;
 
+                kvm_mmu_commit_zap_page(kvm, &invalid_list);
                 spin_unlock(&kvm->mmu_lock);
                 srcu_read_unlock(&kvm->srcu, idx);
         }
@@ -3074,7 +3259,7 @@ static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
 
 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
 {
-        kvm_set_cr3(vcpu, vcpu->arch.cr3);
+        (void)kvm_set_cr3(vcpu, vcpu->arch.cr3);
         return 1;
 }
 
@@ -3331,9 +3516,9 @@ void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
         struct kvm_mmu_page *rev_sp;
         gfn_t gfn;
 
-        if (*sptep & PT_WRITABLE_MASK) {
+        if (is_writable_pte(*sptep)) {
                 rev_sp = page_header(__pa(sptep));
-                gfn = rev_sp->gfns[sptep - rev_sp->spt];
+                gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt);
 
                 if (!gfn_to_memslot(kvm, gfn)) {
                         if (!printk_ratelimit())
@@ -3347,8 +3532,7 @@ void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
                         return;
                 }
 
-                rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
-                                    rev_sp->role.level);
+                rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level);
                 if (!*rmapp) {
                         if (!printk_ratelimit())
                                 return;
@@ -3381,7 +3565,7 @@ static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
 
                         if (!(ent & PT_PRESENT_MASK))
                                 continue;
-                        if (!(ent & PT_WRITABLE_MASK))
+                        if (!is_writable_pte(ent))
                                 continue;
                         inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
                 }
@@ -3409,13 +3593,12 @@ static void audit_write_protection(struct kvm_vcpu *vcpu)
                 if (sp->unsync)
                         continue;
 
-                gfn = unalias_gfn(vcpu->kvm, sp->gfn);
-                slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
+                slot = gfn_to_memslot(vcpu->kvm, sp->gfn);
                 rmapp = &slot->rmap[gfn - slot->base_gfn];
 
                 spte = rmap_next(vcpu->kvm, rmapp, NULL);
                 while (spte) {
-                        if (*spte & PT_WRITABLE_MASK)
+                        if (is_writable_pte(*spte))
                                 printk(KERN_ERR "%s: (%s) shadow page has "
                                 "writable mappings: gfn %lx role %x\n",
                                __func__, audit_msg, sp->gfn,
diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h
index 42f07b1bfbc9..3aab0f0930ef 100644
--- a/arch/x86/kvm/mmutrace.h
+++ b/arch/x86/kvm/mmutrace.h
@@ -190,7 +190,7 @@ DEFINE_EVENT(kvm_mmu_page_class, kvm_mmu_unsync_page,
         TP_ARGS(sp)
 );
 
-DEFINE_EVENT(kvm_mmu_page_class, kvm_mmu_zap_page,
+DEFINE_EVENT(kvm_mmu_page_class, kvm_mmu_prepare_zap_page,
         TP_PROTO(struct kvm_mmu_page *sp),
 
         TP_ARGS(sp)
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 2331bdc2b549..51ef9097960d 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -7,6 +7,7 @@
  * MMU support
  *
  * Copyright (C) 2006 Qumranet, Inc.
+ * Copyright 2010 Red Hat, Inc. and/or its affilates.
  *
  * Authors:
  *   Yaniv Kamay  <yaniv@qumranet.com>
@@ -118,21 +119,25 @@ static int FNAME(walk_addr)(struct guest_walker *walker,
 {
         pt_element_t pte;
         gfn_t table_gfn;
-        unsigned index, pt_access, pte_access;
+        unsigned index, pt_access, uninitialized_var(pte_access);
         gpa_t pte_gpa;
-        int rsvd_fault = 0;
+        bool eperm, present, rsvd_fault;
 
         trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
                                      fetch_fault);
 walk:
+        present = true;
+        eperm = rsvd_fault = false;
         walker->level = vcpu->arch.mmu.root_level;
         pte = vcpu->arch.cr3;
 #if PTTYPE == 64
         if (!is_long_mode(vcpu)) {
                 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
                 trace_kvm_mmu_paging_element(pte, walker->level);
-                if (!is_present_gpte(pte))
-                        goto not_present;
+                if (!is_present_gpte(pte)) {
+                        present = false;
+                        goto error;
+                }
                 --walker->level;
         }
 #endif
@@ -150,37 +155,42 @@ walk:
                 walker->table_gfn[walker->level - 1] = table_gfn;
                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 
-                if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)))
-                        goto not_present;
+                if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) {
+                        present = false;
+                        break;
+                }
 
                 trace_kvm_mmu_paging_element(pte, walker->level);
 
-                if (!is_present_gpte(pte))
-                        goto not_present;
+                if (!is_present_gpte(pte)) {
+                        present = false;
+                        break;
+                }
 
-                rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
-                if (rsvd_fault)
-                        goto access_error;
+                if (is_rsvd_bits_set(vcpu, pte, walker->level)) {
+                        rsvd_fault = true;
+                        break;
+                }
 
                 if (write_fault && !is_writable_pte(pte))
                         if (user_fault || is_write_protection(vcpu))
-                                goto access_error;
+                                eperm = true;
 
                 if (user_fault && !(pte & PT_USER_MASK))
-                        goto access_error;
+                        eperm = true;
 
 #if PTTYPE == 64
                 if (fetch_fault && (pte & PT64_NX_MASK))
-                        goto access_error;
+                        eperm = true;
 #endif
 
-                if (!(pte & PT_ACCESSED_MASK)) {
+                if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
                         trace_kvm_mmu_set_accessed_bit(table_gfn, index,
                                                        sizeof(pte));
-                        mark_page_dirty(vcpu->kvm, table_gfn);
                         if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
                             index, pte, pte|PT_ACCESSED_MASK))
                                 goto walk;
+                        mark_page_dirty(vcpu->kvm, table_gfn);
                         pte |= PT_ACCESSED_MASK;
                 }
 
@@ -213,15 +223,18 @@ walk:
                 --walker->level;
         }
 
+        if (!present || eperm || rsvd_fault)
+                goto error;
+
         if (write_fault && !is_dirty_gpte(pte)) {
                 bool ret;
 
                 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
-                mark_page_dirty(vcpu->kvm, table_gfn);
                 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
                             pte|PT_DIRTY_MASK);
                 if (ret)
                         goto walk;
+                mark_page_dirty(vcpu->kvm, table_gfn);
                 pte |= PT_DIRTY_MASK;
                 walker->ptes[walker->level - 1] = pte;
         }
@@ -229,22 +242,18 @@ walk:
         walker->pt_access = pt_access;
         walker->pte_access = pte_access;
         pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
-                 __func__, (u64)pte, pt_access, pte_access);
+                 __func__, (u64)pte, pte_access, pt_access);
         return 1;
 
-not_present:
+error:
         walker->error_code = 0;
-        goto err;
-
-access_error:
-        walker->error_code = PFERR_PRESENT_MASK;
-
-err:
+        if (present)
+                walker->error_code |= PFERR_PRESENT_MASK;
         if (write_fault)
                 walker->error_code |= PFERR_WRITE_MASK;
         if (user_fault)
                 walker->error_code |= PFERR_USER_MASK;
-        if (fetch_fault)
+        if (fetch_fault && is_nx(vcpu))
                 walker->error_code |= PFERR_FETCH_MASK;
         if (rsvd_fault)
                 walker->error_code |= PFERR_RSVD_MASK;
@@ -252,7 +261,7 @@ err:
         return 0;
 }
 
-static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
+static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
                               u64 *spte, const void *pte)
 {
         pt_element_t gpte;
@@ -263,7 +272,7 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
         gpte = *(const pt_element_t *)pte;
         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
                 if (!is_present_gpte(gpte)) {
-                        if (page->unsync)
+                        if (sp->unsync)
                                 new_spte = shadow_trap_nonpresent_pte;
                         else
                                 new_spte = shadow_notrap_nonpresent_pte;
@@ -272,7 +281,7 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
                 return;
         }
         pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
-        pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
+        pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
         if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
                 return;
         pfn = vcpu->arch.update_pte.pfn;
@@ -285,11 +294,22 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
          * we call mmu_set_spte() with reset_host_protection = true beacuse that
          * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
          */
-        mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
-                     gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
+        mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
+                     is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
                      gpte_to_gfn(gpte), pfn, true, true);
 }
 
+static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
+                                struct guest_walker *gw, int level)
+{
+        int r;
+        pt_element_t curr_pte;
+
+        r = kvm_read_guest_atomic(vcpu->kvm, gw->pte_gpa[level - 1],
+                                  &curr_pte, sizeof(curr_pte));
+        return r || curr_pte != gw->ptes[level - 1];
+}
+
 /*
  * Fetch a shadow pte for a specific level in the paging hierarchy.
  */
@@ -299,75 +319,86 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
                          int *ptwrite, pfn_t pfn)
 {
         unsigned access = gw->pt_access;
-        struct kvm_mmu_page *shadow_page;
-        u64 spte, *sptep = NULL;
-        int direct;
-        gfn_t table_gfn;
-        int r;
-        int level;
-        pt_element_t curr_pte;
-        struct kvm_shadow_walk_iterator iterator;
+        struct kvm_mmu_page *sp = NULL;
+        bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
+        int top_level;
+        unsigned direct_access;
+        struct kvm_shadow_walk_iterator it;
 
         if (!is_present_gpte(gw->ptes[gw->level - 1]))
                 return NULL;
 
-        for_each_shadow_entry(vcpu, addr, iterator) {
-                level = iterator.level;
-                sptep = iterator.sptep;
-                if (iterator.level == hlevel) {
-                        mmu_set_spte(vcpu, sptep, access,
-                                     gw->pte_access & access,
-                                     user_fault, write_fault,
-                                     gw->ptes[gw->level-1] & PT_DIRTY_MASK,
-                                     ptwrite, level,
-                                     gw->gfn, pfn, false, true);
-                        break;
-                }
+        direct_access = gw->pt_access & gw->pte_access;
+        if (!dirty)
+                direct_access &= ~ACC_WRITE_MASK;
 
-                if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
-                        continue;
+        top_level = vcpu->arch.mmu.root_level;
+        if (top_level == PT32E_ROOT_LEVEL)
+                top_level = PT32_ROOT_LEVEL;
+        /*
+         * Verify that the top-level gpte is still there.  Since the page
+         * is a root page, it is either write protected (and cannot be
+         * changed from now on) or it is invalid (in which case, we don't
+         * really care if it changes underneath us after this point).
+         */
+        if (FNAME(gpte_changed)(vcpu, gw, top_level))
+                goto out_gpte_changed;
 
-                if (is_large_pte(*sptep)) {
-                        rmap_remove(vcpu->kvm, sptep);
-                        __set_spte(sptep, shadow_trap_nonpresent_pte);
-                        kvm_flush_remote_tlbs(vcpu->kvm);
-                }
+        for (shadow_walk_init(&it, vcpu, addr);
+             shadow_walk_okay(&it) && it.level > gw->level;
+             shadow_walk_next(&it)) {
+                gfn_t table_gfn;
 
-                if (level <= gw->level) {
-                        int delta = level - gw->level + 1;
-                        direct = 1;
-                        if (!is_dirty_gpte(gw->ptes[level - delta]))
-                                access &= ~ACC_WRITE_MASK;
-                        table_gfn = gpte_to_gfn(gw->ptes[level - delta]);
-                        /* advance table_gfn when emulating 1gb pages with 4k */
-                        if (delta == 0)
-                                table_gfn += PT_INDEX(addr, level);
-                        access &= gw->pte_access;
-                } else {
-                        direct = 0;
-                        table_gfn = gw->table_gfn[level - 2];
-                }
-                shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
-                                               direct, access, sptep);
-                if (!direct) {
-                        r = kvm_read_guest_atomic(vcpu->kvm,
-                                                  gw->pte_gpa[level - 2],
-                                                  &curr_pte, sizeof(curr_pte));
-                        if (r || curr_pte != gw->ptes[level - 2]) {
-                                kvm_mmu_put_page(shadow_page, sptep);
-                                kvm_release_pfn_clean(pfn);
-                                sptep = NULL;
-                                break;
-                        }
+                drop_large_spte(vcpu, it.sptep);
+
+                sp = NULL;
+                if (!is_shadow_present_pte(*it.sptep)) {
+                        table_gfn = gw->table_gfn[it.level - 2];
+                        sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
+                                              false, access, it.sptep);
                 }
 
-                spte = __pa(shadow_page->spt)
-                        | PT_PRESENT_MASK | PT_ACCESSED_MASK
-                        | PT_WRITABLE_MASK | PT_USER_MASK;
-                *sptep = spte;
+                /*
+                 * Verify that the gpte in the page we've just write
+                 * protected is still there.
+                 */
+                if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
+                        goto out_gpte_changed;
+
+                if (sp)
+                        link_shadow_page(it.sptep, sp);
         }
 
-        return sptep;
+        for (;
+             shadow_walk_okay(&it) && it.level > hlevel;
+             shadow_walk_next(&it)) {
+                gfn_t direct_gfn;
+
+                validate_direct_spte(vcpu, it.sptep, direct_access);
+
+                drop_large_spte(vcpu, it.sptep);
+
+                if (is_shadow_present_pte(*it.sptep))
+                        continue;
+
+                direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
+
+                sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
+                                      true, direct_access, it.sptep);
+                link_shadow_page(it.sptep, sp);
+        }
+
+        mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
+                     user_fault, write_fault, dirty, ptwrite, it.level,
+                     gw->gfn, pfn, false, true);
+
+        return it.sptep;
+
+out_gpte_changed:
+        if (sp)
+                kvm_mmu_put_page(sp, it.sptep);
+        kvm_release_pfn_clean(pfn);
+        return NULL;
 }
 
 /*
@@ -431,11 +462,8 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
         pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
 
         /* mmio */
-        if (is_error_pfn(pfn)) {
-                pgprintk("gfn %lx is mmio\n", walker.gfn);
-                kvm_release_pfn_clean(pfn);
-                return 1;
-        }
+        if (is_error_pfn(pfn))
+                return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
 
         spin_lock(&vcpu->kvm->mmu_lock);
         if (mmu_notifier_retry(vcpu, mmu_seq))
@@ -443,6 +471,7 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
         kvm_mmu_free_some_pages(vcpu);
         sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
                              level, &write_pt, pfn);
+        (void)sptep;
         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
                  sptep, *sptep, write_pt);
 
@@ -464,6 +493,7 @@ out_unlock:
 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
 {
         struct kvm_shadow_walk_iterator iterator;
+        struct kvm_mmu_page *sp;
         gpa_t pte_gpa = -1;
         int level;
         u64 *sptep;
@@ -475,10 +505,13 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
                 level = iterator.level;
                 sptep = iterator.sptep;
 
+                sp = page_header(__pa(sptep));
                 if (is_last_spte(*sptep, level)) {
-                        struct kvm_mmu_page *sp = page_header(__pa(sptep));
                         int offset, shift;
 
+                        if (!sp->unsync)
+                                break;
+
                         shift = PAGE_SHIFT -
                                   (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
                         offset = sp->role.quadrant << shift;
@@ -487,16 +520,17 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
                         pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
 
                         if (is_shadow_present_pte(*sptep)) {
-                                rmap_remove(vcpu->kvm, sptep);
                                 if (is_large_pte(*sptep))
                                         --vcpu->kvm->stat.lpages;
+                                drop_spte(vcpu->kvm, sptep,
+                                          shadow_trap_nonpresent_pte);
                                 need_flush = 1;
-                        }
-                        __set_spte(sptep, shadow_trap_nonpresent_pte);
+                        } else
+                                __set_spte(sptep, shadow_trap_nonpresent_pte);
                         break;
                 }
 
-                if (!is_shadow_present_pte(*sptep))
+                if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
                         break;
         }
 
@@ -570,9 +604,9 @@ static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
  * Using the cached information from sp->gfns is safe because:
  * - The spte has a reference to the struct page, so the pfn for a given gfn
  *   can't change unless all sptes pointing to it are nuked first.
- * - Alias changes zap the entire shadow cache.
  */
-static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
+static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
+                            bool clear_unsync)
 {
         int i, offset, nr_present;
         bool reset_host_protection;
@@ -580,6 +614,9 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 
         offset = nr_present = 0;
 
+        /* direct kvm_mmu_page can not be unsync. */
+        BUG_ON(sp->role.direct);
+
         if (PTTYPE == 32)
                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 
@@ -589,7 +626,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
                 unsigned pte_access;
                 pt_element_t gpte;
                 gpa_t pte_gpa;
-                gfn_t gfn = sp->gfns[i];
+                gfn_t gfn;
 
                 if (!is_shadow_present_pte(sp->spt[i]))
                         continue;
@@ -600,16 +637,17 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
                                           sizeof(pt_element_t)))
                         return -EINVAL;
 
-                if (gpte_to_gfn(gpte) != gfn || !is_present_gpte(gpte) ||
-                    !(gpte & PT_ACCESSED_MASK)) {
+                gfn = gpte_to_gfn(gpte);
+                if (is_rsvd_bits_set(vcpu, gpte, PT_PAGE_TABLE_LEVEL)
+                      || gfn != sp->gfns[i] || !is_present_gpte(gpte)
+                      || !(gpte & PT_ACCESSED_MASK)) {
                         u64 nonpresent;
 
-                        rmap_remove(vcpu->kvm, &sp->spt[i]);
-                        if (is_present_gpte(gpte))
+                        if (is_present_gpte(gpte) || !clear_unsync)
                                 nonpresent = shadow_trap_nonpresent_pte;
                         else
                                 nonpresent = shadow_notrap_nonpresent_pte;
-                        __set_spte(&sp->spt[i], nonpresent);
+                        drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
                         continue;
                 }
 
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index ce438e0fdd26..bc5b9b8d4a33 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -4,6 +4,7 @@
  * AMD SVM support
  *
  * Copyright (C) 2006 Qumranet, Inc.
+ * Copyright 2010 Red Hat, Inc. and/or its affilates.
  *
  * Authors:
  *   Yaniv Kamay  <yaniv@qumranet.com>
@@ -130,7 +131,7 @@ static struct svm_direct_access_msrs {
         u32 index;   /* Index of the MSR */
         bool always; /* True if intercept is always on */
 } direct_access_msrs[] = {
-        { .index = MSR_K6_STAR,                         .always = true  },
+        { .index = MSR_STAR,                            .always = true  },
         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 #ifdef CONFIG_X86_64
         { .index = MSR_GS_BASE,                         .always = true  },
@@ -285,11 +286,11 @@ static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 
 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 {
+        vcpu->arch.efer = efer;
         if (!npt_enabled && !(efer & EFER_LMA))
                 efer &= ~EFER_LME;
 
         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
-        vcpu->arch.efer = efer;
 }
 
 static int is_external_interrupt(u32 info)
@@ -383,8 +384,7 @@ static void svm_init_erratum_383(void)
         int err;
         u64 val;
 
-        /* Only Fam10h is affected */
-        if (boot_cpu_data.x86 != 0x10)
+        if (!cpu_has_amd_erratum(amd_erratum_383))
                 return;
 
         /* Use _safe variants to not break nested virtualization */
@@ -640,7 +640,7 @@ static __init int svm_hardware_setup(void)
 
         if (nested) {
                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
-                kvm_enable_efer_bits(EFER_SVME);
+                kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
         }
 
         for_each_possible_cpu(cpu) {
@@ -806,7 +806,7 @@ static void init_vmcb(struct vcpu_svm *svm)
          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
          */
         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
-        kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
+        (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 
         save->cr4 = X86_CR4_PAE;
         /* rdx = ?? */
@@ -903,13 +903,18 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
         svm->asid_generation = 0;
         init_vmcb(svm);
 
-        fx_init(&svm->vcpu);
+        err = fx_init(&svm->vcpu);
+        if (err)
+                goto free_page4;
+
         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
         if (kvm_vcpu_is_bsp(&svm->vcpu))
                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 
         return &svm->vcpu;
 
+free_page4:
+        __free_page(hsave_page);
 free_page3:
         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 free_page2:
@@ -1488,7 +1493,7 @@ static void svm_handle_mce(struct vcpu_svm *svm)
                  */
                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
 
-                set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
+                kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
 
                 return;
         }
@@ -1535,7 +1540,7 @@ static int io_interception(struct vcpu_svm *svm)
         string = (io_info & SVM_IOIO_STR_MASK) != 0;
         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
         if (string || in)
-                return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
+                return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
 
         port = io_info >> 16;
         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
@@ -1957,7 +1962,7 @@ static int nested_svm_vmexit(struct vcpu_svm *svm)
                 svm->vmcb->save.cr3 = hsave->save.cr3;
                 svm->vcpu.arch.cr3 = hsave->save.cr3;
         } else {
-                kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
+                (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
         }
         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
@@ -2080,7 +2085,7 @@ static bool nested_svm_vmrun(struct vcpu_svm *svm)
                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
         } else
-                kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
+                (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
 
         /* Guest paging mode is active - reset mmu */
         kvm_mmu_reset_context(&svm->vcpu);
@@ -2386,16 +2391,12 @@ static int iret_interception(struct vcpu_svm *svm)
 
 static int invlpg_interception(struct vcpu_svm *svm)
 {
-        if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
-                pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
-        return 1;
+        return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
 }
 
 static int emulate_on_interception(struct vcpu_svm *svm)
 {
-        if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
-                pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
-        return 1;
+        return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
 }
 
 static int cr8_write_interception(struct vcpu_svm *svm)
@@ -2431,7 +2432,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
                 *data = tsc_offset + native_read_tsc();
                 break;
         }
-        case MSR_K6_STAR:
+        case MSR_STAR:
                 *data = svm->vmcb->save.star;
                 break;
 #ifdef CONFIG_X86_64
@@ -2555,7 +2556,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
 
                 break;
         }
-        case MSR_K6_STAR:
+        case MSR_STAR:
                 svm->vmcb->save.star = data;
                 break;
 #ifdef CONFIG_X86_64
@@ -2726,6 +2727,99 @@ static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
         [SVM_EXIT_NPF]                          = pf_interception,
 };
 
+void dump_vmcb(struct kvm_vcpu *vcpu)
+{
+        struct vcpu_svm *svm = to_svm(vcpu);
+        struct vmcb_control_area *control = &svm->vmcb->control;
+        struct vmcb_save_area *save = &svm->vmcb->save;
+
+        pr_err("VMCB Control Area:\n");
+        pr_err("cr_read:            %04x\n", control->intercept_cr_read);
+        pr_err("cr_write:           %04x\n", control->intercept_cr_write);
+        pr_err("dr_read:            %04x\n", control->intercept_dr_read);
+        pr_err("dr_write:           %04x\n", control->intercept_dr_write);
+        pr_err("exceptions:         %08x\n", control->intercept_exceptions);
+        pr_err("intercepts:         %016llx\n", control->intercept);
+        pr_err("pause filter count: %d\n", control->pause_filter_count);
+        pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
+        pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
+        pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
+        pr_err("asid:               %d\n", control->asid);
+        pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
+        pr_err("int_ctl:            %08x\n", control->int_ctl);
+        pr_err("int_vector:         %08x\n", control->int_vector);
+        pr_err("int_state:          %08x\n", control->int_state);
+        pr_err("exit_code:          %08x\n", control->exit_code);
+        pr_err("exit_info1:         %016llx\n", control->exit_info_1);
+        pr_err("exit_info2:         %016llx\n", control->exit_info_2);
+        pr_err("exit_int_info:      %08x\n", control->exit_int_info);
+        pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
+        pr_err("nested_ctl:         %lld\n", control->nested_ctl);
+        pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
+        pr_err("event_inj:          %08x\n", control->event_inj);
+        pr_err("event_inj_err:      %08x\n", control->event_inj_err);
+        pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
+        pr_err("next_rip:           %016llx\n", control->next_rip);
+        pr_err("VMCB State Save Area:\n");
+        pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
+                save->es.selector, save->es.attrib,
+                save->es.limit, save->es.base);
+        pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
+                save->cs.selector, save->cs.attrib,
+                save->cs.limit, save->cs.base);
+        pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
+                save->ss.selector, save->ss.attrib,
+                save->ss.limit, save->ss.base);
+        pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
+                save->ds.selector, save->ds.attrib,
+                save->ds.limit, save->ds.base);
+        pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
+                save->fs.selector, save->fs.attrib,
+                save->fs.limit, save->fs.base);
+        pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
+                save->gs.selector, save->gs.attrib,
+                save->gs.limit, save->gs.base);
+        pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
+                save->gdtr.selector, save->gdtr.attrib,
+                save->gdtr.limit, save->gdtr.base);
+        pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
+                save->ldtr.selector, save->ldtr.attrib,
+                save->ldtr.limit, save->ldtr.base);
+        pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
+                save->idtr.selector, save->idtr.attrib,
+                save->idtr.limit, save->idtr.base);
+        pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
+                save->tr.selector, save->tr.attrib,
+                save->tr.limit, save->tr.base);
+        pr_err("cpl:            %d                efer:         %016llx\n",
+                save->cpl, save->efer);
+        pr_err("cr0:            %016llx cr2:          %016llx\n",
+                save->cr0, save->cr2);
+        pr_err("cr3:            %016llx cr4:          %016llx\n",
+                save->cr3, save->cr4);
+        pr_err("dr6:            %016llx dr7:          %016llx\n",
+                save->dr6, save->dr7);
+        pr_err("rip:            %016llx rflags:       %016llx\n",
+                save->rip, save->rflags);
+        pr_err("rsp:            %016llx rax:          %016llx\n",
+                save->rsp, save->rax);
+        pr_err("star:           %016llx lstar:        %016llx\n",
+                save->star, save->lstar);
+        pr_err("cstar:          %016llx sfmask:       %016llx\n",
+                save->cstar, save->sfmask);
+        pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
+                save->kernel_gs_base, save->sysenter_cs);
+        pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
+                save->sysenter_esp, save->sysenter_eip);
+        pr_err("gpat:           %016llx dbgctl:       %016llx\n",
+                save->g_pat, save->dbgctl);
+        pr_err("br_from:        %016llx br_to:        %016llx\n",
+                save->br_from, save->br_to);
+        pr_err("excp_from:      %016llx excp_to:      %016llx\n",
+                save->last_excp_from, save->last_excp_to);
+
+}
+
 static int handle_exit(struct kvm_vcpu *vcpu)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
@@ -2770,6 +2864,8 @@ static int handle_exit(struct kvm_vcpu *vcpu)
                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
                 kvm_run->fail_entry.hardware_entry_failure_reason
                         = svm->vmcb->control.exit_code;
+                pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
+                dump_vmcb(vcpu);
                 return 0;
         }
 
@@ -2826,9 +2922,6 @@ static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
 {
         struct vmcb_control_area *control;
 
-        trace_kvm_inj_virq(irq);
-
-        ++svm->vcpu.stat.irq_injections;
         control = &svm->vmcb->control;
         control->int_vector = irq;
         control->int_ctl &= ~V_INTR_PRIO_MASK;
@@ -2842,6 +2935,9 @@ static void svm_set_irq(struct kvm_vcpu *vcpu)
 
         BUG_ON(!(gif_set(svm)));
 
+        trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
+        ++vcpu->stat.irq_injections;
+
         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
 }
@@ -3327,6 +3423,11 @@ static bool svm_rdtscp_supported(void)
         return false;
 }
 
+static bool svm_has_wbinvd_exit(void)
+{
+        return true;
+}
+
 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
@@ -3411,6 +3512,8 @@ static struct kvm_x86_ops svm_x86_ops = {
         .rdtscp_supported = svm_rdtscp_supported,
 
         .set_supported_cpuid = svm_set_supported_cpuid,
+
+        .has_wbinvd_exit = svm_has_wbinvd_exit,
 };
 
 static int __init svm_init(void)
diff --git a/arch/x86/kvm/timer.c b/arch/x86/kvm/timer.c
index 4ddadb1a5ffe..e16a0dbe74d8 100644
--- a/arch/x86/kvm/timer.c
+++ b/arch/x86/kvm/timer.c
@@ -1,3 +1,17 @@
+/*
+ * Kernel-based Virtual Machine driver for Linux
+ *
+ * This module enables machines with Intel VT-x extensions to run virtual
+ * machines without emulation or binary translation.
+ *
+ * timer support
+ *
+ * Copyright 2010 Red Hat, Inc. and/or its affilates.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
 #include <linux/kvm_host.h>
 #include <linux/kvm.h>
 #include <linux/hrtimer.h>
@@ -18,7 +32,7 @@ static int __kvm_timer_fn(struct kvm_vcpu *vcpu, struct kvm_timer *ktimer)
         if (ktimer->reinject || !atomic_read(&ktimer->pending)) {
                 atomic_inc(&ktimer->pending);
                 /* FIXME: this code should not know anything about vcpus */
-                set_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
+                kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
         }
 
         if (waitqueue_active(q))
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ee03679efe78..49b25eee25ac 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -5,6 +5,7 @@
  * machines without emulation or binary translation.
  *
  * Copyright (C) 2006 Qumranet, Inc.
+ * Copyright 2010 Red Hat, Inc. and/or its affilates.
  *
  * Authors:
  *   Avi Kivity   <avi@qumranet.com>
@@ -36,6 +37,8 @@
 #include <asm/vmx.h>
 #include <asm/virtext.h>
 #include <asm/mce.h>
+#include <asm/i387.h>
+#include <asm/xcr.h>
 
 #include "trace.h"
 
@@ -63,6 +66,9 @@ module_param_named(unrestricted_guest,
 static int __read_mostly emulate_invalid_guest_state = 0;
 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 
+static int __read_mostly vmm_exclusive = 1;
+module_param(vmm_exclusive, bool, S_IRUGO);
+
 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
 #define KVM_GUEST_CR0_MASK                                              \
@@ -173,10 +179,13 @@ static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 
 static int init_rmode(struct kvm *kvm);
 static u64 construct_eptp(unsigned long root_hpa);
+static void kvm_cpu_vmxon(u64 addr);
+static void kvm_cpu_vmxoff(void);
 
 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
+static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 
 static unsigned long *vmx_io_bitmap_a;
 static unsigned long *vmx_io_bitmap_b;
@@ -231,14 +240,14 @@ static u64 host_efer;
 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 
 /*
- * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
+ * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
  * away by decrementing the array size.
  */
 static const u32 vmx_msr_index[] = {
 #ifdef CONFIG_X86_64
         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 #endif
-        MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
+        MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 };
 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 
@@ -334,6 +343,11 @@ static inline bool cpu_has_vmx_ept_1g_page(void)
         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 }
 
+static inline bool cpu_has_vmx_ept_4levels(void)
+{
+        return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
+}
+
 static inline bool cpu_has_vmx_invept_individual_addr(void)
 {
         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
@@ -349,6 +363,16 @@ static inline bool cpu_has_vmx_invept_global(void)
         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 }
 
+static inline bool cpu_has_vmx_invvpid_single(void)
+{
+        return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
+}
+
+static inline bool cpu_has_vmx_invvpid_global(void)
+{
+        return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
+}
+
 static inline bool cpu_has_vmx_ept(void)
 {
         return vmcs_config.cpu_based_2nd_exec_ctrl &
@@ -389,6 +413,12 @@ static inline bool cpu_has_virtual_nmis(void)
         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 }
 
+static inline bool cpu_has_vmx_wbinvd_exit(void)
+{
+        return vmcs_config.cpu_based_2nd_exec_ctrl &
+                SECONDARY_EXEC_WBINVD_EXITING;
+}
+
 static inline bool report_flexpriority(void)
 {
         return flexpriority_enabled;
@@ -453,6 +483,19 @@ static void vmcs_clear(struct vmcs *vmcs)
                        vmcs, phys_addr);
 }
 
+static void vmcs_load(struct vmcs *vmcs)
+{
+        u64 phys_addr = __pa(vmcs);
+        u8 error;
+
+        asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
+                        : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
+                        : "cc", "memory");
+        if (error)
+                printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
+                       vmcs, phys_addr);
+}
+
 static void __vcpu_clear(void *arg)
 {
         struct vcpu_vmx *vmx = arg;
@@ -475,12 +518,27 @@ static void vcpu_clear(struct vcpu_vmx *vmx)
         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 }
 
-static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
+static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 {
         if (vmx->vpid == 0)
                 return;
 
-        __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
+        if (cpu_has_vmx_invvpid_single())
+                __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
+}
+
+static inline void vpid_sync_vcpu_global(void)
+{
+        if (cpu_has_vmx_invvpid_global())
+                __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
+}
+
+static inline void vpid_sync_context(struct vcpu_vmx *vmx)
+{
+        if (cpu_has_vmx_invvpid_single())
+                vpid_sync_vcpu_single(vmx);
+        else
+                vpid_sync_vcpu_global();
 }
 
 static inline void ept_sync_global(void)
@@ -812,6 +870,9 @@ static void __vmx_load_host_state(struct vcpu_vmx *vmx)
                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
         }
 #endif
+        if (current_thread_info()->status & TS_USEDFPU)
+                clts();
+        load_gdt(&__get_cpu_var(host_gdt));
 }
 
 static void vmx_load_host_state(struct vcpu_vmx *vmx)
@@ -828,35 +889,30 @@ static void vmx_load_host_state(struct vcpu_vmx *vmx)
 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
         struct vcpu_vmx *vmx = to_vmx(vcpu);
-        u64 phys_addr = __pa(vmx->vmcs);
         u64 tsc_this, delta, new_offset;
+        u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 
-        if (vcpu->cpu != cpu) {
+        if (!vmm_exclusive)
+                kvm_cpu_vmxon(phys_addr);
+        else if (vcpu->cpu != cpu)
                 vcpu_clear(vmx);
-                kvm_migrate_timers(vcpu);
-                set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
-                local_irq_disable();
-                list_add(&vmx->local_vcpus_link,
-                         &per_cpu(vcpus_on_cpu, cpu));
-                local_irq_enable();
-        }
 
         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
-                u8 error;
-
                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
-                asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
-                              : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
-                              : "cc");
-                if (error)
-                        printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
-                               vmx->vmcs, phys_addr);
+                vmcs_load(vmx->vmcs);
         }
 
         if (vcpu->cpu != cpu) {
                 struct desc_ptr dt;
                 unsigned long sysenter_esp;
 
+                kvm_migrate_timers(vcpu);
+                kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
+                local_irq_disable();
+                list_add(&vmx->local_vcpus_link,
+                         &per_cpu(vcpus_on_cpu, cpu));
+                local_irq_enable();
+
                 vcpu->cpu = cpu;
                 /*
                  * Linux uses per-cpu TSS and GDT, so set these when switching
@@ -884,6 +940,10 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 {
         __vmx_load_host_state(to_vmx(vcpu));
+        if (!vmm_exclusive) {
+                __vcpu_clear(to_vmx(vcpu));
+                kvm_cpu_vmxoff();
+        }
 }
 
 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
@@ -1057,10 +1117,10 @@ static void setup_msrs(struct vcpu_vmx *vmx)
                 if (index >= 0 && vmx->rdtscp_enabled)
                         move_msr_up(vmx, index, save_nmsrs++);
                 /*
-                 * MSR_K6_STAR is only needed on long mode guests, and only
+                 * MSR_STAR is only needed on long mode guests, and only
                  * if efer.sce is enabled.
                  */
-                index = __find_msr_index(vmx, MSR_K6_STAR);
+                index = __find_msr_index(vmx, MSR_STAR);
                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
                         move_msr_up(vmx, index, save_nmsrs++);
         }
@@ -1286,6 +1346,13 @@ static __init int vmx_disabled_by_bios(void)
         /* locked but not enabled */
 }
 
+static void kvm_cpu_vmxon(u64 addr)
+{
+        asm volatile (ASM_VMX_VMXON_RAX
+                        : : "a"(&addr), "m"(addr)
+                        : "memory", "cc");
+}
+
 static int hardware_enable(void *garbage)
 {
         int cpu = raw_smp_processor_id();
@@ -1308,11 +1375,13 @@ static int hardware_enable(void *garbage)
                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
         }
         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
-        asm volatile (ASM_VMX_VMXON_RAX
-                      : : "a"(&phys_addr), "m"(phys_addr)
-                      : "memory", "cc");
 
-        ept_sync_global();
+        if (vmm_exclusive) {
+                kvm_cpu_vmxon(phys_addr);
+                ept_sync_global();
+        }
+
+        store_gdt(&__get_cpu_var(host_gdt));
 
         return 0;
 }
@@ -1334,13 +1403,15 @@ static void vmclear_local_vcpus(void)
 static void kvm_cpu_vmxoff(void)
 {
         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
-        write_cr4(read_cr4() & ~X86_CR4_VMXE);
 }
 
 static void hardware_disable(void *garbage)
 {
-        vmclear_local_vcpus();
-        kvm_cpu_vmxoff();
+        if (vmm_exclusive) {
+                vmclear_local_vcpus();
+                kvm_cpu_vmxoff();
+        }
+        write_cr4(read_cr4() & ~X86_CR4_VMXE);
 }
 
 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
@@ -1539,7 +1610,8 @@ static __init int hardware_setup(void)
         if (!cpu_has_vmx_vpid())
                 enable_vpid = 0;
 
-        if (!cpu_has_vmx_ept()) {
+        if (!cpu_has_vmx_ept() ||
+            !cpu_has_vmx_ept_4levels()) {
                 enable_ept = 0;
                 enable_unrestricted_guest = 0;
         }
@@ -1628,7 +1700,7 @@ static gva_t rmode_tss_base(struct kvm *kvm)
                 gfn_t base_gfn;
 
                 slots = kvm_memslots(kvm);
-                base_gfn = kvm->memslots->memslots[0].base_gfn +
+                base_gfn = slots->memslots[0].base_gfn +
                                  kvm->memslots->memslots[0].npages - 3;
                 return base_gfn << PAGE_SHIFT;
         }
@@ -1759,9 +1831,12 @@ static void exit_lmode(struct kvm_vcpu *vcpu)
 
 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
 {
-        vpid_sync_vcpu_all(to_vmx(vcpu));
-        if (enable_ept)
+        vpid_sync_context(to_vmx(vcpu));
+        if (enable_ept) {
+                if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                        return;
                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
+        }
 }
 
 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
@@ -2507,7 +2582,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
 
-        vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
+        vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
 
@@ -2599,21 +2674,27 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 
 static int init_rmode(struct kvm *kvm)
 {
+        int idx, ret = 0;
+
+        idx = srcu_read_lock(&kvm->srcu);
         if (!init_rmode_tss(kvm))
-                return 0;
+                goto exit;
         if (!init_rmode_identity_map(kvm))
-                return 0;
-        return 1;
+                goto exit;
+
+        ret = 1;
+exit:
+        srcu_read_unlock(&kvm->srcu, idx);
+        return ret;
 }
 
 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
 {
         struct vcpu_vmx *vmx = to_vmx(vcpu);
         u64 msr;
-        int ret, idx;
+        int ret;
 
         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
-        idx = srcu_read_lock(&vcpu->kvm->srcu);
         if (!init_rmode(vmx->vcpu.kvm)) {
                 ret = -ENOMEM;
                 goto out;
@@ -2630,7 +2711,9 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
                 msr |= MSR_IA32_APICBASE_BSP;
         kvm_set_apic_base(&vmx->vcpu, msr);
 
-        fx_init(&vmx->vcpu);
+        ret = fx_init(&vmx->vcpu);
+        if (ret != 0)
+                goto out;
 
         seg_setup(VCPU_SREG_CS);
         /*
@@ -2713,7 +2796,7 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
         vmx_fpu_activate(&vmx->vcpu);
         update_exception_bitmap(&vmx->vcpu);
 
-        vpid_sync_vcpu_all(vmx);
+        vpid_sync_context(vmx);
 
         ret = 0;
 
@@ -2721,7 +2804,6 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
         vmx->emulation_required = 0;
 
 out:
-        srcu_read_unlock(&vcpu->kvm->srcu, idx);
         return ret;
 }
 
@@ -2826,9 +2908,7 @@ static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
 {
         if (!cpu_has_virtual_nmis())
                 return to_vmx(vcpu)->soft_vnmi_blocked;
-        else
-                return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
-                          GUEST_INTR_STATE_NMI);
+        return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
 }
 
 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
@@ -3070,7 +3150,7 @@ static int handle_io(struct kvm_vcpu *vcpu)
         ++vcpu->stat.io_exits;
 
         if (string || in)
-                return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
+                return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
 
         port = exit_qualification >> 16;
         size = (exit_qualification & 7) + 1;
@@ -3090,11 +3170,20 @@ vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
         hypercall[2] = 0xc1;
 }
 
+static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
+{
+        if (err)
+                kvm_inject_gp(vcpu, 0);
+        else
+                skip_emulated_instruction(vcpu);
+}
+
 static int handle_cr(struct kvm_vcpu *vcpu)
 {
         unsigned long exit_qualification, val;
         int cr;
         int reg;
+        int err;
 
         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
         cr = exit_qualification & 15;
@@ -3105,16 +3194,16 @@ static int handle_cr(struct kvm_vcpu *vcpu)
                 trace_kvm_cr_write(cr, val);
                 switch (cr) {
                 case 0:
-                        kvm_set_cr0(vcpu, val);
-                        skip_emulated_instruction(vcpu);
+                        err = kvm_set_cr0(vcpu, val);
+                        complete_insn_gp(vcpu, err);
                         return 1;
                 case 3:
-                        kvm_set_cr3(vcpu, val);
-                        skip_emulated_instruction(vcpu);
+                        err = kvm_set_cr3(vcpu, val);
+                        complete_insn_gp(vcpu, err);
                         return 1;
                 case 4:
-                        kvm_set_cr4(vcpu, val);
-                        skip_emulated_instruction(vcpu);
+                        err = kvm_set_cr4(vcpu, val);
+                        complete_insn_gp(vcpu, err);
                         return 1;
                 case 8: {
                                 u8 cr8_prev = kvm_get_cr8(vcpu);
@@ -3321,30 +3410,25 @@ static int handle_invlpg(struct kvm_vcpu *vcpu)
 static int handle_wbinvd(struct kvm_vcpu *vcpu)
 {
         skip_emulated_instruction(vcpu);
-        /* TODO: Add support for VT-d/pass-through device */
+        kvm_emulate_wbinvd(vcpu);
         return 1;
 }
 
-static int handle_apic_access(struct kvm_vcpu *vcpu)
+static int handle_xsetbv(struct kvm_vcpu *vcpu)
 {
-        unsigned long exit_qualification;
-        enum emulation_result er;
-        unsigned long offset;
+        u64 new_bv = kvm_read_edx_eax(vcpu);
+        u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
 
-        exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
-        offset = exit_qualification & 0xffful;
-
-        er = emulate_instruction(vcpu, 0, 0, 0);
-
-        if (er !=  EMULATE_DONE) {
-                printk(KERN_ERR
-                       "Fail to handle apic access vmexit! Offset is 0x%lx\n",
-                       offset);
-                return -ENOEXEC;
-        }
+        if (kvm_set_xcr(vcpu, index, new_bv) == 0)
+                skip_emulated_instruction(vcpu);
         return 1;
 }
 
+static int handle_apic_access(struct kvm_vcpu *vcpu)
+{
+        return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
+}
+
 static int handle_task_switch(struct kvm_vcpu *vcpu)
 {
         struct vcpu_vmx *vmx = to_vmx(vcpu);
@@ -3554,13 +3638,8 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
                         goto out;
                 }
 
-                if (err != EMULATE_DONE) {
-                        vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
-                        vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
-                        vcpu->run->internal.ndata = 0;
-                        ret = 0;
-                        goto out;
-                }
+                if (err != EMULATE_DONE)
+                        return 0;
 
                 if (signal_pending(current))
                         goto out;
@@ -3623,6 +3702,7 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
+        [EXIT_REASON_XSETBV]                  = handle_xsetbv,
         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
@@ -3656,6 +3736,13 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
         if (enable_ept && is_paging(vcpu))
                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
 
+        if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
+                vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
+                vcpu->run->fail_entry.hardware_entry_failure_reason
+                        = exit_reason;
+                return 0;
+        }
+
         if (unlikely(vmx->fail)) {
                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
                 vcpu->run->fail_entry.hardware_entry_failure_reason
@@ -3861,11 +3948,6 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
                 vmx_set_interrupt_shadow(vcpu, 0);
 
-        /*
-         * Loading guest fpu may have cleared host cr0.ts
-         */
-        vmcs_writel(HOST_CR0, read_cr0());
-
         asm(
                 /* Store host registers */
                 "push %%"R"dx; push %%"R"bp;"
@@ -4001,6 +4083,19 @@ static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
         kmem_cache_free(kvm_vcpu_cache, vmx);
 }
 
+static inline void vmcs_init(struct vmcs *vmcs)
+{
+        u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
+
+        if (!vmm_exclusive)
+                kvm_cpu_vmxon(phys_addr);
+
+        vmcs_clear(vmcs);
+
+        if (!vmm_exclusive)
+                kvm_cpu_vmxoff();
+}
+
 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
 {
         int err;
@@ -4026,7 +4121,7 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
         if (!vmx->vmcs)
                 goto free_msrs;
 
-        vmcs_clear(vmx->vmcs);
+        vmcs_init(vmx->vmcs);
 
         cpu = get_cpu();
         vmx_vcpu_load(&vmx->vcpu, cpu);
@@ -4265,6 +4360,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .rdtscp_supported = vmx_rdtscp_supported,
 
         .set_supported_cpuid = vmx_set_supported_cpuid,
+
+        .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
 };
 
 static int __init vmx_init(void)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 7fa89c39c64f..25f19078b321 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2006 Qumranet, Inc.
  * Copyright (C) 2008 Qumranet, Inc.
  * Copyright IBM Corporation, 2008
+ * Copyright 2010 Red Hat, Inc. and/or its affilates.
  *
  * Authors:
  *   Avi Kivity   <avi@qumranet.com>
@@ -41,17 +42,19 @@
 #include <linux/srcu.h>
 #include <linux/slab.h>
 #include <linux/perf_event.h>
+#include <linux/uaccess.h>
 #include <trace/events/kvm.h>
 
 #define CREATE_TRACE_POINTS
 #include "trace.h"
 
 #include <asm/debugreg.h>
-#include <asm/uaccess.h>
 #include <asm/msr.h>
 #include <asm/desc.h>
 #include <asm/mtrr.h>
 #include <asm/mce.h>
+#include <asm/i387.h>
+#include <asm/xcr.h>
 
 #define MAX_IO_MSRS 256
 #define CR0_RESERVED_BITS                                               \
@@ -62,6 +65,7 @@
         (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
                           | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \
                           | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR  \
+                          | X86_CR4_OSXSAVE \
                           | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
 
 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
@@ -147,6 +151,13 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
         { NULL }
 };
 
+u64 __read_mostly host_xcr0;
+
+static inline u32 bit(int bitno)
+{
+        return 1 << (bitno & 31);
+}
+
 static void kvm_on_user_return(struct user_return_notifier *urn)
 {
         unsigned slot;
@@ -285,7 +296,7 @@ static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
         prev_nr = vcpu->arch.exception.nr;
         if (prev_nr == DF_VECTOR) {
                 /* triple fault -> shutdown */
-                set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
+                kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
                 return;
         }
         class1 = exception_class(prev_nr);
@@ -414,121 +425,163 @@ out:
         return changed;
 }
 
-void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
+int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 {
+        unsigned long old_cr0 = kvm_read_cr0(vcpu);
+        unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
+                                    X86_CR0_CD | X86_CR0_NW;
+
         cr0 |= X86_CR0_ET;
 
 #ifdef CONFIG_X86_64
-        if (cr0 & 0xffffffff00000000UL) {
-                kvm_inject_gp(vcpu, 0);
-                return;
-        }
+        if (cr0 & 0xffffffff00000000UL)
+                return 1;
 #endif
 
         cr0 &= ~CR0_RESERVED_BITS;
 
-        if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
-                kvm_inject_gp(vcpu, 0);
-                return;
-        }
+        if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
+                return 1;
 
-        if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
-                kvm_inject_gp(vcpu, 0);
-                return;
-        }
+        if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
+                return 1;
 
         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 #ifdef CONFIG_X86_64
                 if ((vcpu->arch.efer & EFER_LME)) {
                         int cs_db, cs_l;
 
-                        if (!is_pae(vcpu)) {
-                                kvm_inject_gp(vcpu, 0);
-                                return;
-                        }
+                        if (!is_pae(vcpu))
+                                return 1;
                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
-                        if (cs_l) {
-                                kvm_inject_gp(vcpu, 0);
-                                return;
-
-                        }
+                        if (cs_l)
+                                return 1;
                 } else
 #endif
-                if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
-                        kvm_inject_gp(vcpu, 0);
-                        return;
-                }
-
+                if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
+                        return 1;
         }
 
         kvm_x86_ops->set_cr0(vcpu, cr0);
 
-        kvm_mmu_reset_context(vcpu);
-        return;
+        if ((cr0 ^ old_cr0) & update_bits)
+                kvm_mmu_reset_context(vcpu);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 
 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 {
-        kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
+        (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 }
 EXPORT_SYMBOL_GPL(kvm_lmsw);
 
-void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
+int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 {
-        unsigned long old_cr4 = kvm_read_cr4(vcpu);
-        unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
+        u64 xcr0;
 
-        if (cr4 & CR4_RESERVED_BITS) {
+        /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
+        if (index != XCR_XFEATURE_ENABLED_MASK)
+                return 1;
+        xcr0 = xcr;
+        if (kvm_x86_ops->get_cpl(vcpu) != 0)
+                return 1;
+        if (!(xcr0 & XSTATE_FP))
+                return 1;
+        if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
+                return 1;
+        if (xcr0 & ~host_xcr0)
+                return 1;
+        vcpu->arch.xcr0 = xcr0;
+        vcpu->guest_xcr0_loaded = 0;
+        return 0;
+}
+
+int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
+{
+        if (__kvm_set_xcr(vcpu, index, xcr)) {
                 kvm_inject_gp(vcpu, 0);
+                return 1;
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(kvm_set_xcr);
+
+static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 1, 0);
+        return best && (best->ecx & bit(X86_FEATURE_XSAVE));
+}
+
+static void update_cpuid(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 1, 0);
+        if (!best)
                 return;
+
+        /* Update OSXSAVE bit */
+        if (cpu_has_xsave && best->function == 0x1) {
+                best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
+                if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
+                        best->ecx |= bit(X86_FEATURE_OSXSAVE);
         }
+}
+
+int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
+{
+        unsigned long old_cr4 = kvm_read_cr4(vcpu);
+        unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
+
+        if (cr4 & CR4_RESERVED_BITS)
+                return 1;
+
+        if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
+                return 1;
 
         if (is_long_mode(vcpu)) {
-                if (!(cr4 & X86_CR4_PAE)) {
-                        kvm_inject_gp(vcpu, 0);
-                        return;
-                }
+                if (!(cr4 & X86_CR4_PAE))
+                        return 1;
         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
                    && ((cr4 ^ old_cr4) & pdptr_bits)
-                   && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
-                kvm_inject_gp(vcpu, 0);
-                return;
-        }
+                   && !load_pdptrs(vcpu, vcpu->arch.cr3))
+                return 1;
+
+        if (cr4 & X86_CR4_VMXE)
+                return 1;
 
-        if (cr4 & X86_CR4_VMXE) {
-                kvm_inject_gp(vcpu, 0);
-                return;
-        }
         kvm_x86_ops->set_cr4(vcpu, cr4);
-        vcpu->arch.cr4 = cr4;
-        kvm_mmu_reset_context(vcpu);
+
+        if ((cr4 ^ old_cr4) & pdptr_bits)
+                kvm_mmu_reset_context(vcpu);
+
+        if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
+                update_cpuid(vcpu);
+
+        return 0;
 }
 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 
-void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
+int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 {
         if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
                 kvm_mmu_sync_roots(vcpu);
                 kvm_mmu_flush_tlb(vcpu);
-                return;
+                return 0;
         }
 
         if (is_long_mode(vcpu)) {
-                if (cr3 & CR3_L_MODE_RESERVED_BITS) {
-                        kvm_inject_gp(vcpu, 0);
-                        return;
-                }
+                if (cr3 & CR3_L_MODE_RESERVED_BITS)
+                        return 1;
         } else {
                 if (is_pae(vcpu)) {
-                        if (cr3 & CR3_PAE_RESERVED_BITS) {
-                                kvm_inject_gp(vcpu, 0);
-                                return;
-                        }
-                        if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
-                                kvm_inject_gp(vcpu, 0);
-                                return;
-                        }
+                        if (cr3 & CR3_PAE_RESERVED_BITS)
+                                return 1;
+                        if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
+                                return 1;
                 }
                 /*
                  * We don't check reserved bits in nonpae mode, because
@@ -546,24 +599,28 @@ void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
          * to debug) behavior on the guest side.
          */
         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
-                kvm_inject_gp(vcpu, 0);
-        else {
-                vcpu->arch.cr3 = cr3;
-                vcpu->arch.mmu.new_cr3(vcpu);
-        }
+                return 1;
+        vcpu->arch.cr3 = cr3;
+        vcpu->arch.mmu.new_cr3(vcpu);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 
-void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
+int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 {
-        if (cr8 & CR8_RESERVED_BITS) {
-                kvm_inject_gp(vcpu, 0);
-                return;
-        }
+        if (cr8 & CR8_RESERVED_BITS)
+                return 1;
         if (irqchip_in_kernel(vcpu->kvm))
                 kvm_lapic_set_tpr(vcpu, cr8);
         else
                 vcpu->arch.cr8 = cr8;
+        return 0;
+}
+
+void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
+{
+        if (__kvm_set_cr8(vcpu, cr8))
+                kvm_inject_gp(vcpu, 0);
 }
 EXPORT_SYMBOL_GPL(kvm_set_cr8);
 
@@ -576,7 +633,7 @@ unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
 }
 EXPORT_SYMBOL_GPL(kvm_get_cr8);
 
-int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
+static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 {
         switch (dr) {
         case 0 ... 3:
@@ -585,29 +642,21 @@ int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
                         vcpu->arch.eff_db[dr] = val;
                 break;
         case 4:
-                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
-                        kvm_queue_exception(vcpu, UD_VECTOR);
-                        return 1;
-                }
+                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
+                        return 1; /* #UD */
                 /* fall through */
         case 6:
-                if (val & 0xffffffff00000000ULL) {
-                        kvm_inject_gp(vcpu, 0);
-                        return 1;
-                }
+                if (val & 0xffffffff00000000ULL)
+                        return -1; /* #GP */
                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
                 break;
         case 5:
-                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
-                        kvm_queue_exception(vcpu, UD_VECTOR);
-                        return 1;
-                }
+                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
+                        return 1; /* #UD */
                 /* fall through */
         default: /* 7 */
-                if (val & 0xffffffff00000000ULL) {
-                        kvm_inject_gp(vcpu, 0);
-                        return 1;
-                }
+                if (val & 0xffffffff00000000ULL)
+                        return -1; /* #GP */
                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
                         kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
@@ -618,28 +667,37 @@ int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 
         return 0;
 }
+
+int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
+{
+        int res;
+
+        res = __kvm_set_dr(vcpu, dr, val);
+        if (res > 0)
+                kvm_queue_exception(vcpu, UD_VECTOR);
+        else if (res < 0)
+                kvm_inject_gp(vcpu, 0);
+
+        return res;
+}
 EXPORT_SYMBOL_GPL(kvm_set_dr);
 
-int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
+static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 {
         switch (dr) {
         case 0 ... 3:
                 *val = vcpu->arch.db[dr];
                 break;
         case 4:
-                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
-                        kvm_queue_exception(vcpu, UD_VECTOR);
+                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
                         return 1;
-                }
                 /* fall through */
         case 6:
                 *val = vcpu->arch.dr6;
                 break;
         case 5:
-                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
-                        kvm_queue_exception(vcpu, UD_VECTOR);
+                if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
                         return 1;
-                }
                 /* fall through */
         default: /* 7 */
                 *val = vcpu->arch.dr7;
@@ -648,12 +706,16 @@ int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 
         return 0;
 }
-EXPORT_SYMBOL_GPL(kvm_get_dr);
 
-static inline u32 bit(int bitno)
+int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 {
-        return 1 << (bitno & 31);
+        if (_kvm_get_dr(vcpu, dr, val)) {
+                kvm_queue_exception(vcpu, UD_VECTOR);
+                return 1;
+        }
+        return 0;
 }
+EXPORT_SYMBOL_GPL(kvm_get_dr);
 
 /*
  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
@@ -671,7 +733,7 @@ static u32 msrs_to_save[] = {
         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
         HV_X64_MSR_APIC_ASSIST_PAGE,
         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
-        MSR_K6_STAR,
+        MSR_STAR,
 #ifdef CONFIG_X86_64
         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 #endif
@@ -682,10 +744,14 @@ static unsigned num_msrs_to_save;
 
 static u32 emulated_msrs[] = {
         MSR_IA32_MISC_ENABLE,
+        MSR_IA32_MCG_STATUS,
+        MSR_IA32_MCG_CTL,
 };
 
 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 {
+        u64 old_efer = vcpu->arch.efer;
+
         if (efer & efer_reserved_bits)
                 return 1;
 
@@ -714,11 +780,13 @@ static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 
         kvm_x86_ops->set_efer(vcpu, efer);
 
-        vcpu->arch.efer = efer;
-
         vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
         kvm_mmu_reset_context(vcpu);
 
+        /* Update reserved bits */
+        if ((efer ^ old_efer) & EFER_NX)
+                kvm_mmu_reset_context(vcpu);
+
         return 0;
 }
 
@@ -882,7 +950,7 @@ static int kvm_request_guest_time_update(struct kvm_vcpu *v)
 
         if (!vcpu->time_page)
                 return 0;
-        set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
+        kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
         return 1;
 }
 
@@ -1524,16 +1592,12 @@ static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
 {
         int i, idx;
 
-        vcpu_load(vcpu);
-
         idx = srcu_read_lock(&vcpu->kvm->srcu);
         for (i = 0; i < msrs->nmsrs; ++i)
                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
                         break;
         srcu_read_unlock(&vcpu->kvm->srcu, idx);
 
-        vcpu_put(vcpu);
-
         return i;
 }
 
@@ -1618,6 +1682,7 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_PCI_SEGMENT:
         case KVM_CAP_DEBUGREGS:
         case KVM_CAP_X86_ROBUST_SINGLESTEP:
+        case KVM_CAP_XSAVE:
                 r = 1;
                 break;
         case KVM_CAP_COALESCED_MMIO:
@@ -1641,6 +1706,9 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_MCE:
                 r = KVM_MAX_MCE_BANKS;
                 break;
+        case KVM_CAP_XCRS:
+                r = cpu_has_xsave;
+                break;
         default:
                 r = 0;
                 break;
@@ -1717,8 +1785,28 @@ out:
         return r;
 }
 
+static void wbinvd_ipi(void *garbage)
+{
+        wbinvd();
+}
+
+static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
+{
+        return vcpu->kvm->arch.iommu_domain &&
+                !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
+}
+
 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
+        /* Address WBINVD may be executed by guest */
+        if (need_emulate_wbinvd(vcpu)) {
+                if (kvm_x86_ops->has_wbinvd_exit())
+                        cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
+                else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
+                        smp_call_function_single(vcpu->cpu,
+                                        wbinvd_ipi, NULL, 1);
+        }
+
         kvm_x86_ops->vcpu_load(vcpu, cpu);
         if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
                 unsigned long khz = cpufreq_quick_get(cpu);
@@ -1731,8 +1819,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 
 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
 {
-        kvm_put_guest_fpu(vcpu);
         kvm_x86_ops->vcpu_put(vcpu);
+        kvm_put_guest_fpu(vcpu);
 }
 
 static int is_efer_nx(void)
@@ -1781,7 +1869,6 @@ static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
         if (copy_from_user(cpuid_entries, entries,
                            cpuid->nent * sizeof(struct kvm_cpuid_entry)))
                 goto out_free;
-        vcpu_load(vcpu);
         for (i = 0; i < cpuid->nent; i++) {
                 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
                 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
@@ -1799,7 +1886,7 @@ static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
         r = 0;
         kvm_apic_set_version(vcpu);
         kvm_x86_ops->cpuid_update(vcpu);
-        vcpu_put(vcpu);
+        update_cpuid(vcpu);
 
 out_free:
         vfree(cpuid_entries);
@@ -1820,11 +1907,10 @@ static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
         if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
                            cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
                 goto out;
-        vcpu_load(vcpu);
         vcpu->arch.cpuid_nent = cpuid->nent;
         kvm_apic_set_version(vcpu);
         kvm_x86_ops->cpuid_update(vcpu);
-        vcpu_put(vcpu);
+        update_cpuid(vcpu);
         return 0;
 
 out:
@@ -1837,7 +1923,6 @@ static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
 {
         int r;
 
-        vcpu_load(vcpu);
         r = -E2BIG;
         if (cpuid->nent < vcpu->arch.cpuid_nent)
                 goto out;
@@ -1849,7 +1934,6 @@ static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
 
 out:
         cpuid->nent = vcpu->arch.cpuid_nent;
-        vcpu_put(vcpu);
         return r;
 }
 
@@ -1901,13 +1985,13 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
         /* cpuid 1.ecx */
         const u32 kvm_supported_word4_x86_features =
-                F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
+                F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
                 0 /* DS-CPL, VMX, SMX, EST */ |
                 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
                 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
                 0 /* Reserved, DCA */ | F(XMM4_1) |
                 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
-                0 /* Reserved, XSAVE, OSXSAVE */;
+                0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
         /* cpuid 0x80000001.ecx */
         const u32 kvm_supported_word6_x86_features =
                 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
@@ -1922,7 +2006,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 
         switch (function) {
         case 0:
-                entry->eax = min(entry->eax, (u32)0xb);
+                entry->eax = min(entry->eax, (u32)0xd);
                 break;
         case 1:
                 entry->edx &= kvm_supported_word0_x86_features;
@@ -1980,6 +2064,20 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                 }
                 break;
         }
+        case 0xd: {
+                int i;
+
+                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                for (i = 1; *nent < maxnent; ++i) {
+                        if (entry[i - 1].eax == 0 && i != 2)
+                                break;
+                        do_cpuid_1_ent(&entry[i], function, i);
+                        entry[i].flags |=
+                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+                        ++*nent;
+                }
+                break;
+        }
         case KVM_CPUID_SIGNATURE: {
                 char signature[12] = "KVMKVMKVM\0\0";
                 u32 *sigptr = (u32 *)signature;
@@ -2081,9 +2179,7 @@ out:
 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
                                     struct kvm_lapic_state *s)
 {
-        vcpu_load(vcpu);
         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
-        vcpu_put(vcpu);
 
         return 0;
 }
@@ -2091,11 +2187,9 @@ static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
                                     struct kvm_lapic_state *s)
 {
-        vcpu_load(vcpu);
         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
         kvm_apic_post_state_restore(vcpu);
         update_cr8_intercept(vcpu);
-        vcpu_put(vcpu);
 
         return 0;
 }
@@ -2107,20 +2201,15 @@ static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
                 return -EINVAL;
         if (irqchip_in_kernel(vcpu->kvm))
                 return -ENXIO;
-        vcpu_load(vcpu);
 
         kvm_queue_interrupt(vcpu, irq->irq, false);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
 {
-        vcpu_load(vcpu);
         kvm_inject_nmi(vcpu);
-        vcpu_put(vcpu);
 
         return 0;
 }
@@ -2140,7 +2229,6 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
         int r;
         unsigned bank_num = mcg_cap & 0xff, bank;
 
-        vcpu_load(vcpu);
         r = -EINVAL;
         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
                 goto out;
@@ -2155,7 +2243,6 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
         for (bank = 0; bank < bank_num; bank++)
                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
 out:
-        vcpu_put(vcpu);
         return r;
 }
 
@@ -2188,7 +2275,7 @@ static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
                         printk(KERN_DEBUG "kvm: set_mce: "
                                "injects mce exception while "
                                "previous one is in progress!\n");
-                        set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
+                        kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
                         return 0;
                 }
                 if (banks[1] & MCI_STATUS_VAL)
@@ -2213,8 +2300,6 @@ static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
                                                struct kvm_vcpu_events *events)
 {
-        vcpu_load(vcpu);
-
         events->exception.injected =
                 vcpu->arch.exception.pending &&
                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
@@ -2239,8 +2324,6 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
                          | KVM_VCPUEVENT_VALID_SHADOW);
-
-        vcpu_put(vcpu);
 }
 
 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
@@ -2251,8 +2334,6 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
                               | KVM_VCPUEVENT_VALID_SHADOW))
                 return -EINVAL;
 
-        vcpu_load(vcpu);
-
         vcpu->arch.exception.pending = events->exception.injected;
         vcpu->arch.exception.nr = events->exception.nr;
         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
@@ -2275,22 +2356,16 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
                 vcpu->arch.sipi_vector = events->sipi_vector;
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
                                              struct kvm_debugregs *dbgregs)
 {
-        vcpu_load(vcpu);
-
         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
         dbgregs->dr6 = vcpu->arch.dr6;
         dbgregs->dr7 = vcpu->arch.dr7;
         dbgregs->flags = 0;
-
-        vcpu_put(vcpu);
 }
 
 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
@@ -2299,40 +2374,113 @@ static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
         if (dbgregs->flags)
                 return -EINVAL;
 
-        vcpu_load(vcpu);
-
         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
         vcpu->arch.dr6 = dbgregs->dr6;
         vcpu->arch.dr7 = dbgregs->dr7;
 
-        vcpu_put(vcpu);
+        return 0;
+}
+
+static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
+                                         struct kvm_xsave *guest_xsave)
+{
+        if (cpu_has_xsave)
+                memcpy(guest_xsave->region,
+                        &vcpu->arch.guest_fpu.state->xsave,
+                        sizeof(struct xsave_struct));
+        else {
+                memcpy(guest_xsave->region,
+                        &vcpu->arch.guest_fpu.state->fxsave,
+                        sizeof(struct i387_fxsave_struct));
+                *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
+                        XSTATE_FPSSE;
+        }
+}
+
+static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
+                                        struct kvm_xsave *guest_xsave)
+{
+        u64 xstate_bv =
+                *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
 
+        if (cpu_has_xsave)
+                memcpy(&vcpu->arch.guest_fpu.state->xsave,
+                        guest_xsave->region, sizeof(struct xsave_struct));
+        else {
+                if (xstate_bv & ~XSTATE_FPSSE)
+                        return -EINVAL;
+                memcpy(&vcpu->arch.guest_fpu.state->fxsave,
+                        guest_xsave->region, sizeof(struct i387_fxsave_struct));
+        }
         return 0;
 }
 
+static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
+                                        struct kvm_xcrs *guest_xcrs)
+{
+        if (!cpu_has_xsave) {
+                guest_xcrs->nr_xcrs = 0;
+                return;
+        }
+
+        guest_xcrs->nr_xcrs = 1;
+        guest_xcrs->flags = 0;
+        guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
+        guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
+}
+
+static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
+                                       struct kvm_xcrs *guest_xcrs)
+{
+        int i, r = 0;
+
+        if (!cpu_has_xsave)
+                return -EINVAL;
+
+        if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
+                return -EINVAL;
+
+        for (i = 0; i < guest_xcrs->nr_xcrs; i++)
+                /* Only support XCR0 currently */
+                if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
+                        r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
+                                guest_xcrs->xcrs[0].value);
+                        break;
+                }
+        if (r)
+                r = -EINVAL;
+        return r;
+}
+
 long kvm_arch_vcpu_ioctl(struct file *filp,
                          unsigned int ioctl, unsigned long arg)
 {
         struct kvm_vcpu *vcpu = filp->private_data;
         void __user *argp = (void __user *)arg;
         int r;
-        struct kvm_lapic_state *lapic = NULL;
+        union {
+                struct kvm_lapic_state *lapic;
+                struct kvm_xsave *xsave;
+                struct kvm_xcrs *xcrs;
+                void *buffer;
+        } u;
 
+        u.buffer = NULL;
         switch (ioctl) {
         case KVM_GET_LAPIC: {
                 r = -EINVAL;
                 if (!vcpu->arch.apic)
                         goto out;
-                lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
+                u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
 
                 r = -ENOMEM;
-                if (!lapic)
+                if (!u.lapic)
                         goto out;
-                r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
+                r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
                 if (r)
                         goto out;
                 r = -EFAULT;
-                if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
+                if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
                         goto out;
                 r = 0;
                 break;
@@ -2341,14 +2489,14 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 r = -EINVAL;
                 if (!vcpu->arch.apic)
                         goto out;
-                lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
+                u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
                 r = -ENOMEM;
-                if (!lapic)
+                if (!u.lapic)
                         goto out;
                 r = -EFAULT;
-                if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
+                if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
                         goto out;
-                r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
+                r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
                 if (r)
                         goto out;
                 r = 0;
@@ -2464,9 +2612,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 r = -EFAULT;
                 if (copy_from_user(&mce, argp, sizeof mce))
                         goto out;
-                vcpu_load(vcpu);
                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
-                vcpu_put(vcpu);
                 break;
         }
         case KVM_GET_VCPU_EVENTS: {
@@ -2513,11 +2659,67 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
                 break;
         }
+        case KVM_GET_XSAVE: {
+                u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
+                r = -ENOMEM;
+                if (!u.xsave)
+                        break;
+
+                kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
+
+                r = -EFAULT;
+                if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
+                        break;
+                r = 0;
+                break;
+        }
+        case KVM_SET_XSAVE: {
+                u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
+                r = -ENOMEM;
+                if (!u.xsave)
+                        break;
+
+                r = -EFAULT;
+                if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
+                        break;
+
+                r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
+                break;
+        }
+        case KVM_GET_XCRS: {
+                u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
+                r = -ENOMEM;
+                if (!u.xcrs)
+                        break;
+
+                kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
+
+                r = -EFAULT;
+                if (copy_to_user(argp, u.xcrs,
+                                 sizeof(struct kvm_xcrs)))
+                        break;
+                r = 0;
+                break;
+        }
+        case KVM_SET_XCRS: {
+                u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
+                r = -ENOMEM;
+                if (!u.xcrs)
+                        break;
+
+                r = -EFAULT;
+                if (copy_from_user(u.xcrs, argp,
+                                   sizeof(struct kvm_xcrs)))
+                        break;
+
+                r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
+                break;
+        }
         default:
                 r = -EINVAL;
         }
 out:
-        kfree(lapic);
+        kfree(u.buffer);
         return r;
 }
 
@@ -2560,115 +2762,6 @@ static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
         return kvm->arch.n_alloc_mmu_pages;
 }
 
-gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
-{
-        int i;
-        struct kvm_mem_alias *alias;
-        struct kvm_mem_aliases *aliases;
-
-        aliases = kvm_aliases(kvm);
-
-        for (i = 0; i < aliases->naliases; ++i) {
-                alias = &aliases->aliases[i];
-                if (alias->flags & KVM_ALIAS_INVALID)
-                        continue;
-                if (gfn >= alias->base_gfn
-                    && gfn < alias->base_gfn + alias->npages)
-                        return alias->target_gfn + gfn - alias->base_gfn;
-        }
-        return gfn;
-}
-
-gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
-{
-        int i;
-        struct kvm_mem_alias *alias;
-        struct kvm_mem_aliases *aliases;
-
-        aliases = kvm_aliases(kvm);
-
-        for (i = 0; i < aliases->naliases; ++i) {
-                alias = &aliases->aliases[i];
-                if (gfn >= alias->base_gfn
-                    && gfn < alias->base_gfn + alias->npages)
-                        return alias->target_gfn + gfn - alias->base_gfn;
-        }
-        return gfn;
-}
-
-/*
- * Set a new alias region.  Aliases map a portion of physical memory into
- * another portion.  This is useful for memory windows, for example the PC
- * VGA region.
- */
-static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
-                                         struct kvm_memory_alias *alias)
-{
-        int r, n;
-        struct kvm_mem_alias *p;
-        struct kvm_mem_aliases *aliases, *old_aliases;
-
-        r = -EINVAL;
-        /* General sanity checks */
-        if (alias->memory_size & (PAGE_SIZE - 1))
-                goto out;
-        if (alias->guest_phys_addr & (PAGE_SIZE - 1))
-                goto out;
-        if (alias->slot >= KVM_ALIAS_SLOTS)
-                goto out;
-        if (alias->guest_phys_addr + alias->memory_size
-            < alias->guest_phys_addr)
-                goto out;
-        if (alias->target_phys_addr + alias->memory_size
-            < alias->target_phys_addr)
-                goto out;
-
-        r = -ENOMEM;
-        aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
-        if (!aliases)
-                goto out;
-
-        mutex_lock(&kvm->slots_lock);
-
-        /* invalidate any gfn reference in case of deletion/shrinking */
-        memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
-        aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
-        old_aliases = kvm->arch.aliases;
-        rcu_assign_pointer(kvm->arch.aliases, aliases);
-        synchronize_srcu_expedited(&kvm->srcu);
-        kvm_mmu_zap_all(kvm);
-        kfree(old_aliases);
-
-        r = -ENOMEM;
-        aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
-        if (!aliases)
-                goto out_unlock;
-
-        memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
-
-        p = &aliases->aliases[alias->slot];
-        p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
-        p->npages = alias->memory_size >> PAGE_SHIFT;
-        p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
-        p->flags &= ~(KVM_ALIAS_INVALID);
-
-        for (n = KVM_ALIAS_SLOTS; n > 0; --n)
-                if (aliases->aliases[n - 1].npages)
-                        break;
-        aliases->naliases = n;
-
-        old_aliases = kvm->arch.aliases;
-        rcu_assign_pointer(kvm->arch.aliases, aliases);
-        synchronize_srcu_expedited(&kvm->srcu);
-        kfree(old_aliases);
-        r = 0;
-
-out_unlock:
-        mutex_unlock(&kvm->slots_lock);
-out:
-        return r;
-}
-
 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
 {
         int r;
@@ -2797,7 +2890,6 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
         struct kvm_memory_slot *memslot;
         unsigned long n;
         unsigned long is_dirty = 0;
-        unsigned long *dirty_bitmap = NULL;
 
         mutex_lock(&kvm->slots_lock);
 
@@ -2812,27 +2904,30 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
 
         n = kvm_dirty_bitmap_bytes(memslot);
 
-        r = -ENOMEM;
-        dirty_bitmap = vmalloc(n);
-        if (!dirty_bitmap)
-                goto out;
-        memset(dirty_bitmap, 0, n);
-
         for (i = 0; !is_dirty && i < n/sizeof(long); i++)
                 is_dirty = memslot->dirty_bitmap[i];
 
         /* If nothing is dirty, don't bother messing with page tables. */
         if (is_dirty) {
                 struct kvm_memslots *slots, *old_slots;
+                unsigned long *dirty_bitmap;
 
                 spin_lock(&kvm->mmu_lock);
                 kvm_mmu_slot_remove_write_access(kvm, log->slot);
                 spin_unlock(&kvm->mmu_lock);
 
-                slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
-                if (!slots)
-                        goto out_free;
+                r = -ENOMEM;
+                dirty_bitmap = vmalloc(n);
+                if (!dirty_bitmap)
+                        goto out;
+                memset(dirty_bitmap, 0, n);
 
+                r = -ENOMEM;
+                slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
+                if (!slots) {
+                        vfree(dirty_bitmap);
+                        goto out;
+                }
                 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
                 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
 
@@ -2841,13 +2936,20 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
                 synchronize_srcu_expedited(&kvm->srcu);
                 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
                 kfree(old_slots);
+
+                r = -EFAULT;
+                if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
+                        vfree(dirty_bitmap);
+                        goto out;
+                }
+                vfree(dirty_bitmap);
+        } else {
+                r = -EFAULT;
+                if (clear_user(log->dirty_bitmap, n))
+                        goto out;
         }
 
         r = 0;
-        if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
-                r = -EFAULT;
-out_free:
-        vfree(dirty_bitmap);
 out:
         mutex_unlock(&kvm->slots_lock);
         return r;
@@ -2867,7 +2969,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
         union {
                 struct kvm_pit_state ps;
                 struct kvm_pit_state2 ps2;
-                struct kvm_memory_alias alias;
                 struct kvm_pit_config pit_config;
         } u;
 
@@ -2888,22 +2989,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
                         goto out;
                 break;
         }
-        case KVM_SET_MEMORY_REGION: {
-                struct kvm_memory_region kvm_mem;
-                struct kvm_userspace_memory_region kvm_userspace_mem;
-
-                r = -EFAULT;
-                if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
-                        goto out;
-                kvm_userspace_mem.slot = kvm_mem.slot;
-                kvm_userspace_mem.flags = kvm_mem.flags;
-                kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
-                kvm_userspace_mem.memory_size = kvm_mem.memory_size;
-                r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
-                if (r)
-                        goto out;
-                break;
-        }
         case KVM_SET_NR_MMU_PAGES:
                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
                 if (r)
@@ -2912,14 +2997,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
         case KVM_GET_NR_MMU_PAGES:
                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
                 break;
-        case KVM_SET_MEMORY_ALIAS:
-                r = -EFAULT;
-                if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
-                        goto out;
-                r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
-                if (r)
-                        goto out;
-                break;
         case KVM_CREATE_IRQCHIP: {
                 struct kvm_pic *vpic;
 
@@ -3259,7 +3336,7 @@ static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
                 }
                 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
                 if (ret < 0) {
-                        r = X86EMUL_UNHANDLEABLE;
+                        r = X86EMUL_IO_NEEDED;
                         goto out;
                 }
 
@@ -3315,7 +3392,7 @@ static int kvm_write_guest_virt_system(gva_t addr, void *val,
                 }
                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
                 if (ret < 0) {
-                        r = X86EMUL_UNHANDLEABLE;
+                        r = X86EMUL_IO_NEEDED;
                         goto out;
                 }
 
@@ -3330,10 +3407,10 @@ out:
 static int emulator_read_emulated(unsigned long addr,
                                   void *val,
                                   unsigned int bytes,
+                                  unsigned int *error_code,
                                   struct kvm_vcpu *vcpu)
 {
         gpa_t                 gpa;
-        u32 error_code;
 
         if (vcpu->mmio_read_completed) {
                 memcpy(val, vcpu->mmio_data, bytes);
@@ -3343,12 +3420,10 @@ static int emulator_read_emulated(unsigned long addr,
                 return X86EMUL_CONTINUE;
         }
 
-        gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
+        gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
 
-        if (gpa == UNMAPPED_GVA) {
-                kvm_inject_page_fault(vcpu, addr, error_code);
+        if (gpa == UNMAPPED_GVA)
                 return X86EMUL_PROPAGATE_FAULT;
-        }
 
         /* For APIC access vmexit */
         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
@@ -3370,11 +3445,12 @@ mmio:
         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
 
         vcpu->mmio_needed = 1;
-        vcpu->mmio_phys_addr = gpa;
-        vcpu->mmio_size = bytes;
-        vcpu->mmio_is_write = 0;
+        vcpu->run->exit_reason = KVM_EXIT_MMIO;
+        vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
+        vcpu->run->mmio.len = vcpu->mmio_size = bytes;
+        vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
 
-        return X86EMUL_UNHANDLEABLE;
+        return X86EMUL_IO_NEEDED;
 }
 
 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
@@ -3392,17 +3468,15 @@ int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
 static int emulator_write_emulated_onepage(unsigned long addr,
                                            const void *val,
                                            unsigned int bytes,
+                                           unsigned int *error_code,
                                            struct kvm_vcpu *vcpu)
 {
         gpa_t                 gpa;
-        u32 error_code;
 
-        gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
+        gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
 
-        if (gpa == UNMAPPED_GVA) {
-                kvm_inject_page_fault(vcpu, addr, error_code);
+        if (gpa == UNMAPPED_GVA)
                 return X86EMUL_PROPAGATE_FAULT;
-        }
 
         /* For APIC access vmexit */
         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
@@ -3420,10 +3494,11 @@ mmio:
                 return X86EMUL_CONTINUE;
 
         vcpu->mmio_needed = 1;
-        vcpu->mmio_phys_addr = gpa;
-        vcpu->mmio_size = bytes;
-        vcpu->mmio_is_write = 1;
-        memcpy(vcpu->mmio_data, val, bytes);
+        vcpu->run->exit_reason = KVM_EXIT_MMIO;
+        vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
+        vcpu->run->mmio.len = vcpu->mmio_size = bytes;
+        vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
+        memcpy(vcpu->run->mmio.data, val, bytes);
 
         return X86EMUL_CONTINUE;
 }
@@ -3431,6 +3506,7 @@ mmio:
 int emulator_write_emulated(unsigned long addr,
                             const void *val,
                             unsigned int bytes,
+                            unsigned int *error_code,
                             struct kvm_vcpu *vcpu)
 {
         /* Crossing a page boundary? */
@@ -3438,16 +3514,17 @@ int emulator_write_emulated(unsigned long addr,
                 int rc, now;
 
                 now = -addr & ~PAGE_MASK;
-                rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
+                rc = emulator_write_emulated_onepage(addr, val, now, error_code,
+                                                     vcpu);
                 if (rc != X86EMUL_CONTINUE)
                         return rc;
                 addr += now;
                 val += now;
                 bytes -= now;
         }
-        return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
+        return emulator_write_emulated_onepage(addr, val, bytes, error_code,
+                                               vcpu);
 }
-EXPORT_SYMBOL_GPL(emulator_write_emulated);
 
 #define CMPXCHG_TYPE(t, ptr, old, new) \
         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
@@ -3463,6 +3540,7 @@ static int emulator_cmpxchg_emulated(unsigned long addr,
                                      const void *old,
                                      const void *new,
                                      unsigned int bytes,
+                                     unsigned int *error_code,
                                      struct kvm_vcpu *vcpu)
 {
         gpa_t gpa;
@@ -3484,6 +3562,10 @@ static int emulator_cmpxchg_emulated(unsigned long addr,
                 goto emul_write;
 
         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
+        if (is_error_page(page)) {
+                kvm_release_page_clean(page);
+                goto emul_write;
+        }
 
         kaddr = kmap_atomic(page, KM_USER0);
         kaddr += offset_in_page(gpa);
@@ -3516,7 +3598,7 @@ static int emulator_cmpxchg_emulated(unsigned long addr,
 emul_write:
         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
 
-        return emulator_write_emulated(addr, new, bytes, vcpu);
+        return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
 }
 
 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
@@ -3604,42 +3686,38 @@ int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
         return X86EMUL_CONTINUE;
 }
 
-int emulate_clts(struct kvm_vcpu *vcpu)
+int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
 {
-        kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
-        kvm_x86_ops->fpu_activate(vcpu);
+        if (!need_emulate_wbinvd(vcpu))
+                return X86EMUL_CONTINUE;
+
+        if (kvm_x86_ops->has_wbinvd_exit()) {
+                smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
+                                wbinvd_ipi, NULL, 1);
+                cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
+        }
+        wbinvd();
         return X86EMUL_CONTINUE;
 }
+EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
 
-int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
+int emulate_clts(struct kvm_vcpu *vcpu)
 {
-        return kvm_get_dr(ctxt->vcpu, dr, dest);
+        kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
+        kvm_x86_ops->fpu_activate(vcpu);
+        return X86EMUL_CONTINUE;
 }
 
-int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
+int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
 {
-        unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
-
-        return kvm_set_dr(ctxt->vcpu, dr, value & mask);
+        return _kvm_get_dr(vcpu, dr, dest);
 }
 
-void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
+int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
 {
-        u8 opcodes[4];
-        unsigned long rip = kvm_rip_read(vcpu);
-        unsigned long rip_linear;
-
-        if (!printk_ratelimit())
-                return;
 
-        rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
-
-        kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
-
-        printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
-               context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
+        return __kvm_set_dr(vcpu, dr, value);
 }
-EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
 
 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
 {
@@ -3674,27 +3752,32 @@ static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
         return value;
 }
 
-static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
+static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
 {
+        int res = 0;
+
         switch (cr) {
         case 0:
-                kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
+                res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
                 break;
         case 2:
                 vcpu->arch.cr2 = val;
                 break;
         case 3:
-                kvm_set_cr3(vcpu, val);
+                res = kvm_set_cr3(vcpu, val);
                 break;
         case 4:
-                kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
+                res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
                 break;
         case 8:
-                kvm_set_cr8(vcpu, val & 0xfUL);
+                res = __kvm_set_cr8(vcpu, val & 0xfUL);
                 break;
         default:
                 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
+                res = -1;
         }
+
+        return res;
 }
 
 static int emulator_get_cpl(struct kvm_vcpu *vcpu)
@@ -3707,6 +3790,12 @@ static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
         kvm_x86_ops->get_gdt(vcpu, dt);
 }
 
+static unsigned long emulator_get_cached_segment_base(int seg,
+                                                      struct kvm_vcpu *vcpu)
+{
+        return get_segment_base(vcpu, seg);
+}
+
 static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
                                            struct kvm_vcpu *vcpu)
 {
@@ -3779,11 +3868,6 @@ static void emulator_set_segment_selector(u16 sel, int seg,
         kvm_set_segment(vcpu, &kvm_seg, seg);
 }
 
-static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
-{
-        kvm_x86_ops->set_rflags(vcpu, rflags);
-}
-
 static struct x86_emulate_ops emulate_ops = {
         .read_std            = kvm_read_guest_virt_system,
         .write_std           = kvm_write_guest_virt_system,
@@ -3797,11 +3881,15 @@ static struct x86_emulate_ops emulate_ops = {
         .set_cached_descriptor = emulator_set_cached_descriptor,
         .get_segment_selector = emulator_get_segment_selector,
         .set_segment_selector = emulator_set_segment_selector,
+        .get_cached_segment_base = emulator_get_cached_segment_base,
         .get_gdt             = emulator_get_gdt,
         .get_cr              = emulator_get_cr,
         .set_cr              = emulator_set_cr,
         .cpl                 = emulator_get_cpl,
-        .set_rflags          = emulator_set_rflags,
+        .get_dr              = emulator_get_dr,
+        .set_dr              = emulator_set_dr,
+        .set_msr             = kvm_set_msr,
+        .get_msr             = kvm_get_msr,
 };
 
 static void cache_all_regs(struct kvm_vcpu *vcpu)
@@ -3812,14 +3900,75 @@ static void cache_all_regs(struct kvm_vcpu *vcpu)
         vcpu->arch.regs_dirty = ~0;
 }
 
+static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
+{
+        u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
+        /*
+         * an sti; sti; sequence only disable interrupts for the first
+         * instruction. So, if the last instruction, be it emulated or
+         * not, left the system with the INT_STI flag enabled, it
+         * means that the last instruction is an sti. We should not
+         * leave the flag on in this case. The same goes for mov ss
+         */
+        if (!(int_shadow & mask))
+                kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
+}
+
+static void inject_emulated_exception(struct kvm_vcpu *vcpu)
+{
+        struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
+        if (ctxt->exception == PF_VECTOR)
+                kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
+        else if (ctxt->error_code_valid)
+                kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
+        else
+                kvm_queue_exception(vcpu, ctxt->exception);
+}
+
+static int handle_emulation_failure(struct kvm_vcpu *vcpu)
+{
+        ++vcpu->stat.insn_emulation_fail;
+        trace_kvm_emulate_insn_failed(vcpu);
+        vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+        vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
+        vcpu->run->internal.ndata = 0;
+        kvm_queue_exception(vcpu, UD_VECTOR);
+        return EMULATE_FAIL;
+}
+
+static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
+{
+        gpa_t gpa;
+
+        if (tdp_enabled)
+                return false;
+
+        /*
+         * if emulation was due to access to shadowed page table
+         * and it failed try to unshadow page and re-entetr the
+         * guest to let CPU execute the instruction.
+         */
+        if (kvm_mmu_unprotect_page_virt(vcpu, gva))
+                return true;
+
+        gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
+
+        if (gpa == UNMAPPED_GVA)
+                return true; /* let cpu generate fault */
+
+        if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
+                return true;
+
+        return false;
+}
+
 int emulate_instruction(struct kvm_vcpu *vcpu,
                         unsigned long cr2,
                         u16 error_code,
                         int emulation_type)
 {
-        int r, shadow_mask;
-        struct decode_cache *c;
-        struct kvm_run *run = vcpu->run;
+        int r;
+        struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
 
         kvm_clear_exception_queue(vcpu);
         vcpu->arch.mmio_fault_cr2 = cr2;
@@ -3831,8 +3980,6 @@ int emulate_instruction(struct kvm_vcpu *vcpu,
          */
         cache_all_regs(vcpu);
 
-        vcpu->mmio_is_write = 0;
-
         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
                 int cs_db, cs_l;
                 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
@@ -3846,13 +3993,16 @@ int emulate_instruction(struct kvm_vcpu *vcpu,
                         ? X86EMUL_MODE_VM86 : cs_l
                         ? X86EMUL_MODE_PROT64 : cs_db
                         ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
+                memset(c, 0, sizeof(struct decode_cache));
+                memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
+                vcpu->arch.emulate_ctxt.interruptibility = 0;
+                vcpu->arch.emulate_ctxt.exception = -1;
 
                 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
                 trace_kvm_emulate_insn_start(vcpu);
 
                 /* Only allow emulation of specific instructions on #UD
                  * (namely VMMCALL, sysenter, sysexit, syscall)*/
-                c = &vcpu->arch.emulate_ctxt.decode;
                 if (emulation_type & EMULTYPE_TRAP_UD) {
                         if (!c->twobyte)
                                 return EMULATE_FAIL;
@@ -3880,11 +4030,11 @@ int emulate_instruction(struct kvm_vcpu *vcpu,
 
                 ++vcpu->stat.insn_emulation;
                 if (r)  {
-                        ++vcpu->stat.insn_emulation_fail;
-                        trace_kvm_emulate_insn_failed(vcpu);
-                        if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
+                        if (reexecute_instruction(vcpu, cr2))
                                 return EMULATE_DONE;
-                        return EMULATE_FAIL;
+                        if (emulation_type & EMULTYPE_SKIP)
+                                return EMULATE_FAIL;
+                        return handle_emulation_failure(vcpu);
                 }
         }
 
@@ -3893,48 +4043,42 @@ int emulate_instruction(struct kvm_vcpu *vcpu,
                 return EMULATE_DONE;
         }
 
+        /* this is needed for vmware backdor interface to work since it
+           changes registers values  during IO operation */
+        memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
+
 restart:
         r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
-        shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
 
-        if (r == 0)
-                kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
+        if (r) { /* emulation failed */
+                if (reexecute_instruction(vcpu, cr2))
+                        return EMULATE_DONE;
 
-        if (vcpu->arch.pio.count) {
-                if (!vcpu->arch.pio.in)
-                        vcpu->arch.pio.count = 0;
-                return EMULATE_DO_MMIO;
+                return handle_emulation_failure(vcpu);
         }
 
-        if (r || vcpu->mmio_is_write) {
-                run->exit_reason = KVM_EXIT_MMIO;
-                run->mmio.phys_addr = vcpu->mmio_phys_addr;
-                memcpy(run->mmio.data, vcpu->mmio_data, 8);
-                run->mmio.len = vcpu->mmio_size;
-                run->mmio.is_write = vcpu->mmio_is_write;
+        toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
+        kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
+        memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
+        kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
+
+        if (vcpu->arch.emulate_ctxt.exception >= 0) {
+                inject_emulated_exception(vcpu);
+                return EMULATE_DONE;
         }
 
-        if (r) {
-                if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
-                        goto done;
-                if (!vcpu->mmio_needed) {
-                        ++vcpu->stat.insn_emulation_fail;
-                        trace_kvm_emulate_insn_failed(vcpu);
-                        kvm_report_emulation_failure(vcpu, "mmio");
-                        return EMULATE_FAIL;
-                }
+        if (vcpu->arch.pio.count) {
+                if (!vcpu->arch.pio.in)
+                        vcpu->arch.pio.count = 0;
                 return EMULATE_DO_MMIO;
         }
 
-        if (vcpu->mmio_is_write) {
-                vcpu->mmio_needed = 0;
+        if (vcpu->mmio_needed) {
+                if (vcpu->mmio_is_write)
+                        vcpu->mmio_needed = 0;
                 return EMULATE_DO_MMIO;
         }
 
-done:
-        if (vcpu->arch.exception.pending)
-                vcpu->arch.emulate_ctxt.restart = false;
-
         if (vcpu->arch.emulate_ctxt.restart)
                 goto restart;
 
@@ -4108,6 +4252,9 @@ int kvm_arch_init(void *opaque)
 
         perf_register_guest_info_callbacks(&kvm_guest_cbs);
 
+        if (cpu_has_xsave)
+                host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+
         return 0;
 
 out:
@@ -4270,7 +4417,7 @@ int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
 
         kvm_x86_ops->patch_hypercall(vcpu, instruction);
 
-        return emulator_write_emulated(rip, instruction, 3, vcpu);
+        return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
 }
 
 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
@@ -4506,59 +4653,78 @@ static void inject_pending_event(struct kvm_vcpu *vcpu)
         }
 }
 
+static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
+{
+        if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
+                        !vcpu->guest_xcr0_loaded) {
+                /* kvm_set_xcr() also depends on this */
+                xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
+                vcpu->guest_xcr0_loaded = 1;
+        }
+}
+
+static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
+{
+        if (vcpu->guest_xcr0_loaded) {
+                if (vcpu->arch.xcr0 != host_xcr0)
+                        xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
+                vcpu->guest_xcr0_loaded = 0;
+        }
+}
+
 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
 {
         int r;
         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
                 vcpu->run->request_interrupt_window;
 
-        if (vcpu->requests)
-                if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
-                        kvm_mmu_unload(vcpu);
-
-        r = kvm_mmu_reload(vcpu);
-        if (unlikely(r))
-                goto out;
-
         if (vcpu->requests) {
-                if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
+                if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
+                        kvm_mmu_unload(vcpu);
+                if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
                         __kvm_migrate_timers(vcpu);
-                if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
+                if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu))
                         kvm_write_guest_time(vcpu);
-                if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
+                if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
                         kvm_mmu_sync_roots(vcpu);
-                if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
+                if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
                         kvm_x86_ops->tlb_flush(vcpu);
-                if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
-                                       &vcpu->requests)) {
+                if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
                         r = 0;
                         goto out;
                 }
-                if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
+                if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
                         r = 0;
                         goto out;
                 }
-                if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
+                if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
                         vcpu->fpu_active = 0;
                         kvm_x86_ops->fpu_deactivate(vcpu);
                 }
         }
 
+        r = kvm_mmu_reload(vcpu);
+        if (unlikely(r))
+                goto out;
+
         preempt_disable();
 
         kvm_x86_ops->prepare_guest_switch(vcpu);
         if (vcpu->fpu_active)
                 kvm_load_guest_fpu(vcpu);
+        kvm_load_guest_xcr0(vcpu);
 
-        local_irq_disable();
+        atomic_set(&vcpu->guest_mode, 1);
+        smp_wmb();
 
-        clear_bit(KVM_REQ_KICK, &vcpu->requests);
-        smp_mb__after_clear_bit();
+        local_irq_disable();
 
-        if (vcpu->requests || need_resched() || signal_pending(current)) {
-                set_bit(KVM_REQ_KICK, &vcpu->requests);
+        if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
+            || need_resched() || signal_pending(current)) {
+                atomic_set(&vcpu->guest_mode, 0);
+                smp_wmb();
                 local_irq_enable();
                 preempt_enable();
                 r = 1;
@@ -4603,7 +4769,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
         if (hw_breakpoint_active())
                 hw_breakpoint_restore();
 
-        set_bit(KVM_REQ_KICK, &vcpu->requests);
+        atomic_set(&vcpu->guest_mode, 0);
+        smp_wmb();
         local_irq_enable();
 
         ++vcpu->stat.exits;
@@ -4665,7 +4832,7 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
                         kvm_vcpu_block(vcpu);
                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
-                        if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
+                        if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
                         {
                                 switch(vcpu->arch.mp_state) {
                                 case KVM_MP_STATE_HALTED:
@@ -4717,8 +4884,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
         int r;
         sigset_t sigsaved;
 
-        vcpu_load(vcpu);
-
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 
@@ -4743,7 +4908,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
                 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
-                if (r == EMULATE_DO_MMIO) {
+                if (r != EMULATE_DONE) {
                         r = 0;
                         goto out;
                 }
@@ -4759,14 +4924,11 @@ out:
         if (vcpu->sigset_active)
                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 
-        vcpu_put(vcpu);
         return r;
 }
 
 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
-        vcpu_load(vcpu);
-
         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
@@ -4789,15 +4951,11 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         regs->rip = kvm_rip_read(vcpu);
         regs->rflags = kvm_get_rflags(vcpu);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
-        vcpu_load(vcpu);
-
         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
@@ -4822,8 +4980,6 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 
         vcpu->arch.exception.pending = false;
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -4842,8 +4998,6 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
 {
         struct desc_ptr dt;
 
-        vcpu_load(vcpu);
-
         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
@@ -4875,32 +5029,27 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
                 set_bit(vcpu->arch.interrupt.nr,
                         (unsigned long *)sregs->interrupt_bitmap);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
                                     struct kvm_mp_state *mp_state)
 {
-        vcpu_load(vcpu);
         mp_state->mp_state = vcpu->arch.mp_state;
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
                                     struct kvm_mp_state *mp_state)
 {
-        vcpu_load(vcpu);
         vcpu->arch.mp_state = mp_state->mp_state;
-        vcpu_put(vcpu);
         return 0;
 }
 
 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
                     bool has_error_code, u32 error_code)
 {
+        struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
         int cs_db, cs_l, ret;
         cache_all_regs(vcpu);
 
@@ -4915,6 +5064,8 @@ int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
                 ? X86EMUL_MODE_VM86 : cs_l
                 ? X86EMUL_MODE_PROT64 : cs_db
                 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
+        memset(c, 0, sizeof(struct decode_cache));
+        memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
 
         ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
                                    tss_selector, reason, has_error_code,
@@ -4923,6 +5074,8 @@ int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
         if (ret)
                 return EMULATE_FAIL;
 
+        memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
+        kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
         kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
         return EMULATE_DONE;
 }
@@ -4935,8 +5088,6 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         int pending_vec, max_bits;
         struct desc_ptr dt;
 
-        vcpu_load(vcpu);
-
         dt.size = sregs->idt.limit;
         dt.address = sregs->idt.base;
         kvm_x86_ops->set_idt(vcpu, &dt);
@@ -4996,8 +5147,6 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
             !is_protmode(vcpu))
                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
@@ -5007,12 +5156,10 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
         unsigned long rflags;
         int i, r;
 
-        vcpu_load(vcpu);
-
         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
                 r = -EBUSY;
                 if (vcpu->arch.exception.pending)
-                        goto unlock_out;
+                        goto out;
                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
                         kvm_queue_exception(vcpu, DB_VECTOR);
                 else
@@ -5054,34 +5201,12 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 
         r = 0;
 
-unlock_out:
-        vcpu_put(vcpu);
+out:
 
         return r;
 }
 
 /*
- * fxsave fpu state.  Taken from x86_64/processor.h.  To be killed when
- * we have asm/x86/processor.h
- */
-struct fxsave {
-        u16     cwd;
-        u16     swd;
-        u16     twd;
-        u16     fop;
-        u64     rip;
-        u64     rdp;
-        u32     mxcsr;
-        u32     mxcsr_mask;
-        u32     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
-#ifdef CONFIG_X86_64
-        u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 256 bytes */
-#else
-        u32     xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
-#endif
-};
-
-/*
  * Translate a guest virtual address to a guest physical address.
  */
 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
@@ -5091,7 +5216,6 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
         gpa_t gpa;
         int idx;
 
-        vcpu_load(vcpu);
         idx = srcu_read_lock(&vcpu->kvm->srcu);
         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
         srcu_read_unlock(&vcpu->kvm->srcu, idx);
@@ -5099,16 +5223,14 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
         tr->valid = gpa != UNMAPPED_GVA;
         tr->writeable = 1;
         tr->usermode = 0;
-        vcpu_put(vcpu);
 
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
-        struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
-
-        vcpu_load(vcpu);
+        struct i387_fxsave_struct *fxsave =
+                        &vcpu->arch.guest_fpu.state->fxsave;
 
         memcpy(fpu->fpr, fxsave->st_space, 128);
         fpu->fcw = fxsave->cwd;
@@ -5119,16 +5241,13 @@ int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
         fpu->last_dp = fxsave->rdp;
         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
-        struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
-
-        vcpu_load(vcpu);
+        struct i387_fxsave_struct *fxsave =
+                        &vcpu->arch.guest_fpu.state->fxsave;
 
         memcpy(fxsave->st_space, fpu->fpr, 128);
         fxsave->cwd = fpu->fcw;
@@ -5139,61 +5258,63 @@ int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
         fxsave->rdp = fpu->last_dp;
         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
 
-        vcpu_put(vcpu);
-
         return 0;
 }
 
-void fx_init(struct kvm_vcpu *vcpu)
+int fx_init(struct kvm_vcpu *vcpu)
 {
-        unsigned after_mxcsr_mask;
+        int err;
+
+        err = fpu_alloc(&vcpu->arch.guest_fpu);
+        if (err)
+                return err;
+
+        fpu_finit(&vcpu->arch.guest_fpu);
 
         /*
-         * Touch the fpu the first time in non atomic context as if
-         * this is the first fpu instruction the exception handler
-         * will fire before the instruction returns and it'll have to
-         * allocate ram with GFP_KERNEL.
+         * Ensure guest xcr0 is valid for loading
          */
-        if (!used_math())
-                kvm_fx_save(&vcpu->arch.host_fx_image);
-
-        /* Initialize guest FPU by resetting ours and saving into guest's */
-        preempt_disable();
-        kvm_fx_save(&vcpu->arch.host_fx_image);
-        kvm_fx_finit();
-        kvm_fx_save(&vcpu->arch.guest_fx_image);
-        kvm_fx_restore(&vcpu->arch.host_fx_image);
-        preempt_enable();
+        vcpu->arch.xcr0 = XSTATE_FP;
 
         vcpu->arch.cr0 |= X86_CR0_ET;
-        after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
-        vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
-        memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
-               0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
+
+        return 0;
 }
 EXPORT_SYMBOL_GPL(fx_init);
 
+static void fx_free(struct kvm_vcpu *vcpu)
+{
+        fpu_free(&vcpu->arch.guest_fpu);
+}
+
 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
 {
         if (vcpu->guest_fpu_loaded)
                 return;
 
+        /*
+         * Restore all possible states in the guest,
+         * and assume host would use all available bits.
+         * Guest xcr0 would be loaded later.
+         */
+        kvm_put_guest_xcr0(vcpu);
         vcpu->guest_fpu_loaded = 1;
-        kvm_fx_save(&vcpu->arch.host_fx_image);
-        kvm_fx_restore(&vcpu->arch.guest_fx_image);
+        unlazy_fpu(current);
+        fpu_restore_checking(&vcpu->arch.guest_fpu);
         trace_kvm_fpu(1);
 }
 
 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
 {
+        kvm_put_guest_xcr0(vcpu);
+
         if (!vcpu->guest_fpu_loaded)
                 return;
 
         vcpu->guest_fpu_loaded = 0;
-        kvm_fx_save(&vcpu->arch.guest_fx_image);
-        kvm_fx_restore(&vcpu->arch.host_fx_image);
+        fpu_save_init(&vcpu->arch.guest_fpu);
         ++vcpu->stat.fpu_reload;
-        set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
+        kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
         trace_kvm_fpu(0);
 }
 
@@ -5204,6 +5325,8 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
                 vcpu->arch.time_page = NULL;
         }
 
+        free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
+        fx_free(vcpu);
         kvm_x86_ops->vcpu_free(vcpu);
 }
 
@@ -5217,9 +5340,6 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
 {
         int r;
 
-        /* We do fxsave: this must be aligned. */
-        BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
-
         vcpu->arch.mtrr_state.have_fixed = 1;
         vcpu_load(vcpu);
         r = kvm_arch_vcpu_reset(vcpu);
@@ -5241,6 +5361,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
         kvm_mmu_unload(vcpu);
         vcpu_put(vcpu);
 
+        fx_free(vcpu);
         kvm_x86_ops->vcpu_free(vcpu);
 }
 
@@ -5334,7 +5455,12 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         }
         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
 
+        if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
+                goto fail_free_mce_banks;
+
         return 0;
+fail_free_mce_banks:
+        kfree(vcpu->arch.mce_banks);
 fail_free_lapic:
         kvm_free_lapic(vcpu);
 fail_mmu_destroy:
@@ -5364,12 +5490,6 @@ struct  kvm *kvm_arch_create_vm(void)
         if (!kvm)
                 return ERR_PTR(-ENOMEM);
 
-        kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
-        if (!kvm->arch.aliases) {
-                kfree(kvm);
-                return ERR_PTR(-ENOMEM);
-        }
-
         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
 
@@ -5412,12 +5532,12 @@ static void kvm_free_vcpus(struct kvm *kvm)
 void kvm_arch_sync_events(struct kvm *kvm)
 {
         kvm_free_all_assigned_devices(kvm);
+        kvm_free_pit(kvm);
 }
 
 void kvm_arch_destroy_vm(struct kvm *kvm)
 {
         kvm_iommu_unmap_guest(kvm);
-        kvm_free_pit(kvm);
         kfree(kvm->arch.vpic);
         kfree(kvm->arch.vioapic);
         kvm_free_vcpus(kvm);
@@ -5427,7 +5547,6 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
         if (kvm->arch.ept_identity_pagetable)
                 put_page(kvm->arch.ept_identity_pagetable);
         cleanup_srcu_struct(&kvm->srcu);
-        kfree(kvm->arch.aliases);
         kfree(kvm);
 }
 
@@ -5438,6 +5557,11 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                 int user_alloc)
 {
         int npages = memslot->npages;
+        int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
+
+        /* Prevent internal slot pages from being moved by fork()/COW. */
+        if (memslot->id >= KVM_MEMORY_SLOTS)
+                map_flags = MAP_SHARED | MAP_ANONYMOUS;
 
         /*To keep backward compatibility with older userspace,
          *x86 needs to hanlde !user_alloc case.
@@ -5450,7 +5574,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
                         userspace_addr = do_mmap(NULL, 0,
                                                  npages * PAGE_SIZE,
                                                  PROT_READ | PROT_WRITE,
-                                                 MAP_PRIVATE | MAP_ANONYMOUS,
+                                                 map_flags,
                                                  0);
                         up_write(&current->mm->mmap_sem);
 
@@ -5523,7 +5647,7 @@ void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
 
         me = get_cpu();
         if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
-                if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
+                if (atomic_xchg(&vcpu->guest_mode, 0))
                         smp_send_reschedule(cpu);
         put_cpu();
 }
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index f4b54458285b..b7a404722d2b 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -65,13 +65,6 @@ static inline int is_paging(struct kvm_vcpu *vcpu)
         return kvm_read_cr0_bits(vcpu, X86_CR0_PG);
 }
 
-static inline struct kvm_mem_aliases *kvm_aliases(struct kvm *kvm)
-{
-        return rcu_dereference_check(kvm->arch.aliases,
-                        srcu_read_lock_held(&kvm->srcu)
-                        || lockdep_is_held(&kvm->slots_lock));
-}
-
 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu);
 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu);
 
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f871e04b6965..e10cf070ede0 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -30,6 +30,7 @@ ifeq ($(CONFIG_X86_32),y)
         lib-y += checksum_32.o
         lib-y += strstr_32.o
         lib-y += semaphore_32.o string_32.o
+        lib-y += cmpxchg.o
 ifneq ($(CONFIG_X86_CMPXCHG64),y)
         lib-y += cmpxchg8b_emu.o atomic64_386_32.o
 endif
diff --git a/arch/x86/kernel/cpu/cmpxchg.c b/arch/x86/lib/cmpxchg.c
index 2056ccf572cc..5d619f6df3ee 100644
--- a/arch/x86/kernel/cpu/cmpxchg.c
+++ b/arch/x86/lib/cmpxchg.c
@@ -52,21 +52,3 @@ unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
 }
 EXPORT_SYMBOL(cmpxchg_386_u32);
 #endif
-
-#ifndef CONFIG_X86_CMPXCHG64
-unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
-{
-        u64 prev;
-        unsigned long flags;
-
-        /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
-        local_irq_save(flags);
-        prev = *(u64 *)ptr;
-        if (prev == old)
-                *(u64 *)ptr = new;
-        local_irq_restore(flags);
-        return prev;
-}
-EXPORT_SYMBOL(cmpxchg_486_u64);
-#endif
-
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c
index a725b7f760ae..0002a3a33081 100644
--- a/arch/x86/mm/dump_pagetables.c
+++ b/arch/x86/mm/dump_pagetables.c
@@ -37,6 +37,28 @@ struct addr_marker {
         const char *name;
 };
 
+/* indices for address_markers; keep sync'd w/ address_markers below */
+enum address_markers_idx {
+        USER_SPACE_NR = 0,
+#ifdef CONFIG_X86_64
+        KERNEL_SPACE_NR,
+        LOW_KERNEL_NR,
+        VMALLOC_START_NR,
+        VMEMMAP_START_NR,
+        HIGH_KERNEL_NR,
+        MODULES_VADDR_NR,
+        MODULES_END_NR,
+#else
+        KERNEL_SPACE_NR,
+        VMALLOC_START_NR,
+        VMALLOC_END_NR,
+# ifdef CONFIG_HIGHMEM
+        PKMAP_BASE_NR,
+# endif
+        FIXADDR_START_NR,
+#endif
+};
+
 /* Address space markers hints */
 static struct addr_marker address_markers[] = {
         { 0, "User Space" },
@@ -331,14 +353,12 @@ static int pt_dump_init(void)
 
 #ifdef CONFIG_X86_32
         /* Not a compile-time constant on x86-32 */
-        address_markers[2].start_address = VMALLOC_START;
-        address_markers[3].start_address = VMALLOC_END;
+        address_markers[VMALLOC_START_NR].start_address = VMALLOC_START;
+        address_markers[VMALLOC_END_NR].start_address = VMALLOC_END;
 # ifdef CONFIG_HIGHMEM
-        address_markers[4].start_address = PKMAP_BASE;
-        address_markers[5].start_address = FIXADDR_START;
-# else
-        address_markers[4].start_address = FIXADDR_START;
+        address_markers[PKMAP_BASE_NR].start_address = PKMAP_BASE;
 # endif
+        address_markers[FIXADDR_START_NR].start_address = FIXADDR_START;
 #endif
 
         pe = debugfs_create_file("kernel_page_tables", 0600, NULL, NULL,
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index ee41bba315d1..9a6674689a20 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -2,7 +2,7 @@
  *  linux/arch/x86_64/mm/init.c
  *
  *  Copyright (C) 1995  Linus Torvalds
- *  Copyright (C) 2000  Pavel Machek <pavel@suse.cz>
+ *  Copyright (C) 2000  Pavel Machek <pavel@ucw.cz>
  *  Copyright (C) 2002,2003 Andi Kleen <ak@suse.de>
  */
 
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 12e4d2d3c110..3ba6e0608c55 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -62,8 +62,8 @@ int ioremap_change_attr(unsigned long vaddr, unsigned long size,
 static void __iomem *__ioremap_caller(resource_size_t phys_addr,
                 unsigned long size, unsigned long prot_val, void *caller)
 {
-        unsigned long pfn, offset, vaddr;
-        resource_size_t last_addr;
+        unsigned long offset, vaddr;
+        resource_size_t pfn, last_pfn, last_addr;
         const resource_size_t unaligned_phys_addr = phys_addr;
         const unsigned long unaligned_size = size;
         struct vm_struct *area;
@@ -100,10 +100,8 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
         /*
          * Don't allow anybody to remap normal RAM that we're using..
          */
-        for (pfn = phys_addr >> PAGE_SHIFT;
-                                (pfn << PAGE_SHIFT) < (last_addr & PAGE_MASK);
-                                pfn++) {
-
+        last_pfn = last_addr >> PAGE_SHIFT;
+        for (pfn = phys_addr >> PAGE_SHIFT; pfn <= last_pfn; pfn++) {
                 int is_ram = page_is_ram(pfn);
 
                 if (is_ram && pfn_valid(pfn) && !PageReserved(pfn_to_page(pfn)))
@@ -115,7 +113,7 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
          * Mappings have to be page-aligned
          */
         offset = phys_addr & ~PAGE_MASK;
-        phys_addr &= PAGE_MASK;
+        phys_addr &= PHYSICAL_PAGE_MASK;
         size = PAGE_ALIGN(last_addr+1) - phys_addr;
 
         retval = reserve_memtype(phys_addr, (u64)phys_addr + size,
@@ -613,7 +611,7 @@ void __init early_iounmap(void __iomem *addr, unsigned long size)
                 return;
         }
         offset = virt_addr & ~PAGE_MASK;
-        nrpages = PAGE_ALIGN(offset + size - 1) >> PAGE_SHIFT;
+        nrpages = PAGE_ALIGN(offset + size) >> PAGE_SHIFT;
 
         idx = FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*slot;
         while (nrpages > 0) {
diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c
index 5d0e67fff1a6..e5d5e2ce9f77 100644
--- a/arch/x86/mm/kmmio.c
+++ b/arch/x86/mm/kmmio.c
@@ -45,6 +45,8 @@ struct kmmio_fault_page {
          * Protected by kmmio_lock, when linked into kmmio_page_table.
          */
         int count;
+
+        bool scheduled_for_release;
 };
 
 struct kmmio_delayed_release {
@@ -398,8 +400,11 @@ static void release_kmmio_fault_page(unsigned long page,
         BUG_ON(f->count < 0);
         if (!f->count) {
                 disarm_kmmio_fault_page(f);
-                f->release_next = *release_list;
-                *release_list = f;
+                if (!f->scheduled_for_release) {
+                        f->release_next = *release_list;
+                        *release_list = f;
+                        f->scheduled_for_release = true;
+                }
         }
 }
 
@@ -471,8 +476,10 @@ static void remove_kmmio_fault_pages(struct rcu_head *head)
                         prevp = &f->release_next;
                 } else {
                         *prevp = f->release_next;
+                        f->release_next = NULL;
+                        f->scheduled_for_release = false;
                 }
-                f = f->release_next;
+                f = *prevp;
         }
         spin_unlock_irqrestore(&kmmio_lock, flags);
 
@@ -510,6 +517,9 @@ void unregister_kmmio_probe(struct kmmio_probe *p)
         kmmio_count--;
         spin_unlock_irqrestore(&kmmio_lock, flags);
 
+        if (!release_list)
+                return;
+
         drelease = kmalloc(sizeof(*drelease), GFP_ATOMIC);
         if (!drelease) {
                 pr_crit("leaking kmmio_fault_page objects.\n");
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 64121a18b8cb..f6ff57b7efa5 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -158,7 +158,7 @@ static unsigned long pat_x_mtrr_type(u64 start, u64 end, unsigned long req_type)
         return req_type;
 }
 
-static int pat_pagerange_is_ram(unsigned long start, unsigned long end)
+static int pat_pagerange_is_ram(resource_size_t start, resource_size_t end)
 {
         int ram_page = 0, not_rampage = 0;
         unsigned long page_nr;
diff --git a/arch/x86/mm/pf_in.c b/arch/x86/mm/pf_in.c
index 308e32570d84..38e6d174c497 100644
--- a/arch/x86/mm/pf_in.c
+++ b/arch/x86/mm/pf_in.c
@@ -40,16 +40,16 @@ static unsigned char prefix_codes[] = {
 static unsigned int reg_rop[] = {
         0x8A, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
 };
-static unsigned int reg_wop[] = { 0x88, 0x89 };
+static unsigned int reg_wop[] = { 0x88, 0x89, 0xAA, 0xAB };
 static unsigned int imm_wop[] = { 0xC6, 0xC7 };
 /* IA32 Manual 3, 3-432*/
-static unsigned int rw8[] = { 0x88, 0x8A, 0xC6 };
+static unsigned int rw8[] = { 0x88, 0x8A, 0xC6, 0xAA };
 static unsigned int rw32[] = {
-        0x89, 0x8B, 0xC7, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
+        0x89, 0x8B, 0xC7, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F, 0xAB
 };
-static unsigned int mw8[] = { 0x88, 0x8A, 0xC6, 0xB60F, 0xBE0F };
+static unsigned int mw8[] = { 0x88, 0x8A, 0xC6, 0xB60F, 0xBE0F, 0xAA };
 static unsigned int mw16[] = { 0xB70F, 0xBF0F };
-static unsigned int mw32[] = { 0x89, 0x8B, 0xC7 };
+static unsigned int mw32[] = { 0x89, 0x8B, 0xC7, 0xAB };
 static unsigned int mw64[] = {};
 #else /* not __i386__ */
 static unsigned char prefix_codes[] = {
@@ -63,20 +63,20 @@ static unsigned char prefix_codes[] = {
 static unsigned int reg_rop[] = {
         0x8A, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
 };
-static unsigned int reg_wop[] = { 0x88, 0x89 };
+static unsigned int reg_wop[] = { 0x88, 0x89, 0xAA, 0xAB };
 static unsigned int imm_wop[] = { 0xC6, 0xC7 };
-static unsigned int rw8[] = { 0xC6, 0x88, 0x8A };
+static unsigned int rw8[] = { 0xC6, 0x88, 0x8A, 0xAA };
 static unsigned int rw32[] = {
-        0xC7, 0x89, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
+        0xC7, 0x89, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F, 0xAB
 };
 /* 8 bit only */
-static unsigned int mw8[] = { 0xC6, 0x88, 0x8A, 0xB60F, 0xBE0F };
+static unsigned int mw8[] = { 0xC6, 0x88, 0x8A, 0xB60F, 0xBE0F, 0xAA };
 /* 16 bit only */
 static unsigned int mw16[] = { 0xB70F, 0xBF0F };
 /* 16 or 32 bit */
 static unsigned int mw32[] = { 0xC7 };
 /* 16, 32 or 64 bit */
-static unsigned int mw64[] = { 0x89, 0x8B };
+static unsigned int mw64[] = { 0x89, 0x8B, 0xAB };
 #endif /* not __i386__ */
 
 struct prefix_bits {
@@ -410,7 +410,6 @@ static unsigned long *get_reg_w32(int no, struct pt_regs *regs)
 unsigned long get_ins_reg_val(unsigned long ins_addr, struct pt_regs *regs)
 {
         unsigned int opcode;
-        unsigned char mod_rm;
         int reg;
         unsigned char *p;
         struct prefix_bits prf;
@@ -437,8 +436,13 @@ unsigned long get_ins_reg_val(unsigned long ins_addr, struct pt_regs *regs)
         goto err;
 
 do_work:
-        mod_rm = *p;
-        reg = ((mod_rm >> 3) & 0x7) | (prf.rexr << 3);
+        /* for STOS, source register is fixed */
+        if (opcode == 0xAA || opcode == 0xAB) {
+                reg = arg_AX;
+        } else {
+                unsigned char mod_rm = *p;
+                reg = ((mod_rm >> 3) & 0x7) | (prf.rexr << 3);
+        }
         switch (get_ins_reg_width(ins_addr)) {
         case 1:
                 return *get_reg_w8(reg, prf.rex, regs);
diff --git a/arch/x86/mm/testmmiotrace.c b/arch/x86/mm/testmmiotrace.c
index 8565d944f7cf..38868adf07ea 100644
--- a/arch/x86/mm/testmmiotrace.c
+++ b/arch/x86/mm/testmmiotrace.c
@@ -90,6 +90,27 @@ static void do_test(unsigned long size)
         iounmap(p);
 }
 
+/*
+ * Tests how mmiotrace behaves in face of multiple ioremap / iounmaps in
+ * a short time. We had a bug in deferred freeing procedure which tried
+ * to free this region multiple times (ioremap can reuse the same address
+ * for many mappings).
+ */
+static void do_test_bulk_ioremapping(void)
+{
+        void __iomem *p;
+        int i;
+
+        for (i = 0; i < 10; ++i) {
+                p = ioremap_nocache(mmio_address, PAGE_SIZE);
+                if (p)
+                        iounmap(p);
+        }
+
+        /* Force freeing. If it will crash we will know why. */
+        synchronize_rcu();
+}
+
 static int __init init(void)
 {
         unsigned long size = (read_far) ? (8 << 20) : (16 << 10);
@@ -104,6 +125,7 @@ static int __init init(void)
                    "and writing 16 kB of rubbish in there.\n",
                    size >> 10, mmio_address);
         do_test(size);
+        do_test_bulk_ioremapping();
         pr_info("All done.\n");
         return 0;
 }
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 426f3a1a64d3..c03f14ab6667 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -278,11 +278,9 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
 
 static void do_flush_tlb_all(void *info)
 {
-        unsigned long cpu = smp_processor_id();
-
         __flush_tlb_all();
         if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
-                leave_mm(cpu);
+                leave_mm(smp_processor_id());
 }
 
 void flush_tlb_all(void)
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index b28d2f1253bb..1ba67dc8006a 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -634,6 +634,18 @@ static int __init ppro_init(char **cpu_type)
         if (force_arch_perfmon && cpu_has_arch_perfmon)
                 return 0;
 
+        /*
+         * Documentation on identifying Intel processors by CPU family
+         * and model can be found in the Intel Software Developer's
+         * Manuals (SDM):
+         *
+         *  http://www.intel.com/products/processor/manuals/
+         *
+         * As of May 2010 the documentation for this was in the:
+         * "Intel 64 and IA-32 Architectures Software Developer's
+         * Manual Volume 3B: System Programming Guide", "Table B-1
+         * CPUID Signature Values of DisplayFamily_DisplayModel".
+         */
         switch (cpu_model) {
         case 0 ... 2:
                 *cpu_type = "i386/ppro";
@@ -655,12 +667,12 @@ static int __init ppro_init(char **cpu_type)
         case 15: case 23:
                 *cpu_type = "i386/core_2";
                 break;
+        case 0x1a:
         case 0x2e:
-        case 26:
                 spec = &op_arch_perfmon_spec;
                 *cpu_type = "i386/core_i7";
                 break;
-        case 28:
+        case 0x1c:
                 *cpu_type = "i386/atom";
                 break;
         default:
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 2ec04c424a62..15466c096ba5 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -34,6 +34,15 @@ static const struct dmi_system_id pci_use_crs_table[] __initconst = {
                         DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
                 },
         },
+        /* https://bugzilla.kernel.org/show_bug.cgi?id=16007 */
+        /* 2006 AMD HT/VIA system with two host bridges */
+        {
+                .callback = set_use_crs,
+                .ident = "ASRock ALiveSATA2-GLAN",
+                .matches = {
+                        DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
+                },
+        },
         {}
 };
 
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 215a27ae050d..a0772af64efb 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -125,6 +125,23 @@ void __init dmi_check_skip_isa_align(void)
 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 {
         struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
+        struct resource *bar_r;
+        int bar;
+
+        if (pci_probe & PCI_NOASSIGN_BARS) {
+                /*
+                * If the BIOS did not assign the BAR, zero out the
+                * resource so the kernel doesn't attmept to assign
+                * it later on in pci_assign_unassigned_resources
+                */
+                for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
+                        bar_r = &dev->resource[bar];
+                        if (bar_r->start == 0 && bar_r->end != 0) {
+                                bar_r->flags = 0;
+                                bar_r->end = 0;
+                        }
+                }
+        }
 
         if (pci_probe & PCI_NOASSIGN_ROMS) {
                 if (rom_r->parent)
@@ -509,6 +526,9 @@ char * __devinit  pcibios_setup(char *str)
         } else if (!strcmp(str, "norom")) {
                 pci_probe |= PCI_NOASSIGN_ROMS;
                 return NULL;
+        } else if (!strcmp(str, "nobar")) {
+                pci_probe |= PCI_NOASSIGN_BARS;
+                return NULL;
         } else if (!strcmp(str, "assign-busses")) {
                 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
                 return NULL;
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 9810a0f76c91..f547ee05f715 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -989,7 +989,7 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
         dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
 
         /* Update IRQ for all devices with the same pirq value */
-        while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
+        for_each_pci_dev(dev2) {
                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
                 if (!pin)
                         continue;
@@ -1028,7 +1028,7 @@ void __init pcibios_fixup_irqs(void)
         u8 pin;
 
         DBG(KERN_DEBUG "PCI: IRQ fixup\n");
-        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+        for_each_pci_dev(dev) {
                 /*
                  * If the BIOS has set an out of range IRQ number, just
                  * ignore it.  Also keep track of which IRQ's are
@@ -1052,7 +1052,7 @@ void __init pcibios_fixup_irqs(void)
                 return;
 
         dev = NULL;
-        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+        for_each_pci_dev(dev) {
                 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
                 if (!pin)
                         continue;
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index 8d460eaf524f..c89266be6048 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -36,7 +36,7 @@ int __init pci_legacy_init(void)
         return 0;
 }
 
-void pcibios_scan_specific_bus(int busn)
+void __devinit pcibios_scan_specific_bus(int busn)
 {
         int devfn;
         long node;
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 1290ba54b350..e7e8c5f54956 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -4,7 +4,7 @@
  * Distribute under GPLv2
  *
  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
- * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
+ * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
  */
 
diff --git a/arch/x86/power/hibernate_64.c b/arch/x86/power/hibernate_64.c
index d24f983ba1e5..460f314d13e5 100644
--- a/arch/x86/power/hibernate_64.c
+++ b/arch/x86/power/hibernate_64.c
@@ -4,7 +4,7 @@
  * Distribute under GPLv2
  *
  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
- * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
+ * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
  */
 
diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile
index 6b4ffedb93c9..4a2afa1bac51 100644
--- a/arch/x86/vdso/Makefile
+++ b/arch/x86/vdso/Makefile
@@ -120,7 +120,8 @@ $(obj)/vdso32-syms.lds: $(vdso32.so-y:%=$(obj)/vdso32-%-syms.lds) FORCE
 quiet_cmd_vdso = VDSO    $@
       cmd_vdso = $(CC) -nostdlib -o $@ \
                        $(VDSO_LDFLAGS) $(VDSO_LDFLAGS_$(filter %.lds,$(^F))) \
-                       -Wl,-T,$(filter %.lds,$^) $(filter %.o,$^)
+                       -Wl,-T,$(filter %.lds,$^) $(filter %.o,$^) && \
+                 sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@'
 
 VDSO_LDFLAGS = -fPIC -shared $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
 GCOV_PROFILE := n
diff --git a/arch/x86/vdso/checkundef.sh b/arch/x86/vdso/checkundef.sh
new file mode 100755
index 000000000000..7ee90a9b549d
--- /dev/null
+++ b/arch/x86/vdso/checkundef.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+nm="$1"
+file="$2"
+$nm "$file" | grep '^ *U' > /dev/null 2>&1
+if [ $? -eq 1 ]; then
+    exit 0
+else
+    echo "$file: undefined symbols found" >&2
+    exit 1
+fi
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index 02b442e92007..36df991985b2 100644
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -374,7 +374,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
 #ifdef CONFIG_X86_64
 
-__initcall(sysenter_setup);
+subsys_initcall(sysenter_setup);
 
 #ifdef CONFIG_SYSCTL
 /* Register vsyscall32 into the ABI table */
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index ac74869b8140..43456ee17692 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -74,7 +74,7 @@ static int __init init_vdso_vars(void)
         vdso_enabled = 0;
         return -ENOMEM;
 }
-__initcall(init_vdso_vars);
+subsys_initcall(init_vdso_vars);
 
 struct linux_binprm;
 
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index b83e119fbeb0..68128a1b401a 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -13,6 +13,11 @@ config XEN
           kernel to boot in a paravirtualized environment under the
           Xen hypervisor.
 
+config XEN_PVHVM
+        def_bool y
+        depends on XEN
+        depends on X86_LOCAL_APIC
+
 config XEN_MAX_DOMAIN_MEMORY
        int "Maximum allowed size of a domain in gigabytes"
        default 8 if X86_32
diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile
index 3bb4fc21f4f2..930954685980 100644
--- a/arch/x86/xen/Makefile
+++ b/arch/x86/xen/Makefile
@@ -12,7 +12,7 @@ CFLAGS_mmu.o			:= $(nostackp)
 
 obj-y           := enlighten.o setup.o multicalls.o mmu.o irq.o \
                         time.o xen-asm.o xen-asm_$(BITS).o \
-                        grant-table.o suspend.o
+                        grant-table.o suspend.o platform-pci-unplug.o
 
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 65d8d79b46a8..d4ff5e83621d 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -11,6 +11,7 @@
  * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  */
 
+#include <linux/cpu.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/smp.h>
@@ -35,8 +36,10 @@
 #include <xen/interface/version.h>
 #include <xen/interface/physdev.h>
 #include <xen/interface/vcpu.h>
+#include <xen/interface/memory.h>
 #include <xen/features.h>
 #include <xen/page.h>
+#include <xen/hvm.h>
 #include <xen/hvc-console.h>
 
 #include <asm/paravirt.h>
@@ -55,7 +58,9 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/reboot.h>
+#include <asm/setup.h>
 #include <asm/stackprotector.h>
+#include <asm/hypervisor.h>
 
 #include "xen-ops.h"
 #include "mmu.h"
@@ -76,6 +81,10 @@ struct shared_info xen_dummy_shared_info;
 
 void *xen_initial_gdt;
 
+RESERVE_BRK(shared_info_page_brk, PAGE_SIZE);
+__read_mostly int xen_have_vector_callback;
+EXPORT_SYMBOL_GPL(xen_have_vector_callback);
+
 /*
  * Point at some empty memory to start with. We map the real shared_info
  * page as soon as fixmap is up and running.
@@ -97,6 +106,14 @@ struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
  */
 static int have_vcpu_info_placement = 1;
 
+static void clamp_max_cpus(void)
+{
+#ifdef CONFIG_SMP
+        if (setup_max_cpus > MAX_VIRT_CPUS)
+                setup_max_cpus = MAX_VIRT_CPUS;
+#endif
+}
+
 static void xen_vcpu_setup(int cpu)
 {
         struct vcpu_register_vcpu_info info;
@@ -104,13 +121,17 @@ static void xen_vcpu_setup(int cpu)
         struct vcpu_info *vcpup;
 
         BUG_ON(HYPERVISOR_shared_info == &xen_dummy_shared_info);
-        per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
 
-        if (!have_vcpu_info_placement)
-                return;         /* already tested, not available */
+        if (cpu < MAX_VIRT_CPUS)
+                per_cpu(xen_vcpu,cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
 
-        vcpup = &per_cpu(xen_vcpu_info, cpu);
+        if (!have_vcpu_info_placement) {
+                if (cpu >= MAX_VIRT_CPUS)
+                        clamp_max_cpus();
+                return;
+        }
 
+        vcpup = &per_cpu(xen_vcpu_info, cpu);
         info.mfn = arbitrary_virt_to_mfn(vcpup);
         info.offset = offset_in_page(vcpup);
 
@@ -125,6 +146,7 @@ static void xen_vcpu_setup(int cpu)
         if (err) {
                 printk(KERN_DEBUG "register_vcpu_info failed: err=%d\n", err);
                 have_vcpu_info_placement = 0;
+                clamp_max_cpus();
         } else {
                 /* This cpu is using the registered vcpu info, even if
                    later ones fail to. */
@@ -731,7 +753,6 @@ static void set_xen_basic_apic_ops(void)
 
 #endif
 
-
 static void xen_clts(void)
 {
         struct multicall_space mcs;
@@ -926,10 +947,6 @@ static const struct pv_init_ops xen_init_ops __initdata = {
         .patch = xen_patch,
 };
 
-static const struct pv_time_ops xen_time_ops __initdata = {
-        .sched_clock = xen_sched_clock,
-};
-
 static const struct pv_cpu_ops xen_cpu_ops __initdata = {
         .cpuid = xen_cpuid,
 
@@ -1028,6 +1045,23 @@ static void xen_crash_shutdown(struct pt_regs *regs)
         xen_reboot(SHUTDOWN_crash);
 }
 
+static int
+xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+        xen_reboot(SHUTDOWN_crash);
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block xen_panic_block = {
+        .notifier_call= xen_panic_event,
+};
+
+int xen_panic_handler_init(void)
+{
+        atomic_notifier_chain_register(&panic_notifier_list, &xen_panic_block);
+        return 0;
+}
+
 static const struct machine_ops __initdata xen_machine_ops = {
         .restart = xen_restart,
         .halt = xen_machine_halt,
@@ -1067,7 +1101,6 @@ asmlinkage void __init xen_start_kernel(void)
         /* Install Xen paravirt ops */
         pv_info = xen_info;
         pv_init_ops = xen_init_ops;
-        pv_time_ops = xen_time_ops;
         pv_cpu_ops = xen_cpu_ops;
         pv_apic_ops = xen_apic_ops;
 
@@ -1075,13 +1108,7 @@ asmlinkage void __init xen_start_kernel(void)
         x86_init.oem.arch_setup = xen_arch_setup;
         x86_init.oem.banner = xen_banner;
 
-        x86_init.timers.timer_init = xen_time_init;
-        x86_init.timers.setup_percpu_clockev = x86_init_noop;
-        x86_cpuinit.setup_percpu_clockev = x86_init_noop;
-
-        x86_platform.calibrate_tsc = xen_tsc_khz;
-        x86_platform.get_wallclock = xen_get_wallclock;
-        x86_platform.set_wallclock = xen_set_wallclock;
+        xen_init_time_ops();
 
         /*
          * Set up some pagetable state before starting to set any ptes.
@@ -1206,3 +1233,139 @@ asmlinkage void __init xen_start_kernel(void)
         x86_64_start_reservations((char *)__pa_symbol(&boot_params));
 #endif
 }
+
+static uint32_t xen_cpuid_base(void)
+{
+        uint32_t base, eax, ebx, ecx, edx;
+        char signature[13];
+
+        for (base = 0x40000000; base < 0x40010000; base += 0x100) {
+                cpuid(base, &eax, &ebx, &ecx, &edx);
+                *(uint32_t *)(signature + 0) = ebx;
+                *(uint32_t *)(signature + 4) = ecx;
+                *(uint32_t *)(signature + 8) = edx;
+                signature[12] = 0;
+
+                if (!strcmp("XenVMMXenVMM", signature) && ((eax - base) >= 2))
+                        return base;
+        }
+
+        return 0;
+}
+
+static int init_hvm_pv_info(int *major, int *minor)
+{
+        uint32_t eax, ebx, ecx, edx, pages, msr, base;
+        u64 pfn;
+
+        base = xen_cpuid_base();
+        cpuid(base + 1, &eax, &ebx, &ecx, &edx);
+
+        *major = eax >> 16;
+        *minor = eax & 0xffff;
+        printk(KERN_INFO "Xen version %d.%d.\n", *major, *minor);
+
+        cpuid(base + 2, &pages, &msr, &ecx, &edx);
+
+        pfn = __pa(hypercall_page);
+        wrmsr_safe(msr, (u32)pfn, (u32)(pfn >> 32));
+
+        xen_setup_features();
+
+        pv_info = xen_info;
+        pv_info.kernel_rpl = 0;
+
+        xen_domain_type = XEN_HVM_DOMAIN;
+
+        return 0;
+}
+
+void xen_hvm_init_shared_info(void)
+{
+        int cpu;
+        struct xen_add_to_physmap xatp;
+        static struct shared_info *shared_info_page = 0;
+
+        if (!shared_info_page)
+                shared_info_page = (struct shared_info *)
+                        extend_brk(PAGE_SIZE, PAGE_SIZE);
+        xatp.domid = DOMID_SELF;
+        xatp.idx = 0;
+        xatp.space = XENMAPSPACE_shared_info;
+        xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
+        if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
+                BUG();
+
+        HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
+
+        /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
+         * page, we use it in the event channel upcall and in some pvclock
+         * related functions. We don't need the vcpu_info placement
+         * optimizations because we don't use any pv_mmu or pv_irq op on
+         * HVM.
+         * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is
+         * online but xen_hvm_init_shared_info is run at resume time too and
+         * in that case multiple vcpus might be online. */
+        for_each_online_cpu(cpu) {
+                per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
+        }
+}
+
+#ifdef CONFIG_XEN_PVHVM
+static int __cpuinit xen_hvm_cpu_notify(struct notifier_block *self,
+                                    unsigned long action, void *hcpu)
+{
+        int cpu = (long)hcpu;
+        switch (action) {
+        case CPU_UP_PREPARE:
+                per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
+                break;
+        default:
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata xen_hvm_cpu_notifier = {
+        .notifier_call  = xen_hvm_cpu_notify,
+};
+
+static void __init xen_hvm_guest_init(void)
+{
+        int r;
+        int major, minor;
+
+        r = init_hvm_pv_info(&major, &minor);
+        if (r < 0)
+                return;
+
+        xen_hvm_init_shared_info();
+
+        if (xen_feature(XENFEAT_hvm_callback_vector))
+                xen_have_vector_callback = 1;
+        register_cpu_notifier(&xen_hvm_cpu_notifier);
+        xen_unplug_emulated_devices();
+        have_vcpu_info_placement = 0;
+        x86_init.irqs.intr_init = xen_init_IRQ;
+        xen_hvm_init_time_ops();
+        xen_hvm_init_mmu_ops();
+}
+
+static bool __init xen_hvm_platform(void)
+{
+        if (xen_pv_domain())
+                return false;
+
+        if (!xen_cpuid_base())
+                return false;
+
+        return true;
+}
+
+const __refconst struct hypervisor_x86 x86_hyper_xen_hvm = {
+        .name                   = "Xen HVM",
+        .detect                 = xen_hvm_platform,
+        .init_platform          = xen_hvm_guest_init,
+};
+EXPORT_SYMBOL(x86_hyper_xen_hvm);
+#endif
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 914f04695ce5..413b19b3d0fe 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -58,6 +58,7 @@
 
 #include <xen/page.h>
 #include <xen/interface/xen.h>
+#include <xen/interface/hvm/hvm_op.h>
 #include <xen/interface/version.h>
 #include <xen/hvc-console.h>
 
@@ -1941,6 +1942,40 @@ void __init xen_init_mmu_ops(void)
         pv_mmu_ops = xen_mmu_ops;
 }
 
+#ifdef CONFIG_XEN_PVHVM
+static void xen_hvm_exit_mmap(struct mm_struct *mm)
+{
+        struct xen_hvm_pagetable_dying a;
+        int rc;
+
+        a.domid = DOMID_SELF;
+        a.gpa = __pa(mm->pgd);
+        rc = HYPERVISOR_hvm_op(HVMOP_pagetable_dying, &a);
+        WARN_ON_ONCE(rc < 0);
+}
+
+static int is_pagetable_dying_supported(void)
+{
+        struct xen_hvm_pagetable_dying a;
+        int rc = 0;
+
+        a.domid = DOMID_SELF;
+        a.gpa = 0x00;
+        rc = HYPERVISOR_hvm_op(HVMOP_pagetable_dying, &a);
+        if (rc < 0) {
+                printk(KERN_DEBUG "HVMOP_pagetable_dying not supported\n");
+                return 0;
+        }
+        return 1;
+}
+
+void __init xen_hvm_init_mmu_ops(void)
+{
+        if (is_pagetable_dying_supported())
+                pv_mmu_ops.exit_mmap = xen_hvm_exit_mmap;
+}
+#endif
+
 #ifdef CONFIG_XEN_DEBUG_FS
 
 static struct dentry *d_mmu_debug;
diff --git a/arch/x86/xen/mmu.h b/arch/x86/xen/mmu.h
index 5fe6bc7f5ecf..fa938c4aa2f7 100644
--- a/arch/x86/xen/mmu.h
+++ b/arch/x86/xen/mmu.h
@@ -60,4 +60,5 @@ void  xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
 unsigned long xen_read_cr2_direct(void);
 
 extern void xen_init_mmu_ops(void);
+extern void xen_hvm_init_mmu_ops(void);
 #endif  /* _XEN_MMU_H */
diff --git a/arch/x86/xen/platform-pci-unplug.c b/arch/x86/xen/platform-pci-unplug.c
new file mode 100644
index 000000000000..554c002a1e1a
--- /dev/null
+++ b/arch/x86/xen/platform-pci-unplug.c
@@ -0,0 +1,137 @@
+/******************************************************************************
+ * platform-pci-unplug.c
+ *
+ * Xen platform PCI device driver
+ * Copyright (c) 2010, Citrix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <xen/platform_pci.h>
+
+#define XEN_PLATFORM_ERR_MAGIC -1
+#define XEN_PLATFORM_ERR_PROTOCOL -2
+#define XEN_PLATFORM_ERR_BLACKLIST -3
+
+/* store the value of xen_emul_unplug after the unplug is done */
+int xen_platform_pci_unplug;
+EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
+#ifdef CONFIG_XEN_PVHVM
+static int xen_emul_unplug;
+
+static int __init check_platform_magic(void)
+{
+        short magic;
+        char protocol;
+
+        magic = inw(XEN_IOPORT_MAGIC);
+        if (magic != XEN_IOPORT_MAGIC_VAL) {
+                printk(KERN_ERR "Xen Platform PCI: unrecognised magic value\n");
+                return XEN_PLATFORM_ERR_MAGIC;
+        }
+
+        protocol = inb(XEN_IOPORT_PROTOVER);
+
+        printk(KERN_DEBUG "Xen Platform PCI: I/O protocol version %d\n",
+                        protocol);
+
+        switch (protocol) {
+        case 1:
+                outw(XEN_IOPORT_LINUX_PRODNUM, XEN_IOPORT_PRODNUM);
+                outl(XEN_IOPORT_LINUX_DRVVER, XEN_IOPORT_DRVVER);
+                if (inw(XEN_IOPORT_MAGIC) != XEN_IOPORT_MAGIC_VAL) {
+                        printk(KERN_ERR "Xen Platform: blacklisted by host\n");
+                        return XEN_PLATFORM_ERR_BLACKLIST;
+                }
+                break;
+        default:
+                printk(KERN_WARNING "Xen Platform PCI: unknown I/O protocol version");
+                return XEN_PLATFORM_ERR_PROTOCOL;
+        }
+
+        return 0;
+}
+
+void __init xen_unplug_emulated_devices(void)
+{
+        int r;
+
+        /* check the version of the xen platform PCI device */
+        r = check_platform_magic();
+        /* If the version matches enable the Xen platform PCI driver.
+         * Also enable the Xen platform PCI driver if the version is really old
+         * and the user told us to ignore it. */
+        if (r && !(r == XEN_PLATFORM_ERR_MAGIC &&
+                        (xen_emul_unplug & XEN_UNPLUG_IGNORE)))
+                return;
+        /* Set the default value of xen_emul_unplug depending on whether or
+         * not the Xen PV frontends and the Xen platform PCI driver have
+         * been compiled for this kernel (modules or built-in are both OK). */
+        if (!xen_emul_unplug) {
+                if (xen_must_unplug_nics()) {
+                        printk(KERN_INFO "Netfront and the Xen platform PCI driver have "
+                                        "been compiled for this kernel: unplug emulated NICs.\n");
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_NICS;
+                }
+                if (xen_must_unplug_disks()) {
+                        printk(KERN_INFO "Blkfront and the Xen platform PCI driver have "
+                                        "been compiled for this kernel: unplug emulated disks.\n"
+                                        "You might have to change the root device\n"
+                                        "from /dev/hd[a-d] to /dev/xvd[a-d]\n"
+                                        "in your root= kernel command line option\n");
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_IDE_DISKS;
+                }
+        }
+        /* Now unplug the emulated devices */
+        if (!(xen_emul_unplug & XEN_UNPLUG_IGNORE))
+                outw(xen_emul_unplug, XEN_IOPORT_UNPLUG);
+        xen_platform_pci_unplug = xen_emul_unplug;
+}
+
+static int __init parse_xen_emul_unplug(char *arg)
+{
+        char *p, *q;
+        int l;
+
+        for (p = arg; p; p = q) {
+                q = strchr(p, ',');
+                if (q) {
+                        l = q - p;
+                        q++;
+                } else {
+                        l = strlen(p);
+                }
+                if (!strncmp(p, "all", l))
+                        xen_emul_unplug |= XEN_UNPLUG_ALL;
+                else if (!strncmp(p, "ide-disks", l))
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_IDE_DISKS;
+                else if (!strncmp(p, "aux-ide-disks", l))
+                        xen_emul_unplug |= XEN_UNPLUG_AUX_IDE_DISKS;
+                else if (!strncmp(p, "nics", l))
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_NICS;
+                else if (!strncmp(p, "ignore", l))
+                        xen_emul_unplug |= XEN_UNPLUG_IGNORE;
+                else
+                        printk(KERN_WARNING "unrecognised option '%s' "
+                                 "in parameter 'xen_emul_unplug'\n", p);
+        }
+        return 0;
+}
+early_param("xen_emul_unplug", parse_xen_emul_unplug);
+#endif
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index ad0047f47cd4..328b00305426 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -20,6 +20,7 @@
 #include <xen/page.h>
 #include <xen/interface/callback.h>
 #include <xen/interface/physdev.h>
+#include <xen/interface/memory.h>
 #include <xen/features.h>
 
 #include "xen-ops.h"
@@ -32,6 +33,73 @@ extern void xen_sysenter_target(void);
 extern void xen_syscall_target(void);
 extern void xen_syscall32_target(void);
 
+static unsigned long __init xen_release_chunk(phys_addr_t start_addr,
+                                              phys_addr_t end_addr)
+{
+        struct xen_memory_reservation reservation = {
+                .address_bits = 0,
+                .extent_order = 0,
+                .domid        = DOMID_SELF
+        };
+        unsigned long start, end;
+        unsigned long len = 0;
+        unsigned long pfn;
+        int ret;
+
+        start = PFN_UP(start_addr);
+        end = PFN_DOWN(end_addr);
+
+        if (end <= start)
+                return 0;
+
+        printk(KERN_INFO "xen_release_chunk: looking at area pfn %lx-%lx: ",
+               start, end);
+        for(pfn = start; pfn < end; pfn++) {
+                unsigned long mfn = pfn_to_mfn(pfn);
+
+                /* Make sure pfn exists to start with */
+                if (mfn == INVALID_P2M_ENTRY || mfn_to_pfn(mfn) != pfn)
+                        continue;
+
+                set_xen_guest_handle(reservation.extent_start, &mfn);
+                reservation.nr_extents = 1;
+
+                ret = HYPERVISOR_memory_op(XENMEM_decrease_reservation,
+                                           &reservation);
+                WARN(ret != 1, "Failed to release memory %lx-%lx err=%d\n",
+                     start, end, ret);
+                if (ret == 1) {
+                        set_phys_to_machine(pfn, INVALID_P2M_ENTRY);
+                        len++;
+                }
+        }
+        printk(KERN_CONT "%ld pages freed\n", len);
+
+        return len;
+}
+
+static unsigned long __init xen_return_unused_memory(unsigned long max_pfn,
+                                                     const struct e820map *e820)
+{
+        phys_addr_t max_addr = PFN_PHYS(max_pfn);
+        phys_addr_t last_end = 0;
+        unsigned long released = 0;
+        int i;
+
+        for (i = 0; i < e820->nr_map && last_end < max_addr; i++) {
+                phys_addr_t end = e820->map[i].addr;
+                end = min(max_addr, end);
+
+                released += xen_release_chunk(last_end, end);
+                last_end = e820->map[i].addr + e820->map[i].size;
+        }
+
+        if (last_end < max_addr)
+                released += xen_release_chunk(last_end, max_addr);
+
+        printk(KERN_INFO "released %ld pages of unused memory\n", released);
+        return released;
+}
 
 /**
  * machine_specific_memory_setup - Hook for machine specific memory setup.
@@ -67,6 +135,8 @@ char * __init xen_memory_setup(void)
 
         sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
 
+        xen_return_unused_memory(xen_start_info->nr_pages, &e820);
+
         return "Xen";
 }
 
@@ -156,6 +226,8 @@ void __init xen_arch_setup(void)
         struct physdev_set_iopl set_iopl;
         int rc;
 
+        xen_panic_handler_init();
+
         HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_4gb_segments);
         HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_writable_pagetables);
 
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index a29693fd3138..25f232b18a82 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -394,6 +394,8 @@ static void stop_self(void *v)
         load_cr3(swapper_pg_dir);
         /* should set up a minimal gdt */
 
+        set_cpu_online(cpu, false);
+
         HYPERVISOR_vcpu_op(VCPUOP_down, cpu, NULL);
         BUG();
 }
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
index a9c661108034..1d789d56877c 100644
--- a/arch/x86/xen/suspend.c
+++ b/arch/x86/xen/suspend.c
@@ -26,6 +26,18 @@ void xen_pre_suspend(void)
                 BUG();
 }
 
+void xen_hvm_post_suspend(int suspend_cancelled)
+{
+        int cpu;
+        xen_hvm_init_shared_info();
+        xen_callback_vector();
+        if (xen_feature(XENFEAT_hvm_safe_pvclock)) {
+                for_each_online_cpu(cpu) {
+                        xen_setup_runstate_info(cpu);
+                }
+        }
+}
+
 void xen_post_suspend(int suspend_cancelled)
 {
         xen_build_mfn_list_list();
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index b3c6c59ed302..1a5353a753fc 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -20,6 +20,7 @@
 #include <asm/xen/hypercall.h>
 
 #include <xen/events.h>
+#include <xen/features.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/vcpu.h>
 
@@ -155,47 +156,8 @@ static void do_stolen_accounting(void)
         account_idle_ticks(ticks);
 }
 
-/*
- * Xen sched_clock implementation.  Returns the number of unstolen
- * nanoseconds, which is nanoseconds the VCPU spent in RUNNING+BLOCKED
- * states.
- */
-unsigned long long xen_sched_clock(void)
-{
-        struct vcpu_runstate_info state;
-        cycle_t now;
-        u64 ret;
-        s64 offset;
-
-        /*
-         * Ideally sched_clock should be called on a per-cpu basis
-         * anyway, so preempt should already be disabled, but that's
-         * not current practice at the moment.
-         */
-        preempt_disable();
-
-        now = xen_clocksource_read();
-
-        get_runstate_snapshot(&state);
-
-        WARN_ON(state.state != RUNSTATE_running);
-
-        offset = now - state.state_entry_time;
-        if (offset < 0)
-                offset = 0;
-
-        ret = state.time[RUNSTATE_blocked] +
-                state.time[RUNSTATE_running] +
-                offset;
-
-        preempt_enable();
-
-        return ret;
-}
-
-
 /* Get the TSC speed from Xen */
-unsigned long xen_tsc_khz(void)
+static unsigned long xen_tsc_khz(void)
 {
         struct pvclock_vcpu_time_info *info =
                 &HYPERVISOR_shared_info->vcpu_info[0].time;
@@ -230,7 +192,7 @@ static void xen_read_wallclock(struct timespec *ts)
         put_cpu_var(xen_vcpu);
 }
 
-unsigned long xen_get_wallclock(void)
+static unsigned long xen_get_wallclock(void)
 {
         struct timespec ts;
 
@@ -238,7 +200,7 @@ unsigned long xen_get_wallclock(void)
         return ts.tv_sec;
 }
 
-int xen_set_wallclock(unsigned long now)
+static int xen_set_wallclock(unsigned long now)
 {
         /* do nothing for domU */
         return -1;
@@ -473,7 +435,11 @@ void xen_timer_resume(void)
         }
 }
 
-__init void xen_time_init(void)
+static const struct pv_time_ops xen_time_ops __initdata = {
+        .sched_clock = xen_clocksource_read,
+};
+
+static __init void xen_time_init(void)
 {
         int cpu = smp_processor_id();
         struct timespec tp;
@@ -497,3 +463,47 @@ __init void xen_time_init(void)
         xen_setup_timer(cpu);
         xen_setup_cpu_clockevents();
 }
+
+__init void xen_init_time_ops(void)
+{
+        pv_time_ops = xen_time_ops;
+
+        x86_init.timers.timer_init = xen_time_init;
+        x86_init.timers.setup_percpu_clockev = x86_init_noop;
+        x86_cpuinit.setup_percpu_clockev = x86_init_noop;
+
+        x86_platform.calibrate_tsc = xen_tsc_khz;
+        x86_platform.get_wallclock = xen_get_wallclock;
+        x86_platform.set_wallclock = xen_set_wallclock;
+}
+
+#ifdef CONFIG_XEN_PVHVM
+static void xen_hvm_setup_cpu_clockevents(void)
+{
+        int cpu = smp_processor_id();
+        xen_setup_runstate_info(cpu);
+        xen_setup_timer(cpu);
+        xen_setup_cpu_clockevents();
+}
+
+__init void xen_hvm_init_time_ops(void)
+{
+        /* vector callback is needed otherwise we cannot receive interrupts
+         * on cpu > 0 */
+        if (!xen_have_vector_callback && num_present_cpus() > 1)
+                return;
+        if (!xen_feature(XENFEAT_hvm_safe_pvclock)) {
+                printk(KERN_INFO "Xen doesn't support pvclock on HVM,"
+                                "disable pv timer\n");
+                return;
+        }
+
+        pv_time_ops = xen_time_ops;
+        x86_init.timers.setup_percpu_clockev = xen_time_init;
+        x86_cpuinit.setup_percpu_clockev = xen_hvm_setup_cpu_clockevents;
+
+        x86_platform.calibrate_tsc = xen_tsc_khz;
+        x86_platform.get_wallclock = xen_get_wallclock;
+        x86_platform.set_wallclock = xen_set_wallclock;
+}
+#endif
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index f9153a300bce..7c8ab86163e9 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -38,6 +38,10 @@ void xen_enable_sysenter(void);
 void xen_enable_syscall(void);
 void xen_vcpu_restore(void);
 
+void xen_callback_vector(void);
+void xen_hvm_init_shared_info(void);
+void __init xen_unplug_emulated_devices(void);
+
 void __init xen_build_dynamic_phys_to_machine(void);
 
 void xen_init_irq_ops(void);
@@ -46,11 +50,8 @@ void xen_setup_runstate_info(int cpu);
 void xen_teardown_timer(int cpu);
 cycle_t xen_clocksource_read(void);
 void xen_setup_cpu_clockevents(void);
-unsigned long xen_tsc_khz(void);
-void __init xen_time_init(void);
-unsigned long xen_get_wallclock(void);
-int xen_set_wallclock(unsigned long time);
-unsigned long long xen_sched_clock(void);
+void __init xen_init_time_ops(void);
+void __init xen_hvm_init_time_ops(void);
 
 irqreturn_t xen_debug_interrupt(int irq, void *dev_id);
 
@@ -101,4 +102,6 @@ void xen_sysret32(void);
 void xen_sysret64(void);
 void xen_adjust_exception_frame(void);
 
+extern int xen_panic_handler_init(void);
+
 #endif /* XEN_OPS_H */
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index ebe228d02b08..0859bfd8ae93 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -48,9 +48,6 @@ config HZ
         int
         default 100
 
-config GENERIC_TIME
-        def_bool y
-
 source "init/Kconfig"
 source "kernel/Kconfig.freezer"
 
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 4caffac3ca2e..7608559de93a 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -35,6 +35,8 @@ KBUILD_CFLAGS += -ffreestanding
 
 KBUILD_CFLAGS += -pipe -mlongcalls
 
+KBUILD_CFLAGS += $(call cc-option,-mforce-no-pic,)
+
 vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y))
 plfdirs := $(patsubst %,arch/xtensa/platforms/%/,$(platform-y))
 
diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig
index f19854035e61..7368164843b9 100644
--- a/arch/xtensa/configs/iss_defconfig
+++ b/arch/xtensa/configs/iss_defconfig
@@ -1,193 +1,214 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc2
-# Fri Feb 25 19:21:24 2005
+# Linux kernel version: 2.6.34-rc6
+# Tue Aug  3 00:10:54 2010
 #
-CONFIG_FRAME_POINTER=y
+# CONFIG_FRAME_POINTER is not set
+CONFIG_ZONE_DMA=y
 CONFIG_XTENSA=y
-# CONFIG_UID16 is not set
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_HAVE_DEC_LOCK=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_NO_IOPORT=y
+CONFIG_HZ=100
+CONFIG_GENERIC_TIME=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
+CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_HOTPLUG is not set
-# CONFIG_KOBJECT_UEVENT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-# CONFIG_TINY_SHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 # CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+CONFIG_MMU=y
+# CONFIG_VARIANT_IRQ_SWITCH is not set
 
 #
 # Processor type and features
 #
 CONFIG_XTENSA_VARIANT_FSF=y
-CONFIG_MMU=y
+# CONFIG_XTENSA_VARIANT_DC232B is not set
+# CONFIG_XTENSA_VARIANT_S6000 is not set
 # CONFIG_XTENSA_UNALIGNED_USER is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_MATH_EMULATION is not set
-# CONFIG_HIGHMEM is not set
-
-#
-# Platform options
-#
-CONFIG_XTENSA_PLATFORM_ISS=y
-# CONFIG_XTENSA_PLATFORM_XT2000 is not set
-# CONFIG_XTENSA_PLATFORM_ARUBA is not set
-# CONFIG_XTENSA_CALIBRATE_CCOUNT is not set
-CONFIG_XTENSA_CPU_CLOCK=10
-# CONFIG_GENERIC_CALIBRATE_DELAY is not set
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS0,38400 eth0=tuntap,,tap0 ip=192.168.168.5:192.168.168.1 root=nfs nfsroot=192.168.168.1:/opt/montavista/pro/devkit/xtensa/linux_be/target"
+CONFIG_XTENSA_CALIBRATE_CCOUNT=y
 CONFIG_SERIAL_CONSOLE=y
 CONFIG_XTENSA_ISS_NETWORK=y
 
 #
 # Bus options
 #
+# CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# PC-card bridges
-#
-
-#
-# PCI Hotplug Support
-#
-
+# Platform options
 #
-# Exectuable file formats
+CONFIG_XTENSA_PLATFORM_ISS=y
+# CONFIG_XTENSA_PLATFORM_XT2000 is not set
+# CONFIG_XTENSA_PLATFORM_S6105 is not set
+# CONFIG_GENERIC_CALIBRATE_DELAY is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,38400 eth0=tuntap,,tap0 ip=192.168.168.5:192.168.168.1 root=nfs nfsroot=192.168.168.1:/opt/montavista/pro/devkit/xtensa/linux_be/target"
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+
+#
+# Executable file formats
 #
 CONFIG_KCORE_ELF=y
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
 CONFIG_NET=y
 
 #
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -199,21 +220,28 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-# CONFIG_IP_TCPDIAG is not set
-# CONFIG_IP_TCPDIAG_IPV6 is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
+# CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
-# CONFIG_SCTP_HMAC_NONE is not set
-# CONFIG_SCTP_HMAC_SHA1 is not set
-# CONFIG_SCTP_HMAC_MD5 is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -221,77 +249,126 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-# CONFIG_NET_SCH_CLK_JIFFIES is not set
-# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
-# CONFIG_NET_SCH_CLK_CPU is not set
-# CONFIG_NET_CLS_ROUTE is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-# CONFIG_NETDEVICES is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
 
 #
-# ISDN subsystem
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_ISDN is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
 
 #
-# Telephony Support
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
 #
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
 #
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-
-#
 # Input Device Drivers
 #
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -302,117 +379,159 @@ CONFIG_HW_CONSOLE=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_RTC is not set
 # CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
+# CONFIG_SPI is not set
 
 #
-# Dallas's 1-wire bus
+# PPS support
 #
+# CONFIG_PPS is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
+CONFIG_SOFT_WATCHDOG=y
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Console display driver support
+# Display device support
 #
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# Sound
+# Console display driver support
 #
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
 
 #
-# USB support
+# Special HID drivers
 #
+CONFIG_USB_SUPPORT=y
 # CONFIG_USB_ARCH_HAS_HCD is not set
 # CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+# Enable Host or Gadget support to see Inventra options
 #
 
 #
-# USB Gadget Support
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 # CONFIG_USB_GADGET is not set
 
 #
-# MMC/SD Card support
+# OTG and related infrastructure
 #
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# InfiniBand support
+# TI VLYNQ
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -432,19 +551,14 @@ CONFIG_DUMMY_CONSOLE=y
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-CONFIG_DEVFS_MOUNT=y
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -452,29 +566,22 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V4 is not set
-CONFIG_NFS_DIRECTIO=y
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-# CONFIG_EXPORTFS is not set
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
@@ -485,43 +592,175 @@ CONFIG_SUNRPC=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_STACKOVERFLOW is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_KGDB is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
 
 #
-# Hardware crypto devices
+# Random Number Generation
 #
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
+CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 # CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index a508f2f73bd7..376cd9d5f455 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -115,6 +115,7 @@ extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned lon
 #define flush_cache_vmap(start,end)                     do { } while (0)
 #define flush_cache_vunmap(start,end)                   do { } while (0)
 
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
 #define flush_dcache_page(page)                         do { } while (0)
 
 #define flush_cache_page(vma,addr,pfn)                  do { } while (0)
diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/asm/coprocessor.h
index 65a285d8d3fb..75c94a1658b0 100644
--- a/arch/xtensa/include/asm/coprocessor.h
+++ b/arch/xtensa/include/asm/coprocessor.h
@@ -13,6 +13,7 @@
 #define _XTENSA_COPROCESSOR_H
 
 #include <linux/stringify.h>
+#include <variant/core.h>
 #include <variant/tie.h>
 #include <asm/types.h>
 
diff --git a/arch/xtensa/include/asm/elf.h b/arch/xtensa/include/asm/elf.h
index 5eb6d695e987..6e65eadaae14 100644
--- a/arch/xtensa/include/asm/elf.h
+++ b/arch/xtensa/include/asm/elf.h
@@ -14,6 +14,7 @@
 #define _XTENSA_ELF_H
 
 #include <asm/ptrace.h>
+#include <asm/coprocessor.h>
 
 /* Xtensa processor ELF architecture-magic number */
 
diff --git a/arch/xtensa/include/asm/local64.h b/arch/xtensa/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/xtensa/include/asm/local64.h
@@ -0,0 +1 @@
+#include <asm-generic/local64.h>
diff --git a/arch/xtensa/include/asm/pgalloc.h b/arch/xtensa/include/asm/pgalloc.h
index 4f4a7987eded..40cf9bceda2c 100644
--- a/arch/xtensa/include/asm/pgalloc.h
+++ b/arch/xtensa/include/asm/pgalloc.h
@@ -14,6 +14,7 @@
 #ifdef __KERNEL__
 
 #include <linux/highmem.h>
+#include <linux/slab.h>
 
 /*
  * Allocating and freeing a pmd is trivial: the 1-entry pmd is
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 0ea4937c0b61..3acb26e8dead 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -12,7 +12,6 @@
 #define _XTENSA_PROCESSOR_H
 
 #include <variant/core.h>
-#include <asm/coprocessor.h>
 #include <platform/hardware.h>
 
 #include <linux/compiler.h>
diff --git a/arch/xtensa/include/asm/ptrace.h b/arch/xtensa/include/asm/ptrace.h
index 3c549f798727..0d42c934b66f 100644
--- a/arch/xtensa/include/asm/ptrace.h
+++ b/arch/xtensa/include/asm/ptrace.h
@@ -77,6 +77,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/coprocessor.h>
+
 /*
  * This struct defines the way the registers are stored on the
  * kernel stack during a system call or other kernel entry.
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index 6f56d95f2c1e..2d2728b3e862 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -23,8 +23,8 @@ obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
 #
 # Replicate rules in scripts/Makefile.build
 
-sed-y = -e 's/(\(\.[a-z]*it\|\.ref\|\)\.text)/(\1.literal \1.text)/g'   \
-        -e 's/(\(\.text\.[a-z]*\))/(\1.literal \1)/g'
+sed-y = -e 's/\*(\(\.[a-z]*it\|\.ref\|\)\.text)/*(\1.literal \1.text)/g'    \
+        -e 's/\*(\(\.text\.[a-z]*\))/*(\1.literal \1)/g'
 
 quiet_cmd__cpp_lds_S = LDS     $@
       cmd__cpp_lds_S = $(CPP) $(cpp_flags) -P -C -Uxtensa -D__ASSEMBLY__ $< \
diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offsets.c
index 070ff8af3a21..7dc3f9157185 100644
--- a/arch/xtensa/kernel/asm-offsets.c
+++ b/arch/xtensa/kernel/asm-offsets.c
@@ -13,6 +13,7 @@
  */
 
 #include <asm/processor.h>
+#include <asm/coprocessor.h>
 
 #include <linux/types.h>
 #include <linux/stddef.h>
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index 77fc9f6dc016..5fd01f6aaf37 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -16,6 +16,7 @@
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/processor.h>
+#include <asm/coprocessor.h>
 #include <asm/thread_info.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index d215adcfd4ea..3ef91a73652d 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -184,8 +184,8 @@ _startup:
          * Now clear the BSS segment.
          */
 
-        movi    a2, _bss_start  # start of BSS
-        movi    a3, _bss_end    # end of BSS
+        movi    a2, __bss_start # start of BSS
+        movi    a3, __bss_stop  # end of BSS
 
         __loopt a2, a3, a4, 2
         s32i    a0, a2, 0
diff --git a/arch/xtensa/platforms/iss/network.c b/arch/xtensa/platforms/iss/network.c
index 87e218f98ef4..f717e20d961b 100644
--- a/arch/xtensa/platforms/iss/network.c
+++ b/arch/xtensa/platforms/iss/network.c
@@ -623,6 +623,19 @@ static struct platform_driver iss_net_driver = {
 
 static int driver_registered;
 
+static const struct net_device_ops iss_netdev_ops = {
+        .ndo_open               = iss_net_open,
+        .ndo_stop               = iss_net_close,
+        .ndo_get_stats          = iss_net_get_stats,
+        .ndo_start_xmit         = iss_net_start_xmit,
+        .ndo_validate_addr      = eth_validate_addr,
+        .ndo_change_mtu         = iss_net_change_mtu,
+        .ndo_set_mac_address    = iss_net_set_mac,
+        //.ndo_do_ioctl         = iss_net_ioctl,
+        .ndo_tx_timeout         = iss_net_tx_timeout,
+        .ndo_set_multicast_list = iss_net_set_multicast_list,
+};
+
 static int iss_net_configure(int index, char *init)
 {
         struct net_device *dev;
@@ -686,15 +699,8 @@ static int iss_net_configure(int index, char *init)
          */
         snprintf(dev->name, sizeof dev->name, "eth%d", index);
 
+        dev->netdev_ops = &iss_netdev_ops;
         dev->mtu = lp->mtu;
-        dev->open = iss_net_open;
-        dev->hard_start_xmit = iss_net_start_xmit;
-        dev->stop = iss_net_close;
-        dev->get_stats = iss_net_get_stats;
-        dev->set_multicast_list = iss_net_set_multicast_list;
-        dev->tx_timeout = iss_net_tx_timeout;
-        dev->set_mac_address = iss_net_set_mac;
-        dev->change_mtu = iss_net_change_mtu;
         dev->watchdog_timeo = (HZ >> 1);
         dev->irq = -1;