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-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts156
-rw-r--r--arch/powerpc/platforms/8xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/8xx/mpc86xads.h44
-rw-r--r--arch/powerpc/platforms/8xx/mpc86xads_setup.c289
4 files changed, 175 insertions, 315 deletions
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index 90f2293ed3cd..daf9433e906b 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -12,7 +12,7 @@
12 12
13/ { 13/ {
14 model = "MPC866ADS"; 14 model = "MPC866ADS";
15 compatible = "mpc8xx"; 15 compatible = "fsl,mpc866ads";
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 18
@@ -23,15 +23,15 @@
23 PowerPC,866@0 { 23 PowerPC,866@0 {
24 device_type = "cpu"; 24 device_type = "cpu";
25 reg = <0>; 25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes 26 d-cache-line-size = <10>; // 16 bytes
27 i-cache-line-size = <20>; // 32 bytes 27 i-cache-line-size = <10>; // 16 bytes
28 d-cache-size = <2000>; // L1, 8K 28 d-cache-size = <2000>; // L1, 8K
29 i-cache-size = <4000>; // L1, 16K 29 i-cache-size = <4000>; // L1, 16K
30 timebase-frequency = <0>; 30 timebase-frequency = <0>;
31 bus-frequency = <0>; 31 bus-frequency = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 interrupts = <f 2>; // decrementer interrupt 33 interrupts = <f 2>; // decrementer interrupt
34 interrupt-parent = <&Mpc8xx_pic>; 34 interrupt-parent = <&PIC>;
35 }; 35 };
36 }; 36 };
37 37
@@ -40,107 +40,139 @@
40 reg = <00000000 800000>; 40 reg = <00000000 800000>;
41 }; 41 };
42 42
43 soc866@ff000000 { 43 localbus@ff000100 {
44 compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
45 #address-cells = <2>;
46 #size-cells = <1>;
47 reg = <ff000100 40>;
48
49 ranges = <
50 1 0 ff080000 00008000
51 5 0 ff0a0000 00008000
52 >;
53
54 board-control@1,0 {
55 reg = <1 0 20 5 300 4>;
56 compatible = "fsl,mpc866ads-bcsr";
57 };
58 };
59
60 soc@ff000000 {
44 #address-cells = <1>; 61 #address-cells = <1>;
45 #size-cells = <1>; 62 #size-cells = <1>;
46 device_type = "soc"; 63 device_type = "soc";
47 ranges = <0 ff000000 00100000>; 64 ranges = <0 ff000000 00100000>;
48 reg = <ff000000 00000200>; 65 reg = <ff000000 00000200>;
49 bus-frequency = <0>; 66 bus-frequency = <0>;
50 mdio@e80 { 67
51 device_type = "mdio"; 68 mdio@e00 {
52 compatible = "fs_enet"; 69 compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
53 reg = <e80 8>; 70 reg = <e00 188>;
54 #address-cells = <1>; 71 #address-cells = <1>;
55 #size-cells = <0>; 72 #size-cells = <0>;
56 phy: ethernet-phy@f { 73 PHY: ethernet-phy@f {
57 reg = <f>; 74 reg = <f>;
58 device_type = "ethernet-phy"; 75 device_type = "ethernet-phy";
59 }; 76 };
60 }; 77 };
61 78
62 fec@e00 { 79 ethernet@e00 {
63 device_type = "network"; 80 device_type = "network";
64 compatible = "fs_enet"; 81 compatible = "fsl,mpc866-fec-enet",
65 model = "FEC"; 82 "fsl,pq1-fec-enet";
66 device-id = <1>;
67 reg = <e00 188>; 83 reg = <e00 188>;
68 mac-address = [ 00 00 0C 00 01 FD ]; 84 local-mac-address = [ 00 00 00 00 00 00 ];
69 interrupts = <3 1>; 85 interrupts = <3 1>;
70 interrupt-parent = <&Mpc8xx_pic>; 86 interrupt-parent = <&PIC>;
71 phy-handle = <&Phy>; 87 phy-handle = <&PHY>;
88 linux,network-index = <0>;
72 }; 89 };
73 90
74 mpc8xx_pic: pic@ff000000 { 91 PIC: pic@0 {
75 interrupt-controller; 92 interrupt-controller;
76 #address-cells = <0>;
77 #interrupt-cells = <2>; 93 #interrupt-cells = <2>;
78 reg = <0 24>; 94 reg = <0 24>;
79 device_type = "mpc8xx-pic"; 95 compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
80 compatible = "CPM";
81 }; 96 };
82 97
83 cpm@ff000000 { 98 cpm@9c0 {
84 #address-cells = <1>; 99 #address-cells = <1>;
85 #size-cells = <1>; 100 #size-cells = <1>;
86 device_type = "cpm"; 101 compatible = "fsl,mpc866-cpm", "fsl,cpm1";
87 model = "CPM"; 102 ranges;
88 ranges = <0 0 4000>; 103 reg = <9c0 40>;
89 reg = <860 f0>;
90 command-proc = <9c0>;
91 brg-frequency = <0>; 104 brg-frequency = <0>;
92 interrupts = <0 2>; // cpm error interrupt 105 interrupts = <0 2>; // cpm error interrupt
93 interrupt-parent = <&Cpm_pic>; 106 interrupt-parent = <&CPM_PIC>;
94 107
95 cpm_pic: pic@930 { 108 muram@2000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges = <0 2000 2000>;
112
113 data@0 {
114 compatible = "fsl,cpm-muram-data";
115 reg = <0 1c00>;
116 };
117 };
118
119 brg@9f0 {
120 compatible = "fsl,mpc866-brg",
121 "fsl,cpm1-brg",
122 "fsl,cpm-brg";
123 reg = <9f0 10>;
124 clock-frequency = <0>;
125 };
126
127 CPM_PIC: pic@930 {
96 interrupt-controller; 128 interrupt-controller;
97 #address-cells = <0>; 129 #address-cells = <0>;
98 #interrupt-cells = <2>; 130 #interrupt-cells = <1>;
99 interrupts = <5 2 0 2>; 131 interrupts = <5 2 0 2>;
100 interrupt-parent = <&Mpc8xx_pic>; 132 interrupt-parent = <&PIC>;
101 reg = <930 20>; 133 reg = <930 20>;
102 device_type = "cpm-pic"; 134 compatible = "fsl,mpc866-cpm-pic",
103 compatible = "CPM"; 135 "fsl,cpm1-pic";
104 }; 136 };
105 137
106 smc@a80 { 138
139 serial@a80 {
107 device_type = "serial"; 140 device_type = "serial";
108 compatible = "cpm_uart"; 141 compatible = "fsl,mpc866-smc-uart",
109 model = "SMC"; 142 "fsl,cpm1-smc-uart";
110 device-id = <1>;
111 reg = <a80 10 3e80 40>; 143 reg = <a80 10 3e80 40>;
112 clock-setup = <00ffffff 0>; 144 interrupts = <4>;
113 rx-clock = <1>; 145 interrupt-parent = <&CPM_PIC>;
114 tx-clock = <1>; 146 fsl,cpm-brg = <1>;
115 current-speed = <0>; 147 fsl,cpm-command = <0090>;
116 interrupts = <4 3>;
117 interrupt-parent = <&Cpm_pic>;
118 }; 148 };
119 149
120 smc@a90 { 150 serial@a90 {
121 device_type = "serial"; 151 device_type = "serial";
122 compatible = "cpm_uart"; 152 compatible = "fsl,mpc866-smc-uart",
123 model = "SMC"; 153 "fsl,cpm1-smc-uart";
124 device-id = <2>; 154 reg = <a90 10 3f80 40>;
125 reg = <a90 20 3f80 40>; 155 interrupts = <3>;
126 clock-setup = <ff00ffff 90000>; 156 interrupt-parent = <&CPM_PIC>;
127 rx-clock = <2>; 157 fsl,cpm-brg = <2>;
128 tx-clock = <2>; 158 fsl,cpm-command = <00d0>;
129 current-speed = <0>;
130 interrupts = <3 3>;
131 interrupt-parent = <&Cpm_pic>;
132 }; 159 };
133 160
134 scc@a00 { 161 ethernet@a00 {
135 device_type = "network"; 162 device_type = "network";
136 compatible = "fs_enet"; 163 compatible = "fsl,mpc866-scc-enet",
137 model = "SCC"; 164 "fsl,cpm1-scc-enet";
138 device-id = <1>; 165 reg = <a00 18 3c00 100>;
139 reg = <a00 18 3c00 80>; 166 local-mac-address = [ 00 00 00 00 00 00 ];
140 mac-address = [ 00 00 0C 00 03 FD ]; 167 interrupts = <1e>;
141 interrupts = <1e 3>; 168 interrupt-parent = <&CPM_PIC>;
142 interrupt-parent = <&Cpm_pic>; 169 fsl,cpm-command = <0000>;
170 linux,network-index = <1>;
143 }; 171 };
144 }; 172 };
145 }; 173 };
174
175 chosen {
176 linux,stdout-path = "/soc/cpm/serial@a80";
177 };
146}; 178};
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index bd28655043a0..91fbe4241918 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -18,6 +18,7 @@ config MPC8XXFADS
18config MPC86XADS 18config MPC86XADS
19 bool "MPC86XADS" 19 bool "MPC86XADS"
20 select CPM1 20 select CPM1
21 select PPC_CPM_NEW_BINDING
21 help 22 help
22 MPC86x Application Development System by Freescale Semiconductor. 23 MPC86x Application Development System by Freescale Semiconductor.
23 The MPC86xADS is meant to serve as a platform for s/w and h/w 24 The MPC86xADS is meant to serve as a platform for s/w and h/w
diff --git a/arch/powerpc/platforms/8xx/mpc86xads.h b/arch/powerpc/platforms/8xx/mpc86xads.h
index cffa194ccf1f..17b1fe75e0b2 100644
--- a/arch/powerpc/platforms/8xx/mpc86xads.h
+++ b/arch/powerpc/platforms/8xx/mpc86xads.h
@@ -15,27 +15,6 @@
15#ifndef __ASM_MPC86XADS_H__ 15#ifndef __ASM_MPC86XADS_H__
16#define __ASM_MPC86XADS_H__ 16#define __ASM_MPC86XADS_H__
17 17
18#include <sysdev/fsl_soc.h>
19
20/* U-Boot maps BCSR to 0xff080000 */
21#define BCSR_ADDR ((uint)0xff080000)
22#define BCSR_SIZE ((uint)32)
23#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
24#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
25#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
26#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
27#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
28
29#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
30#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
31
32#define MPC8xx_CPM_OFFSET (0x9c0)
33#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
34#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
35
36#define PCMCIA_MEM_ADDR ((uint)0xff020000)
37#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
38
39/* Bits of interest in the BCSRs. 18/* Bits of interest in the BCSRs.
40 */ 19 */
41#define BCSR1_ETHEN ((uint)0x20000000) 20#define BCSR1_ETHEN ((uint)0x20000000)
@@ -64,28 +43,5 @@
64#define BCSR5_MII1_EN 0x02 43#define BCSR5_MII1_EN 0x02
65#define BCSR5_MII1_RST 0x01 44#define BCSR5_MII1_RST 0x01
66 45
67/* Interrupt level assignments */
68#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
69#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
70#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
71
72/* We don't use the 8259 */
73#define NR_8259_INTS 0
74
75/* CPM Ethernet through SCC1 */
76#define PA_ENET_RXD ((ushort)0x0001)
77#define PA_ENET_TXD ((ushort)0x0002)
78#define PA_ENET_TCLK ((ushort)0x0100)
79#define PA_ENET_RCLK ((ushort)0x0200)
80#define PB_ENET_TENA ((uint)0x00001000)
81#define PC_ENET_CLSN ((ushort)0x0010)
82#define PC_ENET_RENA ((ushort)0x0020)
83
84/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
85 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
86 */
87#define SICR_ENET_MASK ((uint)0x000000ff)
88#define SICR_ENET_CLKRT ((uint)0x0000002c)
89
90#endif /* __ASM_MPC86XADS_H__ */ 46#endif /* __ASM_MPC86XADS_H__ */
91#endif /* __KERNEL__ */ 47#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
index 49012835f453..d2927a434aef 100644
--- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
@@ -6,264 +6,134 @@
6 * 6 *
7 * Copyright 2005 MontaVista Software Inc. 7 * Copyright 2005 MontaVista Software Inc.
8 * 8 *
9 * Heavily modified by Scott Wood <scottwood@freescale.com>
10 * Copyright 2007 Freescale Semiconductor, Inc.
11 *
9 * This file is licensed under the terms of the GNU General Public License 12 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any 13 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied. 14 * kind, whether express or implied.
12 */ 15 */
13 16
14#include <linux/init.h> 17#include <linux/init.h>
15#include <linux/module.h> 18#include <linux/of_platform.h>
16#include <linux/param.h>
17#include <linux/string.h>
18#include <linux/ioport.h>
19#include <linux/device.h>
20#include <linux/delay.h>
21#include <linux/root_dev.h>
22
23#include <linux/fs_enet_pd.h>
24#include <linux/fs_uart_pd.h>
25#include <linux/mii.h>
26 19
27#include <asm/delay.h>
28#include <asm/io.h> 20#include <asm/io.h>
29#include <asm/machdep.h> 21#include <asm/machdep.h>
30#include <asm/page.h>
31#include <asm/processor.h>
32#include <asm/system.h> 22#include <asm/system.h>
33#include <asm/time.h> 23#include <asm/time.h>
34#include <asm/mpc8xx.h> 24#include <asm/mpc8xx.h>
35#include <asm/8xx_immap.h> 25#include <asm/8xx_immap.h>
36#include <asm/commproc.h> 26#include <asm/commproc.h>
37#include <asm/fs_pd.h> 27#include <asm/fs_pd.h>
38#include <asm/prom.h> 28#include <asm/udbg.h>
39 29
40#include <sysdev/commproc.h> 30#include <sysdev/commproc.h>
41 31
42static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi); 32#include "mpc86xads.h"
43static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
44static void init_scc1_ioports(struct fs_platform_info* ptr);
45
46void __init mpc86xads_board_setup(void)
47{
48 cpm8xx_t *cp;
49 unsigned int *bcsr_io;
50 u8 tmpval8;
51
52 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
53 cp = (cpm8xx_t *)immr_map(im_cpm);
54
55 if (bcsr_io == NULL) {
56 printk(KERN_CRIT "Could not remap BCSR\n");
57 return;
58 }
59#ifdef CONFIG_SERIAL_CPM_SMC1
60 clrbits32(bcsr_io, BCSR1_RS232EN_1);
61 clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
62 tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
63 out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
64 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
65#else
66 setbits32(bcsr_io,BCSR1_RS232EN_1);
67 out_be16(&cp->cp_smc[0].smc_smcmr, 0);
68 out_8(&cp->cp_smc[0].smc_smce, 0);
69#endif
70
71#ifdef CONFIG_SERIAL_CPM_SMC2
72 clrbits32(bcsr_io,BCSR1_RS232EN_2);
73 clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
74 setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
75 tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
76 out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
77 clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
78 33
79 init_smc2_uart_ioports(0); 34struct cpm_pin {
80#else 35 int port, pin, flags;
81 setbits32(bcsr_io,BCSR1_RS232EN_2); 36};
82 out_be16(&cp->cp_smc[1].smc_smcmr, 0);
83 out_8(&cp->cp_smc[1].smc_smce, 0);
84#endif
85 immr_unmap(cp);
86 iounmap(bcsr_io);
87}
88 37
38static struct cpm_pin mpc866ads_pins[] = {
39 /* SMC1 */
40 {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
41 {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
42
43 /* SMC2 */
44 {CPM_PORTB, 21, CPM_PIN_INPUT}, /* RX */
45 {CPM_PORTB, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
46
47 /* SCC1 */
48 {CPM_PORTA, 6, CPM_PIN_INPUT}, /* CLK1 */
49 {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
50 {CPM_PORTA, 14, CPM_PIN_INPUT}, /* TX */
51 {CPM_PORTA, 15, CPM_PIN_INPUT}, /* RX */
52 {CPM_PORTB, 19, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
53 {CPM_PORTC, 10, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
54 {CPM_PORTC, 11, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
55
56 /* MII */
57 {CPM_PORTD, 3, CPM_PIN_OUTPUT},
58 {CPM_PORTD, 4, CPM_PIN_OUTPUT},
59 {CPM_PORTD, 5, CPM_PIN_OUTPUT},
60 {CPM_PORTD, 6, CPM_PIN_OUTPUT},
61 {CPM_PORTD, 7, CPM_PIN_OUTPUT},
62 {CPM_PORTD, 8, CPM_PIN_OUTPUT},
63 {CPM_PORTD, 9, CPM_PIN_OUTPUT},
64 {CPM_PORTD, 10, CPM_PIN_OUTPUT},
65 {CPM_PORTD, 11, CPM_PIN_OUTPUT},
66 {CPM_PORTD, 12, CPM_PIN_OUTPUT},
67 {CPM_PORTD, 13, CPM_PIN_OUTPUT},
68 {CPM_PORTD, 14, CPM_PIN_OUTPUT},
69 {CPM_PORTD, 15, CPM_PIN_OUTPUT},
70};
89 71
90static void init_fec1_ioports(struct fs_platform_info* ptr) 72static void __init init_ioports(void)
91{ 73{
92 iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport); 74 int i;
93 75
94 /* configure FEC1 pins */ 76 for (i = 0; i < ARRAY_SIZE(mpc866ads_pins); i++) {
77 struct cpm_pin *pin = &mpc866ads_pins[i];
78 cpm1_set_pin(pin->port, pin->pin, pin->flags);
79 }
95 80
96 setbits16(&io_port->iop_pdpar, 0x1fff); 81 cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
97 setbits16(&io_port->iop_pddir, 0x1fff); 82 cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
83 cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK1, CPM_CLK_TX);
84 cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
98 85
99 immr_unmap(io_port); 86 /* Set FEC1 and FEC2 to MII mode */
87 clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
100} 88}
101 89
102void init_fec_ioports(struct fs_platform_info *fpi) 90static void __init mpc86xads_setup_arch(void)
103{ 91{
104 int fec_no = fs_get_fec_index(fpi->fs_no); 92 struct device_node *np;
93 u32 __iomem *bcsr_io;
94
95 cpm_reset();
96 init_ioports();
105 97
106 switch (fec_no) { 98 np = of_find_compatible_node(NULL, NULL, "fsl,mpc866ads-bcsr");
107 case 0: 99 if (!np) {
108 init_fec1_ioports(fpi); 100 printk(KERN_CRIT "Could not find fsl,mpc866ads-bcsr node\n");
109 break;
110 default:
111 printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
112 return; 101 return;
113 } 102 }
114}
115 103
116static void init_scc1_ioports(struct fs_platform_info* fpi) 104 bcsr_io = of_iomap(np, 0);
117{ 105 of_node_put(np);
118 unsigned *bcsr_io;
119 iop8xx_t *io_port;
120 cpm8xx_t *cp;
121
122 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
123 io_port = (iop8xx_t *)immr_map(im_ioport);
124 cp = (cpm8xx_t *)immr_map(im_cpm);
125 106
126 if (bcsr_io == NULL) { 107 if (bcsr_io == NULL) {
127 printk(KERN_CRIT "Could not remap BCSR\n"); 108 printk(KERN_CRIT "Could not remap BCSR\n");
128 return; 109 return;
129 } 110 }
130 111
131 /* Configure port A pins for Txd and Rxd. 112 clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
132 */
133 setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
134 clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
135 clrbits16(&io_port->iop_paodr, PA_ENET_TXD);
136
137 /* Configure port C pins to enable CLSN and RENA.
138 */
139 clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
140 clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
141 setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
142
143 /* Configure port A for TCLK and RCLK.
144 */
145 setbits16(&io_port->iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
146 clrbits16(&io_port->iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
147 clrbits32(&cp->cp_pbpar, PB_ENET_TENA);
148 clrbits32(&cp->cp_pbdir, PB_ENET_TENA);
149
150 /* Configure Serial Interface clock routing.
151 * First, clear all SCC bits to zero, then set the ones we want.
152 */
153 clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
154 setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
155
156 /* In the original SCC enet driver the following code is placed at
157 the end of the initialization */
158 setbits32(&cp->cp_pbpar, PB_ENET_TENA);
159 setbits32(&cp->cp_pbdir, PB_ENET_TENA);
160
161 clrbits32(bcsr_io+1, BCSR1_ETHEN);
162 iounmap(bcsr_io); 113 iounmap(bcsr_io);
163 immr_unmap(cp);
164 immr_unmap(io_port);
165}
166
167void init_scc_ioports(struct fs_platform_info *fpi)
168{
169 int scc_no = fs_get_scc_index(fpi->fs_no);
170
171 switch (scc_no) {
172 case 0:
173 init_scc1_ioports(fpi);
174 break;
175 default:
176 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
177 return;
178 }
179} 114}
180 115
181 116static int __init mpc86xads_probe(void)
182
183static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr)
184{ 117{
185 unsigned *bcsr_io; 118 unsigned long root = of_get_flat_dt_root();
186 cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm); 119 return of_flat_dt_is_compatible(root, "fsl,mpc866ads");
187
188 setbits32(&cp->cp_pbpar, 0x000000c0);
189 clrbits32(&cp->cp_pbdir, 0x000000c0);
190 clrbits16(&cp->cp_pbodr, 0x00c0);
191 immr_unmap(cp);
192
193 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
194
195 if (bcsr_io == NULL) {
196 printk(KERN_CRIT "Could not remap BCSR1\n");
197 return;
198 }
199 clrbits32(bcsr_io,BCSR1_RS232EN_1);
200 iounmap(bcsr_io);
201} 120}
202 121
203static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi) 122static struct of_device_id __initdata of_bus_ids[] = {
204{ 123 { .name = "soc", },
205 unsigned *bcsr_io; 124 { .name = "cpm", },
206 cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm); 125 { .name = "localbus", },
207 126 {},
208 setbits32(&cp->cp_pbpar, 0x00000c00); 127};
209 clrbits32(&cp->cp_pbdir, 0x00000c00);
210 clrbits16(&cp->cp_pbodr, 0x0c00);
211 immr_unmap(cp);
212
213 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
214
215 if (bcsr_io == NULL) {
216 printk(KERN_CRIT "Could not remap BCSR1\n");
217 return;
218 }
219 clrbits32(bcsr_io,BCSR1_RS232EN_2);
220 iounmap(bcsr_io);
221}
222 128
223void init_smc_ioports(struct fs_uart_platform_info *data) 129static int __init declare_of_platform_devices(void)
224{ 130{
225 int smc_no = fs_uart_id_fsid2smc(data->fs_no); 131 if (machine_is(mpc86x_ads))
132 of_platform_bus_probe(NULL, of_bus_ids, NULL);
226 133
227 switch (smc_no) {
228 case 0:
229 init_smc1_uart_ioports(data);
230 data->brg = data->clk_rx;
231 break;
232 case 1:
233 init_smc2_uart_ioports(data);
234 data->brg = data->clk_rx;
235 break;
236 default:
237 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
238 return;
239 }
240}
241
242int platform_device_skip(const char *model, int id)
243{
244 return 0; 134 return 0;
245} 135}
246 136device_initcall(declare_of_platform_devices);
247static void __init mpc86xads_setup_arch(void)
248{
249 cpm_reset();
250
251 mpc86xads_board_setup();
252
253 ROOT_DEV = Root_NFS;
254}
255
256static int __init mpc86xads_probe(void)
257{
258 char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
259 "model", NULL);
260 if (model == NULL)
261 return 0;
262 if (strcmp(model, "MPC866ADS"))
263 return 0;
264
265 return 1;
266}
267 137
268define_machine(mpc86x_ads) { 138define_machine(mpc86x_ads) {
269 .name = "MPC86x ADS", 139 .name = "MPC86x ADS",
@@ -275,4 +145,5 @@ define_machine(mpc86x_ads) {
275 .calibrate_decr = mpc8xx_calibrate_decr, 145 .calibrate_decr = mpc8xx_calibrate_decr,
276 .set_rtc_time = mpc8xx_set_rtc_time, 146 .set_rtc_time = mpc8xx_set_rtc_time,
277 .get_rtc_time = mpc8xx_get_rtc_time, 147 .get_rtc_time = mpc8xx_get_rtc_time,
148 .progress = udbg_progress,
278}; 149};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 05:28:51 -0400