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-rw-r--r--arch/arm/mach-orion/common.h4
-rw-r--r--arch/arm/mach-orion/pci.c343
-rw-r--r--arch/arm/plat-orion/Makefile2
-rw-r--r--arch/arm/plat-orion/pcie.c245
4 files changed, 334 insertions, 260 deletions
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h
index b676be0a4a86..9a5afefac4dc 100644
--- a/arch/arm/mach-orion/common.h
+++ b/arch/arm/mach-orion/common.h
@@ -43,8 +43,8 @@ struct pci_sys_data;
43struct pci_bus; 43struct pci_bus;
44 44
45void orion_pcie_id(u32 *dev, u32 *rev); 45void orion_pcie_id(u32 *dev, u32 *rev);
46u32 orion_pcie_local_bus_nr(void); 46int orion_pcie_local_bus_nr(void);
47u32 orion_pci_local_bus_nr(void); 47int orion_pci_local_bus_nr(void);
48int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); 48int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
49struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); 49struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
50 50
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
index cfd3d064c209..5240a245c7e4 100644
--- a/arch/arm/mach-orion/pci.c
+++ b/arch/arm/mach-orion/pci.c
@@ -14,6 +14,7 @@
14#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <asm/mach/pci.h> 16#include <asm/mach/pci.h>
17#include <asm/plat-orion/pcie.h>
17#include "common.h" 18#include "common.h"
18 19
19/***************************************************************************** 20/*****************************************************************************
@@ -32,288 +33,136 @@
32/***************************************************************************** 33/*****************************************************************************
33 * PCIE controller 34 * PCIE controller
34 ****************************************************************************/ 35 ****************************************************************************/
35#define PCIE_CTRL ORION_PCIE_REG(0x1a00) 36#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE)
36#define PCIE_STAT ORION_PCIE_REG(0x1a04)
37#define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
38#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
39#define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
40#define PCIE_MASK ORION_PCIE_REG(0x1910)
41#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
42#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
43
44/*
45 * PCIE_STAT bits
46 */
47#define PCIE_STAT_LINK_DOWN 1
48#define PCIE_STAT_BUS_OFFS 8
49#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
50#define PCIE_STAT_DEV_OFFS 20
51#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
52
53/*
54 * PCIE_CONF_ADDR bits
55 */
56#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc))
57#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
58#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
59#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
60#define PCIE_CONF_ADDR_EN (1 << 31)
61
62/*
63 * PCIE Address Decode Windows registers
64 */
65#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
66#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
67#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
68#define PCIE_WIN_CTRL(n) (((n) < 5) ? \
69 ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
70 ORION_PCIE_REG(0x1880))
71#define PCIE_WIN_BASE(n) (((n) < 5) ? \
72 ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
73 ORION_PCIE_REG(0x1884))
74#define PCIE_WIN_REMAP(n) (((n) < 5) ? \
75 ORION_PCIE_REG(0x182c + ((n) << 4)) : \
76 ORION_PCIE_REG(0x188c))
77#define PCIE_MAX_BARS 3
78#define PCIE_MAX_WINS 6
79
80/*
81 * Use PCIE BAR '1' for all DDR banks
82 */
83#define PCIE_DRAM_BAR 1
84
85/*
86 * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
87 * and then reading the PCIE_CONF_DATA register. Need to make sure these
88 * transactions are atomic.
89 */
90static DEFINE_SPINLOCK(orion_pcie_lock);
91 37
92void orion_pcie_id(u32 *dev, u32 *rev) 38void orion_pcie_id(u32 *dev, u32 *rev)
93{ 39{
94 *dev = orion_read(PCIE_DEV_ID) >> 16; 40 *dev = orion_pcie_dev_id(PCIE_BASE);
95 *rev = orion_read(PCIE_DEV_REV) & 0xff; 41 *rev = orion_pcie_rev(PCIE_BASE);
96}
97
98u32 orion_pcie_local_bus_nr(void)
99{
100 u32 stat = orion_read(PCIE_STAT);
101 return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
102}
103
104static u32 orion_pcie_local_dev_nr(void)
105{
106 u32 stat = orion_read(PCIE_STAT);
107 return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
108}
109
110static u32 orion_pcie_no_link(void)
111{
112 u32 stat = orion_read(PCIE_STAT);
113 return(stat & PCIE_STAT_LINK_DOWN);
114}
115
116static void orion_pcie_set_bus_nr(int nr)
117{
118 orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
119 orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
120} 42}
121 43
122/* 44int orion_pcie_local_bus_nr(void)
123 * Setup PCIE BARs and Address Decode Wins:
124 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
125 * WIN[0-3] -> DRAM bank[0-3]
126 */
127static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram)
128{ 45{
129 u32 size; 46 return orion_pcie_get_local_bus_nr(PCIE_BASE);
130 int i;
131
132 /*
133 * First, disable and clear BARs and windows
134 */
135 for (i = 1; i < PCIE_MAX_BARS; i++) {
136 writel(0, PCIE_BAR_CTRL(i));
137 writel(0, PCIE_BAR_LO(i));
138 writel(0, PCIE_BAR_HI(i));
139 }
140
141 for (i = 0; i < PCIE_MAX_WINS; i++) {
142 writel(0, PCIE_WIN_CTRL(i));
143 writel(0, PCIE_WIN_BASE(i));
144 writel(0, PCIE_WIN_REMAP(i));
145 }
146
147 /*
148 * Setup windows for DDR banks. Count total DDR size on the fly.
149 */
150 size = 0;
151 for (i = 0; i < dram->num_cs; i++) {
152 struct mbus_dram_window *cs = dram->cs + i;
153
154 writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i));
155 writel(0, PCIE_WIN_REMAP(i));
156 writel(((cs->size - 1) & 0xffff0000) |
157 (cs->mbus_attr << 8) |
158 (dram->mbus_dram_target_id << 4) |
159 (PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i));
160
161 size += cs->size;
162 }
163
164 /*
165 * Setup BAR[1] to all DRAM banks
166 */
167 writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR));
168 writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR));
169 writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR));
170} 47}
171 48
172static void orion_pcie_master_slave_enable(void) 49static int pcie_valid_config(int bus, int dev)
173{
174 orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
175 PCI_COMMAND_IO |
176 PCI_COMMAND_MEMORY);
177}
178
179static void orion_pcie_enable_interrupts(void)
180{
181 /*
182 * Enable interrupts lines
183 * INTA[24] INTB[25] INTC[26] INTD[27]
184 */
185 orion_setbits(PCIE_MASK, 0xf<<24);
186}
187
188static int orion_pcie_valid_config(u32 bus, u32 dev)
189{ 50{
190 /* 51 /*
191 * Don't go out when trying to access -- 52 * Don't go out when trying to access --
192 * 1. our own device 53 * 1. our own device / nonexisting device on local bus
193 * 2. where there's no device connected (no link) 54 * 2. where there's no device connected (no link)
194 * 3. nonexisting devices on local bus
195 */ 55 */
196 56 if (bus == 0 && dev != 1)
197 if ((orion_pcie_local_bus_nr() == bus) &&
198 (orion_pcie_local_dev_nr() == dev))
199 return 0;
200
201 if (orion_pcie_no_link())
202 return 0; 57 return 0;
203 58
204 if (bus == orion_pcie_local_bus_nr()) 59 if (!orion_pcie_link_up(PCIE_BASE))
205 if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
206 ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
207 return 0; 60 return 0;
208 61
209 return 1; 62 return 1;
210} 63}
211 64
212static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 65
213 int size, u32 *val) 66/*
67 * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
68 * and then reading the PCIE_CONF_DATA register. Need to make sure these
69 * transactions are atomic.
70 */
71static DEFINE_SPINLOCK(orion_pcie_lock);
72
73static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
74 int size, u32 *val)
214{ 75{
215 unsigned long flags; 76 unsigned long flags;
216 unsigned int dev, rev, pcie_addr; 77 int ret;
217 78
218 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 79 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
219 *val = 0xffffffff; 80 *val = 0xffffffff;
220 return PCIBIOS_DEVICE_NOT_FOUND; 81 return PCIBIOS_DEVICE_NOT_FOUND;
221 } 82 }
222 83
223 spin_lock_irqsave(&orion_pcie_lock, flags); 84 spin_lock_irqsave(&orion_pcie_lock, flags);
85 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
86 spin_unlock_irqrestore(&orion_pcie_lock, flags);
224 87
225 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | 88 return ret;
226 PCIE_CONF_DEV(PCI_SLOT(devfn)) | 89}
227 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
228 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
229 90
230 orion_pcie_id(&dev, &rev); 91static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
231 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 92 int where, int size, u32 *val)
232 /* extended register space */ 93{
233 pcie_addr = ORION_PCIE_WA_VIRT_BASE; 94 int ret;
234 pcie_addr |= PCIE_CONF_BUS(bus->number) |
235 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
236 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
237 PCIE_CONF_REG(where);
238 *val = orion_read(pcie_addr);
239 } else
240 *val = orion_read(PCIE_CONF_DATA);
241 95
242 if (size == 1) 96 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
243 *val = (*val >> (8*(where & 0x3))) & 0xff; 97 *val = 0xffffffff;
244 else if (size == 2) 98 return PCIBIOS_DEVICE_NOT_FOUND;
245 *val = (*val >> (8*(where & 0x3))) & 0xffff; 99 }
246 100
247 spin_unlock_irqrestore(&orion_pcie_lock, flags); 101 /*
102 * We only support access to the non-extended configuration
103 * space when using the WA access method (or we would have to
104 * sacrifice 256M of CPU virtual address space.)
105 */
106 if (where >= 0x100) {
107 *val = 0xffffffff;
108 return PCIBIOS_DEVICE_NOT_FOUND;
109 }
248 110
249 return PCIBIOS_SUCCESSFUL; 111 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE,
250} 112 bus, devfn, where, size, val);
251 113
114 return ret;
115}
252 116
253static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, 117static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
254 int size, u32 val) 118 int where, int size, u32 val)
255{ 119{
256 unsigned long flags; 120 unsigned long flags;
257 int ret; 121 int ret;
258 122
259 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 123 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
260 return PCIBIOS_DEVICE_NOT_FOUND; 124 return PCIBIOS_DEVICE_NOT_FOUND;
261 125
262 spin_lock_irqsave(&orion_pcie_lock, flags); 126 spin_lock_irqsave(&orion_pcie_lock, flags);
263 127 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
264 ret = PCIBIOS_SUCCESSFUL;
265
266 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
267 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
268 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
269 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
270
271 if (size == 4) {
272 __raw_writel(val, PCIE_CONF_DATA);
273 } else if (size == 2) {
274 __raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
275 } else if (size == 1) {
276 __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
277 } else {
278 ret = PCIBIOS_BAD_REGISTER_NUMBER;
279 }
280
281 spin_unlock_irqrestore(&orion_pcie_lock, flags); 128 spin_unlock_irqrestore(&orion_pcie_lock, flags);
282 129
283 return ret; 130 return ret;
284} 131}
285 132
286struct pci_ops orion_pcie_ops = { 133struct pci_ops pcie_ops = {
287 .read = orion_pcie_rd_conf, 134 .read = pcie_rd_conf,
288 .write = orion_pcie_wr_conf, 135 .write = pcie_wr_conf,
289}; 136};
290 137
291 138
292static int orion_pcie_setup(struct pci_sys_data *sys) 139static int pcie_setup(struct pci_sys_data *sys)
293{ 140{
294 struct resource *res; 141 struct resource *res;
142 int dev;
295 143
296 /* 144 /*
297 * Point PCIe unit MBUS decode windows to DRAM space. 145 * Generic PCIe unit setup.
298 */
299 orion_setup_pcie_wins(&orion_mbus_dram_info);
300
301 /*
302 * Master + Slave enable
303 */ 146 */
304 orion_pcie_master_slave_enable(); 147 orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info);
305 148
306 /* 149 /*
307 * Enable interrupts lines A-D 150 * Check whether to apply Orion-1/Orion-NAS PCIe config
151 * read transaction workaround.
308 */ 152 */
309 orion_pcie_enable_interrupts(); 153 dev = orion_pcie_dev_id(PCIE_BASE);
154 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
155 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
156 "read transaction workaround\n");
157 pcie_ops.read = pcie_rd_conf_wa;
158 }
310 159
311 /* 160 /*
312 * Request resource 161 * Request resources.
313 */ 162 */
314 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 163 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
315 if (!res) 164 if (!res)
316 panic("orion_pci_setup unable to alloc resources"); 165 panic("pcie_setup unable to alloc resources");
317 166
318 /* 167 /*
319 * IORESOURCE_IO 168 * IORESOURCE_IO
@@ -417,19 +266,19 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
417 */ 266 */
418static DEFINE_SPINLOCK(orion_pci_lock); 267static DEFINE_SPINLOCK(orion_pci_lock);
419 268
420u32 orion_pci_local_bus_nr(void) 269int orion_pci_local_bus_nr(void)
421{ 270{
422 u32 conf = orion_read(PCI_P2P_CONF); 271 u32 conf = orion_read(PCI_P2P_CONF);
423 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 272 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
424} 273}
425 274
426static u32 orion_pci_local_dev_nr(void) 275static int orion_pci_local_dev_nr(void)
427{ 276{
428 u32 conf = orion_read(PCI_P2P_CONF); 277 u32 conf = orion_read(PCI_P2P_CONF);
429 return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); 278 return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
430} 279}
431 280
432static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, 281static int orion_pci_hw_rd_conf(int bus, int dev, u32 func,
433 u32 where, u32 size, u32 *val) 282 u32 where, u32 size, u32 *val)
434{ 283{
435 unsigned long flags; 284 unsigned long flags;
@@ -451,7 +300,7 @@ static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
451 return PCIBIOS_SUCCESSFUL; 300 return PCIBIOS_SUCCESSFUL;
452} 301}
453 302
454static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, 303static int orion_pci_hw_wr_conf(int bus, int dev, u32 func,
455 u32 where, u32 size, u32 val) 304 u32 where, u32 size, u32 val)
456{ 305{
457 unsigned long flags; 306 unsigned long flags;
@@ -508,7 +357,7 @@ static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
508 PCI_FUNC(devfn), where, size, val); 357 PCI_FUNC(devfn), where, size, val);
509} 358}
510 359
511struct pci_ops orion_pci_ops = { 360struct pci_ops pci_ops = {
512 .read = orion_pci_rd_conf, 361 .read = orion_pci_rd_conf,
513 .write = orion_pci_wr_conf, 362 .write = orion_pci_wr_conf,
514}; 363};
@@ -540,7 +389,8 @@ static void orion_pci_set_bus_nr(int nr)
540 389
541static void orion_pci_master_slave_enable(void) 390static void orion_pci_master_slave_enable(void)
542{ 391{
543 u32 bus_nr, dev_nr, func, reg, val; 392 int bus_nr, dev_nr, func, reg;
393 u32 val;
544 394
545 bus_nr = orion_pci_local_bus_nr(); 395 bus_nr = orion_pci_local_bus_nr();
546 dev_nr = orion_pci_local_dev_nr(); 396 dev_nr = orion_pci_local_dev_nr();
@@ -554,8 +404,8 @@ static void orion_pci_master_slave_enable(void)
554static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) 404static void orion_setup_pci_wins(struct mbus_dram_target_info *dram)
555{ 405{
556 u32 win_enable; 406 u32 win_enable;
557 u32 bus; 407 int bus;
558 u32 dev; 408 int dev;
559 int i; 409 int i;
560 410
561 /* 411 /*
@@ -611,7 +461,7 @@ static void orion_setup_pci_wins(struct mbus_dram_target_info *dram)
611 orion_setbits(PCI_ADDR_DECODE_CTRL, 1); 461 orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
612} 462}
613 463
614static int orion_pci_setup(struct pci_sys_data *sys) 464static int pci_setup(struct pci_sys_data *sys)
615{ 465{
616 struct resource *res; 466 struct resource *res;
617 467
@@ -635,7 +485,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
635 */ 485 */
636 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 486 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
637 if (!res) 487 if (!res)
638 panic("orion_pci_setup unable to alloc resources"); 488 panic("pci_setup unable to alloc resources");
639 489
640 /* 490 /*
641 * IORESOURCE_IO 491 * IORESOURCE_IO
@@ -674,16 +524,11 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
674 int ret = 0; 524 int ret = 0;
675 525
676 if (nr == 0) { 526 if (nr == 0) {
677 /* 527 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
678 * PCIE setup 528 ret = pcie_setup(sys);
679 */
680 orion_pcie_set_bus_nr(0);
681 ret = orion_pcie_setup(sys);
682 } else if (nr == 1) { 529 } else if (nr == 1) {
683 /* 530 orion_pci_set_bus_nr(sys->busnr);
684 * PCI setup 531 ret = pci_setup(sys);
685 */
686 ret = orion_pci_setup(sys);
687 } 532 }
688 533
689 return ret; 534 return ret;
@@ -691,31 +536,15 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
691 536
692struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 537struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
693{ 538{
694 struct pci_ops *ops;
695 struct pci_bus *bus; 539 struct pci_bus *bus;
696 540
697
698 if (nr == 0) { 541 if (nr == 0) {
699 u32 pci_bus; 542 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
700 /*
701 * PCIE scan
702 */
703 ops = &orion_pcie_ops;
704 bus = pci_scan_bus(sys->busnr, ops, sys);
705 /*
706 * Set local PCI bus number to follow PCIE bridges (if any)
707 */
708 pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
709 orion_pci_set_bus_nr(pci_bus);
710 } else if (nr == 1) { 543 } else if (nr == 1) {
711 /* 544 bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
712 * PCI scan
713 */
714 ops = &orion_pci_ops;
715 bus = pci_scan_bus(sys->busnr, ops, sys);
716 } else { 545 } else {
717 BUG();
718 bus = NULL; 546 bus = NULL;
547 BUG();
719 } 548 }
720 549
721 return bus; 550 return bus;
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index ea4ce342a196..b33ecb60183d 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o 5obj-y := irq.o pcie.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
new file mode 100644
index 000000000000..f01966a330ee
--- /dev/null
+++ b/arch/arm/plat-orion/pcie.c
@@ -0,0 +1,245 @@
1/*
2 * arch/arm/plat-orion/pcie.c
3 *
4 * Marvell Orion SoC PCIe handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <asm/mach/pci.h>
15#include <asm/plat-orion/pcie.h>
16
17/*
18 * PCIe unit register offsets.
19 */
20#define PCIE_DEV_ID_OFF 0x0000
21#define PCIE_CMD_OFF 0x0004
22#define PCIE_DEV_REV_OFF 0x0008
23#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
24#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
25#define PCIE_HEADER_LOG_4_OFF 0x0128
26#define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
27#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
28#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
29#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
30#define PCIE_WIN5_CTRL_OFF 0x1880
31#define PCIE_WIN5_BASE_OFF 0x1884
32#define PCIE_WIN5_REMAP_OFF 0x188c
33#define PCIE_CONF_ADDR_OFF 0x18f8
34#define PCIE_CONF_ADDR_EN 0x80000000
35#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
36#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
37#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
38#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
39#define PCIE_CONF_DATA_OFF 0x18fc
40#define PCIE_MASK_OFF 0x1910
41#define PCIE_CTRL_OFF 0x1a00
42#define PCIE_STAT_OFF 0x1a04
43#define PCIE_STAT_DEV_OFFS 20
44#define PCIE_STAT_DEV_MASK 0x1f
45#define PCIE_STAT_BUS_OFFS 8
46#define PCIE_STAT_BUS_MASK 0xff
47#define PCIE_STAT_LINK_DOWN 1
48
49
50u32 __init orion_pcie_dev_id(void __iomem *base)
51{
52 return readl(base + PCIE_DEV_ID_OFF) >> 16;
53}
54
55u32 __init orion_pcie_rev(void __iomem *base)
56{
57 return readl(base + PCIE_DEV_REV_OFF) & 0xff;
58}
59
60int __init orion_pcie_link_up(void __iomem *base)
61{
62 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
63}
64
65int __init orion_pcie_get_local_bus_nr(void __iomem *base)
66{
67 u32 stat = readl(base + PCIE_STAT_OFF);
68
69 return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
70}
71
72void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
73{
74 u32 stat;
75
76 stat = readl(base + PCIE_STAT_OFF);
77 stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
78 stat |= nr << PCIE_STAT_BUS_OFFS;
79 writel(stat, base + PCIE_STAT_OFF);
80}
81
82/*
83 * Setup PCIE BARs and Address Decode Wins:
84 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
85 * WIN[0-3] -> DRAM bank[0-3]
86 */
87static void __init orion_pcie_setup_wins(void __iomem *base,
88 struct mbus_dram_target_info *dram)
89{
90 u32 size;
91 int i;
92
93 /*
94 * First, disable and clear BARs and windows.
95 */
96 for (i = 1; i <= 2; i++) {
97 writel(0, base + PCIE_BAR_CTRL_OFF(i));
98 writel(0, base + PCIE_BAR_LO_OFF(i));
99 writel(0, base + PCIE_BAR_HI_OFF(i));
100 }
101
102 for (i = 0; i < 5; i++) {
103 writel(0, base + PCIE_WIN04_CTRL_OFF(i));
104 writel(0, base + PCIE_WIN04_BASE_OFF(i));
105 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
106 }
107
108 writel(0, base + PCIE_WIN5_CTRL_OFF);
109 writel(0, base + PCIE_WIN5_BASE_OFF);
110 writel(0, base + PCIE_WIN5_REMAP_OFF);
111
112 /*
113 * Setup windows for DDR banks. Count total DDR size on the fly.
114 */
115 size = 0;
116 for (i = 0; i < dram->num_cs; i++) {
117 struct mbus_dram_window *cs = dram->cs + i;
118
119 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
120 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
121 writel(((cs->size - 1) & 0xffff0000) |
122 (cs->mbus_attr << 8) |
123 (dram->mbus_dram_target_id << 4) | 1,
124 base + PCIE_WIN04_CTRL_OFF(i));
125
126 size += cs->size;
127 }
128
129 /*
130 * Setup BAR[1] to all DRAM banks.
131 */
132 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
133 writel(0, base + PCIE_BAR_HI_OFF(1));
134 writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
135}
136
137void __init orion_pcie_setup(void __iomem *base,
138 struct mbus_dram_target_info *dram)
139{
140 u16 cmd;
141 u32 mask;
142
143 /*
144 * Point PCIe unit MBUS decode windows to DRAM space.
145 */
146 orion_pcie_setup_wins(base, dram);
147
148 /*
149 * Master + slave enable.
150 */
151 cmd = readw(base + PCIE_CMD_OFF);
152 cmd |= PCI_COMMAND_IO;
153 cmd |= PCI_COMMAND_MEMORY;
154 cmd |= PCI_COMMAND_MASTER;
155 writew(cmd, base + PCIE_CMD_OFF);
156
157 /*
158 * Enable interrupt lines A-D.
159 */
160 mask = readl(base + PCIE_MASK_OFF);
161 mask |= 0x0f000000;
162 writel(mask, base + PCIE_MASK_OFF);
163}
164
165int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
166 u32 devfn, int where, int size, u32 *val)
167{
168 writel(PCIE_CONF_BUS(bus->number) |
169 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
170 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
171 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
172 base + PCIE_CONF_ADDR_OFF);
173
174 *val = readl(base + PCIE_CONF_DATA_OFF);
175
176 if (size == 1)
177 *val = (*val >> (8 * (where & 3))) & 0xff;
178 else if (size == 2)
179 *val = (*val >> (8 * (where & 3))) & 0xffff;
180
181 return PCIBIOS_SUCCESSFUL;
182}
183
184int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
185 u32 devfn, int where, int size, u32 *val)
186{
187 writel(PCIE_CONF_BUS(bus->number) |
188 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
189 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
190 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
191 base + PCIE_CONF_ADDR_OFF);
192
193 *val = readl(base + PCIE_CONF_DATA_OFF);
194
195 if (bus->number != orion_pcie_get_local_bus_nr(base) ||
196 PCI_FUNC(devfn) != 0)
197 *val = readl(base + PCIE_HEADER_LOG_4_OFF);
198
199 if (size == 1)
200 *val = (*val >> (8 * (where & 3))) & 0xff;
201 else if (size == 2)
202 *val = (*val >> (8 * (where & 3))) & 0xffff;
203
204 return PCIBIOS_SUCCESSFUL;
205}
206
207int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
208 u32 devfn, int where, int size, u32 *val)
209{
210 *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
211 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
212 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
213 PCIE_CONF_REG(where)));
214
215 if (size == 1)
216 *val = (*val >> (8 * (where & 3))) & 0xff;
217 else if (size == 2)
218 *val = (*val >> (8 * (where & 3))) & 0xffff;
219
220 return PCIBIOS_SUCCESSFUL;
221}
222
223int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
224 u32 devfn, int where, int size, u32 val)
225{
226 int ret = PCIBIOS_SUCCESSFUL;
227
228 writel(PCIE_CONF_BUS(bus->number) |
229 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
230 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
231 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
232 base + PCIE_CONF_ADDR_OFF);
233
234 if (size == 4) {
235 writel(val, base + PCIE_CONF_DATA_OFF);
236 } else if (size == 2) {
237 writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
238 } else if (size == 1) {
239 writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
240 } else {
241 ret = PCIBIOS_BAD_REGISTER_NUMBER;
242 }
243
244 return ret;
245}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 23:50:33 -0500