diff options
Diffstat (limited to 'arch')
30 files changed, 4484 insertions, 213 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fcd1d8f95a21..0a0c88d0039c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -339,14 +339,14 @@ config ARCH_PNX4008 | |||
339 | This enables support for Philips PNX4008 mobile platform. | 339 | This enables support for Philips PNX4008 mobile platform. |
340 | 340 | ||
341 | config ARCH_PXA | 341 | config ARCH_PXA |
342 | bool "PXA2xx-based" | 342 | bool "PXA2xx/PXA3xx-based" |
343 | depends on MMU | 343 | depends on MMU |
344 | select ARCH_MTD_XIP | 344 | select ARCH_MTD_XIP |
345 | select GENERIC_GPIO | 345 | select GENERIC_GPIO |
346 | select GENERIC_TIME | 346 | select GENERIC_TIME |
347 | select GENERIC_CLOCKEVENTS | 347 | select GENERIC_CLOCKEVENTS |
348 | help | 348 | help |
349 | Support for Intel's PXA2XX processor line. | 349 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
350 | 350 | ||
351 | config ARCH_RPC | 351 | config ARCH_RPC |
352 | bool "RiscPC" | 352 | bool "RiscPC" |
@@ -489,7 +489,7 @@ source arch/arm/mm/Kconfig | |||
489 | config IWMMXT | 489 | config IWMMXT |
490 | bool "Enable iWMMXt support" | 490 | bool "Enable iWMMXt support" |
491 | depends on CPU_XSCALE || CPU_XSC3 | 491 | depends on CPU_XSCALE || CPU_XSC3 |
492 | default y if PXA27x | 492 | default y if PXA27x || PXA3xx |
493 | help | 493 | help |
494 | Enable support for iWMMXt context switching at run time if | 494 | Enable support for iWMMXt context switching at run time if |
495 | running on a CPU that supports it. | 495 | running on a CPU that supports it. |
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index 236bbe578312..67ea99ef6521 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S | |||
@@ -33,10 +33,6 @@ __XScale_start: | |||
33 | bic r0, r0, #0x1000 @ clear Icache | 33 | bic r0, r0, #0x1000 @ clear Icache |
34 | mcr p15, 0, r0, c1, c0, 0 | 34 | mcr p15, 0, r0, c1, c0, 0 |
35 | 35 | ||
36 | #ifdef CONFIG_ARCH_LUBBOCK | ||
37 | mov r7, #MACH_TYPE_LUBBOCK | ||
38 | #endif | ||
39 | |||
40 | #ifdef CONFIG_ARCH_COTULLA_IDP | 36 | #ifdef CONFIG_ARCH_COTULLA_IDP |
41 | mov r7, #MACH_TYPE_COTULLA_IDP | 37 | mov r7, #MACH_TYPE_COTULLA_IDP |
42 | #endif | 38 | #endif |
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e1289a256ce5..3d0b9fa42f84 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile | |||
@@ -17,3 +17,4 @@ obj-$(CONFIG_SHARPSL_PM) += sharpsl_pm.o | |||
17 | obj-$(CONFIG_SHARP_SCOOP) += scoop.o | 17 | obj-$(CONFIG_SHARP_SCOOP) += scoop.o |
18 | obj-$(CONFIG_ARCH_IXP2000) += uengine.o | 18 | obj-$(CONFIG_ARCH_IXP2000) += uengine.o |
19 | obj-$(CONFIG_ARCH_IXP23XX) += uengine.o | 19 | obj-$(CONFIG_ARCH_IXP23XX) += uengine.o |
20 | obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o | ||
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c new file mode 100644 index 000000000000..c03de9bfd76b --- /dev/null +++ b/arch/arm/common/it8152.c | |||
@@ -0,0 +1,387 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/common/it8152.c | ||
3 | * | ||
4 | * Copyright Compulab Ltd, 2002-2007 | ||
5 | * Mike Rapoport <mike@compulab.co.il> | ||
6 | * | ||
7 | * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c | ||
8 | * (see this file for respective copyrights) | ||
9 | * | ||
10 | * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation | ||
11 | * and demux code. | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify | ||
14 | * it under the terms of the GNU General Public License version 2 as | ||
15 | * published by the Free Software Foundation. | ||
16 | */ | ||
17 | |||
18 | #include <linux/sched.h> | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/pci.h> | ||
21 | #include <linux/ptrace.h> | ||
22 | #include <linux/interrupt.h> | ||
23 | #include <linux/mm.h> | ||
24 | #include <linux/slab.h> | ||
25 | #include <linux/init.h> | ||
26 | #include <linux/ioport.h> | ||
27 | #include <linux/irq.h> | ||
28 | #include <linux/io.h> | ||
29 | |||
30 | #include <asm/mach/pci.h> | ||
31 | #include <asm/hardware/it8152.h> | ||
32 | |||
33 | #define MAX_SLOTS 21 | ||
34 | |||
35 | static void it8152_mask_irq(unsigned int irq) | ||
36 | { | ||
37 | if (irq >= IT8152_LD_IRQ(0)) { | ||
38 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | | ||
39 | (1 << (irq - IT8152_LD_IRQ(0)))), | ||
40 | IT8152_INTC_LDCNIMR); | ||
41 | } else if (irq >= IT8152_LP_IRQ(0)) { | ||
42 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | | ||
43 | (1 << (irq - IT8152_LP_IRQ(0)))), | ||
44 | IT8152_INTC_LPCNIMR); | ||
45 | } else if (irq >= IT8152_PD_IRQ(0)) { | ||
46 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | | ||
47 | (1 << (irq - IT8152_PD_IRQ(0)))), | ||
48 | IT8152_INTC_PDCNIMR); | ||
49 | } | ||
50 | } | ||
51 | |||
52 | static void it8152_unmask_irq(unsigned int irq) | ||
53 | { | ||
54 | if (irq >= IT8152_LD_IRQ(0)) { | ||
55 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & | ||
56 | ~(1 << (irq - IT8152_LD_IRQ(0)))), | ||
57 | IT8152_INTC_LDCNIMR); | ||
58 | } else if (irq >= IT8152_LP_IRQ(0)) { | ||
59 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & | ||
60 | ~(1 << (irq - IT8152_LP_IRQ(0)))), | ||
61 | IT8152_INTC_LPCNIMR); | ||
62 | } else if (irq >= IT8152_PD_IRQ(0)) { | ||
63 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & | ||
64 | ~(1 << (irq - IT8152_PD_IRQ(0)))), | ||
65 | IT8152_INTC_PDCNIMR); | ||
66 | } | ||
67 | } | ||
68 | |||
69 | static inline void it8152_irq(int irq) | ||
70 | { | ||
71 | struct irq_desc *desc; | ||
72 | |||
73 | printk(KERN_DEBUG "===> %s: irq=%d\n", __FUNCTION__, irq); | ||
74 | |||
75 | desc = irq_desc + irq; | ||
76 | desc_handle_irq(irq, desc); | ||
77 | } | ||
78 | |||
79 | static struct irq_chip it8152_irq_chip = { | ||
80 | .name = "it8152", | ||
81 | .ack = it8152_mask_irq, | ||
82 | .mask = it8152_mask_irq, | ||
83 | .unmask = it8152_unmask_irq, | ||
84 | }; | ||
85 | |||
86 | void it8152_init_irq(void) | ||
87 | { | ||
88 | int irq; | ||
89 | |||
90 | __raw_writel((0xffff), IT8152_INTC_PDCNIMR); | ||
91 | __raw_writel((0), IT8152_INTC_PDCNIRR); | ||
92 | __raw_writel((0xffff), IT8152_INTC_LPCNIMR); | ||
93 | __raw_writel((0), IT8152_INTC_LPCNIRR); | ||
94 | __raw_writel((0xffff), IT8152_INTC_LDCNIMR); | ||
95 | __raw_writel((0), IT8152_INTC_LDCNIRR); | ||
96 | |||
97 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { | ||
98 | set_irq_chip(irq, &it8152_irq_chip); | ||
99 | set_irq_handler(irq, handle_level_irq); | ||
100 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
101 | } | ||
102 | } | ||
103 | |||
104 | void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) | ||
105 | { | ||
106 | int bits_pd, bits_lp, bits_ld; | ||
107 | int i; | ||
108 | |||
109 | printk(KERN_DEBUG "=> %s: irq = %d\n", __FUNCTION__, irq); | ||
110 | |||
111 | while (1) { | ||
112 | /* Read all */ | ||
113 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); | ||
114 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); | ||
115 | bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); | ||
116 | |||
117 | /* Ack */ | ||
118 | __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR); | ||
119 | __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR); | ||
120 | __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR); | ||
121 | |||
122 | if (!(bits_ld | bits_lp | bits_pd)) { | ||
123 | /* Re-read to guarantee, that there was a moment of | ||
124 | time, when they all three were 0. */ | ||
125 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); | ||
126 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); | ||
127 | if (!(bits_ld | bits_lp | bits_pd)) | ||
128 | return; | ||
129 | } | ||
130 | |||
131 | bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1); | ||
132 | while (bits_pd) { | ||
133 | i = __ffs(bits_pd); | ||
134 | it8152_irq(IT8152_PD_IRQ(i)); | ||
135 | bits_pd &= ~(1 << i); | ||
136 | } | ||
137 | |||
138 | bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); | ||
139 | while (bits_lp) { | ||
140 | i = __ffs(bits_pd); | ||
141 | it8152_irq(IT8152_LP_IRQ(i)); | ||
142 | bits_lp &= ~(1 << i); | ||
143 | } | ||
144 | |||
145 | bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); | ||
146 | while (bits_ld) { | ||
147 | i = __ffs(bits_pd); | ||
148 | it8152_irq(IT8152_LD_IRQ(i)); | ||
149 | bits_ld &= ~(1 << i); | ||
150 | } | ||
151 | } | ||
152 | } | ||
153 | |||
154 | /* mapping for on-chip devices */ | ||
155 | int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
156 | { | ||
157 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && | ||
158 | (dev->device == PCI_DEVICE_ID_ITE_8152)) { | ||
159 | if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO) | ||
160 | return IT8152_AUDIO_INT; | ||
161 | if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB) | ||
162 | return IT8152_USB_INT; | ||
163 | if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA) | ||
164 | return IT8152_CDMA_INT; | ||
165 | } | ||
166 | |||
167 | return 0; | ||
168 | } | ||
169 | |||
170 | static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus, | ||
171 | unsigned int devfn) | ||
172 | { | ||
173 | unsigned long addr = 0; | ||
174 | |||
175 | if (bus->number == 0) { | ||
176 | if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) | ||
177 | addr = (devfn << 8); | ||
178 | } else | ||
179 | addr = (bus->number << 16) | (devfn << 8); | ||
180 | |||
181 | return addr; | ||
182 | } | ||
183 | |||
184 | static int it8152_pci_read_config(struct pci_bus *bus, | ||
185 | unsigned int devfn, int where, | ||
186 | int size, u32 *value) | ||
187 | { | ||
188 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); | ||
189 | u32 v; | ||
190 | int shift; | ||
191 | |||
192 | shift = (where & 3); | ||
193 | |||
194 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | ||
195 | v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift))); | ||
196 | |||
197 | *value = v; | ||
198 | |||
199 | return PCIBIOS_SUCCESSFUL; | ||
200 | } | ||
201 | |||
202 | static int it8152_pci_write_config(struct pci_bus *bus, | ||
203 | unsigned int devfn, int where, | ||
204 | int size, u32 value) | ||
205 | { | ||
206 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); | ||
207 | u32 v, vtemp, mask = 0; | ||
208 | int shift; | ||
209 | |||
210 | if (size == 1) | ||
211 | mask = 0xff; | ||
212 | if (size == 2) | ||
213 | mask = 0xffff; | ||
214 | |||
215 | shift = (where & 3); | ||
216 | |||
217 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | ||
218 | vtemp = __raw_readl(IT8152_PCI_CFG_DATA); | ||
219 | |||
220 | if (mask) | ||
221 | vtemp &= ~(mask << (8 * shift)); | ||
222 | else | ||
223 | vtemp = 0; | ||
224 | |||
225 | v = (value << (8 * shift)); | ||
226 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); | ||
227 | __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA); | ||
228 | |||
229 | return PCIBIOS_SUCCESSFUL; | ||
230 | } | ||
231 | |||
232 | static struct pci_ops it8152_ops = { | ||
233 | .read = it8152_pci_read_config, | ||
234 | .write = it8152_pci_write_config, | ||
235 | }; | ||
236 | |||
237 | static struct resource it8152_io = { | ||
238 | .name = "IT8152 PCI I/O region", | ||
239 | .flags = IORESOURCE_IO, | ||
240 | }; | ||
241 | |||
242 | static struct resource it8152_mem = { | ||
243 | .name = "IT8152 PCI memory region", | ||
244 | .start = 0x10000000, | ||
245 | .end = 0x13e00000, | ||
246 | .flags = IORESOURCE_MEM, | ||
247 | }; | ||
248 | |||
249 | /* | ||
250 | * The following functions are needed for DMA bouncing. | ||
251 | * ITE8152 chip can addrees up to 64MByte, so all the devices | ||
252 | * connected to ITE8152 (PCI and USB) should have limited DMA window | ||
253 | */ | ||
254 | |||
255 | /* | ||
256 | * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all | ||
257 | * other devices. | ||
258 | */ | ||
259 | static int it8152_pci_platform_notify(struct device *dev) | ||
260 | { | ||
261 | if (dev->bus == &pci_bus_type) { | ||
262 | if (dev->dma_mask) | ||
263 | *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET; | ||
264 | dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET; | ||
265 | dmabounce_register_dev(dev, 2048, 4096); | ||
266 | } | ||
267 | return 0; | ||
268 | } | ||
269 | |||
270 | static int it8152_pci_platform_notify_remove(struct device *dev) | ||
271 | { | ||
272 | if (dev->bus == &pci_bus_type) | ||
273 | dmabounce_unregister_dev(dev); | ||
274 | |||
275 | return 0; | ||
276 | } | ||
277 | |||
278 | int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) | ||
279 | { | ||
280 | dev_dbg(dev, "%s: dma_addr %08x, size %08x\n", | ||
281 | __FUNCTION__, dma_addr, size); | ||
282 | return (dev->bus == &pci_bus_type) && | ||
283 | ((dma_addr + size - PHYS_OFFSET) >= SZ_64M); | ||
284 | } | ||
285 | |||
286 | /* | ||
287 | * We override these so we properly do dmabounce otherwise drivers | ||
288 | * are able to set the dma_mask to 0xffffffff and we can no longer | ||
289 | * trap bounces. :( | ||
290 | * | ||
291 | * We just return true on everyhing except for < 64MB in which case | ||
292 | * we will fail miseralby and die since we can't handle that case. | ||
293 | */ | ||
294 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | ||
295 | { | ||
296 | printk(KERN_DEBUG "%s: %s %llx\n", | ||
297 | __FUNCTION__, dev->dev.bus_id, mask); | ||
298 | if (mask >= PHYS_OFFSET + SZ_64M - 1) | ||
299 | return 0; | ||
300 | |||
301 | return -EIO; | ||
302 | } | ||
303 | |||
304 | int | ||
305 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | ||
306 | { | ||
307 | printk(KERN_DEBUG "%s: %s %llx\n", | ||
308 | __FUNCTION__, dev->dev.bus_id, mask); | ||
309 | if (mask >= PHYS_OFFSET + SZ_64M - 1) | ||
310 | return 0; | ||
311 | |||
312 | return -EIO; | ||
313 | } | ||
314 | |||
315 | int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) | ||
316 | { | ||
317 | it8152_io.start = IT8152_IO_BASE + 0x12000; | ||
318 | it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000; | ||
319 | |||
320 | sys->mem_offset = 0x10000000; | ||
321 | sys->io_offset = IT8152_IO_BASE; | ||
322 | |||
323 | if (request_resource(&ioport_resource, &it8152_io)) { | ||
324 | printk(KERN_ERR "PCI: unable to allocate IO region\n"); | ||
325 | goto err0; | ||
326 | } | ||
327 | if (request_resource(&iomem_resource, &it8152_mem)) { | ||
328 | printk(KERN_ERR "PCI: unable to allocate memory region\n"); | ||
329 | goto err1; | ||
330 | } | ||
331 | |||
332 | sys->resource[0] = &it8152_io; | ||
333 | sys->resource[1] = &it8152_mem; | ||
334 | |||
335 | if (platform_notify || platform_notify_remove) { | ||
336 | printk(KERN_ERR "PCI: Can't use platform_notify\n"); | ||
337 | goto err2; | ||
338 | } | ||
339 | |||
340 | platform_notify = it8152_pci_platform_notify; | ||
341 | platform_notify_remove = it8152_pci_platform_notify_remove; | ||
342 | |||
343 | return 1; | ||
344 | |||
345 | err2: | ||
346 | release_resource(&it8152_io); | ||
347 | err1: | ||
348 | release_resource(&it8152_mem); | ||
349 | err0: | ||
350 | return -EBUSY; | ||
351 | } | ||
352 | |||
353 | /* | ||
354 | * If we set up a device for bus mastering, we need to check the latency | ||
355 | * timer as we don't have even crappy BIOSes to set it properly. | ||
356 | * The implementation is from arch/i386/pci/i386.c | ||
357 | */ | ||
358 | unsigned int pcibios_max_latency = 255; | ||
359 | |||
360 | void pcibios_set_master(struct pci_dev *dev) | ||
361 | { | ||
362 | u8 lat; | ||
363 | |||
364 | /* no need to update on-chip OHCI controller */ | ||
365 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && | ||
366 | (dev->device == PCI_DEVICE_ID_ITE_8152) && | ||
367 | ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)) | ||
368 | return; | ||
369 | |||
370 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); | ||
371 | if (lat < 16) | ||
372 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | ||
373 | else if (lat > pcibios_max_latency) | ||
374 | lat = pcibios_max_latency; | ||
375 | else | ||
376 | return; | ||
377 | printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", | ||
378 | pci_name(dev), lat); | ||
379 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | ||
380 | } | ||
381 | |||
382 | |||
383 | struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) | ||
384 | { | ||
385 | return pci_scan_bus(nr, &it8152_ops, sys); | ||
386 | } | ||
387 | |||
diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/cm_x270_defconfig new file mode 100644 index 000000000000..5cab08397ae7 --- /dev/null +++ b/arch/arm/configs/cm_x270_defconfig | |||
@@ -0,0 +1,1410 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.22 | ||
4 | # Wed Jul 18 14:11:48 2007 | ||
5 | # | ||
6 | CONFIG_ARM=y | ||
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
8 | CONFIG_GENERIC_GPIO=y | ||
9 | CONFIG_GENERIC_TIME=y | ||
10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
11 | CONFIG_MMU=y | ||
12 | # CONFIG_NO_IOPORT is not set | ||
13 | CONFIG_GENERIC_HARDIRQS=y | ||
14 | CONFIG_STACKTRACE_SUPPORT=y | ||
15 | CONFIG_LOCKDEP_SUPPORT=y | ||
16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
20 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
22 | CONFIG_GENERIC_HWEIGHT=y | ||
23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
24 | CONFIG_ZONE_DMA=y | ||
25 | CONFIG_ARCH_MTD_XIP=y | ||
26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
28 | |||
29 | # | ||
30 | # Code maturity level options | ||
31 | # | ||
32 | CONFIG_EXPERIMENTAL=y | ||
33 | CONFIG_BROKEN_ON_SMP=y | ||
34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
35 | |||
36 | # | ||
37 | # General setup | ||
38 | # | ||
39 | CONFIG_LOCALVERSION="" | ||
40 | # CONFIG_LOCALVERSION_AUTO is not set | ||
41 | CONFIG_SWAP=y | ||
42 | CONFIG_SYSVIPC=y | ||
43 | CONFIG_SYSVIPC_SYSCTL=y | ||
44 | # CONFIG_POSIX_MQUEUE is not set | ||
45 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
46 | # CONFIG_TASKSTATS is not set | ||
47 | # CONFIG_USER_NS is not set | ||
48 | # CONFIG_AUDIT is not set | ||
49 | CONFIG_IKCONFIG=y | ||
50 | CONFIG_IKCONFIG_PROC=y | ||
51 | CONFIG_LOG_BUF_SHIFT=17 | ||
52 | CONFIG_SYSFS_DEPRECATED=y | ||
53 | # CONFIG_RELAY is not set | ||
54 | CONFIG_BLK_DEV_INITRD=y | ||
55 | CONFIG_INITRAMFS_SOURCE="" | ||
56 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
57 | CONFIG_SYSCTL=y | ||
58 | CONFIG_EMBEDDED=y | ||
59 | CONFIG_UID16=y | ||
60 | CONFIG_SYSCTL_SYSCALL=y | ||
61 | CONFIG_KALLSYMS=y | ||
62 | # CONFIG_KALLSYMS_ALL is not set | ||
63 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
64 | CONFIG_HOTPLUG=y | ||
65 | CONFIG_PRINTK=y | ||
66 | CONFIG_BUG=y | ||
67 | CONFIG_ELF_CORE=y | ||
68 | CONFIG_BASE_FULL=y | ||
69 | CONFIG_FUTEX=y | ||
70 | CONFIG_ANON_INODES=y | ||
71 | # CONFIG_EPOLL is not set | ||
72 | # CONFIG_SIGNALFD is not set | ||
73 | # CONFIG_TIMERFD is not set | ||
74 | # CONFIG_EVENTFD is not set | ||
75 | CONFIG_SHMEM=y | ||
76 | CONFIG_VM_EVENT_COUNTERS=y | ||
77 | CONFIG_SLAB=y | ||
78 | # CONFIG_SLUB is not set | ||
79 | # CONFIG_SLOB is not set | ||
80 | CONFIG_RT_MUTEXES=y | ||
81 | # CONFIG_TINY_SHMEM is not set | ||
82 | CONFIG_BASE_SMALL=0 | ||
83 | CONFIG_MODULES=y | ||
84 | CONFIG_MODULE_UNLOAD=y | ||
85 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
86 | # CONFIG_MODVERSIONS is not set | ||
87 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
88 | CONFIG_KMOD=y | ||
89 | CONFIG_BLOCK=y | ||
90 | # CONFIG_LBD is not set | ||
91 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
92 | # CONFIG_LSF is not set | ||
93 | # CONFIG_BLK_DEV_BSG is not set | ||
94 | |||
95 | # | ||
96 | # IO Schedulers | ||
97 | # | ||
98 | CONFIG_IOSCHED_NOOP=y | ||
99 | CONFIG_IOSCHED_AS=y | ||
100 | CONFIG_IOSCHED_DEADLINE=y | ||
101 | CONFIG_IOSCHED_CFQ=y | ||
102 | CONFIG_DEFAULT_AS=y | ||
103 | # CONFIG_DEFAULT_DEADLINE is not set | ||
104 | # CONFIG_DEFAULT_CFQ is not set | ||
105 | # CONFIG_DEFAULT_NOOP is not set | ||
106 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
107 | |||
108 | # | ||
109 | # System Type | ||
110 | # | ||
111 | # CONFIG_ARCH_AAEC2000 is not set | ||
112 | # CONFIG_ARCH_INTEGRATOR is not set | ||
113 | # CONFIG_ARCH_REALVIEW is not set | ||
114 | # CONFIG_ARCH_VERSATILE is not set | ||
115 | # CONFIG_ARCH_AT91 is not set | ||
116 | # CONFIG_ARCH_CLPS7500 is not set | ||
117 | # CONFIG_ARCH_CLPS711X is not set | ||
118 | # CONFIG_ARCH_CO285 is not set | ||
119 | # CONFIG_ARCH_EBSA110 is not set | ||
120 | # CONFIG_ARCH_EP93XX is not set | ||
121 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
122 | # CONFIG_ARCH_NETX is not set | ||
123 | # CONFIG_ARCH_H720X is not set | ||
124 | # CONFIG_ARCH_IMX is not set | ||
125 | # CONFIG_ARCH_IOP13XX is not set | ||
126 | # CONFIG_ARCH_IOP32X is not set | ||
127 | # CONFIG_ARCH_IOP33X is not set | ||
128 | # CONFIG_ARCH_IXP23XX is not set | ||
129 | # CONFIG_ARCH_IXP2000 is not set | ||
130 | # CONFIG_ARCH_IXP4XX is not set | ||
131 | # CONFIG_ARCH_L7200 is not set | ||
132 | # CONFIG_ARCH_KS8695 is not set | ||
133 | # CONFIG_ARCH_NS9XXX is not set | ||
134 | # CONFIG_ARCH_PNX4008 is not set | ||
135 | CONFIG_ARCH_PXA=y | ||
136 | # CONFIG_ARCH_RPC is not set | ||
137 | # CONFIG_ARCH_SA1100 is not set | ||
138 | # CONFIG_ARCH_S3C2410 is not set | ||
139 | # CONFIG_ARCH_SHARK is not set | ||
140 | # CONFIG_ARCH_LH7A40X is not set | ||
141 | # CONFIG_ARCH_DAVINCI is not set | ||
142 | # CONFIG_ARCH_OMAP is not set | ||
143 | CONFIG_DMABOUNCE=y | ||
144 | |||
145 | # | ||
146 | # Intel PXA2xx Implementations | ||
147 | # | ||
148 | # CONFIG_ARCH_LUBBOCK is not set | ||
149 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
150 | # CONFIG_MACH_MAINSTONE is not set | ||
151 | # CONFIG_ARCH_PXA_IDP is not set | ||
152 | # CONFIG_PXA_SHARPSL is not set | ||
153 | # CONFIG_MACH_TRIZEPS4 is not set | ||
154 | CONFIG_MACH_ARMCORE=y | ||
155 | CONFIG_PXA27x=y | ||
156 | |||
157 | # | ||
158 | # Processor Type | ||
159 | # | ||
160 | CONFIG_CPU_32=y | ||
161 | CONFIG_CPU_XSCALE=y | ||
162 | CONFIG_CPU_32v5=y | ||
163 | CONFIG_CPU_ABRT_EV5T=y | ||
164 | CONFIG_CPU_CACHE_VIVT=y | ||
165 | CONFIG_CPU_TLB_V4WBI=y | ||
166 | CONFIG_CPU_CP15=y | ||
167 | CONFIG_CPU_CP15_MMU=y | ||
168 | |||
169 | # | ||
170 | # Processor Features | ||
171 | # | ||
172 | CONFIG_ARM_THUMB=y | ||
173 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
174 | # CONFIG_OUTER_CACHE is not set | ||
175 | CONFIG_IWMMXT=y | ||
176 | CONFIG_XSCALE_PMU=y | ||
177 | |||
178 | # | ||
179 | # Bus support | ||
180 | # | ||
181 | CONFIG_PCI=y | ||
182 | CONFIG_PCI_SYSCALL=y | ||
183 | CONFIG_PCI_HOST_ITE8152=y | ||
184 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
185 | # CONFIG_PCI_DEBUG is not set | ||
186 | |||
187 | # | ||
188 | # PCCARD (PCMCIA/CardBus) support | ||
189 | # | ||
190 | # CONFIG_PCCARD is not set | ||
191 | |||
192 | # | ||
193 | # Kernel Features | ||
194 | # | ||
195 | # CONFIG_TICK_ONESHOT is not set | ||
196 | # CONFIG_PREEMPT is not set | ||
197 | # CONFIG_NO_IDLE_HZ is not set | ||
198 | CONFIG_HZ=100 | ||
199 | # CONFIG_AEABI is not set | ||
200 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
201 | CONFIG_SELECT_MEMORY_MODEL=y | ||
202 | CONFIG_FLATMEM_MANUAL=y | ||
203 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
204 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
205 | CONFIG_FLATMEM=y | ||
206 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
207 | # CONFIG_SPARSEMEM_STATIC is not set | ||
208 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
209 | # CONFIG_RESOURCES_64BIT is not set | ||
210 | CONFIG_ZONE_DMA_FLAG=1 | ||
211 | CONFIG_BOUNCE=y | ||
212 | CONFIG_VIRT_TO_BUS=y | ||
213 | CONFIG_ALIGNMENT_TRAP=y | ||
214 | |||
215 | # | ||
216 | # Boot options | ||
217 | # | ||
218 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
219 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
220 | CONFIG_CMDLINE="" | ||
221 | # CONFIG_XIP_KERNEL is not set | ||
222 | # CONFIG_KEXEC is not set | ||
223 | |||
224 | # | ||
225 | # Floating point emulation | ||
226 | # | ||
227 | |||
228 | # | ||
229 | # At least one emulation must be selected | ||
230 | # | ||
231 | CONFIG_FPE_NWFPE=y | ||
232 | # CONFIG_FPE_NWFPE_XP is not set | ||
233 | # CONFIG_FPE_FASTFPE is not set | ||
234 | |||
235 | # | ||
236 | # Userspace binary formats | ||
237 | # | ||
238 | CONFIG_BINFMT_ELF=y | ||
239 | # CONFIG_BINFMT_AOUT is not set | ||
240 | # CONFIG_BINFMT_MISC is not set | ||
241 | # CONFIG_ARTHUR is not set | ||
242 | |||
243 | # | ||
244 | # Power management options | ||
245 | # | ||
246 | CONFIG_PM=y | ||
247 | # CONFIG_PM_LEGACY is not set | ||
248 | # CONFIG_PM_DEBUG is not set | ||
249 | # CONFIG_PM_SYSFS_DEPRECATED is not set | ||
250 | # CONFIG_APM_EMULATION is not set | ||
251 | |||
252 | # | ||
253 | # Networking | ||
254 | # | ||
255 | CONFIG_NET=y | ||
256 | |||
257 | # | ||
258 | # Networking options | ||
259 | # | ||
260 | CONFIG_PACKET=y | ||
261 | # CONFIG_PACKET_MMAP is not set | ||
262 | CONFIG_UNIX=y | ||
263 | CONFIG_XFRM=y | ||
264 | # CONFIG_XFRM_USER is not set | ||
265 | # CONFIG_XFRM_SUB_POLICY is not set | ||
266 | # CONFIG_XFRM_MIGRATE is not set | ||
267 | # CONFIG_NET_KEY is not set | ||
268 | CONFIG_INET=y | ||
269 | # CONFIG_IP_MULTICAST is not set | ||
270 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
271 | CONFIG_IP_FIB_HASH=y | ||
272 | CONFIG_IP_PNP=y | ||
273 | CONFIG_IP_PNP_DHCP=y | ||
274 | CONFIG_IP_PNP_BOOTP=y | ||
275 | # CONFIG_IP_PNP_RARP is not set | ||
276 | # CONFIG_NET_IPIP is not set | ||
277 | # CONFIG_NET_IPGRE is not set | ||
278 | # CONFIG_ARPD is not set | ||
279 | # CONFIG_SYN_COOKIES is not set | ||
280 | # CONFIG_INET_AH is not set | ||
281 | # CONFIG_INET_ESP is not set | ||
282 | # CONFIG_INET_IPCOMP is not set | ||
283 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
284 | # CONFIG_INET_TUNNEL is not set | ||
285 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
286 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
287 | CONFIG_INET_XFRM_MODE_BEET=y | ||
288 | CONFIG_INET_DIAG=y | ||
289 | CONFIG_INET_TCP_DIAG=y | ||
290 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
291 | CONFIG_TCP_CONG_CUBIC=y | ||
292 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
293 | # CONFIG_TCP_MD5SIG is not set | ||
294 | # CONFIG_IPV6 is not set | ||
295 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
296 | # CONFIG_INET6_TUNNEL is not set | ||
297 | # CONFIG_NETWORK_SECMARK is not set | ||
298 | # CONFIG_NETFILTER is not set | ||
299 | # CONFIG_IP_DCCP is not set | ||
300 | # CONFIG_IP_SCTP is not set | ||
301 | # CONFIG_TIPC is not set | ||
302 | # CONFIG_ATM is not set | ||
303 | # CONFIG_BRIDGE is not set | ||
304 | # CONFIG_VLAN_8021Q is not set | ||
305 | # CONFIG_DECNET is not set | ||
306 | # CONFIG_LLC2 is not set | ||
307 | # CONFIG_IPX is not set | ||
308 | # CONFIG_ATALK is not set | ||
309 | # CONFIG_X25 is not set | ||
310 | # CONFIG_LAPB is not set | ||
311 | # CONFIG_ECONET is not set | ||
312 | # CONFIG_WAN_ROUTER is not set | ||
313 | |||
314 | # | ||
315 | # QoS and/or fair queueing | ||
316 | # | ||
317 | # CONFIG_NET_SCHED is not set | ||
318 | |||
319 | # | ||
320 | # Network testing | ||
321 | # | ||
322 | # CONFIG_NET_PKTGEN is not set | ||
323 | # CONFIG_HAMRADIO is not set | ||
324 | # CONFIG_IRDA is not set | ||
325 | # CONFIG_BT is not set | ||
326 | # CONFIG_AF_RXRPC is not set | ||
327 | |||
328 | # | ||
329 | # Wireless | ||
330 | # | ||
331 | # CONFIG_CFG80211 is not set | ||
332 | CONFIG_WIRELESS_EXT=y | ||
333 | # CONFIG_MAC80211 is not set | ||
334 | CONFIG_IEEE80211=m | ||
335 | # CONFIG_IEEE80211_DEBUG is not set | ||
336 | CONFIG_IEEE80211_CRYPT_WEP=m | ||
337 | CONFIG_IEEE80211_CRYPT_CCMP=m | ||
338 | # CONFIG_IEEE80211_CRYPT_TKIP is not set | ||
339 | # CONFIG_IEEE80211_SOFTMAC is not set | ||
340 | # CONFIG_RFKILL is not set | ||
341 | # CONFIG_NET_9P is not set | ||
342 | |||
343 | # | ||
344 | # Device Drivers | ||
345 | # | ||
346 | |||
347 | # | ||
348 | # Generic Driver Options | ||
349 | # | ||
350 | CONFIG_STANDALONE=y | ||
351 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
352 | CONFIG_FW_LOADER=y | ||
353 | # CONFIG_DEBUG_DRIVER is not set | ||
354 | # CONFIG_DEBUG_DEVRES is not set | ||
355 | # CONFIG_SYS_HYPERVISOR is not set | ||
356 | # CONFIG_CONNECTOR is not set | ||
357 | CONFIG_MTD=m | ||
358 | # CONFIG_MTD_DEBUG is not set | ||
359 | # CONFIG_MTD_CONCAT is not set | ||
360 | CONFIG_MTD_PARTITIONS=y | ||
361 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
362 | # CONFIG_MTD_AFS_PARTS is not set | ||
363 | |||
364 | # | ||
365 | # User Modules And Translation Layers | ||
366 | # | ||
367 | CONFIG_MTD_CHAR=m | ||
368 | CONFIG_MTD_BLKDEVS=m | ||
369 | CONFIG_MTD_BLOCK=m | ||
370 | # CONFIG_MTD_BLOCK_RO is not set | ||
371 | # CONFIG_FTL is not set | ||
372 | # CONFIG_NFTL is not set | ||
373 | # CONFIG_INFTL is not set | ||
374 | # CONFIG_RFD_FTL is not set | ||
375 | # CONFIG_SSFDC is not set | ||
376 | |||
377 | # | ||
378 | # RAM/ROM/Flash chip drivers | ||
379 | # | ||
380 | # CONFIG_MTD_CFI is not set | ||
381 | # CONFIG_MTD_JEDECPROBE is not set | ||
382 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
383 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
384 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
385 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
386 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
387 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
388 | CONFIG_MTD_CFI_I1=y | ||
389 | CONFIG_MTD_CFI_I2=y | ||
390 | # CONFIG_MTD_CFI_I4 is not set | ||
391 | # CONFIG_MTD_CFI_I8 is not set | ||
392 | # CONFIG_MTD_RAM is not set | ||
393 | # CONFIG_MTD_ROM is not set | ||
394 | # CONFIG_MTD_ABSENT is not set | ||
395 | |||
396 | # | ||
397 | # Mapping drivers for chip access | ||
398 | # | ||
399 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
400 | # CONFIG_MTD_SHARP_SL is not set | ||
401 | # CONFIG_MTD_PLATRAM is not set | ||
402 | |||
403 | # | ||
404 | # Self-contained MTD device drivers | ||
405 | # | ||
406 | # CONFIG_MTD_PMC551 is not set | ||
407 | # CONFIG_MTD_SLRAM is not set | ||
408 | # CONFIG_MTD_PHRAM is not set | ||
409 | # CONFIG_MTD_MTDRAM is not set | ||
410 | # CONFIG_MTD_BLOCK2MTD is not set | ||
411 | |||
412 | # | ||
413 | # Disk-On-Chip Device Drivers | ||
414 | # | ||
415 | # CONFIG_MTD_DOC2000 is not set | ||
416 | # CONFIG_MTD_DOC2001 is not set | ||
417 | # CONFIG_MTD_DOC2001PLUS is not set | ||
418 | CONFIG_MTD_NAND=m | ||
419 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
420 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
421 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
422 | # CONFIG_MTD_NAND_H1900 is not set | ||
423 | CONFIG_MTD_NAND_IDS=m | ||
424 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
425 | # CONFIG_MTD_NAND_SHARPSL is not set | ||
426 | # CONFIG_MTD_NAND_CAFE is not set | ||
427 | CONFIG_MTD_NAND_CM_X270=m | ||
428 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
429 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
430 | # CONFIG_MTD_ONENAND is not set | ||
431 | |||
432 | # | ||
433 | # UBI - Unsorted block images | ||
434 | # | ||
435 | # CONFIG_MTD_UBI is not set | ||
436 | # CONFIG_PARPORT is not set | ||
437 | CONFIG_BLK_DEV=y | ||
438 | # CONFIG_BLK_CPQ_DA is not set | ||
439 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
440 | # CONFIG_BLK_DEV_DAC960 is not set | ||
441 | # CONFIG_BLK_DEV_UMEM is not set | ||
442 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
443 | CONFIG_BLK_DEV_LOOP=y | ||
444 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
445 | # CONFIG_BLK_DEV_NBD is not set | ||
446 | # CONFIG_BLK_DEV_SX8 is not set | ||
447 | # CONFIG_BLK_DEV_UB is not set | ||
448 | CONFIG_BLK_DEV_RAM=y | ||
449 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
450 | CONFIG_BLK_DEV_RAM_SIZE=12000 | ||
451 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | ||
452 | # CONFIG_CDROM_PKTCDVD is not set | ||
453 | # CONFIG_ATA_OVER_ETH is not set | ||
454 | CONFIG_IDE=m | ||
455 | CONFIG_IDE_MAX_HWIFS=4 | ||
456 | CONFIG_BLK_DEV_IDE=m | ||
457 | |||
458 | # | ||
459 | # Please see Documentation/ide.txt for help/info on IDE drives | ||
460 | # | ||
461 | # CONFIG_BLK_DEV_IDE_SATA is not set | ||
462 | CONFIG_BLK_DEV_IDEDISK=m | ||
463 | # CONFIG_IDEDISK_MULTI_MODE is not set | ||
464 | CONFIG_BLK_DEV_IDECD=m | ||
465 | # CONFIG_BLK_DEV_IDETAPE is not set | ||
466 | # CONFIG_BLK_DEV_IDEFLOPPY is not set | ||
467 | # CONFIG_BLK_DEV_IDESCSI is not set | ||
468 | # CONFIG_IDE_TASK_IOCTL is not set | ||
469 | CONFIG_IDE_PROC_FS=y | ||
470 | |||
471 | # | ||
472 | # IDE chipset support/bugfixes | ||
473 | # | ||
474 | # CONFIG_IDE_GENERIC is not set | ||
475 | # CONFIG_BLK_DEV_IDEPCI is not set | ||
476 | # CONFIG_IDEPCI_PCIBUS_ORDER is not set | ||
477 | # CONFIG_IDE_ARM is not set | ||
478 | # CONFIG_BLK_DEV_IDEDMA is not set | ||
479 | # CONFIG_BLK_DEV_HD is not set | ||
480 | |||
481 | # | ||
482 | # SCSI device support | ||
483 | # | ||
484 | # CONFIG_RAID_ATTRS is not set | ||
485 | CONFIG_SCSI=y | ||
486 | CONFIG_SCSI_DMA=y | ||
487 | # CONFIG_SCSI_TGT is not set | ||
488 | # CONFIG_SCSI_NETLINK is not set | ||
489 | # CONFIG_SCSI_PROC_FS is not set | ||
490 | |||
491 | # | ||
492 | # SCSI support type (disk, tape, CD-ROM) | ||
493 | # | ||
494 | CONFIG_BLK_DEV_SD=y | ||
495 | # CONFIG_CHR_DEV_ST is not set | ||
496 | # CONFIG_CHR_DEV_OSST is not set | ||
497 | # CONFIG_BLK_DEV_SR is not set | ||
498 | # CONFIG_CHR_DEV_SG is not set | ||
499 | # CONFIG_CHR_DEV_SCH is not set | ||
500 | |||
501 | # | ||
502 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
503 | # | ||
504 | # CONFIG_SCSI_MULTI_LUN is not set | ||
505 | # CONFIG_SCSI_CONSTANTS is not set | ||
506 | # CONFIG_SCSI_LOGGING is not set | ||
507 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
508 | CONFIG_SCSI_WAIT_SCAN=m | ||
509 | |||
510 | # | ||
511 | # SCSI Transports | ||
512 | # | ||
513 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
514 | # CONFIG_SCSI_FC_ATTRS is not set | ||
515 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
516 | # CONFIG_SCSI_SAS_ATTRS is not set | ||
517 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
518 | |||
519 | # | ||
520 | # SCSI low-level drivers | ||
521 | # | ||
522 | # CONFIG_ISCSI_TCP is not set | ||
523 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | ||
524 | # CONFIG_SCSI_3W_9XXX is not set | ||
525 | # CONFIG_SCSI_ACARD is not set | ||
526 | # CONFIG_SCSI_AACRAID is not set | ||
527 | # CONFIG_SCSI_AIC7XXX is not set | ||
528 | # CONFIG_SCSI_AIC7XXX_OLD is not set | ||
529 | # CONFIG_SCSI_AIC79XX is not set | ||
530 | # CONFIG_SCSI_AIC94XX is not set | ||
531 | # CONFIG_SCSI_DPT_I2O is not set | ||
532 | # CONFIG_SCSI_ARCMSR is not set | ||
533 | # CONFIG_MEGARAID_NEWGEN is not set | ||
534 | # CONFIG_MEGARAID_LEGACY is not set | ||
535 | # CONFIG_MEGARAID_SAS is not set | ||
536 | # CONFIG_SCSI_HPTIOP is not set | ||
537 | # CONFIG_SCSI_DMX3191D is not set | ||
538 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | ||
539 | # CONFIG_SCSI_IPS is not set | ||
540 | # CONFIG_SCSI_INITIO is not set | ||
541 | # CONFIG_SCSI_INIA100 is not set | ||
542 | # CONFIG_SCSI_STEX is not set | ||
543 | # CONFIG_SCSI_SYM53C8XX_2 is not set | ||
544 | # CONFIG_SCSI_QLOGIC_1280 is not set | ||
545 | # CONFIG_SCSI_QLA_FC is not set | ||
546 | # CONFIG_SCSI_QLA_ISCSI is not set | ||
547 | # CONFIG_SCSI_LPFC is not set | ||
548 | # CONFIG_SCSI_DC395x is not set | ||
549 | # CONFIG_SCSI_DC390T is not set | ||
550 | # CONFIG_SCSI_NSP32 is not set | ||
551 | # CONFIG_SCSI_DEBUG is not set | ||
552 | # CONFIG_SCSI_SRP is not set | ||
553 | # CONFIG_ATA is not set | ||
554 | # CONFIG_MD is not set | ||
555 | |||
556 | # | ||
557 | # Fusion MPT device support | ||
558 | # | ||
559 | # CONFIG_FUSION is not set | ||
560 | # CONFIG_FUSION_SPI is not set | ||
561 | # CONFIG_FUSION_FC is not set | ||
562 | # CONFIG_FUSION_SAS is not set | ||
563 | |||
564 | # | ||
565 | # IEEE 1394 (FireWire) support | ||
566 | # | ||
567 | # CONFIG_FIREWIRE is not set | ||
568 | # CONFIG_IEEE1394 is not set | ||
569 | # CONFIG_I2O is not set | ||
570 | CONFIG_NETDEVICES=y | ||
571 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
572 | # CONFIG_DUMMY is not set | ||
573 | # CONFIG_BONDING is not set | ||
574 | # CONFIG_MACVLAN is not set | ||
575 | # CONFIG_EQUALIZER is not set | ||
576 | # CONFIG_TUN is not set | ||
577 | # CONFIG_ARCNET is not set | ||
578 | # CONFIG_PHYLIB is not set | ||
579 | CONFIG_NET_ETHERNET=y | ||
580 | CONFIG_MII=y | ||
581 | # CONFIG_AX88796 is not set | ||
582 | # CONFIG_HAPPYMEAL is not set | ||
583 | # CONFIG_SUNGEM is not set | ||
584 | # CONFIG_CASSINI is not set | ||
585 | # CONFIG_NET_VENDOR_3COM is not set | ||
586 | # CONFIG_SMC91X is not set | ||
587 | CONFIG_DM9000=y | ||
588 | # CONFIG_SMC911X is not set | ||
589 | # CONFIG_NET_TULIP is not set | ||
590 | # CONFIG_HP100 is not set | ||
591 | CONFIG_NET_PCI=y | ||
592 | # CONFIG_PCNET32 is not set | ||
593 | # CONFIG_AMD8111_ETH is not set | ||
594 | # CONFIG_ADAPTEC_STARFIRE is not set | ||
595 | # CONFIG_B44 is not set | ||
596 | # CONFIG_FORCEDETH is not set | ||
597 | # CONFIG_DGRS is not set | ||
598 | # CONFIG_EEPRO100 is not set | ||
599 | # CONFIG_E100 is not set | ||
600 | # CONFIG_FEALNX is not set | ||
601 | # CONFIG_NATSEMI is not set | ||
602 | # CONFIG_NE2K_PCI is not set | ||
603 | # CONFIG_8139CP is not set | ||
604 | CONFIG_8139TOO=m | ||
605 | # CONFIG_8139TOO_PIO is not set | ||
606 | # CONFIG_8139TOO_TUNE_TWISTER is not set | ||
607 | # CONFIG_8139TOO_8129 is not set | ||
608 | # CONFIG_8139_OLD_RX_RESET is not set | ||
609 | # CONFIG_SIS900 is not set | ||
610 | # CONFIG_EPIC100 is not set | ||
611 | # CONFIG_SUNDANCE is not set | ||
612 | # CONFIG_TLAN is not set | ||
613 | # CONFIG_VIA_RHINE is not set | ||
614 | # CONFIG_SC92031 is not set | ||
615 | CONFIG_NETDEV_1000=y | ||
616 | # CONFIG_ACENIC is not set | ||
617 | # CONFIG_DL2K is not set | ||
618 | # CONFIG_E1000 is not set | ||
619 | # CONFIG_NS83820 is not set | ||
620 | # CONFIG_HAMACHI is not set | ||
621 | # CONFIG_YELLOWFIN is not set | ||
622 | # CONFIG_R8169 is not set | ||
623 | # CONFIG_SIS190 is not set | ||
624 | # CONFIG_SKGE is not set | ||
625 | # CONFIG_SKY2 is not set | ||
626 | # CONFIG_VIA_VELOCITY is not set | ||
627 | # CONFIG_TIGON3 is not set | ||
628 | # CONFIG_BNX2 is not set | ||
629 | # CONFIG_QLA3XXX is not set | ||
630 | # CONFIG_ATL1 is not set | ||
631 | CONFIG_NETDEV_10000=y | ||
632 | # CONFIG_CHELSIO_T1 is not set | ||
633 | # CONFIG_CHELSIO_T3 is not set | ||
634 | # CONFIG_IXGB is not set | ||
635 | # CONFIG_S2IO is not set | ||
636 | # CONFIG_MYRI10GE is not set | ||
637 | # CONFIG_NETXEN_NIC is not set | ||
638 | # CONFIG_MLX4_CORE is not set | ||
639 | # CONFIG_TR is not set | ||
640 | |||
641 | # | ||
642 | # Wireless LAN | ||
643 | # | ||
644 | # CONFIG_WLAN_PRE80211 is not set | ||
645 | # CONFIG_WLAN_80211 is not set | ||
646 | |||
647 | # | ||
648 | # USB Network Adapters | ||
649 | # | ||
650 | # CONFIG_USB_CATC is not set | ||
651 | # CONFIG_USB_KAWETH is not set | ||
652 | # CONFIG_USB_PEGASUS is not set | ||
653 | # CONFIG_USB_RTL8150 is not set | ||
654 | # CONFIG_USB_USBNET_MII is not set | ||
655 | # CONFIG_USB_USBNET is not set | ||
656 | # CONFIG_WAN is not set | ||
657 | # CONFIG_FDDI is not set | ||
658 | # CONFIG_HIPPI is not set | ||
659 | # CONFIG_PPP is not set | ||
660 | # CONFIG_SLIP is not set | ||
661 | # CONFIG_NET_FC is not set | ||
662 | # CONFIG_SHAPER is not set | ||
663 | # CONFIG_NETCONSOLE is not set | ||
664 | # CONFIG_NETPOLL is not set | ||
665 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
666 | # CONFIG_ISDN is not set | ||
667 | |||
668 | # | ||
669 | # Input device support | ||
670 | # | ||
671 | CONFIG_INPUT=y | ||
672 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
673 | # CONFIG_INPUT_POLLDEV is not set | ||
674 | |||
675 | # | ||
676 | # Userland interfaces | ||
677 | # | ||
678 | # CONFIG_INPUT_MOUSEDEV is not set | ||
679 | # CONFIG_INPUT_JOYDEV is not set | ||
680 | # CONFIG_INPUT_TSDEV is not set | ||
681 | CONFIG_INPUT_EVDEV=y | ||
682 | # CONFIG_INPUT_EVBUG is not set | ||
683 | |||
684 | # | ||
685 | # Input Device Drivers | ||
686 | # | ||
687 | # CONFIG_INPUT_KEYBOARD is not set | ||
688 | # CONFIG_INPUT_MOUSE is not set | ||
689 | # CONFIG_INPUT_JOYSTICK is not set | ||
690 | # CONFIG_INPUT_TABLET is not set | ||
691 | CONFIG_INPUT_TOUCHSCREEN=y | ||
692 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
693 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
694 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
695 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
696 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
697 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
698 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
699 | CONFIG_TOUCHSCREEN_UCB1400=m | ||
700 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
701 | # CONFIG_INPUT_MISC is not set | ||
702 | |||
703 | # | ||
704 | # Hardware I/O ports | ||
705 | # | ||
706 | # CONFIG_SERIO is not set | ||
707 | # CONFIG_GAMEPORT is not set | ||
708 | |||
709 | # | ||
710 | # Character devices | ||
711 | # | ||
712 | CONFIG_VT=y | ||
713 | CONFIG_VT_CONSOLE=y | ||
714 | CONFIG_HW_CONSOLE=y | ||
715 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
716 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
717 | |||
718 | # | ||
719 | # Serial drivers | ||
720 | # | ||
721 | # CONFIG_SERIAL_8250 is not set | ||
722 | |||
723 | # | ||
724 | # Non-8250 serial port support | ||
725 | # | ||
726 | CONFIG_SERIAL_PXA=y | ||
727 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
728 | CONFIG_SERIAL_CORE=y | ||
729 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
730 | # CONFIG_SERIAL_JSM is not set | ||
731 | CONFIG_UNIX98_PTYS=y | ||
732 | CONFIG_LEGACY_PTYS=y | ||
733 | CONFIG_LEGACY_PTY_COUNT=256 | ||
734 | # CONFIG_IPMI_HANDLER is not set | ||
735 | # CONFIG_WATCHDOG is not set | ||
736 | CONFIG_HW_RANDOM=m | ||
737 | # CONFIG_NVRAM is not set | ||
738 | # CONFIG_R3964 is not set | ||
739 | # CONFIG_APPLICOM is not set | ||
740 | # CONFIG_DRM is not set | ||
741 | # CONFIG_RAW_DRIVER is not set | ||
742 | # CONFIG_TCG_TPM is not set | ||
743 | CONFIG_DEVPORT=y | ||
744 | # CONFIG_I2C is not set | ||
745 | |||
746 | # | ||
747 | # SPI support | ||
748 | # | ||
749 | # CONFIG_SPI is not set | ||
750 | # CONFIG_SPI_MASTER is not set | ||
751 | # CONFIG_W1 is not set | ||
752 | # CONFIG_HWMON is not set | ||
753 | CONFIG_MISC_DEVICES=y | ||
754 | # CONFIG_PHANTOM is not set | ||
755 | # CONFIG_EEPROM_93CX6 is not set | ||
756 | # CONFIG_SGI_IOC4 is not set | ||
757 | # CONFIG_TIFM_CORE is not set | ||
758 | |||
759 | # | ||
760 | # Multifunction device drivers | ||
761 | # | ||
762 | # CONFIG_MFD_SM501 is not set | ||
763 | |||
764 | # | ||
765 | # LED devices | ||
766 | # | ||
767 | CONFIG_NEW_LEDS=y | ||
768 | CONFIG_LEDS_CLASS=y | ||
769 | |||
770 | # | ||
771 | # LED drivers | ||
772 | # | ||
773 | CONFIG_LEDS_CM_X270=y | ||
774 | |||
775 | # | ||
776 | # LED Triggers | ||
777 | # | ||
778 | CONFIG_LEDS_TRIGGERS=y | ||
779 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
780 | # CONFIG_LEDS_TRIGGER_IDE_DISK is not set | ||
781 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
782 | |||
783 | # | ||
784 | # Multimedia devices | ||
785 | # | ||
786 | # CONFIG_VIDEO_DEV is not set | ||
787 | # CONFIG_DVB_CORE is not set | ||
788 | CONFIG_DAB=y | ||
789 | # CONFIG_USB_DABUSB is not set | ||
790 | |||
791 | # | ||
792 | # Graphics support | ||
793 | # | ||
794 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
795 | |||
796 | # | ||
797 | # Display device support | ||
798 | # | ||
799 | # CONFIG_DISPLAY_SUPPORT is not set | ||
800 | # CONFIG_VGASTATE is not set | ||
801 | CONFIG_FB=y | ||
802 | # CONFIG_FIRMWARE_EDID is not set | ||
803 | # CONFIG_FB_DDC is not set | ||
804 | CONFIG_FB_CFB_FILLRECT=y | ||
805 | CONFIG_FB_CFB_COPYAREA=y | ||
806 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
807 | # CONFIG_FB_SYS_FILLRECT is not set | ||
808 | # CONFIG_FB_SYS_COPYAREA is not set | ||
809 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
810 | # CONFIG_FB_SYS_FOPS is not set | ||
811 | CONFIG_FB_DEFERRED_IO=y | ||
812 | # CONFIG_FB_SVGALIB is not set | ||
813 | # CONFIG_FB_MACMODES is not set | ||
814 | # CONFIG_FB_BACKLIGHT is not set | ||
815 | # CONFIG_FB_MODE_HELPERS is not set | ||
816 | # CONFIG_FB_TILEBLITTING is not set | ||
817 | |||
818 | # | ||
819 | # Frame buffer hardware drivers | ||
820 | # | ||
821 | # CONFIG_FB_CIRRUS is not set | ||
822 | # CONFIG_FB_PM2 is not set | ||
823 | # CONFIG_FB_CYBER2000 is not set | ||
824 | # CONFIG_FB_ASILIANT is not set | ||
825 | # CONFIG_FB_IMSTT is not set | ||
826 | # CONFIG_FB_S1D13XXX is not set | ||
827 | # CONFIG_FB_NVIDIA is not set | ||
828 | # CONFIG_FB_RIVA is not set | ||
829 | # CONFIG_FB_MATROX is not set | ||
830 | # CONFIG_FB_RADEON is not set | ||
831 | # CONFIG_FB_ATY128 is not set | ||
832 | # CONFIG_FB_ATY is not set | ||
833 | # CONFIG_FB_S3 is not set | ||
834 | # CONFIG_FB_SAVAGE is not set | ||
835 | # CONFIG_FB_SIS is not set | ||
836 | # CONFIG_FB_NEOMAGIC is not set | ||
837 | # CONFIG_FB_KYRO is not set | ||
838 | # CONFIG_FB_3DFX is not set | ||
839 | # CONFIG_FB_VOODOO1 is not set | ||
840 | # CONFIG_FB_VT8623 is not set | ||
841 | # CONFIG_FB_TRIDENT is not set | ||
842 | # CONFIG_FB_ARK is not set | ||
843 | # CONFIG_FB_PM3 is not set | ||
844 | CONFIG_FB_PXA=y | ||
845 | # CONFIG_FB_PXA_PARAMETERS is not set | ||
846 | CONFIG_FB_MBX=m | ||
847 | # CONFIG_FB_VIRTUAL is not set | ||
848 | |||
849 | # | ||
850 | # Console display driver support | ||
851 | # | ||
852 | # CONFIG_VGA_CONSOLE is not set | ||
853 | CONFIG_DUMMY_CONSOLE=y | ||
854 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
855 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
856 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
857 | # CONFIG_FONTS is not set | ||
858 | CONFIG_FONT_8x8=y | ||
859 | CONFIG_FONT_8x16=y | ||
860 | CONFIG_LOGO=y | ||
861 | CONFIG_LOGO_LINUX_MONO=y | ||
862 | CONFIG_LOGO_LINUX_VGA16=y | ||
863 | CONFIG_LOGO_LINUX_CLUT224=y | ||
864 | |||
865 | # | ||
866 | # Sound | ||
867 | # | ||
868 | CONFIG_SOUND=m | ||
869 | |||
870 | # | ||
871 | # Advanced Linux Sound Architecture | ||
872 | # | ||
873 | CONFIG_SND=m | ||
874 | CONFIG_SND_TIMER=m | ||
875 | CONFIG_SND_PCM=m | ||
876 | # CONFIG_SND_SEQUENCER is not set | ||
877 | CONFIG_SND_OSSEMUL=y | ||
878 | CONFIG_SND_MIXER_OSS=m | ||
879 | CONFIG_SND_PCM_OSS=m | ||
880 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
881 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
882 | CONFIG_SND_SUPPORT_OLD_API=y | ||
883 | CONFIG_SND_VERBOSE_PROCFS=y | ||
884 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
885 | # CONFIG_SND_DEBUG is not set | ||
886 | |||
887 | # | ||
888 | # Generic devices | ||
889 | # | ||
890 | CONFIG_SND_AC97_CODEC=m | ||
891 | # CONFIG_SND_DUMMY is not set | ||
892 | # CONFIG_SND_MTPAV is not set | ||
893 | # CONFIG_SND_SERIAL_U16550 is not set | ||
894 | # CONFIG_SND_MPU401 is not set | ||
895 | |||
896 | # | ||
897 | # PCI devices | ||
898 | # | ||
899 | # CONFIG_SND_AD1889 is not set | ||
900 | # CONFIG_SND_ALS300 is not set | ||
901 | # CONFIG_SND_ALI5451 is not set | ||
902 | # CONFIG_SND_ATIIXP is not set | ||
903 | # CONFIG_SND_ATIIXP_MODEM is not set | ||
904 | # CONFIG_SND_AU8810 is not set | ||
905 | # CONFIG_SND_AU8820 is not set | ||
906 | # CONFIG_SND_AU8830 is not set | ||
907 | # CONFIG_SND_AZT3328 is not set | ||
908 | # CONFIG_SND_BT87X is not set | ||
909 | # CONFIG_SND_CA0106 is not set | ||
910 | # CONFIG_SND_CMIPCI is not set | ||
911 | # CONFIG_SND_CS4281 is not set | ||
912 | # CONFIG_SND_CS46XX is not set | ||
913 | # CONFIG_SND_DARLA20 is not set | ||
914 | # CONFIG_SND_GINA20 is not set | ||
915 | # CONFIG_SND_LAYLA20 is not set | ||
916 | # CONFIG_SND_DARLA24 is not set | ||
917 | # CONFIG_SND_GINA24 is not set | ||
918 | # CONFIG_SND_LAYLA24 is not set | ||
919 | # CONFIG_SND_MONA is not set | ||
920 | # CONFIG_SND_MIA is not set | ||
921 | # CONFIG_SND_ECHO3G is not set | ||
922 | # CONFIG_SND_INDIGO is not set | ||
923 | # CONFIG_SND_INDIGOIO is not set | ||
924 | # CONFIG_SND_INDIGODJ is not set | ||
925 | # CONFIG_SND_EMU10K1 is not set | ||
926 | # CONFIG_SND_EMU10K1X is not set | ||
927 | # CONFIG_SND_ENS1370 is not set | ||
928 | # CONFIG_SND_ENS1371 is not set | ||
929 | # CONFIG_SND_ES1938 is not set | ||
930 | # CONFIG_SND_ES1968 is not set | ||
931 | # CONFIG_SND_FM801 is not set | ||
932 | # CONFIG_SND_HDA_INTEL is not set | ||
933 | # CONFIG_SND_HDSP is not set | ||
934 | # CONFIG_SND_HDSPM is not set | ||
935 | # CONFIG_SND_ICE1712 is not set | ||
936 | # CONFIG_SND_ICE1724 is not set | ||
937 | # CONFIG_SND_INTEL8X0 is not set | ||
938 | # CONFIG_SND_INTEL8X0M is not set | ||
939 | # CONFIG_SND_KORG1212 is not set | ||
940 | # CONFIG_SND_MAESTRO3 is not set | ||
941 | # CONFIG_SND_MIXART is not set | ||
942 | # CONFIG_SND_NM256 is not set | ||
943 | # CONFIG_SND_PCXHR is not set | ||
944 | # CONFIG_SND_RIPTIDE is not set | ||
945 | # CONFIG_SND_RME32 is not set | ||
946 | # CONFIG_SND_RME96 is not set | ||
947 | # CONFIG_SND_RME9652 is not set | ||
948 | # CONFIG_SND_SONICVIBES is not set | ||
949 | # CONFIG_SND_TRIDENT is not set | ||
950 | # CONFIG_SND_VIA82XX is not set | ||
951 | # CONFIG_SND_VIA82XX_MODEM is not set | ||
952 | # CONFIG_SND_VX222 is not set | ||
953 | # CONFIG_SND_YMFPCI is not set | ||
954 | # CONFIG_SND_AC97_POWER_SAVE is not set | ||
955 | |||
956 | # | ||
957 | # ALSA ARM devices | ||
958 | # | ||
959 | CONFIG_SND_PXA2XX_PCM=m | ||
960 | CONFIG_SND_PXA2XX_AC97=m | ||
961 | |||
962 | # | ||
963 | # USB devices | ||
964 | # | ||
965 | # CONFIG_SND_USB_AUDIO is not set | ||
966 | # CONFIG_SND_USB_CAIAQ is not set | ||
967 | |||
968 | # | ||
969 | # System on Chip audio support | ||
970 | # | ||
971 | # CONFIG_SND_SOC is not set | ||
972 | |||
973 | # | ||
974 | # Open Sound System | ||
975 | # | ||
976 | # CONFIG_SOUND_PRIME is not set | ||
977 | CONFIG_AC97_BUS=m | ||
978 | CONFIG_HID_SUPPORT=y | ||
979 | CONFIG_HID=y | ||
980 | # CONFIG_HID_DEBUG is not set | ||
981 | |||
982 | # | ||
983 | # USB Input Devices | ||
984 | # | ||
985 | CONFIG_USB_HID=y | ||
986 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | ||
987 | # CONFIG_HID_FF is not set | ||
988 | # CONFIG_USB_HIDDEV is not set | ||
989 | CONFIG_USB_SUPPORT=y | ||
990 | CONFIG_USB_ARCH_HAS_HCD=y | ||
991 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
992 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
993 | CONFIG_USB=y | ||
994 | # CONFIG_USB_DEBUG is not set | ||
995 | |||
996 | # | ||
997 | # Miscellaneous USB options | ||
998 | # | ||
999 | CONFIG_USB_DEVICEFS=y | ||
1000 | # CONFIG_USB_DEVICE_CLASS is not set | ||
1001 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
1002 | # CONFIG_USB_SUSPEND is not set | ||
1003 | # CONFIG_USB_PERSIST is not set | ||
1004 | # CONFIG_USB_OTG is not set | ||
1005 | |||
1006 | # | ||
1007 | # USB Host Controller Drivers | ||
1008 | # | ||
1009 | # CONFIG_USB_EHCI_HCD is not set | ||
1010 | # CONFIG_USB_ISP116X_HCD is not set | ||
1011 | CONFIG_USB_OHCI_HCD=y | ||
1012 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
1013 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
1014 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
1015 | # CONFIG_USB_UHCI_HCD is not set | ||
1016 | # CONFIG_USB_SL811_HCD is not set | ||
1017 | # CONFIG_USB_R8A66597_HCD is not set | ||
1018 | |||
1019 | # | ||
1020 | # USB Device Class drivers | ||
1021 | # | ||
1022 | # CONFIG_USB_ACM is not set | ||
1023 | # CONFIG_USB_PRINTER is not set | ||
1024 | |||
1025 | # | ||
1026 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
1027 | # | ||
1028 | |||
1029 | # | ||
1030 | # may also be needed; see USB_STORAGE Help for more information | ||
1031 | # | ||
1032 | CONFIG_USB_STORAGE=y | ||
1033 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
1034 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
1035 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
1036 | # CONFIG_USB_STORAGE_DPCM is not set | ||
1037 | # CONFIG_USB_STORAGE_USBAT is not set | ||
1038 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
1039 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
1040 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
1041 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
1042 | # CONFIG_USB_STORAGE_KARMA is not set | ||
1043 | # CONFIG_USB_LIBUSUAL is not set | ||
1044 | |||
1045 | # | ||
1046 | # USB Imaging devices | ||
1047 | # | ||
1048 | # CONFIG_USB_MDC800 is not set | ||
1049 | # CONFIG_USB_MICROTEK is not set | ||
1050 | CONFIG_USB_MON=y | ||
1051 | |||
1052 | # | ||
1053 | # USB port drivers | ||
1054 | # | ||
1055 | |||
1056 | # | ||
1057 | # USB Serial Converter support | ||
1058 | # | ||
1059 | # CONFIG_USB_SERIAL is not set | ||
1060 | |||
1061 | # | ||
1062 | # USB Miscellaneous drivers | ||
1063 | # | ||
1064 | # CONFIG_USB_EMI62 is not set | ||
1065 | # CONFIG_USB_EMI26 is not set | ||
1066 | # CONFIG_USB_ADUTUX is not set | ||
1067 | # CONFIG_USB_AUERSWALD is not set | ||
1068 | # CONFIG_USB_RIO500 is not set | ||
1069 | # CONFIG_USB_LEGOTOWER is not set | ||
1070 | # CONFIG_USB_LCD is not set | ||
1071 | # CONFIG_USB_BERRY_CHARGE is not set | ||
1072 | # CONFIG_USB_LED is not set | ||
1073 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
1074 | # CONFIG_USB_CYTHERM is not set | ||
1075 | # CONFIG_USB_PHIDGET is not set | ||
1076 | # CONFIG_USB_IDMOUSE is not set | ||
1077 | # CONFIG_USB_FTDI_ELAN is not set | ||
1078 | # CONFIG_USB_APPLEDISPLAY is not set | ||
1079 | # CONFIG_USB_LD is not set | ||
1080 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
1081 | # CONFIG_USB_IOWARRIOR is not set | ||
1082 | # CONFIG_USB_TEST is not set | ||
1083 | |||
1084 | # | ||
1085 | # USB DSL modem support | ||
1086 | # | ||
1087 | |||
1088 | # | ||
1089 | # USB Gadget Support | ||
1090 | # | ||
1091 | # CONFIG_USB_GADGET is not set | ||
1092 | CONFIG_MMC=m | ||
1093 | # CONFIG_MMC_DEBUG is not set | ||
1094 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
1095 | |||
1096 | # | ||
1097 | # MMC/SD Card Drivers | ||
1098 | # | ||
1099 | CONFIG_MMC_BLOCK=m | ||
1100 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
1101 | |||
1102 | # | ||
1103 | # MMC/SD Host Controller Drivers | ||
1104 | # | ||
1105 | CONFIG_MMC_PXA=m | ||
1106 | # CONFIG_MMC_SDHCI is not set | ||
1107 | # CONFIG_MMC_TIFM_SD is not set | ||
1108 | |||
1109 | # | ||
1110 | # Real Time Clock | ||
1111 | # | ||
1112 | CONFIG_RTC_LIB=y | ||
1113 | CONFIG_RTC_CLASS=y | ||
1114 | CONFIG_RTC_HCTOSYS=y | ||
1115 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
1116 | # CONFIG_RTC_DEBUG is not set | ||
1117 | |||
1118 | # | ||
1119 | # RTC interfaces | ||
1120 | # | ||
1121 | CONFIG_RTC_INTF_SYSFS=y | ||
1122 | CONFIG_RTC_INTF_PROC=y | ||
1123 | CONFIG_RTC_INTF_DEV=y | ||
1124 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
1125 | # CONFIG_RTC_DRV_TEST is not set | ||
1126 | |||
1127 | # | ||
1128 | # Platform RTC drivers | ||
1129 | # | ||
1130 | # CONFIG_RTC_DRV_CMOS is not set | ||
1131 | # CONFIG_RTC_DRV_DS1553 is not set | ||
1132 | # CONFIG_RTC_DRV_DS1742 is not set | ||
1133 | # CONFIG_RTC_DRV_M48T86 is not set | ||
1134 | # CONFIG_RTC_DRV_M48T59 is not set | ||
1135 | CONFIG_RTC_DRV_V3020=y | ||
1136 | |||
1137 | # | ||
1138 | # on-CPU RTC drivers | ||
1139 | # | ||
1140 | CONFIG_RTC_DRV_SA1100=y | ||
1141 | |||
1142 | # | ||
1143 | # DMA Engine support | ||
1144 | # | ||
1145 | # CONFIG_DMA_ENGINE is not set | ||
1146 | |||
1147 | # | ||
1148 | # DMA Clients | ||
1149 | # | ||
1150 | |||
1151 | # | ||
1152 | # DMA Devices | ||
1153 | # | ||
1154 | |||
1155 | # | ||
1156 | # File systems | ||
1157 | # | ||
1158 | CONFIG_EXT2_FS=y | ||
1159 | # CONFIG_EXT2_FS_XATTR is not set | ||
1160 | # CONFIG_EXT2_FS_XIP is not set | ||
1161 | CONFIG_EXT3_FS=y | ||
1162 | CONFIG_EXT3_FS_XATTR=y | ||
1163 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
1164 | # CONFIG_EXT3_FS_SECURITY is not set | ||
1165 | # CONFIG_EXT4DEV_FS is not set | ||
1166 | CONFIG_JBD=y | ||
1167 | # CONFIG_JBD_DEBUG is not set | ||
1168 | CONFIG_FS_MBCACHE=y | ||
1169 | # CONFIG_REISERFS_FS is not set | ||
1170 | # CONFIG_JFS_FS is not set | ||
1171 | # CONFIG_FS_POSIX_ACL is not set | ||
1172 | # CONFIG_XFS_FS is not set | ||
1173 | # CONFIG_GFS2_FS is not set | ||
1174 | # CONFIG_OCFS2_FS is not set | ||
1175 | # CONFIG_MINIX_FS is not set | ||
1176 | # CONFIG_ROMFS_FS is not set | ||
1177 | CONFIG_INOTIFY=y | ||
1178 | CONFIG_INOTIFY_USER=y | ||
1179 | # CONFIG_QUOTA is not set | ||
1180 | CONFIG_DNOTIFY=y | ||
1181 | # CONFIG_AUTOFS_FS is not set | ||
1182 | # CONFIG_AUTOFS4_FS is not set | ||
1183 | # CONFIG_FUSE_FS is not set | ||
1184 | |||
1185 | # | ||
1186 | # CD-ROM/DVD Filesystems | ||
1187 | # | ||
1188 | # CONFIG_ISO9660_FS is not set | ||
1189 | # CONFIG_UDF_FS is not set | ||
1190 | |||
1191 | # | ||
1192 | # DOS/FAT/NT Filesystems | ||
1193 | # | ||
1194 | CONFIG_FAT_FS=y | ||
1195 | CONFIG_MSDOS_FS=y | ||
1196 | CONFIG_VFAT_FS=y | ||
1197 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
1198 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
1199 | # CONFIG_NTFS_FS is not set | ||
1200 | |||
1201 | # | ||
1202 | # Pseudo filesystems | ||
1203 | # | ||
1204 | CONFIG_PROC_FS=y | ||
1205 | CONFIG_PROC_SYSCTL=y | ||
1206 | CONFIG_SYSFS=y | ||
1207 | CONFIG_TMPFS=y | ||
1208 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
1209 | # CONFIG_HUGETLB_PAGE is not set | ||
1210 | CONFIG_RAMFS=y | ||
1211 | # CONFIG_CONFIGFS_FS is not set | ||
1212 | |||
1213 | # | ||
1214 | # Miscellaneous filesystems | ||
1215 | # | ||
1216 | # CONFIG_ADFS_FS is not set | ||
1217 | # CONFIG_AFFS_FS is not set | ||
1218 | # CONFIG_HFS_FS is not set | ||
1219 | # CONFIG_HFSPLUS_FS is not set | ||
1220 | # CONFIG_BEFS_FS is not set | ||
1221 | # CONFIG_BFS_FS is not set | ||
1222 | # CONFIG_EFS_FS is not set | ||
1223 | # CONFIG_JFFS2_FS is not set | ||
1224 | # CONFIG_CRAMFS is not set | ||
1225 | # CONFIG_VXFS_FS is not set | ||
1226 | # CONFIG_HPFS_FS is not set | ||
1227 | # CONFIG_QNX4FS_FS is not set | ||
1228 | # CONFIG_SYSV_FS is not set | ||
1229 | # CONFIG_UFS_FS is not set | ||
1230 | |||
1231 | # | ||
1232 | # Network File Systems | ||
1233 | # | ||
1234 | CONFIG_NFS_FS=y | ||
1235 | CONFIG_NFS_V3=y | ||
1236 | # CONFIG_NFS_V3_ACL is not set | ||
1237 | # CONFIG_NFS_V4 is not set | ||
1238 | # CONFIG_NFS_DIRECTIO is not set | ||
1239 | # CONFIG_NFSD is not set | ||
1240 | CONFIG_ROOT_NFS=y | ||
1241 | CONFIG_LOCKD=y | ||
1242 | CONFIG_LOCKD_V4=y | ||
1243 | CONFIG_NFS_COMMON=y | ||
1244 | CONFIG_SUNRPC=y | ||
1245 | # CONFIG_SUNRPC_BIND34 is not set | ||
1246 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
1247 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
1248 | CONFIG_SMB_FS=y | ||
1249 | # CONFIG_SMB_NLS_DEFAULT is not set | ||
1250 | # CONFIG_CIFS is not set | ||
1251 | # CONFIG_NCP_FS is not set | ||
1252 | # CONFIG_CODA_FS is not set | ||
1253 | # CONFIG_AFS_FS is not set | ||
1254 | |||
1255 | # | ||
1256 | # Partition Types | ||
1257 | # | ||
1258 | # CONFIG_PARTITION_ADVANCED is not set | ||
1259 | CONFIG_MSDOS_PARTITION=y | ||
1260 | |||
1261 | # | ||
1262 | # Native Language Support | ||
1263 | # | ||
1264 | CONFIG_NLS=y | ||
1265 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
1266 | CONFIG_NLS_CODEPAGE_437=y | ||
1267 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
1268 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
1269 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
1270 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
1271 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
1272 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
1273 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
1274 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
1275 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
1276 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
1277 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
1278 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
1279 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
1280 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
1281 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
1282 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
1283 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
1284 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
1285 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
1286 | # CONFIG_NLS_ISO8859_8 is not set | ||
1287 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
1288 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
1289 | # CONFIG_NLS_ASCII is not set | ||
1290 | CONFIG_NLS_ISO8859_1=y | ||
1291 | # CONFIG_NLS_ISO8859_2 is not set | ||
1292 | # CONFIG_NLS_ISO8859_3 is not set | ||
1293 | # CONFIG_NLS_ISO8859_4 is not set | ||
1294 | # CONFIG_NLS_ISO8859_5 is not set | ||
1295 | # CONFIG_NLS_ISO8859_6 is not set | ||
1296 | # CONFIG_NLS_ISO8859_7 is not set | ||
1297 | # CONFIG_NLS_ISO8859_9 is not set | ||
1298 | # CONFIG_NLS_ISO8859_13 is not set | ||
1299 | # CONFIG_NLS_ISO8859_14 is not set | ||
1300 | # CONFIG_NLS_ISO8859_15 is not set | ||
1301 | # CONFIG_NLS_KOI8_R is not set | ||
1302 | # CONFIG_NLS_KOI8_U is not set | ||
1303 | # CONFIG_NLS_UTF8 is not set | ||
1304 | |||
1305 | # | ||
1306 | # Distributed Lock Manager | ||
1307 | # | ||
1308 | # CONFIG_DLM is not set | ||
1309 | |||
1310 | # | ||
1311 | # Profiling support | ||
1312 | # | ||
1313 | # CONFIG_PROFILING is not set | ||
1314 | |||
1315 | # | ||
1316 | # Kernel hacking | ||
1317 | # | ||
1318 | # CONFIG_PRINTK_TIME is not set | ||
1319 | CONFIG_ENABLE_MUST_CHECK=y | ||
1320 | CONFIG_MAGIC_SYSRQ=y | ||
1321 | # CONFIG_UNUSED_SYMBOLS is not set | ||
1322 | # CONFIG_DEBUG_FS is not set | ||
1323 | # CONFIG_HEADERS_CHECK is not set | ||
1324 | CONFIG_DEBUG_KERNEL=y | ||
1325 | # CONFIG_DEBUG_SHIRQ is not set | ||
1326 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
1327 | CONFIG_SCHED_DEBUG=y | ||
1328 | # CONFIG_SCHEDSTATS is not set | ||
1329 | # CONFIG_TIMER_STATS is not set | ||
1330 | # CONFIG_DEBUG_SLAB is not set | ||
1331 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
1332 | # CONFIG_RT_MUTEX_TESTER is not set | ||
1333 | # CONFIG_DEBUG_SPINLOCK is not set | ||
1334 | # CONFIG_DEBUG_MUTEXES is not set | ||
1335 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
1336 | # CONFIG_PROVE_LOCKING is not set | ||
1337 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
1338 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
1339 | # CONFIG_DEBUG_KOBJECT is not set | ||
1340 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
1341 | CONFIG_DEBUG_INFO=y | ||
1342 | # CONFIG_DEBUG_VM is not set | ||
1343 | # CONFIG_DEBUG_LIST is not set | ||
1344 | CONFIG_FRAME_POINTER=y | ||
1345 | CONFIG_FORCED_INLINING=y | ||
1346 | # CONFIG_RCU_TORTURE_TEST is not set | ||
1347 | # CONFIG_FAULT_INJECTION is not set | ||
1348 | CONFIG_DEBUG_USER=y | ||
1349 | CONFIG_DEBUG_ERRORS=y | ||
1350 | CONFIG_DEBUG_LL=y | ||
1351 | # CONFIG_DEBUG_ICEDCC is not set | ||
1352 | |||
1353 | # | ||
1354 | # Security options | ||
1355 | # | ||
1356 | # CONFIG_KEYS is not set | ||
1357 | # CONFIG_SECURITY is not set | ||
1358 | CONFIG_CRYPTO=y | ||
1359 | CONFIG_CRYPTO_ALGAPI=m | ||
1360 | CONFIG_CRYPTO_BLKCIPHER=m | ||
1361 | CONFIG_CRYPTO_MANAGER=m | ||
1362 | # CONFIG_CRYPTO_HMAC is not set | ||
1363 | # CONFIG_CRYPTO_XCBC is not set | ||
1364 | # CONFIG_CRYPTO_NULL is not set | ||
1365 | # CONFIG_CRYPTO_MD4 is not set | ||
1366 | # CONFIG_CRYPTO_MD5 is not set | ||
1367 | # CONFIG_CRYPTO_SHA1 is not set | ||
1368 | # CONFIG_CRYPTO_SHA256 is not set | ||
1369 | # CONFIG_CRYPTO_SHA512 is not set | ||
1370 | # CONFIG_CRYPTO_WP512 is not set | ||
1371 | # CONFIG_CRYPTO_TGR192 is not set | ||
1372 | # CONFIG_CRYPTO_GF128MUL is not set | ||
1373 | CONFIG_CRYPTO_ECB=m | ||
1374 | CONFIG_CRYPTO_CBC=m | ||
1375 | CONFIG_CRYPTO_PCBC=m | ||
1376 | # CONFIG_CRYPTO_LRW is not set | ||
1377 | # CONFIG_CRYPTO_CRYPTD is not set | ||
1378 | # CONFIG_CRYPTO_DES is not set | ||
1379 | # CONFIG_CRYPTO_FCRYPT is not set | ||
1380 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
1381 | # CONFIG_CRYPTO_TWOFISH is not set | ||
1382 | # CONFIG_CRYPTO_SERPENT is not set | ||
1383 | CONFIG_CRYPTO_AES=m | ||
1384 | # CONFIG_CRYPTO_CAST5 is not set | ||
1385 | # CONFIG_CRYPTO_CAST6 is not set | ||
1386 | # CONFIG_CRYPTO_TEA is not set | ||
1387 | CONFIG_CRYPTO_ARC4=m | ||
1388 | # CONFIG_CRYPTO_KHAZAD is not set | ||
1389 | # CONFIG_CRYPTO_ANUBIS is not set | ||
1390 | # CONFIG_CRYPTO_DEFLATE is not set | ||
1391 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
1392 | # CONFIG_CRYPTO_CRC32C is not set | ||
1393 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
1394 | # CONFIG_CRYPTO_TEST is not set | ||
1395 | CONFIG_CRYPTO_HW=y | ||
1396 | |||
1397 | # | ||
1398 | # Library routines | ||
1399 | # | ||
1400 | CONFIG_BITREVERSE=y | ||
1401 | # CONFIG_CRC_CCITT is not set | ||
1402 | # CONFIG_CRC16 is not set | ||
1403 | # CONFIG_CRC_ITU_T is not set | ||
1404 | CONFIG_CRC32=y | ||
1405 | # CONFIG_CRC7 is not set | ||
1406 | # CONFIG_LIBCRC32C is not set | ||
1407 | CONFIG_PLIST=y | ||
1408 | CONFIG_HAS_IOMEM=y | ||
1409 | CONFIG_HAS_IOPORT=y | ||
1410 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index a2dd930d11ef..e5747547b44c 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c | |||
@@ -279,6 +279,25 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev) | |||
279 | } | 279 | } |
280 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); | 280 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); |
281 | 281 | ||
282 | static void __init pci_fixup_it8152(struct pci_dev *dev) | ||
283 | { | ||
284 | int i; | ||
285 | /* fixup for ITE 8152 devices */ | ||
286 | /* FIXME: add defines for class 0x68000 and 0x80103 */ | ||
287 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || | ||
288 | dev->class == 0x68000 || | ||
289 | dev->class == 0x80103) { | ||
290 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | ||
291 | dev->resource[i].start = 0; | ||
292 | dev->resource[i].end = 0; | ||
293 | dev->resource[i].flags = 0; | ||
294 | } | ||
295 | } | ||
296 | } | ||
297 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); | ||
298 | |||
299 | |||
300 | |||
282 | void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) | 301 | void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) |
283 | { | 302 | { |
284 | if (debug_pci) | 303 | if (debug_pci) |
@@ -292,9 +311,12 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) | |||
292 | */ | 311 | */ |
293 | static inline int pdev_bad_for_parity(struct pci_dev *dev) | 312 | static inline int pdev_bad_for_parity(struct pci_dev *dev) |
294 | { | 313 | { |
295 | return (dev->vendor == PCI_VENDOR_ID_INTERG && | 314 | return ((dev->vendor == PCI_VENDOR_ID_INTERG && |
296 | (dev->device == PCI_DEVICE_ID_INTERG_2000 || | 315 | (dev->device == PCI_DEVICE_ID_INTERG_2000 || |
297 | dev->device == PCI_DEVICE_ID_INTERG_2010)); | 316 | dev->device == PCI_DEVICE_ID_INTERG_2010)) || |
317 | (dev->vendor == PCI_VENDOR_ID_ITE && | ||
318 | dev->device == PCI_DEVICE_ID_ITE_8152)); | ||
319 | |||
298 | } | 320 | } |
299 | 321 | ||
300 | /* | 322 | /* |
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 5ebec6d88b51..656d49661a29 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
@@ -1,6 +1,24 @@ | |||
1 | if ARCH_PXA | 1 | if ARCH_PXA |
2 | 2 | ||
3 | menu "Intel PXA2xx Implementations" | 3 | menu "Intel PXA2xx/PXA3xx Implementations" |
4 | |||
5 | if PXA3xx | ||
6 | |||
7 | menu "Supported PXA3xx Processor Variants" | ||
8 | |||
9 | config CPU_PXA300 | ||
10 | bool "PXA300 (codename Monahans-L)" | ||
11 | |||
12 | config CPU_PXA310 | ||
13 | bool "PXA310 (codename Monahans-LV)" | ||
14 | select CPU_PXA300 | ||
15 | |||
16 | config CPU_PXA320 | ||
17 | bool "PXA320 (codename Monahans-P)" | ||
18 | |||
19 | endmenu | ||
20 | |||
21 | endif | ||
4 | 22 | ||
5 | choice | 23 | choice |
6 | prompt "Select target board" | 24 | prompt "Select target board" |
@@ -41,6 +59,15 @@ config MACH_EM_X270 | |||
41 | bool "CompuLab EM-x270 platform" | 59 | bool "CompuLab EM-x270 platform" |
42 | select PXA27x | 60 | select PXA27x |
43 | 61 | ||
62 | config MACH_ZYLONITE | ||
63 | bool "PXA3xx Development Platform" | ||
64 | select PXA3xx | ||
65 | |||
66 | config MACH_ARMCORE | ||
67 | bool "CompuLab CM-X270 modules" | ||
68 | select PXA27x | ||
69 | select IWMMXT | ||
70 | |||
44 | endchoice | 71 | endchoice |
45 | 72 | ||
46 | if PXA_SHARPSL | 73 | if PXA_SHARPSL |
@@ -130,6 +157,11 @@ config PXA27x | |||
130 | help | 157 | help |
131 | Select code specific to PXA27x variants | 158 | Select code specific to PXA27x variants |
132 | 159 | ||
160 | config PXA3xx | ||
161 | bool | ||
162 | help | ||
163 | Select code specific to PXA3xx variants | ||
164 | |||
133 | config PXA_SHARP_C7xx | 165 | config PXA_SHARP_C7xx |
134 | bool | 166 | bool |
135 | select PXA_SSP | 167 | select PXA_SSP |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 7d6ab5c59ab9..4263527e5123 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
@@ -3,36 +3,51 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Common support (must be linked before board specific support) | 5 | # Common support (must be linked before board specific support) |
6 | obj-y += clock.o generic.o irq.o dma.o time.o | 6 | obj-y += clock.o generic.o irq.o dma.o time.o |
7 | obj-$(CONFIG_PXA25x) += pxa25x.o | 7 | obj-$(CONFIG_PXA25x) += pxa25x.o |
8 | obj-$(CONFIG_PXA27x) += pxa27x.o | 8 | obj-$(CONFIG_PXA27x) += pxa27x.o |
9 | obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o | ||
10 | obj-$(CONFIG_CPU_PXA300) += pxa300.o | ||
11 | obj-$(CONFIG_CPU_PXA320) += pxa320.o | ||
9 | 12 | ||
10 | # Specific board support | 13 | # Specific board support |
11 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 14 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
12 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | 15 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o |
13 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 16 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
14 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o | 17 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o |
15 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o | 18 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o |
16 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o | 19 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o |
17 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o | 20 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o |
18 | obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o | 21 | obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o |
19 | obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o | 22 | obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o |
20 | obj-$(CONFIG_MACH_TOSA) += tosa.o | 23 | obj-$(CONFIG_MACH_TOSA) += tosa.o |
21 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o | 24 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o |
25 | |||
26 | ifeq ($(CONFIG_MACH_ZYLONITE),y) | ||
27 | obj-y += zylonite.o | ||
28 | obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o | ||
29 | obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o | ||
30 | endif | ||
31 | |||
32 | obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o | ||
22 | 33 | ||
23 | # Support for blinky lights | 34 | # Support for blinky lights |
24 | led-y := leds.o | 35 | led-y := leds.o |
25 | led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o | 36 | led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o |
26 | led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o | 37 | led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o |
27 | led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o | 38 | led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o |
28 | led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o | 39 | led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o |
29 | 40 | ||
30 | obj-$(CONFIG_LEDS) += $(led-y) | 41 | obj-$(CONFIG_LEDS) += $(led-y) |
31 | 42 | ||
32 | # Misc features | 43 | # Misc features |
33 | obj-$(CONFIG_PM) += pm.o sleep.o | 44 | obj-$(CONFIG_PM) += pm.o sleep.o |
34 | obj-$(CONFIG_PXA_SSP) += ssp.o | 45 | obj-$(CONFIG_PXA_SSP) += ssp.o |
35 | 46 | ||
36 | ifeq ($(CONFIG_PXA27x),y) | 47 | ifeq ($(CONFIG_PXA27x),y) |
37 | obj-$(CONFIG_PM) += standby.o | 48 | obj-$(CONFIG_PM) += standby.o |
49 | endif | ||
50 | |||
51 | ifeq ($(CONFIG_PCI),y) | ||
52 | obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o | ||
38 | endif | 53 | endif |
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 34a31caa6f9d..83ef5ecaf432 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c | |||
@@ -9,19 +9,15 @@ | |||
9 | #include <linux/string.h> | 9 | #include <linux/string.h> |
10 | #include <linux/clk.h> | 10 | #include <linux/clk.h> |
11 | #include <linux/spinlock.h> | 11 | #include <linux/spinlock.h> |
12 | #include <linux/platform_device.h> | ||
13 | #include <linux/delay.h> | ||
12 | 14 | ||
13 | #include <asm/arch/pxa-regs.h> | 15 | #include <asm/arch/pxa-regs.h> |
14 | #include <asm/hardware.h> | 16 | #include <asm/hardware.h> |
15 | 17 | ||
16 | struct clk { | 18 | #include "devices.h" |
17 | struct list_head node; | 19 | #include "generic.h" |
18 | unsigned long rate; | 20 | #include "clock.h" |
19 | struct module *owner; | ||
20 | const char *name; | ||
21 | unsigned int enabled; | ||
22 | void (*enable)(void); | ||
23 | void (*disable)(void); | ||
24 | }; | ||
25 | 21 | ||
26 | static LIST_HEAD(clocks); | 22 | static LIST_HEAD(clocks); |
27 | static DEFINE_MUTEX(clocks_mutex); | 23 | static DEFINE_MUTEX(clocks_mutex); |
@@ -33,7 +29,8 @@ struct clk *clk_get(struct device *dev, const char *id) | |||
33 | 29 | ||
34 | mutex_lock(&clocks_mutex); | 30 | mutex_lock(&clocks_mutex); |
35 | list_for_each_entry(p, &clocks, node) { | 31 | list_for_each_entry(p, &clocks, node) { |
36 | if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { | 32 | if (strcmp(id, p->name) == 0 && |
33 | (p->dev == NULL || p->dev == dev)) { | ||
37 | clk = p; | 34 | clk = p; |
38 | break; | 35 | break; |
39 | } | 36 | } |
@@ -46,7 +43,6 @@ EXPORT_SYMBOL(clk_get); | |||
46 | 43 | ||
47 | void clk_put(struct clk *clk) | 44 | void clk_put(struct clk *clk) |
48 | { | 45 | { |
49 | module_put(clk->owner); | ||
50 | } | 46 | } |
51 | EXPORT_SYMBOL(clk_put); | 47 | EXPORT_SYMBOL(clk_put); |
52 | 48 | ||
@@ -56,8 +52,12 @@ int clk_enable(struct clk *clk) | |||
56 | 52 | ||
57 | spin_lock_irqsave(&clocks_lock, flags); | 53 | spin_lock_irqsave(&clocks_lock, flags); |
58 | if (clk->enabled++ == 0) | 54 | if (clk->enabled++ == 0) |
59 | clk->enable(); | 55 | clk->ops->enable(clk); |
60 | spin_unlock_irqrestore(&clocks_lock, flags); | 56 | spin_unlock_irqrestore(&clocks_lock, flags); |
57 | |||
58 | if (clk->delay) | ||
59 | udelay(clk->delay); | ||
60 | |||
61 | return 0; | 61 | return 0; |
62 | } | 62 | } |
63 | EXPORT_SYMBOL(clk_enable); | 63 | EXPORT_SYMBOL(clk_enable); |
@@ -70,54 +70,75 @@ void clk_disable(struct clk *clk) | |||
70 | 70 | ||
71 | spin_lock_irqsave(&clocks_lock, flags); | 71 | spin_lock_irqsave(&clocks_lock, flags); |
72 | if (--clk->enabled == 0) | 72 | if (--clk->enabled == 0) |
73 | clk->disable(); | 73 | clk->ops->disable(clk); |
74 | spin_unlock_irqrestore(&clocks_lock, flags); | 74 | spin_unlock_irqrestore(&clocks_lock, flags); |
75 | } | 75 | } |
76 | EXPORT_SYMBOL(clk_disable); | 76 | EXPORT_SYMBOL(clk_disable); |
77 | 77 | ||
78 | unsigned long clk_get_rate(struct clk *clk) | 78 | unsigned long clk_get_rate(struct clk *clk) |
79 | { | 79 | { |
80 | return clk->rate; | 80 | unsigned long rate; |
81 | |||
82 | rate = clk->rate; | ||
83 | if (clk->ops->getrate) | ||
84 | rate = clk->ops->getrate(clk); | ||
85 | |||
86 | return rate; | ||
81 | } | 87 | } |
82 | EXPORT_SYMBOL(clk_get_rate); | 88 | EXPORT_SYMBOL(clk_get_rate); |
83 | 89 | ||
84 | 90 | ||
85 | static void clk_gpio27_enable(void) | 91 | static void clk_gpio27_enable(struct clk *clk) |
86 | { | 92 | { |
87 | pxa_gpio_mode(GPIO11_3_6MHz_MD); | 93 | pxa_gpio_mode(GPIO11_3_6MHz_MD); |
88 | } | 94 | } |
89 | 95 | ||
90 | static void clk_gpio27_disable(void) | 96 | static void clk_gpio27_disable(struct clk *clk) |
91 | { | 97 | { |
92 | } | 98 | } |
93 | 99 | ||
94 | static struct clk clk_gpio27 = { | 100 | static const struct clkops clk_gpio27_ops = { |
95 | .name = "GPIO27_CLK", | ||
96 | .rate = 3686400, | ||
97 | .enable = clk_gpio27_enable, | 101 | .enable = clk_gpio27_enable, |
98 | .disable = clk_gpio27_disable, | 102 | .disable = clk_gpio27_disable, |
99 | }; | 103 | }; |
100 | 104 | ||
101 | int clk_register(struct clk *clk) | 105 | |
106 | void clk_cken_enable(struct clk *clk) | ||
102 | { | 107 | { |
103 | mutex_lock(&clocks_mutex); | 108 | CKEN |= 1 << clk->cken; |
104 | list_add(&clk->node, &clocks); | ||
105 | mutex_unlock(&clocks_mutex); | ||
106 | return 0; | ||
107 | } | 109 | } |
108 | EXPORT_SYMBOL(clk_register); | ||
109 | 110 | ||
110 | void clk_unregister(struct clk *clk) | 111 | void clk_cken_disable(struct clk *clk) |
111 | { | 112 | { |
113 | CKEN &= ~(1 << clk->cken); | ||
114 | } | ||
115 | |||
116 | const struct clkops clk_cken_ops = { | ||
117 | .enable = clk_cken_enable, | ||
118 | .disable = clk_cken_disable, | ||
119 | }; | ||
120 | |||
121 | static struct clk common_clks[] = { | ||
122 | { | ||
123 | .name = "GPIO27_CLK", | ||
124 | .ops = &clk_gpio27_ops, | ||
125 | .rate = 3686400, | ||
126 | }, | ||
127 | }; | ||
128 | |||
129 | void clks_register(struct clk *clks, size_t num) | ||
130 | { | ||
131 | int i; | ||
132 | |||
112 | mutex_lock(&clocks_mutex); | 133 | mutex_lock(&clocks_mutex); |
113 | list_del(&clk->node); | 134 | for (i = 0; i < num; i++) |
135 | list_add(&clks[i].node, &clocks); | ||
114 | mutex_unlock(&clocks_mutex); | 136 | mutex_unlock(&clocks_mutex); |
115 | } | 137 | } |
116 | EXPORT_SYMBOL(clk_unregister); | ||
117 | 138 | ||
118 | static int __init clk_init(void) | 139 | static int __init clk_init(void) |
119 | { | 140 | { |
120 | clk_register(&clk_gpio27); | 141 | clks_register(common_clks, ARRAY_SIZE(common_clks)); |
121 | return 0; | 142 | return 0; |
122 | } | 143 | } |
123 | arch_initcall(clk_init); | 144 | arch_initcall(clk_init); |
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h new file mode 100644 index 000000000000..bc6b77e1592e --- /dev/null +++ b/arch/arm/mach-pxa/clock.h | |||
@@ -0,0 +1,43 @@ | |||
1 | struct clk; | ||
2 | |||
3 | struct clkops { | ||
4 | void (*enable)(struct clk *); | ||
5 | void (*disable)(struct clk *); | ||
6 | unsigned long (*getrate)(struct clk *); | ||
7 | }; | ||
8 | |||
9 | struct clk { | ||
10 | struct list_head node; | ||
11 | const char *name; | ||
12 | struct device *dev; | ||
13 | const struct clkops *ops; | ||
14 | unsigned long rate; | ||
15 | unsigned int cken; | ||
16 | unsigned int delay; | ||
17 | unsigned int enabled; | ||
18 | }; | ||
19 | |||
20 | #define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \ | ||
21 | { \ | ||
22 | .name = _name, \ | ||
23 | .dev = _dev, \ | ||
24 | .ops = &clk_cken_ops, \ | ||
25 | .rate = _rate, \ | ||
26 | .cken = CKEN_##_cken, \ | ||
27 | .delay = _delay, \ | ||
28 | } | ||
29 | |||
30 | #define INIT_CK(_name, _cken, _ops, _dev) \ | ||
31 | { \ | ||
32 | .name = _name, \ | ||
33 | .dev = _dev, \ | ||
34 | .ops = _ops, \ | ||
35 | .cken = CKEN_##_cken, \ | ||
36 | } | ||
37 | |||
38 | extern const struct clkops clk_cken_ops; | ||
39 | |||
40 | void clk_cken_enable(struct clk *clk); | ||
41 | void clk_cken_disable(struct clk *clk); | ||
42 | |||
43 | void clks_register(struct clk *clks, size_t num); | ||
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c new file mode 100644 index 000000000000..878d3b9b8633 --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270-pci.c | |||
@@ -0,0 +1,218 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/cm-x270-pci.c | ||
3 | * | ||
4 | * PCI bios-type initialisation for PCI machines | ||
5 | * | ||
6 | * Bits taken from various places. | ||
7 | * | ||
8 | * Copyright (C) 2007 Compulab, Ltd. | ||
9 | * Mike Rapoport <mike@compulab.co.il> | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/pci.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/device.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/irq.h> | ||
22 | |||
23 | #include <asm/mach/pci.h> | ||
24 | #include <asm/arch/cm-x270.h> | ||
25 | #include <asm/arch/pxa-regs.h> | ||
26 | #include <asm/mach-types.h> | ||
27 | |||
28 | #include <asm/hardware/it8152.h> | ||
29 | |||
30 | unsigned long it8152_base_address = CMX270_IT8152_VIRT; | ||
31 | |||
32 | /* | ||
33 | * Only first 64MB of memory can be accessed via PCI. | ||
34 | * We use GFP_DMA to allocate safe buffers to do map/unmap. | ||
35 | * This is really ugly and we need a better way of specifying | ||
36 | * DMA-capable regions of memory. | ||
37 | */ | ||
38 | void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size, | ||
39 | unsigned long *zhole_size) | ||
40 | { | ||
41 | unsigned int sz = SZ_64M >> PAGE_SHIFT; | ||
42 | |||
43 | printk(KERN_INFO "Adjusting zones for CM-x270\n"); | ||
44 | |||
45 | /* | ||
46 | * Only adjust if > 64M on current system | ||
47 | */ | ||
48 | if (node || (zone_size[0] <= sz)) | ||
49 | return; | ||
50 | |||
51 | zone_size[1] = zone_size[0] - sz; | ||
52 | zone_size[0] = sz; | ||
53 | zhole_size[1] = zhole_size[0]; | ||
54 | zhole_size[0] = 0; | ||
55 | } | ||
56 | |||
57 | static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) | ||
58 | { | ||
59 | /* clear our parent irq */ | ||
60 | GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ); | ||
61 | |||
62 | it8152_irq_demux(irq, desc); | ||
63 | } | ||
64 | |||
65 | void __cmx270_pci_init_irq(void) | ||
66 | { | ||
67 | it8152_init_irq(); | ||
68 | pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ)); | ||
69 | set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING); | ||
70 | |||
71 | set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ), | ||
72 | cmx270_it8152_irq_demux); | ||
73 | } | ||
74 | |||
75 | #ifdef CONFIG_PM | ||
76 | static unsigned long sleep_save_ite[10]; | ||
77 | |||
78 | void __cmx270_pci_suspend(void) | ||
79 | { | ||
80 | /* save ITE state */ | ||
81 | sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR); | ||
82 | sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR); | ||
83 | sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR); | ||
84 | |||
85 | /* Clear ITE IRQ's */ | ||
86 | __raw_writel((0), IT8152_INTC_PDCNIRR); | ||
87 | __raw_writel((0), IT8152_INTC_LPCNIRR); | ||
88 | } | ||
89 | |||
90 | void __cmx270_pci_resume(void) | ||
91 | { | ||
92 | /* restore IT8152 state */ | ||
93 | __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR); | ||
94 | __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR); | ||
95 | __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR); | ||
96 | } | ||
97 | #else | ||
98 | void cmx270_pci_suspend(void) {} | ||
99 | void cmx270_pci_resume(void) {} | ||
100 | #endif | ||
101 | |||
102 | /* PCI IRQ mapping*/ | ||
103 | static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
104 | { | ||
105 | int irq; | ||
106 | |||
107 | printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__, | ||
108 | pci_name(dev), slot, pin); | ||
109 | |||
110 | irq = it8152_pci_map_irq(dev, slot, pin); | ||
111 | if (irq) | ||
112 | return irq; | ||
113 | |||
114 | /* | ||
115 | Here comes the ugly part. The routing is baseboard specific, | ||
116 | but defining a platform for each possible base of CM-x270 is | ||
117 | unrealistic. Here we keep mapping for ATXBase and SB-x270. | ||
118 | */ | ||
119 | /* ATXBASE PCI slot */ | ||
120 | if (slot == 7) | ||
121 | return IT8152_PCI_INTA; | ||
122 | |||
123 | /* ATXBase/SB-x270 CardBus */ | ||
124 | if (slot == 8 || slot == 0) | ||
125 | return IT8152_PCI_INTB; | ||
126 | |||
127 | /* ATXBase Ethernet */ | ||
128 | if (slot == 9) | ||
129 | return IT8152_PCI_INTA; | ||
130 | |||
131 | /* SB-x270 Ethernet */ | ||
132 | if (slot == 16) | ||
133 | return IT8152_PCI_INTA; | ||
134 | |||
135 | /* PC104+ interrupt routing */ | ||
136 | if ((slot == 17) || (slot == 19)) | ||
137 | return IT8152_PCI_INTA; | ||
138 | if ((slot == 18) || (slot == 20)) | ||
139 | return IT8152_PCI_INTB; | ||
140 | |||
141 | return(0); | ||
142 | } | ||
143 | |||
144 | static struct pci_bus * __init | ||
145 | cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys) | ||
146 | { | ||
147 | printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n"); | ||
148 | |||
149 | __raw_writel(0x800, IT8152_PCI_CFG_ADDR); | ||
150 | if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { | ||
151 | printk(KERN_INFO "PCI Bridge found.\n"); | ||
152 | |||
153 | /* set PCI I/O base at 0 */ | ||
154 | writel(0x848, IT8152_PCI_CFG_ADDR); | ||
155 | writel(0, IT8152_PCI_CFG_DATA); | ||
156 | |||
157 | /* set PCI memory base at 0 */ | ||
158 | writel(0x840, IT8152_PCI_CFG_ADDR); | ||
159 | writel(0, IT8152_PCI_CFG_DATA); | ||
160 | |||
161 | writel(0x20, IT8152_GPIO_GPDR); | ||
162 | |||
163 | /* CardBus Controller on ATXbase baseboard */ | ||
164 | writel(0x4000, IT8152_PCI_CFG_ADDR); | ||
165 | if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) { | ||
166 | printk(KERN_INFO "CardBus Bridge found.\n"); | ||
167 | |||
168 | /* Configure socket 0 */ | ||
169 | writel(0x408C, IT8152_PCI_CFG_ADDR); | ||
170 | writel(0x1022, IT8152_PCI_CFG_DATA); | ||
171 | |||
172 | writel(0x4080, IT8152_PCI_CFG_ADDR); | ||
173 | writel(0x3844d060, IT8152_PCI_CFG_DATA); | ||
174 | |||
175 | writel(0x4090, IT8152_PCI_CFG_ADDR); | ||
176 | writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | | ||
177 | 0x60440000), | ||
178 | IT8152_PCI_CFG_DATA); | ||
179 | |||
180 | writel(0x4018, IT8152_PCI_CFG_ADDR); | ||
181 | writel(0xb0000000, IT8152_PCI_CFG_DATA); | ||
182 | |||
183 | /* Configure socket 1 */ | ||
184 | writel(0x418C, IT8152_PCI_CFG_ADDR); | ||
185 | writel(0x1022, IT8152_PCI_CFG_DATA); | ||
186 | |||
187 | writel(0x4180, IT8152_PCI_CFG_ADDR); | ||
188 | writel(0x3844d060, IT8152_PCI_CFG_DATA); | ||
189 | |||
190 | writel(0x4190, IT8152_PCI_CFG_ADDR); | ||
191 | writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | | ||
192 | 0x60440000), | ||
193 | IT8152_PCI_CFG_DATA); | ||
194 | |||
195 | writel(0x4118, IT8152_PCI_CFG_ADDR); | ||
196 | writel(0xb0000000, IT8152_PCI_CFG_DATA); | ||
197 | } | ||
198 | } | ||
199 | return it8152_pci_scan_bus(nr, sys); | ||
200 | } | ||
201 | |||
202 | static struct hw_pci cmx270_pci __initdata = { | ||
203 | .swizzle = pci_std_swizzle, | ||
204 | .map_irq = cmx270_pci_map_irq, | ||
205 | .nr_controllers = 1, | ||
206 | .setup = it8152_pci_setup, | ||
207 | .scan = cmx270_pci_scan_bus, | ||
208 | }; | ||
209 | |||
210 | static int __init cmx270_init_pci(void) | ||
211 | { | ||
212 | if (machine_is_armcore()) | ||
213 | pci_common_init(&cmx270_pci); | ||
214 | |||
215 | return 0; | ||
216 | } | ||
217 | |||
218 | subsys_initcall(cmx270_init_pci); | ||
diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h new file mode 100644 index 000000000000..ffe37b66f9a0 --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270-pci.h | |||
@@ -0,0 +1,13 @@ | |||
1 | extern void __cmx270_pci_init_irq(void); | ||
2 | extern void __cmx270_pci_suspend(void); | ||
3 | extern void __cmx270_pci_resume(void); | ||
4 | |||
5 | #ifdef CONFIG_PCI | ||
6 | #define cmx270_pci_init_irq __cmx270_pci_init_irq | ||
7 | #define cmx270_pci_suspend __cmx270_pci_suspend | ||
8 | #define cmx270_pci_resume __cmx270_pci_resume | ||
9 | #else | ||
10 | #define cmx270_pci_init_irq() do {} while (0) | ||
11 | #define cmx270_pci_suspend() do {} while (0) | ||
12 | #define cmx270_pci_resume() do {} while (0) | ||
13 | #endif | ||
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c new file mode 100644 index 000000000000..177664ccb2e2 --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270.c | |||
@@ -0,0 +1,645 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/cm-x270.c | ||
3 | * | ||
4 | * Copyright (C) 2007 CompuLab, Ltd. | ||
5 | * Mike Rapoport <mike@compulab.co.il> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | #include <linux/pm.h> | ||
14 | #include <linux/fb.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/sysdev.h> | ||
18 | #include <linux/io.h> | ||
19 | #include <linux/delay.h> | ||
20 | |||
21 | #include <linux/dm9000.h> | ||
22 | #include <linux/rtc-v3020.h> | ||
23 | #include <linux/serial_8250.h> | ||
24 | |||
25 | #include <video/mbxfb.h> | ||
26 | |||
27 | #include <asm/mach/arch.h> | ||
28 | #include <asm/mach-types.h> | ||
29 | #include <asm/mach/map.h> | ||
30 | |||
31 | #include <asm/arch/pxa-regs.h> | ||
32 | #include <asm/arch/pxafb.h> | ||
33 | #include <asm/arch/ohci.h> | ||
34 | #include <asm/arch/mmc.h> | ||
35 | #include <asm/arch/bitfield.h> | ||
36 | #include <asm/arch/cm-x270.h> | ||
37 | |||
38 | #include <asm/hardware/it8152.h> | ||
39 | |||
40 | #include "generic.h" | ||
41 | #include "cm-x270-pci.h" | ||
42 | |||
43 | #define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22)) | ||
44 | #define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22)) | ||
45 | |||
46 | static struct resource cmx270_dm9k_resource[] = { | ||
47 | [0] = { | ||
48 | .start = DM9000_PHYS_BASE, | ||
49 | .end = DM9000_PHYS_BASE + 4, | ||
50 | .flags = IORESOURCE_MEM, | ||
51 | }, | ||
52 | [1] = { | ||
53 | .start = DM9000_PHYS_BASE + 8, | ||
54 | .end = DM9000_PHYS_BASE + 8 + 500, | ||
55 | .flags = IORESOURCE_MEM, | ||
56 | }, | ||
57 | [2] = { | ||
58 | .start = CMX270_ETHIRQ, | ||
59 | .end = CMX270_ETHIRQ, | ||
60 | .flags = IORESOURCE_IRQ, | ||
61 | } | ||
62 | }; | ||
63 | |||
64 | /* for the moment we limit ourselves to 32bit IO until some | ||
65 | * better IO routines can be written and tested | ||
66 | */ | ||
67 | static struct dm9000_plat_data cmx270_dm9k_platdata = { | ||
68 | .flags = DM9000_PLATF_32BITONLY, | ||
69 | }; | ||
70 | |||
71 | /* Ethernet device */ | ||
72 | static struct platform_device cmx270_device_dm9k = { | ||
73 | .name = "dm9000", | ||
74 | .id = 0, | ||
75 | .num_resources = ARRAY_SIZE(cmx270_dm9k_resource), | ||
76 | .resource = cmx270_dm9k_resource, | ||
77 | .dev = { | ||
78 | .platform_data = &cmx270_dm9k_platdata, | ||
79 | } | ||
80 | }; | ||
81 | |||
82 | /* audio device */ | ||
83 | static struct platform_device cmx270_audio_device = { | ||
84 | .name = "pxa2xx-ac97", | ||
85 | .id = -1, | ||
86 | }; | ||
87 | |||
88 | /* touchscreen controller */ | ||
89 | static struct platform_device cmx270_ts_device = { | ||
90 | .name = "ucb1400_ts", | ||
91 | .id = -1, | ||
92 | }; | ||
93 | |||
94 | /* RTC */ | ||
95 | static struct resource cmx270_v3020_resource[] = { | ||
96 | [0] = { | ||
97 | .start = RTC_PHYS_BASE, | ||
98 | .end = RTC_PHYS_BASE + 4, | ||
99 | .flags = IORESOURCE_MEM, | ||
100 | }, | ||
101 | }; | ||
102 | |||
103 | struct v3020_platform_data cmx270_v3020_pdata = { | ||
104 | .leftshift = 16, | ||
105 | }; | ||
106 | |||
107 | static struct platform_device cmx270_rtc_device = { | ||
108 | .name = "v3020", | ||
109 | .num_resources = ARRAY_SIZE(cmx270_v3020_resource), | ||
110 | .resource = cmx270_v3020_resource, | ||
111 | .id = -1, | ||
112 | .dev = { | ||
113 | .platform_data = &cmx270_v3020_pdata, | ||
114 | } | ||
115 | }; | ||
116 | |||
117 | /* | ||
118 | * CM-X270 LEDs | ||
119 | */ | ||
120 | static struct platform_device cmx270_led_device = { | ||
121 | .name = "cm-x270-led", | ||
122 | .id = -1, | ||
123 | }; | ||
124 | |||
125 | /* 2700G graphics */ | ||
126 | static u64 fb_dma_mask = ~(u64)0; | ||
127 | |||
128 | static struct resource cmx270_2700G_resource[] = { | ||
129 | /* frame buffer memory including ODFB and External SDRAM */ | ||
130 | [0] = { | ||
131 | .start = MARATHON_PHYS, | ||
132 | .end = MARATHON_PHYS + 0x02000000, | ||
133 | .flags = IORESOURCE_MEM, | ||
134 | }, | ||
135 | /* Marathon registers */ | ||
136 | [1] = { | ||
137 | .start = MARATHON_PHYS + 0x03fe0000, | ||
138 | .end = MARATHON_PHYS + 0x03ffffff, | ||
139 | .flags = IORESOURCE_MEM, | ||
140 | }, | ||
141 | }; | ||
142 | |||
143 | static unsigned long save_lcd_regs[10]; | ||
144 | |||
145 | static int cmx270_marathon_probe(struct fb_info *fb) | ||
146 | { | ||
147 | /* save PXA-270 pin settings before enabling 2700G */ | ||
148 | save_lcd_regs[0] = GPDR1; | ||
149 | save_lcd_regs[1] = GPDR2; | ||
150 | save_lcd_regs[2] = GAFR1_U; | ||
151 | save_lcd_regs[3] = GAFR2_L; | ||
152 | save_lcd_regs[4] = GAFR2_U; | ||
153 | |||
154 | /* Disable PXA-270 on-chip controller driving pins */ | ||
155 | GPDR1 &= ~(0xfc000000); | ||
156 | GPDR2 &= ~(0x00c03fff); | ||
157 | GAFR1_U &= ~(0xfff00000); | ||
158 | GAFR2_L &= ~(0x0fffffff); | ||
159 | GAFR2_U &= ~(0x0000f000); | ||
160 | return 0; | ||
161 | } | ||
162 | |||
163 | static int cmx270_marathon_remove(struct fb_info *fb) | ||
164 | { | ||
165 | GPDR1 = save_lcd_regs[0]; | ||
166 | GPDR2 = save_lcd_regs[1]; | ||
167 | GAFR1_U = save_lcd_regs[2]; | ||
168 | GAFR2_L = save_lcd_regs[3]; | ||
169 | GAFR2_U = save_lcd_regs[4]; | ||
170 | return 0; | ||
171 | } | ||
172 | |||
173 | static struct mbxfb_platform_data cmx270_2700G_data = { | ||
174 | .xres = { | ||
175 | .min = 240, | ||
176 | .max = 1200, | ||
177 | .defval = 640, | ||
178 | }, | ||
179 | .yres = { | ||
180 | .min = 240, | ||
181 | .max = 1200, | ||
182 | .defval = 480, | ||
183 | }, | ||
184 | .bpp = { | ||
185 | .min = 16, | ||
186 | .max = 32, | ||
187 | .defval = 16, | ||
188 | }, | ||
189 | .memsize = 8*1024*1024, | ||
190 | .probe = cmx270_marathon_probe, | ||
191 | .remove = cmx270_marathon_remove, | ||
192 | }; | ||
193 | |||
194 | static struct platform_device cmx270_2700G = { | ||
195 | .name = "mbx-fb", | ||
196 | .dev = { | ||
197 | .platform_data = &cmx270_2700G_data, | ||
198 | .dma_mask = &fb_dma_mask, | ||
199 | .coherent_dma_mask = 0xffffffff, | ||
200 | }, | ||
201 | .num_resources = ARRAY_SIZE(cmx270_2700G_resource), | ||
202 | .resource = cmx270_2700G_resource, | ||
203 | .id = -1, | ||
204 | }; | ||
205 | |||
206 | static u64 ata_dma_mask = ~(u64)0; | ||
207 | |||
208 | static struct platform_device cmx270_ata = { | ||
209 | .name = "pata_cm_x270", | ||
210 | .id = -1, | ||
211 | .dev = { | ||
212 | .dma_mask = &ata_dma_mask, | ||
213 | .coherent_dma_mask = 0xffffffff, | ||
214 | }, | ||
215 | }; | ||
216 | |||
217 | /* platform devices */ | ||
218 | static struct platform_device *platform_devices[] __initdata = { | ||
219 | &cmx270_device_dm9k, | ||
220 | &cmx270_audio_device, | ||
221 | &cmx270_rtc_device, | ||
222 | &cmx270_2700G, | ||
223 | &cmx270_led_device, | ||
224 | &cmx270_ts_device, | ||
225 | &cmx270_ata, | ||
226 | }; | ||
227 | |||
228 | /* Map PCI companion and IDE/General Purpose CS statically */ | ||
229 | static struct map_desc cmx270_io_desc[] __initdata = { | ||
230 | [0] = { /* IDE/general purpose space */ | ||
231 | .virtual = CMX270_IDE104_VIRT, | ||
232 | .pfn = __phys_to_pfn(CMX270_IDE104_PHYS), | ||
233 | .length = SZ_64M - SZ_8M, | ||
234 | .type = MT_DEVICE | ||
235 | }, | ||
236 | [1] = { /* PCI bridge */ | ||
237 | .virtual = CMX270_IT8152_VIRT, | ||
238 | .pfn = __phys_to_pfn(CMX270_IT8152_PHYS), | ||
239 | .length = SZ_64M, | ||
240 | .type = MT_DEVICE | ||
241 | }, | ||
242 | }; | ||
243 | |||
244 | /* | ||
245 | Display definitions | ||
246 | keep these for backwards compatibility, although symbolic names (as | ||
247 | e.g. in lpd270.c) looks better | ||
248 | */ | ||
249 | #define MTYPE_STN320x240 0 | ||
250 | #define MTYPE_TFT640x480 1 | ||
251 | #define MTYPE_CRT640x480 2 | ||
252 | #define MTYPE_CRT800x600 3 | ||
253 | #define MTYPE_TFT320x240 6 | ||
254 | #define MTYPE_STN640x480 7 | ||
255 | |||
256 | static struct pxafb_mode_info generic_stn_320x240_mode = { | ||
257 | .pixclock = 76923, | ||
258 | .bpp = 8, | ||
259 | .xres = 320, | ||
260 | .yres = 240, | ||
261 | .hsync_len = 3, | ||
262 | .vsync_len = 2, | ||
263 | .left_margin = 3, | ||
264 | .upper_margin = 0, | ||
265 | .right_margin = 3, | ||
266 | .lower_margin = 0, | ||
267 | .sync = (FB_SYNC_HOR_HIGH_ACT | | ||
268 | FB_SYNC_VERT_HIGH_ACT), | ||
269 | .cmap_greyscale = 0, | ||
270 | }; | ||
271 | |||
272 | static struct pxafb_mach_info generic_stn_320x240 = { | ||
273 | .modes = &generic_stn_320x240_mode, | ||
274 | .num_modes = 1, | ||
275 | .lccr0 = 0, | ||
276 | .lccr3 = (LCCR3_PixClkDiv(0x03) | | ||
277 | LCCR3_Acb(0xff) | | ||
278 | LCCR3_PCP), | ||
279 | .cmap_inverse = 0, | ||
280 | .cmap_static = 0, | ||
281 | }; | ||
282 | |||
283 | static struct pxafb_mode_info generic_tft_640x480_mode = { | ||
284 | .pixclock = 38461, | ||
285 | .bpp = 8, | ||
286 | .xres = 640, | ||
287 | .yres = 480, | ||
288 | .hsync_len = 60, | ||
289 | .vsync_len = 2, | ||
290 | .left_margin = 70, | ||
291 | .upper_margin = 10, | ||
292 | .right_margin = 70, | ||
293 | .lower_margin = 5, | ||
294 | .sync = 0, | ||
295 | .cmap_greyscale = 0, | ||
296 | }; | ||
297 | |||
298 | static struct pxafb_mach_info generic_tft_640x480 = { | ||
299 | .modes = &generic_tft_640x480_mode, | ||
300 | .num_modes = 1, | ||
301 | .lccr0 = (LCCR0_PAS), | ||
302 | .lccr3 = (LCCR3_PixClkDiv(0x01) | | ||
303 | LCCR3_Acb(0xff) | | ||
304 | LCCR3_PCP), | ||
305 | .cmap_inverse = 0, | ||
306 | .cmap_static = 0, | ||
307 | }; | ||
308 | |||
309 | static struct pxafb_mode_info generic_crt_640x480_mode = { | ||
310 | .pixclock = 38461, | ||
311 | .bpp = 8, | ||
312 | .xres = 640, | ||
313 | .yres = 480, | ||
314 | .hsync_len = 63, | ||
315 | .vsync_len = 2, | ||
316 | .left_margin = 81, | ||
317 | .upper_margin = 33, | ||
318 | .right_margin = 16, | ||
319 | .lower_margin = 10, | ||
320 | .sync = (FB_SYNC_HOR_HIGH_ACT | | ||
321 | FB_SYNC_VERT_HIGH_ACT), | ||
322 | .cmap_greyscale = 0, | ||
323 | }; | ||
324 | |||
325 | static struct pxafb_mach_info generic_crt_640x480 = { | ||
326 | .modes = &generic_crt_640x480_mode, | ||
327 | .num_modes = 1, | ||
328 | .lccr0 = (LCCR0_PAS), | ||
329 | .lccr3 = (LCCR3_PixClkDiv(0x01) | | ||
330 | LCCR3_Acb(0xff)), | ||
331 | .cmap_inverse = 0, | ||
332 | .cmap_static = 0, | ||
333 | }; | ||
334 | |||
335 | static struct pxafb_mode_info generic_crt_800x600_mode = { | ||
336 | .pixclock = 28846, | ||
337 | .bpp = 8, | ||
338 | .xres = 800, | ||
339 | .yres = 600, | ||
340 | .hsync_len = 63, | ||
341 | .vsync_len = 2, | ||
342 | .left_margin = 26, | ||
343 | .upper_margin = 21, | ||
344 | .right_margin = 26, | ||
345 | .lower_margin = 11, | ||
346 | .sync = (FB_SYNC_HOR_HIGH_ACT | | ||
347 | FB_SYNC_VERT_HIGH_ACT), | ||
348 | .cmap_greyscale = 0, | ||
349 | }; | ||
350 | |||
351 | static struct pxafb_mach_info generic_crt_800x600 = { | ||
352 | .modes = &generic_crt_800x600_mode, | ||
353 | .num_modes = 1, | ||
354 | .lccr0 = (LCCR0_PAS), | ||
355 | .lccr3 = (LCCR3_PixClkDiv(0x02) | | ||
356 | LCCR3_Acb(0xff)), | ||
357 | .cmap_inverse = 0, | ||
358 | .cmap_static = 0, | ||
359 | }; | ||
360 | |||
361 | static struct pxafb_mode_info generic_tft_320x240_mode = { | ||
362 | .pixclock = 134615, | ||
363 | .bpp = 16, | ||
364 | .xres = 320, | ||
365 | .yres = 240, | ||
366 | .hsync_len = 63, | ||
367 | .vsync_len = 7, | ||
368 | .left_margin = 75, | ||
369 | .upper_margin = 0, | ||
370 | .right_margin = 15, | ||
371 | .lower_margin = 15, | ||
372 | .sync = 0, | ||
373 | .cmap_greyscale = 0, | ||
374 | }; | ||
375 | |||
376 | static struct pxafb_mach_info generic_tft_320x240 = { | ||
377 | .modes = &generic_tft_320x240_mode, | ||
378 | .num_modes = 1, | ||
379 | .lccr0 = (LCCR0_PAS), | ||
380 | .lccr3 = (LCCR3_PixClkDiv(0x06) | | ||
381 | LCCR3_Acb(0xff) | | ||
382 | LCCR3_PCP), | ||
383 | .cmap_inverse = 0, | ||
384 | .cmap_static = 0, | ||
385 | }; | ||
386 | |||
387 | static struct pxafb_mode_info generic_stn_640x480_mode = { | ||
388 | .pixclock = 57692, | ||
389 | .bpp = 8, | ||
390 | .xres = 640, | ||
391 | .yres = 480, | ||
392 | .hsync_len = 4, | ||
393 | .vsync_len = 2, | ||
394 | .left_margin = 10, | ||
395 | .upper_margin = 5, | ||
396 | .right_margin = 10, | ||
397 | .lower_margin = 5, | ||
398 | .sync = (FB_SYNC_HOR_HIGH_ACT | | ||
399 | FB_SYNC_VERT_HIGH_ACT), | ||
400 | .cmap_greyscale = 0, | ||
401 | }; | ||
402 | |||
403 | static struct pxafb_mach_info generic_stn_640x480 = { | ||
404 | .modes = &generic_stn_640x480_mode, | ||
405 | .num_modes = 1, | ||
406 | .lccr0 = 0, | ||
407 | .lccr3 = (LCCR3_PixClkDiv(0x02) | | ||
408 | LCCR3_Acb(0xff)), | ||
409 | .cmap_inverse = 0, | ||
410 | .cmap_static = 0, | ||
411 | }; | ||
412 | |||
413 | static struct pxafb_mach_info *cmx270_display = &generic_crt_640x480; | ||
414 | |||
415 | static int __init cmx270_set_display(char *str) | ||
416 | { | ||
417 | int disp_type = simple_strtol(str, NULL, 0); | ||
418 | switch (disp_type) { | ||
419 | case MTYPE_STN320x240: | ||
420 | cmx270_display = &generic_stn_320x240; | ||
421 | break; | ||
422 | case MTYPE_TFT640x480: | ||
423 | cmx270_display = &generic_tft_640x480; | ||
424 | break; | ||
425 | case MTYPE_CRT640x480: | ||
426 | cmx270_display = &generic_crt_640x480; | ||
427 | break; | ||
428 | case MTYPE_CRT800x600: | ||
429 | cmx270_display = &generic_crt_800x600; | ||
430 | break; | ||
431 | case MTYPE_TFT320x240: | ||
432 | cmx270_display = &generic_tft_320x240; | ||
433 | break; | ||
434 | case MTYPE_STN640x480: | ||
435 | cmx270_display = &generic_stn_640x480; | ||
436 | break; | ||
437 | default: /* fallback to CRT 640x480 */ | ||
438 | cmx270_display = &generic_crt_640x480; | ||
439 | break; | ||
440 | } | ||
441 | return 1; | ||
442 | } | ||
443 | |||
444 | /* | ||
445 | This should be done really early to get proper configuration for | ||
446 | frame buffer. | ||
447 | Indeed, pxafb parameters can be used istead, but CM-X270 bootloader | ||
448 | has limitied line length for kernel command line, and also it will | ||
449 | break compatibitlty with proprietary releases already in field. | ||
450 | */ | ||
451 | __setup("monitor=", cmx270_set_display); | ||
452 | |||
453 | /* PXA27x OHCI controller setup */ | ||
454 | static int cmx270_ohci_init(struct device *dev) | ||
455 | { | ||
456 | /* Set the Power Control Polarity Low */ | ||
457 | UHCHR = (UHCHR | UHCHR_PCPL) & | ||
458 | ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); | ||
459 | |||
460 | return 0; | ||
461 | } | ||
462 | |||
463 | static struct pxaohci_platform_data cmx270_ohci_platform_data = { | ||
464 | .port_mode = PMM_PERPORT_MODE, | ||
465 | .init = cmx270_ohci_init, | ||
466 | }; | ||
467 | |||
468 | |||
469 | static int cmx270_mci_init(struct device *dev, | ||
470 | irq_handler_t cmx270_detect_int, | ||
471 | void *data) | ||
472 | { | ||
473 | int err; | ||
474 | |||
475 | /* | ||
476 | * setup GPIO for PXA27x MMC controller | ||
477 | */ | ||
478 | pxa_gpio_mode(GPIO32_MMCCLK_MD); | ||
479 | pxa_gpio_mode(GPIO112_MMCCMD_MD); | ||
480 | pxa_gpio_mode(GPIO92_MMCDAT0_MD); | ||
481 | pxa_gpio_mode(GPIO109_MMCDAT1_MD); | ||
482 | pxa_gpio_mode(GPIO110_MMCDAT2_MD); | ||
483 | pxa_gpio_mode(GPIO111_MMCDAT3_MD); | ||
484 | |||
485 | /* SB-X270 uses GPIO105 as SD power enable */ | ||
486 | pxa_gpio_mode(105 | GPIO_OUT); | ||
487 | |||
488 | /* card detect IRQ on GPIO 83 */ | ||
489 | pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ)); | ||
490 | set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING); | ||
491 | |||
492 | err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int, | ||
493 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | ||
494 | "MMC card detect", data); | ||
495 | if (err) { | ||
496 | printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't" | ||
497 | " request MMC card detect IRQ\n"); | ||
498 | return -1; | ||
499 | } | ||
500 | |||
501 | return 0; | ||
502 | } | ||
503 | |||
504 | static void cmx270_mci_setpower(struct device *dev, unsigned int vdd) | ||
505 | { | ||
506 | struct pxamci_platform_data *p_d = dev->platform_data; | ||
507 | |||
508 | if ((1 << vdd) & p_d->ocr_mask) { | ||
509 | printk(KERN_DEBUG "%s: on\n", __FUNCTION__); | ||
510 | GPCR(105) = GPIO_bit(105); | ||
511 | } else { | ||
512 | GPSR(105) = GPIO_bit(105); | ||
513 | printk(KERN_DEBUG "%s: off\n", __FUNCTION__); | ||
514 | } | ||
515 | } | ||
516 | |||
517 | static void cmx270_mci_exit(struct device *dev, void *data) | ||
518 | { | ||
519 | free_irq(CMX270_MMC_IRQ, data); | ||
520 | } | ||
521 | |||
522 | static struct pxamci_platform_data cmx270_mci_platform_data = { | ||
523 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | ||
524 | .init = cmx270_mci_init, | ||
525 | .setpower = cmx270_mci_setpower, | ||
526 | .exit = cmx270_mci_exit, | ||
527 | }; | ||
528 | |||
529 | #ifdef CONFIG_PM | ||
530 | static unsigned long sleep_save_msc[10]; | ||
531 | |||
532 | static int cmx270_suspend(struct sys_device *dev, pm_message_t state) | ||
533 | { | ||
534 | cmx270_pci_suspend(); | ||
535 | |||
536 | /* save MSC registers */ | ||
537 | sleep_save_msc[0] = MSC0; | ||
538 | sleep_save_msc[1] = MSC1; | ||
539 | sleep_save_msc[2] = MSC2; | ||
540 | |||
541 | /* setup power saving mode registers */ | ||
542 | PCFR = 0x0; | ||
543 | PSLR = 0xff400000; | ||
544 | PMCR = 0x00000005; | ||
545 | PWER = 0x80000000; | ||
546 | PFER = 0x00000000; | ||
547 | PRER = 0x00000000; | ||
548 | PGSR0 = 0xC0018800; | ||
549 | PGSR1 = 0x004F0002; | ||
550 | PGSR2 = 0x6021C000; | ||
551 | PGSR3 = 0x00020000; | ||
552 | |||
553 | return 0; | ||
554 | } | ||
555 | |||
556 | static int cmx270_resume(struct sys_device *dev) | ||
557 | { | ||
558 | cmx270_pci_resume(); | ||
559 | |||
560 | /* restore MSC registers */ | ||
561 | MSC0 = sleep_save_msc[0]; | ||
562 | MSC1 = sleep_save_msc[1]; | ||
563 | MSC2 = sleep_save_msc[2]; | ||
564 | |||
565 | return 0; | ||
566 | } | ||
567 | |||
568 | static struct sysdev_class cmx270_pm_sysclass = { | ||
569 | set_kset_name("pm"), | ||
570 | .resume = cmx270_resume, | ||
571 | .suspend = cmx270_suspend, | ||
572 | }; | ||
573 | |||
574 | static struct sys_device cmx270_pm_device = { | ||
575 | .cls = &cmx270_pm_sysclass, | ||
576 | }; | ||
577 | |||
578 | static int __init cmx270_pm_init(void) | ||
579 | { | ||
580 | int error; | ||
581 | error = sysdev_class_register(&cmx270_pm_sysclass); | ||
582 | if (error == 0) | ||
583 | error = sysdev_register(&cmx270_pm_device); | ||
584 | return error; | ||
585 | } | ||
586 | #else | ||
587 | static int __init cmx270_pm_init(void) { return 0; } | ||
588 | #endif | ||
589 | |||
590 | static void __init cmx270_init(void) | ||
591 | { | ||
592 | cmx270_pm_init(); | ||
593 | |||
594 | set_pxa_fb_info(cmx270_display); | ||
595 | |||
596 | /* register CM-X270 platform devices */ | ||
597 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | ||
598 | |||
599 | /* set MCI and OHCI platform parameters */ | ||
600 | pxa_set_mci_info(&cmx270_mci_platform_data); | ||
601 | pxa_set_ohci_info(&cmx270_ohci_platform_data); | ||
602 | |||
603 | /* This enables the STUART */ | ||
604 | pxa_gpio_mode(GPIO46_STRXD_MD); | ||
605 | pxa_gpio_mode(GPIO47_STTXD_MD); | ||
606 | |||
607 | /* This enables the BTUART */ | ||
608 | pxa_gpio_mode(GPIO42_BTRXD_MD); | ||
609 | pxa_gpio_mode(GPIO43_BTTXD_MD); | ||
610 | pxa_gpio_mode(GPIO44_BTCTS_MD); | ||
611 | pxa_gpio_mode(GPIO45_BTRTS_MD); | ||
612 | } | ||
613 | |||
614 | static void __init cmx270_init_irq(void) | ||
615 | { | ||
616 | pxa27x_init_irq(); | ||
617 | |||
618 | |||
619 | cmx270_pci_init_irq(); | ||
620 | |||
621 | /* Setup interrupt for dm9000 */ | ||
622 | pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ)); | ||
623 | set_irq_type(CMX270_ETHIRQ, IRQT_RISING); | ||
624 | |||
625 | /* Setup interrupt for 2700G */ | ||
626 | pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ)); | ||
627 | set_irq_type(CMX270_GFXIRQ, IRQT_FALLING); | ||
628 | } | ||
629 | |||
630 | static void __init cmx270_map_io(void) | ||
631 | { | ||
632 | pxa_map_io(); | ||
633 | iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc)); | ||
634 | } | ||
635 | |||
636 | |||
637 | MACHINE_START(ARMCORE, "Compulab CM-x270") | ||
638 | .boot_params = 0xa0000100, | ||
639 | .phys_io = 0x40000000, | ||
640 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
641 | .map_io = cmx270_map_io, | ||
642 | .init_irq = cmx270_init_irq, | ||
643 | .timer = &pxa_timer, | ||
644 | .init_machine = cmx270_init, | ||
645 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 636fdb1c049c..94c8d5cdd60a 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h | |||
@@ -9,3 +9,6 @@ extern struct platform_device pxa_device_i2c; | |||
9 | extern struct platform_device pxa_device_i2s; | 9 | extern struct platform_device pxa_device_i2s; |
10 | extern struct platform_device pxa_device_ficp; | 10 | extern struct platform_device pxa_device_ficp; |
11 | extern struct platform_device pxa_device_rtc; | 11 | extern struct platform_device pxa_device_rtc; |
12 | |||
13 | extern struct platform_device pxa27x_device_i2c_power; | ||
14 | extern struct platform_device pxa27x_device_ohci; | ||
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 5510f6fdce55..1c34946ee16e 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
@@ -25,10 +25,6 @@ | |||
25 | #include <linux/pm.h> | 25 | #include <linux/pm.h> |
26 | #include <linux/string.h> | 26 | #include <linux/string.h> |
27 | 27 | ||
28 | #include <linux/sched.h> | ||
29 | #include <asm/cnt32_to_63.h> | ||
30 | #include <asm/div64.h> | ||
31 | |||
32 | #include <asm/hardware.h> | 28 | #include <asm/hardware.h> |
33 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
34 | #include <asm/system.h> | 30 | #include <asm/system.h> |
@@ -47,66 +43,39 @@ | |||
47 | #include "generic.h" | 43 | #include "generic.h" |
48 | 44 | ||
49 | /* | 45 | /* |
50 | * This is the PXA2xx sched_clock implementation. This has a resolution | 46 | * Get the clock frequency as reflected by CCCR and the turbo flag. |
51 | * of at least 308ns and a maximum value that depends on the value of | 47 | * We assume these values have been applied via a fcs. |
52 | * CLOCK_TICK_RATE. | 48 | * If info is not 0 we also display the current settings. |
53 | * | ||
54 | * The return value is guaranteed to be monotonic in that range as | ||
55 | * long as there is always less than 582 seconds between successive | ||
56 | * calls to this function. | ||
57 | */ | 49 | */ |
58 | unsigned long long sched_clock(void) | 50 | unsigned int get_clk_frequency_khz(int info) |
59 | { | 51 | { |
60 | unsigned long long v = cnt32_to_63(OSCR); | 52 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) |
61 | /* Note: top bit ov v needs cleared unless multiplier is even. */ | 53 | return pxa25x_get_clk_frequency_khz(info); |
62 | 54 | else if (cpu_is_pxa27x()) | |
63 | #if CLOCK_TICK_RATE == 3686400 | 55 | return pxa27x_get_clk_frequency_khz(info); |
64 | /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */ | 56 | else |
65 | /* The <<1 is used to get rid of tick.hi top bit */ | 57 | return pxa3xx_get_clk_frequency_khz(info); |
66 | v *= 78125<<1; | 58 | } |
67 | do_div(v, 288<<1); | 59 | EXPORT_SYMBOL(get_clk_frequency_khz); |
68 | #elif CLOCK_TICK_RATE == 3250000 | ||
69 | /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */ | ||
70 | v *= 4000; | ||
71 | do_div(v, 13); | ||
72 | #elif CLOCK_TICK_RATE == 3249600 | ||
73 | /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */ | ||
74 | v *= 625000; | ||
75 | do_div(v, 2031); | ||
76 | #else | ||
77 | #warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE" | ||
78 | /* | ||
79 | * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for | ||
80 | * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand | ||
81 | * years range and truncation to unsigned long long limits it to | ||
82 | * sched_clock's max range of ~584 years. This is nice but with | ||
83 | * higher computation cost. | ||
84 | */ | ||
85 | { | ||
86 | union { | ||
87 | unsigned long long val; | ||
88 | struct { unsigned long lo, hi; }; | ||
89 | } x; | ||
90 | unsigned long long y; | ||
91 | |||
92 | x.val = v; | ||
93 | x.hi &= 0x7fffffff; | ||
94 | y = (unsigned long long)x.lo * NSEC_PER_SEC; | ||
95 | x.lo = y; | ||
96 | y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC; | ||
97 | x.hi = do_div(y, CLOCK_TICK_RATE); | ||
98 | do_div(x.val, CLOCK_TICK_RATE); | ||
99 | x.hi += y; | ||
100 | v = x.val; | ||
101 | } | ||
102 | #endif | ||
103 | 60 | ||
104 | return v; | 61 | /* |
62 | * Return the current memory clock frequency in units of 10kHz | ||
63 | */ | ||
64 | unsigned int get_memclk_frequency_10khz(void) | ||
65 | { | ||
66 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) | ||
67 | return pxa25x_get_memclk_frequency_10khz(); | ||
68 | else if (cpu_is_pxa27x()) | ||
69 | return pxa27x_get_memclk_frequency_10khz(); | ||
70 | else | ||
71 | return pxa3xx_get_memclk_frequency_10khz(); | ||
105 | } | 72 | } |
73 | EXPORT_SYMBOL(get_memclk_frequency_10khz); | ||
106 | 74 | ||
107 | /* | 75 | /* |
108 | * Handy function to set GPIO alternate functions | 76 | * Handy function to set GPIO alternate functions |
109 | */ | 77 | */ |
78 | int pxa_last_gpio; | ||
110 | 79 | ||
111 | int pxa_gpio_mode(int gpio_mode) | 80 | int pxa_gpio_mode(int gpio_mode) |
112 | { | 81 | { |
@@ -115,7 +84,7 @@ int pxa_gpio_mode(int gpio_mode) | |||
115 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; | 84 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; |
116 | int gafr; | 85 | int gafr; |
117 | 86 | ||
118 | if (gpio > PXA_LAST_GPIO) | 87 | if (gpio > pxa_last_gpio) |
119 | return -EINVAL; | 88 | return -EINVAL; |
120 | 89 | ||
121 | local_irq_save(flags); | 90 | local_irq_save(flags); |
@@ -136,6 +105,44 @@ int pxa_gpio_mode(int gpio_mode) | |||
136 | 105 | ||
137 | EXPORT_SYMBOL(pxa_gpio_mode); | 106 | EXPORT_SYMBOL(pxa_gpio_mode); |
138 | 107 | ||
108 | int gpio_direction_input(unsigned gpio) | ||
109 | { | ||
110 | unsigned long flags; | ||
111 | u32 mask; | ||
112 | |||
113 | if (gpio > pxa_last_gpio) | ||
114 | return -EINVAL; | ||
115 | |||
116 | mask = GPIO_bit(gpio); | ||
117 | local_irq_save(flags); | ||
118 | GPDR(gpio) &= ~mask; | ||
119 | local_irq_restore(flags); | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | EXPORT_SYMBOL(gpio_direction_input); | ||
124 | |||
125 | int gpio_direction_output(unsigned gpio, int value) | ||
126 | { | ||
127 | unsigned long flags; | ||
128 | u32 mask; | ||
129 | |||
130 | if (gpio > pxa_last_gpio) | ||
131 | return -EINVAL; | ||
132 | |||
133 | mask = GPIO_bit(gpio); | ||
134 | local_irq_save(flags); | ||
135 | if (value) | ||
136 | GPSR(gpio) = mask; | ||
137 | else | ||
138 | GPCR(gpio) = mask; | ||
139 | GPDR(gpio) |= mask; | ||
140 | local_irq_restore(flags); | ||
141 | |||
142 | return 0; | ||
143 | } | ||
144 | EXPORT_SYMBOL(gpio_direction_output); | ||
145 | |||
139 | /* | 146 | /* |
140 | * Return GPIO level | 147 | * Return GPIO level |
141 | */ | 148 | */ |
@@ -159,7 +166,7 @@ EXPORT_SYMBOL(pxa_gpio_set_value); | |||
159 | /* | 166 | /* |
160 | * Routine to safely enable or disable a clock in the CKEN | 167 | * Routine to safely enable or disable a clock in the CKEN |
161 | */ | 168 | */ |
162 | void pxa_set_cken(int clock, int enable) | 169 | void __pxa_set_cken(int clock, int enable) |
163 | { | 170 | { |
164 | unsigned long flags; | 171 | unsigned long flags; |
165 | local_irq_save(flags); | 172 | local_irq_save(flags); |
@@ -172,7 +179,7 @@ void pxa_set_cken(int clock, int enable) | |||
172 | local_irq_restore(flags); | 179 | local_irq_restore(flags); |
173 | } | 180 | } |
174 | 181 | ||
175 | EXPORT_SYMBOL(pxa_set_cken); | 182 | EXPORT_SYMBOL(__pxa_set_cken); |
176 | 183 | ||
177 | /* | 184 | /* |
178 | * Intel PXA2xx internal register mapping. | 185 | * Intel PXA2xx internal register mapping. |
@@ -329,21 +336,80 @@ void __init set_pxa_fb_parent(struct device *parent_dev) | |||
329 | pxa_device_fb.dev.parent = parent_dev; | 336 | pxa_device_fb.dev.parent = parent_dev; |
330 | } | 337 | } |
331 | 338 | ||
339 | static struct resource pxa_resource_ffuart[] = { | ||
340 | { | ||
341 | .start = __PREG(FFUART), | ||
342 | .end = __PREG(FFUART) + 35, | ||
343 | .flags = IORESOURCE_MEM, | ||
344 | }, { | ||
345 | .start = IRQ_FFUART, | ||
346 | .end = IRQ_FFUART, | ||
347 | .flags = IORESOURCE_IRQ, | ||
348 | } | ||
349 | }; | ||
350 | |||
332 | struct platform_device pxa_device_ffuart= { | 351 | struct platform_device pxa_device_ffuart= { |
333 | .name = "pxa2xx-uart", | 352 | .name = "pxa2xx-uart", |
334 | .id = 0, | 353 | .id = 0, |
354 | .resource = pxa_resource_ffuart, | ||
355 | .num_resources = ARRAY_SIZE(pxa_resource_ffuart), | ||
335 | }; | 356 | }; |
357 | |||
358 | static struct resource pxa_resource_btuart[] = { | ||
359 | { | ||
360 | .start = __PREG(BTUART), | ||
361 | .end = __PREG(BTUART) + 35, | ||
362 | .flags = IORESOURCE_MEM, | ||
363 | }, { | ||
364 | .start = IRQ_BTUART, | ||
365 | .end = IRQ_BTUART, | ||
366 | .flags = IORESOURCE_IRQ, | ||
367 | } | ||
368 | }; | ||
369 | |||
336 | struct platform_device pxa_device_btuart = { | 370 | struct platform_device pxa_device_btuart = { |
337 | .name = "pxa2xx-uart", | 371 | .name = "pxa2xx-uart", |
338 | .id = 1, | 372 | .id = 1, |
373 | .resource = pxa_resource_btuart, | ||
374 | .num_resources = ARRAY_SIZE(pxa_resource_btuart), | ||
339 | }; | 375 | }; |
376 | |||
377 | static struct resource pxa_resource_stuart[] = { | ||
378 | { | ||
379 | .start = __PREG(STUART), | ||
380 | .end = __PREG(STUART) + 35, | ||
381 | .flags = IORESOURCE_MEM, | ||
382 | }, { | ||
383 | .start = IRQ_STUART, | ||
384 | .end = IRQ_STUART, | ||
385 | .flags = IORESOURCE_IRQ, | ||
386 | } | ||
387 | }; | ||
388 | |||
340 | struct platform_device pxa_device_stuart = { | 389 | struct platform_device pxa_device_stuart = { |
341 | .name = "pxa2xx-uart", | 390 | .name = "pxa2xx-uart", |
342 | .id = 2, | 391 | .id = 2, |
392 | .resource = pxa_resource_stuart, | ||
393 | .num_resources = ARRAY_SIZE(pxa_resource_stuart), | ||
343 | }; | 394 | }; |
395 | |||
396 | static struct resource pxa_resource_hwuart[] = { | ||
397 | { | ||
398 | .start = __PREG(HWUART), | ||
399 | .end = __PREG(HWUART) + 47, | ||
400 | .flags = IORESOURCE_MEM, | ||
401 | }, { | ||
402 | .start = IRQ_HWUART, | ||
403 | .end = IRQ_HWUART, | ||
404 | .flags = IORESOURCE_IRQ, | ||
405 | } | ||
406 | }; | ||
407 | |||
344 | struct platform_device pxa_device_hwuart = { | 408 | struct platform_device pxa_device_hwuart = { |
345 | .name = "pxa2xx-uart", | 409 | .name = "pxa2xx-uart", |
346 | .id = 3, | 410 | .id = 3, |
411 | .resource = pxa_resource_hwuart, | ||
412 | .num_resources = ARRAY_SIZE(pxa_resource_hwuart), | ||
347 | }; | 413 | }; |
348 | 414 | ||
349 | static struct resource pxai2c_resources[] = { | 415 | static struct resource pxai2c_resources[] = { |
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 91ab2ad8b34b..b30f240a16c7 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
@@ -15,14 +15,40 @@ extern struct sys_timer pxa_timer; | |||
15 | extern void __init pxa_init_irq_low(void); | 15 | extern void __init pxa_init_irq_low(void); |
16 | extern void __init pxa_init_irq_high(void); | 16 | extern void __init pxa_init_irq_high(void); |
17 | extern void __init pxa_init_irq_gpio(int gpio_nr); | 17 | extern void __init pxa_init_irq_gpio(int gpio_nr); |
18 | extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)); | ||
18 | extern void __init pxa25x_init_irq(void); | 19 | extern void __init pxa25x_init_irq(void); |
19 | extern void __init pxa27x_init_irq(void); | 20 | extern void __init pxa27x_init_irq(void); |
21 | extern void __init pxa3xx_init_irq(void); | ||
20 | extern void __init pxa_map_io(void); | 22 | extern void __init pxa_map_io(void); |
21 | 23 | ||
22 | extern unsigned int get_clk_frequency_khz(int info); | 24 | extern unsigned int get_clk_frequency_khz(int info); |
25 | extern int pxa_last_gpio; | ||
23 | 26 | ||
24 | #define SET_BANK(__nr,__start,__size) \ | 27 | #define SET_BANK(__nr,__start,__size) \ |
25 | mi->bank[__nr].start = (__start), \ | 28 | mi->bank[__nr].start = (__start), \ |
26 | mi->bank[__nr].size = (__size), \ | 29 | mi->bank[__nr].size = (__size), \ |
27 | mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) | 30 | mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) |
28 | 31 | ||
32 | #ifdef CONFIG_PXA25x | ||
33 | extern unsigned pxa25x_get_clk_frequency_khz(int); | ||
34 | extern unsigned pxa25x_get_memclk_frequency_10khz(void); | ||
35 | #else | ||
36 | #define pxa25x_get_clk_frequency_khz(x) (0) | ||
37 | #define pxa25x_get_memclk_frequency_10khz() (0) | ||
38 | #endif | ||
39 | |||
40 | #ifdef CONFIG_PXA27x | ||
41 | extern unsigned pxa27x_get_clk_frequency_khz(int); | ||
42 | extern unsigned pxa27x_get_memclk_frequency_10khz(void); | ||
43 | #else | ||
44 | #define pxa27x_get_clk_frequency_khz(x) (0) | ||
45 | #define pxa27x_get_memclk_frequency_10khz() (0) | ||
46 | #endif | ||
47 | |||
48 | #ifdef CONFIG_PXA3xx | ||
49 | extern unsigned pxa3xx_get_clk_frequency_khz(int); | ||
50 | extern unsigned pxa3xx_get_memclk_frequency_10khz(void); | ||
51 | #else | ||
52 | #define pxa3xx_get_clk_frequency_khz(x) (0) | ||
53 | #define pxa3xx_get_memclk_frequency_10khz() (0) | ||
54 | #endif | ||
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index ae2ae08032d7..07acb45b16ea 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -38,33 +38,11 @@ static void pxa_unmask_low_irq(unsigned int irq) | |||
38 | ICMR |= (1 << irq); | 38 | ICMR |= (1 << irq); |
39 | } | 39 | } |
40 | 40 | ||
41 | static int pxa_set_wake(unsigned int irq, unsigned int on) | ||
42 | { | ||
43 | u32 mask; | ||
44 | |||
45 | switch (irq) { | ||
46 | case IRQ_RTCAlrm: | ||
47 | mask = PWER_RTC; | ||
48 | break; | ||
49 | #ifdef CONFIG_PXA27x | ||
50 | /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */ | ||
51 | #endif | ||
52 | default: | ||
53 | return -EINVAL; | ||
54 | } | ||
55 | if (on) | ||
56 | PWER |= mask; | ||
57 | else | ||
58 | PWER &= ~mask; | ||
59 | return 0; | ||
60 | } | ||
61 | |||
62 | static struct irq_chip pxa_internal_chip_low = { | 41 | static struct irq_chip pxa_internal_chip_low = { |
63 | .name = "SC", | 42 | .name = "SC", |
64 | .ack = pxa_mask_low_irq, | 43 | .ack = pxa_mask_low_irq, |
65 | .mask = pxa_mask_low_irq, | 44 | .mask = pxa_mask_low_irq, |
66 | .unmask = pxa_unmask_low_irq, | 45 | .unmask = pxa_unmask_low_irq, |
67 | .set_wake = pxa_set_wake, | ||
68 | }; | 46 | }; |
69 | 47 | ||
70 | void __init pxa_init_irq_low(void) | 48 | void __init pxa_init_irq_low(void) |
@@ -87,7 +65,7 @@ void __init pxa_init_irq_low(void) | |||
87 | } | 65 | } |
88 | } | 66 | } |
89 | 67 | ||
90 | #ifdef CONFIG_PXA27x | 68 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
91 | 69 | ||
92 | /* | 70 | /* |
93 | * This is for the second set of internal IRQs as found on the PXA27x. | 71 | * This is for the second set of internal IRQs as found on the PXA27x. |
@@ -125,26 +103,6 @@ void __init pxa_init_irq_high(void) | |||
125 | } | 103 | } |
126 | #endif | 104 | #endif |
127 | 105 | ||
128 | /* Note that if an input/irq line ever gets changed to an output during | ||
129 | * suspend, the relevant PWER, PRER, and PFER bits should be cleared. | ||
130 | */ | ||
131 | #ifdef CONFIG_PXA27x | ||
132 | |||
133 | /* PXA27x: Various gpios can issue wakeup events. This logic only | ||
134 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | ||
135 | */ | ||
136 | #define PXA27x_GPIO_NOWAKE_MASK \ | ||
137 | ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) | ||
138 | #define WAKEMASK(gpio) \ | ||
139 | (((gpio) <= 15) \ | ||
140 | ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ | ||
141 | : ((gpio == 35) ? (1 << 24) : 0)) | ||
142 | #else | ||
143 | |||
144 | /* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */ | ||
145 | #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0) | ||
146 | #endif | ||
147 | |||
148 | /* | 106 | /* |
149 | * PXA GPIO edge detection for IRQs: | 107 | * PXA GPIO edge detection for IRQs: |
150 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | 108 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. |
@@ -158,11 +116,9 @@ static long GPIO_IRQ_mask[4]; | |||
158 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | 116 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) |
159 | { | 117 | { |
160 | int gpio, idx; | 118 | int gpio, idx; |
161 | u32 mask; | ||
162 | 119 | ||
163 | gpio = IRQ_TO_GPIO(irq); | 120 | gpio = IRQ_TO_GPIO(irq); |
164 | idx = gpio >> 5; | 121 | idx = gpio >> 5; |
165 | mask = WAKEMASK(gpio); | ||
166 | 122 | ||
167 | if (type == IRQT_PROBE) { | 123 | if (type == IRQT_PROBE) { |
168 | /* Don't mess with enabled GPIOs using preconfigured edges or | 124 | /* Don't mess with enabled GPIOs using preconfigured edges or |
@@ -182,19 +138,15 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | |||
182 | if (type & __IRQT_RISEDGE) { | 138 | if (type & __IRQT_RISEDGE) { |
183 | /* printk("rising "); */ | 139 | /* printk("rising "); */ |
184 | __set_bit (gpio, GPIO_IRQ_rising_edge); | 140 | __set_bit (gpio, GPIO_IRQ_rising_edge); |
185 | PRER |= mask; | ||
186 | } else { | 141 | } else { |
187 | __clear_bit (gpio, GPIO_IRQ_rising_edge); | 142 | __clear_bit (gpio, GPIO_IRQ_rising_edge); |
188 | PRER &= ~mask; | ||
189 | } | 143 | } |
190 | 144 | ||
191 | if (type & __IRQT_FALEDGE) { | 145 | if (type & __IRQT_FALEDGE) { |
192 | /* printk("falling "); */ | 146 | /* printk("falling "); */ |
193 | __set_bit (gpio, GPIO_IRQ_falling_edge); | 147 | __set_bit (gpio, GPIO_IRQ_falling_edge); |
194 | PFER |= mask; | ||
195 | } else { | 148 | } else { |
196 | __clear_bit (gpio, GPIO_IRQ_falling_edge); | 149 | __clear_bit (gpio, GPIO_IRQ_falling_edge); |
197 | PFER &= ~mask; | ||
198 | } | 150 | } |
199 | 151 | ||
200 | /* printk("edges\n"); */ | 152 | /* printk("edges\n"); */ |
@@ -213,29 +165,12 @@ static void pxa_ack_low_gpio(unsigned int irq) | |||
213 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | 165 | GEDR0 = (1 << (irq - IRQ_GPIO0)); |
214 | } | 166 | } |
215 | 167 | ||
216 | static int pxa_set_gpio_wake(unsigned int irq, unsigned int on) | ||
217 | { | ||
218 | int gpio = IRQ_TO_GPIO(irq); | ||
219 | u32 mask = WAKEMASK(gpio); | ||
220 | |||
221 | if (!mask) | ||
222 | return -EINVAL; | ||
223 | |||
224 | if (on) | ||
225 | PWER |= mask; | ||
226 | else | ||
227 | PWER &= ~mask; | ||
228 | return 0; | ||
229 | } | ||
230 | |||
231 | |||
232 | static struct irq_chip pxa_low_gpio_chip = { | 168 | static struct irq_chip pxa_low_gpio_chip = { |
233 | .name = "GPIO-l", | 169 | .name = "GPIO-l", |
234 | .ack = pxa_ack_low_gpio, | 170 | .ack = pxa_ack_low_gpio, |
235 | .mask = pxa_mask_low_irq, | 171 | .mask = pxa_mask_low_irq, |
236 | .unmask = pxa_unmask_low_irq, | 172 | .unmask = pxa_unmask_low_irq, |
237 | .set_type = pxa_gpio_irq_type, | 173 | .set_type = pxa_gpio_irq_type, |
238 | .set_wake = pxa_set_gpio_wake, | ||
239 | }; | 174 | }; |
240 | 175 | ||
241 | /* | 176 | /* |
@@ -342,13 +277,14 @@ static struct irq_chip pxa_muxed_gpio_chip = { | |||
342 | .mask = pxa_mask_muxed_gpio, | 277 | .mask = pxa_mask_muxed_gpio, |
343 | .unmask = pxa_unmask_muxed_gpio, | 278 | .unmask = pxa_unmask_muxed_gpio, |
344 | .set_type = pxa_gpio_irq_type, | 279 | .set_type = pxa_gpio_irq_type, |
345 | .set_wake = pxa_set_gpio_wake, | ||
346 | }; | 280 | }; |
347 | 281 | ||
348 | void __init pxa_init_irq_gpio(int gpio_nr) | 282 | void __init pxa_init_irq_gpio(int gpio_nr) |
349 | { | 283 | { |
350 | int irq, i; | 284 | int irq, i; |
351 | 285 | ||
286 | pxa_last_gpio = gpio_nr - 1; | ||
287 | |||
352 | /* clear all GPIO edge detects */ | 288 | /* clear all GPIO edge detects */ |
353 | for (i = 0; i < gpio_nr; i += 32) { | 289 | for (i = 0; i < gpio_nr; i += 32) { |
354 | GFER(i) = 0; | 290 | GFER(i) = 0; |
@@ -375,3 +311,13 @@ void __init pxa_init_irq_gpio(int gpio_nr) | |||
375 | set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); | 311 | set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); |
376 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | 312 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); |
377 | } | 313 | } |
314 | |||
315 | void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) | ||
316 | { | ||
317 | pxa_internal_chip_low.set_wake = set_wake; | ||
318 | #ifdef CONFIG_PXA27x | ||
319 | pxa_internal_chip_high.set_wake = set_wake; | ||
320 | #endif | ||
321 | pxa_low_gpio_chip.set_wake = set_wake; | ||
322 | pxa_muxed_gpio_chip.set_wake = set_wake; | ||
323 | } | ||
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index e70048fd00a5..011a1a72b61c 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
@@ -512,6 +512,25 @@ static void __init lubbock_map_io(void) | |||
512 | pxa_gpio_mode(GPIO44_BTCTS_MD); | 512 | pxa_gpio_mode(GPIO44_BTCTS_MD); |
513 | pxa_gpio_mode(GPIO45_BTRTS_MD); | 513 | pxa_gpio_mode(GPIO45_BTRTS_MD); |
514 | 514 | ||
515 | GPSR(GPIO48_nPOE) = | ||
516 | GPIO_bit(GPIO48_nPOE) | | ||
517 | GPIO_bit(GPIO49_nPWE) | | ||
518 | GPIO_bit(GPIO50_nPIOR) | | ||
519 | GPIO_bit(GPIO51_nPIOW) | | ||
520 | GPIO_bit(GPIO52_nPCE_1) | | ||
521 | GPIO_bit(GPIO53_nPCE_2); | ||
522 | |||
523 | pxa_gpio_mode(GPIO48_nPOE_MD); | ||
524 | pxa_gpio_mode(GPIO49_nPWE_MD); | ||
525 | pxa_gpio_mode(GPIO50_nPIOR_MD); | ||
526 | pxa_gpio_mode(GPIO51_nPIOW_MD); | ||
527 | pxa_gpio_mode(GPIO52_nPCE_1_MD); | ||
528 | pxa_gpio_mode(GPIO53_nPCE_2_MD); | ||
529 | pxa_gpio_mode(GPIO54_pSKTSEL_MD); | ||
530 | pxa_gpio_mode(GPIO55_nPREG_MD); | ||
531 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | ||
532 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | ||
533 | |||
515 | /* This is for the SMC chip select */ | 534 | /* This is for the SMC chip select */ |
516 | pxa_gpio_mode(GPIO79_nCS_3_MD); | 535 | pxa_gpio_mode(GPIO79_nCS_3_MD); |
517 | 536 | ||
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index b02c79c7e6a3..a4bc3483cbb3 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
@@ -444,6 +444,25 @@ static void __init mainstone_init(void) | |||
444 | */ | 444 | */ |
445 | pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); | 445 | pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); |
446 | 446 | ||
447 | GPSR(GPIO48_nPOE) = | ||
448 | GPIO_bit(GPIO48_nPOE) | | ||
449 | GPIO_bit(GPIO49_nPWE) | | ||
450 | GPIO_bit(GPIO50_nPIOR) | | ||
451 | GPIO_bit(GPIO51_nPIOW) | | ||
452 | GPIO_bit(GPIO85_nPCE_1) | | ||
453 | GPIO_bit(GPIO54_nPCE_2); | ||
454 | |||
455 | pxa_gpio_mode(GPIO48_nPOE_MD); | ||
456 | pxa_gpio_mode(GPIO49_nPWE_MD); | ||
457 | pxa_gpio_mode(GPIO50_nPIOR_MD); | ||
458 | pxa_gpio_mode(GPIO51_nPIOW_MD); | ||
459 | pxa_gpio_mode(GPIO85_nPCE_1_MD); | ||
460 | pxa_gpio_mode(GPIO54_nPCE_2_MD); | ||
461 | pxa_gpio_mode(GPIO79_pSKTSEL_MD); | ||
462 | pxa_gpio_mode(GPIO55_nPREG_MD); | ||
463 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | ||
464 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | ||
465 | |||
447 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 466 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
448 | 467 | ||
449 | /* reading Mainstone's "Virtual Configuration Register" | 468 | /* reading Mainstone's "Virtual Configuration Register" |
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c new file mode 100644 index 000000000000..5cd3cadbbd10 --- /dev/null +++ b/arch/arm/mach-pxa/mfp.c | |||
@@ -0,0 +1,235 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/mfp.c | ||
3 | * | ||
4 | * PXA3xx Multi-Function Pin Support | ||
5 | * | ||
6 | * Copyright (C) 2007 Marvell Internation Ltd. | ||
7 | * | ||
8 | * 2007-08-21: eric miao <eric.y.miao@gmail.com> | ||
9 | * initial version | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <asm/hardware.h> | ||
22 | #include <asm/arch/mfp.h> | ||
23 | |||
24 | /* mfp_spin_lock is used to ensure that MFP register configuration | ||
25 | * (most likely a read-modify-write operation) is atomic, and that | ||
26 | * mfp_table[] is consistent | ||
27 | */ | ||
28 | static DEFINE_SPINLOCK(mfp_spin_lock); | ||
29 | |||
30 | static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE); | ||
31 | static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; | ||
32 | |||
33 | #define mfpr_readl(off) \ | ||
34 | __raw_readl(mfpr_mmio_base + (off)) | ||
35 | |||
36 | #define mfpr_writel(off, val) \ | ||
37 | __raw_writel(val, mfpr_mmio_base + (off)) | ||
38 | |||
39 | /* | ||
40 | * perform a read-back of any MFPR register to make sure the | ||
41 | * previous writings are finished | ||
42 | */ | ||
43 | #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) | ||
44 | |||
45 | static inline void __mfp_config(int pin, unsigned long val) | ||
46 | { | ||
47 | unsigned long off = mfp_table[pin].mfpr_off; | ||
48 | |||
49 | mfp_table[pin].mfpr_val = val; | ||
50 | mfpr_writel(off, val); | ||
51 | } | ||
52 | |||
53 | void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num) | ||
54 | { | ||
55 | int i, pin; | ||
56 | unsigned long val, flags; | ||
57 | mfp_cfg_t *mfp_cfg = mfp_cfgs; | ||
58 | |||
59 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
60 | |||
61 | for (i = 0; i < num; i++, mfp_cfg++) { | ||
62 | pin = MFP_CFG_PIN(*mfp_cfg); | ||
63 | val = MFP_CFG_VAL(*mfp_cfg); | ||
64 | |||
65 | BUG_ON(pin >= MFP_PIN_MAX); | ||
66 | |||
67 | __mfp_config(pin, val); | ||
68 | } | ||
69 | |||
70 | mfpr_sync(); | ||
71 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
72 | } | ||
73 | |||
74 | unsigned long pxa3xx_mfp_read(int mfp) | ||
75 | { | ||
76 | unsigned long val, flags; | ||
77 | |||
78 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
79 | |||
80 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
81 | val = mfpr_readl(mfp_table[mfp].mfpr_off); | ||
82 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
83 | |||
84 | return val; | ||
85 | } | ||
86 | |||
87 | void pxa3xx_mfp_write(int mfp, unsigned long val) | ||
88 | { | ||
89 | unsigned long flags; | ||
90 | |||
91 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
92 | |||
93 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
94 | mfpr_writel(mfp_table[mfp].mfpr_off, val); | ||
95 | mfpr_sync(); | ||
96 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
97 | } | ||
98 | |||
99 | void pxa3xx_mfp_set_afds(int mfp, int af, int ds) | ||
100 | { | ||
101 | uint32_t mfpr_off, mfpr_val; | ||
102 | unsigned long flags; | ||
103 | |||
104 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
105 | |||
106 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
107 | mfpr_off = mfp_table[mfp].mfpr_off; | ||
108 | |||
109 | mfpr_val = mfpr_readl(mfpr_off); | ||
110 | mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK); | ||
111 | mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) | | ||
112 | ((ds & 0x7) << MFPR_DRV_OFFSET)); | ||
113 | |||
114 | mfpr_writel(mfpr_off, mfpr_val); | ||
115 | mfpr_sync(); | ||
116 | |||
117 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
118 | } | ||
119 | |||
120 | void pxa3xx_mfp_set_rdh(int mfp, int rdh) | ||
121 | { | ||
122 | uint32_t mfpr_off, mfpr_val; | ||
123 | unsigned long flags; | ||
124 | |||
125 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
126 | |||
127 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
128 | |||
129 | mfpr_off = mfp_table[mfp].mfpr_off; | ||
130 | |||
131 | mfpr_val = mfpr_readl(mfpr_off); | ||
132 | mfpr_val &= ~MFPR_RDH_MASK; | ||
133 | |||
134 | if (likely(rdh)) | ||
135 | mfpr_val |= (1u << MFPR_SS_OFFSET); | ||
136 | |||
137 | mfpr_writel(mfpr_off, mfpr_val); | ||
138 | mfpr_sync(); | ||
139 | |||
140 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
141 | } | ||
142 | |||
143 | void pxa3xx_mfp_set_lpm(int mfp, int lpm) | ||
144 | { | ||
145 | uint32_t mfpr_off, mfpr_val; | ||
146 | unsigned long flags; | ||
147 | |||
148 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
149 | |||
150 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
151 | |||
152 | mfpr_off = mfp_table[mfp].mfpr_off; | ||
153 | mfpr_val = mfpr_readl(mfpr_off); | ||
154 | mfpr_val &= ~MFPR_LPM_MASK; | ||
155 | |||
156 | if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET; | ||
157 | if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET; | ||
158 | if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET; | ||
159 | if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET; | ||
160 | if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET; | ||
161 | |||
162 | mfpr_writel(mfpr_off, mfpr_val); | ||
163 | mfpr_sync(); | ||
164 | |||
165 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
166 | } | ||
167 | |||
168 | void pxa3xx_mfp_set_pull(int mfp, int pull) | ||
169 | { | ||
170 | uint32_t mfpr_off, mfpr_val; | ||
171 | unsigned long flags; | ||
172 | |||
173 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
174 | |||
175 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
176 | |||
177 | mfpr_off = mfp_table[mfp].mfpr_off; | ||
178 | mfpr_val = mfpr_readl(mfpr_off); | ||
179 | mfpr_val &= ~MFPR_PULL_MASK; | ||
180 | mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET); | ||
181 | |||
182 | mfpr_writel(mfpr_off, mfpr_val); | ||
183 | mfpr_sync(); | ||
184 | |||
185 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
186 | } | ||
187 | |||
188 | void pxa3xx_mfp_set_edge(int mfp, int edge) | ||
189 | { | ||
190 | uint32_t mfpr_off, mfpr_val; | ||
191 | unsigned long flags; | ||
192 | |||
193 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
194 | |||
195 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
196 | |||
197 | mfpr_off = mfp_table[mfp].mfpr_off; | ||
198 | mfpr_val = mfpr_readl(mfpr_off); | ||
199 | |||
200 | mfpr_val &= ~MFPR_EDGE_MASK; | ||
201 | mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET; | ||
202 | mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET; | ||
203 | |||
204 | mfpr_writel(mfpr_off, mfpr_val); | ||
205 | mfpr_sync(); | ||
206 | |||
207 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
208 | } | ||
209 | |||
210 | void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) | ||
211 | { | ||
212 | struct pxa3xx_mfp_addr_map *p; | ||
213 | unsigned long offset, flags; | ||
214 | int i; | ||
215 | |||
216 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
217 | |||
218 | for (p = map; p->start != MFP_PIN_INVALID; p++) { | ||
219 | offset = p->offset; | ||
220 | i = p->start; | ||
221 | |||
222 | do { | ||
223 | mfp_table[i].mfpr_off = offset; | ||
224 | mfp_table[i].mfpr_val = 0; | ||
225 | offset += 4; i++; | ||
226 | } while ((i <= p->end) && (p->end != -1)); | ||
227 | } | ||
228 | |||
229 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
230 | } | ||
231 | |||
232 | void __init pxa3xx_init_mfp(void) | ||
233 | { | ||
234 | memset(mfp_table, 0, sizeof(mfp_table)); | ||
235 | } | ||
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 6dfcca72e90f..0d6a72504caa 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
@@ -30,6 +30,7 @@ | |||
30 | 30 | ||
31 | #include "generic.h" | 31 | #include "generic.h" |
32 | #include "devices.h" | 32 | #include "devices.h" |
33 | #include "clock.h" | ||
33 | 34 | ||
34 | /* | 35 | /* |
35 | * Various clock factors driven by the CCCR register. | 36 | * Various clock factors driven by the CCCR register. |
@@ -53,7 +54,7 @@ static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; | |||
53 | * We assume these values have been applied via a fcs. | 54 | * We assume these values have been applied via a fcs. |
54 | * If info is not 0 we also display the current settings. | 55 | * If info is not 0 we also display the current settings. |
55 | */ | 56 | */ |
56 | unsigned int get_clk_frequency_khz(int info) | 57 | unsigned int pxa25x_get_clk_frequency_khz(int info) |
57 | { | 58 | { |
58 | unsigned long cccr, turbo; | 59 | unsigned long cccr, turbo; |
59 | unsigned int l, L, m, M, n2, N; | 60 | unsigned int l, L, m, M, n2, N; |
@@ -86,27 +87,48 @@ unsigned int get_clk_frequency_khz(int info) | |||
86 | return (turbo & 1) ? (N/1000) : (M/1000); | 87 | return (turbo & 1) ? (N/1000) : (M/1000); |
87 | } | 88 | } |
88 | 89 | ||
89 | EXPORT_SYMBOL(get_clk_frequency_khz); | ||
90 | |||
91 | /* | 90 | /* |
92 | * Return the current memory clock frequency in units of 10kHz | 91 | * Return the current memory clock frequency in units of 10kHz |
93 | */ | 92 | */ |
94 | unsigned int get_memclk_frequency_10khz(void) | 93 | unsigned int pxa25x_get_memclk_frequency_10khz(void) |
95 | { | 94 | { |
96 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; | 95 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; |
97 | } | 96 | } |
98 | 97 | ||
99 | EXPORT_SYMBOL(get_memclk_frequency_10khz); | 98 | static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) |
100 | |||
101 | /* | ||
102 | * Return the current LCD clock frequency in units of 10kHz | ||
103 | */ | ||
104 | unsigned int get_lcdclk_frequency_10khz(void) | ||
105 | { | 99 | { |
106 | return get_memclk_frequency_10khz(); | 100 | return pxa25x_get_memclk_frequency_10khz() * 10000; |
107 | } | 101 | } |
108 | 102 | ||
109 | EXPORT_SYMBOL(get_lcdclk_frequency_10khz); | 103 | static const struct clkops clk_pxa25x_lcd_ops = { |
104 | .enable = clk_cken_enable, | ||
105 | .disable = clk_cken_disable, | ||
106 | .getrate = clk_pxa25x_lcd_getrate, | ||
107 | }; | ||
108 | |||
109 | /* | ||
110 | * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) | ||
111 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz | ||
112 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) | ||
113 | */ | ||
114 | static struct clk pxa25x_clks[] = { | ||
115 | INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), | ||
116 | INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), | ||
117 | INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), | ||
118 | INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), | ||
119 | INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), | ||
120 | INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), | ||
121 | INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), | ||
122 | INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), | ||
123 | /* | ||
124 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), | ||
125 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), | ||
126 | INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL), | ||
127 | INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), | ||
128 | INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL), | ||
129 | */ | ||
130 | INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), | ||
131 | }; | ||
110 | 132 | ||
111 | #ifdef CONFIG_PM | 133 | #ifdef CONFIG_PM |
112 | 134 | ||
@@ -205,10 +227,52 @@ static void __init pxa25x_init_pm(void) | |||
205 | } | 227 | } |
206 | #endif | 228 | #endif |
207 | 229 | ||
230 | /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm | ||
231 | */ | ||
232 | |||
233 | static int pxa25x_set_wake(unsigned int irq, unsigned int on) | ||
234 | { | ||
235 | int gpio = IRQ_TO_GPIO(irq); | ||
236 | uint32_t gpio_bit, mask = 0; | ||
237 | |||
238 | if (gpio >= 0 && gpio <= 15) { | ||
239 | gpio_bit = GPIO_bit(gpio); | ||
240 | mask = gpio_bit; | ||
241 | if (on) { | ||
242 | if (GRER(gpio) | gpio_bit) | ||
243 | PRER |= gpio_bit; | ||
244 | else | ||
245 | PRER &= ~gpio_bit; | ||
246 | |||
247 | if (GFER(gpio) | gpio_bit) | ||
248 | PFER |= gpio_bit; | ||
249 | else | ||
250 | PFER &= ~gpio_bit; | ||
251 | } | ||
252 | goto set_pwer; | ||
253 | } | ||
254 | |||
255 | if (irq == IRQ_RTCAlrm) { | ||
256 | mask = PWER_RTC; | ||
257 | goto set_pwer; | ||
258 | } | ||
259 | |||
260 | return -EINVAL; | ||
261 | |||
262 | set_pwer: | ||
263 | if (on) | ||
264 | PWER |= mask; | ||
265 | else | ||
266 | PWER &=~mask; | ||
267 | |||
268 | return 0; | ||
269 | } | ||
270 | |||
208 | void __init pxa25x_init_irq(void) | 271 | void __init pxa25x_init_irq(void) |
209 | { | 272 | { |
210 | pxa_init_irq_low(); | 273 | pxa_init_irq_low(); |
211 | pxa_init_irq_gpio(85); | 274 | pxa_init_irq_gpio(85); |
275 | pxa_init_irq_set_wake(pxa25x_set_wake); | ||
212 | } | 276 | } |
213 | 277 | ||
214 | static struct platform_device *pxa25x_devices[] __initdata = { | 278 | static struct platform_device *pxa25x_devices[] __initdata = { |
@@ -229,6 +293,8 @@ static int __init pxa25x_init(void) | |||
229 | int ret = 0; | 293 | int ret = 0; |
230 | 294 | ||
231 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) { | 295 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) { |
296 | clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); | ||
297 | |||
232 | if ((ret = pxa_init_dma(16))) | 298 | if ((ret = pxa_init_dma(16))) |
233 | return ret; | 299 | return ret; |
234 | #ifdef CONFIG_PM | 300 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 203371ab19db..2d7fc39732e4 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
@@ -27,6 +27,7 @@ | |||
27 | 27 | ||
28 | #include "generic.h" | 28 | #include "generic.h" |
29 | #include "devices.h" | 29 | #include "devices.h" |
30 | #include "clock.h" | ||
30 | 31 | ||
31 | /* Crystal clock: 13MHz */ | 32 | /* Crystal clock: 13MHz */ |
32 | #define BASE_CLK 13000000 | 33 | #define BASE_CLK 13000000 |
@@ -36,7 +37,7 @@ | |||
36 | * We assume these values have been applied via a fcs. | 37 | * We assume these values have been applied via a fcs. |
37 | * If info is not 0 we also display the current settings. | 38 | * If info is not 0 we also display the current settings. |
38 | */ | 39 | */ |
39 | unsigned int get_clk_frequency_khz( int info) | 40 | unsigned int pxa27x_get_clk_frequency_khz(int info) |
40 | { | 41 | { |
41 | unsigned long ccsr, clkcfg; | 42 | unsigned long ccsr, clkcfg; |
42 | unsigned int l, L, m, M, n2, N, S; | 43 | unsigned int l, L, m, M, n2, N, S; |
@@ -79,7 +80,7 @@ unsigned int get_clk_frequency_khz( int info) | |||
79 | * Return the current mem clock frequency in units of 10kHz as | 80 | * Return the current mem clock frequency in units of 10kHz as |
80 | * reflected by CCCR[A], B, and L | 81 | * reflected by CCCR[A], B, and L |
81 | */ | 82 | */ |
82 | unsigned int get_memclk_frequency_10khz(void) | 83 | unsigned int pxa27x_get_memclk_frequency_10khz(void) |
83 | { | 84 | { |
84 | unsigned long ccsr, clkcfg; | 85 | unsigned long ccsr, clkcfg; |
85 | unsigned int l, L, m, M; | 86 | unsigned int l, L, m, M; |
@@ -104,7 +105,7 @@ unsigned int get_memclk_frequency_10khz(void) | |||
104 | /* | 105 | /* |
105 | * Return the current LCD clock frequency in units of 10kHz as | 106 | * Return the current LCD clock frequency in units of 10kHz as |
106 | */ | 107 | */ |
107 | unsigned int get_lcdclk_frequency_10khz(void) | 108 | static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) |
108 | { | 109 | { |
109 | unsigned long ccsr; | 110 | unsigned long ccsr; |
110 | unsigned int l, L, k, K; | 111 | unsigned int l, L, k, K; |
@@ -120,9 +121,47 @@ unsigned int get_lcdclk_frequency_10khz(void) | |||
120 | return (K / 10000); | 121 | return (K / 10000); |
121 | } | 122 | } |
122 | 123 | ||
123 | EXPORT_SYMBOL(get_clk_frequency_khz); | 124 | static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) |
124 | EXPORT_SYMBOL(get_memclk_frequency_10khz); | 125 | { |
125 | EXPORT_SYMBOL(get_lcdclk_frequency_10khz); | 126 | return pxa27x_get_lcdclk_frequency_10khz() * 10000; |
127 | } | ||
128 | |||
129 | static const struct clkops clk_pxa27x_lcd_ops = { | ||
130 | .enable = clk_cken_enable, | ||
131 | .disable = clk_cken_disable, | ||
132 | .getrate = clk_pxa27x_lcd_getrate, | ||
133 | }; | ||
134 | |||
135 | static struct clk pxa27x_clks[] = { | ||
136 | INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), | ||
137 | INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), | ||
138 | |||
139 | INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), | ||
140 | INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | ||
141 | INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), | ||
142 | |||
143 | INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), | ||
144 | INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), | ||
145 | INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev), | ||
146 | INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), | ||
147 | INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), | ||
148 | |||
149 | INIT_CKEN("USBCLK", USB, 48000000, 0, &pxa27x_device_ohci.dev), | ||
150 | INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), | ||
151 | INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), | ||
152 | |||
153 | /* | ||
154 | INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), | ||
155 | INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL), | ||
156 | INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL), | ||
157 | INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL), | ||
158 | INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), | ||
159 | INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), | ||
160 | INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), | ||
161 | INIT_CKEN("IMCLK", IM, 0, 0, NULL), | ||
162 | INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), | ||
163 | */ | ||
164 | }; | ||
126 | 165 | ||
127 | #ifdef CONFIG_PM | 166 | #ifdef CONFIG_PM |
128 | 167 | ||
@@ -267,6 +306,69 @@ static void __init pxa27x_init_pm(void) | |||
267 | } | 306 | } |
268 | #endif | 307 | #endif |
269 | 308 | ||
309 | /* PXA27x: Various gpios can issue wakeup events. This logic only | ||
310 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | ||
311 | */ | ||
312 | #define PXA27x_GPIO_NOWAKE_MASK \ | ||
313 | ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) | ||
314 | #define WAKEMASK(gpio) \ | ||
315 | (((gpio) <= 15) \ | ||
316 | ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ | ||
317 | : ((gpio == 35) ? (1 << 24) : 0)) | ||
318 | |||
319 | static int pxa27x_set_wake(unsigned int irq, unsigned int on) | ||
320 | { | ||
321 | int gpio = IRQ_TO_GPIO(irq); | ||
322 | uint32_t mask; | ||
323 | |||
324 | if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) { | ||
325 | if (WAKEMASK(gpio) == 0) | ||
326 | return -EINVAL; | ||
327 | |||
328 | mask = WAKEMASK(gpio); | ||
329 | |||
330 | if (on) { | ||
331 | if (GRER(gpio) | GPIO_bit(gpio)) | ||
332 | PRER |= mask; | ||
333 | else | ||
334 | PRER &= ~mask; | ||
335 | |||
336 | if (GFER(gpio) | GPIO_bit(gpio)) | ||
337 | PFER |= mask; | ||
338 | else | ||
339 | PFER &= ~mask; | ||
340 | } | ||
341 | goto set_pwer; | ||
342 | } | ||
343 | |||
344 | switch (irq) { | ||
345 | case IRQ_RTCAlrm: | ||
346 | mask = PWER_RTC; | ||
347 | break; | ||
348 | case IRQ_USB: | ||
349 | mask = 1u << 26; | ||
350 | break; | ||
351 | default: | ||
352 | return -EINVAL; | ||
353 | } | ||
354 | |||
355 | set_pwer: | ||
356 | if (on) | ||
357 | PWER |= mask; | ||
358 | else | ||
359 | PWER &=~mask; | ||
360 | |||
361 | return 0; | ||
362 | } | ||
363 | |||
364 | void __init pxa27x_init_irq(void) | ||
365 | { | ||
366 | pxa_init_irq_low(); | ||
367 | pxa_init_irq_high(); | ||
368 | pxa_init_irq_gpio(128); | ||
369 | pxa_init_irq_set_wake(pxa27x_set_wake); | ||
370 | } | ||
371 | |||
270 | /* | 372 | /* |
271 | * device registration specific to PXA27x. | 373 | * device registration specific to PXA27x. |
272 | */ | 374 | */ |
@@ -286,7 +388,7 @@ static struct resource pxa27x_ohci_resources[] = { | |||
286 | }, | 388 | }, |
287 | }; | 389 | }; |
288 | 390 | ||
289 | static struct platform_device pxa27x_device_ohci = { | 391 | struct platform_device pxa27x_device_ohci = { |
290 | .name = "pxa27x-ohci", | 392 | .name = "pxa27x-ohci", |
291 | .id = -1, | 393 | .id = -1, |
292 | .dev = { | 394 | .dev = { |
@@ -314,7 +416,7 @@ static struct resource i2c_power_resources[] = { | |||
314 | }, | 416 | }, |
315 | }; | 417 | }; |
316 | 418 | ||
317 | static struct platform_device pxa27x_device_i2c_power = { | 419 | struct platform_device pxa27x_device_i2c_power = { |
318 | .name = "pxa2xx-i2c", | 420 | .name = "pxa2xx-i2c", |
319 | .id = 1, | 421 | .id = 1, |
320 | .resource = i2c_power_resources, | 422 | .resource = i2c_power_resources, |
@@ -336,17 +438,12 @@ static struct platform_device *devices[] __initdata = { | |||
336 | &pxa27x_device_ohci, | 438 | &pxa27x_device_ohci, |
337 | }; | 439 | }; |
338 | 440 | ||
339 | void __init pxa27x_init_irq(void) | ||
340 | { | ||
341 | pxa_init_irq_low(); | ||
342 | pxa_init_irq_high(); | ||
343 | pxa_init_irq_gpio(128); | ||
344 | } | ||
345 | |||
346 | static int __init pxa27x_init(void) | 441 | static int __init pxa27x_init(void) |
347 | { | 442 | { |
348 | int ret = 0; | 443 | int ret = 0; |
349 | if (cpu_is_pxa27x()) { | 444 | if (cpu_is_pxa27x()) { |
445 | clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); | ||
446 | |||
350 | if ((ret = pxa_init_dma(32))) | 447 | if ((ret = pxa_init_dma(32))) |
351 | return ret; | 448 | return ret; |
352 | #ifdef CONFIG_PM | 449 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c new file mode 100644 index 000000000000..5363b1322652 --- /dev/null +++ b/arch/arm/mach-pxa/pxa300.c | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/pxa300.c | ||
3 | * | ||
4 | * Code specific to PXA300/PXA310 | ||
5 | * | ||
6 | * Copyright (C) 2007 Marvell Internation Ltd. | ||
7 | * | ||
8 | * 2007-08-21: eric miao <eric.y.miao@gmail.com> | ||
9 | * initial version | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | |||
19 | #include <asm/hardware.h> | ||
20 | #include <asm/arch/mfp-pxa300.h> | ||
21 | |||
22 | static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { | ||
23 | |||
24 | MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), | ||
25 | MFP_ADDR_X(GPIO3, GPIO26, 0x027c), | ||
26 | MFP_ADDR_X(GPIO27, GPIO127, 0x0400), | ||
27 | MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec), | ||
28 | |||
29 | MFP_ADDR(nBE0, 0x0204), | ||
30 | MFP_ADDR(nBE1, 0x0208), | ||
31 | |||
32 | MFP_ADDR(nLUA, 0x0244), | ||
33 | MFP_ADDR(nLLA, 0x0254), | ||
34 | |||
35 | MFP_ADDR(DF_CLE_nOE, 0x0240), | ||
36 | MFP_ADDR(DF_nRE_nOE, 0x0200), | ||
37 | MFP_ADDR(DF_ALE_nWE, 0x020C), | ||
38 | MFP_ADDR(DF_INT_RnB, 0x00C8), | ||
39 | MFP_ADDR(DF_nCS0, 0x0248), | ||
40 | MFP_ADDR(DF_nCS1, 0x0278), | ||
41 | MFP_ADDR(DF_nWE, 0x00CC), | ||
42 | |||
43 | MFP_ADDR(DF_ADDR0, 0x0210), | ||
44 | MFP_ADDR(DF_ADDR1, 0x0214), | ||
45 | MFP_ADDR(DF_ADDR2, 0x0218), | ||
46 | MFP_ADDR(DF_ADDR3, 0x021C), | ||
47 | |||
48 | MFP_ADDR(DF_IO0, 0x0220), | ||
49 | MFP_ADDR(DF_IO1, 0x0228), | ||
50 | MFP_ADDR(DF_IO2, 0x0230), | ||
51 | MFP_ADDR(DF_IO3, 0x0238), | ||
52 | MFP_ADDR(DF_IO4, 0x0258), | ||
53 | MFP_ADDR(DF_IO5, 0x0260), | ||
54 | MFP_ADDR(DF_IO6, 0x0268), | ||
55 | MFP_ADDR(DF_IO7, 0x0270), | ||
56 | MFP_ADDR(DF_IO8, 0x0224), | ||
57 | MFP_ADDR(DF_IO9, 0x022C), | ||
58 | MFP_ADDR(DF_IO10, 0x0234), | ||
59 | MFP_ADDR(DF_IO11, 0x023C), | ||
60 | MFP_ADDR(DF_IO12, 0x025C), | ||
61 | MFP_ADDR(DF_IO13, 0x0264), | ||
62 | MFP_ADDR(DF_IO14, 0x026C), | ||
63 | MFP_ADDR(DF_IO15, 0x0274), | ||
64 | |||
65 | MFP_ADDR_END, | ||
66 | }; | ||
67 | |||
68 | /* override pxa300 MFP register addresses */ | ||
69 | static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { | ||
70 | MFP_ADDR_X(GPIO30, GPIO98, 0x0418), | ||
71 | MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), | ||
72 | |||
73 | MFP_ADDR(ULPI_STP, 0x040C), | ||
74 | MFP_ADDR(ULPI_NXT, 0x0410), | ||
75 | MFP_ADDR(ULPI_DIR, 0x0414), | ||
76 | |||
77 | MFP_ADDR_END, | ||
78 | }; | ||
79 | |||
80 | static int __init pxa300_init(void) | ||
81 | { | ||
82 | if (cpu_is_pxa300() || cpu_is_pxa310()) { | ||
83 | pxa3xx_init_mfp(); | ||
84 | pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); | ||
85 | } | ||
86 | |||
87 | if (cpu_is_pxa310()) | ||
88 | pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); | ||
89 | |||
90 | return 0; | ||
91 | } | ||
92 | |||
93 | core_initcall(pxa300_init); | ||
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c new file mode 100644 index 000000000000..cd9eba5b3df9 --- /dev/null +++ b/arch/arm/mach-pxa/pxa320.c | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/pxa320.c | ||
3 | * | ||
4 | * Code specific to PXA320 | ||
5 | * | ||
6 | * Copyright (C) 2007 Marvell Internation Ltd. | ||
7 | * | ||
8 | * 2007-08-21: eric miao <eric.y.miao@gmail.com> | ||
9 | * initial version | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | |||
19 | #include <asm/hardware.h> | ||
20 | #include <asm/arch/mfp.h> | ||
21 | #include <asm/arch/mfp-pxa320.h> | ||
22 | |||
23 | static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { | ||
24 | |||
25 | MFP_ADDR_X(GPIO0, GPIO4, 0x0124), | ||
26 | MFP_ADDR_X(GPIO5, GPIO26, 0x028C), | ||
27 | MFP_ADDR_X(GPIO27, GPIO62, 0x0400), | ||
28 | MFP_ADDR_X(GPIO63, GPIO73, 0x04B4), | ||
29 | MFP_ADDR_X(GPIO74, GPIO98, 0x04F0), | ||
30 | MFP_ADDR_X(GPIO99, GPIO127, 0x0600), | ||
31 | MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674), | ||
32 | MFP_ADDR_X(GPIO6_2, GPIO13_2, 0x0494), | ||
33 | MFP_ADDR_X(GPIO14_2, GPIO17_2, 0x04E0), | ||
34 | |||
35 | MFP_ADDR(nXCVREN, 0x0138), | ||
36 | MFP_ADDR(DF_CLE_nOE, 0x0204), | ||
37 | MFP_ADDR(DF_nADV1_ALE, 0x0208), | ||
38 | MFP_ADDR(DF_SCLK_S, 0x020C), | ||
39 | MFP_ADDR(DF_SCLK_E, 0x0210), | ||
40 | MFP_ADDR(nBE0, 0x0214), | ||
41 | MFP_ADDR(nBE1, 0x0218), | ||
42 | MFP_ADDR(DF_nADV2_ALE, 0x021C), | ||
43 | MFP_ADDR(DF_INT_RnB, 0x0220), | ||
44 | MFP_ADDR(DF_nCS0, 0x0224), | ||
45 | MFP_ADDR(DF_nCS1, 0x0228), | ||
46 | MFP_ADDR(DF_nWE, 0x022C), | ||
47 | MFP_ADDR(DF_nRE_nOE, 0x0230), | ||
48 | MFP_ADDR(nLUA, 0x0234), | ||
49 | MFP_ADDR(nLLA, 0x0238), | ||
50 | MFP_ADDR(DF_ADDR0, 0x023C), | ||
51 | MFP_ADDR(DF_ADDR1, 0x0240), | ||
52 | MFP_ADDR(DF_ADDR2, 0x0244), | ||
53 | MFP_ADDR(DF_ADDR3, 0x0248), | ||
54 | MFP_ADDR(DF_IO0, 0x024C), | ||
55 | MFP_ADDR(DF_IO8, 0x0250), | ||
56 | MFP_ADDR(DF_IO1, 0x0254), | ||
57 | MFP_ADDR(DF_IO9, 0x0258), | ||
58 | MFP_ADDR(DF_IO2, 0x025C), | ||
59 | MFP_ADDR(DF_IO10, 0x0260), | ||
60 | MFP_ADDR(DF_IO3, 0x0264), | ||
61 | MFP_ADDR(DF_IO11, 0x0268), | ||
62 | MFP_ADDR(DF_IO4, 0x026C), | ||
63 | MFP_ADDR(DF_IO12, 0x0270), | ||
64 | MFP_ADDR(DF_IO5, 0x0274), | ||
65 | MFP_ADDR(DF_IO13, 0x0278), | ||
66 | MFP_ADDR(DF_IO6, 0x027C), | ||
67 | MFP_ADDR(DF_IO14, 0x0280), | ||
68 | MFP_ADDR(DF_IO7, 0x0284), | ||
69 | MFP_ADDR(DF_IO15, 0x0288), | ||
70 | |||
71 | MFP_ADDR_END, | ||
72 | }; | ||
73 | |||
74 | static void __init pxa320_init_mfp(void) | ||
75 | { | ||
76 | pxa3xx_init_mfp(); | ||
77 | pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); | ||
78 | } | ||
79 | |||
80 | static int __init pxa320_init(void) | ||
81 | { | ||
82 | if (cpu_is_pxa320()) | ||
83 | pxa320_init_mfp(); | ||
84 | |||
85 | return 0; | ||
86 | } | ||
87 | |||
88 | core_initcall(pxa320_init); | ||
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c new file mode 100644 index 000000000000..39f0de8c189e --- /dev/null +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -0,0 +1,216 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/pxa3xx.c | ||
3 | * | ||
4 | * code specific to pxa3xx aka Monahans | ||
5 | * | ||
6 | * Copyright (C) 2006 Marvell International Ltd. | ||
7 | * | ||
8 | * 2007-09-02: eric miao <eric.y.miao@gmail.com> | ||
9 | * initial version | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/pm.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/irq.h> | ||
22 | |||
23 | #include <asm/hardware.h> | ||
24 | #include <asm/arch/pxa3xx-regs.h> | ||
25 | #include <asm/arch/ohci.h> | ||
26 | #include <asm/arch/pm.h> | ||
27 | #include <asm/arch/dma.h> | ||
28 | #include <asm/arch/ssp.h> | ||
29 | |||
30 | #include "generic.h" | ||
31 | #include "devices.h" | ||
32 | #include "clock.h" | ||
33 | |||
34 | /* Crystal clock: 13MHz */ | ||
35 | #define BASE_CLK 13000000 | ||
36 | |||
37 | /* Ring Oscillator Clock: 60MHz */ | ||
38 | #define RO_CLK 60000000 | ||
39 | |||
40 | #define ACCR_D0CS (1 << 26) | ||
41 | |||
42 | /* crystal frequency to static memory controller multiplier (SMCFS) */ | ||
43 | static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; | ||
44 | |||
45 | /* crystal frequency to HSIO bus frequency multiplier (HSS) */ | ||
46 | static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; | ||
47 | |||
48 | /* | ||
49 | * Get the clock frequency as reflected by CCSR and the turbo flag. | ||
50 | * We assume these values have been applied via a fcs. | ||
51 | * If info is not 0 we also display the current settings. | ||
52 | */ | ||
53 | unsigned int pxa3xx_get_clk_frequency_khz(int info) | ||
54 | { | ||
55 | unsigned long acsr, xclkcfg; | ||
56 | unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; | ||
57 | |||
58 | /* Read XCLKCFG register turbo bit */ | ||
59 | __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); | ||
60 | t = xclkcfg & 0x1; | ||
61 | |||
62 | acsr = ACSR; | ||
63 | |||
64 | xl = acsr & 0x1f; | ||
65 | xn = (acsr >> 8) & 0x7; | ||
66 | hss = (acsr >> 14) & 0x3; | ||
67 | |||
68 | XL = xl * BASE_CLK; | ||
69 | XN = xn * XL; | ||
70 | |||
71 | ro = acsr & ACCR_D0CS; | ||
72 | |||
73 | CLK = (ro) ? RO_CLK : ((t) ? XN : XL); | ||
74 | HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
75 | |||
76 | if (info) { | ||
77 | pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", | ||
78 | RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, | ||
79 | (ro) ? "" : "in"); | ||
80 | pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", | ||
81 | XL / 1000000, (XL % 1000000) / 10000, xl); | ||
82 | pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", | ||
83 | XN / 1000000, (XN % 1000000) / 10000, xn, | ||
84 | (t) ? "" : "in"); | ||
85 | pr_info("HSIO bus clock: %d.%02dMHz\n", | ||
86 | HSS / 1000000, (HSS % 1000000) / 10000); | ||
87 | } | ||
88 | |||
89 | return CLK; | ||
90 | } | ||
91 | |||
92 | /* | ||
93 | * Return the current static memory controller clock frequency | ||
94 | * in units of 10kHz | ||
95 | */ | ||
96 | unsigned int pxa3xx_get_memclk_frequency_10khz(void) | ||
97 | { | ||
98 | unsigned long acsr; | ||
99 | unsigned int smcfs, clk = 0; | ||
100 | |||
101 | acsr = ACSR; | ||
102 | |||
103 | smcfs = (acsr >> 23) & 0x7; | ||
104 | clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; | ||
105 | |||
106 | return (clk / 10000); | ||
107 | } | ||
108 | |||
109 | /* | ||
110 | * Return the current HSIO bus clock frequency | ||
111 | */ | ||
112 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | ||
113 | { | ||
114 | unsigned long acsr; | ||
115 | unsigned int hss, hsio_clk; | ||
116 | |||
117 | acsr = ACSR; | ||
118 | |||
119 | hss = (acsr >> 14) & 0x3; | ||
120 | hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
121 | |||
122 | return hsio_clk; | ||
123 | } | ||
124 | |||
125 | static void clk_pxa3xx_cken_enable(struct clk *clk) | ||
126 | { | ||
127 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
128 | |||
129 | local_irq_disable(); | ||
130 | |||
131 | if (clk->cken < 32) | ||
132 | CKENA |= mask; | ||
133 | else | ||
134 | CKENB |= mask; | ||
135 | |||
136 | local_irq_enable(); | ||
137 | } | ||
138 | |||
139 | static void clk_pxa3xx_cken_disable(struct clk *clk) | ||
140 | { | ||
141 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
142 | |||
143 | local_irq_disable(); | ||
144 | |||
145 | if (clk->cken < 32) | ||
146 | CKENA &= ~mask; | ||
147 | else | ||
148 | CKENB &= ~mask; | ||
149 | |||
150 | local_irq_enable(); | ||
151 | } | ||
152 | |||
153 | static const struct clkops clk_pxa3xx_hsio_ops = { | ||
154 | .enable = clk_pxa3xx_cken_enable, | ||
155 | .disable = clk_pxa3xx_cken_disable, | ||
156 | .getrate = clk_pxa3xx_hsio_getrate, | ||
157 | }; | ||
158 | |||
159 | static struct clk pxa3xx_clks[] = { | ||
160 | INIT_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), | ||
161 | INIT_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), | ||
162 | |||
163 | INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), | ||
164 | INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), | ||
165 | INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), | ||
166 | |||
167 | INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), | ||
168 | INIT_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), | ||
169 | }; | ||
170 | |||
171 | void __init pxa3xx_init_irq(void) | ||
172 | { | ||
173 | /* enable CP6 access */ | ||
174 | u32 value; | ||
175 | __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); | ||
176 | value |= (1 << 6); | ||
177 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | ||
178 | |||
179 | pxa_init_irq_low(); | ||
180 | pxa_init_irq_high(); | ||
181 | pxa_init_irq_gpio(128); | ||
182 | } | ||
183 | |||
184 | /* | ||
185 | * device registration specific to PXA3xx. | ||
186 | */ | ||
187 | |||
188 | static struct platform_device *devices[] __initdata = { | ||
189 | &pxa_device_mci, | ||
190 | &pxa_device_udc, | ||
191 | &pxa_device_fb, | ||
192 | &pxa_device_ffuart, | ||
193 | &pxa_device_btuart, | ||
194 | &pxa_device_stuart, | ||
195 | &pxa_device_i2c, | ||
196 | &pxa_device_i2s, | ||
197 | &pxa_device_ficp, | ||
198 | &pxa_device_rtc, | ||
199 | }; | ||
200 | |||
201 | static int __init pxa3xx_init(void) | ||
202 | { | ||
203 | int ret = 0; | ||
204 | |||
205 | if (cpu_is_pxa3xx()) { | ||
206 | clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); | ||
207 | |||
208 | if ((ret = pxa_init_dma(32))) | ||
209 | return ret; | ||
210 | |||
211 | return platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
212 | } | ||
213 | return 0; | ||
214 | } | ||
215 | |||
216 | subsys_initcall(pxa3xx_init); | ||
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 98d27e646b09..ec4286c7931c 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c | |||
@@ -16,10 +16,48 @@ | |||
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
18 | #include <linux/clockchips.h> | 18 | #include <linux/clockchips.h> |
19 | #include <linux/sched.h> | ||
19 | 20 | ||
21 | #include <asm/div64.h> | ||
22 | #include <asm/cnt32_to_63.h> | ||
20 | #include <asm/mach/irq.h> | 23 | #include <asm/mach/irq.h> |
21 | #include <asm/mach/time.h> | 24 | #include <asm/mach/time.h> |
22 | #include <asm/arch/pxa-regs.h> | 25 | #include <asm/arch/pxa-regs.h> |
26 | #include <asm/mach-types.h> | ||
27 | |||
28 | /* | ||
29 | * This is PXA's sched_clock implementation. This has a resolution | ||
30 | * of at least 308 ns and a maximum value of 208 days. | ||
31 | * | ||
32 | * The return value is guaranteed to be monotonic in that range as | ||
33 | * long as there is always less than 582 seconds between successive | ||
34 | * calls to sched_clock() which should always be the case in practice. | ||
35 | */ | ||
36 | |||
37 | #define OSCR2NS_SCALE_FACTOR 10 | ||
38 | |||
39 | static unsigned long oscr2ns_scale; | ||
40 | |||
41 | static void __init set_oscr2ns_scale(unsigned long oscr_rate) | ||
42 | { | ||
43 | unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR; | ||
44 | do_div(v, oscr_rate); | ||
45 | oscr2ns_scale = v; | ||
46 | /* | ||
47 | * We want an even value to automatically clear the top bit | ||
48 | * returned by cnt32_to_63() without an additional run time | ||
49 | * instruction. So if the LSB is 1 then round it up. | ||
50 | */ | ||
51 | if (oscr2ns_scale & 1) | ||
52 | oscr2ns_scale++; | ||
53 | } | ||
54 | |||
55 | unsigned long long sched_clock(void) | ||
56 | { | ||
57 | unsigned long long v = cnt32_to_63(OSCR); | ||
58 | return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR; | ||
59 | } | ||
60 | |||
23 | 61 | ||
24 | static irqreturn_t | 62 | static irqreturn_t |
25 | pxa_ost0_interrupt(int irq, void *dev_id) | 63 | pxa_ost0_interrupt(int irq, void *dev_id) |
@@ -149,18 +187,29 @@ static struct irqaction pxa_ost0_irq = { | |||
149 | 187 | ||
150 | static void __init pxa_timer_init(void) | 188 | static void __init pxa_timer_init(void) |
151 | { | 189 | { |
190 | unsigned long clock_tick_rate; | ||
191 | |||
152 | OIER = 0; | 192 | OIER = 0; |
153 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; | 193 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; |
154 | 194 | ||
195 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) | ||
196 | clock_tick_rate = 3686400; | ||
197 | else if (machine_is_mainstone()) | ||
198 | clock_tick_rate = 3249600; | ||
199 | else | ||
200 | clock_tick_rate = 3250000; | ||
201 | |||
202 | set_oscr2ns_scale(clock_tick_rate); | ||
203 | |||
155 | ckevt_pxa_osmr0.mult = | 204 | ckevt_pxa_osmr0.mult = |
156 | div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); | 205 | div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); |
157 | ckevt_pxa_osmr0.max_delta_ns = | 206 | ckevt_pxa_osmr0.max_delta_ns = |
158 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); | 207 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); |
159 | ckevt_pxa_osmr0.min_delta_ns = | 208 | ckevt_pxa_osmr0.min_delta_ns = |
160 | clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1; | 209 | clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1; |
161 | 210 | ||
162 | cksrc_pxa_oscr0.mult = | 211 | cksrc_pxa_oscr0.mult = |
163 | clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift); | 212 | clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); |
164 | 213 | ||
165 | setup_irq(IRQ_OST0, &pxa_ost0_irq); | 214 | setup_irq(IRQ_OST0, &pxa_ost0_irq); |
166 | 215 | ||
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c new file mode 100644 index 000000000000..3f18d760dd1b --- /dev/null +++ b/arch/arm/mach-pxa/zylonite.c | |||
@@ -0,0 +1,184 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/zylonite.c | ||
3 | * | ||
4 | * Support for the PXA3xx Development Platform (aka Zylonite) | ||
5 | * | ||
6 | * Copyright (C) 2006 Marvell International Ltd. | ||
7 | * | ||
8 | * 2007-09-04: eric miao <eric.y.miao@gmail.com> | ||
9 | * rewrite to align with latest kernel | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | |||
22 | #include <asm/mach-types.h> | ||
23 | #include <asm/mach/arch.h> | ||
24 | #include <asm/hardware.h> | ||
25 | #include <asm/arch/gpio.h> | ||
26 | #include <asm/arch/pxafb.h> | ||
27 | #include <asm/arch/zylonite.h> | ||
28 | |||
29 | #include "generic.h" | ||
30 | |||
31 | int gpio_backlight; | ||
32 | int gpio_eth_irq; | ||
33 | |||
34 | int lcd_id; | ||
35 | int lcd_orientation; | ||
36 | |||
37 | static struct resource smc91x_resources[] = { | ||
38 | [0] = { | ||
39 | .start = ZYLONITE_ETH_PHYS + 0x300, | ||
40 | .end = ZYLONITE_ETH_PHYS + 0xfffff, | ||
41 | .flags = IORESOURCE_MEM, | ||
42 | }, | ||
43 | [1] = { | ||
44 | .start = -1, /* for run-time assignment */ | ||
45 | .end = -1, | ||
46 | .flags = IORESOURCE_IRQ, | ||
47 | } | ||
48 | }; | ||
49 | |||
50 | static struct platform_device smc91x_device = { | ||
51 | .name = "smc91x", | ||
52 | .id = 0, | ||
53 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
54 | .resource = smc91x_resources, | ||
55 | }; | ||
56 | |||
57 | #if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES) | ||
58 | static void zylonite_backlight_power(int on) | ||
59 | { | ||
60 | gpio_set_value(gpio_backlight, on); | ||
61 | } | ||
62 | |||
63 | static struct pxafb_mode_info toshiba_ltm035a776c_mode = { | ||
64 | .pixclock = 110000, | ||
65 | .xres = 240, | ||
66 | .yres = 320, | ||
67 | .bpp = 16, | ||
68 | .hsync_len = 4, | ||
69 | .left_margin = 6, | ||
70 | .right_margin = 4, | ||
71 | .vsync_len = 2, | ||
72 | .upper_margin = 2, | ||
73 | .lower_margin = 3, | ||
74 | .sync = FB_SYNC_VERT_HIGH_ACT, | ||
75 | }; | ||
76 | |||
77 | static struct pxafb_mode_info toshiba_ltm04c380k_mode = { | ||
78 | .pixclock = 50000, | ||
79 | .xres = 640, | ||
80 | .yres = 480, | ||
81 | .bpp = 16, | ||
82 | .hsync_len = 1, | ||
83 | .left_margin = 0x9f, | ||
84 | .right_margin = 1, | ||
85 | .vsync_len = 44, | ||
86 | .upper_margin = 0, | ||
87 | .lower_margin = 0, | ||
88 | .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, | ||
89 | }; | ||
90 | |||
91 | static struct pxafb_mach_info zylonite_toshiba_lcd_info = { | ||
92 | .num_modes = 1, | ||
93 | .lccr0 = LCCR0_Act, | ||
94 | .lccr3 = LCCR3_PCP, | ||
95 | .pxafb_backlight_power = zylonite_backlight_power, | ||
96 | }; | ||
97 | |||
98 | static struct pxafb_mode_info sharp_ls037_modes[] = { | ||
99 | [0] = { | ||
100 | .pixclock = 158000, | ||
101 | .xres = 240, | ||
102 | .yres = 320, | ||
103 | .bpp = 16, | ||
104 | .hsync_len = 4, | ||
105 | .left_margin = 39, | ||
106 | .right_margin = 39, | ||
107 | .vsync_len = 1, | ||
108 | .upper_margin = 2, | ||
109 | .lower_margin = 3, | ||
110 | .sync = 0, | ||
111 | }, | ||
112 | [1] = { | ||
113 | .pixclock = 39700, | ||
114 | .xres = 480, | ||
115 | .yres = 640, | ||
116 | .bpp = 16, | ||
117 | .hsync_len = 8, | ||
118 | .left_margin = 81, | ||
119 | .right_margin = 81, | ||
120 | .vsync_len = 1, | ||
121 | .upper_margin = 2, | ||
122 | .lower_margin = 7, | ||
123 | .sync = 0, | ||
124 | }, | ||
125 | }; | ||
126 | |||
127 | static struct pxafb_mach_info zylonite_sharp_lcd_info = { | ||
128 | .modes = sharp_ls037_modes, | ||
129 | .num_modes = 2, | ||
130 | .lccr0 = LCCR0_Act, | ||
131 | .lccr3 = LCCR3_PCP | LCCR3_HSP | LCCR3_VSP, | ||
132 | .pxafb_backlight_power = zylonite_backlight_power, | ||
133 | }; | ||
134 | |||
135 | static void __init zylonite_init_lcd(void) | ||
136 | { | ||
137 | /* backlight GPIO: output, default on */ | ||
138 | gpio_direction_output(gpio_backlight, 1); | ||
139 | |||
140 | if (lcd_id & 0x20) { | ||
141 | set_pxa_fb_info(&zylonite_sharp_lcd_info); | ||
142 | return; | ||
143 | } | ||
144 | |||
145 | /* legacy LCD panels, it would be handy here if LCD panel type can | ||
146 | * be decided at run-time | ||
147 | */ | ||
148 | if (1) | ||
149 | zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode; | ||
150 | else | ||
151 | zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; | ||
152 | |||
153 | set_pxa_fb_info(&zylonite_toshiba_lcd_info); | ||
154 | } | ||
155 | #else | ||
156 | static inline void zylonite_init_lcd(void) {} | ||
157 | #endif | ||
158 | |||
159 | static void __init zylonite_init(void) | ||
160 | { | ||
161 | /* board-processor specific initialization */ | ||
162 | zylonite_pxa300_init(); | ||
163 | zylonite_pxa320_init(); | ||
164 | |||
165 | /* | ||
166 | * Note: We depend that the bootloader set | ||
167 | * the correct value to MSC register for SMC91x. | ||
168 | */ | ||
169 | smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq); | ||
170 | smc91x_resources[1].end = gpio_to_irq(gpio_eth_irq); | ||
171 | platform_device_register(&smc91x_device); | ||
172 | |||
173 | zylonite_init_lcd(); | ||
174 | } | ||
175 | |||
176 | MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") | ||
177 | .phys_io = 0x40000000, | ||
178 | .boot_params = 0xa0000100, | ||
179 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
180 | .map_io = pxa_map_io, | ||
181 | .init_irq = pxa3xx_init_irq, | ||
182 | .timer = &pxa_timer, | ||
183 | .init_machine = zylonite_init, | ||
184 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c new file mode 100644 index 000000000000..b5fbd2f4c693 --- /dev/null +++ b/arch/arm/mach-pxa/zylonite_pxa300.c | |||
@@ -0,0 +1,188 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/zylonite_pxa300.c | ||
3 | * | ||
4 | * PXA300/PXA310 specific support code for the | ||
5 | * PXA3xx Development Platform (aka Zylonite) | ||
6 | * | ||
7 | * Copyright (C) 2007 Marvell Internation Ltd. | ||
8 | * 2007-08-21: eric miao <eric.y.miao@gmail.com> | ||
9 | * initial version | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/init.h> | ||
19 | |||
20 | #include <asm/gpio.h> | ||
21 | #include <asm/arch/mfp-pxa300.h> | ||
22 | #include <asm/arch/zylonite.h> | ||
23 | |||
24 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
25 | |||
26 | /* PXA300/PXA310 common configurations */ | ||
27 | static mfp_cfg_t common_mfp_cfg[] __initdata = { | ||
28 | /* LCD */ | ||
29 | GPIO54_LCD_LDD_0, | ||
30 | GPIO55_LCD_LDD_1, | ||
31 | GPIO56_LCD_LDD_2, | ||
32 | GPIO57_LCD_LDD_3, | ||
33 | GPIO58_LCD_LDD_4, | ||
34 | GPIO59_LCD_LDD_5, | ||
35 | GPIO60_LCD_LDD_6, | ||
36 | GPIO61_LCD_LDD_7, | ||
37 | GPIO62_LCD_LDD_8, | ||
38 | GPIO63_LCD_LDD_9, | ||
39 | GPIO64_LCD_LDD_10, | ||
40 | GPIO65_LCD_LDD_11, | ||
41 | GPIO66_LCD_LDD_12, | ||
42 | GPIO67_LCD_LDD_13, | ||
43 | GPIO68_LCD_LDD_14, | ||
44 | GPIO69_LCD_LDD_15, | ||
45 | GPIO70_LCD_LDD_16, | ||
46 | GPIO71_LCD_LDD_17, | ||
47 | GPIO72_LCD_FCLK, | ||
48 | GPIO73_LCD_LCLK, | ||
49 | GPIO74_LCD_PCLK, | ||
50 | GPIO75_LCD_BIAS, | ||
51 | GPIO76_LCD_VSYNC, | ||
52 | GPIO127_LCD_CS_N, | ||
53 | |||
54 | /* BTUART */ | ||
55 | GPIO111_UART2_RTS, | ||
56 | GPIO112_UART2_RXD, | ||
57 | GPIO113_UART2_TXD, | ||
58 | GPIO114_UART2_CTS, | ||
59 | |||
60 | /* STUART */ | ||
61 | GPIO109_UART3_TXD, | ||
62 | GPIO110_UART3_RXD, | ||
63 | |||
64 | /* AC97 */ | ||
65 | GPIO23_AC97_nACRESET, | ||
66 | GPIO24_AC97_SYSCLK, | ||
67 | GPIO29_AC97_BITCLK, | ||
68 | GPIO25_AC97_SDATA_IN_0, | ||
69 | GPIO27_AC97_SDATA_OUT, | ||
70 | GPIO28_AC97_SYNC, | ||
71 | |||
72 | /* Keypad */ | ||
73 | GPIO107_KP_DKIN_0, | ||
74 | GPIO108_KP_DKIN_1, | ||
75 | GPIO115_KP_MKIN_0, | ||
76 | GPIO116_KP_MKIN_1, | ||
77 | GPIO117_KP_MKIN_2, | ||
78 | GPIO118_KP_MKIN_3, | ||
79 | GPIO119_KP_MKIN_4, | ||
80 | GPIO120_KP_MKIN_5, | ||
81 | GPIO2_2_KP_MKIN_6, | ||
82 | GPIO3_2_KP_MKIN_7, | ||
83 | GPIO121_KP_MKOUT_0, | ||
84 | GPIO122_KP_MKOUT_1, | ||
85 | GPIO123_KP_MKOUT_2, | ||
86 | GPIO124_KP_MKOUT_3, | ||
87 | GPIO125_KP_MKOUT_4, | ||
88 | GPIO4_2_KP_MKOUT_5, | ||
89 | GPIO5_2_KP_MKOUT_6, | ||
90 | GPIO6_2_KP_MKOUT_7, | ||
91 | }; | ||
92 | |||
93 | static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { | ||
94 | /* FFUART */ | ||
95 | GPIO30_UART1_RXD, | ||
96 | GPIO31_UART1_TXD, | ||
97 | GPIO32_UART1_CTS, | ||
98 | GPIO37_UART1_RTS, | ||
99 | GPIO33_UART1_DCD, | ||
100 | GPIO34_UART1_DSR, | ||
101 | GPIO35_UART1_RI, | ||
102 | GPIO36_UART1_DTR, | ||
103 | |||
104 | /* Ethernet */ | ||
105 | GPIO2_nCS3, | ||
106 | GPIO99_GPIO, | ||
107 | }; | ||
108 | |||
109 | static mfp_cfg_t pxa310_mfp_cfg[] __initdata = { | ||
110 | /* FFUART */ | ||
111 | GPIO99_UART1_RXD, | ||
112 | GPIO100_UART1_TXD, | ||
113 | GPIO101_UART1_CTS, | ||
114 | GPIO106_UART1_RTS, | ||
115 | |||
116 | /* Ethernet */ | ||
117 | GPIO2_nCS3, | ||
118 | GPIO102_GPIO, | ||
119 | }; | ||
120 | |||
121 | #define NUM_LCD_DETECT_PINS 7 | ||
122 | |||
123 | static int lcd_detect_pins[] __initdata = { | ||
124 | MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */ | ||
125 | MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */ | ||
126 | MFP_PIN_GPIO75, /* LCD_BIAS - LCDID[4] */ | ||
127 | MFP_PIN_GPIO73, /* LCD_LCLK - LCDID[3] */ | ||
128 | MFP_PIN_GPIO72, /* LCD_FCLK - LCDID[2] */ | ||
129 | MFP_PIN_GPIO127,/* LCD_CS_N - LCDID[1] */ | ||
130 | MFP_PIN_GPIO76, /* LCD_VSYNC - LCDID[0] */ | ||
131 | }; | ||
132 | |||
133 | static void __init zylonite_detect_lcd_panel(void) | ||
134 | { | ||
135 | unsigned long mfpr_save[NUM_LCD_DETECT_PINS]; | ||
136 | int i, gpio, id = 0; | ||
137 | |||
138 | /* save the original MFP settings of these pins and configure | ||
139 | * them as GPIO Input, DS01X, Pull Neither, Edge Clear | ||
140 | */ | ||
141 | for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { | ||
142 | mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]); | ||
143 | pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440); | ||
144 | } | ||
145 | |||
146 | for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { | ||
147 | id = id << 1; | ||
148 | gpio = mfp_to_gpio(lcd_detect_pins[i]); | ||
149 | gpio_direction_input(gpio); | ||
150 | |||
151 | if (gpio_get_value(gpio)) | ||
152 | id = id | 0x1; | ||
153 | } | ||
154 | |||
155 | /* lcd id, flush out bit 1 */ | ||
156 | lcd_id = id & 0x3d; | ||
157 | |||
158 | /* lcd orientation, portrait or landscape */ | ||
159 | lcd_orientation = (id >> 6) & 0x1; | ||
160 | |||
161 | /* restore the original MFP settings */ | ||
162 | for (i = 0; i < NUM_LCD_DETECT_PINS; i++) | ||
163 | pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]); | ||
164 | } | ||
165 | |||
166 | void __init zylonite_pxa300_init(void) | ||
167 | { | ||
168 | if (cpu_is_pxa300() || cpu_is_pxa310()) { | ||
169 | /* initialize MFP */ | ||
170 | pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg)); | ||
171 | |||
172 | /* detect LCD panel */ | ||
173 | zylonite_detect_lcd_panel(); | ||
174 | |||
175 | /* GPIO pin assignment */ | ||
176 | gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20); | ||
177 | } | ||
178 | |||
179 | if (cpu_is_pxa300()) { | ||
180 | pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg)); | ||
181 | gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99); | ||
182 | } | ||
183 | |||
184 | if (cpu_is_pxa310()) { | ||
185 | pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg)); | ||
186 | gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102); | ||
187 | } | ||
188 | } | ||
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c new file mode 100644 index 000000000000..63cb36be086b --- /dev/null +++ b/arch/arm/mach-pxa/zylonite_pxa320.c | |||
@@ -0,0 +1,173 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-pxa/zylonite_pxa320.c | ||
3 | * | ||
4 | * PXA320 specific support code for the | ||
5 | * PXA3xx Development Platform (aka Zylonite) | ||
6 | * | ||
7 | * Copyright (C) 2007 Marvell Internation Ltd. | ||
8 | * 2007-08-21: eric miao <eric.y.miao@gmail.com> | ||
9 | * initial version | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/init.h> | ||
19 | |||
20 | #include <asm/arch/gpio.h> | ||
21 | #include <asm/arch/mfp-pxa320.h> | ||
22 | #include <asm/arch/zylonite.h> | ||
23 | |||
24 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
25 | |||
26 | static mfp_cfg_t mfp_cfg[] __initdata = { | ||
27 | /* LCD */ | ||
28 | GPIO6_2_LCD_LDD_0, | ||
29 | GPIO7_2_LCD_LDD_1, | ||
30 | GPIO8_2_LCD_LDD_2, | ||
31 | GPIO9_2_LCD_LDD_3, | ||
32 | GPIO10_2_LCD_LDD_4, | ||
33 | GPIO11_2_LCD_LDD_5, | ||
34 | GPIO12_2_LCD_LDD_6, | ||
35 | GPIO13_2_LCD_LDD_7, | ||
36 | GPIO63_LCD_LDD_8, | ||
37 | GPIO64_LCD_LDD_9, | ||
38 | GPIO65_LCD_LDD_10, | ||
39 | GPIO66_LCD_LDD_11, | ||
40 | GPIO67_LCD_LDD_12, | ||
41 | GPIO68_LCD_LDD_13, | ||
42 | GPIO69_LCD_LDD_14, | ||
43 | GPIO70_LCD_LDD_15, | ||
44 | GPIO71_LCD_LDD_16, | ||
45 | GPIO72_LCD_LDD_17, | ||
46 | GPIO73_LCD_CS_N, | ||
47 | GPIO74_LCD_VSYNC, | ||
48 | GPIO14_2_LCD_FCLK, | ||
49 | GPIO15_2_LCD_LCLK, | ||
50 | GPIO16_2_LCD_PCLK, | ||
51 | GPIO17_2_LCD_BIAS, | ||
52 | |||
53 | /* FFUART */ | ||
54 | GPIO41_UART1_RXD, | ||
55 | GPIO42_UART1_TXD, | ||
56 | GPIO43_UART1_CTS, | ||
57 | GPIO44_UART1_DCD, | ||
58 | GPIO45_UART1_DSR, | ||
59 | GPIO46_UART1_RI, | ||
60 | GPIO47_UART1_DTR, | ||
61 | GPIO48_UART1_RTS, | ||
62 | |||
63 | /* AC97 */ | ||
64 | GPIO34_AC97_SYSCLK, | ||
65 | GPIO35_AC97_SDATA_IN_0, | ||
66 | GPIO37_AC97_SDATA_OUT, | ||
67 | GPIO38_AC97_SYNC, | ||
68 | GPIO39_AC97_BITCLK, | ||
69 | GPIO40_AC97_nACRESET, | ||
70 | |||
71 | /* I2C */ | ||
72 | GPIO32_I2C_SCL, | ||
73 | GPIO33_I2C_SDA, | ||
74 | |||
75 | /* Keypad */ | ||
76 | GPIO105_KP_DKIN_0, | ||
77 | GPIO106_KP_DKIN_1, | ||
78 | GPIO113_KP_MKIN_0, | ||
79 | GPIO114_KP_MKIN_1, | ||
80 | GPIO115_KP_MKIN_2, | ||
81 | GPIO116_KP_MKIN_3, | ||
82 | GPIO117_KP_MKIN_4, | ||
83 | GPIO118_KP_MKIN_5, | ||
84 | GPIO119_KP_MKIN_6, | ||
85 | GPIO120_KP_MKIN_7, | ||
86 | GPIO121_KP_MKOUT_0, | ||
87 | GPIO122_KP_MKOUT_1, | ||
88 | GPIO123_KP_MKOUT_2, | ||
89 | GPIO124_KP_MKOUT_3, | ||
90 | GPIO125_KP_MKOUT_4, | ||
91 | GPIO126_KP_MKOUT_5, | ||
92 | GPIO127_KP_MKOUT_6, | ||
93 | GPIO5_2_KP_MKOUT_7, | ||
94 | |||
95 | /* Ethernet */ | ||
96 | GPIO4_nCS3, | ||
97 | GPIO90_GPIO, | ||
98 | }; | ||
99 | |||
100 | #define NUM_LCD_DETECT_PINS 7 | ||
101 | |||
102 | static int lcd_detect_pins[] __initdata = { | ||
103 | MFP_PIN_GPIO72, /* LCD_LDD_17 - ORIENT */ | ||
104 | MFP_PIN_GPIO71, /* LCD_LDD_16 - LCDID[5] */ | ||
105 | MFP_PIN_GPIO17_2, /* LCD_BIAS - LCDID[4] */ | ||
106 | MFP_PIN_GPIO15_2, /* LCD_LCLK - LCDID[3] */ | ||
107 | MFP_PIN_GPIO14_2, /* LCD_FCLK - LCDID[2] */ | ||
108 | MFP_PIN_GPIO73, /* LCD_CS_N - LCDID[1] */ | ||
109 | MFP_PIN_GPIO74, /* LCD_VSYNC - LCDID[0] */ | ||
110 | /* | ||
111 | * set the MFP_PIN_GPIO 14/15/17 to alternate function other than | ||
112 | * GPIO to avoid input level confliction with 14_2, 15_2, 17_2 | ||
113 | */ | ||
114 | MFP_PIN_GPIO14, | ||
115 | MFP_PIN_GPIO15, | ||
116 | MFP_PIN_GPIO17, | ||
117 | }; | ||
118 | |||
119 | static int lcd_detect_mfpr[] __initdata = { | ||
120 | /* AF0, DS 1X, Pull Neither, Edge Clear */ | ||
121 | 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, | ||
122 | 0xc442, /* Backlight, Pull-Up, AF2 */ | ||
123 | 0x8445, /* AF5 */ | ||
124 | 0x8445, /* AF5 */ | ||
125 | }; | ||
126 | |||
127 | static void __init zylonite_detect_lcd_panel(void) | ||
128 | { | ||
129 | unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)]; | ||
130 | int i, gpio, id = 0; | ||
131 | |||
132 | /* save the original MFP settings of these pins and configure them | ||
133 | * as GPIO Input, DS01X, Pull Neither, Edge Clear | ||
134 | */ | ||
135 | for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) { | ||
136 | mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]); | ||
137 | pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]); | ||
138 | } | ||
139 | |||
140 | for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { | ||
141 | id = id << 1; | ||
142 | gpio = mfp_to_gpio(lcd_detect_pins[i]); | ||
143 | gpio_direction_input(gpio); | ||
144 | |||
145 | if (gpio_get_value(gpio)) | ||
146 | id = id | 0x1; | ||
147 | } | ||
148 | |||
149 | /* lcd id, flush out bit 1 */ | ||
150 | lcd_id = id & 0x3d; | ||
151 | |||
152 | /* lcd orientation, portrait or landscape */ | ||
153 | lcd_orientation = (id >> 6) & 0x1; | ||
154 | |||
155 | /* restore the original MFP settings */ | ||
156 | for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) | ||
157 | pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]); | ||
158 | } | ||
159 | |||
160 | void __init zylonite_pxa320_init(void) | ||
161 | { | ||
162 | if (cpu_is_pxa320()) { | ||
163 | /* initialize MFP */ | ||
164 | pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg)); | ||
165 | |||
166 | /* detect LCD panel */ | ||
167 | zylonite_detect_lcd_panel(); | ||
168 | |||
169 | /* GPIO pin assignment */ | ||
170 | gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14); | ||
171 | gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9); | ||
172 | } | ||
173 | } | ||
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 12161ae445da..7868f4dc1d00 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -322,7 +322,7 @@ config CPU_SA1100 | |||
322 | # XScale | 322 | # XScale |
323 | config CPU_XSCALE | 323 | config CPU_XSCALE |
324 | bool | 324 | bool |
325 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 | 325 | depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 |
326 | default y | 326 | default y |
327 | select CPU_32v5 | 327 | select CPU_32v5 |
328 | select CPU_ABRT_EV5T | 328 | select CPU_ABRT_EV5T |
@@ -333,7 +333,7 @@ config CPU_XSCALE | |||
333 | # XScale Core Version 3 | 333 | # XScale Core Version 3 |
334 | config CPU_XSC3 | 334 | config CPU_XSC3 |
335 | bool | 335 | bool |
336 | depends on ARCH_IXP23XX || ARCH_IOP13XX | 336 | depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx |
337 | default y | 337 | default y |
338 | select CPU_32v5 | 338 | select CPU_32v5 |
339 | select CPU_ABRT_EV5T | 339 | select CPU_ABRT_EV5T |