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-rw-r--r--arch/arm/mach-s3c2400/gpio.c6
-rw-r--r--arch/arm/mach-s3c2410/gpio.c6
-rw-r--r--arch/arm/mach-s3c2410/h1940-bluetooth.c26
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-core.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-fns.h103
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h70
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-s3c2410/include/mach/hardware.h95
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h333
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c5
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c10
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c51
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c19
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c11
-rw-r--r--arch/arm/mach-s3c2410/pm.c5
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.c32
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c43
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c9
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c3
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c17
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c9
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c25
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c34
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c42
-rw-r--r--arch/arm/plat-s3c24xx/pm.c9
-rw-r--r--arch/arm/plat-s3c24xx/setup-i2c.c5
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c20
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c20
30 files changed, 394 insertions, 621 deletions
diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
index 7a7ed4174c8c..6c68e78f3595 100644
--- a/arch/arm/mach-s3c2400/gpio.c
+++ b/arch/arm/mach-s3c2400/gpio.c
@@ -33,10 +33,10 @@
33 33
34int s3c2400_gpio_getirq(unsigned int pin) 34int s3c2400_gpio_getirq(unsigned int pin)
35{ 35{
36 if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7) 36 if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
37 return -1; /* not valid interrupts */ 37 return -EINVAL; /* not valid interrupts */
38 38
39 return (pin - S3C2410_GPE0) + IRQ_EINT0; 39 return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
40} 40}
41 41
42EXPORT_SYMBOL(s3c2400_gpio_getirq); 42EXPORT_SYMBOL(s3c2400_gpio_getirq);
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 36a3132f39e7..7974afca297c 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
39 unsigned long flags; 39 unsigned long flags;
40 unsigned long val; 40 unsigned long val;
41 41
42 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) 42 if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
43 return -1; 43 return -EINVAL;
44 44
45 config &= 0xff; 45 config &= 0xff;
46 46
47 pin -= S3C2410_GPG8; 47 pin -= S3C2410_GPG(8);
48 reg += pin & ~3; 48 reg += pin & ~3;
49 49
50 local_irq_save(flags); 50 local_irq_save(flags);
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 5a6bc56f186b..5aabf117cbb0 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -16,6 +16,8 @@
16#include <linux/string.h> 16#include <linux/string.h>
17#include <linux/ctype.h> 17#include <linux/ctype.h>
18#include <linux/leds.h> 18#include <linux/leds.h>
19#include <linux/gpio.h>
20
19#include <mach/regs-gpio.h> 21#include <mach/regs-gpio.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21#include <mach/h1940-latch.h> 23#include <mach/h1940-latch.h>
@@ -41,9 +43,9 @@ static void h1940bt_enable(int on)
41 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); 43 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
42 /* Reset the chip */ 44 /* Reset the chip */
43 mdelay(10); 45 mdelay(10);
44 s3c2410_gpio_setpin(S3C2410_GPH1, 1); 46 s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
45 mdelay(10); 47 mdelay(10);
46 s3c2410_gpio_setpin(S3C2410_GPH1, 0); 48 s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
47 49
48 state = 1; 50 state = 1;
49 } 51 }
@@ -52,9 +54,9 @@ static void h1940bt_enable(int on)
52 led_trigger_event(bt_led_trigger, 0); 54 led_trigger_event(bt_led_trigger, 0);
53#endif 55#endif
54 56
55 s3c2410_gpio_setpin(S3C2410_GPH1, 1); 57 s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
56 mdelay(10); 58 mdelay(10);
57 s3c2410_gpio_setpin(S3C2410_GPH1, 0); 59 s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
58 mdelay(10); 60 mdelay(10);
59 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); 61 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
60 62
@@ -87,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
87static int __init h1940bt_probe(struct platform_device *pdev) 89static int __init h1940bt_probe(struct platform_device *pdev)
88{ 90{
89 /* Configures BT serial port GPIOs */ 91 /* Configures BT serial port GPIOs */
90 s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0); 92 s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
91 s3c2410_gpio_pullup(S3C2410_GPH0, 1); 93 s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
92 s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP); 94 s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
93 s3c2410_gpio_pullup(S3C2410_GPH1, 1); 95 s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
94 s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0); 96 s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
95 s3c2410_gpio_pullup(S3C2410_GPH2, 1); 97 s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
96 s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0); 98 s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
97 s3c2410_gpio_pullup(S3C2410_GPH3, 1); 99 s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
98 100
99#ifdef CONFIG_LEDS_H1940 101#ifdef CONFIG_LEDS_H1940
100 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); 102 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
index 6c9fbb99ef14..8fe192081d3a 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
24{ 24{
25 struct s3c_gpio_chip *chip; 25 struct s3c_gpio_chip *chip;
26 26
27 if (pin > S3C2410_GPG10) 27 if (pin > S3C2410_GPG(10))
28 return NULL; 28 return NULL;
29 29
30 chip = &s3c24xx_gpios[pin/32]; 30 chip = &s3c24xx_gpios[pin/32];
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
new file mode 100644
index 000000000000..801dff13858d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -0,0 +1,103 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
2 *
3 * Copyright (c) 2003,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - hardware
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* These functions are in the to-be-removed category and it is strongly
14 * encouraged not to use these in new code. They will be marked deprecated
15 * very soon.
16 *
17 * Most of the functionality can be either replaced by the gpiocfg calls
18 * for the s3c platform or by the generic GPIOlib API.
19*/
20
21/* external functions for GPIO support
22 *
23 * These allow various different clients to access the same GPIO
24 * registers without conflicting. If your driver only owns the entire
25 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
26*/
27
28/* s3c2410_gpio_cfgpin
29 *
30 * set the configuration of the given pin to the value passed.
31 *
32 * eg:
33 * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
34 * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
35*/
36
37extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
38
39extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
40
41/* s3c2410_gpio_getirq
42 *
43 * turn the given pin number into the corresponding IRQ number
44 *
45 * returns:
46 * < 0 = no interrupt for this pin
47 * >=0 = interrupt number for the pin
48*/
49
50extern int s3c2410_gpio_getirq(unsigned int pin);
51
52#ifdef CONFIG_CPU_S3C2400
53
54extern int s3c2400_gpio_getirq(unsigned int pin);
55
56#endif /* CONFIG_CPU_S3C2400 */
57
58/* s3c2410_gpio_irqfilter
59 *
60 * set the irq filtering on the given pin
61 *
62 * on = 0 => disable filtering
63 * 1 => enable filtering
64 *
65 * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
66 * width of filter (0 through 63)
67 *
68 *
69*/
70
71extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
72 unsigned int config);
73
74/* s3c2410_gpio_pullup
75 *
76 * configure the pull-up control on the given pin
77 *
78 * to = 1 => disable the pull-up
79 * 0 => enable the pull-up
80 *
81 * eg;
82 *
83 * s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
84 * s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
85*/
86
87extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
88
89/* s3c2410_gpio_getpull
90 *
91 * Read the state of the pull-up on a given pin
92 *
93 * return:
94 * < 0 => error code
95 * 0 => enabled
96 * 1 => disabled
97*/
98
99extern int s3c2410_gpio_getpull(unsigned int pin);
100
101extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
102
103extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index ce1ec69806a1..2edbb9c88ab3 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -11,6 +11,9 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12*/ 12*/
13 13
14#ifndef __MACH_GPIONRS_H
15#define __MACH_GPIONRS_H
16
14#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) 17#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
15 18
16#define S3C2410_GPIO_BANKA (32*0) 19#define S3C2410_GPIO_BANKA (32*0)
@@ -21,3 +24,70 @@
21#define S3C2410_GPIO_BANKF (32*5) 24#define S3C2410_GPIO_BANKF (32*5)
22#define S3C2410_GPIO_BANKG (32*6) 25#define S3C2410_GPIO_BANKG (32*6)
23#define S3C2410_GPIO_BANKH (32*7) 26#define S3C2410_GPIO_BANKH (32*7)
27
28/* GPIO bank sizes */
29#define S3C2410_GPIO_A_NR (32)
30#define S3C2410_GPIO_B_NR (32)
31#define S3C2410_GPIO_C_NR (32)
32#define S3C2410_GPIO_D_NR (32)
33#define S3C2410_GPIO_E_NR (32)
34#define S3C2410_GPIO_F_NR (32)
35#define S3C2410_GPIO_G_NR (32)
36#define S3C2410_GPIO_H_NR (32)
37
38#if CONFIG_S3C_GPIO_SPACE != 0
39#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
40#endif
41
42#define S3C2410_GPIO_NEXT(__gpio) \
43 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
44
45#ifndef __ASSEMBLY__
46
47enum s3c_gpio_number {
48 S3C2410_GPIO_A_START = 0,
49 S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
50 S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
51 S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
52 S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
53 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
54 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
55 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
56};
57
58#endif /* __ASSEMBLY__ */
59
60/* S3C2410 GPIO number definitions. */
61
62#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
63#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
64#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
65#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
66#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
67#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
68#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
69#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
70
71/* compatibility until drivers can be modified */
72
73#define S3C2410_GPA0 S3C2410_GPA(0)
74#define S3C2410_GPA1 S3C2410_GPA(1)
75#define S3C2410_GPA3 S3C2410_GPA(3)
76#define S3C2410_GPA7 S3C2410_GPA(7)
77
78#define S3C2410_GPE0 S3C2410_GPE(0)
79#define S3C2410_GPE1 S3C2410_GPE(1)
80#define S3C2410_GPE2 S3C2410_GPE(2)
81#define S3C2410_GPE3 S3C2410_GPE(3)
82#define S3C2410_GPE4 S3C2410_GPE(4)
83#define S3C2410_GPE5 S3C2410_GPE(5)
84#define S3C2410_GPE6 S3C2410_GPE(6)
85#define S3C2410_GPE7 S3C2410_GPE(7)
86#define S3C2410_GPE8 S3C2410_GPE(8)
87#define S3C2410_GPE9 S3C2410_GPE(9)
88#define S3C2410_GPE10 S3C2410_GPE(10)
89
90#define S3C2410_GPH10 S3C2410_GPH(10)
91
92#endif /* __MACH_GPIONRS_H */
93
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index 51a88cf9526b..15f0b3e7ce69 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -24,5 +24,6 @@
24 24
25#include <asm-generic/gpio.h> 25#include <asm-generic/gpio.h>
26#include <mach/gpio-nrs.h> 26#include <mach/gpio-nrs.h>
27#include <mach/gpio-fns.h>
27 28
28#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) 29#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h
index 74d5a1a4024c..aef5631eac58 100644
--- a/arch/arm/mach-s3c2410/include/mach/hardware.h
+++ b/arch/arm/mach-s3c2410/include/mach/hardware.h
@@ -15,101 +15,6 @@
15 15
16#ifndef __ASSEMBLY__ 16#ifndef __ASSEMBLY__
17 17
18/* external functions for GPIO support
19 *
20 * These allow various different clients to access the same GPIO
21 * registers without conflicting. If your driver only owns the entire
22 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
23*/
24
25/* s3c2410_gpio_cfgpin
26 *
27 * set the configuration of the given pin to the value passed.
28 *
29 * eg:
30 * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
31 * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
32*/
33
34extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
35
36extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
37
38/* s3c2410_gpio_getirq
39 *
40 * turn the given pin number into the corresponding IRQ number
41 *
42 * returns:
43 * < 0 = no interrupt for this pin
44 * >=0 = interrupt number for the pin
45*/
46
47extern int s3c2410_gpio_getirq(unsigned int pin);
48
49/* s3c2410_gpio_irq2pin
50 *
51 * turn the given irq number into the corresponding GPIO number
52 *
53 * returns:
54 * < 0 = no pin
55 * >=0 = gpio pin number
56*/
57
58extern int s3c2410_gpio_irq2pin(unsigned int irq);
59
60#ifdef CONFIG_CPU_S3C2400
61
62extern int s3c2400_gpio_getirq(unsigned int pin);
63
64#endif /* CONFIG_CPU_S3C2400 */
65
66/* s3c2410_gpio_irqfilter
67 *
68 * set the irq filtering on the given pin
69 *
70 * on = 0 => disable filtering
71 * 1 => enable filtering
72 *
73 * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
74 * width of filter (0 through 63)
75 *
76 *
77*/
78
79extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
80 unsigned int config);
81
82/* s3c2410_gpio_pullup
83 *
84 * configure the pull-up control on the given pin
85 *
86 * to = 1 => disable the pull-up
87 * 0 => enable the pull-up
88 *
89 * eg;
90 *
91 * s3c2410_gpio_pullup(S3C2410_GPB0, 0);
92 * s3c2410_gpio_pullup(S3C2410_GPE8, 0);
93*/
94
95extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
96
97/* s3c2410_gpio_getpull
98 *
99 * Read the state of the pull-up on a given pin
100 *
101 * return:
102 * < 0 => error code
103 * 0 => enabled
104 * 1 => disabled
105*/
106
107extern int s3c2410_gpio_getpull(unsigned int pin);
108
109extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
110
111extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
112
113extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); 18extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
114 19
115#ifdef CONFIG_CPU_S3C2440 20#ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 35a03df473fc..b278d0c45ccf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -69,104 +69,58 @@
69#define S3C2400_GPACON S3C2410_GPIOREG(0x00) 69#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
70#define S3C2400_GPADAT S3C2410_GPIOREG(0x04) 70#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
71 71
72#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
73#define S3C2410_GPA0_OUT (0<<0)
74#define S3C2410_GPA0_ADDR0 (1<<0) 72#define S3C2410_GPA0_ADDR0 (1<<0)
75 73
76#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
77#define S3C2410_GPA1_OUT (0<<1)
78#define S3C2410_GPA1_ADDR16 (1<<1) 74#define S3C2410_GPA1_ADDR16 (1<<1)
79 75
80#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
81#define S3C2410_GPA2_OUT (0<<2)
82#define S3C2410_GPA2_ADDR17 (1<<2) 76#define S3C2410_GPA2_ADDR17 (1<<2)
83 77
84#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
85#define S3C2410_GPA3_OUT (0<<3)
86#define S3C2410_GPA3_ADDR18 (1<<3) 78#define S3C2410_GPA3_ADDR18 (1<<3)
87 79
88#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
89#define S3C2410_GPA4_OUT (0<<4)
90#define S3C2410_GPA4_ADDR19 (1<<4) 80#define S3C2410_GPA4_ADDR19 (1<<4)
91 81
92#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
93#define S3C2410_GPA5_OUT (0<<5)
94#define S3C2410_GPA5_ADDR20 (1<<5) 82#define S3C2410_GPA5_ADDR20 (1<<5)
95 83
96#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
97#define S3C2410_GPA6_OUT (0<<6)
98#define S3C2410_GPA6_ADDR21 (1<<6) 84#define S3C2410_GPA6_ADDR21 (1<<6)
99 85
100#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
101#define S3C2410_GPA7_OUT (0<<7)
102#define S3C2410_GPA7_ADDR22 (1<<7) 86#define S3C2410_GPA7_ADDR22 (1<<7)
103 87
104#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
105#define S3C2410_GPA8_OUT (0<<8)
106#define S3C2410_GPA8_ADDR23 (1<<8) 88#define S3C2410_GPA8_ADDR23 (1<<8)
107 89
108#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
109#define S3C2410_GPA9_OUT (0<<9)
110#define S3C2410_GPA9_ADDR24 (1<<9) 90#define S3C2410_GPA9_ADDR24 (1<<9)
111 91
112#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
113#define S3C2410_GPA10_OUT (0<<10)
114#define S3C2410_GPA10_ADDR25 (1<<10) 92#define S3C2410_GPA10_ADDR25 (1<<10)
115#define S3C2400_GPA10_SCKE (1<<10) 93#define S3C2400_GPA10_SCKE (1<<10)
116 94
117#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
118#define S3C2410_GPA11_OUT (0<<11)
119#define S3C2410_GPA11_ADDR26 (1<<11) 95#define S3C2410_GPA11_ADDR26 (1<<11)
120#define S3C2400_GPA11_nCAS0 (1<<11) 96#define S3C2400_GPA11_nCAS0 (1<<11)
121 97
122#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
123#define S3C2410_GPA12_OUT (0<<12)
124#define S3C2410_GPA12_nGCS1 (1<<12) 98#define S3C2410_GPA12_nGCS1 (1<<12)
125#define S3C2400_GPA12_nCAS1 (1<<12) 99#define S3C2400_GPA12_nCAS1 (1<<12)
126 100
127#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
128#define S3C2410_GPA13_OUT (0<<13)
129#define S3C2410_GPA13_nGCS2 (1<<13) 101#define S3C2410_GPA13_nGCS2 (1<<13)
130#define S3C2400_GPA13_nGCS1 (1<<13) 102#define S3C2400_GPA13_nGCS1 (1<<13)
131 103
132#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
133#define S3C2410_GPA14_OUT (0<<14)
134#define S3C2410_GPA14_nGCS3 (1<<14) 104#define S3C2410_GPA14_nGCS3 (1<<14)
135#define S3C2400_GPA14_nGCS2 (1<<14) 105#define S3C2400_GPA14_nGCS2 (1<<14)
136 106
137#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
138#define S3C2410_GPA15_OUT (0<<15)
139#define S3C2410_GPA15_nGCS4 (1<<15) 107#define S3C2410_GPA15_nGCS4 (1<<15)
140#define S3C2400_GPA15_nGCS3 (1<<15) 108#define S3C2400_GPA15_nGCS3 (1<<15)
141 109
142#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
143#define S3C2410_GPA16_OUT (0<<16)
144#define S3C2410_GPA16_nGCS5 (1<<16) 110#define S3C2410_GPA16_nGCS5 (1<<16)
145#define S3C2400_GPA16_nGCS4 (1<<16) 111#define S3C2400_GPA16_nGCS4 (1<<16)
146 112
147#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
148#define S3C2410_GPA17_OUT (0<<17)
149#define S3C2410_GPA17_CLE (1<<17) 113#define S3C2410_GPA17_CLE (1<<17)
150#define S3C2400_GPA17_nGCS5 (1<<17) 114#define S3C2400_GPA17_nGCS5 (1<<17)
151 115
152#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
153#define S3C2410_GPA18_OUT (0<<18)
154#define S3C2410_GPA18_ALE (1<<18) 116#define S3C2410_GPA18_ALE (1<<18)
155 117
156#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
157#define S3C2410_GPA19_OUT (0<<19)
158#define S3C2410_GPA19_nFWE (1<<19) 118#define S3C2410_GPA19_nFWE (1<<19)
159 119
160#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
161#define S3C2410_GPA20_OUT (0<<20)
162#define S3C2410_GPA20_nFRE (1<<20) 120#define S3C2410_GPA20_nFRE (1<<20)
163 121
164#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
165#define S3C2410_GPA21_OUT (0<<21)
166#define S3C2410_GPA21_nRSTOUT (1<<21) 122#define S3C2410_GPA21_nRSTOUT (1<<21)
167 123
168#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
169#define S3C2410_GPA22_OUT (0<<22)
170#define S3C2410_GPA22_nFCE (1<<22) 124#define S3C2410_GPA22_nFCE (1<<22)
171 125
172/* 0x08 and 0x0c are reserved on S3C2410 */ 126/* 0x08 and 0x0c are reserved on S3C2410 */
@@ -194,107 +148,69 @@
194 148
195/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ 149/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
196 150
197#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
198#define S3C2410_GPB0_INP (0x00 << 0)
199#define S3C2410_GPB0_OUTP (0x01 << 0)
200#define S3C2410_GPB0_TOUT0 (0x02 << 0) 151#define S3C2410_GPB0_TOUT0 (0x02 << 0)
201#define S3C2400_GPB0_DATA16 (0x02 << 0) 152#define S3C2400_GPB0_DATA16 (0x02 << 0)
202 153
203#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
204#define S3C2410_GPB1_INP (0x00 << 2)
205#define S3C2410_GPB1_OUTP (0x01 << 2)
206#define S3C2410_GPB1_TOUT1 (0x02 << 2) 154#define S3C2410_GPB1_TOUT1 (0x02 << 2)
207#define S3C2400_GPB1_DATA17 (0x02 << 2) 155#define S3C2400_GPB1_DATA17 (0x02 << 2)
208 156
209#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
210#define S3C2410_GPB2_INP (0x00 << 4)
211#define S3C2410_GPB2_OUTP (0x01 << 4)
212#define S3C2410_GPB2_TOUT2 (0x02 << 4) 157#define S3C2410_GPB2_TOUT2 (0x02 << 4)
213#define S3C2400_GPB2_DATA18 (0x02 << 4) 158#define S3C2400_GPB2_DATA18 (0x02 << 4)
214#define S3C2400_GPB2_TCLK1 (0x03 << 4) 159#define S3C2400_GPB2_TCLK1 (0x03 << 4)
215 160
216#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
217#define S3C2410_GPB3_INP (0x00 << 6)
218#define S3C2410_GPB3_OUTP (0x01 << 6)
219#define S3C2410_GPB3_TOUT3 (0x02 << 6) 161#define S3C2410_GPB3_TOUT3 (0x02 << 6)
220#define S3C2400_GPB3_DATA19 (0x02 << 6) 162#define S3C2400_GPB3_DATA19 (0x02 << 6)
221#define S3C2400_GPB3_TXD1 (0x03 << 6) 163#define S3C2400_GPB3_TXD1 (0x03 << 6)
222 164
223#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
224#define S3C2410_GPB4_INP (0x00 << 8)
225#define S3C2410_GPB4_OUTP (0x01 << 8)
226#define S3C2410_GPB4_TCLK0 (0x02 << 8) 165#define S3C2410_GPB4_TCLK0 (0x02 << 8)
227#define S3C2400_GPB4_DATA20 (0x02 << 8) 166#define S3C2400_GPB4_DATA20 (0x02 << 8)
228#define S3C2410_GPB4_MASK (0x03 << 8) 167#define S3C2410_GPB4_MASK (0x03 << 8)
229#define S3C2400_GPB4_RXD1 (0x03 << 8) 168#define S3C2400_GPB4_RXD1 (0x03 << 8)
230#define S3C2400_GPB4_MASK (0x03 << 8) 169#define S3C2400_GPB4_MASK (0x03 << 8)
231 170
232#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
233#define S3C2410_GPB5_INP (0x00 << 10)
234#define S3C2410_GPB5_OUTP (0x01 << 10)
235#define S3C2410_GPB5_nXBACK (0x02 << 10) 171#define S3C2410_GPB5_nXBACK (0x02 << 10)
236#define S3C2443_GPB5_XBACK (0x03 << 10) 172#define S3C2443_GPB5_XBACK (0x03 << 10)
237#define S3C2400_GPB5_DATA21 (0x02 << 10) 173#define S3C2400_GPB5_DATA21 (0x02 << 10)
238#define S3C2400_GPB5_nCTS1 (0x03 << 10) 174#define S3C2400_GPB5_nCTS1 (0x03 << 10)
239 175
240#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
241#define S3C2410_GPB6_INP (0x00 << 12)
242#define S3C2410_GPB6_OUTP (0x01 << 12)
243#define S3C2410_GPB6_nXBREQ (0x02 << 12) 176#define S3C2410_GPB6_nXBREQ (0x02 << 12)
244#define S3C2443_GPB6_XBREQ (0x03 << 12) 177#define S3C2443_GPB6_XBREQ (0x03 << 12)
245#define S3C2400_GPB6_DATA22 (0x02 << 12) 178#define S3C2400_GPB6_DATA22 (0x02 << 12)
246#define S3C2400_GPB6_nRTS1 (0x03 << 12) 179#define S3C2400_GPB6_nRTS1 (0x03 << 12)
247 180
248#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
249#define S3C2410_GPB7_INP (0x00 << 14)
250#define S3C2410_GPB7_OUTP (0x01 << 14)
251#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 181#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
252#define S3C2443_GPB7_XDACK1 (0x03 << 14) 182#define S3C2443_GPB7_XDACK1 (0x03 << 14)
253#define S3C2400_GPB7_DATA23 (0x02 << 14) 183#define S3C2400_GPB7_DATA23 (0x02 << 14)
254 184
255#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
256#define S3C2410_GPB8_INP (0x00 << 16)
257#define S3C2410_GPB8_OUTP (0x01 << 16)
258#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 185#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
259#define S3C2400_GPB8_DATA24 (0x02 << 16) 186#define S3C2400_GPB8_DATA24 (0x02 << 16)
260 187
261#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
262#define S3C2410_GPB9_INP (0x00 << 18)
263#define S3C2410_GPB9_OUTP (0x01 << 18)
264#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 188#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
265#define S3C2443_GPB9_XDACK0 (0x03 << 18) 189#define S3C2443_GPB9_XDACK0 (0x03 << 18)
266#define S3C2400_GPB9_DATA25 (0x02 << 18) 190#define S3C2400_GPB9_DATA25 (0x02 << 18)
267#define S3C2400_GPB9_I2SSDI (0x03 << 18) 191#define S3C2400_GPB9_I2SSDI (0x03 << 18)
268 192
269#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
270#define S3C2410_GPB10_INP (0x00 << 20)
271#define S3C2410_GPB10_OUTP (0x01 << 20)
272#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 193#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
273#define S3C2443_GPB10_XDREQ0 (0x03 << 20) 194#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
274#define S3C2400_GPB10_DATA26 (0x02 << 20) 195#define S3C2400_GPB10_DATA26 (0x02 << 20)
275#define S3C2400_GPB10_nSS (0x03 << 20) 196#define S3C2400_GPB10_nSS (0x03 << 20)
276 197
277#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
278#define S3C2400_GPB11_INP (0x00 << 22) 198#define S3C2400_GPB11_INP (0x00 << 22)
279#define S3C2400_GPB11_OUTP (0x01 << 22) 199#define S3C2400_GPB11_OUTP (0x01 << 22)
280#define S3C2400_GPB11_DATA27 (0x02 << 22) 200#define S3C2400_GPB11_DATA27 (0x02 << 22)
281 201
282#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
283#define S3C2400_GPB12_INP (0x00 << 24) 202#define S3C2400_GPB12_INP (0x00 << 24)
284#define S3C2400_GPB12_OUTP (0x01 << 24) 203#define S3C2400_GPB12_OUTP (0x01 << 24)
285#define S3C2400_GPB12_DATA28 (0x02 << 24) 204#define S3C2400_GPB12_DATA28 (0x02 << 24)
286 205
287#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
288#define S3C2400_GPB13_INP (0x00 << 26) 206#define S3C2400_GPB13_INP (0x00 << 26)
289#define S3C2400_GPB13_OUTP (0x01 << 26) 207#define S3C2400_GPB13_OUTP (0x01 << 26)
290#define S3C2400_GPB13_DATA29 (0x02 << 26) 208#define S3C2400_GPB13_DATA29 (0x02 << 26)
291 209
292#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
293#define S3C2400_GPB14_INP (0x00 << 28) 210#define S3C2400_GPB14_INP (0x00 << 28)
294#define S3C2400_GPB14_OUTP (0x01 << 28) 211#define S3C2400_GPB14_OUTP (0x01 << 28)
295#define S3C2400_GPB14_DATA30 (0x02 << 28) 212#define S3C2400_GPB14_DATA30 (0x02 << 28)
296 213
297#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
298#define S3C2400_GPB15_INP (0x00 << 30) 214#define S3C2400_GPB15_INP (0x00 << 30)
299#define S3C2400_GPB15_OUTP (0x01 << 30) 215#define S3C2400_GPB15_OUTP (0x01 << 30)
300#define S3C2400_GPB15_DATA31 (0x02 << 30) 216#define S3C2400_GPB15_DATA31 (0x02 << 30)
@@ -315,99 +231,51 @@
315#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) 231#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
316#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) 232#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
317 233
318#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
319#define S3C2410_GPC0_INP (0x00 << 0)
320#define S3C2410_GPC0_OUTP (0x01 << 0)
321#define S3C2410_GPC0_LEND (0x02 << 0) 234#define S3C2410_GPC0_LEND (0x02 << 0)
322#define S3C2400_GPC0_VD0 (0x02 << 0) 235#define S3C2400_GPC0_VD0 (0x02 << 0)
323 236
324#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
325#define S3C2410_GPC1_INP (0x00 << 2)
326#define S3C2410_GPC1_OUTP (0x01 << 2)
327#define S3C2410_GPC1_VCLK (0x02 << 2) 237#define S3C2410_GPC1_VCLK (0x02 << 2)
328#define S3C2400_GPC1_VD1 (0x02 << 2) 238#define S3C2400_GPC1_VD1 (0x02 << 2)
329 239
330#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
331#define S3C2410_GPC2_INP (0x00 << 4)
332#define S3C2410_GPC2_OUTP (0x01 << 4)
333#define S3C2410_GPC2_VLINE (0x02 << 4) 240#define S3C2410_GPC2_VLINE (0x02 << 4)
334#define S3C2400_GPC2_VD2 (0x02 << 4) 241#define S3C2400_GPC2_VD2 (0x02 << 4)
335 242
336#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
337#define S3C2410_GPC3_INP (0x00 << 6)
338#define S3C2410_GPC3_OUTP (0x01 << 6)
339#define S3C2410_GPC3_VFRAME (0x02 << 6) 243#define S3C2410_GPC3_VFRAME (0x02 << 6)
340#define S3C2400_GPC3_VD3 (0x02 << 6) 244#define S3C2400_GPC3_VD3 (0x02 << 6)
341 245
342#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
343#define S3C2410_GPC4_INP (0x00 << 8)
344#define S3C2410_GPC4_OUTP (0x01 << 8)
345#define S3C2410_GPC4_VM (0x02 << 8) 246#define S3C2410_GPC4_VM (0x02 << 8)
346#define S3C2400_GPC4_VD4 (0x02 << 8) 247#define S3C2400_GPC4_VD4 (0x02 << 8)
347 248
348#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
349#define S3C2410_GPC5_INP (0x00 << 10)
350#define S3C2410_GPC5_OUTP (0x01 << 10)
351#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 249#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
352#define S3C2400_GPC5_VD5 (0x02 << 10) 250#define S3C2400_GPC5_VD5 (0x02 << 10)
353 251
354#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
355#define S3C2410_GPC6_INP (0x00 << 12)
356#define S3C2410_GPC6_OUTP (0x01 << 12)
357#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 252#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
358#define S3C2400_GPC6_VD6 (0x02 << 12) 253#define S3C2400_GPC6_VD6 (0x02 << 12)
359 254
360#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
361#define S3C2410_GPC7_INP (0x00 << 14)
362#define S3C2410_GPC7_OUTP (0x01 << 14)
363#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 255#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
364#define S3C2400_GPC7_VD7 (0x02 << 14) 256#define S3C2400_GPC7_VD7 (0x02 << 14)
365 257
366#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
367#define S3C2410_GPC8_INP (0x00 << 16)
368#define S3C2410_GPC8_OUTP (0x01 << 16)
369#define S3C2410_GPC8_VD0 (0x02 << 16) 258#define S3C2410_GPC8_VD0 (0x02 << 16)
370#define S3C2400_GPC8_VD8 (0x02 << 16) 259#define S3C2400_GPC8_VD8 (0x02 << 16)
371 260
372#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
373#define S3C2410_GPC9_INP (0x00 << 18)
374#define S3C2410_GPC9_OUTP (0x01 << 18)
375#define S3C2410_GPC9_VD1 (0x02 << 18) 261#define S3C2410_GPC9_VD1 (0x02 << 18)
376#define S3C2400_GPC9_VD9 (0x02 << 18) 262#define S3C2400_GPC9_VD9 (0x02 << 18)
377 263
378#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
379#define S3C2410_GPC10_INP (0x00 << 20)
380#define S3C2410_GPC10_OUTP (0x01 << 20)
381#define S3C2410_GPC10_VD2 (0x02 << 20) 264#define S3C2410_GPC10_VD2 (0x02 << 20)
382#define S3C2400_GPC10_VD10 (0x02 << 20) 265#define S3C2400_GPC10_VD10 (0x02 << 20)
383 266
384#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
385#define S3C2410_GPC11_INP (0x00 << 22)
386#define S3C2410_GPC11_OUTP (0x01 << 22)
387#define S3C2410_GPC11_VD3 (0x02 << 22) 267#define S3C2410_GPC11_VD3 (0x02 << 22)
388#define S3C2400_GPC11_VD11 (0x02 << 22) 268#define S3C2400_GPC11_VD11 (0x02 << 22)
389 269
390#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
391#define S3C2410_GPC12_INP (0x00 << 24)
392#define S3C2410_GPC12_OUTP (0x01 << 24)
393#define S3C2410_GPC12_VD4 (0x02 << 24) 270#define S3C2410_GPC12_VD4 (0x02 << 24)
394#define S3C2400_GPC12_VD12 (0x02 << 24) 271#define S3C2400_GPC12_VD12 (0x02 << 24)
395 272
396#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
397#define S3C2410_GPC13_INP (0x00 << 26)
398#define S3C2410_GPC13_OUTP (0x01 << 26)
399#define S3C2410_GPC13_VD5 (0x02 << 26) 273#define S3C2410_GPC13_VD5 (0x02 << 26)
400#define S3C2400_GPC13_VD13 (0x02 << 26) 274#define S3C2400_GPC13_VD13 (0x02 << 26)
401 275
402#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
403#define S3C2410_GPC14_INP (0x00 << 28)
404#define S3C2410_GPC14_OUTP (0x01 << 28)
405#define S3C2410_GPC14_VD6 (0x02 << 28) 276#define S3C2410_GPC14_VD6 (0x02 << 28)
406#define S3C2400_GPC14_VD14 (0x02 << 28) 277#define S3C2400_GPC14_VD14 (0x02 << 28)
407 278
408#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
409#define S3C2410_GPC15_INP (0x00 << 30)
410#define S3C2410_GPC15_OUTP (0x01 << 30)
411#define S3C2410_GPC15_VD7 (0x02 << 30) 279#define S3C2410_GPC15_VD7 (0x02 << 30)
412#define S3C2400_GPC15_VD15 (0x02 << 30) 280#define S3C2400_GPC15_VD15 (0x02 << 30)
413 281
@@ -432,99 +300,51 @@
432#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) 300#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
433#define S3C2400_GPDUP S3C2410_GPIOREG(0x28) 301#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
434 302
435#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
436#define S3C2410_GPD0_INP (0x00 << 0)
437#define S3C2410_GPD0_OUTP (0x01 << 0)
438#define S3C2410_GPD0_VD8 (0x02 << 0) 303#define S3C2410_GPD0_VD8 (0x02 << 0)
439#define S3C2400_GPD0_VFRAME (0x02 << 0) 304#define S3C2400_GPD0_VFRAME (0x02 << 0)
440#define S3C2442_GPD0_nSPICS1 (0x03 << 0) 305#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
441 306
442#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
443#define S3C2410_GPD1_INP (0x00 << 2)
444#define S3C2410_GPD1_OUTP (0x01 << 2)
445#define S3C2410_GPD1_VD9 (0x02 << 2) 307#define S3C2410_GPD1_VD9 (0x02 << 2)
446#define S3C2400_GPD1_VM (0x02 << 2) 308#define S3C2400_GPD1_VM (0x02 << 2)
447#define S3C2442_GPD1_SPICLK1 (0x03 << 2) 309#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
448 310
449#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
450#define S3C2410_GPD2_INP (0x00 << 4)
451#define S3C2410_GPD2_OUTP (0x01 << 4)
452#define S3C2410_GPD2_VD10 (0x02 << 4) 311#define S3C2410_GPD2_VD10 (0x02 << 4)
453#define S3C2400_GPD2_VLINE (0x02 << 4) 312#define S3C2400_GPD2_VLINE (0x02 << 4)
454 313
455#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
456#define S3C2410_GPD3_INP (0x00 << 6)
457#define S3C2410_GPD3_OUTP (0x01 << 6)
458#define S3C2410_GPD3_VD11 (0x02 << 6) 314#define S3C2410_GPD3_VD11 (0x02 << 6)
459#define S3C2400_GPD3_VCLK (0x02 << 6) 315#define S3C2400_GPD3_VCLK (0x02 << 6)
460 316
461#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
462#define S3C2410_GPD4_INP (0x00 << 8)
463#define S3C2410_GPD4_OUTP (0x01 << 8)
464#define S3C2410_GPD4_VD12 (0x02 << 8) 317#define S3C2410_GPD4_VD12 (0x02 << 8)
465#define S3C2400_GPD4_LEND (0x02 << 8) 318#define S3C2400_GPD4_LEND (0x02 << 8)
466 319
467#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
468#define S3C2410_GPD5_INP (0x00 << 10)
469#define S3C2410_GPD5_OUTP (0x01 << 10)
470#define S3C2410_GPD5_VD13 (0x02 << 10) 320#define S3C2410_GPD5_VD13 (0x02 << 10)
471#define S3C2400_GPD5_TOUT0 (0x02 << 10) 321#define S3C2400_GPD5_TOUT0 (0x02 << 10)
472 322
473#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
474#define S3C2410_GPD6_INP (0x00 << 12)
475#define S3C2410_GPD6_OUTP (0x01 << 12)
476#define S3C2410_GPD6_VD14 (0x02 << 12) 323#define S3C2410_GPD6_VD14 (0x02 << 12)
477#define S3C2400_GPD6_TOUT1 (0x02 << 12) 324#define S3C2400_GPD6_TOUT1 (0x02 << 12)
478 325
479#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
480#define S3C2410_GPD7_INP (0x00 << 14)
481#define S3C2410_GPD7_OUTP (0x01 << 14)
482#define S3C2410_GPD7_VD15 (0x02 << 14) 326#define S3C2410_GPD7_VD15 (0x02 << 14)
483#define S3C2400_GPD7_TOUT2 (0x02 << 14) 327#define S3C2400_GPD7_TOUT2 (0x02 << 14)
484 328
485#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
486#define S3C2410_GPD8_INP (0x00 << 16)
487#define S3C2410_GPD8_OUTP (0x01 << 16)
488#define S3C2410_GPD8_VD16 (0x02 << 16) 329#define S3C2410_GPD8_VD16 (0x02 << 16)
489#define S3C2400_GPD8_TOUT3 (0x02 << 16) 330#define S3C2400_GPD8_TOUT3 (0x02 << 16)
490 331
491#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
492#define S3C2410_GPD9_INP (0x00 << 18)
493#define S3C2410_GPD9_OUTP (0x01 << 18)
494#define S3C2410_GPD9_VD17 (0x02 << 18) 332#define S3C2410_GPD9_VD17 (0x02 << 18)
495#define S3C2400_GPD9_TCLK0 (0x02 << 18) 333#define S3C2400_GPD9_TCLK0 (0x02 << 18)
496#define S3C2410_GPD9_MASK (0x03 << 18) 334#define S3C2410_GPD9_MASK (0x03 << 18)
497 335
498#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
499#define S3C2410_GPD10_INP (0x00 << 20)
500#define S3C2410_GPD10_OUTP (0x01 << 20)
501#define S3C2410_GPD10_VD18 (0x02 << 20) 336#define S3C2410_GPD10_VD18 (0x02 << 20)
502#define S3C2400_GPD10_nWAIT (0x02 << 20) 337#define S3C2400_GPD10_nWAIT (0x02 << 20)
503 338
504#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
505#define S3C2410_GPD11_INP (0x00 << 22)
506#define S3C2410_GPD11_OUTP (0x01 << 22)
507#define S3C2410_GPD11_VD19 (0x02 << 22) 339#define S3C2410_GPD11_VD19 (0x02 << 22)
508 340
509#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
510#define S3C2410_GPD12_INP (0x00 << 24)
511#define S3C2410_GPD12_OUTP (0x01 << 24)
512#define S3C2410_GPD12_VD20 (0x02 << 24) 341#define S3C2410_GPD12_VD20 (0x02 << 24)
513 342
514#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
515#define S3C2410_GPD13_INP (0x00 << 26)
516#define S3C2410_GPD13_OUTP (0x01 << 26)
517#define S3C2410_GPD13_VD21 (0x02 << 26) 343#define S3C2410_GPD13_VD21 (0x02 << 26)
518 344
519#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
520#define S3C2410_GPD14_INP (0x00 << 28)
521#define S3C2410_GPD14_OUTP (0x01 << 28)
522#define S3C2410_GPD14_VD22 (0x02 << 28) 345#define S3C2410_GPD14_VD22 (0x02 << 28)
523#define S3C2410_GPD14_nSS1 (0x03 << 28) 346#define S3C2410_GPD14_nSS1 (0x03 << 28)
524 347
525#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
526#define S3C2410_GPD15_INP (0x00 << 30)
527#define S3C2410_GPD15_OUTP (0x01 << 30)
528#define S3C2410_GPD15_VD23 (0x02 << 30) 348#define S3C2410_GPD15_VD23 (0x02 << 30)
529#define S3C2410_GPD15_nSS0 (0x03 << 30) 349#define S3C2410_GPD15_nSS0 (0x03 << 30)
530 350
@@ -550,34 +370,22 @@
550#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) 370#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
551#define S3C2400_GPEUP S3C2410_GPIOREG(0x34) 371#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
552 372
553#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
554#define S3C2410_GPE0_INP (0x00 << 0)
555#define S3C2410_GPE0_OUTP (0x01 << 0)
556#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 373#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
557#define S3C2443_GPE0_AC_nRESET (0x03 << 0) 374#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
558#define S3C2400_GPE0_EINT0 (0x02 << 0) 375#define S3C2400_GPE0_EINT0 (0x02 << 0)
559#define S3C2410_GPE0_MASK (0x03 << 0) 376#define S3C2410_GPE0_MASK (0x03 << 0)
560 377
561#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
562#define S3C2410_GPE1_INP (0x00 << 2)
563#define S3C2410_GPE1_OUTP (0x01 << 2)
564#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 378#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
565#define S3C2443_GPE1_AC_SYNC (0x03 << 2) 379#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
566#define S3C2400_GPE1_EINT1 (0x02 << 2) 380#define S3C2400_GPE1_EINT1 (0x02 << 2)
567#define S3C2400_GPE1_nSS (0x03 << 2) 381#define S3C2400_GPE1_nSS (0x03 << 2)
568#define S3C2410_GPE1_MASK (0x03 << 2) 382#define S3C2410_GPE1_MASK (0x03 << 2)
569 383
570#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
571#define S3C2410_GPE2_INP (0x00 << 4)
572#define S3C2410_GPE2_OUTP (0x01 << 4)
573#define S3C2410_GPE2_CDCLK (0x02 << 4) 384#define S3C2410_GPE2_CDCLK (0x02 << 4)
574#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) 385#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
575#define S3C2400_GPE2_EINT2 (0x02 << 4) 386#define S3C2400_GPE2_EINT2 (0x02 << 4)
576#define S3C2400_GPE2_I2SSDI (0x03 << 4) 387#define S3C2400_GPE2_I2SSDI (0x03 << 4)
577 388
578#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
579#define S3C2410_GPE3_INP (0x00 << 6)
580#define S3C2410_GPE3_OUTP (0x01 << 6)
581#define S3C2410_GPE3_I2SSDI (0x02 << 6) 389#define S3C2410_GPE3_I2SSDI (0x02 << 6)
582#define S3C2443_GPE3_AC_SDI (0x03 << 6) 390#define S3C2443_GPE3_AC_SDI (0x03 << 6)
583#define S3C2400_GPE3_EINT3 (0x02 << 6) 391#define S3C2400_GPE3_EINT3 (0x02 << 6)
@@ -585,9 +393,6 @@
585#define S3C2410_GPE3_nSS0 (0x03 << 6) 393#define S3C2410_GPE3_nSS0 (0x03 << 6)
586#define S3C2410_GPE3_MASK (0x03 << 6) 394#define S3C2410_GPE3_MASK (0x03 << 6)
587 395
588#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
589#define S3C2410_GPE4_INP (0x00 << 8)
590#define S3C2410_GPE4_OUTP (0x01 << 8)
591#define S3C2410_GPE4_I2SSDO (0x02 << 8) 396#define S3C2410_GPE4_I2SSDO (0x02 << 8)
592#define S3C2443_GPE4_AC_SDO (0x03 << 8) 397#define S3C2443_GPE4_AC_SDO (0x03 << 8)
593#define S3C2400_GPE4_EINT4 (0x02 << 8) 398#define S3C2400_GPE4_EINT4 (0x02 << 8)
@@ -595,81 +400,48 @@
595#define S3C2410_GPE4_I2SSDI (0x03 << 8) 400#define S3C2410_GPE4_I2SSDI (0x03 << 8)
596#define S3C2410_GPE4_MASK (0x03 << 8) 401#define S3C2410_GPE4_MASK (0x03 << 8)
597 402
598#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
599#define S3C2410_GPE5_INP (0x00 << 10)
600#define S3C2410_GPE5_OUTP (0x01 << 10)
601#define S3C2410_GPE5_SDCLK (0x02 << 10) 403#define S3C2410_GPE5_SDCLK (0x02 << 10)
602#define S3C2443_GPE5_SD1_CLK (0x02 << 10) 404#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
603#define S3C2400_GPE5_EINT5 (0x02 << 10) 405#define S3C2400_GPE5_EINT5 (0x02 << 10)
604#define S3C2400_GPE5_TCLK1 (0x03 << 10) 406#define S3C2400_GPE5_TCLK1 (0x03 << 10)
605 407
606#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
607#define S3C2410_GPE6_INP (0x00 << 12)
608#define S3C2410_GPE6_OUTP (0x01 << 12)
609#define S3C2410_GPE6_SDCMD (0x02 << 12) 408#define S3C2410_GPE6_SDCMD (0x02 << 12)
610#define S3C2443_GPE6_SD1_CMD (0x02 << 12) 409#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
611#define S3C2443_GPE6_AC_BITCLK (0x03 << 12) 410#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
612#define S3C2400_GPE6_EINT6 (0x02 << 12) 411#define S3C2400_GPE6_EINT6 (0x02 << 12)
613 412
614#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
615#define S3C2410_GPE7_INP (0x00 << 14)
616#define S3C2410_GPE7_OUTP (0x01 << 14)
617#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 413#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
618#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) 414#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
619#define S3C2443_GPE7_AC_SDI (0x03 << 14) 415#define S3C2443_GPE7_AC_SDI (0x03 << 14)
620#define S3C2400_GPE7_EINT7 (0x02 << 14) 416#define S3C2400_GPE7_EINT7 (0x02 << 14)
621 417
622#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
623#define S3C2410_GPE8_INP (0x00 << 16)
624#define S3C2410_GPE8_OUTP (0x01 << 16)
625#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 418#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
626#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) 419#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
627#define S3C2443_GPE8_AC_SDO (0x03 << 16) 420#define S3C2443_GPE8_AC_SDO (0x03 << 16)
628#define S3C2400_GPE8_nXDACK0 (0x02 << 16) 421#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
629 422
630#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
631#define S3C2410_GPE9_INP (0x00 << 18)
632#define S3C2410_GPE9_OUTP (0x01 << 18)
633#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 423#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
634#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) 424#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
635#define S3C2443_GPE9_AC_SYNC (0x03 << 18) 425#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
636#define S3C2400_GPE9_nXDACK1 (0x02 << 18) 426#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
637#define S3C2400_GPE9_nXBACK (0x03 << 18) 427#define S3C2400_GPE9_nXBACK (0x03 << 18)
638 428
639#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
640#define S3C2410_GPE10_INP (0x00 << 20)
641#define S3C2410_GPE10_OUTP (0x01 << 20)
642#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 429#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
643#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) 430#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
644#define S3C2443_GPE10_AC_nRESET (0x03 << 20) 431#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
645#define S3C2400_GPE10_nXDREQ0 (0x02 << 20) 432#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
646 433
647#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
648#define S3C2410_GPE11_INP (0x00 << 22)
649#define S3C2410_GPE11_OUTP (0x01 << 22)
650#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 434#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
651#define S3C2400_GPE11_nXDREQ1 (0x02 << 22) 435#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
652#define S3C2400_GPE11_nXBREQ (0x03 << 22) 436#define S3C2400_GPE11_nXBREQ (0x03 << 22)
653 437
654#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
655#define S3C2410_GPE12_INP (0x00 << 24)
656#define S3C2410_GPE12_OUTP (0x01 << 24)
657#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) 438#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
658 439
659#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
660#define S3C2410_GPE13_INP (0x00 << 26)
661#define S3C2410_GPE13_OUTP (0x01 << 26)
662#define S3C2410_GPE13_SPICLK0 (0x02 << 26) 440#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
663 441
664#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
665#define S3C2410_GPE14_INP (0x00 << 28)
666#define S3C2410_GPE14_OUTP (0x01 << 28)
667#define S3C2410_GPE14_IICSCL (0x02 << 28) 442#define S3C2410_GPE14_IICSCL (0x02 << 28)
668#define S3C2410_GPE14_MASK (0x03 << 28) 443#define S3C2410_GPE14_MASK (0x03 << 28)
669 444
670#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
671#define S3C2410_GPE15_INP (0x00 << 30)
672#define S3C2410_GPE15_OUTP (0x01 << 30)
673#define S3C2410_GPE15_IICSDA (0x02 << 30) 445#define S3C2410_GPE15_IICSDA (0x02 << 30)
674#define S3C2410_GPE15_MASK (0x03 << 30) 446#define S3C2410_GPE15_MASK (0x03 << 30)
675 447
@@ -705,55 +477,31 @@
705#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) 477#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
706#define S3C2400_GPFUP S3C2410_GPIOREG(0x40) 478#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
707 479
708#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
709#define S3C2410_GPF0_INP (0x00 << 0)
710#define S3C2410_GPF0_OUTP (0x01 << 0)
711#define S3C2410_GPF0_EINT0 (0x02 << 0) 480#define S3C2410_GPF0_EINT0 (0x02 << 0)
712#define S3C2400_GPF0_RXD0 (0x02 << 0) 481#define S3C2400_GPF0_RXD0 (0x02 << 0)
713 482
714#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
715#define S3C2410_GPF1_INP (0x00 << 2)
716#define S3C2410_GPF1_OUTP (0x01 << 2)
717#define S3C2410_GPF1_EINT1 (0x02 << 2) 483#define S3C2410_GPF1_EINT1 (0x02 << 2)
718#define S3C2400_GPF1_RXD1 (0x02 << 2) 484#define S3C2400_GPF1_RXD1 (0x02 << 2)
719#define S3C2400_GPF1_IICSDA (0x03 << 2) 485#define S3C2400_GPF1_IICSDA (0x03 << 2)
720 486
721#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
722#define S3C2410_GPF2_INP (0x00 << 4)
723#define S3C2410_GPF2_OUTP (0x01 << 4)
724#define S3C2410_GPF2_EINT2 (0x02 << 4) 487#define S3C2410_GPF2_EINT2 (0x02 << 4)
725#define S3C2400_GPF2_TXD0 (0x02 << 4) 488#define S3C2400_GPF2_TXD0 (0x02 << 4)
726 489
727#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
728#define S3C2410_GPF3_INP (0x00 << 6)
729#define S3C2410_GPF3_OUTP (0x01 << 6)
730#define S3C2410_GPF3_EINT3 (0x02 << 6) 490#define S3C2410_GPF3_EINT3 (0x02 << 6)
731#define S3C2400_GPF3_TXD1 (0x02 << 6) 491#define S3C2400_GPF3_TXD1 (0x02 << 6)
732#define S3C2400_GPF3_IICSCL (0x03 << 6) 492#define S3C2400_GPF3_IICSCL (0x03 << 6)
733 493
734#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
735#define S3C2410_GPF4_INP (0x00 << 8)
736#define S3C2410_GPF4_OUTP (0x01 << 8)
737#define S3C2410_GPF4_EINT4 (0x02 << 8) 494#define S3C2410_GPF4_EINT4 (0x02 << 8)
738#define S3C2400_GPF4_nRTS0 (0x02 << 8) 495#define S3C2400_GPF4_nRTS0 (0x02 << 8)
739#define S3C2400_GPF4_nXBACK (0x03 << 8) 496#define S3C2400_GPF4_nXBACK (0x03 << 8)
740 497
741#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
742#define S3C2410_GPF5_INP (0x00 << 10)
743#define S3C2410_GPF5_OUTP (0x01 << 10)
744#define S3C2410_GPF5_EINT5 (0x02 << 10) 498#define S3C2410_GPF5_EINT5 (0x02 << 10)
745#define S3C2400_GPF5_nCTS0 (0x02 << 10) 499#define S3C2400_GPF5_nCTS0 (0x02 << 10)
746#define S3C2400_GPF5_nXBREQ (0x03 << 10) 500#define S3C2400_GPF5_nXBREQ (0x03 << 10)
747 501
748#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
749#define S3C2410_GPF6_INP (0x00 << 12)
750#define S3C2410_GPF6_OUTP (0x01 << 12)
751#define S3C2410_GPF6_EINT6 (0x02 << 12) 502#define S3C2410_GPF6_EINT6 (0x02 << 12)
752#define S3C2400_GPF6_CLKOUT (0x02 << 12) 503#define S3C2400_GPF6_CLKOUT (0x02 << 12)
753 504
754#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
755#define S3C2410_GPF7_INP (0x00 << 14)
756#define S3C2410_GPF7_OUTP (0x01 << 14)
757#define S3C2410_GPF7_EINT7 (0x02 << 14) 505#define S3C2410_GPF7_EINT7 (0x02 << 14)
758 506
759#define S3C2410_GPF_PUPDIS(x) (1<<(x)) 507#define S3C2410_GPF_PUPDIS(x) (1<<(x))
@@ -778,117 +526,69 @@
778#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) 526#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
779#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) 527#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
780 528
781#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
782#define S3C2410_GPG0_INP (0x00 << 0)
783#define S3C2410_GPG0_OUTP (0x01 << 0)
784#define S3C2410_GPG0_EINT8 (0x02 << 0) 529#define S3C2410_GPG0_EINT8 (0x02 << 0)
785#define S3C2400_GPG0_I2SLRCK (0x02 << 0) 530#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
786 531
787#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
788#define S3C2410_GPG1_INP (0x00 << 2)
789#define S3C2410_GPG1_OUTP (0x01 << 2)
790#define S3C2410_GPG1_EINT9 (0x02 << 2) 532#define S3C2410_GPG1_EINT9 (0x02 << 2)
791#define S3C2400_GPG1_I2SSCLK (0x02 << 2) 533#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
792 534
793#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
794#define S3C2410_GPG2_INP (0x00 << 4)
795#define S3C2410_GPG2_OUTP (0x01 << 4)
796#define S3C2410_GPG2_EINT10 (0x02 << 4) 535#define S3C2410_GPG2_EINT10 (0x02 << 4)
797#define S3C2410_GPG2_nSS0 (0x03 << 4) 536#define S3C2410_GPG2_nSS0 (0x03 << 4)
798#define S3C2400_GPG2_CDCLK (0x02 << 4) 537#define S3C2400_GPG2_CDCLK (0x02 << 4)
799 538
800#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
801#define S3C2410_GPG3_INP (0x00 << 6)
802#define S3C2410_GPG3_OUTP (0x01 << 6)
803#define S3C2410_GPG3_EINT11 (0x02 << 6) 539#define S3C2410_GPG3_EINT11 (0x02 << 6)
804#define S3C2410_GPG3_nSS1 (0x03 << 6) 540#define S3C2410_GPG3_nSS1 (0x03 << 6)
805#define S3C2400_GPG3_I2SSDO (0x02 << 6) 541#define S3C2400_GPG3_I2SSDO (0x02 << 6)
806#define S3C2400_GPG3_I2SSDI (0x03 << 6) 542#define S3C2400_GPG3_I2SSDI (0x03 << 6)
807 543
808#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
809#define S3C2410_GPG4_INP (0x00 << 8)
810#define S3C2410_GPG4_OUTP (0x01 << 8)
811#define S3C2410_GPG4_EINT12 (0x02 << 8) 544#define S3C2410_GPG4_EINT12 (0x02 << 8)
812#define S3C2400_GPG4_MMCCLK (0x02 << 8) 545#define S3C2400_GPG4_MMCCLK (0x02 << 8)
813#define S3C2400_GPG4_I2SSDI (0x03 << 8) 546#define S3C2400_GPG4_I2SSDI (0x03 << 8)
814#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 547#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
815#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) 548#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
816 549
817#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
818#define S3C2410_GPG5_INP (0x00 << 10)
819#define S3C2410_GPG5_OUTP (0x01 << 10)
820#define S3C2410_GPG5_EINT13 (0x02 << 10) 550#define S3C2410_GPG5_EINT13 (0x02 << 10)
821#define S3C2400_GPG5_MMCCMD (0x02 << 10) 551#define S3C2400_GPG5_MMCCMD (0x02 << 10)
822#define S3C2400_GPG5_IICSDA (0x03 << 10) 552#define S3C2400_GPG5_IICSDA (0x03 << 10)
823#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ 553#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
824 554
825#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
826#define S3C2410_GPG6_INP (0x00 << 12)
827#define S3C2410_GPG6_OUTP (0x01 << 12)
828#define S3C2410_GPG6_EINT14 (0x02 << 12) 555#define S3C2410_GPG6_EINT14 (0x02 << 12)
829#define S3C2400_GPG6_MMCDAT (0x02 << 12) 556#define S3C2400_GPG6_MMCDAT (0x02 << 12)
830#define S3C2400_GPG6_IICSCL (0x03 << 12) 557#define S3C2400_GPG6_IICSCL (0x03 << 12)
831#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 558#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
832 559
833#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
834#define S3C2410_GPG7_INP (0x00 << 14)
835#define S3C2410_GPG7_OUTP (0x01 << 14)
836#define S3C2410_GPG7_EINT15 (0x02 << 14) 560#define S3C2410_GPG7_EINT15 (0x02 << 14)
837#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 561#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
838#define S3C2400_GPG7_SPIMISO (0x02 << 14) 562#define S3C2400_GPG7_SPIMISO (0x02 << 14)
839#define S3C2400_GPG7_IICSDA (0x03 << 14) 563#define S3C2400_GPG7_IICSDA (0x03 << 14)
840 564
841#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
842#define S3C2410_GPG8_INP (0x00 << 16)
843#define S3C2410_GPG8_OUTP (0x01 << 16)
844#define S3C2410_GPG8_EINT16 (0x02 << 16) 565#define S3C2410_GPG8_EINT16 (0x02 << 16)
845#define S3C2400_GPG8_SPIMOSI (0x02 << 16) 566#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
846#define S3C2400_GPG8_IICSCL (0x03 << 16) 567#define S3C2400_GPG8_IICSCL (0x03 << 16)
847 568
848#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
849#define S3C2410_GPG9_INP (0x00 << 18)
850#define S3C2410_GPG9_OUTP (0x01 << 18)
851#define S3C2410_GPG9_EINT17 (0x02 << 18) 569#define S3C2410_GPG9_EINT17 (0x02 << 18)
852#define S3C2400_GPG9_SPICLK (0x02 << 18) 570#define S3C2400_GPG9_SPICLK (0x02 << 18)
853#define S3C2400_GPG9_MMCCLK (0x03 << 18) 571#define S3C2400_GPG9_MMCCLK (0x03 << 18)
854 572
855#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
856#define S3C2410_GPG10_INP (0x00 << 20)
857#define S3C2410_GPG10_OUTP (0x01 << 20)
858#define S3C2410_GPG10_EINT18 (0x02 << 20) 573#define S3C2410_GPG10_EINT18 (0x02 << 20)
859 574
860#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
861#define S3C2410_GPG11_INP (0x00 << 22)
862#define S3C2410_GPG11_OUTP (0x01 << 22)
863#define S3C2410_GPG11_EINT19 (0x02 << 22) 575#define S3C2410_GPG11_EINT19 (0x02 << 22)
864#define S3C2410_GPG11_TCLK1 (0x03 << 22) 576#define S3C2410_GPG11_TCLK1 (0x03 << 22)
865#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) 577#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
866 578
867#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
868#define S3C2410_GPG12_INP (0x00 << 24)
869#define S3C2410_GPG12_OUTP (0x01 << 24)
870#define S3C2410_GPG12_EINT20 (0x02 << 24) 579#define S3C2410_GPG12_EINT20 (0x02 << 24)
871#define S3C2410_GPG12_XMON (0x03 << 24) 580#define S3C2410_GPG12_XMON (0x03 << 24)
872#define S3C2442_GPG12_nSPICS0 (0x03 << 24) 581#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
873#define S3C2443_GPG12_nINPACK (0x03 << 24) 582#define S3C2443_GPG12_nINPACK (0x03 << 24)
874 583
875#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
876#define S3C2410_GPG13_INP (0x00 << 26)
877#define S3C2410_GPG13_OUTP (0x01 << 26)
878#define S3C2410_GPG13_EINT21 (0x02 << 26) 584#define S3C2410_GPG13_EINT21 (0x02 << 26)
879#define S3C2410_GPG13_nXPON (0x03 << 26) 585#define S3C2410_GPG13_nXPON (0x03 << 26)
880#define S3C2443_GPG13_CF_nREG (0x03 << 26) 586#define S3C2443_GPG13_CF_nREG (0x03 << 26)
881 587
882#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
883#define S3C2410_GPG14_INP (0x00 << 28)
884#define S3C2410_GPG14_OUTP (0x01 << 28)
885#define S3C2410_GPG14_EINT22 (0x02 << 28) 588#define S3C2410_GPG14_EINT22 (0x02 << 28)
886#define S3C2410_GPG14_YMON (0x03 << 28) 589#define S3C2410_GPG14_YMON (0x03 << 28)
887#define S3C2443_GPG14_CF_RESET (0x03 << 28) 590#define S3C2443_GPG14_CF_RESET (0x03 << 28)
888 591
889#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
890#define S3C2410_GPG15_INP (0x00 << 30)
891#define S3C2410_GPG15_OUTP (0x01 << 30)
892#define S3C2410_GPG15_EINT23 (0x02 << 30) 592#define S3C2410_GPG15_EINT23 (0x02 << 30)
893#define S3C2410_GPG15_nYPON (0x03 << 30) 593#define S3C2410_GPG15_nYPON (0x03 << 30)
894#define S3C2443_GPG15_CF_PWR (0x03 << 30) 594#define S3C2443_GPG15_CF_PWR (0x03 << 30)
@@ -907,62 +607,29 @@
907#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) 607#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
908#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) 608#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
909 609
910#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
911#define S3C2410_GPH0_INP (0x00 << 0)
912#define S3C2410_GPH0_OUTP (0x01 << 0)
913#define S3C2410_GPH0_nCTS0 (0x02 << 0) 610#define S3C2410_GPH0_nCTS0 (0x02 << 0)
914 611
915#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
916#define S3C2410_GPH1_INP (0x00 << 2)
917#define S3C2410_GPH1_OUTP (0x01 << 2)
918#define S3C2410_GPH1_nRTS0 (0x02 << 2) 612#define S3C2410_GPH1_nRTS0 (0x02 << 2)
919 613
920#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
921#define S3C2410_GPH2_INP (0x00 << 4)
922#define S3C2410_GPH2_OUTP (0x01 << 4)
923#define S3C2410_GPH2_TXD0 (0x02 << 4) 614#define S3C2410_GPH2_TXD0 (0x02 << 4)
924 615
925#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
926#define S3C2410_GPH3_INP (0x00 << 6)
927#define S3C2410_GPH3_OUTP (0x01 << 6)
928#define S3C2410_GPH3_RXD0 (0x02 << 6) 616#define S3C2410_GPH3_RXD0 (0x02 << 6)
929 617
930#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
931#define S3C2410_GPH4_INP (0x00 << 8)
932#define S3C2410_GPH4_OUTP (0x01 << 8)
933#define S3C2410_GPH4_TXD1 (0x02 << 8) 618#define S3C2410_GPH4_TXD1 (0x02 << 8)
934 619
935#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
936#define S3C2410_GPH5_INP (0x00 << 10)
937#define S3C2410_GPH5_OUTP (0x01 << 10)
938#define S3C2410_GPH5_RXD1 (0x02 << 10) 620#define S3C2410_GPH5_RXD1 (0x02 << 10)
939 621
940#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
941#define S3C2410_GPH6_INP (0x00 << 12)
942#define S3C2410_GPH6_OUTP (0x01 << 12)
943#define S3C2410_GPH6_TXD2 (0x02 << 12) 622#define S3C2410_GPH6_TXD2 (0x02 << 12)
944#define S3C2410_GPH6_nRTS1 (0x03 << 12) 623#define S3C2410_GPH6_nRTS1 (0x03 << 12)
945 624
946#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
947#define S3C2410_GPH7_INP (0x00 << 14)
948#define S3C2410_GPH7_OUTP (0x01 << 14)
949#define S3C2410_GPH7_RXD2 (0x02 << 14) 625#define S3C2410_GPH7_RXD2 (0x02 << 14)
950#define S3C2410_GPH7_nCTS1 (0x03 << 14) 626#define S3C2410_GPH7_nCTS1 (0x03 << 14)
951 627
952#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
953#define S3C2410_GPH8_INP (0x00 << 16)
954#define S3C2410_GPH8_OUTP (0x01 << 16)
955#define S3C2410_GPH8_UCLK (0x02 << 16) 628#define S3C2410_GPH8_UCLK (0x02 << 16)
956 629
957#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
958#define S3C2410_GPH9_INP (0x00 << 18)
959#define S3C2410_GPH9_OUTP (0x01 << 18)
960#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 630#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
961#define S3C2442_GPH9_nSPICS0 (0x03 << 18) 631#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
962 632
963#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
964#define S3C2410_GPH10_INP (0x00 << 20)
965#define S3C2410_GPH10_OUTP (0x01 << 20)
966#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 633#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
967 634
968/* The S3C2412 and S3C2413 move the GPJ register set to after 635/* The S3C2412 and S3C2413 move the GPJ register set to after
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 6d6995afeb43..06a84adfb13f 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -32,6 +32,7 @@
32#include <linux/list.h> 32#include <linux/list.h>
33#include <linux/timer.h> 33#include <linux/timer.h>
34#include <linux/init.h> 34#include <linux/init.h>
35#include <linux/gpio.h>
35#include <linux/device.h> 36#include <linux/device.h>
36#include <linux/platform_device.h> 37#include <linux/platform_device.h>
37#include <linux/proc_fs.h> 38#include <linux/proc_fs.h>
@@ -224,8 +225,8 @@ static void amlm5900_init_pm(void)
224 } else { 225 } else {
225 enable_irq_wake(IRQ_EINT9); 226 enable_irq_wake(IRQ_EINT9);
226 /* configure the suspend/resume status pin */ 227 /* configure the suspend/resume status pin */
227 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); 228 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
228 s3c2410_gpio_pullup(S3C2410_GPF2, 0); 229 s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
229 } 230 }
230} 231}
231static void __init amlm5900_init(void) 232static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 4389c160f7d0..31af898534cd 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -16,6 +16,7 @@
16#include <linux/list.h> 16#include <linux/list.h>
17#include <linux/timer.h> 17#include <linux/timer.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/gpio.h>
19#include <linux/sysdev.h> 20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
@@ -212,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
212static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) 213static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
213{ 214{
214 /* ensure that an nRESET is not generated on resume. */ 215 /* ensure that an nRESET is not generated on resume. */
215 s3c2410_gpio_setpin(S3C2410_GPA21, 1); 216 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
216 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); 217 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
217 218
218 return 0; 219 return 0;
219} 220}
220 221
221static int bast_pm_resume(struct sys_device *sd) 222static int bast_pm_resume(struct sys_device *sd)
222{ 223{
223 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); 224 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
224 return 0; 225 return 0;
225} 226}
226 227
@@ -593,8 +594,6 @@ static void __init bast_map_io(void)
593 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); 594 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
594 s3c24xx_init_clocks(0); 595 s3c24xx_init_clocks(0);
595 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); 596 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
596
597 usb_simtec_init();
598} 597}
599 598
600static void __init bast_init(void) 599static void __init bast_init(void)
@@ -608,6 +607,7 @@ static void __init bast_init(void)
608 i2c_register_board_info(0, bast_i2c_devs, 607 i2c_register_board_info(0, bast_i2c_devs,
609 ARRAY_SIZE(bast_i2c_devs)); 608 ARRAY_SIZE(bast_i2c_devs));
610 609
610 usb_simtec_init();
611 nor_simtec_init(); 611 nor_simtec_init();
612} 612}
613 613
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 7a7c4da4c256..d9cd5ddecf4a 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
127 127
128static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { 128static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
129 .udc_command = h1940_udc_pullup, 129 .udc_command = h1940_udc_pullup,
130 .vbus_pin = S3C2410_GPG5, 130 .vbus_pin = S3C2410_GPG(5),
131 .vbus_pin_inverted = 1, 131 .vbus_pin_inverted = 1,
132}; 132};
133 133
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 2b83f8707710..0f6ed61af415 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -19,6 +19,7 @@
19 19
20#include <linux/gpio_keys.h> 20#include <linux/gpio_keys.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/gpio.h>
22#include <linux/input.h> 23#include <linux/input.h>
23#include <linux/interrupt.h> 24#include <linux/interrupt.h>
24#include <linux/platform_device.h> 25#include <linux/platform_device.h>
@@ -85,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
85{ 86{
86 switch (cmd) { 87 switch (cmd) {
87 case S3C2410_UDC_P_ENABLE : 88 case S3C2410_UDC_P_ENABLE :
88 s3c2410_gpio_setpin(S3C2410_GPB3, 1); 89 s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
89 break; 90 break;
90 case S3C2410_UDC_P_DISABLE : 91 case S3C2410_UDC_P_DISABLE :
91 s3c2410_gpio_setpin(S3C2410_GPB3, 0); 92 s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
92 break; 93 break;
93 case S3C2410_UDC_P_RESET : 94 case S3C2410_UDC_P_RESET :
94 break; 95 break;
@@ -99,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
99 100
100static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = { 101static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
101 .udc_command = n30_udc_pullup, 102 .udc_command = n30_udc_pullup,
102 .vbus_pin = S3C2410_GPG1, 103 .vbus_pin = S3C2410_GPG(1),
103 .vbus_pin_inverted = 0, 104 .vbus_pin_inverted = 0,
104}; 105};
105 106
106static struct gpio_keys_button n30_buttons[] = { 107static struct gpio_keys_button n30_buttons[] = {
107 { 108 {
108 .gpio = S3C2410_GPF0, 109 .gpio = S3C2410_GPF(0),
109 .code = KEY_POWER, 110 .code = KEY_POWER,
110 .desc = "Power", 111 .desc = "Power",
111 .active_low = 0, 112 .active_low = 0,
112 }, 113 },
113 { 114 {
114 .gpio = S3C2410_GPG9, 115 .gpio = S3C2410_GPG(9),
115 .code = KEY_UP, 116 .code = KEY_UP,
116 .desc = "Thumbwheel Up", 117 .desc = "Thumbwheel Up",
117 .active_low = 0, 118 .active_low = 0,
118 }, 119 },
119 { 120 {
120 .gpio = S3C2410_GPG8, 121 .gpio = S3C2410_GPG(8),
121 .code = KEY_DOWN, 122 .code = KEY_DOWN,
122 .desc = "Thumbwheel Down", 123 .desc = "Thumbwheel Down",
123 .active_low = 0, 124 .active_low = 0,
124 }, 125 },
125 { 126 {
126 .gpio = S3C2410_GPG7, 127 .gpio = S3C2410_GPG(7),
127 .code = KEY_ENTER, 128 .code = KEY_ENTER,
128 .desc = "Thumbwheel Press", 129 .desc = "Thumbwheel Press",
129 .active_low = 0, 130 .active_low = 0,
130 }, 131 },
131 { 132 {
132 .gpio = S3C2410_GPF7, 133 .gpio = S3C2410_GPF(7),
133 .code = KEY_HOMEPAGE, 134 .code = KEY_HOMEPAGE,
134 .desc = "Home", 135 .desc = "Home",
135 .active_low = 0, 136 .active_low = 0,
136 }, 137 },
137 { 138 {
138 .gpio = S3C2410_GPF6, 139 .gpio = S3C2410_GPF(6),
139 .code = KEY_CALENDAR, 140 .code = KEY_CALENDAR,
140 .desc = "Calendar", 141 .desc = "Calendar",
141 .active_low = 0, 142 .active_low = 0,
142 }, 143 },
143 { 144 {
144 .gpio = S3C2410_GPF5, 145 .gpio = S3C2410_GPF(5),
145 .code = KEY_ADDRESSBOOK, 146 .code = KEY_ADDRESSBOOK,
146 .desc = "Contacts", 147 .desc = "Contacts",
147 .active_low = 0, 148 .active_low = 0,
148 }, 149 },
149 { 150 {
150 .gpio = S3C2410_GPF4, 151 .gpio = S3C2410_GPF(4),
151 .code = KEY_MAIL, 152 .code = KEY_MAIL,
152 .desc = "Mail", 153 .desc = "Mail",
153 .active_low = 0, 154 .active_low = 0,
@@ -169,73 +170,73 @@ static struct platform_device n30_button_device = {
169 170
170static struct gpio_keys_button n35_buttons[] = { 171static struct gpio_keys_button n35_buttons[] = {
171 { 172 {
172 .gpio = S3C2410_GPF0, 173 .gpio = S3C2410_GPF(0),
173 .code = KEY_POWER, 174 .code = KEY_POWER,
174 .desc = "Power", 175 .desc = "Power",
175 .active_low = 0, 176 .active_low = 0,
176 }, 177 },
177 { 178 {
178 .gpio = S3C2410_GPG9, 179 .gpio = S3C2410_GPG(9),
179 .code = KEY_UP, 180 .code = KEY_UP,
180 .desc = "Joystick Up", 181 .desc = "Joystick Up",
181 .active_low = 0, 182 .active_low = 0,
182 }, 183 },
183 { 184 {
184 .gpio = S3C2410_GPG8, 185 .gpio = S3C2410_GPG(8),
185 .code = KEY_DOWN, 186 .code = KEY_DOWN,
186 .desc = "Joystick Down", 187 .desc = "Joystick Down",
187 .active_low = 0, 188 .active_low = 0,
188 }, 189 },
189 { 190 {
190 .gpio = S3C2410_GPG6, 191 .gpio = S3C2410_GPG(6),
191 .code = KEY_DOWN, 192 .code = KEY_DOWN,
192 .desc = "Joystick Left", 193 .desc = "Joystick Left",
193 .active_low = 0, 194 .active_low = 0,
194 }, 195 },
195 { 196 {
196 .gpio = S3C2410_GPG5, 197 .gpio = S3C2410_GPG(5),
197 .code = KEY_DOWN, 198 .code = KEY_DOWN,
198 .desc = "Joystick Right", 199 .desc = "Joystick Right",
199 .active_low = 0, 200 .active_low = 0,
200 }, 201 },
201 { 202 {
202 .gpio = S3C2410_GPG7, 203 .gpio = S3C2410_GPG(7),
203 .code = KEY_ENTER, 204 .code = KEY_ENTER,
204 .desc = "Joystick Press", 205 .desc = "Joystick Press",
205 .active_low = 0, 206 .active_low = 0,
206 }, 207 },
207 { 208 {
208 .gpio = S3C2410_GPF7, 209 .gpio = S3C2410_GPF(7),
209 .code = KEY_HOMEPAGE, 210 .code = KEY_HOMEPAGE,
210 .desc = "Home", 211 .desc = "Home",
211 .active_low = 0, 212 .active_low = 0,
212 }, 213 },
213 { 214 {
214 .gpio = S3C2410_GPF6, 215 .gpio = S3C2410_GPF(6),
215 .code = KEY_CALENDAR, 216 .code = KEY_CALENDAR,
216 .desc = "Calendar", 217 .desc = "Calendar",
217 .active_low = 0, 218 .active_low = 0,
218 }, 219 },
219 { 220 {
220 .gpio = S3C2410_GPF5, 221 .gpio = S3C2410_GPF(5),
221 .code = KEY_ADDRESSBOOK, 222 .code = KEY_ADDRESSBOOK,
222 .desc = "Contacts", 223 .desc = "Contacts",
223 .active_low = 0, 224 .active_low = 0,
224 }, 225 },
225 { 226 {
226 .gpio = S3C2410_GPF4, 227 .gpio = S3C2410_GPF(4),
227 .code = KEY_MAIL, 228 .code = KEY_MAIL,
228 .desc = "Mail", 229 .desc = "Mail",
229 .active_low = 0, 230 .active_low = 0,
230 }, 231 },
231 { 232 {
232 .gpio = S3C2410_GPF3, 233 .gpio = S3C2410_GPF(3),
233 .code = SW_RADIO, 234 .code = SW_RADIO,
234 .desc = "GPS Antenna", 235 .desc = "GPS Antenna",
235 .active_low = 0, 236 .active_low = 0,
236 }, 237 },
237 { 238 {
238 .gpio = S3C2410_GPG2, 239 .gpio = S3C2410_GPG(2),
239 .code = SW_HEADPHONE_INSERT, 240 .code = SW_HEADPHONE_INSERT,
240 .desc = "Headphone", 241 .desc = "Headphone",
241 .active_low = 0, 242 .active_low = 0,
@@ -259,7 +260,7 @@ static struct platform_device n35_button_device = {
259/* This is the bluetooth LED on the device. */ 260/* This is the bluetooth LED on the device. */
260static struct s3c24xx_led_platdata n30_blue_led_pdata = { 261static struct s3c24xx_led_platdata n30_blue_led_pdata = {
261 .name = "blue_led", 262 .name = "blue_led",
262 .gpio = S3C2410_GPG6, 263 .gpio = S3C2410_GPG(6),
263 .def_trigger = "", 264 .def_trigger = "",
264}; 265};
265 266
@@ -270,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
270static struct s3c24xx_led_platdata n30_warning_led_pdata = { 271static struct s3c24xx_led_platdata n30_warning_led_pdata = {
271 .name = "warning_led", 272 .name = "warning_led",
272 .flags = S3C24XX_LEDF_ACTLOW, 273 .flags = S3C24XX_LEDF_ACTLOW,
273 .gpio = S3C2410_GPD9, 274 .gpio = S3C2410_GPD(9),
274 .def_trigger = "", 275 .def_trigger = "",
275}; 276};
276 277
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 9f1ba9b63f70..2cc9849eb448 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -27,6 +27,7 @@
27#include <linux/list.h> 27#include <linux/list.h>
28#include <linux/timer.h> 28#include <linux/timer.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/gpio.h>
30#include <linux/sysdev.h> 31#include <linux/sysdev.h>
31#include <linux/platform_device.h> 32#include <linux/platform_device.h>
32#include <linux/serial_core.h> 33#include <linux/serial_core.h>
@@ -198,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
198/* LED */ 199/* LED */
199 200
200static struct s3c24xx_led_platdata qt2410_pdata_led = { 201static struct s3c24xx_led_platdata qt2410_pdata_led = {
201 .gpio = S3C2410_GPB0, 202 .gpio = S3C2410_GPB(0),
202 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 203 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
203 .name = "led", 204 .name = "led",
204 .def_trigger = "timer", 205 .def_trigger = "timer",
@@ -218,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
218{ 219{
219 switch (cs) { 220 switch (cs) {
220 case BITBANG_CS_ACTIVE: 221 case BITBANG_CS_ACTIVE:
221 s3c2410_gpio_setpin(S3C2410_GPB5, 0); 222 s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
222 break; 223 break;
223 case BITBANG_CS_INACTIVE: 224 case BITBANG_CS_INACTIVE:
224 s3c2410_gpio_setpin(S3C2410_GPB5, 1); 225 s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
225 break; 226 break;
226 } 227 }
227} 228}
228 229
229static struct s3c2410_spigpio_info spi_gpio_cfg = { 230static struct s3c2410_spigpio_info spi_gpio_cfg = {
230 .pin_clk = S3C2410_GPG7, 231 .pin_clk = S3C2410_GPG(7),
231 .pin_mosi = S3C2410_GPG6, 232 .pin_mosi = S3C2410_GPG(6),
232 .pin_miso = S3C2410_GPG5, 233 .pin_miso = S3C2410_GPG(5),
233 .chip_select = &spi_gpio_cs, 234 .chip_select = &spi_gpio_cs,
234}; 235};
235 236
@@ -346,13 +347,13 @@ static void __init qt2410_machine_init(void)
346 } 347 }
347 s3c24xx_fb_set_platdata(&qt2410_fb_info); 348 s3c24xx_fb_set_platdata(&qt2410_fb_info);
348 349
349 s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); 350 s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
350 s3c2410_gpio_setpin(S3C2410_GPB0, 1); 351 s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
351 352
352 s3c24xx_udc_set_platdata(&qt2410_udc_cfg); 353 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
353 s3c_i2c0_set_platdata(NULL); 354 s3c_i2c0_set_platdata(NULL);
354 355
355 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); 356 s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
356 357
357 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); 358 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
358 s3c_pm_init(); 359 s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 61a1ea9c5c5c..1628cc773a2c 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/gpio.h>
21#include <linux/dm9000.h> 22#include <linux/dm9000.h>
22#include <linux/i2c.h> 23#include <linux/i2c.h>
23 24
@@ -277,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
277 278
278static struct s3c24xx_led_platdata vr1000_led1_pdata = { 279static struct s3c24xx_led_platdata vr1000_led1_pdata = {
279 .name = "led1", 280 .name = "led1",
280 .gpio = S3C2410_GPB0, 281 .gpio = S3C2410_GPB(0),
281 .def_trigger = "", 282 .def_trigger = "",
282}; 283};
283 284
284static struct s3c24xx_led_platdata vr1000_led2_pdata = { 285static struct s3c24xx_led_platdata vr1000_led2_pdata = {
285 .name = "led2", 286 .name = "led2",
286 .gpio = S3C2410_GPB1, 287 .gpio = S3C2410_GPB(1),
287 .def_trigger = "", 288 .def_trigger = "",
288}; 289};
289 290
290static struct s3c24xx_led_platdata vr1000_led3_pdata = { 291static struct s3c24xx_led_platdata vr1000_led3_pdata = {
291 .name = "led3", 292 .name = "led3",
292 .gpio = S3C2410_GPB2, 293 .gpio = S3C2410_GPB(2),
293 .def_trigger = "", 294 .def_trigger = "",
294}; 295};
295 296
@@ -355,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
355 356
356static void vr1000_power_off(void) 357static void vr1000_power_off(void)
357{ 358{
358 s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP); 359 s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
359 s3c2410_gpio_setpin(S3C2410_GPB9, 1); 360 s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
360} 361}
361 362
362static void __init vr1000_map_io(void) 363static void __init vr1000_map_io(void)
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 87fc481d92d4..143e08a599d4 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -25,6 +25,7 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/time.h> 26#include <linux/time.h>
27#include <linux/sysdev.h> 27#include <linux/sysdev.h>
28#include <linux/gpio.h>
28#include <linux/io.h> 29#include <linux/io.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -76,7 +77,7 @@ static void s3c2410_pm_prepare(void)
76 } 77 }
77 78
78 if ( machine_is_aml_m5900() ) 79 if ( machine_is_aml_m5900() )
79 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 80 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
80 81
81} 82}
82 83
@@ -91,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
91 __raw_writel(tmp, S3C2410_GSTATUS2); 92 __raw_writel(tmp, S3C2410_GSTATUS2);
92 93
93 if ( machine_is_aml_m5900() ) 94 if ( machine_is_aml_m5900() )
94 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 95 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
95 96
96 return 0; 97 return 0;
97} 98}
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 8331e8d97e20..6cd9377ddb82 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -18,9 +18,11 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/list.h> 20#include <linux/list.h>
21#include <linux/gpio.h>
21#include <linux/timer.h> 22#include <linux/timer.h>
22#include <linux/init.h> 23#include <linux/init.h>
23#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/gpio.h>
24#include <linux/io.h> 26#include <linux/io.h>
25 27
26#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
@@ -29,7 +31,6 @@
29 31
30#include <mach/bast-map.h> 32#include <mach/bast-map.h>
31#include <mach/bast-irq.h> 33#include <mach/bast-irq.h>
32#include <mach/regs-gpio.h>
33 34
34#include <mach/hardware.h> 35#include <mach/hardware.h>
35#include <asm/irq.h> 36#include <asm/irq.h>
@@ -53,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
53 power_state[port] = to; 54 power_state[port] = to;
54 55
55 if (power_state[0] && power_state[1]) 56 if (power_state[0] && power_state[1])
56 s3c2410_gpio_setpin(S3C2410_GPB4, 0); 57 gpio_set_value(S3C2410_GPB(4), 0);
57 else 58 else
58 s3c2410_gpio_setpin(S3C2410_GPB4, 1); 59 gpio_set_value(S3C2410_GPB(4), 1);
59} 60}
60 61
61static irqreturn_t 62static irqreturn_t
@@ -63,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
63{ 64{
64 struct s3c2410_hcd_info *info = pw; 65 struct s3c2410_hcd_info *info = pw;
65 66
66 if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) { 67 if (gpio_get_value(S3C2410_GPG(10)) == 0) {
67 pr_debug("usb_simtec: over-current irq (oc detected)\n"); 68 pr_debug("usb_simtec: over-current irq (oc detected)\n");
68 s3c2410_usb_report_oc(info, 3); 69 s3c2410_usb_report_oc(info, 3);
69 } else { 70 } else {
@@ -106,10 +107,27 @@ static struct s3c2410_hcd_info usb_simtec_info = {
106 107
107int usb_simtec_init(void) 108int usb_simtec_init(void)
108{ 109{
110 int ret;
111
109 printk("USB Power Control, (c) 2004 Simtec Electronics\n"); 112 printk("USB Power Control, (c) 2004 Simtec Electronics\n");
110 s3c_device_usb.dev.platform_data = &usb_simtec_info;
111 113
112 s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP); 114 ret = gpio_request(S3C2410_GPB(4), "USB power control");
113 s3c2410_gpio_setpin(S3C2410_GPB4, 1); 115 if (ret < 0) {
116 pr_err("%s: failed to get GPB4\n", __func__);
117 return ret;
118 }
119
120 ret = gpio_request(S3C2410_GPG(10), "USB overcurrent");
121 if (ret < 0) {
122 pr_err("%s: failed to get GPG10\n", __func__);
123 gpio_free(S3C2410_GPB(4));
124 return ret;
125 }
126
127 /* turn power on */
128 gpio_direction_output(S3C2410_GPB(4), 1);
129 gpio_direction_input(S3C2410_GPG(10));
130
131 s3c_device_usb.dev.platform_data = &usb_simtec_info;
114 return 0; 132 return 0;
115} 133}
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 8f0d37d43b43..8df506eac903 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -16,6 +16,7 @@
16#include <linux/list.h> 16#include <linux/list.h>
17#include <linux/timer.h> 17#include <linux/timer.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/gpio.h>
19#include <linux/sysdev.h> 20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
@@ -356,8 +357,8 @@ static void jive_lcm_reset(unsigned int set)
356{ 357{
357 printk(KERN_DEBUG "%s(%d)\n", __func__, set); 358 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
358 359
359 s3c2410_gpio_setpin(S3C2410_GPG13, set); 360 s3c2410_gpio_setpin(S3C2410_GPG(13), set);
360 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); 361 s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
361} 362}
362 363
363#undef LCD_UPPER_MARGIN 364#undef LCD_UPPER_MARGIN
@@ -390,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = {
390 391
391static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs) 392static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
392{ 393{
393 s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1); 394 s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
394} 395}
395 396
396static struct s3c2410_spigpio_info jive_lcd_spi = { 397static struct s3c2410_spigpio_info jive_lcd_spi = {
397 .bus_num = 1, 398 .bus_num = 1,
398 .pin_clk = S3C2410_GPG8, 399 .pin_clk = S3C2410_GPG(8),
399 .pin_mosi = S3C2410_GPB8, 400 .pin_mosi = S3C2410_GPB(8),
400 .num_chipselect = 1, 401 .num_chipselect = 1,
401 .chip_select = jive_lcd_spi_chipselect, 402 .chip_select = jive_lcd_spi_chipselect,
402}; 403};
@@ -412,13 +413,13 @@ static struct platform_device jive_device_lcdspi = {
412 413
413static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs) 414static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
414{ 415{
415 s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1); 416 s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
416} 417}
417 418
418static struct s3c2410_spigpio_info jive_wm8750_spi = { 419static struct s3c2410_spigpio_info jive_wm8750_spi = {
419 .bus_num = 2, 420 .bus_num = 2,
420 .pin_clk = S3C2410_GPB4, 421 .pin_clk = S3C2410_GPB(4),
421 .pin_mosi = S3C2410_GPB9, 422 .pin_mosi = S3C2410_GPB(9),
422 .num_chipselect = 1, 423 .num_chipselect = 1,
423 .chip_select = jive_wm8750_chipselect, 424 .chip_select = jive_wm8750_chipselect,
424}; 425};
@@ -479,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = {
479}; 480};
480 481
481static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { 482static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
482 .vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */ 483 .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
483}; 484};
484 485
485/* Jive power management device */ 486/* Jive power management device */
@@ -529,8 +530,8 @@ static void jive_power_off(void)
529{ 530{
530 printk(KERN_INFO "powering system down...\n"); 531 printk(KERN_INFO "powering system down...\n");
531 532
532 s3c2410_gpio_setpin(S3C2410_GPC5, 1); 533 s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
533 s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT); 534 s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
534} 535}
535 536
536static void __init jive_machine_init(void) 537static void __init jive_machine_init(void)
@@ -634,22 +635,22 @@ static void __init jive_machine_init(void)
634 635
635 /* initialise the spi */ 636 /* initialise the spi */
636 637
637 s3c2410_gpio_setpin(S3C2410_GPG13, 0); 638 s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
638 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); 639 s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
639 640
640 s3c2410_gpio_setpin(S3C2410_GPB7, 1); 641 s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
641 s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT); 642 s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
642 643
643 s3c2410_gpio_setpin(S3C2410_GPB6, 0); 644 s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
644 s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT); 645 s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
645 646
646 s3c2410_gpio_setpin(S3C2410_GPG8, 1); 647 s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
647 s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT); 648 s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
648 649
649 /* initialise the WM8750 spi */ 650 /* initialise the WM8750 spi */
650 651
651 s3c2410_gpio_setpin(S3C2410_GPH10, 1); 652 s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
652 s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT); 653 s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
653 654
654 /* Turn off suspend on both USB ports, and switch the 655 /* Turn off suspend on both USB ports, and switch the
655 * selectable USB port to USB device mode. */ 656 * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index eba66aa6bd20..9a5e43419722 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -17,6 +17,7 @@
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/timer.h> 18#include <linux/timer.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/gpio.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
22#include <linux/io.h> 23#include <linux/io.h>
@@ -84,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
84 switch (cmd) 85 switch (cmd)
85 { 86 {
86 case S3C2410_UDC_P_ENABLE : 87 case S3C2410_UDC_P_ENABLE :
87 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 88 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
88 break; 89 break;
89 case S3C2410_UDC_P_DISABLE : 90 case S3C2410_UDC_P_DISABLE :
90 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 91 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
91 break; 92 break;
92 case S3C2410_UDC_P_RESET : 93 case S3C2410_UDC_P_RESET :
93 break; 94 break;
@@ -134,8 +135,8 @@ static void __init smdk2413_machine_init(void)
134{ /* Turn off suspend on both USB ports, and switch the 135{ /* Turn off suspend on both USB ports, and switch the
135 * selectable USB port to USB device mode. */ 136 * selectable USB port to USB device mode. */
136 137
137 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 138 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
138 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT); 139 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
139 140
140 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | 141 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
141 S3C2410_MISCCR_USBSUSPND0 | 142 S3C2410_MISCCR_USBSUSPND0 |
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 9c6abf9fb540..68f3870991bf 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -15,6 +15,7 @@
15#include <linux/list.h> 15#include <linux/list.h>
16#include <linux/timer.h> 16#include <linux/timer.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/gpio.h>
18#include <linux/serial_core.h> 19#include <linux/serial_core.h>
19#include <linux/platform_device.h> 20#include <linux/platform_device.h>
20#include <linux/ata_platform.h> 21#include <linux/ata_platform.h>
@@ -468,7 +469,7 @@ static void __init anubis_map_io(void)
468 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large); 469 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
469 } else { 470 } else {
470 /* ensure that the GPIO is setup */ 471 /* ensure that the GPIO is setup */
471 s3c2410_gpio_setpin(S3C2410_GPA0, 1); 472 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
472 } 473 }
473} 474}
474 475
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 315c42e31278..dfc7010935da 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = {
166}; 166};
167 167
168static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { 168static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
169 .gpio_detect = S3C2410_GPG10, 169 .gpio_detect = S3C2410_GPG(10),
170}; 170};
171 171
172/* 7" LCD panel */ 172/* 7" LCD panel */
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 7aeaa972d7f5..d43edede590e 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/gpio.h>
21#include <linux/string.h> 22#include <linux/string.h>
22#include <linux/serial_core.h> 23#include <linux/serial_core.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
@@ -120,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = {
120static void __init nexcoder_sensorboard_init(void) 121static void __init nexcoder_sensorboard_init(void)
121{ 122{
122 // Initialize SCCB bus 123 // Initialize SCCB bus
123 s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL 124 s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
124 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP); 125 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
125 s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA 126 s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
126 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP); 127 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
127 128
128 // Power up the sensor board 129 // Power up the sensor board
129 s3c2410_gpio_setpin(S3C2410_GPF1, 1); 130 s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
130 s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN 131 s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
131 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 132 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
132 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN 133 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
133} 134}
134 135
135static void __init nexcoder_map_io(void) 136static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index c8a46685ce38..cba064b49a64 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -15,6 +15,7 @@
15#include <linux/list.h> 15#include <linux/list.h>
16#include <linux/timer.h> 16#include <linux/timer.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/gpio.h>
18#include <linux/device.h> 19#include <linux/device.h>
19#include <linux/sysdev.h> 20#include <linux/sysdev.h>
20#include <linux/serial_core.h> 21#include <linux/serial_core.h>
@@ -291,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
291 __raw_writeb(tmp, OSIRIS_VA_CTRL0); 292 __raw_writeb(tmp, OSIRIS_VA_CTRL0);
292 293
293 /* ensure that an nRESET is not generated on resume. */ 294 /* ensure that an nRESET is not generated on resume. */
294 s3c2410_gpio_setpin(S3C2410_GPA21, 1); 295 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
295 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); 296 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
296 297
297 return 0; 298 return 0;
298} 299}
@@ -304,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd)
304 305
305 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); 306 __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
306 307
307 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); 308 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
308 309
309 return 0; 310 return 0;
310} 311}
@@ -384,7 +385,7 @@ static void __init osiris_map_io(void)
384 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large); 385 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
385 } else { 386 } else {
386 /* write-protect line to the NAND */ 387 /* write-protect line to the NAND */
387 s3c2410_gpio_setpin(S3C2410_GPA0, 1); 388 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
388 } 389 }
389 390
390 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ 391 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 1a8347cec20a..aa119863c5ce 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/gpio.h>
21#include <linux/sysdev.h> 22#include <linux/sysdev.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23 24
@@ -47,27 +48,27 @@
47/* LED devices */ 48/* LED devices */
48 49
49static struct s3c24xx_led_platdata smdk_pdata_led4 = { 50static struct s3c24xx_led_platdata smdk_pdata_led4 = {
50 .gpio = S3C2410_GPF4, 51 .gpio = S3C2410_GPF(4),
51 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 52 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
52 .name = "led4", 53 .name = "led4",
53 .def_trigger = "timer", 54 .def_trigger = "timer",
54}; 55};
55 56
56static struct s3c24xx_led_platdata smdk_pdata_led5 = { 57static struct s3c24xx_led_platdata smdk_pdata_led5 = {
57 .gpio = S3C2410_GPF5, 58 .gpio = S3C2410_GPF(5),
58 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 59 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
59 .name = "led5", 60 .name = "led5",
60 .def_trigger = "nand-disk", 61 .def_trigger = "nand-disk",
61}; 62};
62 63
63static struct s3c24xx_led_platdata smdk_pdata_led6 = { 64static struct s3c24xx_led_platdata smdk_pdata_led6 = {
64 .gpio = S3C2410_GPF6, 65 .gpio = S3C2410_GPF(6),
65 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 66 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
66 .name = "led6", 67 .name = "led6",
67}; 68};
68 69
69static struct s3c24xx_led_platdata smdk_pdata_led7 = { 70static struct s3c24xx_led_platdata smdk_pdata_led7 = {
70 .gpio = S3C2410_GPF7, 71 .gpio = S3C2410_GPF(7),
71 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 72 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
72 .name = "led7", 73 .name = "led7",
73}; 74};
@@ -184,15 +185,15 @@ void __init smdk_machine_init(void)
184{ 185{
185 /* Configure the LEDs (even if we have no LED support)*/ 186 /* Configure the LEDs (even if we have no LED support)*/
186 187
187 s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP); 188 s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
188 s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP); 189 s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
189 s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); 190 s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
190 s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); 191 s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
191 192
192 s3c2410_gpio_setpin(S3C2410_GPF4, 1); 193 s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
193 s3c2410_gpio_setpin(S3C2410_GPF5, 1); 194 s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
194 s3c2410_gpio_setpin(S3C2410_GPF6, 1); 195 s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
195 s3c2410_gpio_setpin(S3C2410_GPF7, 1); 196 s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
196 197
197 if (machine_is_smdk2443()) 198 if (machine_is_smdk2443())
198 smdk_nand_info.twrph0 = 50; 199 smdk_nand_info.twrph0 = 50;
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 4a899c279eb5..95df059b5a1d 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -183,35 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
183 183
184int s3c2410_gpio_getirq(unsigned int pin) 184int s3c2410_gpio_getirq(unsigned int pin)
185{ 185{
186 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15) 186 if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
187 return -1; /* not valid interrupts */ 187 return -EINVAL; /* not valid interrupts */
188 188
189 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7) 189 if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
190 return -1; /* not valid pin */ 190 return -EINVAL; /* not valid pin */
191 191
192 if (pin < S3C2410_GPF4) 192 if (pin < S3C2410_GPF(4))
193 return (pin - S3C2410_GPF0) + IRQ_EINT0; 193 return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
194 194
195 if (pin < S3C2410_GPG0) 195 if (pin < S3C2410_GPG(0))
196 return (pin - S3C2410_GPF4) + IRQ_EINT4; 196 return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
197 197
198 return (pin - S3C2410_GPG0) + IRQ_EINT8; 198 return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
199} 199}
200 200
201EXPORT_SYMBOL(s3c2410_gpio_getirq); 201EXPORT_SYMBOL(s3c2410_gpio_getirq);
202
203int s3c2410_gpio_irq2pin(unsigned int irq)
204{
205 if (irq >= IRQ_EINT0 && irq <= IRQ_EINT3)
206 return S3C2410_GPF0 + (irq - IRQ_EINT0);
207
208 if (irq >= IRQ_EINT4 && irq <= IRQ_EINT7)
209 return S3C2410_GPF4 + (irq - IRQ_EINT4);
210
211 if (irq >= IRQ_EINT8 && irq <= IRQ_EINT23)
212 return S3C2410_GPG0 + (irq - IRQ_EINT8);
213
214 return -EINVAL;
215}
216
217EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 4bac12dc0733..6d7a961d3269 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/sysdev.h>
18#include <linux/ioport.h> 19#include <linux/ioport.h>
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/gpio.h> 21#include <linux/gpio.h>
@@ -78,10 +79,10 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
78 79
79struct s3c_gpio_chip s3c24xx_gpios[] = { 80struct s3c_gpio_chip s3c24xx_gpios[] = {
80 [0] = { 81 [0] = {
81 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), 82 .base = S3C2410_GPACON,
82 .pm = __gpio_pm(&s3c_gpio_pm_1bit), 83 .pm = __gpio_pm(&s3c_gpio_pm_1bit),
83 .chip = { 84 .chip = {
84 .base = S3C2410_GPA0, 85 .base = S3C2410_GPA(0),
85 .owner = THIS_MODULE, 86 .owner = THIS_MODULE,
86 .label = "GPIOA", 87 .label = "GPIOA",
87 .ngpio = 24, 88 .ngpio = 24,
@@ -90,50 +91,50 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
90 }, 91 },
91 }, 92 },
92 [1] = { 93 [1] = {
93 .base = S3C24XX_GPIO_BASE(S3C2410_GPB0), 94 .base = S3C2410_GPBCON,
94 .pm = __gpio_pm(&s3c_gpio_pm_2bit), 95 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
95 .chip = { 96 .chip = {
96 .base = S3C2410_GPB0, 97 .base = S3C2410_GPB(0),
97 .owner = THIS_MODULE, 98 .owner = THIS_MODULE,
98 .label = "GPIOB", 99 .label = "GPIOB",
99 .ngpio = 16, 100 .ngpio = 16,
100 }, 101 },
101 }, 102 },
102 [2] = { 103 [2] = {
103 .base = S3C24XX_GPIO_BASE(S3C2410_GPC0), 104 .base = S3C2410_GPCCON,
104 .pm = __gpio_pm(&s3c_gpio_pm_2bit), 105 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
105 .chip = { 106 .chip = {
106 .base = S3C2410_GPC0, 107 .base = S3C2410_GPC(0),
107 .owner = THIS_MODULE, 108 .owner = THIS_MODULE,
108 .label = "GPIOC", 109 .label = "GPIOC",
109 .ngpio = 16, 110 .ngpio = 16,
110 }, 111 },
111 }, 112 },
112 [3] = { 113 [3] = {
113 .base = S3C24XX_GPIO_BASE(S3C2410_GPD0), 114 .base = S3C2410_GPDCON,
114 .pm = __gpio_pm(&s3c_gpio_pm_2bit), 115 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
115 .chip = { 116 .chip = {
116 .base = S3C2410_GPD0, 117 .base = S3C2410_GPD(0),
117 .owner = THIS_MODULE, 118 .owner = THIS_MODULE,
118 .label = "GPIOD", 119 .label = "GPIOD",
119 .ngpio = 16, 120 .ngpio = 16,
120 }, 121 },
121 }, 122 },
122 [4] = { 123 [4] = {
123 .base = S3C24XX_GPIO_BASE(S3C2410_GPE0), 124 .base = S3C2410_GPECON,
124 .pm = __gpio_pm(&s3c_gpio_pm_2bit), 125 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
125 .chip = { 126 .chip = {
126 .base = S3C2410_GPE0, 127 .base = S3C2410_GPE(0),
127 .label = "GPIOE", 128 .label = "GPIOE",
128 .owner = THIS_MODULE, 129 .owner = THIS_MODULE,
129 .ngpio = 16, 130 .ngpio = 16,
130 }, 131 },
131 }, 132 },
132 [5] = { 133 [5] = {
133 .base = S3C24XX_GPIO_BASE(S3C2410_GPF0), 134 .base = S3C2410_GPFCON,
134 .pm = __gpio_pm(&s3c_gpio_pm_2bit), 135 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
135 .chip = { 136 .chip = {
136 .base = S3C2410_GPF0, 137 .base = S3C2410_GPF(0),
137 .owner = THIS_MODULE, 138 .owner = THIS_MODULE,
138 .label = "GPIOF", 139 .label = "GPIOF",
139 .ngpio = 8, 140 .ngpio = 8,
@@ -141,15 +142,24 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
141 }, 142 },
142 }, 143 },
143 [6] = { 144 [6] = {
144 .base = S3C24XX_GPIO_BASE(S3C2410_GPG0), 145 .base = S3C2410_GPGCON,
145 .pm = __gpio_pm(&s3c_gpio_pm_2bit), 146 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
146 .chip = { 147 .chip = {
147 .base = S3C2410_GPG0, 148 .base = S3C2410_GPG(0),
148 .owner = THIS_MODULE, 149 .owner = THIS_MODULE,
149 .label = "GPIOG", 150 .label = "GPIOG",
150 .ngpio = 10, 151 .ngpio = 16,
151 .to_irq = s3c24xx_gpiolib_bankg_toirq, 152 .to_irq = s3c24xx_gpiolib_bankg_toirq,
152 }, 153 },
154 }, {
155 .base = S3C2410_GPHCON,
156 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
157 .chip = {
158 .base = S3C2410_GPH(0),
159 .owner = THIS_MODULE,
160 .label = "GPIOH",
161 .ngpio = 11,
162 },
153 }, 163 },
154}; 164};
155 165
@@ -164,4 +174,4 @@ static __init int s3c24xx_gpiolib_init(void)
164 return 0; 174 return 0;
165} 175}
166 176
167arch_initcall(s3c24xx_gpiolib_init); 177core_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 5135c40a1b90..56e5253ca02c 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -30,6 +30,7 @@
30#include <linux/suspend.h> 30#include <linux/suspend.h>
31#include <linux/errno.h> 31#include <linux/errno.h>
32#include <linux/time.h> 32#include <linux/time.h>
33#include <linux/gpio.h>
33#include <linux/interrupt.h> 34#include <linux/interrupt.h>
34#include <linux/serial_core.h> 35#include <linux/serial_core.h>
35#include <linux/io.h> 36#include <linux/io.h>
@@ -123,12 +124,12 @@ void s3c_pm_configure_extint(void)
123 * and then configure it as an input if it is not 124 * and then configure it as an input if it is not
124 */ 125 */
125 126
126 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { 127 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
127 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0); 128 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
128 } 129 }
129 130
130 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { 131 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
131 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); 132 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
132 } 133 }
133} 134}
134 135
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index d62b7e7fb355..71a6accf114e 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -11,6 +11,7 @@
11*/ 11*/
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/gpio.h>
14 15
15struct platform_device; 16struct platform_device;
16 17
@@ -20,6 +21,6 @@ struct platform_device;
20 21
21void s3c_i2c0_cfg_gpio(struct platform_device *dev) 22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
22{ 23{
23 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); 24 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
24 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); 25 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
25} 26}
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index 8b403cbb53d2..9edf7894eedd 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
22 int enable) 22 int enable)
23{ 23{
24 if (enable) { 24 if (enable) {
25 s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0); 25 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
26 s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0); 26 s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
27 s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0); 27 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
28 s3c2410_gpio_pullup(S3C2410_GPE11, 0); 28 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
29 s3c2410_gpio_pullup(S3C2410_GPE13, 0); 29 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
30 } else { 30 } else {
31 s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT); 31 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT); 32 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_pullup(S3C2410_GPE11, 1); 33 s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
34 s3c2410_gpio_pullup(S3C2410_GPE12, 1); 34 s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
35 s3c2410_gpio_pullup(S3C2410_GPE13, 1); 35 s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
36 } 36 }
37} 37}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 8fccd4e549f0..f34d0fc69ad8 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
22 int enable) 22 int enable)
23{ 23{
24 if (enable) { 24 if (enable) {
25 s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1); 25 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
26 s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1); 26 s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
27 s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1); 27 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
28 s3c2410_gpio_pullup(S3C2410_GPG5, 0); 28 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
29 s3c2410_gpio_pullup(S3C2410_GPG6, 0); 29 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
30 } else { 30 } else {
31 s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT); 31 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT); 32 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_pullup(S3C2410_GPG5, 1); 33 s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
34 s3c2410_gpio_pullup(S3C2410_GPG6, 1); 34 s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
35 s3c2410_gpio_pullup(S3C2410_GPG7, 1); 35 s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
36 } 36 }
37} 37}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 07:31:11 -0500