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-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/boot/dts/versatile-pb.dts37
-rw-r--r--arch/arm/include/asm/mach/pci.h6
-rw-r--r--arch/arm/include/asm/pci.h7
-rw-r--r--arch/arm/kernel/bios32.c3
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c92
-rw-r--r--arch/arm/mach-integrator/pci_v3.c62
-rw-r--r--arch/arm/mach-ks8695/pci.c77
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c94
-rw-r--r--arch/arm64/kernel/pci.c22
-rw-r--r--arch/frv/mb93090-mb00/pci-vdk.c4
-rw-r--r--arch/mips/pci/pci-bcm1480.c4
-rw-r--r--arch/mips/pci/pci-octeon.c4
-rw-r--r--arch/mips/pci/pcie-octeon.c12
-rw-r--r--arch/mn10300/unit-asb2305/pci.c4
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_pciex.c4
-rw-r--r--arch/powerpc/platforms/powermac/pci.c209
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c46
-rw-r--r--arch/tile/kernel/pci.c4
-rw-r--r--arch/x86/pci/xen.c4
20 files changed, 150 insertions, 548 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 97d07ed60a0b..dcb2e0c55be4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1279,6 +1279,9 @@ config PCI_DOMAINS
1279 bool 1279 bool
1280 depends on PCI 1280 depends on PCI
1281 1281
1282config PCI_DOMAINS_GENERIC
1283 def_bool PCI_DOMAINS
1284
1282config PCI_NANOENGINE 1285config PCI_NANOENGINE
1283 bool "BSE nanoEngine PCI support" 1286 bool "BSE nanoEngine PCI support"
1284 depends on SA1100_NANOENGINE 1287 depends on SA1100_NANOENGINE
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index e36c1e82fea7..b83137f66034 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -29,6 +29,43 @@
29 clock-names = "apb_pclk"; 29 clock-names = "apb_pclk";
30 }; 30 };
31 31
32 pci-controller@10001000 {
33 compatible = "arm,versatile-pci";
34 device_type = "pci";
35 reg = <0x10001000 0x1000
36 0x41000000 0x10000
37 0x42000000 0x100000>;
38 bus-range = <0 0xff>;
39 #address-cells = <3>;
40 #size-cells = <2>;
41 #interrupt-cells = <1>;
42
43 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
44 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
45 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
46
47 interrupt-map-mask = <0x1800 0 0 7>;
48 interrupt-map = <0x1800 0 0 1 &sic 28
49 0x1800 0 0 2 &sic 29
50 0x1800 0 0 3 &sic 30
51 0x1800 0 0 4 &sic 27
52
53 0x1000 0 0 1 &sic 27
54 0x1000 0 0 2 &sic 28
55 0x1000 0 0 3 &sic 29
56 0x1000 0 0 4 &sic 30
57
58 0x0800 0 0 1 &sic 30
59 0x0800 0 0 2 &sic 27
60 0x0800 0 0 3 &sic 28
61 0x0800 0 0 4 &sic 29
62
63 0x0000 0 0 1 &sic 29
64 0x0000 0 0 2 &sic 30
65 0x0000 0 0 3 &sic 27
66 0x0000 0 0 4 &sic 28>;
67 };
68
32 fpga { 69 fpga {
33 uart@9000 { 70 uart@9000 {
34 compatible = "arm,pl011", "arm,primecell"; 71 compatible = "arm,pl011", "arm,primecell";
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 8292b5f81e23..28b9bb35949e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -19,9 +19,6 @@ struct pci_bus;
19struct device; 19struct device;
20 20
21struct hw_pci { 21struct hw_pci {
22#ifdef CONFIG_PCI_DOMAINS
23 int domain;
24#endif
25#ifdef CONFIG_PCI_MSI 22#ifdef CONFIG_PCI_MSI
26 struct msi_controller *msi_ctrl; 23 struct msi_controller *msi_ctrl;
27#endif 24#endif
@@ -45,9 +42,6 @@ struct hw_pci {
45 * Per-controller structure 42 * Per-controller structure
46 */ 43 */
47struct pci_sys_data { 44struct pci_sys_data {
48#ifdef CONFIG_PCI_DOMAINS
49 int domain;
50#endif
51#ifdef CONFIG_PCI_MSI 45#ifdef CONFIG_PCI_MSI
52 struct msi_controller *msi_ctrl; 46 struct msi_controller *msi_ctrl;
53#endif 47#endif
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 7e95d8535e24..585dc33a7a24 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -18,13 +18,6 @@ static inline int pcibios_assign_all_busses(void)
18} 18}
19 19
20#ifdef CONFIG_PCI_DOMAINS 20#ifdef CONFIG_PCI_DOMAINS
21static inline int pci_domain_nr(struct pci_bus *bus)
22{
23 struct pci_sys_data *root = bus->sysdata;
24
25 return root->domain;
26}
27
28static inline int pci_proc_domain(struct pci_bus *bus) 21static inline int pci_proc_domain(struct pci_bus *bus)
29{ 22{
30 return pci_domain_nr(bus); 23 return pci_domain_nr(bus);
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index a4effd6d8f2f..ddd75c58b1e8 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -463,9 +463,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
463 if (!sys) 463 if (!sys)
464 panic("PCI: unable to allocate sys data!"); 464 panic("PCI: unable to allocate sys data!");
465 465
466#ifdef CONFIG_PCI_DOMAINS
467 sys->domain = hw->domain;
468#endif
469#ifdef CONFIG_PCI_MSI 466#ifdef CONFIG_PCI_MSI
470 sys->msi_ctrl = hw->msi_ctrl; 467 sys->msi_ctrl = hw->msi_ctrl;
471#endif 468#endif
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 45d6bd09e6ef..c622c306c390 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -30,18 +30,15 @@ struct cns3xxx_pcie {
30 unsigned int irqs[2]; 30 unsigned int irqs[2];
31 struct resource res_io; 31 struct resource res_io;
32 struct resource res_mem; 32 struct resource res_mem;
33 struct hw_pci hw_pci; 33 int port;
34
35 bool linked; 34 bool linked;
36}; 35};
37 36
38static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
39
40static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata) 37static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
41{ 38{
42 struct pci_sys_data *root = sysdata; 39 struct pci_sys_data *root = sysdata;
43 40
44 return &cns3xxx_pcie[root->domain]; 41 return root->private_data;
45} 42}
46 43
47static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev) 44static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
@@ -54,8 +51,8 @@ static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
54 return sysdata_to_cnspci(bus->sysdata); 51 return sysdata_to_cnspci(bus->sysdata);
55} 52}
56 53
57static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus, 54static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
58 unsigned int devfn, int where) 55 unsigned int devfn, int where)
59{ 56{
60 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); 57 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
61 int busno = bus->number; 58 int busno = bus->number;
@@ -91,55 +88,22 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
91static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 88static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
92 int where, int size, u32 *val) 89 int where, int size, u32 *val)
93{ 90{
94 u32 v; 91 int ret;
95 void __iomem *base;
96 u32 mask = (0x1ull << (size * 8)) - 1; 92 u32 mask = (0x1ull << (size * 8)) - 1;
97 int shift = (where % 4) * 8; 93 int shift = (where % 4) * 8;
98 94
99 base = cns3xxx_pci_cfg_base(bus, devfn, where); 95 ret = pci_generic_config_read32(bus, devfn, where, size, val);
100 if (!base) {
101 *val = 0xffffffff;
102 return PCIBIOS_SUCCESSFUL;
103 }
104
105 v = __raw_readl(base);
106 96
107 if (bus->number == 0 && devfn == 0 && 97 if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
108 (where & 0xffc) == PCI_CLASS_REVISION) { 98 (where & 0xffc) == PCI_CLASS_REVISION)
109 /* 99 /*
110 * RC's class is 0xb, but Linux PCI driver needs 0x604 100 * RC's class is 0xb, but Linux PCI driver needs 0x604
111 * for a PCIe bridge. So we must fixup the class code 101 * for a PCIe bridge. So we must fixup the class code
112 * to 0x604 here. 102 * to 0x604 here.
113 */ 103 */
114 v &= 0xff; 104 *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;
115 v |= 0x604 << 16;
116 }
117 105
118 *val = (v >> shift) & mask; 106 return ret;
119
120 return PCIBIOS_SUCCESSFUL;
121}
122
123static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
124 int where, int size, u32 val)
125{
126 u32 v;
127 void __iomem *base;
128 u32 mask = (0x1ull << (size * 8)) - 1;
129 int shift = (where % 4) * 8;
130
131 base = cns3xxx_pci_cfg_base(bus, devfn, where);
132 if (!base)
133 return PCIBIOS_SUCCESSFUL;
134
135 v = __raw_readl(base);
136
137 v &= ~(mask << shift);
138 v |= (val & mask) << shift;
139
140 __raw_writel(v, base);
141
142 return PCIBIOS_SUCCESSFUL;
143} 107}
144 108
145static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys) 109static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
@@ -158,8 +122,9 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
158} 122}
159 123
160static struct pci_ops cns3xxx_pcie_ops = { 124static struct pci_ops cns3xxx_pcie_ops = {
125 .map_bus = cns3xxx_pci_map_bus,
161 .read = cns3xxx_pci_read_config, 126 .read = cns3xxx_pci_read_config,
162 .write = cns3xxx_pci_write_config, 127 .write = pci_generic_config_write,
163}; 128};
164 129
165static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 130static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@@ -192,13 +157,7 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
192 .flags = IORESOURCE_MEM, 157 .flags = IORESOURCE_MEM,
193 }, 158 },
194 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, 159 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
195 .hw_pci = { 160 .port = 0,
196 .domain = 0,
197 .nr_controllers = 1,
198 .ops = &cns3xxx_pcie_ops,
199 .setup = cns3xxx_pci_setup,
200 .map_irq = cns3xxx_pcie_map_irq,
201 },
202 }, 161 },
203 [1] = { 162 [1] = {
204 .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT, 163 .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
@@ -217,19 +176,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
217 .flags = IORESOURCE_MEM, 176 .flags = IORESOURCE_MEM,
218 }, 177 },
219 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, 178 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
220 .hw_pci = { 179 .port = 1,
221 .domain = 1,
222 .nr_controllers = 1,
223 .ops = &cns3xxx_pcie_ops,
224 .setup = cns3xxx_pci_setup,
225 .map_irq = cns3xxx_pcie_map_irq,
226 },
227 }, 180 },
228}; 181};
229 182
230static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci) 183static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
231{ 184{
232 int port = cnspci->hw_pci.domain; 185 int port = cnspci->port;
233 u32 reg; 186 u32 reg;
234 unsigned long time; 187 unsigned long time;
235 188
@@ -260,9 +213,9 @@ static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
260 213
261static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) 214static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
262{ 215{
263 int port = cnspci->hw_pci.domain; 216 int port = cnspci->port;
264 struct pci_sys_data sd = { 217 struct pci_sys_data sd = {
265 .domain = port, 218 .private_data = cnspci,
266 }; 219 };
267 struct pci_bus bus = { 220 struct pci_bus bus = {
268 .number = 0, 221 .number = 0,
@@ -323,6 +276,14 @@ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
323void __init cns3xxx_pcie_init_late(void) 276void __init cns3xxx_pcie_init_late(void)
324{ 277{
325 int i; 278 int i;
279 void *private_data;
280 struct hw_pci hw_pci = {
281 .nr_controllers = 1,
282 .ops = &cns3xxx_pcie_ops,
283 .setup = cns3xxx_pci_setup,
284 .map_irq = cns3xxx_pcie_map_irq,
285 .private_data = &private_data,
286 };
326 287
327 pcibios_min_io = 0; 288 pcibios_min_io = 0;
328 pcibios_min_mem = 0; 289 pcibios_min_mem = 0;
@@ -335,7 +296,8 @@ void __init cns3xxx_pcie_init_late(void)
335 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); 296 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
336 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); 297 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
337 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); 298 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
338 pci_common_init(&cns3xxx_pcie[i].hw_pci); 299 private_data = &cns3xxx_pcie[i];
300 pci_common_init(&hw_pci);
339 } 301 }
340 302
341 pci_assign_unassigned_resources(); 303 pci_assign_unassigned_resources();
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index c186a17c2cff..2565f0e7b5cf 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -356,7 +356,6 @@ static u64 pre_mem_pci_sz;
356 * 7:2 register number 356 * 7:2 register number
357 * 357 *
358 */ 358 */
359static DEFINE_RAW_SPINLOCK(v3_lock);
360 359
361#undef V3_LB_BASE_PREFETCH 360#undef V3_LB_BASE_PREFETCH
362#define V3_LB_BASE_PREFETCH 0 361#define V3_LB_BASE_PREFETCH 0
@@ -457,67 +456,21 @@ static void v3_close_config_window(void)
457static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, 456static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
458 int size, u32 *val) 457 int size, u32 *val)
459{ 458{
460 void __iomem *addr; 459 int ret = pci_generic_config_read(bus, devfn, where, size, val);
461 unsigned long flags;
462 u32 v;
463
464 raw_spin_lock_irqsave(&v3_lock, flags);
465 addr = v3_open_config_window(bus, devfn, where);
466
467 switch (size) {
468 case 1:
469 v = __raw_readb(addr);
470 break;
471
472 case 2:
473 v = __raw_readw(addr);
474 break;
475
476 default:
477 v = __raw_readl(addr);
478 break;
479 }
480
481 v3_close_config_window(); 460 v3_close_config_window();
482 raw_spin_unlock_irqrestore(&v3_lock, flags); 461 return ret;
483
484 *val = v;
485 return PCIBIOS_SUCCESSFUL;
486} 462}
487 463
488static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, 464static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
489 int size, u32 val) 465 int size, u32 val)
490{ 466{
491 void __iomem *addr; 467 int ret = pci_generic_config_write(bus, devfn, where, size, val);
492 unsigned long flags;
493
494 raw_spin_lock_irqsave(&v3_lock, flags);
495 addr = v3_open_config_window(bus, devfn, where);
496
497 switch (size) {
498 case 1:
499 __raw_writeb((u8)val, addr);
500 __raw_readb(addr);
501 break;
502
503 case 2:
504 __raw_writew((u16)val, addr);
505 __raw_readw(addr);
506 break;
507
508 case 4:
509 __raw_writel(val, addr);
510 __raw_readl(addr);
511 break;
512 }
513
514 v3_close_config_window(); 468 v3_close_config_window();
515 raw_spin_unlock_irqrestore(&v3_lock, flags); 469 return ret;
516
517 return PCIBIOS_SUCCESSFUL;
518} 470}
519 471
520static struct pci_ops pci_v3_ops = { 472static struct pci_ops pci_v3_ops = {
473 .map_bus = v3_open_config_window,
521 .read = v3_read_config, 474 .read = v3_read_config,
522 .write = v3_write_config, 475 .write = v3_write_config,
523}; 476};
@@ -658,7 +611,6 @@ static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
658 */ 611 */
659static void __init pci_v3_preinit(void) 612static void __init pci_v3_preinit(void)
660{ 613{
661 unsigned long flags;
662 unsigned int temp; 614 unsigned int temp;
663 phys_addr_t io_address = pci_pio_to_address(io_mem.start); 615 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
664 616
@@ -672,8 +624,6 @@ static void __init pci_v3_preinit(void)
672 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); 624 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
673 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); 625 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
674 626
675 raw_spin_lock_irqsave(&v3_lock, flags);
676
677 /* 627 /*
678 * Unlock V3 registers, but only if they were previously locked. 628 * Unlock V3 registers, but only if they were previously locked.
679 */ 629 */
@@ -736,8 +686,6 @@ static void __init pci_v3_preinit(void)
736 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10)); 686 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
737 v3_writeb(V3_LB_IMASK, 0x28); 687 v3_writeb(V3_LB_IMASK, 0x28);
738 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); 688 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
739
740 raw_spin_unlock_irqrestore(&v3_lock, flags);
741} 689}
742 690
743static void __init pci_v3_postinit(void) 691static void __init pci_v3_postinit(void)
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index bb18193b4bac..c1bc4c3716ed 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -38,8 +38,6 @@
38 38
39 39
40static int pci_dbg; 40static int pci_dbg;
41static int pci_cfg_dbg;
42
43 41
44static void ks8695_pci_setupconfig(unsigned int bus_nr, unsigned int devfn, unsigned int where) 42static void ks8695_pci_setupconfig(unsigned int bus_nr, unsigned int devfn, unsigned int where)
45{ 43{
@@ -59,75 +57,11 @@ static void ks8695_pci_setupconfig(unsigned int bus_nr, unsigned int devfn, unsi
59 } 57 }
60} 58}
61 59
62 60static void __iomem *ks8695_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
63/* 61 int where)
64 * The KS8695 datasheet prohibits anything other than 32bit accesses
65 * to the IO registers, so all our configuration must be done with
66 * 32bit operations, and the correct bit masking and shifting.
67 */
68
69static int ks8695_pci_readconfig(struct pci_bus *bus,
70 unsigned int devfn, int where, int size, u32 *value)
71{
72 ks8695_pci_setupconfig(bus->number, devfn, where);
73
74 *value = __raw_readl(KS8695_PCI_VA + KS8695_PBCD);
75
76 switch (size) {
77 case 4:
78 break;
79 case 2:
80 *value = *value >> ((where & 2) * 8);
81 *value &= 0xffff;
82 break;
83 case 1:
84 *value = *value >> ((where & 3) * 8);
85 *value &= 0xff;
86 break;
87 }
88
89 if (pci_cfg_dbg) {
90 printk("read: %d,%08x,%02x,%d: %08x (%08x)\n",
91 bus->number, devfn, where, size, *value,
92 __raw_readl(KS8695_PCI_VA + KS8695_PBCD));
93 }
94
95 return PCIBIOS_SUCCESSFUL;
96}
97
98static int ks8695_pci_writeconfig(struct pci_bus *bus,
99 unsigned int devfn, int where, int size, u32 value)
100{ 62{
101 unsigned long tmp;
102
103 if (pci_cfg_dbg) {
104 printk("write: %d,%08x,%02x,%d: %08x\n",
105 bus->number, devfn, where, size, value);
106 }
107
108 ks8695_pci_setupconfig(bus->number, devfn, where); 63 ks8695_pci_setupconfig(bus->number, devfn, where);
109 64 return KS8695_PCI_VA + KS8695_PBCD;
110 switch (size) {
111 case 4:
112 __raw_writel(value, KS8695_PCI_VA + KS8695_PBCD);
113 break;
114 case 2:
115 tmp = __raw_readl(KS8695_PCI_VA + KS8695_PBCD);
116 tmp &= ~(0xffff << ((where & 2) * 8));
117 tmp |= value << ((where & 2) * 8);
118
119 __raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD);
120 break;
121 case 1:
122 tmp = __raw_readl(KS8695_PCI_VA + KS8695_PBCD);
123 tmp &= ~(0xff << ((where & 3) * 8));
124 tmp |= value << ((where & 3) * 8);
125
126 __raw_writel(tmp, KS8695_PCI_VA + KS8695_PBCD);
127 break;
128 }
129
130 return PCIBIOS_SUCCESSFUL;
131} 65}
132 66
133static void ks8695_local_writeconfig(int where, u32 value) 67static void ks8695_local_writeconfig(int where, u32 value)
@@ -137,8 +71,9 @@ static void ks8695_local_writeconfig(int where, u32 value)
137} 71}
138 72
139static struct pci_ops ks8695_pci_ops = { 73static struct pci_ops ks8695_pci_ops = {
140 .read = ks8695_pci_readconfig, 74 .map_bus = ks8695_pci_map_bus,
141 .write = ks8695_pci_writeconfig, 75 .read = pci_generic_config_read32,
76 .write = pci_generic_config_write32,
142}; 77};
143 78
144static struct resource pci_mem = { 79static struct resource pci_mem = {
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index b704433c529c..d7ae8d50f6d8 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -22,7 +22,6 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/pci.h> 24#include <linux/pci.h>
25#include <linux/spinlock.h>
26 25
27#include <asm/mach/pci.h> 26#include <asm/mach/pci.h>
28#include <asm/mach-types.h> 27#include <asm/mach-types.h>
@@ -30,97 +29,20 @@
30#include <mach/nanoengine.h> 29#include <mach/nanoengine.h>
31#include <mach/hardware.h> 30#include <mach/hardware.h>
32 31
33static DEFINE_SPINLOCK(nano_lock); 32static void __iomem *nanoengine_pci_map_bus(struct pci_bus *bus,
34 33 unsigned int devfn, int where)
35static int nanoengine_get_pci_address(struct pci_bus *bus,
36 unsigned int devfn, int where, void __iomem **address)
37{ 34{
38 int ret = PCIBIOS_DEVICE_NOT_FOUND; 35 if (bus->number != 0 || (devfn >> 3) != 0)
39 unsigned int busnr = bus->number; 36 return NULL;
40 37
41 *address = (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT + 38 return (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT +
42 ((bus->number << 16) | (devfn << 8) | (where & ~3)); 39 ((bus->number << 16) | (devfn << 8) | (where & ~3));
43
44 ret = (busnr > 255 || devfn > 255 || where > 255) ?
45 PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
46
47 return ret;
48}
49
50static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where,
51 int size, u32 *val)
52{
53 int ret;
54 void __iomem *address;
55 unsigned long flags;
56 u32 v;
57
58 /* nanoEngine PCI bridge does not return -1 for a non-existing
59 * device. We must fake the answer. We know that the only valid
60 * device is device zero at bus 0, which is the network chip. */
61 if (bus->number != 0 || (devfn >> 3) != 0) {
62 v = -1;
63 nanoengine_get_pci_address(bus, devfn, where, &address);
64 goto exit_function;
65 }
66
67 spin_lock_irqsave(&nano_lock, flags);
68
69 ret = nanoengine_get_pci_address(bus, devfn, where, &address);
70 if (ret != PCIBIOS_SUCCESSFUL)
71 return ret;
72 v = __raw_readl(address);
73
74 spin_unlock_irqrestore(&nano_lock, flags);
75
76 v >>= ((where & 3) * 8);
77 v &= (unsigned long)(-1) >> ((4 - size) * 8);
78
79exit_function:
80 *val = v;
81 return PCIBIOS_SUCCESSFUL;
82}
83
84static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where,
85 int size, u32 val)
86{
87 int ret;
88 void __iomem *address;
89 unsigned long flags;
90 unsigned shift;
91 u32 v;
92
93 shift = (where & 3) * 8;
94
95 spin_lock_irqsave(&nano_lock, flags);
96
97 ret = nanoengine_get_pci_address(bus, devfn, where, &address);
98 if (ret != PCIBIOS_SUCCESSFUL)
99 return ret;
100 v = __raw_readl(address);
101 switch (size) {
102 case 1:
103 v &= ~(0xFF << shift);
104 v |= val << shift;
105 break;
106 case 2:
107 v &= ~(0xFFFF << shift);
108 v |= val << shift;
109 break;
110 case 4:
111 v = val;
112 break;
113 }
114 __raw_writel(v, address);
115
116 spin_unlock_irqrestore(&nano_lock, flags);
117
118 return PCIBIOS_SUCCESSFUL;
119} 40}
120 41
121static struct pci_ops pci_nano_ops = { 42static struct pci_ops pci_nano_ops = {
122 .read = nanoengine_read_config, 43 .map_bus = nanoengine_pci_map_bus,
123 .write = nanoengine_write_config, 44 .read = pci_generic_config_read32,
45 .write = pci_generic_config_write32,
124}; 46};
125 47
126static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot, 48static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
index ce5836c14ec1..6f93c24ca801 100644
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@@ -46,25 +46,3 @@ int pcibios_add_device(struct pci_dev *dev)
46 46
47 return 0; 47 return 0;
48} 48}
49
50
51#ifdef CONFIG_PCI_DOMAINS_GENERIC
52static bool dt_domain_found = false;
53
54void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
55{
56 int domain = of_get_pci_domain_nr(parent->of_node);
57
58 if (domain >= 0) {
59 dt_domain_found = true;
60 } else if (dt_domain_found == true) {
61 dev_err(parent, "Node %s is missing \"linux,pci-domain\" property in DT\n",
62 parent->of_node->full_name);
63 return;
64 } else {
65 domain = pci_get_new_domain_nr();
66 }
67
68 bus->domain_nr = domain;
69}
70#endif
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
index efa5d65b0007..b073f4d771a5 100644
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ b/arch/frv/mb93090-mb00/pci-vdk.c
@@ -168,8 +168,8 @@ static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int whe
168} 168}
169 169
170static struct pci_ops pci_direct_frv = { 170static struct pci_ops pci_direct_frv = {
171 pci_frv_read_config, 171 .read = pci_frv_read_config,
172 pci_frv_write_config, 172 .write = pci_frv_write_config,
173}; 173};
174 174
175/* 175/*
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 5ec2a7bae02c..f2355e3e65a1 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -173,8 +173,8 @@ static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
173} 173}
174 174
175struct pci_ops bcm1480_pci_ops = { 175struct pci_ops bcm1480_pci_ops = {
176 bcm1480_pcibios_read, 176 .read = bcm1480_pcibios_read,
177 bcm1480_pcibios_write, 177 .write = bcm1480_pcibios_write,
178}; 178};
179 179
180static struct resource bcm1480_mem_resource = { 180static struct resource bcm1480_mem_resource = {
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index d07e04121cc6..bedb72bd3a27 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -327,8 +327,8 @@ static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
327 327
328 328
329static struct pci_ops octeon_pci_ops = { 329static struct pci_ops octeon_pci_ops = {
330 octeon_read_config, 330 .read = octeon_read_config,
331 octeon_write_config, 331 .write = octeon_write_config,
332}; 332};
333 333
334static struct resource octeon_pci_mem_resource = { 334static struct resource octeon_pci_mem_resource = {
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 5e36c33e5543..eb4a17ba4a53 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -1792,8 +1792,8 @@ static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
1792} 1792}
1793 1793
1794static struct pci_ops octeon_pcie0_ops = { 1794static struct pci_ops octeon_pcie0_ops = {
1795 octeon_pcie0_read_config, 1795 .read = octeon_pcie0_read_config,
1796 octeon_pcie0_write_config, 1796 .write = octeon_pcie0_write_config,
1797}; 1797};
1798 1798
1799static struct resource octeon_pcie0_mem_resource = { 1799static struct resource octeon_pcie0_mem_resource = {
@@ -1813,8 +1813,8 @@ static struct pci_controller octeon_pcie0_controller = {
1813}; 1813};
1814 1814
1815static struct pci_ops octeon_pcie1_ops = { 1815static struct pci_ops octeon_pcie1_ops = {
1816 octeon_pcie1_read_config, 1816 .read = octeon_pcie1_read_config,
1817 octeon_pcie1_write_config, 1817 .write = octeon_pcie1_write_config,
1818}; 1818};
1819 1819
1820static struct resource octeon_pcie1_mem_resource = { 1820static struct resource octeon_pcie1_mem_resource = {
@@ -1834,8 +1834,8 @@ static struct pci_controller octeon_pcie1_controller = {
1834}; 1834};
1835 1835
1836static struct pci_ops octeon_dummy_ops = { 1836static struct pci_ops octeon_dummy_ops = {
1837 octeon_dummy_read_config, 1837 .read = octeon_dummy_read_config,
1838 octeon_dummy_write_config, 1838 .write = octeon_dummy_write_config,
1839}; 1839};
1840 1840
1841static struct resource octeon_dummy_mem_resource = { 1841static struct resource octeon_dummy_mem_resource = {
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
index 471ff398090c..613ca1e55b4b 100644
--- a/arch/mn10300/unit-asb2305/pci.c
+++ b/arch/mn10300/unit-asb2305/pci.c
@@ -228,8 +228,8 @@ static int pci_ampci_write_config(struct pci_bus *bus, unsigned int devfn,
228} 228}
229 229
230static struct pci_ops pci_direct_ampci = { 230static struct pci_ops pci_direct_ampci = {
231 pci_ampci_read_config, 231 .read = pci_ampci_read_config,
232 pci_ampci_write_config, 232 .write = pci_ampci_write_config,
233}; 233};
234 234
235/* 235/*
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
index f22387598040..94170e4f2ce7 100644
--- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
+++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
@@ -399,8 +399,8 @@ static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
399} 399}
400 400
401static struct pci_ops scc_pciex_pci_ops = { 401static struct pci_ops scc_pciex_pci_ops = {
402 scc_pciex_read_config, 402 .read = scc_pciex_read_config,
403 scc_pciex_write_config, 403 .write = scc_pciex_write_config,
404}; 404};
405 405
406static void pciex_clear_intr_all(unsigned int __iomem *base) 406static void pciex_clear_intr_all(unsigned int __iomem *base)
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 04702db35d45..f4071a67ad00 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -133,17 +133,23 @@ static void __init fixup_bus_range(struct device_node *bridge)
133 |(((unsigned int)(off)) & 0xFCUL) \ 133 |(((unsigned int)(off)) & 0xFCUL) \
134 |1UL) 134 |1UL)
135 135
136static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 136static void __iomem *macrisc_cfg_map_bus(struct pci_bus *bus,
137 u8 bus, u8 dev_fn, u8 offset) 137 unsigned int dev_fn,
138 int offset)
138{ 139{
139 unsigned int caddr; 140 unsigned int caddr;
141 struct pci_controller *hose;
140 142
141 if (bus == hose->first_busno) { 143 hose = pci_bus_to_host(bus);
144 if (hose == NULL)
145 return NULL;
146
147 if (bus->number == hose->first_busno) {
142 if (dev_fn < (11 << 3)) 148 if (dev_fn < (11 << 3))
143 return NULL; 149 return NULL;
144 caddr = MACRISC_CFA0(dev_fn, offset); 150 caddr = MACRISC_CFA0(dev_fn, offset);
145 } else 151 } else
146 caddr = MACRISC_CFA1(bus, dev_fn, offset); 152 caddr = MACRISC_CFA1(bus->number, dev_fn, offset);
147 153
148 /* Uninorth will return garbage if we don't read back the value ! */ 154 /* Uninorth will return garbage if we don't read back the value ! */
149 do { 155 do {
@@ -154,129 +160,46 @@ static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
154 return hose->cfg_data + offset; 160 return hose->cfg_data + offset;
155} 161}
156 162
157static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
158 int offset, int len, u32 *val)
159{
160 struct pci_controller *hose;
161 volatile void __iomem *addr;
162
163 hose = pci_bus_to_host(bus);
164 if (hose == NULL)
165 return PCIBIOS_DEVICE_NOT_FOUND;
166 if (offset >= 0x100)
167 return PCIBIOS_BAD_REGISTER_NUMBER;
168 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
169 if (!addr)
170 return PCIBIOS_DEVICE_NOT_FOUND;
171 /*
172 * Note: the caller has already checked that offset is
173 * suitably aligned and that len is 1, 2 or 4.
174 */
175 switch (len) {
176 case 1:
177 *val = in_8(addr);
178 break;
179 case 2:
180 *val = in_le16(addr);
181 break;
182 default:
183 *val = in_le32(addr);
184 break;
185 }
186 return PCIBIOS_SUCCESSFUL;
187}
188
189static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
190 int offset, int len, u32 val)
191{
192 struct pci_controller *hose;
193 volatile void __iomem *addr;
194
195 hose = pci_bus_to_host(bus);
196 if (hose == NULL)
197 return PCIBIOS_DEVICE_NOT_FOUND;
198 if (offset >= 0x100)
199 return PCIBIOS_BAD_REGISTER_NUMBER;
200 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
201 if (!addr)
202 return PCIBIOS_DEVICE_NOT_FOUND;
203 /*
204 * Note: the caller has already checked that offset is
205 * suitably aligned and that len is 1, 2 or 4.
206 */
207 switch (len) {
208 case 1:
209 out_8(addr, val);
210 break;
211 case 2:
212 out_le16(addr, val);
213 break;
214 default:
215 out_le32(addr, val);
216 break;
217 }
218 return PCIBIOS_SUCCESSFUL;
219}
220
221static struct pci_ops macrisc_pci_ops = 163static struct pci_ops macrisc_pci_ops =
222{ 164{
223 .read = macrisc_read_config, 165 .map_bus = macrisc_cfg_map_bus,
224 .write = macrisc_write_config, 166 .read = pci_generic_config_read,
167 .write = pci_generic_config_write,
225}; 168};
226 169
227#ifdef CONFIG_PPC32 170#ifdef CONFIG_PPC32
228/* 171/*
229 * Verify that a specific (bus, dev_fn) exists on chaos 172 * Verify that a specific (bus, dev_fn) exists on chaos
230 */ 173 */
231static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 174static void __iomem *chaos_map_bus(struct pci_bus *bus, unsigned int devfn,
175 int offset)
232{ 176{
233 struct device_node *np; 177 struct device_node *np;
234 const u32 *vendor, *device; 178 const u32 *vendor, *device;
235 179
236 if (offset >= 0x100) 180 if (offset >= 0x100)
237 return PCIBIOS_BAD_REGISTER_NUMBER; 181 return NULL;
238 np = of_pci_find_child_device(bus->dev.of_node, devfn); 182 np = of_pci_find_child_device(bus->dev.of_node, devfn);
239 if (np == NULL) 183 if (np == NULL)
240 return PCIBIOS_DEVICE_NOT_FOUND; 184 return NULL;
241 185
242 vendor = of_get_property(np, "vendor-id", NULL); 186 vendor = of_get_property(np, "vendor-id", NULL);
243 device = of_get_property(np, "device-id", NULL); 187 device = of_get_property(np, "device-id", NULL);
244 if (vendor == NULL || device == NULL) 188 if (vendor == NULL || device == NULL)
245 return PCIBIOS_DEVICE_NOT_FOUND; 189 return NULL;
246 190
247 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 191 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
248 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 192 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
249 return PCIBIOS_BAD_REGISTER_NUMBER; 193 return NULL;
250
251 return PCIBIOS_SUCCESSFUL;
252}
253 194
254static int 195 return macrisc_cfg_map_bus(bus, devfn, offset);
255chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
256 int len, u32 *val)
257{
258 int result = chaos_validate_dev(bus, devfn, offset);
259 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
260 *val = ~0U;
261 if (result != PCIBIOS_SUCCESSFUL)
262 return result;
263 return macrisc_read_config(bus, devfn, offset, len, val);
264}
265
266static int
267chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
268 int len, u32 val)
269{
270 int result = chaos_validate_dev(bus, devfn, offset);
271 if (result != PCIBIOS_SUCCESSFUL)
272 return result;
273 return macrisc_write_config(bus, devfn, offset, len, val);
274} 196}
275 197
276static struct pci_ops chaos_pci_ops = 198static struct pci_ops chaos_pci_ops =
277{ 199{
278 .read = chaos_read_config, 200 .map_bus = chaos_map_bus,
279 .write = chaos_write_config, 201 .read = pci_generic_config_read,
202 .write = pci_generic_config_write,
280}; 203};
281 204
282static void __init setup_chaos(struct pci_controller *hose, 205static void __init setup_chaos(struct pci_controller *hose,
@@ -471,15 +394,24 @@ static struct pci_ops u3_ht_pci_ops =
471 |(((unsigned int)(off)) & 0xfcU) \ 394 |(((unsigned int)(off)) & 0xfcU) \
472 |1UL) 395 |1UL)
473 396
474static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 397static void __iomem *u4_pcie_cfg_map_bus(struct pci_bus *bus,
475 u8 bus, u8 dev_fn, int offset) 398 unsigned int dev_fn,
399 int offset)
476{ 400{
401 struct pci_controller *hose;
477 unsigned int caddr; 402 unsigned int caddr;
478 403
479 if (bus == hose->first_busno) { 404 if (offset >= 0x1000)
405 return NULL;
406
407 hose = pci_bus_to_host(bus);
408 if (!hose)
409 return NULL;
410
411 if (bus->number == hose->first_busno) {
480 caddr = U4_PCIE_CFA0(dev_fn, offset); 412 caddr = U4_PCIE_CFA0(dev_fn, offset);
481 } else 413 } else
482 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 414 caddr = U4_PCIE_CFA1(bus->number, dev_fn, offset);
483 415
484 /* Uninorth will return garbage if we don't read back the value ! */ 416 /* Uninorth will return garbage if we don't read back the value ! */
485 do { 417 do {
@@ -490,74 +422,11 @@ static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
490 return hose->cfg_data + offset; 422 return hose->cfg_data + offset;
491} 423}
492 424
493static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
494 int offset, int len, u32 *val)
495{
496 struct pci_controller *hose;
497 volatile void __iomem *addr;
498
499 hose = pci_bus_to_host(bus);
500 if (hose == NULL)
501 return PCIBIOS_DEVICE_NOT_FOUND;
502 if (offset >= 0x1000)
503 return PCIBIOS_BAD_REGISTER_NUMBER;
504 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
505 if (!addr)
506 return PCIBIOS_DEVICE_NOT_FOUND;
507 /*
508 * Note: the caller has already checked that offset is
509 * suitably aligned and that len is 1, 2 or 4.
510 */
511 switch (len) {
512 case 1:
513 *val = in_8(addr);
514 break;
515 case 2:
516 *val = in_le16(addr);
517 break;
518 default:
519 *val = in_le32(addr);
520 break;
521 }
522 return PCIBIOS_SUCCESSFUL;
523}
524
525static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
526 int offset, int len, u32 val)
527{
528 struct pci_controller *hose;
529 volatile void __iomem *addr;
530
531 hose = pci_bus_to_host(bus);
532 if (hose == NULL)
533 return PCIBIOS_DEVICE_NOT_FOUND;
534 if (offset >= 0x1000)
535 return PCIBIOS_BAD_REGISTER_NUMBER;
536 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
537 if (!addr)
538 return PCIBIOS_DEVICE_NOT_FOUND;
539 /*
540 * Note: the caller has already checked that offset is
541 * suitably aligned and that len is 1, 2 or 4.
542 */
543 switch (len) {
544 case 1:
545 out_8(addr, val);
546 break;
547 case 2:
548 out_le16(addr, val);
549 break;
550 default:
551 out_le32(addr, val);
552 break;
553 }
554 return PCIBIOS_SUCCESSFUL;
555}
556
557static struct pci_ops u4_pcie_pci_ops = 425static struct pci_ops u4_pcie_pci_ops =
558{ 426{
559 .read = u4_pcie_read_config, 427 .map_bus = u4_pcie_cfg_map_bus,
560 .write = u4_pcie_write_config, 428 .read = pci_generic_config_read,
429 .write = pci_generic_config_write,
561}; 430};
562 431
563static void pmac_pci_fixup_u4_of_node(struct pci_dev *dev) 432static void pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6455c1eada1a..271b67e7670c 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -645,61 +645,21 @@ mapped:
645 return pcie->cfg_type1 + offset; 645 return pcie->cfg_type1 + offset;
646} 646}
647 647
648static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
649 int offset, int len, u32 *val)
650{
651 void __iomem *cfg_addr;
652
653 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
654 if (!cfg_addr)
655 return PCIBIOS_DEVICE_NOT_FOUND;
656
657 switch (len) {
658 case 1:
659 *val = in_8(cfg_addr);
660 break;
661 case 2:
662 *val = in_le16(cfg_addr);
663 break;
664 default:
665 *val = in_le32(cfg_addr);
666 break;
667 }
668
669 return PCIBIOS_SUCCESSFUL;
670}
671
672static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 648static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
673 int offset, int len, u32 val) 649 int offset, int len, u32 val)
674{ 650{
675 struct pci_controller *hose = pci_bus_to_host(bus); 651 struct pci_controller *hose = pci_bus_to_host(bus);
676 void __iomem *cfg_addr;
677
678 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
679 if (!cfg_addr)
680 return PCIBIOS_DEVICE_NOT_FOUND;
681 652
682 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 653 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
683 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 654 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
684 val &= 0xffffff00; 655 val &= 0xffffff00;
685 656
686 switch (len) { 657 return pci_generic_config_write(bus, devfn, offset, len, val);
687 case 1:
688 out_8(cfg_addr, val);
689 break;
690 case 2:
691 out_le16(cfg_addr, val);
692 break;
693 default:
694 out_le32(cfg_addr, val);
695 break;
696 }
697
698 return PCIBIOS_SUCCESSFUL;
699} 658}
700 659
701static struct pci_ops mpc83xx_pcie_ops = { 660static struct pci_ops mpc83xx_pcie_ops = {
702 .read = mpc83xx_pcie_read_config, 661 .map_bus = mpc83xx_pcie_remap_cfg,
662 .read = pci_generic_config_read,
703 .write = mpc83xx_pcie_write_config, 663 .write = mpc83xx_pcie_write_config,
704}; 664};
705 665
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index f70c7892fa25..325df47f114d 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -245,7 +245,7 @@ static void fixup_read_and_payload_sizes(void)
245{ 245{
246 struct pci_dev *dev = NULL; 246 struct pci_dev *dev = NULL;
247 int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */ 247 int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
248 int max_read_size = 0x2; /* Limit to 512 byte reads. */ 248 int max_read_size = PCI_EXP_DEVCTL_READRQ_512B;
249 u16 new_values; 249 u16 new_values;
250 250
251 /* Scan for the smallest maximum payload size. */ 251 /* Scan for the smallest maximum payload size. */
@@ -258,7 +258,7 @@ static void fixup_read_and_payload_sizes(void)
258 } 258 }
259 259
260 /* Now, set the max_payload_size for all devices to that value. */ 260 /* Now, set the max_payload_size for all devices to that value. */
261 new_values = (max_read_size << 12) | (smallest_max_payload << 5); 261 new_values = max_read_size | (smallest_max_payload << 5);
262 for_each_pci_dev(dev) 262 for_each_pci_dev(dev)
263 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 263 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
264 PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ, 264 PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index 9098d880c476..d22f4b5bbc04 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -298,12 +298,16 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
298 map_irq.entry_nr = nvec; 298 map_irq.entry_nr = nvec;
299 } else if (type == PCI_CAP_ID_MSIX) { 299 } else if (type == PCI_CAP_ID_MSIX) {
300 int pos; 300 int pos;
301 unsigned long flags;
301 u32 table_offset, bir; 302 u32 table_offset, bir;
302 303
303 pos = dev->msix_cap; 304 pos = dev->msix_cap;
304 pci_read_config_dword(dev, pos + PCI_MSIX_TABLE, 305 pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
305 &table_offset); 306 &table_offset);
306 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); 307 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
308 flags = pci_resource_flags(dev, bir);
309 if (!flags || (flags & IORESOURCE_UNSET))
310 return -EINVAL;
307 311
308 map_irq.table_base = pci_resource_start(dev, bir); 312 map_irq.table_base = pci_resource_start(dev, bir);
309 map_irq.entry_nr = msidesc->msi_attrib.entry_nr; 313 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 22:40:10 -0500