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-rw-r--r--arch/arm/boot/dts/imx51.dtsi2
-rw-r--r--arch/arm/configs/vt8500_v6_v7_defconfig90
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/at91sam9260.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263.c3
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c3
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c6
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c3
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c6
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12.h5
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5.h5
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3.h5
-rw-r--r--arch/arm/mach-at91/sama5d3.c6
-rw-r--r--arch/arm/mach-at91/sysirq_mask.c71
-rw-r--r--arch/arm/mach-highbank/Kconfig2
-rw-r--r--arch/arm/mach-imx/Makefile4
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c7
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c51
-rw-r--r--arch/arm/mach-imx/common.h5
-rw-r--r--arch/arm/mach-imx/src.c15
-rw-r--r--arch/arm/mach-imx/system.c12
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c3
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c2
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c58
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.c2
-rw-r--r--arch/arm/mach-omap2/omap_device.c13
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h3
-rw-r--r--arch/arm/mach-sti/Kconfig2
-rw-r--r--arch/arm/mach-tegra/tegra.c2
33 files changed, 331 insertions, 68 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index f4dcff3a9969..4bcdd3ad15e5 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -190,7 +190,7 @@
190 190
191 usbphy0: usbphy@0 { 191 usbphy0: usbphy@0 {
192 compatible = "usb-nop-xceiv"; 192 compatible = "usb-nop-xceiv";
193 clocks = <&clks 124>; 193 clocks = <&clks 75>;
194 clock-names = "main_clk"; 194 clock-names = "main_clk";
195 status = "okay"; 195 status = "okay";
196 }; 196 };
diff --git a/arch/arm/configs/vt8500_v6_v7_defconfig b/arch/arm/configs/vt8500_v6_v7_defconfig
new file mode 100644
index 000000000000..f0520176acd0
--- /dev/null
+++ b/arch/arm/configs/vt8500_v6_v7_defconfig
@@ -0,0 +1,90 @@
1CONFIG_IRQ_DOMAIN_DEBUG=y
2CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_ARCH_MULTI_V6=y
6CONFIG_ARCH_WM8750=y
7CONFIG_ARCH_WM8850=y
8CONFIG_ARM_ERRATA_720789=y
9CONFIG_ARM_ERRATA_754322=y
10CONFIG_ARM_ERRATA_775420=y
11CONFIG_HAVE_ARM_ARCH_TIMER=y
12CONFIG_AEABI=y
13CONFIG_HIGHMEM=y
14CONFIG_HIGHPTE=y
15CONFIG_ARM_APPENDED_DTB=y
16CONFIG_ARM_ATAG_DTB_COMPAT=y
17CONFIG_VFP=y
18CONFIG_NEON=y
19CONFIG_PM_RUNTIME=y
20CONFIG_NET=y
21CONFIG_UNIX=y
22CONFIG_INET=y
23CONFIG_IP_PNP=y
24CONFIG_IP_PNP_DHCP=y
25CONFIG_DEVTMPFS=y
26CONFIG_DEVTMPFS_MOUNT=y
27CONFIG_PROC_DEVICETREE=y
28CONFIG_EEPROM_93CX6=y
29CONFIG_SCSI=y
30CONFIG_BLK_DEV_SD=y
31CONFIG_NETDEVICES=y
32# CONFIG_NET_CADENCE is not set
33# CONFIG_NET_VENDOR_BROADCOM is not set
34# CONFIG_NET_VENDOR_CIRRUS is not set
35# CONFIG_NET_VENDOR_FARADAY is not set
36# CONFIG_NET_VENDOR_INTEL is not set
37# CONFIG_NET_VENDOR_MARVELL is not set
38# CONFIG_NET_VENDOR_MICREL is not set
39# CONFIG_NET_VENDOR_NATSEMI is not set
40# CONFIG_NET_VENDOR_SEEQ is not set
41# CONFIG_NET_VENDOR_SMSC is not set
42# CONFIG_NET_VENDOR_STMICRO is not set
43CONFIG_VIA_VELOCITY=y
44# CONFIG_NET_VENDOR_WIZNET is not set
45CONFIG_PHYLIB=y
46CONFIG_INPUT_MATRIXKMAP=y
47CONFIG_SERIAL_VT8500=y
48CONFIG_SERIAL_VT8500_CONSOLE=y
49CONFIG_I2C=y
50CONFIG_I2C_WMT=y
51CONFIG_PINCTRL_SINGLE=y
52CONFIG_PINCTRL_WM8750=y
53CONFIG_GPIO_GENERIC_PLATFORM=y
54CONFIG_POWER_SUPPLY=y
55CONFIG_POWER_RESET=y
56CONFIG_MFD_SYSCON=y
57CONFIG_REGULATOR=y
58CONFIG_REGULATOR_FIXED_VOLTAGE=y
59CONFIG_REGULATOR_GPIO=y
60CONFIG_USB=y
61CONFIG_USB_EHCI_HCD=y
62CONFIG_USB_EHCI_HCD_PLATFORM=y
63CONFIG_USB_UHCI_HCD=y
64CONFIG_USB_STORAGE=y
65CONFIG_NOP_USB_XCEIV=y
66CONFIG_USB_GPIO_VBUS=y
67CONFIG_USB_ULPI=y
68CONFIG_MMC=y
69CONFIG_MMC_DEBUG=y
70CONFIG_NEW_LEDS=y
71CONFIG_LEDS_CLASS=y
72CONFIG_LEDS_TRIGGERS=y
73CONFIG_RTC_CLASS=y
74CONFIG_RTC_DRV_VT8500=y
75CONFIG_DMADEVICES=y
76CONFIG_COMMON_CLK_DEBUG=y
77# CONFIG_IOMMU_SUPPORT is not set
78CONFIG_PWM=y
79CONFIG_PWM_VT8500=y
80CONFIG_RESET_CONTROLLER=y
81CONFIG_GENERIC_PHY=y
82CONFIG_EXT4_FS=y
83CONFIG_TMPFS=y
84CONFIG_NFS_FS=y
85CONFIG_NFS_V3_ACL=y
86CONFIG_NFS_V4=y
87CONFIG_ROOT_NFS=y
88CONFIG_PRINTK_TIME=y
89CONFIG_DEBUG_KERNEL=y
90CONFIG_LOCKUP_DETECTOR=y
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1b737097c95..90aab2d5a07f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o gpio.o setup.o 5obj-y := irq.o gpio.o setup.o sysirq_mask.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index f8629a3fa245..d6a1fa85371d 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -351,6 +351,8 @@ static void __init at91sam9260_initialize(void)
351 arm_pm_idle = at91sam9_idle; 351 arm_pm_idle = at91sam9_idle;
352 arm_pm_restart = at91sam9_alt_restart; 352 arm_pm_restart = at91sam9_alt_restart;
353 353
354 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
355
354 /* Register GPIO subsystem */ 356 /* Register GPIO subsystem */
355 at91_gpio_init(at91sam9260_gpio, 3); 357 at91_gpio_init(at91sam9260_gpio, 3);
356} 358}
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 1f3867a17a28..23ba1d8a1531 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -293,6 +293,8 @@ static void __init at91sam9261_initialize(void)
293 arm_pm_idle = at91sam9_idle; 293 arm_pm_idle = at91sam9_idle;
294 arm_pm_restart = at91sam9_alt_restart; 294 arm_pm_restart = at91sam9_alt_restart;
295 295
296 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
297
296 /* Register GPIO subsystem */ 298 /* Register GPIO subsystem */
297 at91_gpio_init(at91sam9261_gpio, 3); 299 at91_gpio_init(at91sam9261_gpio, 3);
298} 300}
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 90d455d294a1..7eccb0fc57bc 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -330,6 +330,9 @@ static void __init at91sam9263_initialize(void)
330 arm_pm_idle = at91sam9_idle; 330 arm_pm_idle = at91sam9_idle;
331 arm_pm_restart = at91sam9_alt_restart; 331 arm_pm_restart = at91sam9_alt_restart;
332 332
333 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
334 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
335
333 /* Register GPIO subsystem */ 336 /* Register GPIO subsystem */
334 at91_gpio_init(at91sam9263_gpio, 5); 337 at91_gpio_init(at91sam9263_gpio, 5);
335} 338}
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index e9bf0b8f40eb..9405aa08b104 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -379,6 +379,9 @@ static void __init at91sam9g45_initialize(void)
379 arm_pm_idle = at91sam9_idle; 379 arm_pm_idle = at91sam9_idle;
380 arm_pm_restart = at91sam9g45_restart; 380 arm_pm_restart = at91sam9g45_restart;
381 381
382 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
383 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
384
382 /* Register GPIO subsystem */ 385 /* Register GPIO subsystem */
383 at91_gpio_init(at91sam9g45_gpio, 5); 386 at91_gpio_init(at91sam9g45_gpio, 5);
384} 387}
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 2d895a297739..388ec3aec4b9 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -224,7 +224,13 @@ static void __init at91sam9n12_map_io(void)
224 at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); 224 at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
225} 225}
226 226
227static void __init at91sam9n12_initialize(void)
228{
229 at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC);
230}
231
227AT91_SOC_START(at91sam9n12) 232AT91_SOC_START(at91sam9n12)
228 .map_io = at91sam9n12_map_io, 233 .map_io = at91sam9n12_map_io,
229 .register_clocks = at91sam9n12_register_clocks, 234 .register_clocks = at91sam9n12_register_clocks,
235 .init = at91sam9n12_initialize,
230AT91_SOC_END 236AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 88995af09c04..0750ffb7e6b1 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -296,6 +296,9 @@ static void __init at91sam9rl_initialize(void)
296 arm_pm_idle = at91sam9_idle; 296 arm_pm_idle = at91sam9_idle;
297 arm_pm_restart = at91sam9_alt_restart; 297 arm_pm_restart = at91sam9_alt_restart;
298 298
299 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
300 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
301
299 /* Register GPIO subsystem */ 302 /* Register GPIO subsystem */
300 at91_gpio_init(at91sam9rl_gpio, 4); 303 at91_gpio_init(at91sam9rl_gpio, 4);
301} 304}
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 916e5a142917..e8a2e075a1b8 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -322,6 +322,11 @@ static void __init at91sam9x5_map_io(void)
322 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); 322 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
323} 323}
324 324
325static void __init at91sam9x5_initialize(void)
326{
327 at91_sysirq_mask_rtc(AT91SAM9X5_BASE_RTC);
328}
329
325/* -------------------------------------------------------------------- 330/* --------------------------------------------------------------------
326 * Interrupt initialization 331 * Interrupt initialization
327 * -------------------------------------------------------------------- */ 332 * -------------------------------------------------------------------- */
@@ -329,4 +334,5 @@ static void __init at91sam9x5_map_io(void)
329AT91_SOC_START(at91sam9x5) 334AT91_SOC_START(at91sam9x5)
330 .map_io = at91sam9x5_map_io, 335 .map_io = at91sam9x5_map_io,
331 .register_clocks = at91sam9x5_register_clocks, 336 .register_clocks = at91sam9x5_register_clocks,
337 .init = at91sam9x5_initialize,
332AT91_SOC_END 338AT91_SOC_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index dc6e2f5f804d..26dee3ce9397 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -34,6 +34,8 @@ extern int __init at91_aic_of_init(struct device_node *node,
34 struct device_node *parent); 34 struct device_node *parent);
35extern int __init at91_aic5_of_init(struct device_node *node, 35extern int __init at91_aic5_of_init(struct device_node *node,
36 struct device_node *parent); 36 struct device_node *parent);
37extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
38extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
37 39
38 40
39 /* Timer */ 41 /* Timer */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index d374b87c0459..0151bcf6163c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -49,6 +49,11 @@
49#define AT91SAM9N12_BASE_USART3 0xf8028000 49#define AT91SAM9N12_BASE_USART3 0xf8028000
50 50
51/* 51/*
52 * System Peripherals
53 */
54#define AT91SAM9N12_BASE_RTC 0xfffffeb0
55
56/*
52 * Internal Memory. 57 * Internal Memory.
53 */ 58 */
54#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 59#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index c75ee19b58d3..2fc76c49e97c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -55,6 +55,11 @@
55#define AT91SAM9X5_BASE_USART2 0xf8024000 55#define AT91SAM9X5_BASE_USART2 0xf8024000
56 56
57/* 57/*
58 * System Peripherals
59 */
60#define AT91SAM9X5_BASE_RTC 0xfffffeb0
61
62/*
58 * Internal Memory. 63 * Internal Memory.
59 */ 64 */
60#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 65#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 31096a8aaf1d..25613d8c6dcd 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -73,6 +73,11 @@
73#define SAMA5D3_BASE_USART3 0xf8024000 73#define SAMA5D3_BASE_USART3 0xf8024000
74 74
75/* 75/*
76 * System Peripherals
77 */
78#define SAMA5D3_BASE_RTC 0xfffffeb0
79
80/*
76 * Internal Memory 81 * Internal Memory
77 */ 82 */
78#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 83#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 401279715ab1..3ea86428ee09 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -371,7 +371,13 @@ static void __init sama5d3_map_io(void)
371 at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); 371 at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
372} 372}
373 373
374static void __init sama5d3_initialize(void)
375{
376 at91_sysirq_mask_rtc(SAMA5D3_BASE_RTC);
377}
378
374AT91_SOC_START(sama5d3) 379AT91_SOC_START(sama5d3)
375 .map_io = sama5d3_map_io, 380 .map_io = sama5d3_map_io,
376 .register_clocks = sama5d3_register_clocks, 381 .register_clocks = sama5d3_register_clocks,
382 .init = sama5d3_initialize,
377AT91_SOC_END 383AT91_SOC_END
diff --git a/arch/arm/mach-at91/sysirq_mask.c b/arch/arm/mach-at91/sysirq_mask.c
new file mode 100644
index 000000000000..2ba694f9626b
--- /dev/null
+++ b/arch/arm/mach-at91/sysirq_mask.c
@@ -0,0 +1,71 @@
1/*
2 * sysirq_mask.c - System-interrupt masking
3 *
4 * Copyright (C) 2013 Johan Hovold <jhovold@gmail.com>
5 *
6 * Functions to disable system interrupts from backup-powered peripherals.
7 *
8 * The RTC and RTT-peripherals are generally powered by backup power (VDDBU)
9 * and are not reset on wake-up, user, watchdog or software reset. This means
10 * that their interrupts may be enabled during early boot (e.g. after a user
11 * reset).
12 *
13 * As the RTC and RTT share the system-interrupt line with the PIT, an
14 * interrupt occurring before a handler has been installed would lead to the
15 * system interrupt being disabled and prevent the system from booting.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 */
22
23#include <linux/io.h>
24#include <mach/at91_rtt.h>
25
26#include "generic.h"
27
28#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
29#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
30
31void __init at91_sysirq_mask_rtc(u32 rtc_base)
32{
33 void __iomem *base;
34 u32 mask;
35
36 base = ioremap(rtc_base, 64);
37 if (!base)
38 return;
39
40 mask = readl_relaxed(base + AT91_RTC_IMR);
41 if (mask) {
42 pr_info("AT91: Disabling rtc irq\n");
43 writel_relaxed(mask, base + AT91_RTC_IDR);
44 (void)readl_relaxed(base + AT91_RTC_IMR); /* flush */
45 }
46
47 iounmap(base);
48}
49
50void __init at91_sysirq_mask_rtt(u32 rtt_base)
51{
52 void __iomem *base;
53 void __iomem *reg;
54 u32 mode;
55
56 base = ioremap(rtt_base, 16);
57 if (!base)
58 return;
59
60 reg = base + AT91_RTT_MR;
61
62 mode = readl_relaxed(reg);
63 if (mode & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)) {
64 pr_info("AT91: Disabling rtt irq\n");
65 mode &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
66 writel_relaxed(mode, reg);
67 (void)readl_relaxed(reg); /* flush */
68 }
69
70 iounmap(base);
71}
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 08332d841440..0aded64a9ebc 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -7,7 +7,7 @@ config ARCH_HIGHBANK
7 select ARCH_SUPPORTS_BIG_ENDIAN 7 select ARCH_SUPPORTS_BIG_ENDIAN
8 select ARCH_WANT_OPTIONAL_GPIOLIB 8 select ARCH_WANT_OPTIONAL_GPIOLIB
9 select ARM_AMBA 9 select ARM_AMBA
10 select ARM_ERRATA_764369 10 select ARM_ERRATA_764369 if SMP
11 select ARM_ERRATA_775420 11 select ARM_ERRATA_775420
12 select ARM_ERRATA_798181 if SMP 12 select ARM_ERRATA_798181 if SMP
13 select ARM_GIC 13 select ARM_GIC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index bbe1f5bb799c..1789e2b31903 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -102,8 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
102 102
103ifeq ($(CONFIG_PM),y) 103ifeq ($(CONFIG_PM),y)
104obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o 104obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
105# i.MX6SL reuses pm-imx6q.c 105# i.MX6SL reuses i.MX6Q code
106obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o 106obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
107endif 107endif
108 108
109# i.MX5 based machines 109# i.MX5 based machines
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index d756d91fd741..04cfd0fcb0e5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -122,13 +122,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
122 { .val = 1, .div = 10, }, 122 { .val = 1, .div = 10, },
123 { .val = 2, .div = 5, }, 123 { .val = 2, .div = 5, },
124 { .val = 3, .div = 4, }, 124 { .val = 3, .div = 4, },
125 { /* sentinel */ }
125}; 126};
126 127
127static struct clk_div_table post_div_table[] = { 128static struct clk_div_table post_div_table[] = {
128 { .val = 2, .div = 1, }, 129 { .val = 2, .div = 1, },
129 { .val = 1, .div = 2, }, 130 { .val = 1, .div = 2, },
130 { .val = 0, .div = 4, }, 131 { .val = 0, .div = 4, },
131 { } 132 { /* sentinel */ }
132}; 133};
133 134
134static struct clk_div_table video_div_table[] = { 135static struct clk_div_table video_div_table[] = {
@@ -136,7 +137,7 @@ static struct clk_div_table video_div_table[] = {
136 { .val = 1, .div = 2, }, 137 { .val = 1, .div = 2, },
137 { .val = 2, .div = 1, }, 138 { .val = 2, .div = 1, },
138 { .val = 3, .div = 4, }, 139 { .val = 3, .div = 4, },
139 { } 140 { /* sentinel */ }
140}; 141};
141 142
142static void __init imx6q_clocks_init(struct device_node *ccm_node) 143static void __init imx6q_clocks_init(struct device_node *ccm_node)
@@ -298,7 +299,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
298 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); 299 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
299 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); 300 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
300 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); 301 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
301 clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); 302 clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
302 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); 303 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
303 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); 304 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
304 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); 305 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index f6640b6a7b31..61364050fccd 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/delay.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/slab.h> 17#include <linux/slab.h>
17#include <linux/jiffies.h> 18#include <linux/jiffies.h>
@@ -45,33 +46,49 @@ struct clk_pllv3 {
45 46
46#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 47#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
47 48
49static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
50{
51 unsigned long timeout = jiffies + msecs_to_jiffies(10);
52 u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
53
54 /* No need to wait for lock when pll is not powered up */
55 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
56 return 0;
57
58 /* Wait for PLL to lock */
59 do {
60 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
61 break;
62 if (time_after(jiffies, timeout))
63 break;
64 usleep_range(50, 500);
65 } while (1);
66
67 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
68}
69
48static int clk_pllv3_prepare(struct clk_hw *hw) 70static int clk_pllv3_prepare(struct clk_hw *hw)
49{ 71{
50 struct clk_pllv3 *pll = to_clk_pllv3(hw); 72 struct clk_pllv3 *pll = to_clk_pllv3(hw);
51 unsigned long timeout;
52 u32 val; 73 u32 val;
74 int ret;
53 75
54 val = readl_relaxed(pll->base); 76 val = readl_relaxed(pll->base);
55 val &= ~BM_PLL_BYPASS;
56 if (pll->powerup_set) 77 if (pll->powerup_set)
57 val |= BM_PLL_POWER; 78 val |= BM_PLL_POWER;
58 else 79 else
59 val &= ~BM_PLL_POWER; 80 val &= ~BM_PLL_POWER;
60 writel_relaxed(val, pll->base); 81 writel_relaxed(val, pll->base);
61 82
62 timeout = jiffies + msecs_to_jiffies(10); 83 ret = clk_pllv3_wait_lock(pll);
63 /* Wait for PLL to lock */ 84 if (ret)
64 do { 85 return ret;
65 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
66 break;
67 if (time_after(jiffies, timeout))
68 break;
69 } while (1);
70 86
71 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 87 val = readl_relaxed(pll->base);
72 return 0; 88 val &= ~BM_PLL_BYPASS;
73 else 89 writel_relaxed(val, pll->base);
74 return -ETIMEDOUT; 90
91 return 0;
75} 92}
76 93
77static void clk_pllv3_unprepare(struct clk_hw *hw) 94static void clk_pllv3_unprepare(struct clk_hw *hw)
@@ -146,7 +163,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
146 val |= div; 163 val |= div;
147 writel_relaxed(val, pll->base); 164 writel_relaxed(val, pll->base);
148 165
149 return 0; 166 return clk_pllv3_wait_lock(pll);
150} 167}
151 168
152static const struct clk_ops clk_pllv3_ops = { 169static const struct clk_ops clk_pllv3_ops = {
@@ -202,7 +219,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
202 val |= div; 219 val |= div;
203 writel_relaxed(val, pll->base); 220 writel_relaxed(val, pll->base);
204 221
205 return 0; 222 return clk_pllv3_wait_lock(pll);
206} 223}
207 224
208static const struct clk_ops clk_pllv3_sys_ops = { 225static const struct clk_ops clk_pllv3_sys_ops = {
@@ -276,7 +293,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
276 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); 293 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
277 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); 294 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
278 295
279 return 0; 296 return clk_pllv3_wait_lock(pll);
280} 297}
281 298
282static const struct clk_ops clk_pllv3_av_ops = { 299static const struct clk_ops clk_pllv3_av_ops = {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 7cbe22d0c6e9..24a7899e36a8 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -127,11 +127,6 @@ static inline void imx_smp_prepare(void) {}
127static inline void imx_scu_standby_enable(void) {} 127static inline void imx_scu_standby_enable(void) {}
128#endif 128#endif
129void imx_src_init(void); 129void imx_src_init(void);
130#ifdef CONFIG_HAVE_IMX_SRC
131void imx_src_prepare_restart(void);
132#else
133static inline void imx_src_prepare_restart(void) {}
134#endif
135void imx_gpc_init(void); 130void imx_gpc_init(void);
136void imx_gpc_pre_suspend(void); 131void imx_gpc_pre_suspend(void);
137void imx_gpc_post_resume(void); 132void imx_gpc_post_resume(void);
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 4754373e7e7d..45f7f4e0a447 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -115,21 +115,6 @@ void imx_set_cpu_arg(int cpu, u32 arg)
115 writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); 115 writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
116} 116}
117 117
118void imx_src_prepare_restart(void)
119{
120 u32 val;
121
122 /* clear enable bits of secondary cores */
123 spin_lock(&scr_lock);
124 val = readl_relaxed(src_base + SRC_SCR);
125 val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
126 writel_relaxed(val, src_base + SRC_SCR);
127 spin_unlock(&scr_lock);
128
129 /* clear persistent entry register of primary core */
130 writel_relaxed(0, src_base + SRC_GPR1);
131}
132
133void __init imx_src_init(void) 118void __init imx_src_init(void)
134{ 119{
135 struct device_node *np; 120 struct device_node *np;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index e6edcd38b282..5e3027d3692f 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -42,9 +42,6 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
42{ 42{
43 unsigned int wcr_enable; 43 unsigned int wcr_enable;
44 44
45 if (cpu_is_imx6q() || cpu_is_imx6dl())
46 imx_src_prepare_restart();
47
48 if (wdog_clk) 45 if (wdog_clk)
49 clk_enable(wdog_clk); 46 clk_enable(wdog_clk);
50 47
@@ -55,7 +52,14 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
55 52
56 /* Assert SRS signal */ 53 /* Assert SRS signal */
57 __raw_writew(wcr_enable, wdog_base); 54 __raw_writew(wcr_enable, wdog_base);
58 /* write twice to ensure the request will not get ignored */ 55 /*
56 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
57 * written twice), we add another two writes to ensure there must be at
58 * least two writes happen in the same one 32kHz clock period. We save
59 * the target check here, since the writes shouldn't be a huge burden
60 * for other platforms.
61 */
62 __raw_writew(wcr_enable, wdog_base);
59 __raw_writew(wcr_enable, wdog_base); 63 __raw_writew(wcr_enable, wdog_base);
60 64
61 /* wait for reset to assert... */ 65 /* wait for reset to assert... */
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 1df6e7602cad..4fc0a195de01 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -198,7 +198,8 @@ static struct mmci_platform_data mmc_data = {
198static void cp_clcd_enable(struct clcd_fb *fb) 198static void cp_clcd_enable(struct clcd_fb *fb)
199{ 199{
200 struct fb_var_screeninfo *var = &fb->fb.var; 200 struct fb_var_screeninfo *var = &fb->fb.var;
201 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2; 201 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
202 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
202 203
203 if (var->bits_per_pixel <= 8 || 204 if (var->bits_per_pixel <= 8 ||
204 (var->bits_per_pixel == 16 && var->green.length == 5)) 205 (var->bits_per_pixel == 16 && var->green.length == 5))
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e15ac005ef17..1f25f3e99c05 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -40,7 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o
40obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o 40obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
41obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o 41obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
42obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) 42obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
43obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) 43obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
44 44
45plus_sec := $(call as-instr,.arch_extension sec,+sec) 45plus_sec := $(call as-instr,.arch_extension sec,+sec)
46AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 46AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index a516c1bda141..d6ed819ff15c 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -510,7 +510,7 @@ static int __init beagle_opp_init(void)
510 mpu_dev = get_cpu_device(0); 510 mpu_dev = get_cpu_device(0);
511 iva_dev = omap_device_get_by_hwmod_name("iva"); 511 iva_dev = omap_device_get_by_hwmod_name("iva");
512 512
513 if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) { 513 if (!mpu_dev || IS_ERR(iva_dev)) {
514 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n", 514 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
515 __func__, mpu_dev, iva_dev); 515 __func__, mpu_dev, iva_dev);
516 return -ENODEV; 516 return -ENODEV;
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 03a2829beb8e..3b05aea56d1f 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -381,6 +381,42 @@ static struct clk_hw_omap dpll4_ck_hw = {
381 381
382DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops); 382DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
383 383
384static const struct clk_div_table dpll4_mx_ck_div_table[] = {
385 { .div = 1, .val = 1 },
386 { .div = 2, .val = 2 },
387 { .div = 3, .val = 3 },
388 { .div = 4, .val = 4 },
389 { .div = 5, .val = 5 },
390 { .div = 6, .val = 6 },
391 { .div = 7, .val = 7 },
392 { .div = 8, .val = 8 },
393 { .div = 9, .val = 9 },
394 { .div = 10, .val = 10 },
395 { .div = 11, .val = 11 },
396 { .div = 12, .val = 12 },
397 { .div = 13, .val = 13 },
398 { .div = 14, .val = 14 },
399 { .div = 15, .val = 15 },
400 { .div = 16, .val = 16 },
401 { .div = 17, .val = 17 },
402 { .div = 18, .val = 18 },
403 { .div = 19, .val = 19 },
404 { .div = 20, .val = 20 },
405 { .div = 21, .val = 21 },
406 { .div = 22, .val = 22 },
407 { .div = 23, .val = 23 },
408 { .div = 24, .val = 24 },
409 { .div = 25, .val = 25 },
410 { .div = 26, .val = 26 },
411 { .div = 27, .val = 27 },
412 { .div = 28, .val = 28 },
413 { .div = 29, .val = 29 },
414 { .div = 30, .val = 30 },
415 { .div = 31, .val = 31 },
416 { .div = 32, .val = 32 },
417 { .div = 0 },
418};
419
384DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, 420DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
385 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 421 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
386 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, 422 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
@@ -524,10 +560,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
524 { .div = 0 } 560 { .div = 0 }
525}; 561};
526 562
527DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, 563DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
528 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 564 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
529 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, 565 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
530 CLK_DIVIDER_ONE_BASED, NULL); 566 0, dpll4_mx_ck_div_table, NULL);
531 567
532static struct clk dpll4_m3x2_ck; 568static struct clk dpll4_m3x2_ck;
533 569
@@ -847,10 +883,10 @@ static struct clk dpll3_m3x2_ck_3630 = {
847 883
848DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1); 884DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
849 885
850DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, 886DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
851 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 887 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
852 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, 888 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
853 CLK_DIVIDER_ONE_BASED, NULL); 889 0, dpll4_mx_ck_div_table, NULL);
854 890
855static struct clk dpll4_m4x2_ck; 891static struct clk dpll4_m4x2_ck;
856 892
@@ -869,7 +905,8 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = {
869 .clkdm_name = "dpll4_clkdm", 905 .clkdm_name = "dpll4_clkdm",
870}; 906};
871 907
872DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops); 908DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
909 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
873 910
874static struct clk dpll4_m4x2_ck_3630 = { 911static struct clk dpll4_m4x2_ck_3630 = {
875 .name = "dpll4_m4x2_ck", 912 .name = "dpll4_m4x2_ck",
@@ -877,6 +914,7 @@ static struct clk dpll4_m4x2_ck_3630 = {
877 .parent_names = dpll4_m4x2_ck_parent_names, 914 .parent_names = dpll4_m4x2_ck_parent_names,
878 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names), 915 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
879 .ops = &dpll4_m5x2_ck_3630_ops, 916 .ops = &dpll4_m5x2_ck_3630_ops,
917 .flags = CLK_SET_RATE_PARENT,
880}; 918};
881 919
882DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, 920DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
@@ -968,8 +1006,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
968 .clkdm_name = "dss_clkdm", 1006 .clkdm_name = "dss_clkdm",
969}; 1007};
970 1008
971DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, 1009DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
972 aes2_ick_ops); 1010 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1011 CLK_SET_RATE_PARENT);
973 1012
974static struct clk dss1_alwon_fck_3430es2; 1013static struct clk dss1_alwon_fck_3430es2;
975 1014
@@ -983,8 +1022,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
983 .clkdm_name = "dss_clkdm", 1022 .clkdm_name = "dss_clkdm",
984}; 1023};
985 1024
986DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, 1025DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
987 aes2_ick_ops); 1026 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1027 CLK_SET_RATE_PARENT);
988 1028
989static struct clk dss2_alwon_fck; 1029static struct clk dss2_alwon_fck;
990 1030
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index b237950eb8a3..ec0dc0b1755e 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
830 OMAP4430_CM_DSS_DSS_CLKCTRL, 830 OMAP4430_CM_DSS_DSS_CLKCTRL,
831 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); 831 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
832 832
833DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, 833DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
834 CLK_SET_RATE_PARENT,
834 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, 835 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
835 0x0, NULL); 836 0x0, NULL);
836 837
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index ef990118d32b..2757504a13c4 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -83,7 +83,7 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
83 pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id, 83 pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
84 gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources), 84 gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
85 &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config)); 85 &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
86 if (!pdev) { 86 if (IS_ERR(pdev)) {
87 pr_err("Unable to register platform device\n"); 87 pr_err("Unable to register platform device\n");
88 gpio_free(gpmc_cfg->gpio_reset); 88 gpio_free(gpmc_cfg->gpio_reset);
89 goto free2; 89 goto free2;
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index b69dd9abb50a..53f0735817bb 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -621,6 +621,7 @@ static int _od_suspend_noirq(struct device *dev)
621 621
622 if (!ret && !pm_runtime_status_suspended(dev)) { 622 if (!ret && !pm_runtime_status_suspended(dev)) {
623 if (pm_generic_runtime_suspend(dev) == 0) { 623 if (pm_generic_runtime_suspend(dev) == 0) {
624 pm_runtime_set_suspended(dev);
624 omap_device_idle(pdev); 625 omap_device_idle(pdev);
625 od->flags |= OMAP_DEVICE_SUSPENDED; 626 od->flags |= OMAP_DEVICE_SUSPENDED;
626 } 627 }
@@ -634,10 +635,18 @@ static int _od_resume_noirq(struct device *dev)
634 struct platform_device *pdev = to_platform_device(dev); 635 struct platform_device *pdev = to_platform_device(dev);
635 struct omap_device *od = to_omap_device(pdev); 636 struct omap_device *od = to_omap_device(pdev);
636 637
637 if ((od->flags & OMAP_DEVICE_SUSPENDED) && 638 if (od->flags & OMAP_DEVICE_SUSPENDED) {
638 !pm_runtime_status_suspended(dev)) {
639 od->flags &= ~OMAP_DEVICE_SUSPENDED; 639 od->flags &= ~OMAP_DEVICE_SUSPENDED;
640 omap_device_enable(pdev); 640 omap_device_enable(pdev);
641 /*
642 * XXX: we run before core runtime pm has resumed itself. At
643 * this point in time, we just restore the runtime pm state and
644 * considering symmetric operations in resume, we donot expect
645 * to fail. If we failed, something changed in core runtime_pm
646 * framework OR some device driver messed things up, hence, WARN
647 */
648 WARN(pm_runtime_set_active(dev),
649 "Could not set %s runtime state active\n", dev_name(dev));
641 pm_generic_runtime_resume(dev); 650 pm_generic_runtime_resume(dev);
642 } 651 }
643 652
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index a085d9cc1f5d..7a976065e138 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -42,7 +42,8 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
42extern void omap4_prm_vcvp_write(u32 val, u8 offset); 42extern void omap4_prm_vcvp_write(u32 val, u8 offset);
43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44 44
45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) 45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
46 defined(CONFIG_SOC_DRA7XX)
46void omap44xx_prm_reconfigure_io_chain(void); 47void omap44xx_prm_reconfigure_io_chain(void);
47#else 48#else
48static inline void omap44xx_prm_reconfigure_io_chain(void) 49static inline void omap44xx_prm_reconfigure_io_chain(void)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index a67f83fd3f78..d71654bc8d54 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -12,7 +12,7 @@ menuconfig ARCH_STI
12 select HAVE_ARM_SCU if SMP 12 select HAVE_ARM_SCU if SMP
13 select ARCH_REQUIRE_GPIOLIB 13 select ARCH_REQUIRE_GPIOLIB
14 select ARM_ERRATA_754322 14 select ARM_ERRATA_754322
15 select ARM_ERRATA_764369 15 select ARM_ERRATA_764369 if SMP
16 select ARM_ERRATA_775420 16 select ARM_ERRATA_775420
17 select PL310_ERRATA_753970 if CACHE_PL310 17 select PL310_ERRATA_753970 if CACHE_PL310
18 select PL310_ERRATA_769419 if CACHE_PL310 18 select PL310_ERRATA_769419 if CACHE_PL310
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ce553d557c31..73368176c6e8 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -90,9 +90,9 @@ static void __init tegra_init_cache(void)
90 90
91static void __init tegra_init_early(void) 91static void __init tegra_init_early(void)
92{ 92{
93 tegra_cpu_reset_handler_init();
94 tegra_apb_io_init(); 93 tegra_apb_io_init();
95 tegra_init_fuse(); 94 tegra_init_fuse();
95 tegra_cpu_reset_handler_init();
96 tegra_init_cache(); 96 tegra_init_cache();
97 tegra_powergate_init(); 97 tegra_powergate_init();
98 tegra_hotplug_init(); 98 tegra_hotplug_init();
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 20:08:04 -0500