175 files changed, 2625 insertions, 2094 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index 7f8f281f2585..97fb7d0365d1 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -76,6 +76,15 @@ config OPTPROBES
        depends on KPROBES && HAVE_OPTPROBES
        depends on !PREEMPT
+config KPROBES_ON_FTRACE
+        def_bool y
+        depends on KPROBES && HAVE_KPROBES_ON_FTRACE
+        depends on DYNAMIC_FTRACE_WITH_REGS
+        help
+         If function tracer is enabled and the arch supports full
+         passing of pt_regs to function tracing, then kprobes can
+         optimize on top of function tracing.
 config UPROBES
        bool "Transparent user-space probes (EXPERIMENTAL)"
        depends on UPROBE_EVENT && PERF_EVENTS
@@ -158,6 +167,9 @@ config HAVE_KRETPROBES
 config HAVE_OPTPROBES
        bool
+config HAVE_KPROBES_ON_FTRACE
+        bool
 config HAVE_NMI_WATCHDOG
        bool
 #
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 9d5904cc7712..9b504af2e966 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -5,7 +5,6 @@ config ALPHA
        select HAVE_IDE
        select HAVE_OPROFILE
        select HAVE_SYSCALL_WRAPPERS
-        select HAVE_IRQ_WORK
        select HAVE_PCSPKR_PLATFORM
        select HAVE_PERF_EVENTS
        select HAVE_DMA_ATTRS
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 14db93e4c8a8..dbc1760f418b 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -1139,6 +1139,7 @@ struct rusage32 {
 SYSCALL_DEFINE2(osf_getrusage, int, who, struct rusage32 __user *, ru)
 {
        struct rusage32 r;
+        cputime_t utime, stime;
        if (who != RUSAGE_SELF && who != RUSAGE_CHILDREN)
                return -EINVAL;
@@ -1146,8 +1147,9 @@ SYSCALL_DEFINE2(osf_getrusage, int, who, struct rusage32 __user *, ru)
        memset(&r, 0, sizeof(r));
        switch (who) {
        case RUSAGE_SELF:
-                jiffies_to_timeval32(current->utime, &r.ru_utime);
+                task_cputime(current, &utime, &stime);
-                jiffies_to_timeval32(current->stime, &r.ru_stime);
+                jiffies_to_timeval32(utime, &r.ru_utime);
+                jiffies_to_timeval32(stime, &r.ru_stime);
                r.ru_minflt = current->min_flt;
                r.ru_majflt = current->maj_flt;
                break;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 67874b82a4ed..9bbe760f2352 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -36,7 +36,6 @@ config ARM
        select HAVE_GENERIC_HARDIRQS
        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
        select HAVE_IDE if PCI || ISA || PCMCIA
-        select HAVE_IRQ_WORK
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_LZMA
        select HAVE_KERNEL_LZO
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 36ae03a3f5d1..87dfa9026c5b 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -351,6 +351,25 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
+static u8 gic_get_cpumask(struct gic_chip_data *gic)
+{
+        void __iomem *base = gic_data_dist_base(gic);
+        u32 mask, i;
+        for (i = mask = 0; i < 32; i += 4) {
+                mask = readl_relaxed(base + GIC_DIST_TARGET + i);
+                mask |= mask >> 16;
+                mask |= mask >> 8;
+                if (mask)
+                        break;
+        }
+        if (!mask)
+                pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
+        return mask;
+}
 static void __init gic_dist_init(struct gic_chip_data *gic)
 {
        unsigned int i;
@@ -369,7 +388,9 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
        /*
         * Set all global interrupts to this CPU only.
         */
-        cpumask = readl_relaxed(base + GIC_DIST_TARGET + 0);
+        cpumask = gic_get_cpumask(gic);
+        cpumask |= cpumask << 8;
+        cpumask |= cpumask << 16;
        for (i = 32; i < gic_irqs; i += 4)
                writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
@@ -400,7 +421,7 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
         * Get what the GIC says our CPU mask is.
         */
        BUG_ON(cpu >= NR_GIC_CPU_IF);
-        cpu_mask = readl_relaxed(dist_base + GIC_DIST_TARGET + 0);
+        cpu_mask = gic_get_cpumask(gic);
        gic_cpu_map[cpu] = cpu_mask;
        /*
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 73cf03aa981e..1c4df27f9332 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -37,7 +37,7 @@
 */
 #define PAGE_OFFSET             UL(CONFIG_PAGE_OFFSET)
 #define TASK_SIZE               (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000))
-#define TASK_UNMAPPED_BASE      (UL(CONFIG_PAGE_OFFSET) / 3)
+#define TASK_UNMAPPED_BASE      ALIGN(TASK_SIZE / 3, SZ_16M)
 /*
 * The maximum size of a 26-bit user space task.
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 4eb6d005ffaa..86dff32a0737 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -7,8 +7,14 @@
 #ifndef __ASSEMBLER__
 unsigned int scu_get_core_count(void __iomem *);
-void scu_enable(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+#ifdef CONFIG_SMP
+void scu_enable(void __iomem *scu_base);
+#else
+static inline void scu_enable(void __iomem *scu_base) {}
+#endif
 #endif
 #endif
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index b9f015e843d8..45eac87ed66a 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
 int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
        unsigned int val;
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (mode > 3 || mode == 1 || cpu > 3)
                return -EINVAL;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e103c290bc9e..85afb031b676 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -414,7 +414,7 @@ config MACH_EXYNOS4_DT
        select CPU_EXYNOS4210
        select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
        select PINCTRL
-        select PINCTRL_EXYNOS4
+        select PINCTRL_EXYNOS
        select USE_OF
        help
          Machine support for Samsung Exynos4 machine with device tree enabled.
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 981dc1e1da51..e6c061282939 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -28,6 +28,7 @@
 #include <asm/arch_timer.h>
 #include <asm/cacheflush.h>
+#include <asm/cputype.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
@@ -59,7 +60,7 @@ static void __init highbank_scu_map_io(void)
 void highbank_set_cpu_jump(int cpu, void *jump_addr)
 {
-        cpu = cpu_logical_map(cpu);
+        cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
        writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h
index 70af9d13fcef..5995df7f2622 100644
--- a/arch/arm/mach-highbank/sysregs.h
+++ b/arch/arm/mach-highbank/sysregs.h
@@ -37,7 +37,7 @@ extern void __iomem *sregs_base;
 static inline void highbank_set_core_pwr(void)
 {
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (scu_base_addr)
                scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
        else
@@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void)
 static inline void highbank_clear_core_pwr(void)
 {
-        int cpu = cpu_logical_map(smp_processor_id());
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
        if (scu_base_addr)
                scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
        else
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
index d6b5073692d2..44754230fdcc 100644
--- a/arch/arm/mach-realview/include/mach/irqs-eb.h
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -115,7 +115,7 @@
 /*
 * Only define NR_IRQS if less than NR_IRQS_EB
 */
-#define NR_IRQS_EB              (IRQ_EB_GIC_START + 96)
+#define NR_IRQS_EB              (IRQ_EB_GIC_START + 128)
 #if defined(CONFIG_MACH_REALVIEW_EB) \
        && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 076c26d43864..dda3904dc64c 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -640,7 +640,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
        if (is_coherent || nommu())
                addr = __alloc_simple_buffer(dev, size, gfp, &page);
-        else if (gfp & GFP_ATOMIC)
+        else if (!(gfp & __GFP_WAIT))
                addr = __alloc_from_pool(size, &page);
        else if (!IS_ENABLED(CONFIG_CMA))
                addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f8f362aafee9..75e915b72471 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -21,7 +21,6 @@ config ARM64
        select HAVE_GENERIC_DMA_COHERENT
        select HAVE_GENERIC_HARDIRQS
        select HAVE_HW_BREAKPOINT if PERF_EVENTS
-        select HAVE_IRQ_WORK
        select HAVE_MEMBLOCK
        select HAVE_PERF_EVENTS
        select IRQ_DOMAIN
diff --git a/arch/avr32/include/asm/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h
index aaf5199d8fcb..b3d18f9f3e8d 100644
--- a/arch/avr32/include/asm/dma-mapping.h
+++ b/arch/avr32/include/asm/dma-mapping.h
@@ -336,4 +336,14 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+/* drivers/base/dma-mapping.c */
+extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+                           void *cpu_addr, dma_addr_t dma_addr, size_t size);
+extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size);
+#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s)
+#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s)
 #endif /* __ASM_AVR32_DMA_MAPPING_H */
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index b6f3ad5441c5..67e4aaad78f5 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -24,7 +24,6 @@ config BLACKFIN
        select HAVE_FUNCTION_TRACER
        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
        select HAVE_IDE
-        select HAVE_IRQ_WORK
        select HAVE_KERNEL_GZIP if RAMKERNEL
        select HAVE_KERNEL_BZIP2 if RAMKERNEL
        select HAVE_KERNEL_LZMA if RAMKERNEL
@@ -38,7 +37,6 @@ config BLACKFIN
        select HAVE_GENERIC_HARDIRQS
        select GENERIC_ATOMIC64
        select GENERIC_IRQ_PROBE
-        select IRQ_PER_CPU if SMP
        select USE_GENERIC_SMP_HELPERS if SMP
        select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
        select GENERIC_SMP_IDLE_THREAD
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index bbf461076a0a..054d9ec57d9d 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -154,4 +154,14 @@ dma_cache_sync(struct device *dev, void *vaddr, size_t size,
        _dma_sync((dma_addr_t)vaddr, size, dir);
 }
+/* drivers/base/dma-mapping.c */
+extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+                           void *cpu_addr, dma_addr_t dma_addr, size_t size);
+extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size);
+#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s)
+#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s)
 #endif                          /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/c6x/include/asm/dma-mapping.h b/arch/c6x/include/asm/dma-mapping.h
index 3c694065030f..88bd0d899bdb 100644
--- a/arch/c6x/include/asm/dma-mapping.h
+++ b/arch/c6x/include/asm/dma-mapping.h
@@ -89,4 +89,19 @@ extern void dma_free_coherent(struct device *, size_t, void *, dma_addr_t);
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent((d), (s), (h), (f))
 #define dma_free_noncoherent(d, s, v, h)  dma_free_coherent((d), (s), (v), (h))
+/* Not supported for now */
+static inline int dma_mmap_coherent(struct device *dev,
+                                    struct vm_area_struct *vma, void *cpu_addr,
+                                    dma_addr_t dma_addr, size_t size)
+{
+        return -EINVAL;
+}
+static inline int dma_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size)
+{
+        return -EINVAL;
+}
 #endif  /* _ASM_C6X_DMA_MAPPING_H */
diff --git a/arch/cris/include/asm/dma-mapping.h b/arch/cris/include/asm/dma-mapping.h
index 8588b2ccf854..2f0f654f1b44 100644
--- a/arch/cris/include/asm/dma-mapping.h
+++ b/arch/cris/include/asm/dma-mapping.h
@@ -158,5 +158,15 @@ dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 {
 }
+/* drivers/base/dma-mapping.c */
+extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+                           void *cpu_addr, dma_addr_t dma_addr, size_t size);
+extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size);
+#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s)
+#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s)
 #endif
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index 9d262645f667..17df48fc8f44 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -3,7 +3,6 @@ config FRV
        default y
        select HAVE_IDE
        select HAVE_ARCH_TRACEHOOK
-        select HAVE_IRQ_WORK
        select HAVE_PERF_EVENTS
        select HAVE_UID16
        select HAVE_GENERIC_HARDIRQS
diff --git a/arch/frv/include/asm/dma-mapping.h b/arch/frv/include/asm/dma-mapping.h
index dfb811002c64..1746a2b8e6e7 100644
--- a/arch/frv/include/asm/dma-mapping.h
+++ b/arch/frv/include/asm/dma-mapping.h
@@ -132,4 +132,19 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
        flush_write_buffers();
 }
+/* Not supported for now */
+static inline int dma_mmap_coherent(struct device *dev,
+                                    struct vm_area_struct *vma, void *cpu_addr,
+                                    dma_addr_t dma_addr, size_t size)
+{
+        return -EINVAL;
+}
+static inline int dma_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size)
+{
+        return -EINVAL;
+}
 #endif  /* _ASM_DMA_MAPPING_H */
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 0744f7d7b1fd..e4decc6b8947 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -12,9 +12,7 @@ config HEXAGON
        # select ARCH_WANT_OPTIONAL_GPIOLIB
        # select ARCH_REQUIRE_GPIOLIB
        # select HAVE_CLK
-        # select IRQ_PER_CPU
        # select GENERIC_PENDING_IRQ if SMP
-        select HAVE_IRQ_WORK
        select GENERIC_ATOMIC64
        select HAVE_PERF_EVENTS
        select HAVE_GENERIC_HARDIRQS
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 3279646120e3..00c2e88f7755 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -29,7 +29,6 @@ config IA64
        select ARCH_DISCARD_MEMBLOCK
        select GENERIC_IRQ_PROBE
        select GENERIC_PENDING_IRQ if SMP
-        select IRQ_PER_CPU
        select GENERIC_IRQ_SHOW
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
diff --git a/arch/ia64/include/asm/cputime.h b/arch/ia64/include/asm/cputime.h
index 7fcf7f08ab06..e2d3f5baf265 100644
--- a/arch/ia64/include/asm/cputime.h
+++ b/arch/ia64/include/asm/cputime.h
@@ -11,99 +11,19 @@
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
- * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in nsec.
+ * If we have CONFIG_VIRT_CPU_ACCOUNTING_NATIVE, we measure cpu time in nsec.
 * Otherwise we measure cpu time in jiffies using the generic definitions.
 */
 #ifndef __IA64_CPUTIME_H
 #define __IA64_CPUTIME_H
-#ifndef CONFIG_VIRT_CPU_ACCOUNTING
+#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
-#include <asm-generic/cputime.h>
+# include <asm-generic/cputime.h>
 #else
+# include <asm/processor.h>
-#include <linux/time.h>
+# include <asm-generic/cputime_nsecs.h>
-#include <linux/jiffies.h>
-#include <asm/processor.h>
-typedef u64 __nocast cputime_t;
-typedef u64 __nocast cputime64_t;
-#define cputime_one_jiffy               jiffies_to_cputime(1)
-/*
- * Convert cputime <-> jiffies (HZ)
- */
-#define cputime_to_jiffies(__ct)        \
-        ((__force u64)(__ct) / (NSEC_PER_SEC / HZ))
-#define jiffies_to_cputime(__jif)       \
-        (__force cputime_t)((__jif) * (NSEC_PER_SEC / HZ))
-#define cputime64_to_jiffies64(__ct)    \
-        ((__force u64)(__ct) / (NSEC_PER_SEC / HZ))
-#define jiffies64_to_cputime64(__jif)   \
-        (__force cputime64_t)((__jif) * (NSEC_PER_SEC / HZ))
-/*
- * Convert cputime <-> microseconds
- */
-#define cputime_to_usecs(__ct)          \
-        ((__force u64)(__ct) / NSEC_PER_USEC)
-#define usecs_to_cputime(__usecs)       \
-        (__force cputime_t)((__usecs) * NSEC_PER_USEC)
-#define usecs_to_cputime64(__usecs)     \
-        (__force cputime64_t)((__usecs) * NSEC_PER_USEC)
-/*
- * Convert cputime <-> seconds
- */
-#define cputime_to_secs(__ct)           \
-        ((__force u64)(__ct) / NSEC_PER_SEC)
-#define secs_to_cputime(__secs)         \
-        (__force cputime_t)((__secs) * NSEC_PER_SEC)
-/*
- * Convert cputime <-> timespec (nsec)
- */
-static inline cputime_t timespec_to_cputime(const struct timespec *val)
-{
-        u64 ret = val->tv_sec * NSEC_PER_SEC + val->tv_nsec;
-        return (__force cputime_t) ret;
-}
-static inline void cputime_to_timespec(const cputime_t ct, struct timespec *val)
-{
-        val->tv_sec  = (__force u64) ct / NSEC_PER_SEC;
-        val->tv_nsec = (__force u64) ct % NSEC_PER_SEC;
-}
-/*
- * Convert cputime <-> timeval (msec)
- */
-static inline cputime_t timeval_to_cputime(struct timeval *val)
-{
-        u64 ret = val->tv_sec * NSEC_PER_SEC + val->tv_usec * NSEC_PER_USEC;
-        return (__force cputime_t) ret;
-}
-static inline void cputime_to_timeval(const cputime_t ct, struct timeval *val)
-{
-        val->tv_sec = (__force u64) ct / NSEC_PER_SEC;
-        val->tv_usec = ((__force u64) ct % NSEC_PER_SEC) / NSEC_PER_USEC;
-}
-/*
- * Convert cputime <-> clock (USER_HZ)
- */
-#define cputime_to_clock_t(__ct)        \
-        ((__force u64)(__ct) / (NSEC_PER_SEC / USER_HZ))
-#define clock_t_to_cputime(__x)         \
-        (__force cputime_t)((__x) * (NSEC_PER_SEC / USER_HZ))
-/*
- * Convert cputime64 to clock.
- */
-#define cputime64_to_clock_t(__ct)      \
-        cputime_to_clock_t((__force cputime_t)__ct)
 extern void arch_vtime_task_switch(struct task_struct *tsk);
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
 #endif /* __IA64_CPUTIME_H */
diff --git a/arch/ia64/include/asm/thread_info.h b/arch/ia64/include/asm/thread_info.h
index ff2ae4136584..020d655ed082 100644
--- a/arch/ia64/include/asm/thread_info.h
+++ b/arch/ia64/include/asm/thread_info.h
@@ -31,7 +31,7 @@ struct thread_info {
        mm_segment_t addr_limit;        /* user-level address space limit */
        int preempt_count;              /* 0=premptable, <0=BUG; will also serve as bh-counter */
        struct restart_block restart_block;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        __u64 ac_stamp;
        __u64 ac_leave;
        __u64 ac_stime;
@@ -69,7 +69,7 @@ struct thread_info {
 #define task_stack_page(tsk)    ((void *)(tsk))
 #define __HAVE_THREAD_FUNCTIONS
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 #define setup_thread_stack(p, org)                      \
        *task_thread_info(p) = *task_thread_info(org);  \
        task_thread_info(p)->ac_stime = 0;              \
diff --git a/arch/ia64/include/asm/xen/minstate.h b/arch/ia64/include/asm/xen/minstate.h
index c57fa910f2c9..00cf03e0cb82 100644
--- a/arch/ia64/include/asm/xen/minstate.h
+++ b/arch/ia64/include/asm/xen/minstate.h
@@ -1,5 +1,5 @@
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 /* read ar.itc in advance, and use it before leaving bank 0 */
 #define XEN_ACCOUNT_GET_STAMP           \
        MOV_FROM_ITC(pUStk, p6, r20, r2);
diff --git a/arch/ia64/kernel/asm-offsets.c b/arch/ia64/kernel/asm-offsets.c
index a48bd9a9927b..46c9e3007315 100644
--- a/arch/ia64/kernel/asm-offsets.c
+++ b/arch/ia64/kernel/asm-offsets.c
@@ -41,7 +41,7 @@ void foo(void)
        DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
        DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
        DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count));
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        DEFINE(TI_AC_STAMP, offsetof(struct thread_info, ac_stamp));
        DEFINE(TI_AC_LEAVE, offsetof(struct thread_info, ac_leave));
        DEFINE(TI_AC_STIME, offsetof(struct thread_info, ac_stime));
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index 6bfd8429ee0f..7a53530f22c2 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -724,7 +724,7 @@ GLOBAL_ENTRY(__paravirt_leave_syscall)
 #endif
 .global __paravirt_work_processed_syscall;
 __paravirt_work_processed_syscall:
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        adds r2=PT(LOADRS)+16,r12
        MOV_FROM_ITC(pUStk, p9, r22, r19)       // fetch time at leave
        adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
@@ -762,7 +762,7 @@ __paravirt_work_processed_syscall:
        ld8 r29=[r2],16         // M0|1 load cr.ipsr
        ld8 r28=[r3],16         // M0|1 load cr.iip
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 (pUStk) add r14=TI_AC_LEAVE+IA64_TASK_SIZE,r13
        ;;
        ld8 r30=[r2],16         // M0|1 load cr.ifs
@@ -793,7 +793,7 @@ __paravirt_work_processed_syscall:
        ld8.fill r1=[r3],16                     // M0|1 load r1
 (pUStk) mov r17=1                               // A
        ;;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 (pUStk) st1 [r15]=r17                           // M2|3
 #else
 (pUStk) st1 [r14]=r17                           // M2|3
@@ -813,7 +813,7 @@ __paravirt_work_processed_syscall:
        shr.u r18=r19,16                // I0|1 get byte size of existing "dirty" partition
        COVER                           // B    add current frame into dirty partition & set cr.ifs
        ;;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        mov r19=ar.bsp                  // M2   get new backing store pointer
        st8 [r14]=r22                   // M    save time at leave
        mov f10=f0                      // F    clear f10
@@ -948,7 +948,7 @@ GLOBAL_ENTRY(__paravirt_leave_kernel)
        adds r16=PT(CR_IPSR)+16,r12
        adds r17=PT(CR_IIP)+16,r12
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        .pred.rel.mutex pUStk,pKStk
        MOV_FROM_PSR(pKStk, r22, r29)   // M2 read PSR now that interrupts are disabled
        MOV_FROM_ITC(pUStk, p9, r22, r29)       // M  fetch time at leave
@@ -981,7 +981,7 @@ GLOBAL_ENTRY(__paravirt_leave_kernel)
        ;;
        ld8.fill r12=[r16],16
        ld8.fill r13=[r17],16
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 (pUStk) adds r3=TI_AC_LEAVE+IA64_TASK_SIZE,r18
 #else
 (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
@@ -989,7 +989,7 @@ GLOBAL_ENTRY(__paravirt_leave_kernel)
        ;;
        ld8 r20=[r16],16        // ar.fpsr
        ld8.fill r15=[r17],16
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18  // deferred
 #endif
        ;;
@@ -997,7 +997,7 @@ GLOBAL_ENTRY(__paravirt_leave_kernel)
        ld8.fill r2=[r17]
 (pUStk) mov r17=1
        ;;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        //  mmi_ :  ld8 st1 shr;;         mmi_ : st8 st1 shr;;
        //  mib  :  mov add br        ->  mib  : ld8 add br
        //  bbb_ :  br  nop cover;;       mbb_ : mov br  cover;;
diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S
index e662f178b990..c4cd45d97749 100644
--- a/arch/ia64/kernel/fsys.S
+++ b/arch/ia64/kernel/fsys.S
@@ -529,7 +529,7 @@ GLOBAL_ENTRY(paravirt_fsys_bubble_down)
        nop.i 0
        ;;
        mov ar.rsc=0                            // M2   set enforced lazy mode, pl 0, LE, loadrs=0
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        MOV_FROM_ITC(p0, p6, r30, r23)          // M    get cycle for accounting
 #else
        nop.m 0
@@ -555,7 +555,7 @@ GLOBAL_ENTRY(paravirt_fsys_bubble_down)
        cmp.ne pKStk,pUStk=r0,r0                // A    set pKStk <- 0, pUStk <- 1
        br.call.sptk.many b7=ia64_syscall_setup // B
        ;;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        // mov.m r30=ar.itc is called in advance
        add r16=TI_AC_STAMP+IA64_TASK_SIZE,r2
        add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r2
diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
index 4738ff7bd66a..9be4e497f3d3 100644
--- a/arch/ia64/kernel/head.S
+++ b/arch/ia64/kernel/head.S
@@ -1073,7 +1073,7 @@ END(ia64_native_sched_clock)
 sched_clock = ia64_native_sched_clock
 #endif
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 GLOBAL_ENTRY(cycle_to_cputime)
        alloc r16=ar.pfs,1,0,0,0
        addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
@@ -1091,7 +1091,7 @@ GLOBAL_ENTRY(cycle_to_cputime)
        shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
        br.ret.sptk.many rp
 END(cycle_to_cputime)
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 #ifdef CONFIG_IA64_BRL_EMU
diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
index fa25689fc453..689ffcaa284e 100644
--- a/arch/ia64/kernel/ivt.S
+++ b/arch/ia64/kernel/ivt.S
@@ -784,7 +784,7 @@ ENTRY(break_fault)
 (p8)    adds r28=16,r28                         // A    switch cr.iip to next bundle
 (p9)    adds r8=1,r8                            // A    increment ei to next slot
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        ;;
        mov b6=r30                              // I0   setup syscall handler branch reg early
 #else
@@ -801,7 +801,7 @@ ENTRY(break_fault)
        //
 ///////////////////////////////////////////////////////////////////////
        st1 [r16]=r0                            // M2|3 clear current->thread.on_ustack flag
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        MOV_FROM_ITC(p0, p14, r30, r18)         // M    get cycle for accounting
 #else
        mov b6=r30                              // I0   setup syscall handler branch reg early
@@ -817,7 +817,7 @@ ENTRY(break_fault)
        cmp.eq p14,p0=r9,r0                     // A    are syscalls being traced/audited?
        br.call.sptk.many b7=ia64_syscall_setup // B
 1:
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
        // mov.m r30=ar.itc is called in advance, and r13 is current
        add r16=TI_AC_STAMP+IA64_TASK_SIZE,r13  // A
        add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r13  // A
@@ -1043,7 +1043,7 @@ END(ia64_syscall_setup)
        DBG_FAULT(16)
        FAULT(16)
-#if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(__IA64_ASM_PARAVIRTUALIZED_NATIVE)
+#if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(__IA64_ASM_PARAVIRTUALIZED_NATIVE)
        /*
         * There is no particular reason for this code to be here, other than
         * that there happens to be space here that would go unused otherwise.
diff --git a/arch/ia64/kernel/minstate.h b/arch/ia64/kernel/minstate.h
index d56753a11636..cc82a7d744c9 100644
--- a/arch/ia64/kernel/minstate.h
+++ b/arch/ia64/kernel/minstate.h
@@ -4,7 +4,7 @@
 #include "entry.h"
 #include "paravirt_inst.h"
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 /* read ar.itc in advance, and use it before leaving bank 0 */
 #define ACCOUNT_GET_STAMP                               \
 (pUStk) mov.m r20=ar.itc;
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index 88a794536bc0..fbaac1afb844 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -77,7 +77,7 @@ static struct clocksource clocksource_itc = {
 };
 static struct clocksource *itc_clocksource;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 #include <linux/kernel_stat.h>
@@ -136,13 +136,14 @@ void vtime_account_system(struct task_struct *tsk)
        account_system_time(tsk, 0, delta, delta);
 }
+EXPORT_SYMBOL_GPL(vtime_account_system);
 void vtime_account_idle(struct task_struct *tsk)
 {
        account_idle_time(vtime_delta(tsk));
 }
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 static irqreturn_t
 timer_interrupt (int irq, void *dev_id)
diff --git a/arch/m68k/include/asm/dma-mapping.h b/arch/m68k/include/asm/dma-mapping.h
index 3e6b8445af6a..292805f0762e 100644
--- a/arch/m68k/include/asm/dma-mapping.h
+++ b/arch/m68k/include/asm/dma-mapping.h
@@ -115,4 +115,14 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t handle)
 #include <asm-generic/dma-mapping-broken.h>
 #endif
+/* drivers/base/dma-mapping.c */
+extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+                           void *cpu_addr, dma_addr_t dma_addr, size_t size);
+extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size);
+#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s)
+#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s)
 #endif  /* _M68K_DMA_MAPPING_H */
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index ae700f49e51d..b0768a657920 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -130,7 +130,6 @@ extern int handle_kernel_fault(struct pt_regs *regs);
 #define start_thread(_regs, _pc, _usp)                  \
 do {                                                    \
        (_regs)->pc = (_pc);                            \
-        ((struct switch_stack *)(_regs))[-1].a6 = 0;    \
        setframeformat(_regs);                          \
        if (current->mm)                                \
                (_regs)->d5 = current->mm->start_data;  \
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2ac626ab9d43..9becc44d9d7a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,7 +4,6 @@ config MIPS
        select HAVE_GENERIC_DMA_COHERENT
        select HAVE_IDE
        select HAVE_OPROFILE
-        select HAVE_IRQ_WORK
        select HAVE_PERF_EVENTS
        select PERF_USE_VMALLOC
        select HAVE_ARCH_KGDB
@@ -2161,7 +2160,6 @@ source "mm/Kconfig"
 config SMP
        bool "Multi-Processing support"
        depends on SYS_SUPPORTS_SMP
-        select IRQ_PER_CPU
        select USE_GENERIC_SMP_HELPERS
        help
          This enables support for systems with more than one CPU. If you have
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig
index d7af29f1fcf0..ba611927749b 100644
--- a/arch/mips/bcm47xx/Kconfig
+++ b/arch/mips/bcm47xx/Kconfig
@@ -8,8 +8,10 @@ config BCM47XX_SSB
        select SSB_DRIVER_EXTIF
        select SSB_EMBEDDED
        select SSB_B43_PCI_BRIDGE if PCI
+        select SSB_DRIVER_PCICORE if PCI
        select SSB_PCICORE_HOSTMODE if PCI
        select SSB_DRIVER_GPIO
+        select GPIOLIB
        default y
        help
         Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
@@ -25,6 +27,7 @@ config BCM47XX_BCMA
        select BCMA_HOST_PCI if PCI
        select BCMA_DRIVER_PCI_HOSTMODE if PCI
        select BCMA_DRIVER_GPIO
+        select GPIOLIB
        default y
        help
         Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 9f883bf76953..33b72144db31 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -30,6 +30,7 @@
 * measurement, and debugging facilities.
 */
+#include <linux/compiler.h>
 #include <linux/irqflags.h>
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-l2c.h>
@@ -285,22 +286,22 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter)
 */
 static void fault_in(uint64_t addr, int len)
 {
-        volatile char *ptr;
+        char *ptr;
-        volatile char dummy;
        /*
         * Adjust addr and length so we get all cache lines even for
         * small ranges spanning two cache lines.
         */
        len += addr & CVMX_CACHE_LINE_MASK;
        addr &= ~CVMX_CACHE_LINE_MASK;
-        ptr = (volatile char *)cvmx_phys_to_ptr(addr);
+        ptr = cvmx_phys_to_ptr(addr);
        /*
         * Invalidate L1 cache to make sure all loads result in data
         * being in L2.
         */
        CVMX_DCACHE_INVALIDATE;
        while (len > 0) {
-                dummy += *ptr;
+                ACCESS_ONCE(*ptr);
                len -= CVMX_CACHE_LINE_SIZE;
                ptr += CVMX_CACHE_LINE_SIZE;
        }
diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h
index e9bfc0813c72..7bfad0520e25 100644
--- a/arch/mips/include/asm/dsp.h
+++ b/arch/mips/include/asm/dsp.h
@@ -16,7 +16,7 @@
 #include <asm/mipsregs.h>
 #define DSP_DEFAULT     0x00000000
-#define DSP_MASK        0x3ff
+#define DSP_MASK        0x3f
 #define __enable_dsp_hazard()                                           \
 do {                                                                    \
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index ab84064283db..33c34adbecfa 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -353,6 +353,7 @@ union mips_instruction {
        struct u_format u_format;
        struct c_format c_format;
        struct r_format r_format;
+        struct p_format p_format;
        struct f_format f_format;
        struct ma_format ma_format;
        struct b_format b_format;
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
index edaa06d9d492..e410df4e1b3a 100644
--- a/arch/mips/include/asm/mach-pnx833x/war.h
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -21,4 +21,4 @@
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
+#endif /* __ASM_MIPS_MACH_PNX833X_WAR_H */
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index c63191055e69..013d5f781263 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -230,6 +230,7 @@ static inline void pud_clear(pud_t *pudp)
 #else
 #define pte_pfn(x)              ((unsigned long)((x).pte >> _PFN_SHIFT))
 #define pfn_pte(pfn, prot)      __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot)      __pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
 #endif
 #define __pgd_offset(address)   pgd_index(address)
diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild
index a1a0452ac185..77d4fb33f75a 100644
--- a/arch/mips/include/uapi/asm/Kbuild
+++ b/arch/mips/include/uapi/asm/Kbuild
@@ -3,6 +3,7 @@ include include/uapi/asm-generic/Kbuild.asm
 header-y += auxvec.h
 header-y += bitsperlong.h
+header-y += break.h
 header-y += byteorder.h
 header-y += cachectl.h
 header-y += errno.h
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/uapi/asm/break.h
index 9161e684cb4c..9161e684cb4c 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/uapi/asm/break.h
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 6a2d758dd8e9..83fa1460e294 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,6 +25,12 @@
 #define MCOUNT_OFFSET_INSNS 4
 #endif
+/* Arch override because MIPS doesn't need to run this from stop_machine() */
+void arch_ftrace_update_code(int command)
+{
+        ftrace_modify_all_code(command);
+}
 /*
 * Check if the address is in kernel space
 *
@@ -89,6 +95,24 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
        return 0;
 }
+#ifndef CONFIG_64BIT
+static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
+                                unsigned int new_code2)
+{
+        int faulted;
+        safe_store_code(new_code1, ip, faulted);
+        if (unlikely(faulted))
+                return -EFAULT;
+        ip += 4;
+        safe_store_code(new_code2, ip, faulted);
+        if (unlikely(faulted))
+                return -EFAULT;
+        flush_icache_range(ip, ip + 8); /* original ip + 12 */
+        return 0;
+}
+#endif
 /*
 * The details about the calling site of mcount on MIPS
 *
@@ -131,8 +155,18 @@ int ftrace_make_nop(struct module *mod,
         * needed.
         */
        new = in_kernel_space(ip) ? INSN_NOP : INSN_B_1F;
+#ifdef CONFIG_64BIT
        return ftrace_modify_code(ip, new);
+#else
+        /*
+         * On 32 bit MIPS platforms, gcc adds a stack adjust
+         * instruction in the delay slot after the branch to
+         * mcount and expects mcount to restore the sp on return.
+         * This is based on a legacy API and does nothing but
+         * waste instructions so it's being removed at runtime.
+         */
+        return ftrace_modify_code_2(ip, new, INSN_NOP);
+#endif
 }
 int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 4c968e7efb74..165867673357 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -46,9 +46,8 @@
        PTR_L   a5, PT_R9(sp)
        PTR_L   a6, PT_R10(sp)
        PTR_L   a7, PT_R11(sp)
-        PTR_ADDIU       sp, PT_SIZE
 #else
-        PTR_ADDIU       sp, (PT_SIZE + 8)
+        PTR_ADDIU       sp, PT_SIZE
 #endif
 .endm
@@ -69,7 +68,9 @@ NESTED(ftrace_caller, PT_SIZE, ra)
        .globl _mcount
 _mcount:
        b       ftrace_stub
-         nop
+        addiu sp,sp,8
+        /* When tracing is activated, it calls ftrace_caller+8 (aka here) */
        lw      t1, function_trace_stop
        bnez    t1, ftrace_stub
         nop
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index eec690af6581..147cec19621d 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -705,7 +705,7 @@ static int vpe_run(struct vpe * v)
                        printk(KERN_WARNING
                               "VPE loader: TC %d is already in use.\n",
-                               t->index);
+                               v->tc->index);
                        return -ENOEXEC;
                }
        } else {
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index f36acd1b3808..a7935bf0fecb 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -408,7 +408,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
 #endif
        /* tell oprofile which irq to use */
-        cp0_perfcount_irq = LTQ_PERF_IRQ;
+        cp0_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
        /*
         * if the timer irq is not one of the mips irqs we need to
diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
index dc81ca8dc0dd..288f7954988d 100644
--- a/arch/mips/lib/delay.c
+++ b/arch/mips/lib/delay.c
@@ -21,7 +21,7 @@ void __delay(unsigned long loops)
        "       .set    noreorder                               \n"
        "       .align  3                                       \n"
        "1:     bnez    %0, 1b                                  \n"
-#if __SIZEOF_LONG__ == 4
+#if BITS_PER_LONG == 32
        "       subu    %0, 1                                   \n"
 #else
        "       dsubu   %0, 1                                   \n"
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 7657fd21cd3f..cacfd31e8ec9 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -190,9 +190,3 @@ void __iounmap(const volatile void __iomem *addr)
 EXPORT_SYMBOL(__ioremap);
 EXPORT_SYMBOL(__iounmap);
-int __virt_addr_valid(const volatile void *kaddr)
-{
-        return pfn_valid(PFN_DOWN(virt_to_phys(kaddr)));
-}
-EXPORT_SYMBOL_GPL(__virt_addr_valid);
diff --git a/arch/mips/mm/mmap.c b/arch/mips/mm/mmap.c
index d9be7540a6be..7e5fe2790d8a 100644
--- a/arch/mips/mm/mmap.c
+++ b/arch/mips/mm/mmap.c
@@ -192,3 +192,9 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
        return ret;
 }
+int __virt_addr_valid(const volatile void *kaddr)
+{
+        return pfn_valid(PFN_DOWN(virt_to_phys(kaddr)));
+}
+EXPORT_SYMBOL_GPL(__virt_addr_valid);
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index 4e7f49d3d5a8..c5ce6992ac4c 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -193,8 +193,11 @@ static void nlm_init_node(void)
 void __init prom_init(void)
 {
-        int i, *argv, *envp;            /* passed as 32 bit ptrs */
+        int *argv, *envp;               /* passed as 32 bit ptrs */
        struct psb_info *prom_infop;
+#ifdef CONFIG_SMP
+        int i;
+#endif
        /* truncate to 32 bit and sign extend all args */
        argv = (int *)(long)(int)fw_arg1;
diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c
index 1552522b8718..6eaa4f2d0e38 100644
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -24,7 +24,7 @@
 #include <asm/mach-ath79/pci.h>
 #define AR71XX_PCI_MEM_BASE     0x10000000
-#define AR71XX_PCI_MEM_SIZE     0x08000000
+#define AR71XX_PCI_MEM_SIZE     0x07000000
 #define AR71XX_PCI_WIN0_OFFS            0x10000000
 #define AR71XX_PCI_WIN1_OFFS            0x11000000
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index 86d77a666458..c11c75be2d7e 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -21,7 +21,7 @@
 #define AR724X_PCI_CTRL_SIZE    0x100
 #define AR724X_PCI_MEM_BASE     0x10000000
-#define AR724X_PCI_MEM_SIZE     0x08000000
+#define AR724X_PCI_MEM_SIZE     0x04000000
 #define AR724X_PCI_REG_RESET            0x18
 #define AR724X_PCI_REG_INT_STATUS       0x4c
diff --git a/arch/mn10300/include/asm/dma-mapping.h b/arch/mn10300/include/asm/dma-mapping.h
index c1be4397b1ed..a18abfc558eb 100644
--- a/arch/mn10300/include/asm/dma-mapping.h
+++ b/arch/mn10300/include/asm/dma-mapping.h
@@ -168,4 +168,19 @@ void dma_cache_sync(void *vaddr, size_t size,
        mn10300_dcache_flush_inv();
 }
+/* Not supported for now */
+static inline int dma_mmap_coherent(struct device *dev,
+                                    struct vm_area_struct *vma, void *cpu_addr,
+                                    dma_addr_t dma_addr, size_t size)
+{
+        return -EINVAL;
+}
+static inline int dma_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size)
+{
+        return -EINVAL;
+}
 #endif
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index b77feffbadea..a32e34ecda9e 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -9,14 +9,12 @@ config PARISC
        select RTC_DRV_GENERIC
        select INIT_ALL_POSSIBLE
        select BUG
-        select HAVE_IRQ_WORK
        select HAVE_PERF_EVENTS
        select GENERIC_ATOMIC64 if !64BIT
        select HAVE_GENERIC_HARDIRQS
        select BROKEN_RODATA
        select GENERIC_IRQ_PROBE
        select GENERIC_PCI_IOMAP
-        select IRQ_PER_CPU
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
        select GENERIC_SMP_IDLE_THREAD
        select GENERIC_STRNCPY_FROM_USER
diff --git a/arch/parisc/include/asm/dma-mapping.h b/arch/parisc/include/asm/dma-mapping.h
index 467bbd510eac..106b395688e1 100644
--- a/arch/parisc/include/asm/dma-mapping.h
+++ b/arch/parisc/include/asm/dma-mapping.h
@@ -238,4 +238,19 @@ void * sba_get_iommu(struct parisc_device *dev);
 /* At the moment, we panic on error for IOMMU resource exaustion */
 #define dma_mapping_error(dev, x)       0
+/* This API cannot be supported on PA-RISC */
+static inline int dma_mmap_coherent(struct device *dev,
+                                    struct vm_area_struct *vma, void *cpu_addr,
+                                    dma_addr_t dma_addr, size_t size)
+{
+        return -EINVAL;
+}
+static inline int dma_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size)
+{
+        return -EINVAL;
+}
 #endif
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 17903f1f356b..561ccca7b1a7 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -118,14 +118,12 @@ config PPC
        select HAVE_SYSCALL_WRAPPERS if PPC64
        select GENERIC_ATOMIC64 if PPC32
        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
-        select HAVE_IRQ_WORK
        select HAVE_PERF_EVENTS
        select HAVE_REGS_AND_STACK_ACCESS_API
        select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
        select HAVE_GENERIC_HARDIRQS
        select ARCH_WANT_IPC_PARSE_VERSION
        select SPARSE_IRQ
-        select IRQ_PER_CPU
        select IRQ_DOMAIN
        select GENERIC_IRQ_SHOW
        select GENERIC_IRQ_SHOW_LEVEL
diff --git a/arch/powerpc/configs/chroma_defconfig b/arch/powerpc/configs/chroma_defconfig
index 29bb11ec6c64..4f35fc462385 100644
--- a/arch/powerpc/configs/chroma_defconfig
+++ b/arch/powerpc/configs/chroma_defconfig
@@ -1,6 +1,6 @@
 CONFIG_PPC64=y
 CONFIG_PPC_BOOK3E_64=y
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
+# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
 CONFIG_SMP=y
 CONFIG_NR_CPUS=256
 CONFIG_EXPERIMENTAL=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 88fa5c46f66f..f7df8362911f 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -1,6 +1,6 @@
 CONFIG_PPC64=y
 CONFIG_PPC_BOOK3E_64=y
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
+# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_EXPERIMENTAL=y
diff --git a/arch/powerpc/configs/pasemi_defconfig b/arch/powerpc/configs/pasemi_defconfig
index 840a2c2d0430..bcedeea0df89 100644
--- a/arch/powerpc/configs/pasemi_defconfig
+++ b/arch/powerpc/configs/pasemi_defconfig
@@ -1,6 +1,6 @@
 CONFIG_PPC64=y
 CONFIG_ALTIVEC=y
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
+# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_EXPERIMENTAL=y
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index 483733bd06d4..607559ab271f 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -8,7 +8,7 @@
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
- * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in
+ * If we have CONFIG_VIRT_CPU_ACCOUNTING_NATIVE, we measure cpu time in
 * the same units as the timebase.  Otherwise we measure cpu time
 * in jiffies using the generic definitions.
 */
@@ -16,7 +16,7 @@
 #ifndef __POWERPC_CPUTIME_H
 #define __POWERPC_CPUTIME_H
-#ifndef CONFIG_VIRT_CPU_ACCOUNTING
+#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 #include <asm-generic/cputime.h>
 #ifdef __KERNEL__
 static inline void setup_cputime_one_jiffy(void) { }
@@ -231,5 +231,5 @@ static inline cputime_t clock_t_to_cputime(const unsigned long clk)
 static inline void arch_vtime_task_switch(struct task_struct *tsk) { }
 #endif /* __KERNEL__ */
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 #endif /* __POWERPC_CPUTIME_H */
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 531fe0c3108f..b1e7f2af1016 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -145,7 +145,7 @@ struct dtl_entry {
 extern struct kmem_cache *dtl_cache;
 /*
- * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
+ * When CONFIG_VIRT_CPU_ACCOUNTING_NATIVE = y, the cpu accounting code controls
 * reading from the dispatch trace log.  If other code wants to consume
 * DTL entries, it can set this pointer to a function that will get
 * called once for each DTL entry that gets processed.
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 9710be3a2d17..136bba62efa4 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -11,6 +11,7 @@
 #include <linux/types.h>
 #include <asm/hw_irq.h>
+#include <linux/device.h>
 #define MAX_HWEVENTS            8
 #define MAX_EVENT_ALTERNATIVES  8
@@ -35,6 +36,7 @@ struct power_pmu {
        void            (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
        int             (*limited_pmc_event)(u64 event_id);
        u32             flags;
+        const struct attribute_group    **attr_groups;
        int             n_generic;
        int             *generic_events;
        int             (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
@@ -109,3 +111,27 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 * If an event_id is not subject to the constraint expressed by a particular
 * field, then it will have 0 in both the mask and value for that field.
 */
+extern ssize_t power_events_sysfs_show(struct device *dev,
+                                struct device_attribute *attr, char *page);
+/*
+ * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix.
+ *
+ * Having a suffix allows us to have aliases in sysfs - eg: the generic
+ * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and
+ * 'PM_CYC' where the latter is the name by which the event is known in
+ * POWER CPU specification.
+ */
+#define EVENT_VAR(_id, _suffix)         event_attr_##_id##_suffix
+#define EVENT_PTR(_id, _suffix)         &EVENT_VAR(_id, _suffix).attr.attr
+#define EVENT_ATTR(_name, _id, _suffix)                                 \
+        PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_PM_##_id,    \
+                        power_events_sysfs_show)
+#define GENERIC_EVENT_ATTR(_name, _id)  EVENT_ATTR(_name, _id, _g)
+#define GENERIC_EVENT_PTR(_id)          EVENT_PTR(_id, _g)
+#define POWER_EVENT_ATTR(_name, _id)    EVENT_ATTR(PM_##_name, _id, _p)
+#define POWER_EVENT_PTR(_id)            EVENT_PTR(_id, _p)
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index ea2a86e8ff95..2d0e1f5d8339 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -24,7 +24,7 @@
 * user_time and system_time fields in the paca.
 */
-#ifndef CONFIG_VIRT_CPU_ACCOUNTING
+#ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
 #define ACCOUNT_STOLEN_TIME
@@ -70,7 +70,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 #endif /* CONFIG_PPC_SPLPAR */
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 /*
 * Macros for storing registers into and loading registers from
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index d22e73e4618b..e514de57a125 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -439,6 +439,8 @@ ret_from_fork:
 ret_from_kernel_thread:
        REST_NVGPRS(r1)
        bl      schedule_tail
+        li      r3,0
+        stw     r3,0(r1)
        mtlr    r14
        mr      r3,r15
        PPC440EP_ERR42
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index b310a0573625..ac057013f9fd 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -94,7 +94,7 @@ system_call_common:
        addi    r9,r1,STACK_FRAME_OVERHEAD
        ld      r11,exception_marker@toc(r2)
        std     r11,-16(r9)             /* "regshere" marker */
-#if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR)
+#if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
 BEGIN_FW_FTR_SECTION
        beq     33f
        /* if from user, see if there are any DTL entries to process */
@@ -110,7 +110,7 @@ BEGIN_FW_FTR_SECTION
        addi    r9,r1,STACK_FRAME_OVERHEAD
 33:
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
        /*
         * A syscall should always be called with interrupts enabled
@@ -664,6 +664,19 @@ resume_kernel:
        ld      r4,TI_FLAGS(r9)
        andi.   r0,r4,_TIF_NEED_RESCHED
        bne     1b
+        /*
+         * arch_local_irq_restore() from preempt_schedule_irq above may
+         * enable hard interrupt but we really should disable interrupts
+         * when we return from the interrupt, and so that we don't get
+         * interrupted after loading SRR0/1.
+         */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  0
+#else
+        ld      r10,PACAKMSR(r13) /* Get kernel MSR without EE */
+        mtmsrd  r10,1             /* Update machine state */
+#endif /* CONFIG_PPC_BOOK3E */
 #endif /* CONFIG_PREEMPT */
        .globl  fast_exc_return_irq
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index c470a40b29f5..a7bc7521c064 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -154,12 +154,12 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs)
 static int kgdb_singlestep(struct pt_regs *regs)
 {
        struct thread_info *thread_info, *exception_thread_info;
-        struct thread_info *backup_current_thread_info = \
+        struct thread_info *backup_current_thread_info;
-                (struct thread_info *)kmalloc(sizeof(struct thread_info), GFP_KERNEL);
        if (user_mode(regs))
                return 0;
+        backup_current_thread_info = (struct thread_info *)kmalloc(sizeof(struct thread_info), GFP_KERNEL);
        /*
         * On Book E and perhaps other processors, singlestep is handled on
         * the critical exception stack.  This causes current_thread_info()
@@ -185,6 +185,7 @@ static int kgdb_singlestep(struct pt_regs *regs)
                /* Restore current_thread_info lastly. */
                memcpy(exception_thread_info, backup_current_thread_info, sizeof *thread_info);
+        kfree(backup_current_thread_info);
        return 1;
 }
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 6f6b1cccc916..f77fa22754bc 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -143,7 +143,7 @@ EXPORT_SYMBOL_GPL(ppc_proc_freq);
 unsigned long ppc_tb_freq;
 EXPORT_SYMBOL_GPL(ppc_tb_freq);
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 /*
 * Factors for converting from cputime_t (timebase ticks) to
 * jiffies, microseconds, seconds, and clock_t (1/USER_HZ seconds).
@@ -347,6 +347,7 @@ void vtime_account_system(struct task_struct *tsk)
        if (stolen)
                account_steal_time(stolen);
 }
+EXPORT_SYMBOL_GPL(vtime_account_system);
 void vtime_account_idle(struct task_struct *tsk)
 {
@@ -377,7 +378,7 @@ void vtime_account_user(struct task_struct *tsk)
        account_user_time(tsk, utime, utimescaled);
 }
-#else /* ! CONFIG_VIRT_CPU_ACCOUNTING */
+#else /* ! CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 #define calc_cputime_factors()
 #endif
@@ -494,10 +495,15 @@ void timer_interrupt(struct pt_regs * regs)
        set_dec(DECREMENTER_MAX);
        /* Some implementations of hotplug will get timer interrupts while
-         * offline, just ignore these
+         * offline, just ignore these and we also need to set
+         * decrementers_next_tb as MAX to make sure __check_irq_replay
+         * don't replay timer interrupt when return, otherwise we'll trap
+         * here infinitely :(
         */
-        if (!cpu_online(smp_processor_id()))
+        if (!cpu_online(smp_processor_id())) {
+                *next_tb = ~(u64)0;
                return;
+        }
        /* Conditionally hard-enable interrupts now that the DEC has been
         * bumped to its maximum value
@@ -663,7 +669,7 @@ int update_persistent_clock(struct timespec now)
        struct rtc_time tm;
        if (!ppc_md.set_rtc_time)
-                return 0;
+                return -ENODEV;
        to_tm(now.tv_sec + 1 + timezone_offset, &tm);
        tm.tm_year -= 1900;
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 56585086413a..7443481a315c 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -115,11 +115,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        sldi    r29,r5,SID_SHIFT - VPN_SHIFT
        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
        or      r29,r28,r29
+        /*
-        /* Calculate hash value for primary slot and store it in r28 */
+         * Calculate hash value for primary slot and store it in r28
-        rldicl  r5,r5,0,25              /* vsid & 0x0000007fffffffff */
+         * r3 = va, r5 = vsid
-        rldicl  r0,r3,64-12,48          /* (ea >> 12) & 0xffff */
+         * r0 = (va >> 12) & ((1ul << (28 - 12)) -1)
-        xor     r28,r5,r0
+         */
+        rldicl  r0,r3,64-12,48
+        xor     r28,r5,r0               /* hash */
        b       4f
 3:      /* Calc vpn and put it in r29 */
@@ -130,11 +132,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        /*
         * calculate hash value for primary slot and
         * store it in r28 for 1T segment
+         * r3 = va, r5 = vsid
         */
-        rldic   r28,r5,25,25            /* (vsid << 25) & 0x7fffffffff */
+        sldi    r28,r5,25               /* vsid << 25 */
-        clrldi  r5,r5,40                /* vsid & 0xffffff */
+        /* r0 =  (va >> 12) & ((1ul << (40 - 12)) -1) */
-        rldicl  r0,r3,64-12,36          /* (ea >> 12) & 0xfffffff */
+        rldicl  r0,r3,64-12,36
-        xor     r28,r28,r5
+        xor     r28,r28,r5              /* vsid ^ ( vsid << 25) */
        xor     r28,r28,r0              /* hash */
        /* Convert linux PTE bits into HW equivalents */
@@ -407,11 +410,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         */
        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
        or      r29,r28,r29
+        /*
-        /* Calculate hash value for primary slot and store it in r28 */
+         * Calculate hash value for primary slot and store it in r28
-        rldicl  r5,r5,0,25              /* vsid & 0x0000007fffffffff */
+         * r3 = va, r5 = vsid
-        rldicl  r0,r3,64-12,48          /* (ea >> 12) & 0xffff */
+         * r0 = (va >> 12) & ((1ul << (28 - 12)) -1)
-        xor     r28,r5,r0
+         */
+        rldicl  r0,r3,64-12,48
+        xor     r28,r5,r0               /* hash */
        b       4f
 3:      /* Calc vpn and put it in r29 */
@@ -426,11 +431,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        /*
         * Calculate hash value for primary slot and
         * store it in r28  for 1T segment
+         * r3 = va, r5 = vsid
         */
-        rldic   r28,r5,25,25            /* (vsid << 25) & 0x7fffffffff */
+        sldi    r28,r5,25               /* vsid << 25 */
-        clrldi  r5,r5,40                /* vsid & 0xffffff */
+        /* r0 = (va >> 12) & ((1ul << (40 - 12)) -1) */
-        rldicl  r0,r3,64-12,36          /* (ea >> 12) & 0xfffffff */
+        rldicl  r0,r3,64-12,36
-        xor     r28,r28,r5
+        xor     r28,r28,r5              /* vsid ^ ( vsid << 25) */
        xor     r28,r28,r0              /* hash */
        /* Convert linux PTE bits into HW equivalents */
@@ -752,25 +758,27 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
        or      r29,r28,r29
-        /* Calculate hash value for primary slot and store it in r28 */
+        /* Calculate hash value for primary slot and store it in r28
-        rldicl  r5,r5,0,25              /* vsid & 0x0000007fffffffff */
+         * r3 = va, r5 = vsid
-        rldicl  r0,r3,64-16,52          /* (ea >> 16) & 0xfff */
+         * r0 = (va >> 16) & ((1ul << (28 - 16)) -1)
-        xor     r28,r5,r0
+         */
+        rldicl  r0,r3,64-16,52
+        xor     r28,r5,r0               /* hash */
        b       4f
 3:      /* Calc vpn and put it in r29 */
        sldi    r29,r5,SID_SHIFT_1T - VPN_SHIFT
        rldicl  r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
        or      r29,r28,r29
        /*
         * calculate hash value for primary slot and
         * store it in r28 for 1T segment
+         * r3 = va, r5 = vsid
         */
-        rldic   r28,r5,25,25            /* (vsid << 25) & 0x7fffffffff */
+        sldi    r28,r5,25               /* vsid << 25 */
-        clrldi  r5,r5,40                /* vsid & 0xffffff */
+        /* r0 = (va >> 16) & ((1ul << (40 - 16)) -1) */
-        rldicl  r0,r3,64-16,40          /* (ea >> 16) & 0xffffff */
+        rldicl  r0,r3,64-16,40
-        xor     r28,r28,r5
+        xor     r28,r28,r5              /* vsid ^ ( vsid << 25) */
        xor     r28,r28,r0              /* hash */
        /* Convert linux PTE bits into HW equivalents */
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index 315f9495e9b2..f444b94935f5 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -52,7 +52,7 @@ static int power7_marked_instr_event(u64 mmcr1)
        for (pmc = 0; pmc < 4; pmc++) {
                psel = mmcr1 & (OPROFILE_PM_PMCSEL_MSK
                                << (OPROFILE_MAX_PMC_NUM - pmc)
-                                * OPROFILE_MAX_PMC_NUM);
+                                * OPROFILE_PMSEL_FIELD_WIDTH);
                psel = (psel >> ((OPROFILE_MAX_PMC_NUM - pmc)
                                 * OPROFILE_PMSEL_FIELD_WIDTH)) & ~1ULL;
                unit = mmcr1 & (OPROFILE_PM_UNIT_MSK
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index aa2465e21f1a..fa476d50791f 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1305,6 +1305,16 @@ static int power_pmu_event_idx(struct perf_event *event)
        return event->hw.idx;
 }
+ssize_t power_events_sysfs_show(struct device *dev,
+                                struct device_attribute *attr, char *page)
+{
+        struct perf_pmu_events_attr *pmu_attr;
+        pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
+        return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
+}
 struct pmu power_pmu = {
        .pmu_enable     = power_pmu_enable,
        .pmu_disable    = power_pmu_disable,
@@ -1537,6 +1547,8 @@ int __cpuinit register_power_pmu(struct power_pmu *pmu)
        pr_info("%s performance monitor hardware support registered\n",
                pmu->name);
+        power_pmu.attr_groups = ppmu->attr_groups;
 #ifdef MSR_HV
        /*
         * Use FCHV to ignore kernel events if MSR.HV is set.
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 2ee01e38d5e2..b554879bd31e 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -51,6 +51,18 @@
 #define MMCR1_PMCSEL_MSK        0xff
 /*
+ * Power7 event codes.
+ */
+#define PME_PM_CYC                      0x1e
+#define PME_PM_GCT_NOSLOT_CYC           0x100f8
+#define PME_PM_CMPLU_STALL              0x4000a
+#define PME_PM_INST_CMPL                0x2
+#define PME_PM_LD_REF_L1                0xc880
+#define PME_PM_LD_MISS_L1               0x400f0
+#define PME_PM_BRU_FIN                  0x10068
+#define PME_PM_BRU_MPRED                0x400f6
+/*
 * Layout of constraint bits:
 * 6666555555555544444444443333333333222222222211111111110000000000
 * 3210987654321098765432109876543210987654321098765432109876543210
@@ -307,14 +319,14 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 }
 static int power7_generic_events[] = {
-        [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
+        [PERF_COUNT_HW_CPU_CYCLES] =                    PME_PM_CYC,
-        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PME_PM_GCT_NOSLOT_CYC,
-        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a,  /* CMPLU_STALL */
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PME_PM_CMPLU_STALL,
-        [PERF_COUNT_HW_INSTRUCTIONS] = 2,
+        [PERF_COUNT_HW_INSTRUCTIONS] =                  PME_PM_INST_CMPL,
-        [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880,      /* LD_REF_L1_LSU*/
+        [PERF_COUNT_HW_CACHE_REFERENCES] =              PME_PM_LD_REF_L1,
-        [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0,         /* LD_MISS_L1   */
+        [PERF_COUNT_HW_CACHE_MISSES] =                  PME_PM_LD_MISS_L1,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068,  /* BRU_FIN      */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PME_PM_BRU_FIN,
-        [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6,        /* BR_MPRED     */
+        [PERF_COUNT_HW_BRANCH_MISSES] =                 PME_PM_BRU_MPRED,
 };
 #define C(x)    PERF_COUNT_HW_CACHE_##x
@@ -362,6 +374,57 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        },
 };
+GENERIC_EVENT_ATTR(cpu-cycles,                  CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-frontend,     GCT_NOSLOT_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-backend,      CMPLU_STALL);
+GENERIC_EVENT_ATTR(instructions,                INST_CMPL);
+GENERIC_EVENT_ATTR(cache-references,            LD_REF_L1);
+GENERIC_EVENT_ATTR(cache-misses,                LD_MISS_L1);
+GENERIC_EVENT_ATTR(branch-instructions,         BRU_FIN);
+GENERIC_EVENT_ATTR(branch-misses,               BRU_MPRED);
+POWER_EVENT_ATTR(CYC,                           CYC);
+POWER_EVENT_ATTR(GCT_NOSLOT_CYC,                GCT_NOSLOT_CYC);
+POWER_EVENT_ATTR(CMPLU_STALL,                   CMPLU_STALL);
+POWER_EVENT_ATTR(INST_CMPL,                     INST_CMPL);
+POWER_EVENT_ATTR(LD_REF_L1,                     LD_REF_L1);
+POWER_EVENT_ATTR(LD_MISS_L1,                    LD_MISS_L1);
+POWER_EVENT_ATTR(BRU_FIN,                       BRU_FIN)
+POWER_EVENT_ATTR(BRU_MPRED,                     BRU_MPRED);
+static struct attribute *power7_events_attr[] = {
+        GENERIC_EVENT_PTR(CYC),
+        GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
+        GENERIC_EVENT_PTR(CMPLU_STALL),
+        GENERIC_EVENT_PTR(INST_CMPL),
+        GENERIC_EVENT_PTR(LD_REF_L1),
+        GENERIC_EVENT_PTR(LD_MISS_L1),
+        GENERIC_EVENT_PTR(BRU_FIN),
+        GENERIC_EVENT_PTR(BRU_MPRED),
+        POWER_EVENT_PTR(CYC),
+        POWER_EVENT_PTR(GCT_NOSLOT_CYC),
+        POWER_EVENT_PTR(CMPLU_STALL),
+        POWER_EVENT_PTR(INST_CMPL),
+        POWER_EVENT_PTR(LD_REF_L1),
+        POWER_EVENT_PTR(LD_MISS_L1),
+        POWER_EVENT_PTR(BRU_FIN),
+        POWER_EVENT_PTR(BRU_MPRED),
+        NULL
+};
+static struct attribute_group power7_pmu_events_group = {
+        .name = "events",
+        .attrs = power7_events_attr,
+};
+static const struct attribute_group *power7_pmu_attr_groups[] = {
+        &power7_pmu_events_group,
+        NULL,
+};
 static struct power_pmu power7_pmu = {
        .name                   = "POWER7",
        .n_counter              = 6,
@@ -373,6 +436,7 @@ static struct power_pmu power7_pmu = {
        .get_alternatives       = power7_get_alternatives,
        .disable_pmc            = power7_disable_pmc,
        .flags                  = PPMU_ALT_SIPR,
+        .attr_groups            = power7_pmu_attr_groups,
        .n_generic              = ARRAY_SIZE(power7_generic_events),
        .generic_events         = power7_generic_events,
        .cache_events           = &power7_cache_events,
diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c
index 25db92a8e1cf..49318385d4fa 100644
--- a/arch/powerpc/platforms/cell/spufs/sched.c
+++ b/arch/powerpc/platforms/cell/spufs/sched.c
@@ -24,6 +24,7 @@
 #include <linux/errno.h>
 #include <linux/sched.h>
+#include <linux/sched/rt.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/slab.h>
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
index 95d00173029f..890f30e70f98 100644
--- a/arch/powerpc/platforms/pasemi/cpufreq.c
+++ b/arch/powerpc/platforms/pasemi/cpufreq.c
@@ -236,6 +236,13 @@ out:
 static int pas_cpufreq_cpu_exit(struct cpufreq_policy *policy)
 {
+        /*
+         * We don't support CPU hotplug. Don't unmap after the system
+         * has already made it to a running state.
+         */
+        if (system_state != SYSTEM_BOOTING)
+                return 0;
        if (sdcasr_mapbase)
                iounmap(sdcasr_mapbase);
        if (sdcpwr_mapbase)
diff --git a/arch/powerpc/platforms/pseries/dtl.c b/arch/powerpc/platforms/pseries/dtl.c
index a7648543c59e..0cc0ac07a55d 100644
--- a/arch/powerpc/platforms/pseries/dtl.c
+++ b/arch/powerpc/platforms/pseries/dtl.c
@@ -57,7 +57,7 @@ static u8 dtl_event_mask = 0x7;
 */
 static int dtl_buf_entries = N_DISPATCH_LOG;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 struct dtl_ring {
        u64     write_index;
        struct dtl_entry *write_ptr;
@@ -142,7 +142,7 @@ static u64 dtl_current_index(struct dtl *dtl)
        return per_cpu(dtl_rings, dtl->cpu).write_index;
 }
-#else /* CONFIG_VIRT_CPU_ACCOUNTING */
+#else /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 static int dtl_start(struct dtl *dtl)
 {
@@ -188,7 +188,7 @@ static u64 dtl_current_index(struct dtl *dtl)
 {
        return lppaca_of(dtl->cpu).dtl_idx;
 }
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 static int dtl_enable(struct dtl *dtl)
 {
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index ca55882465d6..527e12c9573b 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -281,7 +281,7 @@ static struct notifier_block pci_dn_reconfig_nb = {
 struct kmem_cache *dtl_cache;
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
 /*
 * Allocate space for the dispatch trace log for all possible cpus
 * and register the buffers with the hypervisor.  This is used for
@@ -332,12 +332,12 @@ static int alloc_dispatch_logs(void)
        return 0;
 }
-#else /* !CONFIG_VIRT_CPU_ACCOUNTING */
+#else /* !CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 static inline int alloc_dispatch_logs(void)
 {
        return 0;
 }
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
+#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
 static int alloc_dispatch_log_kmem_cache(void)
 {
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index b5ea38c25647..c15ba7d1be64 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -78,7 +78,6 @@ config S390
        select HAVE_KVM if 64BIT
        select HAVE_ARCH_TRACEHOOK
        select INIT_ALL_POSSIBLE
-        select HAVE_IRQ_WORK
        select HAVE_PERF_EVENTS
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
        select HAVE_DEBUG_KMEMLEAK
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index c1d7930a82f4..098adbb62660 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -1365,6 +1365,18 @@ static inline void pmdp_invalidate(struct vm_area_struct *vma,
        __pmd_idte(address, pmdp);
 }
+#define __HAVE_ARCH_PMDP_SET_WRPROTECT
+static inline void pmdp_set_wrprotect(struct mm_struct *mm,
+                                      unsigned long address, pmd_t *pmdp)
+{
+        pmd_t pmd = *pmdp;
+        if (pmd_write(pmd)) {
+                __pmd_idte(address, pmdp);
+                set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
+        }
+}
 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
 {
        pmd_t __pmd;
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index a5f4f5a1d24b..0aa98db8a80d 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -120,6 +120,9 @@ static int s390_next_ktime(ktime_t expires,
        nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires));
        do_div(nsecs, 125);
        S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9);
+        /* Program the maximum value if we have an overflow (== year 2042) */
+        if (unlikely(S390_lowcore.clock_comparator < sched_clock_base_cc))
+                S390_lowcore.clock_comparator = -1ULL;
        set_clock_comparator(S390_lowcore.clock_comparator);
        return 0;
 }
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index e84b8b68444a..ce9cc5aa2033 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -127,7 +127,7 @@ void vtime_account_user(struct task_struct *tsk)
 * Update process times based on virtual cpu times stored by entry.S
 * to the lowcore fields user_timer, system_timer & steal_clock.
 */
-void vtime_account(struct task_struct *tsk)
+void vtime_account_irq_enter(struct task_struct *tsk)
 {
        struct thread_info *ti = task_thread_info(tsk);
        u64 timer, system;
@@ -145,10 +145,10 @@ void vtime_account(struct task_struct *tsk)
        virt_timer_forward(system);
 }
-EXPORT_SYMBOL_GPL(vtime_account);
+EXPORT_SYMBOL_GPL(vtime_account_irq_enter);
 void vtime_account_system(struct task_struct *tsk)
-__attribute__((alias("vtime_account")));
+__attribute__((alias("vtime_account_irq_enter")));
 EXPORT_SYMBOL_GPL(vtime_account_system);
 void __kprobes vtime_stop_cpu(void)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index babc2b826c5c..9c833c585871 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -11,7 +11,6 @@ config SUPERH
        select HAVE_ARCH_TRACEHOOK
        select HAVE_DMA_API_DEBUG
        select HAVE_DMA_ATTRS
-        select HAVE_IRQ_WORK
        select HAVE_PERF_EVENTS
        select HAVE_DEBUG_BUGVERBOSE
        select ARCH_HAVE_CUSTOM_GPIO_H
@@ -91,9 +90,6 @@ config GENERIC_CSUM
 config GENERIC_HWEIGHT
        def_bool y
-config IRQ_PER_CPU
-        def_bool y
 config GENERIC_GPIO
        def_bool n
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 9f2edb5c5551..9bff3db17c8c 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -23,7 +23,6 @@ config SPARC
        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
        select RTC_CLASS
        select RTC_DRV_M48T59
-        select HAVE_IRQ_WORK
        select HAVE_DMA_ATTRS
        select HAVE_DMA_API_DEBUG
        select HAVE_ARCH_JUMP_LABEL
@@ -61,6 +60,7 @@ config SPARC64
        select HAVE_MEMBLOCK
        select HAVE_MEMBLOCK_NODE_MAP
        select HAVE_SYSCALL_WRAPPERS
+        select HAVE_ARCH_TRANSPARENT_HUGEPAGE
        select HAVE_DYNAMIC_FTRACE
        select HAVE_FTRACE_MCOUNT_RECORD
        select HAVE_SYSCALL_TRACEPOINTS
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index 7870be0f5adc..08fcce90316b 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -71,7 +71,6 @@
 #define PMD_PADDR       _AC(0xfffffffe,UL)
 #define PMD_PADDR_SHIFT _AC(11,UL)
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 #define PMD_ISHUGE      _AC(0x00000001,UL)
 /* This is the PMD layout when PMD_ISHUGE is set.  With 4MB huge
@@ -86,7 +85,6 @@
 #define PMD_HUGE_ACCESSED       _AC(0x00000080,UL)
 #define PMD_HUGE_EXEC           _AC(0x00000040,UL)
 #define PMD_HUGE_SPLITTING      _AC(0x00000020,UL)
-#endif
 /* PGDs point to PMD tables which are 8K aligned.  */
 #define PGD_PADDR       _AC(0xfffffffc,UL)
@@ -628,6 +626,12 @@ static inline unsigned long pte_special(pte_t pte)
        return pte_val(pte) & _PAGE_SPECIAL;
 }
+static inline int pmd_large(pmd_t pmd)
+{
+        return (pmd_val(pmd) & (PMD_ISHUGE | PMD_HUGE_PRESENT)) ==
+                (PMD_ISHUGE | PMD_HUGE_PRESENT);
+}
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 static inline int pmd_young(pmd_t pmd)
 {
@@ -646,12 +650,6 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
        return val >> (PAGE_SHIFT - PMD_PADDR_SHIFT);
 }
-static inline int pmd_large(pmd_t pmd)
-{
-        return (pmd_val(pmd) & (PMD_ISHUGE | PMD_HUGE_PRESENT)) ==
-                (PMD_ISHUGE | PMD_HUGE_PRESENT);
-}
 static inline int pmd_trans_splitting(pmd_t pmd)
 {
        return (pmd_val(pmd) & (PMD_ISHUGE|PMD_HUGE_SPLITTING)) ==
diff --git a/arch/sparc/kernel/sbus.c b/arch/sparc/kernel/sbus.c
index 1271b3a27d4e..be5bdf93c767 100644
--- a/arch/sparc/kernel/sbus.c
+++ b/arch/sparc/kernel/sbus.c
@@ -554,10 +554,8 @@ static void __init sbus_iommu_init(struct platform_device *op)
        regs = pr->phys_addr;
        iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
-        if (!iommu)
-                goto fatal_memory_error;
        strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
-        if (!strbuf)
+        if (!iommu || !strbuf)
                goto fatal_memory_error;
        op->dev.archdata.iommu = iommu;
@@ -656,6 +654,8 @@ static void __init sbus_iommu_init(struct platform_device *op)
        return;
 fatal_memory_error:
+        kfree(iommu);
+        kfree(strbuf);
        prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
 }
diff --git a/arch/sparc/mm/gup.c b/arch/sparc/mm/gup.c
index 42c55df3aec3..01ee23dd724d 100644
--- a/arch/sparc/mm/gup.c
+++ b/arch/sparc/mm/gup.c
@@ -66,6 +66,56 @@ static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
        return 1;
 }
+static int gup_huge_pmd(pmd_t *pmdp, pmd_t pmd, unsigned long addr,
+                        unsigned long end, int write, struct page **pages,
+                        int *nr)
+{
+        struct page *head, *page, *tail;
+        u32 mask;
+        int refs;
+        mask = PMD_HUGE_PRESENT;
+        if (write)
+                mask |= PMD_HUGE_WRITE;
+        if ((pmd_val(pmd) & mask) != mask)
+                return 0;
+        refs = 0;
+        head = pmd_page(pmd);
+        page = head + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
+        tail = page;
+        do {
+                VM_BUG_ON(compound_head(page) != head);
+                pages[*nr] = page;
+                (*nr)++;
+                page++;
+                refs++;
+        } while (addr += PAGE_SIZE, addr != end);
+        if (!page_cache_add_speculative(head, refs)) {
+                *nr -= refs;
+                return 0;
+        }
+        if (unlikely(pmd_val(pmd) != pmd_val(*pmdp))) {
+                *nr -= refs;
+                while (refs--)
+                        put_page(head);
+                return 0;
+        }
+        /* Any tail page need their mapcount reference taken before we
+         * return.
+         */
+        while (refs--) {
+                if (PageTail(tail))
+                        get_huge_page_tail(tail);
+                tail++;
+        }
+        return 1;
+}
 static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
                int write, struct page **pages, int *nr)
 {
@@ -77,9 +127,14 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
                pmd_t pmd = *pmdp;
                next = pmd_addr_end(addr, end);
-                if (pmd_none(pmd))
+                if (pmd_none(pmd) || pmd_trans_splitting(pmd))
                        return 0;
-                if (!gup_pte_range(pmd, addr, next, write, pages, nr))
+                if (unlikely(pmd_large(pmd))) {
+                        if (!gup_huge_pmd(pmdp, pmd, addr, next,
+                                          write, pages, nr))
+                                return 0;
+                } else if (!gup_pte_range(pmd, addr, next, write,
+                                          pages, nr))
                        return 0;
        } while (pmdp++, addr = next, addr != end);
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 875d008828b8..1bb7ad4aeff4 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -140,6 +140,8 @@ config ARCH_DEFCONFIG
 source "init/Kconfig"
+source "kernel/Kconfig.freezer"
 menu "Tilera-specific configuration"
 config NR_CPUS
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index 2a9b293fece6..31672918064c 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -250,7 +250,9 @@ static inline void writeq(u64 val, unsigned long addr)
 #define iowrite32 writel
 #define iowrite64 writeq
-static inline void memset_io(void *dst, int val, size_t len)
+#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
+static inline void memset_io(volatile void *dst, int val, size_t len)
 {
        int x;
        BUG_ON((unsigned long)dst & 0x3);
@@ -277,6 +279,8 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
                writel(*(u32 *)(src + x), dst + x);
 }
+#endif
 /*
 * The Tile architecture does not support IOPORT, even with PCI.
 * Unfortunately we can't yet simply not declare these methods,
diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h
index b4e96fef2cf8..241c0bb60b12 100644
--- a/arch/tile/include/asm/irqflags.h
+++ b/arch/tile/include/asm/irqflags.h
@@ -18,32 +18,20 @@
 #include <arch/interrupts.h>
 #include <arch/chip.h>
-#if !defined(__tilegx__) && defined(__ASSEMBLY__)
 /*
 * The set of interrupts we want to allow when interrupts are nominally
 * disabled.  The remainder are effectively "NMI" interrupts from
 * the point of view of the generic Linux code.  Note that synchronous
 * interrupts (aka "non-queued") are not blocked by the mask in any case.
 */
-#if CHIP_HAS_AUX_PERF_COUNTERS()
-#define LINUX_MASKABLE_INTERRUPTS_HI \
-        (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
-#else
-#define LINUX_MASKABLE_INTERRUPTS_HI \
-        (~(INT_MASK_HI(INT_PERF_COUNT)))
-#endif
-#else
-#if CHIP_HAS_AUX_PERF_COUNTERS()
-#define LINUX_MASKABLE_INTERRUPTS \
-        (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
-#else
 #define LINUX_MASKABLE_INTERRUPTS \
-        (~(INT_MASK(INT_PERF_COUNT)))
+        (~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
-#endif
+#if CHIP_HAS_SPLIT_INTR_MASK()
+/* The same macro, but for the two 32-bit SPRs separately. */
+#define LINUX_MASKABLE_INTERRUPTS_LO (-1)
+#define LINUX_MASKABLE_INTERRUPTS_HI \
+        (~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
 #endif
 #ifndef __ASSEMBLY__
@@ -126,7 +114,7 @@
 * to know our current state.
 */
 DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
-#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
+#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
 /* Disable interrupts. */
 #define arch_local_irq_disable() \
@@ -165,7 +153,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
 /* Prevent the given interrupt from being enabled next time we enable irqs. */
 #define arch_local_irq_mask(interrupt) \
-        (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
+        (__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
 /* Prevent the given interrupt from being enabled immediately. */
 #define arch_local_irq_mask_now(interrupt) do { \
@@ -175,7 +163,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
 /* Allow the given interrupt to be enabled next time we enable irqs. */
 #define arch_local_irq_unmask(interrupt) \
-        (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
+        (__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
 /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
 #define arch_local_irq_unmask_now(interrupt) do { \
@@ -250,7 +238,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
 /* Disable interrupts. */
 #define IRQ_DISABLE(tmp0, tmp1)                                 \
        {                                                       \
-         movei  tmp0, -1;                                       \
+         movei  tmp0, LINUX_MASKABLE_INTERRUPTS_LO;             \
         moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI)        \
        };                                                      \
        {                                                       \
diff --git a/arch/tile/include/uapi/arch/interrupts_32.h b/arch/tile/include/uapi/arch/interrupts_32.h
index 96b5710505b6..2efe3f68b2d6 100644
--- a/arch/tile/include/uapi/arch/interrupts_32.h
+++ b/arch/tile/include/uapi/arch/interrupts_32.h
@@ -15,6 +15,7 @@
 #ifndef __ARCH_INTERRUPTS_H__
 #define __ARCH_INTERRUPTS_H__
+#ifndef __KERNEL__
 /** Mask for an interrupt. */
 /* Note: must handle breaking interrupts into high and low words manually. */
 #define INT_MASK_LO(intno) (1 << (intno))
@@ -23,6 +24,7 @@
 #ifndef __ASSEMBLER__
 #define INT_MASK(intno) (1ULL << (intno))
 #endif
+#endif
 /** Where a given interrupt executes */
@@ -92,216 +94,216 @@
 #ifndef __ASSEMBLER__
 #define QUEUED_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_DMATLB_MISS) | \
+    (1ULL << INT_DMATLB_MISS) | \
-    INT_MASK(INT_DMATLB_ACCESS) | \
+    (1ULL << INT_DMATLB_ACCESS) | \
-    INT_MASK(INT_SNITLB_MISS) | \
+    (1ULL << INT_SNITLB_MISS) | \
-    INT_MASK(INT_SN_NOTIFY) | \
+    (1ULL << INT_SN_NOTIFY) | \
-    INT_MASK(INT_SN_FIREWALL) | \
+    (1ULL << INT_SN_FIREWALL) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_DMA_NOTIFY) | \
+    (1ULL << INT_DMA_NOTIFY) | \
-    INT_MASK(INT_IDN_CA) | \
+    (1ULL << INT_IDN_CA) | \
-    INT_MASK(INT_UDN_CA) | \
+    (1ULL << INT_UDN_CA) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DMA_ASID) | \
+    (1ULL << INT_DMA_ASID) | \
-    INT_MASK(INT_SNI_ASID) | \
+    (1ULL << INT_SNI_ASID) | \
-    INT_MASK(INT_DMA_CPL) | \
+    (1ULL << INT_DMA_CPL) | \
-    INT_MASK(INT_SN_CPL) | \
+    (1ULL << INT_SN_CPL) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
    0)
 #define NONQUEUED_INTERRUPTS ( \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_SN_ACCESS) | \
+    (1ULL << INT_SN_ACCESS) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_IDN_REFILL) | \
+    (1ULL << INT_IDN_REFILL) | \
-    INT_MASK(INT_UDN_REFILL) | \
+    (1ULL << INT_UDN_REFILL) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
-    INT_MASK(INT_SN_STATIC_ACCESS) | \
+    (1ULL << INT_SN_STATIC_ACCESS) | \
    0)
 #define CRITICAL_MASKED_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_DMATLB_MISS) | \
+    (1ULL << INT_DMATLB_MISS) | \
-    INT_MASK(INT_DMATLB_ACCESS) | \
+    (1ULL << INT_DMATLB_ACCESS) | \
-    INT_MASK(INT_SNITLB_MISS) | \
+    (1ULL << INT_SNITLB_MISS) | \
-    INT_MASK(INT_SN_NOTIFY) | \
+    (1ULL << INT_SN_NOTIFY) | \
-    INT_MASK(INT_SN_FIREWALL) | \
+    (1ULL << INT_SN_FIREWALL) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_DMA_NOTIFY) | \
+    (1ULL << INT_DMA_NOTIFY) | \
-    INT_MASK(INT_IDN_CA) | \
+    (1ULL << INT_IDN_CA) | \
-    INT_MASK(INT_UDN_CA) | \
+    (1ULL << INT_UDN_CA) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
    0)
 #define CRITICAL_UNMASKED_INTERRUPTS ( \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_SN_ACCESS) | \
+    (1ULL << INT_SN_ACCESS) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_IDN_REFILL) | \
+    (1ULL << INT_IDN_REFILL) | \
-    INT_MASK(INT_UDN_REFILL) | \
+    (1ULL << INT_UDN_REFILL) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DMA_ASID) | \
+    (1ULL << INT_DMA_ASID) | \
-    INT_MASK(INT_SNI_ASID) | \
+    (1ULL << INT_SNI_ASID) | \
-    INT_MASK(INT_DMA_CPL) | \
+    (1ULL << INT_DMA_CPL) | \
-    INT_MASK(INT_SN_CPL) | \
+    (1ULL << INT_SN_CPL) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
-    INT_MASK(INT_SN_STATIC_ACCESS) | \
+    (1ULL << INT_SN_STATIC_ACCESS) | \
    0)
 #define MASKABLE_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_IDN_REFILL) | \
+    (1ULL << INT_IDN_REFILL) | \
-    INT_MASK(INT_UDN_REFILL) | \
+    (1ULL << INT_UDN_REFILL) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_DMATLB_MISS) | \
+    (1ULL << INT_DMATLB_MISS) | \
-    INT_MASK(INT_DMATLB_ACCESS) | \
+    (1ULL << INT_DMATLB_ACCESS) | \
-    INT_MASK(INT_SNITLB_MISS) | \
+    (1ULL << INT_SNITLB_MISS) | \
-    INT_MASK(INT_SN_NOTIFY) | \
+    (1ULL << INT_SN_NOTIFY) | \
-    INT_MASK(INT_SN_FIREWALL) | \
+    (1ULL << INT_SN_FIREWALL) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_DMA_NOTIFY) | \
+    (1ULL << INT_DMA_NOTIFY) | \
-    INT_MASK(INT_IDN_CA) | \
+    (1ULL << INT_IDN_CA) | \
-    INT_MASK(INT_UDN_CA) | \
+    (1ULL << INT_UDN_CA) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
    0)
 #define UNMASKABLE_INTERRUPTS ( \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_SN_ACCESS) | \
+    (1ULL << INT_SN_ACCESS) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DMA_ASID) | \
+    (1ULL << INT_DMA_ASID) | \
-    INT_MASK(INT_SNI_ASID) | \
+    (1ULL << INT_SNI_ASID) | \
-    INT_MASK(INT_DMA_CPL) | \
+    (1ULL << INT_DMA_CPL) | \
-    INT_MASK(INT_SN_CPL) | \
+    (1ULL << INT_SN_CPL) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
-    INT_MASK(INT_SN_STATIC_ACCESS) | \
+    (1ULL << INT_SN_STATIC_ACCESS) | \
    0)
 #define SYNC_INTERRUPTS ( \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_SN_ACCESS) | \
+    (1ULL << INT_SN_ACCESS) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_IDN_REFILL) | \
+    (1ULL << INT_IDN_REFILL) | \
-    INT_MASK(INT_UDN_REFILL) | \
+    (1ULL << INT_UDN_REFILL) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
-    INT_MASK(INT_SN_STATIC_ACCESS) | \
+    (1ULL << INT_SN_STATIC_ACCESS) | \
    0)
 #define NON_SYNC_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_DMATLB_MISS) | \
+    (1ULL << INT_DMATLB_MISS) | \
-    INT_MASK(INT_DMATLB_ACCESS) | \
+    (1ULL << INT_DMATLB_ACCESS) | \
-    INT_MASK(INT_SNITLB_MISS) | \
+    (1ULL << INT_SNITLB_MISS) | \
-    INT_MASK(INT_SN_NOTIFY) | \
+    (1ULL << INT_SN_NOTIFY) | \
-    INT_MASK(INT_SN_FIREWALL) | \
+    (1ULL << INT_SN_FIREWALL) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_DMA_NOTIFY) | \
+    (1ULL << INT_DMA_NOTIFY) | \
-    INT_MASK(INT_IDN_CA) | \
+    (1ULL << INT_IDN_CA) | \
-    INT_MASK(INT_UDN_CA) | \
+    (1ULL << INT_UDN_CA) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DMA_ASID) | \
+    (1ULL << INT_DMA_ASID) | \
-    INT_MASK(INT_SNI_ASID) | \
+    (1ULL << INT_SNI_ASID) | \
-    INT_MASK(INT_DMA_CPL) | \
+    (1ULL << INT_DMA_CPL) | \
-    INT_MASK(INT_SN_CPL) | \
+    (1ULL << INT_SN_CPL) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
    0)
 #endif /* !__ASSEMBLER__ */
 #endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/uapi/arch/interrupts_64.h b/arch/tile/include/uapi/arch/interrupts_64.h
index 5bb58b2e4e6f..13c9f9182348 100644
--- a/arch/tile/include/uapi/arch/interrupts_64.h
+++ b/arch/tile/include/uapi/arch/interrupts_64.h
@@ -15,6 +15,7 @@
 #ifndef __ARCH_INTERRUPTS_H__
 #define __ARCH_INTERRUPTS_H__
+#ifndef __KERNEL__
 /** Mask for an interrupt. */
 #ifdef __ASSEMBLER__
 /* Note: must handle breaking interrupts into high and low words manually. */
@@ -22,6 +23,7 @@
 #else
 #define INT_MASK(intno) (1ULL << (intno))
 #endif
+#endif
 /** Where a given interrupt executes */
@@ -85,192 +87,192 @@
 #ifndef __ASSEMBLER__
 #define QUEUED_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_AUX_TILE_TIMER) | \
+    (1ULL << INT_AUX_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_IPI_3) | \
+    (1ULL << INT_IPI_3) | \
-    INT_MASK(INT_IPI_2) | \
+    (1ULL << INT_IPI_2) | \
-    INT_MASK(INT_IPI_1) | \
+    (1ULL << INT_IPI_1) | \
-    INT_MASK(INT_IPI_0) | \
+    (1ULL << INT_IPI_0) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
    0)
 #define NONQUEUED_INTERRUPTS ( \
-    INT_MASK(INT_SINGLE_STEP_3) | \
+    (1ULL << INT_SINGLE_STEP_3) | \
-    INT_MASK(INT_SINGLE_STEP_2) | \
+    (1ULL << INT_SINGLE_STEP_2) | \
-    INT_MASK(INT_SINGLE_STEP_1) | \
+    (1ULL << INT_SINGLE_STEP_1) | \
-    INT_MASK(INT_SINGLE_STEP_0) | \
+    (1ULL << INT_SINGLE_STEP_0) | \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_ILL_TRANS) | \
+    (1ULL << INT_ILL_TRANS) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
    0)
 #define CRITICAL_MASKED_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_SINGLE_STEP_3) | \
+    (1ULL << INT_SINGLE_STEP_3) | \
-    INT_MASK(INT_SINGLE_STEP_2) | \
+    (1ULL << INT_SINGLE_STEP_2) | \
-    INT_MASK(INT_SINGLE_STEP_1) | \
+    (1ULL << INT_SINGLE_STEP_1) | \
-    INT_MASK(INT_SINGLE_STEP_0) | \
+    (1ULL << INT_SINGLE_STEP_0) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_AUX_TILE_TIMER) | \
+    (1ULL << INT_AUX_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_IPI_3) | \
+    (1ULL << INT_IPI_3) | \
-    INT_MASK(INT_IPI_2) | \
+    (1ULL << INT_IPI_2) | \
-    INT_MASK(INT_IPI_1) | \
+    (1ULL << INT_IPI_1) | \
-    INT_MASK(INT_IPI_0) | \
+    (1ULL << INT_IPI_0) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
    0)
 #define CRITICAL_UNMASKED_INTERRUPTS ( \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_ILL_TRANS) | \
+    (1ULL << INT_ILL_TRANS) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
    0)
 #define MASKABLE_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_SINGLE_STEP_3) | \
+    (1ULL << INT_SINGLE_STEP_3) | \
-    INT_MASK(INT_SINGLE_STEP_2) | \
+    (1ULL << INT_SINGLE_STEP_2) | \
-    INT_MASK(INT_SINGLE_STEP_1) | \
+    (1ULL << INT_SINGLE_STEP_1) | \
-    INT_MASK(INT_SINGLE_STEP_0) | \
+    (1ULL << INT_SINGLE_STEP_0) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_AUX_TILE_TIMER) | \
+    (1ULL << INT_AUX_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_IPI_3) | \
+    (1ULL << INT_IPI_3) | \
-    INT_MASK(INT_IPI_2) | \
+    (1ULL << INT_IPI_2) | \
-    INT_MASK(INT_IPI_1) | \
+    (1ULL << INT_IPI_1) | \
-    INT_MASK(INT_IPI_0) | \
+    (1ULL << INT_IPI_0) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
    0)
 #define UNMASKABLE_INTERRUPTS ( \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_ILL_TRANS) | \
+    (1ULL << INT_ILL_TRANS) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
    0)
 #define SYNC_INTERRUPTS ( \
-    INT_MASK(INT_SINGLE_STEP_3) | \
+    (1ULL << INT_SINGLE_STEP_3) | \
-    INT_MASK(INT_SINGLE_STEP_2) | \
+    (1ULL << INT_SINGLE_STEP_2) | \
-    INT_MASK(INT_SINGLE_STEP_1) | \
+    (1ULL << INT_SINGLE_STEP_1) | \
-    INT_MASK(INT_SINGLE_STEP_0) | \
+    (1ULL << INT_SINGLE_STEP_0) | \
-    INT_MASK(INT_IDN_COMPLETE) | \
+    (1ULL << INT_IDN_COMPLETE) | \
-    INT_MASK(INT_UDN_COMPLETE) | \
+    (1ULL << INT_UDN_COMPLETE) | \
-    INT_MASK(INT_ITLB_MISS) | \
+    (1ULL << INT_ITLB_MISS) | \
-    INT_MASK(INT_ILL) | \
+    (1ULL << INT_ILL) | \
-    INT_MASK(INT_GPV) | \
+    (1ULL << INT_GPV) | \
-    INT_MASK(INT_IDN_ACCESS) | \
+    (1ULL << INT_IDN_ACCESS) | \
-    INT_MASK(INT_UDN_ACCESS) | \
+    (1ULL << INT_UDN_ACCESS) | \
-    INT_MASK(INT_SWINT_3) | \
+    (1ULL << INT_SWINT_3) | \
-    INT_MASK(INT_SWINT_2) | \
+    (1ULL << INT_SWINT_2) | \
-    INT_MASK(INT_SWINT_1) | \
+    (1ULL << INT_SWINT_1) | \
-    INT_MASK(INT_SWINT_0) | \
+    (1ULL << INT_SWINT_0) | \
-    INT_MASK(INT_ILL_TRANS) | \
+    (1ULL << INT_ILL_TRANS) | \
-    INT_MASK(INT_UNALIGN_DATA) | \
+    (1ULL << INT_UNALIGN_DATA) | \
-    INT_MASK(INT_DTLB_MISS) | \
+    (1ULL << INT_DTLB_MISS) | \
-    INT_MASK(INT_DTLB_ACCESS) | \
+    (1ULL << INT_DTLB_ACCESS) | \
    0)
 #define NON_SYNC_INTERRUPTS ( \
-    INT_MASK(INT_MEM_ERROR) | \
+    (1ULL << INT_MEM_ERROR) | \
-    INT_MASK(INT_IDN_FIREWALL) | \
+    (1ULL << INT_IDN_FIREWALL) | \
-    INT_MASK(INT_UDN_FIREWALL) | \
+    (1ULL << INT_UDN_FIREWALL) | \
-    INT_MASK(INT_TILE_TIMER) | \
+    (1ULL << INT_TILE_TIMER) | \
-    INT_MASK(INT_AUX_TILE_TIMER) | \
+    (1ULL << INT_AUX_TILE_TIMER) | \
-    INT_MASK(INT_IDN_TIMER) | \
+    (1ULL << INT_IDN_TIMER) | \
-    INT_MASK(INT_UDN_TIMER) | \
+    (1ULL << INT_UDN_TIMER) | \
-    INT_MASK(INT_IDN_AVAIL) | \
+    (1ULL << INT_IDN_AVAIL) | \
-    INT_MASK(INT_UDN_AVAIL) | \
+    (1ULL << INT_UDN_AVAIL) | \
-    INT_MASK(INT_IPI_3) | \
+    (1ULL << INT_IPI_3) | \
-    INT_MASK(INT_IPI_2) | \
+    (1ULL << INT_IPI_2) | \
-    INT_MASK(INT_IPI_1) | \
+    (1ULL << INT_IPI_1) | \
-    INT_MASK(INT_IPI_0) | \
+    (1ULL << INT_IPI_0) | \
-    INT_MASK(INT_PERF_COUNT) | \
+    (1ULL << INT_PERF_COUNT) | \
-    INT_MASK(INT_AUX_PERF_COUNT) | \
+    (1ULL << INT_AUX_PERF_COUNT) | \
-    INT_MASK(INT_INTCTRL_3) | \
+    (1ULL << INT_INTCTRL_3) | \
-    INT_MASK(INT_INTCTRL_2) | \
+    (1ULL << INT_INTCTRL_2) | \
-    INT_MASK(INT_INTCTRL_1) | \
+    (1ULL << INT_INTCTRL_1) | \
-    INT_MASK(INT_INTCTRL_0) | \
+    (1ULL << INT_INTCTRL_0) | \
-    INT_MASK(INT_BOOT_ACCESS) | \
+    (1ULL << INT_BOOT_ACCESS) | \
-    INT_MASK(INT_WORLD_ACCESS) | \
+    (1ULL << INT_WORLD_ACCESS) | \
-    INT_MASK(INT_I_ASID) | \
+    (1ULL << INT_I_ASID) | \
-    INT_MASK(INT_D_ASID) | \
+    (1ULL << INT_D_ASID) | \
-    INT_MASK(INT_DOUBLE_FAULT) | \
+    (1ULL << INT_DOUBLE_FAULT) | \
    0)
 #endif /* !__ASSEMBLER__ */
 #endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
index 54bc9a6678e8..4ea080902654 100644
--- a/arch/tile/kernel/intvec_64.S
+++ b/arch/tile/kernel/intvec_64.S
@@ -1035,7 +1035,9 @@ handle_syscall:
        /* Ensure that the syscall number is within the legal range. */
        {
         moveli r20, hw2(sys_call_table)
+#ifdef CONFIG_COMPAT
         blbs   r30, .Lcompat_syscall
+#endif
        }
        {
         cmpltu r21, TREG_SYSCALL_NR_NAME, r21
@@ -1093,6 +1095,7 @@ handle_syscall:
         j      .Lresume_userspace   /* jump into middle of interrupt_return */
        }
+#ifdef CONFIG_COMPAT
 .Lcompat_syscall:
        /*
         * Load the base of the compat syscall table in r20, and
@@ -1117,6 +1120,7 @@ handle_syscall:
        { move r15, r4; addxi r4, r4, 0 }
        { move r16, r5; addxi r5, r5, 0 }
        j .Lload_syscall_pointer
+#endif
 .Linvalid_syscall:
        /* Report an invalid syscall back to the user program */
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 0e5661e7d00d..caf93ae11793 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -159,7 +159,7 @@ static void save_arch_state(struct thread_struct *t);
 int copy_thread(unsigned long clone_flags, unsigned long sp,
                unsigned long arg, struct task_struct *p)
 {
-        struct pt_regs *childregs = task_pt_regs(p), *regs = current_pt_regs();
+        struct pt_regs *childregs = task_pt_regs(p);
        unsigned long ksp;
        unsigned long *callee_regs;
diff --git a/arch/tile/kernel/reboot.c b/arch/tile/kernel/reboot.c
index baa3d905fee2..d1b5c913ae72 100644
--- a/arch/tile/kernel/reboot.c
+++ b/arch/tile/kernel/reboot.c
@@ -16,6 +16,7 @@
 #include <linux/reboot.h>
 #include <linux/smp.h>
 #include <linux/pm.h>
+#include <linux/export.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <hv/hypervisor.h>
@@ -49,3 +50,4 @@ void machine_restart(char *cmd)
 /* No interesting distinction to be made here. */
 void (*pm_power_off)(void) = NULL;
+EXPORT_SYMBOL(pm_power_off);
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 6a649a4462d3..d1e15f7b59c6 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -31,6 +31,7 @@
 #include <linux/timex.h>
 #include <linux/hugetlb.h>
 #include <linux/start_kernel.h>
+#include <linux/screen_info.h>
 #include <asm/setup.h>
 #include <asm/sections.h>
 #include <asm/cacheflush.h>
@@ -49,6 +50,10 @@ static inline int ABS(int x) { return x >= 0 ? x : -x; }
 /* Chip information */
 char chip_model[64] __write_once;
+#ifdef CONFIG_VT
+struct screen_info screen_info;
+#endif
 struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
 EXPORT_SYMBOL(node_data);
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
index b2f44c28dda6..ed258b8ae320 100644
--- a/arch/tile/kernel/stack.c
+++ b/arch/tile/kernel/stack.c
@@ -112,7 +112,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
                       p->pc, p->sp, p->ex1);
                p = NULL;
        }
-        if (!kbt->profile || (INT_MASK(p->faultnum) & QUEUED_INTERRUPTS) == 0)
+        if (!kbt->profile || ((1ULL << p->faultnum) & QUEUED_INTERRUPTS) == 0)
                return p;
        return NULL;
 }
@@ -484,6 +484,7 @@ void save_stack_trace(struct stack_trace *trace)
 {
        save_stack_trace_tsk(NULL, trace);
 }
+EXPORT_SYMBOL_GPL(save_stack_trace);
 #endif
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index db4fb89e12d8..8f8ad814b139 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -12,6 +12,7 @@
 *   more details.
 */
+#include <linux/export.h>
 #include <asm/page.h>
 #include <asm/cacheflush.h>
 #include <arch/icache.h>
@@ -165,3 +166,4 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
        __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
 #endif
 }
+EXPORT_SYMBOL_GPL(finv_buffer_remote);
diff --git a/arch/tile/lib/cpumask.c b/arch/tile/lib/cpumask.c
index fdc403614d12..75947edccb26 100644
--- a/arch/tile/lib/cpumask.c
+++ b/arch/tile/lib/cpumask.c
@@ -16,6 +16,7 @@
 #include <linux/ctype.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/export.h>
 /*
 * Allow cropping out bits beyond the end of the array.
@@ -50,3 +51,4 @@ int bitmap_parselist_crop(const char *bp, unsigned long *maskp, int nmaskbits)
        } while (*bp != '\0' && *bp != '\n');
        return 0;
 }
+EXPORT_SYMBOL(bitmap_parselist_crop);
diff --git a/arch/tile/lib/exports.c b/arch/tile/lib/exports.c
index dd5f0a33fdaf..4385cb6fa00a 100644
--- a/arch/tile/lib/exports.c
+++ b/arch/tile/lib/exports.c
@@ -55,6 +55,8 @@ EXPORT_SYMBOL(hv_dev_poll_cancel);
 EXPORT_SYMBOL(hv_dev_close);
 EXPORT_SYMBOL(hv_sysconf);
 EXPORT_SYMBOL(hv_confstr);
+EXPORT_SYMBOL(hv_get_rtc);
+EXPORT_SYMBOL(hv_set_rtc);
 /* libgcc.a */
 uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);
diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c
index 5f7868dcd6d4..1ae911939a18 100644
--- a/arch/tile/mm/homecache.c
+++ b/arch/tile/mm/homecache.c
@@ -408,6 +408,7 @@ void homecache_change_page_home(struct page *page, int order, int home)
                __set_pte(ptep, pte_set_home(pteval, home));
        }
 }
+EXPORT_SYMBOL(homecache_change_page_home);
 struct page *homecache_alloc_pages(gfp_t gfp_mask,
                                   unsigned int order, int home)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 79795af59810..a9e50ac90838 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -28,7 +28,6 @@ config X86
        select HAVE_OPROFILE
        select HAVE_PCSPKR_PLATFORM
        select HAVE_PERF_EVENTS
-        select HAVE_IRQ_WORK
        select HAVE_IOREMAP_PROT
        select HAVE_KPROBES
        select HAVE_MEMBLOCK
@@ -40,10 +39,12 @@ config X86
        select HAVE_DMA_CONTIGUOUS if !SWIOTLB
        select HAVE_KRETPROBES
        select HAVE_OPTPROBES
+        select HAVE_KPROBES_ON_FTRACE
        select HAVE_FTRACE_MCOUNT_RECORD
        select HAVE_FENTRY if X86_64
        select HAVE_C_RECORDMCOUNT
        select HAVE_DYNAMIC_FTRACE
+        select HAVE_DYNAMIC_FTRACE_WITH_REGS
        select HAVE_FUNCTION_TRACER
        select HAVE_FUNCTION_GRAPH_TRACER
        select HAVE_FUNCTION_GRAPH_FP_TEST
@@ -106,6 +107,7 @@ config X86
        select GENERIC_CLOCKEVENTS_BROADCAST if X86_64 || (X86_32 && X86_LOCAL_APIC)
        select GENERIC_TIME_VSYSCALL if X86_64
        select KTIME_SCALAR if X86_32
+        select ALWAYS_USE_PERSISTENT_CLOCK
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
        select HAVE_CONTEXT_TRACKING if X86_64
@@ -114,6 +116,7 @@ config X86
        select MODULES_USE_ELF_RELA if X86_64
        select CLONE_BACKWARDS if X86_32
        select GENERIC_SIGALTSTACK
+        select ARCH_USE_BUILTIN_BSWAP
 config INSTRUCTION_DECODER
        def_bool y
@@ -2138,6 +2141,7 @@ config OLPC_XO1_RTC
 config OLPC_XO1_SCI
        bool "OLPC XO-1 SCI extras"
        depends on OLPC && OLPC_XO1_PM
+        depends on INPUT=y
        select POWER_SUPPLY
        select GPIO_CS5535
        select MFD_CORE
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index ccce0ed67dde..379814bc41e3 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -71,7 +71,7 @@ GCOV_PROFILE := n
 $(obj)/bzImage: asflags-y  := $(SVGA_MODE)
 quiet_cmd_image = BUILD   $@
-cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin > $@
+cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/zoffset.h > $@
 $(obj)/bzImage: $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/tools/build FORCE
        $(call if_changed,image)
@@ -92,7 +92,7 @@ targets += voffset.h
 $(obj)/voffset.h: vmlinux FORCE
        $(call if_changed,voffset)
-sed-zoffset := -e 's/^\([0-9a-fA-F]*\) . \(startup_32\|input_data\|_end\|z_.*\)$$/\#define ZO_\2 0x\1/p'
+sed-zoffset := -e 's/^\([0-9a-fA-F]*\) . \(startup_32\|startup_64\|efi_pe_entry\|efi_stub_entry\|input_data\|_end\|z_.*\)$$/\#define ZO_\2 0x\1/p'
 quiet_cmd_zoffset = ZOFFSET $@
      cmd_zoffset = $(NM) $< | sed -n $(sed-zoffset) > $@
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 18e329ca108e..f8fa41190c35 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -256,10 +256,10 @@ static efi_status_t setup_efi_pci(struct boot_params *params)
        int i;
        struct setup_data *data;
-        data = (struct setup_data *)params->hdr.setup_data;
+        data = (struct setup_data *)(unsigned long)params->hdr.setup_data;
        while (data && data->next)
-                data = (struct setup_data *)data->next;
+                data = (struct setup_data *)(unsigned long)data->next;
        status = efi_call_phys5(sys_table->boottime->locate_handle,
                                EFI_LOCATE_BY_PROTOCOL, &pci_proto,
@@ -295,16 +295,18 @@ static efi_status_t setup_efi_pci(struct boot_params *params)
                if (!pci)
                        continue;
+#ifdef CONFIG_X86_64
                status = efi_call_phys4(pci->attributes, pci,
                                        EfiPciIoAttributeOperationGet, 0,
                                        &attributes);
+#else
+                status = efi_call_phys5(pci->attributes, pci,
+                                        EfiPciIoAttributeOperationGet, 0, 0,
+                                        &attributes);
+#endif
                if (status != EFI_SUCCESS)
                        continue;
-                if (!(attributes & EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM))
-                        continue;
                if (!pci->romimage || !pci->romsize)
                        continue;
@@ -345,9 +347,9 @@ static efi_status_t setup_efi_pci(struct boot_params *params)
                memcpy(rom->romdata, pci->romimage, pci->romsize);
                if (data)
-                        data->next = (uint64_t)rom;
+                        data->next = (unsigned long)rom;
                else
-                        params->hdr.setup_data = (uint64_t)rom;
+                        params->hdr.setup_data = (unsigned long)rom;
                data = (struct setup_data *)rom;
@@ -432,10 +434,9 @@ static efi_status_t setup_gop(struct screen_info *si, efi_guid_t *proto,
                         * Once we've found a GOP supporting ConOut,
                         * don't bother looking any further.
                         */
+                        first_gop = gop;
                        if (conout_found)
                                break;
-                        first_gop = gop;
                }
        }
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index aa4aaf1b2380..1e3184f6072f 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -35,11 +35,11 @@ ENTRY(startup_32)
 #ifdef CONFIG_EFI_STUB
        jmp     preferred_addr
-        .balign 0x10
        /*
         * We don't need the return address, so set up the stack so
-         * efi_main() can find its arugments.
+         * efi_main() can find its arguments.
         */
+ENTRY(efi_pe_entry)
        add     $0x4, %esp
        call    make_boot_params
@@ -50,8 +50,10 @@ ENTRY(startup_32)
        pushl   %eax
        pushl   %esi
        pushl   %ecx
+        sub     $0x4, %esp
-        .org 0x30,0x90
+ENTRY(efi_stub_entry)
+        add     $0x4, %esp
        call    efi_main
        cmpl    $0, %eax
        movl    %eax, %esi
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 2c4b171eec33..f5d1aaa0dec8 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -201,12 +201,12 @@ ENTRY(startup_64)
         */
 #ifdef CONFIG_EFI_STUB
        /*
-         * The entry point for the PE/COFF executable is 0x210, so only
+         * The entry point for the PE/COFF executable is efi_pe_entry, so
-         * legacy boot loaders will execute this jmp.
+         * only legacy boot loaders will execute this jmp.
         */
        jmp     preferred_addr
-        .org 0x210
+ENTRY(efi_pe_entry)
        mov     %rcx, %rdi
        mov     %rdx, %rsi
        pushq   %rdi
@@ -218,7 +218,7 @@ ENTRY(startup_64)
        popq    %rsi
        popq    %rdi
-        .org 0x230,0x90
+ENTRY(efi_stub_entry)
        call    efi_main
        movq    %rax,%rsi
        cmpq    $0,%rax
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index 4b8e165ee572..94c544650020 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -52,6 +52,10 @@ int is_big_kernel;
 #define PECOFF_RELOC_RESERVE 0x20
+unsigned long efi_stub_entry;
+unsigned long efi_pe_entry;
+unsigned long startup_64;
 /*----------------------------------------------------------------------*/
 static const u32 crctab32[] = {
@@ -132,7 +136,7 @@ static void die(const char * str, ...)
 static void usage(void)
 {
-        die("Usage: build setup system [> image]");
+        die("Usage: build setup system [zoffset.h] [> image]");
 }
 #ifdef CONFIG_EFI_STUB
@@ -206,30 +210,54 @@ static void update_pecoff_text(unsigned int text_start, unsigned int file_sz)
         */
        put_unaligned_le32(file_sz - 512, &buf[pe_header + 0x1c]);
-#ifdef CONFIG_X86_32
        /*
-         * Address of entry point.
+         * Address of entry point for PE/COFF executable
-         *
-         * The EFI stub entry point is +16 bytes from the start of
-         * the .text section.
         */
-        put_unaligned_le32(text_start + 16, &buf[pe_header + 0x28]);
+        put_unaligned_le32(text_start + efi_pe_entry, &buf[pe_header + 0x28]);
-#else
-        /*
-         * Address of entry point. startup_32 is at the beginning and
-         * the 64-bit entry point (startup_64) is always 512 bytes
-         * after. The EFI stub entry point is 16 bytes after that, as
-         * the first instruction allows legacy loaders to jump over
-         * the EFI stub initialisation
-         */
-        put_unaligned_le32(text_start + 528, &buf[pe_header + 0x28]);
-#endif /* CONFIG_X86_32 */
        update_pecoff_section_header(".text", text_start, text_sz);
 }
 #endif /* CONFIG_EFI_STUB */
+/*
+ * Parse zoffset.h and find the entry points. We could just #include zoffset.h
+ * but that would mean tools/build would have to be rebuilt every time. It's
+ * not as if parsing it is hard...
+ */
+#define PARSE_ZOFS(p, sym) do { \
+        if (!strncmp(p, "#define ZO_" #sym " ", 11+sizeof(#sym)))       \
+                sym = strtoul(p + 11 + sizeof(#sym), NULL, 16);         \
+} while (0)
+static void parse_zoffset(char *fname)
+{
+        FILE *file;
+        char *p;
+        int c;
+        file = fopen(fname, "r");
+        if (!file)
+                die("Unable to open `%s': %m", fname);
+        c = fread(buf, 1, sizeof(buf) - 1, file);
+        if (ferror(file))
+                die("read-error on `zoffset.h'");
+        buf[c] = 0;
+        p = (char *)buf;
+        while (p && *p) {
+                PARSE_ZOFS(p, efi_stub_entry);
+                PARSE_ZOFS(p, efi_pe_entry);
+                PARSE_ZOFS(p, startup_64);
+                p = strchr(p, '\n');
+                while (p && (*p == '\r' || *p == '\n'))
+                        p++;
+        }
+}
 int main(int argc, char ** argv)
 {
        unsigned int i, sz, setup_sectors;
@@ -241,7 +269,19 @@ int main(int argc, char ** argv)
        void *kernel;
        u32 crc = 0xffffffffUL;
-        if (argc != 3)
+        /* Defaults for old kernel */
+#ifdef CONFIG_X86_32
+        efi_pe_entry = 0x10;
+        efi_stub_entry = 0x30;
+#else
+        efi_pe_entry = 0x210;
+        efi_stub_entry = 0x230;
+        startup_64 = 0x200;
+#endif
+        if (argc == 4)
+                parse_zoffset(argv[3]);
+        else if (argc != 3)
                usage();
        /* Copy the setup code */
@@ -299,6 +339,11 @@ int main(int argc, char ** argv)
 #ifdef CONFIG_EFI_STUB
        update_pecoff_text(setup_sectors * 512, sz + i + ((sys_size * 16) - sz));
+#ifdef CONFIG_X86_64 /* Yes, this is really how we defined it :( */
+        efi_stub_entry -= 0x200;
+#endif
+        put_unaligned_le32(efi_stub_entry, &buf[0x264]);
 #endif
        crc = partial_crc32(buf, i, crc);
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index 102ff7cb3e41..142c4ceff112 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -207,7 +207,7 @@ sysexit_from_sys_call:
        testl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),TI_flags+THREAD_INFO(%rsp,RIP-ARGOFFSET)
        jnz ia32_ret_from_sys_call
        TRACE_IRQS_ON
-        sti
+        ENABLE_INTERRUPTS(CLBR_NONE)
        movl %eax,%esi          /* second arg, syscall return value */
        cmpl $-MAX_ERRNO,%eax   /* is it an error ? */
        jbe 1f
@@ -217,7 +217,7 @@ sysexit_from_sys_call:
        call __audit_syscall_exit
        movq RAX-ARGOFFSET(%rsp),%rax   /* reload syscall return value */
        movl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),%edi
-        cli
+        DISABLE_INTERRUPTS(CLBR_NONE)
        TRACE_IRQS_OFF
        testl %edi,TI_flags+THREAD_INFO(%rsp,RIP-ARGOFFSET)
        jz \exit
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 2d9075e863a0..93fe929d1cee 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -167,6 +167,7 @@
 #define X86_FEATURE_TBM         (6*32+21) /* trailing bit manipulations */
 #define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
 #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
+#define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
 /*
 * Auxiliary flags: Linux defined - For features scattered in various
@@ -309,6 +310,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_hypervisor      boot_cpu_has(X86_FEATURE_HYPERVISOR)
 #define cpu_has_pclmulqdq       boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 #define cpu_has_perfctr_core    boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
+#define cpu_has_perfctr_nb      boot_cpu_has(X86_FEATURE_PERFCTR_NB)
 #define cpu_has_cx8             boot_cpu_has(X86_FEATURE_CX8)
 #define cpu_has_cx16            boot_cpu_has(X86_FEATURE_CX16)
 #define cpu_has_eager_fpu       boot_cpu_has(X86_FEATURE_EAGER_FPU)
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 6e8fdf5ad113..28677c55113f 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -94,6 +94,7 @@ extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size,
 #endif /* CONFIG_X86_32 */
 extern int add_efi_memmap;
+extern unsigned long x86_efi_facility;
 extern void efi_set_executable(efi_memory_desc_t *md, bool executable);
 extern int efi_memblock_x86_reserve_range(void);
 extern void efi_call_phys_prelog(void);
diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h
index 9a25b522d377..86cb51e1ca96 100644
--- a/arch/x86/include/asm/ftrace.h
+++ b/arch/x86/include/asm/ftrace.h
@@ -44,7 +44,6 @@
 #ifdef CONFIG_DYNAMIC_FTRACE
 #define ARCH_SUPPORTS_FTRACE_OPS 1
-#define ARCH_SUPPORTS_FTRACE_SAVE_REGS
 #endif
 #ifndef __ASSEMBLY__
diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h
index 434e2106cc87..b18df579c0e9 100644
--- a/arch/x86/include/asm/hpet.h
+++ b/arch/x86/include/asm/hpet.h
@@ -80,9 +80,9 @@ extern void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg);
 extern void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg);
 #ifdef CONFIG_PCI_MSI
-extern int arch_setup_hpet_msi(unsigned int irq, unsigned int id);
+extern int default_setup_hpet_msi(unsigned int irq, unsigned int id);
 #else
-static inline int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
+static inline int default_setup_hpet_msi(unsigned int irq, unsigned int id)
 {
        return -EINVAL;
 }
@@ -111,6 +111,7 @@ extern void hpet_unregister_irq_handler(rtc_irq_handler handler);
 static inline int hpet_enable(void) { return 0; }
 static inline int is_hpet_enabled(void) { return 0; }
 #define hpet_readl(a) 0
+#define default_setup_hpet_msi  NULL
 #endif
 #endif /* _ASM_X86_HPET_H */
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index eb92a6ed2be7..10a78c3d3d5a 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -101,6 +101,7 @@ static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr,
        irq_attr->polarity      = polarity;
 }
+/* Intel specific interrupt remapping information */
 struct irq_2_iommu {
        struct intel_iommu *iommu;
        u16 irte_index;
@@ -108,6 +109,12 @@ struct irq_2_iommu {
        u8  irte_mask;
 };
+/* AMD specific interrupt remapping information */
+struct irq_2_irte {
+        u16 devid; /* Device ID for IRTE table */
+        u16 index; /* Index into IRTE table*/
+};
 /*
 * This is performance-critical, we want to do it O(1)
 *
@@ -120,7 +127,11 @@ struct irq_cfg {
        u8                      vector;
        u8                      move_in_progress : 1;
 #ifdef CONFIG_IRQ_REMAP
-        struct irq_2_iommu      irq_2_iommu;
+        u8                      remapped : 1;
+        union {
+                struct irq_2_iommu irq_2_iommu;
+                struct irq_2_irte  irq_2_irte;
+        };
 #endif
 };
diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h
index b518c7509933..86095ed14135 100644
--- a/arch/x86/include/asm/hypervisor.h
+++ b/arch/x86/include/asm/hypervisor.h
@@ -25,6 +25,7 @@
 extern void init_hypervisor(struct cpuinfo_x86 *c);
 extern void init_hypervisor_platform(void);
+extern bool hypervisor_x2apic_available(void);
 /*
 * x86 hypervisor information
@@ -41,6 +42,9 @@ struct hypervisor_x86 {
        /* Platform setup (run once per boot) */
        void            (*init_platform)(void);
+        /* X2APIC detection (run once per boot) */
+        bool            (*x2apic_available)(void);
 };
 extern const struct hypervisor_x86 *x86_hyper;
@@ -51,13 +55,4 @@ extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
 extern const struct hypervisor_x86 x86_hyper_xen_hvm;
 extern const struct hypervisor_x86 x86_hyper_kvm;
-static inline bool hypervisor_x2apic_available(void)
-{
-        if (kvm_para_available())
-                return true;
-        if (xen_x2apic_para_available())
-                return true;
-        return false;
-}
 #endif
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 73d8c5398ea9..459e50a424d1 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -144,11 +144,24 @@ extern int timer_through_8259;
        (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
 struct io_apic_irq_attr;
+struct irq_cfg;
 extern int io_apic_set_pci_routing(struct device *dev, int irq,
                 struct io_apic_irq_attr *irq_attr);
 void setup_IO_APIC_irq_extra(u32 gsi);
 extern void ioapic_insert_resources(void);
+extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
+                                     unsigned int, int,
+                                     struct io_apic_irq_attr *);
+extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
+                                     unsigned int, int,
+                                     struct io_apic_irq_attr *);
+extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
+extern void native_compose_msi_msg(struct pci_dev *pdev,
+                                   unsigned int irq, unsigned int dest,
+                                   struct msi_msg *msg, u8 hpet_id);
+extern void native_eoi_ioapic_pin(int apic, int pin, int vector);
 int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
 extern int save_ioapic_entries(void);
@@ -179,6 +192,12 @@ extern void __init native_io_apic_init_mappings(void);
 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
 extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val);
 extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
+extern void native_disable_io_apic(void);
+extern void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries);
+extern void intel_ir_io_apic_print_entries(unsigned int apic, unsigned int nr_entries);
+extern int native_ioapic_set_affinity(struct irq_data *,
+                                      const struct cpumask *,
+                                      bool);
 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 {
@@ -193,6 +212,9 @@ static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned
 {
        x86_io_apic_ops.modify(apic, reg, value);
 }
+extern void io_apic_eoi(unsigned int apic, unsigned int vector);
 #else  /* !CONFIG_X86_IO_APIC */
 #define io_apic_assign_pci_irqs 0
@@ -223,6 +245,12 @@ static inline void disable_ioapic_support(void) { }
 #define native_io_apic_read             NULL
 #define native_io_apic_write            NULL
 #define native_io_apic_modify           NULL
+#define native_disable_io_apic          NULL
+#define native_io_apic_print_entries    NULL
+#define native_ioapic_set_affinity      NULL
+#define native_setup_ioapic_entry       NULL
+#define native_compose_msi_msg          NULL
+#define native_eoi_ioapic_pin           NULL
 #endif
 #endif /* _ASM_X86_IO_APIC_H */
diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
index 5fb9bbbd2f14..95fd3527f632 100644
--- a/arch/x86/include/asm/irq_remapping.h
+++ b/arch/x86/include/asm/irq_remapping.h
@@ -26,8 +26,6 @@
 #ifdef CONFIG_IRQ_REMAP
-extern int irq_remapping_enabled;
 extern void setup_irq_remapping_ops(void);
 extern int irq_remapping_supported(void);
 extern int irq_remapping_prepare(void);
@@ -40,21 +38,19 @@ extern int setup_ioapic_remapped_entry(int irq,
                                       unsigned int destination,
                                       int vector,
                                       struct io_apic_irq_attr *attr);
-extern int set_remapped_irq_affinity(struct irq_data *data,
-                                     const struct cpumask *mask,
-                                     bool force);
 extern void free_remapped_irq(int irq);
 extern void compose_remapped_msi_msg(struct pci_dev *pdev,
                                     unsigned int irq, unsigned int dest,
                                     struct msi_msg *msg, u8 hpet_id);
-extern int msi_alloc_remapped_irq(struct pci_dev *pdev, int irq, int nvec);
-extern int msi_setup_remapped_irq(struct pci_dev *pdev, unsigned int irq,
-                                  int index, int sub_handle);
 extern int setup_hpet_msi_remapped(unsigned int irq, unsigned int id);
+extern void panic_if_irq_remap(const char *msg);
+extern bool setup_remapped_irq(int irq,
+                               struct irq_cfg *cfg,
+                               struct irq_chip *chip);
-#else  /* CONFIG_IRQ_REMAP */
+void irq_remap_modify_chip_defaults(struct irq_chip *chip);
-#define irq_remapping_enabled   0
+#else  /* CONFIG_IRQ_REMAP */
 static inline void setup_irq_remapping_ops(void) { }
 static inline int irq_remapping_supported(void) { return 0; }
@@ -71,30 +67,30 @@ static inline int setup_ioapic_remapped_entry(int irq,
 {
        return -ENODEV;
 }
-static inline int set_remapped_irq_affinity(struct irq_data *data,
-                                            const struct cpumask *mask,
-                                            bool force)
-{
-        return 0;
-}
 static inline void free_remapped_irq(int irq) { }
 static inline void compose_remapped_msi_msg(struct pci_dev *pdev,
                                            unsigned int irq, unsigned int dest,
                                            struct msi_msg *msg, u8 hpet_id)
 {
 }
-static inline int msi_alloc_remapped_irq(struct pci_dev *pdev, int irq, int nvec)
+static inline int setup_hpet_msi_remapped(unsigned int irq, unsigned int id)
 {
        return -ENODEV;
 }
-static inline int msi_setup_remapped_irq(struct pci_dev *pdev, unsigned int irq,
-                                         int index, int sub_handle)
+static inline void panic_if_irq_remap(const char *msg)
+{
+}
+static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
 {
-        return -ENODEV;
 }
-static inline int setup_hpet_msi_remapped(unsigned int irq, unsigned int id)
+static inline bool setup_remapped_irq(int irq,
+                                      struct irq_cfg *cfg,
+                                      struct irq_chip *chip)
 {
-        return -ENODEV;
+        return false;
 }
 #endif /* CONFIG_IRQ_REMAP */
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index 5ed1f16187be..65231e173baf 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -85,13 +85,13 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
        return ret;
 }
-static inline int kvm_para_available(void)
+static inline bool kvm_para_available(void)
 {
        unsigned int eax, ebx, ecx, edx;
        char signature[13];
        if (boot_cpu_data.cpuid_level < 0)
-                return 0;       /* So we don't blow up on old processors */
+                return false;   /* So we don't blow up on old processors */
        if (cpu_has_hypervisor) {
                cpuid(KVM_CPUID_SIGNATURE, &eax, &ebx, &ecx, &edx);
@@ -101,10 +101,10 @@ static inline int kvm_para_available(void)
                signature[12] = 0;
                if (strcmp(signature, "KVMKVMKVM") == 0)
-                        return 1;
+                        return true;
        }
-        return 0;
+        return false;
 }
 static inline unsigned int kvm_arch_para_features(void)
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h
index 48142971b25d..79327e9483a3 100644
--- a/arch/x86/include/asm/linkage.h
+++ b/arch/x86/include/asm/linkage.h
@@ -27,20 +27,20 @@
 #define __asmlinkage_protect0(ret) \
        __asmlinkage_protect_n(ret)
 #define __asmlinkage_protect1(ret, arg1) \
-        __asmlinkage_protect_n(ret, "g" (arg1))
+        __asmlinkage_protect_n(ret, "m" (arg1))
 #define __asmlinkage_protect2(ret, arg1, arg2) \
-        __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2))
+        __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2))
 #define __asmlinkage_protect3(ret, arg1, arg2, arg3) \
-        __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3))
+        __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3))
 #define __asmlinkage_protect4(ret, arg1, arg2, arg3, arg4) \
-        __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \
+        __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3), \
-                              "g" (arg4))
+                              "m" (arg4))
 #define __asmlinkage_protect5(ret, arg1, arg2, arg3, arg4, arg5) \
-        __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \
+        __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3), \
-                              "g" (arg4), "g" (arg5))
+                              "m" (arg4), "m" (arg5))
 #define __asmlinkage_protect6(ret, arg1, arg2, arg3, arg4, arg5, arg6) \
-        __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \
+        __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3), \
-                              "g" (arg4), "g" (arg5), "g" (arg6))
+                              "m" (arg4), "m" (arg5), "m" (arg6))
 #endif /* CONFIG_X86_32 */
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index ecdfee60ee4a..f4076af1f4ed 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -3,6 +3,90 @@
 #include <uapi/asm/mce.h>
+/*
+ * Machine Check support for x86
+ */
+/* MCG_CAP register defines */
+#define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
+#define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
+#define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
+#define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
+#define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
+#define MCG_EXT_CNT_SHIFT       16
+#define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
+#define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
+/* MCG_STATUS register defines */
+#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
+#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
+#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
+/* MCi_STATUS register defines */
+#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
+#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
+#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
+#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
+#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
+#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
+#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
+#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
+#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
+#define MCACOD            0xffff     /* MCA Error Code */
+/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
+#define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
+#define MCACOD_SCRUBMSK 0xfff0
+#define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
+#define MCACOD_DATA     0x0134  /* Data Load */
+#define MCACOD_INSTR    0x0150  /* Instruction Fetch */
+/* MCi_MISC register defines */
+#define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
+#define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
+#define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
+#define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
+#define  MCI_MISC_ADDR_PHYS     2       /* physical address */
+#define  MCI_MISC_ADDR_MEM      3       /* memory address */
+#define  MCI_MISC_ADDR_GENERIC  7       /* generic */
+/* CTL2 register defines */
+#define MCI_CTL2_CMCI_EN                (1ULL << 30)
+#define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
+#define MCJ_CTX_MASK            3
+#define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
+#define MCJ_CTX_RANDOM          0    /* inject context: random */
+#define MCJ_CTX_PROCESS         0x1  /* inject context: process */
+#define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
+#define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
+#define MCJ_EXCEPTION           0x8  /* raise as exception */
+#define MCJ_IRQ_BRAODCAST       0x10 /* do IRQ broadcasting */
+#define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
+/* Software defined banks */
+#define MCE_EXTENDED_BANK       128
+#define MCE_THERMAL_BANK        (MCE_EXTENDED_BANK + 0)
+#define K8_MCE_THRESHOLD_BASE   (MCE_EXTENDED_BANK + 1)
+#define MCE_LOG_LEN 32
+#define MCE_LOG_SIGNATURE       "MACHINECHECK"
+/*
+ * This structure contains all data related to the MCE log.  Also
+ * carries a signature to make it easier to find from external
+ * debugging tools.  Each entry is only valid when its finished flag
+ * is set.
+ */
+struct mce_log {
+        char signature[12]; /* "MACHINECHECK" */
+        unsigned len;       /* = MCE_LOG_LEN */
+        unsigned next;
+        unsigned flags;
+        unsigned recordlen;     /* length of struct mce */
+        struct mce entry[MCE_LOG_LEN];
+};
 struct mca_config {
        bool dont_log_ce;
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index dba7805176bf..c28fd02f4bf7 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -121,9 +121,12 @@ static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq)
 #define arch_teardown_msi_irq x86_teardown_msi_irq
 #define arch_restore_msi_irqs x86_restore_msi_irqs
 /* implemented in arch/x86/kernel/apic/io_apic. */
+struct msi_desc;
 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
 void native_teardown_msi_irq(unsigned int irq);
 void native_restore_msi_irqs(struct pci_dev *dev, int irq);
+int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
+                  unsigned int irq_base, unsigned int irq_offset);
 /* default to the implementation in drivers/lib/msi.c */
 #define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
 #define HAVE_DEFAULT_MSI_RESTORE_IRQS
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 4fabcdf1cfa7..57cb63402213 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -29,8 +29,13 @@
 #define ARCH_PERFMON_EVENTSEL_INV                       (1ULL << 23)
 #define ARCH_PERFMON_EVENTSEL_CMASK                     0xFF000000ULL
-#define AMD_PERFMON_EVENTSEL_GUESTONLY                  (1ULL << 40)
+#define AMD64_EVENTSEL_INT_CORE_ENABLE                  (1ULL << 36)
-#define AMD_PERFMON_EVENTSEL_HOSTONLY                   (1ULL << 41)
+#define AMD64_EVENTSEL_GUESTONLY                        (1ULL << 40)
+#define AMD64_EVENTSEL_HOSTONLY                         (1ULL << 41)
+#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT               37
+#define AMD64_EVENTSEL_INT_CORE_SEL_MASK                \
+        (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
 #define AMD64_EVENTSEL_EVENT    \
        (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
@@ -46,8 +51,12 @@
 #define AMD64_RAW_EVENT_MASK            \
        (X86_RAW_EVENT_MASK          |  \
         AMD64_EVENTSEL_EVENT)
+#define AMD64_RAW_EVENT_MASK_NB         \
+        (AMD64_EVENTSEL_EVENT        |  \
+         ARCH_PERFMON_EVENTSEL_UMASK)
 #define AMD64_NUM_COUNTERS                              4
 #define AMD64_NUM_COUNTERS_CORE                         6
+#define AMD64_NUM_COUNTERS_NB                           4
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL           0x3c
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK         (0x00 << 8)
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 5199db2923d3..fc304279b559 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -142,6 +142,11 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
        return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT;
 }
+static inline unsigned long pud_pfn(pud_t pud)
+{
+        return (pud_val(pud) & PTE_PFN_MASK) >> PAGE_SHIFT;
+}
 #define pte_page(pte)   pfn_to_page(pte_pfn(pte))
 static inline int pmd_large(pmd_t pte)
@@ -781,6 +786,18 @@ static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
       memcpy(dst, src, count * sizeof(pgd_t));
 }
+/*
+ * The x86 doesn't have any external MMU info: the kernel page
+ * tables contain all the necessary information.
+ */
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+                unsigned long addr, pte_t *ptep)
+{
+}
+static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
+                unsigned long addr, pmd_t *pmd)
+{
+}
 #include <asm-generic/pgtable.h>
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
index 8faa215a503e..9ee322103c6d 100644
--- a/arch/x86/include/asm/pgtable_32.h
+++ b/arch/x86/include/asm/pgtable_32.h
@@ -66,13 +66,6 @@ do {						\
        __flush_tlb_one((vaddr));               \
 } while (0)
-/*
- * The i386 doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- */
-#define update_mmu_cache(vma, address, ptep) do { } while (0)
-#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 #endif /* !__ASSEMBLY__ */
 /*
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index 47356f9df82e..615b0c78449f 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -142,9 +142,6 @@ static inline int pgd_large(pgd_t pgd) { return 0; }
 #define pte_offset_map(dir, address) pte_offset_kernel((dir), (address))
 #define pte_unmap(pte) ((void)(pte))/* NOP */
-#define update_mmu_cache(vma, address, ptep) do { } while (0)
-#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 /* Encode and de-code a swap entry */
 #if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE
 #define SWP_TYPE_BITS (_PAGE_BIT_FILE - _PAGE_BIT_PRESENT - 1)
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index 6c7fc25f2c34..5c6e4fb370f5 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -47,6 +47,12 @@
 # define NEED_NOPL      0
 #endif
+#ifdef CONFIG_MATOM
+# define NEED_MOVBE     (1<<(X86_FEATURE_MOVBE & 31))
+#else
+# define NEED_MOVBE     0
+#endif
 #ifdef CONFIG_X86_64
 #ifdef CONFIG_PARAVIRT
 /* Paravirtualized systems may not have PSE or PGE available */
@@ -80,7 +86,7 @@
 #define REQUIRED_MASK2  0
 #define REQUIRED_MASK3  (NEED_NOPL)
-#define REQUIRED_MASK4  0
+#define REQUIRED_MASK4  (NEED_MOVBE)
 #define REQUIRED_MASK5  0
 #define REQUIRED_MASK6  0
 #define REQUIRED_MASK7  0
diff --git a/arch/x86/include/asm/uv/uv.h b/arch/x86/include/asm/uv/uv.h
index b47c2a82ff15..062921ef34e9 100644
--- a/arch/x86/include/asm/uv/uv.h
+++ b/arch/x86/include/asm/uv/uv.h
@@ -16,7 +16,7 @@ extern void uv_system_init(void);
 extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
                                                 struct mm_struct *mm,
                                                 unsigned long start,
-                                                 unsigned end,
+                                                 unsigned long end,
                                                 unsigned int cpu);
 #else   /* X86_UV */
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 57693498519c..7669941cc9d2 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -181,19 +181,38 @@ struct x86_platform_ops {
 };
 struct pci_dev;
+struct msi_msg;
 struct x86_msi_ops {
        int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
+        void (*compose_msi_msg)(struct pci_dev *dev, unsigned int irq,
+                                unsigned int dest, struct msi_msg *msg,
+                               u8 hpet_id);
        void (*teardown_msi_irq)(unsigned int irq);
        void (*teardown_msi_irqs)(struct pci_dev *dev);
        void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
+        int  (*setup_hpet_msi)(unsigned int irq, unsigned int id);
 };
+struct IO_APIC_route_entry;
+struct io_apic_irq_attr;
+struct irq_data;
+struct cpumask;
 struct x86_io_apic_ops {
-        void            (*init)  (void);
+        void            (*init)   (void);
-        unsigned int    (*read)  (unsigned int apic, unsigned int reg);
+        unsigned int    (*read)   (unsigned int apic, unsigned int reg);
-        void            (*write) (unsigned int apic, unsigned int reg, unsigned int value);
+        void            (*write)  (unsigned int apic, unsigned int reg, unsigned int value);
-        void            (*modify)(unsigned int apic, unsigned int reg, unsigned int value);
+        void            (*modify) (unsigned int apic, unsigned int reg, unsigned int value);
+        void            (*disable)(void);
+        void            (*print_entries)(unsigned int apic, unsigned int nr_entries);
+        int             (*set_affinity)(struct irq_data *data,
+                                        const struct cpumask *mask,
+                                        bool force);
+        int             (*setup_entry)(int irq, struct IO_APIC_route_entry *entry,
+                                       unsigned int destination, int vector,
+                                       struct io_apic_irq_attr *attr);
+        void            (*eoi_ioapic_pin)(int apic, int pin, int vector);
 };
 extern struct x86_init_ops x86_init;
diff --git a/arch/x86/include/asm/xor.h b/arch/x86/include/asm/xor.h
index f8fde90bc45e..d8829751b3f8 100644
--- a/arch/x86/include/asm/xor.h
+++ b/arch/x86/include/asm/xor.h
@@ -1,10 +1,499 @@
 #ifdef CONFIG_KMEMCHECK
 /* kmemcheck doesn't handle MMX/SSE/SSE2 instructions */
 # include <asm-generic/xor.h>
+#elif !defined(_ASM_X86_XOR_H)
+#define _ASM_X86_XOR_H
+/*
+ * Optimized RAID-5 checksumming functions for SSE.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * (for example /usr/src/linux/COPYING); if not, write to the Free
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+/*
+ * Cache avoiding checksumming functions utilizing KNI instructions
+ * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
+ */
+/*
+ * Based on
+ * High-speed RAID5 checksumming functions utilizing SSE instructions.
+ * Copyright (C) 1998 Ingo Molnar.
+ */
+/*
+ * x86-64 changes / gcc fixes from Andi Kleen.
+ * Copyright 2002 Andi Kleen, SuSE Labs.
+ *
+ * This hasn't been optimized for the hammer yet, but there are likely
+ * no advantages to be gotten from x86-64 here anyways.
+ */
+#include <asm/i387.h>
+#ifdef CONFIG_X86_32
+/* reduce register pressure */
+# define XOR_CONSTANT_CONSTRAINT "i"
 #else
+# define XOR_CONSTANT_CONSTRAINT "re"
+#endif
+#define OFFS(x)         "16*("#x")"
+#define PF_OFFS(x)      "256+16*("#x")"
+#define PF0(x)          "       prefetchnta "PF_OFFS(x)"(%[p1])         ;\n"
+#define LD(x, y)        "       movaps "OFFS(x)"(%[p1]), %%xmm"#y"      ;\n"
+#define ST(x, y)        "       movaps %%xmm"#y", "OFFS(x)"(%[p1])      ;\n"
+#define PF1(x)          "       prefetchnta "PF_OFFS(x)"(%[p2])         ;\n"
+#define PF2(x)          "       prefetchnta "PF_OFFS(x)"(%[p3])         ;\n"
+#define PF3(x)          "       prefetchnta "PF_OFFS(x)"(%[p4])         ;\n"
+#define PF4(x)          "       prefetchnta "PF_OFFS(x)"(%[p5])         ;\n"
+#define XO1(x, y)       "       xorps "OFFS(x)"(%[p2]), %%xmm"#y"       ;\n"
+#define XO2(x, y)       "       xorps "OFFS(x)"(%[p3]), %%xmm"#y"       ;\n"
+#define XO3(x, y)       "       xorps "OFFS(x)"(%[p4]), %%xmm"#y"       ;\n"
+#define XO4(x, y)       "       xorps "OFFS(x)"(%[p5]), %%xmm"#y"       ;\n"
+#define NOP(x)
+#define BLK64(pf, op, i)                                \
+                pf(i)                                   \
+                op(i, 0)                                \
+                        op(i + 1, 1)                    \
+                                op(i + 2, 2)            \
+                                        op(i + 3, 3)
+static void
+xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i)                                        \
+                LD(i, 0)                                \
+                        LD(i + 1, 1)                    \
+                PF1(i)                                  \
+                                PF1(i + 2)              \
+                                LD(i + 2, 2)            \
+                                        LD(i + 3, 3)    \
+                PF0(i + 4)                              \
+                                PF0(i + 6)              \
+                XO1(i, 0)                               \
+                        XO1(i + 1, 1)                   \
+                                XO1(i + 2, 2)           \
+                                        XO1(i + 3, 3)   \
+                ST(i, 0)                                \
+                        ST(i + 1, 1)                    \
+                                ST(i + 2, 2)            \
+                                        ST(i + 3, 3)    \
+                PF0(0)
+                                PF0(2)
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines),
+          [p1] "+r" (p1), [p2] "+r" (p2)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static void
+xor_sse_2_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i)                        \
+                BLK64(PF0, LD, i)       \
+                BLK64(PF1, XO1, i)      \
+                BLK64(NOP, ST, i)       \
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines),
+          [p1] "+r" (p1), [p2] "+r" (p2)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static void
+xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+          unsigned long *p3)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i) \
+                PF1(i)                                  \
+                                PF1(i + 2)              \
+                LD(i, 0)                                \
+                        LD(i + 1, 1)                    \
+                                LD(i + 2, 2)            \
+                                        LD(i + 3, 3)    \
+                PF2(i)                                  \
+                                PF2(i + 2)              \
+                PF0(i + 4)                              \
+                                PF0(i + 6)              \
+                XO1(i, 0)                               \
+                        XO1(i + 1, 1)                   \
+                                XO1(i + 2, 2)           \
+                                        XO1(i + 3, 3)   \
+                XO2(i, 0)                               \
+                        XO2(i + 1, 1)                   \
+                                XO2(i + 2, 2)           \
+                                        XO2(i + 3, 3)   \
+                ST(i, 0)                                \
+                        ST(i + 1, 1)                    \
+                                ST(i + 2, 2)            \
+                                        ST(i + 3, 3)    \
+                PF0(0)
+                                PF0(2)
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       add %[inc], %[p3]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines),
+          [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static void
+xor_sse_3_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+               unsigned long *p3)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i)                        \
+                BLK64(PF0, LD, i)       \
+                BLK64(PF1, XO1, i)      \
+                BLK64(PF2, XO2, i)      \
+                BLK64(NOP, ST, i)       \
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       add %[inc], %[p3]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines),
+          [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static void
+xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+          unsigned long *p3, unsigned long *p4)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i) \
+                PF1(i)                                  \
+                                PF1(i + 2)              \
+                LD(i, 0)                                \
+                        LD(i + 1, 1)                    \
+                                LD(i + 2, 2)            \
+                                        LD(i + 3, 3)    \
+                PF2(i)                                  \
+                                PF2(i + 2)              \
+                XO1(i, 0)                               \
+                        XO1(i + 1, 1)                   \
+                                XO1(i + 2, 2)           \
+                                        XO1(i + 3, 3)   \
+                PF3(i)                                  \
+                                PF3(i + 2)              \
+                PF0(i + 4)                              \
+                                PF0(i + 6)              \
+                XO2(i, 0)                               \
+                        XO2(i + 1, 1)                   \
+                                XO2(i + 2, 2)           \
+                                        XO2(i + 3, 3)   \
+                XO3(i, 0)                               \
+                        XO3(i + 1, 1)                   \
+                                XO3(i + 2, 2)           \
+                                        XO3(i + 3, 3)   \
+                ST(i, 0)                                \
+                        ST(i + 1, 1)                    \
+                                ST(i + 2, 2)            \
+                                        ST(i + 3, 3)    \
+                PF0(0)
+                                PF0(2)
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       add %[inc], %[p3]       ;\n"
+        "       add %[inc], %[p4]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines), [p1] "+r" (p1),
+          [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static void
+xor_sse_4_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+               unsigned long *p3, unsigned long *p4)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i)                        \
+                BLK64(PF0, LD, i)       \
+                BLK64(PF1, XO1, i)      \
+                BLK64(PF2, XO2, i)      \
+                BLK64(PF3, XO3, i)      \
+                BLK64(NOP, ST, i)       \
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       add %[inc], %[p3]       ;\n"
+        "       add %[inc], %[p4]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines), [p1] "+r" (p1),
+          [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static void
+xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+          unsigned long *p3, unsigned long *p4, unsigned long *p5)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i) \
+                PF1(i)                                  \
+                                PF1(i + 2)              \
+                LD(i, 0)                                \
+                        LD(i + 1, 1)                    \
+                                LD(i + 2, 2)            \
+                                        LD(i + 3, 3)    \
+                PF2(i)                                  \
+                                PF2(i + 2)              \
+                XO1(i, 0)                               \
+                        XO1(i + 1, 1)                   \
+                                XO1(i + 2, 2)           \
+                                        XO1(i + 3, 3)   \
+                PF3(i)                                  \
+                                PF3(i + 2)              \
+                XO2(i, 0)                               \
+                        XO2(i + 1, 1)                   \
+                                XO2(i + 2, 2)           \
+                                        XO2(i + 3, 3)   \
+                PF4(i)                                  \
+                                PF4(i + 2)              \
+                PF0(i + 4)                              \
+                                PF0(i + 6)              \
+                XO3(i, 0)                               \
+                        XO3(i + 1, 1)                   \
+                                XO3(i + 2, 2)           \
+                                        XO3(i + 3, 3)   \
+                XO4(i, 0)                               \
+                        XO4(i + 1, 1)                   \
+                                XO4(i + 2, 2)           \
+                                        XO4(i + 3, 3)   \
+                ST(i, 0)                                \
+                        ST(i + 1, 1)                    \
+                                ST(i + 2, 2)            \
+                                        ST(i + 3, 3)    \
+                PF0(0)
+                                PF0(2)
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       add %[inc], %[p3]       ;\n"
+        "       add %[inc], %[p4]       ;\n"
+        "       add %[inc], %[p5]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines), [p1] "+r" (p1), [p2] "+r" (p2),
+          [p3] "+r" (p3), [p4] "+r" (p4), [p5] "+r" (p5)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static void
+xor_sse_5_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+               unsigned long *p3, unsigned long *p4, unsigned long *p5)
+{
+        unsigned long lines = bytes >> 8;
+        kernel_fpu_begin();
+        asm volatile(
+#undef BLOCK
+#define BLOCK(i)                        \
+                BLK64(PF0, LD, i)       \
+                BLK64(PF1, XO1, i)      \
+                BLK64(PF2, XO2, i)      \
+                BLK64(PF3, XO3, i)      \
+                BLK64(PF4, XO4, i)      \
+                BLK64(NOP, ST, i)       \
+        " .align 32                     ;\n"
+        " 1:                            ;\n"
+                BLOCK(0)
+                BLOCK(4)
+                BLOCK(8)
+                BLOCK(12)
+        "       add %[inc], %[p1]       ;\n"
+        "       add %[inc], %[p2]       ;\n"
+        "       add %[inc], %[p3]       ;\n"
+        "       add %[inc], %[p4]       ;\n"
+        "       add %[inc], %[p5]       ;\n"
+        "       dec %[cnt]              ;\n"
+        "       jnz 1b                  ;\n"
+        : [cnt] "+r" (lines), [p1] "+r" (p1), [p2] "+r" (p2),
+          [p3] "+r" (p3), [p4] "+r" (p4), [p5] "+r" (p5)
+        : [inc] XOR_CONSTANT_CONSTRAINT (256UL)
+        : "memory");
+        kernel_fpu_end();
+}
+static struct xor_block_template xor_block_sse_pf64 = {
+        .name = "prefetch64-sse",
+        .do_2 = xor_sse_2_pf64,
+        .do_3 = xor_sse_3_pf64,
+        .do_4 = xor_sse_4_pf64,
+        .do_5 = xor_sse_5_pf64,
+};
+#undef LD
+#undef XO1
+#undef XO2
+#undef XO3
+#undef XO4
+#undef ST
+#undef NOP
+#undef BLK64
+#undef BLOCK
+#undef XOR_CONSTANT_CONSTRAINT
 #ifdef CONFIG_X86_32
 # include <asm/xor_32.h>
 #else
 # include <asm/xor_64.h>
 #endif
-#endif
+#define XOR_SELECT_TEMPLATE(FASTEST) \
+        AVX_SELECT(FASTEST)
+#endif /* _ASM_X86_XOR_H */
diff --git a/arch/x86/include/asm/xor_32.h b/arch/x86/include/asm/xor_32.h
index f79cb7ec0e06..ce05722e3c68 100644
--- a/arch/x86/include/asm/xor_32.h
+++ b/arch/x86/include/asm/xor_32.h
@@ -2,7 +2,7 @@
 #define _ASM_X86_XOR_32_H
 /*
- * Optimized RAID-5 checksumming functions for MMX and SSE.
+ * Optimized RAID-5 checksumming functions for MMX.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -529,290 +529,6 @@ static struct xor_block_template xor_block_p5_mmx = {
        .do_5 = xor_p5_mmx_5,
 };
-/*
- * Cache avoiding checksumming functions utilizing KNI instructions
- * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
- */
-#define OFFS(x)         "16*("#x")"
-#define PF_OFFS(x)      "256+16*("#x")"
-#define PF0(x)          "       prefetchnta "PF_OFFS(x)"(%1)            ;\n"
-#define LD(x, y)        "       movaps   "OFFS(x)"(%1), %%xmm"#y"       ;\n"
-#define ST(x, y)        "       movaps %%xmm"#y",   "OFFS(x)"(%1)       ;\n"
-#define PF1(x)          "       prefetchnta "PF_OFFS(x)"(%2)            ;\n"
-#define PF2(x)          "       prefetchnta "PF_OFFS(x)"(%3)            ;\n"
-#define PF3(x)          "       prefetchnta "PF_OFFS(x)"(%4)            ;\n"
-#define PF4(x)          "       prefetchnta "PF_OFFS(x)"(%5)            ;\n"
-#define PF5(x)          "       prefetchnta "PF_OFFS(x)"(%6)            ;\n"
-#define XO1(x, y)       "       xorps   "OFFS(x)"(%2), %%xmm"#y"        ;\n"
-#define XO2(x, y)       "       xorps   "OFFS(x)"(%3), %%xmm"#y"        ;\n"
-#define XO3(x, y)       "       xorps   "OFFS(x)"(%4), %%xmm"#y"        ;\n"
-#define XO4(x, y)       "       xorps   "OFFS(x)"(%5), %%xmm"#y"        ;\n"
-#define XO5(x, y)       "       xorps   "OFFS(x)"(%6), %%xmm"#y"        ;\n"
-static void
-xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
-{
-        unsigned long lines = bytes >> 8;
-        kernel_fpu_begin();
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i)                                        \
-                LD(i, 0)                                \
-                        LD(i + 1, 1)                    \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO1(i, 0)                               \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                ST(i, 0)                                \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addl $256, %1           ;\n"
-        "       addl $256, %2           ;\n"
-        "       decl %0                 ;\n"
-        "       jnz 1b                  ;\n"
-        : "+r" (lines),
-          "+r" (p1), "+r" (p2)
-        :
-        : "memory");
-        kernel_fpu_end();
-}
-static void
-xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-          unsigned long *p3)
-{
-        unsigned long lines = bytes >> 8;
-        kernel_fpu_begin();
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                LD(i,0)                                 \
-                        LD(i + 1, 1)                    \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF2(i)                                  \
-                                PF2(i + 2)              \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO1(i,0)                                \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                XO2(i,0)                                \
-                        XO2(i + 1, 1)                   \
-                                XO2(i + 2, 2)           \
-                                        XO2(i + 3, 3)   \
-                ST(i,0)                                 \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addl $256, %1           ;\n"
-        "       addl $256, %2           ;\n"
-        "       addl $256, %3           ;\n"
-        "       decl %0                 ;\n"
-        "       jnz 1b                  ;\n"
-        : "+r" (lines),
-          "+r" (p1), "+r"(p2), "+r"(p3)
-        :
-        : "memory" );
-        kernel_fpu_end();
-}
-static void
-xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-          unsigned long *p3, unsigned long *p4)
-{
-        unsigned long lines = bytes >> 8;
-        kernel_fpu_begin();
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                LD(i,0)                                 \
-                        LD(i + 1, 1)                    \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF2(i)                                  \
-                                PF2(i + 2)              \
-                XO1(i,0)                                \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                PF3(i)                                  \
-                                PF3(i + 2)              \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO2(i,0)                                \
-                        XO2(i + 1, 1)                   \
-                                XO2(i + 2, 2)           \
-                                        XO2(i + 3, 3)   \
-                XO3(i,0)                                \
-                        XO3(i + 1, 1)                   \
-                                XO3(i + 2, 2)           \
-                                        XO3(i + 3, 3)   \
-                ST(i,0)                                 \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addl $256, %1           ;\n"
-        "       addl $256, %2           ;\n"
-        "       addl $256, %3           ;\n"
-        "       addl $256, %4           ;\n"
-        "       decl %0                 ;\n"
-        "       jnz 1b                  ;\n"
-        : "+r" (lines),
-          "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4)
-        :
-        : "memory" );
-        kernel_fpu_end();
-}
-static void
-xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-          unsigned long *p3, unsigned long *p4, unsigned long *p5)
-{
-        unsigned long lines = bytes >> 8;
-        kernel_fpu_begin();
-        /* Make sure GCC forgets anything it knows about p4 or p5,
-           such that it won't pass to the asm volatile below a
-           register that is shared with any other variable.  That's
-           because we modify p4 and p5 there, but we can't mark them
-           as read/write, otherwise we'd overflow the 10-asm-operands
-           limit of GCC < 3.1.  */
-        asm("" : "+r" (p4), "+r" (p5));
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                LD(i,0)                                 \
-                        LD(i + 1, 1)                    \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF2(i)                                  \
-                                PF2(i + 2)              \
-                XO1(i,0)                                \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                PF3(i)                                  \
-                                PF3(i + 2)              \
-                XO2(i,0)                                \
-                        XO2(i + 1, 1)                   \
-                                XO2(i + 2, 2)           \
-                                        XO2(i + 3, 3)   \
-                PF4(i)                                  \
-                                PF4(i + 2)              \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO3(i,0)                                \
-                        XO3(i + 1, 1)                   \
-                                XO3(i + 2, 2)           \
-                                        XO3(i + 3, 3)   \
-                XO4(i,0)                                \
-                        XO4(i + 1, 1)                   \
-                                XO4(i + 2, 2)           \
-                                        XO4(i + 3, 3)   \
-                ST(i,0)                                 \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addl $256, %1           ;\n"
-        "       addl $256, %2           ;\n"
-        "       addl $256, %3           ;\n"
-        "       addl $256, %4           ;\n"
-        "       addl $256, %5           ;\n"
-        "       decl %0                 ;\n"
-        "       jnz 1b                  ;\n"
-        : "+r" (lines),
-          "+r" (p1), "+r" (p2), "+r" (p3)
-        : "r" (p4), "r" (p5)
-        : "memory");
-        /* p4 and p5 were modified, and now the variables are dead.
-           Clobber them just to be sure nobody does something stupid
-           like assuming they have some legal value.  */
-        asm("" : "=r" (p4), "=r" (p5));
-        kernel_fpu_end();
-}
 static struct xor_block_template xor_block_pIII_sse = {
        .name = "pIII_sse",
        .do_2 = xor_sse_2,
@@ -827,26 +543,25 @@ static struct xor_block_template xor_block_pIII_sse = {
 /* Also try the generic routines.  */
 #include <asm-generic/xor.h>
+/* We force the use of the SSE xor block because it can write around L2.
+   We may also be able to load into the L1 only depending on how the cpu
+   deals with a load to a line that is being prefetched.  */
 #undef XOR_TRY_TEMPLATES
 #define XOR_TRY_TEMPLATES                               \
 do {                                                    \
-        xor_speed(&xor_block_8regs);                    \
-        xor_speed(&xor_block_8regs_p);                  \
-        xor_speed(&xor_block_32regs);                   \
-        xor_speed(&xor_block_32regs_p);                 \
        AVX_XOR_SPEED;                                  \
-        if (cpu_has_xmm)                                \
+        if (cpu_has_xmm) {                              \
                xor_speed(&xor_block_pIII_sse);         \
-        if (cpu_has_mmx) {                              \
+                xor_speed(&xor_block_sse_pf64);         \
+        } else if (cpu_has_mmx) {                       \
                xor_speed(&xor_block_pII_mmx);          \
                xor_speed(&xor_block_p5_mmx);           \
+        } else {                                        \
+                xor_speed(&xor_block_8regs);            \
+                xor_speed(&xor_block_8regs_p);          \
+                xor_speed(&xor_block_32regs);           \
+                xor_speed(&xor_block_32regs_p);         \
        }                                               \
 } while (0)
-/* We force the use of the SSE xor block because it can write around L2.
-   We may also be able to load into the L1 only depending on how the cpu
-   deals with a load to a line that is being prefetched.  */
-#define XOR_SELECT_TEMPLATE(FASTEST)                    \
-        AVX_SELECT(cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
 #endif /* _ASM_X86_XOR_32_H */
diff --git a/arch/x86/include/asm/xor_64.h b/arch/x86/include/asm/xor_64.h
index 87ac522c4af5..546f1e3b87cc 100644
--- a/arch/x86/include/asm/xor_64.h
+++ b/arch/x86/include/asm/xor_64.h
@@ -1,301 +1,6 @@
 #ifndef _ASM_X86_XOR_64_H
 #define _ASM_X86_XOR_64_H
-/*
- * Optimized RAID-5 checksumming functions for MMX and SSE.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * You should have received a copy of the GNU General Public License
- * (for example /usr/src/linux/COPYING); if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-/*
- * Cache avoiding checksumming functions utilizing KNI instructions
- * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
- */
-/*
- * Based on
- * High-speed RAID5 checksumming functions utilizing SSE instructions.
- * Copyright (C) 1998 Ingo Molnar.
- */
-/*
- * x86-64 changes / gcc fixes from Andi Kleen.
- * Copyright 2002 Andi Kleen, SuSE Labs.
- *
- * This hasn't been optimized for the hammer yet, but there are likely
- * no advantages to be gotten from x86-64 here anyways.
- */
-#include <asm/i387.h>
-#define OFFS(x)         "16*("#x")"
-#define PF_OFFS(x)      "256+16*("#x")"
-#define PF0(x)          "       prefetchnta "PF_OFFS(x)"(%[p1])         ;\n"
-#define LD(x, y)        "       movaps   "OFFS(x)"(%[p1]), %%xmm"#y"    ;\n"
-#define ST(x, y)        "       movaps %%xmm"#y",   "OFFS(x)"(%[p1])    ;\n"
-#define PF1(x)          "       prefetchnta "PF_OFFS(x)"(%[p2])         ;\n"
-#define PF2(x)          "       prefetchnta "PF_OFFS(x)"(%[p3])         ;\n"
-#define PF3(x)          "       prefetchnta "PF_OFFS(x)"(%[p4])         ;\n"
-#define PF4(x)          "       prefetchnta "PF_OFFS(x)"(%[p5])         ;\n"
-#define PF5(x)          "       prefetchnta "PF_OFFS(x)"(%[p6])         ;\n"
-#define XO1(x, y)       "       xorps   "OFFS(x)"(%[p2]), %%xmm"#y"     ;\n"
-#define XO2(x, y)       "       xorps   "OFFS(x)"(%[p3]), %%xmm"#y"     ;\n"
-#define XO3(x, y)       "       xorps   "OFFS(x)"(%[p4]), %%xmm"#y"     ;\n"
-#define XO4(x, y)       "       xorps   "OFFS(x)"(%[p5]), %%xmm"#y"     ;\n"
-#define XO5(x, y)       "       xorps   "OFFS(x)"(%[p6]), %%xmm"#y"     ;\n"
-static void
-xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
-{
-        unsigned int lines = bytes >> 8;
-        kernel_fpu_begin();
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-                LD(i, 0)                                \
-                        LD(i + 1, 1)                    \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO1(i, 0)                               \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                ST(i, 0)                                \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addq %[inc], %[p1]           ;\n"
-        "       addq %[inc], %[p2]           ;\n"
-                "               decl %[cnt] ; jnz 1b"
-        : [p1] "+r" (p1), [p2] "+r" (p2), [cnt] "+r" (lines)
-        : [inc] "r" (256UL)
-        : "memory");
-        kernel_fpu_end();
-}
-static void
-xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-          unsigned long *p3)
-{
-        unsigned int lines = bytes >> 8;
-        kernel_fpu_begin();
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                LD(i, 0)                                        \
-                        LD(i + 1, 1)                    \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF2(i)                                  \
-                                PF2(i + 2)              \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO1(i, 0)                               \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                XO2(i, 0)                               \
-                        XO2(i + 1, 1)                   \
-                                XO2(i + 2, 2)           \
-                                        XO2(i + 3, 3)   \
-                ST(i, 0)                                \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addq %[inc], %[p1]           ;\n"
-        "       addq %[inc], %[p2]          ;\n"
-        "       addq %[inc], %[p3]           ;\n"
-                "               decl %[cnt] ; jnz 1b"
-        : [cnt] "+r" (lines),
-          [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
-        : [inc] "r" (256UL)
-        : "memory");
-        kernel_fpu_end();
-}
-static void
-xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-          unsigned long *p3, unsigned long *p4)
-{
-        unsigned int lines = bytes >> 8;
-        kernel_fpu_begin();
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                LD(i, 0)                                \
-                        LD(i + 1, 1)                    \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF2(i)                                  \
-                                PF2(i + 2)              \
-                XO1(i, 0)                               \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                PF3(i)                                  \
-                                PF3(i + 2)              \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO2(i, 0)                               \
-                        XO2(i + 1, 1)                   \
-                                XO2(i + 2, 2)           \
-                                        XO2(i + 3, 3)   \
-                XO3(i, 0)                               \
-                        XO3(i + 1, 1)                   \
-                                XO3(i + 2, 2)           \
-                                        XO3(i + 3, 3)   \
-                ST(i, 0)                                \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addq %[inc], %[p1]           ;\n"
-        "       addq %[inc], %[p2]           ;\n"
-        "       addq %[inc], %[p3]           ;\n"
-        "       addq %[inc], %[p4]           ;\n"
-        "       decl %[cnt] ; jnz 1b"
-        : [cnt] "+c" (lines),
-          [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
-        : [inc] "r" (256UL)
-        : "memory" );
-        kernel_fpu_end();
-}
-static void
-xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
-          unsigned long *p3, unsigned long *p4, unsigned long *p5)
-{
-        unsigned int lines = bytes >> 8;
-        kernel_fpu_begin();
-        asm volatile(
-#undef BLOCK
-#define BLOCK(i) \
-                PF1(i)                                  \
-                                PF1(i + 2)              \
-                LD(i, 0)                                \
-                        LD(i + 1, 1)                    \
-                                LD(i + 2, 2)            \
-                                        LD(i + 3, 3)    \
-                PF2(i)                                  \
-                                PF2(i + 2)              \
-                XO1(i, 0)                               \
-                        XO1(i + 1, 1)                   \
-                                XO1(i + 2, 2)           \
-                                        XO1(i + 3, 3)   \
-                PF3(i)                                  \
-                                PF3(i + 2)              \
-                XO2(i, 0)                               \
-                        XO2(i + 1, 1)                   \
-                                XO2(i + 2, 2)           \
-                                        XO2(i + 3, 3)   \
-                PF4(i)                                  \
-                                PF4(i + 2)              \
-                PF0(i + 4)                              \
-                                PF0(i + 6)              \
-                XO3(i, 0)                               \
-                        XO3(i + 1, 1)                   \
-                                XO3(i + 2, 2)           \
-                                        XO3(i + 3, 3)   \
-                XO4(i, 0)                               \
-                        XO4(i + 1, 1)                   \
-                                XO4(i + 2, 2)           \
-                                        XO4(i + 3, 3)   \
-                ST(i, 0)                                \
-                        ST(i + 1, 1)                    \
-                                ST(i + 2, 2)            \
-                                        ST(i + 3, 3)    \
-                PF0(0)
-                                PF0(2)
-        " .align 32                     ;\n"
-        " 1:                            ;\n"
-                BLOCK(0)
-                BLOCK(4)
-                BLOCK(8)
-                BLOCK(12)
-        "       addq %[inc], %[p1]           ;\n"
-        "       addq %[inc], %[p2]           ;\n"
-        "       addq %[inc], %[p3]           ;\n"
-        "       addq %[inc], %[p4]           ;\n"
-        "       addq %[inc], %[p5]           ;\n"
-        "       decl %[cnt] ; jnz 1b"
-        : [cnt] "+c" (lines),
-          [p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4),
-          [p5] "+r" (p5)
-        : [inc] "r" (256UL)
-        : "memory");
-        kernel_fpu_end();
-}
 static struct xor_block_template xor_block_sse = {
        .name = "generic_sse",
        .do_2 = xor_sse_2,
@@ -308,17 +13,15 @@ static struct xor_block_template xor_block_sse = {
 /* Also try the AVX routines */
 #include <asm/xor_avx.h>
+/* We force the use of the SSE xor block because it can write around L2.
+   We may also be able to load into the L1 only depending on how the cpu
+   deals with a load to a line that is being prefetched.  */
 #undef XOR_TRY_TEMPLATES
 #define XOR_TRY_TEMPLATES                       \
 do {                                            \
        AVX_XOR_SPEED;                          \
+        xor_speed(&xor_block_sse_pf64);         \
        xor_speed(&xor_block_sse);              \
 } while (0)
-/* We force the use of the SSE xor block because it can write around L2.
-   We may also be able to load into the L1 only depending on how the cpu
-   deals with a load to a line that is being prefetched.  */
-#define XOR_SELECT_TEMPLATE(FASTEST) \
-        AVX_SELECT(&xor_block_sse)
 #endif /* _ASM_X86_XOR_64_H */
diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mce.h
index 58c829871c31..a0eab85ce7b8 100644
--- a/arch/x86/include/uapi/asm/mce.h
+++ b/arch/x86/include/uapi/asm/mce.h
@@ -4,66 +4,6 @@
 #include <linux/types.h>
 #include <asm/ioctls.h>
-/*
- * Machine Check support for x86
- */
-/* MCG_CAP register defines */
-#define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
-#define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
-#define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
-#define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
-#define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
-#define MCG_EXT_CNT_SHIFT       16
-#define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
-#define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
-/* MCG_STATUS register defines */
-#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
-#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
-#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
-/* MCi_STATUS register defines */
-#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
-#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
-#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
-#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
-#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
-#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
-#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
-#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
-#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
-#define MCACOD            0xffff     /* MCA Error Code */
-/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
-#define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
-#define MCACOD_SCRUBMSK 0xfff0
-#define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
-#define MCACOD_DATA     0x0134  /* Data Load */
-#define MCACOD_INSTR    0x0150  /* Instruction Fetch */
-/* MCi_MISC register defines */
-#define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
-#define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
-#define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
-#define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
-#define  MCI_MISC_ADDR_PHYS     2       /* physical address */
-#define  MCI_MISC_ADDR_MEM      3       /* memory address */
-#define  MCI_MISC_ADDR_GENERIC  7       /* generic */
-/* CTL2 register defines */
-#define MCI_CTL2_CMCI_EN                (1ULL << 30)
-#define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
-#define MCJ_CTX_MASK            3
-#define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
-#define MCJ_CTX_RANDOM          0    /* inject context: random */
-#define MCJ_CTX_PROCESS         0x1  /* inject context: process */
-#define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
-#define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
-#define MCJ_EXCEPTION           0x8  /* raise as exception */
-#define MCJ_IRQ_BRAODCAST       0x10 /* do IRQ broadcasting */
 /* Fields are zero when not available */
 struct mce {
        __u64 status;
@@ -87,35 +27,8 @@ struct mce {
        __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
 };
-/*
- * This structure contains all data related to the MCE log.  Also
- * carries a signature to make it easier to find from external
- * debugging tools.  Each entry is only valid when its finished flag
- * is set.
- */
-#define MCE_LOG_LEN 32
-struct mce_log {
-        char signature[12]; /* "MACHINECHECK" */
-        unsigned len;       /* = MCE_LOG_LEN */
-        unsigned next;
-        unsigned flags;
-        unsigned recordlen;     /* length of struct mce */
-        struct mce entry[MCE_LOG_LEN];
-};
-#define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
-#define MCE_LOG_SIGNATURE       "MACHINECHECK"
 #define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
 #define MCE_GET_LOG_LEN      _IOR('M', 2, int)
 #define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
-/* Software defined banks */
-#define MCE_EXTENDED_BANK       128
-#define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
-#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)
 #endif /* _UAPI_ASM_X86_MCE_H */
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 433a59fb1a74..075a40255591 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -194,6 +194,8 @@
 /* Fam 15h MSRs */
 #define MSR_F15H_PERF_CTL               0xc0010200
 #define MSR_F15H_PERF_CTR               0xc0010201
+#define MSR_F15H_NB_PERF_CTL            0xc0010240
+#define MSR_F15H_NB_PERF_CTR            0xc0010241
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE       0xc0010058
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 34e923a53762..ac3b3d002833 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -65,8 +65,7 @@ obj-$(CONFIG_X86_TSC)		+= trace_clock.o
 obj-$(CONFIG_KEXEC)             += machine_kexec_$(BITS).o
 obj-$(CONFIG_KEXEC)             += relocate_kernel_$(BITS).o crash.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump_$(BITS).o
-obj-$(CONFIG_KPROBES)           += kprobes.o
+obj-y                           += kprobes/
-obj-$(CONFIG_OPTPROBES)         += kprobes-opt.o
 obj-$(CONFIG_MODULES)           += module.o
 obj-$(CONFIG_DOUBLEFAULT)       += doublefault_32.o
 obj-$(CONFIG_KGDB)              += kgdb.o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b994cc84aa7e..a5b4dce1b7ac 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1477,8 +1477,7 @@ void __init bsp_end_local_APIC_setup(void)
         * Now that local APIC setup is completed for BP, configure the fault
         * handling for interrupt remapping.
         */
-        if (irq_remapping_enabled)
+        irq_remap_enable_fault_handling();
-                irq_remap_enable_fault_handling();
 }
@@ -2251,8 +2250,7 @@ static int lapic_suspend(void)
        local_irq_save(flags);
        disable_local_APIC();
-        if (irq_remapping_enabled)
+        irq_remapping_disable();
-                irq_remapping_disable();
        local_irq_restore(flags);
        return 0;
@@ -2268,16 +2266,15 @@ static void lapic_resume(void)
                return;
        local_irq_save(flags);
-        if (irq_remapping_enabled) {
-                /*
+        /*
-                 * IO-APIC and PIC have their own resume routines.
+         * IO-APIC and PIC have their own resume routines.
-                 * We just mask them here to make sure the interrupt
+         * We just mask them here to make sure the interrupt
-                 * subsystem is completely quiet while we enable x2apic
+         * subsystem is completely quiet while we enable x2apic
-                 * and interrupt-remapping.
+         * and interrupt-remapping.
-                 */
+         */
-                mask_ioapic_entries();
+        mask_ioapic_entries();
-                legacy_pic->mask_all();
+        legacy_pic->mask_all();
-        }
        if (x2apic_mode)
                enable_x2apic();
@@ -2320,8 +2317,7 @@ static void lapic_resume(void)
        apic_write(APIC_ESR, 0);
        apic_read(APIC_ESR);
-        if (irq_remapping_enabled)
+        irq_remapping_reenable(x2apic_mode);
-                irq_remapping_reenable(x2apic_mode);
        local_irq_restore(flags);
 }
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index b739d398bb29..9ed796ccc32c 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -68,22 +68,6 @@
 #define for_each_irq_pin(entry, head) \
        for (entry = head; entry; entry = entry->next)
-#ifdef CONFIG_IRQ_REMAP
-static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
-static inline bool irq_remapped(struct irq_cfg *cfg)
-{
-        return cfg->irq_2_iommu.iommu != NULL;
-}
-#else
-static inline bool irq_remapped(struct irq_cfg *cfg)
-{
-        return false;
-}
-static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
-{
-}
-#endif
 /*
 *      Is the SiS APIC rmw bug present ?
 *      -1 = don't know, 0 = no, 1 = yes
@@ -300,9 +284,9 @@ static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
        return cfg;
 }
-static int alloc_irq_from(unsigned int from, int node)
+static int alloc_irqs_from(unsigned int from, unsigned int count, int node)
 {
-        return irq_alloc_desc_from(from, node);
+        return irq_alloc_descs_from(from, count, node);
 }
 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
@@ -326,7 +310,7 @@ static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
                + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
 }
-static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
+void io_apic_eoi(unsigned int apic, unsigned int vector)
 {
        struct io_apic __iomem *io_apic = io_apic_base(apic);
        writel(vector, &io_apic->eoi);
@@ -573,19 +557,10 @@ static void unmask_ioapic_irq(struct irq_data *data)
 * Otherwise, we simulate the EOI message manually by changing the trigger
 * mode to edge and then back to level, with RTE being masked during this.
 */
-static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
+void native_eoi_ioapic_pin(int apic, int pin, int vector)
 {
        if (mpc_ioapic_ver(apic) >= 0x20) {
-                /*
+                io_apic_eoi(apic, vector);
-                 * Intr-remapping uses pin number as the virtual vector
-                 * in the RTE. Actual vector is programmed in
-                 * intr-remapping table entry. Hence for the io-apic
-                 * EOI we use the pin number.
-                 */
-                if (cfg && irq_remapped(cfg))
-                        io_apic_eoi(apic, pin);
-                else
-                        io_apic_eoi(apic, vector);
        } else {
                struct IO_APIC_route_entry entry, entry1;
@@ -606,14 +581,15 @@ static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
        }
 }
-static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
+void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
 {
        struct irq_pin_list *entry;
        unsigned long flags;
        raw_spin_lock_irqsave(&ioapic_lock, flags);
        for_each_irq_pin(entry, cfg->irq_2_pin)
-                __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
+                x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
+                                               cfg->vector);
        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 }
@@ -650,7 +626,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
                }
                raw_spin_lock_irqsave(&ioapic_lock, flags);
-                __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
+                x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector);
                raw_spin_unlock_irqrestore(&ioapic_lock, flags);
        }
@@ -1304,25 +1280,18 @@ static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
                fasteoi = false;
        }
-        if (irq_remapped(cfg)) {
+        if (setup_remapped_irq(irq, cfg, chip))
-                irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
-                irq_remap_modify_chip_defaults(chip);
                fasteoi = trigger != 0;
-        }
        hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
        irq_set_chip_and_handler_name(irq, chip, hdl,
                                      fasteoi ? "fasteoi" : "edge");
 }
-static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
+int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
-                               unsigned int destination, int vector,
+                              unsigned int destination, int vector,
-                               struct io_apic_irq_attr *attr)
+                              struct io_apic_irq_attr *attr)
 {
-        if (irq_remapping_enabled)
-                return setup_ioapic_remapped_entry(irq, entry, destination,
-                                                   vector, attr);
        memset(entry, 0, sizeof(*entry));
        entry->delivery_mode = apic->irq_delivery_mode;
@@ -1370,8 +1339,8 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
                    attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
                    cfg->vector, irq, attr->trigger, attr->polarity, dest);
-        if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
+        if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
-                pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
+                pr_warn("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
                        mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
                __clear_irq_vector(irq, cfg);
@@ -1479,9 +1448,6 @@ static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
        struct IO_APIC_route_entry entry;
        unsigned int dest;
-        if (irq_remapping_enabled)
-                return;
        memset(&entry, 0, sizeof(entry));
        /*
@@ -1513,9 +1479,63 @@ static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
        ioapic_write_entry(ioapic_idx, pin, entry);
 }
-__apicdebuginit(void) print_IO_APIC(int ioapic_idx)
+void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
 {
        int i;
+        pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
+        for (i = 0; i <= nr_entries; i++) {
+                struct IO_APIC_route_entry entry;
+                entry = ioapic_read_entry(apic, i);
+                pr_debug(" %02x %02X  ", i, entry.dest);
+                pr_cont("%1d    %1d    %1d   %1d   %1d    "
+                        "%1d    %1d    %02X\n",
+                        entry.mask,
+                        entry.trigger,
+                        entry.irr,
+                        entry.polarity,
+                        entry.delivery_status,
+                        entry.dest_mode,
+                        entry.delivery_mode,
+                        entry.vector);
+        }
+}
+void intel_ir_io_apic_print_entries(unsigned int apic,
+                                    unsigned int nr_entries)
+{
+        int i;
+        pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
+        for (i = 0; i <= nr_entries; i++) {
+                struct IR_IO_APIC_route_entry *ir_entry;
+                struct IO_APIC_route_entry entry;
+                entry = ioapic_read_entry(apic, i);
+                ir_entry = (struct IR_IO_APIC_route_entry *)&entry;
+                pr_debug(" %02x %04X ", i, ir_entry->index);
+                pr_cont("%1d   %1d    %1d    %1d   %1d   "
+                        "%1d    %1d     %X    %02X\n",
+                        ir_entry->format,
+                        ir_entry->mask,
+                        ir_entry->trigger,
+                        ir_entry->irr,
+                        ir_entry->polarity,
+                        ir_entry->delivery_status,
+                        ir_entry->index2,
+                        ir_entry->zero,
+                        ir_entry->vector);
+        }
+}
+__apicdebuginit(void) print_IO_APIC(int ioapic_idx)
+{
        union IO_APIC_reg_00 reg_00;
        union IO_APIC_reg_01 reg_01;
        union IO_APIC_reg_02 reg_02;
@@ -1568,58 +1588,7 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
        printk(KERN_DEBUG ".... IRQ redirection table:\n");
-        if (irq_remapping_enabled) {
+        x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries);
-                printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
-                        " Pol Stat Indx2 Zero Vect:\n");
-        } else {
-                printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
-                        " Stat Dmod Deli Vect:\n");
-        }
-        for (i = 0; i <= reg_01.bits.entries; i++) {
-                if (irq_remapping_enabled) {
-                        struct IO_APIC_route_entry entry;
-                        struct IR_IO_APIC_route_entry *ir_entry;
-                        entry = ioapic_read_entry(ioapic_idx, i);
-                        ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
-                        printk(KERN_DEBUG " %02x %04X ",
-                                i,
-                                ir_entry->index
-                        );
-                        pr_cont("%1d   %1d    %1d    %1d   %1d   "
-                                "%1d    %1d     %X    %02X\n",
-                                ir_entry->format,
-                                ir_entry->mask,
-                                ir_entry->trigger,
-                                ir_entry->irr,
-                                ir_entry->polarity,
-                                ir_entry->delivery_status,
-                                ir_entry->index2,
-                                ir_entry->zero,
-                                ir_entry->vector
-                        );
-                } else {
-                        struct IO_APIC_route_entry entry;
-                        entry = ioapic_read_entry(ioapic_idx, i);
-                        printk(KERN_DEBUG " %02x %02X  ",
-                                i,
-                                entry.dest
-                        );
-                        pr_cont("%1d    %1d    %1d   %1d   %1d    "
-                                "%1d    %1d    %02X\n",
-                                entry.mask,
-                                entry.trigger,
-                                entry.irr,
-                                entry.polarity,
-                                entry.delivery_status,
-                                entry.dest_mode,
-                                entry.delivery_mode,
-                                entry.vector
-                        );
-                }
-        }
 }
 __apicdebuginit(void) print_IO_APICs(void)
@@ -1921,30 +1890,14 @@ void __init enable_IO_APIC(void)
        clear_IO_APIC();
 }
-/*
+void native_disable_io_apic(void)
- * Not an __init, needed by the reboot code
- */
-void disable_IO_APIC(void)
 {
        /*
-         * Clear the IO-APIC before rebooting:
-         */
-        clear_IO_APIC();
-        if (!legacy_pic->nr_legacy_irqs)
-                return;
-        /*
         * If the i8259 is routed through an IOAPIC
         * Put that IOAPIC in virtual wire mode
         * so legacy interrupts can be delivered.
-         *
-         * With interrupt-remapping, for now we will use virtual wire A mode,
-         * as virtual wire B is little complex (need to configure both
-         * IOAPIC RTE as well as interrupt-remapping table entry).
-         * As this gets called during crash dump, keep this simple for now.
         */
-        if (ioapic_i8259.pin != -1 && !irq_remapping_enabled) {
+        if (ioapic_i8259.pin != -1) {
                struct IO_APIC_route_entry entry;
                memset(&entry, 0, sizeof(entry));
@@ -1964,12 +1917,25 @@ void disable_IO_APIC(void)
                ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
        }
+        if (cpu_has_apic || apic_from_smp_config())
+                disconnect_bsp_APIC(ioapic_i8259.pin != -1);
+}
+/*
+ * Not an __init, needed by the reboot code
+ */
+void disable_IO_APIC(void)
+{
        /*
-         * Use virtual wire A mode when interrupt remapping is enabled.
+         * Clear the IO-APIC before rebooting:
         */
-        if (cpu_has_apic || apic_from_smp_config())
+        clear_IO_APIC();
-                disconnect_bsp_APIC(!irq_remapping_enabled &&
-                                ioapic_i8259.pin != -1);
+        if (!legacy_pic->nr_legacy_irqs)
+                return;
+        x86_io_apic_ops.disable();
 }
 #ifdef CONFIG_X86_32
@@ -2322,12 +2288,8 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
                apic = entry->apic;
                pin = entry->pin;
-                /*
-                 * With interrupt-remapping, destination information comes
+                io_apic_write(apic, 0x11 + pin*2, dest);
-                 * from interrupt-remapping table entry.
-                 */
-                if (!irq_remapped(cfg))
-                        io_apic_write(apic, 0x11 + pin*2, dest);
                reg = io_apic_read(apic, 0x10 + pin*2);
                reg &= ~IO_APIC_REDIR_VECTOR_MASK;
                reg |= vector;
@@ -2369,9 +2331,10 @@ int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
        return 0;
 }
-static int
-ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
+int native_ioapic_set_affinity(struct irq_data *data,
-                    bool force)
+                               const struct cpumask *mask,
+                               bool force)
 {
        unsigned int dest, irq = data->irq;
        unsigned long flags;
@@ -2548,33 +2511,6 @@ static void ack_apic_level(struct irq_data *data)
        ioapic_irqd_unmask(data, cfg, masked);
 }
-#ifdef CONFIG_IRQ_REMAP
-static void ir_ack_apic_edge(struct irq_data *data)
-{
-        ack_APIC_irq();
-}
-static void ir_ack_apic_level(struct irq_data *data)
-{
-        ack_APIC_irq();
-        eoi_ioapic_irq(data->irq, data->chip_data);
-}
-static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
-{
-        seq_printf(p, " IR-%s", data->chip->name);
-}
-static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
-{
-        chip->irq_print_chip = ir_print_prefix;
-        chip->irq_ack = ir_ack_apic_edge;
-        chip->irq_eoi = ir_ack_apic_level;
-        chip->irq_set_affinity = set_remapped_irq_affinity;
-}
-#endif /* CONFIG_IRQ_REMAP */
 static struct irq_chip ioapic_chip __read_mostly = {
        .name                   = "IO-APIC",
        .irq_startup            = startup_ioapic_irq,
@@ -2582,7 +2518,7 @@ static struct irq_chip ioapic_chip __read_mostly = {
        .irq_unmask             = unmask_ioapic_irq,
        .irq_ack                = ack_apic_edge,
        .irq_eoi                = ack_apic_level,
-        .irq_set_affinity       = ioapic_set_affinity,
+        .irq_set_affinity       = native_ioapic_set_affinity,
        .irq_retrigger          = ioapic_retrigger_irq,
 };
@@ -2781,8 +2717,7 @@ static inline void __init check_timer(void)
         * 8259A.
         */
        if (pin1 == -1) {
-                if (irq_remapping_enabled)
+                panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
-                        panic("BIOS bug: timer not connected to IO-APIC");
                pin1 = pin2;
                apic1 = apic2;
                no_pin1 = 1;
@@ -2814,8 +2749,7 @@ static inline void __init check_timer(void)
                                clear_IO_APIC_pin(0, pin1);
                        goto out;
                }
-                if (irq_remapping_enabled)
+                panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
-                        panic("timer doesn't work through Interrupt-remapped IO-APIC");
                local_irq_disable();
                clear_IO_APIC_pin(apic1, pin1);
                if (!no_pin1)
@@ -2982,37 +2916,58 @@ device_initcall(ioapic_init_ops);
 /*
 * Dynamic irq allocate and deallocation
 */
-unsigned int create_irq_nr(unsigned int from, int node)
+unsigned int __create_irqs(unsigned int from, unsigned int count, int node)
 {
-        struct irq_cfg *cfg;
+        struct irq_cfg **cfg;
        unsigned long flags;
-        unsigned int ret = 0;
+        int irq, i;
-        int irq;
        if (from < nr_irqs_gsi)
                from = nr_irqs_gsi;
-        irq = alloc_irq_from(from, node);
+        cfg = kzalloc_node(count * sizeof(cfg[0]), GFP_KERNEL, node);
-        if (irq < 0)
+        if (!cfg)
-                return 0;
-        cfg = alloc_irq_cfg(irq, node);
-        if (!cfg) {
-                free_irq_at(irq, NULL);
                return 0;
+        irq = alloc_irqs_from(from, count, node);
+        if (irq < 0)
+                goto out_cfgs;
+        for (i = 0; i < count; i++) {
+                cfg[i] = alloc_irq_cfg(irq + i, node);
+                if (!cfg[i])
+                        goto out_irqs;
        }
        raw_spin_lock_irqsave(&vector_lock, flags);
-        if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
+        for (i = 0; i < count; i++)
-                ret = irq;
+                if (__assign_irq_vector(irq + i, cfg[i], apic->target_cpus()))
+                        goto out_vecs;
        raw_spin_unlock_irqrestore(&vector_lock, flags);
-        if (ret) {
+        for (i = 0; i < count; i++) {
-                irq_set_chip_data(irq, cfg);
+                irq_set_chip_data(irq + i, cfg[i]);
-                irq_clear_status_flags(irq, IRQ_NOREQUEST);
+                irq_clear_status_flags(irq + i, IRQ_NOREQUEST);
-        } else {
-                free_irq_at(irq, cfg);
        }
-        return ret;
+        kfree(cfg);
+        return irq;
+out_vecs:
+        for (i--; i >= 0; i--)
+                __clear_irq_vector(irq + i, cfg[i]);
+        raw_spin_unlock_irqrestore(&vector_lock, flags);
+out_irqs:
+        for (i = 0; i < count; i++)
+                free_irq_at(irq + i, cfg[i]);
+out_cfgs:
+        kfree(cfg);
+        return 0;
+}
+unsigned int create_irq_nr(unsigned int from, int node)
+{
+        return __create_irqs(from, 1, node);
 }
 int create_irq(void)
@@ -3037,48 +2992,35 @@ void destroy_irq(unsigned int irq)
        irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
-        if (irq_remapped(cfg))
+        free_remapped_irq(irq);
-                free_remapped_irq(irq);
        raw_spin_lock_irqsave(&vector_lock, flags);
        __clear_irq_vector(irq, cfg);
        raw_spin_unlock_irqrestore(&vector_lock, flags);
        free_irq_at(irq, cfg);
 }
+void destroy_irqs(unsigned int irq, unsigned int count)
+{
+        unsigned int i;
+        for (i = 0; i < count; i++)
+                destroy_irq(irq + i);
+}
 /*
 * MSI message composition
 */
-#ifdef CONFIG_PCI_MSI
+void native_compose_msi_msg(struct pci_dev *pdev,
-static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
+                            unsigned int irq, unsigned int dest,
-                           struct msi_msg *msg, u8 hpet_id)
+                            struct msi_msg *msg, u8 hpet_id)
 {
-        struct irq_cfg *cfg;
+        struct irq_cfg *cfg = irq_cfg(irq);
-        int err;
-        unsigned dest;
-        if (disable_apic)
-                return -ENXIO;
-        cfg = irq_cfg(irq);
-        err = assign_irq_vector(irq, cfg, apic->target_cpus());
-        if (err)
-                return err;
-        err = apic->cpu_mask_to_apicid_and(cfg->domain,
+        msg->address_hi = MSI_ADDR_BASE_HI;
-                                           apic->target_cpus(), &dest);
-        if (err)
-                return err;
-        if (irq_remapped(cfg)) {
-                compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
-                return err;
-        }
        if (x2apic_enabled())
-                msg->address_hi = MSI_ADDR_BASE_HI |
+                msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
-                                  MSI_ADDR_EXT_DEST_ID(dest);
-        else
-                msg->address_hi = MSI_ADDR_BASE_HI;
        msg->address_lo =
                MSI_ADDR_BASE_LO |
@@ -3097,8 +3039,32 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
                        MSI_DATA_DELIVERY_FIXED:
                        MSI_DATA_DELIVERY_LOWPRI) |
                MSI_DATA_VECTOR(cfg->vector);
+}
-        return err;
+#ifdef CONFIG_PCI_MSI
+static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
+                           struct msi_msg *msg, u8 hpet_id)
+{
+        struct irq_cfg *cfg;
+        int err;
+        unsigned dest;
+        if (disable_apic)
+                return -ENXIO;
+        cfg = irq_cfg(irq);
+        err = assign_irq_vector(irq, cfg, apic->target_cpus());
+        if (err)
+                return err;
+        err = apic->cpu_mask_to_apicid_and(cfg->domain,
+                                           apic->target_cpus(), &dest);
+        if (err)
+                return err;
+        x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
+        return 0;
 }
 static int
@@ -3136,23 +3102,28 @@ static struct irq_chip msi_chip = {
        .irq_retrigger          = ioapic_retrigger_irq,
 };
-static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
+int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
+                  unsigned int irq_base, unsigned int irq_offset)
 {
        struct irq_chip *chip = &msi_chip;
        struct msi_msg msg;
+        unsigned int irq = irq_base + irq_offset;
        int ret;
        ret = msi_compose_msg(dev, irq, &msg, -1);
        if (ret < 0)
                return ret;
-        irq_set_msi_desc(irq, msidesc);
+        irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
-        write_msi_msg(irq, &msg);
-        if (irq_remapped(irq_get_chip_data(irq))) {
+        /*
-                irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
+         * MSI-X message is written per-IRQ, the offset is always 0.
-                irq_remap_modify_chip_defaults(chip);
+         * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
-        }
+         */
+        if (!irq_offset)
+                write_msi_msg(irq, &msg);
+        setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
        irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
@@ -3163,46 +3134,26 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 {
-        int node, ret, sub_handle, index = 0;
        unsigned int irq, irq_want;
        struct msi_desc *msidesc;
+        int node, ret;
-        /* x86 doesn't support multiple MSI yet */
+        /* Multiple MSI vectors only supported with interrupt remapping */
        if (type == PCI_CAP_ID_MSI && nvec > 1)
                return 1;
        node = dev_to_node(&dev->dev);
        irq_want = nr_irqs_gsi;
-        sub_handle = 0;
        list_for_each_entry(msidesc, &dev->msi_list, list) {
                irq = create_irq_nr(irq_want, node);
                if (irq == 0)
-                        return -1;
+                        return -ENOSPC;
                irq_want = irq + 1;
-                if (!irq_remapping_enabled)
-                        goto no_ir;
-                if (!sub_handle) {
+                ret = setup_msi_irq(dev, msidesc, irq, 0);
-                        /*
-                         * allocate the consecutive block of IRTE's
-                         * for 'nvec'
-                         */
-                        index = msi_alloc_remapped_irq(dev, irq, nvec);
-                        if (index < 0) {
-                                ret = index;
-                                goto error;
-                        }
-                } else {
-                        ret = msi_setup_remapped_irq(dev, irq, index,
-                                                     sub_handle);
-                        if (ret < 0)
-                                goto error;
-                }
-no_ir:
-                ret = setup_msi_irq(dev, msidesc, irq);
                if (ret < 0)
                        goto error;
-                sub_handle++;
        }
        return 0;
@@ -3298,26 +3249,19 @@ static struct irq_chip hpet_msi_type = {
        .irq_retrigger = ioapic_retrigger_irq,
 };
-int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
+int default_setup_hpet_msi(unsigned int irq, unsigned int id)
 {
        struct irq_chip *chip = &hpet_msi_type;
        struct msi_msg msg;
        int ret;
-        if (irq_remapping_enabled) {
-                ret = setup_hpet_msi_remapped(irq, id);
-                if (ret)
-                        return ret;
-        }
        ret = msi_compose_msg(NULL, irq, &msg, id);
        if (ret < 0)
                return ret;
        hpet_msi_write(irq_get_handler_data(irq), &msg);
        irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
-        if (irq_remapped(irq_get_chip_data(irq)))
+        setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
-                irq_remap_modify_chip_defaults(chip);
        irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
        return 0;
@@ -3683,10 +3627,7 @@ void __init setup_ioapic_dest(void)
                else
                        mask = apic->target_cpus();
-                if (irq_remapping_enabled)
+                x86_io_apic_ops.set_affinity(idata, mask, false);
-                        set_remapped_irq_affinity(idata, mask, false);
-                else
-                        ioapic_set_affinity(idata, mask, false);
        }
 }
diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c
index cce91bf26676..7434d8556d09 100644
--- a/arch/x86/kernel/apic/ipi.c
+++ b/arch/x86/kernel/apic/ipi.c
@@ -106,7 +106,7 @@ void default_send_IPI_mask_logical(const struct cpumask *cpumask, int vector)
        unsigned long mask = cpumask_bits(cpumask)[0];
        unsigned long flags;
-        if (WARN_ONCE(!mask, "empty IPI mask"))
+        if (!mask)
                return;
        local_irq_save(flags);
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index e03a1e180e81..562a76d433c8 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -20,18 +20,19 @@ static int set_x2apic_phys_mode(char *arg)
 }
 early_param("x2apic_phys", set_x2apic_phys_mode);
-static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+static bool x2apic_fadt_phys(void)
 {
-        if (x2apic_phys)
+        if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
-                return x2apic_enabled();
+                (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
-        else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
-                (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
-                x2apic_enabled()) {
                printk(KERN_DEBUG "System requires x2apic physical mode\n");
-                return 1;
+                return true;
        }
-        else
+        return false;
-                return 0;
+}
+static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+        return x2apic_enabled() && (x2apic_phys || x2apic_fadt_phys());
 }
 static void
@@ -82,7 +83,7 @@ static void init_x2apic_ldr(void)
 static int x2apic_phys_probe(void)
 {
-        if (x2apic_mode && x2apic_phys)
+        if (x2apic_mode && (x2apic_phys || x2apic_fadt_phys()))
                return 1;
        return apic == &apic_x2apic_phys;
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index d65464e43503..8d7012b7f402 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -899,6 +899,7 @@ static void apm_cpu_idle(void)
        static int use_apm_idle; /* = 0 */
        static unsigned int last_jiffies; /* = 0 */
        static unsigned int last_stime; /* = 0 */
+        cputime_t stime;
        int apm_idle_done = 0;
        unsigned int jiffies_since_last_check = jiffies - last_jiffies;
@@ -906,23 +907,23 @@ static void apm_cpu_idle(void)
        WARN_ONCE(1, "deprecated apm_cpu_idle will be deleted in 2012");
 recalc:
+        task_cputime(current, NULL, &stime);
        if (jiffies_since_last_check > IDLE_CALC_LIMIT) {
                use_apm_idle = 0;
-                last_jiffies = jiffies;
-                last_stime = current->stime;
        } else if (jiffies_since_last_check > idle_period) {
                unsigned int idle_percentage;
-                idle_percentage = current->stime - last_stime;
+                idle_percentage = stime - last_stime;
                idle_percentage *= 100;
                idle_percentage /= jiffies_since_last_check;
                use_apm_idle = (idle_percentage > idle_threshold);
                if (apm_info.forbid_idle)
                        use_apm_idle = 0;
-                last_jiffies = jiffies;
-                last_stime = current->stime;
        }
+        last_jiffies = jiffies;
+        last_stime = stime;
        bucket = IDLE_LEAKY_MAX;
        while (!need_resched()) {
diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c
index a8f8fa9769d6..1e7e84a02eba 100644
--- a/arch/x86/kernel/cpu/hypervisor.c
+++ b/arch/x86/kernel/cpu/hypervisor.c
@@ -79,3 +79,10 @@ void __init init_hypervisor_platform(void)
        if (x86_hyper->init_platform)
                x86_hyper->init_platform();
 }
+bool __init hypervisor_x2apic_available(void)
+{
+        return x86_hyper                   &&
+               x86_hyper->x2apic_available &&
+               x86_hyper->x2apic_available();
+}
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index fe9edec6698a..84c1309c4c0c 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -298,8 +298,7 @@ struct _cache_attr {
                         unsigned int);
 };
-#ifdef CONFIG_AMD_NB
+#if defined(CONFIG_AMD_NB) && defined(CONFIG_SYSFS)
 /*
 * L3 cache descriptors
 */
@@ -524,9 +523,9 @@ store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count,
 static struct _cache_attr subcaches =
        __ATTR(subcaches, 0644, show_subcaches, store_subcaches);
-#else   /* CONFIG_AMD_NB */
+#else
 #define amd_init_l3_cache(x, y)
-#endif /* CONFIG_AMD_NB */
+#endif  /* CONFIG_AMD_NB && CONFIG_SYSFS */
 static int
 __cpuinit cpuid4_cache_lookup_regs(int index,
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 6774c17a5576..bf0f01aea994 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -829,7 +829,7 @@ static inline void x86_assign_hw_event(struct perf_event *event,
        } else {
                hwc->config_base = x86_pmu_config_addr(hwc->idx);
                hwc->event_base  = x86_pmu_event_addr(hwc->idx);
-                hwc->event_base_rdpmc = hwc->idx;
+                hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
        }
 }
@@ -1310,11 +1310,6 @@ static struct attribute_group x86_pmu_format_group = {
        .attrs = NULL,
 };
-struct perf_pmu_events_attr {
-        struct device_attribute attr;
-        u64 id;
-};
 /*
 * Remove all undefined events (x86_pmu.event_map(id) == 0)
 * out of events_attr attributes.
@@ -1348,11 +1343,9 @@ static ssize_t events_sysfs_show(struct device *dev, struct device_attribute *at
 #define EVENT_VAR(_id)  event_attr_##_id
 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
-#define EVENT_ATTR(_name, _id)                                  \
+#define EVENT_ATTR(_name, _id)                                          \
-static struct perf_pmu_events_attr EVENT_VAR(_id) = {           \
+        PMU_EVENT_ATTR(_name, EVENT_VAR(_id), PERF_COUNT_HW_##_id,      \
-        .attr = __ATTR(_name, 0444, events_sysfs_show, NULL),   \
+                        events_sysfs_show)
-        .id   =  PERF_COUNT_HW_##_id,                           \
-};
 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
 EVENT_ATTR(instructions,                INSTRUCTIONS            );
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 115c1ea97746..7f5c75c2afdd 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -325,6 +325,8 @@ struct x86_pmu {
        int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
        unsigned        eventsel;
        unsigned        perfctr;
+        int             (*addr_offset)(int index, bool eventsel);
+        int             (*rdpmc_index)(int index);
        u64             (*event_map)(int);
        int             max_events;
        int             num_counters;
@@ -446,28 +448,21 @@ extern u64 __read_mostly hw_cache_extra_regs
 u64 x86_perf_event_update(struct perf_event *event);
-static inline int x86_pmu_addr_offset(int index)
+static inline unsigned int x86_pmu_config_addr(int index)
 {
-        int offset;
+        return x86_pmu.eventsel + (x86_pmu.addr_offset ?
+                                   x86_pmu.addr_offset(index, true) : index);
-        /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
-        alternative_io(ASM_NOP2,
-                       "shll $1, %%eax",
-                       X86_FEATURE_PERFCTR_CORE,
-                       "=a" (offset),
-                       "a"  (index));
-        return offset;
 }
-static inline unsigned int x86_pmu_config_addr(int index)
+static inline unsigned int x86_pmu_event_addr(int index)
 {
-        return x86_pmu.eventsel + x86_pmu_addr_offset(index);
+        return x86_pmu.perfctr + (x86_pmu.addr_offset ?
+                                  x86_pmu.addr_offset(index, false) : index);
 }
-static inline unsigned int x86_pmu_event_addr(int index)
+static inline int x86_pmu_rdpmc_index(int index)
 {
-        return x86_pmu.perfctr + x86_pmu_addr_offset(index);
+        return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
 }
 int x86_setup_perfctr(struct perf_event *event);
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index c93bc4e813a0..dfdab42aed27 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -132,21 +132,102 @@ static u64 amd_pmu_event_map(int hw_event)
        return amd_perfmon_event_map[hw_event];
 }
-static int amd_pmu_hw_config(struct perf_event *event)
+static struct event_constraint *amd_nb_event_constraint;
+/*
+ * Previously calculated offsets
+ */
+static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
+static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
+static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
+/*
+ * Legacy CPUs:
+ *   4 counters starting at 0xc0010000 each offset by 1
+ *
+ * CPUs with core performance counter extensions:
+ *   6 counters starting at 0xc0010200 each offset by 2
+ *
+ * CPUs with north bridge performance counter extensions:
+ *   4 additional counters starting at 0xc0010240 each offset by 2
+ *   (indexed right above either one of the above core counters)
+ */
+static inline int amd_pmu_addr_offset(int index, bool eventsel)
 {
-        int ret;
+        int offset, first, base;
-        /* pass precise event sampling to ibs: */
+        if (!index)
-        if (event->attr.precise_ip && get_ibs_caps())
+                return index;
-                return -ENOENT;
+        if (eventsel)
+                offset = event_offsets[index];
+        else
+                offset = count_offsets[index];
+        if (offset)
+                return offset;
+        if (amd_nb_event_constraint &&
+            test_bit(index, amd_nb_event_constraint->idxmsk)) {
+                /*
+                 * calculate the offset of NB counters with respect to
+                 * base eventsel or perfctr
+                 */
+                first = find_first_bit(amd_nb_event_constraint->idxmsk,
+                                       X86_PMC_IDX_MAX);
+                if (eventsel)
+                        base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
+                else
+                        base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
+                offset = base + ((index - first) << 1);
+        } else if (!cpu_has_perfctr_core)
+                offset = index;
+        else
+                offset = index << 1;
+        if (eventsel)
+                event_offsets[index] = offset;
+        else
+                count_offsets[index] = offset;
+        return offset;
+}
+static inline int amd_pmu_rdpmc_index(int index)
+{
+        int ret, first;
+        if (!index)
+                return index;
+        ret = rdpmc_indexes[index];
-        ret = x86_pmu_hw_config(event);
        if (ret)
                return ret;
-        if (has_branch_stack(event))
+        if (amd_nb_event_constraint &&
-                return -EOPNOTSUPP;
+            test_bit(index, amd_nb_event_constraint->idxmsk)) {
+                /*
+                 * according to the mnual, ECX value of the NB counters is
+                 * the index of the NB counter (0, 1, 2 or 3) plus 6
+                 */
+                first = find_first_bit(amd_nb_event_constraint->idxmsk,
+                                       X86_PMC_IDX_MAX);
+                ret = index - first + 6;
+        } else
+                ret = index;
+        rdpmc_indexes[index] = ret;
+        return ret;
+}
+static int amd_core_hw_config(struct perf_event *event)
+{
        if (event->attr.exclude_host && event->attr.exclude_guest)
                /*
                 * When HO == GO == 1 the hardware treats that as GO == HO == 0
@@ -156,14 +237,37 @@ static int amd_pmu_hw_config(struct perf_event *event)
                event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
                                      ARCH_PERFMON_EVENTSEL_OS);
        else if (event->attr.exclude_host)
-                event->hw.config |= AMD_PERFMON_EVENTSEL_GUESTONLY;
+                event->hw.config |= AMD64_EVENTSEL_GUESTONLY;
        else if (event->attr.exclude_guest)
-                event->hw.config |= AMD_PERFMON_EVENTSEL_HOSTONLY;
+                event->hw.config |= AMD64_EVENTSEL_HOSTONLY;
+        return 0;
+}
+/*
+ * NB counters do not support the following event select bits:
+ *   Host/Guest only
+ *   Counter mask
+ *   Invert counter mask
+ *   Edge detect
+ *   OS/User mode
+ */
+static int amd_nb_hw_config(struct perf_event *event)
+{
+        /* for NB, we only allow system wide counting mode */
+        if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+                return -EINVAL;
+        if (event->attr.exclude_user || event->attr.exclude_kernel ||
+            event->attr.exclude_host || event->attr.exclude_guest)
+                return -EINVAL;
-        if (event->attr.type != PERF_TYPE_RAW)
+        event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
-                return 0;
+                              ARCH_PERFMON_EVENTSEL_OS);
-        event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
+        if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
+                                 ARCH_PERFMON_EVENTSEL_INT))
+                return -EINVAL;
        return 0;
 }
@@ -181,6 +285,11 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
        return (hwc->config & 0xe0) == 0xe0;
 }
+static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
+{
+        return amd_nb_event_constraint && amd_is_nb_event(hwc);
+}
 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 {
        struct amd_nb *nb = cpuc->amd_nb;
@@ -188,20 +297,37 @@ static inline int amd_has_nb(struct cpu_hw_events *cpuc)
        return nb && nb->nb_id != -1;
 }
-static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
+static int amd_pmu_hw_config(struct perf_event *event)
-                                      struct perf_event *event)
+{
+        int ret;
+        /* pass precise event sampling to ibs: */
+        if (event->attr.precise_ip && get_ibs_caps())
+                return -ENOENT;
+        if (has_branch_stack(event))
+                return -EOPNOTSUPP;
+        ret = x86_pmu_hw_config(event);
+        if (ret)
+                return ret;
+        if (event->attr.type == PERF_TYPE_RAW)
+                event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
+        if (amd_is_perfctr_nb_event(&event->hw))
+                return amd_nb_hw_config(event);
+        return amd_core_hw_config(event);
+}
+static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
+                                           struct perf_event *event)
 {
-        struct hw_perf_event *hwc = &event->hw;
        struct amd_nb *nb = cpuc->amd_nb;
        int i;
        /*
-         * only care about NB events
-         */
-        if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
-                return;
-        /*
         * need to scan whole list because event may not have
         * been assigned during scheduling
         *
@@ -215,6 +341,19 @@ static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
        }
 }
+static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
+{
+        int core_id = cpu_data(smp_processor_id()).cpu_core_id;
+        /* deliver interrupts only to this core */
+        if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
+                hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
+                hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
+                hwc->config |= (u64)(core_id) <<
+                        AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
+        }
+}
 /*
  * AMD64 NorthBridge events need special treatment because
  * counter access needs to be synchronized across all cores
@@ -247,24 +386,24 @@ static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
  *
  * Given that resources are allocated (cmpxchg), they must be
  * eventually freed for others to use. This is accomplished by
-  * calling amd_put_event_constraints().
+  * calling __amd_put_nb_event_constraints()
  *
  * Non NB events are not impacted by this restriction.
  */
 static struct event_constraint *
-amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+__amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
+                               struct event_constraint *c)
 {
        struct hw_perf_event *hwc = &event->hw;
        struct amd_nb *nb = cpuc->amd_nb;
-        struct perf_event *old = NULL;
+        struct perf_event *old;
-        int max = x86_pmu.num_counters;
+        int idx, new = -1;
-        int i, j, k = -1;
-        /*
+        if (!c)
-         * if not NB event or no NB, then no constraints
+                c = &unconstrained;
-         */
-        if (!(amd_has_nb(cpuc) && amd_is_nb_event(hwc)))
+        if (cpuc->is_fake)
-                return &unconstrained;
+                return c;
        /*
         * detect if already present, if so reuse
@@ -276,48 +415,36 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
         * because of successive calls to x86_schedule_events() from
         * hw_perf_group_sched_in() without hw_perf_enable()
         */
-        for (i = 0; i < max; i++) {
+        for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) {
-                /*
+                if (new == -1 || hwc->idx == idx)
-                 * keep track of first free slot
+                        /* assign free slot, prefer hwc->idx */
-                 */
+                        old = cmpxchg(nb->owners + idx, NULL, event);
-                if (k == -1 && !nb->owners[i])
+                else if (nb->owners[idx] == event)
-                        k = i;
+                        /* event already present */
+                        old = event;
+                else
+                        continue;
+                if (old && old != event)
+                        continue;
+                /* reassign to this slot */
+                if (new != -1)
+                        cmpxchg(nb->owners + new, event, NULL);
+                new = idx;
                /* already present, reuse */
-                if (nb->owners[i] == event)
+                if (old == event)
-                        goto done;
-        }
-        /*
-         * not present, so grab a new slot
-         * starting either at:
-         */
-        if (hwc->idx != -1) {
-                /* previous assignment */
-                i = hwc->idx;
-        } else if (k != -1) {
-                /* start from free slot found */
-                i = k;
-        } else {
-                /*
-                 * event not found, no slot found in
-                 * first pass, try again from the
-                 * beginning
-                 */
-                i = 0;
-        }
-        j = i;
-        do {
-                old = cmpxchg(nb->owners+i, NULL, event);
-                if (!old)
                        break;
-                if (++i == max)
+        }
-                        i = 0;
-        } while (i != j);
+        if (new == -1)
-done:
+                return &emptyconstraint;
-        if (!old)
-                return &nb->event_constraints[i];
+        if (amd_is_perfctr_nb_event(hwc))
+                amd_nb_interrupt_hw_config(hwc);
-        return &emptyconstraint;
+        return &nb->event_constraints[new];
 }
 static struct amd_nb *amd_alloc_nb(int cpu)
@@ -364,7 +491,7 @@ static void amd_pmu_cpu_starting(int cpu)
        struct amd_nb *nb;
        int i, nb_id;
-        cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+        cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
        if (boot_cpu_data.x86_max_cores < 2)
                return;
@@ -407,6 +534,26 @@ static void amd_pmu_cpu_dead(int cpu)
        }
 }
+static struct event_constraint *
+amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+{
+        /*
+         * if not NB event or no NB, then no constraints
+         */
+        if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
+                return &unconstrained;
+        return __amd_get_nb_event_constraints(cpuc, event,
+                                              amd_nb_event_constraint);
+}
+static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
+                                      struct perf_event *event)
+{
+        if (amd_has_nb(cpuc) && amd_is_nb_event(&event->hw))
+                __amd_put_nb_event_constraints(cpuc, event);
+}
 PMU_FORMAT_ATTR(event,  "config:0-7,32-35");
 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
 PMU_FORMAT_ATTR(edge,   "config:18"     );
@@ -496,6 +643,9 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
+static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
+static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
 static struct event_constraint *
 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
 {
@@ -561,8 +711,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
                        return &amd_f15_PMC20;
                }
        case AMD_EVENT_NB:
-                /* not yet implemented */
+                return __amd_get_nb_event_constraints(cpuc, event,
-                return &emptyconstraint;
+                                                      amd_nb_event_constraint);
        default:
                return &emptyconstraint;
        }
@@ -587,6 +737,8 @@ static __initconst const struct x86_pmu amd_pmu = {
        .schedule_events        = x86_schedule_events,
        .eventsel               = MSR_K7_EVNTSEL0,
        .perfctr                = MSR_K7_PERFCTR0,
+        .addr_offset            = amd_pmu_addr_offset,
+        .rdpmc_index            = amd_pmu_rdpmc_index,
        .event_map              = amd_pmu_event_map,
        .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
        .num_counters           = AMD64_NUM_COUNTERS,
@@ -608,7 +760,7 @@ static __initconst const struct x86_pmu amd_pmu = {
 static int setup_event_constraints(void)
 {
-        if (boot_cpu_data.x86 >= 0x15)
+        if (boot_cpu_data.x86 == 0x15)
                x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
        return 0;
 }
@@ -638,6 +790,23 @@ static int setup_perfctr_core(void)
        return 0;
 }
+static int setup_perfctr_nb(void)
+{
+        if (!cpu_has_perfctr_nb)
+                return -ENODEV;
+        x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
+        if (cpu_has_perfctr_core)
+                amd_nb_event_constraint = &amd_NBPMC96;
+        else
+                amd_nb_event_constraint = &amd_NBPMC74;
+        printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
+        return 0;
+}
 __init int amd_pmu_init(void)
 {
        /* Performance-monitoring supported from K7 and later: */
@@ -648,6 +817,7 @@ __init int amd_pmu_init(void)
        setup_event_constraints();
        setup_perfctr_core();
+        setup_perfctr_nb();
        /* Events are common for all AMDs */
        memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
@@ -678,7 +848,7 @@ void amd_pmu_disable_virt(void)
         * SVM is disabled the Guest-only bits still gets set and the counter
         * will not count anything.
         */
-        cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+        cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
        /* Reload all events */
        x86_pmu_disable_all();
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 93b9e1181f83..4914e94ad6e8 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2019,7 +2019,10 @@ __init int intel_pmu_init(void)
                break;
        case 28: /* Atom */
-        case 54: /* Cedariew */
+        case 38: /* Lincroft */
+        case 39: /* Penwell */
+        case 53: /* Cloverview */
+        case 54: /* Cedarview */
                memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
                       sizeof(hw_cache_event_ids));
@@ -2084,6 +2087,7 @@ __init int intel_pmu_init(void)
                pr_cont("SandyBridge events, ");
                break;
        case 58: /* IvyBridge */
+        case 62: /* IvyBridge EP */
                memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
                       sizeof(hw_cache_event_ids));
                memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
index f2af39f5dc3d..4820c232a0b9 100644
--- a/arch/x86/kernel/cpu/perf_event_p6.c
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -19,7 +19,7 @@ static const u64 p6_perfmon_event_map[] =
 };
-static __initconst u64 p6_hw_cache_event_ids
+static u64 p6_hw_cache_event_ids
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c
index d22d0c4edcfd..03a36321ec54 100644
--- a/arch/x86/kernel/cpu/vmware.c
+++ b/arch/x86/kernel/cpu/vmware.c
@@ -33,6 +33,9 @@
 #define VMWARE_PORT_CMD_GETVERSION      10
 #define VMWARE_PORT_CMD_GETHZ           45
+#define VMWARE_PORT_CMD_GETVCPU_INFO    68
+#define VMWARE_PORT_CMD_LEGACY_X2APIC   3
+#define VMWARE_PORT_CMD_VCPU_RESERVED   31
 #define VMWARE_PORT(cmd, eax, ebx, ecx, edx)                            \
        __asm__("inl (%%dx)" :                                          \
@@ -125,10 +128,20 @@ static void __cpuinit vmware_set_cpu_features(struct cpuinfo_x86 *c)
        set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
 }
+/* Checks if hypervisor supports x2apic without VT-D interrupt remapping. */
+static bool __init vmware_legacy_x2apic_available(void)
+{
+        uint32_t eax, ebx, ecx, edx;
+        VMWARE_PORT(GETVCPU_INFO, eax, ebx, ecx, edx);
+        return (eax & (1 << VMWARE_PORT_CMD_VCPU_RESERVED)) == 0 &&
+               (eax & (1 << VMWARE_PORT_CMD_LEGACY_X2APIC)) != 0;
+}
 const __refconst struct hypervisor_x86 x86_hyper_vmware = {
        .name                   = "VMware",
        .detect                 = vmware_platform,
        .set_cpu_features       = vmware_set_cpu_features,
        .init_platform          = vmware_platform_setup,
+        .x2apic_available       = vmware_legacy_x2apic_available,
 };
 EXPORT_SYMBOL(x86_hyper_vmware);
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 07a7a04529bc..cb3c591339aa 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1781,6 +1781,7 @@ first_nmi:
         * Leave room for the "copied" frame
         */
        subq $(5*8), %rsp
+        CFI_ADJUST_CFA_OFFSET 5*8
        /* Copy the stack frame to the Saved frame */
        .rept 5
@@ -1863,10 +1864,8 @@ end_repeat_nmi:
 nmi_swapgs:
        SWAPGS_UNSAFE_STACK
 nmi_restore:
-        RESTORE_ALL 8
+        /* Pop the extra iret frame at once */
+        RESTORE_ALL 6*8
-        /* Pop the extra iret frame */
-        addq $(5*8), %rsp
        /* Clear the NMI executing stack variable */
        movq $0, 5*8(%rsp)
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index 8e7f6556028f..3c3f58a0808f 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -300,37 +300,52 @@ ENTRY(startup_32_smp)
        leal -__PAGE_OFFSET(%ecx),%esp
 default_entry:
+#define CR0_STATE       (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
+                         X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
+                         X86_CR0_PG)
+        movl $(CR0_STATE & ~X86_CR0_PG),%eax
+        movl %eax,%cr0
+/*
+ * We want to start out with EFLAGS unambiguously cleared. Some BIOSes leave
+ * bits like NT set. This would confuse the debugger if this code is traced. So
+ * initialize them properly now before switching to protected mode. That means
+ * DF in particular (even though we have cleared it earlier after copying the
+ * command line) because GCC expects it.
+ */
+        pushl $0
+        popfl
 /*
- *      New page tables may be in 4Mbyte page mode and may
+ * New page tables may be in 4Mbyte page mode and may be using the global pages.
- *      be using the global pages. 
 *
- *      NOTE! If we are on a 486 we may have no cr4 at all!
+ * NOTE! If we are on a 486 we may have no cr4 at all! Specifically, cr4 exists
- *      Specifically, cr4 exists if and only if CPUID exists
+ * if and only if CPUID exists and has flags other than the FPU flag set.
- *      and has flags other than the FPU flag set.
 */
+        movl $-1,pa(X86_CPUID)          # preset CPUID level
        movl $X86_EFLAGS_ID,%ecx
        pushl %ecx
-        popfl
+        popfl                           # set EFLAGS=ID
        pushfl
-        popl %eax
+        popl %eax                       # get EFLAGS
-        pushl $0
+        testl $X86_EFLAGS_ID,%eax       # did EFLAGS.ID remained set?
-        popfl
+        jz enable_paging                # hw disallowed setting of ID bit
-        pushfl
+                                        # which means no CPUID and no CR4
-        popl %edx
-        xorl %edx,%eax
+        xorl %eax,%eax
-        testl %ecx,%eax
+        cpuid
-        jz 6f                   # No ID flag = no CPUID = no CR4
+        movl %eax,pa(X86_CPUID)         # save largest std CPUID function
        movl $1,%eax
        cpuid
-        andl $~1,%edx           # Ignore CPUID.FPU
+        andl $~1,%edx                   # Ignore CPUID.FPU
-        jz 6f                   # No flags or only CPUID.FPU = no CR4
+        jz enable_paging                # No flags or only CPUID.FPU = no CR4
        movl pa(mmu_cr4_features),%eax
        movl %eax,%cr4
        testb $X86_CR4_PAE, %al         # check if PAE is enabled
-        jz 6f
+        jz enable_paging
        /* Check if extended functions are implemented */
        movl $0x80000000, %eax
@@ -338,7 +353,7 @@ default_entry:
        /* Value must be in the range 0x80000001 to 0x8000ffff */
        subl $0x80000001, %eax
        cmpl $(0x8000ffff-0x80000001), %eax
-        ja 6f
+        ja enable_paging
        /* Clear bogus XD_DISABLE bits */
        call verify_cpu
@@ -347,7 +362,7 @@ default_entry:
        cpuid
        /* Execute Disable bit supported? */
        btl $(X86_FEATURE_NX & 31), %edx
-        jnc 6f
+        jnc enable_paging
        /* Setup EFER (Extended Feature Enable Register) */
        movl $MSR_EFER, %ecx
@@ -357,15 +372,14 @@ default_entry:
        /* Make changes effective */
        wrmsr
-6:
+enable_paging:
 /*
 * Enable paging
 */
        movl $pa(initial_page_table), %eax
        movl %eax,%cr3          /* set the page table pointer.. */
-        movl %cr0,%eax
+        movl $CR0_STATE,%eax
-        orl  $X86_CR0_PG,%eax
        movl %eax,%cr0          /* ..and set paging (PG) bit */
        ljmp $__BOOT_CS,$1f     /* Clear prefetch and normalize %eip */
 1:
@@ -373,14 +387,6 @@ default_entry:
        addl $__PAGE_OFFSET, %esp
 /*
- * Initialize eflags.  Some BIOS's leave bits like NT set.  This would
- * confuse the debugger if this code is traced.
- * XXX - best to initialize before switching to protected mode.
- */
-        pushl $0
-        popfl
-/*
 * start system 32-bit setup. We need to re-do some of the things done
 * in 16-bit mode for the "real" operations.
 */
@@ -389,31 +395,11 @@ default_entry:
        jz 1f                           # Did we do this already?
        call *%eax
 1:
-        
-/* check if it is 486 or 386. */
 /*
- * XXX - this does a lot of unnecessary setup.  Alignment checks don't
+ * Check if it is 486
- * apply at our cpl of 0 and the stack ought to be aligned already, and
- * we don't need to preserve eflags.
 */
-        movl $-1,X86_CPUID      # -1 for no CPUID initially
+        cmpl $-1,X86_CPUID
-        movb $3,X86             # at least 386
-        pushfl                  # push EFLAGS
-        popl %eax               # get EFLAGS
-        movl %eax,%ecx          # save original EFLAGS
-        xorl $0x240000,%eax     # flip AC and ID bits in EFLAGS
-        pushl %eax              # copy to EFLAGS
-        popfl                   # set EFLAGS
-        pushfl                  # get new EFLAGS
-        popl %eax               # put it in eax
-        xorl %ecx,%eax          # change in flags
-        pushl %ecx              # restore original EFLAGS
-        popfl
-        testl $0x40000,%eax     # check if AC bit changed
-        je is386
-        movb $4,X86             # at least 486
-        testl $0x200000,%eax    # check if ID bit changed
        je is486
        /* get vendor info */
@@ -439,11 +425,10 @@ default_entry:
        movb %cl,X86_MASK
        movl %edx,X86_CAPABILITY
-is486:  movl $0x50022,%ecx      # set AM, WP, NE and MP
+is486:
-        jmp 2f
+        movb $4,X86
+        movl $0x50022,%ecx      # set AM, WP, NE and MP
-is386:  movl $2,%ecx            # set MP
+        movl %cr0,%eax
-2:      movl %cr0,%eax
        andl $0x80000011,%eax   # Save PG,PE,ET
        orl %ecx,%eax
        movl %eax,%cr0
@@ -468,7 +453,6 @@ is386:	movl $2,%ecx		# set MP
        xorl %eax,%eax                  # Clear LDT
        lldt %ax
-        cld                     # gcc2 wants the direction flag cleared at all times
        pushl $0                # fake return address for unwinder
        jmp *(initial_code)
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index e28670f9a589..da85a8e830a1 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -478,7 +478,7 @@ static int hpet_msi_next_event(unsigned long delta,
 static int hpet_setup_msi_irq(unsigned int irq)
 {
-        if (arch_setup_hpet_msi(irq, hpet_blockid)) {
+        if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
                destroy_irq(irq);
                return -EINVAL;
        }
diff --git a/arch/x86/kernel/kprobes/Makefile b/arch/x86/kernel/kprobes/Makefile
new file mode 100644
index 000000000000..0d33169cc1a2
--- /dev/null
+++ b/arch/x86/kernel/kprobes/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for kernel probes
+#
+obj-$(CONFIG_KPROBES)           += core.o
+obj-$(CONFIG_OPTPROBES)         += opt.o
+obj-$(CONFIG_KPROBES_ON_FTRACE) += ftrace.o
diff --git a/arch/x86/kernel/kprobes-common.h b/arch/x86/kernel/kprobes/common.h
index 3230b68ef29a..2e9d4b5af036 100644
--- a/arch/x86/kernel/kprobes-common.h
+++ b/arch/x86/kernel/kprobes/common.h
@@ -99,4 +99,15 @@ static inline unsigned long __recover_optprobed_insn(kprobe_opcode_t *buf, unsig
        return addr;
 }
 #endif
+#ifdef CONFIG_KPROBES_ON_FTRACE
+extern int skip_singlestep(struct kprobe *p, struct pt_regs *regs,
+                           struct kprobe_ctlblk *kcb);
+#else
+static inline int skip_singlestep(struct kprobe *p, struct pt_regs *regs,
+                                  struct kprobe_ctlblk *kcb)
+{
+        return 0;
+}
+#endif
 #endif
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes/core.c
index 57916c0d3cf6..e124554598ee 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -58,7 +58,7 @@
 #include <asm/insn.h>
 #include <asm/debugreg.h>
-#include "kprobes-common.h"
+#include "common.h"
 void jprobe_return_end(void);
@@ -78,7 +78,7 @@ DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
         * Groups, and some special opcodes can not boost.
         * This is non-const and volatile to keep gcc from statically
         * optimizing it out, as variable_test_bit makes gcc think only
-         * *(unsigned long*) is used. 
+         * *(unsigned long*) is used.
         */
 static volatile u32 twobyte_is_boostable[256 / 32] = {
        /*      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f          */
@@ -117,7 +117,7 @@ static void __kprobes __synthesize_relative_insn(void *from, void *to, u8 op)
        struct __arch_relative_insn {
                u8 op;
                s32 raddr;
-        } __attribute__((packed)) *insn;
+        } __packed *insn;
        insn = (struct __arch_relative_insn *)from;
        insn->raddr = (s32)((long)(to) - ((long)(from) + 5));
@@ -541,23 +541,6 @@ reenter_kprobe(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb
        return 1;
 }
-#ifdef KPROBES_CAN_USE_FTRACE
-static void __kprobes skip_singlestep(struct kprobe *p, struct pt_regs *regs,
-                                      struct kprobe_ctlblk *kcb)
-{
-        /*
-         * Emulate singlestep (and also recover regs->ip)
-         * as if there is a 5byte nop
-         */
-        regs->ip = (unsigned long)p->addr + MCOUNT_INSN_SIZE;
-        if (unlikely(p->post_handler)) {
-                kcb->kprobe_status = KPROBE_HIT_SSDONE;
-                p->post_handler(p, regs, 0);
-        }
-        __this_cpu_write(current_kprobe, NULL);
-}
-#endif
 /*
 * Interrupts are disabled on entry as trap3 is an interrupt gate and they
 * remain disabled throughout this function.
@@ -616,13 +599,8 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
        } else if (kprobe_running()) {
                p = __this_cpu_read(current_kprobe);
                if (p->break_handler && p->break_handler(p, regs)) {
-#ifdef KPROBES_CAN_USE_FTRACE
+                        if (!skip_singlestep(p, regs, kcb))
-                        if (kprobe_ftrace(p)) {
+                                setup_singlestep(p, regs, kcb, 0);
-                                skip_singlestep(p, regs, kcb);
-                                return 1;
-                        }
-#endif
-                        setup_singlestep(p, regs, kcb, 0);
                        return 1;
                }
        } /* else: not a kprobe fault; let the kernel handle it */
@@ -1075,50 +1053,6 @@ int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
        return 0;
 }
-#ifdef KPROBES_CAN_USE_FTRACE
-/* Ftrace callback handler for kprobes */
-void __kprobes kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
-                                     struct ftrace_ops *ops, struct pt_regs *regs)
-{
-        struct kprobe *p;
-        struct kprobe_ctlblk *kcb;
-        unsigned long flags;
-        /* Disable irq for emulating a breakpoint and avoiding preempt */
-        local_irq_save(flags);
-        p = get_kprobe((kprobe_opcode_t *)ip);
-        if (unlikely(!p) || kprobe_disabled(p))
-                goto end;
-        kcb = get_kprobe_ctlblk();
-        if (kprobe_running()) {
-                kprobes_inc_nmissed_count(p);
-        } else {
-                /* Kprobe handler expects regs->ip = ip + 1 as breakpoint hit */
-                regs->ip = ip + sizeof(kprobe_opcode_t);
-                __this_cpu_write(current_kprobe, p);
-                kcb->kprobe_status = KPROBE_HIT_ACTIVE;
-                if (!p->pre_handler || !p->pre_handler(p, regs))
-                        skip_singlestep(p, regs, kcb);
-                /*
-                 * If pre_handler returns !0, it sets regs->ip and
-                 * resets current kprobe.
-                 */
-        }
-end:
-        local_irq_restore(flags);
-}
-int __kprobes arch_prepare_kprobe_ftrace(struct kprobe *p)
-{
-        p->ainsn.insn = NULL;
-        p->ainsn.boostable = -1;
-        return 0;
-}
-#endif
 int __init arch_init_kprobes(void)
 {
        return arch_init_optprobes();
diff --git a/arch/x86/kernel/kprobes/ftrace.c b/arch/x86/kernel/kprobes/ftrace.c
new file mode 100644
index 000000000000..23ef5c556f06
--- /dev/null
+++ b/arch/x86/kernel/kprobes/ftrace.c
@@ -0,0 +1,93 @@
+/*
+ * Dynamic Ftrace based Kprobes Optimization
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) Hitachi Ltd., 2012
+ */
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+#include <linux/hardirq.h>
+#include <linux/preempt.h>
+#include <linux/ftrace.h>
+#include "common.h"
+static int __skip_singlestep(struct kprobe *p, struct pt_regs *regs,
+                             struct kprobe_ctlblk *kcb)
+{
+        /*
+         * Emulate singlestep (and also recover regs->ip)
+         * as if there is a 5byte nop
+         */
+        regs->ip = (unsigned long)p->addr + MCOUNT_INSN_SIZE;
+        if (unlikely(p->post_handler)) {
+                kcb->kprobe_status = KPROBE_HIT_SSDONE;
+                p->post_handler(p, regs, 0);
+        }
+        __this_cpu_write(current_kprobe, NULL);
+        return 1;
+}
+int __kprobes skip_singlestep(struct kprobe *p, struct pt_regs *regs,
+                              struct kprobe_ctlblk *kcb)
+{
+        if (kprobe_ftrace(p))
+                return __skip_singlestep(p, regs, kcb);
+        else
+                return 0;
+}
+/* Ftrace callback handler for kprobes */
+void __kprobes kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
+                                     struct ftrace_ops *ops, struct pt_regs *regs)
+{
+        struct kprobe *p;
+        struct kprobe_ctlblk *kcb;
+        unsigned long flags;
+        /* Disable irq for emulating a breakpoint and avoiding preempt */
+        local_irq_save(flags);
+        p = get_kprobe((kprobe_opcode_t *)ip);
+        if (unlikely(!p) || kprobe_disabled(p))
+                goto end;
+        kcb = get_kprobe_ctlblk();
+        if (kprobe_running()) {
+                kprobes_inc_nmissed_count(p);
+        } else {
+                /* Kprobe handler expects regs->ip = ip + 1 as breakpoint hit */
+                regs->ip = ip + sizeof(kprobe_opcode_t);
+                __this_cpu_write(current_kprobe, p);
+                kcb->kprobe_status = KPROBE_HIT_ACTIVE;
+                if (!p->pre_handler || !p->pre_handler(p, regs))
+                        __skip_singlestep(p, regs, kcb);
+                /*
+                 * If pre_handler returns !0, it sets regs->ip and
+                 * resets current kprobe.
+                 */
+        }
+end:
+        local_irq_restore(flags);
+}
+int __kprobes arch_prepare_kprobe_ftrace(struct kprobe *p)
+{
+        p->ainsn.insn = NULL;
+        p->ainsn.boostable = -1;
+        return 0;
+}
diff --git a/arch/x86/kernel/kprobes-opt.c b/arch/x86/kernel/kprobes/opt.c
index c5e410eed403..76dc6f095724 100644
--- a/arch/x86/kernel/kprobes-opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -37,7 +37,7 @@
 #include <asm/insn.h>
 #include <asm/debugreg.h>
-#include "kprobes-common.h"
+#include "common.h"
 unsigned long __recover_optprobed_insn(kprobe_opcode_t *buf, unsigned long addr)
 {
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 9c2bd8bd4b4c..2b44ea5f269d 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -505,6 +505,7 @@ static bool __init kvm_detect(void)
 const struct hypervisor_x86 x86_hyper_kvm __refconst = {
        .name                   = "KVM",
        .detect                 = kvm_detect,
+        .x2apic_available       = kvm_para_available,
 };
 EXPORT_SYMBOL_GPL(x86_hyper_kvm);
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index a7c5661f8496..4929502c1372 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -174,6 +174,9 @@ static int msr_open(struct inode *inode, struct file *file)
        unsigned int cpu;
        struct cpuinfo_x86 *c;
+        if (!capable(CAP_SYS_RAWIO))
+                return -EPERM;
        cpu = iminor(file->f_path.dentry->d_inode);
        if (cpu >= nr_cpu_ids || !cpu_online(cpu))
                return -ENXIO;  /* No such CPU */
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 0f5dec5c80e0..872079a67e4d 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -56,7 +56,7 @@ struct device x86_dma_fallback_dev = {
 EXPORT_SYMBOL(x86_dma_fallback_dev);
 /* Number of entries preallocated for DMA-API debugging */
-#define PREALLOC_DMA_DEBUG_ENTRIES       32768
+#define PREALLOC_DMA_DEBUG_ENTRIES       65536
 int dma_set_mask(struct device *dev, u64 mask)
 {
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 4e8ba39eaf0f..76fa1e9a2b39 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -584,7 +584,7 @@ static void native_machine_emergency_restart(void)
                        break;
                case BOOT_EFI:
-                        if (efi_enabled)
+                        if (efi_enabled(EFI_RUNTIME_SERVICES))
                                efi.reset_system(reboot_mode ?
                                                 EFI_RESET_WARM :
                                                 EFI_RESET_COLD,
diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index 801602b5d745..2e8f3d3b5641 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -149,7 +149,6 @@ unsigned long mach_get_cmos_time(void)
        if (century) {
                century = bcd2bin(century);
                year += century * 100;
-                printk(KERN_INFO "Extended CMOS year: %d\n", century * 100);
        } else
                year += CMOS_YEARS_OFFS;
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 00f6c1472b85..8b24289cc10c 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -807,15 +807,15 @@ void __init setup_arch(char **cmdline_p)
 #ifdef CONFIG_EFI
        if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
                     "EL32", 4)) {
-                efi_enabled = 1;
+                set_bit(EFI_BOOT, &x86_efi_facility);
-                efi_64bit = false;
        } else if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
                     "EL64", 4)) {
-                efi_enabled = 1;
+                set_bit(EFI_BOOT, &x86_efi_facility);
-                efi_64bit = true;
+                set_bit(EFI_64BIT, &x86_efi_facility);
        }
-        if (efi_enabled && efi_memblock_x86_reserve_range())
-                efi_enabled = 0;
+        if (efi_enabled(EFI_BOOT))
+                efi_memblock_x86_reserve_range();
 #endif
        x86_init.oem.arch_setup();
@@ -888,7 +888,7 @@ void __init setup_arch(char **cmdline_p)
        finish_e820_parsing();
-        if (efi_enabled)
+        if (efi_enabled(EFI_BOOT))
                efi_init();
        dmi_scan_machine();
@@ -971,7 +971,7 @@ void __init setup_arch(char **cmdline_p)
         * The EFI specification says that boot service code won't be called
         * after ExitBootServices(). This is, in fact, a lie.
         */
-        if (efi_enabled)
+        if (efi_enabled(EFI_MEMMAP))
                efi_reserve_boot_services();
        /* preallocate 4k for mptable mpc */
@@ -1114,7 +1114,7 @@ void __init setup_arch(char **cmdline_p)
 #ifdef CONFIG_VT
 #if defined(CONFIG_VGA_CONSOLE)
-        if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
+        if (!efi_enabled(EFI_BOOT) || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
                conswitchp = &vga_con;
 #elif defined(CONFIG_DUMMY_CONSOLE)
        conswitchp = &dummy_con;
@@ -1131,14 +1131,14 @@ void __init setup_arch(char **cmdline_p)
        register_refined_jiffies(CLOCK_TICK_RATE);
 #ifdef CONFIG_EFI
-        /* Once setup is done above, disable efi_enabled on mismatched
+        /* Once setup is done above, unmap the EFI memory map on
-         * firmware/kernel archtectures since there is no support for
+         * mismatched firmware/kernel archtectures since there is no
-         * runtime services.
+         * support for runtime services.
         */
-        if (efi_enabled && IS_ENABLED(CONFIG_X86_64) != efi_64bit) {
+        if (efi_enabled(EFI_BOOT) &&
+            IS_ENABLED(CONFIG_X86_64) != efi_enabled(EFI_64BIT)) {
                pr_info("efi: Setup done, disabling due to 32/64-bit mismatch\n");
                efi_unmap_memmap();
-                efi_enabled = 0;
        }
 #endif
 }
diff --git a/arch/x86/kernel/sys_x86_64.c b/arch/x86/kernel/sys_x86_64.c
index 97ef74b88e0f..dbded5aedb81 100644
--- a/arch/x86/kernel/sys_x86_64.c
+++ b/arch/x86/kernel/sys_x86_64.c
@@ -157,7 +157,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
        if (flags & MAP_FIXED)
                return addr;
-        /* for MAP_32BIT mappings we force the legact mmap base */
+        /* for MAP_32BIT mappings we force the legacy mmap base */
        if (!test_thread_flag(TIF_ADDR32) && (flags & MAP_32BIT))
                goto bottomup;
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 06ccb5073a3f..4b9ea101fe3b 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -623,7 +623,8 @@ static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
        ns_now = __cycles_2_ns(tsc_now);
        if (cpu_khz) {
-                *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
+                *scale = ((NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR) +
+                                cpu_khz / 2) / cpu_khz;
                *offset = ns_now - mult_frac(tsc_now, *scale,
                                             (1UL << CYC2NS_SCALE_FACTOR));
        }
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c
index c71025b67462..0ba4cfb4f412 100644
--- a/arch/x86/kernel/uprobes.c
+++ b/arch/x86/kernel/uprobes.c
@@ -680,8 +680,10 @@ static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
                if (auprobe->insn[i] == 0x66)
                        continue;
-                if (auprobe->insn[i] == 0x90)
+                if (auprobe->insn[i] == 0x90) {
+                        regs->ip += i + 1;
                        return true;
+                }
                break;
        }
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 7a3d075a814a..d065d67c2672 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -19,6 +19,7 @@
 #include <asm/time.h>
 #include <asm/irq.h>
 #include <asm/io_apic.h>
+#include <asm/hpet.h>
 #include <asm/pat.h>
 #include <asm/tsc.h>
 #include <asm/iommu.h>
@@ -111,15 +112,22 @@ struct x86_platform_ops x86_platform = {
 EXPORT_SYMBOL_GPL(x86_platform);
 struct x86_msi_ops x86_msi = {
-        .setup_msi_irqs = native_setup_msi_irqs,
+        .setup_msi_irqs         = native_setup_msi_irqs,
-        .teardown_msi_irq = native_teardown_msi_irq,
+        .compose_msi_msg        = native_compose_msi_msg,
-        .teardown_msi_irqs = default_teardown_msi_irqs,
+        .teardown_msi_irq       = native_teardown_msi_irq,
-        .restore_msi_irqs = default_restore_msi_irqs,
+        .teardown_msi_irqs      = default_teardown_msi_irqs,
+        .restore_msi_irqs       = default_restore_msi_irqs,
+        .setup_hpet_msi         = default_setup_hpet_msi,
 };
 struct x86_io_apic_ops x86_io_apic_ops = {
-        .init   = native_io_apic_init_mappings,
+        .init                   = native_io_apic_init_mappings,
-        .read   = native_io_apic_read,
+        .read                   = native_io_apic_read,
-        .write  = native_io_apic_write,
+        .write                  = native_io_apic_write,
-        .modify = native_io_apic_modify,
+        .modify                 = native_io_apic_modify,
+        .disable                = native_disable_io_apic,
+        .print_entries          = native_io_apic_print_entries,
+        .set_affinity           = native_ioapic_set_affinity,
+        .setup_entry            = native_setup_ioapic_entry,
+        .eoi_ioapic_pin         = native_eoi_ioapic_pin,
 };
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 027088f2f7dd..fb674fd3fc22 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -748,13 +748,15 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
                                return;
                }
 #endif
+                /* Kernel addresses are always protection faults: */
+                if (address >= TASK_SIZE)
+                        error_code |= PF_PROT;
-                if (unlikely(show_unhandled_signals))
+                if (likely(show_unhandled_signals))
                        show_signal_msg(regs, error_code, address, tsk);
-                /* Kernel addresses are always protection faults: */
                tsk->thread.cr2         = address;
-                tsk->thread.error_code  = error_code | (address >= TASK_SIZE);
+                tsk->thread.error_code  = error_code;
                tsk->thread.trap_nr     = X86_TRAP_PF;
                force_sig_info_fault(SIGSEGV, si_code, address, tsk, 0);
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 2ead3c8a4c84..d6eeead43758 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -605,7 +605,7 @@ kernel_physical_mapping_init(unsigned long start,
        }
        if (pgd_changed)
-                sync_global_pgds(addr, end);
+                sync_global_pgds(addr, end - 1);
        __flush_tlb_all();
@@ -831,6 +831,9 @@ int kern_addr_valid(unsigned long addr)
        if (pud_none(*pud))
                return 0;
+        if (pud_large(*pud))
+                return pfn_valid(pud_pfn(*pud));
        pmd = pmd_offset(pud, addr);
        if (pmd_none(*pmd))
                return 0;
@@ -981,7 +984,7 @@ vmemmap_populate(struct page *start_page, unsigned long size, int node)
                }
        }
-        sync_global_pgds((unsigned long)start_page, end);
+        sync_global_pgds((unsigned long)start_page, end - 1);
        return 0;
 }
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index ad4439145f85..928bf837040a 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -51,9 +51,6 @@
 #define EFI_DEBUG       1
-int efi_enabled;
-EXPORT_SYMBOL(efi_enabled);
 struct efi __read_mostly efi = {
        .mps        = EFI_INVALID_TABLE_ADDR,
        .acpi       = EFI_INVALID_TABLE_ADDR,
@@ -69,19 +66,28 @@ EXPORT_SYMBOL(efi);
 struct efi_memory_map memmap;
-bool efi_64bit;
 static struct efi efi_phys __initdata;
 static efi_system_table_t efi_systab __initdata;
 static inline bool efi_is_native(void)
 {
-        return IS_ENABLED(CONFIG_X86_64) == efi_64bit;
+        return IS_ENABLED(CONFIG_X86_64) == efi_enabled(EFI_64BIT);
+}
+unsigned long x86_efi_facility;
+/*
+ * Returns 1 if 'facility' is enabled, 0 otherwise.
+ */
+int efi_enabled(int facility)
+{
+        return test_bit(facility, &x86_efi_facility) != 0;
 }
+EXPORT_SYMBOL(efi_enabled);
 static int __init setup_noefi(char *arg)
 {
-        efi_enabled = 0;
+        clear_bit(EFI_RUNTIME_SERVICES, &x86_efi_facility);
        return 0;
 }
 early_param("noefi", setup_noefi);
@@ -426,6 +432,7 @@ void __init efi_reserve_boot_services(void)
 void __init efi_unmap_memmap(void)
 {
+        clear_bit(EFI_MEMMAP, &x86_efi_facility);
        if (memmap.map) {
                early_iounmap(memmap.map, memmap.nr_map * memmap.desc_size);
                memmap.map = NULL;
@@ -460,7 +467,7 @@ void __init efi_free_boot_services(void)
 static int __init efi_systab_init(void *phys)
 {
-        if (efi_64bit) {
+        if (efi_enabled(EFI_64BIT)) {
                efi_system_table_64_t *systab64;
                u64 tmp = 0;
@@ -552,7 +559,7 @@ static int __init efi_config_init(u64 tables, int nr_tables)
        void *config_tables, *tablep;
        int i, sz;
-        if (efi_64bit)
+        if (efi_enabled(EFI_64BIT))
                sz = sizeof(efi_config_table_64_t);
        else
                sz = sizeof(efi_config_table_32_t);
@@ -572,7 +579,7 @@ static int __init efi_config_init(u64 tables, int nr_tables)
                efi_guid_t guid;
                unsigned long table;
-                if (efi_64bit) {
+                if (efi_enabled(EFI_64BIT)) {
                        u64 table64;
                        guid = ((efi_config_table_64_t *)tablep)->guid;
                        table64 = ((efi_config_table_64_t *)tablep)->table;
@@ -684,7 +691,6 @@ void __init efi_init(void)
        if (boot_params.efi_info.efi_systab_hi ||
            boot_params.efi_info.efi_memmap_hi) {
                pr_info("Table located above 4GB, disabling EFI.\n");
-                efi_enabled = 0;
                return;
        }
        efi_phys.systab = (efi_system_table_t *)boot_params.efi_info.efi_systab;
@@ -694,10 +700,10 @@ void __init efi_init(void)
                          ((__u64)boot_params.efi_info.efi_systab_hi<<32));
 #endif
-        if (efi_systab_init(efi_phys.systab)) {
+        if (efi_systab_init(efi_phys.systab))
-                efi_enabled = 0;
                return;
-        }
+        set_bit(EFI_SYSTEM_TABLES, &x86_efi_facility);
        /*
         * Show what we know for posterity
@@ -715,10 +721,10 @@ void __init efi_init(void)
                efi.systab->hdr.revision >> 16,
                efi.systab->hdr.revision & 0xffff, vendor);
-        if (efi_config_init(efi.systab->tables, efi.systab->nr_tables)) {
+        if (efi_config_init(efi.systab->tables, efi.systab->nr_tables))
-                efi_enabled = 0;
                return;
-        }
+        set_bit(EFI_CONFIG_TABLES, &x86_efi_facility);
        /*
         * Note: We currently don't support runtime services on an EFI
@@ -727,15 +733,17 @@ void __init efi_init(void)
        if (!efi_is_native())
                pr_info("No EFI runtime due to 32/64-bit mismatch with kernel\n");
-        else if (efi_runtime_init()) {
+        else {
-                efi_enabled = 0;
+                if (efi_runtime_init())
-                return;
+                        return;
+                set_bit(EFI_RUNTIME_SERVICES, &x86_efi_facility);
        }
-        if (efi_memmap_init()) {
+        if (efi_memmap_init())
-                efi_enabled = 0;
                return;
-        }
+        set_bit(EFI_MEMMAP, &x86_efi_facility);
 #ifdef CONFIG_X86_32
        if (efi_is_native()) {
                x86_platform.get_wallclock = efi_get_time;
@@ -941,7 +949,7 @@ void __init efi_enter_virtual_mode(void)
         *
         * Call EFI services through wrapper functions.
         */
-        efi.runtime_version = efi_systab.fw_revision;
+        efi.runtime_version = efi_systab.hdr.revision;
        efi.get_time = virt_efi_get_time;
        efi.set_time = virt_efi_set_time;
        efi.get_wakeup_time = virt_efi_get_wakeup_time;
@@ -969,6 +977,9 @@ u32 efi_mem_type(unsigned long phys_addr)
        efi_memory_desc_t *md;
        void *p;
+        if (!efi_enabled(EFI_MEMMAP))
+                return 0;
        for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
                md = p;
                if ((md->phys_addr <= phys_addr) &&
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 95fd505dfeb6..2b2003860615 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -38,7 +38,7 @@
 #include <asm/cacheflush.h>
 #include <asm/fixmap.h>
-static pgd_t save_pgd __initdata;
+static pgd_t *save_pgd __initdata;
 static unsigned long efi_flags __initdata;
 static void __init early_code_mapping_set_exec(int executable)
@@ -61,12 +61,20 @@ static void __init early_code_mapping_set_exec(int executable)
 void __init efi_call_phys_prelog(void)
 {
        unsigned long vaddress;
+        int pgd;
+        int n_pgds;
        early_code_mapping_set_exec(1);
        local_irq_save(efi_flags);
-        vaddress = (unsigned long)__va(0x0UL);
-        save_pgd = *pgd_offset_k(0x0UL);
+        n_pgds = DIV_ROUND_UP((max_pfn << PAGE_SHIFT), PGDIR_SIZE);
-        set_pgd(pgd_offset_k(0x0UL), *pgd_offset_k(vaddress));
+        save_pgd = kmalloc(n_pgds * sizeof(pgd_t), GFP_KERNEL);
+        for (pgd = 0; pgd < n_pgds; pgd++) {
+                save_pgd[pgd] = *pgd_offset_k(pgd * PGDIR_SIZE);
+                vaddress = (unsigned long)__va(pgd * PGDIR_SIZE);
+                set_pgd(pgd_offset_k(pgd * PGDIR_SIZE), *pgd_offset_k(vaddress));
+        }
        __flush_tlb_all();
 }
@@ -75,7 +83,11 @@ void __init efi_call_phys_epilog(void)
        /*
         * After the lock is released, the original page table is restored.
         */
-        set_pgd(pgd_offset_k(0x0UL), save_pgd);
+        int pgd;
+        int n_pgds = DIV_ROUND_UP((max_pfn << PAGE_SHIFT) , PGDIR_SIZE);
+        for (pgd = 0; pgd < n_pgds; pgd++)
+                set_pgd(pgd_offset_k(pgd * PGDIR_SIZE), save_pgd[pgd]);
+        kfree(save_pgd);
        __flush_tlb_all();
        local_irq_restore(efi_flags);
        early_code_mapping_set_exec(0);
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index b8b3a37c80cd..dbbdca5f508c 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -1034,7 +1034,8 @@ static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
 * globally purge translation cache of a virtual address or all TLB's
 * @cpumask: mask of all cpu's in which the address is to be removed
 * @mm: mm_struct containing virtual address range
- * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
+ * @start: start virtual address to be removed from TLB
+ * @end: end virtual address to be remove from TLB
 * @cpu: the current cpu
 *
 * This is the entry point for initiating any UV global TLB shootdown.
@@ -1056,7 +1057,7 @@ static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
 */
 const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
                                struct mm_struct *mm, unsigned long start,
-                                unsigned end, unsigned int cpu)
+                                unsigned long end, unsigned int cpu)
 {
        int locals = 0;
        int remotes = 0;
@@ -1113,7 +1114,10 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
        record_send_statistics(stat, locals, hubs, remotes, bau_desc);
-        bau_desc->payload.address = start;
+        if (!end || (end - start) <= PAGE_SIZE)
+                bau_desc->payload.address = start;
+        else
+                bau_desc->payload.address = TLB_FLUSH_ALL;
        bau_desc->payload.sending_cpu = cpu;
        /*
         * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
diff --git a/arch/x86/tools/insn_sanity.c b/arch/x86/tools/insn_sanity.c
index cc2f8c131286..872eb60e7806 100644
--- a/arch/x86/tools/insn_sanity.c
+++ b/arch/x86/tools/insn_sanity.c
@@ -55,7 +55,7 @@ static FILE		*input_file;	/* Input file name */
 static void usage(const char *err)
 {
        if (err)
-                fprintf(stderr, "Error: %s\n\n", err);
+                fprintf(stderr, "%s: Error: %s\n\n", prog, err);
        fprintf(stderr, "Usage: %s [-y|-n|-v] [-s seed[,no]] [-m max] [-i input]\n", prog);
        fprintf(stderr, "\t-y   64bit mode\n");
        fprintf(stderr, "\t-n   32bit mode\n");
@@ -269,7 +269,13 @@ int main(int argc, char **argv)
                insns++;
        }
-        fprintf(stdout, "%s: decoded and checked %d %s instructions with %d errors (seed:0x%x)\n", (errors) ? "Failure" : "Success", insns, (input_file) ? "given" : "random", errors, seed);
+        fprintf(stdout, "%s: %s: decoded and checked %d %s instructions with %d errors (seed:0x%x)\n",
+                prog,
+                (errors) ? "Failure" : "Success",
+                insns,
+                (input_file) ? "given" : "random",
+                errors,
+                seed);
        return errors ? 1 : 0;
 }
diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c
index 205ad328aa52..c74436e687bf 100644
--- a/arch/x86/vdso/vclock_gettime.c
+++ b/arch/x86/vdso/vclock_gettime.c
@@ -60,7 +60,7 @@ notrace static cycle_t vread_tsc(void)
 static notrace cycle_t vread_hpet(void)
 {
-        return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
+        return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + HPET_COUNTER);
 }
 #ifdef CONFIG_PARAVIRT_CLOCK
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 138e5667409a..39928d16be3b 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1517,72 +1517,51 @@ asmlinkage void __init xen_start_kernel(void)
 #endif
 }
-#ifdef CONFIG_XEN_PVHVM
+void __ref xen_hvm_init_shared_info(void)
-#define HVM_SHARED_INFO_ADDR 0xFE700000UL
-static struct shared_info *xen_hvm_shared_info;
-static unsigned long xen_hvm_sip_phys;
-static int xen_major, xen_minor;
-static void xen_hvm_connect_shared_info(unsigned long pfn)
 {
+        int cpu;
        struct xen_add_to_physmap xatp;
+        static struct shared_info *shared_info_page = 0;
+        if (!shared_info_page)
+                shared_info_page = (struct shared_info *)
+                        extend_brk(PAGE_SIZE, PAGE_SIZE);
        xatp.domid = DOMID_SELF;
        xatp.idx = 0;
        xatp.space = XENMAPSPACE_shared_info;
-        xatp.gpfn = pfn;
+        xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
        if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
                BUG();
-}
+        HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
-static void __init xen_hvm_set_shared_info(struct shared_info *sip)
-{
-        int cpu;
-        HYPERVISOR_shared_info = sip;
        /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
         * page, we use it in the event channel upcall and in some pvclock
         * related functions. We don't need the vcpu_info placement
         * optimizations because we don't use any pv_mmu or pv_irq op on
-         * HVM. */
+         * HVM.
-        for_each_online_cpu(cpu)
+         * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is
+         * online but xen_hvm_init_shared_info is run at resume time too and
+         * in that case multiple vcpus might be online. */
+        for_each_online_cpu(cpu) {
                per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
-}
-/* Reconnect the shared_info pfn to a (new) mfn */
-void xen_hvm_resume_shared_info(void)
-{
-        xen_hvm_connect_shared_info(xen_hvm_sip_phys >> PAGE_SHIFT);
-}
-/* Xen tools prior to Xen 4 do not provide a E820_Reserved area for guest usage.
- * On these old tools the shared info page will be placed in E820_Ram.
- * Xen 4 provides a E820_Reserved area at 0xFC000000, and this code expects
- * that nothing is mapped up to HVM_SHARED_INFO_ADDR.
- * Xen 4.3+ provides an explicit 1MB area at HVM_SHARED_INFO_ADDR which is used
- * here for the shared info page. */
-static void __init xen_hvm_init_shared_info(void)
-{
-        if (xen_major < 4) {
-                xen_hvm_shared_info = extend_brk(PAGE_SIZE, PAGE_SIZE);
-                xen_hvm_sip_phys = __pa(xen_hvm_shared_info);
-        } else {
-                xen_hvm_sip_phys = HVM_SHARED_INFO_ADDR;
-                set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_hvm_sip_phys);
-                xen_hvm_shared_info =
-                (struct shared_info *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
        }
-        xen_hvm_connect_shared_info(xen_hvm_sip_phys >> PAGE_SHIFT);
-        xen_hvm_set_shared_info(xen_hvm_shared_info);
 }
+#ifdef CONFIG_XEN_PVHVM
 static void __init init_hvm_pv_info(void)
 {
-        uint32_t ecx, edx, pages, msr, base;
+        int major, minor;
+        uint32_t eax, ebx, ecx, edx, pages, msr, base;
        u64 pfn;
        base = xen_cpuid_base();
+        cpuid(base + 1, &eax, &ebx, &ecx, &edx);
+        major = eax >> 16;
+        minor = eax & 0xffff;
+        printk(KERN_INFO "Xen version %d.%d.\n", major, minor);
        cpuid(base + 2, &pages, &msr, &ecx, &edx);
        pfn = __pa(hypercall_page);
@@ -1633,22 +1612,12 @@ static void __init xen_hvm_guest_init(void)
 static bool __init xen_hvm_platform(void)
 {
-        uint32_t eax, ebx, ecx, edx, base;
        if (xen_pv_domain())
                return false;
-        base = xen_cpuid_base();
+        if (!xen_cpuid_base())
-        if (!base)
                return false;
-        cpuid(base + 1, &eax, &ebx, &ecx, &edx);
-        xen_major = eax >> 16;
-        xen_minor = eax & 0xffff;
-        printk(KERN_INFO "Xen version %d.%d.\n", xen_major, xen_minor);
        return true;
 }
@@ -1668,6 +1637,7 @@ const struct hypervisor_x86 x86_hyper_xen_hvm __refconst = {
        .name                   = "Xen HVM",
        .detect                 = xen_hvm_platform,
        .init_platform          = xen_hvm_guest_init,
+        .x2apic_available       = xen_x2apic_para_available,
 };
 EXPORT_SYMBOL(x86_hyper_xen_hvm);
 #endif
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
index ae8a00c39de4..45329c8c226e 100644
--- a/arch/x86/xen/suspend.c
+++ b/arch/x86/xen/suspend.c
@@ -30,7 +30,7 @@ void xen_arch_hvm_post_suspend(int suspend_cancelled)
 {
 #ifdef CONFIG_XEN_PVHVM
        int cpu;
-        xen_hvm_resume_shared_info();
+        xen_hvm_init_shared_info();
        xen_callback_vector();
        xen_unplug_emulated_devices();
        if (xen_feature(XENFEAT_hvm_safe_pvclock)) {
diff --git a/arch/x86/xen/xen-asm_32.S b/arch/x86/xen/xen-asm_32.S
index f9643fc50de5..33ca6e42a4ca 100644
--- a/arch/x86/xen/xen-asm_32.S
+++ b/arch/x86/xen/xen-asm_32.S
@@ -89,11 +89,11 @@ ENTRY(xen_iret)
         */
 #ifdef CONFIG_SMP
        GET_THREAD_INFO(%eax)
-        movl TI_cpu(%eax), %eax
+        movl %ss:TI_cpu(%eax), %eax
-        movl __per_cpu_offset(,%eax,4), %eax
+        movl %ss:__per_cpu_offset(,%eax,4), %eax
-        mov xen_vcpu(%eax), %eax
+        mov %ss:xen_vcpu(%eax), %eax
 #else
-        movl xen_vcpu, %eax
+        movl %ss:xen_vcpu, %eax
 #endif
        /* check IF state we're restoring */
@@ -106,11 +106,11 @@ ENTRY(xen_iret)
         * resuming the code, so we don't have to be worried about
         * being preempted to another CPU.
         */
-        setz XEN_vcpu_info_mask(%eax)
+        setz %ss:XEN_vcpu_info_mask(%eax)
 xen_iret_start_crit:
        /* check for unmasked and pending */
-        cmpw $0x0001, XEN_vcpu_info_pending(%eax)
+        cmpw $0x0001, %ss:XEN_vcpu_info_pending(%eax)
        /*
         * If there's something pending, mask events again so we can
@@ -118,7 +118,7 @@ xen_iret_start_crit:
         * touch XEN_vcpu_info_mask.
         */
        jne 1f
-        movb $1, XEN_vcpu_info_mask(%eax)
+        movb $1, %ss:XEN_vcpu_info_mask(%eax)
 1:      popl %eax
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index d2e73d19d366..a95b41744ad0 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -40,7 +40,7 @@ void xen_enable_syscall(void);
 void xen_vcpu_restore(void);
 void xen_callback_vector(void);
-void xen_hvm_resume_shared_info(void);
+void xen_hvm_init_shared_info(void);
 void xen_unplug_emulated_devices(void);
 void __init xen_build_dynamic_phys_to_machine(void);
diff --git a/arch/xtensa/include/asm/dma-mapping.h b/arch/xtensa/include/asm/dma-mapping.h
index 4acb5feba1fb..172a02a6ad14 100644
--- a/arch/xtensa/include/asm/dma-mapping.h
+++ b/arch/xtensa/include/asm/dma-mapping.h
@@ -170,4 +170,19 @@ dma_cache_sync(struct device *dev, void *vaddr, size_t size,
        consistent_sync(vaddr, size, direction);
 }
+/* Not supported for now */
+static inline int dma_mmap_coherent(struct device *dev,
+                                    struct vm_area_struct *vma, void *cpu_addr,
+                                    dma_addr_t dma_addr, size_t size)
+{
+        return -EINVAL;
+}
+static inline int dma_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                  void *cpu_addr, dma_addr_t dma_addr,
+                                  size_t size)
+{
+        return -EINVAL;
+}
 #endif  /* _XTENSA_DMA_MAPPING_H */