1160 files changed, 67147 insertions, 16267 deletions
diff --git a/arch/alpha/include/asm/8253pit.h b/arch/alpha/include/asm/8253pit.h
index fef5c1450e47..a71c9c1455a7 100644
--- a/arch/alpha/include/asm/8253pit.h
+++ b/arch/alpha/include/asm/8253pit.h
@@ -1,10 +1,3 @@
 /*
 * 8253/8254 Programmable Interval Timer
 */
-#ifndef _8253PIT_H
-#define _8253PIT_H
-#define PIT_TICK_RATE   1193180UL
-#endif
diff --git a/arch/alpha/include/asm/errno.h b/arch/alpha/include/asm/errno.h
index 69e2655249d2..98099bda9370 100644
--- a/arch/alpha/include/asm/errno.h
+++ b/arch/alpha/include/asm/errno.h
@@ -120,4 +120,6 @@
 #define EOWNERDEAD      136     /* Owner died */
 #define ENOTRECOVERABLE 137     /* State not recoverable */
+#define ERFKILL         138     /* Operation not possible due to RF-kill */
 #endif
diff --git a/arch/alpha/include/asm/kmap_types.h b/arch/alpha/include/asm/kmap_types.h
index 3e6735a34c57..a8d4ec8ea4b6 100644
--- a/arch/alpha/include/asm/kmap_types.h
+++ b/arch/alpha/include/asm/kmap_types.h
@@ -3,30 +3,12 @@
 /* Dummy header just to define km_type. */
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
+#define  __WITH_KM_FENCE
-#else
-# define D(n)
 #endif
-enum km_type {
+#include <asm-generic/kmap_types.h>
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-#undef D
+#undef __WITH_KM_FENCE
 #endif
diff --git a/arch/alpha/kernel/init_task.c b/arch/alpha/kernel/init_task.c
index c2938e574a40..19b86328ffd7 100644
--- a/arch/alpha/kernel/init_task.c
+++ b/arch/alpha/kernel/init_task.c
@@ -10,10 +10,7 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
 struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_mm);
 EXPORT_SYMBOL(init_task);
 union thread_union init_thread_union
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 67c19f8a9944..38c805dfc544 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -227,7 +227,7 @@ struct irqaction timer_irqaction = {
        .name           = "timer",
 };
-static struct hw_interrupt_type rtc_irq_type = {
+static struct irq_chip rtc_irq_type = {
        .typename       = "RTC",
        .startup        = rtc_startup,
        .shutdown       = rtc_enable_disable,
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c
index 9405bee9894e..50bfec9b588f 100644
--- a/arch/alpha/kernel/irq_i8259.c
+++ b/arch/alpha/kernel/irq_i8259.c
@@ -83,7 +83,7 @@ i8259a_end_irq(unsigned int irq)
                i8259a_enable_irq(irq);
 }
-struct hw_interrupt_type i8259a_irq_type = {
+struct irq_chip i8259a_irq_type = {
        .typename       = "XT-PIC",
        .startup        = i8259a_startup_irq,
        .shutdown       = i8259a_disable_irq,
diff --git a/arch/alpha/kernel/irq_impl.h b/arch/alpha/kernel/irq_impl.h
index cc9a8a7aa279..b63ccd7386f1 100644
--- a/arch/alpha/kernel/irq_impl.h
+++ b/arch/alpha/kernel/irq_impl.h
@@ -36,7 +36,7 @@ extern void i8259a_disable_irq(unsigned int);
 extern void i8259a_mask_and_ack_irq(unsigned int);
 extern unsigned int i8259a_startup_irq(unsigned int);
 extern void i8259a_end_irq(unsigned int);
-extern struct hw_interrupt_type i8259a_irq_type;
+extern struct irq_chip i8259a_irq_type;
 extern void init_i8259a_irqs(void);
 extern void handle_irq(int irq);
diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c
index d53edbccbfe5..69199a76ec4a 100644
--- a/arch/alpha/kernel/irq_pyxis.c
+++ b/arch/alpha/kernel/irq_pyxis.c
@@ -70,7 +70,7 @@ pyxis_mask_and_ack_irq(unsigned int irq)
        *(vulp)PYXIS_INT_MASK;
 }
-static struct hw_interrupt_type pyxis_irq_type = {
+static struct irq_chip pyxis_irq_type = {
        .typename       = "PYXIS",
        .startup        = pyxis_startup_irq,
        .shutdown       = pyxis_disable_irq,
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c
index a03fbca4940e..85229369a1f8 100644
--- a/arch/alpha/kernel/irq_srm.c
+++ b/arch/alpha/kernel/irq_srm.c
@@ -48,7 +48,7 @@ srm_end_irq(unsigned int irq)
 }
 /* Handle interrupts from the SRM, assuming no additional weirdness.  */
-static struct hw_interrupt_type srm_irq_type = {
+static struct irq_chip srm_irq_type = {
        .typename       = "SRM",
        .startup        = srm_startup_irq,
        .shutdown       = srm_disable_irq,
diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c
index 80df86cd746b..d2634e4476b4 100644
--- a/arch/alpha/kernel/setup.c
+++ b/arch/alpha/kernel/setup.c
@@ -252,9 +252,9 @@ reserve_std_resources(void)
 }
 #define PFN_MAX         PFN_DOWN(0x80000000)
-#define for_each_mem_cluster(memdesc, cluster, i)               \
+#define for_each_mem_cluster(memdesc, _cluster, i)              \
-        for ((cluster) = (memdesc)->cluster, (i) = 0;           \
+        for ((_cluster) = (memdesc)->cluster, (i) = 0;          \
-             (i) < (memdesc)->numclusters; (i)++, (cluster)++)
+             (i) < (memdesc)->numclusters; (i)++, (_cluster)++)
 static unsigned long __init
 get_mem_size_limit(char *s)
diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c
index e53a1e1c2f21..382035ef7394 100644
--- a/arch/alpha/kernel/sys_alcor.c
+++ b/arch/alpha/kernel/sys_alcor.c
@@ -89,7 +89,7 @@ alcor_end_irq(unsigned int irq)
                alcor_enable_irq(irq);
 }
-static struct hw_interrupt_type alcor_irq_type = {
+static struct irq_chip alcor_irq_type = {
        .typename       = "ALCOR",
        .startup        = alcor_startup_irq,
        .shutdown       = alcor_disable_irq,
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c
index ace475c124f6..ed349436732b 100644
--- a/arch/alpha/kernel/sys_cabriolet.c
+++ b/arch/alpha/kernel/sys_cabriolet.c
@@ -71,7 +71,7 @@ cabriolet_end_irq(unsigned int irq)
                cabriolet_enable_irq(irq);
 }
-static struct hw_interrupt_type cabriolet_irq_type = {
+static struct irq_chip cabriolet_irq_type = {
        .typename       = "CABRIOLET",
        .startup        = cabriolet_startup_irq,
        .shutdown       = cabriolet_disable_irq,
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
index 5bd5259324b7..46e70ece5176 100644
--- a/arch/alpha/kernel/sys_dp264.c
+++ b/arch/alpha/kernel/sys_dp264.c
@@ -198,7 +198,7 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
        return 0;
 }
-static struct hw_interrupt_type dp264_irq_type = {
+static struct irq_chip dp264_irq_type = {
        .typename       = "DP264",
        .startup        = dp264_startup_irq,
        .shutdown       = dp264_disable_irq,
@@ -209,7 +209,7 @@ static struct hw_interrupt_type dp264_irq_type = {
        .set_affinity   = dp264_set_affinity,
 };
-static struct hw_interrupt_type clipper_irq_type = {
+static struct irq_chip clipper_irq_type = {
        .typename       = "CLIPPER",
        .startup        = clipper_startup_irq,
        .shutdown       = clipper_disable_irq,
@@ -298,7 +298,7 @@ clipper_srm_device_interrupt(unsigned long vector)
 }
 static void __init
-init_tsunami_irqs(struct hw_interrupt_type * ops, int imin, int imax)
+init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
 {
        long i;
        for (i = imin; i <= imax; ++i) {
diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c
index 9c5a306dc0ee..660c23ef661f 100644
--- a/arch/alpha/kernel/sys_eb64p.c
+++ b/arch/alpha/kernel/sys_eb64p.c
@@ -69,7 +69,7 @@ eb64p_end_irq(unsigned int irq)
                eb64p_enable_irq(irq);
 }
-static struct hw_interrupt_type eb64p_irq_type = {
+static struct irq_chip eb64p_irq_type = {
        .typename       = "EB64P",
        .startup        = eb64p_startup_irq,
        .shutdown       = eb64p_disable_irq,
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c
index baf60f36cbd7..b99ea488d844 100644
--- a/arch/alpha/kernel/sys_eiger.c
+++ b/arch/alpha/kernel/sys_eiger.c
@@ -80,7 +80,7 @@ eiger_end_irq(unsigned int irq)
                eiger_enable_irq(irq);
 }
-static struct hw_interrupt_type eiger_irq_type = {
+static struct irq_chip eiger_irq_type = {
        .typename       = "EIGER",
        .startup        = eiger_startup_irq,
        .shutdown       = eiger_disable_irq,
diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c
index 2b5caf3d9b15..ef0b83a070ac 100644
--- a/arch/alpha/kernel/sys_jensen.c
+++ b/arch/alpha/kernel/sys_jensen.c
@@ -118,7 +118,7 @@ jensen_local_end(unsigned int irq)
                i8259a_end_irq(1);
 }
-static struct hw_interrupt_type jensen_local_irq_type = {
+static struct irq_chip jensen_local_irq_type = {
        .typename       = "LOCAL",
        .startup        = jensen_local_startup,
        .shutdown       = jensen_local_shutdown,
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index c5a1a2438c67..bbfc4f20ca72 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -169,7 +169,7 @@ marvel_irq_noop_return(unsigned int irq)
        return 0; 
 }
-static struct hw_interrupt_type marvel_legacy_irq_type = {
+static struct irq_chip marvel_legacy_irq_type = {
        .typename       = "LEGACY",
        .startup        = marvel_irq_noop_return,
        .shutdown       = marvel_irq_noop,
@@ -179,7 +179,7 @@ static struct hw_interrupt_type marvel_legacy_irq_type = {
        .end            = marvel_irq_noop,
 };
-static struct hw_interrupt_type io7_lsi_irq_type = {
+static struct irq_chip io7_lsi_irq_type = {
        .typename       = "LSI",
        .startup        = io7_startup_irq,
        .shutdown       = io7_disable_irq,
@@ -189,7 +189,7 @@ static struct hw_interrupt_type io7_lsi_irq_type = {
        .end            = io7_end_irq,
 };
-static struct hw_interrupt_type io7_msi_irq_type = {
+static struct irq_chip io7_msi_irq_type = {
        .typename       = "MSI",
        .startup        = io7_startup_irq,
        .shutdown       = io7_disable_irq,
@@ -273,8 +273,8 @@ init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where)
 static void __init
 init_io7_irqs(struct io7 *io7, 
-              struct hw_interrupt_type *lsi_ops,
+              struct irq_chip *lsi_ops,
-              struct hw_interrupt_type *msi_ops)
+              struct irq_chip *msi_ops)
 {
        long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;
        long i;
diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c
index 8d3e9429c5ee..4e366641a08e 100644
--- a/arch/alpha/kernel/sys_mikasa.c
+++ b/arch/alpha/kernel/sys_mikasa.c
@@ -68,7 +68,7 @@ mikasa_end_irq(unsigned int irq)
                mikasa_enable_irq(irq);
 }
-static struct hw_interrupt_type mikasa_irq_type = {
+static struct irq_chip mikasa_irq_type = {
        .typename       = "MIKASA",
        .startup        = mikasa_startup_irq,
        .shutdown       = mikasa_disable_irq,
diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c
index 538876b62449..35753a173bac 100644
--- a/arch/alpha/kernel/sys_noritake.c
+++ b/arch/alpha/kernel/sys_noritake.c
@@ -73,7 +73,7 @@ noritake_end_irq(unsigned int irq)
                noritake_enable_irq(irq);
 }
-static struct hw_interrupt_type noritake_irq_type = {
+static struct irq_chip noritake_irq_type = {
        .typename       = "NORITAKE",
        .startup        = noritake_startup_irq,
        .shutdown       = noritake_disable_irq,
diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c
index 672cb2df53df..f3aec7e085c8 100644
--- a/arch/alpha/kernel/sys_rawhide.c
+++ b/arch/alpha/kernel/sys_rawhide.c
@@ -135,7 +135,7 @@ rawhide_end_irq(unsigned int irq)
                rawhide_enable_irq(irq);
 }
-static struct hw_interrupt_type rawhide_irq_type = {
+static struct irq_chip rawhide_irq_type = {
        .typename       = "RAWHIDE",
        .startup        = rawhide_startup_irq,
        .shutdown       = rawhide_disable_irq,
diff --git a/arch/alpha/kernel/sys_ruffian.c b/arch/alpha/kernel/sys_ruffian.c
index f15a329b6011..d9f9cfeb9931 100644
--- a/arch/alpha/kernel/sys_ruffian.c
+++ b/arch/alpha/kernel/sys_ruffian.c
@@ -14,6 +14,7 @@
 #include <linux/sched.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
+#include <linux/timex.h>
 #include <linux/init.h>
 #include <asm/ptrace.h>
diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c
index ce1faa6f1df1..fc9246373452 100644
--- a/arch/alpha/kernel/sys_rx164.c
+++ b/arch/alpha/kernel/sys_rx164.c
@@ -72,7 +72,7 @@ rx164_end_irq(unsigned int irq)
                rx164_enable_irq(irq);
 }
-static struct hw_interrupt_type rx164_irq_type = {
+static struct irq_chip rx164_irq_type = {
        .typename       = "RX164",
        .startup        = rx164_startup_irq,
        .shutdown       = rx164_disable_irq,
diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c
index 9e263256a42d..426eb6906d01 100644
--- a/arch/alpha/kernel/sys_sable.c
+++ b/arch/alpha/kernel/sys_sable.c
@@ -501,7 +501,7 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
        spin_unlock(&sable_lynx_irq_lock);
 }
-static struct hw_interrupt_type sable_lynx_irq_type = {
+static struct irq_chip sable_lynx_irq_type = {
        .typename       = "SABLE/LYNX",
        .startup        = sable_lynx_startup_irq,
        .shutdown       = sable_lynx_disable_irq,
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c
index 9bd9a31450c6..830318c21661 100644
--- a/arch/alpha/kernel/sys_takara.c
+++ b/arch/alpha/kernel/sys_takara.c
@@ -74,7 +74,7 @@ takara_end_irq(unsigned int irq)
                takara_enable_irq(irq);
 }
-static struct hw_interrupt_type takara_irq_type = {
+static struct irq_chip takara_irq_type = {
        .typename       = "TAKARA",
        .startup        = takara_startup_irq,
        .shutdown       = takara_disable_irq,
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index 8dd239ebdb9e..88978fc60f83 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -185,7 +185,7 @@ titan_srm_device_interrupt(unsigned long vector)
 static void __init
-init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax)
+init_titan_irqs(struct irq_chip * ops, int imin, int imax)
 {
        long i;
        for (i = imin; i <= imax; ++i) {
@@ -194,7 +194,7 @@ init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax)
        }
 }
-static struct hw_interrupt_type titan_irq_type = {
+static struct irq_chip titan_irq_type = {
       .typename       = "TITAN",
       .startup        = titan_startup_irq,
       .shutdown       = titan_disable_irq,
diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c
index 42c3eede4d09..e91b4c3838a8 100644
--- a/arch/alpha/kernel/sys_wildfire.c
+++ b/arch/alpha/kernel/sys_wildfire.c
@@ -157,7 +157,7 @@ wildfire_end_irq(unsigned int irq)
                wildfire_enable_irq(irq);
 }
-static struct hw_interrupt_type wildfire_irq_type = {
+static struct irq_chip wildfire_irq_type = {
        .typename       = "WILDFIRE",
        .startup        = wildfire_startup_irq,
        .shutdown       = wildfire_disable_irq,
diff --git a/arch/alpha/mm/numa.c b/arch/alpha/mm/numa.c
index a13de49d1265..0eab55749423 100644
--- a/arch/alpha/mm/numa.c
+++ b/arch/alpha/mm/numa.c
@@ -28,9 +28,9 @@ EXPORT_SYMBOL(node_data);
 #define DBGDCONT(args...)
 #endif
-#define for_each_mem_cluster(memdesc, cluster, i)               \
+#define for_each_mem_cluster(memdesc, _cluster, i)              \
-        for ((cluster) = (memdesc)->cluster, (i) = 0;           \
+        for ((_cluster) = (memdesc)->cluster, (i) = 0;          \
-             (i) < (memdesc)->numclusters; (i)++, (cluster)++)
+             (i) < (memdesc)->numclusters; (i)++, (_cluster)++)
 static void __init show_mem_layout(void)
 {
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9d02cdb15b23..29475101a7b3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -34,15 +34,12 @@ config SYS_SUPPORTS_APM_EMULATION
 config GENERIC_GPIO
        bool
-        default n
 config GENERIC_TIME
        bool
-        default n
 config GENERIC_CLOCKEVENTS
        bool
-        default n
 config GENERIC_CLOCKEVENTS_BROADCAST
        bool
@@ -55,7 +52,6 @@ config MMU
 config NO_IOPORT
        bool
-        default n
 config EISA
        bool
@@ -126,11 +122,9 @@ config RWSEM_XCHGADD_ALGORITHM
 config ARCH_HAS_ILOG2_U32
        bool
-        default n
 config ARCH_HAS_ILOG2_U64
        bool
-        default n
 config GENERIC_HWEIGHT
        bool
@@ -253,6 +247,14 @@ config ARCH_CLPS711X
        help
          Support for Cirrus Logic 711x/721x based boards.
+config ARCH_GEMINI
+        bool "Cortina Systems Gemini"
+        select CPU_FA526
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Support for the Cortina Systems Gemini family SoCs
 config ARCH_EBSA110
        bool "EBSA-110"
        select CPU_SA110
@@ -277,14 +279,6 @@ config ARCH_EP93XX
        help
          This enables support for the Cirrus EP93xx series of CPUs.
-config ARCH_GEMINI
-        bool "Cortina Systems Gemini"
-        select CPU_FA526
-        select GENERIC_GPIO
-        select ARCH_REQUIRE_GPIOLIB
-        help
-          Support for the Cortina Systems Gemini family SoCs
 config ARCH_FOOTBRIDGE
        bool "FootBridge"
        select CPU_SA110
@@ -293,6 +287,30 @@ config ARCH_FOOTBRIDGE
          Support for systems based on the DC21285 companion chip
          ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
+config ARCH_MXC
+        bool "Freescale MXC/iMX-based"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select ARCH_MTD_XIP
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
+        help
+          Support for Freescale MXC/iMX-based family of processors
+config ARCH_STMP3XXX
+        bool "Freescale STMP3xxx"
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select USB_ARCH_HAS_EHCI
+        help
+          Support for systems based on the Freescale 3xxx CPUs.
 config ARCH_NETX
        bool "Hilscher NetX based"
        select CPU_ARM926T
@@ -309,15 +327,6 @@ config ARCH_H720X
        help
          This enables support for systems based on the Hynix HMS720x
-config ARCH_IMX
-        bool "IMX"
-        select CPU_ARM920T
-        select GENERIC_GPIO
-        select GENERIC_TIME
-        select GENERIC_CLOCKEVENTS
-        help
-          Support for Motorola's i.MX family of processors (MX1, MXL).
 config ARCH_IOP13XX
        bool "IOP13xx-based"
        depends on MMU
@@ -398,6 +407,7 @@ config ARCH_KIRKWOOD
        select CPU_FEROCEON
        select PCI
        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
        select PLAT_ORION
@@ -405,28 +415,6 @@ config ARCH_KIRKWOOD
          Support for the following Marvell Kirkwood series SoCs:
          88F6180, 88F6192 and 88F6281.
-config ARCH_KS8695
-        bool "Micrel/Kendin KS8695"
-        select CPU_ARM922T
-        select GENERIC_GPIO
-        select ARCH_REQUIRE_GPIOLIB
-        help
-          Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
-          System-on-Chip devices.
-config ARCH_NS9XXX
-        bool "NetSilicon NS9xxx"
-        select CPU_ARM926T
-        select GENERIC_GPIO
-        select GENERIC_TIME
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        help
-          Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
-          System.
-          <http://www.digi.com/products/microprocessors/index.jsp>
 config ARCH_LOKI
        bool "Marvell Loki (88RC8480)"
        select CPU_FEROCEON
@@ -441,6 +429,7 @@ config ARCH_MV78XX0
        select CPU_FEROCEON
        select PCI
        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
        select PLAT_ORION
@@ -448,23 +437,13 @@ config ARCH_MV78XX0
          Support for the following Marvell MV78xx0 series SoCs:
          MV781x0, MV782x0.
-config ARCH_MXC
-        bool "Freescale MXC/iMX-based"
-        select GENERIC_TIME
-        select GENERIC_CLOCKEVENTS
-        select ARCH_MTD_XIP
-        select GENERIC_GPIO
-        select ARCH_REQUIRE_GPIOLIB
-        select HAVE_CLK
-        help
-          Support for Freescale MXC/iMX-based family of processors
 config ARCH_ORION5X
        bool "Marvell Orion"
        depends on MMU
        select CPU_FEROCEON
        select PCI
        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
        select PLAT_ORION
@@ -473,6 +452,52 @@ config ARCH_ORION5X
          Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
          Orion-2 (5281), Orion-1-90 (6183).
+config ARCH_MMP
+        bool "Marvell PXA168/910"
+        depends on MMU
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select TICK_ONESHOT
+        select PLAT_PXA
+        help
+          Support for Marvell's PXA168/910 processor line.
+config ARCH_KS8695
+        bool "Micrel/Kendin KS8695"
+        select CPU_ARM922T
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
+          System-on-Chip devices.
+config ARCH_NS9XXX
+        bool "NetSilicon NS9xxx"
+        select CPU_ARM926T
+        select GENERIC_GPIO
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK
+        help
+          Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
+          System.
+          <http://www.digi.com/products/microprocessors/index.jsp>
+config ARCH_W90X900
+        bool "Nuvoton W90X900 CPU"
+        select CPU_ARM926T
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_GPIO
+        select COMMON_CLKDEV
+        help
+                Support for Nuvoton (Winbond logic dept.) ARM9 processor,You
+                can login www.mcuos.com or www.nuvoton.com to know more.
 config ARCH_PNX4008
        bool "Philips Nexperia PNX4008 Mobile"
        select CPU_ARM926T
@@ -495,19 +520,16 @@ config ARCH_PXA
        help
          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
-config ARCH_MMP
+config ARCH_MSM
-        bool "Marvell PXA168/910"
+        bool "Qualcomm MSM"
-        depends on MMU
+        select CPU_V6
-        select GENERIC_GPIO
-        select ARCH_REQUIRE_GPIOLIB
-        select HAVE_CLK
-        select COMMON_CLKDEV
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
-        select TICK_ONESHOT
-        select PLAT_PXA
        help
-          Support for Marvell's PXA168/910 processor line.
+          Support for Qualcomm MSM7K based systems.  This runs on the ARM11
+          apps processor of the MSM7K and depends on a shared memory
+          interface to the ARM9 modem processor which runs the baseband stack
+          and controls some vital subsystems (clock and power control, etc).
 config ARCH_RPC
        bool "RiscPC"
@@ -576,6 +598,20 @@ config ARCH_LH7A40X
          core with a wide array of integrated devices for
          hand-held and low-power applications.
+config ARCH_U300
+        bool "ST-Ericsson U300 Series"
+        depends on MMU
+        select CPU_ARM926T
+        select ARM_AMBA
+        select ARM_VIC
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_GPIO
+        help
+          Support for ST-Ericsson U300 series mobile platforms.
 config ARCH_DAVINCI
        bool "TI DaVinci"
        select CPU_ARM926T
@@ -587,6 +623,7 @@ config ARCH_DAVINCI
        select ZONE_DMA
        select HAVE_IDE
        select COMMON_CLKDEV
+        select GENERIC_ALLOCATOR
        help
          Support for TI's DaVinci platform.
@@ -600,24 +637,6 @@ config ARCH_OMAP
        help
          Support for TI's OMAP platform (OMAP1 and OMAP2).
-config ARCH_MSM
-        bool "Qualcomm MSM"
-        select CPU_V6
-        select GENERIC_TIME
-        select GENERIC_CLOCKEVENTS
-        help
-          Support for Qualcomm MSM7K based systems.  This runs on the ARM11
-          apps processor of the MSM7K and depends on a shared memory
-          interface to the ARM9 modem processor which runs the baseband stack
-          and controls some vital subsystems (clock and power control, etc).
-config ARCH_W90X900
-        bool "Nuvoton W90X900 CPU"
-        select CPU_ARM926T
-        help
-                Support for Nuvoton (Winbond logic dept.) ARM9 processor,You
-                can login www.mcuos.com or www.nuvoton.com to know more.
 endchoice
 source "arch/arm/mach-clps711x/Kconfig"
@@ -681,9 +700,9 @@ source "arch/arm/mach-s3c6400/Kconfig"
 source "arch/arm/mach-s3c6410/Kconfig"
 endif
-source "arch/arm/mach-lh7a40x/Kconfig"
+source "arch/arm/plat-stmp3xxx/Kconfig"
-source "arch/arm/mach-imx/Kconfig"
+source "arch/arm/mach-lh7a40x/Kconfig"
 source "arch/arm/mach-h720x/Kconfig"
@@ -707,6 +726,8 @@ source "arch/arm/mach-ks8695/Kconfig"
 source "arch/arm/mach-msm/Kconfig"
+source "arch/arm/mach-u300/Kconfig"
 source "arch/arm/mach-w90x900/Kconfig"
 # Definitions to make life easier
@@ -859,8 +880,11 @@ source "kernel/time/Kconfig"
 config SMP
        bool "Symmetric Multi-Processing (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
+        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
+                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
+        depends on GENERIC_CLOCKEVENTS
        select USE_GENERIC_SMP_HELPERS
+        select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
        help
          This enables support for systems with more than one CPU. If you have
          a system with only one CPU, like most personal computers, say N. If
@@ -878,6 +902,18 @@ config SMP
          If you don't know what to do here, say N.
+config HAVE_ARM_SCU
+        bool
+        depends on SMP
+        help
+          This option enables support for the ARM system coherency unit
+config HAVE_ARM_TWD
+        bool
+        depends on SMP
+        help
+          This options enables support for the ARM timer and watchdog unit
 choice
        prompt "Memory split"
        default VMSPLIT_3G
@@ -916,8 +952,10 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
        bool "Use local timer interrupts"
-        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP)
+        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
+                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
        default y
+        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
        help
          Enable support for local timers on SMP platforms, rather then the
          legacy IPI broadcast method.  Local timers allows the system
@@ -979,7 +1017,6 @@ config OABI_COMPAT
 config ARCH_HAS_HOLES_MEMORYMODEL
        bool
-        default n
 # Discontigmem is deprecated
 config ARCH_DISCONTIGMEM_ENABLE
@@ -1022,12 +1059,12 @@ source "mm/Kconfig"
 config LEDS
        bool "Timer and CPU usage LEDs"
        depends on ARCH_CDB89712 || ARCH_EBSA110 || \
-                   ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
+                   ARCH_EBSA285 || ARCH_INTEGRATOR || \
                   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
                   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
                   ARCH_AT91 || ARCH_DAVINCI || \
-                   ARCH_KS8695 || MACH_RD88F5182
+                   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
        help
          If you say Y here, the LEDs on your machine will be used
          to provide useful information about your current system status.
@@ -1085,6 +1122,22 @@ config ALIGNMENT_TRAP
          correct operation of some network protocols. With an IP-only
          configuration it is safe to say N, otherwise say Y.
+config UACCESS_WITH_MEMCPY
+        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
+        depends on MMU && EXPERIMENTAL
+        default y if CPU_FEROCEON
+        help
+          Implement faster copy_to_user and clear_user methods for CPU
+          cores where a 8-word STM instruction give significantly higher
+          memory write throughput than a sequence of individual 32bit stores.
+          A possible side effect is a slight increase in scheduling latency
+          between threads sharing the same address space if they invoke
+          such copy operations with large buffers.
+          However, if the CPU data cache is using a write-allocate mode,
+          this option is unlikely to provide any performance gain.
 endmenu
 menu "Boot options"
@@ -1188,7 +1241,7 @@ endmenu
 menu "CPU Power Management"
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA)
 source "drivers/cpufreq/Kconfig"
@@ -1213,14 +1266,11 @@ config CPU_FREQ_INTEGRATOR
          If in doubt, say Y.
-config CPU_FREQ_IMX
+config CPU_FREQ_PXA
-        tristate "CPUfreq driver for i.MX CPUs"
+        bool
-        depends on ARCH_IMX && CPU_FREQ
+        depends on CPU_FREQ && ARCH_PXA && PXA25x
-        default n
+        default y
-        help
+        select CPU_FREQ_DEFAULT_GOV_USERSPACE
-          This enables the CPUfreq driver for i.MX CPUs.
-          If in doubt, say N.
 endif
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e84729bf13d4..c877d6df23d1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -11,6 +11,9 @@
 # Copyright (C) 1995-2001 by Russell King
 LDFLAGS_vmlinux :=-p --no-undefined -X
+ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
+LDFLAGS_vmlinux += --be8
+endif
 CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
 OBJCOPYFLAGS    :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
 GZFLAGS         :=-9
@@ -99,64 +102,73 @@ CHECKFLAGS	+= -D__arm__
 #Default value
 head-y          := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
 textofs-y       := 0x00008000
+textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
- machine-$(CONFIG_ARCH_RPC)        := rpc
- machine-$(CONFIG_ARCH_EBSA110)    := ebsa110
- machine-$(CONFIG_FOOTBRIDGE)      := footbridge
- machine-$(CONFIG_ARCH_SHARK)      := shark
- machine-$(CONFIG_ARCH_SA1100)     := sa1100
-ifeq ($(CONFIG_ARCH_SA1100),y)
 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
- textofs-$(CONFIG_SA1111)          := 0x00208000
+ifeq ($(CONFIG_ARCH_SA1100),y)
+textofs-$(CONFIG_SA1111) := 0x00208000
 endif
- machine-$(CONFIG_ARCH_PXA)        := pxa
- machine-$(CONFIG_ARCH_MMP)        := mmp
+# Machine directory name.  This list is sorted alphanumerically
-    plat-$(CONFIG_PLAT_PXA)        := pxa
+# by CONFIG_* macro name.
- machine-$(CONFIG_ARCH_L7200)      := l7200
+machine-$(CONFIG_ARCH_AAEC2000)         := aaec2000
- machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
+machine-$(CONFIG_ARCH_AT91)             := at91
- machine-$(CONFIG_ARCH_GEMINI)     := gemini
+machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
- textofs-$(CONFIG_ARCH_CLPS711X)   := 0x00028000
+machine-$(CONFIG_ARCH_DAVINCI)          := davinci
- machine-$(CONFIG_ARCH_CLPS711X)   := clps711x
+machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
- machine-$(CONFIG_ARCH_IOP32X)     := iop32x
+machine-$(CONFIG_ARCH_EP93XX)           := ep93xx
- machine-$(CONFIG_ARCH_IOP33X)     := iop33x
+machine-$(CONFIG_ARCH_GEMINI)           := gemini
- machine-$(CONFIG_ARCH_IOP13XX)    := iop13xx
+machine-$(CONFIG_ARCH_H720X)            := h720x
-    plat-$(CONFIG_PLAT_IOP)        := iop
+machine-$(CONFIG_ARCH_INTEGRATOR)       := integrator
- machine-$(CONFIG_ARCH_IXP4XX)     := ixp4xx
+machine-$(CONFIG_ARCH_IOP13XX)          := iop13xx
- machine-$(CONFIG_ARCH_IXP2000)    := ixp2000
+machine-$(CONFIG_ARCH_IOP32X)           := iop32x
- machine-$(CONFIG_ARCH_IXP23XX)    := ixp23xx
+machine-$(CONFIG_ARCH_IOP33X)           := iop33x
- machine-$(CONFIG_ARCH_OMAP1)      := omap1
+machine-$(CONFIG_ARCH_IXP2000)          := ixp2000
- machine-$(CONFIG_ARCH_OMAP2)      := omap2
+machine-$(CONFIG_ARCH_IXP23XX)          := ixp23xx
- machine-$(CONFIG_ARCH_OMAP3)      := omap2
+machine-$(CONFIG_ARCH_IXP4XX)           := ixp4xx
-    plat-$(CONFIG_ARCH_OMAP)       := omap
+machine-$(CONFIG_ARCH_KIRKWOOD)         := kirkwood
- machine-$(CONFIG_ARCH_S3C2410)    := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
+machine-$(CONFIG_ARCH_KS8695)           := ks8695
- machine-$(CONFIG_ARCH_S3C24A0)    := s3c24a0
+machine-$(CONFIG_ARCH_L7200)            := l7200
-    plat-$(CONFIG_PLAT_S3C24XX)    := s3c24xx s3c
+machine-$(CONFIG_ARCH_LH7A40X)          := lh7a40x
- machine-$(CONFIG_ARCH_S3C64XX)    := s3c6400 s3c6410
+machine-$(CONFIG_ARCH_LOKI)             := loki
-    plat-$(CONFIG_PLAT_S3C64XX)    := s3c64xx s3c
+machine-$(CONFIG_ARCH_MMP)              := mmp
- machine-$(CONFIG_ARCH_LH7A40X)    := lh7a40x
+machine-$(CONFIG_ARCH_MSM)              := msm
- machine-$(CONFIG_ARCH_VERSATILE)  := versatile
+machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
- machine-$(CONFIG_ARCH_IMX)        := imx
+machine-$(CONFIG_ARCH_MX1)              := mx1
- machine-$(CONFIG_ARCH_H720X)      := h720x
+machine-$(CONFIG_ARCH_MX2)              := mx2
- machine-$(CONFIG_ARCH_AAEC2000)   := aaec2000
+machine-$(CONFIG_ARCH_MX3)              := mx3
- machine-$(CONFIG_ARCH_REALVIEW)   := realview
+machine-$(CONFIG_ARCH_NETX)             := netx
- machine-$(CONFIG_ARCH_AT91)       := at91
+machine-$(CONFIG_ARCH_NS9XXX)           := ns9xxx
- machine-$(CONFIG_ARCH_EP93XX)     := ep93xx
+machine-$(CONFIG_ARCH_OMAP1)            := omap1
- machine-$(CONFIG_ARCH_PNX4008)    := pnx4008
+machine-$(CONFIG_ARCH_OMAP2)            := omap2
- machine-$(CONFIG_ARCH_NETX)       := netx
+machine-$(CONFIG_ARCH_OMAP3)            := omap2
- machine-$(CONFIG_ARCH_NS9XXX)     := ns9xxx
+machine-$(CONFIG_ARCH_OMAP4)            := omap2
- machine-$(CONFIG_ARCH_DAVINCI)    := davinci
+machine-$(CONFIG_ARCH_ORION5X)          := orion5x
- machine-$(CONFIG_ARCH_KIRKWOOD)   := kirkwood
+machine-$(CONFIG_ARCH_PNX4008)          := pnx4008
- machine-$(CONFIG_ARCH_KS8695)     := ks8695
+machine-$(CONFIG_ARCH_PXA)              := pxa
-    plat-$(CONFIG_ARCH_MXC)        := mxc
+machine-$(CONFIG_ARCH_REALVIEW)         := realview
- machine-$(CONFIG_ARCH_MX2)        := mx2
+machine-$(CONFIG_ARCH_RPC)              := rpc
- machine-$(CONFIG_ARCH_MX3)        := mx3
+machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
- machine-$(CONFIG_ARCH_MX1)        := mx1
+machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
- machine-$(CONFIG_ARCH_ORION5X)    := orion5x
+machine-$(CONFIG_ARCH_S3C64XX)          := s3c6400 s3c6410
-    plat-$(CONFIG_PLAT_ORION)      := orion
+machine-$(CONFIG_ARCH_SA1100)           := sa1100
- machine-$(CONFIG_ARCH_MSM)        := msm
+machine-$(CONFIG_ARCH_SHARK)            := shark
- machine-$(CONFIG_ARCH_LOKI)       := loki
+machine-$(CONFIG_ARCH_STMP378X)         := stmp378x
- machine-$(CONFIG_ARCH_MV78XX0)    := mv78xx0
+machine-$(CONFIG_ARCH_STMP37XX)         := stmp37xx
- machine-$(CONFIG_ARCH_W90X900)    := w90x900
+machine-$(CONFIG_ARCH_U300)             := u300
+machine-$(CONFIG_ARCH_VERSATILE)        := versatile
+machine-$(CONFIG_ARCH_W90X900)          := w90x900
+machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+# Platform directory name.  This list is sorted alphanumerically
+# by CONFIG_* macro name.
+plat-$(CONFIG_ARCH_MXC)         := mxc
+plat-$(CONFIG_ARCH_OMAP)        := omap
+plat-$(CONFIG_PLAT_IOP)         := iop
+plat-$(CONFIG_PLAT_ORION)       := orion
+plat-$(CONFIG_PLAT_PXA)         := pxa
+plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx s3c
+plat-$(CONFIG_PLAT_S3C64XX)     := s3c64xx s3c
+plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
 ifeq ($(CONFIG_ARCH_EBSA110),y)
 # This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index fbe5eef1f6c9..ce39dc540085 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -40,7 +40,7 @@ ifeq ($(CONFIG_PXA_SHARPSL),y)
 OBJS            += head-sharpsl.o
 endif
-ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
+ifeq ($(CONFIG_CPU_ENDIAN_BE32),y)
 ifeq ($(CONFIG_CPU_CP15),y)
 OBJS            += big-endian.o
 else
@@ -78,6 +78,9 @@ EXTRA_AFLAGS  := -Wa,-march=all
 # linker symbols.  We only define initrd_phys and params_phys if the
 # machine class defined the corresponding makefile variable.
 LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
+ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
+LDFLAGS_vmlinux += --be8
+endif
 ifneq ($(INITRD_PHYS),)
 LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
 endif
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b371fba1b954..01d49be3b2ca 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -438,6 +438,9 @@ __armv4_mmu_cache_on:
                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                orr     r0, r0, #0x0030
+#ifdef CONFIG_CPU_ENDIAN_BE8
+                orr     r0, r0, #1 << 25        @ big-endian page tables
+#endif
                bl      __common_mmu_cache_on
                mov     r0, #0
                mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
@@ -455,6 +458,9 @@ __armv7_mmu_cache_on:
                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                orr     r0, r0, #0x003c         @ write buffer
+#ifdef CONFIG_CPU_ENDIAN_BE8
+                orr     r0, r0, #1 << 25        @ big-endian page tables
+#endif
                orrne   r0, r0, #1              @ MMU enabled
                movne   r1, #-1
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index a2cd9beaf37d..4efbb9df0444 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -4,6 +4,14 @@ config ARM_GIC
 config ARM_VIC
        bool
+config ARM_VIC_NR
+        int
+        default 2
+        depends on ARM_VIC
+        help
+          The maximum number of VICs available in the system, for
+          power management.
 config ICST525
        bool
@@ -27,10 +35,6 @@ config SHARP_LOCOMO
 config SHARP_PARAM
        bool
-config SHARPSL_PM
-        bool
-        select APM_EMULATION
 config SHARP_SCOOP
        bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 7cb7961d81cb..76be7ff2a7ca 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_TIMER_ACORN)       += time-acorn.o
 obj-$(CONFIG_SHARP_LOCOMO)      += locomo.o
 obj-$(CONFIG_SHARP_PARAM)       += sharpsl_param.o
-obj-$(CONFIG_SHARPSL_PM)        += sharpsl_pm.o
 obj-$(CONFIG_SHARP_SCOOP)       += scoop.o
 obj-$(CONFIG_ARCH_IXP2000)      += uengine.o
 obj-$(CONFIG_ARCH_IXP23XX)      += uengine.o
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c
index 5589444ff437..f37afd9422f3 100644
--- a/arch/arm/common/clkdev.c
+++ b/arch/arm/common/clkdev.c
@@ -135,6 +135,24 @@ struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
 }
 EXPORT_SYMBOL(clkdev_alloc);
+int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
+        struct device *dev)
+{
+        struct clk *r = clk_get(dev, id);
+        struct clk_lookup *l;
+        if (IS_ERR(r))
+                return PTR_ERR(r);
+        l = clkdev_alloc(r, alias, alias_dev_name);
+        clk_put(r);
+        if (!l)
+                return -ENODEV;
+        clkdev_add(l);
+        return 0;
+}
+EXPORT_SYMBOL(clk_add_alias);
 /*
 * clkdev_drop - remove a clock dynamically allocated
 */
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c
deleted file mode 100644
index 140f1d721d50..000000000000
--- a/arch/arm/common/sharpsl_pm.c
+++ /dev/null
@@ -1,859 +0,0 @@
-/*
- * Battery and Power Management code for the Sharp SL-C7xx and SL-Cxx00
- * series of PDAs
- *
- * Copyright (c) 2004-2005 Richard Purdie
- *
- * Based on code written by Sharp for 2.4 kernels
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#undef DEBUG
-#include <linux/module.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/apm_bios.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <linux/apm-emulation.h>
-#include <linux/suspend.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/pm.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/regs-rtc.h>
-#include <mach/sharpsl.h>
-#include <asm/hardware/sharpsl_pm.h>
-/*
- * Constants
- */
-#define SHARPSL_CHARGE_ON_TIME_INTERVAL        (msecs_to_jiffies(1*60*1000))  /* 1 min */
-#define SHARPSL_CHARGE_FINISH_TIME             (msecs_to_jiffies(10*60*1000)) /* 10 min */
-#define SHARPSL_BATCHK_TIME                    (msecs_to_jiffies(15*1000))    /* 15 sec */
-#define SHARPSL_BATCHK_TIME_SUSPEND            (60*10)                        /* 10 min */
-#define SHARPSL_WAIT_CO_TIME                   15  /* 15 sec */
-#define SHARPSL_WAIT_DISCHARGE_ON              100 /* 100 msec */
-#define SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP   10  /* 10 msec */
-#define SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT   10  /* 10 msec */
-#define SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN   10  /* 10 msec */
-#define SHARPSL_CHARGE_WAIT_TIME               15  /* 15 msec */
-#define SHARPSL_CHARGE_CO_CHECK_TIME           5   /* 5 msec */
-#define SHARPSL_CHARGE_RETRY_CNT               1   /* eqv. 10 min */
-/*
- * Prototypes
- */
-#ifdef CONFIG_PM
-static int sharpsl_off_charge_battery(void);
-static int sharpsl_check_battery_voltage(void);
-static int sharpsl_fatal_check(void);
-#endif
-static int sharpsl_check_battery_temp(void);
-static int sharpsl_ac_check(void);
-static int sharpsl_average_value(int ad);
-static void sharpsl_average_clear(void);
-static void sharpsl_charge_toggle(struct work_struct *private_);
-static void sharpsl_battery_thread(struct work_struct *private_);
-/*
- * Variables
- */
-struct sharpsl_pm_status sharpsl_pm;
-DECLARE_DELAYED_WORK(toggle_charger, sharpsl_charge_toggle);
-DECLARE_DELAYED_WORK(sharpsl_bat, sharpsl_battery_thread);
-DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger);
-static int get_percentage(int voltage)
-{
-        int i = sharpsl_pm.machinfo->bat_levels - 1;
-        int bl_status = sharpsl_pm.machinfo->backlight_get_status ? sharpsl_pm.machinfo->backlight_get_status() : 0;
-        struct battery_thresh *thresh;
-        if (sharpsl_pm.charge_mode == CHRG_ON)
-                thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_acin_bl : sharpsl_pm.machinfo->bat_levels_acin;
-        else
-                thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_noac_bl : sharpsl_pm.machinfo->bat_levels_noac;
-        while (i > 0 && (voltage > thresh[i].voltage))
-                i--;
-        return thresh[i].percentage;
-}
-static int get_apm_status(int voltage)
-{
-        int low_thresh, high_thresh;
-        if (sharpsl_pm.charge_mode == CHRG_ON) {
-                high_thresh = sharpsl_pm.machinfo->status_high_acin;
-                low_thresh = sharpsl_pm.machinfo->status_low_acin;
-        } else {
-                high_thresh = sharpsl_pm.machinfo->status_high_noac;
-                low_thresh = sharpsl_pm.machinfo->status_low_noac;
-        }
-        if (voltage >= high_thresh)
-                return APM_BATTERY_STATUS_HIGH;
-        if (voltage >= low_thresh)
-                return APM_BATTERY_STATUS_LOW;
-        return APM_BATTERY_STATUS_CRITICAL;
-}
-void sharpsl_battery_kick(void)
-{
-        schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(125));
-}
-EXPORT_SYMBOL(sharpsl_battery_kick);
-static void sharpsl_battery_thread(struct work_struct *private_)
-{
-        int voltage, percent, apm_status, i = 0;
-        if (!sharpsl_pm.machinfo)
-                return;
-        sharpsl_pm.battstat.ac_status = (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN) ? APM_AC_ONLINE : APM_AC_OFFLINE);
-        /* Corgi cannot confirm when battery fully charged so periodically kick! */
-        if (!sharpsl_pm.machinfo->batfull_irq && (sharpsl_pm.charge_mode == CHRG_ON)
-                        && time_after(jiffies, sharpsl_pm.charge_start_time +  SHARPSL_CHARGE_ON_TIME_INTERVAL))
-                schedule_delayed_work(&toggle_charger, 0);
-        while(1) {
-                voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
-                if (voltage > 0) break;
-                if (i++ > 5) {
-                        voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage;
-                        dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n");
-                        break;
-                }
-        }
-        voltage = sharpsl_average_value(voltage);
-        apm_status = get_apm_status(voltage);
-        percent = get_percentage(voltage);
-        /* At low battery voltages, the voltage has a tendency to start
-           creeping back up so we try to avoid this here */
-        if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE) || (apm_status == APM_BATTERY_STATUS_HIGH) ||  percent <= sharpsl_pm.battstat.mainbat_percent) {
-                sharpsl_pm.battstat.mainbat_voltage = voltage;
-                sharpsl_pm.battstat.mainbat_status = apm_status;
-                sharpsl_pm.battstat.mainbat_percent = percent;
-        }
-        dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
-                        sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
-#ifdef CONFIG_BACKLIGHT_CORGI
-        /* If battery is low. limit backlight intensity to save power. */
-        if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
-                        && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
-                        (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) {
-                if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) {
-                        sharpsl_pm.machinfo->backlight_limit(1);
-                        sharpsl_pm.flags |= SHARPSL_BL_LIMIT;
-                }
-        } else if (sharpsl_pm.flags & SHARPSL_BL_LIMIT) {
-                sharpsl_pm.machinfo->backlight_limit(0);
-                sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
-        }
-#endif
-        /* Suspend if critical battery level */
-        if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
-                        && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
-                        && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) {
-                sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
-                dev_err(sharpsl_pm.dev, "Fatal Off\n");
-                apm_queue_event(APM_CRITICAL_SUSPEND);
-        }
-        schedule_delayed_work(&sharpsl_bat, SHARPSL_BATCHK_TIME);
-}
-void sharpsl_pm_led(int val)
-{
-        if (val == SHARPSL_LED_ERROR) {
-                dev_err(sharpsl_pm.dev, "Charging Error!\n");
-        } else if (val == SHARPSL_LED_ON) {
-                dev_dbg(sharpsl_pm.dev, "Charge LED On\n");
-                led_trigger_event(sharpsl_charge_led_trigger, LED_FULL);
-        } else {
-                dev_dbg(sharpsl_pm.dev, "Charge LED Off\n");
-                led_trigger_event(sharpsl_charge_led_trigger, LED_OFF);
-        }
-}
-static void sharpsl_charge_on(void)
-{
-        dev_dbg(sharpsl_pm.dev, "Turning Charger On\n");
-        sharpsl_pm.full_count = 0;
-        sharpsl_pm.charge_mode = CHRG_ON;
-        schedule_delayed_work(&toggle_charger, msecs_to_jiffies(250));
-        schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(500));
-}
-static void sharpsl_charge_off(void)
-{
-        dev_dbg(sharpsl_pm.dev, "Turning Charger Off\n");
-        sharpsl_pm.machinfo->charge(0);
-        sharpsl_pm_led(SHARPSL_LED_OFF);
-        sharpsl_pm.charge_mode = CHRG_OFF;
-        schedule_delayed_work(&sharpsl_bat, 0);
-}
-static void sharpsl_charge_error(void)
-{
-        sharpsl_pm_led(SHARPSL_LED_ERROR);
-        sharpsl_pm.machinfo->charge(0);
-        sharpsl_pm.charge_mode = CHRG_ERROR;
-}
-static void sharpsl_charge_toggle(struct work_struct *private_)
-{
-        dev_dbg(sharpsl_pm.dev, "Toogling Charger at time: %lx\n", jiffies);
-        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
-                sharpsl_charge_off();
-                return;
-        } else if ((sharpsl_check_battery_temp() < 0) || (sharpsl_ac_check() < 0)) {
-                sharpsl_charge_error();
-                return;
-        }
-        sharpsl_pm_led(SHARPSL_LED_ON);
-        sharpsl_pm.machinfo->charge(0);
-        mdelay(SHARPSL_CHARGE_WAIT_TIME);
-        sharpsl_pm.machinfo->charge(1);
-        sharpsl_pm.charge_start_time = jiffies;
-}
-static void sharpsl_ac_timer(unsigned long data)
-{
-        int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-        dev_dbg(sharpsl_pm.dev, "AC Status: %d\n",acin);
-        sharpsl_average_clear();
-        if (acin && (sharpsl_pm.charge_mode != CHRG_ON))
-                sharpsl_charge_on();
-        else if (sharpsl_pm.charge_mode == CHRG_ON)
-                sharpsl_charge_off();
-        schedule_delayed_work(&sharpsl_bat, 0);
-}
-irqreturn_t sharpsl_ac_isr(int irq, void *dev_id)
-{
-        /* Delay the event slightly to debounce */
-        /* Must be a smaller delay than the chrg_full_isr below */
-        mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
-        return IRQ_HANDLED;
-}
-static void sharpsl_chrg_full_timer(unsigned long data)
-{
-        dev_dbg(sharpsl_pm.dev, "Charge Full at time: %lx\n", jiffies);
-        sharpsl_pm.full_count++;
-        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
-                dev_dbg(sharpsl_pm.dev, "Charge Full: AC removed - stop charging!\n");
-                if (sharpsl_pm.charge_mode == CHRG_ON)
-                        sharpsl_charge_off();
-        } else if (sharpsl_pm.full_count < 2) {
-                dev_dbg(sharpsl_pm.dev, "Charge Full: Count too low\n");
-                schedule_delayed_work(&toggle_charger, 0);
-        } else if (time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_FINISH_TIME)) {
-                dev_dbg(sharpsl_pm.dev, "Charge Full: Interrupt generated too slowly - retry.\n");
-                schedule_delayed_work(&toggle_charger, 0);
-        } else {
-                sharpsl_charge_off();
-                sharpsl_pm.charge_mode = CHRG_DONE;
-                dev_dbg(sharpsl_pm.dev, "Charge Full: Charging Finished\n");
-        }
-}
-/* Charging Finished Interrupt (Not present on Corgi) */
-/* Can trigger at the same time as an AC status change so
-   delay until after that has been processed */
-irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
-{
-        if (sharpsl_pm.flags & SHARPSL_SUSPENDED)
-                return IRQ_HANDLED;
-        /* delay until after any ac interrupt */
-        mod_timer(&sharpsl_pm.chrg_full_timer, jiffies + msecs_to_jiffies(500));
-        return IRQ_HANDLED;
-}
-irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id)
-{
-        int is_fatal = 0;
-        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) {
-                dev_err(sharpsl_pm.dev, "Battery now Unlocked! Suspending.\n");
-                is_fatal = 1;
-        }
-        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL)) {
-                dev_err(sharpsl_pm.dev, "Fatal Batt Error! Suspending.\n");
-                is_fatal = 1;
-        }
-        if (!(sharpsl_pm.flags & SHARPSL_APM_QUEUED) && is_fatal) {
-                sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
-                apm_queue_event(APM_CRITICAL_SUSPEND);
-        }
-        return IRQ_HANDLED;
-}
-/*
- * Maintain an average of the last 10 readings
- */
-#define SHARPSL_CNV_VALUE_NUM    10
-static int sharpsl_ad_index;
-static void sharpsl_average_clear(void)
-{
-        sharpsl_ad_index = 0;
-}
-static int sharpsl_average_value(int ad)
-{
-        int i, ad_val = 0;
-        static int sharpsl_ad[SHARPSL_CNV_VALUE_NUM+1];
-        if (sharpsl_pm.battstat.mainbat_status != APM_BATTERY_STATUS_HIGH) {
-                sharpsl_ad_index = 0;
-                return ad;
-        }
-        sharpsl_ad[sharpsl_ad_index] = ad;
-        sharpsl_ad_index++;
-        if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) {
-                for (i=0; i < (SHARPSL_CNV_VALUE_NUM-1); i++)
-                        sharpsl_ad[i] = sharpsl_ad[i+1];
-                sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1;
-        }
-        for (i=0; i < sharpsl_ad_index; i++)
-                ad_val += sharpsl_ad[i];
-        return (ad_val / sharpsl_ad_index);
-}
-/*
- * Take an array of 5 integers, remove the maximum and minimum values
- * and return the average.
- */
-static int get_select_val(int *val)
-{
-        int i, j, k, temp, sum = 0;
-        /* Find MAX val */
-        temp = val[0];
-        j=0;
-        for (i=1; i<5; i++) {
-                if (temp < val[i]) {
-                        temp = val[i];
-                        j = i;
-                }
-        }
-        /* Find MIN val */
-        temp = val[4];
-        k=4;
-        for (i=3; i>=0; i--) {
-                if (temp > val[i]) {
-                        temp = val[i];
-                        k = i;
-                }
-        }
-        for (i=0; i<5; i++)
-                if (i != j && i != k )
-                        sum += val[i];
-        dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]);
-        return (sum/3);
-}
-static int sharpsl_check_battery_temp(void)
-{
-        int val, i, buff[5];
-        /* Check battery temperature */
-        for (i=0; i<5; i++) {
-                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
-                sharpsl_pm.machinfo->measure_temp(1);
-                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
-                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_TEMP);
-                sharpsl_pm.machinfo->measure_temp(0);
-        }
-        val = get_select_val(buff);
-        dev_dbg(sharpsl_pm.dev, "Temperature: %d\n", val);
-        if (val > sharpsl_pm.machinfo->charge_on_temp) {
-                printk(KERN_WARNING "Not charging: temperature out of limits.\n");
-                return -1;
-        }
-        return 0;
-}
-#ifdef CONFIG_PM
-static int sharpsl_check_battery_voltage(void)
-{
-        int val, i, buff[5];
-        /* disable charge, enable discharge */
-        sharpsl_pm.machinfo->charge(0);
-        sharpsl_pm.machinfo->discharge(1);
-        mdelay(SHARPSL_WAIT_DISCHARGE_ON);
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(1);
-        /* Check battery voltage */
-        for (i=0; i<5; i++) {
-                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
-                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
-        }
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(0);
-        sharpsl_pm.machinfo->discharge(0);
-        val = get_select_val(buff);
-        dev_dbg(sharpsl_pm.dev, "Battery Voltage: %d\n", val);
-        if (val < sharpsl_pm.machinfo->charge_on_volt)
-                return -1;
-        return 0;
-}
-#endif
-static int sharpsl_ac_check(void)
-{
-        int temp, i, buff[5];
-        for (i=0; i<5; i++) {
-                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT);
-                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN);
-        }
-        temp = get_select_val(buff);
-        dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n",temp);
-        if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) {
-                dev_err(sharpsl_pm.dev, "Error: AC check failed.\n");
-                return -1;
-        }
-        return 0;
-}
-#ifdef CONFIG_PM
-static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state)
-{
-        sharpsl_pm.flags |= SHARPSL_SUSPENDED;
-        flush_scheduled_work();
-        if (sharpsl_pm.charge_mode == CHRG_ON)
-                sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
-        else
-                sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
-        return 0;
-}
-static int sharpsl_pm_resume(struct platform_device *pdev)
-{
-        /* Clear the reset source indicators as they break the bootloader upon reboot */
-        RCSR = 0x0f;
-        sharpsl_average_clear();
-        sharpsl_pm.flags &= ~SHARPSL_APM_QUEUED;
-        sharpsl_pm.flags &= ~SHARPSL_SUSPENDED;
-        return 0;
-}
-static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
-{
-        dev_dbg(sharpsl_pm.dev, "Time is: %08x\n",RCNR);
-        dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n",sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG);
-        /* not charging and AC-IN! */
-        if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) {
-                dev_dbg(sharpsl_pm.dev, "Activating Offline Charger...\n");
-                sharpsl_pm.charge_mode = CHRG_OFF;
-                sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
-                sharpsl_off_charge_battery();
-        }
-        sharpsl_pm.machinfo->presuspend();
-        PEDR = 0xffffffff; /* clear it */
-        sharpsl_pm.flags &= ~SHARPSL_ALARM_ACTIVE;
-        if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) {
-                RTSR &= RTSR_ALE;
-                RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND;
-                dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n",RTAR);
-                sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE;
-        } else if (alarm_enable) {
-                RTSR &= RTSR_ALE;
-                RTAR = alarm_time;
-                dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n",RTAR);
-        } else {
-                dev_dbg(sharpsl_pm.dev, "No alarms set.\n");
-        }
-        pxa_pm_enter(state);
-        sharpsl_pm.machinfo->postsuspend();
-        dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n",PEDR);
-}
-static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
-{
-        if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable) )
-        {
-                if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) {
-                        dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n");
-                        corgi_goto_sleep(alarm_time, alarm_enable, state);
-                        return 1;
-                }
-                if(sharpsl_off_charge_battery()) {
-                        dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n");
-                        corgi_goto_sleep(alarm_time, alarm_enable, state);
-                        return 1;
-                }
-                dev_dbg(sharpsl_pm.dev, "User triggered wakeup in offline charger.\n");
-        }
-        if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) || (sharpsl_fatal_check() < 0) )
-        {
-                dev_err(sharpsl_pm.dev, "Fatal condition. Suspend.\n");
-                corgi_goto_sleep(alarm_time, alarm_enable, state);
-                return 1;
-        }
-        return 0;
-}
-static int corgi_pxa_pm_enter(suspend_state_t state)
-{
-        unsigned long alarm_time = RTAR;
-        unsigned int alarm_status = ((RTSR & RTSR_ALE) != 0);
-        dev_dbg(sharpsl_pm.dev, "SharpSL suspending for first time.\n");
-        corgi_goto_sleep(alarm_time, alarm_status, state);
-        while (corgi_enter_suspend(alarm_time,alarm_status,state))
-                {}
-        if (sharpsl_pm.machinfo->earlyresume)
-                sharpsl_pm.machinfo->earlyresume();
-        dev_dbg(sharpsl_pm.dev, "SharpSL resuming...\n");
-        return 0;
-}
-/*
- * Check for fatal battery errors
- * Fatal returns -1
- */
-static int sharpsl_fatal_check(void)
-{
-        int buff[5], temp, i, acin;
-        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check entered\n");
-        /* Check AC-Adapter */
-        acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
-        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
-                sharpsl_pm.machinfo->charge(0);
-                udelay(100);
-                sharpsl_pm.machinfo->discharge(1);      /* enable discharge */
-                mdelay(SHARPSL_WAIT_DISCHARGE_ON);
-        }
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(1);
-        /* Check battery : check inserting battery ? */
-        for (i=0; i<5; i++) {
-                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
-                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
-        }
-        if (sharpsl_pm.machinfo->discharge1)
-                sharpsl_pm.machinfo->discharge1(0);
-        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
-                udelay(100);
-                sharpsl_pm.machinfo->charge(1);
-                sharpsl_pm.machinfo->discharge(0);
-        }
-        temp = get_select_val(buff);
-        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT));
-        if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) ||
-                        (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt)))
-                return -1;
-        return 0;
-}
-static int sharpsl_off_charge_error(void)
-{
-        dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
-        sharpsl_pm.machinfo->charge(0);
-        sharpsl_pm_led(SHARPSL_LED_ERROR);
-        sharpsl_pm.charge_mode = CHRG_ERROR;
-        return 1;
-}
-/*
- * Charging Control while suspended
- * Return 1 - go straight to sleep
- * Return 0 - sleep or wakeup depending on other factors
- */
-static int sharpsl_off_charge_battery(void)
-{
-        int time;
-        dev_dbg(sharpsl_pm.dev, "Charge Mode: %d\n", sharpsl_pm.charge_mode);
-        if (sharpsl_pm.charge_mode == CHRG_OFF) {
-                dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 1\n");
-                /* AC Check */
-                if ((sharpsl_ac_check() < 0) || (sharpsl_check_battery_temp() < 0))
-                        return sharpsl_off_charge_error();
-                /* Start Charging */
-                sharpsl_pm_led(SHARPSL_LED_ON);
-                sharpsl_pm.machinfo->charge(0);
-                mdelay(SHARPSL_CHARGE_WAIT_TIME);
-                sharpsl_pm.machinfo->charge(1);
-                sharpsl_pm.charge_mode = CHRG_ON;
-                sharpsl_pm.full_count = 0;
-                return 1;
-        } else if (sharpsl_pm.charge_mode != CHRG_ON) {
-                return 1;
-        }
-        if (sharpsl_pm.full_count == 0) {
-                int time;
-                dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 2\n");
-                if ((sharpsl_check_battery_temp() < 0) || (sharpsl_check_battery_voltage() < 0))
-                        return sharpsl_off_charge_error();
-                sharpsl_pm.machinfo->charge(0);
-                mdelay(SHARPSL_CHARGE_WAIT_TIME);
-                sharpsl_pm.machinfo->charge(1);
-                sharpsl_pm.charge_mode = CHRG_ON;
-                mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
-                time = RCNR;
-                while(1) {
-                        /* Check if any wakeup event had occurred */
-                        if (sharpsl_pm.machinfo->charger_wakeup() != 0)
-                                return 0;
-                        /* Check for timeout */
-                        if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
-                                return 1;
-                        if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
-                                dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
-                                sharpsl_pm.full_count++;
-                                sharpsl_pm.machinfo->charge(0);
-                                mdelay(SHARPSL_CHARGE_WAIT_TIME);
-                                sharpsl_pm.machinfo->charge(1);
-                                return 1;
-                        }
-                }
-        }
-        dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 3\n");
-        mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
-        time = RCNR;
-        while(1) {
-                /* Check if any wakeup event had occurred */
-                if (sharpsl_pm.machinfo->charger_wakeup() != 0)
-                        return 0;
-                /* Check for timeout */
-                if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) {
-                        if (sharpsl_pm.full_count > SHARPSL_CHARGE_RETRY_CNT) {
-                                dev_dbg(sharpsl_pm.dev, "Offline Charger: Not charged sufficiently. Retrying.\n");
-                                sharpsl_pm.full_count = 0;
-                        }
-                        sharpsl_pm.full_count++;
-                        return 1;
-                }
-                if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
-                        dev_dbg(sharpsl_pm.dev, "Offline Charger: Charging complete.\n");
-                        sharpsl_pm_led(SHARPSL_LED_OFF);
-                        sharpsl_pm.machinfo->charge(0);
-                        sharpsl_pm.charge_mode = CHRG_DONE;
-                        return 1;
-                }
-        }
-}
-#else
-#define sharpsl_pm_suspend      NULL
-#define sharpsl_pm_resume       NULL
-#endif
-static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
-        return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_percent);
-}
-static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf)
-{
-        return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_voltage);
-}
-static DEVICE_ATTR(battery_percentage, 0444, battery_percentage_show, NULL);
-static DEVICE_ATTR(battery_voltage, 0444, battery_voltage_show, NULL);
-extern void (*apm_get_power_status)(struct apm_power_info *);
-static void sharpsl_apm_get_power_status(struct apm_power_info *info)
-{
-        info->ac_line_status = sharpsl_pm.battstat.ac_status;
-        if (sharpsl_pm.charge_mode == CHRG_ON)
-                info->battery_status = APM_BATTERY_STATUS_CHARGING;
-        else
-                info->battery_status = sharpsl_pm.battstat.mainbat_status;
-        info->battery_flag = (1 << info->battery_status);
-        info->battery_life = sharpsl_pm.battstat.mainbat_percent;
-}
-#ifdef CONFIG_PM
-static struct platform_suspend_ops sharpsl_pm_ops = {
-        .enter          = corgi_pxa_pm_enter,
-        .valid          = suspend_valid_only_mem,
-};
-#endif
-static int __init sharpsl_pm_probe(struct platform_device *pdev)
-{
-        int ret;
-        if (!pdev->dev.platform_data)
-                return -EINVAL;
-        sharpsl_pm.dev = &pdev->dev;
-        sharpsl_pm.machinfo = pdev->dev.platform_data;
-        sharpsl_pm.charge_mode = CHRG_OFF;
-        sharpsl_pm.flags = 0;
-        init_timer(&sharpsl_pm.ac_timer);
-        sharpsl_pm.ac_timer.function = sharpsl_ac_timer;
-        init_timer(&sharpsl_pm.chrg_full_timer);
-        sharpsl_pm.chrg_full_timer.function = sharpsl_chrg_full_timer;
-        led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger);
-        sharpsl_pm.machinfo->init();
-        ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage);
-        ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage);
-        if (ret != 0)
-                dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret);
-        apm_get_power_status = sharpsl_apm_get_power_status;
-#ifdef CONFIG_PM
-        suspend_set_ops(&sharpsl_pm_ops);
-#endif
-        mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
-        return 0;
-}
-static int sharpsl_pm_remove(struct platform_device *pdev)
-{
-        suspend_set_ops(NULL);
-        device_remove_file(&pdev->dev, &dev_attr_battery_percentage);
-        device_remove_file(&pdev->dev, &dev_attr_battery_voltage);
-        led_trigger_unregister_simple(sharpsl_charge_led_trigger);
-        sharpsl_pm.machinfo->exit();
-        del_timer_sync(&sharpsl_pm.chrg_full_timer);
-        del_timer_sync(&sharpsl_pm.ac_timer);
-        return 0;
-}
-static struct platform_driver sharpsl_pm_driver = {
-        .probe          = sharpsl_pm_probe,
-        .remove         = sharpsl_pm_remove,
-        .suspend        = sharpsl_pm_suspend,
-        .resume         = sharpsl_pm_resume,
-        .driver         = {
-                .name           = "sharpsl-pm",
-        },
-};
-static int __devinit sharpsl_pm_init(void)
-{
-        return platform_driver_register(&sharpsl_pm_driver);
-}
-static void sharpsl_pm_exit(void)
-{
-        platform_driver_unregister(&sharpsl_pm_driver);
-}
-late_initcall(sharpsl_pm_init);
-module_exit(sharpsl_pm_exit);
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index b2a781d9ce05..887c6eb3a18a 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/sysdev.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
@@ -39,11 +40,219 @@ static void vic_unmask_irq(unsigned int irq)
        writel(1 << irq, base + VIC_INT_ENABLE);
 }
+/**
+ * vic_init2 - common initialisation code
+ * @base: Base of the VIC.
+ *
+ * Common initialisation code for registeration
+ * and resume.
+*/
+static void vic_init2(void __iomem *base)
+{
+        int i;
+        for (i = 0; i < 16; i++) {
+                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                writel(VIC_VECT_CNTL_ENABLE | i, reg);
+        }
+        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+}
+#if defined(CONFIG_PM)
+/**
+ * struct vic_device - VIC PM device
+ * @sysdev: The system device which is registered.
+ * @irq: The IRQ number for the base of the VIC.
+ * @base: The register base for the VIC.
+ * @resume_sources: A bitmask of interrupts for resume.
+ * @resume_irqs: The IRQs enabled for resume.
+ * @int_select: Save for VIC_INT_SELECT.
+ * @int_enable: Save for VIC_INT_ENABLE.
+ * @soft_int: Save for VIC_INT_SOFT.
+ * @protect: Save for VIC_PROTECT.
+ */
+struct vic_device {
+        struct sys_device sysdev;
+        void __iomem    *base;
+        int             irq;
+        u32             resume_sources;
+        u32             resume_irqs;
+        u32             int_select;
+        u32             int_enable;
+        u32             soft_int;
+        u32             protect;
+};
+/* we cannot allocate memory when VICs are initially registered */
+static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
+static inline struct vic_device *to_vic(struct sys_device *sys)
+{
+        return container_of(sys, struct vic_device, sysdev);
+}
+static int vic_id;
+static int vic_class_resume(struct sys_device *dev)
+{
+        struct vic_device *vic = to_vic(dev);
+        void __iomem *base = vic->base;
+        printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
+        /* re-initialise static settings */
+        vic_init2(base);
+        writel(vic->int_select, base + VIC_INT_SELECT);
+        writel(vic->protect, base + VIC_PROTECT);
+        /* set the enabled ints and then clear the non-enabled */
+        writel(vic->int_enable, base + VIC_INT_ENABLE);
+        writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
+        /* and the same for the soft-int register */
+        writel(vic->soft_int, base + VIC_INT_SOFT);
+        writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
+        return 0;
+}
+static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
+{
+        struct vic_device *vic = to_vic(dev);
+        void __iomem *base = vic->base;
+        printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
+        vic->int_select = readl(base + VIC_INT_SELECT);
+        vic->int_enable = readl(base + VIC_INT_ENABLE);
+        vic->soft_int = readl(base + VIC_INT_SOFT);
+        vic->protect = readl(base + VIC_PROTECT);
+        /* set the interrupts (if any) that are used for
+         * resuming the system */
+        writel(vic->resume_irqs, base + VIC_INT_ENABLE);
+        writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
+        return 0;
+}
+struct sysdev_class vic_class = {
+        .name           = "vic",
+        .suspend        = vic_class_suspend,
+        .resume         = vic_class_resume,
+};
+/**
+ * vic_pm_register - Register a VIC for later power management control
+ * @base: The base address of the VIC.
+ * @irq: The base IRQ for the VIC.
+ * @resume_sources: bitmask of interrupts allowed for resume sources.
+ *
+ * Register the VIC with the system device tree so that it can be notified
+ * of suspend and resume requests and ensure that the correct actions are
+ * taken to re-instate the settings on resume.
+ */
+static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+{
+        struct vic_device *v;
+        if (vic_id >= ARRAY_SIZE(vic_devices))
+                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
+        else {
+                v = &vic_devices[vic_id];
+                v->base = base;
+                v->resume_sources = resume_sources;
+                v->irq = irq;
+                vic_id++;
+        }
+}
+/**
+ * vic_pm_init - initicall to register VIC pm
+ *
+ * This is called via late_initcall() to register
+ * the resources for the VICs due to the early
+ * nature of the VIC's registration.
+*/
+static int __init vic_pm_init(void)
+{
+        struct vic_device *dev = vic_devices;
+        int err;
+        int id;
+        if (vic_id == 0)
+                return 0;
+        err = sysdev_class_register(&vic_class);
+        if (err) {
+                printk(KERN_ERR "%s: cannot register class\n", __func__);
+                return err;
+        }
+        for (id = 0; id < vic_id; id++, dev++) {
+                dev->sysdev.id = id;
+                dev->sysdev.cls = &vic_class;
+                err = sysdev_register(&dev->sysdev);
+                if (err) {
+                        printk(KERN_ERR "%s: failed to register device\n",
+                               __func__);
+                        return err;
+                }
+        }
+        return 0;
+}
+late_initcall(vic_pm_init);
+static struct vic_device *vic_from_irq(unsigned int irq)
+{
+        struct vic_device *v = vic_devices;
+        unsigned int base_irq = irq & ~31;
+        int id;
+        for (id = 0; id < vic_id; id++, v++) {
+                if (v->irq == base_irq)
+                        return v;
+        }
+        return NULL;
+}
+static int vic_set_wake(unsigned int irq, unsigned int on)
+{
+        struct vic_device *v = vic_from_irq(irq);
+        unsigned int off = irq & 31;
+        if (!v)
+                return -EINVAL;
+        if (on)
+                v->resume_irqs |= 1 << off;
+        else
+                v->resume_irqs &= ~(1 << off);
+        return 0;
+}
+#else
+static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
+#define vic_set_wake NULL
+#endif /* CONFIG_PM */
 static struct irq_chip vic_chip = {
        .name   = "VIC",
        .ack    = vic_mask_irq,
        .mask   = vic_mask_irq,
        .unmask = vic_unmask_irq,
+        .set_wake = vic_set_wake,
 };
 /**
@@ -51,9 +260,10 @@ static struct irq_chip vic_chip = {
 * @base: iomem base address
 * @irq_start: starting interrupt number, must be muliple of 32
 * @vic_sources: bitmask of interrupt sources to allow
+ * @resume_sources: bitmask of interrupt sources to allow for resume
 */
 void __init vic_init(void __iomem *base, unsigned int irq_start,
-                     u32 vic_sources)
+                     u32 vic_sources, u32 resume_sources)
 {
        unsigned int i;
@@ -77,12 +287,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
                writel(value, base + VIC_PL190_VECT_ADDR);
        }
-        for (i = 0; i < 16; i++) {
+        vic_init2(base);
-                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                writel(VIC_VECT_CNTL_ENABLE | i, reg);
-        }
-        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
        for (i = 0; i < 32; i++) {
                if (vic_sources & (1 << i)) {
@@ -94,4 +299,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                }
        }
+        vic_pm_register(base, irq_start, resume_sources);
 }
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
index 227da0843ead..d18d21bb41e4 100644
--- a/arch/arm/configs/cm_x300_defconfig
+++ b/arch/arm/configs/cm_x300_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc3
+# Linux kernel version: 2.6.30-rc8
-# Tue Aug 19 11:26:54 2008
+# Thu Jun  4 09:53:21 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
@@ -44,15 +42,24 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=18
-# CONFIG_CGROUPS is not set
 CONFIG_GROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
 # CONFIG_RT_GROUP_SCHED is not set
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -61,31 +68,37 @@ CONFIG_NAMESPACES=y
 # CONFIG_IPC_NS is not set
 # CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
@@ -93,19 +106,13 @@ CONFIG_SLUB=y
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
@@ -113,11 +120,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -133,7 +137,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 #
 # System Type
@@ -143,10 +147,10 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
@@ -167,14 +171,17 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_MMP is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
 #
 # Intel PXA2xx/PXA3xx Implementations
@@ -187,16 +194,24 @@ CONFIG_CPU_PXA300=y
 # CONFIG_CPU_PXA310 is not set
 # CONFIG_CPU_PXA320 is not set
 # CONFIG_CPU_PXA930 is not set
+# CONFIG_CPU_PXA935 is not set
 # CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_VIPER is not set
 # CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_H5000 is not set
 # CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_EXEDA is not set
 # CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_COLIBRI300 is not set
+# CONFIG_MACH_COLIBRI320 is not set
 # CONFIG_MACH_ZYLONITE is not set
 # CONFIG_MACH_LITTLETON is not set
 # CONFIG_MACH_TAVOREVB is not set
@@ -204,19 +219,15 @@ CONFIG_CPU_PXA300=y
 # CONFIG_MACH_ARMCORE is not set
 CONFIG_MACH_CM_X300=y
 # CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_HIMALAYA is not set
+# CONFIG_MACH_MIOA701 is not set
 # CONFIG_MACH_PCM027 is not set
 # CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_MACH_CSB726 is not set
 # CONFIG_PXA_EZX is not set
 CONFIG_PXA3xx=y
 # CONFIG_PXA_PWM is not set
+CONFIG_PLAT_PXA=y
-#
-# Boot options
-#
-#
-# Power management
-#
 #
 # Processor Type
@@ -241,6 +252,7 @@ CONFIG_IO_36=y
 CONFIG_OUTER_CACHE=y
 CONFIG_CACHE_XSC3L2=y
 CONFIG_IWMMXT=y
+CONFIG_COMMON_CLKDEV=y
 #
 # Bus support
@@ -256,25 +268,33 @@ CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HIGHMEM=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_ZONE_DMA_FLAG=0
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 CONFIG_ALIGNMENT_TRAP=y
 #
@@ -287,7 +307,7 @@ CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=jffs2 console=ttyS2,38400"
 # CONFIG_KEXEC is not set
 #
-# CPU Frequency scaling
+# CPU Power Management
 #
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_TABLE=y
@@ -304,6 +324,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
 # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_IDLE is not set
 #
 # Floating point emulation
@@ -320,6 +341,8 @@ CONFIG_FPE_NWFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
@@ -376,6 +399,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -385,7 +409,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 #
 # Network testing
@@ -407,8 +433,7 @@ CONFIG_BT_HIDP=m
 #
 # Bluetooth device drivers
 #
-CONFIG_BT_HCIUSB=m
+# CONFIG_BT_HCIBTUSB is not set
-CONFIG_BT_HCIUSB_SCO=y
 # CONFIG_BT_HCIBTSDIO is not set
 # CONFIG_BT_HCIUART is not set
 # CONFIG_BT_HCIBCM203X is not set
@@ -416,19 +441,15 @@ CONFIG_BT_HCIUSB_SCO=y
 # CONFIG_BT_HCIBFUSB is not set
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
-#
-# Wireless
-#
 # CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
 CONFIG_WIRELESS_EXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
 # CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
+# CONFIG_WIMAX is not set
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_CRYPT_TKIP=m
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -453,6 +474,7 @@ CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
 # CONFIG_MTD_AFS_PARTS is not set
@@ -494,7 +516,6 @@ CONFIG_MTD_CFI_I2=y
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_SHARP_SL is not set
 # CONFIG_MTD_PLATRAM is not set
 #
@@ -516,16 +537,23 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 # CONFIG_MTD_NAND_H1900 is not set
+# CONFIG_MTD_NAND_GPIO is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_SHARPSL is not set
 CONFIG_MTD_NAND_PXA3xx=y
+# CONFIG_MTD_NAND_PXA3xx_BUILTIN is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 #
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
 # UBI - Unsorted block images
 #
 # CONFIG_MTD_UBI is not set
@@ -585,11 +613,15 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_SRP_ATTRS is not set
 CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -604,11 +636,17 @@ CONFIG_MII=y
 CONFIG_DM9000=y
 CONFIG_DM9000_DEBUGLEVEL=0
 CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
+# CONFIG_ETHOC is not set
 # CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -624,10 +662,13 @@ CONFIG_LIBERTAS_SDIO=m
 # CONFIG_LIBERTAS_DEBUG is not set
 # CONFIG_USB_ZD1201 is not set
 # CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_HOSTAP is not set
 #
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
 # USB Network Adapters
 #
 # CONFIG_USB_CATC is not set
@@ -677,18 +718,21 @@ CONFIG_KEYBOARD_PXA27x=m
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
 # CONFIG_INPUT_MISC is not set
 #
@@ -721,10 +765,10 @@ CONFIG_SERIAL_PXA_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
@@ -763,12 +807,8 @@ CONFIG_I2C_PXA=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
@@ -782,6 +822,10 @@ CONFIG_GPIOLIB=y
 # CONFIG_GPIO_SYSFS is not set
 #
+# Memory mapped GPIO expanders:
+#
+#
 # I2C GPIO expanders:
 #
 # CONFIG_GPIO_MAX732X is not set
@@ -798,12 +842,14 @@ CONFIG_GPIO_PCA953X=y
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 #
@@ -811,12 +857,19 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 #
 # Multimedia devices
@@ -842,6 +895,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -862,12 +916,15 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 #
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_OVERLAY is not set
 # CONFIG_FB_PXA_SMARTPANEL is not set
 # CONFIG_FB_PXA_PARAMETERS is not set
 # CONFIG_FB_MBX is not set
 # CONFIG_FB_W100 is not set
-# CONFIG_FB_AM200EPD is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 #
@@ -899,9 +956,11 @@ CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE is not set
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
+CONFIG_SND_JACK=y
 # CONFIG_SND_SEQUENCER is not set
 # CONFIG_SND_MIXER_OSS is not set
 # CONFIG_SND_PCM_OSS is not set
@@ -916,12 +975,15 @@ CONFIG_SND_DRIVERS=y
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
 CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_LIB=m
 # CONFIG_SND_PXA2XX_AC97 is not set
 CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
 CONFIG_SND_SOC=m
 CONFIG_SND_PXA2XX_SOC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
@@ -932,9 +994,39 @@ CONFIG_HID_DEBUG=y
 # USB Input Devices
 #
 CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_PID is not set
-# CONFIG_HID_FF is not set
 # CONFIG_USB_HIDDEV is not set
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+# CONFIG_DRAGONRISE_FF is not set
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KYE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+CONFIG_HID_TOPSEED=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -952,11 +1044,14 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_SUSPEND is not set
 # CONFIG_USB_OTG is not set
 CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 #
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
@@ -965,6 +1060,7 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 # CONFIG_USB_MUSB_HDRC is not set
 #
@@ -973,20 +1069,20 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
 # CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 #
-# may also be needed; see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
 # CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
@@ -994,7 +1090,6 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_SIERRA is not set
 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
@@ -1015,6 +1110,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1022,7 +1118,6 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@@ -1031,13 +1126,20 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 #
-# MMC/SD Card Drivers
+# MMC/SD/SDIO Card Drivers
 #
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_BLOCK_BOUNCE=y
@@ -1045,10 +1147,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_MMC_TEST is not set
 #
-# MMC/SD Host Controller Drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
 CONFIG_MMC_PXA=m
 # CONFIG_MMC_SDHCI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -1057,7 +1161,10 @@ CONFIG_LEDS_CLASS=y
 #
 # CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP5521 is not set
 # CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
 #
 # LED Triggers
@@ -1065,7 +1172,13 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 # CONFIG_LEDS_TRIGGER_TIMER is not set
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
 # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+#
+# iptables trigger is under Netfilter config (LED target)
+#
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -1096,6 +1209,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
 #
 # SPI RTC drivers
@@ -1105,28 +1219,27 @@ CONFIG_RTC_INTF_DEV=y
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+CONFIG_RTC_DRV_V3020=y
 #
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SA1100=y
+# CONFIG_RTC_DRV_PXA is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
-#
-# Voltage and Current regulators
-#
 # CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 #
 # File systems
@@ -1135,15 +1248,18 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1153,6 +1269,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -1173,15 +1294,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
-#
-# Miscellaneous filesystems
-#
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1201,6 +1320,7 @@ CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -1209,6 +1329,7 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1313,6 +1434,7 @@ CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
 # CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -1329,6 +1451,7 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
@@ -1336,22 +1459,38 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FTRACE=y
+# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_FTRACE is not set
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
@@ -1363,17 +1502,28 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_TEST is not set
@@ -1442,15 +1592,21 @@ CONFIG_CRYPTO_DES=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
 CONFIG_CRC_T10DIF=y
@@ -1460,7 +1616,10 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index eb2738b5be5f..ac18662f38cc 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc2
+# Linux kernel version: 2.6.30-rc7
-# Wed Apr 15 08:16:53 2009
+# Tue May 26 07:24:28 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -179,6 +179,7 @@ CONFIG_ARCH_DAVINCI=y
 # CONFIG_ARCH_OMAP is not set
 # CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_W90X900 is not set
+CONFIG_AINTC=y
 #
 # TI DaVinci Implementations
@@ -188,11 +189,17 @@ CONFIG_ARCH_DAVINCI=y
 # DaVinci Core Type
 #
 CONFIG_ARCH_DAVINCI_DM644x=y
+CONFIG_ARCH_DAVINCI_DM355=y
+CONFIG_ARCH_DAVINCI_DM646x=y
 #
 # DaVinci Board Type
 #
 CONFIG_MACH_DAVINCI_EVM=y
+CONFIG_MACH_SFFSDR=y
+CONFIG_MACH_DAVINCI_DM355_EVM=y
+CONFIG_MACH_DM355_LEOPARD=y
+CONFIG_MACH_DAVINCI_DM6467_EVM=y
 CONFIG_DAVINCI_MUX=y
 CONFIG_DAVINCI_MUX_DEBUG=y
 CONFIG_DAVINCI_MUX_WARNINGS=y
@@ -245,7 +252,7 @@ CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -661,7 +668,10 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
+CONFIG_TI_DAVINCI_EMAC=y
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=4
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
 # CONFIG_ETHOC is not set
 # CONFIG_SMC911X is not set
 # CONFIG_SMSC911X is not set
@@ -963,6 +973,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_ASIC3 is not set
+# CONFIG_MFD_DM355EVM_MSP is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_TPS65010 is not set
@@ -1317,6 +1328,7 @@ CONFIG_MMC_BLOCK=m
 # MMC/SD/SDIO Host Controller Drivers
 #
 # CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_DAVINCI is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
@@ -1778,6 +1790,7 @@ CONFIG_CRC32=y
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=m
 CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 3f89d5f25bce..3fb083b81b0a 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -1,12 +1,19 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20-rc1
+# Linux kernel version: 2.6.30-rc3
-# Sat Dec 16 06:05:24 2006
+# Tue May 19 12:26:49 2009
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
@@ -15,42 +22,54 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
-CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -58,31 +77,38 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 #
 # IO Schedulers
@@ -96,6 +122,7 @@ CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
 #
 # System Type
@@ -105,29 +132,40 @@ CONFIG_DEFAULT_IOSCHED="deadline"
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 CONFIG_ARCH_EP93XX=y
 # CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 #
@@ -138,14 +176,24 @@ CONFIG_CRUNCH=y
 #
 # EP93xx Platforms
 #
+# CONFIG_EP93XX_SDCE0_PHYS_OFFSET is not set
+CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET=y
 CONFIG_MACH_ADSSPHERE=y
+CONFIG_MACH_EDB93XX=y
+CONFIG_MACH_EDB9301=y
 CONFIG_MACH_EDB9302=y
-CONFIG_MACH_EDB9302A=y
+CONFIG_MACH_EDB9307=y
 CONFIG_MACH_EDB9312=y
 CONFIG_MACH_EDB9315=y
-CONFIG_MACH_EDB9315A=y
 CONFIG_MACH_GESBC9312=y
+CONFIG_MACH_MICRO9=y
+CONFIG_MACH_MICRO9H=y
+CONFIG_MACH_MICRO9M=y
+CONFIG_MACH_MICRO9L=y
 CONFIG_MACH_TS72XX=y
+CONFIG_EP93XX_EARLY_UART1=y
+# CONFIG_EP93XX_EARLY_UART2 is not set
+# CONFIG_EP93XX_EARLY_UART3 is not set
 #
 # Processor Type
@@ -154,6 +202,7 @@ CONFIG_CPU_32=y
 CONFIG_CPU_ARM920T=y
 CONFIG_CPU_32v4T=y
 CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
@@ -168,34 +217,47 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
 CONFIG_ARM_VIC=y
+CONFIG_COMMON_CLKDEV=y
 #
 # Bus support
 #
 CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
-#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
-# PCCARD (PCMCIA/CardBus) support
-#
 # CONFIG_PCCARD is not set
 #
 # Kernel Features
 #
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=100
-# CONFIG_AEABI is not set
+CONFIG_AEABI=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 CONFIG_ALIGNMENT_TRAP=y
 #
@@ -205,6 +267,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/nfs ip=bootp"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
 #
 # Floating point emulation
@@ -221,32 +289,31 @@ CONFIG_FPE_NWFPE_XP=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
 #
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-#
-# Networking
-#
 CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
@@ -267,6 +334,7 @@ CONFIG_SYN_COOKIES=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
@@ -276,6 +344,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 CONFIG_IPV6=y
 # CONFIG_IPV6_PRIVACY is not set
 # CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 # CONFIG_INET6_AH is not set
 # CONFIG_INET6_ESP is not set
 # CONFIG_INET6_IPCOMP is not set
@@ -289,25 +358,15 @@ CONFIG_IPV6=y
 # CONFIG_IPV6_SIT is not set
 # CONFIG_IPV6_TUNNEL is not set
 # CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -317,20 +376,28 @@ CONFIG_IPV6=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 #
 # Device Drivers
@@ -339,41 +406,39 @@ CONFIG_IPV6=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
 CONFIG_MTD_REDBOOT_PARTS=y
 CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
 # CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
 # CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 #
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 #
 # RAM/ROM/Flash chip drivers
@@ -404,16 +469,13 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 CONFIG_MTD_ROM=y
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x0
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=1
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -431,49 +493,58 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_VERIFY_WRITE=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND_TS7250=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_TS7250 is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
-#
+# CONFIG_MTD_ALAUDA is not set
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 #
-# Parallel port support
+# LPDDR flash memory drivers
-#
-# CONFIG_PARPORT is not set
-#
-# Plug and Play support
 #
+# CONFIG_MTD_LPDDR is not set
 #
-# Block devices
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 CONFIG_BLK_DEV_NBD=y
 # CONFIG_BLK_DEV_UB is not set
 # CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+CONFIG_EEPROM_LEGACY=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_SCSI_PROC_FS is not set
@@ -495,6 +566,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 #
 # SCSI Transports
@@ -502,92 +574,71 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
-#
+CONFIG_SCSI_LOWLEVEL=y
-# SCSI low-level drivers
-#
 # CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
 # CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
-#
+# CONFIG_SCSI_OSD_INITIATOR is not set
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_VETH is not set
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_EP93XX_ETH=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 #
-# Wireless LAN (non-hamradio)
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_NET_RADIO is not set
 #
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+CONFIG_USB_RTL8150=y
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 #
@@ -605,6 +656,7 @@ CONFIG_EP93XX_ETH=y
 # Character devices
 #
 # CONFIG_VT is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 #
@@ -621,104 +673,101 @@ CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_EP93XX_WATCHDOG=y
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 #
-# TPM devices
+# I2C Hardware Bus support
 #
-# CONFIG_TCG_TPM is not set
 #
-# I2C support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
-CONFIG_I2C=y
+# CONFIG_I2C_GPIO is not set
-CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
 #
-# I2C Algorithms
+# External I2C/SMBus adapter drivers
 #
-CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_ALGOPCA is not set
+# CONFIG_I2C_TINY_USB is not set
 #
-# I2C Hardware Bus support
+# Other I2C/SMBus bus drivers
 #
-# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_DS1374 is not set
-CONFIG_EEPROM_LEGACY=y
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 CONFIG_I2C_DEBUG_CORE=y
 CONFIG_I2C_DEBUG_ALGO=y
 CONFIG_I2C_DEBUG_BUS=y
 CONFIG_I2C_DEBUG_CHIP=y
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
 #
-# SPI support
+# Memory mapped GPIO expanders:
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 #
-# Dallas's 1-wire bus
+# I2C GPIO expanders:
 #
-# CONFIG_W1 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
 #
-# Hardware Monitoring support
+# PCI GPIO expanders:
 #
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -732,158 +781,188 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
 # CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
 #
-# Misc devices
+# Watchdog Device Drivers
 #
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_EP93XX_WATCHDOG=y
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
+# CONFIG_SSB is not set
 #
-# LED Triggers
+# Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
 #
 # Multimedia devices
 #
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_DAB is not set
-# CONFIG_USB_DABUSB is not set
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 #
-# Sound
+# Display device support
 #
+# CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
-#
-# USB support
-#
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 #
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 CONFIG_USB_DYNAMIC_MINORS=y
-# CONFIG_USB_MULTITHREAD_PROBE is not set
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 #
-# may also be needed; see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
 #
-# USB Input Devices
-#
-#
-# USB HID Boot Protocol drivers
-#
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
 #
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-CONFIG_USB_RTL8150=y
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_MON is not set
-#
 # USB port drivers
 #
-#
-# USB Serial Converter support
-#
 CONFIG_USB_SERIAL=y
 CONFIG_USB_SERIAL_CONSOLE=y
+# CONFIG_USB_EZUSB is not set
 # CONFIG_USB_SERIAL_GENERIC is not set
 # CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_AIRPRIME is not set
 # CONFIG_USB_SERIAL_ARK3116 is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CP210X is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
@@ -895,6 +974,7 @@ CONFIG_USB_SERIAL_CONSOLE=y
 # CONFIG_USB_SERIAL_EDGEPORT_TI is not set
 # CONFIG_USB_SERIAL_GARMIN is not set
 # CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
 # CONFIG_USB_SERIAL_KLSI is not set
@@ -902,16 +982,23 @@ CONFIG_USB_SERIAL_CONSOLE=y
 # CONFIG_USB_SERIAL_MCT_U232 is not set
 # CONFIG_USB_SERIAL_MOS7720 is not set
 # CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
 # CONFIG_USB_SERIAL_NAVMAN is not set
 CONFIG_USB_SERIAL_PL2303=y
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
 # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
 # CONFIG_USB_SERIAL_DEBUG is not set
 #
@@ -920,38 +1007,34 @@ CONFIG_USB_SERIAL_PL2303=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
-#
+# CONFIG_USB_VST is not set
-# USB DSL modem support
-#
-#
-# USB Gadget Support
-#
 # CONFIG_USB_GADGET is not set
 #
-# MMC/SD Card support
+# OTG and related infrastructure
 #
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
-#
+# CONFIG_ACCESSIBILITY is not set
-# Real Time Clock
+# CONFIG_NEW_LEDS is not set
-#
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
@@ -965,24 +1048,55 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_X1205 is not set
 CONFIG_RTC_DRV_DS1307=y
-# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+#
+# SPI RTC drivers
+#
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
 CONFIG_RTC_DRV_M48T86=y
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
 CONFIG_RTC_DRV_EP93XX=y
+# CONFIG_RTC_DRV_PL030 is not set
 # CONFIG_RTC_DRV_PL031 is not set
-# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_DMADEVICES is not set
-# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 #
 # File systems
@@ -991,27 +1105,31 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
+# CONFIG_BTRFS_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -1032,16 +1150,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
-#
-# Miscellaneous filesystems
-#
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -1049,33 +1164,35 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
-#
+CONFIG_NETWORK_FILESYSTEMS=y
-# Network File Systems
-#
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
@@ -1087,7 +1204,6 @@ CONFIG_SUNRPC=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 #
 # Partition Types
@@ -1109,10 +1225,7 @@ CONFIG_MSDOS_PARTITION=y
 # CONFIG_SUN_PARTITION is not set
 # CONFIG_KARMA_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -1153,49 +1266,83 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
 #
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-#
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
 CONFIG_DEBUG_SLAB=y
 # CONFIG_DEBUG_SLAB_LEAK is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
-CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_SG is not set
-CONFIG_FORCED_INLINING=y
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
@@ -1204,21 +1351,115 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
 #
-# Cryptographic options
+# Random Number Generation
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 CONFIG_LIBCRC32C=y
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
-CONFIG_IOMAP_COPY=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index dcf8153a947d..0a1abb978d7e 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -182,6 +182,7 @@ CONFIG_ARCH_KIRKWOOD=y
 CONFIG_MACH_DB88F6281_BP=y
 CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
+CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_TS219=y
 CONFIG_PLAT_ORION=y
@@ -270,7 +271,9 @@ CONFIG_CMDLINE=""
 #
 # CPU Power Management
 #
-# CONFIG_CPU_IDLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 #
 # Floating point emulation
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index f56837f69ca7..957fd5fa27ca 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -190,6 +190,7 @@ CONFIG_ARCH_PXA=y
 # CONFIG_MACH_SAAR is not set
 # CONFIG_MACH_ARMCORE is not set
 # CONFIG_MACH_CM_X300 is not set
+CONFIG_MACH_H4700=y
 CONFIG_MACH_MAGICIAN=y
 # CONFIG_MACH_MIOA701 is not set
 # CONFIG_MACH_PCM027 is not set
@@ -828,7 +829,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
+CONFIG_MFD_ASIC3=y
 CONFIG_HTC_EGPIO=y
 CONFIG_HTC_PASIC3=y
 # CONFIG_TPS65010 is not set
@@ -891,7 +892,7 @@ CONFIG_FB_PXA_OVERLAY=y
 # CONFIG_FB_PXA_SMARTPANEL is not set
 # CONFIG_FB_PXA_PARAMETERS is not set
 # CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
+CONFIG_FB_W100=y
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
diff --git a/arch/arm/configs/mx21_defconfig b/arch/arm/configs/mx21_defconfig
new file mode 100644
index 000000000000..4b04290d8e81
--- /dev/null
+++ b/arch/arm/configs/mx21_defconfig
@@ -0,0 +1,1170 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc1
+# Tue Apr 14 16:58:09 2009
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+#
+# Freescale MXC Implementations
+#
+# CONFIG_ARCH_MX1 is not set
+CONFIG_ARCH_MX2=y
+# CONFIG_ARCH_MX3 is not set
+CONFIG_MACH_MX21=y
+# CONFIG_MACH_MX27 is not set
+#
+# MX2 platforms:
+#
+CONFIG_MACH_MX21ADS=y
+# CONFIG_MXC_IRQ_PRIOR is not set
+CONFIG_MXC_PWM=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_UNIX is not set
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=3
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_MXC=y
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_CS89x0=y
+CONFIG_CS89x0_NONISA_IRQ=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_8250_EXTENDED is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+#
+# Frame buffer hardware drivers
+#
+CONFIG_FB_IMX=y
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_MXC=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_VFAT_FS is not set
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig
new file mode 100644
index 000000000000..28be17fbc157
--- /dev/null
+++ b/arch/arm/configs/omap3_evm_defconfig
@@ -0,0 +1,1528 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc5
+# Mon May 18 14:01:52 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_MCBSP is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_SERIAL_WAKE=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OVERO is not set
+CONFIG_MACH_OMAP3EVM=y
+# CONFIG_MACH_OMAP3_PANDORA is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_OMAP_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+CONFIG_SMC911X=y
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=y
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ZERO_HNPTEST is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=m
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
new file mode 100644
index 000000000000..23e43ea4efa1
--- /dev/null
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -0,0 +1,866 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc7
+# Tue Jun  9 12:36:23 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+#
+# TI OMAP Implementations
+#
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP3 is not set
+CONFIG_ARCH_OMAP4=y
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_RESET_CLOCKS is not set
+# CONFIG_OMAP_MUX is not set
+# CONFIG_OMAP_MCBSP is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+#
+# OMAP Board Type
+#
+CONFIG_MACH_OMAP_4430SDP=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_DCACHE_DISABLE=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_GIC=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=2
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_UNEVICTABLE_LRU is not set
+CONFIG_HAVE_MLOCK=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_NEON is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig
new file mode 100644
index 000000000000..213fe9c5eaae
--- /dev/null
+++ b/arch/arm/configs/omap_zoom2_defconfig
@@ -0,0 +1,1211 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-rc5
+# Fri Oct 10 11:49:41 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM7X00A is not set
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_OMAP_SERIAL_WAKE=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OMAP_LDP is not set
+CONFIG_MACH_OMAP_ZOOM2=y
+# CONFIG_MACH_OVERO is not set
+#
+# Boot options
+#
+#
+# Power management
+#
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_NEON is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_OMAP24XX=y
+#
+# SPI Protocol Masters
+#
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+CONFIG_W1=y
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_GPIO is not set
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+# CONFIG_W1_SLAVE_DS2760 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_OMAP is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 5b98f7645119..9e2385293ecb 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -903,7 +903,8 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_TIMERIOMEM=m
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
index 593102da8cd7..eb2cb31825c0 100644
--- a/arch/arm/configs/rx51_defconfig
+++ b/arch/arm/configs/rx51_defconfig
@@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw console=ttyMTD5"
+CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig
new file mode 100644
index 000000000000..44461f197a17
--- /dev/null
+++ b/arch/arm/configs/stmp378x_defconfig
@@ -0,0 +1,1141 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc2
+# Thu Apr 23 02:44:13 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-default"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
+CONFIG_INITRAMFS_COMPRESSION_GZIP=y
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_TRACEPOINTS=y
+CONFIG_MARKERS=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_ARCH_STMP3XXX=y
+#
+# Freescale STMP3xxx implementations
+#
+# CONFIG_ARCH_STMP37XX is not set
+CONFIG_ARCH_STMP378X=y
+# CONFIG_MACH_STMP37XX is not set
+CONFIG_MACH_STMP378X=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HIGHMEM=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+CONFIG_NET_SCHED=y
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_PARTITIONS is not set
+# CONFIG_MTD_TESTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=6144
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+#
+# Encoders/decoders and other helper chips
+#
+#
+# Audio decoders
+#
+#
+# RDS decoders
+#
+#
+# Video decoders
+#
+#
+# Video and audio decoders
+#
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+#
+# Video encoders
+#
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_SELFTEST=y
+CONFIG_DEBUG_OBJECTS_FREE=y
+CONFIG_DEBUG_OBJECTS_TIMERS=y
+CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
+CONFIG_DEBUG_SLAB=y
+CONFIG_DEBUG_SLAB_LEAK=y
+CONFIG_DEBUG_PREEMPT=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_LOCKDEP=y
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_LOCKDEP is not set
+CONFIG_TRACE_IRQFLAGS=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+CONFIG_DEBUG_KOBJECT=y
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+CONFIG_FUNCTION_TRACER=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+CONFIG_CONTEXT_SWITCH_TRACER=y
+# CONFIG_EVENT_TRACER is not set
+CONFIG_BOOT_TRACER=y
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_STACK_TRACER=y
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig
new file mode 100644
index 000000000000..401279d531d5
--- /dev/null
+++ b/arch/arm/configs/stmp37xx_defconfig
@@ -0,0 +1,1002 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29.1
+# Mon Apr 20 04:41:26 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-default"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_TRACEPOINTS=y
+CONFIG_MARKERS=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_ARCH_STMP3XXX=y
+#
+# Freescale STMP3xxx implementations
+#
+CONFIG_ARCH_STMP37XX=y
+# CONFIG_ARCH_STMP378X is not set
+CONFIG_MACH_STMP37XX=y
+# CONFIG_MACH_STMP378X is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=6144
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_UINPUT is not set
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_STMP_DBG is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+#
+# Encoders/decoders and other helper chips
+#
+#
+# Audio decoders
+#
+#
+# Video decoders
+#
+#
+# Video and audio decoders
+#
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+#
+# Video encoders
+#
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_SOC_CAMERA is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+#
+# Tracers
+#
+CONFIG_FUNCTION_TRACER=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_BOOT_TRACER=y
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_STACK_TRACER=y
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
new file mode 100644
index 000000000000..2d827e121147
--- /dev/null
+++ b/arch/arm/configs/u300_defconfig
@@ -0,0 +1,1115 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc6
+# Mon Jun  1 09:18:22 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_AIO is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+CONFIG_ARCH_U300=y
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+#
+# ST-Ericsson AB U300/U330/U335/U365 Platform
+#
+#
+# ST-Ericsson Mobile Platform Products
+#
+CONFIG_MACH_U300=y
+#
+# ST-Ericsson U300/U330/U335/U365 Feature Selections
+#
+# CONFIG_MACH_U300_BS2X is not set
+# CONFIG_MACH_U300_BS330 is not set
+CONFIG_MACH_U300_BS335=y
+# CONFIG_MACH_U300_BS365 is not set
+# CONFIG_MACH_U300_SINGLE_RAM is not set
+CONFIG_MACH_U300_DUAL_RAM=y
+CONFIG_U300_DEBUG=y
+# CONFIG_MACH_U300_SEMI_IS_SHARED is not set
+#
+# All the settings below must match the bootloader's settings
+#
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_ARM_VIC=y
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_ALIGNMENT_TRAP=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/mtdblock2 rw rootfstype=yaffs2 console=ttyAMA0,115200n8 ab3100.force=0,0x48 mtdparts=u300nand:128k@0x0(bootrecords)ro,8064k@128k(free)ro,253952k@8192k(platform) lpj=515072"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+#
+# Multimedia devices
+#
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_ARMCLCD is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_ARMMMCI=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+CONFIG_DMADEVICES=y
+#
+# DMA Devices
+#
+# CONFIG_AUXDISPLAY is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/w90p910_defconfig b/arch/arm/configs/w90p910_defconfig
index 56bda7c6d670..5245655a0ad3 100644
--- a/arch/arm/configs/w90p910_defconfig
+++ b/arch/arm/configs/w90p910_defconfig
@@ -1,11 +1,11 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc8-git8
+# Linux kernel version: 2.6.30
-# Sat Nov 15 10:05:00 2008
+# Wed Jun 10 22:09:25 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
 # CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
@@ -22,8 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -42,10 +40,19 @@ CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_BSD_PROCESS_ACCT=y
 # CONFIG_BSD_PROCESS_ACCT_V3 is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
@@ -56,52 +63,53 @@ CONFIG_USER_NS=y
 # CONFIG_PID_NS is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+CONFIG_TRACEPOINTS=y
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_SLOW_WORK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-# CONFIG_HAVE_CLK is not set
-CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 # CONFIG_MODULES is not set
 CONFIG_BLOCK=y
 CONFIG_LBD=y
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_LSF=y
 CONFIG_BLK_DEV_BSG=y
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -117,7 +125,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
 #
 # System Type
@@ -127,10 +135,10 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
@@ -151,23 +159,17 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MMP is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
+# CONFIG_ARCH_MSM is not set
 CONFIG_ARCH_W90X900=y
-#
-# Boot options
-#
-#
-# Power management
-#
 CONFIG_CPU_W90P910=y
 #
@@ -198,6 +200,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
 # CONFIG_OUTER_CACHE is not set
+CONFIG_COMMON_CLKDEV=y
 #
 # Bus support
@@ -209,27 +212,32 @@ CONFIG_ARM_THUMB=y
 #
 # Kernel Features
 #
-# CONFIG_TICK_ONESHOT is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_ZONE_DMA_FLAG=0
-CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 CONFIG_ALIGNMENT_TRAP=y
 #
@@ -237,12 +245,17 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0
 CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 initrd=0xa00000,4000000 mem=64M"
+CONFIG_CMDLINE="root=/dev/ram0 console=ttyS0,115200n8 rdinit=/sbin/init mem=64M"
 # CONFIG_XIP_KERNEL is not set
 CONFIG_KEXEC=y
 CONFIG_ATAGS_PROC=y
 #
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
 # Floating point emulation
 #
@@ -258,6 +271,8 @@ CONFIG_FPE_NWFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 # CONFIG_BINFMT_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
@@ -282,11 +297,93 @@ CONFIG_FW_LOADER=y
 CONFIG_FIRMWARE_IN_KERNEL=y
 CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=16384
@@ -300,9 +397,41 @@ CONFIG_HAVE_IDE=y
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
+CONFIG_SCSI=y
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
@@ -354,38 +483,57 @@ CONFIG_HW_CONSOLE=y
 #
 # Serial drivers
 #
-# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_8250_EXTENDED is not set
 #
 # Non-8250 serial port support
 #
-CONFIG_SERIAL_W90X900=y
-# CONFIG_SERIAL_W90X900_PORT1 is not set
-# CONFIG_SERIAL_W90X900_PORT2 is not set
-# CONFIG_SERIAL_W90X900_PORT3 is not set
-# CONFIG_SERIAL_W90X900_PORT4 is not set
-CONFIG_SERIAL_W90X900_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 #
@@ -393,10 +541,11 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6393XB is not set
-# CONFIG_MFD_TC6387XB is not set
 #
 # Multimedia devices
@@ -433,33 +582,131 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
-#
-# Voltage and Current regulators
-#
 # CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
 # CONFIG_QUOTA is not set
@@ -469,6 +716,11 @@ CONFIG_FS_POSIX_ACL=y
 CONFIG_GENERIC_ACL=y
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -486,15 +738,13 @@ CONFIG_GENERIC_ACL=y
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
-#
-# Miscellaneous filesystems
-#
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -502,15 +752,22 @@ CONFIG_TMPFS_POSIX_ACL=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 #
 # Partition Types
@@ -586,18 +843,36 @@ CONFIG_FRAME_WARN=1024
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
+CONFIG_STACKTRACE=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_LATENCYTOP is not set
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FTRACE=y
+CONFIG_NOP_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FUNCTION_TRACER=y
-# CONFIG_FTRACE is not set
+CONFIG_RING_BUFFER=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
 # CONFIG_DEBUG_USER is not set
 #
@@ -605,14 +880,15 @@ CONFIG_HAVE_ARCH_KGDB=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
+CONFIG_BINARY_PRINTF=y
 #
 # Library routines
 #
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@@ -620,7 +896,10 @@ CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_CRC32 is not set
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index bb7d695f3900..1a711ea8418b 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -429,6 +429,14 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
                __flush_anon_page(vma, page, vmaddr);
 }
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+        /* highmem pages are always flushed upon kunmap already */
+        if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
+                __cpuc_flush_dcache_page(page_address(page));
+}
 #define flush_dcache_mmap_lock(mapping) \
        spin_lock_irq(&(mapping)->tree_lock)
 #define flush_dcache_mmap_unlock(mapping) \
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7b9d27e749b8..b3e656c6fb78 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,6 +8,21 @@
 #define CPUID_TCM       2
 #define CPUID_TLBTYPE   3
+#define CPUID_EXT_PFR0  "c1, 0"
+#define CPUID_EXT_PFR1  "c1, 1"
+#define CPUID_EXT_DFR0  "c1, 2"
+#define CPUID_EXT_AFR0  "c1, 3"
+#define CPUID_EXT_MMFR0 "c1, 4"
+#define CPUID_EXT_MMFR1 "c1, 5"
+#define CPUID_EXT_MMFR2 "c1, 6"
+#define CPUID_EXT_MMFR3 "c1, 7"
+#define CPUID_EXT_ISAR0 "c2, 0"
+#define CPUID_EXT_ISAR1 "c2, 1"
+#define CPUID_EXT_ISAR2 "c2, 2"
+#define CPUID_EXT_ISAR3 "c2, 3"
+#define CPUID_EXT_ISAR4 "c2, 4"
+#define CPUID_EXT_ISAR5 "c2, 5"
 #ifdef CONFIG_CPU_CP15
 #define read_cpuid(reg)                                                 \
        ({                                                              \
@@ -18,9 +33,19 @@
                    : "cc");                                            \
                __val;                                                  \
        })
+#define read_cpuid_ext(ext_reg)                                         \
+        ({                                                              \
+                unsigned int __val;                                     \
+                asm("mrc        p15, 0, %0, c0, " ext_reg               \
+                    : "=r" (__val)                                      \
+                    :                                                   \
+                    : "cc");                                            \
+                __val;                                                  \
+        })
 #else
 extern unsigned int processor_id;
 #define read_cpuid(reg) (processor_id)
+#define read_cpuid_ext(reg) 0
 #endif
 /*
diff --git a/arch/arm/include/asm/hardware/arm_twd.h b/arch/arm/include/asm/hardware/arm_twd.h
deleted file mode 100644
index e521b70713c8..000000000000
--- a/arch/arm/include/asm/hardware/arm_twd.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __ASM_HARDWARE_TWD_H
-#define __ASM_HARDWARE_TWD_H
-#define TWD_TIMER_LOAD                  0x00
-#define TWD_TIMER_COUNTER               0x04
-#define TWD_TIMER_CONTROL               0x08
-#define TWD_TIMER_INTSTAT               0x0C
-#define TWD_WDOG_LOAD                   0x20
-#define TWD_WDOG_COUNTER                0x24
-#define TWD_WDOG_CONTROL                0x28
-#define TWD_WDOG_INTSTAT                0x2C
-#define TWD_WDOG_RESETSTAT              0x30
-#define TWD_WDOG_DISABLE                0x34
-#define TWD_TIMER_CONTROL_ENABLE        (1 << 0)
-#define TWD_TIMER_CONTROL_ONESHOT       (0 << 1)
-#define TWD_TIMER_CONTROL_PERIODIC      (1 << 1)
-#define TWD_TIMER_CONTROL_IT_ENABLE     (1 << 2)
-#endif
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 64f2252a25cd..cdb9022716fd 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -24,6 +24,8 @@
 #define L2X0_CACHE_TYPE                 0x004
 #define L2X0_CTRL                       0x100
 #define L2X0_AUX_CTRL                   0x104
+#define L2X0_TAG_LATENCY_CTRL           0x108
+#define L2X0_DATA_LATENCY_CTRL          0x10C
 #define L2X0_EVENT_CNT_CTRL             0x200
 #define L2X0_EVENT_CNT1_CFG             0x204
 #define L2X0_EVENT_CNT0_CFG             0x208
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
new file mode 100644
index 000000000000..6a6c66be7f65
--- /dev/null
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -0,0 +1,138 @@
+/* arch/arm/include/asm/hardware/pl080.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * ARM PrimeCell PL080 DMA controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* Note, there are some Samsung updates to this controller block which
+ * make it not entierly compatible with the PL080 specification from
+ * ARM. When in doubt, check the Samsung documentation first.
+ *
+ * The Samsung defines are PL080S, and add an extra controll register,
+ * the ability to move more than 2^11 counts of data and some extra
+ * OneNAND features.
+*/
+#define PL080_INT_STATUS                        (0x00)
+#define PL080_TC_STATUS                         (0x04)
+#define PL080_TC_CLEAR                          (0x08)
+#define PL080_ERR_STATUS                        (0x0C)
+#define PL080_ERR_CLEAR                         (0x10)
+#define PL080_RAW_TC_STATUS                     (0x14)
+#define PL080_RAW_ERR_STATUS                    (0x18)
+#define PL080_EN_CHAN                           (0x1c)
+#define PL080_SOFT_BREQ                         (0x20)
+#define PL080_SOFT_SREQ                         (0x24)
+#define PL080_SOFT_LBREQ                        (0x28)
+#define PL080_SOFT_LSREQ                        (0x2C)
+#define PL080_CONFIG                            (0x30)
+#define PL080_CONFIG_M2_BE                      (1 << 2)
+#define PL080_CONFIG_M1_BE                      (1 << 1)
+#define PL080_CONFIG_ENABLE                     (1 << 0)
+#define PL080_SYNC                              (0x34)
+/* Per channel configuration registers */
+#define PL008_Cx_STRIDE                         (0x20)
+#define PL080_Cx_BASE(x)                        ((0x100 + (x * 0x20)))
+#define PL080_Cx_SRC_ADDR(x)                    ((0x100 + (x * 0x20)))
+#define PL080_Cx_DST_ADDR(x)                    ((0x104 + (x * 0x20)))
+#define PL080_Cx_LLI(x)                         ((0x108 + (x * 0x20)))
+#define PL080_Cx_CONTROL(x)                     ((0x10C + (x * 0x20)))
+#define PL080_Cx_CONFIG(x)                      ((0x110 + (x * 0x20)))
+#define PL080S_Cx_CONTROL2(x)                   ((0x110 + (x * 0x20)))
+#define PL080S_Cx_CONFIG(x)                     ((0x114 + (x * 0x20)))
+#define PL080_CH_SRC_ADDR                       (0x00)
+#define PL080_CH_DST_ADDR                       (0x04)
+#define PL080_CH_LLI                            (0x08)
+#define PL080_CH_CONTROL                        (0x0C)
+#define PL080_CH_CONFIG                         (0x10)
+#define PL080S_CH_CONTROL2                      (0x10)
+#define PL080S_CH_CONFIG                        (0x14)
+#define PL080_LLI_ADDR_MASK                     (0x3fffffff << 2)
+#define PL080_LLI_ADDR_SHIFT                    (2)
+#define PL080_LLI_LM_AHB2                       (1 << 0)
+#define PL080_CONTROL_TC_IRQ_EN                 (1 << 31)
+#define PL080_CONTROL_PROT_MASK                 (0x7 << 28)
+#define PL080_CONTROL_PROT_SHIFT                (28)
+#define PL080_CONTROL_PROT_SYS                  (1 << 28)
+#define PL080_CONTROL_DST_INCR                  (1 << 27)
+#define PL080_CONTROL_SRC_INCR                  (1 << 26)
+#define PL080_CONTROL_DST_AHB2                  (1 << 25)
+#define PL080_CONTROL_SRC_AHB2                  (1 << 24)
+#define PL080_CONTROL_DWIDTH_MASK               (0x7 << 21)
+#define PL080_CONTROL_DWIDTH_SHIFT              (21)
+#define PL080_CONTROL_SWIDTH_MASK               (0x7 << 18)
+#define PL080_CONTROL_SWIDTH_SHIFT              (18)
+#define PL080_CONTROL_DB_SIZE_MASK              (0x7 << 15)
+#define PL080_CONTROL_DB_SIZE_SHIFT             (15)
+#define PL080_CONTROL_SB_SIZE_MASK              (0x7 << 12)
+#define PL080_CONTROL_SB_SIZE_SHIFT             (12)
+#define PL080_CONTROL_TRANSFER_SIZE_MASK        (0xfff << 0)
+#define PL080_CONTROL_TRANSFER_SIZE_SHIFT       (0)
+#define PL080_BSIZE_1                           (0x0)
+#define PL080_BSIZE_4                           (0x1)
+#define PL080_BSIZE_8                           (0x2)
+#define PL080_BSIZE_16                          (0x3)
+#define PL080_BSIZE_32                          (0x4)
+#define PL080_BSIZE_64                          (0x5)
+#define PL080_BSIZE_128                         (0x6)
+#define PL080_BSIZE_256                         (0x7)
+#define PL080_WIDTH_8BIT                        (0x0)
+#define PL080_WIDTH_16BIT                       (0x1)
+#define PL080_WIDTH_32BIT                       (0x2)
+#define PL080_CONFIG_HALT                       (1 << 18)
+#define PL080_CONFIG_ACTIVE                     (1 << 17)  /* RO */
+#define PL080_CONFIG_LOCK                       (1 << 16)
+#define PL080_CONFIG_TC_IRQ_MASK                (1 << 15)
+#define PL080_CONFIG_ERR_IRQ_MASK               (1 << 14)
+#define PL080_CONFIG_FLOW_CONTROL_MASK          (0x7 << 11)
+#define PL080_CONFIG_FLOW_CONTROL_SHIFT         (11)
+#define PL080_CONFIG_DST_SEL_MASK               (0xf << 6)
+#define PL080_CONFIG_DST_SEL_SHIFT              (6)
+#define PL080_CONFIG_SRC_SEL_MASK               (0xf << 1)
+#define PL080_CONFIG_SRC_SEL_SHIFT              (1)
+#define PL080_CONFIG_ENABLE                     (1 << 0)
+#define PL080_FLOW_MEM2MEM                      (0x0)
+#define PL080_FLOW_MEM2PER                      (0x1)
+#define PL080_FLOW_PER2MEM                      (0x2)
+#define PL080_FLOW_SRC2DST                      (0x3)
+#define PL080_FLOW_SRC2DST_DST                  (0x4)
+#define PL080_FLOW_MEM2PER_PER                  (0x5)
+#define PL080_FLOW_PER2MEM_PER                  (0x6)
+#define PL080_FLOW_SRC2DST_SRC                  (0x7)
+/* DMA linked list chain structure */
+struct pl080_lli {
+        u32     src_addr;
+        u32     dst_addr;
+        u32     next_lli;
+        u32     control0;
+};
+struct pl080s_lli {
+        u32     src_addr;
+        u32     dst_addr;
+        u32     next_lli;
+        u32     control0;
+        u32     control1;
+};
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index f87328d4a180..5d72550a8097 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -41,7 +41,7 @@
 #define VIC_PL192_VECT_ADDR             0xF00
 #ifndef __ASSEMBLY__
-void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
+void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
 #endif
 #endif
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
new file mode 100644
index 000000000000..50c7e7cfd670
--- /dev/null
+++ b/arch/arm/include/asm/localtimer.h
@@ -0,0 +1,63 @@
+/*
+ *  arch/arm/include/asm/localtimer.h
+ *
+ *  Copyright (C) 2004-2005 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_LOCALTIMER_H
+#define __ASM_ARM_LOCALTIMER_H
+struct clock_event_device;
+/*
+ * Setup a per-cpu timer, whether it be a local timer or dummy broadcast
+ */
+void percpu_timer_setup(void);
+/*
+ * Called from assembly, this is the local timer IRQ handler
+ */
+asmlinkage void do_local_timer(struct pt_regs *);
+#ifdef CONFIG_LOCAL_TIMERS
+#ifdef CONFIG_HAVE_ARM_TWD
+#include "smp_twd.h"
+#define local_timer_ack()       twd_timer_ack()
+#define local_timer_stop()      twd_timer_stop()
+#else
+/*
+ * Platform provides this to acknowledge a local timer IRQ.
+ * Returns true if the local timer IRQ is to be processed.
+ */
+int local_timer_ack(void);
+/*
+ * Stop a local timer interrupt.
+ */
+void local_timer_stop(void);
+#endif
+/*
+ * Setup a local timer interrupt for a CPU.
+ */
+void local_timer_setup(struct clock_event_device *);
+#else
+static inline void local_timer_stop(void)
+{
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 58cf91f38e6f..742c2aaeb020 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -30,6 +30,14 @@ struct map_desc {
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
+struct mem_type;
+extern const struct mem_type *get_mem_type(unsigned int type);
+/*
+ * external interface to remap single page with appropriate type
+ */
+extern int ioremap_page(unsigned long virt, unsigned long phys,
+                        const struct mem_type *mtype);
 #else
 #define iotable_init(map,num)   do { } while (0)
 #endif
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 110295c5461d..1cd2d6416bda 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -342,7 +342,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
        return __va(ptr);
 }
-#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
+#define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd)))
 /*
 * Conversion functions: convert a page and protection to a page entry,
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 1845892260e7..6a89567ffc5b 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -71,6 +71,7 @@ struct thread_struct {
                regs->ARM_cpsr = USR26_MODE;                            \
        if (elf_hwcap & HWCAP_THUMB && pc & 1)                          \
                regs->ARM_cpsr |= PSR_T_BIT;                            \
+        regs->ARM_cpsr |= PSR_ENDSTATE;                                 \
        regs->ARM_pc = pc & ~1;         /* pc */                        \
        regs->ARM_sp = sp;              /* sp */                        \
        regs->ARM_r2 = stack[2];        /* r2 (envp) */                 \
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 236a06b9b7ce..67b833c9b6b9 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -50,6 +50,7 @@
 #define PSR_F_BIT       0x00000040
 #define PSR_I_BIT       0x00000080
 #define PSR_A_BIT       0x00000100
+#define PSR_E_BIT       0x00000200
 #define PSR_J_BIT       0x01000000
 #define PSR_Q_BIT       0x08000000
 #define PSR_V_BIT       0x10000000
@@ -65,6 +66,22 @@
 #define PSR_x           0x0000ff00      /* Extension            */
 #define PSR_c           0x000000ff      /* Control              */
+/*
+ * ARMv7 groups of APSR bits
+ */
+#define PSR_ISET_MASK   0x01000010      /* ISA state (J, T) mask */
+#define PSR_IT_MASK     0x0600fc00      /* If-Then execution state mask */
+#define PSR_ENDIAN_MASK 0x00000200      /* Endianness state mask */
+/*
+ * Default endianness state
+ */
+#ifdef CONFIG_CPU_ENDIAN_BE8
+#define PSR_ENDSTATE    PSR_E_BIT
+#else
+#define PSR_ENDSTATE    0
+#endif
 #ifndef __ASSEMBLY__
 /*
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index ada93a8fc2ef..4fc1565e4f93 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -29,6 +29,7 @@
 #define SZ_512                          0x00000200
 #define SZ_1K                           0x00000400
+#define SZ_2K                           0x00000800
 #define SZ_4K                           0x00001000
 #define SZ_8K                           0x00002000
 #define SZ_16K                          0x00004000
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 5995935338e1..a06e735b262a 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -41,7 +41,7 @@ extern void show_ipi_list(struct seq_file *p);
 asmlinkage void do_IPI(struct pt_regs *regs);
 /*
- * Setup the SMP cpu_possible_map
+ * Setup the set of possible CPUs (via set_cpu_possible)
 */
 extern void smp_init_cpus(void);
@@ -56,11 +56,6 @@ extern void smp_store_cpu_info(unsigned int cpuid);
 extern void smp_cross_call(const struct cpumask *mask);
 /*
- * Broadcast a clock event to other CPUs.
- */
-extern void smp_timer_broadcast(const struct cpumask *mask);
-/*
 * Boot a secondary CPU, and assign it the specified idle task.
 * This also gives us the initial stack to use for this CPU.
 */
@@ -101,43 +96,8 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 #define arch_send_call_function_ipi_mask arch_send_call_function_ipi_mask
 /*
- * Local timer interrupt handling function (can be IPI'ed).
- */
-extern void local_timer_interrupt(void);
-#ifdef CONFIG_LOCAL_TIMERS
-/*
- * Stop a local timer interrupt.
- */
-extern void local_timer_stop(void);
-/*
- * Platform provides this to acknowledge a local timer IRQ
- */
-extern int local_timer_ack(void);
-#else
-static inline void local_timer_stop(void)
-{
-}
-#endif
-/*
- * Setup a local timer interrupt for a CPU.
- */
-extern void local_timer_setup(void);
-/*
 * show local interrupt info
 */
 extern void show_local_irqs(struct seq_file *);
-/*
- * Called from assembly, this is the local timer IRQ handler
- */
-asmlinkage void do_local_timer(struct pt_regs *);
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
new file mode 100644
index 000000000000..2376835015d6
--- /dev/null
+++ b/arch/arm/include/asm/smp_scu.h
@@ -0,0 +1,7 @@
+#ifndef __ASMARM_ARCH_SCU_H
+#define __ASMARM_ARCH_SCU_H
+unsigned int scu_get_core_count(void __iomem *);
+void scu_enable(void __iomem *);
+#endif
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
new file mode 100644
index 000000000000..7be0978b2625
--- /dev/null
+++ b/arch/arm/include/asm/smp_twd.h
@@ -0,0 +1,12 @@
+#ifndef __ASMARM_SMP_TWD_H
+#define __ASMARM_SMP_TWD_H
+struct clock_event_device;
+extern void __iomem *twd_base;
+void twd_timer_stop(void);
+int twd_timer_ack(void);
+void twd_timer_setup(struct clock_event_device *);
+#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a62218013c78..c964f3fc3bc5 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -40,6 +40,12 @@
 #define TLB_V6_I_ASID   (1 << 18)
 #define TLB_BTB         (1 << 28)
+/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
+#define TLB_V7_UIS_PAGE (1 << 19)
+#define TLB_V7_UIS_FULL (1 << 20)
+#define TLB_V7_UIS_ASID (1 << 21)
 #define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
 #define TLB_DCLEAN      (1 << 30)
 #define TLB_WB          (1 << 31)
@@ -176,9 +182,17 @@
 # define v6wbi_always_flags     (-1UL)
 #endif
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+                         TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
+#else
+#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+                         TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+#endif
 #ifdef CONFIG_CPU_TLB_V7
-# define v7wbi_possible_flags   v6wbi_tlb_flags
+# define v7wbi_possible_flags   v7wbi_tlb_flags
-# define v7wbi_always_flags     v6wbi_tlb_flags
+# define v7wbi_always_flags     v7wbi_tlb_flags
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
@@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void)
                asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
                asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
+        if (tlb_flag(TLB_V7_UIS_FULL))
+                asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
        if (tlb_flag(TLB_BTB)) {
                /* flush the branch target cache */
@@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
                asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
        if (tlb_flag(TLB_V6_I_ASID))
                asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
+        if (tlb_flag(TLB_V7_UIS_ASID))
+                asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
        if (tlb_flag(TLB_BTB)) {
                /* flush the branch target cache */
@@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
        if (tlb_flag(TLB_V6_I_PAGE))
                asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
+        if (tlb_flag(TLB_V7_UIS_PAGE))
+                asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
        if (tlb_flag(TLB_BTB)) {
                /* flush the branch target cache */
@@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
                asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
        if (tlb_flag(TLB_V6_I_PAGE))
                asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
+        if (tlb_flag(TLB_V7_UIS_PAGE))
+                asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
        if (tlb_flag(TLB_BTB)) {
                /* flush the branch target cache */
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 7897464e0c24..0da9bc9b3b1d 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -386,7 +386,9 @@ do {									\
 #ifdef CONFIG_MMU
 extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n);
 extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n);
+extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n);
 extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
+extern unsigned long __must_check __clear_user_std(void __user *addr, unsigned long n);
 #else
 #define __copy_from_user(to,from,n)     (memcpy(to, (void __force *)from, n), 0)
 #define __copy_to_user(to,from,n)       (memcpy((void __force *)to, from, n), 0)
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 11a5197a221f..ff89d0b3abc5 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -22,6 +22,8 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
 obj-$(CONFIG_SMP)               += smp.o
+obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
+obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_KPROBES)           += kprobes.o kprobes-decode.o
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 83b1da6b7baa..fc8af43c5000 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -482,6 +482,9 @@ __und_usr:
        subeq   r4, r2, #4                      @ ARM instr at LR - 4
        subne   r4, r2, #2                      @ Thumb instr at LR - 2
 1:      ldreqt  r0, [r4]
+#ifdef CONFIG_CPU_ENDIAN_BE8
+        reveq   r0, r0                          @ little endian instruction
+#endif
        beq     call_fpe
        @ Thumb instruction
 #if __LINUX_ARM_ARCH__ >= 7
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index b55cb0331809..366e5097a41a 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -210,6 +210,9 @@ ENTRY(vector_swi)
  A710( teq     ip, #0x0f000000                                         )
  A710( bne     .Larm710bug                                             )
 #endif
+#ifdef CONFIG_CPU_ENDIAN_BE8
+        rev     r10, r10                        @ little endian instruction
+#endif
 #elif defined(CONFIG_AEABI)
diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c
index e859af349467..3f470866bb89 100644
--- a/arch/arm/kernel/init_task.c
+++ b/arch/arm/kernel/init_task.c
@@ -14,10 +14,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index c3265a2e7cd4..1585423699ee 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -365,7 +365,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
        regs.ARM_r2 = (unsigned long)fn;
        regs.ARM_r3 = (unsigned long)do_exit;
        regs.ARM_pc = (unsigned long)kernel_thread_helper;
-        regs.ARM_cpsr = SVC_MODE;
+        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
        return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 80b8b5c7e07a..93bb4247b7ed 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -426,9 +426,13 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
                 */
                thumb = handler & 1;
-                if (thumb)
+                if (thumb) {
                        cpsr |= PSR_T_BIT;
-                else
+#if __LINUX_ARM_ARCH__ >= 7
+                        /* clear the If-Then Thumb-2 execution state */
+                        cpsr &= ~PSR_IT_MASK;
+#endif
+                } else
                        cpsr &= ~PSR_T_BIT;
        }
 #endif
@@ -532,7 +536,7 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
        return err;
 }
-static inline void restart_syscall(struct pt_regs *regs)
+static inline void setup_syscall_restart(struct pt_regs *regs)
 {
        regs->ARM_r0 = regs->ARM_ORIG_r0;
        regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
@@ -567,7 +571,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
                        }
                        /* fallthrough */
                case -ERESTARTNOINTR:
-                        restart_syscall(regs);
+                        setup_syscall_restart(regs);
                }
        }
@@ -691,7 +695,7 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
                if (regs->ARM_r0 == -ERESTARTNOHAND ||
                    regs->ARM_r0 == -ERESTARTSYS ||
                    regs->ARM_r0 == -ERESTARTNOINTR) {
-                        restart_syscall(regs);
+                        setup_syscall_restart(regs);
                }
        }
        single_step_set(current);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 6014dfd22af4..de885fd256c5 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -22,16 +22,20 @@
 #include <linux/smp.h>
 #include <linux/seq_file.h>
 #include <linux/irq.h>
+#include <linux/percpu.h>
+#include <linux/clockchips.h>
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/cpu.h>
+#include <asm/cputype.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
+#include <asm/localtimer.h>
 /*
 * as from 2.5, kernels no longer have an init_tasks structure
@@ -163,7 +167,7 @@ int __cpuexit __cpu_disable(void)
         * Take this CPU offline.  Once we clear this, we can't return,
         * and we must not schedule until we're ready to give up the cpu.
         */
-        cpu_clear(cpu, cpu_online_map);
+        set_cpu_online(cpu, false);
        /*
         * OK - migrate IRQs away from this CPU
@@ -274,9 +278,9 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
        local_fiq_enable();
        /*
-         * Setup local timer for this CPU.
+         * Setup the percpu timer for this CPU.
         */
-        local_timer_setup();
+        percpu_timer_setup();
        calibrate_delay();
@@ -285,7 +289,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
        /*
         * OK, now it's safe to let the boot CPU continue
         */
-        cpu_set(cpu, cpu_online_map);
+        set_cpu_online(cpu, true);
        /*
         * OK, it's off to the idle thread for us
@@ -383,10 +387,16 @@ void show_local_irqs(struct seq_file *p)
        seq_putc(p, '\n');
 }
+/*
+ * Timer (local or broadcast) support
+ */
+static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
 static void ipi_timer(void)
 {
+        struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
        irq_enter();
-        local_timer_interrupt();
+        evt->event_handler(evt);
        irq_exit();
 }
@@ -405,6 +415,42 @@ asmlinkage void __exception do_local_timer(struct pt_regs *regs)
 }
 #endif
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+static void smp_timer_broadcast(const struct cpumask *mask)
+{
+        send_ipi_message(mask, IPI_TIMER);
+}
+static void broadcast_timer_set_mode(enum clock_event_mode mode,
+        struct clock_event_device *evt)
+{
+}
+static void local_timer_setup(struct clock_event_device *evt)
+{
+        evt->name       = "dummy_timer";
+        evt->features   = CLOCK_EVT_FEAT_ONESHOT |
+                          CLOCK_EVT_FEAT_PERIODIC |
+                          CLOCK_EVT_FEAT_DUMMY;
+        evt->rating     = 400;
+        evt->mult       = 1;
+        evt->set_mode   = broadcast_timer_set_mode;
+        evt->broadcast  = smp_timer_broadcast;
+        clockevents_register_device(evt);
+}
+#endif
+void __cpuinit percpu_timer_setup(void)
+{
+        unsigned int cpu = smp_processor_id();
+        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
+        evt->cpumask = cpumask_of(cpu);
+        local_timer_setup(evt);
+}
 static DEFINE_SPINLOCK(stop_lock);
 /*
@@ -417,7 +463,7 @@ static void ipi_cpu_stop(unsigned int cpu)
        dump_stack();
        spin_unlock(&stop_lock);
-        cpu_clear(cpu, cpu_online_map);
+        set_cpu_online(cpu, false);
        local_fiq_disable();
        local_irq_disable();
@@ -501,11 +547,6 @@ void smp_send_reschedule(int cpu)
        send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
 }
-void smp_timer_broadcast(const struct cpumask *mask)
-{
-        send_ipi_message(mask, IPI_TIMER);
-}
 void smp_send_stop(void)
 {
        cpumask_t mask = cpu_online_map;
@@ -545,6 +586,12 @@ struct tlb_args {
        unsigned long ta_end;
 };
+/* all SMP configurations have the extended CPUID registers */
+static inline int tlb_ops_need_broadcast(void)
+{
+        return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
+}
 static inline void ipi_flush_tlb_all(void *ignored)
 {
        local_flush_tlb_all();
@@ -587,51 +634,61 @@ static inline void ipi_flush_tlb_kernel_range(void *arg)
 void flush_tlb_all(void)
 {
-        on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+        if (tlb_ops_need_broadcast())
+                on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+        else
+                local_flush_tlb_all();
 }
 void flush_tlb_mm(struct mm_struct *mm)
 {
-        on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask);
+        if (tlb_ops_need_broadcast())
+                on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask);
+        else
+                local_flush_tlb_mm(mm);
 }
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 {
-        struct tlb_args ta;
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
-        ta.ta_vma = vma;
+                ta.ta_vma = vma;
-        ta.ta_start = uaddr;
+                ta.ta_start = uaddr;
+                on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask);
-        on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask);
+        } else
+                local_flush_tlb_page(vma, uaddr);
 }
 void flush_tlb_kernel_page(unsigned long kaddr)
 {
-        struct tlb_args ta;
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
-        ta.ta_start = kaddr;
+                ta.ta_start = kaddr;
+                on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
-        on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
+        } else
+                local_flush_tlb_kernel_page(kaddr);
 }
 void flush_tlb_range(struct vm_area_struct *vma,
                     unsigned long start, unsigned long end)
 {
-        struct tlb_args ta;
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
-        ta.ta_vma = vma;
+                ta.ta_vma = vma;
-        ta.ta_start = start;
+                ta.ta_start = start;
-        ta.ta_end = end;
+                ta.ta_end = end;
+                on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask);
-        on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask);
+        } else
+                local_flush_tlb_range(vma, start, end);
 }
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 {
-        struct tlb_args ta;
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
-        ta.ta_start = start;
+                ta.ta_start = start;
-        ta.ta_end = end;
+                ta.ta_end = end;
+                on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
-        on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
+        } else
+                local_flush_tlb_kernel_range(start, end);
 }
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
new file mode 100644
index 000000000000..d3831f616ee9
--- /dev/null
+++ b/arch/arm/kernel/smp_scu.c
@@ -0,0 +1,48 @@
+/*
+ *  linux/arch/arm/kernel/smp_scu.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/smp_scu.h>
+#include <asm/cacheflush.h>
+#define SCU_CTRL                0x00
+#define SCU_CONFIG              0x04
+#define SCU_CPU_STATUS          0x08
+#define SCU_INVALIDATE          0x0c
+#define SCU_FPGA_REVISION       0x10
+/*
+ * Get the number of CPU cores from the SCU configuration
+ */
+unsigned int __init scu_get_core_count(void __iomem *scu_base)
+{
+        unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
+        return (ncores & 0x03) + 1;
+}
+/*
+ * Enable the SCU
+ */
+void __init scu_enable(void __iomem *scu_base)
+{
+        u32 scu_ctrl;
+        scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+        scu_ctrl |= 1;
+        __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
+        /*
+         * Ensure that the data accessed by CPU0 before the SCU was
+         * initialised is visible to the other CPUs.
+         */
+        flush_cache_all();
+}
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
new file mode 100644
index 000000000000..d8c88c633c6f
--- /dev/null
+++ b/arch/arm/kernel/smp_twd.c
@@ -0,0 +1,175 @@
+/*
+ *  linux/arch/arm/kernel/smp_twd.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/jiffies.h>
+#include <linux/clockchips.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/gic.h>
+#define TWD_TIMER_LOAD                  0x00
+#define TWD_TIMER_COUNTER               0x04
+#define TWD_TIMER_CONTROL               0x08
+#define TWD_TIMER_INTSTAT               0x0C
+#define TWD_WDOG_LOAD                   0x20
+#define TWD_WDOG_COUNTER                0x24
+#define TWD_WDOG_CONTROL                0x28
+#define TWD_WDOG_INTSTAT                0x2C
+#define TWD_WDOG_RESETSTAT              0x30
+#define TWD_WDOG_DISABLE                0x34
+#define TWD_TIMER_CONTROL_ENABLE        (1 << 0)
+#define TWD_TIMER_CONTROL_ONESHOT       (0 << 1)
+#define TWD_TIMER_CONTROL_PERIODIC      (1 << 1)
+#define TWD_TIMER_CONTROL_IT_ENABLE     (1 << 2)
+/* set up by the platform code */
+void __iomem *twd_base;
+static unsigned long twd_timer_rate;
+static void twd_set_mode(enum clock_event_mode mode,
+                        struct clock_event_device *clk)
+{
+        unsigned long ctrl;
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* timer load already set up */
+                ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
+                        | TWD_TIMER_CONTROL_PERIODIC;
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* period set, and timer enabled in 'next_event' hook */
+                ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                ctrl = 0;
+        }
+        __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
+}
+static int twd_set_next_event(unsigned long evt,
+                        struct clock_event_device *unused)
+{
+        unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+        ctrl |= TWD_TIMER_CONTROL_ENABLE;
+        __raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
+        __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
+        return 0;
+}
+/*
+ * local_timer_ack: checks for a local timer interrupt.
+ *
+ * If a local timer interrupt has occurred, acknowledge and return 1.
+ * Otherwise, return 0.
+ */
+int twd_timer_ack(void)
+{
+        if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
+                __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+                return 1;
+        }
+        return 0;
+}
+static void __cpuinit twd_calibrate_rate(void)
+{
+        unsigned long load, count;
+        u64 waitjiffies;
+        /*
+         * If this is the first time round, we need to work out how fast
+         * the timer ticks
+         */
+        if (twd_timer_rate == 0) {
+                printk(KERN_INFO "Calibrating local timer... ");
+                /* Wait for a tick to start */
+                waitjiffies = get_jiffies_64() + 1;
+                while (get_jiffies_64() < waitjiffies)
+                        udelay(10);
+                /* OK, now the tick has started, let's get the timer going */
+                waitjiffies += 5;
+                                 /* enable, no interrupt or reload */
+                __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
+                                 /* maximum value */
+                __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
+                while (get_jiffies_64() < waitjiffies)
+                        udelay(10);
+                count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
+                twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
+                printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
+                        (twd_timer_rate / 100000) % 100);
+        }
+        load = twd_timer_rate / HZ;
+        __raw_writel(load, twd_base + TWD_TIMER_LOAD);
+}
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit twd_timer_setup(struct clock_event_device *clk)
+{
+        unsigned long flags;
+        twd_calibrate_rate();
+        clk->name = "local_timer";
+        clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        clk->rating = 350;
+        clk->set_mode = twd_set_mode;
+        clk->set_next_event = twd_set_next_event;
+        clk->shift = 20;
+        clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
+        clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
+        clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
+        /* Make sure our local interrupt controller has this enabled */
+        local_irq_save(flags);
+        get_irq_chip(clk->irq)->unmask(clk->irq);
+        local_irq_restore(flags);
+        clockevents_register_device(clk);
+}
+/*
+ * take a local timer down
+ */
+void __cpuexit twd_timer_stop(void)
+{
+        __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+}
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index c90f27250ead..6c0779792546 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -141,6 +141,7 @@ SECTIONS
        .data : AT(__data_loc) {
                _data = .;              /* address in memory */
+                _sdata = .;
                /*
                 * first, the init task union, aligned
@@ -192,6 +193,7 @@ SECTIONS
                __bss_start = .;        /* BSS                          */
                *(.bss)
                *(COMMON)
+                __bss_stop = .;
                _end = .;
        }
                                        /* Stabs debugging sections.    */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 866f84a586ff..030ba7219f48 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -29,6 +29,9 @@ else
 endif
 endif
+# using lib_ here won't override already available weak symbols
+obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
 lib-$(CONFIG_MMU) += $(mmu-y)
 ifeq ($(CONFIG_CPU_32v3),y)
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index 4d6bc71231f3..844f56785ebc 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -18,7 +18,8 @@
 *          : sz   - number of bytes to clear
 * Returns  : number of bytes NOT cleared
 */
-ENTRY(__clear_user)
+ENTRY(__clear_user_std)
+WEAK(__clear_user)
                stmfd   sp!, {r1, lr}
                mov     r2, #0
                cmp     r1, #4
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 22f968bbdffd..878820f0a320 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -86,7 +86,8 @@
        .text
-ENTRY(__copy_to_user)
+ENTRY(__copy_to_user_std)
+WEAK(__copy_to_user)
 #include "copy_template.S"
diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c
new file mode 100644
index 000000000000..6b967ffb6552
--- /dev/null
+++ b/arch/arm/lib/uaccess_with_memcpy.c
@@ -0,0 +1,228 @@
+/*
+ *  linux/arch/arm/lib/uaccess_with_memcpy.c
+ *
+ *  Written by: Lennert Buytenhek and Nicolas Pitre
+ *  Copyright (C) 2009 Marvell Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/ctype.h>
+#include <linux/uaccess.h>
+#include <linux/rwsem.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/hardirq.h> /* for in_atomic() */
+#include <asm/current.h>
+#include <asm/page.h>
+static int
+pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
+{
+        unsigned long addr = (unsigned long)_addr;
+        pgd_t *pgd;
+        pmd_t *pmd;
+        pte_t *pte;
+        spinlock_t *ptl;
+        pgd = pgd_offset(current->mm, addr);
+        if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd)))
+                return 0;
+        pmd = pmd_offset(pgd, addr);
+        if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd)))
+                return 0;
+        pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl);
+        if (unlikely(!pte_present(*pte) || !pte_young(*pte) ||
+            !pte_write(*pte) || !pte_dirty(*pte))) {
+                pte_unmap_unlock(pte, ptl);
+                return 0;
+        }
+        *ptep = pte;
+        *ptlp = ptl;
+        return 1;
+}
+static unsigned long noinline
+__copy_to_user_memcpy(void __user *to, const void *from, unsigned long n)
+{
+        int atomic;
+        if (unlikely(segment_eq(get_fs(), KERNEL_DS))) {
+                memcpy((void *)to, from, n);
+                return 0;
+        }
+        /* the mmap semaphore is taken only if not in an atomic context */
+        atomic = in_atomic();
+        if (!atomic)
+                down_read(&current->mm->mmap_sem);
+        while (n) {
+                pte_t *pte;
+                spinlock_t *ptl;
+                int tocopy;
+                while (!pin_page_for_write(to, &pte, &ptl)) {
+                        if (!atomic)
+                                up_read(&current->mm->mmap_sem);
+                        if (__put_user(0, (char __user *)to))
+                                goto out;
+                        if (!atomic)
+                                down_read(&current->mm->mmap_sem);
+                }
+                tocopy = (~(unsigned long)to & ~PAGE_MASK) + 1;
+                if (tocopy > n)
+                        tocopy = n;
+                memcpy((void *)to, from, tocopy);
+                to += tocopy;
+                from += tocopy;
+                n -= tocopy;
+                pte_unmap_unlock(pte, ptl);
+        }
+        if (!atomic)
+                up_read(&current->mm->mmap_sem);
+out:
+        return n;
+}
+unsigned long
+__copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        /*
+         * This test is stubbed out of the main function above to keep
+         * the overhead for small copies low by avoiding a large
+         * register dump on the stack just to reload them right away.
+         * With frame pointer disabled, tail call optimization kicks in
+         * as well making this test almost invisible.
+         */
+        if (n < 64)
+                return __copy_to_user_std(to, from, n);
+        return __copy_to_user_memcpy(to, from, n);
+}
+        
+static unsigned long noinline
+__clear_user_memset(void __user *addr, unsigned long n)
+{
+        if (unlikely(segment_eq(get_fs(), KERNEL_DS))) {
+                memset((void *)addr, 0, n);
+                return 0;
+        }
+        down_read(&current->mm->mmap_sem);
+        while (n) {
+                pte_t *pte;
+                spinlock_t *ptl;
+                int tocopy;
+                while (!pin_page_for_write(addr, &pte, &ptl)) {
+                        up_read(&current->mm->mmap_sem);
+                        if (__put_user(0, (char __user *)addr))
+                                goto out;
+                        down_read(&current->mm->mmap_sem);
+                }
+                tocopy = (~(unsigned long)addr & ~PAGE_MASK) + 1;
+                if (tocopy > n)
+                        tocopy = n;
+                memset((void *)addr, 0, tocopy);
+                addr += tocopy;
+                n -= tocopy;
+                pte_unmap_unlock(pte, ptl);
+        }
+        up_read(&current->mm->mmap_sem);
+out:
+        return n;
+}
+unsigned long __clear_user(void __user *addr, unsigned long n)
+{
+        /* See rational for this in __copy_to_user() above. */
+        if (n < 64)
+                return __clear_user_std(addr, n);
+        return __clear_user_memset(addr, n);
+}
+#if 0
+/*
+ * This code is disabled by default, but kept around in case the chosen
+ * thresholds need to be revalidated.  Some overhead (small but still)
+ * would be implied by a runtime determined variable threshold, and
+ * so far the measurement on concerned targets didn't show a worthwhile
+ * variation.
+ *
+ * Note that a fairly precise sched_clock() implementation is needed
+ * for results to make some sense.
+ */
+#include <linux/vmalloc.h>
+static int __init test_size_treshold(void)
+{
+        struct page *src_page, *dst_page;
+        void *user_ptr, *kernel_ptr;
+        unsigned long long t0, t1, t2;
+        int size, ret;
+        ret = -ENOMEM;
+        src_page = alloc_page(GFP_KERNEL);
+        if (!src_page)
+                goto no_src;
+        dst_page = alloc_page(GFP_KERNEL);
+        if (!dst_page)
+                goto no_dst;
+        kernel_ptr = page_address(src_page);
+        user_ptr = vmap(&dst_page, 1, VM_IOREMAP, __pgprot(__P010));
+        if (!user_ptr)
+                goto no_vmap;
+        /* warm up the src page dcache */
+        ret = __copy_to_user_memcpy(user_ptr, kernel_ptr, PAGE_SIZE);
+        for (size = PAGE_SIZE; size >= 4; size /= 2) {
+                t0 = sched_clock();
+                ret |= __copy_to_user_memcpy(user_ptr, kernel_ptr, size);
+                t1 = sched_clock();
+                ret |= __copy_to_user_std(user_ptr, kernel_ptr, size);
+                t2 = sched_clock();
+                printk("copy_to_user: %d %llu %llu\n", size, t1 - t0, t2 - t1);
+        }
+        for (size = PAGE_SIZE; size >= 4; size /= 2) {
+                t0 = sched_clock();
+                ret |= __clear_user_memset(user_ptr, size);
+                t1 = sched_clock();
+                ret |= __clear_user_std(user_ptr, size);
+                t2 = sched_clock();
+                printk("clear_user: %d %llu %llu\n", size, t1 - t0, t2 - t1);
+        }
+        if (ret)
+                ret = -EFAULT;
+        vunmap(user_ptr);
+no_vmap:
+        put_page(dst_page);
+no_dst:
+        put_page(src_page);
+no_src:
+        return ret;
+}
+subsys_initcall(test_size_treshold);
+#endif
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index e263fda3e2d1..970fd6b6753e 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -156,6 +156,8 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = {
 * MCI (SD/MMC)
 */
 static struct at91_mmc_data __initdata afeb9260_mmc_data = {
+        .det_pin        = AT91_PIN_PC9,
+        .wp_pin         = AT91_PIN_PC4,
        .slot_b         = 1,
        .wire4          = 1,
 };
@@ -164,6 +166,8 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = {
 static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        }, {
                I2C_BOARD_INFO("fm3130", 0x68),
        }, {
                I2C_BOARD_INFO("24c64", 0x50),
@@ -196,6 +200,8 @@ static void __init afeb9260_board_init(void)
        /* I2C */
        at91_add_device_i2c(afeb9260_i2c_devices,
                        ARRAY_SIZE(afeb9260_i2c_devices));
+        /* Audio */
+        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
 }
 MACHINE_START(AFEB9260, "Custom afeb9260 board")
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 438efbb17482..cc270beadd5d 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -218,6 +218,13 @@ static struct gpio_led ek_leds[] = {
        }
 };
+static struct i2c_board_info __initdata ek_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("24c512", 0x50),
+        },
+};
 static void __init ek_board_init(void)
 {
        /* Serial */
@@ -235,7 +242,7 @@ static void __init ek_board_init(void)
        /* MMC */
        at91_add_device_mmc(0, &ek_mmc_data);
        /* I2C */
-        at91_add_device_i2c(NULL, 0);
+        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
        /* LEDs */
        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
        /* PCK0 provides MCLK to the WM8731 */
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index e4345106ee57..bac578fe0d3d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -43,6 +43,25 @@
 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
+/*
+ * Chips have some kind of clocks : group them by functionality
+ */
+#define cpu_has_utmi()          (  cpu_is_at91cap9() \
+                                || cpu_is_at91sam9rl())
+#define cpu_has_800M_plla()     (cpu_is_at91sam9g20())
+#define cpu_has_pllb()          (!cpu_is_at91sam9rl())
+#define cpu_has_upll()          (0)
+/* USB host HS & FS */
+#define cpu_has_uhp()           (!cpu_is_at91sam9rl())
+/* USB device FS only */
+#define cpu_has_udpfs()         (!cpu_is_at91sam9rl())
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -140,7 +159,7 @@ static struct clk utmi_clk = {
 };
 static struct clk uhpck = {
        .name           = "uhpck",
-        .parent         = &pllb,
+        /*.parent               = ... we choose parent at runtime */
        .mode           = pmc_sys_mode,
 };
@@ -173,7 +192,11 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
                case AT91_PMC_CSS_PLLA:
                        return &plla;
                case AT91_PMC_CSS_PLLB:
-                        return &pllb;
+                        if (cpu_has_upll())
+                                /* CSS_PLLB == CSS_UPLL */
+                                return &utmi_clk;
+                        else if (cpu_has_pllb())
+                                return &pllb;
        }
        return NULL;
@@ -322,7 +345,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
                        u32     pckr;
                        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
-                        pckr &= AT91_PMC_CSS_PLLB;      /* clock selection */
+                        pckr &= AT91_PMC_CSS;   /* clock selection */
                        pckr |= prescale << 2;
                        at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
                        clk->rate_hz = actual;
@@ -361,7 +384,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 }
 EXPORT_SYMBOL(clk_set_parent);
-/* establish PCK0..PCK3 parentage and rate */
+/* establish PCK0..PCKN parentage and rate */
 static void __init init_programmable_clock(struct clk *clk)
 {
        struct clk      *parent;
@@ -389,11 +412,13 @@ static int at91_clk_show(struct seq_file *s, void *unused)
        seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
        seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
        seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
-        if (!cpu_is_at91sam9rl())
+        if (cpu_has_pllb())
                seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
-        if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
+        if (cpu_has_utmi())
                seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
        seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
+        if (cpu_has_upll())
+                seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
        seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
        seq_printf(s, "\n");
@@ -554,16 +579,60 @@ static struct clk *const standard_pmc_clocks[] __initdata = {
        &clk32k,
        &main_clk,
        &plla,
-        &pllb,
-        /* PLLB children (USB) */
-        &udpck,
-        &uhpck,
        /* MCK */
        &mck
 };
+/* PLLB generated USB full speed clock init */
+static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
+{
+        /*
+         * USB clock init:  choose 48 MHz PLLB value,
+         * disable 48MHz clock during usb peripheral suspend.
+         *
+         * REVISIT:  assumes MCK doesn't derive from PLLB!
+         */
+        uhpck.parent = &pllb;
+        at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+        pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+        if (cpu_is_at91rm9200()) {
+                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
+                udpck.pmc_mask = AT91RM9200_PMC_UDP;
+                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
+                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
+                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
+        } else if (cpu_is_at91cap9()) {
+                uhpck.pmc_mask = AT91CAP9_PMC_UHP;
+        }
+        at91_sys_write(AT91_CKGR_PLLBR, 0);
+        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+}
+/* UPLL generated USB full speed clock init */
+static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
+{
+        /*
+         * USB clock init: choose 480 MHz from UPLL,
+         */
+        unsigned int usbr = AT91_PMC_USBS_UPLL;
+        /* Setup divider by 10 to reach 48 MHz */
+        usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
+        at91_sys_write(AT91_PMC_USB, usbr);
+        /* Now set uhpck values */
+        uhpck.parent = &utmi_clk;
+        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
+        uhpck.rate_hz = utmi_clk.parent->rate_hz;
+        uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+}
 int __init at91_clock_init(unsigned long main_clock)
 {
        unsigned tmp, freq, mckr;
@@ -585,43 +654,37 @@ int __init at91_clock_init(unsigned long main_clock)
        /* report if PLLA is more than mildly overclocked */
        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-        if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
+        if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000)
-           || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
+           || (cpu_has_800M_plla() && plla.rate_hz > 800000000))
                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-        /*
-         * USB clock init:  choose 48 MHz PLLB value,
+        if (cpu_has_upll() && !cpu_has_pllb()) {
-         * disable 48MHz clock during usb peripheral suspend.
+                /* setup UTMI clock as the fourth primary clock
-         *
+                 * (instead of pllb) */
-         * REVISIT:  assumes MCK doesn't derive from PLLB!
+                utmi_clk.type |= CLK_TYPE_PRIMARY;
-         */
+                utmi_clk.id = 3;
-        at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
-        pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-        if (cpu_is_at91rm9200()) {
-                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
-                udpck.pmc_mask = AT91RM9200_PMC_UDP;
-                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
-                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-        } else if (cpu_is_at91cap9()) {
-                uhpck.pmc_mask = AT91CAP9_PMC_UHP;
        }
-        at91_sys_write(AT91_CKGR_PLLBR, 0);
-        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
        /*
         * USB HS clock init
         */
-        if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
+        if (cpu_has_utmi())
                /*
                 * multiplier is hard-wired to 40
                 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                 */
                utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
-        }
+        /*
+         * USB FS clock init
+         */
+        if (cpu_has_pllb())
+                at91_pllb_usbfs_clock_init(main_clock);
+        if (cpu_has_upll())
+                /* assumes that we choose UPLL for USB and not PLLA */
+                at91_upll_usbfs_clock_init(main_clock);
        /*
         * MCK and CPU derive from one of those primary clocks.
@@ -631,21 +694,31 @@ int __init at91_clock_init(unsigned long main_clock)
        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
        freq = mck.parent->rate_hz;
        freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
-        if (cpu_is_at91rm9200())
+        if (cpu_is_at91rm9200()) {
                mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
-        else if (cpu_is_at91sam9g20()) {
+        } else if (cpu_is_at91sam9g20()) {
                mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
                        freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
                if (mckr & AT91_PMC_PDIV)
                        freq /= 2;              /* processor clock division */
-        } else
+        } else {
                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+        }
        /* Register the PMC's standard clocks */
        for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
                list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
-        if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
+        if (cpu_has_pllb())
+                list_add_tail(&pllb.node, &clocks);
+        if (cpu_has_uhp())
+                list_add_tail(&uhpck.node, &clocks);
+        if (cpu_has_udpfs())
+                list_add_tail(&udpck.node, &clocks);
+        if (cpu_has_utmi())
                list_add_tail(&utmi_clk.node, &clocks);
        /* MCK and CPU clock are "always on" */
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 9561e33b8a9a..64589eaaaee8 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -23,7 +23,7 @@
 #define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
 #define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define         AT91CAP9_PMC_DDR        (1 <<  2)               /* DDR Clock [AT91CAP9 revC only] */
+#define         AT91CAP9_PMC_DDR        (1 <<  2)               /* DDR Clock [CAP9 revC & some SAM9 only] */
 #define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
 #define         AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
@@ -39,11 +39,11 @@
 #define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
 #define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
-#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
+#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [some SAM9, CAP9] */
 #define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
 #define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
 #define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
-#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI PLL Start-up Time */
+#define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI BIAS Start-up Time */
 #define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
@@ -72,6 +72,7 @@
 #define                 AT91_PMC_CSS_MAIN               (1 << 0)
 #define                 AT91_PMC_CSS_PLLA               (2 << 0)
 #define                 AT91_PMC_CSS_PLLB               (3 << 0)
+#define                 AT91_PMC_CSS_UPLL               (3 << 0)        /* [some SAM9 only] */
 #define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
 #define                 AT91_PMC_PRES_1                 (0 << 2)
 #define                 AT91_PMC_PRES_2                 (1 << 2)
@@ -88,12 +89,25 @@
 #define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
 #define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
 #define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
-#define                 AT91SAM9_PMC_MDIV_6             (3 << 8)
+#define                 AT91SAM9_PMC_MDIV_6             (3 << 8)        /* [some SAM9 only] */
+#define                 AT91SAM9_PMC_MDIV_3             (3 << 8)        /* [some SAM9 only] */
 #define         AT91_PMC_PDIV           (1 << 12)               /* Processor Clock Division [some SAM9 only] */
 #define                 AT91_PMC_PDIV_1                 (0 << 12)
 #define                 AT91_PMC_PDIV_2                 (1 << 12)
+#define         AT91_PMC_PLLADIV2       (1 << 12)               /* PLLA divisor by 2 [some SAM9 only] */
+#define                 AT91_PMC_PLLADIV2_OFF           (0 << 12)
+#define                 AT91_PMC_PLLADIV2_ON            (1 << 12)
-#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
+#define AT91_PMC_USB            (AT91_PMC + 0x38)       /* USB Clock Register [some SAM9 only] */
+#define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
+#define                 AT91_PMC_USBS_PLLA              (0 << 0)
+#define                 AT91_PMC_USBS_UPLL              (1 << 0)
+#define         AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
+#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-N Registers */
+#define         AT91_PMC_CSSMCK         (0x1 <<  8)             /* CSS or Master Clock Selection */
+#define                 AT91_PMC_CSSMCK_CSS             (0 << 8)
+#define                 AT91_PMC_CSSMCK_MCK             (1 << 8)
 #define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
 #define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
@@ -102,7 +116,7 @@
 #define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
 #define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [AT91CAP9 only] */
+#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9, AT91CAP9 only] */
 #define         AT91_PMC_OSCSEL         (1 <<  7)               /* Slow Clock Oscillator [AT91CAP9 revC only] */
 #define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a9c78bc72b84..be747f5c6cd8 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -1,11 +1,26 @@
 if ARCH_DAVINCI
+config AINTC
+        bool
+config CP_INTC
+        bool
 menu "TI DaVinci Implementations"
 comment "DaVinci Core Type"
 config ARCH_DAVINCI_DM644x
        bool "DaVinci 644x based system"
+        select AINTC
+config ARCH_DAVINCI_DM355
+        bool "DaVinci 355 based system"
+        select AINTC
+config ARCH_DAVINCI_DM646x
+        bool "DaVinci 646x based system"
+        select AINTC
 comment "DaVinci Board Type"
@@ -17,6 +32,34 @@ config MACH_DAVINCI_EVM
          Configure this option to specify the whether the board used
          for development is a DM644x EVM
+config MACH_SFFSDR
+        bool "Lyrtech SFFSDR"
+        depends on ARCH_DAVINCI_DM644x
+        help
+          Say Y here to select the Lyrtech Small Form Factor
+          Software Defined Radio (SFFSDR) board.
+config MACH_DAVINCI_DM355_EVM
+        bool "TI DM355 EVM"
+        depends on ARCH_DAVINCI_DM355
+        help
+          Configure this option to specify the whether the board used
+          for development is a DM355 EVM
+config MACH_DM355_LEOPARD
+        bool "DM355 Leopard board"
+        depends on ARCH_DAVINCI_DM355
+        help
+          Configure this option to specify the whether the board used
+          for development is a DM355 Leopard board.
+config MACH_DAVINCI_DM6467_EVM
+        bool "TI DM6467 EVM"
+        depends on ARCH_DAVINCI_DM646x
+        help
+          Configure this option to specify the whether the board used
+          for development is a DM6467 EVM
 config DAVINCI_MUX
        bool "DAVINCI multiplexing support"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 1674661942f3..059ab78084ba 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -4,13 +4,22 @@
 #
 # Common objects
-obj-y                   := time.o irq.o clock.o serial.o io.o id.o psc.o \
+obj-y                   := time.o clock.o serial.o io.o psc.o \
-                           gpio.o devices.o dma.o usb.o
+                           gpio.o devices.o dma.o usb.o common.o sram.o
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
 # Chip specific
 obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o
+obj-$(CONFIG_AINTC)                     += irq.o
+obj-$(CONFIG_CP_INTC)                   += cp_intc.o
 # Board specific
 obj-$(CONFIG_MACH_DAVINCI_EVM)          += board-dm644x-evm.o
+obj-$(CONFIG_MACH_SFFSDR)               += board-sffsdr.o
+obj-$(CONFIG_MACH_DAVINCI_DM355_EVM)    += board-dm355-evm.o
+obj-$(CONFIG_MACH_DM355_LEOPARD)        += board-dm355-leopard.o
+obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)   += board-dm646x-evm.o
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
new file mode 100644
index 000000000000..5ac2f565d860
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -0,0 +1,298 @@
+/*
+ * TI DaVinci EVM board support
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <mach/hardware.h>
+#include <mach/dm355.h>
+#include <mach/psc.h>
+#include <mach/common.h>
+#include <mach/i2c.h>
+#include <mach/serial.h>
+#include <mach/nand.h>
+#include <mach/mmc.h>
+#include <mach/common.h>
+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x01e10000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x02000000
+/* NOTE:  this is geared for the standard config, with a socketed
+ * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
+ * swap chips, maybe with a different block size, partitioning may
+ * need to be changed.
+ */
+#define NAND_BLOCK_SIZE         SZ_128K
+static struct mtd_partition davinci_nand_partitions[] = {
+        {
+                /* UBL (a few copies) plus U-Boot */
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = 15 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        }, {
+                /* U-Boot environment */
+                .name           = "params",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 1 * NAND_BLOCK_SIZE,
+                .mask_flags     = 0,
+        }, {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_4M,
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem1",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_512M,
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem2",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        }
+        /* two blocks with bad block table (and mirror) at the end */
+};
+static struct davinci_nand_pdata davinci_nand_data = {
+        .mask_chipsel           = BIT(14),
+        .parts                  = davinci_nand_partitions,
+        .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
+        .ecc_mode               = NAND_ECC_HW_SYNDROME,
+        .options                = NAND_USE_FLASH_BBT,
+};
+static struct resource davinci_nand_resources[] = {
+        {
+                .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device davinci_nand_device = {
+        .name                   = "davinci_nand",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(davinci_nand_resources),
+        .resource               = davinci_nand_resources,
+        .dev                    = {
+                .platform_data  = &davinci_nand_data,
+        },
+};
+static struct davinci_i2c_platform_data i2c_pdata = {
+        .bus_freq       = 400   /* kHz */,
+        .bus_delay      = 0     /* usec */,
+};
+static int dm355evm_mmc_gpios = -EINVAL;
+static void dm355evm_mmcsd_gpios(unsigned gpio)
+{
+        gpio_request(gpio + 0, "mmc0_ro");
+        gpio_request(gpio + 1, "mmc0_cd");
+        gpio_request(gpio + 2, "mmc1_ro");
+        gpio_request(gpio + 3, "mmc1_cd");
+        /* we "know" these are input-only so we don't
+         * need to call gpio_direction_input()
+         */
+        dm355evm_mmc_gpios = gpio;
+}
+static struct i2c_board_info dm355evm_i2c_info[] = {
+        { I2C_BOARD_INFO("dm355evm_msp", 0x25),
+                .platform_data = dm355evm_mmcsd_gpios,
+                /* plus irq */ },
+        /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
+        /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
+};
+static void __init evm_init_i2c(void)
+{
+        davinci_init_i2c(&i2c_pdata);
+        gpio_request(5, "dm355evm_msp");
+        gpio_direction_input(5);
+        dm355evm_i2c_info[0].irq = gpio_to_irq(5);
+        i2c_register_board_info(1, dm355evm_i2c_info,
+                        ARRAY_SIZE(dm355evm_i2c_info));
+}
+static struct resource dm355evm_dm9000_rsrc[] = {
+        {
+                /* addr */
+                .start  = 0x04014000,
+                .end    = 0x04014001,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                /* data */
+                .start  = 0x04014002,
+                .end    = 0x04014003,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ
+                        | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
+        },
+};
+static struct platform_device dm355evm_dm9000 = {
+        .name           = "dm9000",
+        .id             = -1,
+        .resource       = dm355evm_dm9000_rsrc,
+        .num_resources  = ARRAY_SIZE(dm355evm_dm9000_rsrc),
+};
+static struct platform_device *davinci_evm_devices[] __initdata = {
+        &dm355evm_dm9000,
+        &davinci_nand_device,
+};
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
+};
+static void __init dm355_evm_map_io(void)
+{
+        dm355_init();
+}
+static int dm355evm_mmc_get_cd(int module)
+{
+        if (!gpio_is_valid(dm355evm_mmc_gpios))
+                return -ENXIO;
+        /* low == card present */
+        return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1);
+}
+static int dm355evm_mmc_get_ro(int module)
+{
+        if (!gpio_is_valid(dm355evm_mmc_gpios))
+                return -ENXIO;
+        /* high == card's write protect switch active */
+        return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0);
+}
+static struct davinci_mmc_config dm355evm_mmc_config = {
+        .get_cd         = dm355evm_mmc_get_cd,
+        .get_ro         = dm355evm_mmc_get_ro,
+        .wires          = 4,
+        .max_freq       = 50000000,
+        .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+        .version        = MMC_CTLR_VERSION_1,
+};
+/* Don't connect anything to J10 unless you're only using USB host
+ * mode *and* have to do so with some kind of gender-bender.  If
+ * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
+ * the ID pin won't need any help.
+ */
+#ifdef CONFIG_USB_MUSB_PERIPHERAL
+#define USB_ID_VALUE    0       /* ID pulled high; *should* float */
+#else
+#define USB_ID_VALUE    1       /* ID pulled low */
+#endif
+static struct spi_eeprom at25640a = {
+        .byte_len       = SZ_64K / 8,
+        .name           = "at25640a",
+        .page_size      = 32,
+        .flags          = EE_ADDR2,
+};
+static struct spi_board_info dm355_evm_spi_info[] __initconst = {
+        {
+                .modalias       = "at25",
+                .platform_data  = &at25640a,
+                .max_speed_hz   = 10 * 1000 * 1000,     /* at 3v3 */
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+        },
+};
+static __init void dm355_evm_init(void)
+{
+        struct clk *aemif;
+        gpio_request(1, "dm9000");
+        gpio_direction_input(1);
+        dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
+        aemif = clk_get(&dm355evm_dm9000.dev, "aemif");
+        if (IS_ERR(aemif))
+                WARN("%s: unable to get AEMIF clock\n", __func__);
+        else
+                clk_enable(aemif);
+        platform_add_devices(davinci_evm_devices,
+                             ARRAY_SIZE(davinci_evm_devices));
+        evm_init_i2c();
+        davinci_serial_init(&uart_config);
+        /* NOTE:  NAND flash timings set by the UBL are slower than
+         * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
+         * but could be 0x0400008c for about 25% faster page reads.
+         */
+        gpio_request(2, "usb_id_toggle");
+        gpio_direction_output(2, USB_ID_VALUE);
+        /* irlml6401 switches over 1A in under 8 msec */
+        setup_usb(500, 8);
+        davinci_setup_mmc(0, &dm355evm_mmc_config);
+        davinci_setup_mmc(1, &dm355evm_mmc_config);
+        dm355_init_spi0(BIT(0), dm355_evm_spi_info,
+                        ARRAY_SIZE(dm355_evm_spi_info));
+}
+static __init void dm355_evm_irq_init(void)
+{
+        davinci_irq_init();
+}
+MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
+        .phys_io      = IO_PHYS,
+        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params  = (0x80000100),
+        .map_io       = dm355_evm_map_io,
+        .init_irq     = dm355_evm_irq_init,
+        .timer        = &davinci_timer,
+        .init_machine = dm355_evm_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
new file mode 100644
index 000000000000..28c9008df4f4
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -0,0 +1,296 @@
+/*
+ * DM355 leopard board support
+ *
+ * Based on board-dm355-evm.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <mach/hardware.h>
+#include <mach/dm355.h>
+#include <mach/psc.h>
+#include <mach/common.h>
+#include <mach/i2c.h>
+#include <mach/serial.h>
+#include <mach/nand.h>
+#include <mach/mmc.h>
+#include <mach/common.h>
+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x01e10000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x02000000
+/* NOTE:  this is geared for the standard config, with a socketed
+ * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
+ * swap chips, maybe with a different block size, partitioning may
+ * need to be changed.
+ */
+#define NAND_BLOCK_SIZE         SZ_128K
+static struct mtd_partition davinci_nand_partitions[] = {
+        {
+                /* UBL (a few copies) plus U-Boot */
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = 15 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE, /* force read-only */
+        }, {
+                /* U-Boot environment */
+                .name           = "params",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 1 * NAND_BLOCK_SIZE,
+                .mask_flags     = 0,
+        }, {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_4M,
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem1",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_512M,
+                .mask_flags     = 0,
+        }, {
+                .name           = "filesystem2",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        }
+        /* two blocks with bad block table (and mirror) at the end */
+};
+static struct davinci_nand_pdata davinci_nand_data = {
+        .mask_chipsel           = BIT(14),
+        .parts                  = davinci_nand_partitions,
+        .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
+        .ecc_mode               = NAND_ECC_HW_SYNDROME,
+        .options                = NAND_USE_FLASH_BBT,
+};
+static struct resource davinci_nand_resources[] = {
+        {
+                .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device davinci_nand_device = {
+        .name                   = "davinci_nand",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(davinci_nand_resources),
+        .resource               = davinci_nand_resources,
+        .dev                    = {
+                .platform_data  = &davinci_nand_data,
+        },
+};
+static struct davinci_i2c_platform_data i2c_pdata = {
+        .bus_freq       = 400   /* kHz */,
+        .bus_delay      = 0     /* usec */,
+};
+static int leopard_mmc_gpio = -EINVAL;
+static void dm355leopard_mmcsd_gpios(unsigned gpio)
+{
+        gpio_request(gpio + 0, "mmc0_ro");
+        gpio_request(gpio + 1, "mmc0_cd");
+        gpio_request(gpio + 2, "mmc1_ro");
+        gpio_request(gpio + 3, "mmc1_cd");
+        /* we "know" these are input-only so we don't
+         * need to call gpio_direction_input()
+         */
+        leopard_mmc_gpio = gpio;
+}
+static struct i2c_board_info dm355leopard_i2c_info[] = {
+        { I2C_BOARD_INFO("dm355leopard_msp", 0x25),
+                .platform_data = dm355leopard_mmcsd_gpios,
+                /* plus irq */ },
+        /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */
+        /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */
+};
+static void __init leopard_init_i2c(void)
+{
+        davinci_init_i2c(&i2c_pdata);
+        gpio_request(5, "dm355leopard_msp");
+        gpio_direction_input(5);
+        dm355leopard_i2c_info[0].irq = gpio_to_irq(5);
+        i2c_register_board_info(1, dm355leopard_i2c_info,
+                        ARRAY_SIZE(dm355leopard_i2c_info));
+}
+static struct resource dm355leopard_dm9000_rsrc[] = {
+        {
+                /* addr */
+                .start  = 0x04000000,
+                .end    = 0x04000001,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                /* data */
+                .start  = 0x04000016,
+                .end    = 0x04000017,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ
+                        | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */,
+        },
+};
+static struct platform_device dm355leopard_dm9000 = {
+        .name           = "dm9000",
+        .id             = -1,
+        .resource       = dm355leopard_dm9000_rsrc,
+        .num_resources  = ARRAY_SIZE(dm355leopard_dm9000_rsrc),
+};
+static struct platform_device *davinci_leopard_devices[] __initdata = {
+        &dm355leopard_dm9000,
+        &davinci_nand_device,
+};
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
+};
+static void __init dm355_leopard_map_io(void)
+{
+        dm355_init();
+}
+static int dm355leopard_mmc_get_cd(int module)
+{
+        if (!gpio_is_valid(leopard_mmc_gpio))
+                return -ENXIO;
+        /* low == card present */
+        return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1);
+}
+static int dm355leopard_mmc_get_ro(int module)
+{
+        if (!gpio_is_valid(leopard_mmc_gpio))
+                return -ENXIO;
+        /* high == card's write protect switch active */
+        return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0);
+}
+static struct davinci_mmc_config dm355leopard_mmc_config = {
+        .get_cd         = dm355leopard_mmc_get_cd,
+        .get_ro         = dm355leopard_mmc_get_ro,
+        .wires          = 4,
+        .max_freq       = 50000000,
+        .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+};
+/* Don't connect anything to J10 unless you're only using USB host
+ * mode *and* have to do so with some kind of gender-bender.  If
+ * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
+ * the ID pin won't need any help.
+ */
+#ifdef CONFIG_USB_MUSB_PERIPHERAL
+#define USB_ID_VALUE    0       /* ID pulled high; *should* float */
+#else
+#define USB_ID_VALUE    1       /* ID pulled low */
+#endif
+static struct spi_eeprom at25640a = {
+        .byte_len       = SZ_64K / 8,
+        .name           = "at25640a",
+        .page_size      = 32,
+        .flags          = EE_ADDR2,
+};
+static struct spi_board_info dm355_leopard_spi_info[] __initconst = {
+        {
+                .modalias       = "at25",
+                .platform_data  = &at25640a,
+                .max_speed_hz   = 10 * 1000 * 1000,     /* at 3v3 */
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+        },
+};
+static __init void dm355_leopard_init(void)
+{
+        struct clk *aemif;
+        gpio_request(9, "dm9000");
+        gpio_direction_input(9);
+        dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9);
+        aemif = clk_get(&dm355leopard_dm9000.dev, "aemif");
+        if (IS_ERR(aemif))
+                WARN("%s: unable to get AEMIF clock\n", __func__);
+        else
+                clk_enable(aemif);
+        platform_add_devices(davinci_leopard_devices,
+                             ARRAY_SIZE(davinci_leopard_devices));
+        leopard_init_i2c();
+        davinci_serial_init(&uart_config);
+        /* NOTE:  NAND flash timings set by the UBL are slower than
+         * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
+         * but could be 0x0400008c for about 25% faster page reads.
+         */
+        gpio_request(2, "usb_id_toggle");
+        gpio_direction_output(2, USB_ID_VALUE);
+        /* irlml6401 switches over 1A in under 8 msec */
+        setup_usb(500, 8);
+        davinci_setup_mmc(0, &dm355leopard_mmc_config);
+        davinci_setup_mmc(1, &dm355leopard_mmc_config);
+        dm355_init_spi0(BIT(0), dm355_leopard_spi_info,
+                        ARRAY_SIZE(dm355_leopard_spi_info));
+}
+static __init void dm355_leopard_irq_init(void)
+{
+        davinci_irq_init();
+}
+MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
+        .phys_io      = IO_PHYS,
+        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params  = (0x80000100),
+        .map_io       = dm355_leopard_map_io,
+        .init_irq     = dm355_leopard_irq_init,
+        .timer        = &davinci_timer,
+        .init_machine = dm355_leopard_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index b2e7f9c63bc5..d9d40450bdc5 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -16,12 +16,11 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <linux/memory.h>
-#include <linux/etherdevice.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pcf857x.h>
 #include <linux/i2c/at24.h>
+#include <linux/etherdevice.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@@ -44,6 +43,9 @@
 #include <mach/mux.h>
 #include <mach/psc.h>
 #include <mach/nand.h>
+#include <mach/mmc.h>
+#include <mach/emac.h>
+#include <mach/common.h>
 #define DM644X_EVM_PHY_MASK             (0x2)
 #define DM644X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
@@ -436,45 +438,15 @@ static struct pcf857x_platform_data pcf_data_u35 = {
 *  - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
 *  - ... newer boards may have more
 */
-static struct memory_accessor *at24_mem_acc;
-static void at24_setup(struct memory_accessor *mem_acc, void *context)
-{
-        DECLARE_MAC_BUF(mac_str);
-        char mac_addr[6];
-        at24_mem_acc = mem_acc;
-        /* Read MAC addr from EEPROM */
-        if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) {
-                printk(KERN_INFO "Read MAC addr from EEPROM: %s\n",
-                       print_mac(mac_str, mac_addr));
-        }
-}
 static struct at24_platform_data eeprom_info = {
        .byte_len       = (256*1024) / 8,
        .page_size      = 64,
        .flags          = AT24_FLAG_ADDR16,
-        .setup          = at24_setup,
+        .setup          = davinci_get_mac_addr,
+        .context        = (void *)0x7f00,
 };
-int dm6446evm_eeprom_read(void *buf, off_t off, size_t count)
-{
-        if (at24_mem_acc)
-                return at24_mem_acc->read(at24_mem_acc, buf, off, count);
-        return -ENODEV;
-}
-EXPORT_SYMBOL(dm6446evm_eeprom_read);
-int dm6446evm_eeprom_write(void *buf, off_t off, size_t count)
-{
-        if (at24_mem_acc)
-                return at24_mem_acc->write(at24_mem_acc, buf, off, count);
-        return -ENODEV;
-}
-EXPORT_SYMBOL(dm6446evm_eeprom_write);
 /*
 * MSP430 supports RTC, card detection, input from IR remote, and
 * a bit more.  It triggers interrupts on GPIO(7) from pressing
@@ -545,6 +517,27 @@ static int dm6444evm_msp430_get_pins(void)
        return (buf[3] << 8) | buf[2];
 }
+static int dm6444evm_mmc_get_cd(int module)
+{
+        int status = dm6444evm_msp430_get_pins();
+        return (status < 0) ? status : !(status & BIT(1));
+}
+static int dm6444evm_mmc_get_ro(int module)
+{
+        int status = dm6444evm_msp430_get_pins();
+        return (status < 0) ? status : status & BIT(6 + 8);
+}
+static struct davinci_mmc_config dm6446evm_mmc_config = {
+        .get_cd         = dm6444evm_mmc_get_cd,
+        .get_ro         = dm6444evm_mmc_get_ro,
+        .wires          = 4,
+        .version        = MMC_CTLR_VERSION_1
+};
 static struct i2c_board_info __initdata i2c_info[] =  {
        {
                I2C_BOARD_INFO("dm6446evm_msp", 0x23),
@@ -598,7 +591,6 @@ static struct davinci_uart_config uart_config __initdata = {
 static void __init
 davinci_evm_map_io(void)
 {
-        davinci_map_common_io();
        dm644x_init();
 }
@@ -639,6 +631,7 @@ static int davinci_phy_fixup(struct phy_device *phydev)
 static __init void davinci_evm_init(void)
 {
        struct clk *aemif_clk;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
        aemif_clk = clk_get(NULL, "aemif");
        clk_enable(aemif_clk);
@@ -671,8 +664,13 @@ static __init void davinci_evm_init(void)
                             ARRAY_SIZE(davinci_evm_devices));
        evm_init_i2c();
+        davinci_setup_mmc(0, &dm6446evm_mmc_config);
        davinci_serial_init(&uart_config);
+        soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
+        soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
        /* Register the fixup for PHY on DaVinci */
        phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
                                        davinci_phy_fixup);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
new file mode 100644
index 000000000000..e17de6352624
--- /dev/null
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -0,0 +1,262 @@
+/*
+ * TI DaVinci DM646X EVM board
+ *
+ * Derived from: arch/arm/mach-davinci/board-evm.c
+ * Copyright (C) 2006 Texas Instruments.
+ *
+ * (C) 2007-2008, MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/major.h>
+#include <linux/root_dev.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/i2c/pcf857x.h>
+#include <linux/etherdevice.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <mach/dm646x.h>
+#include <mach/common.h>
+#include <mach/psc.h>
+#include <mach/serial.h>
+#include <mach/i2c.h>
+#include <mach/mmc.h>
+#include <mach/emac.h>
+#include <mach/common.h>
+#define DM646X_EVM_PHY_MASK             (0x2)
+#define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
+};
+/* LEDS */
+static struct gpio_led evm_leds[] = {
+        { .name = "DS1", .active_low = 1, },
+        { .name = "DS2", .active_low = 1, },
+        { .name = "DS3", .active_low = 1, },
+        { .name = "DS4", .active_low = 1, },
+};
+static __initconst struct gpio_led_platform_data evm_led_data = {
+        .num_leds = ARRAY_SIZE(evm_leds),
+        .leds     = evm_leds,
+};
+static struct platform_device *evm_led_dev;
+static int evm_led_setup(struct i2c_client *client, int gpio,
+                        unsigned int ngpio, void *c)
+{
+        struct gpio_led *leds = evm_leds;
+        int status;
+        while (ngpio--) {
+                leds->gpio = gpio++;
+                leds++;
+        };
+        evm_led_dev = platform_device_alloc("leds-gpio", 0);
+        platform_device_add_data(evm_led_dev, &evm_led_data,
+                                sizeof(evm_led_data));
+        evm_led_dev->dev.parent = &client->dev;
+        status = platform_device_add(evm_led_dev);
+        if (status < 0) {
+                platform_device_put(evm_led_dev);
+                evm_led_dev = NULL;
+        }
+        return status;
+}
+static int evm_led_teardown(struct i2c_client *client, int gpio,
+                                unsigned ngpio, void *c)
+{
+        if (evm_led_dev) {
+                platform_device_unregister(evm_led_dev);
+                evm_led_dev = NULL;
+        }
+        return 0;
+}
+static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
+static int evm_sw_setup(struct i2c_client *client, int gpio,
+                        unsigned ngpio, void *c)
+{
+        int status;
+        int i;
+        char label[10];
+        for (i = 0; i < 4; ++i) {
+                snprintf(label, 10, "user_sw%d", i);
+                status = gpio_request(gpio, label);
+                if (status)
+                        goto out_free;
+                evm_sw_gpio[i] = gpio++;
+                status = gpio_direction_input(evm_sw_gpio[i]);
+                if (status) {
+                        gpio_free(evm_sw_gpio[i]);
+                        evm_sw_gpio[i] = -EINVAL;
+                        goto out_free;
+                }
+                status = gpio_export(evm_sw_gpio[i], 0);
+                if (status) {
+                        gpio_free(evm_sw_gpio[i]);
+                        evm_sw_gpio[i] = -EINVAL;
+                        goto out_free;
+                }
+        }
+        return status;
+out_free:
+        for (i = 0; i < 4; ++i) {
+                if (evm_sw_gpio[i] != -EINVAL) {
+                        gpio_free(evm_sw_gpio[i]);
+                        evm_sw_gpio[i] = -EINVAL;
+                }
+        }
+        return status;
+}
+static int evm_sw_teardown(struct i2c_client *client, int gpio,
+                        unsigned ngpio, void *c)
+{
+        int i;
+        for (i = 0; i < 4; ++i) {
+                if (evm_sw_gpio[i] != -EINVAL) {
+                        gpio_unexport(evm_sw_gpio[i]);
+                        gpio_free(evm_sw_gpio[i]);
+                        evm_sw_gpio[i] = -EINVAL;
+                }
+        }
+        return 0;
+}
+static int evm_pcf_setup(struct i2c_client *client, int gpio,
+                        unsigned int ngpio, void *c)
+{
+        int status;
+        if (ngpio < 8)
+                return -EINVAL;
+        status = evm_sw_setup(client, gpio, 4, c);
+        if (status)
+                return status;
+        return evm_led_setup(client, gpio+4, 4, c);
+}
+static int evm_pcf_teardown(struct i2c_client *client, int gpio,
+                        unsigned int ngpio, void *c)
+{
+        BUG_ON(ngpio < 8);
+        evm_sw_teardown(client, gpio, 4, c);
+        evm_led_teardown(client, gpio+4, 4, c);
+        return 0;
+}
+static struct pcf857x_platform_data pcf_data = {
+        .gpio_base      = DAVINCI_N_GPIO+1,
+        .setup          = evm_pcf_setup,
+        .teardown       = evm_pcf_teardown,
+};
+/* Most of this EEPROM is unused, but U-Boot uses some data:
+ *  - 0x7f00, 6 bytes Ethernet Address
+ *  - ... newer boards may have more
+ */
+static struct at24_platform_data eeprom_info = {
+        .byte_len       = (256*1024) / 8,
+        .page_size      = 64,
+        .flags          = AT24_FLAG_ADDR16,
+        .setup          = davinci_get_mac_addr,
+        .context        = (void *)0x7f00,
+};
+static struct i2c_board_info __initdata i2c_info[] =  {
+        {
+                I2C_BOARD_INFO("24c256", 0x50),
+                .platform_data  = &eeprom_info,
+        },
+        {
+                I2C_BOARD_INFO("pcf8574a", 0x38),
+                .platform_data  = &pcf_data,
+        },
+};
+static struct davinci_i2c_platform_data i2c_pdata = {
+        .bus_freq       = 100 /* kHz */,
+        .bus_delay      = 0 /* usec */,
+};
+static void __init evm_init_i2c(void)
+{
+        davinci_init_i2c(&i2c_pdata);
+        i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
+}
+static void __init davinci_map_io(void)
+{
+        dm646x_init();
+}
+static __init void evm_init(void)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        evm_init_i2c();
+        davinci_serial_init(&uart_config);
+        soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
+        soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
+}
+static __init void davinci_dm646x_evm_irq_init(void)
+{
+        davinci_irq_init();
+}
+MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
+        .phys_io      = IO_PHYS,
+        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params  = (0x80000100),
+        .map_io       = davinci_map_io,
+        .init_irq     = davinci_dm646x_evm_irq_init,
+        .timer        = &davinci_timer,
+        .init_machine = evm_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
new file mode 100644
index 000000000000..748a8e48541e
--- /dev/null
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -0,0 +1,189 @@
+/*
+ * Lyrtech SFFSDR board support.
+ *
+ * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * Based on DV-EVM platform, original copyright follows:
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/etherdevice.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/io.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <mach/dm644x.h>
+#include <mach/common.h>
+#include <mach/i2c.h>
+#include <mach/serial.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+#include <mach/common.h>
+#define SFFSDR_PHY_MASK         (0x2)
+#define SFFSDR_MDIO_FREQUENCY   (2200000) /* PHY bus frequency */
+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
+struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
+        /* U-Boot Environment: Block 0
+         * UBL:                Block 1
+         * U-Boot:             Blocks 6-7 (256 kb)
+         * Integrity Kernel:   Blocks 8-31 (3 Mb)
+         * Integrity Data:     Blocks 100-END
+         */
+        {
+                .name           = "Linux Kernel",
+                .offset         = 32 * SZ_128K,
+                .size           = 16 * SZ_128K, /* 2 Mb */
+                .mask_flags     = MTD_WRITEABLE, /* Force read-only */
+        },
+        {
+                .name           = "Linux ROOT",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 256 * SZ_128K, /* 32 Mb */
+                .mask_flags     = 0, /* R/W */
+        },
+};
+static struct flash_platform_data davinci_sffsdr_nandflash_data = {
+        .parts          = davinci_sffsdr_nandflash_partition,
+        .nr_parts       = ARRAY_SIZE(davinci_sffsdr_nandflash_partition),
+};
+static struct resource davinci_sffsdr_nandflash_resource[] = {
+        {
+                .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device davinci_sffsdr_nandflash_device = {
+        .name           = "davinci_nand", /* Name of driver */
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &davinci_sffsdr_nandflash_data,
+        },
+        .num_resources  = ARRAY_SIZE(davinci_sffsdr_nandflash_resource),
+        .resource       = davinci_sffsdr_nandflash_resource,
+};
+static struct emac_platform_data sffsdr_emac_pdata = {
+        .phy_mask       = SFFSDR_PHY_MASK,
+        .mdio_max_freq  = SFFSDR_MDIO_FREQUENCY,
+};
+static struct at24_platform_data eeprom_info = {
+        .byte_len       = (64*1024) / 8,
+        .page_size      = 32,
+        .flags          = AT24_FLAG_ADDR16,
+};
+static struct i2c_board_info __initdata i2c_info[] =  {
+        {
+                I2C_BOARD_INFO("24lc64", 0x50),
+                .platform_data  = &eeprom_info,
+        },
+        /* Other I2C devices:
+         * MSP430,  addr 0x23 (not used)
+         * PCA9543, addr 0x70 (setup done by U-Boot)
+         * ADS7828, addr 0x48 (ADC for voltage monitoring.)
+         */
+};
+static struct davinci_i2c_platform_data i2c_pdata = {
+        .bus_freq       = 20 /* kHz */,
+        .bus_delay      = 100 /* usec */,
+};
+static void __init sffsdr_init_i2c(void)
+{
+        davinci_init_i2c(&i2c_pdata);
+        i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
+}
+static struct platform_device *davinci_sffsdr_devices[] __initdata = {
+        &davinci_sffsdr_nandflash_device,
+};
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
+};
+static void __init davinci_sffsdr_map_io(void)
+{
+        dm644x_init();
+}
+static __init void davinci_sffsdr_init(void)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        platform_add_devices(davinci_sffsdr_devices,
+                             ARRAY_SIZE(davinci_sffsdr_devices));
+        sffsdr_init_i2c();
+        davinci_serial_init(&uart_config);
+        soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK;
+        soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
+        setup_usb(0, 0); /* We support only peripheral mode. */
+        /* mux VLYNQ pins */
+        davinci_cfg_reg(DM644X_VLYNQEN);
+        davinci_cfg_reg(DM644X_VLYNQWD);
+}
+static __init void davinci_sffsdr_irq_init(void)
+{
+        davinci_irq_init();
+}
+MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
+        /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
+        .phys_io      = IO_PHYS,
+        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params  = (DAVINCI_DDR_BASE + 0x100),
+        .map_io       = davinci_sffsdr_map_io,
+        .init_irq     = davinci_sffsdr_irq_init,
+        .timer        = &davinci_timer,
+        .init_machine = davinci_sffsdr_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index f0baaa15a57e..39bf321d70a2 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -42,7 +42,8 @@ static void __clk_enable(struct clk *clk)
        if (clk->parent)
                __clk_enable(clk->parent);
        if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-                davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
+                davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
+                                clk->lpsc, 1);
 }
 static void __clk_disable(struct clk *clk)
@@ -50,7 +51,8 @@ static void __clk_disable(struct clk *clk)
        if (WARN_ON(clk->usecount == 0))
                return;
        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
-                davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
+                davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
+                                clk->lpsc, 0);
        if (clk->parent)
                __clk_disable(clk->parent);
 }
@@ -164,11 +166,11 @@ static int __init clk_disable_unused(void)
                        continue;
                /* ignore if in Disabled or SwRstDisable states */
-                if (!davinci_psc_is_clk_active(ck->lpsc))
+                if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
                        continue;
                pr_info("Clocks: disable unused %s\n", ck->name);
-                davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
+                davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
        }
        spin_unlock_irq(&clockfw_lock);
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 35736ec202f8..27233cb4a2fb 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -67,6 +67,7 @@ struct clk {
        u8                      usecount;
        u8                      flags;
        u8                      lpsc;
+        u8                      psc_ctlr;
        struct clk              *parent;
        struct pll_data         *pll_data;
        u32                     div_reg;
@@ -93,4 +94,7 @@ struct davinci_clk {
        }
 int davinci_clk_init(struct davinci_clk *clocks);
+extern struct platform_device davinci_wdt_device;
 #endif
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
new file mode 100644
index 000000000000..61ede19c6b54
--- /dev/null
+++ b/arch/arm/mach-davinci/common.c
@@ -0,0 +1,108 @@
+/*
+ * Code commons to all DaVinci SoCs.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/etherdevice.h>
+#include <asm/tlb.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/cputype.h>
+#include <mach/emac.h>
+#include "clock.h"
+struct davinci_soc_info davinci_soc_info;
+EXPORT_SYMBOL(davinci_soc_info);
+void __iomem *davinci_intc_base;
+int davinci_intc_type;
+void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context)
+{
+        char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
+        off_t offset = (off_t)context;
+        /* Read MAC addr from EEPROM */
+        if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN)
+                pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
+}
+static struct davinci_id * __init davinci_get_id(u32 jtag_id)
+{
+        int i;
+        struct davinci_id *dip;
+        u8 variant = (jtag_id & 0xf0000000) >> 28;
+        u16 part_no = (jtag_id & 0x0ffff000) >> 12;
+        for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num;
+                        i++, dip++)
+                /* Don't care about the manufacturer right now */
+                if ((dip->part_no == part_no) && (dip->variant == variant))
+                        return dip;
+        return NULL;
+}
+void __init davinci_common_init(struct davinci_soc_info *soc_info)
+{
+        int ret;
+        struct davinci_id *dip;
+        if (!soc_info) {
+                ret = -EINVAL;
+                goto err;
+        }
+        memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info));
+        if (davinci_soc_info.io_desc && (davinci_soc_info.io_desc_num > 0))
+                iotable_init(davinci_soc_info.io_desc,
+                                davinci_soc_info.io_desc_num);
+        /*
+         * Normally devicemaps_init() would flush caches and tlb after
+         * mdesc->map_io(), but we must also do it here because of the CPU
+         * revision check below.
+         */
+        local_flush_tlb_all();
+        flush_cache_all();
+        /*
+         * We want to check CPU revision early for cpu_is_xxxx() macros.
+         * IO space mapping must be initialized before we can do that.
+         */
+        davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base);
+        dip = davinci_get_id(davinci_soc_info.jtag_id);
+        if (!dip) {
+                ret = -EINVAL;
+                goto err;
+        }
+        davinci_soc_info.cpu_id = dip->cpu_id;
+        pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant);
+        if (davinci_soc_info.cpu_clks) {
+                ret = davinci_clk_init(davinci_soc_info.cpu_clks);
+                if (ret != 0)
+                        goto err;
+        }
+        davinci_intc_base = davinci_soc_info.intc_base;
+        davinci_intc_type = davinci_soc_info.intc_type;
+        return;
+err:
+        pr_err("davinci_common_init: SoC Initialization failed\n");
+}
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
new file mode 100644
index 000000000000..96c8e97a7deb
--- /dev/null
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -0,0 +1,161 @@
+/*
+ * TI Common Platform Interrupt Controller (cp_intc) driver
+ *
+ * Author: Steve Chen <schen@mvista.com>
+ * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach/cp_intc.h>
+static void __iomem *cp_intc_base;
+static inline unsigned int cp_intc_read(unsigned offset)
+{
+        return __raw_readl(cp_intc_base + offset);
+}
+static inline void cp_intc_write(unsigned long value, unsigned offset)
+{
+        __raw_writel(value, cp_intc_base + offset);
+}
+static void cp_intc_ack_irq(unsigned int irq)
+{
+        cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR);
+}
+/* Disable interrupt */
+static void cp_intc_mask_irq(unsigned int irq)
+{
+        /* XXX don't know why we need to disable nIRQ here... */
+        cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
+        cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR);
+        cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
+}
+/* Enable interrupt */
+static void cp_intc_unmask_irq(unsigned int irq)
+{
+        cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET);
+}
+static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
+{
+        unsigned reg            = BIT_WORD(irq);
+        unsigned mask           = BIT_MASK(irq);
+        unsigned polarity       = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
+        unsigned type           = cp_intc_read(CP_INTC_SYS_TYPE(reg));
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_RISING:
+                polarity |= mask;
+                type |= mask;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                polarity &= ~mask;
+                type |= mask;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                polarity |= mask;
+                type &= ~mask;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                polarity &= ~mask;
+                type &= ~mask;
+                break;
+        default:
+                return -EINVAL;
+        }
+        cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
+        cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
+        return 0;
+}
+static struct irq_chip cp_intc_irq_chip = {
+        .name           = "cp_intc",
+        .ack            = cp_intc_ack_irq,
+        .mask           = cp_intc_mask_irq,
+        .unmask         = cp_intc_unmask_irq,
+        .set_type       = cp_intc_set_irq_type,
+};
+void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
+                         u8 *irq_prio)
+{
+        unsigned num_reg        = BITS_TO_LONGS(num_irq);
+        int i;
+        cp_intc_base = base;
+        cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
+        /* Disable all host interrupts */
+        cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
+        /* Disable system interrupts */
+        for (i = 0; i < num_reg; i++)
+                cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
+        /* Set to normal mode, no nesting, no priority hold */
+        cp_intc_write(0, CP_INTC_CTRL);
+        cp_intc_write(0, CP_INTC_HOST_CTRL);
+        /* Clear system interrupt status */
+        for (i = 0; i < num_reg; i++)
+                cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
+        /* Enable nIRQ (what about nFIQ?) */
+        cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
+        /*
+         * Priority is determined by host channel: lower channel number has
+         * higher priority i.e. channel 0 has highest priority and channel 31
+         * had the lowest priority.
+         */
+        num_reg = (num_irq + 3) >> 2;   /* 4 channels per register */
+        if (irq_prio) {
+                unsigned j, k;
+                u32 val;
+                for (k = i = 0; i < num_reg; i++) {
+                        for (val = j = 0; j < 4; j++, k++) {
+                                val >>= 8;
+                                if (k < num_irq)
+                                        val |= irq_prio[k] << 24;
+                        }
+                        cp_intc_write(val, CP_INTC_CHAN_MAP(i));
+                }
+        } else  {
+                /*
+                 * Default everything to channel 15 if priority not specified.
+                 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
+                 * are mapped to nIRQ.
+                 */
+                for (i = 0; i < num_reg; i++)
+                        cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
+        }
+        /* Set up genirq dispatching for cp_intc */
+        for (i = 0; i < num_irq; i++) {
+                set_irq_chip(i, &cp_intc_irq_chip);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+                set_irq_handler(i, handle_edge_irq);
+        }
+        /* Enable global interrupt */
+        cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
+}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a31370b93dd2..de16f347566a 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,8 +23,14 @@
 #include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <mach/mux.h>
+#include <mach/edma.h>
+#include <mach/mmc.h>
+#include <mach/time.h>
 #define DAVINCI_I2C_BASE             0x01C21000
+#define DAVINCI_MMCSD0_BASE          0x01E10000
+#define DM355_MMCSD0_BASE            0x01E11000
+#define DM355_MMCSD1_BASE            0x01E00000
 static struct resource i2c_resources[] = {
        {
@@ -54,3 +60,208 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
        (void) platform_device_register(&davinci_i2c_device);
 }
+#if     defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
+static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
+static struct resource mmcsd0_resources[] = {
+        {
+                /* different on dm355 */
+                .start = DAVINCI_MMCSD0_BASE,
+                .end   = DAVINCI_MMCSD0_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        /* IRQs:  MMC/SD, then SDIO */
+        {
+                .start = IRQ_MMCINT,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                /* different on dm355 */
+                .start = IRQ_SDIOINT,
+                .flags = IORESOURCE_IRQ,
+        },
+        /* DMA channels: RX, then TX */
+        {
+                .start = DAVINCI_DMA_MMCRXEVT,
+                .flags = IORESOURCE_DMA,
+        }, {
+                .start = DAVINCI_DMA_MMCTXEVT,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device davinci_mmcsd0_device = {
+        .name = "davinci_mmc",
+        .id = 0,
+        .dev = {
+                .dma_mask = &mmcsd0_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources = ARRAY_SIZE(mmcsd0_resources),
+        .resource = mmcsd0_resources,
+};
+static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32);
+static struct resource mmcsd1_resources[] = {
+        {
+                .start = DM355_MMCSD1_BASE,
+                .end   = DM355_MMCSD1_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        /* IRQs:  MMC/SD, then SDIO */
+        {
+                .start = IRQ_DM355_MMCINT1,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = IRQ_DM355_SDIOINT1,
+                .flags = IORESOURCE_IRQ,
+        },
+        /* DMA channels: RX, then TX */
+        {
+                .start = 30,    /* rx */
+                .flags = IORESOURCE_DMA,
+        }, {
+                .start = 31,    /* tx */
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device davinci_mmcsd1_device = {
+        .name = "davinci_mmc",
+        .id = 1,
+        .dev = {
+                .dma_mask = &mmcsd1_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources = ARRAY_SIZE(mmcsd1_resources),
+        .resource = mmcsd1_resources,
+};
+void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
+{
+        struct platform_device  *pdev = NULL;
+        if (WARN_ON(cpu_is_davinci_dm646x()))
+                return;
+        /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
+         * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
+         *
+         * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
+         * not handled right here ...
+         */
+        switch (module) {
+        case 1:
+                if (!cpu_is_davinci_dm355())
+                        break;
+                /* REVISIT we may not need all these pins if e.g. this
+                 * is a hard-wired SDIO device...
+                 */
+                davinci_cfg_reg(DM355_SD1_CMD);
+                davinci_cfg_reg(DM355_SD1_CLK);
+                davinci_cfg_reg(DM355_SD1_DATA0);
+                davinci_cfg_reg(DM355_SD1_DATA1);
+                davinci_cfg_reg(DM355_SD1_DATA2);
+                davinci_cfg_reg(DM355_SD1_DATA3);
+                pdev = &davinci_mmcsd1_device;
+                break;
+        case 0:
+                if (cpu_is_davinci_dm355()) {
+                        mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
+                        mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
+                        mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
+                        /* expose all 6 MMC0 signals:  CLK, CMD, DATA[0..3] */
+                        davinci_cfg_reg(DM355_MMCSD0);
+                        /* enable RX EDMA */
+                        davinci_cfg_reg(DM355_EVT26_MMC0_RX);
+                }
+                else if (cpu_is_davinci_dm644x()) {
+                        /* REVISIT: should this be in board-init code? */
+                        void __iomem *base =
+                                IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
+                        /* Power-on 3.3V IO cells */
+                        __raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
+                        /*Set up the pull regiter for MMC */
+                        davinci_cfg_reg(DM644X_MSTK);
+                }
+                pdev = &davinci_mmcsd0_device;
+                break;
+        }
+        if (WARN_ON(!pdev))
+                return;
+        pdev->dev.platform_data = config;
+        platform_device_register(pdev);
+}
+#else
+void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
+{
+}
+#endif
+/*-------------------------------------------------------------------------*/
+static struct resource wdt_resources[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+        },
+};
+struct platform_device davinci_wdt_device = {
+        .name           = "watchdog",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
+        .resource       = wdt_resources,
+};
+static void davinci_init_wdt(void)
+{
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        wdt_resources[0].start = (resource_size_t)soc_info->wdt_base;
+        wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1;
+        platform_device_register(&davinci_wdt_device);
+}
+/*-------------------------------------------------------------------------*/
+struct davinci_timer_instance davinci_timer_instance[2] = {
+        {
+                .base           = IO_ADDRESS(DAVINCI_TIMER0_BASE),
+                .bottom_irq     = IRQ_TINT0_TINT12,
+                .top_irq        = IRQ_TINT0_TINT34,
+        },
+        {
+                .base           = IO_ADDRESS(DAVINCI_TIMER1_BASE),
+                .bottom_irq     = IRQ_TINT1_TINT12,
+                .top_irq        = IRQ_TINT1_TINT34,
+        },
+};
+/*-------------------------------------------------------------------------*/
+static int __init davinci_init_devices(void)
+{
+        /* please keep these calls, and their implementations above,
+         * in alphabetical order so they're easier to sort through.
+         */
+        davinci_init_wdt();
+        return 0;
+}
+arch_initcall(davinci_init_devices);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
new file mode 100644
index 000000000000..baaaf328de2e
--- /dev/null
+++ b/arch/arm/mach-davinci/dm355.c
@@ -0,0 +1,730 @@
+/*
+ * TI DaVinci DM355 chip specific setup
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <asm/mach/map.h>
+#include <mach/dm355.h>
+#include <mach/clock.h>
+#include <mach/cputype.h>
+#include <mach/edma.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+#include <mach/irqs.h>
+#include <mach/time.h>
+#include <mach/serial.h>
+#include <mach/common.h>
+#include "clock.h"
+#include "mux.h"
+#define DM355_UART2_BASE        (IO_PHYS + 0x206000)
+/*
+ * Device specific clocks
+ */
+#define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
+static struct pll_data pll1_data = {
+        .num       = 1,
+        .phys_base = DAVINCI_PLL1_BASE,
+        .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
+};
+static struct pll_data pll2_data = {
+        .num       = 2,
+        .phys_base = DAVINCI_PLL2_BASE,
+        .flags     = PLL_HAS_PREDIV,
+};
+static struct clk ref_clk = {
+        .name = "ref_clk",
+        /* FIXME -- crystal rate is board-specific */
+        .rate = DM355_REF_FREQ,
+};
+static struct clk pll1_clk = {
+        .name = "pll1",
+        .parent = &ref_clk,
+        .flags = CLK_PLL,
+        .pll_data = &pll1_data,
+};
+static struct clk pll1_aux_clk = {
+        .name = "pll1_aux_clk",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL | PRE_PLL,
+};
+static struct clk pll1_sysclk1 = {
+        .name = "pll1_sysclk1",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV1,
+};
+static struct clk pll1_sysclk2 = {
+        .name = "pll1_sysclk2",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV2,
+};
+static struct clk pll1_sysclk3 = {
+        .name = "pll1_sysclk3",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV3,
+};
+static struct clk pll1_sysclk4 = {
+        .name = "pll1_sysclk4",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV4,
+};
+static struct clk pll1_sysclkbp = {
+        .name = "pll1_sysclkbp",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL | PRE_PLL,
+        .div_reg = BPDIV
+};
+static struct clk vpss_dac_clk = {
+        .name = "vpss_dac",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM355_LPSC_VPSS_DAC,
+};
+static struct clk vpss_master_clk = {
+        .name = "vpss_master",
+        .parent = &pll1_sysclk4,
+        .lpsc = DAVINCI_LPSC_VPSSMSTR,
+        .flags = CLK_PSC,
+};
+static struct clk vpss_slave_clk = {
+        .name = "vpss_slave",
+        .parent = &pll1_sysclk4,
+        .lpsc = DAVINCI_LPSC_VPSSSLV,
+};
+static struct clk clkout1_clk = {
+        .name = "clkout1",
+        .parent = &pll1_aux_clk,
+        /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
+};
+static struct clk clkout2_clk = {
+        .name = "clkout2",
+        .parent = &pll1_sysclkbp,
+};
+static struct clk pll2_clk = {
+        .name = "pll2",
+        .parent = &ref_clk,
+        .flags = CLK_PLL,
+        .pll_data = &pll2_data,
+};
+static struct clk pll2_sysclk1 = {
+        .name = "pll2_sysclk1",
+        .parent = &pll2_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV1,
+};
+static struct clk pll2_sysclkbp = {
+        .name = "pll2_sysclkbp",
+        .parent = &pll2_clk,
+        .flags = CLK_PLL | PRE_PLL,
+        .div_reg = BPDIV
+};
+static struct clk clkout3_clk = {
+        .name = "clkout3",
+        .parent = &pll2_sysclkbp,
+        /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
+};
+static struct clk arm_clk = {
+        .name = "arm_clk",
+        .parent = &pll1_sysclk1,
+        .lpsc = DAVINCI_LPSC_ARM,
+        .flags = ALWAYS_ENABLED,
+};
+/*
+ * NOT LISTED below, and not touched by Linux
+ *   - in SyncReset state by default
+ *      .lpsc = DAVINCI_LPSC_TPCC,
+ *      .lpsc = DAVINCI_LPSC_TPTC0,
+ *      .lpsc = DAVINCI_LPSC_TPTC1,
+ *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
+ *      .lpsc = DAVINCI_LPSC_MEMSTICK,
+ *   - in Enabled state by default
+ *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
+ *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
+ *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
+ *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
+ *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
+ *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
+ *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
+ *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
+ */
+static struct clk mjcp_clk = {
+        .name = "mjcp",
+        .parent = &pll1_sysclk1,
+        .lpsc = DAVINCI_LPSC_IMCOP,
+};
+static struct clk uart0_clk = {
+        .name = "uart0",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_UART0,
+};
+static struct clk uart1_clk = {
+        .name = "uart1",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_UART1,
+};
+static struct clk uart2_clk = {
+        .name = "uart2",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_UART2,
+};
+static struct clk i2c_clk = {
+        .name = "i2c",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_I2C,
+};
+static struct clk asp0_clk = {
+        .name = "asp0",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_McBSP,
+};
+static struct clk asp1_clk = {
+        .name = "asp1",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM355_LPSC_McBSP1,
+};
+static struct clk mmcsd0_clk = {
+        .name = "mmcsd0",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_MMC_SD,
+};
+static struct clk mmcsd1_clk = {
+        .name = "mmcsd1",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM355_LPSC_MMC_SD1,
+};
+static struct clk spi0_clk = {
+        .name = "spi0",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_SPI,
+};
+static struct clk spi1_clk = {
+        .name = "spi1",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM355_LPSC_SPI1,
+};
+static struct clk spi2_clk = {
+        .name = "spi2",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM355_LPSC_SPI2,
+};
+static struct clk gpio_clk = {
+        .name = "gpio",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_GPIO,
+};
+static struct clk aemif_clk = {
+        .name = "aemif",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_AEMIF,
+};
+static struct clk pwm0_clk = {
+        .name = "pwm0",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_PWM0,
+};
+static struct clk pwm1_clk = {
+        .name = "pwm1",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_PWM1,
+};
+static struct clk pwm2_clk = {
+        .name = "pwm2",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_PWM2,
+};
+static struct clk pwm3_clk = {
+        .name = "pwm3",
+        .parent = &pll1_aux_clk,
+        .lpsc = DM355_LPSC_PWM3,
+};
+static struct clk timer0_clk = {
+        .name = "timer0",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_TIMER0,
+};
+static struct clk timer1_clk = {
+        .name = "timer1",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_TIMER1,
+};
+static struct clk timer2_clk = {
+        .name = "timer2",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_TIMER2,
+        .usecount = 1,              /* REVISIT: why cant' this be disabled? */
+};
+static struct clk timer3_clk = {
+        .name = "timer3",
+        .parent = &pll1_aux_clk,
+        .lpsc = DM355_LPSC_TIMER3,
+};
+static struct clk rto_clk = {
+        .name = "rto",
+        .parent = &pll1_aux_clk,
+        .lpsc = DM355_LPSC_RTO,
+};
+static struct clk usb_clk = {
+        .name = "usb",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_USB,
+};
+static struct davinci_clk dm355_clks[] = {
+        CLK(NULL, "ref", &ref_clk),
+        CLK(NULL, "pll1", &pll1_clk),
+        CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
+        CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
+        CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
+        CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
+        CLK(NULL, "pll1_aux", &pll1_aux_clk),
+        CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
+        CLK(NULL, "vpss_dac", &vpss_dac_clk),
+        CLK(NULL, "vpss_master", &vpss_master_clk),
+        CLK(NULL, "vpss_slave", &vpss_slave_clk),
+        CLK(NULL, "clkout1", &clkout1_clk),
+        CLK(NULL, "clkout2", &clkout2_clk),
+        CLK(NULL, "pll2", &pll2_clk),
+        CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
+        CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
+        CLK(NULL, "clkout3", &clkout3_clk),
+        CLK(NULL, "arm", &arm_clk),
+        CLK(NULL, "mjcp", &mjcp_clk),
+        CLK(NULL, "uart0", &uart0_clk),
+        CLK(NULL, "uart1", &uart1_clk),
+        CLK(NULL, "uart2", &uart2_clk),
+        CLK("i2c_davinci.1", NULL, &i2c_clk),
+        CLK("soc-audio.0", NULL, &asp0_clk),
+        CLK("soc-audio.1", NULL, &asp1_clk),
+        CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
+        CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
+        CLK(NULL, "spi0", &spi0_clk),
+        CLK(NULL, "spi1", &spi1_clk),
+        CLK(NULL, "spi2", &spi2_clk),
+        CLK(NULL, "gpio", &gpio_clk),
+        CLK(NULL, "aemif", &aemif_clk),
+        CLK(NULL, "pwm0", &pwm0_clk),
+        CLK(NULL, "pwm1", &pwm1_clk),
+        CLK(NULL, "pwm2", &pwm2_clk),
+        CLK(NULL, "pwm3", &pwm3_clk),
+        CLK(NULL, "timer0", &timer0_clk),
+        CLK(NULL, "timer1", &timer1_clk),
+        CLK("watchdog", NULL, &timer2_clk),
+        CLK(NULL, "timer3", &timer3_clk),
+        CLK(NULL, "rto", &rto_clk),
+        CLK(NULL, "usb", &usb_clk),
+        CLK(NULL, NULL, NULL),
+};
+/*----------------------------------------------------------------------*/
+static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
+static struct resource dm355_spi0_resources[] = {
+        {
+                .start = 0x01c66000,
+                .end   = 0x01c667ff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_DM355_SPINT0_1,
+                .flags = IORESOURCE_IRQ,
+        },
+        /* Not yet used, so not included:
+         * IORESOURCE_IRQ:
+         *  - IRQ_DM355_SPINT0_0
+         * IORESOURCE_DMA:
+         *  - DAVINCI_DMA_SPI_SPIX
+         *  - DAVINCI_DMA_SPI_SPIR
+         */
+};
+static struct platform_device dm355_spi0_device = {
+        .name = "spi_davinci",
+        .id = 0,
+        .dev = {
+                .dma_mask = &dm355_spi0_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources = ARRAY_SIZE(dm355_spi0_resources),
+        .resource = dm355_spi0_resources,
+};
+void __init dm355_init_spi0(unsigned chipselect_mask,
+                struct spi_board_info *info, unsigned len)
+{
+        /* for now, assume we need MISO */
+        davinci_cfg_reg(DM355_SPI0_SDI);
+        /* not all slaves will be wired up */
+        if (chipselect_mask & BIT(0))
+                davinci_cfg_reg(DM355_SPI0_SDENA0);
+        if (chipselect_mask & BIT(1))
+                davinci_cfg_reg(DM355_SPI0_SDENA1);
+        spi_register_board_info(info, len);
+        platform_device_register(&dm355_spi0_device);
+}
+/*----------------------------------------------------------------------*/
+#define PINMUX0         0x00
+#define PINMUX1         0x04
+#define PINMUX2         0x08
+#define PINMUX3         0x0c
+#define PINMUX4         0x10
+#define INTMUX          0x18
+#define EVTMUX          0x1c
+/*
+ * Device specific mux setup
+ *
+ *      soc     description     mux  mode   mode  mux    dbg
+ *                              reg  offset mask  mode
+ */
+static const struct mux_config dm355_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
+MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
+MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
+MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
+MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
+MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
+MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
+MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
+MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
+MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
+MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
+MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
+MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
+MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
+MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
+MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
+MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
+MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
+INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
+INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
+INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
+EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
+EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
+EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
+#endif
+};
+static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+        [IRQ_DM355_CCDC_VDINT0]         = 2,
+        [IRQ_DM355_CCDC_VDINT1]         = 6,
+        [IRQ_DM355_CCDC_VDINT2]         = 6,
+        [IRQ_DM355_IPIPE_HST]           = 6,
+        [IRQ_DM355_H3AINT]              = 6,
+        [IRQ_DM355_IPIPE_SDR]           = 6,
+        [IRQ_DM355_IPIPEIFINT]          = 6,
+        [IRQ_DM355_OSDINT]              = 7,
+        [IRQ_DM355_VENCINT]             = 6,
+        [IRQ_ASQINT]                    = 6,
+        [IRQ_IMXINT]                    = 6,
+        [IRQ_USBINT]                    = 4,
+        [IRQ_DM355_RTOINT]              = 4,
+        [IRQ_DM355_UARTINT2]            = 7,
+        [IRQ_DM355_TINT6]               = 7,
+        [IRQ_CCINT0]                    = 5,    /* dma */
+        [IRQ_CCERRINT]                  = 5,    /* dma */
+        [IRQ_TCERRINT0]                 = 5,    /* dma */
+        [IRQ_TCERRINT]                  = 5,    /* dma */
+        [IRQ_DM355_SPINT2_1]            = 7,
+        [IRQ_DM355_TINT7]               = 4,
+        [IRQ_DM355_SDIOINT0]            = 7,
+        [IRQ_MBXINT]                    = 7,
+        [IRQ_MBRINT]                    = 7,
+        [IRQ_MMCINT]                    = 7,
+        [IRQ_DM355_MMCINT1]             = 7,
+        [IRQ_DM355_PWMINT3]             = 7,
+        [IRQ_DDRINT]                    = 7,
+        [IRQ_AEMIFINT]                  = 7,
+        [IRQ_DM355_SDIOINT1]            = 4,
+        [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
+        [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
+        [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
+        [IRQ_TINT1_TINT34]              = 7,    /* system tick */
+        [IRQ_PWMINT0]                   = 7,
+        [IRQ_PWMINT1]                   = 7,
+        [IRQ_PWMINT2]                   = 7,
+        [IRQ_I2C]                       = 3,
+        [IRQ_UARTINT0]                  = 3,
+        [IRQ_UARTINT1]                  = 3,
+        [IRQ_DM355_SPINT0_0]            = 3,
+        [IRQ_DM355_SPINT0_1]            = 3,
+        [IRQ_DM355_GPIO0]               = 3,
+        [IRQ_DM355_GPIO1]               = 7,
+        [IRQ_DM355_GPIO2]               = 4,
+        [IRQ_DM355_GPIO3]               = 4,
+        [IRQ_DM355_GPIO4]               = 7,
+        [IRQ_DM355_GPIO5]               = 7,
+        [IRQ_DM355_GPIO6]               = 7,
+        [IRQ_DM355_GPIO7]               = 7,
+        [IRQ_DM355_GPIO8]               = 7,
+        [IRQ_DM355_GPIO9]               = 7,
+        [IRQ_DM355_GPIOBNK0]            = 7,
+        [IRQ_DM355_GPIOBNK1]            = 7,
+        [IRQ_DM355_GPIOBNK2]            = 7,
+        [IRQ_DM355_GPIOBNK3]            = 7,
+        [IRQ_DM355_GPIOBNK4]            = 7,
+        [IRQ_DM355_GPIOBNK5]            = 7,
+        [IRQ_DM355_GPIOBNK6]            = 7,
+        [IRQ_COMMTX]                    = 7,
+        [IRQ_COMMRX]                    = 7,
+        [IRQ_EMUINT]                    = 7,
+};
+/*----------------------------------------------------------------------*/
+static const s8 dma_chan_dm355_no_event[] = {
+        12, 13, 24, 56, 57,
+        58, 59, 60, 61, 62,
+        63,
+        -1
+};
+static struct edma_soc_info dm355_edma_info = {
+        .n_channel      = 64,
+        .n_region       = 4,
+        .n_slot         = 128,
+        .n_tc           = 2,
+        .noevent        = dma_chan_dm355_no_event,
+};
+static struct resource edma_resources[] = {
+        {
+                .name   = "edma_cc",
+                .start  = 0x01c00000,
+                .end    = 0x01c00000 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc0",
+                .start  = 0x01c10000,
+                .end    = 0x01c10000 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc1",
+                .start  = 0x01c10400,
+                .end    = 0x01c10400 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_CCINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_CCERRINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* not using (or muxing) TC*_ERR */
+};
+static struct platform_device dm355_edma_device = {
+        .name                   = "edma",
+        .id                     = -1,
+        .dev.platform_data      = &dm355_edma_info,
+        .num_resources          = ARRAY_SIZE(edma_resources),
+        .resource               = edma_resources,
+};
+/*----------------------------------------------------------------------*/
+static struct map_desc dm355_io_desc[] = {
+        {
+                .virtual        = IO_VIRT,
+                .pfn            = __phys_to_pfn(IO_PHYS),
+                .length         = IO_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = SRAM_VIRT,
+                .pfn            = __phys_to_pfn(0x00010000),
+                .length         = SZ_32K,
+                /* MT_MEMORY_NONCACHED requires supersection alignment */
+                .type           = MT_DEVICE,
+        },
+};
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id dm355_ids[] = {
+        {
+                .variant        = 0x0,
+                .part_no        = 0xb73b,
+                .manufacturer   = 0x00f,
+                .cpu_id         = DAVINCI_CPU_ID_DM355,
+                .name           = "dm355",
+        },
+};
+static void __iomem *dm355_psc_bases[] = {
+        IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
+};
+/*
+ * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
+ * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
+ * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
+ * T1_TOP: Timer 1, top   :  <unused>
+ */
+struct davinci_timer_info dm355_timer_info = {
+        .timers         = davinci_timer_instance,
+        .clockevent_id  = T0_BOT,
+        .clocksource_id = T0_TOP,
+};
+static struct plat_serial8250_port dm355_serial_platform_data[] = {
+        {
+                .mapbase        = DAVINCI_UART0_BASE,
+                .irq            = IRQ_UARTINT0,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART1_BASE,
+                .irq            = IRQ_UARTINT1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DM355_UART2_BASE,
+                .irq            = IRQ_DM355_UARTINT2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .flags          = 0
+        },
+};
+static struct platform_device dm355_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = dm355_serial_platform_data,
+        },
+};
+static struct davinci_soc_info davinci_soc_info_dm355 = {
+        .io_desc                = dm355_io_desc,
+        .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
+        .jtag_id_base           = IO_ADDRESS(0x01c40028),
+        .ids                    = dm355_ids,
+        .ids_num                = ARRAY_SIZE(dm355_ids),
+        .cpu_clks               = dm355_clks,
+        .psc_bases              = dm355_psc_bases,
+        .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
+        .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+        .pinmux_pins            = dm355_pins,
+        .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
+        .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
+        .intc_irq_prios         = dm355_default_priorities,
+        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
+        .timer_info             = &dm355_timer_info,
+        .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
+        .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
+        .gpio_num               = 104,
+        .gpio_irq               = IRQ_DM355_GPIOBNK0,
+        .serial_dev             = &dm355_serial_device,
+        .sram_dma               = 0x00010000,
+        .sram_len               = SZ_32K,
+};
+void __init dm355_init(void)
+{
+        davinci_common_init(&davinci_soc_info_dm355);
+}
+static int __init dm355_init_devices(void)
+{
+        if (!cpu_is_davinci_dm355())
+                return 0;
+        davinci_cfg_reg(DM355_INT_EDMA_CC);
+        platform_device_register(&dm355_edma_device);
+        return 0;
+}
+postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d428ef192eac..fb5449b3c97b 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -11,7 +11,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/serial_8250.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
 #include <mach/dm644x.h>
 #include <mach/clock.h>
@@ -20,6 +24,9 @@
 #include <mach/irqs.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
+#include <mach/time.h>
+#include <mach/serial.h>
+#include <mach/common.h>
 #include "clock.h"
 #include "mux.h"
@@ -312,7 +319,14 @@ struct davinci_clk dm644x_clks[] = {
        CLK(NULL, NULL, NULL),
 };
-#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
+static struct emac_platform_data dm644x_emac_pdata = {
+        .ctrl_reg_offset        = DM644X_EMAC_CNTRL_OFFSET,
+        .ctrl_mod_reg_offset    = DM644X_EMAC_CNTRL_MOD_OFFSET,
+        .ctrl_ram_offset        = DM644X_EMAC_CNTRL_RAM_OFFSET,
+        .mdio_reg_offset        = DM644X_EMAC_MDIO_OFFSET,
+        .ctrl_ram_size          = DM644X_EMAC_CNTRL_RAM_SIZE,
+        .version                = EMAC_VERSION_1,
+};
 static struct resource dm644x_emac_resources[] = {
        {
@@ -330,11 +344,15 @@ static struct resource dm644x_emac_resources[] = {
 static struct platform_device dm644x_emac_device = {
       .name            = "davinci_emac",
       .id              = 1,
+       .dev = {
+               .platform_data   = &dm644x_emac_pdata,
+       },
       .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
       .resource        = dm644x_emac_resources,
 };
-#endif
+#define PINMUX0         0x00
+#define PINMUX1         0x04
 /*
 * Device specific mux setup
@@ -343,6 +361,7 @@ static struct platform_device dm644x_emac_device = {
 *                              reg  offset mask  mode
 */
 static const struct mux_config dm644x_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
@@ -383,8 +402,76 @@ MUX_CFG(DM644X, RGB666,		0,   22,    1,	  1,	 true)
 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
+#endif
 };
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+        [IRQ_VDINT0]            = 2,
+        [IRQ_VDINT1]            = 6,
+        [IRQ_VDINT2]            = 6,
+        [IRQ_HISTINT]           = 6,
+        [IRQ_H3AINT]            = 6,
+        [IRQ_PRVUINT]           = 6,
+        [IRQ_RSZINT]            = 6,
+        [7]                     = 7,
+        [IRQ_VENCINT]           = 6,
+        [IRQ_ASQINT]            = 6,
+        [IRQ_IMXINT]            = 6,
+        [IRQ_VLCDINT]           = 6,
+        [IRQ_USBINT]            = 4,
+        [IRQ_EMACINT]           = 4,
+        [14]                    = 7,
+        [15]                    = 7,
+        [IRQ_CCINT0]            = 5,    /* dma */
+        [IRQ_CCERRINT]          = 5,    /* dma */
+        [IRQ_TCERRINT0]         = 5,    /* dma */
+        [IRQ_TCERRINT]          = 5,    /* dma */
+        [IRQ_PSCIN]             = 7,
+        [21]                    = 7,
+        [IRQ_IDE]               = 4,
+        [23]                    = 7,
+        [IRQ_MBXINT]            = 7,
+        [IRQ_MBRINT]            = 7,
+        [IRQ_MMCINT]            = 7,
+        [IRQ_SDIOINT]           = 7,
+        [28]                    = 7,
+        [IRQ_DDRINT]            = 7,
+        [IRQ_AEMIFINT]          = 7,
+        [IRQ_VLQINT]            = 4,
+        [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
+        [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
+        [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
+        [IRQ_TINT1_TINT34]      = 7,    /* system tick */
+        [IRQ_PWMINT0]           = 7,
+        [IRQ_PWMINT1]           = 7,
+        [IRQ_PWMINT2]           = 7,
+        [IRQ_I2C]               = 3,
+        [IRQ_UARTINT0]          = 3,
+        [IRQ_UARTINT1]          = 3,
+        [IRQ_UARTINT2]          = 3,
+        [IRQ_SPINT0]            = 3,
+        [IRQ_SPINT1]            = 3,
+        [45]                    = 7,
+        [IRQ_DSP2ARM0]          = 4,
+        [IRQ_DSP2ARM1]          = 4,
+        [IRQ_GPIO0]             = 7,
+        [IRQ_GPIO1]             = 7,
+        [IRQ_GPIO2]             = 7,
+        [IRQ_GPIO3]             = 7,
+        [IRQ_GPIO4]             = 7,
+        [IRQ_GPIO5]             = 7,
+        [IRQ_GPIO6]             = 7,
+        [IRQ_GPIO7]             = 7,
+        [IRQ_GPIOBNK0]          = 7,
+        [IRQ_GPIOBNK1]          = 7,
+        [IRQ_GPIOBNK2]          = 7,
+        [IRQ_GPIOBNK3]          = 7,
+        [IRQ_GPIOBNK4]          = 7,
+        [IRQ_COMMTX]            = 7,
+        [IRQ_COMMRX]            = 7,
+        [IRQ_EMUINT]            = 7,
+};
 /*----------------------------------------------------------------------*/
@@ -444,10 +531,118 @@ static struct platform_device dm644x_edma_device = {
 };
 /*----------------------------------------------------------------------*/
+static struct map_desc dm644x_io_desc[] = {
+        {
+                .virtual        = IO_VIRT,
+                .pfn            = __phys_to_pfn(IO_PHYS),
+                .length         = IO_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = SRAM_VIRT,
+                .pfn            = __phys_to_pfn(0x00008000),
+                .length         = SZ_16K,
+                /* MT_MEMORY_NONCACHED requires supersection alignment */
+                .type           = MT_DEVICE,
+        },
+};
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id dm644x_ids[] = {
+        {
+                .variant        = 0x0,
+                .part_no        = 0xb700,
+                .manufacturer   = 0x017,
+                .cpu_id         = DAVINCI_CPU_ID_DM6446,
+                .name           = "dm6446",
+        },
+};
+static void __iomem *dm644x_psc_bases[] = {
+        IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
+};
+/*
+ * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
+ * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
+ * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
+ * T1_TOP: Timer 1, top   :  <unused>
+ */
+struct davinci_timer_info dm644x_timer_info = {
+        .timers         = davinci_timer_instance,
+        .clockevent_id  = T0_BOT,
+        .clocksource_id = T0_TOP,
+};
+static struct plat_serial8250_port dm644x_serial_platform_data[] = {
+        {
+                .mapbase        = DAVINCI_UART0_BASE,
+                .irq            = IRQ_UARTINT0,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART1_BASE,
+                .irq            = IRQ_UARTINT1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART2_BASE,
+                .irq            = IRQ_UARTINT2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .flags          = 0
+        },
+};
+static struct platform_device dm644x_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = dm644x_serial_platform_data,
+        },
+};
+static struct davinci_soc_info davinci_soc_info_dm644x = {
+        .io_desc                = dm644x_io_desc,
+        .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
+        .jtag_id_base           = IO_ADDRESS(0x01c40028),
+        .ids                    = dm644x_ids,
+        .ids_num                = ARRAY_SIZE(dm644x_ids),
+        .cpu_clks               = dm644x_clks,
+        .psc_bases              = dm644x_psc_bases,
+        .psc_bases_num          = ARRAY_SIZE(dm644x_psc_bases),
+        .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+        .pinmux_pins            = dm644x_pins,
+        .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
+        .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
+        .intc_irq_prios         = dm644x_default_priorities,
+        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
+        .timer_info             = &dm644x_timer_info,
+        .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
+        .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
+        .gpio_num               = 71,
+        .gpio_irq               = IRQ_GPIOBNK0,
+        .serial_dev             = &dm644x_serial_device,
+        .emac_pdata             = &dm644x_emac_pdata,
+        .sram_dma               = 0x00008000,
+        .sram_len               = SZ_16K,
+};
 void __init dm644x_init(void)
 {
-        davinci_clk_init(dm644x_clks);
+        davinci_common_init(&davinci_soc_info_dm644x);
-        davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
 }
 static int __init dm644x_init_devices(void)
@@ -456,6 +651,7 @@ static int __init dm644x_init_devices(void)
                return 0;
        platform_device_register(&dm644x_edma_device);
+        platform_device_register(&dm644x_emac_device);
        return 0;
 }
 postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
new file mode 100644
index 000000000000..334f0711e0f5
--- /dev/null
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -0,0 +1,636 @@
+/*
+ * TI DaVinci DM644x chip specific setup
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
+#include <mach/dm646x.h>
+#include <mach/clock.h>
+#include <mach/cputype.h>
+#include <mach/edma.h>
+#include <mach/irqs.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+#include <mach/time.h>
+#include <mach/serial.h>
+#include <mach/common.h>
+#include "clock.h"
+#include "mux.h"
+/*
+ * Device specific clocks
+ */
+#define DM646X_REF_FREQ         27000000
+#define DM646X_AUX_FREQ         24000000
+static struct pll_data pll1_data = {
+        .num       = 1,
+        .phys_base = DAVINCI_PLL1_BASE,
+};
+static struct pll_data pll2_data = {
+        .num       = 2,
+        .phys_base = DAVINCI_PLL2_BASE,
+};
+static struct clk ref_clk = {
+        .name = "ref_clk",
+        .rate = DM646X_REF_FREQ,
+};
+static struct clk aux_clkin = {
+        .name = "aux_clkin",
+        .rate = DM646X_AUX_FREQ,
+};
+static struct clk pll1_clk = {
+        .name = "pll1",
+        .parent = &ref_clk,
+        .pll_data = &pll1_data,
+        .flags = CLK_PLL,
+};
+static struct clk pll1_sysclk1 = {
+        .name = "pll1_sysclk1",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV1,
+};
+static struct clk pll1_sysclk2 = {
+        .name = "pll1_sysclk2",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV2,
+};
+static struct clk pll1_sysclk3 = {
+        .name = "pll1_sysclk3",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV3,
+};
+static struct clk pll1_sysclk4 = {
+        .name = "pll1_sysclk4",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV4,
+};
+static struct clk pll1_sysclk5 = {
+        .name = "pll1_sysclk5",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV5,
+};
+static struct clk pll1_sysclk6 = {
+        .name = "pll1_sysclk6",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV6,
+};
+static struct clk pll1_sysclk8 = {
+        .name = "pll1_sysclk8",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV8,
+};
+static struct clk pll1_sysclk9 = {
+        .name = "pll1_sysclk9",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV9,
+};
+static struct clk pll1_sysclkbp = {
+        .name = "pll1_sysclkbp",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL | PRE_PLL,
+        .div_reg = BPDIV,
+};
+static struct clk pll1_aux_clk = {
+        .name = "pll1_aux_clk",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL | PRE_PLL,
+};
+static struct clk pll2_clk = {
+        .name = "pll2_clk",
+        .parent = &ref_clk,
+        .pll_data = &pll2_data,
+        .flags = CLK_PLL,
+};
+static struct clk pll2_sysclk1 = {
+        .name = "pll2_sysclk1",
+        .parent = &pll2_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV1,
+};
+static struct clk dsp_clk = {
+        .name = "dsp",
+        .parent = &pll1_sysclk1,
+        .lpsc = DM646X_LPSC_C64X_CPU,
+        .flags = PSC_DSP,
+        .usecount = 1,                  /* REVISIT how to disable? */
+};
+static struct clk arm_clk = {
+        .name = "arm",
+        .parent = &pll1_sysclk2,
+        .lpsc = DM646X_LPSC_ARM,
+        .flags = ALWAYS_ENABLED,
+};
+static struct clk uart0_clk = {
+        .name = "uart0",
+        .parent = &aux_clkin,
+        .lpsc = DM646X_LPSC_UART0,
+};
+static struct clk uart1_clk = {
+        .name = "uart1",
+        .parent = &aux_clkin,
+        .lpsc = DM646X_LPSC_UART1,
+};
+static struct clk uart2_clk = {
+        .name = "uart2",
+        .parent = &aux_clkin,
+        .lpsc = DM646X_LPSC_UART2,
+};
+static struct clk i2c_clk = {
+        .name = "I2CCLK",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_I2C,
+};
+static struct clk gpio_clk = {
+        .name = "gpio",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_GPIO,
+};
+static struct clk aemif_clk = {
+        .name = "aemif",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_AEMIF,
+        .flags = ALWAYS_ENABLED,
+};
+static struct clk emac_clk = {
+        .name = "emac",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_EMAC,
+};
+static struct clk pwm0_clk = {
+        .name = "pwm0",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_PWM0,
+        .usecount = 1,            /* REVIST: disabling hangs system */
+};
+static struct clk pwm1_clk = {
+        .name = "pwm1",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_PWM1,
+        .usecount = 1,            /* REVIST: disabling hangs system */
+};
+static struct clk timer0_clk = {
+        .name = "timer0",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_TIMER0,
+};
+static struct clk timer1_clk = {
+        .name = "timer1",
+        .parent = &pll1_sysclk3,
+        .lpsc = DM646X_LPSC_TIMER1,
+};
+static struct clk timer2_clk = {
+        .name = "timer2",
+        .parent = &pll1_sysclk3,
+        .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
+};
+static struct clk vpif0_clk = {
+        .name = "vpif0",
+        .parent = &ref_clk,
+        .lpsc = DM646X_LPSC_VPSSMSTR,
+        .flags = ALWAYS_ENABLED,
+};
+static struct clk vpif1_clk = {
+        .name = "vpif1",
+        .parent = &ref_clk,
+        .lpsc = DM646X_LPSC_VPSSSLV,
+        .flags = ALWAYS_ENABLED,
+};
+struct davinci_clk dm646x_clks[] = {
+        CLK(NULL, "ref", &ref_clk),
+        CLK(NULL, "aux", &aux_clkin),
+        CLK(NULL, "pll1", &pll1_clk),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
+        CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
+        CLK(NULL, "pll1_aux", &pll1_aux_clk),
+        CLK(NULL, "pll2", &pll2_clk),
+        CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
+        CLK(NULL, "dsp", &dsp_clk),
+        CLK(NULL, "arm", &arm_clk),
+        CLK(NULL, "uart0", &uart0_clk),
+        CLK(NULL, "uart1", &uart1_clk),
+        CLK(NULL, "uart2", &uart2_clk),
+        CLK("i2c_davinci.1", NULL, &i2c_clk),
+        CLK(NULL, "gpio", &gpio_clk),
+        CLK(NULL, "aemif", &aemif_clk),
+        CLK("davinci_emac.1", NULL, &emac_clk),
+        CLK(NULL, "pwm0", &pwm0_clk),
+        CLK(NULL, "pwm1", &pwm1_clk),
+        CLK(NULL, "timer0", &timer0_clk),
+        CLK(NULL, "timer1", &timer1_clk),
+        CLK("watchdog", NULL, &timer2_clk),
+        CLK(NULL, "vpif0", &vpif0_clk),
+        CLK(NULL, "vpif1", &vpif1_clk),
+        CLK(NULL, NULL, NULL),
+};
+static struct emac_platform_data dm646x_emac_pdata = {
+        .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
+        .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
+        .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
+        .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
+        .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
+        .version                = EMAC_VERSION_2,
+};
+static struct resource dm646x_emac_resources[] = {
+        {
+                .start  = DM646X_EMAC_BASE,
+                .end    = DM646X_EMAC_BASE + 0x47ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DM646X_EMACRXTHINT,
+                .end    = IRQ_DM646X_EMACRXTHINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DM646X_EMACRXINT,
+                .end    = IRQ_DM646X_EMACRXINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DM646X_EMACTXINT,
+                .end    = IRQ_DM646X_EMACTXINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DM646X_EMACMISCINT,
+                .end    = IRQ_DM646X_EMACMISCINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dm646x_emac_device = {
+        .name           = "davinci_emac",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &dm646x_emac_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
+        .resource       = dm646x_emac_resources,
+};
+#define PINMUX0         0x00
+#define PINMUX1         0x04
+/*
+ * Device specific mux setup
+ *
+ *      soc     description     mux  mode   mode  mux    dbg
+ *                              reg  offset mask  mode
+ */
+static const struct mux_config dm646x_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+MUX_CFG(DM646X, ATAEN,          0,   0,     1,    1,     true)
+MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
+MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
+MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
+MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
+MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
+MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
+MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
+MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
+MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
+MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
+MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
+MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
+MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
+#endif
+};
+static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+        [IRQ_DM646X_VP_VERTINT0]        = 7,
+        [IRQ_DM646X_VP_VERTINT1]        = 7,
+        [IRQ_DM646X_VP_VERTINT2]        = 7,
+        [IRQ_DM646X_VP_VERTINT3]        = 7,
+        [IRQ_DM646X_VP_ERRINT]          = 7,
+        [IRQ_DM646X_RESERVED_1]         = 7,
+        [IRQ_DM646X_RESERVED_2]         = 7,
+        [IRQ_DM646X_WDINT]              = 7,
+        [IRQ_DM646X_CRGENINT0]          = 7,
+        [IRQ_DM646X_CRGENINT1]          = 7,
+        [IRQ_DM646X_TSIFINT0]           = 7,
+        [IRQ_DM646X_TSIFINT1]           = 7,
+        [IRQ_DM646X_VDCEINT]            = 7,
+        [IRQ_DM646X_USBINT]             = 7,
+        [IRQ_DM646X_USBDMAINT]          = 7,
+        [IRQ_DM646X_PCIINT]             = 7,
+        [IRQ_CCINT0]                    = 7,    /* dma */
+        [IRQ_CCERRINT]                  = 7,    /* dma */
+        [IRQ_TCERRINT0]                 = 7,    /* dma */
+        [IRQ_TCERRINT]                  = 7,    /* dma */
+        [IRQ_DM646X_TCERRINT2]          = 7,
+        [IRQ_DM646X_TCERRINT3]          = 7,
+        [IRQ_DM646X_IDE]                = 7,
+        [IRQ_DM646X_HPIINT]             = 7,
+        [IRQ_DM646X_EMACRXTHINT]        = 7,
+        [IRQ_DM646X_EMACRXINT]          = 7,
+        [IRQ_DM646X_EMACTXINT]          = 7,
+        [IRQ_DM646X_EMACMISCINT]        = 7,
+        [IRQ_DM646X_MCASP0TXINT]        = 7,
+        [IRQ_DM646X_MCASP0RXINT]        = 7,
+        [IRQ_AEMIFINT]                  = 7,
+        [IRQ_DM646X_RESERVED_3]         = 7,
+        [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
+        [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
+        [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
+        [IRQ_TINT1_TINT34]              = 7,    /* system tick */
+        [IRQ_PWMINT0]                   = 7,
+        [IRQ_PWMINT1]                   = 7,
+        [IRQ_DM646X_VLQINT]             = 7,
+        [IRQ_I2C]                       = 7,
+        [IRQ_UARTINT0]                  = 7,
+        [IRQ_UARTINT1]                  = 7,
+        [IRQ_DM646X_UARTINT2]           = 7,
+        [IRQ_DM646X_SPINT0]             = 7,
+        [IRQ_DM646X_SPINT1]             = 7,
+        [IRQ_DM646X_DSP2ARMINT]         = 7,
+        [IRQ_DM646X_RESERVED_4]         = 7,
+        [IRQ_DM646X_PSCINT]             = 7,
+        [IRQ_DM646X_GPIO0]              = 7,
+        [IRQ_DM646X_GPIO1]              = 7,
+        [IRQ_DM646X_GPIO2]              = 7,
+        [IRQ_DM646X_GPIO3]              = 7,
+        [IRQ_DM646X_GPIO4]              = 7,
+        [IRQ_DM646X_GPIO5]              = 7,
+        [IRQ_DM646X_GPIO6]              = 7,
+        [IRQ_DM646X_GPIO7]              = 7,
+        [IRQ_DM646X_GPIOBNK0]           = 7,
+        [IRQ_DM646X_GPIOBNK1]           = 7,
+        [IRQ_DM646X_GPIOBNK2]           = 7,
+        [IRQ_DM646X_DDRINT]             = 7,
+        [IRQ_DM646X_AEMIFINT]           = 7,
+        [IRQ_COMMTX]                    = 7,
+        [IRQ_COMMRX]                    = 7,
+        [IRQ_EMUINT]                    = 7,
+};
+/*----------------------------------------------------------------------*/
+static const s8 dma_chan_dm646x_no_event[] = {
+         0,  1,  2,  3, 13,
+        14, 15, 24, 25, 26,
+        27, 30, 31, 54, 55,
+        56,
+        -1
+};
+static struct edma_soc_info dm646x_edma_info = {
+        .n_channel      = 64,
+        .n_region       = 6,    /* 0-1, 4-7 */
+        .n_slot         = 512,
+        .n_tc           = 4,
+        .noevent        = dma_chan_dm646x_no_event,
+};
+static struct resource edma_resources[] = {
+        {
+                .name   = "edma_cc",
+                .start  = 0x01c00000,
+                .end    = 0x01c00000 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc0",
+                .start  = 0x01c10000,
+                .end    = 0x01c10000 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc1",
+                .start  = 0x01c10400,
+                .end    = 0x01c10400 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc2",
+                .start  = 0x01c10800,
+                .end    = 0x01c10800 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc3",
+                .start  = 0x01c10c00,
+                .end    = 0x01c10c00 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_CCINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_CCERRINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* not using TC*_ERR */
+};
+static struct platform_device dm646x_edma_device = {
+        .name                   = "edma",
+        .id                     = -1,
+        .dev.platform_data      = &dm646x_edma_info,
+        .num_resources          = ARRAY_SIZE(edma_resources),
+        .resource               = edma_resources,
+};
+/*----------------------------------------------------------------------*/
+static struct map_desc dm646x_io_desc[] = {
+        {
+                .virtual        = IO_VIRT,
+                .pfn            = __phys_to_pfn(IO_PHYS),
+                .length         = IO_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = SRAM_VIRT,
+                .pfn            = __phys_to_pfn(0x00010000),
+                .length         = SZ_32K,
+                /* MT_MEMORY_NONCACHED requires supersection alignment */
+                .type           = MT_DEVICE,
+        },
+};
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id dm646x_ids[] = {
+        {
+                .variant        = 0x0,
+                .part_no        = 0xb770,
+                .manufacturer   = 0x017,
+                .cpu_id         = DAVINCI_CPU_ID_DM6467,
+                .name           = "dm6467",
+        },
+};
+static void __iomem *dm646x_psc_bases[] = {
+        IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
+};
+/*
+ * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
+ * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
+ * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
+ * T1_TOP: Timer 1, top   :  <unused>
+ */
+struct davinci_timer_info dm646x_timer_info = {
+        .timers         = davinci_timer_instance,
+        .clockevent_id  = T0_BOT,
+        .clocksource_id = T0_TOP,
+};
+static struct plat_serial8250_port dm646x_serial_platform_data[] = {
+        {
+                .mapbase        = DAVINCI_UART0_BASE,
+                .irq            = IRQ_UARTINT0,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM32,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART1_BASE,
+                .irq            = IRQ_UARTINT1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM32,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART2_BASE,
+                .irq            = IRQ_DM646X_UARTINT2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM32,
+                .regshift       = 2,
+        },
+        {
+                .flags          = 0
+        },
+};
+static struct platform_device dm646x_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = dm646x_serial_platform_data,
+        },
+};
+static struct davinci_soc_info davinci_soc_info_dm646x = {
+        .io_desc                = dm646x_io_desc,
+        .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
+        .jtag_id_base           = IO_ADDRESS(0x01c40028),
+        .ids                    = dm646x_ids,
+        .ids_num                = ARRAY_SIZE(dm646x_ids),
+        .cpu_clks               = dm646x_clks,
+        .psc_bases              = dm646x_psc_bases,
+        .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
+        .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
+        .pinmux_pins            = dm646x_pins,
+        .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
+        .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
+        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
+        .intc_irq_prios         = dm646x_default_priorities,
+        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
+        .timer_info             = &dm646x_timer_info,
+        .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
+        .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
+        .gpio_num               = 43, /* Only 33 usable */
+        .gpio_irq               = IRQ_DM646X_GPIOBNK0,
+        .serial_dev             = &dm646x_serial_device,
+        .emac_pdata             = &dm646x_emac_pdata,
+        .sram_dma               = 0x10010000,
+        .sram_len               = SZ_32K,
+};
+void __init dm646x_init(void)
+{
+        davinci_common_init(&davinci_soc_info_dm646x);
+}
+static int __init dm646x_init_devices(void)
+{
+        if (!cpu_is_davinci_dm646x())
+                return 0;
+        platform_device_register(&dm646x_edma_device);
+        platform_device_register(&dm646x_emac_device);
+        return 0;
+}
+postcore_initcall(dm646x_init_devices);
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 1aba41c6351e..1b6532159c58 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -23,6 +23,7 @@
 #include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <mach/gpio.h>
 #include <asm/mach/irq.h>
@@ -37,14 +38,13 @@ struct davinci_gpio {
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
-static unsigned __initdata ngpio;
 /* create a non-inlined version */
 static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
 {
        return __gpio_to_controller(gpio);
 }
+static int __init davinci_gpio_irq_setup(void);
 /*--------------------------------------------------------------------------*/
@@ -115,23 +115,16 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 static int __init davinci_gpio_setup(void)
 {
        int i, base;
+        unsigned ngpio;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        /* The gpio banks conceptually expose a segmented bitmap,
+        /*
+         * The gpio banks conceptually expose a segmented bitmap,
         * and "ngpio" is one more than the largest zero-based
         * bit index that's valid.
         */
-        if (cpu_is_davinci_dm355()) {           /* or dm335() */
+        ngpio = soc_info->gpio_num;
-                ngpio = 104;
+        if (ngpio == 0) {
-        } else if (cpu_is_davinci_dm644x()) {   /* or dm337() */
-                ngpio = 71;
-        } else if (cpu_is_davinci_dm646x()) {
-                /* NOTE:  each bank has several "reserved" bits,
-                 * unusable as GPIOs.  Only 33 of the GPIO numbers
-                 * are usable, and we're not rejecting the others.
-                 */
-                ngpio = 43;
-        } else {
-                /* if cpu_is_davinci_dm643x() ngpio = 111 */
                pr_err("GPIO setup:  how many GPIOs?\n");
                return -EINVAL;
        }
@@ -157,6 +150,7 @@ static int __init davinci_gpio_setup(void)
                gpiochip_add(&chips[i].chip);
        }
+        davinci_gpio_irq_setup();
        return 0;
 }
 pure_initcall(davinci_gpio_setup);
@@ -187,10 +181,15 @@ static void gpio_irq_enable(unsigned irq)
 {
        struct gpio_controller *__iomem g = get_irq_chip_data(irq);
        u32 mask = __gpio_mask(irq_to_gpio(irq));
+        unsigned status = irq_desc[irq].status;
+        status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
+        if (!status)
+                status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
-        if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
+        if (status & IRQ_TYPE_EDGE_FALLING)
                __raw_writel(mask, &g->set_falling);
-        if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
+        if (status & IRQ_TYPE_EDGE_RISING)
                __raw_writel(mask, &g->set_rising);
 }
@@ -205,10 +204,13 @@ static int gpio_irq_type(unsigned irq, unsigned trigger)
        irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
        irq_desc[irq].status |= trigger;
-        __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
+        /* don't enable the IRQ if it's currently disabled */
-                     ? &g->set_falling : &g->clr_falling);
+        if (irq_desc[irq].depth == 0) {
-        __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
+                __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
-                     ? &g->set_rising : &g->clr_rising);
+                             ? &g->set_falling : &g->clr_falling);
+                __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
+                             ? &g->set_rising : &g->clr_rising);
+        }
        return 0;
 }
@@ -230,6 +232,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                mask <<= 16;
        /* temporarily mask (level sensitive) parent IRQ */
+        desc->chip->mask(irq);
        desc->chip->ack(irq);
        while (1) {
                u32             status;
@@ -268,17 +271,15 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 static int __init davinci_gpio_irq_setup(void)
 {
        unsigned        gpio, irq, bank;
-        unsigned        bank_irq;
        struct clk      *clk;
        u32             binten = 0;
+        unsigned        ngpio, bank_irq;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        ngpio = soc_info->gpio_num;
-        if (cpu_is_davinci_dm355()) {           /* or dm335() */
+        bank_irq = soc_info->gpio_irq;
-                bank_irq = IRQ_DM355_GPIOBNK0;
+        if (bank_irq == 0) {
-        } else if (cpu_is_davinci_dm644x()) {
-                bank_irq = IRQ_GPIOBNK0;
-        } else if (cpu_is_davinci_dm646x()) {
-                bank_irq = IRQ_DM646X_GPIOBNK0;
-        } else {
                printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
                return -EINVAL;
        }
@@ -318,11 +319,9 @@ static int __init davinci_gpio_irq_setup(void)
        /* BINTEN -- per-bank interrupt enable. genirq would also let these
         * bits be set/cleared dynamically.
         */
-        __raw_writel(binten, (void *__iomem)
+        __raw_writel(binten, soc_info->gpio_base + 0x08);
-                     IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
        printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
        return 0;
 }
-arch_initcall(davinci_gpio_irq_setup);
diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c
deleted file mode 100644
index 018b994cd794..000000000000
--- a/arch/arm/mach-davinci/id.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Davinci CPU identification code
- *
- * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * Derived from OMAP1 CPU identification code.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#define JTAG_ID_BASE            IO_ADDRESS(0x01c40028)
-static unsigned int davinci_revision;
-struct davinci_id {
-        u8      variant;        /* JTAG ID bits 31:28 */
-        u16     part_no;        /* JTAG ID bits 27:12 */
-        u32     manufacturer;   /* JTAG ID bits 11:1 */
-        u32     type;           /* Cpu id bits [31:8], cpu class bits [7:0] */
-};
-/* Register values to detect the DaVinci version */
-static struct davinci_id davinci_ids[] __initdata = {
-        {
-                /* DM6446 */
-                .part_no      = 0xb700,
-                .variant      = 0x0,
-                .manufacturer = 0x017,
-                .type         = 0x64460000,
-        },
-        {
-                /* DM646X */
-                .part_no      = 0xb770,
-                .variant      = 0x0,
-                .manufacturer = 0x017,
-                .type         = 0x64670000,
-        },
-        {
-                /* DM355 */
-                .part_no        = 0xb73b,
-                .variant        = 0x0,
-                .manufacturer   = 0x00f,
-                .type           = 0x03550000,
-        },
-};
-/*
- * Get Device Part No. from JTAG ID register
- */
-static u16 __init davinci_get_part_no(void)
-{
-        u32 dev_id, part_no;
-        dev_id = __raw_readl(JTAG_ID_BASE);
-        part_no = ((dev_id >> 12) & 0xffff);
-        return part_no;
-}
-/*
- * Get Device Revision from JTAG ID register
- */
-static u8 __init davinci_get_variant(void)
-{
-        u32 variant;
-        variant = __raw_readl(JTAG_ID_BASE);
-        variant = (variant >> 28) & 0xf;
-        return variant;
-}
-unsigned int davinci_rev(void)
-{
-        return davinci_revision >> 16;
-}
-EXPORT_SYMBOL(davinci_rev);
-void __init davinci_check_revision(void)
-{
-        int i;
-        u16 part_no;
-        u8 variant;
-        part_no = davinci_get_part_no();
-        variant = davinci_get_variant();
-        /* First check only the major version in a safe way */
-        for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
-                if (part_no == (davinci_ids[i].part_no)) {
-                        davinci_revision = davinci_ids[i].type;
-                        break;
-                }
-        }
-        /* Check if we can find the dev revision */
-        for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
-                if (part_no == davinci_ids[i].part_no &&
-                    variant == davinci_ids[i].variant) {
-                        davinci_revision = davinci_ids[i].type;
-                        break;
-                }
-        }
-        printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n",
-               davinci_rev(), variant);
-}
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
deleted file mode 100644
index 3216f21c1238..000000000000
--- a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * DaVinci DM6446 EVM board specific headers
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or ifndef.
- */
-#ifndef _MACH_DAVINCI_DM6446EVM_H
-#define _MACH_DAVINCI_DM6446EVM_H
-#include <linux/types.h>
-int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
-int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 191770976250..a1f03b606d8f 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -17,7 +17,8 @@ struct sys_timer;
 extern struct sys_timer davinci_timer;
 extern void davinci_irq_init(void);
-extern void davinci_map_common_io(void);
+extern void __iomem *davinci_intc_base;
+extern int davinci_intc_type;
 /* parameters describe VBUS sourcing for host mode */
 extern void setup_usb(unsigned mA, unsigned potpgt_msec);
@@ -25,4 +26,56 @@ extern void setup_usb(unsigned mA, unsigned potpgt_msec);
 /* parameters describe VBUS sourcing for host mode */
 extern void setup_usb(unsigned mA, unsigned potpgt_msec);
+struct davinci_timer_instance {
+        void __iomem    *base;
+        u32             bottom_irq;
+        u32             top_irq;
+        unsigned long   cmp_off;
+        unsigned int    cmp_irq;
+};
+struct davinci_timer_info {
+        struct davinci_timer_instance   *timers;
+        unsigned int                    clockevent_id;
+        unsigned int                    clocksource_id;
+};
+/* SoC specific init support */
+struct davinci_soc_info {
+        struct map_desc                 *io_desc;
+        unsigned long                   io_desc_num;
+        u32                             cpu_id;
+        u32                             jtag_id;
+        void __iomem                    *jtag_id_base;
+        struct davinci_id               *ids;
+        unsigned long                   ids_num;
+        struct davinci_clk              *cpu_clks;
+        void __iomem                    **psc_bases;
+        unsigned long                   psc_bases_num;
+        void __iomem                    *pinmux_base;
+        const struct mux_config         *pinmux_pins;
+        unsigned long                   pinmux_pins_num;
+        void __iomem                    *intc_base;
+        int                             intc_type;
+        u8                              *intc_irq_prios;
+        unsigned long                   intc_irq_num;
+        struct davinci_timer_info       *timer_info;
+        void __iomem                    *wdt_base;
+        void __iomem                    *gpio_base;
+        unsigned                        gpio_num;
+        unsigned                        gpio_irq;
+        struct platform_device          *serial_dev;
+        struct emac_platform_data       *emac_pdata;
+        dma_addr_t                      sram_dma;
+        unsigned                        sram_len;
+};
+extern struct davinci_soc_info davinci_soc_info;
+extern void davinci_common_init(struct davinci_soc_info *soc_info);
+/* standard place to map on-chip SRAMs; they *may* support DMA */
+#define SRAM_VIRT       0xfffe0000
+#define SRAM_SIZE       SZ_128K
 #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
new file mode 100644
index 000000000000..c4d27eec8064
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -0,0 +1,57 @@
+/*
+ * TI Common Platform Interrupt Controller (cp_intc) definitions
+ *
+ * Author: Steve Chen <schen@mvista.com>
+ * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef __ASM_HARDWARE_CP_INTC_H
+#define __ASM_HARDWARE_CP_INTC_H
+#define CP_INTC_REV                     0x00
+#define CP_INTC_CTRL                    0x04
+#define CP_INTC_HOST_CTRL               0x0C
+#define CP_INTC_GLOBAL_ENABLE           0x10
+#define CP_INTC_GLOBAL_NESTING_LEVEL    0x1C
+#define CP_INTC_SYS_STAT_IDX_SET        0x20
+#define CP_INTC_SYS_STAT_IDX_CLR        0x24
+#define CP_INTC_SYS_ENABLE_IDX_SET      0x28
+#define CP_INTC_SYS_ENABLE_IDX_CLR      0x2C
+#define CP_INTC_GLOBAL_WAKEUP_ENABLE    0x30
+#define CP_INTC_HOST_ENABLE_IDX_SET     0x34
+#define CP_INTC_HOST_ENABLE_IDX_CLR     0x38
+#define CP_INTC_PACING_PRESCALE         0x40
+#define CP_INTC_VECTOR_BASE             0x50
+#define CP_INTC_VECTOR_SIZE             0x54
+#define CP_INTC_VECTOR_NULL             0x58
+#define CP_INTC_PRIO_IDX                0x80
+#define CP_INTC_PRIO_VECTOR             0x84
+#define CP_INTC_SECURE_ENABLE           0x90
+#define CP_INTC_SECURE_PRIO_IDX         0x94
+#define CP_INTC_PACING_PARAM(n)         (0x0100 + (n << 4))
+#define CP_INTC_PACING_DEC(n)           (0x0104 + (n << 4))
+#define CP_INTC_PACING_MAP(n)           (0x0108 + (n << 4))
+#define CP_INTC_SYS_RAW_STAT(n)         (0x0200 + (n << 2))
+#define CP_INTC_SYS_STAT_CLR(n)         (0x0280 + (n << 2))
+#define CP_INTC_SYS_ENABLE_SET(n)       (0x0300 + (n << 2))
+#define CP_INTC_SYS_ENABLE_CLR(n)       (0x0380 + (n << 2))
+#define CP_INTC_CHAN_MAP(n)             (0x0400 + (n << 2))
+#define CP_INTC_HOST_MAP(n)             (0x0800 + (n << 2))
+#define CP_INTC_HOST_PRIO_IDX(n)        (0x0900 + (n << 2))
+#define CP_INTC_SYS_POLARITY(n)         (0x0D00 + (n << 2))
+#define CP_INTC_SYS_TYPE(n)             (0x0D80 + (n << 2))
+#define CP_INTC_WAKEUP_ENABLE(n)        (0x0E00 + (n << 2))
+#define CP_INTC_DEBUG_SELECT(n)         (0x0F00 + (n << 2))
+#define CP_INTC_SYS_SECURE_ENABLE(n)    (0x1000 + (n << 2))
+#define CP_INTC_HOST_NESTING_LEVEL(n)   (0x1100 + (n << 2))
+#define CP_INTC_HOST_ENABLE(n)          (0x1500 + (n << 2))
+#define CP_INTC_HOST_PRIO_VECTOR(n)     (0x1600 + (n << 2))
+#define CP_INTC_VECTOR_ADDR(n)          (0x2000 + (n << 2))
+void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
+                         u8 *irq_prio);
+#endif  /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 27cfb1b3a662..d12a5ed2959a 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -16,17 +16,30 @@
 #ifndef _ASM_ARCH_CPU_H
 #define _ASM_ARCH_CPU_H
-extern unsigned int davinci_rev(void);
+#include <mach/common.h>
-#define IS_DAVINCI_CPU(type, id)                        \
+struct davinci_id {
-static inline int is_davinci_dm ##type(void)            \
+        u8      variant;        /* JTAG ID bits 31:28 */
-{                                                       \
+        u16     part_no;        /* JTAG ID bits 27:12 */
-        return (davinci_rev() == (id)) ? 1 : 0;         \
+        u16     manufacturer;   /* JTAG ID bits 11:1 */
+        u32     cpu_id;
+        char    *name;
+};
+/* Can use lower 16 bits of cpu id  for a variant when required */
+#define DAVINCI_CPU_ID_DM6446           0x64460000
+#define DAVINCI_CPU_ID_DM6467           0x64670000
+#define DAVINCI_CPU_ID_DM355            0x03550000
+#define IS_DAVINCI_CPU(type, id)                                        \
+static inline int is_davinci_ ##type(void)                              \
+{                                                                       \
+        return (davinci_soc_info.cpu_id == (id));                       \
 }
-IS_DAVINCI_CPU(644x, 0x6446)
+IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
-IS_DAVINCI_CPU(646x, 0x6467)
+IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
-IS_DAVINCI_CPU(355, 0x355)
+IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
 #ifdef CONFIG_ARCH_DAVINCI_DM644x
 #define cpu_is_davinci_dm644x() is_davinci_dm644x()
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index e6c0f0d5d062..de3fc2182b47 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -9,6 +9,16 @@
 * or implied.
 */
+/* Modifications
+ * Jan 2009     Chaithrika U S  Added senduart, busyuart, waituart
+ *                              macros, based on debug-8250.S file
+ *                              but using 32-bit accesses required for
+ *                              some davinci devices.
+ */
+#include <linux/serial_reg.h>
+#define UART_SHIFT      2
                .macro addruart, rx
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
@@ -17,5 +27,22 @@
                orr     \rx, \rx, #0x00c20000   @ UART 0
                .endm
-#define UART_SHIFT      2
+                .macro  senduart,rd,rx
-#include <asm/hardware/debug-8250.S>
+                str     \rd, [\rx, #UART_TX << UART_SHIFT]
+                .endm
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #UART_LSR << UART_SHIFT]
+                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                bne     1002b
+                .endm
+                .macro  waituart,rd,rx
+#ifdef FLOW_CONTROL
+1001:           ldr     \rd, [\rx, #UART_MSR << UART_SHIFT]
+                tst     \rd, #UART_MSR_CTS
+                beq     1001b
+#endif
+                .endm
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
new file mode 100644
index 000000000000..54903b72438e
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -0,0 +1,22 @@
+/*
+ * Chip specific defines for DM355 SoC
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DM355_H
+#define __ASM_ARCH_DM355_H
+#include <mach/hardware.h>
+struct spi_board_info;
+void __init dm355_init(void);
+void dm355_init_spi0(unsigned chipselect_mask,
+                struct spi_board_info *info, unsigned len);
+#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 3dcb9f4e58b4..15d42b92a8c9 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -24,6 +24,7 @@
 #include <linux/platform_device.h>
 #include <mach/hardware.h>
+#include <mach/emac.h>
 #define DM644X_EMAC_BASE                (0x01C80000)
 #define DM644X_EMAC_CNTRL_OFFSET        (0x0000)
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
new file mode 100644
index 000000000000..1fc764c8646e
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -0,0 +1,26 @@
+/*
+ * Chip specific defines for DM646x SoC
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DM646X_H
+#define __ASM_ARCH_DM646X_H
+#include <mach/hardware.h>
+#include <mach/emac.h>
+#define DM646X_EMAC_BASE                (0x01C80000)
+#define DM646X_EMAC_CNTRL_OFFSET        (0x0000)
+#define DM646X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
+#define DM646X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
+#define DM646X_EMAC_MDIO_OFFSET         (0x4000)
+#define DM646X_EMAC_CNTRL_RAM_SIZE      (0x2000)
+void __init dm646x_init(void);
+#endif /* __ASM_ARCH_DM646X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index f6fc5396dafc..24a379239d7f 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -208,10 +208,6 @@ void edma_clear_event(unsigned channel);
 void edma_pause(unsigned channel);
 void edma_resume(unsigned channel);
-/* UNRELATED TO DMA */
-int davinci_alloc_iram(unsigned size);
-void davinci_free_iram(unsigned addr, unsigned size);
 /* platform_data for EDMA driver */
 struct edma_soc_info {
diff --git a/arch/arm/mach-davinci/include/mach/emac.h b/arch/arm/mach-davinci/include/mach/emac.h
new file mode 100644
index 000000000000..beff4fb7c845
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/emac.h
@@ -0,0 +1,36 @@
+/*
+ * TI DaVinci EMAC platform support
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef _MACH_DAVINCI_EMAC_H
+#define _MACH_DAVINCI_EMAC_H
+#include <linux/if_ether.h>
+#include <linux/memory.h>
+struct emac_platform_data {
+        char mac_addr[ETH_ALEN];
+        u32 ctrl_reg_offset;
+        u32 ctrl_mod_reg_offset;
+        u32 ctrl_ram_offset;
+        u32 mdio_reg_offset;
+        u32 ctrl_ram_size;
+        u32 phy_mask;
+        u32 mdio_max_freq;
+        u8 rmii_en;
+        u8 version;
+};
+enum {
+        EMAC_VERSION_1, /* DM644x */
+        EMAC_VERSION_2, /* DM646x */
+};
+void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context);
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 039b84f933b3..fbdebc7cb409 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -15,17 +15,36 @@
                .endm
                .macro  get_irqnr_preamble, base, tmp
-                ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
+                ldr \base, =davinci_intc_base
+                ldr \base, [\base]
                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
+                ldr \tmp, =davinci_intc_type
+                ldr \tmp, [\tmp]
+                cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
+                beq 1001f
+#endif
+#if defined(CONFIG_AINTC)
                ldr \tmp, [\base, #0x14]
-                mov \tmp, \tmp, lsr #2
+                movs \tmp, \tmp, lsr #2
                sub \irqnr, \tmp, #1
-                cmp \tmp, #0
+                b 1002f
+#endif
+#if defined(CONFIG_CP_INTC)
+1001:           ldr \irqnr, [\base, #0x80] /* get irq number */
+                and \irqnr, \irqnr, #0xff  /* irq is in bits 0-9 */
+                mov \tmp, \irqnr, lsr #3
+                and \tmp, \tmp, #0xfc
+                add \tmp, \tmp, #0x280 /* get the register offset */
+                ldr \irqstat, [\base, \tmp] /* get the intc status */
+                cmp \irqstat, #0x0
+#endif
+1002:
                .endm
                .macro  irq_prio_table
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index efe3281364e6..ae0745568316 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -17,6 +17,7 @@
 #include <asm-generic/gpio.h>
 #include <mach/irqs.h>
+#include <mach/common.h>
 #define DAVINCI_GPIO_BASE 0x01C67000
@@ -67,15 +68,16 @@ static inline struct gpio_controller *__iomem
 __gpio_to_controller(unsigned gpio)
 {
        void *__iomem ptr;
+        void __iomem *base = davinci_soc_info.gpio_base;
        if (gpio < 32 * 1)
-                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
+                ptr = base + 0x10;
        else if (gpio < 32 * 2)
-                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
+                ptr = base + 0x38;
        else if (gpio < 32 * 3)
-                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
+                ptr = base + 0x60;
        else if (gpio < 32 * 4)
-                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88);
+                ptr = base + 0x88;
        else
                ptr = NULL;
        return ptr;
@@ -142,13 +144,13 @@ static inline int gpio_to_irq(unsigned gpio)
 {
        if (gpio >= DAVINCI_N_GPIO)
                return -EINVAL;
-        return DAVINCI_N_AINTC_IRQ + gpio;
+        return davinci_soc_info.intc_irq_num + gpio;
 }
 static inline int irq_to_gpio(unsigned irq)
 {
        /* caller guarantees gpio_to_irq() succeeded */
-        return irq - DAVINCI_N_AINTC_IRQ;
+        return irq - davinci_soc_info.intc_irq_num;
 }
 #endif                          /* __DAVINCI_GPIO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 18066074c995..bc5d6aaa69a3 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -30,6 +30,9 @@
 /* Base address */
 #define DAVINCI_ARM_INTC_BASE 0x01C48000
+#define DAVINCI_INTC_TYPE_AINTC         0
+#define DAVINCI_INTC_TYPE_CP_INTC       1
 /* Interrupt lines */
 #define IRQ_VDINT0       0
 #define IRQ_VDINT1       1
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 86c25c7f3ce3..c712c7cdf38f 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -21,7 +21,6 @@
 * Definitions
 **************************************************************************/
 #define DAVINCI_DDR_BASE    0x80000000
-#define DAVINCI_IRAM_BASE   0x00008000 /* ARM Internal RAM */
 #define PHYS_OFFSET DAVINCI_DDR_BASE
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h
new file mode 100644
index 000000000000..5a85e24f3673
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/mmc.h
@@ -0,0 +1,33 @@
+/*
+ *  Board-specific MMC configuration
+ */
+#ifndef _DAVINCI_MMC_H
+#define _DAVINCI_MMC_H
+#include <linux/types.h>
+#include <linux/mmc/host.h>
+struct davinci_mmc_config {
+        /* get_cd()/get_wp() may sleep */
+        int     (*get_cd)(int module);
+        int     (*get_ro)(int module);
+        /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */
+        u8      wires;
+        u32     max_freq;
+        /* any additional host capabilities: OR'd in to mmc->f_caps */
+        u32     caps;
+        /* Version of the MMC/SD controller */
+        u8      version;
+};
+void davinci_setup_mmc(int module, struct davinci_mmc_config *config);
+enum {
+        MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
+        MMC_CTLR_VERSION_2,     /* DA830 */
+};
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index bae22cb3e27b..27378458542f 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -19,16 +19,6 @@
 #ifndef __INC_MACH_MUX_H
 #define __INC_MACH_MUX_H
-/* System module registers */
-#define PINMUX0                 0x00
-#define PINMUX1                 0x04
-/* dm355 only */
-#define PINMUX2                 0x08
-#define PINMUX3                 0x0c
-#define PINMUX4                 0x10
-#define INTMUX                  0x18
-#define EVTMUX                  0x1c
 struct mux_config {
        const char *name;
        const char *mux_reg_name;
@@ -168,15 +158,9 @@ enum davinci_dm355_index {
 #ifdef CONFIG_DAVINCI_MUX
 /* setup pin muxing */
-extern void davinci_mux_init(void);
-extern int davinci_mux_register(const struct mux_config *pins,
-                                unsigned long size);
 extern int davinci_cfg_reg(unsigned long reg_cfg);
 #else
 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
-static inline void davinci_mux_init(void) {}
-static inline int davinci_mux_register(const struct mux_config *pins,
-                                       unsigned long size) { return 0; }
 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 55a90d419fac..ab8a2586d1cc 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -27,6 +27,8 @@
 #ifndef __ASM_ARCH_PSC_H
 #define __ASM_ARCH_PSC_H
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE    0x01C41000
 /* Power and Sleep Controller (PSC) Domains */
 #define DAVINCI_GPSC_ARMDOMAIN      0
 #define DAVINCI_GPSC_DSPDOMAIN      1
@@ -116,8 +118,8 @@
 #define DM646X_LPSC_TIMER1         35
 #define DM646X_LPSC_ARM_INTC       45
-extern int davinci_psc_is_clk_active(unsigned int id);
+extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
-extern void davinci_psc_config(unsigned int domain, unsigned int id,
+extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-                               char enable);
+                unsigned int id, char enable);
 #endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 632847d74a1c..794fa5cf93c1 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -18,8 +18,6 @@
 #define DAVINCI_UART1_BASE      (IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE      (IO_PHYS + 0x20800)
-#define DM355_UART2_BASE        (IO_PHYS + 0x206000)
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU             0x0c
 #define UART_DM646X_SCR                 0x10
@@ -30,6 +28,6 @@ struct davinci_uart_config {
        unsigned int enabled_uarts;
 };
-extern void davinci_serial_init(struct davinci_uart_config *);
+extern int davinci_serial_init(struct davinci_uart_config *);
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h
new file mode 100644
index 000000000000..111f7cc71e07
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/sram.h
@@ -0,0 +1,27 @@
+/*
+ * mach/sram.h - DaVinci simple SRAM allocator
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_SRAM_H
+#define __MACH_SRAM_H
+/* ARBITRARY:  SRAM allocations are multiples of this 2^N size */
+#define SRAM_GRANULARITY        512
+/*
+ * SRAM allocations return a CPU virtual address, or NULL on error.
+ * If a DMA address is requested and the SRAM supports DMA, its
+ * mapped address is also returned.
+ *
+ * Errors include SRAM memory not being available, and requesting
+ * DMA mapped SRAM on systems which don't allow that.
+ */
+extern void *sram_alloc(size_t len, dma_addr_t *dma);
+extern void sram_free(void *addr, size_t len);
+#endif /* __MACH_SRAM_H */
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
new file mode 100644
index 000000000000..1c971d8d8ba8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -0,0 +1,35 @@
+/*
+ * Local header file for DaVinci time code.
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
+#define __ARCH_ARM_MACH_DAVINCI_TIME_H
+#define DAVINCI_TIMER0_BASE             (IO_PHYS + 0x21400)
+#define DAVINCI_TIMER1_BASE             (IO_PHYS + 0x21800)
+#define DAVINCI_WDOG_BASE               (IO_PHYS + 0x21C00)
+enum {
+        T0_BOT,
+        T0_TOP,
+        T1_BOT,
+        T1_TOP,
+        NUM_TIMERS
+};
+#define IS_TIMER1(id)           (id & 0x2)
+#define IS_TIMER0(id)           (!IS_TIMER1(id))
+#define IS_TIMER_TOP(id)        ((id & 0x1))
+#define IS_TIMER_BOT(id)        (!IS_TIMER_TOP(id))
+#define ID_TO_TIMER(id)         (IS_TIMER1(id) != 0)
+extern struct davinci_timer_instance davinci_timer_instance[];
+#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 8c165def37b6..1e27475f9a23 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -13,11 +13,24 @@
 #include <linux/serial_reg.h>
 #include <mach/serial.h>
+#include <asm/mach-types.h>
+extern unsigned int __machine_arch_type;
+static u32 *uart;
+static u32 *get_uart_base(void)
+{
+        /* Add logic here for new platforms, using __macine_arch_type */
+        return (u32 *)DAVINCI_UART0_BASE;
+}
 /* PORT_16C550A, in polled non-fifo mode */
 static void putc(char c)
 {
-        volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE;
+        if (!uart)
+                uart = get_uart_base();
        while (!(uart[UART_LSR] & UART_LSR_THRE))
                barrier();
@@ -26,7 +39,9 @@ static void putc(char c)
 static inline void flush(void)
 {
-        volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE;
+        if (!uart)
+                uart = get_uart_base();
        while (!(uart[UART_LSR] & UART_LSR_THRE))
                barrier();
 }
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index a548abb513e2..49912b48b1b0 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -9,47 +9,9 @@
 */
 #include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/io.h>
 #include <asm/tlb.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-#include <mach/clock.h>
-extern void davinci_check_revision(void);
-/*
- * The machine specific code may provide the extra mapping besides the
- * default mapping provided here.
- */
-static struct map_desc davinci_io_desc[] __initdata = {
-        {
-                .virtual        = IO_VIRT,
-                .pfn            = __phys_to_pfn(IO_PHYS),
-                .length         = IO_SIZE,
-                .type           = MT_DEVICE
-        },
-};
-void __init davinci_map_common_io(void)
-{
-        iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc));
-        /* Normally devicemaps_init() would flush caches and tlb after
-         * mdesc->map_io(), but we must also do it here because of the CPU
-         * revision check below.
-         */
-        local_flush_tlb_all();
-        flush_cache_all();
-        /* We want to check CPU revision early for cpu_is_xxxx() macros.
-         * IO space mapping must be initialized before we can do that.
-         */
-        davinci_check_revision();
-}
 #define BETWEEN(p, st, sz)      ((p) >= (st) && (p) < ((st) + (sz)))
 #define XLATE(p, pst, vst)      ((void __iomem *)((p) - (pst) + (vst)))
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 5a324c90e291..af92ffee8471 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -26,6 +26,7 @@
 #include <mach/hardware.h>
 #include <mach/cputype.h>
+#include <mach/common.h>
 #include <asm/mach/irq.h>
 #define IRQ_BIT(irq)            ((irq) & 0x1f)
@@ -41,18 +42,14 @@
 #define IRQ_INTPRI0_REG_OFFSET  0x0030
 #define IRQ_INTPRI7_REG_OFFSET  0x004C
-const u8 *davinci_def_priorities;
-#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
 static inline unsigned int davinci_irq_readl(int offset)
 {
-        return __raw_readl(INTC_BASE + offset);
+        return __raw_readl(davinci_intc_base + offset);
 }
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
-        __raw_writel(value, INTC_BASE + offset);
+        __raw_writel(value, davinci_intc_base + offset);
 }
 /* Disable interrupt */
@@ -113,217 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = {
        .unmask = davinci_unmask_irq,
 };
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
-        [IRQ_VDINT0]            = 2,
-        [IRQ_VDINT1]            = 6,
-        [IRQ_VDINT2]            = 6,
-        [IRQ_HISTINT]           = 6,
-        [IRQ_H3AINT]            = 6,
-        [IRQ_PRVUINT]           = 6,
-        [IRQ_RSZINT]            = 6,
-        [7]                     = 7,
-        [IRQ_VENCINT]           = 6,
-        [IRQ_ASQINT]            = 6,
-        [IRQ_IMXINT]            = 6,
-        [IRQ_VLCDINT]           = 6,
-        [IRQ_USBINT]            = 4,
-        [IRQ_EMACINT]           = 4,
-        [14]                    = 7,
-        [15]                    = 7,
-        [IRQ_CCINT0]            = 5,    /* dma */
-        [IRQ_CCERRINT]          = 5,    /* dma */
-        [IRQ_TCERRINT0]         = 5,    /* dma */
-        [IRQ_TCERRINT]          = 5,    /* dma */
-        [IRQ_PSCIN]             = 7,
-        [21]                    = 7,
-        [IRQ_IDE]               = 4,
-        [23]                    = 7,
-        [IRQ_MBXINT]            = 7,
-        [IRQ_MBRINT]            = 7,
-        [IRQ_MMCINT]            = 7,
-        [IRQ_SDIOINT]           = 7,
-        [28]                    = 7,
-        [IRQ_DDRINT]            = 7,
-        [IRQ_AEMIFINT]          = 7,
-        [IRQ_VLQINT]            = 4,
-        [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
-        [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
-        [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
-        [IRQ_TINT1_TINT34]      = 7,    /* system tick */
-        [IRQ_PWMINT0]           = 7,
-        [IRQ_PWMINT1]           = 7,
-        [IRQ_PWMINT2]           = 7,
-        [IRQ_I2C]               = 3,
-        [IRQ_UARTINT0]          = 3,
-        [IRQ_UARTINT1]          = 3,
-        [IRQ_UARTINT2]          = 3,
-        [IRQ_SPINT0]            = 3,
-        [IRQ_SPINT1]            = 3,
-        [45]                    = 7,
-        [IRQ_DSP2ARM0]          = 4,
-        [IRQ_DSP2ARM1]          = 4,
-        [IRQ_GPIO0]             = 7,
-        [IRQ_GPIO1]             = 7,
-        [IRQ_GPIO2]             = 7,
-        [IRQ_GPIO3]             = 7,
-        [IRQ_GPIO4]             = 7,
-        [IRQ_GPIO5]             = 7,
-        [IRQ_GPIO6]             = 7,
-        [IRQ_GPIO7]             = 7,
-        [IRQ_GPIOBNK0]          = 7,
-        [IRQ_GPIOBNK1]          = 7,
-        [IRQ_GPIOBNK2]          = 7,
-        [IRQ_GPIOBNK3]          = 7,
-        [IRQ_GPIOBNK4]          = 7,
-        [IRQ_COMMTX]            = 7,
-        [IRQ_COMMRX]            = 7,
-        [IRQ_EMUINT]            = 7,
-};
-static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
-        [IRQ_DM646X_VP_VERTINT0]        = 7,
-        [IRQ_DM646X_VP_VERTINT1]        = 7,
-        [IRQ_DM646X_VP_VERTINT2]        = 7,
-        [IRQ_DM646X_VP_VERTINT3]        = 7,
-        [IRQ_DM646X_VP_ERRINT]          = 7,
-        [IRQ_DM646X_RESERVED_1]         = 7,
-        [IRQ_DM646X_RESERVED_2]         = 7,
-        [IRQ_DM646X_WDINT]              = 7,
-        [IRQ_DM646X_CRGENINT0]          = 7,
-        [IRQ_DM646X_CRGENINT1]          = 7,
-        [IRQ_DM646X_TSIFINT0]           = 7,
-        [IRQ_DM646X_TSIFINT1]           = 7,
-        [IRQ_DM646X_VDCEINT]            = 7,
-        [IRQ_DM646X_USBINT]             = 7,
-        [IRQ_DM646X_USBDMAINT]          = 7,
-        [IRQ_DM646X_PCIINT]             = 7,
-        [IRQ_CCINT0]                    = 7,    /* dma */
-        [IRQ_CCERRINT]                  = 7,    /* dma */
-        [IRQ_TCERRINT0]                 = 7,    /* dma */
-        [IRQ_TCERRINT]                  = 7,    /* dma */
-        [IRQ_DM646X_TCERRINT2]          = 7,
-        [IRQ_DM646X_TCERRINT3]          = 7,
-        [IRQ_DM646X_IDE]                = 7,
-        [IRQ_DM646X_HPIINT]             = 7,
-        [IRQ_DM646X_EMACRXTHINT]        = 7,
-        [IRQ_DM646X_EMACRXINT]          = 7,
-        [IRQ_DM646X_EMACTXINT]          = 7,
-        [IRQ_DM646X_EMACMISCINT]        = 7,
-        [IRQ_DM646X_MCASP0TXINT]        = 7,
-        [IRQ_DM646X_MCASP0RXINT]        = 7,
-        [IRQ_AEMIFINT]                  = 7,
-        [IRQ_DM646X_RESERVED_3]         = 7,
-        [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
-        [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
-        [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
-        [IRQ_TINT1_TINT34]              = 7,    /* system tick */
-        [IRQ_PWMINT0]                   = 7,
-        [IRQ_PWMINT1]                   = 7,
-        [IRQ_DM646X_VLQINT]             = 7,
-        [IRQ_I2C]                       = 7,
-        [IRQ_UARTINT0]                  = 7,
-        [IRQ_UARTINT1]                  = 7,
-        [IRQ_DM646X_UARTINT2]           = 7,
-        [IRQ_DM646X_SPINT0]             = 7,
-        [IRQ_DM646X_SPINT1]             = 7,
-        [IRQ_DM646X_DSP2ARMINT]         = 7,
-        [IRQ_DM646X_RESERVED_4]         = 7,
-        [IRQ_DM646X_PSCINT]             = 7,
-        [IRQ_DM646X_GPIO0]              = 7,
-        [IRQ_DM646X_GPIO1]              = 7,
-        [IRQ_DM646X_GPIO2]              = 7,
-        [IRQ_DM646X_GPIO3]              = 7,
-        [IRQ_DM646X_GPIO4]              = 7,
-        [IRQ_DM646X_GPIO5]              = 7,
-        [IRQ_DM646X_GPIO6]              = 7,
-        [IRQ_DM646X_GPIO7]              = 7,
-        [IRQ_DM646X_GPIOBNK0]           = 7,
-        [IRQ_DM646X_GPIOBNK1]           = 7,
-        [IRQ_DM646X_GPIOBNK2]           = 7,
-        [IRQ_DM646X_DDRINT]             = 7,
-        [IRQ_DM646X_AEMIFINT]           = 7,
-        [IRQ_COMMTX]                    = 7,
-        [IRQ_COMMRX]                    = 7,
-        [IRQ_EMUINT]                    = 7,
-};
-static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
-        [IRQ_DM355_CCDC_VDINT0]         = 2,
-        [IRQ_DM355_CCDC_VDINT1]         = 6,
-        [IRQ_DM355_CCDC_VDINT2]         = 6,
-        [IRQ_DM355_IPIPE_HST]           = 6,
-        [IRQ_DM355_H3AINT]              = 6,
-        [IRQ_DM355_IPIPE_SDR]           = 6,
-        [IRQ_DM355_IPIPEIFINT]          = 6,
-        [IRQ_DM355_OSDINT]              = 7,
-        [IRQ_DM355_VENCINT]             = 6,
-        [IRQ_ASQINT]                    = 6,
-        [IRQ_IMXINT]                    = 6,
-        [IRQ_USBINT]                    = 4,
-        [IRQ_DM355_RTOINT]              = 4,
-        [IRQ_DM355_UARTINT2]            = 7,
-        [IRQ_DM355_TINT6]               = 7,
-        [IRQ_CCINT0]                    = 5,    /* dma */
-        [IRQ_CCERRINT]                  = 5,    /* dma */
-        [IRQ_TCERRINT0]                 = 5,    /* dma */
-        [IRQ_TCERRINT]                  = 5,    /* dma */
-        [IRQ_DM355_SPINT2_1]            = 7,
-        [IRQ_DM355_TINT7]               = 4,
-        [IRQ_DM355_SDIOINT0]            = 7,
-        [IRQ_MBXINT]                    = 7,
-        [IRQ_MBRINT]                    = 7,
-        [IRQ_MMCINT]                    = 7,
-        [IRQ_DM355_MMCINT1]             = 7,
-        [IRQ_DM355_PWMINT3]             = 7,
-        [IRQ_DDRINT]                    = 7,
-        [IRQ_AEMIFINT]                  = 7,
-        [IRQ_DM355_SDIOINT1]            = 4,
-        [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
-        [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
-        [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
-        [IRQ_TINT1_TINT34]              = 7,    /* system tick */
-        [IRQ_PWMINT0]                   = 7,
-        [IRQ_PWMINT1]                   = 7,
-        [IRQ_PWMINT2]                   = 7,
-        [IRQ_I2C]                       = 3,
-        [IRQ_UARTINT0]                  = 3,
-        [IRQ_UARTINT1]                  = 3,
-        [IRQ_DM355_SPINT0_0]            = 3,
-        [IRQ_DM355_SPINT0_1]            = 3,
-        [IRQ_DM355_GPIO0]               = 3,
-        [IRQ_DM355_GPIO1]               = 7,
-        [IRQ_DM355_GPIO2]               = 4,
-        [IRQ_DM355_GPIO3]               = 4,
-        [IRQ_DM355_GPIO4]               = 7,
-        [IRQ_DM355_GPIO5]               = 7,
-        [IRQ_DM355_GPIO6]               = 7,
-        [IRQ_DM355_GPIO7]               = 7,
-        [IRQ_DM355_GPIO8]               = 7,
-        [IRQ_DM355_GPIO9]               = 7,
-        [IRQ_DM355_GPIOBNK0]            = 7,
-        [IRQ_DM355_GPIOBNK1]            = 7,
-        [IRQ_DM355_GPIOBNK2]            = 7,
-        [IRQ_DM355_GPIOBNK3]            = 7,
-        [IRQ_DM355_GPIOBNK4]            = 7,
-        [IRQ_DM355_GPIOBNK5]            = 7,
-        [IRQ_DM355_GPIOBNK6]            = 7,
-        [IRQ_COMMTX]                    = 7,
-        [IRQ_COMMRX]                    = 7,
-        [IRQ_EMUINT]                    = 7,
-};
 /* ARM Interrupt Controller Initialization */
 void __init davinci_irq_init(void)
 {
        unsigned i;
+        const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
-        if (cpu_is_davinci_dm644x())
-                davinci_def_priorities = dm644x_default_priorities;
-        else if (cpu_is_davinci_dm646x())
-                davinci_def_priorities = dm646x_default_priorities;
-        else if (cpu_is_davinci_dm355())
-                davinci_def_priorities = dm355_default_priorities;
        /* Clear all interrupt requests */
        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index bbba0b247a44..d310f579aa85 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,18 +21,7 @@
 #include <mach/hardware.h>
 #include <mach/mux.h>
+#include <mach/common.h>
-static const struct mux_config *mux_table;
-static unsigned long pin_table_sz;
-int __init davinci_mux_register(const struct mux_config *pins,
-                                unsigned long size)
-{
-        mux_table = pins;
-        pin_table_sz = size;
-        return 0;
-}
 /*
 * Sets the DAVINCI MUX register based on the table
@@ -40,23 +29,24 @@ int __init davinci_mux_register(const struct mux_config *pins,
 int __init_or_module davinci_cfg_reg(const unsigned long index)
 {
        static DEFINE_SPINLOCK(mux_spin_lock);
-        void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        void __iomem *base = soc_info->pinmux_base;
        unsigned long flags;
        const struct mux_config *cfg;
        unsigned int reg_orig = 0, reg = 0;
        unsigned int mask, warn = 0;
-        if (!mux_table)
+        if (!soc_info->pinmux_pins)
                BUG();
-        if (index >= pin_table_sz) {
+        if (index >= soc_info->pinmux_pins_num) {
                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
-                       index, pin_table_sz);
+                       index, soc_info->pinmux_pins_num);
                dump_stack();
                return -ENODEV;
        }
-        cfg = &mux_table[index];
+        cfg = &soc_info->pinmux_pins[index];
        if (cfg->name == NULL) {
                printk(KERN_ERR "No entry for the specified index\n");
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 84171abf5f7b..a78b657e916e 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -28,8 +28,6 @@
 #include <mach/psc.h>
 #include <mach/mux.h>
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
 /* PSC register offsets */
 #define EPCPR           0x070
 #define PTCMD           0x120
@@ -42,22 +40,42 @@
 #define MDSTAT_STATE_MASK 0x1f
 /* Return nonzero iff the domain's clock is active */
-int __init davinci_psc_is_clk_active(unsigned int id)
+int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 {
-        void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
+        void __iomem *psc_base;
-        u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
+        u32 mdstat;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
+                pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
+                                (int)soc_info->psc_bases, ctlr);
+                return 0;
+        }
+        psc_base = soc_info->psc_bases[ctlr];
+        mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
        /* if clocked, state can be "Enable" or "SyncReset" */
        return mdstat & BIT(12);
 }
 /* Enable or disable a PSC domain */
-void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
+void davinci_psc_config(unsigned int domain, unsigned int ctlr,
+                unsigned int id, char enable)
 {
        u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
-        void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
+        void __iomem *psc_base;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
        u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
+        if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
+                pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
+                                (int)soc_info->psc_bases, ctlr);
+                return;
+        }
+        psc_base = soc_info->psc_bases[ctlr];
        mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
        mdctl &= ~MDSTAT_STATE_MASK;
        mdctl |= next_state;
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 695075796522..c530c7333d0a 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -33,6 +33,8 @@
 #include <mach/serial.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
+#include <mach/common.h>
 #include "clock.h"
 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
@@ -49,44 +51,6 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
        __raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
 }
-static struct plat_serial8250_port serial_platform_data[] = {
-        {
-                .mapbase        = DAVINCI_UART0_BASE,
-                .irq            = IRQ_UARTINT0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                  UPF_IOREMAP,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-        },
-        {
-                .mapbase        = DAVINCI_UART1_BASE,
-                .irq            = IRQ_UARTINT1,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                  UPF_IOREMAP,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-        },
-        {
-                .mapbase        = DAVINCI_UART2_BASE,
-                .irq            = IRQ_UARTINT2,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                  UPF_IOREMAP,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-        },
-        {
-                .flags          = 0
-        },
-};
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
-        },
-};
 static void __init davinci_serial_reset(struct plat_serial8250_port *p)
 {
        unsigned int pwremu = 0;
@@ -106,35 +70,22 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
                                 UART_DM646X_SCR_TX_WATERMARK);
 }
-void __init davinci_serial_init(struct davinci_uart_config *info)
+int __init davinci_serial_init(struct davinci_uart_config *info)
 {
        int i;
        char name[16];
        struct clk *uart_clk;
-        struct device *dev = &serial_device.dev;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        struct device *dev = &soc_info->serial_dev->dev;
+        struct plat_serial8250_port *p = dev->platform_data;
        /*
         * Make sure the serial ports are muxed on at this point.
-         * You have to mux them off in device drivers later on
+         * You have to mux them off in device drivers later on if not needed.
-         * if not needed.
         */
-        for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) {
+        for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) {
-                struct plat_serial8250_port *p = serial_platform_data + i;
+                if (!(info->enabled_uarts & (1 << i)))
-                if (!(info->enabled_uarts & (1 << i))) {
-                        p->flags = 0;
                        continue;
-                }
-                if (cpu_is_davinci_dm646x())
-                        p->iotype = UPIO_MEM32;
-                if (cpu_is_davinci_dm355()) {
-                        if (i == 2) {
-                                p->mapbase = (unsigned long)DM355_UART2_BASE;
-                                p->irq = IRQ_DM355_UARTINT2;
-                        }
-                }
                sprintf(name, "uart%d", i);
                uart_clk = clk_get(dev, name);
@@ -147,11 +98,6 @@ void __init davinci_serial_init(struct davinci_uart_config *info)
                        davinci_serial_reset(p);
                }
        }
-}
-static int __init davinci_init(void)
+        return platform_device_register(soc_info->serial_dev);
-{
-        return platform_device_register(&serial_device);
 }
-arch_initcall(davinci_init);
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
new file mode 100644
index 000000000000..db54b2a66b4d
--- /dev/null
+++ b/arch/arm/mach-davinci/sram.c
@@ -0,0 +1,74 @@
+/*
+ * mach-davinci/sram.c - DaVinci simple SRAM allocator
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/genalloc.h>
+#include <mach/common.h>
+#include <mach/memory.h>
+#include <mach/sram.h>
+static struct gen_pool *sram_pool;
+void *sram_alloc(size_t len, dma_addr_t *dma)
+{
+        unsigned long vaddr;
+        dma_addr_t dma_base = davinci_soc_info.sram_dma;
+        if (dma)
+                *dma = 0;
+        if (!sram_pool || (dma && !dma_base))
+                return NULL;
+        vaddr = gen_pool_alloc(sram_pool, len);
+        if (!vaddr)
+                return NULL;
+        if (dma)
+                *dma = dma_base + (vaddr - SRAM_VIRT);
+        return (void *)vaddr;
+}
+EXPORT_SYMBOL(sram_alloc);
+void sram_free(void *addr, size_t len)
+{
+        gen_pool_free(sram_pool, (unsigned long) addr, len);
+}
+EXPORT_SYMBOL(sram_free);
+/*
+ * REVISIT This supports CPU and DMA access to/from SRAM, but it
+ * doesn't (yet?) support some other notable uses of SRAM:  as TCM
+ * for data and/or instructions; and holding code needed to enter
+ * and exit suspend states (while DRAM can't be used).
+ */
+static int __init sram_init(void)
+{
+        unsigned len = davinci_soc_info.sram_len;
+        int status = 0;
+        if (len) {
+                len = min(len, SRAM_SIZE);
+                sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1);
+                if (!sram_pool)
+                        status = -ENOMEM;
+        }
+        if (sram_pool)
+                status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1);
+        WARN_ON(status < 0);
+        return status;
+}
+core_initcall(sram_init);
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 494e01bff5c3..0884ca57bfb0 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -19,6 +19,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 #include <mach/hardware.h>
 #include <asm/system.h>
@@ -28,52 +29,41 @@
 #include <asm/errno.h>
 #include <mach/io.h>
 #include <mach/cputype.h>
+#include <mach/time.h>
 #include "clock.h"
 static struct clock_event_device clockevent_davinci;
 static unsigned int davinci_clock_tick_rate;
-#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
-#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
-#define DAVINCI_WDOG_BASE   (IO_PHYS + 0x21C00)
-enum {
-        T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS,
-};
-#define IS_TIMER1(id)    (id & 0x2)
-#define IS_TIMER0(id)    (!IS_TIMER1(id))
-#define IS_TIMER_TOP(id) ((id & 0x1))
-#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
-static int timer_irqs[NUM_TIMERS] = {
-        IRQ_TINT0_TINT12,
-        IRQ_TINT0_TINT34,
-        IRQ_TINT1_TINT12,
-        IRQ_TINT1_TINT34,
-};
 /*
 * This driver configures the 2 64-bit count-up timers as 4 independent
 * 32-bit count-up timers used as follows:
- *
- * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
- * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
- * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
- * T1_TOP: Timer 1, top   :  <unused>
 */
-#define TID_CLOCKEVENT  T0_BOT
-#define TID_CLOCKSOURCE T0_TOP
+enum {
+        TID_CLOCKEVENT,
+        TID_CLOCKSOURCE,
+};
 /* Timer register offsets */
-#define PID12                        0x0
+#define PID12                   0x0
-#define TIM12                        0x10
+#define TIM12                   0x10
-#define TIM34                        0x14
+#define TIM34                   0x14
-#define PRD12                        0x18
+#define PRD12                   0x18
-#define PRD34                        0x1c
+#define PRD34                   0x1c
-#define TCR                          0x20
+#define TCR                     0x20
-#define TGCR                         0x24
+#define TGCR                    0x24
-#define WDTCR                        0x28
+#define WDTCR                   0x28
+/* Offsets of the 8 compare registers */
+#define CMP12_0                 0x60
+#define CMP12_1                 0x64
+#define CMP12_2                 0x68
+#define CMP12_3                 0x6c
+#define CMP12_4                 0x70
+#define CMP12_5                 0x74
+#define CMP12_6                 0x78
+#define CMP12_7                 0x7c
 /* Timer register bitfields */
 #define TCR_ENAMODE_DISABLE          0x0
@@ -105,6 +95,7 @@ struct timer_s {
        unsigned int id;
        unsigned long period;
        unsigned long opts;
+        unsigned long flags;
        void __iomem *base;
        unsigned long tim_off;
        unsigned long prd_off;
@@ -114,30 +105,58 @@ struct timer_s {
 static struct timer_s timers[];
 /* values for 'opts' field of struct timer_s */
-#define TIMER_OPTS_DISABLED   0x00
+#define TIMER_OPTS_DISABLED             0x01
-#define TIMER_OPTS_ONESHOT    0x01
+#define TIMER_OPTS_ONESHOT              0x02
-#define TIMER_OPTS_PERIODIC   0x02
+#define TIMER_OPTS_PERIODIC             0x04
+#define TIMER_OPTS_STATE_MASK           0x07
+#define TIMER_OPTS_USE_COMPARE          0x80000000
+#define USING_COMPARE(t)                ((t)->opts & TIMER_OPTS_USE_COMPARE)
+static char *id_to_name[] = {
+        [T0_BOT]        = "timer0_0",
+        [T0_TOP]        = "timer0_1",
+        [T1_BOT]        = "timer1_0",
+        [T1_TOP]        = "timer1_1",
+};
 static int timer32_config(struct timer_s *t)
 {
-        u32 tcr = __raw_readl(t->base + TCR);
+        u32 tcr;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        /* disable timer */
-        tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
+        if (USING_COMPARE(t)) {
-        __raw_writel(tcr, t->base + TCR);
+                struct davinci_timer_instance *dtip =
+                                soc_info->timer_info->timers;
-        /* reset counter to zero, set new period */
+                int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
-        __raw_writel(0, t->base + t->tim_off);
-        __raw_writel(t->period, t->base + t->prd_off);
+                /*
+                 * Next interrupt should be the current time reg value plus
-        /* Set enable mode */
+                 * the new period (using 32-bit unsigned addition/wrapping
-        if (t->opts & TIMER_OPTS_ONESHOT) {
+                 * to 0 on overflow).  This assumes that the clocksource
-                tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
+                 * is setup to count to 2^32-1 before wrapping around to 0.
-        } else if (t->opts & TIMER_OPTS_PERIODIC) {
+                 */
-                tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
+                __raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
+                        t->base + dtip[event_timer].cmp_off);
+        } else {
+                tcr = __raw_readl(t->base + TCR);
+                /* disable timer */
+                tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
+                __raw_writel(tcr, t->base + TCR);
+                /* reset counter to zero, set new period */
+                __raw_writel(0, t->base + t->tim_off);
+                __raw_writel(t->period, t->base + t->prd_off);
+                /* Set enable mode */
+                if (t->opts & TIMER_OPTS_ONESHOT)
+                        tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
+                else if (t->opts & TIMER_OPTS_PERIODIC)
+                        tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
+                __raw_writel(tcr, t->base + TCR);
        }
-        __raw_writel(tcr, t->base + TCR);
        return 0;
 }
@@ -182,13 +201,14 @@ static struct timer_s timers[] = {
 static void __init timer_init(void)
 {
-        u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
        int i;
        /* Global init of each 64-bit timer as a whole */
        for(i=0; i<2; i++) {
                u32 tgcr;
-                void __iomem *base = IO_ADDRESS(phys_bases[i]);
+                void __iomem *base = dtip[i].base;
                /* Disabled, Internal clock source */
                __raw_writel(0, base + TCR);
@@ -214,33 +234,33 @@ static void __init timer_init(void)
        /* Init of each timer as a 32-bit timer */
        for (i=0; i< ARRAY_SIZE(timers); i++) {
                struct timer_s *t = &timers[i];
-                u32 phys_base;
+                int timer = ID_TO_TIMER(t->id);
+                u32 irq;
-                if (t->name) {
-                        t->id = i;
+                t->base = dtip[timer].base;
-                        phys_base = (IS_TIMER1(t->id) ?
-                               DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
+                if (IS_TIMER_BOT(t->id)) {
-                        t->base = IO_ADDRESS(phys_base);
+                        t->enamode_shift = 6;
+                        t->tim_off = TIM12;
-                        if (IS_TIMER_BOT(t->id)) {
+                        t->prd_off = PRD12;
-                                t->enamode_shift = 6;
+                        irq = dtip[timer].bottom_irq;
-                                t->tim_off = TIM12;
+                } else {
-                                t->prd_off = PRD12;
+                        t->enamode_shift = 22;
-                        } else {
+                        t->tim_off = TIM34;
-                                t->enamode_shift = 22;
+                        t->prd_off = PRD34;
-                                t->tim_off = TIM34;
+                        irq = dtip[timer].top_irq;
-                                t->prd_off = PRD34;
+                }
-                        }
+                /* Register interrupt */
-                        /* Register interrupt */
+                t->irqaction.name = t->name;
-                        t->irqaction.name = t->name;
+                t->irqaction.dev_id = (void *)t;
-                        t->irqaction.dev_id = (void *)t;
-                        if (t->irqaction.handler != NULL) {
+                if (t->irqaction.handler != NULL) {
-                                setup_irq(timer_irqs[t->id], &t->irqaction);
+                        irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
-                        }
+                        setup_irq(irq, &t->irqaction);
-                        timer32_config(&timers[i]);
                }
+                timer32_config(&timers[i]);
        }
 }
@@ -255,7 +275,6 @@ static cycle_t read_cycles(struct clocksource *cs)
 }
 static struct clocksource clocksource_davinci = {
-        .name           = "timer0_1",
        .rating         = 300,
        .read           = read_cycles,
        .mask           = CLOCKSOURCE_MASK(32),
@@ -284,15 +303,18 @@ static void davinci_set_mode(enum clock_event_mode mode,
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                t->period = davinci_clock_tick_rate / (HZ);
-                t->opts = TIMER_OPTS_PERIODIC;
+                t->opts &= ~TIMER_OPTS_STATE_MASK;
+                t->opts |= TIMER_OPTS_PERIODIC;
                timer32_config(t);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
-                t->opts = TIMER_OPTS_ONESHOT;
+                t->opts &= ~TIMER_OPTS_STATE_MASK;
+                t->opts |= TIMER_OPTS_ONESHOT;
                break;
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
-                t->opts = TIMER_OPTS_DISABLED;
+                t->opts &= ~TIMER_OPTS_STATE_MASK;
+                t->opts |= TIMER_OPTS_DISABLED;
                break;
        case CLOCK_EVT_MODE_RESUME:
                break;
@@ -300,7 +322,6 @@ static void davinci_set_mode(enum clock_event_mode mode,
 }
 static struct clock_event_device clockevent_davinci = {
-        .name           = "timer0_0",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .shift          = 32,
        .set_next_event = davinci_set_next_event,
@@ -311,10 +332,42 @@ static struct clock_event_device clockevent_davinci = {
 static void __init davinci_timer_init(void)
 {
        struct clk *timer_clk;
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        unsigned int clockevent_id;
+        unsigned int clocksource_id;
        static char err[] __initdata = KERN_ERR
                "%s: can't register clocksource!\n";
+        clockevent_id = soc_info->timer_info->clockevent_id;
+        clocksource_id = soc_info->timer_info->clocksource_id;
+        timers[TID_CLOCKEVENT].id = clockevent_id;
+        timers[TID_CLOCKSOURCE].id = clocksource_id;
+        /*
+         * If using same timer for both clock events & clocksource,
+         * a compare register must be used to generate an event interrupt.
+         * This is equivalent to a oneshot timer only (not periodic).
+         */
+        if (clockevent_id == clocksource_id) {
+                struct davinci_timer_instance *dtip =
+                                soc_info->timer_info->timers;
+                int event_timer = ID_TO_TIMER(clockevent_id);
+                /* Only bottom timers can use compare regs */
+                if (IS_TIMER_TOP(clockevent_id))
+                        pr_warning("davinci_timer_init: Invalid use"
+                                " of system timers.  Results unpredictable.\n");
+                else if ((dtip[event_timer].cmp_off == 0)
+                                || (dtip[event_timer].cmp_irq == 0))
+                        pr_warning("davinci_timer_init:  Invalid timer instance"
+                                " setup.  Results unpredictable.\n");
+                else {
+                        timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
+                        clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
+                }
+        }
        /* init timer hw */
        timer_init();
@@ -325,6 +378,7 @@ static void __init davinci_timer_init(void)
        davinci_clock_tick_rate = clk_get_rate(timer_clk);
        /* setup clocksource */
+        clocksource_davinci.name = id_to_name[clocksource_id];
        clocksource_davinci.mult =
                clocksource_khz2mult(davinci_clock_tick_rate/1000,
                                     clocksource_davinci.shift);
@@ -332,12 +386,12 @@ static void __init davinci_timer_init(void)
                printk(err, clocksource_davinci.name);
        /* setup clockevent */
+        clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
        clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
                                         clockevent_davinci.shift);
        clockevent_davinci.max_delta_ns =
                clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
-        clockevent_davinci.min_delta_ns =
+        clockevent_davinci.min_delta_ns = 50000; /* 50 usec */
-                clockevent_delta2ns(1, &clockevent_davinci);
        clockevent_davinci.cpumask = cpumask_of(0);
        clockevents_register_device(&clockevent_davinci);
@@ -349,15 +403,14 @@ struct sys_timer davinci_timer = {
 /* reset board using watchdog timer */
-void davinci_watchdog_reset(void) {
+void davinci_watchdog_reset(void)
+{
        u32 tgcr, wdtcr;
-        void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
+        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        struct device dev;
+        void __iomem *base = soc_info->wdt_base;
        struct clk *wd_clk;
-        char *name = "watchdog";
-        dev_set_name(&dev, name);
+        wd_clk = clk_get(&davinci_wdt_device.dev, NULL);
-        wd_clk = clk_get(&dev, NULL);
        if (WARN_ON(IS_ERR(wd_clk)))
                return;
        clk_enable(wd_clk);
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 56bddcef6905..d7291c682a64 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -9,87 +9,135 @@ config CRUNCH
 comment "EP93xx Platforms"
+choice
+        prompt "EP93xx first SDRAM bank selection"
+        default EP93XX_SDCE3_SYNC_PHYS_OFFSET
+config EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        bool "0x00000000 - SDCE3/SyncBoot"
+        help
+          Select this option if you want support for EP93xx boards with the
+          first SDRAM bank at 0x00000000
+config EP93XX_SDCE0_PHYS_OFFSET
+        bool "0xc0000000 - SDCEO"
+        help
+          Select this option if you want support for EP93xx boards with the
+          first SDRAM bank at 0xc0000000
+endchoice
 config MACH_ADSSPHERE
        bool "Support ADS Sphere"
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
        help
          Say 'Y' here if you want your kernel to support the ADS
          Sphere board.
+config MACH_EDB93XX
+        bool
+config MACH_EDB9301
+        bool "Support Cirrus Logic EDB9301"
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        select MACH_EDB93XX
+        help
+          Say 'Y' here if you want your kernel to support the Cirrus
+          Logic EDB9301 Evaluation Board.
 config MACH_EDB9302
        bool "Support Cirrus Logic EDB9302"
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        select MACH_EDB93XX
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9302 Evaluation Board.
 config MACH_EDB9302A
        bool "Support Cirrus Logic EDB9302A"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        select MACH_EDB93XX
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9302A Evaluation Board.
 config MACH_EDB9307
        bool "Support Cirrus Logic EDB9307"
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        select MACH_EDB93XX
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9307 Evaluation Board.
 config MACH_EDB9307A
        bool "Support Cirrus Logic EDB9307A"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        select MACH_EDB93XX
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9307A Evaluation Board.
 config MACH_EDB9312
        bool "Support Cirrus Logic EDB9312"
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        select MACH_EDB93XX
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9312 Evaluation Board.
 config MACH_EDB9315
        bool "Support Cirrus Logic EDB9315"
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        select MACH_EDB93XX
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9315 Evaluation Board.
 config MACH_EDB9315A
        bool "Support Cirrus Logic EDB9315A"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        select MACH_EDB93XX
        help
          Say 'Y' here if you want your kernel to support the Cirrus
          Logic EDB9315A Evaluation Board.
 config MACH_GESBC9312
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
        bool "Support Glomation GESBC-9312-sx"
        help
          Say 'Y' here if you want your kernel to support the Glomation
          GESBC-9312-sx board.
 config MACH_MICRO9
-        bool
+        bool
-        default n
 config MACH_MICRO9H
-       bool "Support Contec Hypercontrol Micro9-H"
+        bool "Support Contec Hypercontrol Micro9-H"
-       select MACH_MICRO9
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
-       help
+        select MACH_MICRO9
-         Say 'Y' here if you want your kernel to support the
+        help
-         Contec Hypercontrol Micro9-H board.
+          Say 'Y' here if you want your kernel to support the
+          Contec Hypercontrol Micro9-H board.
 config MACH_MICRO9M
-       bool "Support Contec Hypercontrol Micro9-M"
+        bool "Support Contec Hypercontrol Micro9-M"
-       select MACH_MICRO9
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
-       help
+        select MACH_MICRO9
-         Say 'Y' here if you want your kernel to support the
+        help
-         Contec Hypercontrol Micro9-M board.
+          Say 'Y' here if you want your kernel to support the
+          Contec Hypercontrol Micro9-M board.
 config MACH_MICRO9L
-       bool "Support Contec Hypercontrol Micro9-L"
+        bool "Support Contec Hypercontrol Micro9-L"
-       select MACH_MICRO9
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
-       help
+        select MACH_MICRO9
-         Say 'Y' here if you want your kernel to support the
+        help
-         Contec Hypercontrol Micro9-L board.
+          Say 'Y' here if you want your kernel to support the
+          Contec Hypercontrol Micro9-L board.
 config MACH_TS72XX
        bool "Support Technologic Systems TS-72xx SBC"
+        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
        help
          Say 'Y' here if you want your kernel to support the
          Technologic Systems TS-72xx board.
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 9522e205b73f..eae6199a9891 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -7,13 +7,7 @@ obj-n			:=
 obj-                    :=
 obj-$(CONFIG_MACH_ADSSPHERE)    += adssphere.o
-obj-$(CONFIG_MACH_EDB9302)      += edb9302.o
+obj-$(CONFIG_MACH_EDB93XX)      += edb93xx.o
-obj-$(CONFIG_MACH_EDB9302A)     += edb9302a.o
-obj-$(CONFIG_MACH_EDB9307)      += edb9307.o
-obj-$(CONFIG_MACH_EDB9307A)     += edb9307a.o
-obj-$(CONFIG_MACH_EDB9312)      += edb9312.o
-obj-$(CONFIG_MACH_EDB9315)      += edb9315.o
-obj-$(CONFIG_MACH_EDB9315A)     += edb9315a.o
 obj-$(CONFIG_MACH_GESBC9312)    += gesbc9312.o
 obj-$(CONFIG_MACH_MICRO9)       += micro9.o
 obj-$(CONFIG_MACH_TS72XX)       += ts72xx.o
diff --git a/arch/arm/mach-ep93xx/Makefile.boot b/arch/arm/mach-ep93xx/Makefile.boot
index d5561ad15bad..27a085a8f12a 100644
--- a/arch/arm/mach-ep93xx/Makefile.boot
+++ b/arch/arm/mach-ep93xx/Makefile.boot
@@ -1,2 +1,5 @@
-   zreladdr-y   := 0x00008000
+   zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)     := 0x00008000
-params_phys-y   := 0x00000100
+params_phys-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)     := 0x00000100
+   zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)          := 0xc0008000
+params_phys-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)          := 0xc0000100
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index b2eede5531c8..6c4c1633ed12 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -72,58 +72,58 @@ static struct clk clk_h;
 static struct clk clk_p;
 static struct clk clk_pll2;
 static struct clk clk_usb_host = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = EP93XX_SYSCON_CLOCK_USH_EN,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_USH_EN,
 };
 /* DMA Clocks */
 static struct clk clk_m2p0 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00020000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
 };
 static struct clk clk_m2p1 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00010000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
 };
 static struct clk clk_m2p2 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00080000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
 };
 static struct clk clk_m2p3 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00040000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
 };
 static struct clk clk_m2p4 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00200000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
 };
 static struct clk clk_m2p5 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00100000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
 };
 static struct clk clk_m2p6 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00800000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
 };
 static struct clk clk_m2p7 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x00400000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
 };
 static struct clk clk_m2p8 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x02000000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
 };
 static struct clk clk_m2p9 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x01000000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
 };
 static struct clk clk_m2m0 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x04000000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
 };
 static struct clk clk_m2m1 = {
-        .enable_reg     = EP93XX_SYSCON_CLOCK_CONTROL,
+        .enable_reg     = EP93XX_SYSCON_PWRCNT,
-        .enable_mask    = 0x08000000,
+        .enable_mask    = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
 };
 #define INIT_CK(dev,con,ck)                                     \
@@ -138,7 +138,7 @@ static struct clk_lookup clocks[] = {
        INIT_CK(NULL, "hclk", &clk_h),
        INIT_CK(NULL, "pclk", &clk_p),
        INIT_CK(NULL, "pll2", &clk_pll2),
-        INIT_CK(NULL, "usb_host", &clk_usb_host),
+        INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
        INIT_CK(NULL, "m2p0", &clk_m2p0),
        INIT_CK(NULL, "m2p1", &clk_m2p1),
        INIT_CK(NULL, "m2p2", &clk_m2p2),
@@ -186,8 +186,8 @@ static unsigned long get_uart_rate(struct clk *clk)
 {
        u32 value;
-        value = __raw_readl(EP93XX_SYSCON_CLOCK_CONTROL);
+        value = __raw_readl(EP93XX_SYSCON_PWRCNT);
-        if (value & EP93XX_SYSCON_CLOCK_UARTBAUD)
+        if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
                return EP93XX_EXT_CLK_RATE;
        else
                return EP93XX_EXT_CLK_RATE / 2;
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index ae24486f858a..204dc5cbd0b8 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -155,7 +155,7 @@ static unsigned char gpio_int_unmasked[3];
 static unsigned char gpio_int_enabled[3];
 static unsigned char gpio_int_type1[3];
 static unsigned char gpio_int_type2[3];
-static unsigned char gpio_int_debouce[3];
+static unsigned char gpio_int_debounce[3];
 /* Port ordering is: A B F */
 static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
@@ -192,11 +192,11 @@ void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
        int port_mask = 1 << (line & 7);
        if (enable)
-                gpio_int_debouce[port] |= port_mask;
+                gpio_int_debounce[port] |= port_mask;
        else
-                gpio_int_debouce[port] &= ~port_mask;
+                gpio_int_debounce[port] &= ~port_mask;
-        __raw_writeb(gpio_int_debouce[port],
+        __raw_writeb(gpio_int_debounce[port],
                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
 }
 EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
@@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void)
 {
        int gpio_irq;
-        vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
+        vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
-        vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
+        vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
        for (gpio_irq = gpio_to_irq(0);
             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
@@ -450,10 +450,19 @@ static struct amba_device uart3_device = {
 };
+static struct resource ep93xx_rtc_resource[] = {
+        {
+                .start          = EP93XX_RTC_PHYS_BASE,
+                .end            = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
 static struct platform_device ep93xx_rtc_device = {
-       .name           = "ep93xx-rtc",
+        .name           = "ep93xx-rtc",
-       .id             = -1,
+        .id             = -1,
-       .num_resources  = 0,
+        .num_resources  = ARRAY_SIZE(ep93xx_rtc_resource),
+        .resource       = ep93xx_rtc_resource,
 };
diff --git a/arch/arm/mach-ep93xx/edb9302.c b/arch/arm/mach-ep93xx/edb9302.c
deleted file mode 100644
index 8bf8d7c78f1a..000000000000
--- a/arch/arm/mach-ep93xx/edb9302.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/edb9302.c
- * Cirrus Logic EDB9302 support.
- *
- * Copyright (C) 2006 George Kashperko <george@chas.com.ua>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct physmap_flash_data edb9302_flash_data = {
-        .width          = 2,
-};
-static struct resource edb9302_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device edb9302_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb9302_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb9302_flash_resource,
-};
-static struct ep93xx_eth_data edb9302_eth_data = {
-        .phy_id         = 1,
-};
-static void __init edb9302_init_machine(void)
-{
-        ep93xx_init_devices();
-        platform_device_register(&edb9302_flash);
-        ep93xx_register_eth(&edb9302_eth_data, 1);
-}
-MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
-        /* Maintainer: George Kashperko <george@chas.com.ua> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
-        .map_io         = ep93xx_map_io,
-        .init_irq       = ep93xx_init_irq,
-        .timer          = &ep93xx_timer,
-        .init_machine   = edb9302_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c
deleted file mode 100644
index a352c57c7b46..000000000000
--- a/arch/arm/mach-ep93xx/edb9302a.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/edb9302a.c
- * Cirrus Logic EDB9302A support.
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct physmap_flash_data edb9302a_flash_data = {
-        .width          = 2,
-};
-static struct resource edb9302a_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device edb9302a_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb9302a_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb9302a_flash_resource,
-};
-static struct ep93xx_eth_data edb9302a_eth_data = {
-        .phy_id         = 1,
-};
-static void __init edb9302a_init_machine(void)
-{
-        ep93xx_init_devices();
-        platform_device_register(&edb9302a_flash);
-        ep93xx_register_eth(&edb9302a_eth_data, 1);
-}
-MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
-        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
-        .map_io         = ep93xx_map_io,
-        .init_irq       = ep93xx_init_irq,
-        .timer          = &ep93xx_timer,
-        .init_machine   = edb9302a_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9307.c b/arch/arm/mach-ep93xx/edb9307.c
deleted file mode 100644
index 5ab22f63a4eb..000000000000
--- a/arch/arm/mach-ep93xx/edb9307.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/edb9307.c
- * Cirrus Logic EDB9307 support.
- *
- * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct physmap_flash_data edb9307_flash_data = {
-        .width          = 4,
-};
-static struct resource edb9307_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device edb9307_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb9307_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb9307_flash_resource,
-};
-static struct ep93xx_eth_data edb9307_eth_data = {
-        .phy_id         = 1,
-};
-static void __init edb9307_init_machine(void)
-{
-        ep93xx_init_devices();
-        platform_device_register(&edb9307_flash);
-        ep93xx_register_eth(&edb9307_eth_data, 1);
-}
-MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
-        /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
-        .map_io         = ep93xx_map_io,
-        .init_irq       = ep93xx_init_irq,
-        .timer          = &ep93xx_timer,
-        .init_machine   = edb9307_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9307a.c b/arch/arm/mach-ep93xx/edb9307a.c
deleted file mode 100644
index 6171167d3315..000000000000
--- a/arch/arm/mach-ep93xx/edb9307a.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/edb9307a.c
- * Cirrus Logic EDB9307A support.
- *
- * Copyright (C) 2008 H Hartley Sweeten <hsweeten@visionengravers.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct physmap_flash_data edb9307a_flash_data = {
-        .width          = 2,
-};
-static struct resource edb9307a_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device edb9307a_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb9307a_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb9307a_flash_resource,
-};
-static struct ep93xx_eth_data edb9307a_eth_data = {
-        .phy_id         = 1,
-};
-static struct i2c_board_info __initdata edb9307a_i2c_data[] = {
-        {
-                /* On-board battery backed RTC */
-                I2C_BOARD_INFO("isl1208", 0x6f),
-        },
-        /*
-         * The I2C signals are also routed to the Expansion Connector (J4)
-         */
-};
-static void __init edb9307a_init_machine(void)
-{
-        ep93xx_init_devices();
-        platform_device_register(&edb9307a_flash);
-        ep93xx_register_eth(&edb9307a_eth_data, 1);
-        ep93xx_init_i2c(edb9307a_i2c_data, ARRAY_SIZE(edb9307a_i2c_data));
-}
-MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
-        /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
-        .map_io         = ep93xx_map_io,
-        .init_irq       = ep93xx_init_irq,
-        .timer          = &ep93xx_timer,
-        .init_machine   = edb9307a_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9312.c b/arch/arm/mach-ep93xx/edb9312.c
deleted file mode 100644
index d7179f66d804..000000000000
--- a/arch/arm/mach-ep93xx/edb9312.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/edb9312.c
- * Cirrus Logic EDB9312 support.
- *
- * Copyright (C) 2006 Infosys Technologies Limited
- *      Toufeeq Hussain <toufeeq_hussain@infosys.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct physmap_flash_data edb9312_flash_data = {
-        .width          = 4,
-};
-static struct resource edb9312_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device edb9312_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb9312_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb9312_flash_resource,
-};
-static struct ep93xx_eth_data edb9312_eth_data = {
-        .phy_id         = 1,
-};
-static void __init edb9312_init_machine(void)
-{
-        ep93xx_init_devices();
-        platform_device_register(&edb9312_flash);
-        ep93xx_register_eth(&edb9312_eth_data, 1);
-}
-MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
-        /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
-        .map_io         = ep93xx_map_io,
-        .init_irq       = ep93xx_init_irq,
-        .timer          = &ep93xx_timer,
-        .init_machine   = edb9312_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9315.c b/arch/arm/mach-ep93xx/edb9315.c
deleted file mode 100644
index 025af6eaca10..000000000000
--- a/arch/arm/mach-ep93xx/edb9315.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/edb9315.c
- * Cirrus Logic EDB9315 support.
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct physmap_flash_data edb9315_flash_data = {
-        .width          = 4,
-};
-static struct resource edb9315_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device edb9315_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb9315_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb9315_flash_resource,
-};
-static struct ep93xx_eth_data edb9315_eth_data = {
-        .phy_id         = 1,
-};
-static void __init edb9315_init_machine(void)
-{
-        ep93xx_init_devices();
-        platform_device_register(&edb9315_flash);
-        ep93xx_register_eth(&edb9315_eth_data, 1);
-}
-MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
-        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
-        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
-        .map_io         = ep93xx_map_io,
-        .init_irq       = ep93xx_init_irq,
-        .timer          = &ep93xx_timer,
-        .init_machine   = edb9315_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb9315a.c b/arch/arm/mach-ep93xx/edb9315a.c
deleted file mode 100644
index 4c9cc8a39f5c..000000000000
--- a/arch/arm/mach-ep93xx/edb9315a.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/edb9315a.c
- * Cirrus Logic EDB9315A support.
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-static struct physmap_flash_data edb9315a_flash_data = {
-        .width          = 2,
-};
-static struct resource edb9315a_flash_resource = {
-        .start          = EP93XX_CS6_PHYS_BASE,
-        .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device edb9315a_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &edb9315a_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &edb9315a_flash_resource,
-};
-static struct ep93xx_eth_data edb9315a_eth_data = {
-        .phy_id         = 1,
-};
-static void __init edb9315a_init_machine(void)
-{
-        ep93xx_init_devices();
-        platform_device_register(&edb9315a_flash);
-        ep93xx_register_eth(&edb9315a_eth_data, 1);
-}
-MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
-        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .phys_io        = EP93XX_APB_PHYS_BASE,
-        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
-        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
-        .map_io         = ep93xx_map_io,
-        .init_irq       = ep93xx_init_irq,
-        .timer          = &ep93xx_timer,
-        .init_machine   = edb9315a_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
new file mode 100644
index 000000000000..e9e45b92457e
--- /dev/null
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -0,0 +1,217 @@
+/*
+ * arch/arm/mach-ep93xx/edb93xx.c
+ * Cirrus Logic EDB93xx Development Board support.
+ *
+ * EDB93XX, EDB9301, EDB9307A
+ * Copyright (C) 2008-2009 H Hartley Sweeten <hsweeten@visionengravers.com>
+ *
+ * EDB9302
+ * Copyright (C) 2006 George Kashperko <george@chas.com.ua>
+ *
+ * EDB9302A, EDB9315, EDB9315A
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * EDB9307
+ * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
+ *
+ * EDB9312
+ * Copyright (C) 2006 Infosys Technologies Limited
+ *                    Toufeeq Hussain <toufeeq_hussain@infosys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+static struct physmap_flash_data edb93xx_flash_data;
+static struct resource edb93xx_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device edb93xx_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &edb93xx_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &edb93xx_flash_resource,
+};
+static void __init __edb93xx_register_flash(unsigned int width,
+                        resource_size_t start, resource_size_t size)
+{
+        edb93xx_flash_data.width        = width;
+        edb93xx_flash_resource.start    = start;
+        edb93xx_flash_resource.end      = start + size - 1;
+        platform_device_register(&edb93xx_flash);
+}
+static void __init edb93xx_register_flash(void)
+{
+        if (machine_is_edb9307() || machine_is_edb9312() ||
+            machine_is_edb9315()) {
+                __edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
+        } else {
+                __edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
+        }
+}
+static struct ep93xx_eth_data edb93xx_eth_data = {
+        .phy_id         = 1,
+};
+static struct i2c_board_info __initdata edb93xxa_i2c_data[] = {
+        {
+                I2C_BOARD_INFO("isl1208", 0x6f),
+        },
+};
+static struct i2c_board_info __initdata edb93xx_i2c_data[] = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+        },
+};
+static void __init edb93xx_register_i2c(void)
+{
+        if (machine_is_edb9302a() || machine_is_edb9307a() ||
+            machine_is_edb9315a()) {
+                ep93xx_register_i2c(edb93xxa_i2c_data,
+                                ARRAY_SIZE(edb93xxa_i2c_data));
+        } else if (machine_is_edb9307() || machine_is_edb9312() ||
+                   machine_is_edb9315()) {
+                ep93xx_register_i2c(edb93xx_i2c_data,
+                                ARRAY_SIZE(edb93xx_i2c_data));
+        }
+}
+static void __init edb93xx_init_machine(void)
+{
+        ep93xx_init_devices();
+        edb93xx_register_flash();
+        ep93xx_register_eth(&edb93xx_eth_data, 1);
+        edb93xx_register_i2c();
+}
+#ifdef CONFIG_MACH_EDB9301
+MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
+        /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_EDB9302
+MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
+        /* Maintainer: George Kashperko <george@chas.com.ua> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_EDB9302A
+MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_EDB9307
+MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
+        /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_EDB9307A
+MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
+        /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_EDB9312
+MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
+        /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_EDB9315
+MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_EDB9315A
+MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = edb93xx_init_machine,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 1732de7629a5..967c079180db 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -147,13 +147,27 @@
 #define EP93XX_PWM_BASE                 (EP93XX_APB_VIRT_BASE + 0x00110000)
 #define EP93XX_RTC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00120000)
+#define EP93XX_RTC_PHYS_BASE            (EP93XX_APB_PHYS_BASE + 0x00120000)
 #define EP93XX_SYSCON_BASE              (EP93XX_APB_VIRT_BASE + 0x00130000)
 #define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
 #define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
-#define EP93XX_SYSCON_CLOCK_CONTROL     EP93XX_SYSCON_REG(0x04)
+#define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_CLOCK_UARTBAUD    0x20000000
+#define EP93XX_SYSCON_PWRCNT_FIR_EN     (1<<31)
-#define EP93XX_SYSCON_CLOCK_USH_EN      0x10000000
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD   (1<<29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN     (1<<28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1   (1<<27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0   (1<<26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8   (1<<25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9   (1<<24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6   (1<<23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7   (1<<22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4   (1<<21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5   (1<<20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2   (1<<19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3   (1<<18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0   (1<<17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
 #define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
 #define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h
index 5c80c3c8158d..925b12ea0990 100644
--- a/arch/arm/mach-ep93xx/include/mach/memory.h
+++ b/arch/arm/mach-ep93xx/include/mach/memory.h
@@ -5,6 +5,12 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
+#if defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)
 #define PHYS_OFFSET             UL(0x00000000)
+#elif defined(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)
+#define PHYS_OFFSET             UL(0xc0000000)
+#else
+#error "Kconfig bug: No EP93xx PHYS_OFFSET set"
+#endif
 #endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
deleted file mode 100644
index cddd194ac6eb..000000000000
--- a/arch/arm/mach-imx/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-menu "IMX Implementations"
-        depends on ARCH_IMX
-config ARCH_MX1ADS
-        bool "mx1ads"
-        depends on ARCH_IMX
-        select ISA
-        help
-          Say Y here if you are using the Motorola MX1ADS board
-endmenu
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
deleted file mode 100644
index b047c7e795a9..000000000000
--- a/arch/arm/mach-imx/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-# Object file lists.
-obj-y                   += irq.o time.o dma.o generic.o clock.o
-obj-$(CONFIG_CPU_FREQ_IMX)      += cpufreq.o
-# Specific board support
-obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
-# Support for blinky lights
-led-y := leds.o
-obj-$(CONFIG_LEDS)      +=  $(led-y)
-led-$(CONFIG_ARCH_MX1ADS) += leds-mx1ads.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
deleted file mode 100644
index fd72ce5b8081..000000000000
--- a/arch/arm/mach-imx/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-    zreladdr-$(CONFIG_ARCH_MX1ADS)      := 0x08008000
diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c
deleted file mode 100644
index cf332aeb942e..000000000000
--- a/arch/arm/mach-imx/clock.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/math64.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-/*
- * Very simple approach: We can't disable clocks, so we do
- * not need refcounting
- */
-struct clk {
-        struct list_head node;
-        const char *name;
-        unsigned long (*get_rate)(void);
-};
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned long imx_decode_pll(unsigned int pll, u32 f_ref)
-{
-        unsigned long long ll;
-        unsigned long quot;
-        u32 mfi = (pll >> 10) & 0xf;
-        u32 mfn = pll & 0x3ff;
-        u32 mfd = (pll >> 16) & 0x3ff;
-        u32 pd =  (pll >> 26) & 0xf;
-        mfi = mfi <= 5 ? 5 : mfi;
-        ll = 2 * (unsigned long long)f_ref *
-                ((mfi << 16) + (mfn << 16) / (mfd + 1));
-        quot = (pd + 1) * (1 << 16);
-        ll += quot / 2;
-        do_div(ll, quot);
-        return (unsigned long)ll;
-}
-static unsigned long imx_get_system_clk(void)
-{
-        u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
-        return imx_decode_pll(SPCTL0, f_ref);
-}
-static unsigned long imx_get_mcu_clk(void)
-{
-        return imx_decode_pll(MPCTL0, CLK32 * 512);
-}
-/*
- *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
- */
-static unsigned long imx_get_perclk1(void)
-{
-        return imx_get_system_clk() / (((PCDR) & 0xf)+1);
-}
-/*
- *  get peripheral clock 2 ( LCD, SD, SPI[12] )
- */
-static unsigned long imx_get_perclk2(void)
-{
-        return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
-}
-/*
- *  get peripheral clock 3 ( SSI )
- */
-static unsigned long imx_get_perclk3(void)
-{
-        return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
-}
-/*
- *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
- */
-static unsigned long imx_get_hclk(void)
-{
-        return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
-}
-static struct clk clk_system_clk = {
-        .name = "system_clk",
-        .get_rate = imx_get_system_clk,
-};
-static struct clk clk_hclk = {
-        .name = "hclk",
-        .get_rate = imx_get_hclk,
-};
-static struct clk clk_mcu_clk = {
-        .name = "mcu_clk",
-        .get_rate = imx_get_mcu_clk,
-};
-static struct clk clk_perclk1 = {
-        .name = "perclk1",
-        .get_rate = imx_get_perclk1,
-};
-static struct clk clk_uart_clk = {
-        .name = "uart_clk",
-        .get_rate = imx_get_perclk1,
-};
-static struct clk clk_perclk2 = {
-        .name = "perclk2",
-        .get_rate = imx_get_perclk2,
-};
-static struct clk clk_perclk3 = {
-        .name = "perclk3",
-        .get_rate = imx_get_perclk3,
-};
-static struct clk *clks[] = {
-        &clk_perclk1,
-        &clk_perclk2,
-        &clk_perclk3,
-        &clk_system_clk,
-        &clk_hclk,
-        &clk_mcu_clk,
-        &clk_uart_clk,
-};
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        mutex_lock(&clocks_mutex);
-        list_for_each_entry(p, &clocks, node) {
-                if (!strcmp(p->name, id)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-found:
-        mutex_unlock(&clocks_mutex);
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-int clk_enable(struct clk *clk)
-{
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return clk->get_rate();
-}
-EXPORT_SYMBOL(clk_get_rate);
-int imx_clocks_init(void)
-{
-        int i;
-        mutex_lock(&clocks_mutex);
-        for (i = 0; i < ARRAY_SIZE(clks); i++)
-                list_add(&clks[i]->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-        return 0;
-}
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
deleted file mode 100644
index 434b4ca0af67..000000000000
--- a/arch/arm/mach-imx/cpufreq.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * cpu.c: clock scaling for the iMX
- *
- * Copyright (C) 2000 2001, The Delft University of Technology
- * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com>
- * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
- *
- * Based on SA1100 version written by:
- * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
- * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-/*#define DEBUG*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <asm/system.h>
-#include <mach/hardware.h>
-#include "generic.h"
-#ifndef __val2mfld
-#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
-#endif
-#ifndef __mfld2val
-#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
-#endif
-#define CR_920T_CLOCK_MODE      0xC0000000
-#define CR_920T_FASTBUS_MODE    0x00000000
-#define CR_920T_ASYNC_MODE      0xC0000000
-static u32 mpctl0_at_boot;
-static u32 bclk_div_at_boot;
-static struct clk *system_clk, *mcu_clk;
-static void imx_set_async_mode(void)
-{
-        adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
-}
-static void imx_set_fastbus_mode(void)
-{
-        adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE);
-}
-static void imx_set_mpctl0(u32 mpctl0)
-{
-        unsigned long flags;
-        if (mpctl0 == 0) {
-                local_irq_save(flags);
-                CSCR &= ~CSCR_MPEN;
-                local_irq_restore(flags);
-                return;
-        }
-        local_irq_save(flags);
-        MPCTL0 = mpctl0;
-        CSCR |= CSCR_MPEN;
-        local_irq_restore(flags);
-}
-/**
- * imx_compute_mpctl - compute new PLL parameters
- * @new_mpctl:  pointer to location assigned by new PLL control register value
- * @cur_mpctl:  current PLL control register parameters
- * @f_ref:      reference source frequency Hz
- * @freq:       required frequency in Hz
- * @relation:   is one of %CPUFREQ_RELATION_L (supremum)
- *              and %CPUFREQ_RELATION_H (infimum)
- */
-long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation)
-{
-        u32 mfi;
-        u32 mfn;
-        u32 mfd;
-        u32 pd;
-        unsigned long long ll;
-        long l;
-        long quot;
-        /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */
-        /*  PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */
-        if (cur_mpctl) {
-                mfd = ((cur_mpctl >> 16) & 0x3ff) + 1;
-                pd =  ((cur_mpctl >> 26) & 0xf) + 1;
-        } else {
-                pd=2; mfd=313;
-        }
-        /* pd=2; mfd=313; mfi=8; mfn=183; */
-        /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */
-        quot = (f_ref + (1 << 9)) >> 10;
-        l = (freq * pd + quot) / (2 * quot);
-        mfi = l >> 10;
-        mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10;
-        mfd -= 1;
-        pd -= 1;
-        *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16)
-                | ((pd & 0xf) << 26);
-        ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
-        quot = (pd+1) * (1<<16);
-        ll += quot / 2;
-        do_div(ll, quot);
-        freq = ll;
-        pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n",
-                pd, mfd, mfi, mfn, freq);
-        return freq;
-}
-static int imx_verify_speed(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-        cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
-        return 0;
-}
-static unsigned int imx_get_speed(unsigned int cpu)
-{
-        unsigned int freq;
-        unsigned int cr;
-        unsigned int cscr;
-        unsigned int bclk_div;
-        if (cpu)
-                return 0;
-        cscr = CSCR;
-        bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1;
-        cr = get_cr();
-        if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
-                freq = clk_get_rate(system_clk);
-                freq = (freq + bclk_div/2) / bclk_div;
-        } else {
-                freq = clk_get_rate(mcu_clk);
-                if (cscr & CSCR_MPU_PRESC)
-                        freq /= 2;
-        }
-        freq = (freq + 500) / 1000;
-        return freq;
-}
-static int imx_set_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq,
-                          unsigned int relation)
-{
-        struct cpufreq_freqs freqs;
-        u32 mpctl0 = 0;
-        u32 cscr;
-        unsigned long flags;
-        long freq;
-        long sysclk;
-        unsigned int bclk_div = bclk_div_at_boot;
-        /*
-         * Some governors do not respects CPU and policy lower limits
-         * which leads to bad things (division by zero etc), ensure
-         * that such things do not happen.
-         */
-        if(target_freq < policy->cpuinfo.min_freq)
-                target_freq = policy->cpuinfo.min_freq;
-        if(target_freq < policy->min)
-                target_freq = policy->min;
-        freq = target_freq * 1000;
-        pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
-                        freq, mpctl0_at_boot);
-        sysclk = clk_get_rate(system_clk);
-        if (freq > sysclk / bclk_div_at_boot + 1000000) {
-                freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation);
-                if (freq < 0) {
-                        printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
-                        return -EINVAL;
-                }
-        } else {
-                if(freq + 1000 < sysclk) {
-                        if (relation == CPUFREQ_RELATION_L)
-                                bclk_div = (sysclk - 1000) / freq;
-                        else
-                                bclk_div = (sysclk + freq + 1000) / freq;
-                        if(bclk_div > 16)
-                                bclk_div = 16;
-                        if(bclk_div < bclk_div_at_boot)
-                                bclk_div = bclk_div_at_boot;
-                }
-                freq = (sysclk + bclk_div / 2) / bclk_div;
-        }
-        freqs.old = imx_get_speed(0);
-        freqs.new = (freq + 500) / 1000;
-        freqs.cpu = 0;
-        freqs.flags = 0;
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-        local_irq_save(flags);
-        imx_set_fastbus_mode();
-        imx_set_mpctl0(mpctl0);
-        cscr = CSCR;
-        cscr &= ~CSCR_BCLK_DIV;
-        cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1);
-        CSCR = cscr;
-        if(mpctl0) {
-                CSCR |= CSCR_MPLL_RESTART;
-                /* Wait until MPLL is stabilized */
-                while( CSCR & CSCR_MPLL_RESTART );
-                imx_set_async_mode();
-        }
-        local_irq_restore(flags);
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-        pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n",
-                        freq, mpctl0? "MPLL": "SPLL");
-        return 0;
-}
-static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
-{
-        printk(KERN_INFO "i.MX cpu freq change driver v1.0\n");
-        if (policy->cpu != 0)
-                return -EINVAL;
-        policy->cur = policy->min = policy->max = imx_get_speed(0);
-        policy->cpuinfo.min_freq = 8000;
-        policy->cpuinfo.max_freq = 200000;
-         /* Manual states, that PLL stabilizes in two CLK32 periods */
-        policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32;
-        return 0;
-}
-static struct cpufreq_driver imx_driver = {
-        .flags          = CPUFREQ_STICKY,
-        .verify         = imx_verify_speed,
-        .target         = imx_set_target,
-        .get            = imx_get_speed,
-        .init           = imx_cpufreq_driver_init,
-        .name           = "imx",
-};
-static int __init imx_cpufreq_init(void)
-{
-        bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1;
-        mpctl0_at_boot = 0;
-        system_clk = clk_get(NULL, "system_clk");
-        if (IS_ERR(system_clk))
-                return PTR_ERR(system_clk);
-        mcu_clk = clk_get(NULL, "mcu_clk");
-        if (IS_ERR(mcu_clk)) {
-                clk_put(system_clk);
-                return PTR_ERR(mcu_clk);
-        }
-        if((CSCR & CSCR_MPEN) &&
-           ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
-                mpctl0_at_boot = MPCTL0;
-        return cpufreq_register_driver(&imx_driver);
-}
-arch_initcall(imx_cpufreq_init);
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
deleted file mode 100644
index 1536583eece0..000000000000
--- a/arch/arm/mach-imx/dma.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/dma.c
- *
- *  imx DMA registration and IRQ dispatching
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- *
- *  2004-03-03 Sascha Hauer <sascha@saschahauer.de>
- *             initial version heavily inspired by
- *             linux/arch/arm/mach-pxa/dma.c
- *
- *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- *             Changed to support scatter gather DMA
- *             by taking Russell's code from RiscPC
- *
- *  2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- *             Corrected error handling code.
- *
- */
-#undef DEBUG
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <asm/scatterlist.h>
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <mach/imx-dma.h>
-struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- * @dma_ch: i.MX DMA channel number
- * @lastcount: number of bytes transferred during last transfer
- *
- * Functions prepares DMA controller for next sg data chunk transfer.
- * The @lastcount argument informs function about number of bytes transferred
- * during last block. Zero value can be used for @lastcount to setup DMA
- * for the first chunk.
- */
-static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount)
-{
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        unsigned int nextcount;
-        unsigned int nextaddr;
-        if (!imxdma->name) {
-                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-                       __func__, dma_ch);
-                return 0;
-        }
-        imxdma->resbytes -= lastcount;
-        if (!imxdma->sg) {
-                pr_debug("imxdma%d: no sg data\n", dma_ch);
-                return 0;
-        }
-        imxdma->sgbc += lastcount;
-        if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) {
-                if ((imxdma->sgcount <= 1) || !imxdma->resbytes) {
-                        pr_debug("imxdma%d: sg transfer limit reached\n",
-                                 dma_ch);
-                        imxdma->sgcount=0;
-                        imxdma->sg = NULL;
-                        return 0;
-                } else {
-                        imxdma->sgcount--;
-                        imxdma->sg++;
-                        imxdma->sgbc = 0;
-                }
-        }
-        nextcount = imxdma->sg->length - imxdma->sgbc;
-        nextaddr = imxdma->sg->dma_address + imxdma->sgbc;
-        if(imxdma->resbytes < nextcount)
-                nextcount = imxdma->resbytes;
-        if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
-                DAR(dma_ch) = nextaddr;
-        else
-                SAR(dma_ch) = nextaddr;
-        CNTR(dma_ch) = nextcount;
-        pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n",
-                 dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch));
-        return nextcount;
-}
-/*
- * imx_dma_setup_sg_base - scatter-gather DMA emulation
- * @dma_ch: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- *
- * Functions sets up i.MX DMA state for emulated scatter-gather transfer
- * and sets up channel registers to be ready for the first chunk
- */
-static int
-imx_dma_setup_sg_base(imx_dmach_t dma_ch,
-                      struct scatterlist *sg, unsigned int sgcount)
-{
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        imxdma->sg = sg;
-        imxdma->sgcount = sgcount;
-        imxdma->sgbc = 0;
-        return imx_dma_sg_next(dma_ch, 0);
-}
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer
- * @dma_ch: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- *              to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * The function setups DMA channel source and destination addresses for transfer
- * specified by provided parameters. The scatter-gather emulation is disabled,
- * because linear data block
- * form the physical address range is transferred.
- * Return value: if incorrect parameters are provided -%EINVAL.
- *              Zero indicates success.
- */
-int
-imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
-                     unsigned int dma_length, unsigned int dev_addr,
-                     unsigned int dmamode)
-{
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        imxdma->sg = NULL;
-        imxdma->sgcount = 0;
-        imxdma->dma_mode = dmamode;
-        imxdma->resbytes = dma_length;
-        if (!dma_address) {
-                printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-                       dma_ch);
-                return -EINVAL;
-        }
-        if (!dma_length) {
-                printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-                       dma_ch);
-                return -EINVAL;
-        }
-        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-                pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n",
-                        dma_ch, (unsigned int)dma_address, dma_length,
-                        dev_addr);
-                SAR(dma_ch) = dev_addr;
-                DAR(dma_ch) = (unsigned int)dma_address;
-        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-                pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n",
-                        dma_ch, (unsigned int)dma_address, dma_length,
-                        dev_addr);
-                SAR(dma_ch) = (unsigned int)dma_address;
-                DAR(dma_ch) = dev_addr;
-        } else {
-                printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-                       dma_ch);
-                return -EINVAL;
-        }
-        CNTR(dma_ch) = dma_length;
-        return 0;
-}
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @dma_ch: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for transfer
- * specified by provided parameters. The scatter-gather emulation is set up
- * according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical
- * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(imx_dmach_t dma_ch,
-                 struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
-                 unsigned int dev_addr, unsigned int dmamode)
-{
-        int res;
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        imxdma->sg = NULL;
-        imxdma->sgcount = 0;
-        imxdma->dma_mode = dmamode;
-        imxdma->resbytes = dma_length;
-        if (!sg || !sgcount) {
-                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
-                       dma_ch);
-                return -EINVAL;
-        }
-        if (!sg->length) {
-                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-                       dma_ch);
-                return -EINVAL;
-        }
-        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-                pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n",
-                        dma_ch, sg, sgcount, dma_length, dev_addr);
-                SAR(dma_ch) = dev_addr;
-        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-                pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n",
-                        dma_ch, sg, sgcount, dma_length, dev_addr);
-                DAR(dma_ch) = dev_addr;
-        } else {
-                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-                       dma_ch);
-                return -EINVAL;
-        }
-        res = imx_dma_setup_sg_base(dma_ch, sg, sgcount);
-        if (res <= 0) {
-                printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch);
-                return -EINVAL;
-        }
-        return 0;
-}
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers
- * @dma_ch: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- *              ends successfully
- * @err_handler: the pointer to the function called if the premature
- *              end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(imx_dmach_t dma_ch,
-                       void (*irq_handler) (int, void *),
-                       void (*err_handler) (int, void *, int),
-                       void *data)
-{
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        unsigned long flags;
-        if (!imxdma->name) {
-                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-                       __func__, dma_ch);
-                return -ENODEV;
-        }
-        local_irq_save(flags);
-        DISR = (1 << dma_ch);
-        imxdma->irq_handler = irq_handler;
-        imxdma->err_handler = err_handler;
-        imxdma->data = data;
-        local_irq_restore(flags);
-        return 0;
-}
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @dma_ch: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(imx_dmach_t dma_ch)
-{
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        unsigned long flags;
-        pr_debug("imxdma%d: imx_dma_enable\n", dma_ch);
-        if (!imxdma->name) {
-                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-                       __func__, dma_ch);
-                return;
-        }
-        local_irq_save(flags);
-        DISR = (1 << dma_ch);
-        DIMR &= ~(1 << dma_ch);
-        CCR(dma_ch) |= CCR_CEN;
-        local_irq_restore(flags);
-}
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @dma_ch: i.MX DMA channel number
- */
-void imx_dma_disable(imx_dmach_t dma_ch)
-{
-        unsigned long flags;
-        pr_debug("imxdma%d: imx_dma_disable\n", dma_ch);
-        local_irq_save(flags);
-        DIMR |= (1 << dma_ch);
-        CCR(dma_ch) &= ~CCR_CEN;
-        DISR = (1 << dma_ch);
-        local_irq_restore(flags);
-}
-/**
- * imx_dma_request - request/allocate specified channel number
- * @dma_ch: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(imx_dmach_t dma_ch, const char *name)
-{
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        unsigned long flags;
-        /* basic sanity checks */
-        if (!name)
-                return -EINVAL;
-        if (dma_ch >= IMX_DMA_CHANNELS) {
-                printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
-                       __func__, dma_ch);
-                return -EINVAL;
-        }
-        local_irq_save(flags);
-        if (imxdma->name) {
-                local_irq_restore(flags);
-                return -ENODEV;
-        }
-        imxdma->name = name;
-        imxdma->irq_handler = NULL;
-        imxdma->err_handler = NULL;
-        imxdma->data = NULL;
-        imxdma->sg = NULL;
-        local_irq_restore(flags);
-        return 0;
-}
-/**
- * imx_dma_free - release previously acquired channel
- * @dma_ch: i.MX DMA channel number
- */
-void imx_dma_free(imx_dmach_t dma_ch)
-{
-        unsigned long flags;
-        struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
-        if (!imxdma->name) {
-                printk(KERN_CRIT
-                       "%s: trying to free channel %d which is already freed\n",
-                       __func__, dma_ch);
-                return;
-        }
-        local_irq_save(flags);
-        /* Disable interrupts */
-        DIMR |= (1 << dma_ch);
-        CCR(dma_ch) &= ~CCR_CEN;
-        imxdma->name = NULL;
-        local_irq_restore(flags);
-}
-/**
- * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
- * @name: the driver/caller own non-%NULL identification
- * @prio: one of the hardware distinguished priority level:
- *        %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
- *
- * This function tries to find free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               On successful allocation channel is returned.
- */
-imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio)
-{
-        int i;
-        int best;
-        switch (prio) {
-        case (DMA_PRIO_HIGH):
-                best = 8;
-                break;
-        case (DMA_PRIO_MEDIUM):
-                best = 4;
-                break;
-        case (DMA_PRIO_LOW):
-        default:
-                best = 0;
-                break;
-        }
-        for (i = best; i < IMX_DMA_CHANNELS; i++) {
-                if (!imx_dma_request(i, name)) {
-                        return i;
-                }
-        }
-        for (i = best - 1; i >= 0; i--) {
-                if (!imx_dma_request(i, name)) {
-                        return i;
-                }
-        }
-        printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-        return -ENODEV;
-}
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
-        int i, disr = DISR;
-        struct imx_dma_channel *channel;
-        unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR;
-        int errcode;
-        DISR = disr & err_mask;
-        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-                if(!(err_mask & (1 << i)))
-                        continue;
-                channel = &imx_dma_channels[i];
-                errcode = 0;
-                if (DBTOSR & (1 << i)) {
-                        DBTOSR = (1 << i);
-                        errcode |= IMX_DMA_ERR_BURST;
-                }
-                if (DRTOSR & (1 << i)) {
-                        DRTOSR = (1 << i);
-                        errcode |= IMX_DMA_ERR_REQUEST;
-                }
-                if (DSESR & (1 << i)) {
-                        DSESR = (1 << i);
-                        errcode |= IMX_DMA_ERR_TRANSFER;
-                }
-                if (DBOSR & (1 << i)) {
-                        DBOSR = (1 << i);
-                        errcode |= IMX_DMA_ERR_BUFFER;
-                }
-                /*
-                 * The cleaning of @sg field would be questionable
-                 * there, because its value can help to compute
-                 * remaining/transferred bytes count in the handler
-                 */
-                /*imx_dma_channels[i].sg = NULL;*/
-                if (channel->name && channel->err_handler) {
-                        channel->err_handler(i, channel->data, errcode);
-                        continue;
-                }
-                imx_dma_channels[i].sg = NULL;
-                printk(KERN_WARNING
-                       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
-                       i, channel->name,
-                       errcode&IMX_DMA_ERR_BURST?    " burst":"",
-                       errcode&IMX_DMA_ERR_REQUEST?  " request":"",
-                       errcode&IMX_DMA_ERR_TRANSFER? " transfer":"",
-                       errcode&IMX_DMA_ERR_BUFFER?   " buffer":"");
-        }
-        return IRQ_HANDLED;
-}
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-        int i, disr = DISR;
-        pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-                     disr);
-        DISR = disr;
-        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-                if (disr & (1 << i)) {
-                        struct imx_dma_channel *channel = &imx_dma_channels[i];
-                        if (channel->name) {
-                                if (imx_dma_sg_next(i, CNTR(i))) {
-                                        CCR(i) &= ~CCR_CEN;
-                                        mb();
-                                        CCR(i) |= CCR_CEN;
-                                } else {
-                                        if (channel->irq_handler)
-                                                channel->irq_handler(i,
-                                                        channel->data);
-                                }
-                        } else {
-                                /*
-                                 * IRQ for an unregistered DMA channel:
-                                 * let's clear the interrupts and disable it.
-                                 */
-                                printk(KERN_WARNING
-                                       "spurious IRQ for DMA channel %d\n", i);
-                        }
-                }
-        }
-        return IRQ_HANDLED;
-}
-static int __init imx_dma_init(void)
-{
-        int ret;
-        int i;
-        /* reset DMA module */
-        DCR = DCR_DRST;
-        ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-        if (ret) {
-                printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
-                return ret;
-        }
-        ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
-        if (ret) {
-                printk(KERN_CRIT "Wow!  Can't register ERRIRQ for DMA\n");
-                free_irq(DMA_INT, NULL);
-        }
-        /* enable DMA module */
-        DCR = DCR_DEN;
-        /* clear all interrupts */
-        DISR = (1 << IMX_DMA_CHANNELS) - 1;
-        /* enable interrupts */
-        DIMR = (1 << IMX_DMA_CHANNELS) - 1;
-        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-                imx_dma_channels[i].sg = NULL;
-                imx_dma_channels[i].dma_num = i;
-        }
-        return ret;
-}
-arch_initcall(imx_dma_init);
-EXPORT_SYMBOL(imx_dma_setup_single);
-EXPORT_SYMBOL(imx_dma_setup_sg);
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-EXPORT_SYMBOL(imx_dma_enable);
-EXPORT_SYMBOL(imx_dma_disable);
-EXPORT_SYMBOL(imx_dma_request);
-EXPORT_SYMBOL(imx_dma_free);
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-EXPORT_SYMBOL(imx_dma_channels);
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
deleted file mode 100644
index 05f1739ee127..000000000000
--- a/arch/arm/mach-imx/generic.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- *  arch/arm/mach-imx/generic.c
- *
- *  author: Sascha Hauer
- *  Created: april 20th, 2004
- *  Copyright: Synertronixx GmbH
- *
- *  Common code for i.MX machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <asm/errno.h>
-#include <mach/hardware.h>
-#include <mach/imx-regs.h>
-#include <asm/mach/map.h>
-#include <mach/mmc.h>
-#include <mach/gpio.h>
-unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG];
-void imx_gpio_mode(int gpio_mode)
-{
-        unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-        unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-        unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
-        unsigned int tmp;
-        /* Pullup enable */
-        if(gpio_mode & GPIO_PUEN)
-                PUEN(port) |= (1<<pin);
-        else
-                PUEN(port) &= ~(1<<pin);
-        /* Data direction */
-        if(gpio_mode & GPIO_OUT)
-                DDIR(port) |= 1<<pin;
-        else
-                DDIR(port) &= ~(1<<pin);
-        /* Primary / alternate function */
-        if(gpio_mode & GPIO_AF)
-                GPR(port) |= (1<<pin);
-        else
-                GPR(port) &= ~(1<<pin);
-        /* use as gpio? */
-        if(gpio_mode &  GPIO_GIUS)
-                GIUS(port) |= (1<<pin);
-        else
-                GIUS(port) &= ~(1<<pin);
-        /* Output / input configuration */
-        /* FIXME: I'm not very sure about OCR and ICONF, someone
-         * should have a look over it
-         */
-        if(pin<16) {
-                tmp = OCR1(port);
-                tmp &= ~( 3<<(pin*2));
-                tmp |= (ocr << (pin*2));
-                OCR1(port) = tmp;
-                ICONFA1(port) &= ~( 3<<(pin*2));
-                ICONFA1(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
-                ICONFB1(port) &= ~( 3<<(pin*2));
-                ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
-        } else {
-                tmp = OCR2(port);
-                tmp &= ~( 3<<((pin-16)*2));
-                tmp |= (ocr << ((pin-16)*2));
-                OCR2(port) = tmp;
-                ICONFA2(port) &= ~( 3<<((pin-16)*2));
-                ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2);
-                ICONFB2(port) &= ~( 3<<((pin-16)*2));
-                ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2);
-        }
-}
-EXPORT_SYMBOL(imx_gpio_mode);
-int imx_gpio_request(unsigned gpio, const char *label)
-{
-        if(gpio >= (GPIO_PORT_MAX + 1) * 32) {
-                printk(KERN_ERR "imx_gpio: Attempt to request nonexistent GPIO %d for \"%s\"\n",
-                        gpio, label ? label : "?");
-                return -EINVAL;
-        }
-        if(test_and_set_bit(gpio, imx_gpio_alloc_map)) {
-                printk(KERN_ERR "imx_gpio: GPIO %d already used. Allocation for \"%s\" failed\n",
-                        gpio, label ? label : "?");
-                return -EBUSY;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(imx_gpio_request);
-void imx_gpio_free(unsigned gpio)
-{
-        if(gpio >= (GPIO_PORT_MAX + 1) * 32)
-                return;
-        clear_bit(gpio, imx_gpio_alloc_map);
-}
-EXPORT_SYMBOL(imx_gpio_free);
-int imx_gpio_direction_input(unsigned gpio)
-{
-        imx_gpio_mode(gpio | GPIO_IN | GPIO_GIUS | GPIO_DR);
-        return 0;
-}
-EXPORT_SYMBOL(imx_gpio_direction_input);
-int imx_gpio_direction_output(unsigned gpio, int value)
-{
-        imx_gpio_set_value(gpio, value);
-        imx_gpio_mode(gpio | GPIO_OUT | GPIO_GIUS | GPIO_DR);
-        return 0;
-}
-EXPORT_SYMBOL(imx_gpio_direction_output);
-int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
-                                int alloc_mode, const char *label)
-{
-        const int *p = pin_list;
-        int i;
-        unsigned gpio;
-        unsigned mode;
-        for (i = 0; i < count; i++) {
-                gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
-                mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
-                if (gpio >= (GPIO_PORT_MAX + 1) * 32)
-                        goto setup_error;
-                if (alloc_mode & IMX_GPIO_ALLOC_MODE_RELEASE)
-                        imx_gpio_free(gpio);
-                else if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_NO_ALLOC))
-                        if (imx_gpio_request(gpio, label))
-                                if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_TRY_ALLOC))
-                                        goto setup_error;
-                if (!(alloc_mode & (IMX_GPIO_ALLOC_MODE_ALLOC_ONLY |
-                                    IMX_GPIO_ALLOC_MODE_RELEASE)))
-                        imx_gpio_mode(gpio | mode);
-                p++;
-        }
-        return 0;
-setup_error:
-        if(alloc_mode & (IMX_GPIO_ALLOC_MODE_NO_ALLOC |
-                         IMX_GPIO_ALLOC_MODE_TRY_ALLOC))
-                return -EINVAL;
-        while (p != pin_list) {
-                p--;
-                gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
-                imx_gpio_free(gpio);
-        }
-        return -EINVAL;
-}
-EXPORT_SYMBOL(imx_gpio_setup_multiple_pins);
-void __imx_gpio_set_value(unsigned gpio, int value)
-{
-        imx_gpio_set_value_inline(gpio, value);
-}
-EXPORT_SYMBOL(__imx_gpio_set_value);
-int imx_gpio_to_irq(unsigned gpio)
-{
-        return IRQ_GPIOA(0) + gpio;
-}
-EXPORT_SYMBOL(imx_gpio_to_irq);
-int imx_irq_to_gpio(unsigned irq)
-{
-        if (irq < IRQ_GPIOA(0))
-                return -EINVAL;
-        return irq - IRQ_GPIOA(0);
-}
-EXPORT_SYMBOL(imx_irq_to_gpio);
-static struct resource imx_mmc_resources[] = {
-        [0] = {
-                .start  = 0x00214000,
-                .end    = 0x002140FF,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = (SDHC_INT),
-                .end    = (SDHC_INT),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static u64 imxmmmc_dmamask = 0xffffffffUL;
-static struct platform_device imx_mmc_device = {
-        .name           = "imx-mmc",
-        .id             = 0,
-        .dev            = {
-                .dma_mask = &imxmmmc_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(imx_mmc_resources),
-        .resource       = imx_mmc_resources,
-};
-void __init imx_set_mmc_info(struct imxmmc_platform_data *info)
-{
-        imx_mmc_device.dev.platform_data = info;
-}
-static struct platform_device *devices[] __initdata = {
-        &imx_mmc_device,
-};
-static struct map_desc imx_io_desc[] __initdata = {
-        {
-                .virtual        = IMX_IO_BASE,
-                .pfn            = __phys_to_pfn(IMX_IO_PHYS),
-                .length         = IMX_IO_SIZE,
-                .type           = MT_DEVICE
-        }
-};
-void __init
-imx_map_io(void)
-{
-        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
-}
-static int __init imx_init(void)
-{
-        return platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-subsys_initcall(imx_init);
diff --git a/arch/arm/mach-imx/generic.h b/arch/arm/mach-imx/generic.h
deleted file mode 100644
index e91003e4bef3..000000000000
--- a/arch/arm/mach-imx/generic.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/generic.h
- *
- * Author:      Sascha Hauer <sascha@saschahauer.de>
- * Copyright:   Synertronixx GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-extern void __init imx_map_io(void);
-extern void __init imx_init_irq(void);
-struct sys_timer;
-extern struct sys_timer imx_timer;
diff --git a/arch/arm/mach-imx/include/mach/debug-macro.S b/arch/arm/mach-imx/include/mach/debug-macro.S
deleted file mode 100644
index 87802bbfe633..000000000000
--- a/arch/arm/mach-imx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/* arch/arm/mach-imx/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-                .macro  addruart,rx
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x00000000        @ physical
-                movne   \rx, #0xe0000000        @ virtual
-                orreq   \rx, \rx, #0x00200000   @ physical
-                orr     \rx, \rx, #0x00006000   @ UART1 offset
-                .endm
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x40]       @ TXDATA
-                .endm
-                .macro  waituart,rd,rx
-                .endm
-                .macro  busyuart,rd,rx
-1002:           ldr     \rd, [\rx, #0x98]       @ SR2
-                tst     \rd, #1 << 3            @ TXDC
-                beq     1002b                   @ wait until transmit done
-                .endm
diff --git a/arch/arm/mach-imx/include/mach/dma.h b/arch/arm/mach-imx/include/mach/dma.h
deleted file mode 100644
index 621ff2c730f2..000000000000
--- a/arch/arm/mach-imx/include/mach/dma.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *  linux/include/asm-arm/imxads/dma.h
- *
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-typedef enum {
-        DMA_PRIO_HIGH = 0,
-        DMA_PRIO_MEDIUM = 1,
-        DMA_PRIO_LOW = 2
-} imx_dma_prio;
-#define DMA_REQ_UART3_T        2
-#define DMA_REQ_UART3_R        3
-#define DMA_REQ_SSI2_T         4
-#define DMA_REQ_SSI2_R         5
-#define DMA_REQ_CSI_STAT       6
-#define DMA_REQ_CSI_R          7
-#define DMA_REQ_MSHC           8
-#define DMA_REQ_DSPA_DCT_DOUT  9
-#define DMA_REQ_DSPA_DCT_DIN  10
-#define DMA_REQ_DSPA_MAC      11
-#define DMA_REQ_EXT           12
-#define DMA_REQ_SDHC          13
-#define DMA_REQ_SPI1_R        14
-#define DMA_REQ_SPI1_T        15
-#define DMA_REQ_SSI_T         16
-#define DMA_REQ_SSI_R         17
-#define DMA_REQ_ASP_DAC       18
-#define DMA_REQ_ASP_ADC       19
-#define DMA_REQ_USP_EP(x)    (20+(x))
-#define DMA_REQ_SPI2_R        26
-#define DMA_REQ_SPI2_T        27
-#define DMA_REQ_UART2_T       28
-#define DMA_REQ_UART2_R       29
-#define DMA_REQ_UART1_T       30
-#define DMA_REQ_UART1_R       31
-#endif                          /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-imx/include/mach/entry-macro.S b/arch/arm/mach-imx/include/mach/entry-macro.S
deleted file mode 100644
index e4db679f7766..000000000000
--- a/arch/arm/mach-imx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-imx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for iMX-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-                .macro  disable_fiq
-                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-#define AITC_NIVECSR   0x40
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =IO_ADDRESS(IMX_AITC_BASE)
-                @ Load offset & priority of the highest priority
-                @ interrupt pending.
-                ldr     \irqstat, [\base, #AITC_NIVECSR]
-                @ Shift off the priority leaving the offset or
-                @ "interrupt number", use arithmetic shift to
-                @ transform illegal source (0xffff) as -1
-                mov     \irqnr, \irqstat, asr #16
-                adds    \tmp, \irqnr, #1
-                .endm
diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h
deleted file mode 100644
index 6c2942f82922..000000000000
--- a/arch/arm/mach-imx/include/mach/gpio.h
+++ /dev/null
@@ -1,106 +0,0 @@
-#ifndef _IMX_GPIO_H
-#include <linux/kernel.h>
-#include <mach/hardware.h>
-#include <mach/imx-regs.h>
-#define IMX_GPIO_ALLOC_MODE_NORMAL      0
-#define IMX_GPIO_ALLOC_MODE_NO_ALLOC    1
-#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC   2
-#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY  4
-#define IMX_GPIO_ALLOC_MODE_RELEASE     8
-extern int imx_gpio_request(unsigned gpio, const char *label);
-extern void imx_gpio_free(unsigned gpio);
-extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
-                                        int alloc_mode, const char *label);
-extern int imx_gpio_direction_input(unsigned gpio);
-extern int imx_gpio_direction_output(unsigned gpio, int value);
-extern void __imx_gpio_set_value(unsigned gpio, int value);
-static inline int imx_gpio_get_value(unsigned gpio)
-{
-        return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
-}
-static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
-{
-        unsigned long flags;
-        raw_local_irq_save(flags);
-        if(value)
-                DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
-        else
-                DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
-        raw_local_irq_restore(flags);
-}
-static inline void imx_gpio_set_value(unsigned gpio, int value)
-{
-        if(__builtin_constant_p(gpio))
-                imx_gpio_set_value_inline(gpio, value);
-        else
-                __imx_gpio_set_value(gpio, value);
-}
-extern int imx_gpio_to_irq(unsigned gpio);
-extern int imx_irq_to_gpio(unsigned irq);
-/*-------------------------------------------------------------------------*/
-/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
- * to allow future extension of GPIO logic.
- */
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return imx_gpio_request(gpio, label);
-}
-static inline void gpio_free(unsigned gpio)
-{
-        might_sleep();
-        imx_gpio_free(gpio);
-}
-static inline  int gpio_direction_input(unsigned gpio)
-{
-        return imx_gpio_direction_input(gpio);
-}
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        return imx_gpio_direction_output(gpio, value);
-}
-static inline int gpio_get_value(unsigned gpio)
-{
-        return imx_gpio_get_value(gpio);
-}
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        imx_gpio_set_value(gpio, value);
-}
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return imx_gpio_to_irq(gpio);
-}
-static inline int irq_to_gpio(unsigned irq)
-{
-        return imx_irq_to_gpio(irq);
-}
-#endif
diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h
deleted file mode 100644
index c73e9e724c75..000000000000
--- a/arch/arm/mach-imx/include/mach/hardware.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *  arch/arm/mach-imx/include/mach/hardware.h
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
-#include "imx-regs.h"
-#ifndef __ASSEMBLY__
-# define __REG(x)       (*((volatile u32 *)IO_ADDRESS(x)))
-# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
-#endif
-/*
- * Memory map
- */
-#define IMX_IO_PHYS             0x00200000
-#define IMX_IO_SIZE             0x00100000
-#define IMX_IO_BASE             0xe0000000
-#define IMX_CS0_PHYS            0x10000000
-#define IMX_CS0_SIZE            0x02000000
-#define IMX_CS0_VIRT            0xe8000000
-#define IMX_CS1_PHYS            0x12000000
-#define IMX_CS1_SIZE            0x01000000
-#define IMX_CS1_VIRT            0xea000000
-#define IMX_CS2_PHYS            0x13000000
-#define IMX_CS2_SIZE            0x01000000
-#define IMX_CS2_VIRT            0xeb000000
-#define IMX_CS3_PHYS            0x14000000
-#define IMX_CS3_SIZE            0x01000000
-#define IMX_CS3_VIRT            0xec000000
-#define IMX_CS4_PHYS            0x15000000
-#define IMX_CS4_SIZE            0x01000000
-#define IMX_CS4_VIRT            0xed000000
-#define IMX_CS5_PHYS            0x16000000
-#define IMX_CS5_SIZE            0x01000000
-#define IMX_CS5_VIRT            0xee000000
-#define IMX_FB_VIRT             0xF1000000
-#define IMX_FB_SIZE             (256*1024)
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
-#ifndef __ASSEMBLY__
-/*
- * Handy routine to set GPIO functions
- */
-extern void imx_gpio_mode( int gpio_mode );
-#endif
-#define MAXIRQNUM                       62
-#define MAXFIQNUM                       62
-#define MAXSWINUM                       62
-/*
- * Use SDRAM for memory
- */
-#define MEM_SIZE                0x01000000
-#ifdef CONFIG_ARCH_MX1ADS
-#include "mx1ads.h"
-#endif
-#endif
diff --git a/arch/arm/mach-imx/include/mach/imx-dma.h b/arch/arm/mach-imx/include/mach/imx-dma.h
deleted file mode 100644
index bbe54df7f0de..000000000000
--- a/arch/arm/mach-imx/include/mach/imx-dma.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *  linux/include/asm-arm/imxads/dma.h
- *
- *  Copyright (C) 1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <mach/dma.h>
-#ifndef __ASM_ARCH_IMX_DMA_H
-#define __ASM_ARCH_IMX_DMA_H
-#define IMX_DMA_CHANNELS  11
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @sgbc: counter of processed bytes in the actual read/written chunk
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-struct imx_dma_channel {
-        const char *name;
-        void (*irq_handler) (int, void *);
-        void (*err_handler) (int, void *, int errcode);
-        void *data;
-        unsigned int  dma_mode;
-        struct scatterlist *sg;
-        unsigned int sgbc;
-        unsigned int sgcount;
-        unsigned int resbytes;
-        int dma_num;
-};
-extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-#define IMX_DMA_ERR_BURST     1
-#define IMX_DMA_ERR_REQUEST   2
-#define IMX_DMA_ERR_TRANSFER  4
-#define IMX_DMA_ERR_BUFFER    8
-/* The type to distinguish channel numbers parameter from ordinal int type */
-typedef int imx_dmach_t;
-#define DMA_MODE_READ           0
-#define DMA_MODE_WRITE          1
-#define DMA_MODE_MASK           1
-int
-imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
-                unsigned int dma_length, unsigned int dev_addr, unsigned int dmamode);
-int
-imx_dma_setup_sg(imx_dmach_t dma_ch,
-                 struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
-                 unsigned int dev_addr, unsigned int dmamode);
-int
-imx_dma_setup_handlers(imx_dmach_t dma_ch,
-                void (*irq_handler) (int, void *),
-                void (*err_handler) (int, void *, int), void *data);
-void imx_dma_enable(imx_dmach_t dma_ch);
-void imx_dma_disable(imx_dmach_t dma_ch);
-int imx_dma_request(imx_dmach_t dma_ch, const char *name);
-void imx_dma_free(imx_dmach_t dma_ch);
-imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
-#endif  /* _ASM_ARCH_IMX_DMA_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
deleted file mode 100644
index 490297fc0e38..000000000000
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ /dev/null
@@ -1,376 +0,0 @@
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-/* ------------------------------------------------------------------------
- *  Motorola IMX system registers
- * ------------------------------------------------------------------------
- *
- */
-/*
- *  Register BASEs, based on OFFSETs
- *
- */
-#define IMX_AIPI1_BASE             (0x00000 + IMX_IO_BASE)
-#define IMX_WDT_BASE               (0x01000 + IMX_IO_BASE)
-#define IMX_TIM1_BASE              (0x02000 + IMX_IO_BASE)
-#define IMX_TIM2_BASE              (0x03000 + IMX_IO_BASE)
-#define IMX_RTC_BASE               (0x04000 + IMX_IO_BASE)
-#define IMX_LCDC_BASE              (0x05000 + IMX_IO_BASE)
-#define IMX_UART1_BASE             (0x06000 + IMX_IO_BASE)
-#define IMX_UART2_BASE             (0x07000 + IMX_IO_BASE)
-#define IMX_PWM_BASE               (0x08000 + IMX_IO_BASE)
-#define IMX_DMAC_BASE              (0x09000 + IMX_IO_BASE)
-#define IMX_AIPI2_BASE             (0x10000 + IMX_IO_BASE)
-#define IMX_SIM_BASE               (0x11000 + IMX_IO_BASE)
-#define IMX_USBD_BASE              (0x12000 + IMX_IO_BASE)
-#define IMX_SPI1_BASE              (0x13000 + IMX_IO_BASE)
-#define IMX_MMC_BASE               (0x14000 + IMX_IO_BASE)
-#define IMX_ASP_BASE               (0x15000 + IMX_IO_BASE)
-#define IMX_BTA_BASE               (0x16000 + IMX_IO_BASE)
-#define IMX_I2C_BASE               (0x17000 + IMX_IO_BASE)
-#define IMX_SSI_BASE               (0x18000 + IMX_IO_BASE)
-#define IMX_SPI2_BASE              (0x19000 + IMX_IO_BASE)
-#define IMX_MSHC_BASE              (0x1A000 + IMX_IO_BASE)
-#define IMX_PLL_BASE               (0x1B000 + IMX_IO_BASE)
-#define IMX_GPIO_BASE              (0x1C000 + IMX_IO_BASE)
-#define IMX_EIM_BASE               (0x20000 + IMX_IO_BASE)
-#define IMX_SDRAMC_BASE            (0x21000 + IMX_IO_BASE)
-#define IMX_MMA_BASE               (0x22000 + IMX_IO_BASE)
-#define IMX_AITC_BASE              (0x23000 + IMX_IO_BASE)
-#define IMX_CSI_BASE               (0x24000 + IMX_IO_BASE)
-/* PLL registers */
-#define CSCR   __REG(IMX_PLL_BASE)        /* Clock Source Control Register */
-#define CSCR_SPLL_RESTART       (1<<22)
-#define CSCR_MPLL_RESTART       (1<<21)
-#define CSCR_SYSTEM_SEL         (1<<16)
-#define CSCR_BCLK_DIV           (0xf<<10)
-#define CSCR_MPU_PRESC          (1<<15)
-#define CSCR_SPEN               (1<<1)
-#define CSCR_MPEN               (1<<0)
-#define MPCTL0 __REG(IMX_PLL_BASE + 0x4)  /* MCU PLL Control Register 0 */
-#define MPCTL1 __REG(IMX_PLL_BASE + 0x8)  /* MCU PLL and System Clock Register 1 */
-#define SPCTL0 __REG(IMX_PLL_BASE + 0xc)  /* System PLL Control Register 0 */
-#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
-#define PCDR   __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
-/*
- *  GPIO Module and I/O Multiplexer
- *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
- */
-#define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
-#define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
-#define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
-#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
-#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
-#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
-#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
-#define DR(x)      __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
-#define GIUS(x)    __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
-#define SSR(x)     __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
-#define ICR1(x)    __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
-#define ICR2(x)    __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
-#define IMR(x)     __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
-#define ISR(x)     __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
-#define GPR(x)     __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
-#define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
-#define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
-#define GPIO_PORT_MAX  3
-#define GPIO_PIN_MASK 0x1f
-#define GPIO_PORT_MASK (0x3 << 5)
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORTA (0<<5)
-#define GPIO_PORTB (1<<5)
-#define GPIO_PORTC (2<<5)
-#define GPIO_PORTD (3<<5)
-#define GPIO_OUT   (1<<7)
-#define GPIO_IN    (0<<7)
-#define GPIO_PUEN  (1<<8)
-#define GPIO_PF    (0<<9)
-#define GPIO_AF    (1<<9)
-#define GPIO_OCR_SHIFT 10
-#define GPIO_OCR_MASK (3<<10)
-#define GPIO_AIN   (0<<10)
-#define GPIO_BIN   (1<<10)
-#define GPIO_CIN   (2<<10)
-#define GPIO_DR    (3<<10)
-#define GPIO_AOUT_SHIFT 12
-#define GPIO_AOUT_MASK (3<<12)
-#define GPIO_AOUT     (0<<12)
-#define GPIO_AOUT_ISR (1<<12)
-#define GPIO_AOUT_0   (2<<12)
-#define GPIO_AOUT_1   (3<<12)
-#define GPIO_BOUT_SHIFT 14
-#define GPIO_BOUT_MASK (3<<14)
-#define GPIO_BOUT      (0<<14)
-#define GPIO_BOUT_ISR  (1<<14)
-#define GPIO_BOUT_0    (2<<14)
-#define GPIO_BOUT_1    (3<<14)
-#define GPIO_GIUS      (1<<16)
-/* assignements for GPIO alternate/primary functions */
-/* FIXME: This list is not completed. The correct directions are
- * missing on some (many) pins
- */
-#define PA0_AIN_SPI2_CLK     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
-#define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
-#define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
-#define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
-#define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
-#define PA4_PF_CSI_D0        ( GPIO_PORTA | GPIO_PF | 4 )
-#define PA5_PF_CSI_D1        ( GPIO_PORTA | GPIO_PF | 5 )
-#define PA6_PF_CSI_D2        ( GPIO_PORTA | GPIO_PF | 6 )
-#define PA7_PF_CSI_D3        ( GPIO_PORTA | GPIO_PF | 7 )
-#define PA8_PF_CSI_D4        ( GPIO_PORTA | GPIO_PF | 8 )
-#define PA9_PF_CSI_D5        ( GPIO_PORTA | GPIO_PF | 9 )
-#define PA10_PF_CSI_D6       ( GPIO_PORTA | GPIO_PF | 10 )
-#define PA11_PF_CSI_D7       ( GPIO_PORTA | GPIO_PF | 11 )
-#define PA12_PF_CSI_VSYNC    ( GPIO_PORTA | GPIO_PF | 12 )
-#define PA13_PF_CSI_HSYNC    ( GPIO_PORTA | GPIO_PF | 13 )
-#define PA14_PF_CSI_PIXCLK   ( GPIO_PORTA | GPIO_PF | 14 )
-#define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
-#define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
-#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
-#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
-#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
-#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
-#define PA21_PF_A0           ( GPIO_PORTA | GPIO_PF | 21 )
-#define PA22_PF_CS4          ( GPIO_PORTA | GPIO_PF | 22 )
-#define PA23_PF_CS5          ( GPIO_PORTA | GPIO_PF | 23 )
-#define PA24_PF_A16          ( GPIO_PORTA | GPIO_PF | 24 )
-#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
-#define PA25_PF_A17          ( GPIO_PORTA | GPIO_PF | 25 )
-#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
-#define PA26_PF_A18          ( GPIO_PORTA | GPIO_PF | 26 )
-#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
-#define PA27_PF_A19          ( GPIO_PORTA | GPIO_PF | 27 )
-#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
-#define PA28_PF_A20          ( GPIO_PORTA | GPIO_PF | 28 )
-#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
-#define PA29_PF_A21          ( GPIO_PORTA | GPIO_PF | 29 )
-#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
-#define PA30_PF_A22          ( GPIO_PORTA | GPIO_PF | 30 )
-#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
-#define PA31_PF_A23          ( GPIO_PORTA | GPIO_PF | 31 )
-#define PA31_AF_ETMTRACECLK  ( GPIO_PORTA | GPIO_AF | 31 )
-#define PB8_PF_SD_DAT0       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
-#define PB8_AF_MS_PIO        ( GPIO_PORTB | GPIO_AF | 8 )
-#define PB9_PF_SD_DAT1       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9 )
-#define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
-#define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
-#define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
-#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | 11 )
-#define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
-#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | 12 )
-#define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
-#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
-#define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
-#define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
-#define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
-#define PB16_AF_SSI_RXDAT    ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
-#define PB17_AF_SSI_TXDAT    ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
-#define PB18_AF_SSI_TXFS     ( GPIO_PORTB | GPIO_AF | 18 )
-#define PB19_AF_SSI_TXCLK    ( GPIO_PORTB | GPIO_AF | 19 )
-#define PB20_PF_USBD_AFE     ( GPIO_PORTB | GPIO_PF | 20 )
-#define PB21_PF_USBD_OE      ( GPIO_PORTB | GPIO_PF | 21 )
-#define PB22_PFUSBD_RCV      ( GPIO_PORTB | GPIO_PF | 22 )
-#define PB23_PF_USBD_SUSPND  ( GPIO_PORTB | GPIO_PF | 23 )
-#define PB24_PF_USBD_VP      ( GPIO_PORTB | GPIO_PF | 24 )
-#define PB25_PF_USBD_VM      ( GPIO_PORTB | GPIO_PF | 25 )
-#define PB26_PF_USBD_VPO     ( GPIO_PORTB | GPIO_PF | 26 )
-#define PB27_PF_USBD_VMO     ( GPIO_PORTB | GPIO_PF | 27 )
-#define PB28_PF_UART2_CTS    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
-#define PB29_PF_UART2_RTS    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
-#define PB30_PF_UART2_TXD    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
-#define PB31_PF_UART2_RXD    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
-#define PC3_PF_SSI_RXFS      ( GPIO_PORTC | GPIO_PF | 3 )
-#define PC4_PF_SSI_RXCLK     ( GPIO_PORTC | GPIO_PF | 4 )
-#define PC5_PF_SSI_RXDAT     ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
-#define PC6_PF_SSI_TXDAT     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
-#define PC7_PF_SSI_TXFS      ( GPIO_PORTC | GPIO_PF | 7 )
-#define PC8_PF_SSI_TXCLK     ( GPIO_PORTC | GPIO_PF | 8 )
-#define PC9_PF_UART1_CTS     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
-#define PC10_PF_UART1_RTS    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
-#define PC11_PF_UART1_TXD    ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
-#define PC12_PF_UART1_RXD    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
-#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
-#define PC14_PF_SPI1_SCLK    ( GPIO_PORTC | GPIO_PF | 14 )
-#define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
-#define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
-#define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
-#define PC24_BIN_UART3_RI    ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
-#define PC25_BIN_UART3_DSR   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
-#define PC26_AOUT_UART3_DTR  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
-#define PC27_BIN_UART3_DCD   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
-#define PC28_BIN_UART3_CTS   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
-#define PC29_AOUT_UART3_RTS  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
-#define PC30_BIN_UART3_TX    ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
-#define PC31_AOUT_UART3_RX   ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
-#define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
-#define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR     ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK    ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
-#define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
-#define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS      ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
-#define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
-#define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
-#define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
-#define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
-#define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
-#define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
-#define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
-#define PD14_PF_FLM_VSYNC    ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
-#define PD15_PF_LD0          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
-#define PD16_PF_LD1          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
-#define PD17_PF_LD2          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
-#define PD18_PF_LD3          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
-#define PD19_PF_LD4          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
-#define PD20_PF_LD5          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
-#define PD21_PF_LD6          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
-#define PD22_PF_LD7          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
-#define PD23_PF_LD8          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
-#define PD24_PF_LD9          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
-#define PD25_PF_LD10         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
-#define PD26_PF_LD11         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
-#define PD27_PF_LD12         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
-#define PD28_PF_LD13         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
-#define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
-#define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
-#define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
-/*
- * PWM controller
- */
-#define PWMC    __REG(IMX_PWM_BASE + 0x00)      /* PWM Control Register         */
-#define PWMS    __REG(IMX_PWM_BASE + 0x04)      /* PWM Sample Register          */
-#define PWMP    __REG(IMX_PWM_BASE + 0x08)      /* PWM Period Register          */
-#define PWMCNT  __REG(IMX_PWM_BASE + 0x0C)      /* PWM Counter Register         */
-#define PWMC_HCTR               (0x01<<18)              /* Halfword FIFO Data Swapping  */
-#define PWMC_BCTR               (0x01<<17)              /* Byte FIFO Data Swapping      */
-#define PWMC_SWR                (0x01<<16)              /* Software Reset               */
-#define PWMC_CLKSRC             (0x01<<15)              /* Clock Source                 */
-#define PWMC_PRESCALER(x)       (((x-1) & 0x7F) << 8)   /* PRESCALER                    */
-#define PWMC_IRQ                (0x01<< 7)              /* Interrupt Request            */
-#define PWMC_IRQEN              (0x01<< 6)              /* Interrupt Request Enable     */
-#define PWMC_FIFOAV             (0x01<< 5)              /* FIFO Available               */
-#define PWMC_EN                 (0x01<< 4)              /* Enables/Disables the PWM     */
-#define PWMC_REPEAT(x)          (((x) & 0x03) << 2)     /* Sample Repeats               */
-#define PWMC_CLKSEL(x)          (((x) & 0x03) << 0)     /* Clock Selection              */
-#define PWMS_SAMPLE(x)          ((x) & 0xFFFF)          /* Contains a two-sample word   */
-#define PWMP_PERIOD(x)          ((x) & 0xFFFF)          /* Represents the PWM's period  */
-#define PWMC_COUNTER(x)         ((x) & 0xFFFF)          /* Represents the current count value   */
-/*
- *  DMA Controller
- */
-#define DCR     __REG(IMX_DMAC_BASE +0x00)      /* DMA Control Register */
-#define DISR    __REG(IMX_DMAC_BASE +0x04)      /* DMA Interrupt status Register */
-#define DIMR    __REG(IMX_DMAC_BASE +0x08)      /* DMA Interrupt mask Register */
-#define DBTOSR  __REG(IMX_DMAC_BASE +0x0c)      /* DMA Burst timeout status Register */
-#define DRTOSR  __REG(IMX_DMAC_BASE +0x10)      /* DMA Request timeout Register */
-#define DSESR   __REG(IMX_DMAC_BASE +0x14)      /* DMA Transfer Error Status Register */
-#define DBOSR   __REG(IMX_DMAC_BASE +0x18)      /* DMA Buffer overflow status Register */
-#define DBTOCR  __REG(IMX_DMAC_BASE +0x1c)      /* DMA Burst timeout control Register */
-#define WSRA    __REG(IMX_DMAC_BASE +0x40)      /* W-Size Register A */
-#define XSRA    __REG(IMX_DMAC_BASE +0x44)      /* X-Size Register A */
-#define YSRA    __REG(IMX_DMAC_BASE +0x48)      /* Y-Size Register A */
-#define WSRB    __REG(IMX_DMAC_BASE +0x4c)      /* W-Size Register B */
-#define XSRB    __REG(IMX_DMAC_BASE +0x50)      /* X-Size Register B */
-#define YSRB    __REG(IMX_DMAC_BASE +0x54)      /* Y-Size Register B */
-#define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
-#define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
-#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
-#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
-#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
-#define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
-#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
-#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff )
-#define CNTR_CNT(x)        ((x) & 0xffffff )
-#define CCR_DMOD_LINEAR    ( 0x0 << 12 )
-#define CCR_DMOD_2D        ( 0x1 << 12 )
-#define CCR_DMOD_FIFO      ( 0x2 << 12 )
-#define CCR_DMOD_EOBFIFO   ( 0x3 << 12 )
-#define CCR_SMOD_LINEAR    ( 0x0 << 10 )
-#define CCR_SMOD_2D        ( 0x1 << 10 )
-#define CCR_SMOD_FIFO      ( 0x2 << 10 )
-#define CCR_SMOD_EOBFIFO   ( 0x3 << 10 )
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        ( 0x0 << 6 )
-#define CCR_DSIZ_8         ( 0x1 << 6 )
-#define CCR_DSIZ_16        ( 0x2 << 6 )
-#define CCR_SSIZ_32        ( 0x0 << 4 )
-#define CCR_SSIZ_8         ( 0x1 << 4 )
-#define CCR_SSIZ_16        ( 0x2 << 4 )
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-/*
- *  Interrupt controller
- */
-#define IMX_INTCNTL        __REG(IMX_AITC_BASE+0x00)
-#define INTCNTL_FIAD       (1<<19)
-#define INTCNTL_NIAD       (1<<20)
-#define IMX_NIMASK         __REG(IMX_AITC_BASE+0x04)
-#define IMX_INTENNUM       __REG(IMX_AITC_BASE+0x08)
-#define IMX_INTDISNUM      __REG(IMX_AITC_BASE+0x0c)
-#define IMX_INTENABLEH     __REG(IMX_AITC_BASE+0x10)
-#define IMX_INTENABLEL     __REG(IMX_AITC_BASE+0x14)
-/*
- *  General purpose timers
- */
-#define IMX_TCTL(x)        __REG( 0x00 + (x))
-#define TCTL_SWR           (1<<15)
-#define TCTL_FRR           (1<<8)
-#define TCTL_CAP_RIS       (1<<6)
-#define TCTL_CAP_FAL       (2<<6)
-#define TCTL_CAP_RIS_FAL   (3<<6)
-#define TCTL_OM            (1<<5)
-#define TCTL_IRQEN         (1<<4)
-#define TCTL_CLK_PCLK1     (1<<1)
-#define TCTL_CLK_PCLK1_16  (2<<1)
-#define TCTL_CLK_TIN       (3<<1)
-#define TCTL_CLK_32        (4<<1)
-#define TCTL_TEN           (1<<0)
-#define IMX_TPRER(x)       __REG( 0x04 + (x))
-#define IMX_TCMP(x)        __REG( 0x08 + (x))
-#define IMX_TCR(x)         __REG( 0x0C + (x))
-#define IMX_TCN(x)         __REG( 0x10 + (x))
-#define IMX_TSTAT(x)       __REG( 0x14 + (x))
-#define TSTAT_CAPT         (1<<1)
-#define TSTAT_COMP         (1<<0)
-#endif                          // _IMX_REGS_H
diff --git a/arch/arm/mach-imx/include/mach/imx-uart.h b/arch/arm/mach-imx/include/mach/imx-uart.h
deleted file mode 100644
index d54eb1d48026..000000000000
--- a/arch/arm/mach-imx/include/mach/imx-uart.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef ASMARM_ARCH_UART_H
-#define ASMARM_ARCH_UART_H
-#define IMXUART_HAVE_RTSCTS (1<<0)
-struct imxuart_platform_data {
-        int (*init)(struct platform_device *pdev);
-        void (*exit)(struct platform_device *pdev);
-        unsigned int flags;
-};
-#endif
diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h
deleted file mode 100644
index 67812c5ac1f9..000000000000
--- a/arch/arm/mach-imx/include/mach/irqs.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- *  arch/arm/mach-imxads/include/mach/irqs.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ARM_IRQS_H__
-#define __ARM_IRQS_H__
-/* Use the imx definitions */
-#include <mach/hardware.h>
-/*
- *  IMX Interrupt numbers
- *
- */
-#define INT_SOFTINT                 0
-#define CSI_INT                     6
-#define DSPA_MAC_INT                7
-#define DSPA_INT                    8
-#define COMP_INT                    9
-#define MSHC_XINT                   10
-#define GPIO_INT_PORTA              11
-#define GPIO_INT_PORTB              12
-#define GPIO_INT_PORTC              13
-#define LCDC_INT                    14
-#define SIM_INT                     15
-#define SIM_DATA_INT                16
-#define RTC_INT                     17
-#define RTC_SAMINT                  18
-#define UART2_MINT_PFERR            19
-#define UART2_MINT_RTS              20
-#define UART2_MINT_DTR              21
-#define UART2_MINT_UARTC            22
-#define UART2_MINT_TX               23
-#define UART2_MINT_RX               24
-#define UART1_MINT_PFERR            25
-#define UART1_MINT_RTS              26
-#define UART1_MINT_DTR              27
-#define UART1_MINT_UARTC            28
-#define UART1_MINT_TX               29
-#define UART1_MINT_RX               30
-#define VOICE_DAC_INT               31
-#define VOICE_ADC_INT               32
-#define PEN_DATA_INT                33
-#define PWM_INT                     34
-#define SDHC_INT                    35
-#define I2C_INT                     39
-#define CSPI_INT                    41
-#define SSI_TX_INT                  42
-#define SSI_TX_ERR_INT              43
-#define SSI_RX_INT                  44
-#define SSI_RX_ERR_INT              45
-#define TOUCH_INT                   46
-#define USBD_INT0                   47
-#define USBD_INT1                   48
-#define USBD_INT2                   49
-#define USBD_INT3                   50
-#define USBD_INT4                   51
-#define USBD_INT5                   52
-#define USBD_INT6                   53
-#define BTSYS_INT                   55
-#define BTTIM_INT                   56
-#define BTWUI_INT                   57
-#define TIM2_INT                    58
-#define TIM1_INT                    59
-#define DMA_ERR                     60
-#define DMA_INT                     61
-#define GPIO_INT_PORTD              62
-#define IMX_IRQS                         (64)
-/* note: the IMX has four gpio ports (A-D), but only
- *       the following pins are connected to the outside
- *       world:
- *
- * PORT A: bits 0-31
- * PORT B: bits 8-31
- * PORT C: bits 3-17
- * PORT D: bits 6-31
- *
- * We map these interrupts straight on. As a result we have
- * several holes in the interrupt mapping. We do this for two
- * reasons:
- *   - mapping the interrupts without holes would get
- *     far more complicated
- *   - Motorola could well decide to bring some processor
- *     with more pins connected
- */
-#define IRQ_GPIOA(x)  (IMX_IRQS + x)
-#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
-#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
-#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
-/* decode irq number to use with IMR(x), ISR(x) and friends */
-#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
-/* all normal IRQs can be FIQs */
-#define FIQ_START       0
-/* switch betwean IRQ and FIQ */
-extern int imx_set_irq_fiq(unsigned int irq, unsigned int type);
-#define NR_IRQS (IRQ_GPIOD(32) + 1)
-#define IRQ_GPIO(x)
-#endif
diff --git a/arch/arm/mach-imx/include/mach/mmc.h b/arch/arm/mach-imx/include/mach/mmc.h
deleted file mode 100644
index 4712f354dcca..000000000000
--- a/arch/arm/mach-imx/include/mach/mmc.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef ASMARM_ARCH_MMC_H
-#define ASMARM_ARCH_MMC_H
-#include <linux/mmc/host.h>
-struct device;
-struct imxmmc_platform_data {
-        int (*card_present)(struct device *);
-        int (*get_ro)(struct device *);
-};
-extern void imx_set_mmc_info(struct imxmmc_platform_data *info);
-#endif
diff --git a/arch/arm/mach-imx/include/mach/mx1ads.h b/arch/arm/mach-imx/include/mach/mx1ads.h
deleted file mode 100644
index def05d510eb3..000000000000
--- a/arch/arm/mach-imx/include/mach/mx1ads.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-imx/include/mach/mx1ads.h
- *
- * Copyright (C) 2004 Robert Schwebel, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#ifndef __ASM_ARCH_MX1ADS_H
-#define __ASM_ARCH_MX1ADS_H
-/* ------------------------------------------------------------------------ */
-/* Memory Map for the M9328MX1ADS (MX1ADS) Board                            */
-/* ------------------------------------------------------------------------ */
-#define MX1ADS_FLASH_PHYS               0x10000000
-#define MX1ADS_FLASH_SIZE               (16*1024*1024)
-#define IMX_FB_PHYS                     (0x0C000000 - 0x40000)
-#define CLK32 32000
-#endif /* __ASM_ARCH_MX1ADS_H */
diff --git a/arch/arm/mach-imx/include/mach/spi_imx.h b/arch/arm/mach-imx/include/mach/spi_imx.h
deleted file mode 100644
index 4186430feecf..000000000000
--- a/arch/arm/mach-imx/include/mach/spi_imx.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * arch/arm/mach-imx/include/mach/spi_imx.h
- *
- * Copyright (C) 2006 SWAPP
- *      Andrea Paterniani <a.paterniani@swapp-eng.it>
- *
- * Initial version inspired by:
- *      linux-2.6.17-rc3-mm1/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef SPI_IMX_H_
-#define SPI_IMX_H_
-/*-------------------------------------------------------------------------*/
-/**
- * struct spi_imx_master - device.platform_data for SPI controller devices.
- * @num_chipselect: chipselects are used to distinguish individual
- *      SPI slaves, and are numbered from zero to num_chipselects - 1.
- *      each slave has a chipselect signal, but it's common that not
- *      every chipselect is connected to a slave.
- * @enable_dma: if true enables DMA driven transfers.
-*/
-struct spi_imx_master {
-        u8 num_chipselect;
-        u8 enable_dma:1;
-};
-/*-------------------------------------------------------------------------*/
-/*-------------------------------------------------------------------------*/
-/**
- * struct spi_imx_chip - spi_board_info.controller_data for SPI
- * slave devices, copied to spi_device.controller_data.
- * @enable_loopback : used for test purpouse to internally connect RX and TX
- *      sections.
- * @enable_dma : enables dma transfer (provided that controller driver has
- *      dma enabled too).
- * @ins_ss_pulse : enable /SS pulse insertion between SPI burst.
- * @bclk_wait : number of bclk waits between each bits_per_word SPI burst.
- * @cs_control : function pointer to board-specific function to assert/deassert
- *      I/O port to control HW generation of devices chip-select.
-*/
-struct spi_imx_chip {
-        u8      enable_loopback:1;
-        u8      enable_dma:1;
-        u8      ins_ss_pulse:1;
-        u16     bclk_wait:15;
-        void (*cs_control)(u32 control);
-};
-/* Chip-select state */
-#define SPI_CS_ASSERT                   (1 << 0)
-#define SPI_CS_DEASSERT                 (1 << 1)
-/*-------------------------------------------------------------------------*/
-#endif /* SPI_IMX_H_*/
diff --git a/arch/arm/mach-imx/include/mach/uncompress.h b/arch/arm/mach-imx/include/mach/uncompress.h
deleted file mode 100644
index 70523e67a8f6..000000000000
--- a/arch/arm/mach-imx/include/mach/uncompress.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- *  arch/arm/mach-imxads/include/mach/uncompress.h
- *
- *
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
-#define UART1_BASE 0x206000
-#define UART2_BASE 0x207000
-#define USR2 0x98
-#define USR2_TXFE (1<<14)
-#define TXR  0x40
-#define UCR1 0x80
-#define UCR1_UARTEN 1
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-static void putc(int c)
-{
-        unsigned long serial_port;
-        do {
-                serial_port = UART1_BASE;
-                if ( UART(UCR1) & UCR1_UARTEN )
-                        break;
-                serial_port = UART2_BASE;
-                if ( UART(UCR1) & UCR1_UARTEN )
-                        break;
-                return;
-        } while(0);
-        while (!(UART(USR2) & USR2_TXFE))
-                barrier();
-        UART(TXR) = c;
-}
-static inline void flush(void)
-{
-}
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
deleted file mode 100644
index 531b95deadc0..000000000000
--- a/arch/arm/mach-imx/irq.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/irq.c
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *  03/03/2004   Sascha Hauer <sascha@saschahauer.de>
- *               Copied from the motorola bsp package and added gpio demux
- *               interrupt handler
- */
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
-/*
- *
- * We simply use the ENABLE DISABLE registers inside of the IMX
- * to turn on/off specific interrupts.
- *
- */
-#define INTCNTL_OFF               0x00
-#define NIMASK_OFF                0x04
-#define INTENNUM_OFF              0x08
-#define INTDISNUM_OFF             0x0C
-#define INTENABLEH_OFF            0x10
-#define INTENABLEL_OFF            0x14
-#define INTTYPEH_OFF              0x18
-#define INTTYPEL_OFF              0x1C
-#define NIPRIORITY_OFF(x)         (0x20+4*(7-(x)))
-#define NIVECSR_OFF               0x40
-#define FIVECSR_OFF               0x44
-#define INTSRCH_OFF               0x48
-#define INTSRCL_OFF               0x4C
-#define INTFRCH_OFF               0x50
-#define INTFRCL_OFF               0x54
-#define NIPNDH_OFF                0x58
-#define NIPNDL_OFF                0x5C
-#define FIPNDH_OFF                0x60
-#define FIPNDL_OFF                0x64
-#define VA_AITC_BASE              IO_ADDRESS(IMX_AITC_BASE)
-#define IMX_AITC_INTCNTL         (VA_AITC_BASE + INTCNTL_OFF)
-#define IMX_AITC_NIMASK          (VA_AITC_BASE + NIMASK_OFF)
-#define IMX_AITC_INTENNUM        (VA_AITC_BASE + INTENNUM_OFF)
-#define IMX_AITC_INTDISNUM       (VA_AITC_BASE + INTDISNUM_OFF)
-#define IMX_AITC_INTENABLEH      (VA_AITC_BASE + INTENABLEH_OFF)
-#define IMX_AITC_INTENABLEL      (VA_AITC_BASE + INTENABLEL_OFF)
-#define IMX_AITC_INTTYPEH        (VA_AITC_BASE + INTTYPEH_OFF)
-#define IMX_AITC_INTTYPEL        (VA_AITC_BASE + INTTYPEL_OFF)
-#define IMX_AITC_NIPRIORITY(x)   (VA_AITC_BASE + NIPRIORITY_OFF(x))
-#define IMX_AITC_NIVECSR         (VA_AITC_BASE + NIVECSR_OFF)
-#define IMX_AITC_FIVECSR         (VA_AITC_BASE + FIVECSR_OFF)
-#define IMX_AITC_INTSRCH         (VA_AITC_BASE + INTSRCH_OFF)
-#define IMX_AITC_INTSRCL         (VA_AITC_BASE + INTSRCL_OFF)
-#define IMX_AITC_INTFRCH         (VA_AITC_BASE + INTFRCH_OFF)
-#define IMX_AITC_INTFRCL         (VA_AITC_BASE + INTFRCL_OFF)
-#define IMX_AITC_NIPNDH          (VA_AITC_BASE + NIPNDH_OFF)
-#define IMX_AITC_NIPNDL          (VA_AITC_BASE + NIPNDL_OFF)
-#define IMX_AITC_FIPNDH          (VA_AITC_BASE + FIPNDH_OFF)
-#define IMX_AITC_FIPNDL          (VA_AITC_BASE + FIPNDL_OFF)
-#if 0
-#define DEBUG_IRQ(fmt...)       printk(fmt)
-#else
-#define DEBUG_IRQ(fmt...)       do { } while (0)
-#endif
-static void
-imx_mask_irq(unsigned int irq)
-{
-        __raw_writel(irq, IMX_AITC_INTDISNUM);
-}
-static void
-imx_unmask_irq(unsigned int irq)
-{
-        __raw_writel(irq, IMX_AITC_INTENNUM);
-}
-#ifdef CONFIG_FIQ
-int imx_set_irq_fiq(unsigned int irq, unsigned int type)
-{
-        unsigned int irqt;
-        if (irq >= IMX_IRQS)
-                return -EINVAL;
-        if (irq < IMX_IRQS / 2) {
-                irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq);
-                __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL);
-        } else {
-                irq -= IMX_IRQS / 2;
-                irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq);
-                __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH);
-        }
-        return 0;
-}
-EXPORT_SYMBOL(imx_set_irq_fiq);
-#endif /* CONFIG_FIQ */
-static int
-imx_gpio_irq_type(unsigned int _irq, unsigned int type)
-{
-        unsigned int irq_type = 0, irq, reg, bit;
-        irq = _irq - IRQ_GPIOA(0);
-        reg = irq >> 5;
-        bit = 1 << (irq % 32);
-        if (type == IRQ_TYPE_PROBE) {
-                /* Don't mess with enabled GPIOs using preconfigured edges or
-                   GPIOs set to alternate function during probe */
-                /* TODO: support probe */
-//              if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
-//                  GPIO_bit(gpio))
-//                      return 0;
-//              if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
-//                      return 0;
-//              type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-        }
-        GIUS(reg) |= bit;
-        DDIR(reg) &= ~(bit);
-        DEBUG_IRQ("setting type of irq %d to ", _irq);
-        if (type & IRQ_TYPE_EDGE_RISING) {
-                DEBUG_IRQ("rising edges\n");
-                irq_type = 0x0;
-        }
-        if (type & IRQ_TYPE_EDGE_FALLING) {
-                DEBUG_IRQ("falling edges\n");
-                irq_type = 0x1;
-        }
-        if (type & IRQ_TYPE_LEVEL_LOW) {
-                DEBUG_IRQ("low level\n");
-                irq_type = 0x3;
-        }
-        if (type & IRQ_TYPE_LEVEL_HIGH) {
-                DEBUG_IRQ("high level\n");
-                irq_type = 0x2;
-        }
-        if (irq % 32 < 16) {
-                ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
-                    (irq_type << ((irq % 16) * 2));
-        } else {
-                ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
-                    (irq_type << ((irq % 16) * 2));
-        }
-        return 0;
-}
-static void
-imx_gpio_ack_irq(unsigned int irq)
-{
-        DEBUG_IRQ("%s: irq %d\n", __func__, irq);
-        ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
-}
-static void
-imx_gpio_mask_irq(unsigned int irq)
-{
-        DEBUG_IRQ("%s: irq %d\n", __func__, irq);
-        IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
-}
-static void
-imx_gpio_unmask_irq(unsigned int irq)
-{
-        DEBUG_IRQ("%s: irq %d\n", __func__, irq);
-        IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
-}
-static void
-imx_gpio_handler(unsigned int mask, unsigned int irq,
-                 struct irq_desc *desc)
-{
-        while (mask) {
-                if (mask & 1) {
-                        DEBUG_IRQ("handling irq %d\n", irq);
-                        generic_handle_irq(irq);
-                }
-                irq++;
-                mask >>= 1;
-        }
-}
-static void
-imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-        mask = ISR(0);
-        irq = IRQ_GPIOA(0);
-        imx_gpio_handler(mask, irq, desc);
-}
-static void
-imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-        mask = ISR(1);
-        irq = IRQ_GPIOB(0);
-        imx_gpio_handler(mask, irq, desc);
-}
-static void
-imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-        mask = ISR(2);
-        irq = IRQ_GPIOC(0);
-        imx_gpio_handler(mask, irq, desc);
-}
-static void
-imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-        mask = ISR(3);
-        irq = IRQ_GPIOD(0);
-        imx_gpio_handler(mask, irq, desc);
-}
-static struct irq_chip imx_internal_chip = {
-        .name = "MPU",
-        .ack = imx_mask_irq,
-        .mask = imx_mask_irq,
-        .unmask = imx_unmask_irq,
-};
-static struct irq_chip imx_gpio_chip = {
-        .name = "GPIO",
-        .ack = imx_gpio_ack_irq,
-        .mask = imx_gpio_mask_irq,
-        .unmask = imx_gpio_unmask_irq,
-        .set_type = imx_gpio_irq_type,
-};
-void __init
-imx_init_irq(void)
-{
-        unsigned int irq;
-        DEBUG_IRQ("Initializing imx interrupts\n");
-        /* Disable all interrupts initially. */
-        /* Do not rely on the bootloader. */
-        __raw_writel(0, IMX_AITC_INTENABLEH);
-        __raw_writel(0, IMX_AITC_INTENABLEL);
-        /* Mask all GPIO interrupts as well */
-        IMR(0) = 0;
-        IMR(1) = 0;
-        IMR(2) = 0;
-        IMR(3) = 0;
-        for (irq = 0; irq < IMX_IRQS; irq++) {
-                set_irq_chip(irq, &imx_internal_chip);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
-                set_irq_chip(irq, &imx_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
-        set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
-        set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
-        set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
-        /* Release masking of interrupts according to priority */
-        __raw_writel(-1, IMX_AITC_NIMASK);
-#ifdef CONFIG_FIQ
-        /* Initialize FIQ */
-        init_FIQ();
-#endif
-}
diff --git a/arch/arm/mach-imx/leds-mx1ads.c b/arch/arm/mach-imx/leds-mx1ads.c
deleted file mode 100644
index 1d48f2762cbc..000000000000
--- a/arch/arm/mach-imx/leds-mx1ads.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * linux/arch/arm/mach-imx/leds-mx1ads.c
- *
- * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/system.h>
-#include <asm/leds.h>
-#include "leds.h"
-/*
- * The MX1ADS Board has only one usable LED,
- * so select only the timer led or the
- * cpu usage led
- */
-void
-mx1ads_leds_event(led_event_t ledevt)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (ledevt) {
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                DR(0) &= ~(1<<2);
-                break;
-        case led_idle_end:
-                DR(0) |= 1<<2;
-                break;
-#endif
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                DR(0) ^= 1<<2;
-#endif
-        default:
-                break;
-        }
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-imx/leds.c b/arch/arm/mach-imx/leds.c
deleted file mode 100644
index cf30803e019b..000000000000
--- a/arch/arm/mach-imx/leds.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * linux/arch/arm/mach-imx/leds.c
- *
- * Copyright (C) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include "leds.h"
-static int __init
-leds_init(void)
-{
-        if (machine_is_mx1ads()) {
-                leds_event = mx1ads_leds_event;
-        }
-        return 0;
-}
-__initcall(leds_init);
diff --git a/arch/arm/mach-imx/leds.h b/arch/arm/mach-imx/leds.h
deleted file mode 100644
index 49dc1c1da338..000000000000
--- a/arch/arm/mach-imx/leds.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-imx/leds.h
- *
- * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * blinky lights for IMX-based systems
- *
- */
-extern void mx1ads_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c
deleted file mode 100644
index 87fa1ff43b0b..000000000000
--- a/arch/arm/mach-imx/mx1ads.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/arm/mach-imx/mx1ads.c
- *
- * Initially based on:
- *      linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
- *      Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- *
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <asm/system.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/mmc.h>
-#include <mach/imx-uart.h>
-#include <linux/interrupt.h>
-#include "generic.h"
-static struct resource cs89x0_resources[] = {
-        [0] = {
-                .start  = IMX_CS4_PHYS + 0x300,
-                .end    = IMX_CS4_PHYS + 0x300 + 16,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_GPIOC(17),
-                .end    = IRQ_GPIOC(17),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device cs89x0_device = {
-        .name           = "cirrus-cs89x0",
-        .num_resources  = ARRAY_SIZE(cs89x0_resources),
-        .resource       = cs89x0_resources,
-};
-static struct imxuart_platform_data uart_pdata = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static struct resource imx_uart1_resources[] = {
-        [0] = {
-                .start  = 0x00206000,
-                .end    = 0x002060FF,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = (UART1_MINT_RX),
-                .end    = (UART1_MINT_RX),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = (UART1_MINT_TX),
-                .end    = (UART1_MINT_TX),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = UART1_MINT_RTS,
-                .end    = UART1_MINT_RTS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device imx_uart1_device = {
-        .name           = "imx-uart",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(imx_uart1_resources),
-        .resource       = imx_uart1_resources,
-        .dev = {
-                .platform_data = &uart_pdata,
-        }
-};
-static struct resource imx_uart2_resources[] = {
-        [0] = {
-                .start  = 0x00207000,
-                .end    = 0x002070FF,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = (UART2_MINT_RX),
-                .end    = (UART2_MINT_RX),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = (UART2_MINT_TX),
-                .end    = (UART2_MINT_TX),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = UART2_MINT_RTS,
-                .end    = UART2_MINT_RTS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device imx_uart2_device = {
-        .name           = "imx-uart",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(imx_uart2_resources),
-        .resource       = imx_uart2_resources,
-        .dev = {
-                .platform_data = &uart_pdata,
-        }
-};
-static struct platform_device *devices[] __initdata = {
-        &cs89x0_device,
-        &imx_uart1_device,
-        &imx_uart2_device,
-};
-#if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE)
-static int mx1ads_mmc_card_present(struct device *dev)
-{
-        /* MMC/SD Card Detect is PB 20 on MX1ADS V1.0.7 */
-        return (SSR(1) & (1 << 20) ? 0 : 1);
-}
-static struct imxmmc_platform_data mx1ads_mmc_info = {
-       .card_present = mx1ads_mmc_card_present,
-};
-#endif
-static void __init
-mx1ads_init(void)
-{
-#ifdef CONFIG_LEDS
-        imx_gpio_mode(GPIO_PORTA | GPIO_OUT | 2);
-#endif
-#if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE)
-        /* SD/MMC card detect */
-        imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_IN | 20);
-        imx_set_mmc_info(&mx1ads_mmc_info);
-#endif
-        imx_gpio_mode(PC9_PF_UART1_CTS);
-        imx_gpio_mode(PC10_PF_UART1_RTS);
-        imx_gpio_mode(PC11_PF_UART1_TXD);
-        imx_gpio_mode(PC12_PF_UART1_RXD);
-        imx_gpio_mode(PB28_PF_UART2_CTS);
-        imx_gpio_mode(PB29_PF_UART2_RTS);
-        imx_gpio_mode(PB30_PF_UART2_TXD);
-        imx_gpio_mode(PB31_PF_UART2_RXD);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-static void __init
-mx1ads_map_io(void)
-{
-        imx_map_io();
-}
-MACHINE_START(MX1ADS, "Motorola MX1ADS")
-        /* Maintainer: Sascha Hauer, Pengutronix */
-        .phys_io        = 0x00200000,
-        .io_pg_offst    = ((0xe0000000) >> 18) & 0xfffc,
-        .boot_params    = 0x08000100,
-        .map_io         = mx1ads_map_io,
-        .init_irq       = imx_init_irq,
-        .timer          = &imx_timer,
-        .init_machine   = mx1ads_init,
-MACHINE_END
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
deleted file mode 100644
index 5aef18b599e5..000000000000
--- a/arch/arm/mach-imx/time.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/time.c
- *
- *  Copyright (C) 2000-2001 Deep Blue Solutions
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/time.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/irq.h>
-#include <asm/mach/time.h>
-/* Use timer 1 as system timer */
-#define TIMER_BASE IMX_TIM1_BASE
-static struct clock_event_device clockevent_imx;
-static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-imx_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = &clockevent_imx;
-        uint32_t tstat;
-        irqreturn_t ret = IRQ_NONE;
-        /* clear the interrupt */
-        tstat = IMX_TSTAT(TIMER_BASE);
-        IMX_TSTAT(TIMER_BASE) = 0;
-        if (tstat & TSTAT_COMP) {
-                evt->event_handler(evt);
-                ret = IRQ_HANDLED;
-        }
-        return ret;
-}
-static struct irqaction imx_timer_irq = {
-        .name           = "i.MX Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = imx_timer_interrupt,
-};
-/*
- * Set up timer hardware into expected mode and state.
- */
-static void __init imx_timer_hardware_init(void)
-{
-        /*
-         * Initialise to a known state (all timers off, and timing reset)
-         */
-        IMX_TCTL(TIMER_BASE) = 0;
-        IMX_TPRER(TIMER_BASE) = 0;
-        IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN;
-}
-cycle_t imx_get_cycles(struct clocksource *cs)
-{
-        return IMX_TCN(TIMER_BASE);
-}
-static struct clocksource clocksource_imx = {
-        .name           = "imx_timer1",
-        .rating         = 200,
-        .read           = imx_get_cycles,
-        .mask           = 0xFFFFFFFF,
-        .shift          = 20,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-static int __init imx_clocksource_init(unsigned long rate)
-{
-        clocksource_imx.mult =
-                clocksource_hz2mult(rate, clocksource_imx.shift);
-        clocksource_register(&clocksource_imx);
-        return 0;
-}
-static int imx_set_next_event(unsigned long evt,
-                                  struct clock_event_device *unused)
-{
-        unsigned long tcmp;
-        tcmp = IMX_TCN(TIMER_BASE) + evt;
-        IMX_TCMP(TIMER_BASE) = tcmp;
-        return (int32_t)(tcmp - IMX_TCN(TIMER_BASE)) < 0 ? -ETIME : 0;
-}
-#ifdef DEBUG
-static const char *clock_event_mode_label[]={
-        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
-        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
-        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
-        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
-};
-#endif /*DEBUG*/
-static void imx_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
-{
-        unsigned long flags;
-        /*
-         * The timer interrupt generation is disabled at least
-         * for enough time to call imx_set_next_event()
-         */
-        local_irq_save(flags);
-        /* Disable interrupt in GPT module */
-        IMX_TCTL(TIMER_BASE) &= ~TCTL_IRQEN;
-        if (mode != clockevent_mode) {
-                /* Set event time into far-far future */
-                IMX_TCMP(TIMER_BASE) = IMX_TCN(TIMER_BASE) - 3;
-                /* Clear pending interrupt */
-                IMX_TSTAT(TIMER_BASE) &= ~TSTAT_COMP;
-        }
-#ifdef DEBUG
-        printk(KERN_INFO "imx_set_mode: changing mode from %s to %s\n",
-                clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]);
-#endif /*DEBUG*/
-        /* Remember timer mode */
-        clockevent_mode = mode;
-        local_irq_restore(flags);
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                printk(KERN_ERR "imx_set_mode: Periodic mode is not supported for i.MX\n");
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                /*
-                 * Do not put overhead of interrupt enable/disable into
-                 * imx_set_next_event(), the core has about 4 minutes
-                 * to call imx_set_next_event() or shutdown clock after
-                 * mode switching
-                 */
-                local_irq_save(flags);
-                IMX_TCTL(TIMER_BASE) |= TCTL_IRQEN;
-                local_irq_restore(flags);
-                break;
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_RESUME:
-                /* Left event sources disabled, no more interrupts appears */
-                break;
-        }
-}
-static struct clock_event_device clockevent_imx = {
-        .name           = "imx_timer1",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
-        .set_mode       = imx_set_mode,
-        .set_next_event = imx_set_next_event,
-        .rating         = 200,
-};
-static int __init imx_clockevent_init(unsigned long rate)
-{
-        clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC,
-                                        clockevent_imx.shift);
-        clockevent_imx.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &clockevent_imx);
-        clockevent_imx.min_delta_ns =
-                clockevent_delta2ns(0xf, &clockevent_imx);
-        clockevent_imx.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_imx);
-        return 0;
-}
-extern int imx_clocks_init(void);
-static void __init imx_timer_init(void)
-{
-        struct clk *clk;
-        unsigned long rate;
-        imx_clocks_init();
-        clk = clk_get(NULL, "perclk1");
-        clk_enable(clk);
-        rate = clk_get_rate(clk);
-        imx_timer_hardware_init();
-        imx_clocksource_init(rate);
-        imx_clockevent_init(rate);
-        /*
-         * Make irqs happen for the system timer
-         */
-        setup_irq(TIM1_INT, &imx_timer_irq);
-}
-struct sys_timer imx_timer = {
-        .init           = imx_timer_init,
-};
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 2c5a02b8520e..264f4d59f898 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -78,6 +78,12 @@ config MACH_IXDP465
          IXDP465 Development Platform (Also known as BMP).
          For more information on this platform, see <file:Documentation/arm/IXP4xx>.
+config MACH_GORAMO_MLR
+        bool "GORAMO Multi Link Router"
+        help
+          Say 'Y' here if you want your kernel to support GORAMO
+          MultiLink router.
 config MACH_KIXRP435
        bool "KIXRP435"
        help
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index 2e6bbf927a74..47d1f60d23fa 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MACH_DSMG600)      += dsmg600-setup.o
 obj-$(CONFIG_MACH_GATEWAY7001)  += gateway7001-setup.o
 obj-$(CONFIG_MACH_WG302V2)      += wg302v2-setup.o
 obj-$(CONFIG_MACH_FSG)          += fsg-setup.o
+obj-$(CONFIG_MACH_GORAMO_MLR)   += goramo_mlr.o
 obj-$(CONFIG_PCI)               += $(obj-pci-$(CONFIG_PCI)) common-pci.o
 obj-$(CONFIG_IXP4XX_QMGR)       += ixp4xx_qmgr.o
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
new file mode 100644
index 000000000000..a733b8ff3cec
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -0,0 +1,507 @@
+/*
+ * Goramo MultiLink router platform code
+ * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
+ */
+#include <linux/delay.h>
+#include <linux/hdlc.h>
+#include <linux/i2c-gpio.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/serial_8250.h>
+#include <asm/mach-types.h>
+#include <asm/system.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/pci.h>
+#define xgpio_irq(n)            (IRQ_IXP4XX_GPIO ## n)
+#define gpio_irq(n)             xgpio_irq(n)
+#define SLOT_ETHA               0x0B    /* IDSEL = AD21 */
+#define SLOT_ETHB               0x0C    /* IDSEL = AD20 */
+#define SLOT_MPCI               0x0D    /* IDSEL = AD19 */
+#define SLOT_NEC                0x0E    /* IDSEL = AD18 */
+#define IRQ_ETHA                IRQ_IXP4XX_GPIO4
+#define IRQ_ETHB                IRQ_IXP4XX_GPIO5
+#define IRQ_NEC                 IRQ_IXP4XX_GPIO3
+#define IRQ_MPCI                IRQ_IXP4XX_GPIO12
+/* GPIO lines */
+#define GPIO_SCL                0
+#define GPIO_SDA                1
+#define GPIO_STR                2
+#define GPIO_HSS0_DCD_N         6
+#define GPIO_HSS1_DCD_N         7
+#define GPIO_HSS0_CTS_N         10
+#define GPIO_HSS1_CTS_N         11
+#define GPIO_HSS1_RTS_N         13
+#define GPIO_HSS0_RTS_N         14
+/* Control outputs from 74HC4094 */
+#define CONTROL_HSS0_CLK_INT    0
+#define CONTROL_HSS1_CLK_INT    1
+#define CONTROL_HSS0_DTR_N      2
+#define CONTROL_HSS1_DTR_N      3
+#define CONTROL_EXT             4
+#define CONTROL_AUTO_RESET      5
+#define CONTROL_PCI_RESET_N     6
+#define CONTROL_EEPROM_WC_N     7
+/* offsets from start of flash ROM = 0x50000000 */
+#define CFG_ETH0_ADDRESS        0x40 /* 6 bytes */
+#define CFG_ETH1_ADDRESS        0x46 /* 6 bytes */
+#define CFG_REV                 0x4C /* u32 */
+#define CFG_SDRAM_SIZE          0x50 /* u32 */
+#define CFG_SDRAM_CONF          0x54 /* u32 */
+#define CFG_SDRAM_MODE          0x58 /* u32 */
+#define CFG_SDRAM_REFRESH       0x5C /* u32 */
+#define CFG_HW_BITS             0x60 /* u32 */
+#define  CFG_HW_USB_PORTS       0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
+#define  CFG_HW_HAS_PCI_SLOT    0x00000008
+#define  CFG_HW_HAS_ETH0        0x00000010
+#define  CFG_HW_HAS_ETH1        0x00000020
+#define  CFG_HW_HAS_HSS0        0x00000040
+#define  CFG_HW_HAS_HSS1        0x00000080
+#define  CFG_HW_HAS_UART0       0x00000100
+#define  CFG_HW_HAS_UART1       0x00000200
+#define  CFG_HW_HAS_EEPROM      0x00000400
+#define FLASH_CMD_READ_ARRAY    0xFF
+#define FLASH_CMD_READ_ID       0x90
+#define FLASH_SER_OFF           0x102 /* 0x81 in 16-bit mode */
+static u32 hw_bits = 0xFFFFFFFD;    /* assume all hardware present */;
+static u8 control_value;
+static void set_scl(u8 value)
+{
+        gpio_line_set(GPIO_SCL, !!value);
+        udelay(3);
+}
+static void set_sda(u8 value)
+{
+        gpio_line_set(GPIO_SDA, !!value);
+        udelay(3);
+}
+static void set_str(u8 value)
+{
+        gpio_line_set(GPIO_STR, !!value);
+        udelay(3);
+}
+static inline void set_control(int line, int value)
+{
+        if (value)
+                control_value |=  (1 << line);
+        else
+                control_value &= ~(1 << line);
+}
+static void output_control(void)
+{
+        int i;
+        gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
+        gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
+        for (i = 0; i < 8; i++) {
+                set_scl(0);
+                set_sda(control_value & (0x80 >> i)); /* MSB first */
+                set_scl(1);     /* active edge */
+        }
+        set_str(1);
+        set_str(0);
+        set_scl(0);
+        set_sda(1);             /* Be ready for START */
+        set_scl(1);
+}
+static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
+static int hss_set_clock(int port, unsigned int clock_type)
+{
+        int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
+        switch (clock_type) {
+        case CLOCK_DEFAULT:
+        case CLOCK_EXT:
+                set_control(ctrl_int, 0);
+                output_control();
+                return CLOCK_EXT;
+        case CLOCK_INT:
+                set_control(ctrl_int, 1);
+                output_control();
+                return CLOCK_INT;
+        default:
+                return -EINVAL;
+        }
+}
+static irqreturn_t hss_dcd_irq(int irq, void *pdev)
+{
+        int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N));
+        gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
+        set_carrier_cb_tab[port](pdev, !i);
+        return IRQ_HANDLED;
+}
+static int hss_open(int port, void *pdev,
+                    void (*set_carrier_cb)(void *pdev, int carrier))
+{
+        int i, irq;
+        if (!port)
+                irq = gpio_irq(GPIO_HSS0_DCD_N);
+        else
+                irq = gpio_irq(GPIO_HSS1_DCD_N);
+        gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
+        set_carrier_cb(pdev, !i);
+        set_carrier_cb_tab[!!port] = set_carrier_cb;
+        if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
+                printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
+                       irq, i);
+                return i;
+        }
+        set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
+        output_control();
+        gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
+        return 0;
+}
+static void hss_close(int port, void *pdev)
+{
+        free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N),
+                 pdev);
+        set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
+        set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
+        output_control();
+        gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
+}
+/* Flash memory */
+static struct flash_platform_data flash_data = {
+        .map_name       = "cfi_probe",
+        .width          = 2,
+};
+static struct resource flash_resource = {
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device device_flash = {
+        .name           = "IXP4XX-Flash",
+        .id             = 0,
+        .dev            = { .platform_data = &flash_data },
+        .num_resources  = 1,
+        .resource       = &flash_resource,
+};
+/* I^2C interface */
+static struct i2c_gpio_platform_data i2c_data = {
+        .sda_pin        = GPIO_SDA,
+        .scl_pin        = GPIO_SCL,
+};
+static struct platform_device device_i2c = {
+        .name           = "i2c-gpio",
+        .id             = 0,
+        .dev            = { .platform_data = &i2c_data },
+};
+/* IXP425 2 UART ports */
+static struct resource uart_resources[] = {
+        {
+                .start          = IXP4XX_UART1_BASE_PHYS,
+                .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IXP4XX_UART2_BASE_PHYS,
+                .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+static struct plat_serial8250_port uart_data[] = {
+        {
+                .mapbase        = IXP4XX_UART1_BASE_PHYS,
+                .membase        = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
+                        REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        {
+                .mapbase        = IXP4XX_UART2_BASE_PHYS,
+                .membase        = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
+                        REG_OFFSET,
+                .irq            = IRQ_IXP4XX_UART2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = IXP4XX_UART_XTAL,
+        },
+        { },
+};
+static struct platform_device device_uarts = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev.platform_data      = uart_data,
+        .num_resources          = 2,
+        .resource               = uart_resources,
+};
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info eth_plat[] = {
+        {
+                .phy            = 0,
+                .rxq            = 3,
+                .txreadyq       = 32,
+        }, {
+                .phy            = 1,
+                .rxq            = 4,
+                .txreadyq       = 33,
+        }
+};
+static struct platform_device device_eth_tab[] = {
+        {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEB,
+                .dev.platform_data      = eth_plat,
+        }, {
+                .name                   = "ixp4xx_eth",
+                .id                     = IXP4XX_ETH_NPEC,
+                .dev.platform_data      = eth_plat + 1,
+        }
+};
+/* IXP425 2 synchronous serial ports */
+static struct hss_plat_info hss_plat[] = {
+        {
+                .set_clock      = hss_set_clock,
+                .open           = hss_open,
+                .close          = hss_close,
+                .txreadyq       = 34,
+        }, {
+                .set_clock      = hss_set_clock,
+                .open           = hss_open,
+                .close          = hss_close,
+                .txreadyq       = 35,
+        }
+};
+static struct platform_device device_hss_tab[] = {
+        {
+                .name                   = "ixp4xx_hss",
+                .id                     = 0,
+                .dev.platform_data      = hss_plat,
+        }, {
+                .name                   = "ixp4xx_hss",
+                .id                     = 1,
+                .dev.platform_data      = hss_plat + 1,
+        }
+};
+static struct platform_device *device_tab[6] __initdata = {
+        &device_flash,          /* index 0 */
+};
+static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
+{
+#ifdef __ARMEB__
+        return __raw_readb(flash + addr);
+#else
+        return __raw_readb(flash + (addr ^ 3));
+#endif
+}
+static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
+{
+#ifdef __ARMEB__
+        return __raw_readw(flash + addr);
+#else
+        return __raw_readw(flash + (addr ^ 2));
+#endif
+}
+static void __init gmlr_init(void)
+{
+        u8 __iomem *flash;
+        int i, devices = 1; /* flash */
+        ixp4xx_sys_init();
+        if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
+                printk(KERN_ERR "goramo-mlr: unable to access system"
+                       " configuration data\n");
+        else {
+                system_rev = __raw_readl(flash + CFG_REV);
+                hw_bits = __raw_readl(flash + CFG_HW_BITS);
+                for (i = 0; i < ETH_ALEN; i++) {
+                        eth_plat[0].hwaddr[i] =
+                                flash_readb(flash, CFG_ETH0_ADDRESS + i);
+                        eth_plat[1].hwaddr[i] =
+                                flash_readb(flash, CFG_ETH1_ADDRESS + i);
+                }
+                __raw_writew(FLASH_CMD_READ_ID, flash);
+                system_serial_high = flash_readw(flash, FLASH_SER_OFF);
+                system_serial_high <<= 16;
+                system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
+                system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
+                system_serial_low <<= 16;
+                system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
+                __raw_writew(FLASH_CMD_READ_ARRAY, flash);
+                iounmap(flash);
+        }
+        switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
+        case CFG_HW_HAS_UART0:
+                memset(&uart_data[1], 0, sizeof(uart_data[1]));
+                device_uarts.num_resources = 1;
+                break;
+        case CFG_HW_HAS_UART1:
+                device_uarts.dev.platform_data = &uart_data[1];
+                device_uarts.resource = &uart_resources[1];
+                device_uarts.num_resources = 1;
+                break;
+        }
+        if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
+                device_tab[devices++] = &device_uarts; /* max index 1 */
+        if (hw_bits & CFG_HW_HAS_ETH0)
+                device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
+        if (hw_bits & CFG_HW_HAS_ETH1)
+                device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
+        if (hw_bits & CFG_HW_HAS_HSS0)
+                device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
+        if (hw_bits & CFG_HW_HAS_HSS1)
+                device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
+        if (hw_bits & CFG_HW_HAS_EEPROM)
+                device_tab[devices++] = &device_i2c; /* max index 6 */
+        gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
+        gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
+        gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT);
+        gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT);
+        gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
+        gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
+        gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
+        set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
+        set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
+        set_control(CONTROL_HSS0_DTR_N, 1);
+        set_control(CONTROL_HSS1_DTR_N, 1);
+        set_control(CONTROL_EEPROM_WC_N, 1);
+        set_control(CONTROL_PCI_RESET_N, 1);
+        output_control();
+        msleep(1);            /* Wait for PCI devices to initialize */
+        flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
+        flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+        platform_add_devices(device_tab, devices);
+}
+#ifdef CONFIG_PCI
+static void __init gmlr_pci_preinit(void)
+{
+        set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW);
+        set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW);
+        ixp4xx_pci_preinit();
+}
+static void __init gmlr_pci_postinit(void)
+{
+        if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
+            (hw_bits & CFG_HW_USB_PORTS) < 5) {
+                /* need to adjust number of USB ports on NEC chip */
+                u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
+                if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
+                        value &= ~7;
+                        value |= (hw_bits & CFG_HW_USB_PORTS);
+                        ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
+                }
+        }
+}
+static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        switch(slot) {
+        case SLOT_ETHA: return IRQ_ETHA;
+        case SLOT_ETHB: return IRQ_ETHB;
+        case SLOT_NEC:  return IRQ_NEC;
+        default:        return IRQ_MPCI;
+        }
+}
+static struct hw_pci gmlr_hw_pci __initdata = {
+        .nr_controllers = 1,
+        .preinit        = gmlr_pci_preinit,
+        .postinit       = gmlr_pci_postinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = ixp4xx_setup,
+        .scan           = ixp4xx_scan_bus,
+        .map_irq        = gmlr_map_irq,
+};
+static int __init gmlr_pci_init(void)
+{
+        if (machine_is_goramo_mlr() &&
+            (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
+                pci_common_init(&gmlr_hw_pci);
+        return 0;
+}
+subsys_initcall(gmlr_pci_init);
+#endif /* CONFIG_PCI */
+MACHINE_START(GORAMO_MLR, "MultiLink")
+        /* Maintainer: Krzysztof Halasa */
+        .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
+        .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+        .map_io         = ixp4xx_map_io,
+        .init_irq       = ixp4xx_init_irq,
+        .timer          = &ixp4xx_timer,
+        .boot_params    = 0x0100,
+        .init_machine   = gmlr_init,
+MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index def7773be67c..b2ef65db0e91 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -26,6 +26,8 @@
 #define IXP46X_PROCESSOR_ID_VALUE       0x69054200 /* including IXP455 */
 #define IXP46X_PROCESSOR_ID_MASK        0xfffffff0
+#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
+                                IXP42X_PROCESSOR_ID_VALUE)
 #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
                         IXP42X_PROCESSOR_ID_VALUE)
 #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
@@ -35,8 +37,11 @@
 static inline u32 ixp4xx_read_feature_bits(void)
 {
-        unsigned int val = ~*IXP4XX_EXP_CFG2;
+        u32 val = ~*IXP4XX_EXP_CFG2;
+        if (cpu_is_ixp42x_rev_a0())
+                return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
+                                               IXP4XX_FEATURE_AES);
        if (cpu_is_ixp42x())
                return val & IXP42X_FEATURE_MASK;
        if (cpu_is_ixp43x())
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
index 0cbe6ceb67c5..9e7cad2d54cb 100644
--- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h
+++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
@@ -15,7 +15,7 @@
 #define DEBUG_QMGR      0
 #define HALF_QUEUES     32
-#define QUEUES          64      /* only 32 lower queues currently supported */
+#define QUEUES          64
 #define MAX_QUEUE_LENGTH 4      /* in dwords */
 #define QUEUE_STAT1_EMPTY               1 /* queue status bits */
@@ -110,48 +110,95 @@ static inline u32 qmgr_get_entry(unsigned int queue)
        return val;
 }
-static inline int qmgr_get_stat1(unsigned int queue)
+static inline int __qmgr_get_stat1(unsigned int queue)
 {
        extern struct qmgr_regs __iomem *qmgr_regs;
        return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
                >> ((queue & 7) << 2)) & 0xF;
 }
-static inline int qmgr_get_stat2(unsigned int queue)
+static inline int __qmgr_get_stat2(unsigned int queue)
 {
        extern struct qmgr_regs __iomem *qmgr_regs;
+        BUG_ON(queue >= HALF_QUEUES);
        return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
                >> ((queue & 0xF) << 1)) & 0x3;
 }
+/**
+ * qmgr_stat_empty() - checks if a hardware queue is empty
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue is empty.
+ */
 static inline int qmgr_stat_empty(unsigned int queue)
 {
-        return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
+        BUG_ON(queue >= HALF_QUEUES);
+        return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
 }
-static inline int qmgr_stat_nearly_empty(unsigned int queue)
+/**
+ * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue is below low watermark.
+ */
+static inline int qmgr_stat_below_low_watermark(unsigned int queue)
 {
-        return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
+        extern struct qmgr_regs __iomem *qmgr_regs;
+        if (queue >= HALF_QUEUES)
+                return (__raw_readl(&qmgr_regs->statne_h) >>
+                        (queue - HALF_QUEUES)) & 0x01;
+        return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
 }
-static inline int qmgr_stat_nearly_full(unsigned int queue)
+/**
+ * qmgr_stat_above_high_watermark() - checks if a queue is above high watermark
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue is above high watermark
+ */
+static inline int qmgr_stat_above_high_watermark(unsigned int queue)
 {
-        return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
+        BUG_ON(queue >= HALF_QUEUES);
+        return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL;
 }
+/**
+ * qmgr_stat_full() - checks if a hardware queue is full
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue is full.
+ */
 static inline int qmgr_stat_full(unsigned int queue)
 {
-        return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
+        extern struct qmgr_regs __iomem *qmgr_regs;
+        if (queue >= HALF_QUEUES)
+                return (__raw_readl(&qmgr_regs->statf_h) >>
+                        (queue - HALF_QUEUES)) & 0x01;
+        return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
 }
+/**
+ * qmgr_stat_underflow() - checks if a hardware queue experienced underflow
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue experienced underflow.
+ */
 static inline int qmgr_stat_underflow(unsigned int queue)
 {
-        return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
+        return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW;
 }
+/**
+ * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue experienced overflow.
+ */
 static inline int qmgr_stat_overflow(unsigned int queue)
 {
-        return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
+        return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
 }
 #endif
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index 7bb8e778e4b6..47ac69c7ec78 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -386,15 +386,6 @@ static int npe_reset(struct npe *npe)
        /* reset the NPE */
        ixp4xx_write_feature_bits(val &
                                  ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
-        for (i = 0; i < MAX_RETRIES; i++) {
-                if (!(ixp4xx_read_feature_bits() &
-                      (IXP4XX_FEATURE_RESET_NPEA << npe->id)))
-                        break;  /* reset completed */
-                udelay(1);
-        }
-        if (i == MAX_RETRIES)
-                return -ETIMEDOUT;
        /* deassert reset */
        ixp4xx_write_feature_bits(val |
                                  (IXP4XX_FEATURE_RESET_NPEA << npe->id));
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index bfddc73d0a20..bfdbe4b5a3cc 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -18,8 +18,8 @@ struct qmgr_regs __iomem *qmgr_regs;
 static struct resource *mem_res;
 static spinlock_t qmgr_lock;
 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
-static void (*irq_handlers[HALF_QUEUES])(void *pdev);
+static void (*irq_handlers[QUEUES])(void *pdev);
-static void *irq_pdevs[HALF_QUEUES];
+static void *irq_pdevs[QUEUES];
 #if DEBUG_QMGR
 char qmgr_queue_descs[QUEUES][32];
@@ -28,51 +28,112 @@ char qmgr_queue_descs[QUEUES][32];
 void qmgr_set_irq(unsigned int queue, int src,
                  void (*handler)(void *pdev), void *pdev)
 {
-        u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
-        int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
        unsigned long flags;
-        src &= 7;
        spin_lock_irqsave(&qmgr_lock, flags);
-        __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
+        if (queue < HALF_QUEUES) {
+                u32 __iomem *reg;
+                int bit;
+                BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL);
+                reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
+                bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
+                __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),
+                             reg);
+        } else
+                /* IRQ source for queues 32-63 is fixed */
+                BUG_ON(src != QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY);
        irq_handlers[queue] = handler;
        irq_pdevs[queue] = pdev;
        spin_unlock_irqrestore(&qmgr_lock, flags);
 }
-static irqreturn_t qmgr_irq1(int irq, void *pdev)
+static irqreturn_t qmgr_irq1_a0(int irq, void *pdev)
 {
-        int i;
+        int i, ret = 0;
-        u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
+        u32 en_bitmap, src, stat;
-        __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
+        /* ACK - it may clear any bits so don't rely on it */
-        for (i = 0; i < HALF_QUEUES; i++)
+        __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
-                if (val & (1 << i))
+        en_bitmap = qmgr_regs->irqen[0];
+        while (en_bitmap) {
+                i = __fls(en_bitmap); /* number of the last "low" queue */
+                en_bitmap &= ~BIT(i);
+                src = qmgr_regs->irqsrc[i >> 3];
+                stat = qmgr_regs->stat1[i >> 3];
+                if (src & 4) /* the IRQ condition is inverted */
+                        stat = ~stat;
+                if (stat & BIT(src & 3)) {
                        irq_handlers[i](irq_pdevs[i]);
+                        ret = IRQ_HANDLED;
+                }
+        }
+        return ret;
+}
+static irqreturn_t qmgr_irq2_a0(int irq, void *pdev)
+{
+        int i, ret = 0;
+        u32 req_bitmap;
+        /* ACK - it may clear any bits so don't rely on it */
+        __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);
+        req_bitmap = qmgr_regs->irqen[1] & qmgr_regs->statne_h;
+        while (req_bitmap) {
+                i = __fls(req_bitmap); /* number of the last "high" queue */
+                req_bitmap &= ~BIT(i);
+                irq_handlers[HALF_QUEUES + i](irq_pdevs[HALF_QUEUES + i]);
+                ret = IRQ_HANDLED;
+        }
+        return ret;
+}
-        return val ? IRQ_HANDLED : 0;
+static irqreturn_t qmgr_irq(int irq, void *pdev)
+{
+        int i, half = (irq == IRQ_IXP4XX_QM1 ? 0 : 1);
+        u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
+        if (!req_bitmap)
+                return 0;
+        __raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */
+        while (req_bitmap) {
+                i = __fls(req_bitmap); /* number of the last queue */
+                req_bitmap &= ~BIT(i);
+                i += half * HALF_QUEUES;
+                irq_handlers[i](irq_pdevs[i]);
+        }
+        return IRQ_HANDLED;
 }
 void qmgr_enable_irq(unsigned int queue)
 {
        unsigned long flags;
+        int half = queue / 32;
+        u32 mask = 1 << (queue & (HALF_QUEUES - 1));
        spin_lock_irqsave(&qmgr_lock, flags);
-        __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
+        __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,
-                     &qmgr_regs->irqen[0]);
+                     &qmgr_regs->irqen[half]);
        spin_unlock_irqrestore(&qmgr_lock, flags);
 }
 void qmgr_disable_irq(unsigned int queue)
 {
        unsigned long flags;
+        int half = queue / 32;
+        u32 mask = 1 << (queue & (HALF_QUEUES - 1));
        spin_lock_irqsave(&qmgr_lock, flags);
-        __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
+        __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,
-                     &qmgr_regs->irqen[0]);
+                     &qmgr_regs->irqen[half]);
-        __raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */
+        __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */
        spin_unlock_irqrestore(&qmgr_lock, flags);
 }
@@ -98,8 +159,7 @@ int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
        u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
        int err;
-        if (queue >= HALF_QUEUES)
+        BUG_ON(queue >= QUEUES);
-                return -ERANGE;
        if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
                return -EINVAL;
@@ -180,7 +240,7 @@ void qmgr_release_queue(unsigned int queue)
 {
        u32 cfg, addr, mask[4];
-        BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
+        BUG_ON(queue >= QUEUES); /* not in valid range */
        spin_lock_irq(&qmgr_lock);
        cfg = __raw_readl(&qmgr_regs->sram[queue]);
@@ -224,6 +284,8 @@ void qmgr_release_queue(unsigned int queue)
 static int qmgr_init(void)
 {
        int i, err;
+        irq_handler_t handler1, handler2;
        mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
                                     IXP4XX_QMGR_REGION_SIZE,
                                     "IXP4xx Queue Manager");
@@ -247,23 +309,42 @@ static int qmgr_init(void)
                __raw_writel(0, &qmgr_regs->irqen[i]);
        }
+        __raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);
+        __raw_writel(0, &qmgr_regs->statf_h);
        for (i = 0; i < QUEUES; i++)
                __raw_writel(0, &qmgr_regs->sram[i]);
-        err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
+        if (cpu_is_ixp42x_rev_a0()) {
-                          "IXP4xx Queue Manager", NULL);
+                handler1 = qmgr_irq1_a0;
+                handler2 = qmgr_irq2_a0;
+        } else
+                handler1 = handler2 = qmgr_irq;
+        err = request_irq(IRQ_IXP4XX_QM1, handler1, 0, "IXP4xx Queue Manager",
+                          NULL);
        if (err) {
-                printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
+                printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n",
-                       IRQ_IXP4XX_QM1);
+                       IRQ_IXP4XX_QM1, err);
                goto error_irq;
        }
+        err = request_irq(IRQ_IXP4XX_QM2, handler2, 0, "IXP4xx Queue Manager",
+                          NULL);
+        if (err) {
+                printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n",
+                       IRQ_IXP4XX_QM2, err);
+                goto error_irq2;
+        }
        used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
        spin_lock_init(&qmgr_lock);
        printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
        return 0;
+error_irq2:
+        free_irq(IRQ_IXP4XX_QM1, NULL);
 error_irq:
        iounmap(qmgr_regs);
 error_map:
@@ -274,7 +355,9 @@ error_map:
 static void qmgr_remove(void)
 {
        free_irq(IRQ_IXP4XX_QM1, NULL);
+        free_irq(IRQ_IXP4XX_QM2, NULL);
        synchronize_irq(IRQ_IXP4XX_QM1);
+        synchronize_irq(IRQ_IXP4XX_QM2);
        iounmap(qmgr_regs);
        release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
 }
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index b5421cccd7e1..25100f7acf4c 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -20,6 +20,12 @@ config MACH_RD88F6281
          Say 'Y' here if you want your kernel to support the
          Marvell RD-88F6281 Reference Board.
+config MACH_MV88F6281GTW_GE
+        bool "Marvell 88F6281 GTW GE Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell 88F6281 GTW GE Board.
 config MACH_SHEEVAPLUG
        bool "Marvell SheevaPlug Reference Board"
        help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 8f03c9b9bdd9..9dd680e964d6 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -3,5 +3,8 @@ obj-y				+= common.o addr-map.o irq.o pcie.o mpp.o
 obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
 obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
 obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
+obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o
+obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 5db4f0bbe5ee..1da5d1c18ecb 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -20,6 +20,7 @@
 */
 #define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
+#define TARGET_SRAM             3
 #define TARGET_PCIE             4
 #define ATTR_DEV_SPI_ROM        0x1e
 #define ATTR_DEV_BOOT           0x1d
@@ -30,6 +31,7 @@
 #define ATTR_DEV_CS0            0x3e
 #define ATTR_PCIE_IO            0xe0
 #define ATTR_PCIE_MEM           0xe8
+#define ATTR_SRAM               0x01
 /*
 * Helpers to get DDR bank info
@@ -48,7 +50,6 @@
 struct mbus_dram_target_info kirkwood_mbus_dram_info;
-static int __initdata win_alloc_count;
 static int __init cpu_win_can_remap(int win)
 {
@@ -112,7 +113,11 @@ void __init kirkwood_setup_cpu_mbus(void)
        setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
                      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
-        win_alloc_count = 3;
+        /*
+         * Setup window for SRAM.
+         */
+        setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+                      TARGET_SRAM, ATTR_SRAM, -1);
        /*
         * Setup MBUS dram target info.
@@ -140,8 +145,3 @@ void __init kirkwood_setup_cpu_mbus(void)
        }
        kirkwood_mbus_dram_info.num_cs = cs;
 }
-void __init kirkwood_setup_sram_win(u32 base, u32 size)
-{
-        setup_cpu_win(win_alloc_count++, base, size, 0x03, 0x00, -1);
-}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index be1ca28fed3f..0f6919838011 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -16,6 +16,7 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/mtd/nand.h>
 #include <linux/spi/orion_spi.h>
 #include <net/dsa.h>
 #include <asm/page.h>
@@ -29,6 +30,7 @@
 #include <plat/mvsdio.h>
 #include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
+#include <plat/orion_wdt.h>
 #include <plat/time.h>
 #include "common.h"
@@ -54,6 +56,13 @@ void __init kirkwood_map_io(void)
        iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
 }
+/*
+ * Default clock control bits.  Any bit _not_ set in this variable
+ * will be cleared from the hardware after platform devices have been
+ * registered.  Some reserved bits must be set to 1.
+ */
+unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
+        
 /*****************************************************************************
 * EHCI
@@ -95,6 +104,7 @@ static struct platform_device kirkwood_ehci = {
 void __init kirkwood_ehci_init(void)
 {
+        kirkwood_clk_ctrl |= CGC_USB0;
        platform_device_register(&kirkwood_ehci);
 }
@@ -151,6 +161,7 @@ static struct platform_device kirkwood_ge00 = {
 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
+        kirkwood_clk_ctrl |= CGC_GE0;
        eth_data->shared = &kirkwood_ge00_shared;
        kirkwood_ge00.dev.platform_data = eth_data;
@@ -212,6 +223,7 @@ static struct platform_device kirkwood_ge01 = {
 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
+        kirkwood_clk_ctrl |= CGC_GE1;
        eth_data->shared = &kirkwood_ge01_shared;
        kirkwood_ge01.dev.platform_data = eth_data;
@@ -258,6 +270,43 @@ void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
 /*****************************************************************************
+ * NAND flash
+ ****************************************************************************/
+static struct resource kirkwood_nand_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
+        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
+                                KIRKWOOD_NAND_MEM_SIZE - 1,
+};
+static struct orion_nand_data kirkwood_nand_data = {
+        .cle            = 0,
+        .ale            = 1,
+        .width          = 8,
+};
+static struct platform_device kirkwood_nand_flash = {
+        .name           = "orion_nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &kirkwood_nand_data,
+        },
+        .resource       = &kirkwood_nand_resource,
+        .num_resources  = 1,
+};
+void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
+                               int chip_delay)
+{
+        kirkwood_clk_ctrl |= CGC_RUNIT;
+        kirkwood_nand_data.parts = parts;
+        kirkwood_nand_data.nr_parts = nr_parts;
+        kirkwood_nand_data.chip_delay = chip_delay;
+        platform_device_register(&kirkwood_nand_flash);
+}
+/*****************************************************************************
 * SoC RTC
 ****************************************************************************/
 static struct resource kirkwood_rtc_resource = {
@@ -301,6 +350,9 @@ static struct platform_device kirkwood_sata = {
 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 {
+        kirkwood_clk_ctrl |= CGC_SATA0;
+        if (sata_data->n_ports > 1)
+                kirkwood_clk_ctrl |= CGC_SATA1;
        sata_data->dram = &kirkwood_mbus_dram_info;
        kirkwood_sata.dev.platform_data = sata_data;
        platform_device_register(&kirkwood_sata);
@@ -346,6 +398,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
        else
                mvsdio_data->clock = 200000000;
        mvsdio_data->dram = &kirkwood_mbus_dram_info;
+        kirkwood_clk_ctrl |= CGC_SDIO;
        kirkwood_sdio.dev.platform_data = mvsdio_data;
        platform_device_register(&kirkwood_sdio);
 }
@@ -377,6 +430,7 @@ static struct platform_device kirkwood_spi = {
 void __init kirkwood_spi_init()
 {
+        kirkwood_clk_ctrl |= CGC_RUNIT;
        platform_device_register(&kirkwood_spi);
 }
@@ -507,6 +561,43 @@ void __init kirkwood_uart1_init(void)
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+static struct resource kirkwood_crypto_res[] = {
+        {
+                .name   = "regs",
+                .start  = CRYPTO_PHYS_BASE,
+                .end    = CRYPTO_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sram",
+                .start  = KIRKWOOD_SRAM_PHYS_BASE,
+                .end    = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "crypto interrupt",
+                .start  = IRQ_KIRKWOOD_CRYPTO,
+                .end    = IRQ_KIRKWOOD_CRYPTO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device kirkwood_crypto_device = {
+        .name           = "mv_crypto",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_crypto_res),
+        .resource       = kirkwood_crypto_res,
+};
+void __init kirkwood_crypto_init(void)
+{
+        kirkwood_clk_ctrl |= CGC_CRYPTO;
+        platform_device_register(&kirkwood_crypto_device);
+}
+/*****************************************************************************
 * XOR
 ****************************************************************************/
 static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
@@ -597,6 +688,7 @@ static struct platform_device kirkwood_xor01_channel = {
 static void __init kirkwood_xor0_init(void)
 {
+        kirkwood_clk_ctrl |= CGC_XOR0;
        platform_device_register(&kirkwood_xor0_shared);
        /*
@@ -695,6 +787,7 @@ static struct platform_device kirkwood_xor11_channel = {
 static void __init kirkwood_xor1_init(void)
 {
+        kirkwood_clk_ctrl |= CGC_XOR1;
        platform_device_register(&kirkwood_xor1_shared);
        /*
@@ -713,6 +806,29 @@ static void __init kirkwood_xor1_init(void)
 /*****************************************************************************
+ * Watchdog
+ ****************************************************************************/
+static struct orion_wdt_platform_data kirkwood_wdt_data = {
+        .tclk           = 0,
+};
+static struct platform_device kirkwood_wdt_device = {
+        .name           = "orion_wdt",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &kirkwood_wdt_data,
+        },
+        .num_resources  = 0,
+};
+static void __init kirkwood_wdt_init(void)
+{
+        kirkwood_wdt_data.tclk = kirkwood_tclk;
+        platform_device_register(&kirkwood_wdt_device);
+}
+/*****************************************************************************
 * Time handling
 ****************************************************************************/
 int kirkwood_tclk;
@@ -804,6 +920,49 @@ void __init kirkwood_init(void)
        /* internal devices that every board has */
        kirkwood_rtc_init();
+        kirkwood_wdt_init();
        kirkwood_xor0_init();
        kirkwood_xor1_init();
+        kirkwood_crypto_init();
+}
+static int __init kirkwood_clock_gate(void)
+{
+        unsigned int curr = readl(CLOCK_GATING_CTRL);
+        printk(KERN_DEBUG "Gating clock of unused units\n");
+        printk(KERN_DEBUG "before: 0x%08x\n", curr);
+        /* Make sure those units are accessible */
+        writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
+        /* For SATA: first shutdown the phy */
+        if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
+                /* Disable PLL and IVREF */
+                writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
+                /* Disable PHY */
+                writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
+        }
+        if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
+                /* Disable PLL and IVREF */
+                writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
+                /* Disable PHY */
+                writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
+        }
+        
+        /* For PCIe: first shutdown the phy */
+        if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
+                writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
+                while (1)
+                        if (readl(PCIE_STATUS) & 0x1)
+                                break;
+                writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
+        }
+        /* Now gate clock the required units */
+        writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
+        printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
+        return 0;
 }
+late_initcall(kirkwood_clock_gate);
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 6ee88406f381..d7de43464358 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -15,6 +15,7 @@ struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 struct mvsdio_platform_data;
+struct mtd_partition;
 /*
 * Basic Kirkwood init functions used early by machine-setup.
@@ -25,7 +26,6 @@ void kirkwood_init_irq(void);
 extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
 void kirkwood_setup_cpu_mbus(void);
-void kirkwood_setup_sram_win(u32 base, u32 size);
 void kirkwood_pcie_id(u32 *dev, u32 *rev);
@@ -40,9 +40,11 @@ void kirkwood_spi_init(void);
 void kirkwood_i2c_init(void);
 void kirkwood_uart0_init(void);
 void kirkwood_uart1_init(void);
+void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 #endif
diff --git a/arch/arm/mach-kirkwood/cpuidle.c b/arch/arm/mach-kirkwood/cpuidle.c
new file mode 100644
index 000000000000..f68d33f1f396
--- /dev/null
+++ b/arch/arm/mach-kirkwood/cpuidle.c
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-kirkwood/cpuidle.c
+ *
+ * CPU idle Marvell Kirkwood SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The cpu idle uses wait-for-interrupt and DDR self refresh in order
+ * to implement two idle states -
+ * #1 wait-for-interrupt
+ * #2 wait-for-interrupt and DDR self refresh
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+#include <asm/proc-fns.h>
+#include <mach/kirkwood.h>
+#define KIRKWOOD_MAX_STATES     2
+static struct cpuidle_driver kirkwood_idle_driver = {
+        .name =         "kirkwood_idle",
+        .owner =        THIS_MODULE,
+};
+static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
+/* Actual code that puts the SoC in different idle states */
+static int kirkwood_enter_idle(struct cpuidle_device *dev,
+                               struct cpuidle_state *state)
+{
+        struct timeval before, after;
+        int idle_time;
+        local_irq_disable();
+        do_gettimeofday(&before);
+        if (state == &dev->states[0])
+                /* Wait for interrupt state */
+                cpu_do_idle();
+        else if (state == &dev->states[1]) {
+                /*
+                 * Following write will put DDR in self refresh.
+                 * Note that we have 256 cycles before DDR puts it
+                 * self in self-refresh, so the wait-for-interrupt
+                 * call afterwards won't get the DDR from self refresh
+                 * mode.
+                 */
+                writel(0x7, DDR_OPERATION_BASE);
+                cpu_do_idle();
+        }
+        do_gettimeofday(&after);
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                        (after.tv_usec - before.tv_usec);
+        return idle_time;
+}
+/* Initialize CPU idle by registering the idle states */
+static int kirkwood_init_cpuidle(void)
+{
+        struct cpuidle_device *device;
+        cpuidle_register_driver(&kirkwood_idle_driver);
+        device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id());
+        device->state_count = KIRKWOOD_MAX_STATES;
+        /* Wait for interrupt state */
+        device->states[0].enter = kirkwood_enter_idle;
+        device->states[0].exit_latency = 1;
+        device->states[0].target_residency = 10000;
+        device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
+        strcpy(device->states[0].name, "WFI");
+        strcpy(device->states[0].desc, "Wait for interrupt");
+        /* Wait for interrupt and DDR self refresh state */
+        device->states[1].enter = kirkwood_enter_idle;
+        device->states[1].exit_latency = 10;
+        device->states[1].target_residency = 10000;
+        device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
+        strcpy(device->states[1].name, "DDR SR");
+        strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
+        if (cpuidle_register_device(device)) {
+                printk(KERN_ERR "kirkwood_init_cpuidle: Failed registering\n");
+                return -EIO;
+        }
+        return 0;
+}
+device_initcall(kirkwood_init_cpuidle);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 5505d5837752..39bdf4bcace9 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -11,14 +11,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
-#include <plat/orion_nand.h>
 #include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
@@ -39,32 +37,6 @@ static struct mtd_partition db88f6281_nand_parts[] = {
        },
 };
-static struct resource db88f6281_nand_resource = {
-        .flags          = IORESOURCE_MEM,
-        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
-        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
-                          KIRKWOOD_NAND_MEM_SIZE - 1,
-};
-static struct orion_nand_data db88f6281_nand_data = {
-        .parts          = db88f6281_nand_parts,
-        .nr_parts       = ARRAY_SIZE(db88f6281_nand_parts),
-        .cle            = 0,
-        .ale            = 1,
-        .width          = 8,
-        .chip_delay     = 25,
-};
-static struct platform_device db88f6281_nand_flash = {
-        .name           = "orion_nand",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &db88f6281_nand_data,
-        },
-        .resource       = &db88f6281_nand_resource,
-        .num_resources  = 1,
-};
 static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
@@ -92,13 +64,12 @@ static void __init db88f6281_init(void)
        kirkwood_init();
        kirkwood_mpp_conf(db88f6281_mpp_config);
+        kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25);
        kirkwood_ehci_init();
        kirkwood_ge00_init(&db88f6281_ge00_data);
        kirkwood_sata_init(&db88f6281_sata_data);
        kirkwood_uart0_init();
        kirkwood_sdio_init(&db88f6281_mvsdio_data);
-        
-        platform_device_register(&db88f6281_nand_flash);
 }
 static int __init db88f6281_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 4f7029f521cc..9e80d9232c83 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -17,12 +17,15 @@
 #define CPU_RESET               0x00000002
 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define WDT_RESET_OUT_EN        0x00000002
 #define SOFT_RESET_OUT_EN       0x00000004
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define SOFT_RESET              0x00000001
 #define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
+#define WDT_INT_REQ             0x0008
 #define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
 #define BRIDGE_INT_TIMER0       0x0002
 #define BRIDGE_INT_TIMER1       0x0004
@@ -39,4 +42,22 @@
 #define L2_CONFIG_REG           (BRIDGE_VIRT_BASE | 0x0128)
 #define L2_WRITETHROUGH         0x00000010
+#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE | 0x11c)
+#define CGC_GE0                 (1 << 0)
+#define CGC_PEX0                (1 << 2)
+#define CGC_USB0                (1 << 3)
+#define CGC_SDIO                (1 << 4)
+#define CGC_TSU                 (1 << 5)
+#define CGC_DUNIT               (1 << 6)
+#define CGC_RUNIT               (1 << 7)
+#define CGC_XOR0                (1 << 8)
+#define CGC_AUDIO               (1 << 9)
+#define CGC_SATA0               (1 << 14)
+#define CGC_SATA1               (1 << 15)
+#define CGC_XOR1                (1 << 16)
+#define CGC_CRYPTO              (1 << 17)
+#define CGC_GE1                 (1 << 19)
+#define CGC_TDM                 (1 << 20)
+#define CGC_RESERVED            ((1 << 18) | (0x6 << 21))
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
index be07be0ef522..a643a846d5fb 100644
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -19,6 +19,31 @@ static inline void __iomem *__io(unsigned long addr)
                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
 }
+static inline void __iomem *
+__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
+{
+        void __iomem *retval;
+        unsigned long offs = paddr - KIRKWOOD_REGS_PHYS_BASE;
+        if (mtype == MT_DEVICE && size && offs < KIRKWOOD_REGS_SIZE &&
+            size <= KIRKWOOD_REGS_SIZE && offs + size <= KIRKWOOD_REGS_SIZE) {
+                retval = (void __iomem *)KIRKWOOD_REGS_VIRT_BASE + offs;
+        } else {
+                retval = __arm_ioremap(paddr, size, mtype);
+        }
+        return retval;
+}
+static inline void
+__arch_iounmap(void __iomem *addr)
+{
+        if (addr < (void __iomem *)KIRKWOOD_REGS_VIRT_BASE ||
+            addr >= (void __iomem *)(KIRKWOOD_REGS_VIRT_BASE + KIRKWOOD_REGS_SIZE))
+                __iounmap(addr);
+}
+#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
+#define __arch_iounmap(a)       __arch_iounmap(a)
 #define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index b3e13958821d..07af858814a0 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -20,16 +20,18 @@
 * f1000000     on-chip peripheral registers
 * f2000000     PCIe I/O space
 * f3000000     NAND controller address window
+ * f4000000     Security Accelerator SRAM
 *
 * virt         phys            size
 * fee00000     f1000000        1M      on-chip peripheral registers
 * fef00000     f2000000        1M      PCIe I/O space
 */
+#define KIRKWOOD_SRAM_PHYS_BASE         0xf4000000
+#define KIRKWOOD_SRAM_SIZE              SZ_2K
 #define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
-#define KIRKWOOD_NAND_MEM_SIZE          SZ_64K /* 1K is sufficient, but 64K
+#define KIRKWOOD_NAND_MEM_SIZE          SZ_1K
-                                                * is the minimal window size
-                                                */
 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
 #define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
@@ -48,6 +50,7 @@
 */
 #define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
 #define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
+#define DDR_OPERATION_BASE      (DDR_VIRT_BASE | 0x1418)
 #define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
 #define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
@@ -63,7 +66,11 @@
 #define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
 #define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
+#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE | 0x70)
+#define PCIE_STATUS             (PCIE_VIRT_BASE | 0x1a04)
 #define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
@@ -80,6 +87,11 @@
 #define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
 #define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
+#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
+#define SATA0_IF_CTRL           (SATA_VIRT_BASE | 0x2050)
+#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE | 0x2330)
+#define SATA1_IF_CTRL           (SATA_VIRT_BASE | 0x4050)
+#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE | 0x4330)
 #define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 63c44934391a..a5900f64e38c 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -48,6 +48,9 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
        if (!variant_mask)
                return;
+        /* Initialize gpiolib. */
+        orion_gpio_init();
        printk(KERN_DEBUG "initial MPP regs:");
        for (i = 0; i < MPP_NR_REGS; i++) {
                mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
new file mode 100644
index 000000000000..0358f45766cb
--- /dev/null
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+ *
+ * Marvell 88F6281 GTW GE Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/timer.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <net/dsa.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
+};
+static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = {
+        .port_names[0]  = "lan1",
+        .port_names[1]  = "lan2",
+        .port_names[2]  = "lan3",
+        .port_names[3]  = "lan4",
+        .port_names[4]  = "wan",
+        .port_names[5]  = "cpu",
+};
+static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = {
+        .nr_chips       = 1,
+        .chip           = &mv88f6281gtw_ge_switch_chip_data,
+};
+static const struct flash_platform_data mv88f6281gtw_ge_spi_slave_data = {
+        .type           = "mx25l12805d",
+};
+static struct spi_board_info __initdata mv88f6281gtw_ge_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &mv88f6281gtw_ge_spi_slave_data,
+                .irq            = -1,
+                .max_speed_hz   = 50000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+static struct gpio_keys_button mv88f6281gtw_ge_button_pins[] = {
+        {
+                .code           = KEY_RESTART,
+                .gpio           = 47,
+                .desc           = "SWR Button",
+                .active_low     = 1,
+        }, {
+                .code           = KEY_F1,
+                .gpio           = 46,
+                .desc           = "WPS Button(F1)",
+                .active_low     = 1,
+        },
+};
+static struct gpio_keys_platform_data mv88f6281gtw_ge_button_data = {
+        .buttons        = mv88f6281gtw_ge_button_pins,
+        .nbuttons       = ARRAY_SIZE(mv88f6281gtw_ge_button_pins),
+};
+static struct platform_device mv88f6281gtw_ge_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &mv88f6281gtw_ge_button_data,
+        },
+};
+static struct gpio_led mv88f6281gtw_ge_led_pins[] = {
+        {
+                .name           = "gtw:green:Status",
+                .gpio           = 20,
+                .active_low     = 0,
+        }, {
+                .name           = "gtw:red:Status",
+                .gpio           = 21,
+                .active_low     = 0,
+        }, {
+                .name           = "gtw:green:USB",
+                .gpio           = 12,
+                .active_low     = 0,
+        },
+};
+static struct gpio_led_platform_data mv88f6281gtw_ge_led_data = {
+        .leds           = mv88f6281gtw_ge_led_pins,
+        .num_leds       = ARRAY_SIZE(mv88f6281gtw_ge_led_pins),
+};
+static struct platform_device mv88f6281gtw_ge_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &mv88f6281gtw_ge_led_data,
+        },
+};
+static unsigned int mv88f6281gtw_ge_mpp_config[] __initdata = {
+        MPP12_GPO,      /* Status#_USB pin  */
+        MPP20_GPIO,     /* Status#_GLED pin */
+        MPP21_GPIO,     /* Status#_RLED pin */
+        MPP46_GPIO,     /* WPS_Switch pin   */
+        MPP47_GPIO,     /* SW_Init pin      */
+        0
+};
+static void __init mv88f6281gtw_ge_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(mv88f6281gtw_ge_mpp_config);
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data);
+        kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ);
+        spi_register_board_info(mv88f6281gtw_ge_spi_slave_info,
+                                ARRAY_SIZE(mv88f6281gtw_ge_spi_slave_info));
+        kirkwood_spi_init();
+        kirkwood_uart0_init();
+        platform_device_register(&mv88f6281gtw_ge_leds);
+        platform_device_register(&mv88f6281gtw_ge_buttons);
+}
+static int __init mv88f6281gtw_ge_pci_init(void)
+{
+        if (machine_is_mv88f6281gtw_ge())
+                kirkwood_pcie_init();
+        return 0;
+}
+subsys_initcall(mv88f6281gtw_ge_pci_init);
+MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = mv88f6281gtw_ge_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 73fccacd1a73..d90b9aae308d 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -14,6 +14,7 @@
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <mach/bridge-regs.h>
 #include "common.h"
@@ -95,6 +96,7 @@ static struct pci_ops pcie_ops = {
 static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
 {
        struct resource *res;
+        extern unsigned int kirkwood_clk_ctrl;
        /*
         * Generic PCIe unit setup.
@@ -133,6 +135,8 @@ static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
        sys->resource[2] = NULL;
        sys->io_offset = 0;
+        kirkwood_clk_ctrl |= CGC_PEX0;
        return 1;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 2f0e4ef3db0f..8bf4153d0840 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -11,8 +11,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/spi/flash.h>
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31e996d65fc4..31708ddbc83e 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
-#include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
@@ -22,7 +21,6 @@
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include <plat/mvsdio.h>
-#include <plat/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
@@ -42,32 +40,6 @@ static struct mtd_partition rd88f6281_nand_parts[] = {
        },
 };
-static struct resource rd88f6281_nand_resource = {
-        .flags          = IORESOURCE_MEM,
-        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
-        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
-                          KIRKWOOD_NAND_MEM_SIZE - 1,
-};
-static struct orion_nand_data rd88f6281_nand_data = {
-        .parts          = rd88f6281_nand_parts,
-        .nr_parts       = ARRAY_SIZE(rd88f6281_nand_parts),
-        .cle            = 0,
-        .ale            = 1,
-        .width          = 8,
-        .chip_delay     = 25,
-};
-static struct platform_device rd88f6281_nand_flash = {
-        .name           = "orion_nand",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &rd88f6281_nand_data,
-        },
-        .resource       = &rd88f6281_nand_resource,
-        .num_resources  = 1,
-};
 static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_NONE,
        .speed          = SPEED_1000,
@@ -114,6 +86,7 @@ static void __init rd88f6281_init(void)
        kirkwood_init();
        kirkwood_mpp_conf(rd88f6281_mpp_config);
+        kirkwood_nand_init(ARRAY_AND_SIZE(rd88f6281_nand_parts), 25);
        kirkwood_ehci_init();
        kirkwood_ge00_init(&rd88f6281_ge00_data);
@@ -129,8 +102,6 @@ static void __init rd88f6281_init(void)
        kirkwood_sata_init(&rd88f6281_sata_data);
        kirkwood_sdio_init(&rd88f6281_mvsdio_data);
        kirkwood_uart0_init();
-        platform_device_register(&rd88f6281_nand_flash);
 }
 static int __init rd88f6281_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 831e4a56cae1..c7319eeac8bb 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -11,7 +11,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
@@ -20,7 +19,6 @@
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include <plat/mvsdio.h>
-#include <plat/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
@@ -40,38 +38,12 @@ static struct mtd_partition sheevaplug_nand_parts[] = {
        },
 };
-static struct resource sheevaplug_nand_resource = {
-        .flags          = IORESOURCE_MEM,
-        .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
-        .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
-                          KIRKWOOD_NAND_MEM_SIZE - 1,
-};
-static struct orion_nand_data sheevaplug_nand_data = {
-        .parts          = sheevaplug_nand_parts,
-        .nr_parts       = ARRAY_SIZE(sheevaplug_nand_parts),
-        .cle            = 0,
-        .ale            = 1,
-        .width          = 8,
-        .chip_delay     = 25,
-};
-static struct platform_device sheevaplug_nand_flash = {
-        .name           = "orion_nand",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &sheevaplug_nand_data,
-        },
-        .resource       = &sheevaplug_nand_resource,
-        .num_resources  = 1,
-};
 static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
 static struct mvsdio_platform_data sheevaplug_mvsdio_data = {
-        // unfortunately the CD signal has not been connected */
+        /* unfortunately the CD signal has not been connected */
 };
 static struct gpio_led sheevaplug_led_pins[] = {
@@ -111,6 +83,7 @@ static void __init sheevaplug_init(void)
        kirkwood_mpp_conf(sheevaplug_mpp_config);
        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(sheevaplug_nand_parts), 25);
        if (gpio_request(29, "USB Power Enable") != 0 ||
            gpio_direction_output(29, 1) != 0)
@@ -120,7 +93,6 @@ static void __init sheevaplug_init(void)
        kirkwood_ge00_init(&sheevaplug_ge00_data);
        kirkwood_sdio_init(&sheevaplug_mvsdio_data);
-        platform_device_register(&sheevaplug_nand_flash);
        platform_device_register(&sheevaplug_leds);
 }
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index e83e45ebf7a4..16295cfd5e29 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -52,6 +52,7 @@
 /*
 * Interrupt numbers for PXA910
 */
+#define IRQ_PXA910_NONE                 (-1)
 #define IRQ_PXA910_AIRQ                 0
 #define IRQ_PXA910_SSP3                 1
 #define IRQ_PXA910_SSP2                 2
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index 2e914649b9e4..3b216bf41e7f 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -253,6 +253,10 @@
 #define GPIO58_LCD_PCLK_WR      MFP_CFG(GPIO58, AF1)
 #define GPIO85_LCD_VSYNC        MFP_CFG(GPIO85, AF1)
+/* I2C */
+#define GPIO105_CI2C_SDA        MFP_CFG(GPIO105, AF1)
+#define GPIO106_CI2C_SCL        MFP_CFG(GPIO106, AF1)
 /* I2S */
 #define GPIO113_I2S_MCLK        MFP_CFG(GPIO113,AF6)
 #define GPIO114_I2S_FRM         MFP_CFG(GPIO114,AF1)
@@ -260,4 +264,27 @@
 #define GPIO116_I2S_RXD         MFP_CFG(GPIO116,AF2)
 #define GPIO117_I2S_TXD         MFP_CFG(GPIO117,AF2)
+/* PWM */
+#define GPIO96_PWM3_OUT         MFP_CFG(GPIO96, AF1)
+#define GPIO97_PWM2_OUT         MFP_CFG(GPIO97, AF1)
+#define GPIO98_PWM1_OUT         MFP_CFG(GPIO98, AF1)
+#define GPIO104_PWM4_OUT        MFP_CFG(GPIO104, AF1)
+#define GPIO106_PWM2_OUT        MFP_CFG(GPIO106, AF2)
+#define GPIO74_PWM4_OUT         MFP_CFG(GPIO74, AF2)
+#define GPIO75_PWM3_OUT         MFP_CFG(GPIO75, AF2)
+#define GPIO76_PWM2_OUT         MFP_CFG(GPIO76, AF2)
+#define GPIO77_PWM1_OUT         MFP_CFG(GPIO77, AF2)
+#define GPIO82_PWM4_OUT         MFP_CFG(GPIO82, AF2)
+#define GPIO83_PWM3_OUT         MFP_CFG(GPIO83, AF2)
+#define GPIO84_PWM2_OUT         MFP_CFG(GPIO84, AF2)
+#define GPIO85_PWM1_OUT         MFP_CFG(GPIO85, AF2)
+#define GPIO84_PWM1_OUT         MFP_CFG(GPIO84, AF4)
+#define GPIO122_PWM3_OUT        MFP_CFG(GPIO122, AF3)
+#define GPIO123_PWM1_OUT        MFP_CFG(GPIO123, AF1)
+#define GPIO124_PWM2_OUT        MFP_CFG(GPIO124, AF1)
+#define GPIO125_PWM3_OUT        MFP_CFG(GPIO125, AF1)
+#define GPIO126_PWM4_OUT        MFP_CFG(GPIO126, AF1)
+#define GPIO86_PWM1_OUT         MFP_CFG(GPIO86, AF2)
+#define GPIO86_PWM2_OUT         MFP_CFG(GPIO86, AF3)
 #endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
index d97de36c50ad..bf1189ff9a34 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -159,4 +159,12 @@
 #define MMC1_CD_MMC1_CD         MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM)
 #define MMC1_WP_MMC1_WP         MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM)
+/* PWM */
+#define GPIO27 PWM3 AF2         MFP_CFG(GPIO27, AF2)
+#define GPIO51_PWM2_OUT         MFP_CFG(GPIO51, AF2)
+#define GPIO117_PWM1_OUT        MFP_CFG(GPIO117, AF2)
+#define GPIO118_PWM2_OUT        MFP_CFG(GPIO118, AF2)
+#define GPIO119_PWM3_OUT        MFP_CFG(GPIO119, AF2)
+#define GPIO120_PWM4_OUT        MFP_CFG(GPIO120, AF2)
 #endif /* __ASM_MACH MFP_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index ef0a8a2076e9..6bf1f0eefcd1 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -1,10 +1,18 @@
 #ifndef __ASM_MACH_PXA168_H
 #define __ASM_MACH_PXA168_H
+#include <linux/i2c.h>
 #include <mach/devices.h>
+#include <plat/i2c.h>
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
+extern struct pxa_device_desc pxa168_device_twsi0;
+extern struct pxa_device_desc pxa168_device_twsi1;
+extern struct pxa_device_desc pxa168_device_pwm1;
+extern struct pxa_device_desc pxa168_device_pwm2;
+extern struct pxa_device_desc pxa168_device_pwm3;
+extern struct pxa_device_desc pxa168_device_pwm4;
 static inline int pxa168_add_uart(int id)
 {
@@ -20,4 +28,40 @@ static inline int pxa168_add_uart(int id)
        return pxa_register_device(d, NULL, 0);
 }
+static inline int pxa168_add_twsi(int id, struct i2c_pxa_platform_data *data,
+                                  struct i2c_board_info *info, unsigned size)
+{
+        struct pxa_device_desc *d = NULL;
+        int ret;
+        switch (id) {
+        case 0: d = &pxa168_device_twsi0; break;
+        case 1: d = &pxa168_device_twsi1; break;
+        default:
+                return -EINVAL;
+        }
+        ret = i2c_register_board_info(id, info, size);
+        if (ret)
+                return ret;
+        return pxa_register_device(d, data, sizeof(*data));
+}
+static inline int pxa168_add_pwm(int id)
+{
+        struct pxa_device_desc *d = NULL;
+        switch (id) {
+        case 1: d = &pxa168_device_pwm1; break;
+        case 2: d = &pxa168_device_pwm2; break;
+        case 3: d = &pxa168_device_pwm3; break;
+        case 4: d = &pxa168_device_pwm4; break;
+        default:
+                return -EINVAL;
+        }
+        return pxa_register_device(d, NULL, 0);
+}
 #endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index b7aeaf574c36..6ae1ed7a0a9f 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -1,10 +1,18 @@
 #ifndef __ASM_MACH_PXA910_H
 #define __ASM_MACH_PXA910_H
+#include <linux/i2c.h>
 #include <mach/devices.h>
+#include <plat/i2c.h>
 extern struct pxa_device_desc pxa910_device_uart1;
 extern struct pxa_device_desc pxa910_device_uart2;
+extern struct pxa_device_desc pxa910_device_twsi0;
+extern struct pxa_device_desc pxa910_device_twsi1;
+extern struct pxa_device_desc pxa910_device_pwm1;
+extern struct pxa_device_desc pxa910_device_pwm2;
+extern struct pxa_device_desc pxa910_device_pwm3;
+extern struct pxa_device_desc pxa910_device_pwm4;
 static inline int pxa910_add_uart(int id)
 {
@@ -20,4 +28,40 @@ static inline int pxa910_add_uart(int id)
        return pxa_register_device(d, NULL, 0);
 }
+static inline int pxa910_add_twsi(int id, struct i2c_pxa_platform_data *data,
+                                  struct i2c_board_info *info, unsigned size)
+{
+        struct pxa_device_desc *d = NULL;
+        int ret;
+        switch (id) {
+        case 0: d = &pxa910_device_twsi0; break;
+        case 1: d = &pxa910_device_twsi1; break;
+        default:
+                return -EINVAL;
+        }
+        ret = i2c_register_board_info(id, info, size);
+        if (ret)
+                return ret;
+        return pxa_register_device(d, data, sizeof(*data));
+}
+static inline int pxa910_add_pwm(int id)
+{
+        struct pxa_device_desc *d = NULL;
+        switch (id) {
+        case 1: d = &pxa910_device_pwm1; break;
+        case 2: d = &pxa910_device_pwm2; break;
+        case 3: d = &pxa910_device_pwm3; break;
+        case 4: d = &pxa910_device_pwm4; break;
+        default:
+                return -EINVAL;
+        }
+        return pxa_register_device(d, NULL, 0);
+}
 #endif /* __ASM_MACH_PXA910_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index c6b8c9dc2026..98ccbee4bd0c 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -22,8 +22,10 @@
 #define APBC_PXA168_UART1       APBC_REG(0x000)
 #define APBC_PXA168_UART2       APBC_REG(0x004)
 #define APBC_PXA168_GPIO        APBC_REG(0x008)
-#define APBC_PXA168_PWM0        APBC_REG(0x00c)
+#define APBC_PXA168_PWM1        APBC_REG(0x00c)
-#define APBC_PXA168_PWM1        APBC_REG(0x010)
+#define APBC_PXA168_PWM2        APBC_REG(0x010)
+#define APBC_PXA168_PWM3        APBC_REG(0x014)
+#define APBC_PXA168_PWM4        APBC_REG(0x018)
 #define APBC_PXA168_SSP1        APBC_REG(0x01c)
 #define APBC_PXA168_SSP2        APBC_REG(0x020)
 #define APBC_PXA168_RTC         APBC_REG(0x028)
@@ -48,10 +50,10 @@
 #define APBC_PXA910_UART0       APBC_REG(0x000)
 #define APBC_PXA910_UART1       APBC_REG(0x004)
 #define APBC_PXA910_GPIO        APBC_REG(0x008)
-#define APBC_PXA910_PWM0        APBC_REG(0x00c)
+#define APBC_PXA910_PWM1        APBC_REG(0x00c)
-#define APBC_PXA910_PWM1        APBC_REG(0x010)
+#define APBC_PXA910_PWM2        APBC_REG(0x010)
-#define APBC_PXA910_PWM2        APBC_REG(0x014)
+#define APBC_PXA910_PWM3        APBC_REG(0x014)
-#define APBC_PXA910_PWM3        APBC_REG(0x018)
+#define APBC_PXA910_PWM4        APBC_REG(0x018)
 #define APBC_PXA910_SSP1        APBC_REG(0x01c)
 #define APBC_PXA910_SSP2        APBC_REG(0x020)
 #define APBC_PXA910_IPC         APBC_REG(0x024)
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index ae924468658c..71b1ae338753 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -65,11 +65,23 @@ void __init pxa168_init_irq(void)
 /* APB peripheral clocks */
 static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
 static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
+static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
+        INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
+        INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
+        INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
 };
 static int __init pxa168_init(void)
@@ -109,3 +121,9 @@ struct sys_timer pxa168_timer = {
 /* on-chip devices */
 PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
 PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
+PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
+PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
+PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
+PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10);
+PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10);
+PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 453f8f7758bf..5882ca6b49fb 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -103,11 +103,23 @@ void __init pxa910_init_irq(void)
 /* APB peripheral clocks */
 static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
 static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
+static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
 /* device and clock bindings */
 static struct clk_lookup pxa910_clkregs[] = {
        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
+        INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
+        INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
+        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
 };
 static int __init pxa910_init(void)
@@ -156,3 +168,9 @@ struct sys_timer pxa910_timer = {
 */
 PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22);
 PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24);
+PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
+PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
+PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10);
+PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
+PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
+PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index f289b0ea7dcf..22b4ff893b3c 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -28,6 +28,9 @@ void __init mv78xx0_init_irq(void)
 {
        int i;
+        /* Initialize gpiolib. */
+        orion_gpio_init();
        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
        orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
index 0dec6f300ffc..7622c9b38c97 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-mx1/generic.c
@@ -26,6 +26,7 @@
 #include <asm/mach/map.h>
+#include <mach/common.h>
 #include <mach/hardware.h>
 static struct map_desc imx_io_desc[] __initdata = {
@@ -37,7 +38,9 @@ static struct map_desc imx_io_desc[] __initdata = {
        }
 };
-void __init mxc_map_io(void)
+void __init mx1_map_io(void)
 {
+        mxc_set_cpu_type(MXC_CPU_MX1);
        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
index e54057fb855b..e5b0c0a83c3b 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -12,77 +12,56 @@
 * warranty of any kind, whether express or implied.
 */
-#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pcf857x.h>
 #include <linux/init.h>
+#include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/i2c/pcf857x.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
+#include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <mach/i2c.h>
+#include <mach/imx-uart.h>
 #include <mach/iomux.h>
+#include <mach/irqs.h>
 #include "devices.h"
-/*
+static int mx1ads_pins[] = {
- * UARTs platform data
+        /* UART1 */
- */
-static int mxc_uart1_pins[] = {
        PC9_PF_UART1_CTS,
        PC10_PF_UART1_RTS,
        PC11_PF_UART1_TXD,
        PC12_PF_UART1_RXD,
-};
+        /* UART2 */
-static int uart1_mxc_init(struct platform_device *pdev)
-{
-        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
-                        ARRAY_SIZE(mxc_uart1_pins), "UART1");
-}
-static int uart1_mxc_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart1_pins,
-                        ARRAY_SIZE(mxc_uart1_pins));
-        return 0;
-}
-static int mxc_uart2_pins[] = {
        PB28_PF_UART2_CTS,
        PB29_PF_UART2_RTS,
        PB30_PF_UART2_TXD,
        PB31_PF_UART2_RXD,
+        /* I2C */
+        PA15_PF_I2C_SDA,
+        PA16_PF_I2C_SCL,
+        /* SPI */
+        PC13_PF_SPI1_SPI_RDY,
+        PC14_PF_SPI1_SCLK,
+        PC15_PF_SPI1_SS,
+        PC16_PF_SPI1_MISO,
+        PC17_PF_SPI1_MOSI,
 };
-static int uart2_mxc_init(struct platform_device *pdev)
+/*
-{
+ * UARTs platform data
-        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+ */
-                        ARRAY_SIZE(mxc_uart2_pins), "UART2");
-}
-static int uart2_mxc_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart2_pins,
-                        ARRAY_SIZE(mxc_uart2_pins));
-        return 0;
-}
 static struct imxuart_platform_data uart_pdata[] = {
        {
-                .init = uart1_mxc_init,
-                .exit = uart1_mxc_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart2_mxc_init,
-                .exit = uart2_mxc_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        },
 };
@@ -111,24 +90,6 @@ static struct platform_device flash_device = {
 /*
 * I2C
 */
-static int i2c_pins[] = {
-        PA15_PF_I2C_SDA,
-        PA16_PF_I2C_SCL,
-};
-static int i2c_init(struct device *dev)
-{
-        return mxc_gpio_setup_multiple_pins(i2c_pins,
-                        ARRAY_SIZE(i2c_pins), "I2C");
-}
-static void i2c_exit(struct device *dev)
-{
-        mxc_gpio_release_multiple_pins(i2c_pins,
-                        ARRAY_SIZE(i2c_pins));
-}
 static struct pcf857x_platform_data pcf857x_data[] = {
        {
                .gpio_base = 4 * 32,
@@ -139,8 +100,6 @@ static struct pcf857x_platform_data pcf857x_data[] = {
 static struct imxi2c_platform_data mx1ads_i2c_data = {
        .bitrate = 100000,
-        .init = i2c_init,
-        .exit = i2c_exit,
 };
 static struct i2c_board_info mx1ads_i2c_devices[] = {
@@ -160,6 +119,9 @@ static struct i2c_board_info mx1ads_i2c_devices[] = {
 */
 static void __init mx1ads_init(void)
 {
+        mxc_gpio_setup_multiple_pins(mx1ads_pins,
+                ARRAY_SIZE(mx1ads_pins), "mx1ads");
        /* UART */
        mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
        mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
@@ -188,7 +150,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
        .phys_io        = IMX_IO_PHYS,
        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx1_map_io,
        .init_irq       = mxc_init_irq,
        .timer          = &mx1ads_timer,
        .init_machine   = mx1ads_init,
@@ -198,7 +160,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
        .phys_io        = IMX_IO_PHYS,
        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx1_map_io,
        .init_irq       = mxc_init_irq,
        .timer          = &mx1ads_timer,
        .init_machine   = mx1ads_init,
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c
index 0e71f3fa28bf..20e0b5bcdffc 100644
--- a/arch/arm/mach-mx1/scb9328.c
+++ b/arch/arm/mach-mx1/scb9328.c
@@ -153,7 +153,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
        .phys_io        = 0x00200000,
        .io_pg_offst    = ((0xe0200000) >> 18) & 0xfffc,
        .boot_params    = 0x08000100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx1_map_io,
        .init_irq       = mxc_init_irq,
        .timer          = &scb9328_timer,
        .init_machine   = scb9328_init,
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index 42a788842f49..c77da586b71d 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -18,6 +18,13 @@ endchoice
 comment "MX2 platforms:"
+config MACH_MX21ADS
+        bool "MX21ADS platform"
+        depends on MACH_MX21
+        help
+          Include support for MX21ADS platform. This includes specific
+          configurations for the board and its peripherals.
 config MACH_MX27ADS
        bool "MX27ADS platform"
        depends on MACH_MX27
@@ -46,4 +53,18 @@ config MACH_PCM970_BASEBOARD
 endchoice
+config MACH_MX27_3DS
+        bool "MX27PDK platform"
+        depends on MACH_MX27
+        help
+          Include support for MX27PDK platform. This includes specific
+          configurations for the board and its peripherals.
+config MACH_MX27LITE
+        bool "LogicPD MX27 LITEKIT platform"
+        depends on MACH_MX27
+        help
+          Include support for MX27 LITEKIT platform. This includes specific
+          configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 950649a91540..b9b1cca4e9bc 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -11,6 +11,10 @@ obj-$(CONFIG_MACH_MX21) += clock_imx21.o
 obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
 obj-$(CONFIG_MACH_MX27) += clock_imx27.o
+obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o
 obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
+obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o
+obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index e4b08ca804ea..0850fb88ec15 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -48,6 +48,25 @@ static void _clk_disable(struct clk *clk)
        __raw_writel(reg, clk->enable_reg);
 }
+static unsigned long _clk_generic_round_rate(struct clk *clk,
+                        unsigned long rate,
+                        u32 max_divisor)
+{
+        u32 div;
+        unsigned long parent_rate;
+        parent_rate = clk_get_rate(clk->parent);
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+        if (div > max_divisor)
+                div = max_divisor;
+        return parent_rate / div;
+}
 static int _clk_spll_enable(struct clk *clk)
 {
        u32 reg;
@@ -78,19 +97,7 @@ static void _clk_spll_disable(struct clk *clk)
 static unsigned long _clk_perclkx_round_rate(struct clk *clk,
                                             unsigned long rate)
 {
-        u32 div;
+        return _clk_generic_round_rate(clk, rate, 64);
-        unsigned long parent_rate;
-        parent_rate = clk_get_rate(clk->parent);
-        div = parent_rate / rate;
-        if (parent_rate % rate)
-                div++;
-        if (div > 64)
-                div = 64;
-        return parent_rate / div;
 }
 static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
@@ -130,6 +137,32 @@ static unsigned long _clk_usb_recalc(struct clk *clk)
        return parent_rate / (usb_pdf + 1U);
 }
+static unsigned long _clk_usb_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        return _clk_generic_round_rate(clk, rate, 8);
+}
+static int _clk_usb_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+        parent_rate = clk_get_rate(clk->parent);
+        div = parent_rate / rate;
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+        reg = CSCR() & ~CCM_CSCR_USB_MASK;
+        reg |= div << CCM_CSCR_USB_OFFSET;
+        __raw_writel(reg, CCM_CSCR);
+        return 0;
+}
 static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
 {
        unsigned long parent_rate;
@@ -595,11 +628,14 @@ static struct clk csi_clk[] = {
 static struct clk usb_clk[] = {
        {
                .parent = &spll_clk,
+                .secondary = &usb_clk[1],
                .get_rate = _clk_usb_recalc,
                .enable = _clk_enable,
                .enable_reg = CCM_PCCR_USBOTG_REG,
                .enable_shift = CCM_PCCR_USBOTG_OFFSET,
                .disable = _clk_disable,
+                .round_rate = _clk_usb_round_rate,
+                .set_rate = _clk_usb_set_rate,
        }, {
                .parent = &hclk_clk,
                .enable = _clk_enable,
@@ -768,18 +804,7 @@ static struct clk rtc_clk = {
 static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
 {
-        u32 div;
+        return _clk_generic_round_rate(clk, rate, 8);
-        unsigned long parent_rate;
-        parent_rate = clk_get_rate(clk->parent);
-        div = parent_rate / rate;
-        if (parent_rate % rate)
-                div++;
-        if (div > 8)
-                div = 8;
-        return parent_rate / div;
 }
 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
@@ -921,7 +946,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
        _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
-        _REGISTER_CLOCK(NULL, "usb", usb_clk[0])
+        _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
        _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
        _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index bd51dd04948e..169372f69d8f 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -69,7 +69,17 @@ static struct map_desc mxc_io_desc[] __initdata = {
 * system startup to create static physical to virtual
 * memory map for the IO modules.
 */
-void __init mxc_map_io(void)
+void __init mx21_map_io(void)
 {
+        mxc_set_cpu_type(MXC_CPU_MX21);
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
+void __init mx27_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX27);
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c
new file mode 100644
index 000000000000..a5ee461cb405
--- /dev/null
+++ b/arch/arm/mach-mx2/mx21ads.c
@@ -0,0 +1,286 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/imx-uart.h>
+#include <mach/imxfb.h>
+#include <mach/iomux.h>
+#include <mach/mxc_nand.h>
+#include <mach/mmc.h>
+#include <mach/board-mx21ads.h>
+#include "devices.h"
+static unsigned int mx21ads_pins[] = {
+        /* CS8900A */
+        (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* UART3 (IrDA) - only TXD and RXD */
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        /* UART4 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* LCDC */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA24_PF_REV,     /* Sharp panel dedicated signal */
+        PA25_PF_CLS,     /* Sharp panel dedicated signal */
+        PA26_PF_PS,      /* Sharp panel dedicated signal */
+        PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        PA31_PF_OE_ACD,
+        /* MMC/SDHC */
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        /* NFC */
+        PF0_PF_NRFB,
+        PF1_PF_NFCE,
+        PF2_PF_NFWP,
+        PF3_PF_NFCLE,
+        PF4_PF_NFALE,
+        PF5_PF_NFRE,
+        PF6_PF_NFWE,
+        PF7_PF_NFIO0,
+        PF8_PF_NFIO1,
+        PF9_PF_NFIO2,
+        PF10_PF_NFIO3,
+        PF11_PF_NFIO4,
+        PF12_PF_NFIO5,
+        PF13_PF_NFIO6,
+        PF14_PF_NFIO7,
+};
+/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
+static struct physmap_flash_data mx21ads_flash_data = {
+        .width = 4,
+};
+static struct resource mx21ads_flash_resource = {
+        .start = CS0_BASE_ADDR,
+        .end = CS0_BASE_ADDR + 0x02000000 - 1,
+        .flags = IORESOURCE_MEM,
+};
+static struct platform_device mx21ads_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &mx21ads_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &mx21ads_flash_resource,
+};
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct imxuart_platform_data uart_norts_pdata = {
+};
+static int mx21ads_fb_init(struct platform_device *pdev)
+{
+        u16 tmp;
+        tmp = __raw_readw(MX21ADS_IO_REG);
+        tmp |= MX21ADS_IO_LCDON;
+        __raw_writew(tmp, MX21ADS_IO_REG);
+        return 0;
+}
+static void mx21ads_fb_exit(struct platform_device *pdev)
+{
+        u16 tmp;
+        tmp = __raw_readw(MX21ADS_IO_REG);
+        tmp &= ~MX21ADS_IO_LCDON;
+        __raw_writew(tmp, MX21ADS_IO_REG);
+}
+/*
+ * Connected is a portrait Sharp-QVGA display
+ * of type: LQ035Q7DB02
+ */
+static struct imx_fb_platform_data mx21ads_fb_data = {
+        .pixclock       = 188679, /* in ps */
+        .xres           = 240,
+        .yres           = 320,
+        .bpp            = 16,
+        .hsync_len      = 2,
+        .left_margin    = 6,
+        .right_margin   = 16,
+        .vsync_len      = 1,
+        .upper_margin   = 8,
+        .lower_margin   = 10,
+        .fixed_screen_cpu = 0,
+        .pcr            = 0xFB108BC7,
+        .pwmr           = 0x00A901ff,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020008,
+        .init = mx21ads_fb_init,
+        .exit = mx21ads_fb_exit,
+};
+static int mx21ads_sdhc_get_ro(struct device *dev)
+{
+        return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
+}
+static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
+        void *data)
+{
+        int ret;
+        ret = request_irq(IRQ_GPIOD(25), detect_irq,
+                IRQF_TRIGGER_FALLING, "mmc-detect", data);
+        if (ret)
+                goto out;
+        return 0;
+out:
+        return ret;
+}
+static void mx21ads_sdhc_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIOD(25), data);
+}
+static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
+        .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
+        .get_ro = mx21ads_sdhc_get_ro,
+        .init = mx21ads_sdhc_init,
+        .exit = mx21ads_sdhc_exit,
+};
+static struct mxc_nand_platform_data mx21ads_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+static struct map_desc mx21ads_io_desc[] __initdata = {
+        /*
+         * Memory-mapped I/O on MX21ADS Base board:
+         *   - CS8900A Ethernet controller
+         *   - ST16C2552CJ UART
+         *   - CPU and Base board version
+         *   - Base board I/O register
+         */
+        {
+                .virtual = MX21ADS_MMIO_BASE_ADDR,
+                .pfn = __phys_to_pfn(CS1_BASE_ADDR),
+                .length = MX21ADS_MMIO_SIZE,
+                .type = MT_DEVICE,
+        },
+};
+static void __init mx21ads_map_io(void)
+{
+        mx21_map_io();
+        iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
+}
+static struct platform_device *platform_devices[] __initdata = {
+        &mx21ads_nor_mtd_device,
+};
+static void __init mx21ads_board_init(void)
+{
+        mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
+                        "mx21ads");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
+        mxc_register_device(&mxc_uart_device3, &uart_pdata);
+        mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
+        mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
+        mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+static void __init mx21ads_timer_init(void)
+{
+        mx21_clocks_init(32768, 26000000);
+}
+static struct sys_timer mx21ads_timer = {
+        .init   = mx21ads_timer_init,
+};
+MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
+        /* maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx21ads_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mx21ads_board_init,
+        .timer          = &mx21ads_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 4a3b097adc12..02daddac6995 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -23,6 +23,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -33,9 +35,117 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux.h>
 #include <mach/board-mx27ads.h>
+#include <mach/mxc_nand.h>
+#include <mach/i2c.h>
+#include <mach/imxfb.h>
+#include <mach/mmc.h>
 #include "devices.h"
+static unsigned int mx27ads_pins[] = {
+        /* UART0 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* UART1 */
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD,
+        /* UART2 */
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS,
+        /* UART3 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* UART4 */
+        PB18_AF_UART5_TXD,
+        PB19_AF_UART5_RXD,
+        PB20_AF_UART5_CTS,
+        PB21_AF_UART5_RTS,
+        /* UART5 */
+        PB10_AF_UART6_TXD,
+        PB12_AF_UART6_CTS,
+        PB11_AF_UART6_RXD,
+        PB13_AF_UART6_RTS,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* I2C2 */
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* FB */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA24_PF_REV,
+        PA25_PF_CLS,
+        PA26_PF_PS,
+        PA27_PF_SPL_SPR,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        PA31_PF_OE_ACD,
+        /* OWIRE */
+        PE16_AF_OWIRE,
+        /* SDHC1*/
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        /* SDHC2*/
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+};
+static struct mxc_nand_platform_data mx27ads_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
 /* ADS's NOR flash */
 static struct physmap_flash_data mx27ads_flash_data = {
        .width = 2,
@@ -58,189 +168,113 @@ static struct platform_device mx27ads_nor_mtd_device = {
        .resource = &mx27ads_flash_resource,
 };
-static int mxc_uart0_pins[] = {
+static struct imxi2c_platform_data mx27ads_i2c_data = {
-        PE12_PF_UART1_TXD,
+        .bitrate = 100000,
-        PE13_PF_UART1_RXD,
-        PE14_PF_UART1_CTS,
-        PE15_PF_UART1_RTS
 };
-static int uart_mxc_port0_init(struct platform_device *pdev)
+static struct i2c_board_info mx27ads_i2c_devices[] = {
-{
-        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
-                        ARRAY_SIZE(mxc_uart0_pins), "UART0");
-}
-static int uart_mxc_port0_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart0_pins,
-                        ARRAY_SIZE(mxc_uart0_pins));
-        return 0;
-}
-static int mxc_uart1_pins[] = {
-        PE3_PF_UART2_CTS,
-        PE4_PF_UART2_RTS,
-        PE6_PF_UART2_TXD,
-        PE7_PF_UART2_RXD
 };
-static int uart_mxc_port1_init(struct platform_device *pdev)
+void lcd_power(int on)
 {
-        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+        if (on)
-                        ARRAY_SIZE(mxc_uart1_pins), "UART1");
+                __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
+        else
+                __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 }
-static int uart_mxc_port1_exit(struct platform_device *pdev)
+static struct imx_fb_platform_data mx27ads_fb_data = {
-{
+        .pixclock       = 188679,
-        mxc_gpio_release_multiple_pins(mxc_uart1_pins,
+        .xres           = 240,
-                        ARRAY_SIZE(mxc_uart1_pins));
+        .yres           = 320,
-        return 0;
-}
+        .bpp            = 16,
+        .hsync_len      = 1,
-static int mxc_uart2_pins[] = {
+        .left_margin    = 9,
-        PE8_PF_UART3_TXD,
+        .right_margin   = 16,
-        PE9_PF_UART3_RXD,
-        PE10_PF_UART3_CTS,
+        .vsync_len      = 1,
-        PE11_PF_UART3_RTS
+        .upper_margin   = 7,
+        .lower_margin   = 9,
+        .fixed_screen_cpu = 0,
+        /*
+         * - HSYNC active high
+         * - VSYNC active high
+         * - clk notenabled while idle
+         * - clock inverted
+         * - data not inverted
+         * - data enable low active
+         * - enable sharp mode
+         */
+        .pcr            = 0xFB008BC0,
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020010,
+        .lcd_power      = lcd_power,
 };
-static int uart_mxc_port2_init(struct platform_device *pdev)
+static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+                              void *data)
 {
-        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+        return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
-                        ARRAY_SIZE(mxc_uart2_pins), "UART2");
+                           "sdhc1-card-detect", data);
 }
-static int uart_mxc_port2_exit(struct platform_device *pdev)
+static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+                              void *data)
 {
-        mxc_gpio_release_multiple_pins(mxc_uart2_pins,
+        return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
-                        ARRAY_SIZE(mxc_uart2_pins));
+                           "sdhc2-card-detect", data);
-        return 0;
 }
-static int mxc_uart3_pins[] = {
+static void mx27ads_sdhc1_exit(struct device *dev, void *data)
-        PB26_AF_UART4_RTS,
-        PB28_AF_UART4_TXD,
-        PB29_AF_UART4_CTS,
-        PB31_AF_UART4_RXD
-};
-static int uart_mxc_port3_init(struct platform_device *pdev)
 {
-        return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
+        free_irq(IRQ_GPIOE(21), data);
-                        ARRAY_SIZE(mxc_uart3_pins), "UART3");
 }
-static int uart_mxc_port3_exit(struct platform_device *pdev)
+static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 {
-        mxc_gpio_release_multiple_pins(mxc_uart3_pins,
+        free_irq(IRQ_GPIOB(7), data);
-                        ARRAY_SIZE(mxc_uart3_pins));
-        return 0;
 }
-static int mxc_uart4_pins[] = {
+static struct imxmmc_platform_data sdhc1_pdata = {
-        PB18_AF_UART5_TXD,
+        .init = mx27ads_sdhc1_init,
-        PB19_AF_UART5_RXD,
+        .exit = mx27ads_sdhc1_exit,
-        PB20_AF_UART5_CTS,
-        PB21_AF_UART5_RTS
 };
-static int uart_mxc_port4_init(struct platform_device *pdev)
+static struct imxmmc_platform_data sdhc2_pdata = {
-{
+        .init = mx27ads_sdhc2_init,
-        return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
+        .exit = mx27ads_sdhc2_exit,
-                        ARRAY_SIZE(mxc_uart4_pins), "UART4");
-}
-static int uart_mxc_port4_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart4_pins,
-                        ARRAY_SIZE(mxc_uart4_pins));
-        return 0;
-}
-static int mxc_uart5_pins[] = {
-        PB10_AF_UART6_TXD,
-        PB12_AF_UART6_CTS,
-        PB11_AF_UART6_RXD,
-        PB13_AF_UART6_RTS
 };
-static int uart_mxc_port5_init(struct platform_device *pdev)
-{
-        return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
-                        ARRAY_SIZE(mxc_uart5_pins), "UART5");
-}
-static int uart_mxc_port5_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart5_pins,
-                        ARRAY_SIZE(mxc_uart5_pins));
-        return 0;
-}
 static struct platform_device *platform_devices[] __initdata = {
        &mx27ads_nor_mtd_device,
        &mxc_fec_device,
+        &mxc_w1_master_device,
 };
-static int mxc_fec_pins[] = {
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN
-};
-static void gpio_fec_active(void)
-{
-        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
-                        ARRAY_SIZE(mxc_fec_pins), "FEC");
-}
 static struct imxuart_platform_data uart_pdata[] = {
        {
-                .init = uart_mxc_port0_init,
-                .exit = uart_mxc_port0_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart_mxc_port1_init,
-                .exit = uart_mxc_port1_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart_mxc_port2_init,
-                .exit = uart_mxc_port2_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart_mxc_port3_init,
-                .exit = uart_mxc_port3_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart_mxc_port4_init,
-                .exit = uart_mxc_port4_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart_mxc_port5_init,
-                .exit = uart_mxc_port5_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        },
 };
 static void __init mx27ads_board_init(void)
 {
-        gpio_fec_active();
+        mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
+                        "mx27ads");
        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
@@ -248,6 +282,15 @@ static void __init mx27ads_board_init(void)
        mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
        mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
        mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
+        mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info);
+        /* only the i2c master 1 is used on this CPU card */
+        i2c_register_board_info(1, mx27ads_i2c_devices,
+                                ARRAY_SIZE(mx27ads_i2c_devices));
+        mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
+        mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
+        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
+        mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
@@ -277,7 +320,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = {
 static void __init mx27ads_map_io(void)
 {
-        mxc_map_io();
+        mx27_map_io();
        iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
 }
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mx27lite.c
new file mode 100644
index 000000000000..3ae11cb8c04b
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27lite.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux.h>
+#include <mach/board-mx27lite.h>
+#include "devices.h"
+static unsigned int mx27lite_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+};
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct platform_device *platform_devices[] __initdata = {
+        &mxc_fec_device,
+};
+static void __init mx27lite_init(void)
+{
+        mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
+                "imx27lite");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+static void __init mx27lite_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+static struct sys_timer mx27lite_timer = {
+        .init   = mx27lite_timer_init,
+};
+MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mx27lite_init,
+        .timer          = &mx27lite_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c
new file mode 100644
index 000000000000..1d9238c7a6c3
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27pdk.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux.h>
+#include <mach/board-mx27pdk.h>
+#include "devices.h"
+static unsigned int mx27pdk_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+};
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct platform_device *platform_devices[] __initdata = {
+        &mxc_fec_device,
+};
+static void __init mx27pdk_init(void)
+{
+        mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
+                "mx27pdk");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+static void __init mx27pdk_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+static struct sys_timer mx27pdk_timer = {
+        .init   = mx27pdk_timer_init,
+};
+MACHINE_START(MX27_3DS, "Freescale MX27PDK")
+        /* maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mx27pdk_init,
+        .timer          = &mx27pdk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index aa4eaa61d1b5..a4628d004343 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -17,28 +17,84 @@
 * MA 02110-1301, USA.
 */
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
+#include <linux/io.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
-#include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/board-pcm038.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/iomux.h>
-#ifdef CONFIG_I2C_IMX
 #include <mach/i2c.h>
-#endif
+#include <mach/iomux.h>
-#include <asm/mach/time.h>
 #include <mach/imx-uart.h>
-#include <mach/board-pcm038.h>
 #include <mach/mxc_nand.h>
 #include "devices.h"
+static int pcm038_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* UART2 */
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD,
+        /* UART3 */
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* I2C2 */
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* SPI1 */
+        PD25_PF_CSPI1_RDY,
+        PD27_PF_CSPI1_SS1,
+        PD28_PF_CSPI1_SS0,
+        PD29_PF_CSPI1_SCLK,
+        PD30_PF_CSPI1_MISO,
+        PD31_PF_CSPI1_MOSI,
+        /* SSI1 */
+        PC20_PF_SSI1_FS,
+        PC21_PF_SSI1_RXD,
+        PC22_PF_SSI1_TXD,
+        PC23_PF_SSI1_CLK,
+        /* SSI4 */
+        PC16_PF_SSI4_FS,
+        PC17_PF_SSI4_RXD,
+        PC18_PF_SSI4_TXD,
+        PC19_PF_SSI4_CLK,
+};
 /*
 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
 * 16 bit width
@@ -88,107 +144,16 @@ static struct platform_device pcm038_nor_mtd_device = {
        .resource = &pcm038_flash_resource,
 };
-static int mxc_uart0_pins[] = {
-        PE12_PF_UART1_TXD,
-        PE13_PF_UART1_RXD,
-        PE14_PF_UART1_CTS,
-        PE15_PF_UART1_RTS
-};
-static int uart_mxc_port0_init(struct platform_device *pdev)
-{
-        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
-                        ARRAY_SIZE(mxc_uart0_pins), "UART0");
-}
-static int uart_mxc_port0_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart0_pins,
-                        ARRAY_SIZE(mxc_uart0_pins));
-        return 0;
-}
-static int mxc_uart1_pins[] = {
-        PE3_PF_UART2_CTS,
-        PE4_PF_UART2_RTS,
-        PE6_PF_UART2_TXD,
-        PE7_PF_UART2_RXD
-};
-static int uart_mxc_port1_init(struct platform_device *pdev)
-{
-        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
-                        ARRAY_SIZE(mxc_uart1_pins), "UART1");
-}
-static int uart_mxc_port1_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart1_pins,
-                        ARRAY_SIZE(mxc_uart1_pins));
-        return 0;
-}
-static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
-                                PE9_PF_UART3_RXD,
-                                PE10_PF_UART3_CTS,
-                                PE11_PF_UART3_RTS };
-static int uart_mxc_port2_init(struct platform_device *pdev)
-{
-        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
-                        ARRAY_SIZE(mxc_uart2_pins), "UART2");
-}
-static int uart_mxc_port2_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_uart2_pins,
-                        ARRAY_SIZE(mxc_uart2_pins));
-        return 0;
-}
 static struct imxuart_platform_data uart_pdata[] = {
        {
-                .init = uart_mxc_port0_init,
-                .exit = uart_mxc_port0_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart_mxc_port1_init,
-                .exit = uart_mxc_port1_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        }, {
-                .init = uart_mxc_port2_init,
-                .exit = uart_mxc_port2_exit,
                .flags = IMXUART_HAVE_RTSCTS,
        },
 };
-static int mxc_fec_pins[] = {
-        PD0_AIN_FEC_TXD0,
-        PD1_AIN_FEC_TXD1,
-        PD2_AIN_FEC_TXD2,
-        PD3_AIN_FEC_TXD3,
-        PD4_AOUT_FEC_RX_ER,
-        PD5_AOUT_FEC_RXD1,
-        PD6_AOUT_FEC_RXD2,
-        PD7_AOUT_FEC_RXD3,
-        PD8_AF_FEC_MDIO,
-        PD9_AIN_FEC_MDC,
-        PD10_AOUT_FEC_CRS,
-        PD11_AOUT_FEC_TX_CLK,
-        PD12_AOUT_FEC_RXD0,
-        PD13_AOUT_FEC_RX_DV,
-        PD14_AOUT_FEC_RX_CLK,
-        PD15_AOUT_FEC_COL,
-        PD16_AIN_FEC_TX_ER,
-        PF23_AIN_FEC_TX_EN
-};
-static void gpio_fec_active(void)
-{
-        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
-                        ARRAY_SIZE(mxc_fec_pins), "FEC");
-}
 static struct mxc_nand_platform_data pcm038_nand_board_info = {
        .width = 1,
        .hw_ecc = 1,
@@ -210,27 +175,8 @@ static void __init pcm038_init_sram(void)
        __raw_writel(0x22220a00, CSCR_A(1));
 }
-#ifdef CONFIG_I2C_IMX
-static int mxc_i2c1_pins[] = {
-        PC5_PF_I2C2_SDA,
-        PC6_PF_I2C2_SCL
-};
-static int pcm038_i2c_1_init(struct device *dev)
-{
-        return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
-                        "I2C1");
-}
-static void pcm038_i2c_1_exit(struct device *dev)
-{
-        mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
-}
 static struct imxi2c_platform_data pcm038_i2c_1_data = {
        .bitrate = 100000,
-        .init = pcm038_i2c_1_init,
-        .exit = pcm038_i2c_1_exit,
 };
 static struct at24_platform_data board_eeprom = {
@@ -253,11 +199,12 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
                .type = "lm75"
        }
 };
-#endif
 static void __init pcm038_init(void)
 {
-        gpio_fec_active();
+        mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
+                        "PCM038");
        pcm038_init_sram();
        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
@@ -267,13 +214,11 @@ static void __init pcm038_init(void)
        mxc_gpio_mode(PE16_AF_OWIRE);
        mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
-#ifdef CONFIG_I2C_IMX
        /* only the i2c master 1 is used on this CPU card */
        i2c_register_board_info(1, pcm038_i2c_devices,
                                ARRAY_SIZE(pcm038_i2c_devices));
        mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
-#endif
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
@@ -295,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
        .phys_io        = AIPI_BASE_ADDR,
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx27_map_io,
        .init_irq       = mxc_init_irq,
        .init_machine   = pcm038_init,
        .timer          = &pcm038_timer,
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index bf4e520bc1bc..6a3acaf57dd4 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -16,71 +16,107 @@
 * MA 02110-1301, USA.
 */
-#include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/platform_device.h>
 #include <asm/mach/arch.h>
-#include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/mmc.h>
-#include <mach/imxfb.h>
 #include <mach/iomux.h>
+#include <mach/imxfb.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
 #include "devices.h"
-static int pcm970_sdhc2_get_ro(struct device *dev)
+static int pcm970_pins[] = {
-{
+        /* SDHC */
-        return gpio_get_value(GPIO_PORTC + 28);
-}
-static int pcm970_sdhc2_pins[] = {
        PB4_PF_SD2_D0,
        PB5_PF_SD2_D1,
        PB6_PF_SD2_D2,
        PB7_PF_SD2_D3,
        PB8_PF_SD2_CMD,
        PB9_PF_SD2_CLK,
+        GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN, /* card detect */
+        /* display */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA24_PF_REV,
+        PA25_PF_CLS,
+        PA26_PF_PS,
+        PA27_PF_SPL_SPR,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        PA31_PF_OE_ACD,
+        /*
+         * it seems the data line misses a pullup, so we must enable
+         * the internal pullup as a local workaround
+         */
+        PD17_PF_I2C_DATA | GPIO_PUEN,
+        PD18_PF_I2C_CLK,
+        /* Camera */
+        PB10_PF_CSI_D0,
+        PB11_PF_CSI_D1,
+        PB12_PF_CSI_D2,
+        PB13_PF_CSI_D3,
+        PB14_PF_CSI_D4,
+        PB15_PF_CSI_MCLK,
+        PB16_PF_CSI_PIXCLK,
+        PB17_PF_CSI_D5,
+        PB18_PF_CSI_D6,
+        PB19_PF_CSI_D7,
+        PB20_PF_CSI_VSYNC,
+        PB21_PF_CSI_HSYNC,
 };
+static int pcm970_sdhc2_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO_PORTC + 28);
+}
 static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
 {
        int ret;
-        ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins,
+        ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
-                ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2");
-        if(ret)
-                return ret;
-        ret = request_irq(IRQ_GPIOC(29), detect_irq, 0,
                                "imx-mmc-detect", data);
        if (ret)
-                goto out_release_gpio;
+                return ret;
-        set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING);
        ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
-        if (ret)
+        if (ret) {
-                goto out_release_gpio;
+                free_irq(IRQ_GPIOC(29), data);
+                return ret;
+        }
-        mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN);
        gpio_direction_input(GPIO_PORTC + 28);
        return 0;
-out_release_gpio:
-        mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
-                        ARRAY_SIZE(pcm970_sdhc2_pins));
-        return ret;
 }
 static void pcm970_sdhc2_exit(struct device *dev, void *data)
 {
        free_irq(IRQ_GPIOC(29), data);
        gpio_free(GPIO_PORTC + 28);
-        mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
-                        ARRAY_SIZE(pcm970_sdhc2_pins));
 }
 static struct imxmmc_platform_data sdhc_pdata = {
@@ -89,29 +125,6 @@ static struct imxmmc_platform_data sdhc_pdata = {
        .exit = pcm970_sdhc2_exit,
 };
-static int mxc_fb_pins[] = {
-        PA5_PF_LSCLK,   PA6_PF_LD0,     PA7_PF_LD1,     PA8_PF_LD2,
-        PA9_PF_LD3,     PA10_PF_LD4,    PA11_PF_LD5,    PA12_PF_LD6,
-        PA13_PF_LD7,    PA14_PF_LD8,    PA15_PF_LD9,    PA16_PF_LD10,
-        PA17_PF_LD11,   PA18_PF_LD12,   PA19_PF_LD13,   PA20_PF_LD14,
-        PA21_PF_LD15,   PA22_PF_LD16,   PA23_PF_LD17,   PA24_PF_REV,
-        PA25_PF_CLS,    PA26_PF_PS,     PA27_PF_SPL_SPR, PA28_PF_HSYNC,
-        PA29_PF_VSYNC,  PA30_PF_CONTRAST, PA31_PF_OE_ACD
-};
-static int pcm038_fb_init(struct platform_device *pdev)
-{
-        return mxc_gpio_setup_multiple_pins(mxc_fb_pins,
-                        ARRAY_SIZE(mxc_fb_pins), "FB");
-}
-static int pcm038_fb_exit(struct platform_device *pdev)
-{
-        mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins));
-        return 0;
-}
 /*
 * Connected is a portrait Sharp-QVGA display
 * of type: LQ035Q7DH06
@@ -144,9 +157,6 @@ static struct imx_fb_platform_data pcm038_fb_data = {
        .pwmr           = 0x00A903FF,
        .lscr1          = 0x00120300,
        .dmacr          = 0x00020010,
-        .init = pcm038_fb_init,
-        .exit = pcm038_fb_exit,
 };
 /*
@@ -157,6 +167,9 @@ static struct imx_fb_platform_data pcm038_fb_data = {
 */
 void __init pcm970_baseboard_init(void)
 {
+        mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
+                        "PCM970");
        mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 }
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 194b8428bba4..17a21a291e2f 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -1,10 +1,12 @@
 if ARCH_MX3
 config ARCH_MX31
+        select ARCH_HAS_RNGA
        bool
 config ARCH_MX35
        bool
+        select ARCH_MXC_IOMUX_V3
 comment "MX3 platforms:"
@@ -37,7 +39,6 @@ config MACH_PCM037
 config MACH_MX31LITE
        bool "Support MX31 LITEKIT (LogicPD)"
        select ARCH_MX31
-        default n
        help
          Include support for MX31 LITEKIT platform. This includes specific
          configurations for the board and its peripherals.
@@ -45,7 +46,6 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
        bool "Support MX31PDK (3DS)"
        select ARCH_MX31
-        default n
        help
          Include support for MX31PDK (3DS) platform. This includes specific
          configurations for the board and its peripherals.
@@ -53,17 +53,43 @@ config MACH_MX31_3DS
 config MACH_MX31MOBOARD
        bool "Support mx31moboard platforms (EPFL Mobots group)"
        select ARCH_MX31
-        default n
        help
          Include support for mx31moboard platform. This includes specific
          configurations for the board and its peripherals.
+config MACH_MX31LILLY
+        bool "Support MX31 LILLY-1131 platforms (INCO startec)"
+        select ARCH_MX31
+        help
+          Include support for mx31 based LILLY1131 modules. This includes
+          specific configurations for the board and its peripherals.
 config MACH_QONG
        bool "Support Dave/DENX QongEVB-LITE platform"
        select ARCH_MX31
-        default n
        help
          Include support for Dave/DENX QongEVB-LITE platform. This includes
          specific configurations for the board and its peripherals.
+config MACH_PCM043
+        bool "Support Phytec pcm043 (i.MX35) platforms"
+        select ARCH_MX35
+        help
+          Include support for Phytec pcm043 platform. This includes
+          specific configurations for the board and its peripherals.
+config MACH_ARMADILLO5X0
+        bool "Support Atmark Armadillo-500 Development Base Board"
+        select ARCH_MX31
+        help
+          Include support for Atmark Armadillo-500 platform. This includes
+          specific configurations for the board and its peripherals.
+config MACH_MX35_3DS
+        bool "Support MX35PDK platform"
+        select ARCH_MX35
+        default n
+        help
+          Include support for MX35PDK platform. This includes specific
+          configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 272c8a953b30..0322696bd11a 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -8,9 +8,13 @@ obj-y				:= mm.o devices.o
 obj-$(CONFIG_ARCH_MX31)         += clock.o iomux.o
 obj-$(CONFIG_ARCH_MX35)         += clock-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mx31ads.o
+obj-$(CONFIG_MACH_MX31LILLY)    += mx31lilly.o mx31lilly-db.o
 obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o
 obj-$(CONFIG_MACH_PCM037)       += pcm037.o
 obj-$(CONFIG_MACH_MX31_3DS)     += mx31pdk.o
 obj-$(CONFIG_MACH_MX31MOBOARD)  += mx31moboard.o mx31moboard-devboard.o \
                                   mx31moboard-marxbot.o
 obj-$(CONFIG_MACH_QONG)         += qong.o
+obj-$(CONFIG_MACH_PCM043)       += pcm043.o
+obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o
+obj-$(CONFIG_MACH_MX35_3DS)     += mx35pdk.o
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
new file mode 100644
index 000000000000..541181090b37
--- /dev/null
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -0,0 +1,295 @@
+/*
+ * armadillo5x0.c
+ *
+ * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ * updates in http://alberdroid.blogspot.com/
+ *
+ * Based on Atmark Techno, Inc. armadillo 500 BSP 2008
+ * Based on mx31ads.c and pcm037.c Great Work!
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-armadillo5x0.h>
+#include <mach/mmc.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include "devices.h"
+static int armadillo5x0_pins[] = {
+        /* UART1 */
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        /* UART2 */
+        MX31_PIN_CTS2__CTS2,
+        MX31_PIN_RTS2__RTS2,
+        MX31_PIN_TXD2__TXD2,
+        MX31_PIN_RXD2__RXD2,
+        /* LAN9118_IRQ */
+        IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO),
+        /* SDHC1 */
+        MX31_PIN_SD1_DATA3__SD1_DATA3,
+        MX31_PIN_SD1_DATA2__SD1_DATA2,
+        MX31_PIN_SD1_DATA1__SD1_DATA1,
+        MX31_PIN_SD1_DATA0__SD1_DATA0,
+        MX31_PIN_SD1_CLK__SD1_CLK,
+        MX31_PIN_SD1_CMD__SD1_CMD,
+        /* Framebuffer */
+        MX31_PIN_LD0__LD0,
+        MX31_PIN_LD1__LD1,
+        MX31_PIN_LD2__LD2,
+        MX31_PIN_LD3__LD3,
+        MX31_PIN_LD4__LD4,
+        MX31_PIN_LD5__LD5,
+        MX31_PIN_LD6__LD6,
+        MX31_PIN_LD7__LD7,
+        MX31_PIN_LD8__LD8,
+        MX31_PIN_LD9__LD9,
+        MX31_PIN_LD10__LD10,
+        MX31_PIN_LD11__LD11,
+        MX31_PIN_LD12__LD12,
+        MX31_PIN_LD13__LD13,
+        MX31_PIN_LD14__LD14,
+        MX31_PIN_LD15__LD15,
+        MX31_PIN_LD16__LD16,
+        MX31_PIN_LD17__LD17,
+        MX31_PIN_VSYNC3__VSYNC3,
+        MX31_PIN_HSYNC__HSYNC,
+        MX31_PIN_FPSHIFT__FPSHIFT,
+        MX31_PIN_DRDY0__DRDY0,
+        IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
+};
+/*
+ * FB support
+ */
+static const struct fb_videomode fb_modedb[] = {
+        {       /* 640x480 @ 60 Hz */
+                .name           = "CRT-VGA",
+                .refresh        = 60,
+                .xres           = 640,
+                .yres           = 480,
+                .pixclock       = 39721,
+                .left_margin    = 35,
+                .right_margin   = 115,
+                .upper_margin   = 43,
+                .lower_margin   = 1,
+                .hsync_len      = 10,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_OE_ACT_HIGH,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        }, {/* 800x600 @ 56 Hz */
+                .name           = "CRT-SVGA",
+                .refresh        = 56,
+                .xres           = 800,
+                .yres           = 600,
+                .pixclock       = 30000,
+                .left_margin    = 30,
+                .right_margin   = 108,
+                .upper_margin   = 13,
+                .lower_margin   = 10,
+                .hsync_len      = 10,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT |
+                                  FB_SYNC_VERT_HIGH_ACT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+};
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "CRT-VGA",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+/*
+ * SDHC 1
+ * MMC support
+ */
+static int armadillo5x0_sdhc1_get_ro(struct device *dev)
+{
+        return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
+}
+static int armadillo5x0_sdhc1_init(struct device *dev,
+                                   irq_handler_t detect_irq, void *data)
+{
+        int ret;
+        int gpio_det, gpio_wp;
+        gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK);
+        gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B);
+        ret = gpio_request(gpio_det, "sdhc-card-detect");
+        if (ret)
+                return ret;
+        gpio_direction_input(gpio_det);
+        ret = gpio_request(gpio_wp, "sdhc-write-protect");
+        if (ret)
+                goto err_gpio_free;
+        gpio_direction_input(gpio_wp);
+        /* When supported the trigger type have to be BOTH */
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "sdhc-detect", data);
+        if (ret)
+                goto err_gpio_free_2;
+        return 0;
+err_gpio_free_2:
+        gpio_free(gpio_wp);
+err_gpio_free:
+        gpio_free(gpio_det);
+        return ret;
+}
+static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
+        gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
+        gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
+}
+static struct imxmmc_platform_data sdhc_pdata = {
+        .get_ro = armadillo5x0_sdhc1_get_ro,
+        .init = armadillo5x0_sdhc1_init,
+        .exit = armadillo5x0_sdhc1_exit,
+};
+/*
+ * SMSC 9118
+ * Network support
+ */
+static struct resource armadillo5x0_smc911x_resources[] = {
+        {
+                .start  = CS3_BASE_ADDR,
+                .end    = CS3_BASE_ADDR + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+static struct smsc911x_platform_config smsc911x_info = {
+        .flags          = SMSC911X_USE_32BIT,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+static struct platform_device armadillo5x0_smc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(armadillo5x0_smc911x_resources),
+        .resource       = armadillo5x0_smc911x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_info,
+        },
+};
+/* UART device data */
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct platform_device *devices[] __initdata = {
+        &armadillo5x0_smc911x_device,
+};
+/*
+ * Perform board specific initializations
+ */
+static void __init armadillo5x0_init(void)
+{
+        mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
+                        ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        /* Register UART */
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        /* SMSC9118 IRQ pin */
+        gpio_direction_input(MX31_PIN_GPIO1_0);
+        /* Register SDHC */
+        mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
+        /* Register FB */
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+}
+static void __init armadillo5x0_timer_init(void)
+{
+        mx31_clocks_init(26000000);
+}
+static struct sys_timer armadillo5x0_timer = {
+        .init   = armadillo5x0_timer_init,
+};
+MACHINE_START(ARMADILLO5X0, "Armadillo-500")
+        /* Maintainer: Alberto Panizzo  */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .map_io         = mx31_map_io,
+        .init_irq       = mxc_init_irq,
+        .timer          = &armadillo5x0_timer,
+        .init_machine   = armadillo5x0_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 3c1e06f56dd6..577ee83d1f60 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -147,34 +147,16 @@ static struct arm_ahb_div clk_consumer[] = {
        { .arm = 0, .ahb = 0, .sel = 0},
 };
-static struct arm_ahb_div clk_automotive[] = {
-        { .arm = 1, .ahb = 3, .sel = 0},
-        { .arm = 1, .ahb = 2, .sel = 1},
-        { .arm = 2, .ahb = 1, .sel = 1},
-        { .arm = 0, .ahb = 0, .sel = 0},
-        { .arm = 1, .ahb = 6, .sel = 0},
-        { .arm = 1, .ahb = 4, .sel = 1},
-        { .arm = 2, .ahb = 2, .sel = 1},
-        { .arm = 0, .ahb = 0, .sel = 0},
-};
 static unsigned long get_rate_arm(void)
 {
        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
        struct arm_ahb_div *aad;
        unsigned long fref = get_rate_mpll();
-        if (pdr0 & 1) {
+        aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-                /* consumer path */
+        if (aad->sel)
-                aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+                fref = fref * 2 / 3;
-                if (aad->sel)
-                        fref = fref * 2 / 3;
-        } else {
-                /* auto path */
-                aad = &clk_automotive[(pdr0 >> 9) & 0x7];
-                if (aad->sel)
-                        fref = fref * 3 / 4;
-        }
        return fref / aad->arm;
 }
@@ -184,12 +166,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
        struct arm_ahb_div *aad;
        unsigned long fref = get_rate_mpll();
-        if (pdr0 & 1)
+        aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-                /* consumer path */
-                aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-        else
-                /* auto path */
-                aad = &clk_automotive[(pdr0 >> 9) & 0x7];
        return fref / aad->ahb;
 }
@@ -430,7 +407,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
        _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
-        _REGISTER_CLOCK(NULL, "ipu", ipu_clk)
+        _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
+        _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
        _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
@@ -462,8 +440,6 @@ int __init mx35_clocks_init()
        int i;
        unsigned int ll = 0;
-        mxc_set_cpu_type(MXC_CPU_MX35);
 #ifdef CONFIG_DEBUG_LL_CONSOLE
        ll = (3 << 16);
 #endif
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index a68fcf981edf..8b14239724c9 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -483,7 +483,7 @@ DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
 DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &ahb_clk);
+DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
 DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
@@ -566,13 +566,18 @@ int __init mx31_clocks_init(unsigned long fref)
        u32 reg;
        int i;
-        mxc_set_cpu_type(MXC_CPU_MX31);
        ckih_rate = fref;
        for (i = 0; i < ARRAY_SIZE(lookups); i++)
                clkdev_add(&lookups[i]);
+        /* change the csi_clk parent if necessary */
+        reg = __raw_readl(MXC_CCM_CCMR);
+        if (!(reg & MXC_CCM_CCMR_CSCS))
+                if (clk_set_parent(&csi_clk, &usb_pll_clk))
+                        pr_err("%s: error changing csi_clk parent\n", __func__);
        /* Turn off all possible clocks */
        __raw_writel((3 << 4), MXC_CCM_CGR0);
        __raw_writel(0, MXC_CCM_CGR1);
@@ -581,6 +586,12 @@ int __init mx31_clocks_init(unsigned long fref)
                                           MX32, but still required to be set */
                     MXC_CCM_CGR2);
+        /*
+         * Before turning off usb_pll make sure ipg_per_clk is generated
+         * by ipg_clk and not usb_pll.
+         */
+        __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
        usb_pll_disable(&usb_pll_clk);
        pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 380be0c9b213..d927eddcad46 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -17,13 +17,17 @@
 * Boston, MA  02110-1301, USA.
 */
+#include <linux/dma-mapping.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/gpio.h>
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/common.h>
 #include <mach/imx-uart.h>
+#include <mach/mx3_camera.h>
 #include "devices.h"
@@ -283,6 +287,21 @@ struct platform_device mxcsdhc_device1 = {
        .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
        .resource = mxcsdhc1_resources,
 };
+static struct resource rnga_resources[] = {
+        {
+                .start = RNGA_BASE_ADDR,
+                .end = RNGA_BASE_ADDR + 0x28,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct platform_device mxc_rnga_device = {
+        .name = "mxc_rnga",
+        .id = -1,
+        .num_resources = 1,
+        .resource = rnga_resources,
+};
 #endif /* CONFIG_ARCH_MX31 */
 /* i.MX31 Image Processing Unit */
@@ -329,10 +348,54 @@ struct platform_device mx3_fb = {
        .num_resources  = ARRAY_SIZE(fb_resources),
        .resource       = fb_resources,
        .dev            = {
-                .coherent_dma_mask = 0xffffffff,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
       },
 };
+static struct resource camera_resources[] = {
+        {
+                .start  = IPU_CTRL_BASE_ADDR + 0x60,
+                .end    = IPU_CTRL_BASE_ADDR + 0x87,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+struct platform_device mx3_camera = {
+        .name           = "mx3-camera",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(camera_resources),
+        .resource       = camera_resources,
+        .dev            = {
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+static struct resource otg_resources[] = {
+        {
+                .start  = OTG_BASE_ADDR,
+                .end    = OTG_BASE_ADDR + 0x1ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_USB3,
+                .end    = MXC_INT_USB3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static u64 otg_dmamask = DMA_BIT_MASK(32);
+/* OTG gadget device */
+struct platform_device mxc_otg_udc_device = {
+        .name           = "fsl-usb2-udc",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &otg_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = otg_resources,
+        .num_resources  = ARRAY_SIZE(otg_resources),
+};
 #ifdef CONFIG_ARCH_MX35
 static struct resource mxc_fec_resources[] = {
        {
@@ -359,6 +422,7 @@ static int mx3_devices_init(void)
        if (cpu_is_mx31()) {
                mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
                mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
+                mxc_register_device(&mxc_rnga_device, NULL);
        }
        if (cpu_is_mx35()) {
                mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 88c04b296fab..ffd494ddd4ac 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -11,6 +11,10 @@ extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
+extern struct platform_device mx3_camera;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxcsdhc_device0;
 extern struct platform_device mxcsdhc_device1;
+extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_rnga_device;
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index 40ffc5a664d9..c66ccbcdc11b 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -21,7 +21,6 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
-#include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
@@ -94,15 +93,13 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
 EXPORT_SYMBOL(mxc_iomux_set_pad);
 /*
- * setups a single pin:
+ * allocs a single pin:
 *      - reserves the pin so that it is not claimed by another driver
 *      - setups the iomux according to the configuration
- *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
 */
-int mxc_iomux_setup_pin(const unsigned int pin, const char *label)
+int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
 {
        unsigned pad = pin & IOMUX_PADNUM_MASK;
-        unsigned gpio;
        if (pad >= (PIN_MAX + 1)) {
                printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
@@ -113,19 +110,13 @@ int mxc_iomux_setup_pin(const unsigned int pin, const char *label)
        if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
                printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
                        pad, label ? label : "?");
-                return -EINVAL;
+                return -EBUSY;
        }
        mxc_iomux_mode(pin);
-        /* if we have a gpio, we can allocate it */
-        gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
-        if (gpio < (GPIO_PORT_MAX + 1) * 32)
-                if (gpio_request(gpio, label))
-                        return -EINVAL;
        return 0;
 }
-EXPORT_SYMBOL(mxc_iomux_setup_pin);
+EXPORT_SYMBOL(mxc_iomux_alloc_pin);
 int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
                const char *label)
@@ -135,7 +126,8 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
        int ret = -EINVAL;
        for (i = 0; i < count; i++) {
-                if (mxc_iomux_setup_pin(*p, label))
+                ret = mxc_iomux_alloc_pin(*p, label);
+                if (ret)
                        goto setup_error;
                p++;
        }
@@ -150,14 +142,9 @@ EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
 void mxc_iomux_release_pin(const unsigned int pin)
 {
        unsigned pad = pin & IOMUX_PADNUM_MASK;
-        unsigned gpio;
        if (pad < (PIN_MAX + 1))
                clear_bit(pad, mxc_pin_alloc_map);
-        gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
-        if (gpio < (GPIO_PORT_MAX + 1) * 32)
-                gpio_free(gpio);
 }
 EXPORT_SYMBOL(mxc_iomux_release_pin);
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 9e1459cb4b74..1f5fdd456cb9 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -72,8 +72,17 @@ static struct map_desc mxc_io_desc[] __initdata = {
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
 */
-void __init mxc_map_io(void)
+void __init mx31_map_io(void)
 {
+        mxc_set_cpu_type(MXC_CPU_MX31);
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+void __init mx35_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX35);
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index a6d6efefa6aa..30e2767a78ae 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -187,7 +187,7 @@ static void __init mx31ads_init_expio(void)
        /*
         * Configure INT line as GPIO input
         */
-        mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
+        mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
        /* disable the interrupt and clear the status */
        __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
@@ -511,7 +511,7 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
 */
 static void __init mx31ads_map_io(void)
 {
-        mxc_map_io();
+        mx31_map_io();
        iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
 }
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
new file mode 100644
index 000000000000..3b3a78f49c23
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -0,0 +1,216 @@
+/*
+ *  LILLY-1131 development board support
+ *
+ *    Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ *  based on code for other MX31 boards,
+ *
+ *    Copyright 2005-2007 Freescale Semiconductor
+ *    Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ *    Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lilly.h>
+#include <mach/mmc.h>
+#include <mach/mx3fb.h>
+#include <mach/ipu.h>
+#include "devices.h"
+/*
+ * This file contains board-specific initialization routines for the
+ * LILLY-1131 development board. If you design an own baseboard for the
+ * module, use this file as base for support code.
+ */
+static unsigned int lilly_db_board_pins[] __initdata = {
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        MX31_PIN_CTS2__CTS2,
+        MX31_PIN_RTS2__RTS2,
+        MX31_PIN_TXD2__TXD2,
+        MX31_PIN_RXD2__RXD2,
+        MX31_PIN_CSPI3_MOSI__RXD3,
+        MX31_PIN_CSPI3_MISO__TXD3,
+        MX31_PIN_CSPI3_SCLK__RTS3,
+        MX31_PIN_CSPI3_SPI_RDY__CTS3,
+        MX31_PIN_SD1_DATA3__SD1_DATA3,
+        MX31_PIN_SD1_DATA2__SD1_DATA2,
+        MX31_PIN_SD1_DATA1__SD1_DATA1,
+        MX31_PIN_SD1_DATA0__SD1_DATA0,
+        MX31_PIN_SD1_CLK__SD1_CLK,
+        MX31_PIN_SD1_CMD__SD1_CMD,
+        MX31_PIN_LD0__LD0,
+        MX31_PIN_LD1__LD1,
+        MX31_PIN_LD2__LD2,
+        MX31_PIN_LD3__LD3,
+        MX31_PIN_LD4__LD4,
+        MX31_PIN_LD5__LD5,
+        MX31_PIN_LD6__LD6,
+        MX31_PIN_LD7__LD7,
+        MX31_PIN_LD8__LD8,
+        MX31_PIN_LD9__LD9,
+        MX31_PIN_LD10__LD10,
+        MX31_PIN_LD11__LD11,
+        MX31_PIN_LD12__LD12,
+        MX31_PIN_LD13__LD13,
+        MX31_PIN_LD14__LD14,
+        MX31_PIN_LD15__LD15,
+        MX31_PIN_LD16__LD16,
+        MX31_PIN_LD17__LD17,
+        MX31_PIN_VSYNC3__VSYNC3,
+        MX31_PIN_HSYNC__HSYNC,
+        MX31_PIN_FPSHIFT__FPSHIFT,
+        MX31_PIN_DRDY0__DRDY0,
+        MX31_PIN_CONTRAST__CONTRAST,
+};
+/* UART */
+static struct imxuart_platform_data uart_pdata __initdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+/* MMC support */
+static int mxc_mmc1_get_ro(struct device *dev)
+{
+        return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
+}
+static int gpio_det, gpio_wp;
+static int mxc_mmc1_init(struct device *dev,
+                         irq_handler_t detect_irq, void *data)
+{
+        int ret;
+        gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
+        gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
+        ret = gpio_request(gpio_det, "MMC detect");
+        if (ret)
+                return ret;
+        ret = gpio_request(gpio_wp, "MMC w/p");
+        if (ret)
+                goto exit_free_det;
+        gpio_direction_input(gpio_det);
+        gpio_direction_input(gpio_wp);
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "MMC detect", data);
+        if (ret)
+                goto exit_free_wp;
+        return 0;
+exit_free_wp:
+        gpio_free(gpio_wp);
+exit_free_det:
+        gpio_free(gpio_det);
+        return ret;
+}
+static void mxc_mmc1_exit(struct device *dev, void *data)
+{
+        gpio_free(gpio_det);
+        gpio_free(gpio_wp);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
+}
+static struct imxmmc_platform_data mmc_pdata = {
+        .get_ro = mxc_mmc1_get_ro,
+        .init   = mxc_mmc1_init,
+        .exit   = mxc_mmc1_exit,
+};
+/* Framebuffer support */
+static struct ipu_platform_data ipu_data __initdata = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+static const struct fb_videomode fb_modedb = {
+        /* 640x480 TFT panel (IPS-056T) */
+        .name           = "CRT-VGA",
+        .refresh        = 64,
+        .xres           = 640,
+        .yres           = 480,
+        .pixclock       = 30000,
+        .left_margin    = 200,
+        .right_margin   = 2,
+        .upper_margin   = 2,
+        .lower_margin   = 2,
+        .hsync_len      = 3,
+        .vsync_len      = 1,
+        .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
+        .vmode          = FB_VMODE_NONINTERLACED,
+        .flag           = 0,
+};
+static struct mx3fb_platform_data fb_pdata __initdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "CRT-VGA",
+        .mode           = &fb_modedb,
+        .num_modes      = 1,
+};
+#define LCD_VCC_EN_GPIO  (7)
+static void __init mx31lilly_init_fb(void)
+{
+        if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) {
+                printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n");
+                return;
+        }
+        mxc_register_device(&mx3_ipu, &ipu_data);
+        mxc_register_device(&mx3_fb, &fb_pdata);
+        gpio_direction_output(LCD_VCC_EN_GPIO, 1);
+}
+void __init mx31lilly_db_init(void)
+{
+        mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
+                                        ARRAY_SIZE(lilly_db_board_pins),
+                                        "development board pins");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
+        mx31lilly_init_fb();
+}
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c
new file mode 100644
index 000000000000..6ab2f163cb95
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lilly.c
@@ -0,0 +1,155 @@
+/*
+ *  LILLY-1131 module support
+ *
+ *    Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ *  based on code for other MX31 boards,
+ *
+ *    Copyright 2005-2007 Freescale Semiconductor
+ *    Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ *    Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/smsc911x.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lilly.h>
+#include "devices.h"
+/*
+ * This file contains module-specific initialization routines for LILLY-1131.
+ * Initialization of peripherals found on the baseboard is implemented in the
+ * appropriate baseboard support code.
+ */
+/* SMSC ethernet support */
+static struct resource smsc91x_resources[] = {
+        {
+                .start  = CS4_BASE_ADDR,
+                .end    = CS4_BASE_ADDR + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
+        }
+};
+static struct smsc911x_platform_config smsc911x_config = {
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_32BIT |
+                          SMSC911X_SAVE_MAC_ADDRESS |
+                          SMSC911X_FORCE_INTERNAL_PHY,
+};
+static struct platform_device smsc91x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smsc91x_resources),
+        .resource       = smsc91x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_config,
+        }
+};
+/* NOR flash */
+static struct physmap_flash_data nor_flash_data = {
+        .width  = 2,
+};
+static struct resource nor_flash_resource = {
+        .start  = 0xa0000000,
+        .end    = 0xa1ffffff,
+        .flags  = IORESOURCE_MEM,
+};
+static struct platform_device physmap_flash_device = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &nor_flash_data,
+        },
+        .resource = &nor_flash_resource,
+        .num_resources = 1,
+};
+static struct platform_device *devices[] __initdata = {
+        &smsc91x_device,
+        &physmap_flash_device,
+        &mxc_i2c_device1,
+};
+static int mx31lilly_baseboard;
+core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
+static void __init mx31lilly_board_init(void)
+{
+        switch (mx31lilly_baseboard) {
+        case MX31LILLY_NOBOARD:
+                break;
+        case MX31LILLY_DB:
+                mx31lilly_db_init();
+                break;
+        default:
+                printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n",
+                        mx31lilly_baseboard);
+        }
+        mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA");
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+static void __init mx31lilly_timer_init(void)
+{
+        mx31_clocks_init(26000000);
+}
+static struct sys_timer mx31lilly_timer = {
+        .init   = mx31lilly_timer_init,
+};
+MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx31_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mx31lilly_board_init,
+        .timer          = &mx31lilly_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index 894d98cd9941..86fe70fa3e13 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -22,6 +22,9 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/memory.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -32,11 +35,64 @@
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <mach/board-mx31lite.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include <mach/irqs.h>
+#include <mach/mxc_nand.h>
+#include "devices.h"
 /*
 * This file contains the board-specific initialization routines.
 */
+static unsigned int mx31lite_pins[] = {
+        /* UART1 */
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        /* LAN9117 IRQ pin */
+        IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
+};
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct mxc_nand_platform_data mx31lite_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+static struct smsc911x_platform_config smsc911x_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags          = SMSC911X_USE_16BIT,
+};
+static struct resource smsc911x_resources[] = {
+        [0] = {
+                .start          = CS4_BASE_ADDR,
+                .end            = CS4_BASE_ADDR + 0x100,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IOMUX_TO_IRQ(MX31_PIN_SFS6),
+                .end            = IOMUX_TO_IRQ(MX31_PIN_SFS6),
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+        .resource       = smsc911x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_config,
+        },
+};
 /*
 * This structure defines the MX31 memory map.
 */
@@ -59,7 +115,7 @@ static struct map_desc mx31lite_io_desc[] __initdata = {
 */
 void __init mx31lite_map_io(void)
 {
-        mxc_map_io();
+        mx31_map_io();
        iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
 }
@@ -68,6 +124,22 @@ void __init mx31lite_map_io(void)
 */
 static void __init mxc_board_init(void)
 {
+        int ret;
+        mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
+                                      "mx31lite");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+        /* SMSC9117 IRQ pin */
+        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
+        if (ret)
+                pr_warning("could not get LAN irq gpio\n");
+        else {
+                gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+                platform_device_register(&smsc911x_device);
+        }
 }
 static void __init mx31lite_timer_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index d080b4add79c..4704405165a1 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -16,33 +16,142 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <linux/types.h>
+#include <linux/fsl_devices.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/types.h>
-#include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
 #include "devices.h"
+static unsigned int devboard_pins[] = {
+        /* UART1 */
+        MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
+        MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
+        /* SDHC2 */
+        MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
+        MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
+        MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
+        MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
+        /* USB OTG */
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
+        MX31_PIN_USB_OC__GPIO1_30,
+};
 static struct imxuart_platform_data uart_pdata = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-static int mxc_uart1_pins[] = {
+#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
-        MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
+#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
-        MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
+static int devboard_sdhc2_get_ro(struct device *dev)
+{
+        return gpio_get_value(SDHC2_WP);
+}
+static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+                void *data)
+{
+        int ret;
+        ret = gpio_request(SDHC2_CD, "sdhc-detect");
+        if (ret)
+                return ret;
+        gpio_direction_input(SDHC2_CD);
+        ret = gpio_request(SDHC2_WP, "sdhc-wp");
+        if (ret)
+                goto err_gpio_free;
+        gpio_direction_input(SDHC2_WP);
+        ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
+                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                "sdhc2-card-detect", data);
+        if (ret)
+                goto err_gpio_free_2;
+        return 0;
+err_gpio_free_2:
+        gpio_free(SDHC2_WP);
+err_gpio_free:
+        gpio_free(SDHC2_CD);
+        return ret;
+}
+static void devboard_sdhc2_exit(struct device *dev, void *data)
+{
+        free_irq(gpio_to_irq(SDHC2_CD), data);
+        gpio_free(SDHC2_WP);
+        gpio_free(SDHC2_CD);
+}
+static struct imxmmc_platform_data sdhc2_pdata = {
+        .get_ro = devboard_sdhc2_get_ro,
+        .init   = devboard_sdhc2_init,
+        .exit   = devboard_sdhc2_exit,
+};
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
 };
+#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
+#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+static void devboard_usbotg_init(void)
+{
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
+        gpio_request(OTG_EN_B, "usb-udc-en");
+        gpio_direction_output(OTG_EN_B, 0);
+}
 /*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
 void __init mx31moboard_devboard_init(void)
 {
        printk(KERN_INFO "Initializing mx31devboard peripherals\n");
-        mxc_iomux_setup_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins), "uart1");
+        mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
+                "devboard");
        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        devboard_usbotg_init();
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 9ef9566823fb..641c3d6153ae 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -16,22 +16,144 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <linux/types.h>
+#include <linux/fsl_devices.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/types.h>
-#include <mach/hardware.h>
 #include <mach/common.h>
+#include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/mmc.h>
 #include "devices.h"
+static unsigned int marxbot_pins[] = {
+        /* SDHC2 */
+        MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
+        MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
+        MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
+        MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
+        /* CSI */
+        MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
+        MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
+        MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
+        MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
+        MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
+        MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
+        MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
+        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
+        MX31_PIN_TXD2__GPIO1_28,
+        /* USB OTG */
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
+        MX31_PIN_USB_OC__GPIO1_30,
+};
+#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
+#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
+static int marxbot_sdhc2_get_ro(struct device *dev)
+{
+        return gpio_get_value(SDHC2_WP);
+}
+static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+                void *data)
+{
+        int ret;
+        ret = gpio_request(SDHC2_CD, "sdhc-detect");
+        if (ret)
+                return ret;
+        gpio_direction_input(SDHC2_CD);
+        ret = gpio_request(SDHC2_WP, "sdhc-wp");
+        if (ret)
+                goto err_gpio_free;
+        gpio_direction_input(SDHC2_WP);
+        ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
+                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                "sdhc2-card-detect", data);
+        if (ret)
+                goto err_gpio_free_2;
+        return 0;
+err_gpio_free_2:
+        gpio_free(SDHC2_WP);
+err_gpio_free:
+        gpio_free(SDHC2_CD);
+        return ret;
+}
+static void marxbot_sdhc2_exit(struct device *dev, void *data)
+{
+        free_irq(gpio_to_irq(SDHC2_CD), data);
+        gpio_free(SDHC2_WP);
+        gpio_free(SDHC2_CD);
+}
+static struct imxmmc_platform_data sdhc2_pdata = {
+        .get_ro = marxbot_sdhc2_get_ro,
+        .init   = marxbot_sdhc2_init,
+        .exit   = marxbot_sdhc2_exit,
+};
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
+#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+static void marxbot_usbotg_init(void)
+{
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
+        gpio_request(OTG_EN_B, "usb-udc-en");
+        gpio_direction_output(OTG_EN_B, 0);
+}
 /*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
 void __init mx31moboard_marxbot_init(void)
 {
        printk(KERN_INFO "Initializing mx31marxbot peripherals\n");
+        mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
+                "marxbot");
+        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        marxbot_usbotg_init();
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index 34c2a1b99d4f..a17f2e411609 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -16,26 +16,47 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <linux/types.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
-#include <linux/platform_device.h>
+#include <linux/memory.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
-#include <linux/memory.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <mach/board-mx31moboard.h>
 #include <mach/common.h>
+#include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/board-mx31moboard.h>
+#include <mach/i2c.h>
+#include <mach/mmc.h>
 #include "devices.h"
+static unsigned int moboard_pins[] = {
+        /* UART0 */
+        MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
+        /* UART4 */
+        MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
+        MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
+        /* I2C0 */
+        MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL,
+        /* I2C1 */
+        MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL,
+        /* SDHC1 */
+        MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2,
+        MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
+        MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
+        MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
+};
 static struct physmap_flash_data mx31moboard_flash_data = {
        .width          = 2,
 };
@@ -60,17 +81,69 @@ static struct imxuart_platform_data uart_pdata = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-static struct platform_device *devices[] __initdata = {
+static struct imxi2c_platform_data moboard_i2c0_pdata = {
-        &mx31moboard_flash,
+        .bitrate = 400000,
 };
-static int mxc_uart0_pins[] = {
+static struct imxi2c_platform_data moboard_i2c1_pdata = {
-        MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
+        .bitrate = 100000,
-        MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
 };
-static int mxc_uart4_pins[] = {
-        MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
+#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
-        MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
+#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
+static int moboard_sdhc1_get_ro(struct device *dev)
+{
+        return gpio_get_value(SDHC1_WP);
+}
+static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+                void *data)
+{
+        int ret;
+        ret = gpio_request(SDHC1_CD, "sdhc-detect");
+        if (ret)
+                return ret;
+        gpio_direction_input(SDHC1_CD);
+        ret = gpio_request(SDHC1_WP, "sdhc-wp");
+        if (ret)
+                goto err_gpio_free;
+        gpio_direction_input(SDHC1_WP);
+        ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq,
+                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                "sdhc1-card-detect", data);
+        if (ret)
+                goto err_gpio_free_2;
+        return 0;
+err_gpio_free_2:
+        gpio_free(SDHC1_WP);
+err_gpio_free:
+        gpio_free(SDHC1_CD);
+        return ret;
+}
+static void moboard_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(gpio_to_irq(SDHC1_CD), data);
+        gpio_free(SDHC1_WP);
+        gpio_free(SDHC1_CD);
+}
+static struct imxmmc_platform_data sdhc1_pdata = {
+        .get_ro = moboard_sdhc1_get_ro,
+        .init   = moboard_sdhc1_init,
+        .exit   = moboard_sdhc1_exit,
+};
+static struct platform_device *devices[] __initdata = {
+        &mx31moboard_flash,
 };
 static int mx31moboard_baseboard;
@@ -81,14 +154,19 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
 */
 static void __init mxc_board_init(void)
 {
+        mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
+                "moboard");
        platform_add_devices(devices, ARRAY_SIZE(devices));
-        mxc_iomux_setup_multiple_pins(mxc_uart0_pins, ARRAY_SIZE(mxc_uart0_pins), "uart0");
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_iomux_setup_multiple_pins(mxc_uart4_pins, ARRAY_SIZE(mxc_uart4_pins), "uart4");
        mxc_register_device(&mxc_uart_device4, &uart_pdata);
+        mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
+        mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
+        mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
        switch (mx31moboard_baseboard) {
        case MX31NOBOARD:
                break;
@@ -99,7 +177,8 @@ static void __init mxc_board_init(void)
                mx31moboard_marxbot_init();
                break;
        default:
-                printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard);
+                printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
+                        mx31moboard_baseboard);
        }
 }
@@ -117,7 +196,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
        .phys_io        = AIPS1_BASE_ADDR,
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx31_map_io,
        .init_irq       = mxc_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &mx31moboard_timer,
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index bc63f1785691..c19838d2e369 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -20,6 +20,9 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/platform_device.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -41,21 +44,192 @@
 * @ingroup System
 */
+static int mx31pdk_pins[] = {
+        /* UART1 */
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
+};
 static struct imxuart_platform_data uart_pdata = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-static int uart_pins[] = {
+/*
-        MX31_PIN_CTS1__CTS1,
+ * Support for the SMSC9217 on the Debug board.
-        MX31_PIN_RTS1__RTS1,
+ */
-        MX31_PIN_TXD1__TXD1,
-        MX31_PIN_RXD1__RXD1
+static struct smsc911x_platform_config smsc911x_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+};
+static struct resource smsc911x_resources[] = {
+        {
+                .start          = LAN9217_BASE_ADDR,
+                .end            = LAN9217_BASE_ADDR + 0xff,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = EXPIO_INT_ENET,
+                .end            = EXPIO_INT_ENET,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+        .resource       = smsc911x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_config,
+        },
 };
-static inline void mxc_init_imx_uart(void)
+/*
+ * Routines for the CPLD on the debug board. It contains a CPLD handling
+ * LEDs, switches, interrupts for Ethernet.
+ */
+static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
 {
-        mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
+        uint32_t imr_val;
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        uint32_t int_valid;
+        uint32_t expio_irq;
+        imr_val = __raw_readw(CPLD_INT_MASK_REG);
+        int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
+        expio_irq = MXC_EXP_IO_BASE;
+        for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+                if ((int_valid & 1) == 0)
+                        continue;
+                generic_handle_irq(expio_irq);
+        }
+}
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param irq           an expio virtual irq number
+ */
+static void expio_mask_irq(uint32_t irq)
+{
+        uint16_t reg;
+        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
+        /* mask the interrupt */
+        reg = __raw_readw(CPLD_INT_MASK_REG);
+        reg |= 1 << expio;
+        __raw_writew(reg, CPLD_INT_MASK_REG);
+}
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param irq           an expanded io virtual irq number
+ */
+static void expio_ack_irq(uint32_t irq)
+{
+        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
+        /* clear the interrupt status */
+        __raw_writew(1 << expio, CPLD_INT_RESET_REG);
+        __raw_writew(0, CPLD_INT_RESET_REG);
+        /* mask the interrupt */
+        expio_mask_irq(irq);
+}
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param irq           a expio virtual irq number
+ */
+static void expio_unmask_irq(uint32_t irq)
+{
+        uint16_t reg;
+        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
+        /* unmask the interrupt */
+        reg = __raw_readw(CPLD_INT_MASK_REG);
+        reg &= ~(1 << expio);
+        __raw_writew(reg, CPLD_INT_MASK_REG);
+}
+static struct irq_chip expio_irq_chip = {
+        .ack = expio_ack_irq,
+        .mask = expio_mask_irq,
+        .unmask = expio_unmask_irq,
+};
+static int __init mx31pdk_init_expio(void)
+{
+        int i;
+        int ret;
+        /* Check if there's a debug board connected */
+        if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
+            (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
+            (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
+                /* No Debug board found */
+                return -ENODEV;
+        }
+        pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n",
+                __raw_readw(CPLD_CODE_VER_REG));
+        /*
+         * Configure INT line as GPIO input
+         */
+        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
+        if (ret)
+                pr_warning("could not get LAN irq gpio\n");
+        else
+                gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+        /* Disable the interrupts and clear the status */
+        __raw_writew(0, CPLD_INT_MASK_REG);
+        __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
+        __raw_writew(0, CPLD_INT_RESET_REG);
+        __raw_writew(0x1F, CPLD_INT_MASK_REG);
+        for (i = MXC_EXP_IO_BASE;
+             i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
+             i++) {
+                set_irq_chip(i, &expio_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
+        set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler);
+        return 0;
+}
+/*
+ * This structure defines the MX31 memory map.
+ */
+static struct map_desc mx31pdk_io_desc[] __initdata = {
+        {
+                .virtual = SPBA0_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
+                .length = SPBA0_SIZE,
+                .type = MT_DEVICE_NONSHARED,
+        }, {
+                .virtual = CS5_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(CS5_BASE_ADDR),
+                .length = CS5_SIZE,
+                .type = MT_DEVICE,
+        },
+};
+/*
+ * Set up static virtual mappings.
+ */
+static void __init mx31pdk_map_io(void)
+{
+        mx31_map_io();
+        iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
 }
 /*!
@@ -63,7 +237,13 @@ static inline void mxc_init_imx_uart(void)
 */
 static void __init mxc_board_init(void)
 {
-        mxc_init_imx_uart();
+        mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins),
+                                      "mx31pdk");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        if (!mx31pdk_init_expio())
+                platform_device_register(&smsc911x_device);
 }
 static void __init mx31pdk_timer_init(void)
@@ -84,7 +264,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        .phys_io        = AIPS1_BASE_ADDR,
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx31pdk_map_io,
        .init_irq       = mxc_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &mx31pdk_timer,
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c
new file mode 100644
index 000000000000..6d15374414b9
--- /dev/null
+++ b/arch/arm/mach-mx3/mx35pdk.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx35.h>
+#include "devices.h"
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct platform_device *devices[] __initdata = {
+        &mxc_fec_device,
+};
+static struct pad_desc mx35pdk_pads[] = {
+        /* UART1 */
+        MX35_PAD_CTS1__UART1_CTS,
+        MX35_PAD_RTS1__UART1_RTS,
+        MX35_PAD_TXD1__UART1_TXD_MUX,
+        MX35_PAD_RXD1__UART1_RXD_MUX,
+        /* FEC */
+        MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+        MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX35_PAD_FEC_COL__FEC_COL,
+        MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+        MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+        MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX35_PAD_FEC_MDC__FEC_MDC,
+        MX35_PAD_FEC_MDIO__FEC_MDIO,
+        MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+        MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+        MX35_PAD_FEC_CRS__FEC_CRS,
+        MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+        MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+        MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+        MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+        MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+        MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+};
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+}
+static void __init mx35pdk_timer_init(void)
+{
+        mx35_clocks_init();
+}
+struct sys_timer mx35pdk_timer = {
+        .init   = mx35pdk_timer_init,
+};
+MACHINE_START(MX35_3DS, "Freescale MX35PDK")
+        /* Maintainer: Freescale Semiconductor, Inc */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx35_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &mx35pdk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index b5227d837b2f..c6f61a1f06c8 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -28,6 +28,10 @@
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
+#include <linux/delay.h>
+#include <linux/spi/spi.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -37,7 +41,9 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/ipu.h>
 #include <mach/board-pcm037.h>
+#include <mach/mx3fb.h>
 #include <mach/mxc_nand.h>
 #include <mach/mmc.h>
 #ifdef CONFIG_I2C_IMX
@@ -46,6 +52,76 @@
 #include "devices.h"
+static unsigned int pcm037_pins[] = {
+        /* I2C */
+        MX31_PIN_CSPI2_MOSI__SCL,
+        MX31_PIN_CSPI2_MISO__SDA,
+        /* SDHC1 */
+        MX31_PIN_SD1_DATA3__SD1_DATA3,
+        MX31_PIN_SD1_DATA2__SD1_DATA2,
+        MX31_PIN_SD1_DATA1__SD1_DATA1,
+        MX31_PIN_SD1_DATA0__SD1_DATA0,
+        MX31_PIN_SD1_CLK__SD1_CLK,
+        MX31_PIN_SD1_CMD__SD1_CMD,
+        IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
+        IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
+        /* SPI1 */
+        MX31_PIN_CSPI1_MOSI__MOSI,
+        MX31_PIN_CSPI1_MISO__MISO,
+        MX31_PIN_CSPI1_SCLK__SCLK,
+        MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI1_SS0__SS0,
+        MX31_PIN_CSPI1_SS1__SS1,
+        MX31_PIN_CSPI1_SS2__SS2,
+        /* UART1 */
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        /* UART2 */
+        MX31_PIN_TXD2__TXD2,
+        MX31_PIN_RXD2__RXD2,
+        MX31_PIN_CTS2__CTS2,
+        MX31_PIN_RTS2__RTS2,
+        /* UART3 */
+        MX31_PIN_CSPI3_MOSI__RXD3,
+        MX31_PIN_CSPI3_MISO__TXD3,
+        MX31_PIN_CSPI3_SCLK__RTS3,
+        MX31_PIN_CSPI3_SPI_RDY__CTS3,
+        /* LAN9217 irq pin */
+        IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
+        /* Onewire */
+        MX31_PIN_BATT_LINE__OWIRE,
+        /* Framebuffer */
+        MX31_PIN_LD0__LD0,
+        MX31_PIN_LD1__LD1,
+        MX31_PIN_LD2__LD2,
+        MX31_PIN_LD3__LD3,
+        MX31_PIN_LD4__LD4,
+        MX31_PIN_LD5__LD5,
+        MX31_PIN_LD6__LD6,
+        MX31_PIN_LD7__LD7,
+        MX31_PIN_LD8__LD8,
+        MX31_PIN_LD9__LD9,
+        MX31_PIN_LD10__LD10,
+        MX31_PIN_LD11__LD11,
+        MX31_PIN_LD12__LD12,
+        MX31_PIN_LD13__LD13,
+        MX31_PIN_LD14__LD14,
+        MX31_PIN_LD15__LD15,
+        MX31_PIN_LD16__LD16,
+        MX31_PIN_LD17__LD17,
+        MX31_PIN_VSYNC3__VSYNC3,
+        MX31_PIN_HSYNC__HSYNC,
+        MX31_PIN_FPSHIFT__FPSHIFT,
+        MX31_PIN_DRDY0__DRDY0,
+        MX31_PIN_D3_REV__D3_REV,
+        MX31_PIN_CONTRAST__CONTRAST,
+        MX31_PIN_D3_SPL__D3_SPL,
+        MX31_PIN_D3_CLS__D3_CLS,
+        MX31_PIN_LCS0__GPI03_23,
+};
 static struct physmap_flash_data pcm037_flash_data = {
        .width  = 2,
 };
@@ -56,6 +132,54 @@ static struct resource pcm037_flash_resource = {
        .flags  = IORESOURCE_MEM,
 };
+static int usbotg_pins[] = {
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+        MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+        MX31_PIN_USBOTG_STP__USBOTG_STP,
+};
+/* USB OTG HS port */
+static int __init gpio_usbotg_hs_activate(void)
+{
+        int ret = mxc_iomux_setup_multiple_pins(usbotg_pins,
+                                        ARRAY_SIZE(usbotg_pins), "usbotg");
+        if (ret < 0) {
+                printk(KERN_ERR "Cannot set up OTG pins\n");
+                return ret;
+        }
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+        return 0;
+}
+/* OTG config */
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
 static struct platform_device pcm037_flash = {
        .name   = "physmap-flash",
        .id     = 0,
@@ -127,26 +251,8 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = {
 };
 #ifdef CONFIG_I2C_IMX
-static int i2c_1_pins[] = {
-        MX31_PIN_CSPI2_MOSI__SCL,
-        MX31_PIN_CSPI2_MISO__SDA,
-};
-static int pcm037_i2c_1_init(struct device *dev)
-{
-        return mxc_iomux_setup_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins),
-                        "i2c-1");
-}
-static void pcm037_i2c_1_exit(struct device *dev)
-{
-        mxc_iomux_release_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins));
-}
 static struct imxi2c_platform_data pcm037_i2c_1_data = {
        .bitrate = 100000,
-        .init = pcm037_i2c_1_init,
-        .exit = pcm037_i2c_1_exit,
 };
 static struct at24_platform_data board_eeprom = {
@@ -166,48 +272,119 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
 };
 #endif
-static int sdhc1_pins[] = {
+/* Not connected by default */
-        MX31_PIN_SD1_DATA3__SD1_DATA3,
+#ifdef PCM970_SDHC_RW_SWITCH
-        MX31_PIN_SD1_DATA2__SD1_DATA2,
+static int pcm970_sdhc1_get_ro(struct device *dev)
-        MX31_PIN_SD1_DATA1__SD1_DATA1,
+{
-        MX31_PIN_SD1_DATA0__SD1_DATA0,
+        return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
-        MX31_PIN_SD1_CLK__SD1_CLK,
+}
-        MX31_PIN_SD1_CMD__SD1_CMD,
+#endif
-};
+#define SDHC1_GPIO_WP   IOMUX_TO_GPIO(MX31_PIN_SFS6)
+#define SDHC1_GPIO_DET  IOMUX_TO_GPIO(MX31_PIN_SCK6)
-static int pcm970_sdhc1_init(struct device *dev, irq_handler_t h, void *data)
+static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+                void *data)
 {
-        return mxc_iomux_setup_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins),
+        int ret;
-                                "sdhc-1");
+        ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
+        if (ret)
+                return ret;
+        gpio_direction_input(SDHC1_GPIO_DET);
+#ifdef PCM970_SDHC_RW_SWITCH
+        ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
+        if (ret)
+                goto err_gpio_free;
+        gpio_direction_input(SDHC1_GPIO_WP);
+#endif
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
+                        IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                                "sdhc-detect", data);
+        if (ret)
+                goto err_gpio_free_2;
+        return 0;
+err_gpio_free_2:
+#ifdef PCM970_SDHC_RW_SWITCH
+        gpio_free(SDHC1_GPIO_WP);
+err_gpio_free:
+#endif
+        gpio_free(SDHC1_GPIO_DET);
+        return ret;
 }
 static void pcm970_sdhc1_exit(struct device *dev, void *data)
 {
-        mxc_iomux_release_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins));
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
+        gpio_free(SDHC1_GPIO_DET);
+        gpio_free(SDHC1_GPIO_WP);
 }
-/* No card and rw detection at the moment */
 static struct imxmmc_platform_data sdhc_pdata = {
+#ifdef PCM970_SDHC_RW_SWITCH
+        .get_ro = pcm970_sdhc1_get_ro,
+#endif
        .init = pcm970_sdhc1_init,
        .exit = pcm970_sdhc1_exit,
 };
 static struct platform_device *devices[] __initdata = {
        &pcm037_flash,
-        &pcm037_eth,
        &pcm037_sram_device,
 };
-static int uart0_pins[] = {
+static struct ipu_platform_data mx3_ipu_data = {
-        MX31_PIN_CTS1__CTS1,
+        .irq_base = MXC_IPU_IRQ_START,
-        MX31_PIN_RTS1__RTS1,
-        MX31_PIN_TXD1__TXD1,
-        MX31_PIN_RXD1__RXD1
 };
-static int uart2_pins[] = {
+static const struct fb_videomode fb_modedb[] = {
-        MX31_PIN_CSPI3_MOSI__RXD3,
+        {
-        MX31_PIN_CSPI3_MISO__TXD3
+                /* 240x320 @ 60 Hz Sharp */
+                .name           = "Sharp-LQ035Q7DH06-QVGA",
+                .refresh        = 60,
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = 185925,
+                .left_margin    = 9,
+                .right_margin   = 16,
+                .upper_margin   = 7,
+                .lower_margin   = 9,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
+                                  FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        }, {
+                /* 240x320 @ 60 Hz */
+                .name           = "TX090",
+                .refresh        = 60,
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = 38255,
+                .left_margin    = 144,
+                .right_margin   = 0,
+                .upper_margin   = 7,
+                .lower_margin   = 40,
+                .hsync_len      = 96,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+};
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "Sharp-LQ035Q7DH06-QVGA",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
 };
 /*
@@ -215,21 +392,28 @@ static int uart2_pins[] = {
 */
 static void __init mxc_board_init(void)
 {
+        int ret;
+        mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
+                        "pcm037");
        platform_add_devices(devices, ARRAY_SIZE(devices));
-        mxc_iomux_setup_multiple_pins(uart0_pins, ARRAY_SIZE(uart0_pins), "uart-0");
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_iomux_setup_multiple_pins(uart2_pins, ARRAY_SIZE(uart2_pins), "uart-2");
        mxc_register_device(&mxc_uart_device2, &uart_pdata);
-        mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire");
        mxc_register_device(&mxc_w1_master_device, NULL);
        /* LAN9217 IRQ pin */
-        if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
+        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
-                                "pcm037-eth"))
+        if (ret)
+                pr_warning("could not get LAN irq gpio\n");
+        else {
                gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+                platform_device_register(&pcm037_eth);
+        }
 #ifdef CONFIG_I2C_IMX
        i2c_register_board_info(1, pcm037_i2c_devices,
@@ -239,6 +423,10 @@ static void __init mxc_board_init(void)
 #endif
        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
        mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        if (!gpio_usbotg_hs_activate())
+                mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
 static void __init pcm037_timer_init(void)
@@ -255,7 +443,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
        .phys_io        = AIPS1_BASE_ADDR,
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx31_map_io,
        .init_irq       = mxc_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &pcm037_timer,
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c
new file mode 100644
index 000000000000..8d27c324abf2
--- /dev/null
+++ b/arch/arm/mach-mx3/pcm043.c
@@ -0,0 +1,252 @@
+/*
+ *  Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/smc911x.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
+#include <mach/i2c.h>
+#endif
+#include <mach/iomux-mx35.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include "devices.h"
+static const struct fb_videomode fb_modedb[] = {
+        {
+                /* 240x320 @ 60 Hz */
+                .name           = "Sharp-LQ035Q7",
+                .refresh        = 60,
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = 185925,
+                .left_margin    = 9,
+                .right_margin   = 16,
+                .upper_margin   = 7,
+                .lower_margin   = 9,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        }, {
+                /* 240x320 @ 60 Hz */
+                .name           = "TX090",
+                .refresh        = 60,
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = 38255,
+                .left_margin    = 144,
+                .right_margin   = 0,
+                .upper_margin   = 7,
+                .lower_margin   = 40,
+                .hsync_len      = 96,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+};
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "Sharp-LQ035Q7",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+static struct physmap_flash_data pcm043_flash_data = {
+        .width  = 2,
+};
+static struct resource pcm043_flash_resource = {
+        .start  = 0xa0000000,
+        .end    = 0xa1ffffff,
+        .flags  = IORESOURCE_MEM,
+};
+static struct platform_device pcm043_flash = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &pcm043_flash_data,
+        },
+        .resource = &pcm043_flash_resource,
+        .num_resources = 1,
+};
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
+static struct imxi2c_platform_data pcm043_i2c_1_data = {
+        .bitrate = 50000,
+};
+static struct at24_platform_data board_eeprom = {
+        .byte_len = 4096,
+        .page_size = 32,
+        .flags = AT24_FLAG_ADDR16,
+};
+static struct i2c_board_info pcm043_i2c_devices[] = {
+       {
+                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+                .platform_data = &board_eeprom,
+        }, {
+                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                .type = "pcf8563",
+        }
+};
+#endif
+static struct platform_device *devices[] __initdata = {
+        &pcm043_flash,
+        &mxc_fec_device,
+};
+static struct pad_desc pcm043_pads[] = {
+        /* UART1 */
+        MX35_PAD_CTS1__UART1_CTS,
+        MX35_PAD_RTS1__UART1_RTS,
+        MX35_PAD_TXD1__UART1_TXD_MUX,
+        MX35_PAD_RXD1__UART1_RXD_MUX,
+        /* UART2 */
+        MX35_PAD_CTS2__UART2_CTS,
+        MX35_PAD_RTS2__UART2_RTS,
+        MX35_PAD_TXD2__UART2_TXD_MUX,
+        MX35_PAD_RXD2__UART2_RXD_MUX,
+        /* FEC */
+        MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+        MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX35_PAD_FEC_COL__FEC_COL,
+        MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+        MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+        MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX35_PAD_FEC_MDC__FEC_MDC,
+        MX35_PAD_FEC_MDIO__FEC_MDIO,
+        MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+        MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+        MX35_PAD_FEC_CRS__FEC_CRS,
+        MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+        MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+        MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+        MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+        MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+        MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+        /* I2C1 */
+        MX35_PAD_I2C1_CLK__I2C1_SCL,
+        MX35_PAD_I2C1_DAT__I2C1_SDA,
+        /* Display */
+        MX35_PAD_LD0__IPU_DISPB_DAT_0,
+        MX35_PAD_LD1__IPU_DISPB_DAT_1,
+        MX35_PAD_LD2__IPU_DISPB_DAT_2,
+        MX35_PAD_LD3__IPU_DISPB_DAT_3,
+        MX35_PAD_LD4__IPU_DISPB_DAT_4,
+        MX35_PAD_LD5__IPU_DISPB_DAT_5,
+        MX35_PAD_LD6__IPU_DISPB_DAT_6,
+        MX35_PAD_LD7__IPU_DISPB_DAT_7,
+        MX35_PAD_LD8__IPU_DISPB_DAT_8,
+        MX35_PAD_LD9__IPU_DISPB_DAT_9,
+        MX35_PAD_LD10__IPU_DISPB_DAT_10,
+        MX35_PAD_LD11__IPU_DISPB_DAT_11,
+        MX35_PAD_LD12__IPU_DISPB_DAT_12,
+        MX35_PAD_LD13__IPU_DISPB_DAT_13,
+        MX35_PAD_LD14__IPU_DISPB_DAT_14,
+        MX35_PAD_LD15__IPU_DISPB_DAT_15,
+        MX35_PAD_LD16__IPU_DISPB_DAT_16,
+        MX35_PAD_LD17__IPU_DISPB_DAT_17,
+        MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+        MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+        MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+        MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
+        MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
+};
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
+        i2c_register_board_info(0, pcm043_i2c_devices,
+                        ARRAY_SIZE(pcm043_i2c_devices));
+        mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
+#endif
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+}
+static void __init pcm043_timer_init(void)
+{
+        mx35_clocks_init();
+}
+struct sys_timer pcm043_timer = {
+        .init   = pcm043_timer_init,
+};
+MACHINE_START(PCM043, "Phytec Phycore pcm043")
+        /* Maintainer: Pengutronix */
+        .phys_io        = AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx35_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &pcm043_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c
index 5a01e48fd8f1..82b31c4ab11f 100644
--- a/arch/arm/mach-mx3/qong.c
+++ b/arch/arm/mach-mx3/qong.c
@@ -279,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        .phys_io        = AIPS1_BASE_ADDR,
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
-        .map_io         = mxc_map_io,
+        .map_io         = mx31_map_io,
        .init_irq       = mxc_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &qong_timer,
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 79df60c20e70..43da8bb4926b 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -168,7 +168,7 @@ void __init netx_init_irq(void)
 {
        int irq;
-        vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0);
+        vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
        for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
                set_irq_chip(irq, &netx_hif_chip);
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index cd8de89c5fad..55ecc01ea206 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -46,7 +46,6 @@ config MACH_OMAP_H2
 config MACH_OMAP_H3
        bool "TI H3 Support"
        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-#       select GPIOEXPANDER_OMAP
        help
          TI OMAP 1710 H3 board support. Say Y here if you have such
          a board.
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 1bda8f5d7546..6867cd3ad0b4 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -13,6 +13,10 @@ obj-$(CONFIG_OMAP_32K_TIMER)	+= timer32k.o
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
+# DSP
+obj-$(CONFIG_OMAP_MBOX_FWK)     += mailbox_mach.o
+mailbox_mach-objs               := mailbox.o
 led-y := leds.o
 # Specific board support
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index d1ed1365319e..e70fc7c66bbb 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -33,8 +33,11 @@
 #include <mach/common.h>
 #include <mach/dsp_common.h>
 #include <mach/omapfb.h>
+#include <mach/hwa742.h>
 #include <mach/lcd_mipid.h>
 #include <mach/mmc.h>
+#include <mach/usb.h>
+#include <mach/clock.h>
 #define ADS7846_PENDOWN_GPIO    15
@@ -162,6 +165,15 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
        },
 };
+static struct hwa742_platform_data nokia770_hwa742_platform_data = {
+        .te_connected           = 1,
+};
+static void hwa742_dev_init(void)
+{
+        clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
+        omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
+}
 /* assume no Mini-AB port */
@@ -370,6 +382,7 @@ static void __init omap_nokia770_init(void)
        omap_serial_init();
        omap_register_i2c_bus(1, 100, NULL, 0);
        omap_dsp_init();
+        hwa742_dev_init();
        ads7846_dev_init();
        mipid_dev_init();
        omap_usb_init(&nokia770_usb_config);
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 336e51dc6127..436eed22801b 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -776,7 +776,7 @@ int __init omap1_clk_init(void)
        arm_idlect1_mask = ~0;
        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
-                clk_init_one(c->lk.clk);
+                clk_preinit(c->lk.clk);
        cpu_mask = 0;
        if (cpu_is_omap16xx())
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 9774c1f5311e..5218943c91c0 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -53,11 +53,12 @@
 #include <mach/clock.h>
 #include <mach/sram.h>
 #include <mach/tc.h>
-#include <mach/pm.h>
 #include <mach/mux.h>
 #include <mach/dma.h>
 #include <mach/dmtimer.h>
+#include "pm.h"
 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
@@ -101,7 +102,7 @@ static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 * going idle we continue to do idle even if we get
 * a clock tick interrupt . .
 */
-void omap_pm_idle(void)
+void omap1_pm_idle(void)
 {
        extern __u32 arm_idlect1_mask;
        __u32 use_idlect1 = arm_idlect1_mask;
@@ -222,7 +223,7 @@ static void omap_pm_wakeup_setup(void)
 #define EN_APICK        6       /* ARM_IDLECT2 */
 #define DSP_EN          1       /* ARM_RSTCT1 */
-void omap_pm_suspend(void)
+void omap1_pm_suspend(void)
 {
        unsigned long arg0 = 0, arg1 = 0;
@@ -610,7 +611,7 @@ static int omap_pm_enter(suspend_state_t state)
        {
        case PM_SUSPEND_STANDBY:
        case PM_SUSPEND_MEM:
-                omap_pm_suspend();
+                omap1_pm_suspend();
                break;
        default:
                return -EINVAL;
@@ -683,7 +684,7 @@ static int __init omap_pm_init(void)
                return -ENODEV;
        }
-        pm_idle = omap_pm_idle;
+        pm_idle = omap1_pm_idle;
        if (cpu_is_omap730())
                setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/mach-omap1/pm.h
index ce6ee7927537..9ed5e2c1de4d 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/mach-omap1/pm.h
@@ -1,7 +1,7 @@
 /*
- * arch/arm/plat-omap/include/mach/pm.h
+ * arch/arm/mach-omap1/pm.h
 *
- * Header file for OMAP Power Management Routines
+ * Header file for OMAP1 Power Management Routines
 *
 * Author: MontaVista Software, Inc.
 *         support@mvista.com
@@ -31,8 +31,8 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#ifndef __ASM_ARCH_OMAP_PM_H
+#ifndef __ARCH_ARM_MACH_OMAP1_PM_H
-#define __ASM_ARCH_OMAP_PM_H
+#define __ARCH_ARM_MACH_OMAP1_PM_H
 /*
 * ----------------------------------------------------------------------------
@@ -106,8 +106,7 @@
 #if     !defined(CONFIG_ARCH_OMAP730) && \
        !defined(CONFIG_ARCH_OMAP15XX) && \
-        !defined(CONFIG_ARCH_OMAP16XX) && \
+        !defined(CONFIG_ARCH_OMAP16XX)
-        !defined(CONFIG_ARCH_OMAP24XX)
 #warning "Power management for this processor not implemented yet"
 #endif
@@ -115,29 +114,27 @@
 #include <linux/clk.h>
+extern struct kset power_subsys;
 extern void prevent_idle_sleep(void);
 extern void allow_idle_sleep(void);
-extern void omap_pm_idle(void);
+extern void omap1_pm_idle(void);
-extern void omap_pm_suspend(void);
+extern void omap1_pm_suspend(void);
 extern void omap730_cpu_suspend(unsigned short, unsigned short);
 extern void omap1510_cpu_suspend(unsigned short, unsigned short);
 extern void omap1610_cpu_suspend(unsigned short, unsigned short);
-extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
-                                        void __iomem *sdrc_power);
 extern void omap730_idle_loop_suspend(void);
 extern void omap1510_idle_loop_suspend(void);
 extern void omap1610_idle_loop_suspend(void);
-extern void omap24xx_idle_loop_suspend(void);
 extern unsigned int omap730_cpu_suspend_sz;
 extern unsigned int omap1510_cpu_suspend_sz;
 extern unsigned int omap1610_cpu_suspend_sz;
-extern unsigned int omap24xx_cpu_suspend_sz;
 extern unsigned int omap730_idle_loop_suspend_sz;
 extern unsigned int omap1510_idle_loop_suspend_sz;
 extern unsigned int omap1610_idle_loop_suspend_sz;
-extern unsigned int omap24xx_idle_loop_suspend_sz;
 #ifdef CONFIG_OMAP_SERIAL_WAKE
 extern void omap_serial_wake_trigger(int enable);
@@ -170,10 +167,6 @@ extern void omap_serial_wake_trigger(int enable);
 #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
 #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
-#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
-#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
-#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
 /*
 * List of global OMAP registers to preserve.
 * More ones like CP and general purpose register values are preserved
@@ -283,63 +276,5 @@ enum mpui1610_save_state {
 #endif
 };
-enum omap24xx_save_state {
-        OMAP24XX_SLEEP_SAVE_START = 0,
-        OMAP24XX_SLEEP_SAVE_INTC_MIR0,
-        OMAP24XX_SLEEP_SAVE_INTC_MIR1,
-        OMAP24XX_SLEEP_SAVE_INTC_MIR2,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
-        OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
-        OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
-        OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
-        OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
-        OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
-        OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
-        OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
-        OMAP24XX_SLEEP_SAVE_GPIO3_OE,
-        OMAP24XX_SLEEP_SAVE_GPIO4_OE,
-        OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
-        OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
-        OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
-        OMAP24XX_SLEEP_SAVE_SIZE
-};
 #endif /* ASSEMBLER */
 #endif /* __ASM_ARCH_OMAP_PM_H */
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 842090b148f1..f754cee4f3c3 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -26,9 +26,6 @@
 #include <mach/mux.h>
 #include <mach/gpio.h>
 #include <mach/fpga.h>
-#ifdef CONFIG_PM
-#include <mach/pm.h>
-#endif
 static struct clk * uart1_ck;
 static struct clk * uart2_ck;
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index f3eac932092d..22e8568339b0 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -35,7 +35,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
-#include <mach/pm.h>
+#include "pm.h"
                .text
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 64ab386a65c7..a755eb5e2361 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -25,7 +25,7 @@ config ARCH_OMAP3430
        select ARCH_OMAP_OTG
 comment "OMAP Board Type"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
+        depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
 config MACH_OMAP_GENERIC
        bool "Generic OMAP board"
@@ -56,6 +56,10 @@ config MACH_OVERO
        bool "Gumstix Overo board"
        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+config MACH_OMAP3EVM
+        bool "OMAP 3530 EVM board"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
 config MACH_OMAP3_PANDORA
        bool "OMAP3 Pandora"
        depends on ARCH_OMAP3 && ARCH_OMAP34XX
@@ -67,3 +71,11 @@ config MACH_OMAP_3430SDP
 config MACH_NOKIA_RX51
        bool "Nokia RX-51 board"
        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+config MACH_OMAP_ZOOM2
+        bool "OMAP3 Zoom2 board"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+config MACH_OMAP_4430SDP
+        bool "OMAP 4430 SDP board"
+        depends on ARCH_OMAP4
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c49d9bfa3abd..735bae5b0dec 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,12 +3,21 @@
 #
 # Common support
-obj-y := irq.o id.o io.o sdrc.o control.o prcm.o clock.o mux.o \
+obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
-                devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
-                clockdomain.o
+omap-2-3-common                         = irq.o sdrc.o
+prcm-common                             = prcm.o powerdomain.o
+clock-common                            = clock.o clockdomain.o
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common)
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+# SMP support ONLY available for OMAP4
+obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 # Functions loaded to SRAM
 obj-$(CONFIG_ARCH_OMAP2420)             += sram242x.o
 obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
@@ -20,14 +29,21 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sdrc2xxx.o
 # Power Management
 ifeq ($(CONFIG_PM),y)
-obj-y                                   += pm.o
+obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
 obj-$(CONFIG_ARCH_OMAP24XX)             += sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
+obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 endif
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
+iommu-y                                 += iommu2.o
+iommu-$(CONFIG_ARCH_OMAP3)              += omap3-iommu.o
+obj-$(CONFIG_OMAP_IOMMU)                += $(iommu-y)
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
@@ -40,6 +56,8 @@ obj-$(CONFIG_MACH_OMAP_LDP)		+= board-ldp.o \
                                           mmc-twl4030.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o \
                                           mmc-twl4030.o
+obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o \
+                                           mmc-twl4030.o
 obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o \
                                           mmc-twl4030.o
 obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o \
@@ -48,8 +66,17 @@ obj-$(CONFIG_MACH_OMAP_3430SDP)		+= board-3430sdp.o \
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
                                           board-rx51-peripherals.o \
                                           mmc-twl4030.o
+obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom2.o \
+                                           mmc-twl4030.o \
+                                           board-zoom-debugboard.o
+obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 # Platform specific device init code
-ifeq ($(CONFIG_USB_MUSB_SOC),y)
 obj-y                                   += usb-musb.o
-endif
+onenand-$(CONFIG_MTD_ONENAND_OMAP2)     := gpmc-onenand.o
+obj-y                                   += $(onenand-m) $(onenand-y)
+smc91x-$(CONFIG_SMC91X)                 := gpmc-smc91x.o
+obj-y                                   += $(smc91x-m) $(smc91x-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 22143651037e..9c3fdcdf76c3 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -36,14 +36,12 @@
 #include <mach/common.h>
 #include <mach/gpmc.h>
 #include <mach/usb.h>
+#include <mach/gpmc-smc91x.h>
 #include "mmc-twl4030.h"
 #define SDP2430_CS0_BASE        0x04000000
-#define SDP2430_FLASH_CS        0
+#define SECONDARY_LCD_GPIO              147
-#define SDP2430_SMC91X_CS       5
-#define SDP2430_ETHR_GPIO_IRQ           149
 static struct mtd_partition sdp2430_partitions[] = {
        /* bootloader (U-Boot, etc) in first sector */
@@ -99,100 +97,53 @@ static struct platform_device sdp2430_flash_device = {
        .resource       = &sdp2430_flash_resource,
 };
-static struct resource sdp2430_smc91x_resources[] = {
+static struct platform_device sdp2430_lcd_device = {
-        [0] = {
+        .name           = "sdp2430_lcd",
-                .start  = SDP2430_CS0_BASE,
-                .end    = SDP2430_CS0_BASE + SZ_64M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ),
-                .end    = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-static struct platform_device sdp2430_smc91x_device = {
-        .name           = "smc91x",
        .id             = -1,
-        .num_resources  = ARRAY_SIZE(sdp2430_smc91x_resources),
-        .resource       = sdp2430_smc91x_resources,
 };
 static struct platform_device *sdp2430_devices[] __initdata = {
-        &sdp2430_smc91x_device,
        &sdp2430_flash_device,
+        &sdp2430_lcd_device,
 };
-static inline void __init sdp2430_init_smc91x(void)
+static struct omap_lcd_config sdp2430_lcd_config __initdata = {
-{
+        .ctrl_name      = "internal",
-        int eth_cs;
+};
-        unsigned long cs_mem_base;
-        unsigned int rate;
-        struct clk *gpmc_fck;
-        eth_cs = SDP2430_SMC91X_CS;
+#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
-        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+static struct omap_smc91x_platform_data board_smc91x_data = {
-        if (IS_ERR(gpmc_fck)) {
+        .cs             = 5,
-                WARN_ON(1);
+        .gpio_irq       = 149,
-                return;
+        .flags          = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
-        }
+                                IORESOURCE_IRQ_LOWLEVEL,
-        clk_enable(gpmc_fck);
+};
-        rate = clk_get_rate(gpmc_fck);
-        /* Make sure CS1 timings are correct, for 2430 always muxed */
-        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
-        if (rate >= 160000000) {
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
-        } else if (rate >= 130000000) {
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
-        } else { /* rate = 100000000 */
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
-                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
-        }
-        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
+static void __init board_smc91x_init(void)
-                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+{
-                goto out;
+        if (omap_rev() > OMAP3430_REV_ES1_0)
-        }
+                board_smc91x_data.gpio_irq = 6;
+        else
+                board_smc91x_data.gpio_irq = 29;
-        sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
+        gpmc_smc91x_init(&board_smc91x_data);
-        sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f;
+}
-        udelay(100);
-        if (gpio_request(SDP2430_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
+#else
-                printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
-                        SDP2430_ETHR_GPIO_IRQ);
-                gpmc_cs_free(eth_cs);
-                goto out;
-        }
-        gpio_direction_input(SDP2430_ETHR_GPIO_IRQ);
-out:
+static inline void board_smc91x_init(void)
-        clk_disable(gpmc_fck);
+{
-        clk_put(gpmc_fck);
 }
+#endif
 static void __init omap_2430sdp_init_irq(void)
 {
        omap2_init_common_hw(NULL);
        omap_init_irq();
        omap_gpio_init();
-        sdp2430_init_smc91x();
 }
 static struct omap_uart_config sdp2430_uart_config __initdata = {
@@ -201,6 +152,7 @@ static struct omap_uart_config sdp2430_uart_config __initdata = {
 static struct omap_board_config_kernel sdp2430_config[] = {
        {OMAP_TAG_UART, &sdp2430_uart_config},
+        {OMAP_TAG_LCD, &sdp2430_lcd_config},
 };
@@ -248,6 +200,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
 static void __init omap_2430sdp_init(void)
 {
+        int ret;
        omap2430_i2c_init();
        platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
@@ -256,6 +210,12 @@ static void __init omap_2430sdp_init(void)
        omap_serial_init();
        twl4030_mmc_init(mmc);
        usb_musb_init();
+        board_smc91x_init();
+        /* Turn off secondary LCD backlight */
+        ret = gpio_request(SECONDARY_LCD_GPIO, "Secondary LCD backlight");
+        if (ret == 0)
+                gpio_direction_output(SECONDARY_LCD_GPIO, 0);
 }
 static void __init omap_2430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index ed9274972122..496a90e4ea7a 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -39,15 +39,13 @@
 #include <mach/control.h>
 #include <mach/keypad.h>
+#include <mach/gpmc-smc91x.h>
+#include "sdram-qimonda-hyb18m512160af-6.h"
 #include "mmc-twl4030.h"
 #define CONFIG_DISABLE_HFCLK 1
-#define SDP3430_ETHR_GPIO_IRQ_SDPV1     29
-#define SDP3430_ETHR_GPIO_IRQ_SDPV2     6
-#define SDP3430_SMC91X_CS               3
 #define SDP3430_TS_GPIO_IRQ_SDPV1       3
 #define SDP3430_TS_GPIO_IRQ_SDPV2       2
@@ -56,24 +54,6 @@
 #define TWL4030_MSECURE_GPIO 22
-static struct resource sdp3430_smc91x_resources[] = {
-        [0] = {
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0,
-                .end    = 0,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-static struct platform_device sdp3430_smc91x_device = {
-        .name           = "smc91x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(sdp3430_smc91x_resources),
-        .resource       = sdp3430_smc91x_resources,
-};
 static int sdp3430_keymap[] = {
        KEY(0, 0, KEY_LEFT),
        KEY(0, 1, KEY_RIGHT),
@@ -184,48 +164,14 @@ static struct regulator_consumer_supply sdp3430_vdvi_supply = {
 };
 static struct platform_device *sdp3430_devices[] __initdata = {
-        &sdp3430_smc91x_device,
        &sdp3430_lcd_device,
 };
-static inline void __init sdp3430_init_smc91x(void)
-{
-        int eth_cs;
-        unsigned long cs_mem_base;
-        int eth_gpio = 0;
-        eth_cs = SDP3430_SMC91X_CS;
-        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
-                return;
-        }
-        sdp3430_smc91x_resources[0].start = cs_mem_base + 0x300;
-        sdp3430_smc91x_resources[0].end = cs_mem_base + 0x30f;
-        udelay(100);
-        if (omap_rev() > OMAP3430_REV_ES1_0)
-                eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV2;
-        else
-                eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV1;
-        sdp3430_smc91x_resources[1].start = gpio_to_irq(eth_gpio);
-        if (gpio_request(eth_gpio, "SMC91x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
-                        eth_gpio);
-                return;
-        }
-        gpio_direction_input(eth_gpio);
-}
 static void __init omap_3430sdp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(hyb18m512160af6_sdrc_params);
        omap_init_irq();
        omap_gpio_init();
-        sdp3430_init_smc91x();
 }
 static struct omap_uart_config sdp3430_uart_config __initdata = {
@@ -506,6 +452,32 @@ static int __init omap3430_i2c_init(void)
        return 0;
 }
+#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+static struct omap_smc91x_platform_data board_smc91x_data = {
+        .cs             = 3,
+        .flags          = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
+                                IORESOURCE_IRQ_LOWLEVEL,
+};
+static void __init board_smc91x_init(void)
+{
+        if (omap_rev() > OMAP3430_REV_ES1_0)
+                board_smc91x_data.gpio_irq = 6;
+        else
+                board_smc91x_data.gpio_irq = 29;
+        gpmc_smc91x_init(&board_smc91x_data);
+}
+#else
+static inline void board_smc91x_init(void)
+{
+}
+#endif
 static void __init omap_3430sdp_init(void)
 {
        omap3430_i2c_init();
@@ -522,6 +494,7 @@ static void __init omap_3430sdp_init(void)
        ads7846_dev_init();
        omap_serial_init();
        usb_musb_init();
+        board_smc91x_init();
 }
 static void __init omap_3430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
new file mode 100644
index 000000000000..57e477bd89c6
--- /dev/null
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -0,0 +1,94 @@
+/*
+ * Board support file for OMAP4430 SDP.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Based on mach-omap2/board-3430sdp.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/board.h>
+#include <mach/common.h>
+#include <mach/control.h>
+#include <mach/timer-gp.h>
+#include <asm/hardware/gic.h>
+static struct platform_device sdp4430_lcd_device = {
+        .name           = "sdp4430_lcd",
+        .id             = -1,
+};
+static struct platform_device *sdp4430_devices[] __initdata = {
+        &sdp4430_lcd_device,
+};
+static struct omap_uart_config sdp4430_uart_config __initdata = {
+        .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2),
+};
+static struct omap_lcd_config sdp4430_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
+static struct omap_board_config_kernel sdp4430_config[] __initdata = {
+        { OMAP_TAG_UART,        &sdp4430_uart_config },
+        { OMAP_TAG_LCD,         &sdp4430_lcd_config },
+};
+static void __init gic_init_irq(void)
+{
+        gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
+        gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+}
+static void __init omap_4430sdp_init_irq(void)
+{
+        omap2_init_common_hw(NULL);
+#ifdef CONFIG_OMAP_32K_TIMER
+        omap2_gp_clockevent_set_gptimer(1);
+#endif
+        gic_init_irq();
+        omap_gpio_init();
+}
+static void __init omap_4430sdp_init(void)
+{
+        platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
+        omap_board_config = sdp4430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp4430_config);
+        omap_serial_init();
+}
+static void __init omap_4430sdp_map_io(void)
+{
+        omap2_set_globals_443x();
+        omap2_map_common_io();
+}
+MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
+        /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = omap_4430sdp_map_io,
+        .init_irq       = omap_4430sdp_init_irq,
+        .init_machine   = omap_4430sdp_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index da57b0fcda14..d8bc0a7dcb8d 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -16,11 +16,13 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/input.h>
+#include <linux/gpio_keys.h>
 #include <linux/workqueue.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/regulator/machine.h>
 #include <linux/i2c/twl4030.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
@@ -39,6 +41,7 @@
 #include <asm/delay.h>
 #include <mach/control.h>
 #include <mach/usb.h>
+#include <mach/keypad.h>
 #include "mmc-twl4030.h"
@@ -77,8 +80,163 @@ static struct platform_device ldp_smsc911x_device = {
        },
 };
-static struct platform_device *ldp_devices[] __initdata = {
+static int ldp_twl4030_keymap[] = {
-        &ldp_smsc911x_device,
+        KEY(0, 0, KEY_1),
+        KEY(1, 0, KEY_2),
+        KEY(2, 0, KEY_3),
+        KEY(0, 1, KEY_4),
+        KEY(1, 1, KEY_5),
+        KEY(2, 1, KEY_6),
+        KEY(3, 1, KEY_F5),
+        KEY(0, 2, KEY_7),
+        KEY(1, 2, KEY_8),
+        KEY(2, 2, KEY_9),
+        KEY(3, 2, KEY_F6),
+        KEY(0, 3, KEY_F7),
+        KEY(1, 3, KEY_0),
+        KEY(2, 3, KEY_F8),
+        PERSISTENT_KEY(4, 5),
+        KEY(4, 4, KEY_VOLUMEUP),
+        KEY(5, 5, KEY_VOLUMEDOWN),
+        0
+};
+static struct twl4030_keypad_data ldp_kp_twl4030_data = {
+        .rows           = 6,
+        .cols           = 6,
+        .keymap         = ldp_twl4030_keymap,
+        .keymapsize     = ARRAY_SIZE(ldp_twl4030_keymap),
+        .rep            = 1,
+};
+static struct gpio_keys_button ldp_gpio_keys_buttons[] = {
+        [0] = {
+                .code                   = KEY_ENTER,
+                .gpio                   = 101,
+                .desc                   = "enter sw",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [1] = {
+                .code                   = KEY_F1,
+                .gpio                   = 102,
+                .desc                   = "func 1",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [2] = {
+                .code                   = KEY_F2,
+                .gpio                   = 103,
+                .desc                   = "func 2",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [3] = {
+                .code                   = KEY_F3,
+                .gpio                   = 104,
+                .desc                   = "func 3",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [4] = {
+                .code                   = KEY_F4,
+                .gpio                   = 105,
+                .desc                   = "func 4",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [5] = {
+                .code                   = KEY_LEFT,
+                .gpio                   = 106,
+                .desc                   = "left sw",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [6] = {
+                .code                   = KEY_RIGHT,
+                .gpio                   = 107,
+                .desc                   = "right sw",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [7] = {
+                .code                   = KEY_UP,
+                .gpio                   = 108,
+                .desc                   = "up sw",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+        [8] = {
+                .code                   = KEY_DOWN,
+                .gpio                   = 109,
+                .desc                   = "down sw",
+                .active_low             = 1,
+                .debounce_interval      = 30,
+        },
+};
+static struct gpio_keys_platform_data ldp_gpio_keys = {
+        .buttons                = ldp_gpio_keys_buttons,
+        .nbuttons               = ARRAY_SIZE(ldp_gpio_keys_buttons),
+        .rep                    = 1,
+};
+static struct platform_device ldp_gpio_keys_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ldp_gpio_keys,
+        },
+};
+static int ts_gpio;
+/**
+ * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
+ *
+ * @return - void. If request gpio fails then Flag KERN_ERR.
+ */
+static void ads7846_dev_init(void)
+{
+        if (gpio_request(ts_gpio, "ads7846 irq") < 0) {
+                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+                return;
+        }
+        gpio_direction_input(ts_gpio);
+        omap_set_gpio_debounce(ts_gpio, 1);
+        omap_set_gpio_debounce_time(ts_gpio, 0xa);
+}
+static int ads7846_get_pendown_state(void)
+{
+        return !gpio_get_value(ts_gpio);
+}
+static struct ads7846_platform_data tsc2046_config __initdata = {
+        .get_pendown_state      = ads7846_get_pendown_state,
+        .keep_vref_on           = 1,
+};
+static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+static struct spi_board_info ldp_spi_board_info[] __initdata = {
+        [0] = {
+                /*
+                 * TSC2046 operates at a max freqency of 2MHz, so
+                 * operate slightly below at 1.5MHz
+                 */
+                .modalias               = "ads7846",
+                .bus_num                = 1,
+                .chip_select            = 0,
+                .max_speed_hz           = 1500000,
+                .controller_data        = &tsc2046_mcspi_config,
+                .irq                    = 0,
+                .platform_data          = &tsc2046_config,
+        },
 };
 static inline void __init ldp_init_smsc911x(void)
@@ -122,8 +280,22 @@ static struct omap_uart_config ldp_uart_config __initdata = {
        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
 };
+static struct platform_device ldp_lcd_device = {
+        .name           = "ldp_lcd",
+        .id             = -1,
+};
+static struct omap_lcd_config ldp_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
 static struct omap_board_config_kernel ldp_config[] __initdata = {
        { OMAP_TAG_UART,        &ldp_uart_config },
+        { OMAP_TAG_LCD,         &ldp_lcd_config },
+};
+static struct twl4030_usb_data ldp_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
 };
 static struct twl4030_gpio_platform_data ldp_gpio_data = {
@@ -132,12 +304,39 @@ static struct twl4030_gpio_platform_data ldp_gpio_data = {
        .irq_end        = TWL4030_GPIO_IRQ_END,
 };
+static struct twl4030_madc_platform_data ldp_madc_data = {
+        .irq_line       = 1,
+};
+static struct regulator_consumer_supply ldp_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data ldp_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &ldp_vmmc1_supply,
+};
 static struct twl4030_platform_data ldp_twldata = {
        .irq_base       = TWL4030_IRQ_BASE,
        .irq_end        = TWL4030_IRQ_END,
        /* platform_data for children goes here */
+        .madc           = &ldp_madc_data,
+        .usb            = &ldp_usb_data,
+        .vmmc1          = &ldp_vmmc1,
        .gpio           = &ldp_gpio_data,
+        .keypad         = &ldp_kp_twl4030_data,
 };
 static struct i2c_board_info __initdata ldp_i2c_boardinfo[] = {
@@ -168,15 +367,29 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
        {}      /* Terminator */
 };
+static struct platform_device *ldp_devices[] __initdata = {
+        &ldp_smsc911x_device,
+        &ldp_lcd_device,
+        &ldp_gpio_keys_device,
+};
 static void __init omap_ldp_init(void)
 {
        omap_i2c_init();
        platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
        omap_board_config = ldp_config;
        omap_board_config_size = ARRAY_SIZE(ldp_config);
+        ts_gpio = 54;
+        ldp_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
+        spi_register_board_info(ldp_spi_board_info,
+                                ARRAY_SIZE(ldp_spi_board_info));
+        ads7846_dev_init();
        omap_serial_init();
-        twl4030_mmc_init(mmc);
        usb_musb_init();
+        twl4030_mmc_init(mmc);
+        /* link regulators to MMC adapters */
+        ldp_vmmc1_supply.dev = mmc[0].dev;
 }
 static void __init omap_ldp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 3a7a29d1f9a7..991ac9c38032 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/regulator/machine.h>
 #include <linux/i2c/twl4030.h>
 #include <mach/hardware.h>
@@ -105,6 +106,8 @@ static struct platform_device omap3beagle_nand_device = {
        .resource       = &omap3beagle_nand_resource,
 };
+#include "sdram-micron-mt46h32m32lf-6.h"
 static struct omap_uart_config omap3_beagle_uart_config __initdata = {
        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
 };
@@ -118,6 +121,23 @@ static struct twl4030_hsmmc_info mmc[] = {
        {}      /* Terminator */
 };
+static struct platform_device omap3_beagle_lcd_device = {
+        .name           = "omap3beagle_lcd",
+        .id             = -1,
+};
+static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
+static struct regulator_consumer_supply beagle_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+static struct regulator_consumer_supply beagle_vsim_supply = {
+        .supply                 = "vmmc_aux",
+};
 static struct gpio_led gpio_leds[];
 static int beagle_twl_gpio_setup(struct device *dev,
@@ -128,6 +148,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
        mmc[0].gpio_cd = gpio + 0;
        twl4030_mmc_init(mmc);
+        /* link regulators to MMC adapters */
+        beagle_vmmc1_supply.dev = mmc[0].dev;
+        beagle_vsim_supply.dev = mmc[0].dev;
        /* REVISIT: need ehci-omap hooks for external VBUS
         * power switch and overcurrent detect
         */
@@ -156,12 +180,85 @@ static struct twl4030_gpio_platform_data beagle_gpio_data = {
        .setup          = beagle_twl_gpio_setup,
 };
+static struct regulator_consumer_supply beagle_vdac_supply = {
+        .supply         = "vdac",
+        .dev            = &omap3_beagle_lcd_device.dev,
+};
+static struct regulator_consumer_supply beagle_vdvi_supply = {
+        .supply         = "vdvi",
+        .dev            = &omap3_beagle_lcd_device.dev,
+};
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data beagle_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &beagle_vmmc1_supply,
+};
+/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+static struct regulator_init_data beagle_vsim = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 3000000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &beagle_vsim_supply,
+};
+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+static struct regulator_init_data beagle_vdac = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &beagle_vdac_supply,
+};
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data beagle_vpll2 = {
+        .constraints = {
+                .name                   = "VDVI",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &beagle_vdvi_supply,
+};
 static struct twl4030_platform_data beagle_twldata = {
        .irq_base       = TWL4030_IRQ_BASE,
        .irq_end        = TWL4030_IRQ_END,
        /* platform_data for children goes here */
        .gpio           = &beagle_gpio_data,
+        .vmmc1          = &beagle_vmmc1,
+        .vsim           = &beagle_vsim,
+        .vdac           = &beagle_vdac,
+        .vpll2          = &beagle_vpll2,
 };
 static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = {
@@ -185,7 +282,7 @@ static int __init omap3_beagle_i2c_init(void)
 static void __init omap3_beagle_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
        omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
        omap2_gp_clockevent_set_gptimer(12);
@@ -193,15 +290,6 @@ static void __init omap3_beagle_init_irq(void)
        omap_gpio_init();
 }
-static struct platform_device omap3_beagle_lcd_device = {
-        .name           = "omap3beagle_lcd",
-        .id             = -1,
-};
-static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
-        .ctrl_name      = "internal",
-};
 static struct gpio_led gpio_leds[] = {
        {
                .name                   = "beagleboard::usr0",
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
new file mode 100644
index 000000000000..d3cc145814d0
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -0,0 +1,329 @@
+/*
+ * linux/arch/arm/mach-omap2/board-omap3evm.c
+ *
+ * Copyright (C) 2008 Texas Instruments
+ *
+ * Modified from mach-omap2/board-3430sdp.c
+ *
+ * Initial code: Syed Mohammed Khasim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+#include <linux/i2c/twl4030.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/board.h>
+#include <mach/mux.h>
+#include <mach/usb.h>
+#include <mach/common.h>
+#include <mach/mcspi.h>
+#include <mach/keypad.h>
+#include "sdram-micron-mt46h32m32lf-6.h"
+#include "mmc-twl4030.h"
+#define OMAP3_EVM_TS_GPIO       175
+#define OMAP3EVM_ETHR_START     0x2c000000
+#define OMAP3EVM_ETHR_SIZE      1024
+#define OMAP3EVM_ETHR_GPIO_IRQ  176
+#define OMAP3EVM_SMC911X_CS     5
+static struct resource omap3evm_smc911x_resources[] = {
+        [0] =   {
+                .start  = OMAP3EVM_ETHR_START,
+                .end    = (OMAP3EVM_ETHR_START + OMAP3EVM_ETHR_SIZE - 1),
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] =   {
+                .start  = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ),
+                .end    = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device omap3evm_smc911x_device = {
+        .name           = "smc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(omap3evm_smc911x_resources),
+        .resource       = &omap3evm_smc911x_resources[0],
+};
+static inline void __init omap3evm_init_smc911x(void)
+{
+        int eth_cs;
+        struct clk *l3ck;
+        unsigned int rate;
+        eth_cs = OMAP3EVM_SMC911X_CS;
+        l3ck = clk_get(NULL, "l3_ck");
+        if (IS_ERR(l3ck))
+                rate = 100000000;
+        else
+                rate = clk_get_rate(l3ck);
+        if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMC911x irq") < 0) {
+                printk(KERN_ERR "Failed to request GPIO%d for smc911x IRQ\n",
+                        OMAP3EVM_ETHR_GPIO_IRQ);
+                return;
+        }
+        gpio_direction_input(OMAP3EVM_ETHR_GPIO_IRQ);
+}
+static struct omap_uart_config omap3_evm_uart_config __initdata = {
+        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
+};
+static struct twl4030_hsmmc_info mmc[] = {
+        {
+                .mmc            = 1,
+                .wires          = 4,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = 63,
+        },
+        {}      /* Terminator */
+};
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "omap3evm::ledb",
+                /* normally not visible (board underside) */
+                .default_trigger        = "default-on",
+                .gpio                   = -EINVAL,      /* gets replaced */
+                .active_low             = true,
+        },
+};
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+static int omap3evm_twl_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
+{
+        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+        omap_cfg_reg(L8_34XX_GPIO63);
+        mmc[0].gpio_cd = gpio + 0;
+        twl4030_mmc_init(mmc);
+        /*
+         * Most GPIOs are for USB OTG.  Some are mostly sent to
+         * the P2 connector; notably LEDA for the LCD backlight.
+         */
+        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
+        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+        platform_device_register(&leds_gpio);
+        return 0;
+}
+static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .setup          = omap3evm_twl_gpio_setup,
+};
+static struct twl4030_usb_data omap3evm_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+static int omap3evm_keymap[] = {
+        KEY(0, 0, KEY_LEFT),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_A),
+        KEY(0, 3, KEY_B),
+        KEY(1, 0, KEY_DOWN),
+        KEY(1, 1, KEY_UP),
+        KEY(1, 2, KEY_E),
+        KEY(1, 3, KEY_F),
+        KEY(2, 0, KEY_ENTER),
+        KEY(2, 1, KEY_I),
+        KEY(2, 2, KEY_J),
+        KEY(2, 3, KEY_K),
+        KEY(3, 0, KEY_M),
+        KEY(3, 1, KEY_N),
+        KEY(3, 2, KEY_O),
+        KEY(3, 3, KEY_P)
+};
+static struct twl4030_keypad_data omap3evm_kp_data = {
+        .rows           = 4,
+        .cols           = 4,
+        .keymap         = omap3evm_keymap,
+        .keymapsize     = ARRAY_SIZE(omap3evm_keymap),
+        .rep            = 1,
+};
+static struct twl4030_madc_platform_data omap3evm_madc_data = {
+        .irq_line       = 1,
+};
+static struct twl4030_platform_data omap3evm_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+        /* platform_data for children goes here */
+        .keypad         = &omap3evm_kp_data,
+        .madc           = &omap3evm_madc_data,
+        .usb            = &omap3evm_usb_data,
+        .gpio           = &omap3evm_gpio_data,
+};
+static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags = I2C_CLIENT_WAKE,
+                .irq = INT_34XX_SYS_NIRQ,
+                .platform_data = &omap3evm_twldata,
+        },
+};
+static int __init omap3_evm_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, omap3evm_i2c_boardinfo,
+                        ARRAY_SIZE(omap3evm_i2c_boardinfo));
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        omap_register_i2c_bus(3, 400, NULL, 0);
+        return 0;
+}
+static struct platform_device omap3_evm_lcd_device = {
+        .name           = "omap3evm_lcd",
+        .id             = -1,
+};
+static struct omap_lcd_config omap3_evm_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
+static void ads7846_dev_init(void)
+{
+        if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0)
+                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
+        gpio_direction_input(OMAP3_EVM_TS_GPIO);
+        omap_set_gpio_debounce(OMAP3_EVM_TS_GPIO, 1);
+        omap_set_gpio_debounce_time(OMAP3_EVM_TS_GPIO, 0xa);
+}
+static int ads7846_get_pendown_state(void)
+{
+        return !gpio_get_value(OMAP3_EVM_TS_GPIO);
+}
+struct ads7846_platform_data ads7846_config = {
+        .x_max                  = 0x0fff,
+        .y_max                  = 0x0fff,
+        .x_plate_ohms           = 180,
+        .pressure_max           = 255,
+        .debounce_max           = 10,
+        .debounce_tol           = 3,
+        .debounce_rep           = 1,
+        .get_pendown_state      = ads7846_get_pendown_state,
+        .keep_vref_on           = 1,
+        .settle_delay_usecs     = 150,
+};
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+struct spi_board_info omap3evm_spi_board_info[] = {
+        [0] = {
+                .modalias               = "ads7846",
+                .bus_num                = 1,
+                .chip_select            = 0,
+                .max_speed_hz           = 1500000,
+                .controller_data        = &ads7846_mcspi_config,
+                .irq                    = OMAP_GPIO_IRQ(OMAP3_EVM_TS_GPIO),
+                .platform_data          = &ads7846_config,
+        },
+};
+static void __init omap3_evm_init_irq(void)
+{
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap_init_irq();
+        omap_gpio_init();
+        omap3evm_init_smc911x();
+}
+static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+        { OMAP_TAG_UART,        &omap3_evm_uart_config },
+        { OMAP_TAG_LCD,         &omap3_evm_lcd_config },
+};
+static struct platform_device *omap3_evm_devices[] __initdata = {
+        &omap3_evm_lcd_device,
+        &omap3evm_smc911x_device,
+};
+static void __init omap3_evm_init(void)
+{
+        omap3_evm_i2c_init();
+        platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
+        omap_board_config = omap3_evm_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
+        spi_register_board_info(omap3evm_spi_board_info,
+                                ARRAY_SIZE(omap3evm_spi_board_info));
+        omap_serial_init();
+        usb_musb_init();
+        ads7846_dev_init();
+}
+static void __init omap3_evm_map_io(void)
+{
+        omap2_set_globals_343x();
+        omap2_map_common_io();
+}
+MACHINE_START(OMAP3EVM, "OMAP3 EVM")
+        /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_evm_map_io,
+        .init_irq       = omap3_evm_init_irq,
+        .init_machine   = omap3_evm_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 402f09c6cf10..e32aa23ce962 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -23,7 +23,11 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/regulator/machine.h>
 #include <linux/i2c/twl4030.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -35,11 +39,154 @@
 #include <mach/hardware.h>
 #include <mach/mcspi.h>
 #include <mach/usb.h>
+#include <mach/keypad.h>
+#include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 #define OMAP3_PANDORA_TS_GPIO           94
+/* hardware debounce: (value + 1) * 31us */
+#define GPIO_DEBOUNCE_TIME              127
+static struct gpio_led pandora_gpio_leds[] = {
+        {
+                .name                   = "pandora::sd1",
+                .default_trigger        = "mmc0",
+                .gpio                   = 128,
+        }, {
+                .name                   = "pandora::sd2",
+                .default_trigger        = "mmc1",
+                .gpio                   = 129,
+        }, {
+                .name                   = "pandora::bluetooth",
+                .gpio                   = 158,
+        }, {
+                .name                   = "pandora::wifi",
+                .gpio                   = 159,
+        },
+};
+static struct gpio_led_platform_data pandora_gpio_led_data = {
+        .leds           = pandora_gpio_leds,
+        .num_leds       = ARRAY_SIZE(pandora_gpio_leds),
+};
+static struct platform_device pandora_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &pandora_gpio_led_data,
+        },
+};
+#define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr) \
+{                                                               \
+        .gpio           = gpio_num,                             \
+        .type           = ev_type,                              \
+        .code           = ev_code,                              \
+        .active_low     = act_low,                              \
+        .desc           = "btn " descr,                         \
+}
+#define GPIO_BUTTON_LOW(gpio_num, event_code, description)      \
+        GPIO_BUTTON(gpio_num, EV_KEY, event_code, 1, description)
+static struct gpio_keys_button pandora_gpio_keys[] = {
+        GPIO_BUTTON_LOW(110,    KEY_UP,         "up"),
+        GPIO_BUTTON_LOW(103,    KEY_DOWN,       "down"),
+        GPIO_BUTTON_LOW(96,     KEY_LEFT,       "left"),
+        GPIO_BUTTON_LOW(98,     KEY_RIGHT,      "right"),
+        GPIO_BUTTON_LOW(111,    BTN_A,          "a"),
+        GPIO_BUTTON_LOW(106,    BTN_B,          "b"),
+        GPIO_BUTTON_LOW(109,    BTN_X,          "x"),
+        GPIO_BUTTON_LOW(101,    BTN_Y,          "y"),
+        GPIO_BUTTON_LOW(102,    BTN_TL,         "l"),
+        GPIO_BUTTON_LOW(97,     BTN_TL2,        "l2"),
+        GPIO_BUTTON_LOW(105,    BTN_TR,         "r"),
+        GPIO_BUTTON_LOW(107,    BTN_TR2,        "r2"),
+        GPIO_BUTTON_LOW(104,    KEY_LEFTCTRL,   "ctrl"),
+        GPIO_BUTTON_LOW(99,     KEY_MENU,       "menu"),
+        GPIO_BUTTON_LOW(176,    KEY_COFFEE,     "hold"),
+        GPIO_BUTTON(100, EV_KEY, KEY_LEFTALT, 0, "alt"),
+        GPIO_BUTTON(108, EV_SW, SW_LID, 1, "lid"),
+};
+static struct gpio_keys_platform_data pandora_gpio_key_info = {
+        .buttons        = pandora_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(pandora_gpio_keys),
+};
+static struct platform_device pandora_keys_gpio = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &pandora_gpio_key_info,
+        },
+};
+static void __init pandora_keys_gpio_init(void)
+{
+        /* set debounce time for GPIO banks 4 and 6 */
+        omap_set_gpio_debounce_time(32 * 3, GPIO_DEBOUNCE_TIME);
+        omap_set_gpio_debounce_time(32 * 5, GPIO_DEBOUNCE_TIME);
+}
+static int pandora_keypad_map[] = {
+        /* col, row, code */
+        KEY(0, 0, KEY_9),
+        KEY(0, 1, KEY_0),
+        KEY(0, 2, KEY_BACKSPACE),
+        KEY(0, 3, KEY_O),
+        KEY(0, 4, KEY_P),
+        KEY(0, 5, KEY_K),
+        KEY(0, 6, KEY_L),
+        KEY(0, 7, KEY_ENTER),
+        KEY(1, 0, KEY_8),
+        KEY(1, 1, KEY_7),
+        KEY(1, 2, KEY_6),
+        KEY(1, 3, KEY_5),
+        KEY(1, 4, KEY_4),
+        KEY(1, 5, KEY_3),
+        KEY(1, 6, KEY_2),
+        KEY(1, 7, KEY_1),
+        KEY(2, 0, KEY_I),
+        KEY(2, 1, KEY_U),
+        KEY(2, 2, KEY_Y),
+        KEY(2, 3, KEY_T),
+        KEY(2, 4, KEY_R),
+        KEY(2, 5, KEY_E),
+        KEY(2, 6, KEY_W),
+        KEY(2, 7, KEY_Q),
+        KEY(3, 0, KEY_J),
+        KEY(3, 1, KEY_H),
+        KEY(3, 2, KEY_G),
+        KEY(3, 3, KEY_F),
+        KEY(3, 4, KEY_D),
+        KEY(3, 5, KEY_S),
+        KEY(3, 6, KEY_A),
+        KEY(3, 7, KEY_LEFTSHIFT),
+        KEY(4, 0, KEY_N),
+        KEY(4, 1, KEY_B),
+        KEY(4, 2, KEY_V),
+        KEY(4, 3, KEY_C),
+        KEY(4, 4, KEY_X),
+        KEY(4, 5, KEY_Z),
+        KEY(4, 6, KEY_DOT),
+        KEY(4, 7, KEY_COMMA),
+        KEY(5, 0, KEY_M),
+        KEY(5, 1, KEY_SPACE),
+        KEY(5, 2, KEY_FN),
+};
+static struct twl4030_keypad_data pandora_kp_data = {
+        .rows           = 8,
+        .cols           = 6,
+        .keymap         = pandora_keypad_map,
+        .keymapsize     = ARRAY_SIZE(pandora_keypad_map),
+        .rep            = 1,
+};
 static struct twl4030_hsmmc_info omap3pandora_mmc[] = {
        {
                .mmc            = 1,
@@ -69,6 +216,14 @@ static struct omap_uart_config omap3pandora_uart_config __initdata = {
        .enabled_uarts  = (1 << 2), /* UART3 */
 };
+static struct regulator_consumer_supply pandora_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+static struct regulator_consumer_supply pandora_vmmc2_supply = {
+        .supply                 = "vmmc",
+};
 static int omap3pandora_twl_gpio_setup(struct device *dev,
                unsigned gpio, unsigned ngpio)
 {
@@ -77,6 +232,10 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
        omap3pandora_mmc[1].gpio_cd = gpio + 1;
        twl4030_mmc_init(omap3pandora_mmc);
+        /* link regulators to MMC adapters */
+        pandora_vmmc1_supply.dev = omap3pandora_mmc[0].dev;
+        pandora_vmmc2_supply.dev = omap3pandora_mmc[1].dev;
        return 0;
 }
@@ -87,6 +246,36 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
        .setup          = omap3pandora_twl_gpio_setup,
 };
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data pandora_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &pandora_vmmc1_supply,
+};
+/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
+static struct regulator_init_data pandora_vmmc2 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &pandora_vmmc2_supply,
+};
 static struct twl4030_usb_data omap3pandora_usb_data = {
        .usb_mode       = T2_USB_MODE_ULPI,
 };
@@ -96,6 +285,9 @@ static struct twl4030_platform_data omap3pandora_twldata = {
        .irq_end        = TWL4030_IRQ_END,
        .gpio           = &omap3pandora_gpio_data,
        .usb            = &omap3pandora_usb_data,
+        .vmmc1          = &pandora_vmmc1,
+        .vmmc2          = &pandora_vmmc2,
+        .keypad         = &pandora_kp_data,
 };
 static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
@@ -118,7 +310,7 @@ static int __init omap3pandora_i2c_init(void)
 static void __init omap3pandora_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
        omap_init_irq();
        omap_gpio_init();
 }
@@ -188,6 +380,8 @@ static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
 static struct platform_device *omap3pandora_devices[] __initdata = {
        &omap3pandora_lcd_device,
+        &pandora_leds_gpio,
+        &pandora_keys_gpio,
 };
 static void __init omap3pandora_init(void)
@@ -201,6 +395,7 @@ static void __init omap3pandora_init(void)
        spi_register_board_info(omap3pandora_spi_board_info,
                        ARRAY_SIZE(omap3pandora_spi_board_info));
        omap3pandora_ads7846_init();
+        pandora_keys_gpio_init();
        usb_musb_init();
 }
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index b1f23bea863f..dff5528fbfb5 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -27,6 +27,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/i2c/twl4030.h>
+#include <linux/regulator/machine.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -45,6 +46,7 @@
 #include <mach/nand.h>
 #include <mach/usb.h>
+#include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 #define OVERO_GPIO_BT_XGATE     15
@@ -271,21 +273,76 @@ static struct omap_uart_config overo_uart_config __initdata = {
        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
 };
+static struct twl4030_hsmmc_info mmc[] = {
+        {
+                .mmc            = 1,
+                .wires          = 4,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        {
+                .mmc            = 2,
+                .wires          = 4,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+                .transceiver    = true,
+                .ocr_mask       = 0x00100000,   /* 3.3V */
+        },
+        {}      /* Terminator */
+};
+static struct regulator_consumer_supply overo_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+static int overo_twl_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
+{
+        twl4030_mmc_init(mmc);
+        overo_vmmc1_supply.dev = mmc[0].dev;
+        return 0;
+}
 static struct twl4030_gpio_platform_data overo_gpio_data = {
        .gpio_base      = OMAP_MAX_GPIO_LINES,
        .irq_base       = TWL4030_GPIO_IRQ_BASE,
        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .setup          = overo_twl_gpio_setup,
+};
+static struct twl4030_usb_data overo_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+static struct regulator_init_data overo_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &overo_vmmc1_supply,
 };
+/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */
 static struct twl4030_platform_data overo_twldata = {
        .irq_base       = TWL4030_IRQ_BASE,
        .irq_end        = TWL4030_IRQ_END,
        .gpio           = &overo_gpio_data,
+        .usb            = &overo_usb_data,
+        .vmmc1          = &overo_vmmc1,
 };
 static struct i2c_board_info __initdata overo_i2c_boardinfo[] = {
        {
-                I2C_BOARD_INFO("twl4030", 0x48),
+                I2C_BOARD_INFO("tps65950", 0x48),
                .flags = I2C_CLIENT_WAKE,
                .irq = INT_34XX_SYS_NIRQ,
                .platform_data = &overo_twldata,
@@ -303,7 +360,7 @@ static int __init overo_i2c_init(void)
 static void __init overo_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
        omap_init_irq();
        omap_gpio_init();
 }
@@ -326,23 +383,6 @@ static struct platform_device *overo_devices[] __initdata = {
        &overo_lcd_device,
 };
-static struct twl4030_hsmmc_info mmc[] __initdata = {
-        {
-                .mmc            = 1,
-                .wires          = 4,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-        },
-        {
-                .mmc            = 2,
-                .wires          = 4,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-                .transceiver    = true,
-        },
-        {}      /* Terminator */
-};
 static void __init overo_init(void)
 {
        overo_i2c_init();
@@ -350,7 +390,6 @@ static void __init overo_init(void)
        omap_board_config = overo_config;
        omap_board_config_size = ARRAY_SIZE(overo_config);
        omap_serial_init();
-        twl4030_mmc_init(mmc);
        overo_flash_init();
        usb_musb_init();
        overo_ads7846_init();
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index a7381729645c..da93b86234ed 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -27,30 +27,13 @@
 #include <mach/dma.h>
 #include <mach/gpmc.h>
 #include <mach/keypad.h>
+#include <mach/onenand.h>
+#include <mach/gpmc-smc91x.h>
 #include "mmc-twl4030.h"
+#define SYSTEM_REV_B_USES_VAUX3 0x1699
-#define SMC91X_CS                       1
+#define SYSTEM_REV_S_USES_VAUX3 0x8
-#define SMC91X_GPIO_IRQ                 54
-#define SMC91X_GPIO_RESET               164
-#define SMC91X_GPIO_PWRDWN              86
-static struct resource rx51_smc91x_resources[] = {
-        [0] = {
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
-        },
-};
-static struct platform_device rx51_smc91x_device = {
-        .name           = "smc91x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(rx51_smc91x_resources),
-        .resource       = rx51_smc91x_resources,
-};
 static int rx51_keymap[] = {
        KEY(0, 0, KEY_Q),
@@ -107,98 +90,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
        .rep            = 1,
 };
-static struct platform_device *rx51_peripherals_devices[] = {
-        &rx51_smc91x_device,
-};
-/*
- * Timings are taken from smsc-lan91c96-ms.pdf
- */
-static int smc91x_init_gpmc(int cs)
-{
-        struct gpmc_timings t;
-        const int t2_r = 45;            /* t2 in Figure 12.10 */
-        const int t2_w = 30;            /* t2 in Figure 12.11 */
-        const int t3 = 15;              /* t3 in Figure 12.10 */
-        const int t5_r = 0;             /* t5 in Figure 12.10 */
-        const int t6_r = 45;            /* t6 in Figure 12.10 */
-        const int t6_w = 0;             /* t6 in Figure 12.11 */
-        const int t7_w = 15;            /* t7 in Figure 12.11 */
-        const int t15 = 12;             /* t15 in Figure 12.2 */
-        const int t20 = 185;            /* t20 in Figure 12.2 */
-        memset(&t, 0, sizeof(t));
-        t.cs_on = t15;
-        t.cs_rd_off = t3 + t2_r + t5_r; /* Figure 12.10 */
-        t.cs_wr_off = t3 + t2_w + t6_w; /* Figure 12.11 */
-        t.adv_on = t3;                  /* Figure 12.10 */
-        t.adv_rd_off = t3 + t2_r;       /* Figure 12.10 */
-        t.adv_wr_off = t3 + t2_w;       /* Figure 12.11 */
-        t.oe_off = t3 + t2_r + t5_r;    /* Figure 12.10 */
-        t.oe_on = t.oe_off - t6_r;      /* Figure 12.10 */
-        t.we_off = t3 + t2_w + t6_w;    /* Figure 12.11 */
-        t.we_on = t.we_off - t7_w;      /* Figure 12.11 */
-        t.rd_cycle = t20;               /* Figure 12.2 */
-        t.wr_cycle = t20;               /* Figure 12.4 */
-        t.access = t3 + t2_r + t5_r;    /* Figure 12.10 */
-        t.wr_access = t3 + t2_w + t6_w; /* Figure 12.11 */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16);
-        return gpmc_cs_set_timings(cs, &t);
-}
-static void __init rx51_init_smc91x(void)
-{
-        unsigned long cs_mem_base;
-        int ret;
-        omap_cfg_reg(U8_34XX_GPIO54_DOWN);
-        omap_cfg_reg(G25_34XX_GPIO86_OUT);
-        omap_cfg_reg(H19_34XX_GPIO164_OUT);
-        if (gpmc_cs_request(SMC91X_CS, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
-                return;
-        }
-        rx51_smc91x_resources[0].start = cs_mem_base + 0x300;
-        rx51_smc91x_resources[0].end = cs_mem_base + 0x30f;
-        smc91x_init_gpmc(SMC91X_CS);
-        if (gpio_request(SMC91X_GPIO_IRQ, "SMC91X irq") < 0)
-                goto free1;
-        gpio_direction_input(SMC91X_GPIO_IRQ);
-        rx51_smc91x_resources[1].start = gpio_to_irq(SMC91X_GPIO_IRQ);
-        ret = gpio_request(SMC91X_GPIO_PWRDWN, "SMC91X powerdown");
-        if (ret)
-                goto free2;
-        gpio_direction_output(SMC91X_GPIO_PWRDWN, 0);
-        ret = gpio_request(SMC91X_GPIO_RESET, "SMC91X reset");
-        if (ret)
-                goto free3;
-        gpio_direction_output(SMC91X_GPIO_RESET, 0);
-        gpio_set_value(SMC91X_GPIO_RESET, 1);
-        msleep(100);
-        gpio_set_value(SMC91X_GPIO_RESET, 0);
-        return;
-free3:
-        gpio_free(SMC91X_GPIO_PWRDWN);
-free2:
-        gpio_free(SMC91X_GPIO_IRQ);
-free1:
-        gpmc_cs_free(SMC91X_CS);
-        printk(KERN_ERR "Could not initialize smc91x\n");
-}
 static struct twl4030_madc_platform_data rx51_madc_data = {
        .irq_line               = 1,
 };
@@ -259,7 +150,7 @@ static struct regulator_init_data rx51_vaux2 = {
 };
 /* VAUX3 - adds more power to VIO_18 rail */
-static struct regulator_init_data rx51_vaux3 = {
+static struct regulator_init_data rx51_vaux3_cam = {
        .constraints = {
                .name                   = "VCAM_DIG_18",
                .min_uV                 = 1800000,
@@ -272,6 +163,22 @@ static struct regulator_init_data rx51_vaux3 = {
        },
 };
+static struct regulator_init_data rx51_vaux3_mmc = {
+        .constraints = {
+                .name                   = "VMMC2_30",
+                .min_uV                 = 2800000,
+                .max_uV                 = 3000000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &rx51_vmmc2_supply,
+};
 static struct regulator_init_data rx51_vaux4 = {
        .constraints = {
                .name                   = "VCAM_ANA_28",
@@ -382,10 +289,8 @@ static struct twl4030_platform_data rx51_twldata = {
        .vaux1                  = &rx51_vaux1,
        .vaux2                  = &rx51_vaux2,
-        .vaux3                  = &rx51_vaux3,
        .vaux4                  = &rx51_vaux4,
        .vmmc1                  = &rx51_vmmc1,
-        .vmmc2                  = &rx51_vmmc2,
        .vsim                   = &rx51_vsim,
        .vdac                   = &rx51_vdac,
 };
@@ -401,6 +306,13 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
 static int __init rx51_i2c_init(void)
 {
+        if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
+            system_rev >= SYSTEM_REV_B_USES_VAUX3)
+                rx51_twldata.vaux3 = &rx51_vaux3_mmc;
+        else {
+                rx51_twldata.vaux3 = &rx51_vaux3_cam;
+                rx51_twldata.vmmc2 = &rx51_vmmc2;
+        }
        omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1,
                        ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
        omap_register_i2c_bus(2, 100, NULL, 0);
@@ -408,12 +320,94 @@ static int __init rx51_i2c_init(void)
        return 0;
 }
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+static struct mtd_partition onenand_partitions[] = {
+        {
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = 0x20000,
+                .mask_flags     = MTD_WRITEABLE,        /* Force read-only */
+        },
+        {
+                .name           = "config",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x60000,
+        },
+        {
+                .name           = "log",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x40000,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x200000,
+        },
+        {
+                .name           = "initfs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 0x200000,
+        },
+        {
+                .name           = "rootfs",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+static struct omap_onenand_platform_data board_onenand_data = {
+        .cs             = 0,
+        .gpio_irq       = 65,
+        .parts          = onenand_partitions,
+        .nr_parts       = ARRAY_SIZE(onenand_partitions),
+};
+static void __init board_onenand_init(void)
+{
+        gpmc_onenand_init(&board_onenand_data);
+}
+#else
+static inline void board_onenand_init(void)
+{
+}
+#endif
+#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+static struct omap_smc91x_platform_data board_smc91x_data = {
+        .cs             = 1,
+        .gpio_irq       = 54,
+        .gpio_pwrdwn    = 86,
+        .gpio_reset     = 164,
+        .flags          = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_HIGHLEVEL,
+};
+static void __init board_smc91x_init(void)
+{
+        omap_cfg_reg(U8_34XX_GPIO54_DOWN);
+        omap_cfg_reg(G25_34XX_GPIO86_OUT);
+        omap_cfg_reg(H19_34XX_GPIO164_OUT);
+        gpmc_smc91x_init(&board_smc91x_data);
+}
+#else
+static inline void board_smc91x_init(void)
+{
+}
+#endif
 void __init rx51_peripherals_init(void)
 {
-        platform_add_devices(rx51_peripherals_devices,
-                                ARRAY_SIZE(rx51_peripherals_devices));
        rx51_i2c_init();
-        rx51_init_smc91x();
+        board_onenand_init();
+        board_smc91x_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
new file mode 100644
index 000000000000..bac5c4321ff7
--- /dev/null
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Inc.
+ * Mikkel Christensen <mlc@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/serial_8250.h>
+#include <linux/smsc911x.h>
+#include <mach/gpmc.h>
+#define ZOOM2_SMSC911X_CS       7
+#define ZOOM2_SMSC911X_GPIO     158
+#define ZOOM2_QUADUART_CS       3
+#define ZOOM2_QUADUART_GPIO     102
+#define QUART_CLK               1843200
+#define DEBUG_BASE              0x08000000
+#define ZOOM2_ETHR_START        DEBUG_BASE
+static struct resource zoom2_smsc911x_resources[] = {
+        [0] = {
+                .start  = ZOOM2_ETHR_START,
+                .end    = ZOOM2_ETHR_START + SZ_4K,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+static struct smsc911x_platform_config zoom2_smsc911x_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_32BIT,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+};
+static struct platform_device zoom2_smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(zoom2_smsc911x_resources),
+        .resource       = zoom2_smsc911x_resources,
+        .dev            = {
+                .platform_data = &zoom2_smsc911x_config,
+        },
+};
+static inline void __init zoom2_init_smsc911x(void)
+{
+        int eth_cs;
+        unsigned long cs_mem_base;
+        int eth_gpio = 0;
+        eth_cs = ZOOM2_SMSC911X_CS;
+        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
+                return;
+        }
+        zoom2_smsc911x_resources[0].start = cs_mem_base + 0x0;
+        zoom2_smsc911x_resources[0].end   = cs_mem_base + 0xff;
+        eth_gpio = ZOOM2_SMSC911X_GPIO;
+        zoom2_smsc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
+        if (gpio_request(eth_gpio, "smsc911x irq") < 0) {
+                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
+                                eth_gpio);
+                return;
+        }
+        gpio_direction_input(eth_gpio);
+}
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .mapbase        = 0x10000000,
+                .irq            = OMAP_GPIO_IRQ(102),
+                .flags          = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
+                .iotype         = UPIO_MEM,
+                .regshift       = 1,
+                .uartclk        = QUART_CLK,
+        }, {
+                .flags          = 0
+        }
+};
+static struct platform_device zoom2_debugboard_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM1,
+        .dev                    = {
+                .platform_data  = serial_platform_data,
+        },
+};
+static inline void __init zoom2_init_quaduart(void)
+{
+        int quart_cs;
+        unsigned long cs_mem_base;
+        int quart_gpio = 0;
+        quart_cs = ZOOM2_QUADUART_CS;
+        if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem"
+                                "for Quad UART(TL16CP754C)\n");
+                return;
+        }
+        quart_gpio = ZOOM2_QUADUART_GPIO;
+        if (gpio_request(quart_gpio, "TL16CP754C GPIO") < 0) {
+                printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
+                                                                quart_gpio);
+                return;
+        }
+        gpio_direction_input(quart_gpio);
+}
+static inline int omap_zoom2_debugboard_detect(void)
+{
+        int debug_board_detect = 0;
+        debug_board_detect = ZOOM2_SMSC911X_GPIO;
+        if (gpio_request(debug_board_detect, "Zoom2 debug board detect") < 0) {
+                printk(KERN_ERR "Failed to request GPIO%d for Zoom2 debug"
+                "board detect\n", debug_board_detect);
+                return 0;
+        }
+        gpio_direction_input(debug_board_detect);
+        if (!gpio_get_value(debug_board_detect)) {
+                gpio_free(debug_board_detect);
+                return 0;
+        }
+        return 1;
+}
+static struct platform_device *zoom2_devices[] __initdata = {
+        &zoom2_smsc911x_device,
+        &zoom2_debugboard_serial_device,
+};
+int __init omap_zoom2_debugboard_init(void)
+{
+        if (!omap_zoom2_debugboard_detect())
+                return 0;
+        zoom2_init_smsc911x();
+        zoom2_init_quaduart();
+        return platform_add_devices(zoom2_devices, ARRAY_SIZE(zoom2_devices));
+}
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
new file mode 100644
index 000000000000..bcc0f7632dea
--- /dev/null
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Inc.
+ * Mikkel Christensen <mlc@ti.com>
+ *
+ * Modified from mach-omap2/board-ldp.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/i2c/twl4030.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/common.h>
+#include <mach/usb.h>
+#include "mmc-twl4030.h"
+static void __init omap_zoom2_init_irq(void)
+{
+        omap2_init_common_hw(NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+static struct omap_uart_config zoom2_uart_config __initdata = {
+        .enabled_uarts  = ((1 << 0) | (1 << 1) | (1 << 2)),
+};
+static struct omap_board_config_kernel zoom2_config[] __initdata = {
+        { OMAP_TAG_UART,        &zoom2_uart_config },
+};
+static struct twl4030_gpio_platform_data zoom2_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+};
+static struct twl4030_platform_data zoom2_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+        /* platform_data for children goes here */
+        .gpio           = &zoom2_gpio_data,
+};
+static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags          = I2C_CLIENT_WAKE,
+                .irq            = INT_34XX_SYS_NIRQ,
+                .platform_data  = &zoom2_twldata,
+        },
+};
+static int __init omap_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, zoom2_i2c_boardinfo,
+                        ARRAY_SIZE(zoom2_i2c_boardinfo));
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        omap_register_i2c_bus(3, 400, NULL, 0);
+        return 0;
+}
+static struct twl4030_hsmmc_info mmc[] __initdata = {
+        {
+                .mmc            = 1,
+                .wires          = 4,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        {}      /* Terminator */
+};
+extern int __init omap_zoom2_debugboard_init(void);
+static void __init omap_zoom2_init(void)
+{
+        omap_i2c_init();
+        omap_board_config = zoom2_config;
+        omap_board_config_size = ARRAY_SIZE(zoom2_config);
+        omap_serial_init();
+        omap_zoom2_debugboard_init();
+        twl4030_mmc_init(mmc);
+        usb_musb_init();
+}
+static void __init omap_zoom2_map_io(void)
+{
+        omap2_set_globals_343x();
+        omap2_map_common_io();
+}
+MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = omap_zoom2_map_io,
+        .init_irq       = omap_zoom2_init_irq,
+        .init_machine   = omap_zoom2_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4247a1534411..ba528f85749c 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -91,9 +91,9 @@ static void _omap2xxx_clk_commit(struct clk *clk)
                return;
        prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
-                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+                OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
        /* OCP barrier */
-        prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+        prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
 }
 /*
@@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        const struct clksel_rate *clkr;
        u32 last_div = 0;
-        printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
+        pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-               clk->name, target_rate);
+                 clk->name, target_rate);
        *new_div = 1;
@@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
                /* Sanity check */
                if (clkr->div <= last_div)
-                        printk(KERN_ERR "clock: clksel_rate table not sorted "
+                        pr_err("clock: clksel_rate table not sorted "
                               "for clock %s", clk->name);
                last_div = clkr->div;
@@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        }
        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find divisor for target "
+                pr_err("clock: Could not find divisor for target "
                       "rate %ld for clock %s parent %s\n", target_rate,
                       clk->name, clk->parent->name);
                return ~0;
@@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
        *new_div = clkr->div;
-        printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
+        pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-               (clk->parent->rate / clkr->div));
+                 (clk->parent->rate / clkr->div));
        return (clk->parent->rate / clkr->div);
 }
@@ -1035,7 +1035,7 @@ void omap2_clk_disable_unused(struct clk *clk)
        if ((regval32 & (1 << clk->enable_bit)) == v)
                return;
-        printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
+        printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
        if (cpu_is_omap34xx()) {
                omap2_clk_enable(clk);
                omap2_clk_disable(clk);
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index e4cef333e291..44de0271fc2f 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -233,6 +233,8 @@ static struct prcm_config *curr_prcm_set;
 static struct clk *vclk;
 static struct clk *sclk;
+static void __iomem *prcm_clksrc_ctrl;
 /*-------------------------------------------------------------------------
 * Omap24xx specific clock functions
 *-------------------------------------------------------------------------*/
@@ -269,10 +271,9 @@ static int omap2_enable_osc_ck(struct clk *clk)
 {
        u32 pcc;
-        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+        pcc = __raw_readl(prcm_clksrc_ctrl);
-        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
+        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-                      OMAP24XX_PRCM_CLKSRC_CTRL);
        return 0;
 }
@@ -281,10 +282,9 @@ static void omap2_disable_osc_ck(struct clk *clk)
 {
        u32 pcc;
-        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+        pcc = __raw_readl(prcm_clksrc_ctrl);
-        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
+        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-                      OMAP24XX_PRCM_CLKSRC_CTRL);
 }
 static const struct clkops clkops_oscck = {
@@ -654,7 +654,7 @@ static u32 omap2_get_sysclkdiv(void)
 {
        u32 div;
-        div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+        div = __raw_readl(prcm_clksrc_ctrl);
        div &= OMAP_SYSCLKDIV_MASK;
        div >>= OMAP_SYSCLKDIV_SHIFT;
@@ -714,15 +714,18 @@ int __init omap2_clk_init(void)
        struct omap_clk *c;
        u32 clkrate;
-        if (cpu_is_omap242x())
+        if (cpu_is_omap242x()) {
+                prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
                cpu_mask = RATE_IN_242X;
-        else if (cpu_is_omap2430())
+        } else if (cpu_is_omap2430()) {
+                prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
                cpu_mask = RATE_IN_243X;
+        }
        clk_init(&omap2_clk_functions);
        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
-                clk_init_one(c->lk.clk);
+                clk_preinit(c->lk.clk);
        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
        propagate_rate(&osc_ck);
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 88c5acb40fcf..458f00cdcbea 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,6 +24,17 @@
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
+#ifdef CONFIG_ARCH_OMAP2420
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2420_PRCM_CLKOUT_CTRL
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2420_PRCM_CLKEMUL_CTRL
+#else
+#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2430_PRCM_CLKOUT_CTRL
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2430_PRCM_CLKEMUL_CTRL
+#endif
 static unsigned long omap2_table_mpu_recalc(struct clk *clk);
 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index ba05aa42bd8e..9e43fe5209d3 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -129,6 +129,9 @@ static struct omap_clk omap34xx_clks[] = {
        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
+        CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
@@ -281,6 +284,8 @@ static struct omap_clk omap34xx_clks[] = {
 #define MAX_DPLL_WAIT_TRIES             1000000
+#define MIN_SDRC_DLL_LOCK_FREQ          83000000
 /**
 * omap3_dpll_recalc - recalculate DPLL rate
 * @clk: DPLL struct clk
@@ -703,6 +708,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 {
        u32 new_div = 0;
+        u32 unlock_dll = 0;
        unsigned long validrate, sdrcrate;
        struct omap_sdrc_params *sp;
@@ -729,17 +735,22 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        if (!sp)
                return -EINVAL;
-        pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+        if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
-                validrate);
+                pr_debug("clock: will unlock SDRC DLL\n");
-        pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
+                unlock_dll = 1;
-                sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
+        }
+        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+                 validrate);
+        pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
+                 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
        /* REVISIT: SRAM code doesn't support other M2 divisors yet */
        WARN_ON(new_div != 1 && new_div != 2);
        /* REVISIT: Add SDRC_MR changing to this code also */
        omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-                                  sp->actim_ctrlb, new_div);
+                                  sp->actim_ctrlb, new_div, unlock_dll);
        return 0;
 }
@@ -956,7 +967,7 @@ int __init omap2_clk_init(void)
        clk_init(&omap2_clk_functions);
        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
-                clk_init_one(c->lk.clk);
+                clk_preinit(c->lk.clk);
        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
                if (c->cpu & cpu_clkflg) {
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 017a30e9aa1d..e433aec4efdd 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -27,6 +27,8 @@
 #include "prm.h"
 #include "prm-regbits-34xx.h"
+#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
 static unsigned long omap3_dpll_recalc(struct clk *clk);
 static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
 static void omap3_dpll_allow_idle(struct clk *clk);
@@ -1228,6 +1230,37 @@ static struct clk d2d_26m_fck = {
        .recalc         = &followparent_recalc,
 };
+static struct clk modem_fck = {
+        .name           = "modem_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clk_clkdm,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk sad2d_ick = {
+        .name           = "sad2d_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+static struct clk mad2d_ick = {
+        .name           = "mad2d_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
 static const struct clksel omap343x_gpt_clksel[] = {
        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
        { .parent = &sys_ck,       .rates = gpt_sys_rates },
@@ -1945,8 +1978,6 @@ static struct clk usb_l4_ick = {
        .recalc         = &omap2_clksel_recalc,
 };
-/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
 /* SECURITY_L4_ICK2 based clocks */
 static struct clk security_l4_ick2 = {
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index 281d5da19188..fe319ae4ca0a 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -195,7 +195,7 @@ static struct clockdomain sgx_clkdm = {
 static struct clockdomain d2d_clkdm = {
        .name           = "d2d_clkdm",
        .pwrdm          = { .name = "core_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP,
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
        .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6f3f5a36aae6..6923deb98a28 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -145,6 +145,8 @@
 #define OMAP3430_CLKACTIVITY_MPU_MASK                   (1 << 0)
 /* CM_FCLKEN1_CORE specific bits */
+#define OMAP3430_EN_MODEM                               (1 << 31)
+#define OMAP3430_EN_MODEM_SHIFT                         31
 /* CM_ICLKEN1_CORE specific bits */
 #define OMAP3430_EN_ICR                                 (1 << 29)
@@ -161,6 +163,8 @@
 #define OMAP3430_EN_MAILBOXES_SHIFT                     7
 #define OMAP3430_EN_OMAPCTRL                            (1 << 6)
 #define OMAP3430_EN_OMAPCTRL_SHIFT                      6
+#define OMAP3430_EN_SAD2D                               (1 << 3)
+#define OMAP3430_EN_SAD2D_SHIFT                         3
 #define OMAP3430_EN_SDRC                                (1 << 1)
 #define OMAP3430_EN_SDRC_SHIFT                          1
@@ -176,6 +180,10 @@
 #define OMAP3430_EN_DES1                                (1 << 0)
 #define OMAP3430_EN_DES1_SHIFT                          0
+/* CM_ICLKEN3_CORE */
+#define OMAP3430_EN_MAD2D_SHIFT                         3
+#define OMAP3430_EN_MAD2D                               (1 << 3)
 /* CM_FCLKEN3_CORE specific bits */
 #define OMAP3430ES2_EN_TS_SHIFT                         1
 #define OMAP3430ES2_EN_TS_MASK                          (1 << 1)
@@ -231,6 +239,8 @@
 #define OMAP3430ES2_ST_CPEFUSE_MASK                     (1 << 0)
 /* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_MODEM                             (1 << 31)
+#define OMAP3430_AUTO_MODEM_SHIFT                       31
 #define OMAP3430ES2_AUTO_MMC3                           (1 << 30)
 #define OMAP3430ES2_AUTO_MMC3_SHIFT                     30
 #define OMAP3430ES2_AUTO_ICR                            (1 << 29)
@@ -287,6 +297,8 @@
 #define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
 #define OMAP3430ES1_AUTO_D2D                            (1 << 3)
 #define OMAP3430ES1_AUTO_D2D_SHIFT                      3
+#define OMAP3430_AUTO_SAD2D                             (1 << 3)
+#define OMAP3430_AUTO_SAD2D_SHIFT                       3
 #define OMAP3430_AUTO_SSI                               (1 << 0)
 #define OMAP3430_AUTO_SSI_SHIFT                         0
@@ -308,6 +320,8 @@
 #define OMAP3430ES2_AUTO_USBTLL                         (1 << 2)
 #define OMAP3430ES2_AUTO_USBTLL_SHIFT                   2
 #define OMAP3430ES2_AUTO_USBTLL_MASK                    (1 << 2)
+#define OMAP3430_AUTO_MAD2D_SHIFT                       3
+#define OMAP3430_AUTO_MAD2D                             (1 << 3)
 /* CM_CLKSEL_CORE */
 #define OMAP3430_CLKSEL_SSI_SHIFT                       8
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 65fdf78c91e1..1d3c93bf86d3 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -16,17 +16,12 @@
 #include "prcm-common.h"
-#ifndef __ASSEMBLER__
-#define OMAP_CM_REGADDR(module, reg)                                    \
-                        IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
-#else
 #define OMAP2420_CM_REGADDR(module, reg)                                \
                        IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
 #define OMAP2430_CM_REGADDR(module, reg)                                \
                        IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
 #define OMAP34XX_CM_REGADDR(module, reg)                                \
                        IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
-#endif
 /*
 * Architecture-specific global CM registers
@@ -38,6 +33,7 @@
 #define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
 #define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 /*
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
new file mode 100644
index 000000000000..2fd22f9c5f0e
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -0,0 +1,330 @@
+/*
+ * linux/arch/arm/mach-omap2/gpmc-onenand.c
+ *
+ * Copyright (C) 2006 - 2009 Nokia Corporation
+ * Contacts:    Juha Yrjola
+ *              Tony Lindgren
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/onenand_regs.h>
+#include <linux/io.h>
+#include <asm/mach/flash.h>
+#include <mach/onenand.h>
+#include <mach/board.h>
+#include <mach/gpmc.h>
+static struct omap_onenand_platform_data *gpmc_onenand_data;
+static struct platform_device gpmc_onenand_device = {
+        .name           = "omap2-onenand",
+        .id             = -1,
+};
+static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
+{
+        struct gpmc_timings t;
+        const int t_cer = 15;
+        const int t_avdp = 12;
+        const int t_aavdh = 7;
+        const int t_ce = 76;
+        const int t_aa = 76;
+        const int t_oe = 20;
+        const int t_cez = 20; /* max of t_cez, t_oez */
+        const int t_ds = 30;
+        const int t_wpl = 40;
+        const int t_wph = 30;
+        memset(&t, 0, sizeof(t));
+        t.sync_clk = 0;
+        t.cs_on = 0;
+        t.adv_on = 0;
+        /* Read */
+        t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
+        t.oe_on  = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
+        t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
+        t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
+        t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
+        t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
+        t.cs_rd_off = t.oe_off;
+        t.rd_cycle  = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
+        /* Write */
+        t.adv_wr_off = t.adv_rd_off;
+        t.we_on  = t.oe_on;
+        if (cpu_is_omap34xx()) {
+                t.wr_data_mux_bus = t.we_on;
+                t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
+        }
+        t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
+        t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
+        t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
+        /* Configure GPMC for asynchronous read */
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
+                          GPMC_CONFIG1_DEVICESIZE_16 |
+                          GPMC_CONFIG1_MUXADDDATA);
+        return gpmc_cs_set_timings(cs, &t);
+}
+static void set_onenand_cfg(void __iomem *onenand_base, int latency,
+                                int sync_read, int sync_write, int hf)
+{
+        u32 reg;
+        reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
+        reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
+        reg |=  (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
+                ONENAND_SYS_CFG1_BL_16;
+        if (sync_read)
+                reg |= ONENAND_SYS_CFG1_SYNC_READ;
+        else
+                reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
+        if (sync_write)
+                reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
+        else
+                reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
+        if (hf)
+                reg |= ONENAND_SYS_CFG1_HF;
+        else
+                reg &= ~ONENAND_SYS_CFG1_HF;
+        writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+}
+static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+                                        void __iomem *onenand_base,
+                                        int freq)
+{
+        struct gpmc_timings t;
+        const int t_cer  = 15;
+        const int t_avdp = 12;
+        const int t_cez  = 20; /* max of t_cez, t_oez */
+        const int t_ds   = 30;
+        const int t_wpl  = 40;
+        const int t_wph  = 30;
+        int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
+        int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+        int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
+        int err, ticks_cez;
+        int cs = cfg->cs;
+        u32 reg;
+        if (cfg->flags & ONENAND_SYNC_READ) {
+                sync_read = 1;
+        } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
+                sync_read = 1;
+                sync_write = 1;
+        }
+        if (!freq) {
+                /* Very first call freq is not known */
+                err = omap2_onenand_set_async_mode(cs, onenand_base);
+                if (err)
+                        return err;
+                reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
+                switch ((reg >> 4) & 0xf) {
+                case 0:
+                        freq = 40;
+                        break;
+                case 1:
+                        freq = 54;
+                        break;
+                case 2:
+                        freq = 66;
+                        break;
+                case 3:
+                        freq = 83;
+                        break;
+                case 4:
+                        freq = 104;
+                        break;
+                default:
+                        freq = 54;
+                        break;
+                }
+                first_time = 1;
+        }
+        switch (freq) {
+        case 83:
+                min_gpmc_clk_period = 12; /* 83 MHz */
+                t_ces   = 5;
+                t_avds  = 4;
+                t_avdh  = 2;
+                t_ach   = 6;
+                t_aavdh = 6;
+                t_rdyo  = 9;
+                break;
+        case 66:
+                min_gpmc_clk_period = 15; /* 66 MHz */
+                t_ces   = 6;
+                t_avds  = 5;
+                t_avdh  = 2;
+                t_ach   = 6;
+                t_aavdh = 6;
+                t_rdyo  = 11;
+                break;
+        default:
+                min_gpmc_clk_period = 18; /* 54 MHz */
+                t_ces   = 7;
+                t_avds  = 7;
+                t_avdh  = 7;
+                t_ach   = 9;
+                t_aavdh = 7;
+                t_rdyo  = 15;
+                sync_write = 0;
+                break;
+        }
+        tick_ns = gpmc_ticks_to_ns(1);
+        div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
+        gpmc_clk_ns = gpmc_ticks_to_ns(div);
+        if (gpmc_clk_ns < 15) /* >66Mhz */
+                hf = 1;
+        if (hf)
+                latency = 6;
+        else if (gpmc_clk_ns >= 25) /* 40 MHz*/
+                latency = 3;
+        else
+                latency = 4;
+        if (first_time)
+                set_onenand_cfg(onenand_base, latency,
+                                        sync_read, sync_write, hf);
+        if (div == 1) {
+                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
+                reg |= (1 << 7);
+                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
+                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
+                reg |= (1 << 7);
+                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
+                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
+                reg |= (1 << 7);
+                reg |= (1 << 23);
+                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
+        } else {
+                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
+                reg &= ~(1 << 7);
+                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
+                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
+                reg &= ~(1 << 7);
+                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
+                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
+                reg &= ~(1 << 7);
+                reg &= ~(1 << 23);
+                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
+        }
+        /* Set synchronous read timings */
+        memset(&t, 0, sizeof(t));
+        t.sync_clk = min_gpmc_clk_period;
+        t.cs_on = 0;
+        t.adv_on = 0;
+        fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
+        fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
+        t.page_burst_access = gpmc_clk_ns;
+        /* Read */
+        t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
+        t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
+        t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
+        t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
+        t.cs_rd_off = t.oe_off;
+        ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
+        t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
+                     ticks_cez);
+        /* Write */
+        if (sync_write) {
+                t.adv_wr_off = t.adv_rd_off;
+                t.we_on  = 0;
+                t.we_off = t.cs_rd_off;
+                t.cs_wr_off = t.cs_rd_off;
+                t.wr_cycle  = t.rd_cycle;
+                if (cpu_is_omap34xx()) {
+                        t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
+                                        gpmc_ns_to_ticks(min_gpmc_clk_period +
+                                        t_rdyo));
+                        t.wr_access = t.access;
+                }
+        } else {
+                t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
+                                                        t_avdp, t_cer));
+                t.we_on  = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
+                t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
+                t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
+                t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
+                if (cpu_is_omap34xx()) {
+                        t.wr_data_mux_bus = t.we_on;
+                        t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
+                }
+        }
+        /* Configure GPMC for synchronous read */
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
+                          GPMC_CONFIG1_WRAPBURST_SUPP |
+                          GPMC_CONFIG1_READMULTIPLE_SUPP |
+                          (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
+                          (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
+                          (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
+                          GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
+                          GPMC_CONFIG1_PAGE_LEN(2) |
+                          (cpu_is_omap34xx() ? 0 :
+                                (GPMC_CONFIG1_WAIT_READ_MON |
+                                 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
+                          GPMC_CONFIG1_DEVICESIZE_16 |
+                          GPMC_CONFIG1_DEVICETYPE_NOR |
+                          GPMC_CONFIG1_MUXADDDATA);
+        err = gpmc_cs_set_timings(cs, &t);
+        if (err)
+                return err;
+        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
+        return 0;
+}
+static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
+{
+        struct device *dev = &gpmc_onenand_device.dev;
+        /* Set sync timings in GPMC */
+        if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
+                        freq) < 0) {
+                dev_err(dev, "Unable to set synchronous mode\n");
+                return -EINVAL;
+        }
+        return 0;
+}
+void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
+{
+        gpmc_onenand_data = _onenand_data;
+        gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
+        gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
+        if (cpu_is_omap24xx() &&
+                        (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
+                printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
+                gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
+                gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
+        }
+        if (platform_device_register(&gpmc_onenand_device) < 0) {
+                printk(KERN_ERR "Unable to register OneNAND device\n");
+                return;
+        }
+}
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
new file mode 100644
index 000000000000..df99d31d8b64
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-omap2/gpmc-smc91x.c
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Contact:     Tony Lindgren
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/smc91x.h>
+#include <mach/board.h>
+#include <mach/gpmc.h>
+#include <mach/gpmc-smc91x.h>
+static struct omap_smc91x_platform_data *gpmc_cfg;
+static struct resource gpmc_smc91x_resources[] = {
+        [0] = {
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct smc91x_platdata gpmc_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
+};
+static struct platform_device gpmc_smc91x_device = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(gpmc_smc91x_resources),
+        .resource       = gpmc_smc91x_resources,
+        .dev            = {
+                .platform_data = &gpmc_smc91x_info,
+        },
+};
+/*
+ * Set the gpmc timings for smc91c96. The timings are taken
+ * from the data sheet available at:
+ * http://www.smsc.com/main/catalog/lan91c96.html
+ * REVISIT: Level shifters can add at least to the access latency.
+ */
+static int smc91c96_gpmc_retime(void)
+{
+        struct gpmc_timings t;
+        const int t3 = 10;      /* Figure 12.2 read and 12.4 write */
+        const int t4_r = 20;    /* Figure 12.2 read */
+        const int t4_w = 5;     /* Figure 12.4 write */
+        const int t5 = 25;      /* Figure 12.2 read */
+        const int t6 = 15;      /* Figure 12.2 read */
+        const int t7 = 5;       /* Figure 12.4 write */
+        const int t8 = 5;       /* Figure 12.4 write */
+        const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
+        u32 l;
+        memset(&t, 0, sizeof(t));
+        /* Read timings */
+        t.cs_on = 0;
+        t.adv_on = t.cs_on;
+        t.oe_on = t.adv_on + t3;
+        t.access = t.oe_on + t5;
+        t.oe_off = t.access;
+        t.adv_rd_off = t.oe_off + max(t4_r, t6);
+        t.cs_rd_off = t.oe_off;
+        t.rd_cycle = t20 - t.oe_on;
+        /* Write timings */
+        t.we_on = t.adv_on + t3;
+        if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) {
+                t.wr_data_mux_bus = t.we_on;
+                t.we_off = t.wr_data_mux_bus + t7;
+        } else
+                t.we_off = t.we_on + t7;
+        if (cpu_is_omap34xx())
+                t.wr_access = t.we_off;
+        t.adv_wr_off = t.we_off + max(t4_w, t8);
+        t.cs_wr_off = t.we_off + t4_w;
+        t.wr_cycle = t20 - t.we_on;
+        l = GPMC_CONFIG1_DEVICESIZE_16;
+        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
+                l |= GPMC_CONFIG1_MUXADDDATA;
+        if (gpmc_cfg->flags & GPMC_READ_MON)
+                l |= GPMC_CONFIG1_WAIT_READ_MON;
+        if (gpmc_cfg->flags & GPMC_WRITE_MON)
+                l |= GPMC_CONFIG1_WAIT_WRITE_MON;
+        if (gpmc_cfg->wait_pin)
+                l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
+        gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
+        /*
+         * FIXME: Calculate the address and data bus muxed timings.
+         * Note that at least adv_rd_off needs to be changed according
+         * to omap3430 TRM Figure 11-11. Are the sdp boards using the
+         * FPGA in between smc91x and omap as the timings are different
+         * from above?
+         */
+        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
+                return 0;
+        return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
+}
+/*
+ * Initialize smc91x device connected to the GPMC. Note that we
+ * assume that pin multiplexing is done in the board-*.c file,
+ * or in the bootloader.
+ */
+void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
+{
+        unsigned long cs_mem_base;
+        int ret;
+        gpmc_cfg = board_data;
+        if (gpmc_cfg->flags & GPMC_TIMINGS_SMC91C96)
+                gpmc_cfg->retime = smc91c96_gpmc_retime;
+        if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+                return;
+        }
+        gpmc_smc91x_resources[0].start = cs_mem_base + 0x300;
+        gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
+        gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
+        if (gpmc_cfg->retime) {
+                ret = gpmc_cfg->retime();
+                if (ret != 0)
+                        goto free1;
+        }
+        if (gpio_request(gpmc_cfg->gpio_irq, "SMC91X irq") < 0)
+                goto free1;
+        gpio_direction_input(gpmc_cfg->gpio_irq);
+        gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
+        if (gpmc_cfg->gpio_pwrdwn) {
+                ret = gpio_request(gpmc_cfg->gpio_pwrdwn, "SMC91X powerdown");
+                if (ret)
+                        goto free2;
+                gpio_direction_output(gpmc_cfg->gpio_pwrdwn, 0);
+        }
+        if (gpmc_cfg->gpio_reset) {
+                ret = gpio_request(gpmc_cfg->gpio_reset, "SMC91X reset");
+                if (ret)
+                        goto free3;
+                gpio_direction_output(gpmc_cfg->gpio_reset, 0);
+                gpio_set_value(gpmc_cfg->gpio_reset, 1);
+                msleep(100);
+                gpio_set_value(gpmc_cfg->gpio_reset, 0);
+        }
+        if (platform_device_register(&gpmc_smc91x_device) < 0) {
+                printk(KERN_ERR "Unable to register smc91x device\n");
+                gpio_free(gpmc_cfg->gpio_reset);
+                goto free3;
+        }
+        return;
+free3:
+        if (gpmc_cfg->gpio_pwrdwn)
+                gpio_free(gpmc_cfg->gpio_pwrdwn);
+free2:
+        gpio_free(gpmc_cfg->gpio_irq);
+free1:
+        gpmc_cs_free(gpmc_cfg->cs);
+        printk(KERN_ERR "Could not initialize smc91x\n");
+}
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2249049c1d5a..f91934b2b092 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -5,6 +5,9 @@
 *
 * Author: Juha Yrjola
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -424,6 +427,9 @@ void __init gpmc_init(void)
        } else if (cpu_is_omap34xx()) {
                ck = "gpmc_fck";
                l = OMAP34XX_GPMC_BASE;
+        } else if (cpu_is_omap44xx()) {
+                ck = "gpmc_fck";
+                l = OMAP44XX_GPMC_BASE;
        }
        gpmc_l3_clk = clk_get(NULL, ck);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 34b5914e0f8b..458990e20c60 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,6 +6,9 @@
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -200,7 +203,10 @@ void __init omap2_check_revision(void)
                omap24xx_check_revision();
        else if (cpu_is_omap34xx())
                omap34xx_check_revision();
-        else
+        else if (cpu_is_omap44xx()) {
+                printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
+                return;
+        } else
                pr_err("OMAP revision unknown, please fix!\n");
        /*
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 916fcd3a2328..32afd9448216 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -4,12 +4,14 @@
 * OMAP2 I/O mapping code
 *
 * Copyright (C) 2005 Nokia Corporation
- * Copyright (C) 2007 Texas Instruments
+ * Copyright (C) 2007-2009 Texas Instruments
 *
 * Author:
 *      Juha Yrjola <juha.yrjola@nokia.com>
 *      Syed Khasim <x0khasim@ti.com>
 *
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -30,6 +32,7 @@
 #include <mach/sdrc.h>
 #include <mach/gpmc.h>
+#ifndef CONFIG_ARCH_OMAP4       /* FIXME: Remove this once clkdev is ready */
 #include "clock.h"
 #include <mach/powerdomain.h>
@@ -38,7 +41,7 @@
 #include <mach/clockdomain.h>
 #include "clockdomains.h"
+#endif
 /*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
@@ -166,6 +169,46 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
        },
 };
 #endif
+#ifdef  CONFIG_ARCH_OMAP4
+static struct map_desc omap44xx_io_desc[] __initdata = {
+        {
+                .virtual        = L3_44XX_VIRT,
+                .pfn            = __phys_to_pfn(L3_44XX_PHYS),
+                .length         = L3_44XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_44XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_44XX_PHYS),
+                .length         = L4_44XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_WK_44XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_WK_44XX_PHYS),
+                .length         = L4_WK_44XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = OMAP44XX_GPMC_VIRT,
+                .pfn            = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
+                .length         = OMAP44XX_GPMC_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_PER_44XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
+                .length         = L4_PER_44XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_EMU_44XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_EMU_44XX_PHYS),
+                .length         = L4_EMU_44XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+#endif
 void __init omap2_map_common_io(void)
 {
@@ -183,6 +226,9 @@ void __init omap2_map_common_io(void)
        iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
+#endif
        /* Normally devicemaps_init() would flush caches and tlb after
         * mdesc->map_io(), but we must also do it here because of the CPU
         * revision check below.
@@ -198,9 +244,11 @@ void __init omap2_map_common_io(void)
 void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
 {
        omap2_mux_init();
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
        pwrdm_init(powerdomains_omap);
        clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
        omap2_clk_init();
        omap2_sdrc_init(sp);
+#endif
        gpmc_init();
 }
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
new file mode 100644
index 000000000000..015f22a53ead
--- /dev/null
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -0,0 +1,323 @@
+/*
+ * omap iommu: omap2/3 architecture specific functions
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
+ *              Paul Mundt and Toshihiro Kobayashi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/stringify.h>
+#include <mach/iommu.h>
+/*
+ * omap2 architecture specific register bit definitions
+ */
+#define IOMMU_ARCH_VERSION      0x00000011
+/* SYSCONF */
+#define MMU_SYS_IDLE_SHIFT      3
+#define MMU_SYS_IDLE_FORCE      (0 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_NONE       (1 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_SMART      (2 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_IDLE_MASK       (3 << MMU_SYS_IDLE_SHIFT)
+#define MMU_SYS_SOFTRESET       (1 << 1)
+#define MMU_SYS_AUTOIDLE        1
+/* SYSSTATUS */
+#define MMU_SYS_RESETDONE       1
+/* IRQSTATUS & IRQENABLE */
+#define MMU_IRQ_MULTIHITFAULT   (1 << 4)
+#define MMU_IRQ_TABLEWALKFAULT  (1 << 3)
+#define MMU_IRQ_EMUMISS         (1 << 2)
+#define MMU_IRQ_TRANSLATIONFAULT        (1 << 1)
+#define MMU_IRQ_TLBMISS         (1 << 0)
+#define MMU_IRQ_MASK    \
+        (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
+         MMU_IRQ_TRANSLATIONFAULT)
+/* MMU_CNTL */
+#define MMU_CNTL_SHIFT          1
+#define MMU_CNTL_MASK           (7 << MMU_CNTL_SHIFT)
+#define MMU_CNTL_EML_TLB        (1 << 3)
+#define MMU_CNTL_TWL_EN         (1 << 2)
+#define MMU_CNTL_MMU_EN         (1 << 1)
+#define get_cam_va_mask(pgsz)                           \
+        (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
+         ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
+         ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
+         ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
+static int omap2_iommu_enable(struct iommu *obj)
+{
+        u32 l, pa;
+        unsigned long timeout;
+        if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
+                return -EINVAL;
+        pa = virt_to_phys(obj->iopgd);
+        if (!IS_ALIGNED(pa, SZ_16K))
+                return -EINVAL;
+        iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
+        timeout = jiffies + msecs_to_jiffies(20);
+        do {
+                l = iommu_read_reg(obj, MMU_SYSSTATUS);
+                if (l & MMU_SYS_RESETDONE)
+                        break;
+        } while (time_after(jiffies, timeout));
+        if (!(l & MMU_SYS_RESETDONE)) {
+                dev_err(obj->dev, "can't take mmu out of reset\n");
+                return -ENODEV;
+        }
+        l = iommu_read_reg(obj, MMU_REVISION);
+        dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
+                 (l >> 4) & 0xf, l & 0xf);
+        l = iommu_read_reg(obj, MMU_SYSCONFIG);
+        l &= ~MMU_SYS_IDLE_MASK;
+        l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
+        iommu_write_reg(obj, l, MMU_SYSCONFIG);
+        iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
+        iommu_write_reg(obj, pa, MMU_TTB);
+        l = iommu_read_reg(obj, MMU_CNTL);
+        l &= ~MMU_CNTL_MASK;
+        l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
+        iommu_write_reg(obj, l, MMU_CNTL);
+        return 0;
+}
+static void omap2_iommu_disable(struct iommu *obj)
+{
+        u32 l = iommu_read_reg(obj, MMU_CNTL);
+        l &= ~MMU_CNTL_MASK;
+        iommu_write_reg(obj, l, MMU_CNTL);
+        iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
+        dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
+}
+static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
+{
+        int i;
+        u32 stat, da;
+        const char *err_msg[] = {
+                "tlb miss",
+                "translation fault",
+                "emulation miss",
+                "table walk fault",
+                "multi hit fault",
+        };
+        stat = iommu_read_reg(obj, MMU_IRQSTATUS);
+        stat &= MMU_IRQ_MASK;
+        if (!stat)
+                return 0;
+        da = iommu_read_reg(obj, MMU_FAULT_AD);
+        *ra = da;
+        dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
+        for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
+                if (stat & (1 << i))
+                        printk("%s ", err_msg[i]);
+        }
+        printk("\n");
+        iommu_write_reg(obj, stat, MMU_IRQSTATUS);
+        return stat;
+}
+static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
+{
+        cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
+        cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
+}
+static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
+{
+        iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
+        iommu_write_reg(obj, cr->ram, MMU_RAM);
+}
+static u32 omap2_cr_to_virt(struct cr_regs *cr)
+{
+        u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
+        u32 mask = get_cam_va_mask(cr->cam & page_size);
+        return cr->cam & mask;
+}
+static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
+{
+        struct cr_regs *cr;
+        if (e->da & ~(get_cam_va_mask(e->pgsz))) {
+                dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
+                        e->da);
+                return ERR_PTR(-EINVAL);
+        }
+        cr = kmalloc(sizeof(*cr), GFP_KERNEL);
+        if (!cr)
+                return ERR_PTR(-ENOMEM);
+        cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
+        cr->ram = e->pa | e->endian | e->elsz | e->mixed;
+        return cr;
+}
+static inline int omap2_cr_valid(struct cr_regs *cr)
+{
+        return cr->cam & MMU_CAM_V;
+}
+static u32 omap2_get_pte_attr(struct iotlb_entry *e)
+{
+        u32 attr;
+        attr = e->mixed << 5;
+        attr |= e->endian;
+        attr |= e->elsz >> 3;
+        attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
+        return attr;
+}
+static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
+{
+        char *p = buf;
+        /* FIXME: Need more detail analysis of cam/ram */
+        p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
+        return p - buf;
+}
+#define pr_reg(name)                                                    \
+        p += sprintf(p, "%20s: %08x\n",                                 \
+                     __stringify(name), iommu_read_reg(obj, MMU_##name));
+static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
+{
+        char *p = buf;
+        pr_reg(REVISION);
+        pr_reg(SYSCONFIG);
+        pr_reg(SYSSTATUS);
+        pr_reg(IRQSTATUS);
+        pr_reg(IRQENABLE);
+        pr_reg(WALKING_ST);
+        pr_reg(CNTL);
+        pr_reg(FAULT_AD);
+        pr_reg(TTB);
+        pr_reg(LOCK);
+        pr_reg(LD_TLB);
+        pr_reg(CAM);
+        pr_reg(RAM);
+        pr_reg(GFLUSH);
+        pr_reg(FLUSH_ENTRY);
+        pr_reg(READ_CAM);
+        pr_reg(READ_RAM);
+        pr_reg(EMU_FAULT_AD);
+        return p - buf;
+}
+static void omap2_iommu_save_ctx(struct iommu *obj)
+{
+        int i;
+        u32 *p = obj->ctx;
+        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
+                p[i] = iommu_read_reg(obj, i * sizeof(u32));
+                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
+        }
+        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
+}
+static void omap2_iommu_restore_ctx(struct iommu *obj)
+{
+        int i;
+        u32 *p = obj->ctx;
+        for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
+                iommu_write_reg(obj, p[i], i * sizeof(u32));
+                dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
+        }
+        BUG_ON(p[0] != IOMMU_ARCH_VERSION);
+}
+static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
+{
+        e->da           = cr->cam & MMU_CAM_VATAG_MASK;
+        e->pa           = cr->ram & MMU_RAM_PADDR_MASK;
+        e->valid        = cr->cam & MMU_CAM_V;
+        e->pgsz         = cr->cam & MMU_CAM_PGSZ_MASK;
+        e->endian       = cr->ram & MMU_RAM_ENDIAN_MASK;
+        e->elsz         = cr->ram & MMU_RAM_ELSZ_MASK;
+        e->mixed        = cr->ram & MMU_RAM_MIXED;
+}
+static const struct iommu_functions omap2_iommu_ops = {
+        .version        = IOMMU_ARCH_VERSION,
+        .enable         = omap2_iommu_enable,
+        .disable        = omap2_iommu_disable,
+        .fault_isr      = omap2_iommu_fault_isr,
+        .tlb_read_cr    = omap2_tlb_read_cr,
+        .tlb_load_cr    = omap2_tlb_load_cr,
+        .cr_to_e        = omap2_cr_to_e,
+        .cr_to_virt     = omap2_cr_to_virt,
+        .alloc_cr       = omap2_alloc_cr,
+        .cr_valid       = omap2_cr_valid,
+        .dump_cr        = omap2_dump_cr,
+        .get_pte_attr   = omap2_get_pte_attr,
+        .save_ctx       = omap2_iommu_save_ctx,
+        .restore_ctx    = omap2_iommu_restore_ctx,
+        .dump_ctx       = omap2_iommu_dump_ctx,
+};
+static int __init omap2_iommu_init(void)
+{
+        return install_iommu_arch(&omap2_iommu_ops);
+}
+module_init(omap2_iommu_init);
+static void __exit omap2_iommu_exit(void)
+{
+        uninstall_iommu_arch(&omap2_iommu_ops);
+}
+module_exit(omap2_iommu_exit);
+MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
+MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 998c5c45587e..b82863887f10 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -28,7 +28,6 @@
 #define INTC_MIR_CLEAR0         0x0088
 #define INTC_MIR_SET0           0x008c
 #define INTC_PENDING_IRQ0       0x0098
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG        32
@@ -134,7 +133,6 @@ static struct irq_chip omap_irq_chip = {
        .ack    = omap_mask_ack_irq,
        .mask   = omap_mask_irq,
        .unmask = omap_unmask_irq,
-        .disable = omap_mask_irq,
 };
 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
@@ -157,6 +155,22 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
        intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 }
+int omap_irq_pending(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
+                struct omap_irq_bank *bank = irq_banks + i;
+                int irq;
+                for (irq = 0; irq < bank->nr_irqs; irq += 32)
+                        if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
+                                               ((irq >> 5) << 5)))
+                                return 1;
+        }
+        return 0;
+}
 void __init omap_init_irq(void)
 {
        unsigned long nr_of_irqs = 0;
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index dc40b3e72206..9756a878fd90 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -16,8 +16,8 @@
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
-#include <linux/i2c/twl4030.h>
+#include <linux/mmc/host.h>
-#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
 #include <mach/hardware.h>
 #include <mach/control.h>
@@ -26,31 +26,9 @@
 #include "mmc-twl4030.h"
-#if defined(CONFIG_TWL4030_CORE) && \
-        (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
-#define LDO_CLR                 0x00
+#if defined(CONFIG_REGULATOR) && \
-#define VSEL_S2_CLR             0x40
+        (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
-#define VMMC1_DEV_GRP           0x27
-#define VMMC1_CLR               0x00
-#define VMMC1_315V              0x03
-#define VMMC1_300V              0x02
-#define VMMC1_285V              0x01
-#define VMMC1_185V              0x00
-#define VMMC1_DEDICATED         0x2A
-#define VMMC2_DEV_GRP           0x2B
-#define VMMC2_CLR               0x40
-#define VMMC2_315V              0x0c
-#define VMMC2_300V              0x0b
-#define VMMC2_285V              0x0a
-#define VMMC2_280V              0x09
-#define VMMC2_260V              0x08
-#define VMMC2_185V              0x06
-#define VMMC2_DEDICATED         0x2E
-#define VMMC_DEV_GRP_P1         0x20
 static u16 control_pbias_offset;
 static u16 control_devconf1_offset;
@@ -59,19 +37,16 @@ static u16 control_devconf1_offset;
 static struct twl_mmc_controller {
        struct omap_mmc_platform_data   *mmc;
-        u8              twl_vmmc_dev_grp;
+        /* Vcc == configured supply
-        u8              twl_mmc_dedicated;
+         * Vcc_alt == optional
-        char            name[HSMMC_NAME_LEN + 1];
+         *   -  MMC1, supply for DAT4..DAT7
-} hsmmc[OMAP34XX_NR_MMC] = {
+         *   -  MMC2/MMC2, external level shifter voltage supply, for
-        {
+         *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
-                .twl_vmmc_dev_grp               = VMMC1_DEV_GRP,
+         */
-                .twl_mmc_dedicated              = VMMC1_DEDICATED,
+        struct regulator                *vcc;
-        },
+        struct regulator                *vcc_aux;
-        {
+        char                            name[HSMMC_NAME_LEN + 1];
-                .twl_vmmc_dev_grp               = VMMC2_DEV_GRP,
+} hsmmc[OMAP34XX_NR_MMC];
-                .twl_mmc_dedicated              = VMMC2_DEDICATED,
-        },
-};
 static int twl_mmc_card_detect(int irq)
 {
@@ -117,16 +92,60 @@ static int twl_mmc_late_init(struct device *dev)
        int ret = 0;
        int i;
-        ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
+        /* MMC/SD/SDIO doesn't require a card detect switch */
-        if (ret)
+        if (gpio_is_valid(mmc->slots[0].switch_pin)) {
-                goto done;
+                ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
-        ret = gpio_direction_input(mmc->slots[0].switch_pin);
+                if (ret)
-        if (ret)
+                        goto done;
-                goto err;
+                ret = gpio_direction_input(mmc->slots[0].switch_pin);
+                if (ret)
+                        goto err;
+        }
+        /* require at least main regulator */
        for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
                if (hsmmc[i].name == mmc->slots[0].name) {
+                        struct regulator *reg;
                        hsmmc[i].mmc = mmc;
+                        reg = regulator_get(dev, "vmmc");
+                        if (IS_ERR(reg)) {
+                                dev_dbg(dev, "vmmc regulator missing\n");
+                                /* HACK: until fixed.c regulator is usable,
+                                 * we don't require a main regulator
+                                 * for MMC2 or MMC3
+                                 */
+                                if (i != 0)
+                                        break;
+                                ret = PTR_ERR(reg);
+                                goto err;
+                        }
+                        hsmmc[i].vcc = reg;
+                        mmc->slots[0].ocr_mask = mmc_regulator_get_ocrmask(reg);
+                        /* allow an aux regulator */
+                        reg = regulator_get(dev, "vmmc_aux");
+                        hsmmc[i].vcc_aux = IS_ERR(reg) ? NULL : reg;
+                        /* UGLY HACK:  workaround regulator framework bugs.
+                         * When the bootloader leaves a supply active, it's
+                         * initialized with zero usecount ... and we can't
+                         * disable it without first enabling it.  Until the
+                         * framework is fixed, we need a workaround like this
+                         * (which is safe for MMC, but not in general).
+                         */
+                        if (regulator_is_enabled(hsmmc[i].vcc) > 0) {
+                                regulator_enable(hsmmc[i].vcc);
+                                regulator_disable(hsmmc[i].vcc);
+                        }
+                        if (hsmmc[i].vcc_aux) {
+                                if (regulator_is_enabled(reg) > 0) {
+                                        regulator_enable(reg);
+                                        regulator_disable(reg);
+                                }
+                        }
                        break;
                }
        }
@@ -173,96 +192,6 @@ static int twl_mmc_resume(struct device *dev, int slot)
 #define twl_mmc_resume  NULL
 #endif
-/*
- * Sets the MMC voltage in twl4030
- */
-#define MMC1_OCR        (MMC_VDD_165_195 \
-                |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
-#define MMC2_OCR        (MMC_VDD_165_195 \
-                |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \
-                |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32)
-static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
-{
-        int ret;
-        u8 vmmc = 0, dev_grp_val;
-        if (!vdd)
-                goto doit;
-        if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) {
-                /* VMMC1:  max 220 mA.  And for 8-bit mode,
-                 * VSIM:  max 50 mA
-                 */
-                switch (1 << vdd) {
-                case MMC_VDD_165_195:
-                        vmmc = VMMC1_185V;
-                        /* and VSIM_180V */
-                        break;
-                case MMC_VDD_28_29:
-                        vmmc = VMMC1_285V;
-                        /* and VSIM_280V */
-                        break;
-                case MMC_VDD_29_30:
-                case MMC_VDD_30_31:
-                        vmmc = VMMC1_300V;
-                        /* and VSIM_300V */
-                        break;
-                case MMC_VDD_31_32:
-                        vmmc = VMMC1_315V;
-                        /* error if VSIM needed */
-                        break;
-                default:
-                        return -EINVAL;
-                }
-        } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) {
-                /* VMMC2:  max 100 mA */
-                switch (1 << vdd) {
-                case MMC_VDD_165_195:
-                        vmmc = VMMC2_185V;
-                        break;
-                case MMC_VDD_25_26:
-                case MMC_VDD_26_27:
-                        vmmc = VMMC2_260V;
-                        break;
-                case MMC_VDD_27_28:
-                        vmmc = VMMC2_280V;
-                        break;
-                case MMC_VDD_28_29:
-                        vmmc = VMMC2_285V;
-                        break;
-                case MMC_VDD_29_30:
-                case MMC_VDD_30_31:
-                        vmmc = VMMC2_300V;
-                        break;
-                case MMC_VDD_31_32:
-                        vmmc = VMMC2_315V;
-                        break;
-                default:
-                        return -EINVAL;
-                }
-        } else {
-                return -EINVAL;
-        }
-doit:
-        if (vdd)
-                dev_grp_val = VMMC_DEV_GRP_P1;  /* Power up */
-        else
-                dev_grp_val = LDO_CLR;          /* Power down */
-        ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-                                        dev_grp_val, c->twl_vmmc_dev_grp);
-        if (ret || !vdd)
-                return ret;
-        ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
-                                        vmmc, c->twl_mmc_dedicated);
-        return ret;
-}
 static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
                                int vdd)
 {
@@ -273,11 +202,13 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
        /*
         * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
-         * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both
+         * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
         * 1.8V and 3.0V modes, controlled by the PBIAS register.
         *
         * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
         * is most naturally TWL VSIM; those pins also use PBIAS.
+         *
+         * FIXME handle VMMC1A as needed ...
         */
        if (power_on) {
                if (cpu_is_omap2430()) {
@@ -300,7 +231,7 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
                reg &= ~OMAP2_PBIASLITEPWRDNZ0;
                omap_ctrl_writel(reg, control_pbias_offset);
-                ret = twl_mmc_set_voltage(c, vdd);
+                ret = mmc_regulator_set_ocr(c->vcc, vdd);
                /* 100ms delay required for PBIAS configuration */
                msleep(100);
@@ -316,7 +247,7 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
                reg &= ~OMAP2_PBIASLITEPWRDNZ0;
                omap_ctrl_writel(reg, control_pbias_offset);
-                ret = twl_mmc_set_voltage(c, 0);
+                ret = mmc_regulator_set_ocr(c->vcc, 0);
                /* 100ms delay required for PBIAS configuration */
                msleep(100);
@@ -329,19 +260,33 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
        return ret;
 }
-static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
+static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd)
 {
-        int ret;
+        int ret = 0;
        struct twl_mmc_controller *c = &hsmmc[1];
        struct omap_mmc_platform_data *mmc = dev->platform_data;
+        /* If we don't see a Vcc regulator, assume it's a fixed
+         * voltage always-on regulator.
+         */
+        if (!c->vcc)
+                return 0;
        /*
-         * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP
+         * Assume Vcc regulator is used only to power the card ... OMAP
         * VDDS is used to power the pins, optionally with a transceiver to
         * support cards using voltages other than VDDS (1.8V nominal).  When a
         * transceiver is used, DAT3..7 are muxed as transceiver control pins.
+         *
+         * In some cases this regulator won't support enable/disable;
+         * e.g. it's a fixed rail for a WLAN chip.
+         *
+         * In other cases vcc_aux switches interface power.  Example, for
+         * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
+         * chips/cards need an interface voltage rail too.
         */
        if (power_on) {
+                /* only MMC2 supports a CLKIN */
                if (mmc->slots[0].internal_clock) {
                        u32 reg;
@@ -349,24 +294,23 @@ static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vd
                        reg |= OMAP2_MMCSDIO2ADPCLKISEL;
                        omap_ctrl_writel(reg, control_devconf1_offset);
                }
-                ret = twl_mmc_set_voltage(c, vdd);
+                ret = mmc_regulator_set_ocr(c->vcc, vdd);
+                /* enable interface voltage rail, if needed */
+                if (ret == 0 && c->vcc_aux) {
+                        ret = regulator_enable(c->vcc_aux);
+                        if (ret < 0)
+                                ret = mmc_regulator_set_ocr(c->vcc, 0);
+                }
        } else {
-                ret = twl_mmc_set_voltage(c, 0);
+                if (c->vcc_aux && (ret = regulator_is_enabled(c->vcc_aux)) > 0)
+                        ret = regulator_disable(c->vcc_aux);
+                if (ret == 0)
+                        ret = mmc_regulator_set_ocr(c->vcc, 0);
        }
        return ret;
 }
-static int twl_mmc3_set_power(struct device *dev, int slot, int power_on,
-                int vdd)
-{
-        /*
-         * Assume MMC3 has self-powered device connected, for example on-board
-         * chip with external power source.
-         */
-        return 0;
-}
 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
 void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
@@ -412,10 +356,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
                mmc->slots[0].wires = c->wires;
                mmc->slots[0].internal_clock = !c->ext_clock;
                mmc->dma_mask = 0xffffffff;
+                mmc->init = twl_mmc_late_init;
-                /* note: twl4030 card detect GPIOs normally switch VMMCx ... */
+                /* note: twl4030 card detect GPIOs can disable VMMCx ... */
                if (gpio_is_valid(c->gpio_cd)) {
-                        mmc->init = twl_mmc_late_init;
                        mmc->cleanup = twl_mmc_cleanup;
                        mmc->suspend = twl_mmc_suspend;
                        mmc->resume = twl_mmc_resume;
@@ -439,26 +383,28 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
                } else
                        mmc->slots[0].gpio_wp = -EINVAL;
-                /* NOTE:  we assume OMAP's MMC1 and MMC2 use
+                /* NOTE:  MMC slots should have a Vcc regulator set up.
-                 * the TWL4030's VMMC1 and VMMC2, respectively;
+                 * This may be from a TWL4030-family chip, another
-                 * and that MMC3 device has it's own power source.
+                 * controllable regulator, or a fixed supply.
+                 *
+                 * temporary HACK: ocr_mask instead of fixed supply
                 */
+                mmc->slots[0].ocr_mask = c->ocr_mask;
                switch (c->mmc) {
                case 1:
+                        /* on-chip level shifting via PBIAS0/PBIAS1 */
                        mmc->slots[0].set_power = twl_mmc1_set_power;
-                        mmc->slots[0].ocr_mask = MMC1_OCR;
                        break;
                case 2:
-                        mmc->slots[0].set_power = twl_mmc2_set_power;
+                        if (c->ext_clock)
-                        if (c->transceiver)
+                                c->transceiver = 1;
-                                mmc->slots[0].ocr_mask = MMC2_OCR;
+                        if (c->transceiver && c->wires > 4)
-                        else
+                                c->wires = 4;
-                                mmc->slots[0].ocr_mask = MMC_VDD_165_195;
+                        /* FALLTHROUGH */
-                        break;
                case 3:
-                        mmc->slots[0].set_power = twl_mmc3_set_power;
+                        /* off-chip level shifting, or none */
-                        mmc->slots[0].ocr_mask = MMC_VDD_165_195;
+                        mmc->slots[0].set_power = twl_mmc23_set_power;
                        break;
                default:
                        pr_err("MMC%d configuration not supported!\n", c->mmc);
diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/mmc-twl4030.h
index ea59e8624290..3807c45c9a6c 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.h
+++ b/arch/arm/mach-omap2/mmc-twl4030.h
@@ -16,9 +16,10 @@ struct twl4030_hsmmc_info {
        int     gpio_wp;        /* or -EINVAL */
        char    *name;          /* or NULL for default */
        struct device *dev;     /* returned: pointer to mmc adapter */
+        int     ocr_mask;       /* temporary HACK */
 };
-#if     defined(CONFIG_TWL4030_CORE) && \
+#if defined(CONFIG_REGULATOR) && \
        (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
new file mode 100644
index 000000000000..4afadba09477
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -0,0 +1,46 @@
+/*
+ * Secondary CPU startup routine source file.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Author:
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Interface functions needed for the SMP. This file is based on arm
+ * realview smp platform.
+ * Copyright (c) 2003 ARM Limited.
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+/* Physical address needed since MMU not enabled yet on secondary core */
+#define OMAP4_AUX_CORE_BOOT1_PA                 0x48281804
+        __INIT
+/*
+ * OMAP4 specific entry point for secondary CPU to jump from ROM
+ * code.  This routine also provides a holding flag into which
+ * secondary core is held until we're ready for it to initialise.
+ * The primary core will update the this flag using a hardware
+ * register AuxCoreBoot1.
+ */
+ENTRY(omap_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #0x0f
+hold:   ldr     r1, =OMAP4_AUX_CORE_BOOT1_PA    @ read from AuxCoreBoot1
+        ldr     r2, [r1]
+        cmp     r2, r0
+        bne     hold
+        /*
+         * we've been released from the cpu_release,secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
new file mode 100644
index 000000000000..8fe8d230f21b
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -0,0 +1,178 @@
+/*
+ * OMAP4 SMP source file. It contains platform specific fucntions
+ * needed for the linux smp kernel.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Author:
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Platform file needed for the OMAP4 SMP. This file is based on arm
+ * realview smp platform.
+ * * Copyright (c) 2002 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
+#include <mach/hardware.h>
+/* Registers used for communicating startup information */
+#define OMAP4_AUXCOREBOOT_REG0          (OMAP44XX_VA_WKUPGEN_BASE + 0x800)
+#define OMAP4_AUXCOREBOOT_REG1          (OMAP44XX_VA_WKUPGEN_BASE + 0x804)
+/* SCU base address */
+static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE;
+/*
+ * Use SCU config register to count number of cores
+ */
+static inline unsigned int get_core_count(void)
+{
+        if (scu_base)
+                return scu_get_core_count(scu_base);
+        return 1;
+}
+static DEFINE_SPINLOCK(boot_lock);
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        trace_hardirqs_off();
+        /*
+         * If any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+        /*
+         * Set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+        /*
+         * Update the AuxCoreBoot1 with boot state for secondary core.
+         * omap_secondary_startup() routine will hold the secondary core till
+         * the AuxCoreBoot1 register is updated with cpu state
+         * A barrier is added to ensure that write buffer is drained
+         */
+        __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1);
+        smp_wmb();
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout))
+                ;
+        /*
+         * Now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+        return 0;
+}
+static void __init wakeup_secondary(void)
+{
+        /*
+         * Write the address of secondary startup routine into the
+         * AuxCoreBoot0 where ROM code will jump and start executing
+         * on secondary core once out of WFE
+         * A barrier is added to ensure that write buffer is drained
+         */
+        __raw_writel(virt_to_phys(omap_secondary_startup),         \
+                                        OMAP4_AUXCOREBOOT_REG0);
+        smp_wmb();
+        /*
+         * Send a 'sev' to wake the secondary core from WFE.
+         */
+        set_event();
+        mb();
+}
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+        unsigned int i, ncores = get_core_count();
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+        unsigned int ncores = get_core_count();
+        unsigned int cpu = smp_processor_id();
+        int i;
+        /* sanity check */
+        if (ncores == 0) {
+                printk(KERN_ERR
+                       "OMAP4: strange core count of 0? Default to 1\n");
+                ncores = 1;
+        }
+        if (ncores > NR_CPUS) {
+                printk(KERN_WARNING
+                       "OMAP4: no. of cores (%d) greater than configured "
+                       "maximum of %d - clipping\n",
+                       ncores, NR_CPUS);
+                ncores = NR_CPUS;
+        }
+        smp_store_cpu_info(cpu);
+        /*
+         * are we trying to boot more cores than exist?
+         */
+        if (max_cpus > ncores)
+                max_cpus = ncores;
+        /*
+         * Initialise the present map, which describes the set of CPUs
+         * actually populated at the present time.
+         */
+        for (i = 0; i < max_cpus; i++)
+                set_cpu_present(i, true);
+        if (max_cpus > 1) {
+                /*
+                 * Enable the local timer or broadcast device for the
+                 * boot CPU, but only if we have more than one CPU.
+                 */
+                percpu_timer_setup();
+                /*
+                 * Initialise the SCU and wake up the secondary core using
+                 * wakeup_secondary().
+                 */
+                scu_enable(scu_base);
+                wakeup_secondary();
+        }
+}
diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c
new file mode 100644
index 000000000000..194189c746c2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3-iommu.c
@@ -0,0 +1,105 @@
+/*
+ * omap iommu: omap3 device registration
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/platform_device.h>
+#include <mach/iommu.h>
+#define OMAP3_MMU1_BASE 0x480bd400
+#define OMAP3_MMU2_BASE 0x5d000000
+#define OMAP3_MMU1_IRQ  24
+#define OMAP3_MMU2_IRQ  28
+static unsigned long iommu_base[] __initdata = {
+        OMAP3_MMU1_BASE,
+        OMAP3_MMU2_BASE,
+};
+static int iommu_irq[] __initdata = {
+        OMAP3_MMU1_IRQ,
+        OMAP3_MMU2_IRQ,
+};
+static const struct iommu_platform_data omap3_iommu_pdata[] __initconst = {
+        {
+                .name = "isp",
+                .nr_tlb_entries = 8,
+                .clk_name = "cam_ick",
+        },
+#if defined(CONFIG_MPU_BRIDGE_IOMMU)
+        {
+                .name = "iva2",
+                .nr_tlb_entries = 32,
+                .clk_name = "iva2_ck",
+        },
+#endif
+};
+#define NR_IOMMU_DEVICES ARRAY_SIZE(omap3_iommu_pdata)
+static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES];
+static int __init omap3_iommu_init(void)
+{
+        int i, err;
+        for (i = 0; i < NR_IOMMU_DEVICES; i++) {
+                struct platform_device *pdev;
+                struct resource res[2];
+                pdev = platform_device_alloc("omap-iommu", i);
+                if (!pdev) {
+                        err = -ENOMEM;
+                        goto err_out;
+                }
+                memset(res, 0,  sizeof(res));
+                res[0].start = iommu_base[i];
+                res[0].end = iommu_base[i] + MMU_REG_SIZE - 1;
+                res[0].flags = IORESOURCE_MEM;
+                res[1].start = res[1].end = iommu_irq[i];
+                res[1].flags = IORESOURCE_IRQ;
+                err = platform_device_add_resources(pdev, res,
+                                                    ARRAY_SIZE(res));
+                if (err)
+                        goto err_out;
+                err = platform_device_add_data(pdev, &omap3_iommu_pdata[i],
+                                               sizeof(omap3_iommu_pdata[0]));
+                if (err)
+                        goto err_out;
+                err = platform_device_add(pdev);
+                if (err)
+                        goto err_out;
+                omap3_iommu_pdev[i] = pdev;
+        }
+        return 0;
+err_out:
+        while (i--)
+                platform_device_put(omap3_iommu_pdev[i]);
+        return err;
+}
+module_init(omap3_iommu_init);
+static void __exit omap3_iommu_exit(void)
+{
+        int i;
+        for (i = 0; i < NR_IOMMU_DEVICES; i++)
+                platform_device_unregister(omap3_iommu_pdev[i]);
+}
+module_exit(omap3_iommu_exit);
+MODULE_AUTHOR("Hiroshi DOYU");
+MODULE_DESCRIPTION("omap iommu: omap3 device registration");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
new file mode 100644
index 000000000000..6cc375a275be
--- /dev/null
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -0,0 +1,152 @@
+/*
+ * OMAP Power Management debug routines
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Copyright (C) 2006-2008 Nokia Corporation
+ *
+ * Written by:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Tony Lindgren
+ * Juha Yrjola
+ * Amit Kucheria <amit.kucheria@nokia.com>
+ * Igor Stoppa <igor.stoppa@nokia.com>
+ * Jouni Hogander
+ *
+ * Based on pm.c for omap2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <mach/clock.h>
+#include <mach/board.h>
+#include "prm.h"
+#include "cm.h"
+#include "pm.h"
+int omap2_pm_debug;
+#define DUMP_PRM_MOD_REG(mod, reg)    \
+        regs[reg_count].name = #mod "." #reg; \
+        regs[reg_count++].val = prm_read_mod_reg(mod, reg)
+#define DUMP_CM_MOD_REG(mod, reg)     \
+        regs[reg_count].name = #mod "." #reg; \
+        regs[reg_count++].val = cm_read_mod_reg(mod, reg)
+#define DUMP_PRM_REG(reg) \
+        regs[reg_count].name = #reg; \
+        regs[reg_count++].val = __raw_readl(reg)
+#define DUMP_CM_REG(reg) \
+        regs[reg_count].name = #reg; \
+        regs[reg_count++].val = __raw_readl(reg)
+#define DUMP_INTC_REG(reg, off) \
+        regs[reg_count].name = #reg; \
+        regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
+void omap2_pm_dump(int mode, int resume, unsigned int us)
+{
+        struct reg {
+                const char *name;
+                u32 val;
+        } regs[32];
+        int reg_count = 0, i;
+        const char *s1 = NULL, *s2 = NULL;
+        if (!resume) {
+#if 0
+                /* MPU */
+                DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
+                DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
+                DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
+                DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
+                DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
+#endif
+#if 0
+                /* INTC */
+                DUMP_INTC_REG(INTC_MIR0, 0x0084);
+                DUMP_INTC_REG(INTC_MIR1, 0x00a4);
+                DUMP_INTC_REG(INTC_MIR2, 0x00c4);
+#endif
+#if 0
+                DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
+                if (cpu_is_omap24xx()) {
+                        DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+                        DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
+                                        OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
+                        DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
+                                        OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
+                }
+                DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
+                DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
+                DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
+                DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
+                DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
+                DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
+                DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
+#endif
+#if 0
+                /* DSP */
+                if (cpu_is_omap24xx()) {
+                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
+                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
+                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
+                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
+                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
+                        DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
+                        DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
+                }
+#endif
+        } else {
+                DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
+                if (cpu_is_omap24xx())
+                        DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
+                DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
+                DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+#if 1
+                DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
+                DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
+                DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
+#endif
+        }
+        switch (mode) {
+        case 0:
+                s1 = "full";
+                s2 = "retention";
+                break;
+        case 1:
+                s1 = "MPU";
+                s2 = "retention";
+                break;
+        case 2:
+                s1 = "MPU";
+                s2 = "idle";
+                break;
+        }
+        if (!resume)
+#ifdef CONFIG_NO_HZ
+                printk(KERN_INFO
+                       "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
+                       jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
+                                        jiffies));
+#else
+                printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
+#endif
+        else
+                printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
+                        us / 1000, us % 1000);
+        for (i = 0; i < reg_count; i++)
+                printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
+}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
deleted file mode 100644
index ea8ceaed09cb..000000000000
--- a/arch/arm/mach-omap2/pm.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/pm.c
- *
- * OMAP2 Power Management Routines
- *
- * Copyright (C) 2006 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Based on pm.c for omap1
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/suspend.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/interrupt.h>
-#include <linux/sysfs.h>
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/atomic.h>
-#include <asm/mach/time.h>
-#include <asm/mach/irq.h>
-#include <mach/irqs.h>
-#include <mach/clock.h>
-#include <mach/sram.h>
-#include <mach/pm.h>
-static struct clk *vclk;
-static void (*omap2_sram_idle)(void);
-static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
-static void (*saved_idle)(void);
-extern void __init pmdomain_init(void);
-extern void pmdomain_set_autoidle(void);
-static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE];
-void omap2_pm_idle(void)
-{
-        local_irq_disable();
-        local_fiq_disable();
-        if (need_resched()) {
-                local_fiq_enable();
-                local_irq_enable();
-                return;
-        }
-        omap2_sram_idle();
-        local_fiq_enable();
-        local_irq_enable();
-}
-static int omap2_pm_prepare(void)
-{
-        /* We cannot sleep in idle until we have resumed */
-        saved_idle = pm_idle;
-        pm_idle = NULL;
-        return 0;
-}
-static int omap2_pm_suspend(void)
-{
-        return 0;
-}
-static int omap2_pm_enter(suspend_state_t state)
-{
-        int ret = 0;
-        switch (state)
-        {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                ret = omap2_pm_suspend();
-                break;
-        default:
-                ret = -EINVAL;
-        }
-        return ret;
-}
-static void omap2_pm_finish(void)
-{
-        pm_idle = saved_idle;
-}
-static struct platform_suspend_ops omap_pm_ops = {
-        .prepare        = omap2_pm_prepare,
-        .enter          = omap2_pm_enter,
-        .finish         = omap2_pm_finish,
-        .valid          = suspend_valid_only_mem,
-};
-static int __init omap2_pm_init(void)
-{
-        return 0;
-}
-__initcall(omap2_pm_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
new file mode 100644
index 000000000000..f7b3baf76678
--- /dev/null
+++ b/arch/arm/mach-omap2/pm.h
@@ -0,0 +1,38 @@
+/*
+ * OMAP2/3 Power Management Routines
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Jouni Hogander
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
+#define __ARCH_ARM_MACH_OMAP2_PM_H
+extern int omap2_pm_init(void);
+extern int omap3_pm_init(void);
+#ifdef CONFIG_PM_DEBUG
+extern void omap2_pm_dump(int mode, int resume, unsigned int us);
+extern int omap2_pm_debug;
+#else
+#define omap2_pm_dump(mode, resume, us)         do {} while (0);
+#define omap2_pm_debug                          0
+#endif /* CONFIG_PM_DEBUG */
+extern void omap24xx_idle_loop_suspend(void);
+extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
+                                        void __iomem *sdrc_power);
+extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
+extern void save_secure_ram_context(u32 *addr);
+extern unsigned int omap24xx_idle_loop_suspend_sz;
+extern unsigned int omap34xx_suspend_sz;
+extern unsigned int save_secure_ram_context_sz;
+extern unsigned int omap24xx_cpu_suspend_sz;
+extern unsigned int omap34xx_cpu_suspend_sz;
+#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
new file mode 100644
index 000000000000..db1025562fb0
--- /dev/null
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -0,0 +1,549 @@
+/*
+ * OMAP2 Power Management Routines
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Copyright (C) 2006-2008 Nokia Corporation
+ *
+ * Written by:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Tony Lindgren
+ * Juha Yrjola
+ * Amit Kucheria <amit.kucheria@nokia.com>
+ * Igor Stoppa <igor.stoppa@nokia.com>
+ *
+ * Based on pm.c for omap1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/suspend.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <linux/interrupt.h>
+#include <linux/sysfs.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/time.h>
+#include <linux/gpio.h>
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
+#include <mach/control.h>
+#include <mach/mux.h>
+#include <mach/dma.h>
+#include <mach/board.h>
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+#include "pm.h"
+#include <mach/powerdomain.h>
+#include <mach/clockdomain.h>
+static void (*omap2_sram_idle)(void);
+static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
+                                  void __iomem *sdrc_power);
+static struct powerdomain *mpu_pwrdm;
+static struct powerdomain *core_pwrdm;
+static struct clockdomain *dsp_clkdm;
+static struct clockdomain *gfx_clkdm;
+static struct clk *osc_ck, *emul_ck;
+static int omap2_fclks_active(void)
+{
+        u32 f1, f2;
+        f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        /* Ignore UART clocks.  These are handled by UART core (serial.c) */
+        f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
+        f2 &= ~OMAP24XX_EN_UART3;
+        if (f1 | f2)
+                return 1;
+        return 0;
+}
+static void omap2_enter_full_retention(void)
+{
+        u32 l;
+        struct timespec ts_preidle, ts_postidle, ts_idle;
+        /* There is 1 reference hold for all children of the oscillator
+         * clock, the following will remove it. If no one else uses the
+         * oscillator itself it will be disabled if/when we enter retention
+         * mode.
+         */
+        clk_disable(osc_ck);
+        /* Clear old wake-up events */
+        /* REVISIT: These write to reserved bits? */
+        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+        /*
+         * Set MPU powerdomain's next power state to RETENTION;
+         * preserve logic state during retention
+         */
+        pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
+        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
+        /* Workaround to kill USB */
+        l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
+        omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
+        omap2_gpio_prepare_for_retention();
+        if (omap2_pm_debug) {
+                omap2_pm_dump(0, 0, 0);
+                getnstimeofday(&ts_preidle);
+        }
+        /* One last check for pending IRQs to avoid extra latency due
+         * to sleeping unnecessarily. */
+        if (omap_irq_pending())
+                goto no_sleep;
+        omap_uart_prepare_idle(0);
+        omap_uart_prepare_idle(1);
+        omap_uart_prepare_idle(2);
+        /* Jump to SRAM suspend code */
+        omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
+                           OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
+                           OMAP_SDRC_REGADDR(SDRC_POWER));
+        omap_uart_resume_idle(2);
+        omap_uart_resume_idle(1);
+        omap_uart_resume_idle(0);
+no_sleep:
+        if (omap2_pm_debug) {
+                unsigned long long tmp;
+                getnstimeofday(&ts_postidle);
+                ts_idle = timespec_sub(ts_postidle, ts_preidle);
+                tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
+                omap2_pm_dump(0, 1, tmp);
+        }
+        omap2_gpio_resume_after_retention();
+        clk_enable(osc_ck);
+        /* clear CORE wake-up events */
+        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
+        prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
+        /* MPU domain wake events */
+        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        if (l & 0x01)
+                prm_write_mod_reg(0x01, OCP_MOD,
+                                  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        if (l & 0x20)
+                prm_write_mod_reg(0x20, OCP_MOD,
+                                  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        /* Mask future PRCM-to-MPU interrupts */
+        prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+}
+static int omap2_i2c_active(void)
+{
+        u32 l;
+        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
+}
+static int sti_console_enabled;
+static int omap2_allow_mpu_retention(void)
+{
+        u32 l;
+        /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
+        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
+                 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
+                 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
+                return 0;
+        /* Check for UART3. */
+        l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        if (l & OMAP24XX_EN_UART3)
+                return 0;
+        if (sti_console_enabled)
+                return 0;
+        return 1;
+}
+static void omap2_enter_mpu_retention(void)
+{
+        int only_idle = 0;
+        struct timespec ts_preidle, ts_postidle, ts_idle;
+        /* Putting MPU into the WFI state while a transfer is active
+         * seems to cause the I2C block to timeout. Why? Good question. */
+        if (omap2_i2c_active())
+                return;
+        /* The peripherals seem not to be able to wake up the MPU when
+         * it is in retention mode. */
+        if (omap2_allow_mpu_retention()) {
+                /* REVISIT: These write to reserved bits? */
+                prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+                prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+                prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+                /* Try to enter MPU retention */
+                prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
+                                  OMAP_LOGICRETSTATE,
+                                  MPU_MOD, PM_PWSTCTRL);
+        } else {
+                /* Block MPU retention */
+                prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
+                only_idle = 1;
+        }
+        if (omap2_pm_debug) {
+                omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
+                getnstimeofday(&ts_preidle);
+        }
+        omap2_sram_idle();
+        if (omap2_pm_debug) {
+                unsigned long long tmp;
+                getnstimeofday(&ts_postidle);
+                ts_idle = timespec_sub(ts_postidle, ts_preidle);
+                tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
+                omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
+        }
+}
+static int omap2_can_sleep(void)
+{
+        if (omap2_fclks_active())
+                return 0;
+        if (osc_ck->usecount > 1)
+                return 0;
+        if (omap_dma_running())
+                return 0;
+        return 1;
+}
+static void omap2_pm_idle(void)
+{
+        local_irq_disable();
+        local_fiq_disable();
+        if (!omap2_can_sleep()) {
+                if (omap_irq_pending())
+                        goto out;
+                omap2_enter_mpu_retention();
+                goto out;
+        }
+        if (omap_irq_pending())
+                goto out;
+        omap2_enter_full_retention();
+out:
+        local_fiq_enable();
+        local_irq_enable();
+}
+static int omap2_pm_prepare(void)
+{
+        /* We cannot sleep in idle until we have resumed */
+        disable_hlt();
+        return 0;
+}
+static int omap2_pm_suspend(void)
+{
+        u32 wken_wkup, mir1;
+        wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+        prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
+        /* Mask GPT1 */
+        mir1 = omap_readl(0x480fe0a4);
+        omap_writel(1 << 5, 0x480fe0ac);
+        omap_uart_prepare_suspend();
+        omap2_enter_full_retention();
+        omap_writel(mir1, 0x480fe0a4);
+        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
+        return 0;
+}
+static int omap2_pm_enter(suspend_state_t state)
+{
+        int ret = 0;
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                ret = omap2_pm_suspend();
+                break;
+        default:
+                ret = -EINVAL;
+        }
+        return ret;
+}
+static void omap2_pm_finish(void)
+{
+        enable_hlt();
+}
+static struct platform_suspend_ops omap_pm_ops = {
+        .prepare        = omap2_pm_prepare,
+        .enter          = omap2_pm_enter,
+        .finish         = omap2_pm_finish,
+        .valid          = suspend_valid_only_mem,
+};
+static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
+{
+        omap2_clkdm_allow_idle(clkdm);
+        return 0;
+}
+static void __init prcm_setup_regs(void)
+{
+        int i, num_mem_banks;
+        struct powerdomain *pwrdm;
+        /* Enable autoidle */
+        prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
+                          OMAP2_PRCM_SYSCONFIG_OFFSET);
+        /* Set all domain wakeup dependencies */
+        prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
+        if (cpu_is_omap2430())
+                prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
+        /*
+         * Set CORE powerdomain memory banks to retain their contents
+         * during RETENTION
+         */
+        num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
+        for (i = 0; i < num_mem_banks; i++)
+                pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
+        /* Set CORE powerdomain's next power state to RETENTION */
+        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
+        /*
+         * Set MPU powerdomain's next power state to RETENTION;
+         * preserve logic state during retention
+         */
+        pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
+        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
+        /* Force-power down DSP, GFX powerdomains */
+        pwrdm = clkdm_get_pwrdm(dsp_clkdm);
+        pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
+        omap2_clkdm_sleep(dsp_clkdm);
+        pwrdm = clkdm_get_pwrdm(gfx_clkdm);
+        pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
+        omap2_clkdm_sleep(gfx_clkdm);
+        /* Enable clockdomain hardware-supervised control for all clkdms */
+        clkdm_for_each(_pm_clkdm_enable_hwsup);
+        /* Enable clock autoidle for all domains */
+        cm_write_mod_reg(OMAP24XX_AUTO_CAM |
+                         OMAP24XX_AUTO_MAILBOXES |
+                         OMAP24XX_AUTO_WDT4 |
+                         OMAP2420_AUTO_WDT3 |
+                         OMAP24XX_AUTO_MSPRO |
+                         OMAP2420_AUTO_MMC |
+                         OMAP24XX_AUTO_FAC |
+                         OMAP2420_AUTO_EAC |
+                         OMAP24XX_AUTO_HDQ |
+                         OMAP24XX_AUTO_UART2 |
+                         OMAP24XX_AUTO_UART1 |
+                         OMAP24XX_AUTO_I2C2 |
+                         OMAP24XX_AUTO_I2C1 |
+                         OMAP24XX_AUTO_MCSPI2 |
+                         OMAP24XX_AUTO_MCSPI1 |
+                         OMAP24XX_AUTO_MCBSP2 |
+                         OMAP24XX_AUTO_MCBSP1 |
+                         OMAP24XX_AUTO_GPT12 |
+                         OMAP24XX_AUTO_GPT11 |
+                         OMAP24XX_AUTO_GPT10 |
+                         OMAP24XX_AUTO_GPT9 |
+                         OMAP24XX_AUTO_GPT8 |
+                         OMAP24XX_AUTO_GPT7 |
+                         OMAP24XX_AUTO_GPT6 |
+                         OMAP24XX_AUTO_GPT5 |
+                         OMAP24XX_AUTO_GPT4 |
+                         OMAP24XX_AUTO_GPT3 |
+                         OMAP24XX_AUTO_GPT2 |
+                         OMAP2420_AUTO_VLYNQ |
+                         OMAP24XX_AUTO_DSS,
+                         CORE_MOD, CM_AUTOIDLE1);
+        cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
+                         OMAP24XX_AUTO_SSI |
+                         OMAP24XX_AUTO_USB,
+                         CORE_MOD, CM_AUTOIDLE2);
+        cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
+                         OMAP24XX_AUTO_GPMC |
+                         OMAP24XX_AUTO_SDMA,
+                         CORE_MOD, CM_AUTOIDLE3);
+        cm_write_mod_reg(OMAP24XX_AUTO_PKA |
+                         OMAP24XX_AUTO_AES |
+                         OMAP24XX_AUTO_RNG |
+                         OMAP24XX_AUTO_SHA |
+                         OMAP24XX_AUTO_DES,
+                         CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
+        cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
+        /* Put DPLL and both APLLs into autoidle mode */
+        cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
+                         (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+                         (0x03 << OMAP24XX_AUTO_54M_SHIFT),
+                         PLL_MOD, CM_AUTOIDLE);
+        cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
+                         OMAP24XX_AUTO_WDT1 |
+                         OMAP24XX_AUTO_MPU_WDT |
+                         OMAP24XX_AUTO_GPIOS |
+                         OMAP24XX_AUTO_32KSYNC |
+                         OMAP24XX_AUTO_GPT1,
+                         WKUP_MOD, CM_AUTOIDLE);
+        /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
+         * stabilisation */
+        prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                          OMAP2_PRCM_CLKSSETUP_OFFSET);
+        /* Configure automatic voltage transition */
+        prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                          OMAP2_PRCM_VOLTSETUP_OFFSET);
+        prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
+                          (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
+                          OMAP24XX_MEMRETCTRL |
+                          (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
+                          (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
+                          OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
+        /* Enable wake-up events */
+        prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
+                          WKUP_MOD, PM_WKEN);
+}
+int __init omap2_pm_init(void)
+{
+        u32 l;
+        if (!cpu_is_omap24xx())
+                return -ENODEV;
+        printk(KERN_INFO "Power Management for OMAP2 initializing\n");
+        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
+        printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
+        /* Look up important powerdomains, clockdomains */
+        mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
+        if (!mpu_pwrdm)
+                pr_err("PM: mpu_pwrdm not found\n");
+        core_pwrdm = pwrdm_lookup("core_pwrdm");
+        if (!core_pwrdm)
+                pr_err("PM: core_pwrdm not found\n");
+        dsp_clkdm = clkdm_lookup("dsp_clkdm");
+        if (!dsp_clkdm)
+                pr_err("PM: mpu_clkdm not found\n");
+        gfx_clkdm = clkdm_lookup("gfx_clkdm");
+        if (!gfx_clkdm)
+                pr_err("PM: gfx_clkdm not found\n");
+        osc_ck = clk_get(NULL, "osc_ck");
+        if (IS_ERR(osc_ck)) {
+                printk(KERN_ERR "could not get osc_ck\n");
+                return -ENODEV;
+        }
+        if (cpu_is_omap242x()) {
+                emul_ck = clk_get(NULL, "emul_ck");
+                if (IS_ERR(emul_ck)) {
+                        printk(KERN_ERR "could not get emul_ck\n");
+                        clk_put(osc_ck);
+                        return -ENODEV;
+                }
+        }
+        prcm_setup_regs();
+        /* Hack to prevent MPU retention when STI console is enabled. */
+        {
+                const struct omap_sti_console_config *sti;
+                sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
+                                      struct omap_sti_console_config);
+                if (sti != NULL && sti->enable)
+                        sti_console_enabled = 1;
+        }
+        /*
+         * We copy the assembler sleep/wakeup routines to SRAM.
+         * These routines need to be in SRAM as that's the only
+         * memory the MPU can see when it wakes up.
+         */
+        if (cpu_is_omap24xx()) {
+                omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
+                                                 omap24xx_idle_loop_suspend_sz);
+                omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
+                                                    omap24xx_cpu_suspend_sz);
+        }
+        suspend_set_ops(&omap_pm_ops);
+        pm_idle = omap2_pm_idle;
+        return 0;
+}
+late_initcall(omap2_pm_init);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
new file mode 100644
index 000000000000..841d4c5ed8be
--- /dev/null
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -0,0 +1,710 @@
+/*
+ * OMAP3 Power Management Routines
+ *
+ * Copyright (C) 2006-2008 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ * Jouni Hogander
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * Based on pm.c for omap1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <mach/sram.h>
+#include <mach/clockdomain.h>
+#include <mach/powerdomain.h>
+#include <mach/control.h>
+#include <mach/serial.h>
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm-regbits-34xx.h"
+#include "prm.h"
+#include "pm.h"
+struct power_state {
+        struct powerdomain *pwrdm;
+        u32 next_state;
+        u32 saved_state;
+        struct list_head node;
+};
+static LIST_HEAD(pwrst_list);
+static void (*_omap_sram_idle)(u32 *addr, int save_state);
+static struct powerdomain *mpu_pwrdm;
+/* PRCM Interrupt Handler for wakeups */
+static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
+{
+        u32 wkst, irqstatus_mpu;
+        u32 fclk, iclk;
+        /* WKUP */
+        wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
+        if (wkst) {
+                iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+                fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+                cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
+                cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
+                prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
+                while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
+                        cpu_relax();
+                cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
+                cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
+        }
+        /* CORE */
+        wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
+        if (wkst) {
+                iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
+                fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
+                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
+                prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
+                while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
+                        cpu_relax();
+                cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
+                cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
+        }
+        wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
+        if (wkst) {
+                iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
+                fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
+                cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+                prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
+                while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
+                        cpu_relax();
+                cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
+                cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+        }
+        /* PER */
+        wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
+        if (wkst) {
+                iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
+                fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
+                cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
+                cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
+                prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
+                while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
+                        cpu_relax();
+                cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
+                cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
+        }
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                /* USBHOST */
+                wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
+                if (wkst) {
+                        iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                               CM_ICLKEN);
+                        fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                               CM_FCLKEN);
+                        cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
+                                            CM_ICLKEN);
+                        cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
+                                            CM_FCLKEN);
+                        prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
+                                          PM_WKST);
+                        while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                                PM_WKST))
+                                cpu_relax();
+                        cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
+                                         CM_ICLKEN);
+                        cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
+                                         CM_FCLKEN);
+                }
+        }
+        irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
+                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
+                cpu_relax();
+        return IRQ_HANDLED;
+}
+static void omap_sram_idle(void)
+{
+        /* Variable to tell what needs to be saved and restored
+         * in omap_sram_idle*/
+        /* save_state = 0 => Nothing to save and restored */
+        /* save_state = 1 => Only L1 and logic lost */
+        /* save_state = 2 => Only L2 lost */
+        /* save_state = 3 => L1, L2 and logic lost */
+        int save_state = 0, mpu_next_state;
+        if (!_omap_sram_idle)
+                return;
+        mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
+        switch (mpu_next_state) {
+        case PWRDM_POWER_RET:
+                /* No need to save context */
+                save_state = 0;
+                break;
+        default:
+                /* Invalid state */
+                printk(KERN_ERR "Invalid mpu state in sram_idle\n");
+                return;
+        }
+        omap2_gpio_prepare_for_retention();
+        omap_uart_prepare_idle(0);
+        omap_uart_prepare_idle(1);
+        omap_uart_prepare_idle(2);
+        _omap_sram_idle(NULL, save_state);
+        cpu_init();
+        omap_uart_resume_idle(2);
+        omap_uart_resume_idle(1);
+        omap_uart_resume_idle(0);
+        omap2_gpio_resume_after_retention();
+}
+/*
+ * Check if functional clocks are enabled before entering
+ * sleep. This function could be behind CONFIG_PM_DEBUG
+ * when all drivers are configuring their sysconfig registers
+ * properly and using their clocks properly.
+ */
+static int omap3_fclks_active(void)
+{
+        u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
+                fck_cam = 0, fck_per = 0, fck_usbhost = 0;
+        fck_core1 = cm_read_mod_reg(CORE_MOD,
+                                    CM_FCLKEN1);
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                fck_core3 = cm_read_mod_reg(CORE_MOD,
+                                            OMAP3430ES2_CM_FCLKEN3);
+                fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+                                          CM_FCLKEN);
+                fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                              CM_FCLKEN);
+        } else
+                fck_sgx = cm_read_mod_reg(GFX_MOD,
+                                          OMAP3430ES2_CM_FCLKEN3);
+        fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
+                                  CM_FCLKEN);
+        fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
+                                  CM_FCLKEN);
+        fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
+                                  CM_FCLKEN);
+        /* Ignore UART clocks.  These are handled by UART core (serial.c) */
+        fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
+        fck_per &= ~OMAP3430_EN_UART3;
+        if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
+            fck_cam | fck_per | fck_usbhost)
+                return 1;
+        return 0;
+}
+static int omap3_can_sleep(void)
+{
+        if (!omap_uart_can_sleep())
+                return 0;
+        if (omap3_fclks_active())
+                return 0;
+        return 1;
+}
+/* This sets pwrdm state (other than mpu & core. Currently only ON &
+ * RET are supported. Function is assuming that clkdm doesn't have
+ * hw_sup mode enabled. */
+static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+{
+        u32 cur_state;
+        int sleep_switch = 0;
+        int ret = 0;
+        if (pwrdm == NULL || IS_ERR(pwrdm))
+                return -EINVAL;
+        while (!(pwrdm->pwrsts & (1 << state))) {
+                if (state == PWRDM_POWER_OFF)
+                        return ret;
+                state--;
+        }
+        cur_state = pwrdm_read_next_pwrst(pwrdm);
+        if (cur_state == state)
+                return ret;
+        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
+                omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+                sleep_switch = 1;
+                pwrdm_wait_transition(pwrdm);
+        }
+        ret = pwrdm_set_next_pwrst(pwrdm, state);
+        if (ret) {
+                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
+                       pwrdm->name);
+                goto err;
+        }
+        if (sleep_switch) {
+                omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+                pwrdm_wait_transition(pwrdm);
+        }
+err:
+        return ret;
+}
+static void omap3_pm_idle(void)
+{
+        local_irq_disable();
+        local_fiq_disable();
+        if (!omap3_can_sleep())
+                goto out;
+        if (omap_irq_pending())
+                goto out;
+        omap_sram_idle();
+out:
+        local_fiq_enable();
+        local_irq_enable();
+}
+static int omap3_pm_prepare(void)
+{
+        disable_hlt();
+        return 0;
+}
+static int omap3_pm_suspend(void)
+{
+        struct power_state *pwrst;
+        int state, ret = 0;
+        /* Read current next_pwrsts */
+        list_for_each_entry(pwrst, &pwrst_list, node)
+                pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+        /* Set ones wanted by suspend */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
+                        goto restore;
+                if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
+                        goto restore;
+        }
+        omap_uart_prepare_suspend();
+        omap_sram_idle();
+restore:
+        /* Restore next_pwrsts */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
+                if (state > pwrst->next_state) {
+                        printk(KERN_INFO "Powerdomain (%s) didn't enter "
+                               "target state %d\n",
+                               pwrst->pwrdm->name, pwrst->next_state);
+                        ret = -1;
+                }
+        }
+        if (ret)
+                printk(KERN_ERR "Could not enter target state in pm_suspend\n");
+        else
+                printk(KERN_INFO "Successfully put all powerdomains "
+                       "to target state\n");
+        return ret;
+}
+static int omap3_pm_enter(suspend_state_t state)
+{
+        int ret = 0;
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                ret = omap3_pm_suspend();
+                break;
+        default:
+                ret = -EINVAL;
+        }
+        return ret;
+}
+static void omap3_pm_finish(void)
+{
+        enable_hlt();
+}
+static struct platform_suspend_ops omap_pm_ops = {
+        .prepare        = omap3_pm_prepare,
+        .enter          = omap3_pm_enter,
+        .finish         = omap3_pm_finish,
+        .valid          = suspend_valid_only_mem,
+};
+/**
+ * omap3_iva_idle(): ensure IVA is in idle so it can be put into
+ *                   retention
+ *
+ * In cases where IVA2 is activated by bootcode, it may prevent
+ * full-chip retention or off-mode because it is not idle.  This
+ * function forces the IVA2 into idle state so it can go
+ * into retention/off and thus allow full-chip retention/off.
+ *
+ **/
+static void __init omap3_iva_idle(void)
+{
+        /* ensure IVA2 clock is disabled */
+        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        /* if no clock activity, nothing else to do */
+        if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
+              OMAP3430_CLKACTIVITY_IVA2_MASK))
+                return;
+        /* Reset IVA2 */
+        prm_write_mod_reg(OMAP3430_RST1_IVA2 |
+                          OMAP3430_RST2_IVA2 |
+                          OMAP3430_RST3_IVA2,
+                          OMAP3430_IVA2_MOD, RM_RSTCTRL);
+        /* Enable IVA2 clock */
+        cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
+                         OMAP3430_IVA2_MOD, CM_FCLKEN);
+        /* Set IVA2 boot mode to 'idle' */
+        omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
+                         OMAP343X_CONTROL_IVA2_BOOTMOD);
+        /* Un-reset IVA2 */
+        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
+        /* Disable IVA2 clock */
+        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        /* Reset IVA2 */
+        prm_write_mod_reg(OMAP3430_RST1_IVA2 |
+                          OMAP3430_RST2_IVA2 |
+                          OMAP3430_RST3_IVA2,
+                          OMAP3430_IVA2_MOD, RM_RSTCTRL);
+}
+static void __init omap3_d2d_idle(void)
+{
+        u16 mask, padconf;
+        /* In a stand alone OMAP3430 where there is not a stacked
+         * modem for the D2D Idle Ack and D2D MStandby must be pulled
+         * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
+         * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
+        mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
+        padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
+        padconf |= mask;
+        omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
+        padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
+        padconf |= mask;
+        omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
+        /* reset modem */
+        prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
+                          OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
+                          CORE_MOD, RM_RSTCTRL);
+        prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
+}
+static void __init prcm_setup_regs(void)
+{
+        /* XXX Reset all wkdeps. This should be done when initializing
+         * powerdomains */
+        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+        prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+                prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+        } else
+                prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+        /*
+         * Enable interface clock autoidle for all modules.
+         * Note that in the long run this should be done by clockfw
+         */
+        cm_write_mod_reg(
+                OMAP3430_AUTO_MODEM |
+                OMAP3430ES2_AUTO_MMC3 |
+                OMAP3430ES2_AUTO_ICR |
+                OMAP3430_AUTO_AES2 |
+                OMAP3430_AUTO_SHA12 |
+                OMAP3430_AUTO_DES2 |
+                OMAP3430_AUTO_MMC2 |
+                OMAP3430_AUTO_MMC1 |
+                OMAP3430_AUTO_MSPRO |
+                OMAP3430_AUTO_HDQ |
+                OMAP3430_AUTO_MCSPI4 |
+                OMAP3430_AUTO_MCSPI3 |
+                OMAP3430_AUTO_MCSPI2 |
+                OMAP3430_AUTO_MCSPI1 |
+                OMAP3430_AUTO_I2C3 |
+                OMAP3430_AUTO_I2C2 |
+                OMAP3430_AUTO_I2C1 |
+                OMAP3430_AUTO_UART2 |
+                OMAP3430_AUTO_UART1 |
+                OMAP3430_AUTO_GPT11 |
+                OMAP3430_AUTO_GPT10 |
+                OMAP3430_AUTO_MCBSP5 |
+                OMAP3430_AUTO_MCBSP1 |
+                OMAP3430ES1_AUTO_FAC | /* This is es1 only */
+                OMAP3430_AUTO_MAILBOXES |
+                OMAP3430_AUTO_OMAPCTRL |
+                OMAP3430ES1_AUTO_FSHOSTUSB |
+                OMAP3430_AUTO_HSOTGUSB |
+                OMAP3430_AUTO_SAD2D |
+                OMAP3430_AUTO_SSI,
+                CORE_MOD, CM_AUTOIDLE1);
+        cm_write_mod_reg(
+                OMAP3430_AUTO_PKA |
+                OMAP3430_AUTO_AES1 |
+                OMAP3430_AUTO_RNG |
+                OMAP3430_AUTO_SHA11 |
+                OMAP3430_AUTO_DES1,
+                CORE_MOD, CM_AUTOIDLE2);
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                cm_write_mod_reg(
+                        OMAP3430_AUTO_MAD2D |
+                        OMAP3430ES2_AUTO_USBTLL,
+                        CORE_MOD, CM_AUTOIDLE3);
+        }
+        cm_write_mod_reg(
+                OMAP3430_AUTO_WDT2 |
+                OMAP3430_AUTO_WDT1 |
+                OMAP3430_AUTO_GPIO1 |
+                OMAP3430_AUTO_32KSYNC |
+                OMAP3430_AUTO_GPT12 |
+                OMAP3430_AUTO_GPT1 ,
+                WKUP_MOD, CM_AUTOIDLE);
+        cm_write_mod_reg(
+                OMAP3430_AUTO_DSS,
+                OMAP3430_DSS_MOD,
+                CM_AUTOIDLE);
+        cm_write_mod_reg(
+                OMAP3430_AUTO_CAM,
+                OMAP3430_CAM_MOD,
+                CM_AUTOIDLE);
+        cm_write_mod_reg(
+                OMAP3430_AUTO_GPIO6 |
+                OMAP3430_AUTO_GPIO5 |
+                OMAP3430_AUTO_GPIO4 |
+                OMAP3430_AUTO_GPIO3 |
+                OMAP3430_AUTO_GPIO2 |
+                OMAP3430_AUTO_WDT3 |
+                OMAP3430_AUTO_UART3 |
+                OMAP3430_AUTO_GPT9 |
+                OMAP3430_AUTO_GPT8 |
+                OMAP3430_AUTO_GPT7 |
+                OMAP3430_AUTO_GPT6 |
+                OMAP3430_AUTO_GPT5 |
+                OMAP3430_AUTO_GPT4 |
+                OMAP3430_AUTO_GPT3 |
+                OMAP3430_AUTO_GPT2 |
+                OMAP3430_AUTO_MCBSP4 |
+                OMAP3430_AUTO_MCBSP3 |
+                OMAP3430_AUTO_MCBSP2,
+                OMAP3430_PER_MOD,
+                CM_AUTOIDLE);
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                cm_write_mod_reg(
+                        OMAP3430ES2_AUTO_USBHOST,
+                        OMAP3430ES2_USBHOST_MOD,
+                        CM_AUTOIDLE);
+        }
+        /*
+         * Set all plls to autoidle. This is needed until autoidle is
+         * enabled by clockfw
+         */
+        cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
+                         OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+        cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
+                         MPU_MOD,
+                         CM_AUTOIDLE2);
+        cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+                         (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
+                         PLL_MOD,
+                         CM_AUTOIDLE);
+        cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+                         PLL_MOD,
+                         CM_AUTOIDLE2);
+        /*
+         * Enable control of expternal oscillator through
+         * sys_clkreq. In the long run clock framework should
+         * take care of this.
+         */
+        prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
+                             1 << OMAP_AUTOEXTCLKMODE_SHIFT,
+                             OMAP3430_GR_MOD,
+                             OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+        /* setup wakup source */
+        prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
+                          OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
+                          WKUP_MOD, PM_WKEN);
+        /* No need to write EN_IO, that is always enabled */
+        prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
+                          OMAP3430_EN_GPT12,
+                          WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
+        /* For some reason IO doesn't generate wakeup event even if
+         * it is selected to mpu wakeup goup */
+        prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
+                          OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        /* Don't attach IVA interrupts */
+        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+        /* Clear any pending 'reset' flags */
+        prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+        /* Clear any pending PRCM interrupts */
+        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        omap3_iva_idle();
+        omap3_d2d_idle();
+}
+static int __init pwrdms_setup(struct powerdomain *pwrdm)
+{
+        struct power_state *pwrst;
+        if (!pwrdm->pwrsts)
+                return 0;
+        pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
+        if (!pwrst)
+                return -ENOMEM;
+        pwrst->pwrdm = pwrdm;
+        pwrst->next_state = PWRDM_POWER_RET;
+        list_add(&pwrst->node, &pwrst_list);
+        if (pwrdm_has_hdwr_sar(pwrdm))
+                pwrdm_enable_hdwr_sar(pwrdm);
+        return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+}
+/*
+ * Enable hw supervised mode for all clockdomains if it's
+ * supported. Initiate sleep transition for other clockdomains, if
+ * they are not used
+ */
+static int __init clkdms_setup(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+                omap2_clkdm_allow_idle(clkdm);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+                 atomic_read(&clkdm->usecount) == 0)
+                omap2_clkdm_sleep(clkdm);
+        return 0;
+}
+int __init omap3_pm_init(void)
+{
+        struct power_state *pwrst, *tmp;
+        int ret;
+        if (!cpu_is_omap34xx())
+                return -ENODEV;
+        printk(KERN_ERR "Power Management for TI OMAP3.\n");
+        /* XXX prcm_setup_regs needs to be before enabling hw
+         * supervised mode for powerdomains */
+        prcm_setup_regs();
+        ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
+                          (irq_handler_t)prcm_interrupt_handler,
+                          IRQF_DISABLED, "prcm", NULL);
+        if (ret) {
+                printk(KERN_ERR "request_irq failed to register for 0x%x\n",
+                       INT_34XX_PRCM_MPU_IRQ);
+                goto err1;
+        }
+        ret = pwrdm_for_each(pwrdms_setup);
+        if (ret) {
+                printk(KERN_ERR "Failed to setup powerdomains\n");
+                goto err2;
+        }
+        (void) clkdm_for_each(clkdms_setup);
+        mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
+        if (mpu_pwrdm == NULL) {
+                printk(KERN_ERR "Failed to get mpu_pwrdm\n");
+                goto err2;
+        }
+        _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
+                                         omap34xx_cpu_suspend_sz);
+        suspend_set_ops(&omap_pm_ops);
+        pm_idle = omap3_pm_idle;
+err1:
+        return ret;
+err2:
+        free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
+        list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
+                list_del(&pwrst->node);
+                kfree(pwrst);
+        }
+        return ret;
+}
+late_initcall(omap3_pm_init);
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 812d50ee495d..cb1ae84e0925 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -276,6 +276,8 @@
 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
 #define OMAP3430_EN_GPIO1                               (1 << 3)
 #define OMAP3430_EN_GPIO1_SHIFT                         3
+#define OMAP3430_EN_GPT12                               (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT                         1
 #define OMAP3430_EN_GPT1                                (1 << 0)
 #define OMAP3430_EN_GPT1_SHIFT                          0
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 826d326b8062..9937e2814696 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -16,17 +16,12 @@
 #include "prcm-common.h"
-#ifndef __ASSEMBLER__
-#define OMAP_PRM_REGADDR(module, reg)                                   \
-                        IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
-#else
 #define OMAP2420_PRM_REGADDR(module, reg)                               \
                        IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
 #define OMAP2430_PRM_REGADDR(module, reg)                               \
                        IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
 #define OMAP34XX_PRM_REGADDR(module, reg)                               \
                        IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
-#endif
 /*
 * Architecture-specific global PRM registers
@@ -38,80 +33,132 @@
 *
 */
-/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */
+#define OMAP2_PRCM_REVISION_OFFSET      0x0000
-#define OMAP24XX_PRCM_VOLTCTRL_OFFSET           0x0050
+#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET        0x0080
+#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
+#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
-/* 242x GR_MOD registers, use these only for assembly code */
-#define OMAP242X_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-                                                OMAP24XX_PRCM_VOLTCTRL_OFFSET)
+#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP242X_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
-                                                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
+#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
-/* 243x GR_MOD registers, use these only for assembly code */
+#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
-#define OMAP243X_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
-                                                OMAP24XX_PRCM_VOLTCTRL_OFFSET)
+#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
-#define OMAP243X_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD,   \
+#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-                                                OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
+#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
+#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
-/* These will disappear */
+#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
-#define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
+#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
-#define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
-#define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
-#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
-#define OMAP24XX_PRCM_CLKCFG_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP24XX_PRCM_CLKCFG_STATUS     OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
-#define OMAP24XX_PRCM_VOLTSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
-#define OMAP24XX_PRCM_CLKSSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP24XX_PRCM_POLCTRL           OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
+#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_PRM_REVISION           OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
-#define OMAP3430_PRM_SYSCONFIG          OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
+#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
-#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP3430_PRM_IRQENABLE_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP3430_PRM_VC_SMPS_SA         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP3430_PRM_VC_CH_CONF         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP3430_PRM_VC_I2C_CFG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
-#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
-#define OMAP3430_PRM_RSTCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3_PRM_REVISION_OFFSET       0x0004
-#define OMAP3430_PRM_RSTTIME            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
-#define OMAP3430_PRM_RSTST              OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
-#define OMAP3430_PRM_VOLTCTRL           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
-#define OMAP3430_PRM_SRAM_PCHARGE       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
-#define OMAP3430_PRM_CLKSRC_CTRL        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
-#define OMAP3430_PRM_VOLTSETUP1         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP3430_PRM_VOLTOFFSET         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
-#define OMAP3430_PRM_CLKSETUP           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
-#define OMAP3430_PRM_POLCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
-#define OMAP3430_PRM_VOLTSETUP2         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
-#define OMAP3430_PRM_VP1_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
-#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
-#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
-#define OMAP3430_PRM_VP1_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
-#define OMAP3430_PRM_VP1_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
-#define OMAP3430_PRM_VP1_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
-#define OMAP3430_PRM_VP2_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
-#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
-#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
-#define OMAP3430_PRM_VP2_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
-#define OMAP3430_PRM_VP2_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
-#define OMAP3430_PRM_VP2_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
-#define OMAP3430_PRM_CLKSEL             OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
-#define OMAP3430_PRM_CLKOUT_CTRL        OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
+#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
+#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3_PRM_RSTST_OFFSET  0x0058
+#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
+#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
+#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
+#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
+#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
+#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
+#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
+#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
+#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
+#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
+#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
+#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 /*
 * Module specific PRM registers from PRM_BASE + domain offset
@@ -156,9 +203,11 @@
 #define OMAP3430_PM_MPUGRPSEL                           0x00a4
 #define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
 #define OMAP3430_PM_IVAGRPSEL                           0x00a8
 #define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
 #define OMAP3430_PM_PREPWSTST                           0x00e8
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
new file mode 100644
index 000000000000..02e1c2d4705f
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -0,0 +1,55 @@
+/*
+ * SDRC register values for the Micron MT46H32M32LF-6
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
+#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
+#include <mach/sdrc.h>
+/* Micron MT46H32M32LF-6 */
+/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
+static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
+        [0] = {
+                .rate        = 166000000,
+                .actim_ctrla = 0x9a9db4c6,
+                .actim_ctrlb = 0x00011217,
+                .rfr_ctrl    = 0x0004dc01,
+                .mr          = 0x00000032,
+        },
+        [1] = {
+                .rate        = 165941176,
+                .actim_ctrla = 0x9a9db4c6,
+                .actim_ctrlb = 0x00011217,
+                .rfr_ctrl    = 0x0004dc01,
+                .mr          = 0x00000032,
+        },
+        [2] = {
+                .rate        = 83000000,
+                .actim_ctrla = 0x51512283,
+                .actim_ctrlb = 0x0001120c,
+                .rfr_ctrl    = 0x00025501,
+                .mr          = 0x00000032,
+        },
+        [3] = {
+                .rate        = 82970588,
+                .actim_ctrla = 0x51512283,
+                .actim_ctrlb = 0x0001120c,
+                .rfr_ctrl    = 0x00025501,
+                .mr          = 0x00000032,
+        },
+        [4] = {
+                .rate        = 0
+        },
+};
+#endif
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
new file mode 100644
index 000000000000..3751d293cb1f
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -0,0 +1,54 @@
+/*
+ * SDRC register values for the Qimonda HYB18M512160AF-6
+ *
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
+#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
+#include <mach/sdrc.h>
+/* Qimonda HYB18M512160AF-6 */
+static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
+        [0] = {
+                .rate        = 166000000,
+                .actim_ctrla = 0x629db4c6,
+                .actim_ctrlb = 0x00012214,
+                .rfr_ctrl    = 0x0004dc01,
+                .mr          = 0x00000032,
+        },
+        [1] = {
+                .rate        = 165941176,
+                .actim_ctrla = 0x629db4c6,
+                .actim_ctrlb = 0x00012214,
+                .rfr_ctrl    = 0x0004dc01,
+                .mr          = 0x00000032,
+        },
+        [2] = {
+                .rate        = 83000000,
+                .actim_ctrla = 0x31512283,
+                .actim_ctrlb = 0x0001220a,
+                .rfr_ctrl    = 0x00025501,
+                .mr          = 0x00000022,
+        },
+        [3] = {
+                .rate        = 82970588,
+                .actim_ctrla = 0x31512283,
+                .actim_ctrlb = 0x0001220a,
+                .rfr_ctrl    = 0x00025501,
+                .mr          = 0x00000022,
+        },
+        [4] = {
+                .rate        = 0
+        },
+};
+#endif
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 2a30060cb4b7..2045441e8385 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -37,6 +37,10 @@ static struct omap_sdrc_params *sdrc_init_params;
 void __iomem *omap2_sdrc_base;
 void __iomem *omap2_sms_base;
+/* SDRC_POWER register bits */
+#define SDRC_POWER_EXTCLKDIS_SHIFT              3
+#define SDRC_POWER_PWDENA_SHIFT                 2
+#define SDRC_POWER_PAGEPOLICY_SHIFT             0
 /**
 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
@@ -56,9 +60,12 @@ struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
 {
        struct omap_sdrc_params *sp;
+        if (!sdrc_init_params)
+                return NULL;
        sp = sdrc_init_params;
-        while (sp->rate != r)
+        while (sp->rate && sp->rate != r)
                sp++;
        if (!sp->rate)
@@ -74,7 +81,14 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
        omap2_sms_base = omap2_globals->sms;
 }
-/* turn on smart idle modes for SDRAM scheduler and controller */
+/**
+ * omap2_sdrc_init - initialize SMS, SDRC devices on boot
+ * @sp: pointer to a null-terminated list of struct omap_sdrc_params
+ *
+ * Turn on smart idle modes for SDRAM scheduler and controller.
+ * Program a known-good configuration for the SDRC to deal with buggy
+ * bootloaders.
+ */
 void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
 {
        u32 l;
@@ -90,4 +104,10 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
        sdrc_write_reg(l, SDRC_SYSCONFIG);
        sdrc_init_params = sp;
+        /* XXX Enable SRFRONIDLEREQ here also? */
+        l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
+                (1 << SDRC_POWER_PWDENA_SHIFT) |
+                (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
+        sdrc_write_reg(l, SDRC_POWER);
 }
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 0afdad5ae9fb..feaec7eaf6bd 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -99,7 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
        m_type = omap2xxx_sdrc_get_type();
        local_irq_save(flags);
-        __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+        if (cpu_is_omap2420())
+                __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
+        else
+                __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
        omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
        curr_perf_level = level;
        local_irq_restore(flags);
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 4dcf39c285b9..b094c15bfe47 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -6,8 +6,13 @@
 * Copyright (C) 2005-2008 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
+ * Major rework for PM support by Kevin Hilman
+ *
 * Based off of arch/arm/mach-omap/omap1/serial.c
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
+ *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
@@ -21,9 +26,50 @@
 #include <mach/common.h>
 #include <mach/board.h>
+#include <mach/clock.h>
+#include <mach/control.h>
+#include "prm.h"
+#include "pm.h"
+#include "prm-regbits-34xx.h"
+#define UART_OMAP_WER           0x17    /* Wake-up enable register */
+#define DEFAULT_TIMEOUT (5 * HZ)
-static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
+struct omap_uart_state {
-static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
+        int num;
+        int can_sleep;
+        struct timer_list timer;
+        u32 timeout;
+        void __iomem *wk_st;
+        void __iomem *wk_en;
+        u32 wk_mask;
+        u32 padconf;
+        struct clk *ick;
+        struct clk *fck;
+        int clocked;
+        struct plat_serial8250_port *p;
+        struct list_head node;
+#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
+        int context_valid;
+        /* Registers to be saved/restored for OFF-mode */
+        u16 dll;
+        u16 dlh;
+        u16 ier;
+        u16 sysc;
+        u16 scr;
+        u16 wer;
+#endif
+};
+static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
+static LIST_HEAD(uart_list);
 static struct plat_serial8250_port serial_platform_data[] = {
        {
@@ -74,33 +120,369 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 * properly. Note that the TX watermark initialization may not be needed
 * once the 8250.c watermark handling code is merged.
 */
-static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
+static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 {
+        struct plat_serial8250_port *p = uart->p;
        serial_write_reg(p, UART_OMAP_MDR1, 0x07);
        serial_write_reg(p, UART_OMAP_SCR, 0x08);
        serial_write_reg(p, UART_OMAP_MDR1, 0x00);
        serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 }
-void omap_serial_enable_clocks(int enable)
+#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
+static int enable_off_mode; /* to be removed by full off-mode patches */
+static void omap_uart_save_context(struct omap_uart_state *uart)
 {
-        int i;
+        u16 lcr = 0;
-        for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+        struct plat_serial8250_port *p = uart->p;
-                if (uart_ick[i] && uart_fck[i]) {
-                        if (enable) {
+        if (!enable_off_mode)
-                                clk_enable(uart_ick[i]);
+                return;
-                                clk_enable(uart_fck[i]);
-                        } else {
+        lcr = serial_read_reg(p, UART_LCR);
-                                clk_disable(uart_ick[i]);
+        serial_write_reg(p, UART_LCR, 0xBF);
-                                clk_disable(uart_fck[i]);
+        uart->dll = serial_read_reg(p, UART_DLL);
+        uart->dlh = serial_read_reg(p, UART_DLM);
+        serial_write_reg(p, UART_LCR, lcr);
+        uart->ier = serial_read_reg(p, UART_IER);
+        uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
+        uart->scr = serial_read_reg(p, UART_OMAP_SCR);
+        uart->wer = serial_read_reg(p, UART_OMAP_WER);
+        uart->context_valid = 1;
+}
+static void omap_uart_restore_context(struct omap_uart_state *uart)
+{
+        u16 efr = 0;
+        struct plat_serial8250_port *p = uart->p;
+        if (!enable_off_mode)
+                return;
+        if (!uart->context_valid)
+                return;
+        uart->context_valid = 0;
+        serial_write_reg(p, UART_OMAP_MDR1, 0x7);
+        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+        efr = serial_read_reg(p, UART_EFR);
+        serial_write_reg(p, UART_EFR, UART_EFR_ECB);
+        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(p, UART_IER, 0x0);
+        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(p, UART_DLL, uart->dll);
+        serial_write_reg(p, UART_DLM, uart->dlh);
+        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(p, UART_IER, uart->ier);
+        serial_write_reg(p, UART_FCR, 0xA1);
+        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(p, UART_EFR, efr);
+        serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
+        serial_write_reg(p, UART_OMAP_SCR, uart->scr);
+        serial_write_reg(p, UART_OMAP_WER, uart->wer);
+        serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
+        serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+}
+#else
+static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
+static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
+#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
+static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
+{
+        if (uart->clocked)
+                return;
+        clk_enable(uart->ick);
+        clk_enable(uart->fck);
+        uart->clocked = 1;
+        omap_uart_restore_context(uart);
+}
+#ifdef CONFIG_PM
+static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
+{
+        if (!uart->clocked)
+                return;
+        omap_uart_save_context(uart);
+        uart->clocked = 0;
+        clk_disable(uart->ick);
+        clk_disable(uart->fck);
+}
+static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
+                                          int enable)
+{
+        struct plat_serial8250_port *p = uart->p;
+        u16 sysc;
+        sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
+        if (enable)
+                sysc |= 0x2 << 3;
+        else
+                sysc |= 0x1 << 3;
+        serial_write_reg(p, UART_OMAP_SYSC, sysc);
+}
+static void omap_uart_block_sleep(struct omap_uart_state *uart)
+{
+        omap_uart_enable_clocks(uart);
+        omap_uart_smart_idle_enable(uart, 0);
+        uart->can_sleep = 0;
+        if (uart->timeout)
+                mod_timer(&uart->timer, jiffies + uart->timeout);
+        else
+                del_timer(&uart->timer);
+}
+static void omap_uart_allow_sleep(struct omap_uart_state *uart)
+{
+        if (!uart->clocked)
+                return;
+        omap_uart_smart_idle_enable(uart, 1);
+        uart->can_sleep = 1;
+        del_timer(&uart->timer);
+}
+static void omap_uart_idle_timer(unsigned long data)
+{
+        struct omap_uart_state *uart = (struct omap_uart_state *)data;
+        omap_uart_allow_sleep(uart);
+}
+void omap_uart_prepare_idle(int num)
+{
+        struct omap_uart_state *uart;
+        list_for_each_entry(uart, &uart_list, node) {
+                if (num == uart->num && uart->can_sleep) {
+                        omap_uart_disable_clocks(uart);
+                        return;
+                }
+        }
+}
+void omap_uart_resume_idle(int num)
+{
+        struct omap_uart_state *uart;
+        list_for_each_entry(uart, &uart_list, node) {
+                if (num == uart->num) {
+                        omap_uart_enable_clocks(uart);
+                        /* Check for IO pad wakeup */
+                        if (cpu_is_omap34xx() && uart->padconf) {
+                                u16 p = omap_ctrl_readw(uart->padconf);
+                                if (p & OMAP3_PADCONF_WAKEUPEVENT0)
+                                        omap_uart_block_sleep(uart);
                        }
+                        /* Check for normal UART wakeup */
+                        if (__raw_readl(uart->wk_st) & uart->wk_mask)
+                                omap_uart_block_sleep(uart);
+                        return;
                }
        }
 }
+void omap_uart_prepare_suspend(void)
+{
+        struct omap_uart_state *uart;
+        list_for_each_entry(uart, &uart_list, node) {
+                omap_uart_allow_sleep(uart);
+        }
+}
+int omap_uart_can_sleep(void)
+{
+        struct omap_uart_state *uart;
+        int can_sleep = 1;
+        list_for_each_entry(uart, &uart_list, node) {
+                if (!uart->clocked)
+                        continue;
+                if (!uart->can_sleep) {
+                        can_sleep = 0;
+                        continue;
+                }
+                /* This UART can now safely sleep. */
+                omap_uart_allow_sleep(uart);
+        }
+        return can_sleep;
+}
+/**
+ * omap_uart_interrupt()
+ *
+ * This handler is used only to detect that *any* UART interrupt has
+ * occurred.  It does _nothing_ to handle the interrupt.  Rather,
+ * any UART interrupt will trigger the inactivity timer so the
+ * UART will not idle or sleep for its timeout period.
+ *
+ **/
+static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
+{
+        struct omap_uart_state *uart = dev_id;
+        omap_uart_block_sleep(uart);
+        return IRQ_NONE;
+}
+static u32 sleep_timeout = DEFAULT_TIMEOUT;
+static void omap_uart_idle_init(struct omap_uart_state *uart)
+{
+        u32 v;
+        struct plat_serial8250_port *p = uart->p;
+        int ret;
+        uart->can_sleep = 0;
+        uart->timeout = sleep_timeout;
+        setup_timer(&uart->timer, omap_uart_idle_timer,
+                    (unsigned long) uart);
+        mod_timer(&uart->timer, jiffies + uart->timeout);
+        omap_uart_smart_idle_enable(uart, 0);
+        if (cpu_is_omap34xx()) {
+                u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
+                u32 wk_mask = 0;
+                u32 padconf = 0;
+                uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
+                uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
+                switch (uart->num) {
+                case 0:
+                        wk_mask = OMAP3430_ST_UART1_MASK;
+                        padconf = 0x182;
+                        break;
+                case 1:
+                        wk_mask = OMAP3430_ST_UART2_MASK;
+                        padconf = 0x17a;
+                        break;
+                case 2:
+                        wk_mask = OMAP3430_ST_UART3_MASK;
+                        padconf = 0x19e;
+                        break;
+                }
+                uart->wk_mask = wk_mask;
+                uart->padconf = padconf;
+        } else if (cpu_is_omap24xx()) {
+                u32 wk_mask = 0;
+                if (cpu_is_omap2430()) {
+                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
+                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
+                } else if (cpu_is_omap2420()) {
+                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
+                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
+                }
+                switch (uart->num) {
+                case 0:
+                        wk_mask = OMAP24XX_ST_UART1_MASK;
+                        break;
+                case 1:
+                        wk_mask = OMAP24XX_ST_UART2_MASK;
+                        break;
+                case 2:
+                        wk_mask = OMAP24XX_ST_UART3_MASK;
+                        break;
+                }
+                uart->wk_mask = wk_mask;
+        } else {
+                uart->wk_en = 0;
+                uart->wk_st = 0;
+                uart->wk_mask = 0;
+                uart->padconf = 0;
+        }
+        /* Set wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                v = __raw_readl(uart->wk_en);
+                v |= uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+        /* Ensure IOPAD wake-enables are set */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v;
+                v = omap_ctrl_readw(uart->padconf);
+                v |= OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+        p->flags |= UPF_SHARE_IRQ;
+        ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
+                          "serial idle", (void *)uart);
+        WARN_ON(ret);
+}
+static ssize_t sleep_timeout_show(struct kobject *kobj,
+                                  struct kobj_attribute *attr,
+                                  char *buf)
+{
+        return sprintf(buf, "%u\n", sleep_timeout / HZ);
+}
+static ssize_t sleep_timeout_store(struct kobject *kobj,
+                                   struct kobj_attribute *attr,
+                                   const char *buf, size_t n)
+{
+        struct omap_uart_state *uart;
+        unsigned int value;
+        if (sscanf(buf, "%u", &value) != 1) {
+                printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
+                return -EINVAL;
+        }
+        sleep_timeout = value * HZ;
+        list_for_each_entry(uart, &uart_list, node) {
+                uart->timeout = sleep_timeout;
+                if (uart->timeout)
+                        mod_timer(&uart->timer, jiffies + uart->timeout);
+                else
+                        /* A zero value means disable timeout feature */
+                        omap_uart_block_sleep(uart);
+        }
+        return n;
+}
+static struct kobj_attribute sleep_timeout_attr =
+        __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+#else
+static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+#endif /* CONFIG_PM */
+static struct platform_device serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = serial_platform_data,
+        },
+};
 void __init omap_serial_init(void)
 {
-        int i;
+        int i, err;
        const struct omap_uart_config *info;
        char name[16];
@@ -114,9 +496,14 @@ void __init omap_serial_init(void)
        if (info == NULL)
                return;
+        if (cpu_is_omap44xx()) {
+                for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
+                        serial_platform_data[i].irq += 32;
+        }
        for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
                struct plat_serial8250_port *p = serial_platform_data + i;
+                struct omap_uart_state *uart = &omap_uart[i];
                if (!(info->enabled_uarts & (1 << i))) {
                        p->membase = NULL;
@@ -125,35 +512,39 @@ void __init omap_serial_init(void)
                }
                sprintf(name, "uart%d_ick", i+1);
-                uart_ick[i] = clk_get(NULL, name);
+                uart->ick = clk_get(NULL, name);
-                if (IS_ERR(uart_ick[i])) {
+                if (IS_ERR(uart->ick)) {
                        printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
-                        uart_ick[i] = NULL;
+                        uart->ick = NULL;
-                } else
+                }
-                        clk_enable(uart_ick[i]);
                sprintf(name, "uart%d_fck", i+1);
-                uart_fck[i] = clk_get(NULL, name);
+                uart->fck = clk_get(NULL, name);
-                if (IS_ERR(uart_fck[i])) {
+                if (IS_ERR(uart->fck)) {
                        printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
-                        uart_fck[i] = NULL;
+                        uart->fck = NULL;
-                } else
+                }
-                        clk_enable(uart_fck[i]);
-                omap_serial_reset(p);
+                if (!uart->ick || !uart->fck)
+                        continue;
+                uart->num = i;
+                p->private_data = uart;
+                uart->p = p;
+                list_add(&uart->node, &uart_list);
+                omap_uart_enable_clocks(uart);
+                omap_uart_reset(uart);
+                omap_uart_idle_init(uart);
        }
-}
-static struct platform_device serial_device = {
+        err = platform_device_register(&serial_device);
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
+#ifdef CONFIG_PM
-        .dev                    = {
+        if (!err)
-                .platform_data  = serial_platform_data,
+                err = sysfs_create_file(&serial_device.dev.kobj,
-        },
+                                        &sleep_timeout_attr.attr);
-};
+#endif
-static int __init omap_init(void)
-{
-        return platform_device_register(&serial_device);
 }
-arch_initcall(omap_init);
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index bf9e96105e11..130aadbfa083 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -28,7 +28,6 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
-#include <mach/pm.h>
 #include <mach/omap24xx.h>
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
new file mode 100644
index 000000000000..e5e2553e79a6
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -0,0 +1,436 @@
+/*
+ * linux/arch/arm/mach-omap2/sleep.S
+ *
+ * (C) Copyright 2007
+ * Texas Instruments
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/io.h>
+#include <mach/control.h>
+#include "prm.h"
+#include "sdrc.h"
+#define PM_PREPWSTST_CORE_V     OMAP34XX_PRM_REGADDR(CORE_MOD, \
+                                OMAP3430_PM_PREPWSTST)
+#define PM_PREPWSTST_MPU_V      OMAP34XX_PRM_REGADDR(MPU_MOD, \
+                                OMAP3430_PM_PREPWSTST)
+#define PM_PWSTCTRL_MPU_P       OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL)
+#define SCRATCHPAD_MEM_OFFS     0x310 /* Move this as correct place is
+                                       * available */
+#define SCRATCHPAD_BASE_P       OMAP343X_CTRL_REGADDR(\
+                                OMAP343X_CONTROL_MEM_WKUP +\
+                                SCRATCHPAD_MEM_OFFS)
+#define SDRC_POWER_V            OMAP34XX_SDRC_REGADDR(SDRC_POWER)
+        .text
+/* Function call to get the restore pointer for resume from OFF */
+ENTRY(get_restore_pointer)
+        stmfd   sp!, {lr}     @ save registers on stack
+        adr     r0, restore
+        ldmfd   sp!, {pc}     @ restore regs and return
+ENTRY(get_restore_pointer_sz)
+        .word   . - get_restore_pointer_sz
+/*
+ * Forces OMAP into idle state
+ *
+ * omap34xx_suspend() - This bit of code just executes the WFI
+ * for normal idles.
+ *
+ * Note: This code get's copied to internal SRAM at boot. When the OMAP
+ *       wakes up it continues execution at the point it went to sleep.
+ */
+ENTRY(omap34xx_cpu_suspend)
+        stmfd   sp!, {r0-r12, lr}               @ save registers on stack
+loop:
+        /*b     loop*/  @Enable to debug by stepping through code
+        /* r0 contains restore pointer in sdram */
+        /* r1 contains information about saving context */
+        ldr     r4, sdrc_power          @ read the SDRC_POWER register
+        ldr     r5, [r4]                @ read the contents of SDRC_POWER
+        orr     r5, r5, #0x40           @ enable self refresh on idle req
+        str     r5, [r4]                @ write back to SDRC_POWER register
+        cmp     r1, #0x0
+        /* If context save is required, do that and execute wfi */
+        bne     save_context_wfi
+        /* Data memory barrier and Data sync barrier */
+        mov     r1, #0
+        mcr     p15, 0, r1, c7, c10, 4
+        mcr     p15, 0, r1, c7, c10, 5
+        wfi                             @ wait for interrupt
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        bl i_dll_wait
+        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
+restore:
+        /* b restore*/  @ Enable to debug restore code
+        /* Check what was the reason for mpu reset and store the reason in r9*/
+        /* 1 - Only L1 and logic lost */
+        /* 2 - Only L2 lost - In this case, we wont be here */
+        /* 3 - Both L1 and L2 lost */
+        ldr     r1, pm_pwstctrl_mpu
+        ldr     r2, [r1]
+        and     r2, r2, #0x3
+        cmp     r2, #0x0        @ Check if target power state was OFF or RET
+        moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
+        movne   r9, #0x1        @ Only L1 and L2 lost => avoid L2 invalidation
+        bne     logic_l1_restore
+        /* Execute smi to invalidate L2 cache */
+        mov r12, #0x1                         @ set up to invalide L2
+smi:    .word 0xE1600070                @ Call SMI monitor (smieq)
+logic_l1_restore:
+        mov     r1, #0
+        /* Invalidate all instruction caches to PoU
+         * and flush branch target cache */
+        mcr     p15, 0, r1, c7, c5, 0
+        ldr     r4, scratchpad_base
+        ldr     r3, [r4,#0xBC]
+        ldmia   r3!, {r4-r6}
+        mov     sp, r4
+        msr     spsr_cxsf, r5
+        mov     lr, r6
+        ldmia   r3!, {r4-r9}
+        /* Coprocessor access Control Register */
+        mcr p15, 0, r4, c1, c0, 2
+        /* TTBR0 */
+        MCR p15, 0, r5, c2, c0, 0
+        /* TTBR1 */
+        MCR p15, 0, r6, c2, c0, 1
+        /* Translation table base control register */
+        MCR p15, 0, r7, c2, c0, 2
+        /*domain access Control Register */
+        MCR p15, 0, r8, c3, c0, 0
+        /* data fault status Register */
+        MCR p15, 0, r9, c5, c0, 0
+        ldmia  r3!,{r4-r8}
+        /* instruction fault status Register */
+        MCR p15, 0, r4, c5, c0, 1
+        /*Data Auxiliary Fault Status Register */
+        MCR p15, 0, r5, c5, c1, 0
+        /*Instruction Auxiliary Fault Status Register*/
+        MCR p15, 0, r6, c5, c1, 1
+        /*Data Fault Address Register */
+        MCR p15, 0, r7, c6, c0, 0
+        /*Instruction Fault Address Register*/
+        MCR p15, 0, r8, c6, c0, 2
+        ldmia  r3!,{r4-r7}
+        /* user r/w thread and process ID */
+        MCR p15, 0, r4, c13, c0, 2
+        /* user ro thread and process ID */
+        MCR p15, 0, r5, c13, c0, 3
+        /*Privileged only thread and process ID */
+        MCR p15, 0, r6, c13, c0, 4
+        /* cache size selection */
+        MCR p15, 2, r7, c0, c0, 0
+        ldmia  r3!,{r4-r8}
+        /* Data TLB lockdown registers */
+        MCR p15, 0, r4, c10, c0, 0
+        /* Instruction TLB lockdown registers */
+        MCR p15, 0, r5, c10, c0, 1
+        /* Secure or Nonsecure Vector Base Address */
+        MCR p15, 0, r6, c12, c0, 0
+        /* FCSE PID */
+        MCR p15, 0, r7, c13, c0, 0
+        /* Context PID */
+        MCR p15, 0, r8, c13, c0, 1
+        ldmia  r3!,{r4-r5}
+        /* primary memory remap register */
+        MCR p15, 0, r4, c10, c2, 0
+        /*normal memory remap register */
+        MCR p15, 0, r5, c10, c2, 1
+        /* Restore cpsr */
+        ldmia   r3!,{r4}        /*load CPSR from SDRAM*/
+        msr     cpsr, r4        /*store cpsr */
+        /* Enabling MMU here */
+        mrc     p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
+        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
+        and     r7, #0x7
+        cmp     r7, #0x0
+        beq     usettbr0
+ttbr_error:
+        /* More work needs to be done to support N[0:2] value other than 0
+        * So looping here so that the error can be detected
+        */
+        b       ttbr_error
+usettbr0:
+        mrc     p15, 0, r2, c2, c0, 0
+        ldr     r5, ttbrbit_mask
+        and     r2, r5
+        mov     r4, pc
+        ldr     r5, table_index_mask
+        and     r4, r5 /* r4 = 31 to 20 bits of pc */
+        /* Extract the value to be written to table entry */
+        ldr     r1, table_entry
+        add     r1, r1, r4 /* r1 has value to be written to table entry*/
+        /* Getting the address of table entry to modify */
+        lsr     r4, #18
+        add     r2, r4 /* r2 has the location which needs to be modified */
+        /* Storing previous entry of location being modified */
+        ldr     r5, scratchpad_base
+        ldr     r4, [r2]
+        str     r4, [r5, #0xC0]
+        /* Modify the table entry */
+        str     r1, [r2]
+        /* Storing address of entry being modified
+         * - will be restored after enabling MMU */
+        ldr     r5, scratchpad_base
+        str     r2, [r5, #0xC4]
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 4   @ Flush prefetch buffer
+        mcr     p15, 0, r0, c7, c5, 6   @ Invalidate branch predictor array
+        mcr     p15, 0, r0, c8, c5, 0   @ Invalidate instruction TLB
+        mcr     p15, 0, r0, c8, c6, 0   @ Invalidate data TLB
+        /* Restore control register  but dont enable caches here*/
+        /* Caches will be enabled after restoring MMU table entry */
+        ldmia   r3!, {r4}
+        /* Store previous value of control register in scratchpad */
+        str     r4, [r5, #0xC8]
+        ldr     r2, cache_pred_disable_mask
+        and     r4, r2
+        mcr     p15, 0, r4, c1, c0, 0
+        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
+save_context_wfi:
+        /*b     save_context_wfi*/      @ enable to debug save code
+        mov     r8, r0 /* Store SDRAM address in r8 */
+        /* Check what that target sleep state is:stored in r1*/
+        /* 1 - Only L1 and logic lost */
+        /* 2 - Only L2 lost */
+        /* 3 - Both L1 and L2 lost */
+        cmp     r1, #0x2 /* Only L2 lost */
+        beq     clean_l2
+        cmp     r1, #0x1 /* L2 retained */
+        /* r9 stores whether to clean L2 or not*/
+        moveq   r9, #0x0 /* Dont Clean L2 */
+        movne   r9, #0x1 /* Clean L2 */
+l1_logic_lost:
+        /* Store sp and spsr to SDRAM */
+        mov     r4, sp
+        mrs     r5, spsr
+        mov     r6, lr
+        stmia   r8!, {r4-r6}
+        /* Save all ARM registers */
+        /* Coprocessor access control register */
+        mrc     p15, 0, r6, c1, c0, 2
+        stmia   r8!, {r6}
+        /* TTBR0, TTBR1 and Translation table base control */
+        mrc     p15, 0, r4, c2, c0, 0
+        mrc     p15, 0, r5, c2, c0, 1
+        mrc     p15, 0, r6, c2, c0, 2
+        stmia   r8!, {r4-r6}
+        /* Domain access control register, data fault status register,
+        and instruction fault status register */
+        mrc     p15, 0, r4, c3, c0, 0
+        mrc     p15, 0, r5, c5, c0, 0
+        mrc     p15, 0, r6, c5, c0, 1
+        stmia   r8!, {r4-r6}
+        /* Data aux fault status register, instruction aux fault status,
+        datat fault address register and instruction fault address register*/
+        mrc     p15, 0, r4, c5, c1, 0
+        mrc     p15, 0, r5, c5, c1, 1
+        mrc     p15, 0, r6, c6, c0, 0
+        mrc     p15, 0, r7, c6, c0, 2
+        stmia   r8!, {r4-r7}
+        /* user r/w thread and process ID, user r/o thread and process ID,
+        priv only thread and process ID, cache size selection */
+        mrc     p15, 0, r4, c13, c0, 2
+        mrc     p15, 0, r5, c13, c0, 3
+        mrc     p15, 0, r6, c13, c0, 4
+        mrc     p15, 2, r7, c0, c0, 0
+        stmia   r8!, {r4-r7}
+        /* Data TLB lockdown, instruction TLB lockdown registers */
+        mrc     p15, 0, r5, c10, c0, 0
+        mrc     p15, 0, r6, c10, c0, 1
+        stmia   r8!, {r5-r6}
+        /* Secure or non secure vector base address, FCSE PID, Context PID*/
+        mrc     p15, 0, r4, c12, c0, 0
+        mrc     p15, 0, r5, c13, c0, 0
+        mrc     p15, 0, r6, c13, c0, 1
+        stmia   r8!, {r4-r6}
+        /* Primary remap, normal remap registers */
+        mrc     p15, 0, r4, c10, c2, 0
+        mrc     p15, 0, r5, c10, c2, 1
+        stmia   r8!,{r4-r5}
+        /* Store current cpsr*/
+        mrs     r2, cpsr
+        stmia   r8!, {r2}
+        mrc     p15, 0, r4, c1, c0, 0
+        /* save control register */
+        stmia   r8!, {r4}
+clean_caches:
+        /* Clean Data or unified cache to POU*/
+        /* How to invalidate only L1 cache???? - #FIX_ME# */
+        /* mcr  p15, 0, r11, c7, c11, 1 */
+        cmp     r9, #1 /* Check whether L2 inval is required or not*/
+        bne     skip_l2_inval
+clean_l2:
+        /* read clidr */
+        mrc     p15, 1, r0, c0, c0, 1
+        /* extract loc from clidr */
+        ands    r3, r0, #0x7000000
+        /* left align loc bit field */
+        mov     r3, r3, lsr #23
+        /* if loc is 0, then no need to clean */
+        beq     finished
+        /* start clean at cache level 0 */
+        mov     r10, #0
+loop1:
+        /* work out 3x current cache level */
+        add     r2, r10, r10, lsr #1
+        /* extract cache type bits from clidr*/
+        mov     r1, r0, lsr r2
+        /* mask of the bits for current cache only */
+        and     r1, r1, #7
+        /* see what cache we have at this level */
+        cmp     r1, #2
+        /* skip if no cache, or just i-cache */
+        blt     skip
+        /* select current cache level in cssr */
+        mcr     p15, 2, r10, c0, c0, 0
+        /* isb to sych the new cssr&csidr */
+        isb
+        /* read the new csidr */
+        mrc     p15, 1, r1, c0, c0, 0
+        /* extract the length of the cache lines */
+        and     r2, r1, #7
+        /* add 4 (line length offset) */
+        add     r2, r2, #4
+        ldr     r4, assoc_mask
+        /* find maximum number on the way size */
+        ands    r4, r4, r1, lsr #3
+        /* find bit position of way size increment */
+        clz     r5, r4
+        ldr     r7, numset_mask
+        /* extract max number of the index size*/
+        ands    r7, r7, r1, lsr #13
+loop2:
+        mov     r9, r4
+        /* create working copy of max way size*/
+loop3:
+        /* factor way and cache number into r11 */
+        orr     r11, r10, r9, lsl r5
+        /* factor index number into r11 */
+        orr     r11, r11, r7, lsl r2
+        /*clean & invalidate by set/way */
+        mcr     p15, 0, r11, c7, c10, 2
+        /* decrement the way*/
+        subs    r9, r9, #1
+        bge     loop3
+        /*decrement the index */
+        subs    r7, r7, #1
+        bge     loop2
+skip:
+        add     r10, r10, #2
+        /* increment cache number */
+        cmp     r3, r10
+        bgt     loop1
+finished:
+        /*swith back to cache level 0 */
+        mov     r10, #0
+        /* select current cache level in cssr */
+        mcr     p15, 2, r10, c0, c0, 0
+        isb
+skip_l2_inval:
+        /* Data memory barrier and Data sync barrier */
+        mov     r1, #0
+        mcr     p15, 0, r1, c7, c10, 4
+        mcr     p15, 0, r1, c7, c10, 5
+        wfi                             @ wait for interrupt
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        bl i_dll_wait
+        /* restore regs and return */
+        ldmfd   sp!, {r0-r12, pc}
+i_dll_wait:
+        ldr     r4, clk_stabilize_delay
+i_dll_delay:
+        subs    r4, r4, #0x1
+        bne     i_dll_delay
+        ldr     r4, sdrc_power
+        ldr     r5, [r4]
+        bic     r5, r5, #0x40
+        str     r5, [r4]
+        bx      lr
+pm_prepwstst_core:
+        .word   PM_PREPWSTST_CORE_V
+pm_prepwstst_mpu:
+        .word   PM_PREPWSTST_MPU_V
+pm_pwstctrl_mpu:
+        .word   PM_PWSTCTRL_MPU_P
+scratchpad_base:
+        .word   SCRATCHPAD_BASE_P
+sdrc_power:
+        .word SDRC_POWER_V
+context_mem:
+        .word   0x803E3E14
+clk_stabilize_delay:
+        .word 0x000001FF
+assoc_mask:
+        .word   0x3ff
+numset_mask:
+        .word   0x7fff
+ttbrbit_mask:
+        .word   0xFFFFC000
+table_index_mask:
+        .word   0xFFF00000
+table_entry:
+        .word   0x00000C02
+cache_pred_disable_mask:
+        .word   0xFFFFE7FB
+ENTRY(omap34xx_cpu_suspend_sz)
+        .word   . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index af4bd3490227..bb299851116d 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -124,11 +124,11 @@ omap242x_sdi_cm_clksel2_pll:
 omap242x_sdi_sdrc_dlla_ctrl:
        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 omap242x_sdi_prcm_voltctrl:
-        .word OMAP242X_PRCM_VOLTCTRL
+        .word OMAP2420_PRCM_VOLTCTRL
 prcm_mask_val:
        .word 0xFFFF3FFC
 omap242x_sdi_timer_32ksynct_cr:
-        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+        .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
 ENTRY(omap242x_sram_ddr_init_sz)
        .word   . - omap242x_sram_ddr_init
@@ -220,11 +220,11 @@ omap242x_srs_sdrc_dlla_ctrl:
 omap242x_srs_sdrc_rfr_ctrl:
        .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 omap242x_srs_prcm_voltctrl:
-        .word OMAP242X_PRCM_VOLTCTRL
+        .word OMAP2420_PRCM_VOLTCTRL
 ddr_prcm_mask_val:
        .word 0xFFFF3FFC
 omap242x_srs_timer_32ksynct:
-        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+        .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
 ENTRY(omap242x_sram_reprogram_sdrc_sz)
        .word   . - omap242x_sram_reprogram_sdrc
@@ -305,7 +305,7 @@ wait_dll_lock:
        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 omap242x_ssp_set_config:
-        .word OMAP242X_PRCM_CLKCFG_CTRL
+        .word OMAP2420_PRCM_CLKCFG_CTRL
 omap242x_ssp_pll_ctl:
        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
 omap242x_ssp_pll_stat:
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index 84363e269e8c..9955abcaeb31 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -124,11 +124,11 @@ omap243x_sdi_cm_clksel2_pll:
 omap243x_sdi_sdrc_dlla_ctrl:
        .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 omap243x_sdi_prcm_voltctrl:
-        .word OMAP243X_PRCM_VOLTCTRL
+        .word OMAP2430_PRCM_VOLTCTRL
 prcm_mask_val:
        .word 0xFFFF3FFC
 omap243x_sdi_timer_32ksynct_cr:
-        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+        .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
 ENTRY(omap243x_sram_ddr_init_sz)
        .word   . - omap243x_sram_ddr_init
@@ -220,11 +220,11 @@ omap243x_srs_sdrc_dlla_ctrl:
 omap243x_srs_sdrc_rfr_ctrl:
        .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 omap243x_srs_prcm_voltctrl:
-        .word OMAP243X_PRCM_VOLTCTRL
+        .word OMAP2430_PRCM_VOLTCTRL
 ddr_prcm_mask_val:
        .word 0xFFFF3FFC
 omap243x_srs_timer_32ksynct:
-        .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
+        .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
 ENTRY(omap243x_sram_reprogram_sdrc_sz)
        .word   . - omap243x_sram_reprogram_sdrc
@@ -305,7 +305,7 @@ wait_dll_lock:
        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 omap243x_ssp_set_config:
-        .word OMAP243X_PRCM_CLKCFG_CTRL
+        .word OMAP2430_PRCM_CLKCFG_CTRL
 omap243x_ssp_pll_ctl:
        .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
 omap243x_ssp_pll_stat:
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 2c7146136342..c080c82521e1 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -40,69 +40,74 @@
 /*
 * Change frequency of core dpll
 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
+ * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
+ *      SDRC rates < 83MHz
 */
 ENTRY(omap3_sram_configure_core_dpll)
        stmfd   sp!, {r1-r12, lr}       @ store regs to stack
+        ldr     r4, [sp, #52]           @ pull extra args off the stack
+        dsb                             @ flush buffered writes to interconnect
        cmp     r3, #0x2
        blne    configure_sdrc
-        cmp     r3, #0x2
+        cmp     r4, #0x1
+        bleq    unlock_dll
        blne    lock_dll
-        cmp     r3, #0x1
-        blne    unlock_dll
        bl      sdram_in_selfrefresh    @ put the SDRAM in self refresh
        bl      configure_core_dpll
        bl      enable_sdrc
-        cmp     r3, #0x1
+        cmp     r4, #0x1
-        blne    wait_dll_unlock
+        bleq    wait_dll_unlock
-        cmp     r3, #0x2
        blne    wait_dll_lock
        cmp     r3, #0x1
        blne    configure_sdrc
+        isb                             @ prevent speculative exec past here
        mov     r0, #0                  @ return value
        ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
 unlock_dll:
-        ldr     r4, omap3_sdrc_dlla_ctrl
+        ldr     r11, omap3_sdrc_dlla_ctrl
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        orr     r5, r5, #0x4
+        orr     r12, r12, #0x4
-        str     r5, [r4]
+        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 lock_dll:
-        ldr     r4, omap3_sdrc_dlla_ctrl
+        ldr     r11, omap3_sdrc_dlla_ctrl
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        bic     r5, r5, #0x4
+        bic     r12, r12, #0x4
-        str     r5, [r4]
+        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 sdram_in_selfrefresh:
-        mov     r5, #0x0                @ Move 0 to R5
+        ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
-        mcr     p15, 0, r5, c7, c10, 5  @ memory barrier
+        ldr     r12, [r11]              @ read the contents of SDRC_POWER
-        ldr     r4, omap3_sdrc_power    @ read the SDRC_POWER register
+        mov     r9, r12                 @ keep a copy of SDRC_POWER bits
-        ldr     r5, [r4]                @ read the contents of SDRC_POWER
+        orr     r12, r12, #0x40         @ enable self refresh on idle req
-        orr     r5, r5, #0x40           @ enable self refresh on idle req
+        bic     r12, r12, #0x4          @ clear PWDENA
-        str     r5, [r4]                @ write back to SDRC_POWER register
+        str     r12, [r11]              @ write back to SDRC_POWER register
-        ldr     r4, omap3_cm_iclken1_core       @ read the CM_ICLKEN1_CORE reg
+        ldr     r12, [r11]              @ posted-write barrier for SDRC
-        ldr     r5, [r4]
+        ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
-        bic     r5, r5, #0x2            @ disable iclk bit for SRDC
+        ldr     r12, [r11]
-        str     r5, [r4]
+        bic     r12, r12, #0x2          @ disable iclk bit for SDRC
+        str     r12, [r11]
 wait_sdrc_idle:
-        ldr     r4, omap3_cm_idlest1_core
+        ldr     r11, omap3_cm_idlest1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x2            @ check for SDRC idle
+        and     r12, r12, #0x2          @ check for SDRC idle
-        cmp     r5, #2
+        cmp     r12, #2
        bne     wait_sdrc_idle
        bx      lr
 configure_core_dpll:
-        ldr     r4, omap3_cm_clksel1_pll
+        ldr     r11, omap3_cm_clksel1_pll
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        ldr     r6, core_m2_mask_val    @ modify m2 for core dpll
+        ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
-        and     r5, r5, r6
+        and     r12, r12, r10
-        orr     r5, r5, r3, lsl #0x1B   @ r3 contains the M2 val
+        orr     r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
-        str     r5, [r4]
+        str     r12, [r11]
-        mov     r5, #0x800              @ wait for the clock to stabilise
+        ldr     r12, [r11]              @ posted-write barrier for CM
+        mov     r12, #0x800             @ wait for the clock to stabilise
        cmp     r3, #2
        bne     wait_clk_stable
        bx      lr
 wait_clk_stable:
-        subs    r5, r5, #1
+        subs    r12, r12, #1
        bne     wait_clk_stable
        nop
        nop
@@ -116,42 +121,42 @@ wait_clk_stable:
        nop
        bx      lr
 enable_sdrc:
-        ldr     r4, omap3_cm_iclken1_core
+        ldr     r11, omap3_cm_iclken1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        orr     r5, r5, #0x2            @ enable iclk bit for SDRC
+        orr     r12, r12, #0x2          @ enable iclk bit for SDRC
-        str     r5, [r4]
+        str     r12, [r11]
 wait_sdrc_idle1:
-        ldr     r4, omap3_cm_idlest1_core
+        ldr     r11, omap3_cm_idlest1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x2
+        and     r12, r12, #0x2
-        cmp     r5, #0
+        cmp     r12, #0
        bne     wait_sdrc_idle1
-        ldr     r4, omap3_sdrc_power
+restore_sdrc_power_val:
-        ldr     r5, [r4]
+        ldr     r11, omap3_sdrc_power
-        bic     r5, r5, #0x40
+        str     r9, [r11]               @ restore SDRC_POWER, no barrier needed
-        str     r5, [r4]
        bx      lr
 wait_dll_lock:
-        ldr     r4, omap3_sdrc_dlla_status
+        ldr     r11, omap3_sdrc_dlla_status
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x4
+        and     r12, r12, #0x4
-        cmp     r5, #0x4
+        cmp     r12, #0x4
        bne     wait_dll_lock
        bx      lr
 wait_dll_unlock:
-        ldr     r4, omap3_sdrc_dlla_status
+        ldr     r11, omap3_sdrc_dlla_status
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x4
+        and     r12, r12, #0x4
-        cmp     r5, #0x0
+        cmp     r12, #0x0
        bne     wait_dll_unlock
        bx      lr
 configure_sdrc:
-        ldr     r4, omap3_sdrc_rfr_ctrl
+        ldr     r11, omap3_sdrc_rfr_ctrl
-        str     r0, [r4]
+        str     r0, [r11]
-        ldr     r4, omap3_sdrc_actim_ctrla
+        ldr     r11, omap3_sdrc_actim_ctrla
-        str     r1, [r4]
+        str     r1, [r11]
-        ldr     r4, omap3_sdrc_actim_ctrlb
+        ldr     r11, omap3_sdrc_actim_ctrlb
-        str     r2, [r4]
+        str     r2, [r11]
+        ldr     r2, [r11]               @ posted-write barrier for SDRC
        bx      lr
 omap3_sdrc_power:
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index f36aba12090e..97eeeebcb066 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -17,9 +17,10 @@
 *
 * Some parts based off of TI's 24xx code:
 *
- *   Copyright (C) 2004 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Texas Instruments, Inc.
 *
 * Roughly modelled after the OMAP1 MPU timer code.
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
@@ -37,6 +38,7 @@
 #include <asm/mach/time.h>
 #include <mach/dmtimer.h>
+#include <asm/localtimer.h>
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
@@ -82,7 +84,8 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
        case CLOCK_EVT_MODE_PERIODIC:
                period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
                period -= 1;
+                if (cpu_is_omap44xx())
+                        period = 0xff;  /* FIXME: */
                omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
@@ -145,6 +148,9 @@ static void __init omap2_gp_clockevent_init(void)
                     "timer-gp: omap_dm_timer_set_source() failed\n");
        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
+        if (cpu_is_omap44xx())
+                /* Assuming 32kHz clk is driving GPT1 */
+                tick_rate = 32768;      /* FIXME: */
        pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
                gptimer_id, tick_rate);
@@ -224,6 +230,9 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
+#ifdef CONFIG_LOCAL_TIMERS
+        twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
+#endif
        omap_dm_timer_init();
        omap2_gp_clockevent_init();
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
new file mode 100644
index 000000000000..c1a650a9910f
--- /dev/null
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -0,0 +1,34 @@
+/*
+ * The MPU local timer source file. In OMAP4, both cortex-a9 cores have
+ * own timer in it's MPU domain. These timers will be driving the
+ * linux kernel SMP tick framework when active. These timers are not
+ * part of the wake up domain.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Author:
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This file is based on arm realview smp platform file.
+ * Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        evt->irq = INT_44XX_LOCALTIMER_IRQ;
+        twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 34a56a136efd..d85296dc896c 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -28,10 +28,20 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/pm.h>
 #include <mach/mux.h>
 #include <mach/usb.h>
+#define OTG_SYSCONFIG   (OMAP34XX_HSUSB_OTG_BASE + 0x404)
+static void __init usb_musb_pm_init(void)
+{
+        /* Ensure force-idle mode for OTG controller */
+        if (cpu_is_omap34xx())
+                omap_writel(0, OTG_SYSCONFIG);
+}
+#ifdef CONFIG_USB_MUSB_SOC
 static struct resource musb_resources[] = {
        [0] = { /* start and end set dynamically */
                .flags  = IORESOURCE_MEM,
@@ -184,4 +194,13 @@ void __init usb_musb_init(void)
                printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
                return;
        }
+        usb_musb_pm_init();
+}
+#else
+void __init usb_musb_init(void)
+{
+        usb_musb_pm_init();
 }
+#endif /* CONFIG_USB_MUSB_SOC */
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index c14d12137276..6f3f77d031d0 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <linux/errno.h>
 #include <mach/hardware.h>
 #include "common.h"
@@ -44,6 +45,7 @@
 #define TARGET_DEV_BUS          1
 #define TARGET_PCI              3
 #define TARGET_PCIE             4
+#define TARGET_SRAM             9
 #define ATTR_PCIE_MEM           0x59
 #define ATTR_PCIE_IO            0x51
 #define ATTR_PCIE_WA            0x79
@@ -53,6 +55,7 @@
 #define ATTR_DEV_CS1            0x1d
 #define ATTR_DEV_CS2            0x1b
 #define ATTR_DEV_BOOT           0xf
+#define ATTR_SRAM               0x0
 /*
 * Helpers to get DDR bank info
@@ -87,13 +90,13 @@ static int __init orion5x_cpu_win_can_remap(int win)
        return 0;
 }
-static void __init setup_cpu_win(int win, u32 base, u32 size,
+static int __init setup_cpu_win(int win, u32 base, u32 size,
                                 u8 target, u8 attr, int remap)
 {
        if (win >= 8) {
                printk(KERN_ERR "setup_cpu_win: trying to allocate "
                                "window %d\n", win);
-                return;
+                return -ENOSPC;
        }
        writel(base & 0xffff0000, CPU_WIN_BASE(win));
@@ -107,6 +110,7 @@ static void __init setup_cpu_win(int win, u32 base, u32 size,
                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
                writel(0, CPU_WIN_REMAP_HI(win));
        }
+        return 0;
 }
 void __init orion5x_setup_cpu_mbus_bridge(void)
@@ -193,3 +197,9 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
        setup_cpu_win(win_alloc_count++, base, size,
                      TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
+int __init orion5x_setup_sram_win(void)
+{
+        return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE,
+                        ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
+}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b1c7778d9f96..eafcc49009ea 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -31,7 +31,7 @@
 #include <plat/ehci-orion.h>
 #include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
-#include <plat/orion5x_wdt.h>
+#include <plat/orion_wdt.h>
 #include <plat/time.h>
 #include "common.h"
@@ -536,16 +536,52 @@ void __init orion5x_xor_init(void)
        platform_device_register(&orion5x_xor1_channel);
 }
+static struct resource orion5x_crypto_res[] = {
+        {
+                .name   = "regs",
+                .start  = ORION5X_CRYPTO_PHYS_BASE,
+                .end    = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sram",
+                .start  = ORION5X_SRAM_PHYS_BASE,
+                .end    = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "crypto interrupt",
+                .start  = IRQ_ORION5X_CESA,
+                .end    = IRQ_ORION5X_CESA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device orion5x_crypto_device = {
+        .name           = "mv_crypto",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(orion5x_crypto_res),
+        .resource       = orion5x_crypto_res,
+};
+int __init orion5x_crypto_init(void)
+{
+        int ret;
+        ret = orion5x_setup_sram_win();
+        if (ret)
+                return ret;
+        return platform_device_register(&orion5x_crypto_device);
+}
 /*****************************************************************************
 * Watchdog
 ****************************************************************************/
-static struct orion5x_wdt_platform_data orion5x_wdt_data = {
+static struct orion_wdt_platform_data orion5x_wdt_data = {
        .tclk                   = 0,
 };
 static struct platform_device orion5x_wdt_device = {
-        .name           = "orion5x_wdt",
+        .name           = "orion_wdt",
        .id             = -1,
        .dev            = {
                .platform_data  = &orion5x_wdt_data,
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 798b9a5e3da9..de483e83edd7 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -26,6 +26,7 @@ void orion5x_setup_dev0_win(u32 base, u32 size);
 void orion5x_setup_dev1_win(u32 base, u32 size);
 void orion5x_setup_dev2_win(u32 base, u32 size);
 void orion5x_setup_pcie_wa_win(u32 base, u32 size);
+int orion5x_setup_sram_win(void);
 void orion5x_ehci0_init(void);
 void orion5x_ehci1_init(void);
@@ -37,6 +38,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
+int orion5x_crypto_init(void);
 /*
 * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index be896e59d3e7..5c9744cd8ef6 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -17,8 +17,8 @@
 #define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
-#define CPU_RESET_MASK          (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
-#define WDT_RESET               0x0002
+#define WDT_RESET_OUT_EN        0x0002
 #define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 377a773ae53f..2d8766570531 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -24,6 +24,7 @@
 * f1000000     on-chip peripheral registers
 * f2000000     PCIe I/O space
 * f2100000     PCI I/O space
+ * f2200000     SRAM dedicated for the crypto unit
 * f4000000     device bus mappings (boot)
 * fa000000     device bus mappings (cs0)
 * fa800000     device bus mappings (cs2)
@@ -49,6 +50,9 @@
 #define ORION5X_PCI_IO_BUS_BASE         0x00100000
 #define ORION5X_PCI_IO_SIZE             SZ_1M
+#define ORION5X_SRAM_PHYS_BASE          (0xf2200000)
+#define ORION5X_SRAM_SIZE               SZ_8K
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
 #define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
@@ -94,6 +98,8 @@
 #define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
 #define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
 #define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
 #define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index e912490fff23..60e734c10458 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -23,7 +23,7 @@ static inline void arch_reset(char mode, const char *cmd)
        /*
         * Enable and issue soft reset
         */
-        orion5x_setbits(CPU_RESET_MASK, (1 << 2));
+        orion5x_setbits(RSTOUTn_MASK, (1 << 2));
        orion5x_setbits(CPU_SOFT_RESET, 1);
 }
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index e23a3f91d6c6..bc4c3b9aaf83 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -124,6 +124,9 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
        u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
        u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
+        /* Initialize gpiolib. */
+        orion_gpio_init();
        while (mode->mpp >= 0) {
                u32 *reg;
                int num_type;
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 41e6d5033d54..61c086b66723 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -181,9 +181,9 @@ static void mss2_power_off(void)
        /*
         * Enable and issue soft reset
         */
-        reg = readl(CPU_RESET_MASK);
+        reg = readl(RSTOUTn_MASK);
        reg |= 1 << 2;
-        writel(reg, CPU_RESET_MASK);
+        writel(reg, RSTOUTn_MASK);
        reg = readl(CPU_SOFT_RESET);
        reg |= 1;
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
index 0f9cdf458952..37b3d4875291 100644
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -25,6 +25,7 @@ struct fpga_devices {
        /* Technologic Systems */
        struct fpga_device      ts_rtc;
        struct fpga_device      ts_nand;
+        struct fpga_device      ts_rng;
 };
 struct ts78xx_fpga_data {
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 9a6b397f972d..5041d1bc26b1 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -17,6 +17,7 @@
 #include <linux/m48t86.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/timeriomem-rng.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -270,12 +271,57 @@ static void ts78xx_ts_nand_unload(void)
 }
 /*****************************************************************************
+ * HW RNG
+ ****************************************************************************/
+#define TS_RNG_DATA     (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
+static struct resource ts78xx_ts_rng_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = TS_RNG_DATA,
+        .end            = TS_RNG_DATA + 4 - 1,
+};
+static struct timeriomem_rng_data ts78xx_ts_rng_data = {
+        .period         = 1000000, /* one second */
+};
+static struct platform_device ts78xx_ts_rng_device = {
+        .name           = "timeriomem_rng",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ts78xx_ts_rng_data,
+        },
+        .resource       = &ts78xx_ts_rng_resource,
+        .num_resources  = 1,
+};
+static int ts78xx_ts_rng_load(void)
+{
+        int rc;
+        if (ts78xx_fpga.supports.ts_rng.init == 0) {
+                rc = platform_device_register(&ts78xx_ts_rng_device);
+                if (!rc)
+                        ts78xx_fpga.supports.ts_rng.init = 1;
+        } else
+                rc = platform_device_add(&ts78xx_ts_rng_device);
+        return rc;
+};
+static void ts78xx_ts_rng_unload(void)
+{
+        platform_device_del(&ts78xx_ts_rng_device);
+}
+/*****************************************************************************
 * FPGA 'hotplug' support code
 ****************************************************************************/
 static void ts78xx_fpga_devices_zero_init(void)
 {
        ts78xx_fpga.supports.ts_rtc.init = 0;
        ts78xx_fpga.supports.ts_nand.init = 0;
+        ts78xx_fpga.supports.ts_rng.init = 0;
 }
 static void ts78xx_fpga_supports(void)
@@ -289,10 +335,12 @@ static void ts78xx_fpga_supports(void)
        case TS7800_REV_5:
                ts78xx_fpga.supports.ts_rtc.present = 1;
                ts78xx_fpga.supports.ts_nand.present = 1;
+                ts78xx_fpga.supports.ts_rng.present = 1;
                break;
        default:
                ts78xx_fpga.supports.ts_rtc.present = 0;
                ts78xx_fpga.supports.ts_nand.present = 0;
+                ts78xx_fpga.supports.ts_rng.present = 0;
        }
 }
@@ -316,6 +364,14 @@ static int ts78xx_fpga_load_devices(void)
                }
                ret |= tmp;
        }
+        if (ts78xx_fpga.supports.ts_rng.present == 1) {
+                tmp = ts78xx_ts_rng_load();
+                if (tmp) {
+                        printk(KERN_INFO "TS-78xx: RNG not registered\n");
+                        ts78xx_fpga.supports.ts_rng.present = 0;
+                }
+                ret |= tmp;
+        }
        return ret;
 }
@@ -328,6 +384,8 @@ static int ts78xx_fpga_unload_devices(void)
                ts78xx_ts_rtc_unload();
        if (ts78xx_fpga.supports.ts_nand.present == 1)
                ts78xx_ts_nand_unload();
+        if (ts78xx_fpga.supports.ts_rng.present == 1)
+                ts78xx_ts_rng_unload();
        return ret;
 }
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 7ddc22c2bb54..69208217b220 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -15,6 +15,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
+#include <net/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -97,6 +98,20 @@ static struct mv643xx_eth_platform_data wnr854t_eth_data = {
        .duplex         = DUPLEX_FULL,
 };
+static struct dsa_chip_data wnr854t_switch_chip_data = {
+        .port_names[0] = "lan3",
+        .port_names[1] = "lan4",
+        .port_names[2] = "wan",
+        .port_names[3] = "cpu",
+        .port_names[5] = "lan1",
+        .port_names[7] = "lan2",
+};
+static struct dsa_platform_data wnr854t_switch_plat_data = {
+        .nr_chips       = 1,
+        .chip           = &wnr854t_switch_chip_data,
+};
 static void __init wnr854t_init(void)
 {
        /*
@@ -110,6 +125,7 @@ static void __init wnr854t_init(void)
         * Configure peripherals.
         */
        orion5x_eth_init(&wnr854t_eth_data);
+        orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
        orion5x_uart0_init();
        orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 17d3fbd368a3..f4533f8ff4e8 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -51,6 +51,12 @@ config MACH_INTELMOTE2
        select IWMMXT
        select PXA_HAVE_BOARD_IRQS
+config MACH_STARGATE2
+        bool "Intel Stargate 2 Platform"
+        select PXA27x
+        select IWMMXT
+        select PXA_HAVE_BOARD_IRQS
 config ARCH_LUBBOCK
        bool "Intel DBPXA250 Development Platform"
        select PXA25x
@@ -88,6 +94,10 @@ config PXA_SHARPSL
          SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa)
          handheld computer.
+config SHARPSL_PM
+        bool
+        select APM_EMULATION
 config CORGI_SSP_DEPRECATED
        bool
        select PXA_SSP
@@ -280,6 +290,7 @@ config MACH_ZYLONITE
        select PXA3xx
        select PXA_SSP
        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
 config MACH_LITTLETON
        bool "PXA3xx Form Factor Platform (aka Littleton)"
@@ -308,6 +319,14 @@ config MACH_CM_X300
        select PXA3xx
        select CPU_PXA300
+config MACH_H4700
+        bool "HP iPAQ hx4700"
+        select PXA27x
+        select IWMMXT
+        select PXA_SSP
+        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
 config MACH_MAGICIAN
        bool "Enable HTC Magician Support"
        select PXA27x
@@ -505,12 +524,6 @@ config PXA_SSP
        help
          Enable support for PXA2xx SSP ports
-config PXA_PWM
-        tristate
-        default BACKLIGHT_PWM
-        help
-          Enable support for PXA2xx/PXA3xx PWM controllers
 config TOSA_BT
        tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
        depends on MACH_TOSA
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 682dbf4e14b0..d18ffef44b8c 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -15,7 +15,6 @@ endif
 # Generic drivers that other drivers may depend upon
 obj-$(CONFIG_PXA_SSP)           += ssp.o
-obj-$(CONFIG_PXA_PWM)           += pwm.o
 # SoC-specific code
 obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
@@ -47,6 +46,7 @@ obj-$(CONFIG_MACH_PCM027)	+= pcm027.o
 obj-$(CONFIG_MACH_PCM990_BASEBOARD)     += pcm990-baseboard.o
 obj-$(CONFIG_MACH_TOSA)         += tosa.o
 obj-$(CONFIG_MACH_EM_X270)      += em-x270.o
+obj-$(CONFIG_MACH_H4700)        += hx4700.o
 obj-$(CONFIG_MACH_MAGICIAN)     += magician.o
 obj-$(CONFIG_MACH_HIMALAYA)     += himalaya.o
 obj-$(CONFIG_MACH_MIOA701)      += mioa701.o mioa701_bootresume.o
@@ -78,6 +78,7 @@ obj-$(CONFIG_MACH_CM_X300)      += cm-x300.o
 obj-$(CONFIG_PXA_EZX)           += ezx.o
 obj-$(CONFIG_MACH_INTELMOTE2)   += imote2.o
+obj-$(CONFIG_MACH_STARGATE2)    += stargate2.o
 obj-$(CONFIG_MACH_CSB726)       += csb726.o
 obj-$(CONFIG_CSB726_CSB701)     += csb701.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index db52d2c4791d..49ae38292310 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -86,20 +86,3 @@ void clks_register(struct clk_lookup *clks, size_t num)
        for (i = 0; i < num; i++)
                clkdev_add(&clks[i]);
 }
-int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
-        struct device *dev)
-{
-        struct clk *r = clk_get(dev, id);
-        struct clk_lookup *l;
-        if (!r)
-                return -ENODEV;
-        l = clkdev_alloc(r, alias, alias_dev_name);
-        clk_put(r);
-        if (!l)
-                return -ENODEV;
-        clkdev_add(l);
-        return 0;
-}
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 34576ba5f5fd..1d2cec25391d 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -335,6 +335,10 @@ void __init cmx270_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_pin_config));
+#ifdef CONFIG_PM
+        pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
+#endif
        cmx270_init_rtc();
        cmx270_init_mmc();
        cmx270_init_ohci();
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index a9f48b1cb54a..465da26591bd 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -21,18 +21,20 @@
 #include <linux/gpio.h>
 #include <linux/dm9000.h>
 #include <linux/leds.h>
+#include <linux/rtc-v3020.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/setup.h>
 #include <mach/pxa300.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/pxa3xx_nand.h>
 #include <asm/mach/map.h>
@@ -46,6 +48,11 @@
 #define CM_X300_MMC2_IRQ        IRQ_GPIO(GPIO82_MMC2_IRQ)
+#define GPIO95_RTC_CS           (95)
+#define GPIO96_RTC_WR           (96)
+#define GPIO97_RTC_RD           (97)
+#define GPIO98_RTC_IO           (98)
 static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
        /* LCD */
        GPIO54_LCD_LDD_0,
@@ -135,6 +142,12 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
        GPIO85_GPIO,                    /* MMC WP */
        GPIO99_GPIO,                    /* Ethernet IRQ */
+        /* RTC GPIOs */
+        GPIO95_GPIO,                    /* RTC CS */
+        GPIO96_GPIO,                    /* RTC WR */
+        GPIO97_GPIO,                    /* RTC RD */
+        GPIO98_GPIO,                    /* RTC IO */
        /* Standard I2C */
        GPIO21_I2C_SCL,
        GPIO22_I2C_SDA,
@@ -265,6 +278,7 @@ static struct mtd_partition cm_x300_nand_partitions[] = {
 static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
        .enable_arbiter = 1,
+        .keep_config    = 1,
        .parts          = cm_x300_nand_partitions,
        .nr_parts       = ARRAY_SIZE(cm_x300_nand_partitions),
 };
@@ -441,6 +455,31 @@ static void __init cm_x300_init_i2c(void)
 static inline void cm_x300_init_i2c(void) {}
 #endif
+#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
+struct v3020_platform_data cm_x300_v3020_pdata = {
+        .use_gpio       = 1,
+        .gpio_cs        = GPIO95_RTC_CS,
+        .gpio_wr        = GPIO96_RTC_WR,
+        .gpio_rd        = GPIO97_RTC_RD,
+        .gpio_io        = GPIO98_RTC_IO,
+};
+static struct platform_device cm_x300_rtc_device = {
+        .name           = "v3020",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cm_x300_v3020_pdata,
+        }
+};
+static void __init cm_x300_init_rtc(void)
+{
+        platform_device_register(&cm_x300_rtc_device);
+}
+#else
+static inline void cm_x300_init_rtc(void) {}
+#endif
 static void __init cm_x300_init(void)
 {
        /* board-processor specific GPIO initialization */
@@ -453,6 +492,19 @@ static void __init cm_x300_init(void)
        cm_x300_init_nand();
        cm_x300_init_leds();
        cm_x300_init_i2c();
+        cm_x300_init_rtc();
+}
+static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
+                                 char **cmdline, struct meminfo *mi)
+{
+        mi->nr_banks = 2;
+        mi->bank[0].start = 0xa0000000;
+        mi->bank[0].node = 0;
+        mi->bank[0].size = (64*1024*1024);
+        mi->bank[1].start = 0xc0000000;
+        mi->bank[1].node = 0;
+        mi->bank[1].size = (64*1024*1024);
 }
 MACHINE_START(CM_X300, "CM-X300 module")
@@ -463,4 +515,5 @@ MACHINE_START(CM_X300, "CM-X300 module")
        .init_irq       = pxa3xx_init_irq,
        .timer          = &pxa_timer,
        .init_machine   = cm_x300_init,
+        .fixup          = cm_x300_fixup,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 930e364ccde9..962dda2e154a 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -42,7 +42,7 @@
 #include <asm/mach/irq.h>
 #include <mach/pxa25x.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
@@ -445,13 +445,8 @@ static struct ads7846_platform_data corgi_ads7846_info = {
        .wait_for_sync          = corgi_wait_for_hsync,
 };
-static void corgi_ads7846_cs(u32 command)
-{
-        gpio_set_value(CORGI_GPIO_ADS7846_CS, !(command == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip corgi_ads7846_chip = {
-        .cs_control     = corgi_ads7846_cs,
+        .gpio_cs        = CORGI_GPIO_ADS7846_CS,
 };
 static void corgi_bl_kick_battery(void)
@@ -475,22 +470,12 @@ static struct corgi_lcd_platform_data corgi_lcdcon_info = {
        .kick_battery           = corgi_bl_kick_battery,
 };
-static void corgi_lcdcon_cs(u32 command)
-{
-        gpio_set_value(CORGI_GPIO_LCDCON_CS, !(command == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip corgi_lcdcon_chip = {
-        .cs_control     = corgi_lcdcon_cs,
+        .gpio_cs        = CORGI_GPIO_LCDCON_CS,
 };
-static void corgi_max1111_cs(u32 command)
-{
-        gpio_set_value(CORGI_GPIO_MAX1111_CS, !(command == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip corgi_max1111_chip = {
-        .cs_control     = corgi_max1111_cs,
+        .gpio_cs        = CORGI_GPIO_MAX1111_CS,
 };
 static struct spi_board_info corgi_spi_devices[] = {
@@ -520,32 +505,8 @@ static struct spi_board_info corgi_spi_devices[] = {
 static void __init corgi_init_spi(void)
 {
-        int err;
-        err = gpio_request(CORGI_GPIO_ADS7846_CS, "ADS7846_CS");
-        if (err)
-                return;
-        err = gpio_request(CORGI_GPIO_LCDCON_CS, "LCDCON_CS");
-        if (err)
-                goto err_free_1;
-        err = gpio_request(CORGI_GPIO_MAX1111_CS, "MAX1111_CS");
-        if (err)
-                goto err_free_2;
-        gpio_direction_output(CORGI_GPIO_ADS7846_CS, 1);
-        gpio_direction_output(CORGI_GPIO_LCDCON_CS, 1);
-        gpio_direction_output(CORGI_GPIO_MAX1111_CS, 1);
        pxa2xx_set_spi_info(1, &corgi_spi_info);
        spi_register_board_info(ARRAY_AND_SIZE(corgi_spi_devices));
-        return;
-err_free_2:
-        gpio_free(CORGI_GPIO_LCDCON_CS);
-err_free_1:
-        gpio_free(CORGI_GPIO_ADS7846_CS);
 }
 #else
 static inline void corgi_init_spi(void) {}
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 7f04b3a761d1..a093282fe4db 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -41,7 +41,6 @@ static void corgi_charger_init(void)
        pxa_gpio_mode(CORGI_GPIO_CHRG_ON | GPIO_OUT);
        pxa_gpio_mode(CORGI_GPIO_CHRG_UKN | GPIO_OUT);
        pxa_gpio_mode(CORGI_GPIO_KEY_INT | GPIO_IN);
-        sharpsl_pm_pxa_init();
 }
 static void corgi_measure_temp(int on)
@@ -191,7 +190,7 @@ unsigned long corgipm_read_devdata(int type)
 static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
        .init            = corgi_charger_init,
-        .exit            = sharpsl_pm_pxa_remove,
+        .exit            = NULL,
        .gpio_batlock    = CORGI_GPIO_BAT_COVER,
        .gpio_acin       = CORGI_GPIO_AC_IN,
        .gpio_batfull    = CORGI_GPIO_CHRG_FULL,
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 083a1d851d49..3a8ee2272add 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -36,6 +36,8 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/cpufreq.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
 #include <mach/pxa2xx-regs.h>
@@ -47,6 +49,8 @@ MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
 #define freq_debug  0
 #endif
+static struct regulator *vcc_core;
 static unsigned int pxa27x_maxfreq;
 module_param(pxa27x_maxfreq, uint, 0);
 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
@@ -58,6 +62,8 @@ typedef struct {
        unsigned int cccr;
        unsigned int div2;
        unsigned int cclkcfg;
+        int vmin;
+        int vmax;
 } pxa_freqs_t;
 /* Define the refresh period in mSec for the SDRAM and the number of rows */
@@ -82,24 +88,24 @@ static unsigned int sdram_rows;
 static pxa_freqs_t pxa255_run_freqs[] =
 {
-        /* CPU   MEMBUS  CCCR  DIV2 CCLKCFG        run  turbo PXbus SDRAM */
+        /* CPU   MEMBUS  CCCR  DIV2 CCLKCFG                run  turbo PXbus SDRAM */
-        { 99500,  99500, 0x121, 1,  CCLKCFG},   /*  99,   99,   50,   50  */
+        { 99500,  99500, 0x121, 1,  CCLKCFG, -1, -1},   /*  99,   99,   50,   50  */
-        {132700, 132700, 0x123, 1,  CCLKCFG},   /* 133,  133,   66,   66  */
+        {132700, 132700, 0x123, 1,  CCLKCFG, -1, -1},   /* 133,  133,   66,   66  */
-        {199100,  99500, 0x141, 0,  CCLKCFG},   /* 199,  199,   99,   99  */
+        {199100,  99500, 0x141, 0,  CCLKCFG, -1, -1},   /* 199,  199,   99,   99  */
-        {265400, 132700, 0x143, 1,  CCLKCFG},   /* 265,  265,  133,   66  */
+        {265400, 132700, 0x143, 1,  CCLKCFG, -1, -1},   /* 265,  265,  133,   66  */
-        {331800, 165900, 0x145, 1,  CCLKCFG},   /* 331,  331,  166,   83  */
+        {331800, 165900, 0x145, 1,  CCLKCFG, -1, -1},   /* 331,  331,  166,   83  */
-        {398100,  99500, 0x161, 0,  CCLKCFG},   /* 398,  398,  196,   99  */
+        {398100,  99500, 0x161, 0,  CCLKCFG, -1, -1},   /* 398,  398,  196,   99  */
 };
 /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
 static pxa_freqs_t pxa255_turbo_freqs[] =
 {
        /* CPU   MEMBUS  CCCR  DIV2 CCLKCFG        run  turbo PXbus SDRAM */
-        { 99500, 99500,  0x121, 1,  CCLKCFG},   /*  99,   99,   50,   50  */
+        { 99500, 99500,  0x121, 1,  CCLKCFG, -1, -1},   /*  99,   99,   50,   50  */
-        {199100, 99500,  0x221, 0,  CCLKCFG},   /*  99,  199,   50,   99  */
+        {199100, 99500,  0x221, 0,  CCLKCFG, -1, -1},   /*  99,  199,   50,   99  */
-        {298500, 99500,  0x321, 0,  CCLKCFG},   /*  99,  287,   50,   99  */
+        {298500, 99500,  0x321, 0,  CCLKCFG, -1, -1},   /*  99,  287,   50,   99  */
-        {298600, 99500,  0x1c1, 0,  CCLKCFG},   /* 199,  287,   99,   99  */
+        {298600, 99500,  0x1c1, 0,  CCLKCFG, -1, -1},   /* 199,  287,   99,   99  */
-        {398100, 99500,  0x241, 0,  CCLKCFG},   /* 199,  398,   99,   99  */
+        {398100, 99500,  0x241, 0,  CCLKCFG, -1, -1},   /* 199,  398,   99,   99  */
 };
 #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
@@ -148,13 +154,13 @@ MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table
   ((T)  ? CCLKCFG_TURBO : 0))
 static pxa_freqs_t pxa27x_freqs[] = {
-        {104000, 104000, PXA27x_CCCR(1,  8, 2), 0, CCLKCFG2(1, 0, 1)},
+        {104000, 104000, PXA27x_CCCR(1,  8, 2), 0, CCLKCFG2(1, 0, 1),  900000, 1705000 },
-        {156000, 104000, PXA27x_CCCR(1,  8, 6), 0, CCLKCFG2(1, 1, 1)},
+        {156000, 104000, PXA27x_CCCR(1,  8, 6), 0, CCLKCFG2(1, 1, 1), 1000000, 1705000 },
-        {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)},
+        {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
-        {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)},
+        {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
-        {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)},
+        {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
-        {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)},
+        {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
-        {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)}
+        {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
 };
 #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
@@ -163,6 +169,47 @@ static struct cpufreq_frequency_table
 extern unsigned get_clk_frequency_khz(int info);
+#ifdef CONFIG_REGULATOR
+static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
+{
+        int ret = 0;
+        int vmin, vmax;
+        if (!cpu_is_pxa27x())
+                return 0;
+        vmin = pxa_freq->vmin;
+        vmax = pxa_freq->vmax;
+        if ((vmin == -1) || (vmax == -1))
+                return 0;
+        ret = regulator_set_voltage(vcc_core, vmin, vmax);
+        if (ret)
+                pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
+                       vmin, vmax);
+        return ret;
+}
+static __init void pxa_cpufreq_init_voltages(void)
+{
+        vcc_core = regulator_get(NULL, "vcc_core");
+        if (IS_ERR(vcc_core)) {
+                pr_info("cpufreq: Didn't find vcc_core regulator\n");
+                vcc_core = NULL;
+        } else {
+                pr_info("cpufreq: Found vcc_core regulator\n");
+        }
+}
+#else
+static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
+{
+        return 0;
+}
+static __init void pxa_cpufreq_init_voltages(void) { }
+#endif
 static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
                             pxa_freqs_t **pxa_freqs)
 {
@@ -251,6 +298,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
        unsigned long flags;
        unsigned int new_freq_cpu, new_freq_mem;
        unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
+        int ret = 0;
        /* Get the current policy */
        find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
@@ -273,6 +321,10 @@ static int pxa_set_target(struct cpufreq_policy *policy,
                         freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
                         (new_freq_mem / 2000) : (new_freq_mem / 1000));
+        if (vcc_core && freqs.new > freqs.old)
+                ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
+        if (ret)
+                return ret;
        /*
         * Tell everyone what we're about to do...
         * you should add a notify client with any platform specific
@@ -335,6 +387,18 @@ static int pxa_set_target(struct cpufreq_policy *policy,
         */
        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+        /*
+         * Even if voltage setting fails, we don't report it, as the frequency
+         * change succeeded. The voltage reduction is not a critical failure,
+         * only power savings will suffer from this.
+         *
+         * Note: if the voltage change fails, and a return value is returned, a
+         * bug is triggered (seems a deadlock). Should anybody find out where,
+         * the "return 0" should become a "return ret".
+         */
+        if (vcc_core && freqs.new < freqs.old)
+                ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
        return 0;
 }
@@ -349,6 +413,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
        if (cpu_is_pxa27x())
                pxa27x_guess_max_freq();
+        pxa_cpufreq_init_voltages();
        init_sdram_rows();
        /* set default policy and cpuinfo */
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 2b289f83a61a..7d3e1b46e550 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -16,15 +16,17 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/sm501.h>
+#include <linux/smsc911x.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/csb726.h>
 #include <mach/mfp-pxa27x.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
 #include <mach/pxa2xx-regs.h>
+#include <mach/audio.h>
 #include "generic.h"
 #include "devices.h"
@@ -275,15 +277,26 @@ static struct resource csb726_lan_resources[] = {
        {
                .start  = CSB726_IRQ_LAN,
                .end    = CSB726_IRQ_LAN,
-                .flags  = IORESOURCE_IRQ,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
        },
 };
+struct smsc911x_platform_config csb726_lan_config = {
+        .irq_type       = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags          = SMSC911X_USE_32BIT,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+};
 static struct platform_device csb726_lan = {
-        .name           = "smc911x",
+        .name           = "smsc911x",
        .id             = -1,
        .num_resources  = ARRAY_SIZE(csb726_lan_resources),
        .resource       = csb726_lan_resources,
+        .dev            = {
+                .platform_data  = &csb726_lan_config,
+        },
 };
 static struct platform_device *devices[] __initdata = {
@@ -303,6 +316,7 @@ static void __init csb726_init(void)
        pxa27x_set_i2c_power_info(NULL);
        pxa_set_mci_info(&csb726_mci);
        pxa_set_ohci_info(&csb726_ohci_platform_data);
+        pxa_set_ac97_info(NULL);
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 29970f703f3c..ecc08f360b68 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -8,7 +8,7 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/ohci.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxa2xx_spi.h>
@@ -290,7 +290,7 @@ static struct resource pxa3xx_resources_i2c_power[] = {
 };
 struct platform_device pxa3xx_device_i2c_power = {
-        .name           = "pxa2xx-i2c",
+        .name           = "pxa3xx-pwri2c",
        .id             = 1,
        .resource       = pxa3xx_resources_i2c_power,
        .num_resources  = ARRAY_SIZE(pxa3xx_resources_i2c_power),
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index bc0f73fbd4ca..243e0802b5f4 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -28,6 +28,8 @@
 #include <linux/spi/libertas_spi.h>
 #include <linux/power_supply.h>
 #include <linux/apm-emulation.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
 #include <media/soc_camera.h>
@@ -41,7 +43,7 @@
 #include <mach/ohci.h>
 #include <mach/mmc.h>
 #include <mach/pxa27x_keypad.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/camera.h>
 #include <mach/pxa2xx_spi.h>
@@ -52,23 +54,31 @@
 #define GPIO13_MMC_CD           (13)
 #define GPIO95_MMC_WP           (95)
 #define GPIO56_NAND_RB          (56)
+#define GPIO93_CAM_RESET        (93)
+#define GPIO16_USB_HUB_RESET    (16)
 /* eXeda specific GPIOs */
 #define GPIO114_MMC_CD          (114)
 #define GPIO20_NAND_RB          (20)
 #define GPIO38_SD_PWEN          (38)
+#define GPIO37_WLAN_RST         (37)
+#define GPIO95_TOUCHPAD_INT     (95)
+#define GPIO130_CAM_RESET       (130)
+#define GPIO10_USB_HUB_RESET    (10)
 /* common  GPIOs */
 #define GPIO11_NAND_CS          (11)
-#define GPIO93_CAM_RESET        (93)
 #define GPIO41_ETHIRQ           (41)
 #define EM_X270_ETHIRQ          IRQ_GPIO(GPIO41_ETHIRQ)
 #define GPIO115_WLAN_PWEN       (115)
 #define GPIO19_WLAN_STRAP       (19)
+#define GPIO9_USB_VBUS_EN       (9)
 static int mmc_cd;
 static int nand_rb;
 static int dm9000_flags;
+static int cam_reset;
+static int usb_hub_reset;
 static unsigned long common_pin_config[] = {
        /* AC'97 */
@@ -180,7 +190,6 @@ static unsigned long common_pin_config[] = {
        /* power controls */
        GPIO20_GPIO     | MFP_LPM_DRIVE_LOW,    /* GPRS_PWEN */
-        GPIO93_GPIO     | MFP_LPM_DRIVE_LOW,    /* Camera reset */
        GPIO115_GPIO    | MFP_LPM_DRIVE_LOW,    /* WLAN_PWEN */
        /* NAND controls */
@@ -191,14 +200,18 @@ static unsigned long common_pin_config[] = {
 };
 static unsigned long em_x270_pin_config[] = {
-        GPIO13_GPIO,    /* MMC card detect */
+        GPIO13_GPIO,                            /* MMC card detect */
-        GPIO56_GPIO,    /* NAND Ready/Busy */
+        GPIO16_GPIO,                            /* USB hub reset */
-        GPIO95_GPIO,    /* MMC Write protect */
+        GPIO56_GPIO,                            /* NAND Ready/Busy */
+        GPIO93_GPIO     | MFP_LPM_DRIVE_LOW,    /* Camera reset */
+        GPIO95_GPIO,                            /* MMC Write protect */
 };
 static unsigned long exeda_pin_config[] = {
+        GPIO10_GPIO,                            /* USB hub reset */
        GPIO20_GPIO,                            /* NAND Ready/Busy */
        GPIO38_GPIO     | MFP_LPM_DRIVE_LOW,    /* SD slot power */
+        GPIO95_GPIO,                            /* touchpad IRQ */
        GPIO114_GPIO,                           /* MMC card detect */
 };
@@ -464,18 +477,79 @@ static inline void em_x270_init_nor(void) {}
 /* PXA27x OHCI controller setup */
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static struct regulator *em_x270_usb_ldo;
+static int em_x270_usb_hub_init(void)
+{
+        int err;
+        em_x270_usb_ldo = regulator_get(NULL, "vcc usb");
+        if (IS_ERR(em_x270_usb_ldo))
+                return PTR_ERR(em_x270_usb_ldo);
+        err = gpio_request(GPIO9_USB_VBUS_EN, "vbus en");
+        if (err)
+                goto err_free_usb_ldo;
+        err = gpio_request(usb_hub_reset, "hub rst");
+        if (err)
+                goto err_free_vbus_gpio;
+        /* USB Hub power-on and reset */
+        gpio_direction_output(usb_hub_reset, 0);
+        regulator_enable(em_x270_usb_ldo);
+        gpio_set_value(usb_hub_reset, 1);
+        gpio_set_value(usb_hub_reset, 0);
+        regulator_disable(em_x270_usb_ldo);
+        regulator_enable(em_x270_usb_ldo);
+        gpio_set_value(usb_hub_reset, 1);
+        /* enable VBUS */
+        gpio_direction_output(GPIO9_USB_VBUS_EN, 1);
+        return 0;
+err_free_vbus_gpio:
+        gpio_free(GPIO9_USB_VBUS_EN);
+err_free_usb_ldo:
+        regulator_put(em_x270_usb_ldo);
+        return err;
+}
 static int em_x270_ohci_init(struct device *dev)
 {
+        int err;
+        /* we don't want to entirely disable USB if the HUB init failed */
+        err = em_x270_usb_hub_init();
+        if (err)
+                pr_err("USB Hub initialization failed: %d\n", err);
        /* enable port 2 transiever */
        UP2OCR = UP2OCR_HXS | UP2OCR_HXOE;
        return 0;
 }
+static void em_x270_ohci_exit(struct device *dev)
+{
+        gpio_free(usb_hub_reset);
+        gpio_free(GPIO9_USB_VBUS_EN);
+        if (!IS_ERR(em_x270_usb_ldo)) {
+                if (regulator_is_enabled(em_x270_usb_ldo))
+                        regulator_disable(em_x270_usb_ldo);
+                regulator_put(em_x270_usb_ldo);
+        }
+}
 static struct pxaohci_platform_data em_x270_ohci_platform_data = {
        .port_mode      = PMM_PERPORT_MODE,
        .flags          = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
        .init           = em_x270_ohci_init,
+        .exit           = em_x270_ohci_exit,
 };
 static void __init em_x270_init_ohci(void)
@@ -677,26 +751,52 @@ static int em_x270_libertas_setup(struct spi_device *spi)
        if (err)
                return err;
+        err = gpio_request(GPIO19_WLAN_STRAP, "WLAN STRAP");
+        if (err)
+                goto err_free_pwen;
+        if (machine_is_exeda()) {
+                err = gpio_request(GPIO37_WLAN_RST, "WLAN RST");
+                if (err)
+                        goto err_free_strap;
+                gpio_direction_output(GPIO37_WLAN_RST, 1);
+                msleep(100);
+        }
        gpio_direction_output(GPIO19_WLAN_STRAP, 1);
-        mdelay(100);
+        msleep(100);
        pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_libertas_pin_config));
        gpio_direction_output(GPIO115_WLAN_PWEN, 0);
-        mdelay(100);
+        msleep(100);
        gpio_set_value(GPIO115_WLAN_PWEN, 1);
-        mdelay(100);
+        msleep(100);
        spi->bits_per_word = 16;
        spi_setup(spi);
        return 0;
+err_free_strap:
+        gpio_free(GPIO19_WLAN_STRAP);
+err_free_pwen:
+        gpio_free(GPIO115_WLAN_PWEN);
+        return err;
 }
 static int em_x270_libertas_teardown(struct spi_device *spi)
 {
        gpio_set_value(GPIO115_WLAN_PWEN, 0);
        gpio_free(GPIO115_WLAN_PWEN);
+        gpio_free(GPIO19_WLAN_STRAP);
+        if (machine_is_exeda()) {
+                gpio_set_value(GPIO37_WLAN_RST, 0);
+                gpio_free(GPIO37_WLAN_RST);
+        }
        return 0;
 }
@@ -863,26 +963,26 @@ static int em_x270_sensor_init(struct device *dev)
 {
        int ret;
-        ret = gpio_request(GPIO93_CAM_RESET, "camera reset");
+        ret = gpio_request(cam_reset, "camera reset");
        if (ret)
                return ret;
-        gpio_direction_output(GPIO93_CAM_RESET, 0);
+        gpio_direction_output(cam_reset, 0);
        em_x270_camera_ldo = regulator_get(NULL, "vcc cam");
        if (em_x270_camera_ldo == NULL) {
-                gpio_free(GPIO93_CAM_RESET);
+                gpio_free(cam_reset);
                return -ENODEV;
        }
        ret = regulator_enable(em_x270_camera_ldo);
        if (ret) {
                regulator_put(em_x270_camera_ldo);
-                gpio_free(GPIO93_CAM_RESET);
+                gpio_free(cam_reset);
                return ret;
        }
-        gpio_set_value(GPIO93_CAM_RESET, 1);
+        gpio_set_value(cam_reset, 1);
        return 0;
 }
@@ -902,7 +1002,7 @@ static int em_x270_sensor_power(struct device *dev, int on)
        if (on == is_on)
                return 0;
-        gpio_set_value(GPIO93_CAM_RESET, !on);
+        gpio_set_value(cam_reset, !on);
        if (on)
                ret = regulator_enable(em_x270_camera_ldo);
@@ -912,7 +1012,7 @@ static int em_x270_sensor_power(struct device *dev, int on)
        if (ret)
                return ret;
-        gpio_set_value(GPIO93_CAM_RESET, on);
+        gpio_set_value(cam_reset, on);
        return 0;
 }
@@ -929,13 +1029,8 @@ static struct i2c_board_info em_x270_i2c_cam_info[] = {
        },
 };
-static struct i2c_pxa_platform_data em_x270_i2c_info = {
-        .fast_mode = 1,
-};
 static void  __init em_x270_init_camera(void)
 {
-        pxa_set_i2c_info(&em_x270_i2c_info);
        i2c_register_board_info(0, ARRAY_AND_SIZE(em_x270_i2c_cam_info));
        pxa_set_camera_info(&em_x270_camera_platform_data);
 }
@@ -985,7 +1080,7 @@ struct led_info em_x270_led_info = {
 };
 struct power_supply_info em_x270_psy_info = {
-        .name = "LP555597P6H-FPS",
+        .name = "battery",
        .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
        .voltage_max_design = 4200000,
        .voltage_min_design = 3000000,
@@ -1069,6 +1164,29 @@ static void __init em_x270_init_da9030(void)
        i2c_register_board_info(1, &em_x270_i2c_pmic_info, 1);
 }
+static struct pca953x_platform_data exeda_gpio_ext_pdata = {
+        .gpio_base = 128,
+};
+static struct i2c_board_info exeda_i2c_info[] = {
+        {
+                I2C_BOARD_INFO("pca9555", 0x21),
+                .platform_data = &exeda_gpio_ext_pdata,
+        },
+};
+static struct i2c_pxa_platform_data em_x270_i2c_info = {
+        .fast_mode = 1,
+};
+static void __init em_x270_init_i2c(void)
+{
+        pxa_set_i2c_info(&em_x270_i2c_info);
+        if (machine_is_exeda())
+                i2c_register_board_info(0, ARRAY_AND_SIZE(exeda_i2c_info));
+}
 static void __init em_x270_module_init(void)
 {
        pr_info("%s\n", __func__);
@@ -1077,6 +1195,8 @@ static void __init em_x270_module_init(void)
        mmc_cd = GPIO13_MMC_CD;
        nand_rb = GPIO56_NAND_RB;
        dm9000_flags = DM9000_PLATF_32BITONLY;
+        cam_reset = GPIO93_CAM_RESET;
+        usb_hub_reset = GPIO16_USB_HUB_RESET;
 }
 static void __init em_x270_exeda_init(void)
@@ -1087,12 +1207,18 @@ static void __init em_x270_exeda_init(void)
        mmc_cd = GPIO114_MMC_CD;
        nand_rb = GPIO20_NAND_RB;
        dm9000_flags = DM9000_PLATF_16BITONLY;
+        cam_reset = GPIO130_CAM_RESET;
+        usb_hub_reset = GPIO10_USB_HUB_RESET;
 }
 static void __init em_x270_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config));
+#ifdef CONFIG_PM
+        pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
+#endif
        if (machine_is_em_x270())
                em_x270_module_init();
        else if (machine_is_exeda())
@@ -1111,8 +1237,9 @@ static void __init em_x270_init(void)
        em_x270_init_keypad();
        em_x270_init_gpio_keys();
        em_x270_init_ac97();
-        em_x270_init_camera();
        em_x270_init_spi();
+        em_x270_init_i2c();
+        em_x270_init_camera();
 }
 MACHINE_START(EM_X270, "Compulab EM-X270")
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 7db966dc29ce..588b265e5755 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -17,6 +17,7 @@
 #include <linux/delay.h>
 #include <linux/pwm_backlight.h>
 #include <linux/input.h>
+#include <linux/gpio_keys.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -25,13 +26,19 @@
 #include <mach/pxa27x.h>
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/hardware.h>
 #include <mach/pxa27x_keypad.h>
 #include "devices.h"
 #include "generic.h"
+#define GPIO12_A780_FLIP_LID            12
+#define GPIO15_A1200_FLIP_LID           15
+#define GPIO15_A910_FLIP_LID            15
+#define GPIO12_E680_LOCK_SWITCH         12
+#define GPIO15_E6_LOCK_SWITCH           15
 static struct platform_pwm_backlight_data ezx_backlight_data = {
        .pwm_id         = 0,
        .max_brightness = 1023,
@@ -88,7 +95,7 @@ static struct pxafb_mach_info ezx_fb_info_2 = {
        .lcd_conn       = LCD_COLOR_TFT_18BPP,
 };
-static struct platform_device *devices[] __initdata = {
+static struct platform_device *ezx_devices[] __initdata = {
        &ezx_backlight_device,
 };
@@ -651,6 +658,35 @@ static struct pxa27x_keypad_platform_data e2_keypad_platform_data = {
 #endif /* CONFIG_MACH_EZX_E2 */
 #ifdef CONFIG_MACH_EZX_A780
+/* gpio_keys */
+static struct gpio_keys_button a780_buttons[] = {
+        [0] = {
+                .code       = SW_LID,
+                .gpio       = GPIO12_A780_FLIP_LID,
+                .active_low = 0,
+                .desc       = "A780 flip lid",
+                .type       = EV_SW,
+                .wakeup     = 1,
+        },
+};
+static struct gpio_keys_platform_data a780_gpio_keys_platform_data = {
+        .buttons  = a780_buttons,
+        .nbuttons = ARRAY_SIZE(a780_buttons),
+};
+static struct platform_device a780_gpio_keys = {
+        .name = "gpio-keys",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &a780_gpio_keys_platform_data,
+        },
+};
+static struct platform_device *a780_devices[] __initdata = {
+        &a780_gpio_keys,
+};
 static void __init a780_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
@@ -663,7 +699,8 @@ static void __init a780_init(void)
        pxa_set_keypad_info(&a780_keypad_platform_data);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
+        platform_add_devices(ARRAY_AND_SIZE(a780_devices));
 }
 MACHINE_START(EZX_A780, "Motorola EZX A780")
@@ -678,10 +715,39 @@ MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_E680
+/* gpio_keys */
+static struct gpio_keys_button e680_buttons[] = {
+        [0] = {
+                .code       = KEY_SCREENLOCK,
+                .gpio       = GPIO12_E680_LOCK_SWITCH,
+                .active_low = 0,
+                .desc       = "E680 lock switch",
+                .type       = EV_KEY,
+                .wakeup     = 1,
+        },
+};
+static struct gpio_keys_platform_data e680_gpio_keys_platform_data = {
+        .buttons  = e680_buttons,
+        .nbuttons = ARRAY_SIZE(e680_buttons),
+};
+static struct platform_device e680_gpio_keys = {
+        .name = "gpio-keys",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &e680_gpio_keys_platform_data,
+        },
+};
 static struct i2c_board_info __initdata e680_i2c_board_info[] = {
        { I2C_BOARD_INFO("tea5767", 0x81) },
 };
+static struct platform_device *e680_devices[] __initdata = {
+        &e680_gpio_keys,
+};
 static void __init e680_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
@@ -695,7 +761,8 @@ static void __init e680_init(void)
        pxa_set_keypad_info(&e680_keypad_platform_data);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
+        platform_add_devices(ARRAY_AND_SIZE(e680_devices));
 }
 MACHINE_START(EZX_E680, "Motorola EZX E680")
@@ -710,10 +777,39 @@ MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_A1200
+/* gpio_keys */
+static struct gpio_keys_button a1200_buttons[] = {
+        [0] = {
+                .code       = SW_LID,
+                .gpio       = GPIO15_A1200_FLIP_LID,
+                .active_low = 0,
+                .desc       = "A1200 flip lid",
+                .type       = EV_SW,
+                .wakeup     = 1,
+        },
+};
+static struct gpio_keys_platform_data a1200_gpio_keys_platform_data = {
+        .buttons  = a1200_buttons,
+        .nbuttons = ARRAY_SIZE(a1200_buttons),
+};
+static struct platform_device a1200_gpio_keys = {
+        .name = "gpio-keys",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &a1200_gpio_keys_platform_data,
+        },
+};
 static struct i2c_board_info __initdata a1200_i2c_board_info[] = {
        { I2C_BOARD_INFO("tea5767", 0x81) },
 };
+static struct platform_device *a1200_devices[] __initdata = {
+        &a1200_gpio_keys,
+};
 static void __init a1200_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
@@ -727,7 +823,8 @@ static void __init a1200_init(void)
        pxa_set_keypad_info(&a1200_keypad_platform_data);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
+        platform_add_devices(ARRAY_AND_SIZE(a1200_devices));
 }
 MACHINE_START(EZX_A1200, "Motorola EZX A1200")
@@ -742,6 +839,35 @@ MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_A910
+/* gpio_keys */
+static struct gpio_keys_button a910_buttons[] = {
+        [0] = {
+                .code       = SW_LID,
+                .gpio       = GPIO15_A910_FLIP_LID,
+                .active_low = 0,
+                .desc       = "A910 flip lid",
+                .type       = EV_SW,
+                .wakeup     = 1,
+        },
+};
+static struct gpio_keys_platform_data a910_gpio_keys_platform_data = {
+        .buttons  = a910_buttons,
+        .nbuttons = ARRAY_SIZE(a910_buttons),
+};
+static struct platform_device a910_gpio_keys = {
+        .name = "gpio-keys",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &a910_gpio_keys_platform_data,
+        },
+};
+static struct platform_device *a910_devices[] __initdata = {
+        &a910_gpio_keys,
+};
 static void __init a910_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
@@ -754,7 +880,8 @@ static void __init a910_init(void)
        pxa_set_keypad_info(&a910_keypad_platform_data);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
+        platform_add_devices(ARRAY_AND_SIZE(a910_devices));
 }
 MACHINE_START(EZX_A910, "Motorola EZX A910")
@@ -769,10 +896,39 @@ MACHINE_END
 #endif
 #ifdef CONFIG_MACH_EZX_E6
+/* gpio_keys */
+static struct gpio_keys_button e6_buttons[] = {
+        [0] = {
+                .code       = KEY_SCREENLOCK,
+                .gpio       = GPIO15_E6_LOCK_SWITCH,
+                .active_low = 0,
+                .desc       = "E6 lock switch",
+                .type       = EV_KEY,
+                .wakeup     = 1,
+        },
+};
+static struct gpio_keys_platform_data e6_gpio_keys_platform_data = {
+        .buttons  = e6_buttons,
+        .nbuttons = ARRAY_SIZE(e6_buttons),
+};
+static struct platform_device e6_gpio_keys = {
+        .name = "gpio-keys",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &e6_gpio_keys_platform_data,
+        },
+};
 static struct i2c_board_info __initdata e6_i2c_board_info[] = {
        { I2C_BOARD_INFO("tea5767", 0x81) },
 };
+static struct platform_device *e6_devices[] __initdata = {
+        &e6_gpio_keys,
+};
 static void __init e6_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
@@ -786,7 +942,8 @@ static void __init e6_init(void)
        pxa_set_keypad_info(&e6_keypad_platform_data);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
+        platform_add_devices(ARRAY_AND_SIZE(e6_devices));
 }
 MACHINE_START(EZX_E6, "Motorola EZX E6")
@@ -805,6 +962,9 @@ static struct i2c_board_info __initdata e2_i2c_board_info[] = {
        { I2C_BOARD_INFO("tea5767", 0x81) },
 };
+static struct platform_device *e2_devices[] __initdata = {
+};
 static void __init e2_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(ezx_pin_config));
@@ -818,7 +978,8 @@ static void __init e2_init(void)
        pxa_set_keypad_info(&e2_keypad_platform_data);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
+        platform_add_devices(ARRAY_AND_SIZE(e2_devices));
 }
 MACHINE_START(EZX_E2, "Motorola EZX E2")
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
new file mode 100644
index 000000000000..7fff467e84fc
--- /dev/null
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -0,0 +1,851 @@
+/*
+ * Support for HP iPAQ hx4700 PDAs.
+ *
+ * Copyright (c) 2008-2009 Philipp Zabel
+ *
+ * Based on code:
+ *    Copyright (c) 2004 Hewlett-Packard Company.
+ *    Copyright (c) 2005 SDG Systems, LLC
+ *    Copyright (c) 2006 Anton Vorontsov <cbou@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/lcd.h>
+#include <linux/mfd/htc-egpio.h>
+#include <linux/mfd/asic3.h>
+#include <linux/mtd/physmap.h>
+#include <linux/pda_power.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/bq24022.h>
+#include <linux/regulator/machine.h>
+#include <linux/spi/ads7846.h>
+#include <linux/spi/spi.h>
+#include <linux/usb/gpio_vbus.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/pxa27x.h>
+#include <mach/hx4700.h>
+#include <plat/i2c.h>
+#include <mach/irda.h>
+#include <mach/pxa2xx_spi.h>
+#include <video/w100fb.h>
+#include "devices.h"
+#include "generic.h"
+/* Physical address space information */
+#define ATI_W3220_PHYS  PXA_CS2_PHYS /* ATI Imageon 3220 Graphics */
+#define ASIC3_PHYS      PXA_CS3_PHYS
+#define ASIC3_SD_PHYS   (PXA_CS3_PHYS + 0x02000000)
+static unsigned long hx4700_pin_config[] __initdata = {
+        /* SDRAM and Static Memory I/O Signals */
+        GPIO20_nSDCS_2,
+        GPIO21_nSDCS_3,
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,   /* W3220 */
+        GPIO79_nCS_3,   /* ASIC3 */
+        GPIO80_nCS_4,
+        GPIO33_nCS_5,   /* EGPIO, WLAN */
+        /* PC CARD */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO54_nPCE_2,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+        GPIO85_nPCE_1,
+        GPIO104_PSKTSEL,
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+        /* FFUART (RS-232) */
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+        GPIO36_FFUART_DCD,
+        GPIO37_FFUART_DSR,
+        GPIO38_FFUART_RI,
+        GPIO39_FFUART_TXD,
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+        /* PWM 1 (Backlight) */
+        GPIO17_PWM1_OUT,
+        /* I2S */
+        GPIO28_I2S_BITCLK_OUT,
+        GPIO29_I2S_SDATA_IN,
+        GPIO30_I2S_SDATA_OUT,
+        GPIO31_I2S_SYNC,
+        GPIO113_I2S_SYSCLK,
+        /* SSP 1 (NavPoint) */
+        GPIO23_SSP1_SCLK,
+        GPIO24_SSP1_SFRM,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+        /* SSP 2 (TSC2046) */
+        GPIO19_SSP2_SCLK,
+        GPIO86_SSP2_RXD,
+        GPIO87_SSP2_TXD,
+        GPIO88_GPIO,
+        /* HX4700 specific input GPIOs */
+        GPIO12_GPIO,    /* ASIC3_IRQ */
+        GPIO13_GPIO,    /* W3220_IRQ */
+        GPIO14_GPIO,    /* nWLAN_IRQ */
+        GPIO10_GPIO,    /* GSM_IRQ */
+        GPIO13_GPIO,    /* CPLD_IRQ */
+        GPIO107_GPIO,   /* DS1WM_IRQ */
+        GPIO108_GPIO,   /* GSM_READY */
+        GPIO58_GPIO,    /* TSC2046_nPENIRQ */
+        GPIO66_GPIO,    /* nSDIO_IRQ */
+};
+#define HX4700_GPIO_IN(num, _desc) \
+        { .gpio = (num), .dir = 0, .desc = (_desc) }
+#define HX4700_GPIO_OUT(num, _init, _desc) \
+        { .gpio = (num), .dir = 1, .init = (_init), .desc = (_desc) }
+struct gpio_ress {
+        unsigned gpio : 8;
+        unsigned dir : 1;
+        unsigned init : 1;
+        char *desc;
+};
+static int hx4700_gpio_request(struct gpio_ress *gpios, int size)
+{
+        int i, rc = 0;
+        int gpio;
+        int dir;
+        for (i = 0; (!rc) && (i < size); i++) {
+                gpio = gpios[i].gpio;
+                dir = gpios[i].dir;
+                rc = gpio_request(gpio, gpios[i].desc);
+                if (rc) {
+                        pr_err("Error requesting GPIO %d(%s) : %d\n",
+                               gpio, gpios[i].desc, rc);
+                        continue;
+                }
+                if (dir)
+                        gpio_direction_output(gpio, gpios[i].init);
+                else
+                        gpio_direction_input(gpio);
+        }
+        while ((rc) && (--i >= 0))
+                gpio_free(gpios[i].gpio);
+        return rc;
+}
+/*
+ * IRDA
+ */
+static void irda_transceiver_mode(struct device *dev, int mode)
+{
+        gpio_set_value(GPIO105_HX4700_nIR_ON, mode & IR_OFF);
+}
+static struct pxaficp_platform_data ficp_info = {
+        .transceiver_cap  = IR_SIRMODE | IR_OFF,
+        .transceiver_mode = irda_transceiver_mode,
+};
+/*
+ * GPIO Keys
+ */
+#define INIT_KEY(_code, _gpio, _active_low, _desc)      \
+        {                                               \
+                .code       = KEY_##_code,              \
+                .gpio       = _gpio,                    \
+                .active_low = _active_low,              \
+                .desc       = _desc,                    \
+                .type       = EV_KEY,                   \
+                .wakeup     = 1,                        \
+        }
+static struct gpio_keys_button gpio_keys_buttons[] = {
+        INIT_KEY(POWER,       GPIO0_HX4700_nKEY_POWER,   1, "Power button"),
+        INIT_KEY(MAIL,        GPIO94_HX4700_KEY_MAIL,    0, "Mail button"),
+        INIT_KEY(ADDRESSBOOK, GPIO99_HX4700_KEY_CONTACTS,0, "Contacts button"),
+        INIT_KEY(RECORD,      GPIOD6_nKEY_RECORD,        1, "Record button"),
+        INIT_KEY(CALENDAR,    GPIOD1_nKEY_CALENDAR,      1, "Calendar button"),
+        INIT_KEY(HOMEPAGE,    GPIOD3_nKEY_HOME,          1, "Home button"),
+};
+static struct gpio_keys_platform_data gpio_keys_data = {
+        .buttons = gpio_keys_buttons,
+        .nbuttons = ARRAY_SIZE(gpio_keys_buttons),
+};
+static struct platform_device gpio_keys = {
+        .name = "gpio-keys",
+        .dev  = {
+                .platform_data = &gpio_keys_data,
+        },
+        .id   = -1,
+};
+/*
+ * ASIC3
+ */
+static u16 asic3_gpio_config[] = {
+        /* ASIC3 GPIO banks A and B along with some of C and D
+           implement the buffering for the CF slot. */
+        ASIC3_CONFIG_GPIO(0, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(1, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(2, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(3, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(4, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(5, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(6, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(7, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(8, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(9, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(10, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(11, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(12, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(13, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(14, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(15, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(16, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(17, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(18, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(19, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(20, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(21, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(22, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(23, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(24, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(25, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(26, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(27, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(28, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(29, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(30, 1, 1, 0),
+        ASIC3_CONFIG_GPIO(31, 1, 1, 0),
+        /* GPIOC - CF, LEDs, SD */
+        ASIC3_GPIOC0_LED0,              /* red */
+        ASIC3_GPIOC1_LED1,              /* green */
+        ASIC3_GPIOC2_LED2,              /* blue */
+        ASIC3_GPIOC4_CF_nCD,
+        ASIC3_GPIOC5_nCIOW,
+        ASIC3_GPIOC6_nCIOR,
+        ASIC3_GPIOC7_nPCE_1,
+        ASIC3_GPIOC8_nPCE_2,
+        ASIC3_GPIOC9_nPOE,
+        ASIC3_GPIOC10_nPWE,
+        ASIC3_GPIOC11_PSKTSEL,
+        ASIC3_GPIOC12_nPREG,
+        ASIC3_GPIOC13_nPWAIT,
+        ASIC3_GPIOC14_nPIOIS16,
+        ASIC3_GPIOC15_nPIOR,
+        /* GPIOD: input GPIOs, CF */
+        ASIC3_GPIOD11_nCIOIS16,
+        ASIC3_GPIOD12_nCWAIT,
+        ASIC3_GPIOD15_nPIOW,
+};
+static struct resource asic3_resources[] = {
+        /* GPIO part */
+        [0] = {
+                .start  = ASIC3_PHYS,
+                .end    = ASIC3_PHYS + ASIC3_MAP_SIZE_16BIT - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ),
+                .end    = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ),
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* SD part */
+        [2] = {
+                .start  = ASIC3_SD_PHYS,
+                .end    = ASIC3_SD_PHYS + ASIC3_MAP_SIZE_16BIT - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [3] = {
+                .start  = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
+                .end    = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct asic3_platform_data asic3_platform_data = {
+        .gpio_config     = asic3_gpio_config,
+        .gpio_config_num = ARRAY_SIZE(asic3_gpio_config),
+        .irq_base        = IRQ_BOARD_START,
+        .gpio_base       = HX4700_ASIC3_GPIO_BASE,
+};
+static struct platform_device asic3 = {
+        .name          = "asic3",
+        .id            = -1,
+        .resource      = asic3_resources,
+        .num_resources = ARRAY_SIZE(asic3_resources),
+        .dev = {
+                .platform_data = &asic3_platform_data,
+        },
+};
+/*
+ * EGPIO
+ */
+static struct resource egpio_resources[] = {
+        [0] = {
+                .start = PXA_CS5_PHYS,
+                .end   = PXA_CS5_PHYS + 0x4 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+static struct htc_egpio_chip egpio_chips[] = {
+        [0] = {
+                .reg_start = 0,
+                .gpio_base = HX4700_EGPIO_BASE,
+                .num_gpios = 8,
+                .direction = HTC_EGPIO_OUTPUT,
+        },
+};
+static struct htc_egpio_platform_data egpio_info = {
+        .reg_width = 16,
+        .bus_width = 16,
+        .chip      = egpio_chips,
+        .num_chips = ARRAY_SIZE(egpio_chips),
+};
+static struct platform_device egpio = {
+        .name          = "htc-egpio",
+        .id            = -1,
+        .resource      = egpio_resources,
+        .num_resources = ARRAY_SIZE(egpio_resources),
+        .dev = {
+                .platform_data = &egpio_info,
+        },
+};
+/*
+ * LCD - Sony display connected to ATI Imageon w3220
+ */
+static int lcd_power;
+static void sony_lcd_init(void)
+{
+        gpio_set_value(GPIO84_HX4700_LCD_SQN, 1);
+        gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
+        gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
+        gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 0);
+        gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
+        mdelay(10);
+        gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
+        gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
+        mdelay(20);
+        gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1);
+        mdelay(5);
+        gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 1);
+        /* FIXME: init w3220 registers here */
+        mdelay(5);
+        gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 1);
+        mdelay(10);
+        gpio_set_value(GPIO62_HX4700_LCD_nRESET, 1);
+        mdelay(10);
+        gpio_set_value(GPIO59_HX4700_LCD_PC1, 1);
+        mdelay(10);
+        gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 1);
+}
+static void sony_lcd_off(void)
+{
+        gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
+        gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
+        mdelay(10);
+        gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 0);
+        mdelay(10);
+        gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
+        mdelay(10);
+        gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
+}
+static int hx4700_lcd_set_power(struct lcd_device *ldev, int level)
+{
+        switch (level) {
+        case FB_BLANK_UNBLANK:
+                sony_lcd_init();
+                break;
+        case FB_BLANK_NORMAL:
+        case FB_BLANK_VSYNC_SUSPEND:
+        case FB_BLANK_HSYNC_SUSPEND:
+        case FB_BLANK_POWERDOWN:
+                sony_lcd_off();
+                break;
+        }
+        lcd_power = level;
+        return 0;
+}
+static int hx4700_lcd_get_power(struct lcd_device *lm)
+{
+        return lcd_power;
+}
+static struct lcd_ops hx4700_lcd_ops = {
+        .get_power = hx4700_lcd_get_power,
+        .set_power = hx4700_lcd_set_power,
+};
+static struct lcd_device *hx4700_lcd_device;
+#ifdef CONFIG_PM
+static void w3220_lcd_suspend(struct w100fb_par *wfb)
+{
+        sony_lcd_off();
+}
+static void w3220_lcd_resume(struct w100fb_par *wfb)
+{
+        sony_lcd_init();
+}
+#else
+#define w3220_lcd_resume        NULL
+#define w3220_lcd_suspend       NULL
+#endif
+static struct w100_tg_info w3220_tg_info = {
+        .suspend        = w3220_lcd_suspend,
+        .resume         = w3220_lcd_resume,
+};
+/*                               W3220_VGA              QVGA */
+static struct w100_gen_regs w3220_regs = {
+        .lcd_format =        0x00000003,
+        .lcdd_cntl1 =        0x00000000,
+        .lcdd_cntl2 =        0x0003ffff,
+        .genlcd_cntl1 =      0x00abf003,        /* 0x00fff003 */
+        .genlcd_cntl2 =      0x00000003,
+        .genlcd_cntl3 =      0x000102aa,
+};
+static struct w100_mode w3220_modes[] = {
+{
+        .xres           = 480,
+        .yres           = 640,
+        .left_margin    = 15,
+        .right_margin   = 16,
+        .upper_margin   = 8,
+        .lower_margin   = 7,
+        .crtc_ss        = 0x00000000,
+        .crtc_ls        = 0xa1ff01f9,   /* 0x21ff01f9 */
+        .crtc_gs        = 0xc0000000,   /* 0x40000000 */
+        .crtc_vpos_gs   = 0x0000028f,
+        .crtc_ps1_active = 0x00000000,  /* 0x41060010 */
+        .crtc_rev       = 0,
+        .crtc_dclk      = 0x80000000,
+        .crtc_gclk      = 0x040a0104,
+        .crtc_goe       = 0,
+        .pll_freq       = 95,
+        .pixclk_divider = 4,
+        .pixclk_divider_rotated = 4,
+        .pixclk_src     = CLK_SRC_PLL,
+        .sysclk_divider = 0,
+        .sysclk_src     = CLK_SRC_PLL,
+},
+{
+        .xres           = 240,
+        .yres           = 320,
+        .left_margin    = 9,
+        .right_margin   = 8,
+        .upper_margin   = 5,
+        .lower_margin   = 4,
+        .crtc_ss        = 0x80150014,
+        .crtc_ls        = 0xa0fb00f7,
+        .crtc_gs        = 0xc0080007,
+        .crtc_vpos_gs   = 0x00080007,
+        .crtc_rev       = 0x0000000a,
+        .crtc_dclk      = 0x81700030,
+        .crtc_gclk      = 0x8015010f,
+        .crtc_goe       = 0x00000000,
+        .pll_freq       = 95,
+        .pixclk_divider = 4,
+        .pixclk_divider_rotated = 4,
+        .pixclk_src     = CLK_SRC_PLL,
+        .sysclk_divider = 0,
+        .sysclk_src     = CLK_SRC_PLL,
+},
+};
+struct w100_mem_info w3220_mem_info = {
+        .ext_cntl        = 0x09640011,
+        .sdram_mode_reg  = 0x00600021,
+        .ext_timing_cntl = 0x1a001545,  /* 0x15001545 */
+        .io_cntl         = 0x7ddd7333,
+        .size            = 0x1fffff,
+};
+struct w100_bm_mem_info w3220_bm_mem_info = {
+        .ext_mem_bw = 0x50413e01,
+        .offset = 0,
+        .ext_timing_ctl = 0x00043f7f,
+        .ext_cntl = 0x00000010,
+        .mode_reg = 0x00250000,
+        .io_cntl = 0x0fff0000,
+        .config = 0x08301480,
+};
+static struct w100_gpio_regs w3220_gpio_info = {
+        .init_data1 = 0xdfe00100,       /* GPIO_DATA */
+        .gpio_dir1  = 0xffff0000,       /* GPIO_CNTL1 */
+        .gpio_oe1   = 0x00000000,       /* GPIO_CNTL2 */
+        .init_data2 = 0x00000000,       /* GPIO_DATA2 */
+        .gpio_dir2  = 0x00000000,       /* GPIO_CNTL3 */
+        .gpio_oe2   = 0x00000000,       /* GPIO_CNTL4 */
+};
+static struct w100fb_mach_info w3220_info = {
+        .tg        = &w3220_tg_info,
+        .mem       = &w3220_mem_info,
+        .bm_mem    = &w3220_bm_mem_info,
+        .gpio      = &w3220_gpio_info,
+        .regs      = &w3220_regs,
+        .modelist  = w3220_modes,
+        .num_modes = 2,
+        .xtal_freq = 16000000,
+};
+static struct resource w3220_resources[] = {
+        [0] = {
+                .start  = ATI_W3220_PHYS,
+                .end    = ATI_W3220_PHYS + 0x00ffffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device w3220 = {
+        .name   = "w100fb",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &w3220_info,
+        },
+        .num_resources = ARRAY_SIZE(w3220_resources),
+        .resource      = w3220_resources,
+};
+/*
+ * Backlight
+ */
+static struct platform_pwm_backlight_data backlight_data = {
+        .pwm_id         = 1,
+        .max_brightness = 200,
+        .dft_brightness = 100,
+        .pwm_period_ns  = 30923,
+};
+static struct platform_device backlight = {
+        .name = "pwm-backlight",
+        .id   = -1,
+        .dev  = {
+                .parent        = &pxa27x_device_pwm1.dev,
+                .platform_data = &backlight_data,
+        },
+};
+/*
+ * USB "Transceiver"
+ */
+static struct gpio_vbus_mach_info gpio_vbus_info = {
+        .gpio_pullup        = GPIO76_HX4700_USBC_PUEN,
+        .gpio_vbus          = GPIOD14_nUSBC_DETECT,
+        .gpio_vbus_inverted = 1,
+};
+static struct platform_device gpio_vbus = {
+        .name          = "gpio-vbus",
+        .id            = -1,
+        .dev = {
+                .platform_data = &gpio_vbus_info,
+        },
+};
+/*
+ * Touchscreen - TSC2046 connected to SSP2
+ */
+static const struct ads7846_platform_data tsc2046_info = {
+        .model            = 7846,
+        .vref_delay_usecs = 100,
+        .pressure_max     = 512,
+        .debounce_max     = 10,
+        .debounce_tol     = 3,
+        .debounce_rep     = 1,
+        .gpio_pendown     = GPIO58_HX4700_TSC2046_nPENIRQ,
+};
+static struct pxa2xx_spi_chip tsc2046_chip = {
+        .tx_threshold = 1,
+        .rx_threshold = 2,
+        .timeout      = 64,
+        .gpio_cs      = GPIO88_HX4700_TSC2046_CS,
+};
+static struct spi_board_info tsc2046_board_info[] __initdata = {
+        {
+                .modalias        = "ads7846",
+                .bus_num         = 2,
+                .max_speed_hz    = 2600000, /* 100 kHz sample rate */
+                .irq             = gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ),
+                .platform_data   = &tsc2046_info,
+                .controller_data = &tsc2046_chip,
+        },
+};
+static struct pxa2xx_spi_master pxa_ssp2_master_info = {
+        .num_chipselect = 1,
+        .clock_enable   = CKEN_SSP2,
+        .enable_dma     = 1,
+};
+/*
+ * External power
+ */
+static int power_supply_init(struct device *dev)
+{
+        return gpio_request(GPIOD9_nAC_IN, "AC charger detect");
+}
+static int hx4700_is_ac_online(void)
+{
+        return !gpio_get_value(GPIOD9_nAC_IN);
+}
+static void power_supply_exit(struct device *dev)
+{
+        gpio_free(GPIOD9_nAC_IN);
+}
+static char *hx4700_supplicants[] = {
+        "ds2760-battery.0", "backup-battery"
+};
+static struct pda_power_pdata power_supply_info = {
+        .init            = power_supply_init,
+        .is_ac_online    = hx4700_is_ac_online,
+        .exit            = power_supply_exit,
+        .supplied_to     = hx4700_supplicants,
+        .num_supplicants = ARRAY_SIZE(hx4700_supplicants),
+};
+static struct resource power_supply_resources[] = {
+        [0] = {
+                .name  = "ac",
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
+                         IORESOURCE_IRQ_LOWEDGE,
+                .start = gpio_to_irq(GPIOD9_nAC_IN),
+                .end   = gpio_to_irq(GPIOD9_nAC_IN),
+        },
+        [1] = {
+                .name  = "usb",
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
+                         IORESOURCE_IRQ_LOWEDGE,
+                .start = gpio_to_irq(GPIOD14_nUSBC_DETECT),
+                .end   = gpio_to_irq(GPIOD14_nUSBC_DETECT),
+        },
+};
+static struct platform_device power_supply = {
+        .name = "pda-power",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &power_supply_info,
+        },
+        .resource      = power_supply_resources,
+        .num_resources = ARRAY_SIZE(power_supply_resources),
+};
+/*
+ * Battery charger
+ */
+static struct regulator_consumer_supply bq24022_consumers[] = {
+        {
+                .dev = &gpio_vbus.dev,
+                .supply = "vbus_draw",
+        },
+        {
+                .dev = &power_supply.dev,
+                .supply = "ac_draw",
+        },
+};
+static struct regulator_init_data bq24022_init_data = {
+        .constraints = {
+                .max_uA         = 500000,
+                .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(bq24022_consumers),
+        .consumer_supplies      = bq24022_consumers,
+};
+static struct bq24022_mach_info bq24022_info = {
+        .gpio_nce   = GPIO72_HX4700_BQ24022_nCHARGE_EN,
+        .gpio_iset2 = GPIO96_HX4700_BQ24022_ISET2,
+        .init_data  = &bq24022_init_data,
+};
+static struct platform_device bq24022 = {
+        .name = "bq24022",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &bq24022_info,
+        },
+};
+/*
+ * StrataFlash
+ */
+static void hx4700_set_vpp(struct map_info *map, int vpp)
+{
+        gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
+}
+static struct resource strataflash_resource = {
+        .start = PXA_CS0_PHYS,
+        .end   = PXA_CS0_PHYS + SZ_128M - 1,
+        .flags = IORESOURCE_MEM,
+};
+static struct physmap_flash_data strataflash_data = {
+        .width = 4,
+        .set_vpp = hx4700_set_vpp,
+};
+static struct platform_device strataflash = {
+        .name          = "physmap-flash",
+        .id            = -1,
+        .resource      = &strataflash_resource,
+        .num_resources = 1,
+        .dev = {
+                .platform_data = &strataflash_data,
+        },
+};
+/*
+ * PCMCIA
+ */
+static struct platform_device pcmcia = {
+        .name = "hx4700-pcmcia",
+        .dev  = {
+                .parent = &asic3.dev,
+        },
+};
+/*
+ * Platform devices
+ */
+static struct platform_device *devices[] __initdata = {
+        &asic3,
+        &gpio_keys,
+        &backlight,
+        &w3220,
+        &egpio,
+        &bq24022,
+        &gpio_vbus,
+        &power_supply,
+        &strataflash,
+        &pcmcia,
+};
+static struct gpio_ress global_gpios[] = {
+        HX4700_GPIO_IN(GPIO12_HX4700_ASIC3_IRQ, "ASIC3_IRQ"),
+        HX4700_GPIO_IN(GPIO13_HX4700_W3220_IRQ, "W3220_IRQ"),
+        HX4700_GPIO_IN(GPIO14_HX4700_nWLAN_IRQ, "WLAN_IRQ"),
+        HX4700_GPIO_OUT(GPIO59_HX4700_LCD_PC1,          1, "LCD_PC1"),
+        HX4700_GPIO_OUT(GPIO62_HX4700_LCD_nRESET,       1, "LCD_RESET"),
+        HX4700_GPIO_OUT(GPIO70_HX4700_LCD_SLIN1,        1, "LCD_SLIN1"),
+        HX4700_GPIO_OUT(GPIO84_HX4700_LCD_SQN,          1, "LCD_SQN"),
+        HX4700_GPIO_OUT(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1, "LCD_LVDD"),
+        HX4700_GPIO_OUT(GPIO111_HX4700_LCD_AVDD_3V3_ON, 1, "LCD_AVDD"),
+        HX4700_GPIO_OUT(GPIO32_HX4700_RS232_ON,         1, "RS232_ON"),
+        HX4700_GPIO_OUT(GPIO71_HX4700_ASIC3_nRESET,     1, "ASIC3_nRESET"),
+        HX4700_GPIO_OUT(GPIO82_HX4700_EUART_RESET,      1, "EUART_RESET"),
+        HX4700_GPIO_OUT(GPIO105_HX4700_nIR_ON,          1, "nIR_EN"),
+};
+static void __init hx4700_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
+        hx4700_gpio_request(ARRAY_AND_SIZE(global_gpios));
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        pxa_set_ficp_info(&ficp_info);
+        pxa27x_set_i2c_power_info(NULL);
+        pxa_set_i2c_info(NULL);
+        pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
+        spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
+        hx4700_lcd_device = lcd_device_register("w100fb", NULL,
+                                        (void *)&w3220_info, &hx4700_lcd_ops);
+        gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 0);
+        mdelay(10);
+        gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 1);
+        mdelay(10);
+}
+MACHINE_START(H4700, "HP iPAQ HX4700")
+        .phys_io      = 0x40000000,
+        .io_pg_offst  = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params  = 0xa0000100,
+        .map_io       = pxa_map_io,
+        .init_irq     = pxa27x_init_irq,
+        .init_machine = hx4700_init,
+        .timer        = &pxa_timer,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c
index 2b27336c29f1..961807dc6467 100644
--- a/arch/arm/mach-pxa/imote2.c
+++ b/arch/arm/mach-pxa/imote2.c
@@ -22,6 +22,7 @@
 #include <linux/spi/spi.h>
 #include <linux/i2c.h>
 #include <linux/mfd/da903x.h>
+#include <linux/sht15.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -29,7 +30,7 @@
 #include <asm/mach/flash.h>
 #include <mach/pxa27x.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/udc.h>
 #include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
@@ -102,6 +103,10 @@ static unsigned long imote2_pin_config[] __initdata = {
        GPIO96_GPIO,    /* accelerometer interrupt */
        GPIO99_GPIO,    /* ADC interrupt */
+        /* SHT15 */
+        GPIO100_GPIO,
+        GPIO98_GPIO,
        /* Connector pins specified as gpios */
        GPIO94_GPIO, /* large basic connector pin 14 */
        GPIO10_GPIO, /* large basic connector pin 23 */
@@ -112,6 +117,26 @@ static unsigned long imote2_pin_config[] __initdata = {
        GPIO105_GPIO, /* blue led */
 };
+static struct sht15_platform_data platform_data_sht15 = {
+        .gpio_data =  100,
+        .gpio_sck  =  98,
+};
+static struct platform_device sht15 = {
+        .name = "sht15",
+        .id = -1,
+        .dev = {
+                .platform_data = &platform_data_sht15,
+        },
+};
+static struct regulator_consumer_supply imote2_sensor_3_con[] = {
+        {
+                .dev = &sht15.dev,
+                .supply = "vcc",
+        },
+};
 static struct gpio_led imote2_led_pins[] = {
        {
                .name       =  "imote2:red",
@@ -257,6 +282,8 @@ static struct regulator_init_data imote2_ldo_init_data[] = {
                        .min_uV = 2800000,
                        .max_uV = 3000000,
                },
+                .num_consumer_supplies = ARRAY_SIZE(imote2_sensor_3_con),
+                .consumer_supplies = imote2_sensor_3_con,
        },
        [vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/
                .constraints = {
@@ -432,6 +459,9 @@ static struct i2c_board_info __initdata imote2_i2c_board_info[] = {
                .type = "tmp175",
                .addr = 0x4A,
                .irq = IRQ_GPIO(96),
+        }, { /* IMB400 Multimedia board */
+                .type = "wm8940",
+                .addr = 0x1A,
        },
 };
@@ -456,25 +486,12 @@ static struct pxa2xx_spi_master pxa_ssp_master_2_info = {
        .num_chipselect = 1,
 };
-/* Patch posted by Eric Miao <eric.miao@marvell.com> will remove
- * the need for these functions.
- */
-static void spi1control(u32 command)
-{
-        gpio_set_value(24, command & PXA2XX_CS_ASSERT ? 0 : 1);
-};
-static void spi3control(u32 command)
-{
-        gpio_set_value(39, command & PXA2XX_CS_ASSERT ? 0 : 1);
-};
 static struct pxa2xx_spi_chip staccel_chip_info = {
        .tx_threshold = 8,
        .rx_threshold = 8,
        .dma_burst_size = 8,
        .timeout = 235,
-        .cs_control = spi1control,
+        .gpio_cs = 24,
 };
 static struct pxa2xx_spi_chip cc2420_info = {
@@ -482,7 +499,7 @@ static struct pxa2xx_spi_chip cc2420_info = {
        .rx_threshold = 8,
        .dma_burst_size = 8,
        .timeout = 235,
-        .cs_control = spi3control,
+        .gpio_cs = 39,
 };
 static struct spi_board_info spi_board_info[] __initdata = {
@@ -521,6 +538,7 @@ static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
 static struct platform_device *imote2_devices[] = {
        &imote2_flash_device,
        &imote2_leds,
+        &sht15,
 };
 static struct i2c_pxa_platform_data i2c_pwr_pdata = {
@@ -538,8 +556,6 @@ static void __init imote2_init(void)
        /* SPI chip select directions - all other directions should
         * be handled by drivers.*/
        gpio_direction_output(37, 0);
-        gpio_direction_output(24, 0);
-        gpio_direction_output(39, 0);
        platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices));
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
new file mode 100644
index 000000000000..9eaeed1f87f1
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/hx4700.h
@@ -0,0 +1,131 @@
+/*
+ * GPIO and IRQ definitions for HP iPAQ hx4700
+ *
+ * Copyright (c) 2008 Philipp Zabel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef _HX4700_H_
+#define _HX4700_H_
+#include <linux/gpio.h>
+#include <linux/mfd/asic3.h>
+#define HX4700_ASIC3_GPIO_BASE  NR_BUILTIN_GPIO
+#define HX4700_EGPIO_BASE       (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
+/*
+ * PXA GPIOs
+ */
+#define GPIO0_HX4700_nKEY_POWER                 0
+#define GPIO12_HX4700_ASIC3_IRQ                 12
+#define GPIO13_HX4700_W3220_IRQ                 13
+#define GPIO14_HX4700_nWLAN_IRQ                 14
+#define GPIO18_HX4700_RDY                       18
+#define GPIO22_HX4700_LCD_RL                    22
+#define GPIO27_HX4700_CODEC_ON                  27
+#define GPIO32_HX4700_RS232_ON                  32
+#define GPIO52_HX4700_CPU_nBATT_FAULT           52
+#define GPIO58_HX4700_TSC2046_nPENIRQ           58
+#define GPIO59_HX4700_LCD_PC1                   59
+#define GPIO60_HX4700_CF_RNB                    60
+#define GPIO61_HX4700_W3220_nRESET              61
+#define GPIO62_HX4700_LCD_nRESET                62
+#define GPIO63_HX4700_CPU_SS_nRESET             63
+#define GPIO65_HX4700_TSC2046_PEN_PU            65
+#define GPIO66_HX4700_ASIC3_nSDIO_IRQ           66
+#define GPIO67_HX4700_EUART_PS                  67
+#define GPIO70_HX4700_LCD_SLIN1                 70
+#define GPIO71_HX4700_ASIC3_nRESET              71
+#define GPIO72_HX4700_BQ24022_nCHARGE_EN        72
+#define GPIO73_HX4700_LCD_UD_1                  73
+#define GPIO75_HX4700_EARPHONE_nDET             75
+#define GPIO76_HX4700_USBC_PUEN                 76
+#define GPIO81_HX4700_CPU_GP_nRESET             81
+#define GPIO82_HX4700_EUART_RESET               82
+#define GPIO83_HX4700_WLAN_nRESET               83
+#define GPIO84_HX4700_LCD_SQN                   84
+#define GPIO85_HX4700_nPCE1                     85
+#define GPIO88_HX4700_TSC2046_CS                88
+#define GPIO91_HX4700_FLASH_VPEN                91
+#define GPIO92_HX4700_HP_DRIVER                 92
+#define GPIO93_HX4700_EUART_INT                 93
+#define GPIO94_HX4700_KEY_MAIL                  94
+#define GPIO95_HX4700_BATT_OFF                  95
+#define GPIO96_HX4700_BQ24022_ISET2             96
+#define GPIO97_HX4700_nBL_DETECT                97
+#define GPIO99_HX4700_KEY_CONTACTS              99
+#define GPIO100_HX4700_AUTO_SENSE               100 /* BL auto brightness */
+#define GPIO102_HX4700_SYNAPTICS_POWER_ON       102
+#define GPIO103_HX4700_SYNAPTICS_INT            103
+#define GPIO105_HX4700_nIR_ON                   105
+#define GPIO106_HX4700_CPU_BT_nRESET            106
+#define GPIO107_HX4700_SPK_nSD                  107
+#define GPIO109_HX4700_CODEC_nPDN               109
+#define GPIO110_HX4700_LCD_LVDD_3V3_ON          110
+#define GPIO111_HX4700_LCD_AVDD_3V3_ON          111
+#define GPIO112_HX4700_LCD_N2V7_7V3_ON          112
+#define GPIO114_HX4700_CF_RESET                 114
+#define GPIO116_HX4700_CPU_HW_nRESET            116
+/*
+ * ASIC3 GPIOs
+ */
+#define GPIOC_BASE              (HX4700_ASIC3_GPIO_BASE + 32)
+#define GPIOD_BASE              (HX4700_ASIC3_GPIO_BASE + 48)
+#define GPIOC0_LED_RED          (GPIOC_BASE + 0)
+#define GPIOC1_LED_GREEN        (GPIOC_BASE + 1)
+#define GPIOC2_LED_BLUE         (GPIOC_BASE + 2)
+#define GPIOC3_nSD_CS           (GPIOC_BASE + 3)
+#define GPIOC4_CF_nCD           (GPIOC_BASE + 4)        /* Input */
+#define GPIOC5_nCIOW            (GPIOC_BASE + 5)        /* Output, to CF */
+#define GPIOC6_nCIOR            (GPIOC_BASE + 6)        /* Output, to CF */
+#define GPIOC7_nPCE1            (GPIOC_BASE + 7)        /* Input, from CPU */
+#define GPIOC8_nPCE2            (GPIOC_BASE + 8)        /* Input, from CPU */
+#define GPIOC9_nPOE             (GPIOC_BASE + 9)        /* Input, from CPU */
+#define GPIOC10_CF_nPWE         (GPIOC_BASE + 10)       /* Input */
+#define GPIOC11_PSKTSEL         (GPIOC_BASE + 11)       /* Input, from CPU */
+#define GPIOC12_nPREG           (GPIOC_BASE + 12)       /* Input, from CPU */
+#define GPIOC13_nPWAIT          (GPIOC_BASE + 13)       /* Output, to CPU */
+#define GPIOC14_nPIOIS16        (GPIOC_BASE + 14)       /* Output, to CPU */
+#define GPIOC15_nPIOR           (GPIOC_BASE + 15)       /* Input, from CPU */
+#define GPIOD0_CPU_SS_INT       (GPIOD_BASE + 0)        /* Input */
+#define GPIOD1_nKEY_CALENDAR    (GPIOD_BASE + 1)
+#define GPIOD2_BLUETOOTH_WAKEUP (GPIOD_BASE + 2)
+#define GPIOD3_nKEY_HOME        (GPIOD_BASE + 3)
+#define GPIOD4_CF_nCD           (GPIOD_BASE + 4)        /* Input, from CF */
+#define GPIOD5_nPIO             (GPIOD_BASE + 5)        /* Input */
+#define GPIOD6_nKEY_RECORD      (GPIOD_BASE + 6)
+#define GPIOD7_nSDIO_DETECT     (GPIOD_BASE + 7)
+#define GPIOD8_COM_DCD          (GPIOD_BASE + 8)        /* Input */
+#define GPIOD9_nAC_IN           (GPIOD_BASE + 9)
+#define GPIOD10_nSDIO_IRQ       (GPIOD_BASE + 10)       /* Input */
+#define GPIOD11_nCIOIS16        (GPIOD_BASE + 11)       /* Input, from CF */
+#define GPIOD12_nCWAIT          (GPIOD_BASE + 12)       /* Input, from CF */
+#define GPIOD13_CF_RNB          (GPIOD_BASE + 13)       /* Input */
+#define GPIOD14_nUSBC_DETECT    (GPIOD_BASE + 14)
+#define GPIOD15_nPIOW           (GPIOD_BASE + 15)       /* Input, from CPU */
+/*
+ * EGPIOs
+ */
+#define EGPIO0_VCC_3V3_EN       (HX4700_EGPIO_BASE + 0) /* WLAN support chip */
+#define EGPIO1_WL_VREG_EN       (HX4700_EGPIO_BASE + 1) /* WLAN power */
+#define EGPIO2_VCC_2V1_WL_EN    (HX4700_EGPIO_BASE + 2) /* unused */
+#define EGPIO3_SS_PWR_ON        (HX4700_EGPIO_BASE + 3) /* smart slot power */
+#define EGPIO4_CF_3V3_ON        (HX4700_EGPIO_BASE + 4) /* CF 3.3V enable */
+#define EGPIO5_BT_3V3_ON        (HX4700_EGPIO_BASE + 5) /* BT 3.3V enable */
+#define EGPIO6_WL1V8_EN         (HX4700_EGPIO_BASE + 6) /* WLAN 1.8V enable */
+#define EGPIO7_VCC_3V3_WL_EN    (HX4700_EGPIO_BASE + 7) /* WLAN 3.3V enable */
+#define EGPIO8_USB_3V3_ON       (HX4700_EGPIO_BASE + 8) /* unused */
+#endif /* _HX4700_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 32bb4a2eb7f1..6a1d95993342 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -91,13 +91,23 @@
 #define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
 /*
- * The next 16 interrupts are for board specific purposes.  Since
+ * The following interrupts are for board specific purposes. Since
 * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase IRQ_BOARD_END, but keep it
+ * these.  There will be 16 IRQs by default.  If it is not enough,
- * within sensible limits.
+ * IRQ_BOARD_END is allowed be customized for each board, but keep
+ * the numbers within sensible limits and in descending order, so
+ * when multiple config options are selected, the maximum will be
+ * used.
 */
 #define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
+#if defined(CONFIG_MACH_H4700)
+#define IRQ_BOARD_END           (IRQ_BOARD_START + 70)
+#elif defined(CONFIG_MACH_ZYLONITE)
+#define IRQ_BOARD_END           (IRQ_BOARD_START + 32)
+#else
 #define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
+#endif
 #define IRQ_SA1111_START        (IRQ_BOARD_END)
 #define IRQ_GPAIN0              (IRQ_BOARD_END + 0)
@@ -188,8 +198,6 @@
 #define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
 #elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
 #define NR_IRQS                 (IRQ_BOARD_END)
-#elif defined(CONFIG_MACH_ZYLONITE)
-#define NR_IRQS                 (IRQ_BOARD_START + 32)
 #else
 #define NR_IRQS                 (IRQ_BOARD_START)
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
index 07897e61d05a..3ce4682eabb6 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -283,6 +283,9 @@
 #define GPIO41_UART1_TXD        MFP_CFG_LPM(GPIO41, AF4, FLOAT)
 #define GPIO42_UART1_RXD        MFP_CFG_LPM(GPIO42, AF4, FLOAT)
 #define GPIO42_UART1_TXD        MFP_CFG_LPM(GPIO42, AF2, FLOAT)
+#define GPIO75_UART1_RXD        MFP_CFG_LPM(GPIO75, AF1, FLOAT)
+#define GPIO76_UART1_RXD        MFP_CFG_LPM(GPIO76, AF3, FLOAT)
+#define GPIO76_UART1_TXD        MFP_CFG_LPM(GPIO76, AF1, FLOAT)
 #define GPIO97_UART1_RXD        MFP_CFG_LPM(GPIO97, AF1, FLOAT)
 #define GPIO97_UART1_TXD        MFP_CFG_LPM(GPIO97, AF6, FLOAT)
 #define GPIO98_UART1_RXD        MFP_CFG_LPM(GPIO98, AF6, FLOAT)
@@ -291,6 +294,9 @@
 #define GPIO43_UART1_RTS        MFP_CFG_LPM(GPIO43, AF4, FLOAT)
 #define GPIO48_UART1_CTS        MFP_CFG_LPM(GPIO48, AF4, FLOAT)
 #define GPIO48_UART1_RTS        MFP_CFG_LPM(GPIO48, AF2, FLOAT)
+#define GPIO77_UART1_CTS        MFP_CFG_LPM(GPIO77, AF1, FLOAT)
+#define GPIO82_UART1_RTS        MFP_CFG_LPM(GPIO82, AF1, FLOAT)
+#define GPIO82_UART1_CTS        MFP_CFG_LPM(GPIO82, AF3, FLOAT)
 #define GPIO99_UART1_CTS        MFP_CFG_LPM(GPIO99, AF1, FLOAT)
 #define GPIO99_UART1_RTS        MFP_CFG_LPM(GPIO99, AF6, FLOAT)
 #define GPIO104_UART1_CTS       MFP_CFG_LPM(GPIO104, AF6, FLOAT)
@@ -299,13 +305,18 @@
 #define GPIO45_UART1_DSR        MFP_CFG_LPM(GPIO45, AF2, FLOAT)
 #define GPIO47_UART1_DTR        MFP_CFG_LPM(GPIO47, AF2, FLOAT)
 #define GPIO47_UART1_DSR        MFP_CFG_LPM(GPIO47, AF4, FLOAT)
+#define GPIO79_UART1_DSR        MFP_CFG_LPM(GPIO79, AF1, FLOAT)
+#define GPIO81_UART1_DTR        MFP_CFG_LPM(GPIO81, AF1, FLOAT)
+#define GPIO81_UART1_DSR        MFP_CFG_LPM(GPIO81, AF3, FLOAT)
 #define GPIO101_UART1_DTR       MFP_CFG_LPM(GPIO101, AF6, FLOAT)
 #define GPIO101_UART1_DSR       MFP_CFG_LPM(GPIO101, AF1, FLOAT)
 #define GPIO103_UART1_DTR       MFP_CFG_LPM(GPIO103, AF1, FLOAT)
 #define GPIO103_UART1_DSR       MFP_CFG_LPM(GPIO103, AF6, FLOAT)
 #define GPIO44_UART1_DCD        MFP_CFG_LPM(GPIO44, AF2, FLOAT)
+#define GPIO78_UART1_DCD        MFP_CFG_LPM(GPIO78, AF1, FLOAT)
 #define GPIO100_UART1_DCD       MFP_CFG_LPM(GPIO100, AF1, FLOAT)
 #define GPIO46_UART1_RI         MFP_CFG_LPM(GPIO46, AF2, FLOAT)
+#define GPIO80_UART1_RI         MFP_CFG_LPM(GPIO80, AF1, FLOAT)
 #define GPIO102_UART1_RI        MFP_CFG_LPM(GPIO102, AF1, FLOAT)
 /* UART2 */
@@ -438,6 +449,9 @@
 #define GPIO2_RDY               MFP_CFG(GPIO2, AF1)
 #define GPIO5_NPIOR             MFP_CFG(GPIO5, AF3)
+#define GPIO6_NPIOW             MFP_CFG(GPIO6, AF3)
+#define GPIO7_NPIOS16           MFP_CFG(GPIO7, AF3)
+#define GPIO8_NPWAIT            MFP_CFG(GPIO8, AF3)
 #define GPIO11_PWM0_OUT         MFP_CFG(GPIO11, AF1)
 #define GPIO12_PWM1_OUT         MFP_CFG(GPIO12, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h
index fb13c82ad6dc..8721b8010221 100644
--- a/arch/arm/mach-pxa/include/mach/palmld.h
+++ b/arch/arm/mach-pxa/include/mach/palmld.h
@@ -56,7 +56,6 @@
 #define GPIO_NR_PALMLD_LED_AMBER        94
 /* IDE */
-#define GPIO_NR_PALMLD_IDE_IRQ          95
 #define GPIO_NR_PALMLD_IDE_RESET        98
 #define GPIO_NR_PALMLD_IDE_PWEN         115
diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index a6eeef8a075f..fd8360c6839d 100644
--- a/arch/arm/mach-pxa/include/mach/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
@@ -27,6 +27,8 @@ extern void pxa27x_cpu_suspend(unsigned int);
 extern void pxa_cpu_resume(void);
 extern int pxa_pm_enter(suspend_state_t state);
+extern int pxa_pm_prepare(void);
+extern void pxa_pm_finish(void);
 /* NOTE: this is for PM debugging on Lubbock,  it's really a big
 * ugly, but let's keep the crap minimum here, instead of direct
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
index 6876e16c2970..0b702693f458 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -16,4 +16,7 @@
 #define ARB_DMA_PARK            (1<<25)    /* Be parked with DMA when idle */
 #define ARB_CORE_PARK           (1<<24)    /* Be parked with core when idle */
 #define ARB_LOCK_FLAG           (1<<23)    /* Only Locking masters gain access to the bus */
+extern int __init pxa27x_set_pwrmode(unsigned int mode);
 #endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/include/asm/hardware/sharpsl_pm.h b/arch/arm/mach-pxa/include/mach/sharpsl_pm.h
index 2d00db22b981..1920dc6b05dc 100644
--- a/arch/arm/include/asm/hardware/sharpsl_pm.h
+++ b/arch/arm/mach-pxa/include/mach/sharpsl_pm.h
@@ -8,8 +8,8 @@
 * published by the Free Software Foundation.
 *
 */
+#ifndef _MACH_SHARPSL_PM
-#include <linux/interrupt.h>
+#define _MACH_SHARPSL_PM
 struct sharpsl_charger_machinfo {
        void (*init)(void);
@@ -100,7 +100,5 @@ extern struct sharpsl_pm_status sharpsl_pm;
 void sharpsl_battery_kick(void);
 void sharpsl_pm_led(int val);
-irqreturn_t sharpsl_ac_isr(int irq, void *dev_id);
-irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id);
-irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id);
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 5706cea95d11..b54749413e96 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -36,7 +36,8 @@ static inline void flush(void)
 static inline void arch_decomp_setup(void)
 {
        if (machine_is_littleton() || machine_is_intelmote2()
-                        || machine_is_csb726())
+            || machine_is_csb726() || machine_is_stargate2()
+            || machine_is_cm_x300())
                UART = STUART;
 }
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index c872b9feb4d4..55b3788fd1ae 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -42,14 +42,17 @@
 #include <mach/pxa300.h>
 #include <mach/pxafb.h>
 #include <mach/ssp.h>
+#include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxa3xx_nand.h>
 #include <mach/littleton.h>
 #include "generic.h"
+#define GPIO_MMC1_CARD_DETECT   mfp_to_gpio(MFP_PIN_GPIO15)
 /* Littleton MFP configurations */
 static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
        /* LCD */
@@ -98,6 +101,15 @@ static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
        GPIO123_KP_MKOUT_2,
        GPIO124_KP_MKOUT_3,
        GPIO125_KP_MKOUT_4,
+        /* MMC1 */
+        GPIO3_MMC1_DAT0,
+        GPIO4_MMC1_DAT1,
+        GPIO5_MMC1_DAT2,
+        GPIO6_MMC1_DAT3,
+        GPIO7_MMC1_CLK,
+        GPIO8_MMC1_CMD,
+        GPIO15_GPIO, /* card detect */
 };
 static struct resource smc91x_resources[] = {
@@ -179,15 +191,10 @@ static struct pxa2xx_spi_master littleton_spi_info = {
        .num_chipselect         = 1,
 };
-static void littleton_tdo24m_cs(u32 cmd)
-{
-        gpio_set_value(LITTLETON_GPIO_LCD_CS, !(cmd == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip littleton_tdo24m_chip = {
        .rx_threshold   = 1,
        .tx_threshold   = 1,
-        .cs_control     = littleton_tdo24m_cs,
+        .gpio_cs        = LITTLETON_GPIO_LCD_CS,
 };
 static struct spi_board_info littleton_spi_devices[] __initdata = {
@@ -202,16 +209,6 @@ static struct spi_board_info littleton_spi_devices[] __initdata = {
 static void __init littleton_init_spi(void)
 {
-        int err;
-        err = gpio_request(LITTLETON_GPIO_LCD_CS, "LCD_CS");
-        if (err) {
-                pr_warning("failed to request GPIO for LCS CS\n");
-                return;
-        }
-        gpio_direction_output(LITTLETON_GPIO_LCD_CS, 1);
        pxa2xx_set_spi_info(2, &littleton_spi_info);
        spi_register_board_info(ARRAY_AND_SIZE(littleton_spi_devices));
 }
@@ -267,6 +264,56 @@ static void __init littleton_init_keypad(void)
 static inline void littleton_init_keypad(void) {}
 #endif
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+static int littleton_mci_init(struct device *dev,
+                              irq_handler_t littleton_detect_int, void *data)
+{
+        int err, gpio_cd = GPIO_MMC1_CARD_DETECT;
+        err = gpio_request(gpio_cd, "mmc card detect");
+        if (err)
+                goto err_request_cd;
+        gpio_direction_input(gpio_cd);
+        err = request_irq(gpio_to_irq(gpio_cd), littleton_detect_int,
+                          IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                          "mmc card detect", data);
+        if (err) {
+                dev_err(dev, "failed to request card detect IRQ\n");
+                goto err_request_irq;
+        }
+        return 0;
+err_request_irq:
+        gpio_free(gpio_cd);
+err_request_cd:
+        return err;
+}
+static void littleton_mci_exit(struct device *dev, void *data)
+{
+        int gpio_cd = GPIO_MMC1_CARD_DETECT;
+        free_irq(gpio_to_irq(gpio_cd), data);
+        gpio_free(gpio_cd);
+}
+static struct pxamci_platform_data littleton_mci_platform_data = {
+        .detect_delay   = 20,
+        .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .init           = littleton_mci_init,
+        .exit           = littleton_mci_exit,
+};
+static void __init littleton_init_mmc(void)
+{
+        pxa_set_mci_info(&littleton_mci_platform_data);
+}
+#else
+static inline void littleton_init_mmc(void) {}
+#endif
 #if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
 static struct mtd_partition littleton_nand_partitions[] = {
        [0] = {
@@ -407,6 +454,7 @@ static void __init littleton_init(void)
        littleton_init_spi();
        littleton_init_i2c();
+        littleton_init_mmc();
        littleton_init_lcd();
        littleton_init_keypad();
        littleton_init_nand();
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index c899bbd94dc0..ca39669cffc5 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -36,7 +36,7 @@
 #include <mach/pxa27x.h>
 #include <mach/magician.h>
 #include <mach/pxafb.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
@@ -745,6 +745,14 @@ static struct platform_device strataflash = {
 };
 /*
+ * I2C
+ */
+static struct i2c_pxa_platform_data i2c_info = {
+        .fast_mode = 1,
+};
+/*
 * Platform devices
 */
@@ -771,7 +779,7 @@ static void __init magician_init(void)
        pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        platform_add_devices(ARRAY_AND_SIZE(devices));
        err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN");
        if (!err) {
@@ -779,7 +787,7 @@ static void __init magician_init(void)
                pxa_set_ficp_info(&magician_ficp_info);
        }
        pxa27x_set_i2c_power_info(NULL);
-        pxa_set_i2c_info(NULL);
+        pxa_set_i2c_info(&i2c_info);
        pxa_set_mci_info(&magician_mci_info);
        pxa_set_ohci_info(&magician_ohci_info);
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index a6c8429e975f..f4dabf0273ca 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -46,7 +46,7 @@
 #include <mach/mainstone.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index ff8052ce0a05..4dc8c2ec40a9 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -48,7 +48,7 @@
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/pxa27x-udc.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
 #include <media/soc_camera.h>
@@ -798,7 +798,7 @@ static void mioa701_restart(char c, const char *cmd)
        arm_machine_restart('s', cmd);
 }
-struct gpio_ress global_gpios[] = {
+static struct gpio_ress global_gpios[] = {
        MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"),
        MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"),
        MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power")
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 471a853e548b..ed70f281dd09 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -129,7 +129,7 @@ static unsigned long palmld_pin_config[] __initdata = {
        GPIO81_GPIO,    /* wifi reset */
        /* HDD */
-        GPIO95_GPIO,    /* HDD irq */
+        GPIO98_GPIO,    /* HDD reset */
        GPIO115_GPIO,   /* HDD power */
        /* MISC */
@@ -496,6 +496,14 @@ static struct platform_device palmld_asoc = {
 };
 /******************************************************************************
+ * HDD
+ ******************************************************************************/
+static struct platform_device palmld_hdd = {
+        .name   = "pata_palmld",
+        .id     = -1,
+};
+/******************************************************************************
 * Framebuffer
 ******************************************************************************/
 static struct pxafb_mode_info palmld_lcd_modes[] = {
@@ -524,30 +532,18 @@ static struct pxafb_mach_info palmld_lcd_screen = {
 /******************************************************************************
 * Power management - standby
 ******************************************************************************/
-#ifdef CONFIG_PM
+static void __init palmld_pm_init(void)
-static u32 *addr __initdata;
-static u32 resume[3] __initdata = {
-        0xe3a00101,     /* mov  r0,     #0x40000000 */
-        0xe380060f,     /* orr  r0, r0, #0x00f00000 */
-        0xe590f008,     /* ldr  pc, [r0, #0x08] */
-};
-static int __init palmld_pm_init(void)
 {
-        int i;
+        static u32 resume[] = {
+                0xe3a00101,     /* mov  r0,     #0x40000000 */
-        /* this is where the bootloader jumps */
+                0xe380060f,     /* orr  r0, r0, #0x00f00000 */
-        addr = phys_to_virt(PALMLD_STR_BASE);
+                0xe590f008,     /* ldr  pc, [r0, #0x08] */
+        };
-        for (i = 0; i < 3; i++)
-                addr[i] = resume[i];
+        /* copy the bootloader */
+        memcpy(phys_to_virt(PALMLD_STR_BASE), resume, sizeof(resume));
-        return 0;
 }
-device_initcall(palmld_pm_init);
-#endif
 /******************************************************************************
 * Machine init
 ******************************************************************************/
@@ -559,6 +555,7 @@ static struct platform_device *devices[] __initdata = {
        &palmld_leds,
        &power_supply,
        &palmld_asoc,
+        &palmld_hdd,
 };
 static struct map_desc palmld_io_desc[] __initdata = {
@@ -586,6 +583,7 @@ static void __init palmld_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config));
+        palmld_pm_init();
        set_pxa_fb_info(&palmld_lcd_screen);
        pxa_set_mci_info(&palmld_mci_platform_data);
        pxa_set_ac97_info(&palmld_ac97_pdata);
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 05bf979b78a6..aae64a12a734 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -26,6 +26,7 @@
 #include <linux/gpio.h>
 #include <linux/wm97xx_batt.h>
 #include <linux/power_supply.h>
+#include <linux/usb/gpio_vbus.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -343,11 +344,18 @@ static struct pxaficp_platform_data palmt5_ficp_platform_data = {
 /******************************************************************************
 * UDC
 ******************************************************************************/
-static struct pxa2xx_udc_mach_info palmt5_udc_info __initdata = {
+static struct gpio_vbus_mach_info palmt5_udc_info = {
        .gpio_vbus              = GPIO_NR_PALMT5_USB_DETECT_N,
        .gpio_vbus_inverted     = 1,
        .gpio_pullup            = GPIO_NR_PALMT5_USB_PULLUP,
-        .gpio_pullup_inverted   = 0,
+};
+static struct platform_device palmt5_gpio_vbus = {
+        .name   = "gpio-vbus",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmt5_udc_info,
+        },
 };
 /******************************************************************************
@@ -466,30 +474,18 @@ static struct pxafb_mach_info palmt5_lcd_screen = {
 /******************************************************************************
 * Power management - standby
 ******************************************************************************/
-#ifdef CONFIG_PM
+static void __init palmt5_pm_init(void)
-static u32 *addr __initdata;
-static u32 resume[3] __initdata = {
-        0xe3a00101,     /* mov  r0,     #0x40000000 */
-        0xe380060f,     /* orr  r0, r0, #0x00f00000 */
-        0xe590f008,     /* ldr  pc, [r0, #0x08] */
-};
-static int __init palmt5_pm_init(void)
 {
-        int i;
+        static u32 resume[] = {
+                0xe3a00101,     /* mov  r0,     #0x40000000 */
-        /* this is where the bootloader jumps */
+                0xe380060f,     /* orr  r0, r0, #0x00f00000 */
-        addr = phys_to_virt(PALMT5_STR_BASE);
+                0xe590f008,     /* ldr  pc, [r0, #0x08] */
+        };
-        for (i = 0; i < 3; i++)
-                addr[i] = resume[i];
+        /* copy the bootloader */
+        memcpy(phys_to_virt(PALMT5_STR_BASE), resume, sizeof(resume));
-        return 0;
 }
-device_initcall(palmt5_pm_init);
-#endif
 /******************************************************************************
 * Machine init
 ******************************************************************************/
@@ -500,6 +496,7 @@ static struct platform_device *devices[] __initdata = {
        &palmt5_backlight,
        &power_supply,
        &palmt5_asoc,
+        &palmt5_gpio_vbus,
 };
 /* setup udc GPIOs initial state */
@@ -515,14 +512,15 @@ static void __init palmt5_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config));
+        palmt5_pm_init();
        set_pxa_fb_info(&palmt5_lcd_screen);
        pxa_set_mci_info(&palmt5_mci_platform_data);
        palmt5_udc_init();
        pxa_set_ac97_info(&palmt5_ac97_pdata);
-        pxa_set_udc_info(&palmt5_udc_info);
        pxa_set_ficp_info(&palmt5_ficp_platform_data);
        pxa_set_keypad_info(&palmt5_keypad_platform_data);
        wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 43fcf2e86887..d823b09801df 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/wm97xx_batt.h>
 #include <linux/power_supply.h>
+#include <linux/usb/gpio_vbus.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -37,6 +38,7 @@
 #include <mach/mfp-pxa25x.h>
 #include <mach/irda.h>
 #include <mach/udc.h>
+#include <mach/palmasoc.h>
 #include "generic.h"
 #include "devices.h"
@@ -107,6 +109,7 @@ static unsigned long palmte2_pin_config[] __initdata = {
        GPIO1_RST,      /* reset */
        GPIO4_GPIO,     /* Hotsync button */
        GPIO9_GPIO,     /* power detect */
+        GPIO15_GPIO,    /* earphone detect */
        GPIO37_GPIO,    /* LCD power */
        GPIO56_GPIO,    /* Backlight power */
 };
@@ -318,11 +321,18 @@ static struct pxaficp_platform_data palmte2_ficp_platform_data = {
 /******************************************************************************
 * UDC
 ******************************************************************************/
-static struct pxa2xx_udc_mach_info palmte2_udc_info __initdata = {
+static struct gpio_vbus_mach_info palmte2_udc_info = {
        .gpio_vbus              = GPIO_NR_PALMTE2_USB_DETECT_N,
        .gpio_vbus_inverted     = 1,
        .gpio_pullup            = GPIO_NR_PALMTE2_USB_PULLUP,
-        .gpio_pullup_inverted   = 0,
+};
+static struct platform_device palmte2_gpio_vbus = {
+        .name   = "gpio-vbus",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmte2_udc_info,
+        },
 };
 /******************************************************************************
@@ -395,6 +405,21 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
 };
 /******************************************************************************
+ * aSoC audio
+ ******************************************************************************/
+static struct palm27x_asoc_info palmte2_asoc_pdata = {
+        .jack_gpio      = GPIO_NR_PALMTE2_EARPHONE_DETECT,
+};
+static struct platform_device palmte2_asoc = {
+        .name = "palm27x-asoc",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &palmte2_asoc_pdata,
+        },
+};
+/******************************************************************************
 * Framebuffer
 ******************************************************************************/
 static struct pxafb_mode_info palmte2_lcd_modes[] = {
@@ -429,6 +454,8 @@ static struct platform_device *devices[] __initdata = {
 #endif
        &palmte2_backlight,
        &power_supply,
+        &palmte2_asoc,
+        &palmte2_gpio_vbus,
 };
 /* setup udc GPIOs initial state */
@@ -447,7 +474,6 @@ static void __init palmte2_init(void)
        set_pxa_fb_info(&palmte2_lcd_screen);
        pxa_set_mci_info(&palmte2_mci_platform_data);
        palmte2_udc_init();
-        pxa_set_udc_info(&palmte2_udc_info);
        pxa_set_ac97_info(NULL);
        pxa_set_ficp_info(&palmte2_ficp_platform_data);
        wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index e99a893c58a7..6c15d84bde53 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -27,6 +27,7 @@
 #include <linux/gpio.h>
 #include <linux/wm97xx_batt.h>
 #include <linux/power_supply.h>
+#include <linux/usb/gpio_vbus.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -359,11 +360,18 @@ static struct pxaficp_platform_data palmtx_ficp_platform_data = {
 /******************************************************************************
 * UDC
 ******************************************************************************/
-static struct pxa2xx_udc_mach_info palmtx_udc_info __initdata = {
+static struct gpio_vbus_mach_info palmtx_udc_info = {
        .gpio_vbus              = GPIO_NR_PALMTX_USB_DETECT_N,
        .gpio_vbus_inverted     = 1,
        .gpio_pullup            = GPIO_NR_PALMTX_USB_PULLUP,
-        .gpio_pullup_inverted   = 0,
+};
+static struct platform_device palmtx_gpio_vbus = {
+        .name   = "gpio-vbus",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmtx_udc_info,
+        },
 };
 /******************************************************************************
@@ -483,30 +491,18 @@ static struct pxafb_mach_info palmtx_lcd_screen = {
 /******************************************************************************
 * Power management - standby
 ******************************************************************************/
-#ifdef CONFIG_PM
+static void __init palmtx_pm_init(void)
-static u32 *addr __initdata;
-static u32 resume[3] __initdata = {
-        0xe3a00101,     /* mov  r0,     #0x40000000 */
-        0xe380060f,     /* orr  r0, r0, #0x00f00000 */
-        0xe590f008,     /* ldr  pc, [r0, #0x08] */
-};
-static int __init palmtx_pm_init(void)
 {
-        int i;
+        static u32 resume[] = {
+                0xe3a00101,     /* mov  r0,     #0x40000000 */
-        /* this is where the bootloader jumps */
+                0xe380060f,     /* orr  r0, r0, #0x00f00000 */
-        addr = phys_to_virt(PALMTX_STR_BASE);
+                0xe590f008,     /* ldr  pc, [r0, #0x08] */
+        };
-        for (i = 0; i < 3; i++)
-                addr[i] = resume[i];
+        /* copy the bootloader */
+        memcpy(phys_to_virt(PALMTX_STR_BASE), resume, sizeof(resume));
-        return 0;
 }
-device_initcall(palmtx_pm_init);
-#endif
 /******************************************************************************
 * Machine init
 ******************************************************************************/
@@ -517,6 +513,7 @@ static struct platform_device *devices[] __initdata = {
        &palmtx_backlight,
        &power_supply,
        &palmtx_asoc,
+        &palmtx_gpio_vbus,
 };
 static struct map_desc palmtx_io_desc[] __initdata = {
@@ -548,11 +545,11 @@ static void __init palmtx_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config));
+        palmtx_pm_init();
        set_pxa_fb_info(&palmtx_lcd_screen);
        pxa_set_mci_info(&palmtx_mci_platform_data);
        palmtx_udc_init();
        pxa_set_ac97_info(&palmtx_ac97_pdata);
-        pxa_set_udc_info(&palmtx_udc_info);
        pxa_set_ficp_info(&palmtx_ficp_platform_data);
        pxa_set_keypad_info(&palmtx_keypad_platform_data);
        wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 6c12b5a3132f..01791d74e08e 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -28,7 +28,7 @@
 #include <media/soc_camera.h>
 #include <asm/gpio.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/camera.h>
 #include <asm/mach/map.h>
 #include <mach/pxa27x.h>
@@ -380,12 +380,12 @@ static struct pca953x_platform_data pca9536_data = {
        .gpio_base      = NR_BUILTIN_GPIO,
 };
-static int gpio_bus_switch;
+static int gpio_bus_switch = -EINVAL;
 static int pcm990_camera_set_bus_param(struct soc_camera_link *link,
-                unsigned long flags)
+                                       unsigned long flags)
 {
-        if (gpio_bus_switch <= 0) {
+        if (gpio_bus_switch < 0) {
                if (flags == SOCAM_DATAWIDTH_10)
                        return 0;
                else
@@ -404,25 +404,34 @@ static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link)
 {
        int ret;
-        if (!gpio_bus_switch) {
+        if (gpio_bus_switch < 0) {
                ret = gpio_request(NR_BUILTIN_GPIO, "camera");
                if (!ret) {
                        gpio_bus_switch = NR_BUILTIN_GPIO;
                        gpio_direction_output(gpio_bus_switch, 0);
-                } else
+                }
-                        gpio_bus_switch = -EINVAL;
        }
-        if (gpio_bus_switch > 0)
+        if (gpio_bus_switch >= 0)
                return SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_10;
        else
                return SOCAM_DATAWIDTH_10;
 }
+static void pcm990_camera_free_bus(struct soc_camera_link *link)
+{
+        if (gpio_bus_switch < 0)
+                return;
+        gpio_free(gpio_bus_switch);
+        gpio_bus_switch = -EINVAL;
+}
 static struct soc_camera_link iclink = {
        .bus_id = 0, /* Must match with the camera ID above */
        .query_bus_param = pcm990_camera_query_bus_param,
        .set_bus_param = pcm990_camera_set_bus_param,
+        .free_bus = pcm990_camera_free_bus,
 };
 /* Board I2C devices. */
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 884b174c8ead..7693355ee637 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -79,7 +79,7 @@ static int pxa_pm_valid(suspend_state_t state)
        return -EINVAL;
 }
-static int pxa_pm_prepare(void)
+int pxa_pm_prepare(void)
 {
        int ret = 0;
@@ -89,7 +89,7 @@ static int pxa_pm_prepare(void)
        return ret;
 }
-static void pxa_pm_finish(void)
+void pxa_pm_finish(void)
 {
        if (pxa_cpu_pm_fns && pxa_cpu_pm_fns->finish)
                pxa_cpu_pm_fns->finish();
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 036bbde4d221..ac431ed10399 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -39,7 +39,7 @@
 #include <mach/pxa25x.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/poodle.h>
 #include <mach/pxafb.h>
@@ -214,13 +214,8 @@ static struct ads7846_platform_data poodle_ads7846_info = {
        .gpio_pendown           = POODLE_GPIO_TP_INT,
 };
-static void ads7846_cs(u32 command)
-{
-        gpio_set_value(POODLE_GPIO_TP_CS, !(command == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip poodle_ads7846_chip = {
-        .cs_control             = ads7846_cs,
+        .gpio_cs                = POODLE_GPIO_TP_CS,
 };
 static struct spi_board_info poodle_spi_devices[] = {
@@ -236,14 +231,6 @@ static struct spi_board_info poodle_spi_devices[] = {
 static void __init poodle_init_spi(void)
 {
-        int err;
-        err = gpio_request(POODLE_GPIO_TP_CS, "ADS7846_CS");
-        if (err)
-                return;
-        gpio_direction_output(POODLE_GPIO_TP_CS, 1);
        pxa2xx_set_spi_info(1, &poodle_spi_info);
        spi_register_board_info(ARRAY_AND_SIZE(poodle_spi_devices));
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index a425ec71e657..ec68cc16b4e3 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -27,7 +27,7 @@
 #include <mach/ohci.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include "generic.h"
 #include "devices.h"
@@ -204,6 +204,23 @@ static struct clk_lookup pxa27x_clkregs[] = {
 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 /*
+ * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
+ */
+static unsigned int pwrmode = PWRMODE_SLEEP;
+int __init pxa27x_set_pwrmode(unsigned int mode)
+{
+        switch (mode) {
+        case PWRMODE_SLEEP:
+        case PWRMODE_DEEPSLEEP:
+                pwrmode = mode;
+                return 0;
+        }
+        return -EINVAL;
+}
+/*
 * List of global PXA peripheral registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
@@ -254,7 +271,7 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
                pxa_cpu_standby();
                break;
        case PM_SUSPEND_MEM:
-                pxa27x_cpu_suspend(PWRMODE_SLEEP);
+                pxa27x_cpu_suspend(pwrmode);
                break;
        }
 }
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index b02d4544dc95..6f678d93bf4e 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -30,7 +30,7 @@
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/ssp.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include "generic.h"
 #include "devices.h"
@@ -552,7 +552,7 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 static struct platform_device *devices[] __initdata = {
-/*      &pxa_device_udc,        The UDC driver is PXA25x only */
+        &pxa27x_device_udc,
        &pxa_device_ffuart,
        &pxa_device_btuart,
        &pxa_device_stuart,
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index ff8239991430..8241a63ea589 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -27,7 +27,7 @@
 #include <asm/mach/arch.h>
 #include <mach/pxa930.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/pxafb.h>
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h
index 047909a76651..55259f4756c8 100644
--- a/arch/arm/mach-pxa/sharpsl.h
+++ b/arch/arm/mach-pxa/sharpsl.h
@@ -7,7 +7,7 @@
 *
 */
-#include <asm/hardware/sharpsl_pm.h>
+#include <mach/sharpsl_pm.h>
 /*
 * SharpSL SSP Driver
@@ -44,8 +44,6 @@ void corgi_lcdtg_hw_init(int mode);
 extern struct battery_thresh spitz_battery_levels_acin[];
 extern struct battery_thresh spitz_battery_levels_noac[];
-void sharpsl_pm_pxa_init(void);
-void sharpsl_pm_pxa_remove(void);
 int sharpsl_pm_pxa_read_max1111(int channel);
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 16b4ec67e3b6..2546c066cd6e 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -15,20 +15,69 @@
 #undef DEBUG
 #include <linux/module.h>
-#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/suspend.h>
+#include <linux/gpio.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <mach/pm.h>
+#include <mach/pxa2xx-regs.h>
 #include <mach/pxa2xx-gpio.h>
+#include <mach/regs-rtc.h>
 #include <mach/sharpsl.h>
+#include <mach/sharpsl_pm.h>
 #include "sharpsl.h"
+/*
+ * Constants
+ */
+#define SHARPSL_CHARGE_ON_TIME_INTERVAL        (msecs_to_jiffies(1*60*1000))  /* 1 min */
+#define SHARPSL_CHARGE_FINISH_TIME             (msecs_to_jiffies(10*60*1000)) /* 10 min */
+#define SHARPSL_BATCHK_TIME                    (msecs_to_jiffies(15*1000))    /* 15 sec */
+#define SHARPSL_BATCHK_TIME_SUSPEND            (60*10)                        /* 10 min */
+#define SHARPSL_WAIT_CO_TIME                   15  /* 15 sec */
+#define SHARPSL_WAIT_DISCHARGE_ON              100 /* 100 msec */
+#define SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP   10  /* 10 msec */
+#define SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT   10  /* 10 msec */
+#define SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN   10  /* 10 msec */
+#define SHARPSL_CHARGE_WAIT_TIME               15  /* 15 msec */
+#define SHARPSL_CHARGE_CO_CHECK_TIME           5   /* 5 msec */
+#define SHARPSL_CHARGE_RETRY_CNT               1   /* eqv. 10 min */
+/*
+ * Prototypes
+ */
+#ifdef CONFIG_PM
+static int sharpsl_off_charge_battery(void);
+static int sharpsl_check_battery_voltage(void);
+static int sharpsl_fatal_check(void);
+#endif
+static int sharpsl_check_battery_temp(void);
+static int sharpsl_ac_check(void);
+static int sharpsl_average_value(int ad);
+static void sharpsl_average_clear(void);
+static void sharpsl_charge_toggle(struct work_struct *private_);
+static void sharpsl_battery_thread(struct work_struct *private_);
+/*
+ * Variables
+ */
+struct sharpsl_pm_status sharpsl_pm;
+static DECLARE_DELAYED_WORK(toggle_charger, sharpsl_charge_toggle);
+static DECLARE_DELAYED_WORK(sharpsl_bat, sharpsl_battery_thread);
+DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger);
 struct battery_thresh spitz_battery_levels_acin[] = {
        { 213, 100},
        { 212,  98},
@@ -144,42 +193,789 @@ int sharpsl_pm_pxa_read_max1111(int channel)
 #endif
 }
-void sharpsl_pm_pxa_init(void)
+static int get_percentage(int voltage)
+{
+        int i = sharpsl_pm.machinfo->bat_levels - 1;
+        int bl_status = sharpsl_pm.machinfo->backlight_get_status ? sharpsl_pm.machinfo->backlight_get_status() : 0;
+        struct battery_thresh *thresh;
+        if (sharpsl_pm.charge_mode == CHRG_ON)
+                thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_acin_bl : sharpsl_pm.machinfo->bat_levels_acin;
+        else
+                thresh = bl_status ? sharpsl_pm.machinfo->bat_levels_noac_bl : sharpsl_pm.machinfo->bat_levels_noac;
+        while (i > 0 && (voltage > thresh[i].voltage))
+                i--;
+        return thresh[i].percentage;
+}
+static int get_apm_status(int voltage)
+{
+        int low_thresh, high_thresh;
+        if (sharpsl_pm.charge_mode == CHRG_ON) {
+                high_thresh = sharpsl_pm.machinfo->status_high_acin;
+                low_thresh = sharpsl_pm.machinfo->status_low_acin;
+        } else {
+                high_thresh = sharpsl_pm.machinfo->status_high_noac;
+                low_thresh = sharpsl_pm.machinfo->status_low_noac;
+        }
+        if (voltage >= high_thresh)
+                return APM_BATTERY_STATUS_HIGH;
+        if (voltage >= low_thresh)
+                return APM_BATTERY_STATUS_LOW;
+        return APM_BATTERY_STATUS_CRITICAL;
+}
+void sharpsl_battery_kick(void)
+{
+        schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(125));
+}
+EXPORT_SYMBOL(sharpsl_battery_kick);
+static void sharpsl_battery_thread(struct work_struct *private_)
+{
+        int voltage, percent, apm_status, i = 0;
+        if (!sharpsl_pm.machinfo)
+                return;
+        sharpsl_pm.battstat.ac_status = (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN) ? APM_AC_ONLINE : APM_AC_OFFLINE);
+        /* Corgi cannot confirm when battery fully charged so periodically kick! */
+        if (!sharpsl_pm.machinfo->batfull_irq && (sharpsl_pm.charge_mode == CHRG_ON)
+                        && time_after(jiffies, sharpsl_pm.charge_start_time +  SHARPSL_CHARGE_ON_TIME_INTERVAL))
+                schedule_delayed_work(&toggle_charger, 0);
+        while(1) {
+                voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
+                if (voltage > 0) break;
+                if (i++ > 5) {
+                        voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage;
+                        dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n");
+                        break;
+                }
+        }
+        voltage = sharpsl_average_value(voltage);
+        apm_status = get_apm_status(voltage);
+        percent = get_percentage(voltage);
+        /* At low battery voltages, the voltage has a tendency to start
+           creeping back up so we try to avoid this here */
+        if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE) || (apm_status == APM_BATTERY_STATUS_HIGH) ||  percent <= sharpsl_pm.battstat.mainbat_percent) {
+                sharpsl_pm.battstat.mainbat_voltage = voltage;
+                sharpsl_pm.battstat.mainbat_status = apm_status;
+                sharpsl_pm.battstat.mainbat_percent = percent;
+        }
+        dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
+                        sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
+#ifdef CONFIG_BACKLIGHT_CORGI
+        /* If battery is low. limit backlight intensity to save power. */
+        if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
+                        && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
+                        (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) {
+                if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) {
+                        sharpsl_pm.machinfo->backlight_limit(1);
+                        sharpsl_pm.flags |= SHARPSL_BL_LIMIT;
+                }
+        } else if (sharpsl_pm.flags & SHARPSL_BL_LIMIT) {
+                sharpsl_pm.machinfo->backlight_limit(0);
+                sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
+        }
+#endif
+        /* Suspend if critical battery level */
+        if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
+                        && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
+                        && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) {
+                sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
+                dev_err(sharpsl_pm.dev, "Fatal Off\n");
+                apm_queue_event(APM_CRITICAL_SUSPEND);
+        }
+        schedule_delayed_work(&sharpsl_bat, SHARPSL_BATCHK_TIME);
+}
+void sharpsl_pm_led(int val)
+{
+        if (val == SHARPSL_LED_ERROR) {
+                dev_err(sharpsl_pm.dev, "Charging Error!\n");
+        } else if (val == SHARPSL_LED_ON) {
+                dev_dbg(sharpsl_pm.dev, "Charge LED On\n");
+                led_trigger_event(sharpsl_charge_led_trigger, LED_FULL);
+        } else {
+                dev_dbg(sharpsl_pm.dev, "Charge LED Off\n");
+                led_trigger_event(sharpsl_charge_led_trigger, LED_OFF);
+        }
+}
+static void sharpsl_charge_on(void)
+{
+        dev_dbg(sharpsl_pm.dev, "Turning Charger On\n");
+        sharpsl_pm.full_count = 0;
+        sharpsl_pm.charge_mode = CHRG_ON;
+        schedule_delayed_work(&toggle_charger, msecs_to_jiffies(250));
+        schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(500));
+}
+static void sharpsl_charge_off(void)
+{
+        dev_dbg(sharpsl_pm.dev, "Turning Charger Off\n");
+        sharpsl_pm.machinfo->charge(0);
+        sharpsl_pm_led(SHARPSL_LED_OFF);
+        sharpsl_pm.charge_mode = CHRG_OFF;
+        schedule_delayed_work(&sharpsl_bat, 0);
+}
+static void sharpsl_charge_error(void)
 {
-        pxa_gpio_mode(sharpsl_pm.machinfo->gpio_acin | GPIO_IN);
+        sharpsl_pm_led(SHARPSL_LED_ERROR);
-        pxa_gpio_mode(sharpsl_pm.machinfo->gpio_batfull | GPIO_IN);
+        sharpsl_pm.machinfo->charge(0);
-        pxa_gpio_mode(sharpsl_pm.machinfo->gpio_batlock | GPIO_IN);
+        sharpsl_pm.charge_mode = CHRG_ERROR;
+}
+static void sharpsl_charge_toggle(struct work_struct *private_)
+{
+        dev_dbg(sharpsl_pm.dev, "Toogling Charger at time: %lx\n", jiffies);
+        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
+                sharpsl_charge_off();
+                return;
+        } else if ((sharpsl_check_battery_temp() < 0) || (sharpsl_ac_check() < 0)) {
+                sharpsl_charge_error();
+                return;
+        }
+        sharpsl_pm_led(SHARPSL_LED_ON);
+        sharpsl_pm.machinfo->charge(0);
+        mdelay(SHARPSL_CHARGE_WAIT_TIME);
+        sharpsl_pm.machinfo->charge(1);
+        sharpsl_pm.charge_start_time = jiffies;
+}
+static void sharpsl_ac_timer(unsigned long data)
+{
+        int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
+        dev_dbg(sharpsl_pm.dev, "AC Status: %d\n",acin);
+        sharpsl_average_clear();
+        if (acin && (sharpsl_pm.charge_mode != CHRG_ON))
+                sharpsl_charge_on();
+        else if (sharpsl_pm.charge_mode == CHRG_ON)
+                sharpsl_charge_off();
+        schedule_delayed_work(&sharpsl_bat, 0);
+}
+static irqreturn_t sharpsl_ac_isr(int irq, void *dev_id)
+{
+        /* Delay the event slightly to debounce */
+        /* Must be a smaller delay than the chrg_full_isr below */
+        mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
+        return IRQ_HANDLED;
+}
+static void sharpsl_chrg_full_timer(unsigned long data)
+{
+        dev_dbg(sharpsl_pm.dev, "Charge Full at time: %lx\n", jiffies);
+        sharpsl_pm.full_count++;
+        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
+                dev_dbg(sharpsl_pm.dev, "Charge Full: AC removed - stop charging!\n");
+                if (sharpsl_pm.charge_mode == CHRG_ON)
+                        sharpsl_charge_off();
+        } else if (sharpsl_pm.full_count < 2) {
+                dev_dbg(sharpsl_pm.dev, "Charge Full: Count too low\n");
+                schedule_delayed_work(&toggle_charger, 0);
+        } else if (time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_FINISH_TIME)) {
+                dev_dbg(sharpsl_pm.dev, "Charge Full: Interrupt generated too slowly - retry.\n");
+                schedule_delayed_work(&toggle_charger, 0);
+        } else {
+                sharpsl_charge_off();
+                sharpsl_pm.charge_mode = CHRG_DONE;
+                dev_dbg(sharpsl_pm.dev, "Charge Full: Charging Finished\n");
+        }
+}
+/* Charging Finished Interrupt (Not present on Corgi) */
+/* Can trigger at the same time as an AC status change so
+   delay until after that has been processed */
+static irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id)
+{
+        if (sharpsl_pm.flags & SHARPSL_SUSPENDED)
+                return IRQ_HANDLED;
+        /* delay until after any ac interrupt */
+        mod_timer(&sharpsl_pm.chrg_full_timer, jiffies + msecs_to_jiffies(500));
+        return IRQ_HANDLED;
+}
+static irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id)
+{
+        int is_fatal = 0;
+        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) {
+                dev_err(sharpsl_pm.dev, "Battery now Unlocked! Suspending.\n");
+                is_fatal = 1;
+        }
+        if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL)) {
+                dev_err(sharpsl_pm.dev, "Fatal Batt Error! Suspending.\n");
+                is_fatal = 1;
+        }
+        if (!(sharpsl_pm.flags & SHARPSL_APM_QUEUED) && is_fatal) {
+                sharpsl_pm.flags |= SHARPSL_APM_QUEUED;
+                apm_queue_event(APM_CRITICAL_SUSPEND);
+        }
+        return IRQ_HANDLED;
+}
+/*
+ * Maintain an average of the last 10 readings
+ */
+#define SHARPSL_CNV_VALUE_NUM    10
+static int sharpsl_ad_index;
+static void sharpsl_average_clear(void)
+{
+        sharpsl_ad_index = 0;
+}
+static int sharpsl_average_value(int ad)
+{
+        int i, ad_val = 0;
+        static int sharpsl_ad[SHARPSL_CNV_VALUE_NUM+1];
+        if (sharpsl_pm.battstat.mainbat_status != APM_BATTERY_STATUS_HIGH) {
+                sharpsl_ad_index = 0;
+                return ad;
+        }
+        sharpsl_ad[sharpsl_ad_index] = ad;
+        sharpsl_ad_index++;
+        if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) {
+                for (i=0; i < (SHARPSL_CNV_VALUE_NUM-1); i++)
+                        sharpsl_ad[i] = sharpsl_ad[i+1];
+                sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1;
+        }
+        for (i=0; i < sharpsl_ad_index; i++)
+                ad_val += sharpsl_ad[i];
+        return (ad_val / sharpsl_ad_index);
+}
+/*
+ * Take an array of 5 integers, remove the maximum and minimum values
+ * and return the average.
+ */
+static int get_select_val(int *val)
+{
+        int i, j, k, temp, sum = 0;
+        /* Find MAX val */
+        temp = val[0];
+        j=0;
+        for (i=1; i<5; i++) {
+                if (temp < val[i]) {
+                        temp = val[i];
+                        j = i;
+                }
+        }
+        /* Find MIN val */
+        temp = val[4];
+        k=4;
+        for (i=3; i>=0; i--) {
+                if (temp > val[i]) {
+                        temp = val[i];
+                        k = i;
+                }
+        }
+        for (i=0; i<5; i++)
+                if (i != j && i != k )
+                        sum += val[i];
+        dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]);
+        return (sum/3);
+}
+static int sharpsl_check_battery_temp(void)
+{
+        int val, i, buff[5];
+        /* Check battery temperature */
+        for (i=0; i<5; i++) {
+                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
+                sharpsl_pm.machinfo->measure_temp(1);
+                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP);
+                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_TEMP);
+                sharpsl_pm.machinfo->measure_temp(0);
+        }
+        val = get_select_val(buff);
+        dev_dbg(sharpsl_pm.dev, "Temperature: %d\n", val);
+        if (val > sharpsl_pm.machinfo->charge_on_temp) {
+                printk(KERN_WARNING "Not charging: temperature out of limits.\n");
+                return -1;
+        }
+        return 0;
+}
+#ifdef CONFIG_PM
+static int sharpsl_check_battery_voltage(void)
+{
+        int val, i, buff[5];
+        /* disable charge, enable discharge */
+        sharpsl_pm.machinfo->charge(0);
+        sharpsl_pm.machinfo->discharge(1);
+        mdelay(SHARPSL_WAIT_DISCHARGE_ON);
+        if (sharpsl_pm.machinfo->discharge1)
+                sharpsl_pm.machinfo->discharge1(1);
+        /* Check battery voltage */
+        for (i=0; i<5; i++) {
+                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
+                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
+        }
+        if (sharpsl_pm.machinfo->discharge1)
+                sharpsl_pm.machinfo->discharge1(0);
+        sharpsl_pm.machinfo->discharge(0);
+        val = get_select_val(buff);
+        dev_dbg(sharpsl_pm.dev, "Battery Voltage: %d\n", val);
+        if (val < sharpsl_pm.machinfo->charge_on_volt)
+                return -1;
+        return 0;
+}
+#endif
+static int sharpsl_ac_check(void)
+{
+        int temp, i, buff[5];
+        for (i=0; i<5; i++) {
+                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT);
+                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN);
+        }
+        temp = get_select_val(buff);
+        dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n",temp);
+        if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) {
+                dev_err(sharpsl_pm.dev, "Error: AC check failed.\n");
+                return -1;
+        }
+        return 0;
+}
+#ifdef CONFIG_PM
+static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        sharpsl_pm.flags |= SHARPSL_SUSPENDED;
+        flush_scheduled_work();
+        if (sharpsl_pm.charge_mode == CHRG_ON)
+                sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
+        else
+                sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
+        return 0;
+}
+static int sharpsl_pm_resume(struct platform_device *pdev)
+{
+        /* Clear the reset source indicators as they break the bootloader upon reboot */
+        RCSR = 0x0f;
+        sharpsl_average_clear();
+        sharpsl_pm.flags &= ~SHARPSL_APM_QUEUED;
+        sharpsl_pm.flags &= ~SHARPSL_SUSPENDED;
+        return 0;
+}
+static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
+{
+        dev_dbg(sharpsl_pm.dev, "Time is: %08x\n",RCNR);
+        dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n",sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG);
+        /* not charging and AC-IN! */
+        if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) {
+                dev_dbg(sharpsl_pm.dev, "Activating Offline Charger...\n");
+                sharpsl_pm.charge_mode = CHRG_OFF;
+                sharpsl_pm.flags &= ~SHARPSL_DO_OFFLINE_CHRG;
+                sharpsl_off_charge_battery();
+        }
+        sharpsl_pm.machinfo->presuspend();
+        PEDR = 0xffffffff; /* clear it */
+        sharpsl_pm.flags &= ~SHARPSL_ALARM_ACTIVE;
+        if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) {
+                RTSR &= RTSR_ALE;
+                RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND;
+                dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n",RTAR);
+                sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE;
+        } else if (alarm_enable) {
+                RTSR &= RTSR_ALE;
+                RTAR = alarm_time;
+                dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n",RTAR);
+        } else {
+                dev_dbg(sharpsl_pm.dev, "No alarms set.\n");
+        }
+        pxa_pm_enter(state);
+        sharpsl_pm.machinfo->postsuspend();
+        dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n",PEDR);
+}
+static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state)
+{
+        if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable) )
+        {
+                if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) {
+                        dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n");
+                        corgi_goto_sleep(alarm_time, alarm_enable, state);
+                        return 1;
+                }
+                if(sharpsl_off_charge_battery()) {
+                        dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n");
+                        corgi_goto_sleep(alarm_time, alarm_enable, state);
+                        return 1;
+                }
+                dev_dbg(sharpsl_pm.dev, "User triggered wakeup in offline charger.\n");
+        }
+        if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) || (sharpsl_fatal_check() < 0) )
+        {
+                dev_err(sharpsl_pm.dev, "Fatal condition. Suspend.\n");
+                corgi_goto_sleep(alarm_time, alarm_enable, state);
+                return 1;
+        }
+        return 0;
+}
+static int corgi_pxa_pm_enter(suspend_state_t state)
+{
+        unsigned long alarm_time = RTAR;
+        unsigned int alarm_status = ((RTSR & RTSR_ALE) != 0);
+        dev_dbg(sharpsl_pm.dev, "SharpSL suspending for first time.\n");
+        corgi_goto_sleep(alarm_time, alarm_status, state);
+        while (corgi_enter_suspend(alarm_time,alarm_status,state))
+                {}
+        if (sharpsl_pm.machinfo->earlyresume)
+                sharpsl_pm.machinfo->earlyresume();
+        dev_dbg(sharpsl_pm.dev, "SharpSL resuming...\n");
+        return 0;
+}
+/*
+ * Check for fatal battery errors
+ * Fatal returns -1
+ */
+static int sharpsl_fatal_check(void)
+{
+        int buff[5], temp, i, acin;
+        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check entered\n");
+        /* Check AC-Adapter */
+        acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
+        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
+                sharpsl_pm.machinfo->charge(0);
+                udelay(100);
+                sharpsl_pm.machinfo->discharge(1);      /* enable discharge */
+                mdelay(SHARPSL_WAIT_DISCHARGE_ON);
+        }
+        if (sharpsl_pm.machinfo->discharge1)
+                sharpsl_pm.machinfo->discharge1(1);
+        /* Check battery : check inserting battery ? */
+        for (i=0; i<5; i++) {
+                buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT);
+                mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT);
+        }
+        if (sharpsl_pm.machinfo->discharge1)
+                sharpsl_pm.machinfo->discharge1(0);
+        if (acin && (sharpsl_pm.charge_mode == CHRG_ON)) {
+                udelay(100);
+                sharpsl_pm.machinfo->charge(1);
+                sharpsl_pm.machinfo->discharge(0);
+        }
+        temp = get_select_val(buff);
+        dev_dbg(sharpsl_pm.dev, "sharpsl_fatal_check: acin: %d, discharge voltage: %d, no discharge: %ld\n", acin, temp, sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT));
+        if ((acin && (temp < sharpsl_pm.machinfo->fatal_acin_volt)) ||
+                        (!acin && (temp < sharpsl_pm.machinfo->fatal_noacin_volt)))
+                return -1;
+        return 0;
+}
+static int sharpsl_off_charge_error(void)
+{
+        dev_err(sharpsl_pm.dev, "Offline Charger: Error occurred.\n");
+        sharpsl_pm.machinfo->charge(0);
+        sharpsl_pm_led(SHARPSL_LED_ERROR);
+        sharpsl_pm.charge_mode = CHRG_ERROR;
+        return 1;
+}
+/*
+ * Charging Control while suspended
+ * Return 1 - go straight to sleep
+ * Return 0 - sleep or wakeup depending on other factors
+ */
+static int sharpsl_off_charge_battery(void)
+{
+        int time;
+        dev_dbg(sharpsl_pm.dev, "Charge Mode: %d\n", sharpsl_pm.charge_mode);
+        if (sharpsl_pm.charge_mode == CHRG_OFF) {
+                dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 1\n");
+                /* AC Check */
+                if ((sharpsl_ac_check() < 0) || (sharpsl_check_battery_temp() < 0))
+                        return sharpsl_off_charge_error();
+                /* Start Charging */
+                sharpsl_pm_led(SHARPSL_LED_ON);
+                sharpsl_pm.machinfo->charge(0);
+                mdelay(SHARPSL_CHARGE_WAIT_TIME);
+                sharpsl_pm.machinfo->charge(1);
+                sharpsl_pm.charge_mode = CHRG_ON;
+                sharpsl_pm.full_count = 0;
+                return 1;
+        } else if (sharpsl_pm.charge_mode != CHRG_ON) {
+                return 1;
+        }
+        if (sharpsl_pm.full_count == 0) {
+                int time;
+                dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 2\n");
+                if ((sharpsl_check_battery_temp() < 0) || (sharpsl_check_battery_voltage() < 0))
+                        return sharpsl_off_charge_error();
+                sharpsl_pm.machinfo->charge(0);
+                mdelay(SHARPSL_CHARGE_WAIT_TIME);
+                sharpsl_pm.machinfo->charge(1);
+                sharpsl_pm.charge_mode = CHRG_ON;
+                mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
+                time = RCNR;
+                while(1) {
+                        /* Check if any wakeup event had occurred */
+                        if (sharpsl_pm.machinfo->charger_wakeup() != 0)
+                                return 0;
+                        /* Check for timeout */
+                        if ((RCNR - time) > SHARPSL_WAIT_CO_TIME)
+                                return 1;
+                        if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
+                                dev_dbg(sharpsl_pm.dev, "Offline Charger: Charge full occurred. Retrying to check\n");
+                                sharpsl_pm.full_count++;
+                                sharpsl_pm.machinfo->charge(0);
+                                mdelay(SHARPSL_CHARGE_WAIT_TIME);
+                                sharpsl_pm.machinfo->charge(1);
+                                return 1;
+                        }
+                }
+        }
+        dev_dbg(sharpsl_pm.dev, "Offline Charger: Step 3\n");
+        mdelay(SHARPSL_CHARGE_CO_CHECK_TIME);
+        time = RCNR;
+        while(1) {
+                /* Check if any wakeup event had occurred */
+                if (sharpsl_pm.machinfo->charger_wakeup() != 0)
+                        return 0;
+                /* Check for timeout */
+                if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) {
+                        if (sharpsl_pm.full_count > SHARPSL_CHARGE_RETRY_CNT) {
+                                dev_dbg(sharpsl_pm.dev, "Offline Charger: Not charged sufficiently. Retrying.\n");
+                                sharpsl_pm.full_count = 0;
+                        }
+                        sharpsl_pm.full_count++;
+                        return 1;
+                }
+                if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_CHRGFULL)) {
+                        dev_dbg(sharpsl_pm.dev, "Offline Charger: Charging complete.\n");
+                        sharpsl_pm_led(SHARPSL_LED_OFF);
+                        sharpsl_pm.machinfo->charge(0);
+                        sharpsl_pm.charge_mode = CHRG_DONE;
+                        return 1;
+                }
+        }
+}
+#else
+#define sharpsl_pm_suspend      NULL
+#define sharpsl_pm_resume       NULL
+#endif
+static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_percent);
+}
+static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_voltage);
+}
+static DEVICE_ATTR(battery_percentage, 0444, battery_percentage_show, NULL);
+static DEVICE_ATTR(battery_voltage, 0444, battery_voltage_show, NULL);
+extern void (*apm_get_power_status)(struct apm_power_info *);
+static void sharpsl_apm_get_power_status(struct apm_power_info *info)
+{
+        info->ac_line_status = sharpsl_pm.battstat.ac_status;
+        if (sharpsl_pm.charge_mode == CHRG_ON)
+                info->battery_status = APM_BATTERY_STATUS_CHARGING;
+        else
+                info->battery_status = sharpsl_pm.battstat.mainbat_status;
+        info->battery_flag = (1 << info->battery_status);
+        info->battery_life = sharpsl_pm.battstat.mainbat_percent;
+}
+#ifdef CONFIG_PM
+static struct platform_suspend_ops sharpsl_pm_ops = {
+        .prepare        = pxa_pm_prepare,
+        .finish         = pxa_pm_finish,
+        .enter          = corgi_pxa_pm_enter,
+        .valid          = suspend_valid_only_mem,
+};
+#endif
+static int __init sharpsl_pm_probe(struct platform_device *pdev)
+{
+        int ret;
+        if (!pdev->dev.platform_data)
+                return -EINVAL;
+        sharpsl_pm.dev = &pdev->dev;
+        sharpsl_pm.machinfo = pdev->dev.platform_data;
+        sharpsl_pm.charge_mode = CHRG_OFF;
+        sharpsl_pm.flags = 0;
+        init_timer(&sharpsl_pm.ac_timer);
+        sharpsl_pm.ac_timer.function = sharpsl_ac_timer;
+        init_timer(&sharpsl_pm.chrg_full_timer);
+        sharpsl_pm.chrg_full_timer.function = sharpsl_chrg_full_timer;
+        led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger);
+        sharpsl_pm.machinfo->init();
+        gpio_request(sharpsl_pm.machinfo->gpio_acin, "AC IN");
+        gpio_direction_input(sharpsl_pm.machinfo->gpio_acin);
+        gpio_request(sharpsl_pm.machinfo->gpio_batfull, "Battery Full");
+        gpio_direction_input(sharpsl_pm.machinfo->gpio_batfull);
+        gpio_request(sharpsl_pm.machinfo->gpio_batlock, "Battery Lock");
+        gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock);
        /* Register interrupt handlers */
-        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED, "AC Input Detect", sharpsl_ac_isr)) {
+        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin));
        }
-        else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQ_TYPE_EDGE_BOTH);
-        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED, "Battery Cover", sharpsl_fatal_isr)) {
+        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock));
        }
-        else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQ_TYPE_EDGE_FALLING);
        if (sharpsl_pm.machinfo->gpio_fatal) {
-                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED, "Fatal Battery", sharpsl_fatal_isr)) {
+                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal));
                }
-                else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQ_TYPE_EDGE_FALLING);
        }
        if (sharpsl_pm.machinfo->batfull_irq)
        {
                /* Register interrupt handler. */
-                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED, "CO", sharpsl_chrg_full_isr)) {
+                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull));
                }
-                else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQ_TYPE_EDGE_RISING);
        }
+        ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage);
+        ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage);
+        if (ret != 0)
+                dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret);
+        apm_get_power_status = sharpsl_apm_get_power_status;
+#ifdef CONFIG_PM
+        suspend_set_ops(&sharpsl_pm_ops);
+#endif
+        mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
+        return 0;
 }
-void sharpsl_pm_pxa_remove(void)
+static int sharpsl_pm_remove(struct platform_device *pdev)
 {
+        suspend_set_ops(NULL);
+        device_remove_file(&pdev->dev, &dev_attr_battery_percentage);
+        device_remove_file(&pdev->dev, &dev_attr_battery_voltage);
+        led_trigger_unregister_simple(sharpsl_charge_led_trigger);
        free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
        free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
@@ -188,4 +984,39 @@ void sharpsl_pm_pxa_remove(void)
        if (sharpsl_pm.machinfo->batfull_irq)
                free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
+        gpio_free(sharpsl_pm.machinfo->gpio_batlock);
+        gpio_free(sharpsl_pm.machinfo->gpio_batfull);
+        gpio_free(sharpsl_pm.machinfo->gpio_acin);
+        if (sharpsl_pm.machinfo->exit)
+                sharpsl_pm.machinfo->exit();
+        del_timer_sync(&sharpsl_pm.chrg_full_timer);
+        del_timer_sync(&sharpsl_pm.ac_timer);
+        return 0;
 }
+static struct platform_driver sharpsl_pm_driver = {
+        .probe          = sharpsl_pm_probe,
+        .remove         = sharpsl_pm_remove,
+        .suspend        = sharpsl_pm_suspend,
+        .resume         = sharpsl_pm_resume,
+        .driver         = {
+                .name           = "sharpsl-pm",
+        },
+};
+static int __devinit sharpsl_pm_init(void)
+{
+        return platform_driver_register(&sharpsl_pm_driver);
+}
+static void sharpsl_pm_exit(void)
+{
+        platform_driver_unregister(&sharpsl_pm_driver);
+}
+late_initcall(sharpsl_pm_init);
+module_exit(sharpsl_pm_exit);
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 5a45fe340a10..dda310fe71c8 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -13,19 +13,11 @@
 */
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
-#include <linux/major.h>
-#include <linux/fs.h>
-#include <linux/interrupt.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/mmc/host.h>
 #include <linux/mtd/physmap.h>
-#include <linux/pm.h>
-#include <linux/backlight.h>
-#include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/spi/spi.h>
@@ -34,31 +26,22 @@
 #include <linux/mtd/sharpsl.h>
 #include <asm/setup.h>
-#include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
+#include <asm/mach/sharpsl_param.h>
-#include <asm/mach/irq.h>
+#include <asm/hardware/scoop.h>
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
-#include <mach/udc.h>
 #include <mach/pxafb.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
-#include <mach/sharpsl.h>
-#include <asm/mach/sharpsl_param.h>
-#include <asm/hardware/scoop.h>
 #include "generic.h"
 #include "devices.h"
@@ -317,13 +300,8 @@ static struct ads7846_platform_data spitz_ads7846_info = {
        .wait_for_sync          = spitz_wait_for_hsync,
 };
-static void spitz_ads7846_cs(u32 command)
-{
-        gpio_set_value(SPITZ_GPIO_ADS7846_CS, !(command == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip spitz_ads7846_chip = {
-        .cs_control             = spitz_ads7846_cs,
+        .gpio_cs                = SPITZ_GPIO_ADS7846_CS,
 };
 static void spitz_bl_kick_battery(void)
@@ -347,22 +325,12 @@ static struct corgi_lcd_platform_data spitz_lcdcon_info = {
        .kick_battery           = spitz_bl_kick_battery,
 };
-static void spitz_lcdcon_cs(u32 command)
-{
-        gpio_set_value(SPITZ_GPIO_LCDCON_CS, !(command == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
-        .cs_control     = spitz_lcdcon_cs,
+        .gpio_cs        = SPITZ_GPIO_LCDCON_CS,
 };
-static void spitz_max1111_cs(u32 command)
-{
-        gpio_set_value(SPITZ_GPIO_MAX1111_CS, !(command == PXA2XX_CS_ASSERT));
-}
 static struct pxa2xx_spi_chip spitz_max1111_chip = {
-        .cs_control     = spitz_max1111_cs,
+        .gpio_cs        = SPITZ_GPIO_MAX1111_CS,
 };
 static struct spi_board_info spitz_spi_devices[] = {
@@ -392,30 +360,6 @@ static struct spi_board_info spitz_spi_devices[] = {
 static void __init spitz_init_spi(void)
 {
-        int err;
-        err = gpio_request(SPITZ_GPIO_ADS7846_CS, "ADS7846_CS");
-        if (err)
-                return;
-        err = gpio_request(SPITZ_GPIO_LCDCON_CS, "LCDCON_CS");
-        if (err)
-                goto err_free_1;
-        err = gpio_request(SPITZ_GPIO_MAX1111_CS, "MAX1111_CS");
-        if (err)
-                goto err_free_2;
-        err = gpio_direction_output(SPITZ_GPIO_ADS7846_CS, 1);
-        if (err)
-                goto err_free_3;
-        err = gpio_direction_output(SPITZ_GPIO_LCDCON_CS, 1);
-        if (err)
-                goto err_free_3;
-        err = gpio_direction_output(SPITZ_GPIO_MAX1111_CS, 1);
-        if (err)
-                goto err_free_3;
        if (machine_is_akita()) {
                spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
                spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
@@ -423,14 +367,6 @@ static void __init spitz_init_spi(void)
        pxa2xx_set_spi_info(2, &spitz_spi_info);
        spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
-        return;
-err_free_3:
-        gpio_free(SPITZ_GPIO_MAX1111_CS);
-err_free_2:
-        gpio_free(SPITZ_GPIO_LCDCON_CS);
-err_free_1:
-        gpio_free(SPITZ_GPIO_ADS7846_CS);
 }
 #else
 static inline void spitz_init_spi(void) {}
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 2e4490562c9e..724ffb030317 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -41,7 +41,6 @@ static void spitz_charger_init(void)
 {
        pxa_gpio_mode(SPITZ_GPIO_KEY_INT | GPIO_IN);
        pxa_gpio_mode(SPITZ_GPIO_SYNC | GPIO_IN);
-        sharpsl_pm_pxa_init();
 }
 static void spitz_measure_temp(int on)
@@ -182,7 +181,7 @@ unsigned long spitzpm_read_devdata(int type)
 struct sharpsl_charger_machinfo spitz_pm_machinfo = {
        .init             = spitz_charger_init,
-        .exit             = sharpsl_pm_pxa_remove,
+        .exit             = NULL,
        .gpio_batlock     = SPITZ_GPIO_BAT_COVER,
        .gpio_acin        = SPITZ_GPIO_AC_IN,
        .gpio_batfull     = SPITZ_GPIO_CHRG_FULL,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
new file mode 100644
index 000000000000..3b205b69f3fb
--- /dev/null
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -0,0 +1,796 @@
+/*
+ *  linux/arch/arm/mach-pxa/stargate2.c
+ *
+ *  Author:     Ed C. Epp
+ *  Created:    Nov 05, 2002
+ *  Copyright:  Intel Corp.
+ *
+ *  Modified 2009:  Jonathan Cameron <jic23@cam.ac.uk>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/bitops.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/partitions.h>
+#include <linux/i2c/pcf857x.h>
+#include <linux/i2c/at24.h>
+#include <linux/smc91x.h>
+#include <linux/gpio.h>
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
+#include <mach/pxa27x.h>
+#include <plat/i2c.h>
+#include <mach/mmc.h>
+#include <mach/udc.h>
+#include <mach/pxa2xx_spi.h>
+#include <mach/pxa27x-udc.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/da903x.h>
+#include <linux/sht15.h>
+#include "devices.h"
+#include "generic.h"
+/* Bluetooth */
+#define SG2_BT_RESET            81
+/* SD */
+#define SG2_GPIO_nSD_DETECT     90
+#define SG2_SD_POWER_ENABLE     89
+static unsigned long stargate2_pin_config[] __initdata = {
+        GPIO15_nCS_1, /* SRAM */
+        /* SMC91x */
+        GPIO80_nCS_4,
+        GPIO40_GPIO, /*cable detect?*/
+        /* Device Identification for wakeup*/
+        GPIO102_GPIO,
+        /* Button */
+        GPIO91_GPIO | WAKEUP_ON_LEVEL_HIGH,
+        /* DA9030 */
+        GPIO1_GPIO,
+        /* Compact Flash */
+        GPIO79_PSKTSEL,
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+        GPIO120_GPIO, /* Buff ctrl */
+        GPIO108_GPIO, /* Power ctrl */
+        GPIO82_GPIO, /* Reset */
+        GPIO53_GPIO, /* SG2_S0_GPIO_DETECT */
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO112_MMC_CMD,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO90_GPIO, /* nSD detect */
+        GPIO89_GPIO, /* SD_POWER_ENABLE */
+        /* Bluetooth */
+        GPIO81_GPIO, /* reset */
+        /* cc2420 802.15.4 radio */
+        GPIO22_GPIO,            /* CC_RSTN  (out)*/
+        GPIO114_GPIO,           /* CC_FIFO (in) */
+        GPIO116_GPIO,           /* CC_CCA (in) */
+        GPIO0_GPIO,             /* CC_FIFOP (in) */
+        GPIO16_GPIO,            /* CCSFD (in) */
+        GPIO39_GPIO,            /* CSn (out) */
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+        /* SSP 3 - 802.15.4 radio */
+        GPIO39_GPIO, /* chip select */
+        GPIO34_SSP3_SCLK,
+        GPIO35_SSP3_TXD,
+        GPIO41_SSP3_RXD,
+        /* SSP 2 */
+        GPIO11_SSP2_RXD,
+        GPIO38_SSP2_TXD,
+        GPIO36_SSP2_SCLK,
+        GPIO37_GPIO, /* chip select */
+        /* SSP 1 */
+        GPIO26_SSP1_RXD,
+        GPIO25_SSP1_TXD,
+        GPIO23_SSP1_SCLK,
+        GPIO24_GPIO, /* chip select */
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+        /* STUART */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+        /* Basic sensor board */
+        GPIO96_GPIO,    /* accelerometer interrupt */
+        GPIO99_GPIO,    /* ADC interrupt */
+        /* Connector pins specified as gpios */
+        GPIO94_GPIO, /* large basic connector pin 14 */
+        GPIO10_GPIO, /* large basic connector pin 23 */
+        /* SHT15 */
+        GPIO100_GPIO,
+        GPIO98_GPIO,
+};
+/**
+ * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state
+ **/
+static int stargate2_reset_bluetooth(void)
+{
+        int err;
+        err = gpio_request(SG2_BT_RESET, "SG2_BT_RESET");
+        if (err) {
+                printk(KERN_ERR "Could not get gpio for bluetooth reset \n");
+                return err;
+        }
+        gpio_direction_output(SG2_BT_RESET, 1);
+        mdelay(5);
+        /* now reset it - 5 msec minimum */
+        gpio_set_value(SG2_BT_RESET, 0);
+        mdelay(10);
+        gpio_set_value(SG2_BT_RESET, 1);
+        gpio_free(SG2_BT_RESET);
+        return 0;
+}
+static struct led_info stargate2_leds[] = {
+        {
+                .name = "sg2:red",
+                .flags = DA9030_LED_RATE_ON,
+        }, {
+                .name = "sg2:blue",
+                .flags = DA9030_LED_RATE_ON,
+        }, {
+                .name = "sg2:green",
+                .flags = DA9030_LED_RATE_ON,
+        },
+};
+static struct sht15_platform_data platform_data_sht15 = {
+        .gpio_data =  100,
+        .gpio_sck  =  98,
+};
+static struct platform_device sht15 = {
+        .name = "sht15",
+        .id = -1,
+        .dev = {
+                .platform_data = &platform_data_sht15,
+        },
+};
+static struct regulator_consumer_supply stargate2_sensor_3_con[] = {
+        {
+                .dev = &sht15.dev,
+                .supply = "vcc",
+        },
+};
+enum stargate2_ldos{
+        vcc_vref,
+        vcc_cc2420,
+        /* a mote connector? */
+        vcc_mica,
+        /* the CSR bluecore chip */
+        vcc_bt,
+        /* The two voltages available to sensor boards */
+        vcc_sensor_1_8,
+        vcc_sensor_3,
+        /* directly connected to the pxa27x */
+        vcc_sram_ext,
+        vcc_pxa_pll,
+        vcc_pxa_usim, /* Reference voltage for certain gpios */
+        vcc_pxa_mem,
+        vcc_pxa_flash,
+        vcc_pxa_core, /*Dc-Dc buck not yet supported */
+        vcc_lcd,
+        vcc_bb,
+        vcc_bbio, /*not sure!*/
+        vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/
+};
+/* The values of the various regulator constraints are obviously dependent
+ * on exactly what is wired to each ldo.  Unfortunately this information is
+ * not generally available.  More information has been requested from Xbow.
+ */
+static struct regulator_init_data stargate2_ldo_init_data[] = {
+        [vcc_bbio] = {
+                .constraints = { /* board default 1.8V */
+                        .name = "vcc_bbio",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_bb] = {
+                .constraints = { /* board default 2.8V */
+                        .name = "vcc_bb",
+                        .min_uV = 2700000,
+                        .max_uV = 3000000,
+                },
+        },
+        [vcc_pxa_flash] = {
+                .constraints = {/* default is 1.8V */
+                        .name = "vcc_pxa_flash",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_cc2420] = { /* also vcc_io */
+                .constraints = {
+                        /* board default is 2.8V */
+                        .name = "vcc_cc2420",
+                        .min_uV = 2700000,
+                        .max_uV = 3300000,
+                },
+        },
+        [vcc_vref] = { /* Reference for what? */
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_vref",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_sram_ext] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_sram_ext",
+                        .min_uV = 2800000,
+                        .max_uV = 2800000,
+                },
+        },
+        [vcc_mica] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_mica",
+                        .min_uV = 2800000,
+                        .max_uV = 2800000,
+                },
+        },
+        [vcc_bt] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_bt",
+                        .min_uV = 2800000,
+                        .max_uV = 2800000,
+                },
+        },
+        [vcc_lcd] = {
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_lcd",
+                        .min_uV = 2700000,
+                        .max_uV = 3300000,
+                },
+        },
+        [vcc_io] = { /* Same or higher than everything
+                          * bar vccbat and vccusb */
+                .constraints = { /* default 2.8V */
+                        .name = "vcc_io",
+                        .min_uV = 2692000,
+                        .max_uV = 3300000,
+                },
+        },
+        [vcc_sensor_1_8] = {
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_sensor_1_8",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+        [vcc_sensor_3] = { /* curiously default 2.8V */
+                .constraints = {
+                        .name = "vcc_sensor_3",
+                        .min_uV = 2800000,
+                        .max_uV = 3000000,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(stargate2_sensor_3_con),
+                .consumer_supplies = stargate2_sensor_3_con,
+        },
+        [vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/
+                .constraints = {
+                        .name = "vcc_pxa_pll",
+                        .min_uV = 1170000,
+                        .max_uV = 1430000,
+                },
+        },
+        [vcc_pxa_usim] = {
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_pxa_usim",
+                        .min_uV = 1710000,
+                        .max_uV = 2160000,
+                },
+        },
+        [vcc_pxa_mem] = {
+                .constraints = { /* default 1.8V */
+                        .name = "vcc_pxa_mem",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                },
+        },
+};
+static struct da903x_subdev_info stargate2_da9030_subdevs[] = {
+        {
+                .name = "da903x-led",
+                .id = DA9030_ID_LED_2,
+                .platform_data = &stargate2_leds[0],
+        }, {
+                .name = "da903x-led",
+                .id = DA9030_ID_LED_3,
+                .platform_data = &stargate2_leds[2],
+        }, {
+                .name = "da903x-led",
+                .id = DA9030_ID_LED_4,
+                .platform_data = &stargate2_leds[1],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO2,
+                .platform_data = &stargate2_ldo_init_data[vcc_bbio],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO3,
+                .platform_data = &stargate2_ldo_init_data[vcc_bb],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO4,
+                .platform_data = &stargate2_ldo_init_data[vcc_pxa_flash],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO5,
+                .platform_data = &stargate2_ldo_init_data[vcc_cc2420],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO6,
+                .platform_data = &stargate2_ldo_init_data[vcc_vref],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO7,
+                .platform_data = &stargate2_ldo_init_data[vcc_sram_ext],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO8,
+                .platform_data = &stargate2_ldo_init_data[vcc_mica],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO9,
+                .platform_data = &stargate2_ldo_init_data[vcc_bt],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO10,
+                .platform_data = &stargate2_ldo_init_data[vcc_sensor_1_8],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO11,
+                .platform_data = &stargate2_ldo_init_data[vcc_sensor_3],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO12,
+                .platform_data = &stargate2_ldo_init_data[vcc_lcd],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO15,
+                .platform_data = &stargate2_ldo_init_data[vcc_pxa_pll],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO17,
+                .platform_data = &stargate2_ldo_init_data[vcc_pxa_usim],
+        }, {
+                .name = "da903x-regulator", /*pxa vcc i/o and cc2420 vcc i/o */
+                .id = DA9030_ID_LDO18,
+                .platform_data = &stargate2_ldo_init_data[vcc_io],
+        }, {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_LDO19,
+                .platform_data = &stargate2_ldo_init_data[vcc_pxa_mem],
+        },
+};
+static struct da903x_platform_data stargate2_da9030_pdata = {
+        .num_subdevs = ARRAY_SIZE(stargate2_da9030_subdevs),
+        .subdevs = stargate2_da9030_subdevs,
+};
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .name = "smc91x-regs",
+                .start = (PXA_CS4_PHYS + 0x300),
+                .end = (PXA_CS4_PHYS + 0xfffff),
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_GPIO(40),
+                .end = IRQ_GPIO(40),
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+static struct smc91x_platdata stargate2_smc91x_info = {
+        .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT
+        | SMC91X_NOWAIT | SMC91X_USE_DMA,
+};
+static struct platform_device smc91x_device = {
+        .name = "smc91x",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(smc91x_resources),
+        .resource = smc91x_resources,
+        .dev = {
+                .platform_data = &stargate2_smc91x_info,
+        },
+};
+static struct pxamci_platform_data stargate2_mci_platform_data;
+/*
+ * The card detect interrupt isn't debounced so we delay it by 250ms
+ * to give the card a chance to fully insert / eject.
+ */
+static int stargate2_mci_init(struct device *dev,
+                              irq_handler_t stargate2_detect_int,
+                              void *data)
+{
+        int err;
+        err = gpio_request(SG2_SD_POWER_ENABLE, "SG2_sd_power_enable");
+        if (err) {
+                printk(KERN_ERR "Can't get the gpio for SD power control");
+                goto return_err;
+        }
+        gpio_direction_output(SG2_SD_POWER_ENABLE, 0);
+        err = gpio_request(SG2_GPIO_nSD_DETECT, "SG2_sd_detect");
+        if (err) {
+                printk(KERN_ERR "Can't get the sd detect gpio");
+                goto free_power_en;
+        }
+        gpio_direction_input(SG2_GPIO_nSD_DETECT);
+        /* Delay to allow for full insertion */
+        stargate2_mci_platform_data.detect_delay = msecs_to_jiffies(250);
+        err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT),
+                          stargate2_detect_int,
+                          IRQ_TYPE_EDGE_BOTH,
+                          "MMC card detect",
+                          data);
+        if (err) {
+                printk(KERN_ERR "can't request MMC card detect IRQ\n");
+                goto free_nsd_detect;
+        }
+        return 0;
+ free_nsd_detect:
+        gpio_free(SG2_GPIO_nSD_DETECT);
+ free_power_en:
+        gpio_free(SG2_SD_POWER_ENABLE);
+ return_err:
+        return err;
+}
+/**
+ * stargate2_mci_setpower() - set state of mmc power supply
+ *
+ * Very simple control. Either it is on or off and is controlled by
+ * a gpio pin */
+static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
+{
+        gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd);
+}
+static void stargate2_mci_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), data);
+        gpio_free(SG2_SD_POWER_ENABLE);
+        gpio_free(SG2_GPIO_nSD_DETECT);
+}
+static struct pxamci_platform_data stargate2_mci_platform_data = {
+        .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .init = stargate2_mci_init,
+        .setpower = stargate2_mci_setpower,
+        .exit = stargate2_mci_exit,
+};
+static struct mtd_partition stargate2flash_partitions[] = {
+        {
+                .name = "Bootloader",
+                .size = 0x00040000,
+                .offset = 0,
+                .mask_flags = 0,
+        }, {
+                .name = "Kernel",
+                .size = 0x00200000,
+                .offset = 0x00040000,
+                .mask_flags = 0
+        }, {
+                .name = "Filesystem",
+                .size = 0x01DC0000,
+                .offset = 0x00240000,
+                .mask_flags = 0
+        },
+};
+static struct resource flash_resources = {
+        .start = PXA_CS0_PHYS,
+        .end = PXA_CS0_PHYS + SZ_32M - 1,
+        .flags = IORESOURCE_MEM,
+};
+static struct flash_platform_data stargate2_flash_data = {
+        .map_name = "cfi_probe",
+        .parts = stargate2flash_partitions,
+        .nr_parts = ARRAY_SIZE(stargate2flash_partitions),
+        .name = "PXA27xOnChipROM",
+        .width = 2,
+};
+static struct platform_device stargate2_flash_device = {
+        .name = "pxa2xx-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &stargate2_flash_data,
+        },
+        .resource = &flash_resources,
+        .num_resources = 1,
+};
+/*
+ * SRAM - The Stargate 2 has 32MB of SRAM.
+ *
+ * Here it is made available as an MTD. This will then
+ * typically have a cifs filesystem created on it to provide
+ * fast temporary storage.
+ */
+static struct resource sram_resources = {
+        .start = PXA_CS1_PHYS,
+        .end = PXA_CS1_PHYS + SZ_32M-1,
+        .flags = IORESOURCE_MEM,
+};
+static struct platdata_mtd_ram stargate2_sram_pdata = {
+        .mapname = "Stargate2 SRAM",
+        .bankwidth = 2,
+};
+static struct platform_device stargate2_sram = {
+        .name = "mtd-ram",
+        .id = 0,
+        .resource = &sram_resources,
+        .num_resources = 1,
+        .dev = {
+                .platform_data = &stargate2_sram_pdata,
+        },
+};
+static struct pcf857x_platform_data platform_data_pcf857x = {
+        .gpio_base = 128,
+        .n_latch = 0,
+        .setup = NULL,
+        .teardown = NULL,
+        .context = NULL,
+};
+static struct at24_platform_data pca9500_eeprom_pdata = {
+        .byte_len = 256,
+        .page_size = 4,
+};
+static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {
+        /* Techically this a pca9500 - but it's compatible with the 8574
+         * for gpio expansion and the 24c02 for eeprom access.
+         */
+        {
+                .type = "pcf8574",
+                .addr =  0x27,
+                .platform_data = &platform_data_pcf857x,
+        }, {
+                .type = "24c02",
+                .addr = 0x57,
+                .platform_data = &pca9500_eeprom_pdata,
+        }, {
+                .type = "max1238",
+                .addr = 0x35,
+        }, { /* ITS400 Sensor board only */
+                .type = "max1363",
+                .addr = 0x34,
+                /* Through a nand gate - Also beware, on V2 sensor board the
+                 * pull up resistors are missing.
+                 */
+                .irq = IRQ_GPIO(99),
+        }, { /* ITS400 Sensor board only */
+                .type = "tsl2561",
+                .addr = 0x49,
+                /* Through a nand gate - Also beware, on V2 sensor board the
+                 * pull up resistors are missing.
+                 */
+                .irq = IRQ_GPIO(99),
+        }, { /* ITS400 Sensor board only */
+                .type = "tmp175",
+                .addr = 0x4A,
+                .irq = IRQ_GPIO(96),
+        },
+};
+static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = {
+        {
+                .type = "da9030",
+                .addr = 0x49,
+                .platform_data = &stargate2_da9030_pdata,
+                .irq = gpio_to_irq(1),
+        },
+};
+static struct pxa2xx_spi_master pxa_ssp_master_0_info = {
+        .num_chipselect = 1,
+};
+static struct pxa2xx_spi_master pxa_ssp_master_1_info = {
+        .num_chipselect = 1,
+};
+static struct pxa2xx_spi_master pxa_ssp_master_2_info = {
+        .num_chipselect = 1,
+};
+/* An upcoming kernel change will scrap SFRM usage so these
+ * drivers have been moved to use gpio's via cs_control */
+static struct pxa2xx_spi_chip staccel_chip_info = {
+        .tx_threshold = 8,
+        .rx_threshold = 8,
+        .dma_burst_size = 8,
+        .timeout = 235,
+        .gpio_cs = 24,
+};
+static struct pxa2xx_spi_chip cc2420_info = {
+        .tx_threshold = 8,
+        .rx_threshold = 8,
+        .dma_burst_size = 8,
+        .timeout = 235,
+        .gpio_cs = 39,
+};
+static struct spi_board_info spi_board_info[] __initdata = {
+        {
+                .modalias = "lis3l02dq",
+                .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */
+                .bus_num = 1,
+                .chip_select = 0,
+                .controller_data = &staccel_chip_info,
+                .irq = IRQ_GPIO(96),
+        }, {
+                .modalias = "cc2420",
+                .max_speed_hz = 6500000,
+                .bus_num = 3,
+                .chip_select = 0,
+                .controller_data = &cc2420_info,
+        },
+};
+static void sg2_udc_command(int cmd)
+{
+        switch (cmd) {
+        case PXA2XX_UDC_CMD_CONNECT:
+                UP2OCR |=  UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE;
+                break;
+        case PXA2XX_UDC_CMD_DISCONNECT:
+                UP2OCR &= ~(UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE);
+                break;
+        }
+}
+/* Board doesn't support cable detection - so always lie and say
+ * something is there.
+ */
+static int sg2_udc_detect(void)
+{
+        return 1;
+}
+static struct pxa2xx_udc_mach_info stargate2_udc_info __initdata = {
+        .udc_is_connected       = sg2_udc_detect,
+        .udc_command            = sg2_udc_command,
+};
+static struct platform_device *stargate2_devices[] = {
+        &stargate2_flash_device,
+        &stargate2_sram,
+        &smc91x_device,
+        &sht15,
+};
+static struct i2c_pxa_platform_data i2c_pwr_pdata = {
+        .fast_mode = 1,
+};
+static struct i2c_pxa_platform_data i2c_pdata = {
+        .fast_mode = 1,
+};
+static void __init stargate2_init(void)
+{
+        /* This is probably a board specific hack as this must be set
+           prior to connecting the MFP stuff up. */
+        MECR &= ~MECR_NOS;
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config));
+        /* spi chip selects */
+        gpio_direction_output(37, 0);
+        gpio_direction_output(24, 0);
+        gpio_direction_output(39, 0);
+        platform_add_devices(ARRAY_AND_SIZE(stargate2_devices));
+        pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
+        pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info);
+        pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info);
+        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+        i2c_register_board_info(0, ARRAY_AND_SIZE(stargate2_i2c_board_info));
+        i2c_register_board_info(1,
+                                ARRAY_AND_SIZE(stargate2_pwr_i2c_board_info));
+        pxa27x_set_i2c_power_info(&i2c_pwr_pdata);
+        pxa_set_i2c_info(&i2c_pdata);
+        pxa_set_mci_info(&stargate2_mci_platform_data);
+        pxa_set_udc_info(&stargate2_udc_info);
+        stargate2_reset_bluetooth();
+}
+MACHINE_START(STARGATE2, "Stargate 2")
+        .phys_io = 0x40000000,
+        .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io = pxa_map_io,
+        .init_irq = pxa27x_init_irq,
+        .timer = &pxa_timer,
+        .init_machine = stargate2_init,
+        .boot_params = 0xA0000100,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c
index fb0294bd4310..c31e601eb49c 100644
--- a/arch/arm/mach-pxa/tosa-bt.c
+++ b/arch/arm/mach-pxa/tosa-bt.c
@@ -35,21 +35,25 @@ static void tosa_bt_off(struct tosa_bt_data *data)
        gpio_set_value(data->gpio_reset, 0);
 }
-static int tosa_bt_toggle_radio(void *data, enum rfkill_state state)
+static int tosa_bt_set_block(void *data, bool blocked)
 {
-        pr_info("BT_RADIO going: %s\n",
+        pr_info("BT_RADIO going: %s\n", blocked ? "off" : "on");
-                        state == RFKILL_STATE_ON ? "on" : "off");
-        if (state == RFKILL_STATE_ON) {
+        if (!blocked) {
                pr_info("TOSA_BT: going ON\n");
                tosa_bt_on(data);
        } else {
                pr_info("TOSA_BT: going OFF\n");
                tosa_bt_off(data);
        }
        return 0;
 }
+static const struct rfkill_ops tosa_bt_rfkill_ops = {
+        .set_block = tosa_bt_set_block,
+};
 static int tosa_bt_probe(struct platform_device *dev)
 {
        int rc;
@@ -70,18 +74,14 @@ static int tosa_bt_probe(struct platform_device *dev)
        if (rc)
                goto err_pwr_dir;
-        rfk = rfkill_allocate(&dev->dev, RFKILL_TYPE_BLUETOOTH);
+        rfk = rfkill_alloc("tosa-bt", &dev->dev, RFKILL_TYPE_BLUETOOTH,
+                           &tosa_bt_rfkill_ops, data);
        if (!rfk) {
                rc = -ENOMEM;
                goto err_rfk_alloc;
        }
-        rfk->name = "tosa-bt";
+        rfkill_set_led_trigger_name(rfk, "tosa-bt");
-        rfk->toggle_radio = tosa_bt_toggle_radio;
-        rfk->data = data;
-#ifdef CONFIG_RFKILL_LEDS
-        rfk->led_trigger.name = "tosa-bt";
-#endif
        rc = rfkill_register(rfk);
        if (rc)
@@ -92,9 +92,7 @@ static int tosa_bt_probe(struct platform_device *dev)
        return 0;
 err_rfkill:
-        if (rfk)
+        rfkill_destroy(rfk);
-                rfkill_free(rfk);
-        rfk = NULL;
 err_rfk_alloc:
        tosa_bt_off(data);
 err_pwr_dir:
@@ -113,8 +111,10 @@ static int __devexit tosa_bt_remove(struct platform_device *dev)
        platform_set_drvdata(dev, NULL);
-        if (rfk)
+        if (rfk) {
                rfkill_unregister(rfk);
+                rfkill_destroy(rfk);
+        }
        rfk = NULL;
        tosa_bt_off(data);
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index a0bd46ef5d30..117ad5920e53 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -31,7 +31,6 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/pda_power.h>
-#include <linux/rfkill.h>
 #include <linux/spi/spi.h>
 #include <asm/setup.h>
@@ -40,7 +39,7 @@
 #include <mach/pxa25x.h>
 #include <mach/reset.h>
 #include <mach/irda.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/tosa_bt.h>
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index f79c9cb70ae4..825f540176d2 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -47,7 +47,7 @@
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index dd031cc41847..d33c232b686c 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -45,7 +45,7 @@
 #include <mach/pxa25x.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/regs-uart.h>
 #include <mach/viper.h>
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index c256c57642c0..cefd1c0a854a 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -21,7 +21,7 @@
 #include <linux/gpio.h>
 #include <mach/pxa300.h>
-#include <mach/i2c.h>
+#include <plat/i2c.h>
 #include <mach/zylonite.h>
 #include "generic.h"
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index b6ec10627776..d4cfa2145386 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -24,7 +24,6 @@ config REALVIEW_EB_ARM11MP
 config REALVIEW_EB_ARM11MP_REVB
        bool "Support ARM11MPCore RevB tile"
        depends on REALVIEW_EB_ARM11MP
-        default n
        help
          Enable support for the ARM11MPCore RevB tile on the Realview
          platform. Since there are device address differences, a
@@ -48,6 +47,15 @@ config MACH_REALVIEW_PB1176
        help
          Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
+config REALVIEW_PB1176_SECURE_FLASH
+        bool "Allow access to the secure flash memory block"
+        depends on MACH_REALVIEW_PB1176
+        default n
+        help
+          Select this option if Linux will only run in secure mode on the
+          RealView PB1176 platform and access to the secure flash memory
+          block (64MB @ 0x3c000000) is required.
 config MACH_REALVIEW_PBA8
        bool "Support RealView/PB-A8 platform"
        select CPU_V7
@@ -58,6 +66,13 @@ config MACH_REALVIEW_PBA8
          PB-A8 is a platform with an on-board Cortex-A8 and has support for
          PCI-E and Compact Flash.
+config MACH_REALVIEW_PBX
+        bool "Support RealView/PBX platform"
+        select ARM_GIC
+        select HAVE_PATA_PLATFORM
+        help
+          Include support for the ARM(R) RealView PBX platform.
 config REALVIEW_HIGH_PHYS_OFFSET
        bool "High physical base address for the RealView platform"
        depends on !MACH_REALVIEW_PB1176
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 7bea8ffc4b59..e704edb733c0 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -7,5 +7,7 @@ obj-$(CONFIG_MACH_REALVIEW_EB)		+= realview_eb.o
 obj-$(CONFIG_MACH_REALVIEW_PB11MP)      += realview_pb11mp.o
 obj-$(CONFIG_MACH_REALVIEW_PB1176)      += realview_pb1176.o
 obj-$(CONFIG_MACH_REALVIEW_PBA8)        += realview_pba8.o
-obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o localtimer.o
+obj-$(CONFIG_MACH_REALVIEW_PBX)         += realview_pbx.o
+obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 076acbc50706..9ea9c05093cd 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -48,6 +48,9 @@
 #include <asm/hardware/gic.h>
+#include <mach/platform.h>
+#include <mach/irqs.h>
 #include "core.h"
 #include "clock.h"
@@ -578,21 +581,22 @@ void realview_leds_event(led_event_t ledevt)
 {
        unsigned long flags;
        u32 val;
+        u32 led = 1 << smp_processor_id();
        local_irq_save(flags);
        val = readl(VA_LEDS_BASE);
        switch (ledevt) {
        case led_idle_start:
-                val = val & ~REALVIEW_SYS_LED0;
+                val = val & ~led;
                break;
        case led_idle_end:
-                val = val | REALVIEW_SYS_LED0;
+                val = val | led;
                break;
        case led_timer:
-                val = val ^ REALVIEW_SYS_LED1;
+                val = val ^ REALVIEW_SYS_LED7;
                break;
        case led_halted:
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 21c08637683b..59a337ba4be7 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -51,9 +51,6 @@ extern struct mmc_platform_data realview_mmc0_plat_data;
 extern struct mmc_platform_data realview_mmc1_plat_data;
 extern struct clcd_board clcd_plat_data;
 extern void __iomem *gic_cpu_base_addr;
-#ifdef CONFIG_LOCAL_TIMERS
-extern void __iomem *twd_base;
-#endif
 extern void __iomem *timer0_va_base;
 extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h
index 268d7701fa9b..794a8d91a6a6 100644
--- a/arch/arm/mach-realview/include/mach/board-eb.h
+++ b/arch/arm/mach-realview/include/mach/board-eb.h
@@ -62,111 +62,6 @@
 #define REALVIEW_EB11MP_SYS_PLD_CTRL1   0x74            /* Register offset for MPCore sysctl */
 #endif
-#define IRQ_EB_GIC_START        32
-/*
- * RealView EB interrupt sources
- */
-#define IRQ_EB_WDOG             (IRQ_EB_GIC_START + 0)          /* Watchdog timer */
-#define IRQ_EB_SOFT             (IRQ_EB_GIC_START + 1)          /* Software interrupt */
-#define IRQ_EB_COMMRx           (IRQ_EB_GIC_START + 2)          /* Debug Comm Rx interrupt */
-#define IRQ_EB_COMMTx           (IRQ_EB_GIC_START + 3)          /* Debug Comm Tx interrupt */
-#define IRQ_EB_TIMER0_1         (IRQ_EB_GIC_START + 4)          /* Timer 0 and 1 */
-#define IRQ_EB_TIMER2_3         (IRQ_EB_GIC_START + 5)          /* Timer 2 and 3 */
-#define IRQ_EB_GPIO0            (IRQ_EB_GIC_START + 6)          /* GPIO 0 */
-#define IRQ_EB_GPIO1            (IRQ_EB_GIC_START + 7)          /* GPIO 1 */
-#define IRQ_EB_GPIO2            (IRQ_EB_GIC_START + 8)          /* GPIO 2 */
-                                                                /* 9 reserved */
-#define IRQ_EB_RTC              (IRQ_EB_GIC_START + 10)         /* Real Time Clock */
-#define IRQ_EB_SSP              (IRQ_EB_GIC_START + 11)         /* Synchronous Serial Port */
-#define IRQ_EB_UART0            (IRQ_EB_GIC_START + 12)         /* UART 0 on development chip */
-#define IRQ_EB_UART1            (IRQ_EB_GIC_START + 13)         /* UART 1 on development chip */
-#define IRQ_EB_UART2            (IRQ_EB_GIC_START + 14)         /* UART 2 on development chip */
-#define IRQ_EB_UART3            (IRQ_EB_GIC_START + 15)         /* UART 3 on development chip */
-#define IRQ_EB_SCI              (IRQ_EB_GIC_START + 16)         /* Smart Card Interface */
-#define IRQ_EB_MMCI0A           (IRQ_EB_GIC_START + 17)         /* Multimedia Card 0A */
-#define IRQ_EB_MMCI0B           (IRQ_EB_GIC_START + 18)         /* Multimedia Card 0B */
-#define IRQ_EB_AACI             (IRQ_EB_GIC_START + 19)         /* Audio Codec */
-#define IRQ_EB_KMI0             (IRQ_EB_GIC_START + 20)         /* Keyboard/Mouse port 0 */
-#define IRQ_EB_KMI1             (IRQ_EB_GIC_START + 21)         /* Keyboard/Mouse port 1 */
-#define IRQ_EB_CHARLCD          (IRQ_EB_GIC_START + 22)         /* Character LCD */
-#define IRQ_EB_CLCD             (IRQ_EB_GIC_START + 23)         /* CLCD controller */
-#define IRQ_EB_DMA              (IRQ_EB_GIC_START + 24)         /* DMA controller */
-#define IRQ_EB_PWRFAIL          (IRQ_EB_GIC_START + 25)         /* Power failure */
-#define IRQ_EB_PISMO            (IRQ_EB_GIC_START + 26)         /* PISMO interface */
-#define IRQ_EB_DoC              (IRQ_EB_GIC_START + 27)         /* Disk on Chip memory controller */
-#define IRQ_EB_ETH              (IRQ_EB_GIC_START + 28)         /* Ethernet controller */
-#define IRQ_EB_USB              (IRQ_EB_GIC_START + 29)         /* USB controller */
-#define IRQ_EB_TSPEN            (IRQ_EB_GIC_START + 30)         /* Touchscreen pen */
-#define IRQ_EB_TSKPAD           (IRQ_EB_GIC_START + 31)         /* Touchscreen keypad */
-/*
- * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
- */
-#define IRQ_EB11MP_AACI         (IRQ_EB_GIC_START + 0)
-#define IRQ_EB11MP_TIMER0_1     (IRQ_EB_GIC_START + 1)
-#define IRQ_EB11MP_TIMER2_3     (IRQ_EB_GIC_START + 2)
-#define IRQ_EB11MP_USB          (IRQ_EB_GIC_START + 3)
-#define IRQ_EB11MP_UART0        (IRQ_EB_GIC_START + 4)
-#define IRQ_EB11MP_UART1        (IRQ_EB_GIC_START + 5)
-#define IRQ_EB11MP_RTC          (IRQ_EB_GIC_START + 6)
-#define IRQ_EB11MP_KMI0         (IRQ_EB_GIC_START + 7)
-#define IRQ_EB11MP_KMI1         (IRQ_EB_GIC_START + 8)
-#define IRQ_EB11MP_ETH          (IRQ_EB_GIC_START + 9)
-#define IRQ_EB11MP_EB_IRQ1      (IRQ_EB_GIC_START + 10)         /* main GIC */
-#define IRQ_EB11MP_EB_IRQ2      (IRQ_EB_GIC_START + 11)         /* tile GIC */
-#define IRQ_EB11MP_EB_FIQ1      (IRQ_EB_GIC_START + 12)         /* main GIC */
-#define IRQ_EB11MP_EB_FIQ2      (IRQ_EB_GIC_START + 13)         /* tile GIC */
-#define IRQ_EB11MP_MMCI0A       (IRQ_EB_GIC_START + 14)
-#define IRQ_EB11MP_MMCI0B       (IRQ_EB_GIC_START + 15)
-#define IRQ_EB11MP_PMU_CPU0     (IRQ_EB_GIC_START + 17)
-#define IRQ_EB11MP_PMU_CPU1     (IRQ_EB_GIC_START + 18)
-#define IRQ_EB11MP_PMU_CPU2     (IRQ_EB_GIC_START + 19)
-#define IRQ_EB11MP_PMU_CPU3     (IRQ_EB_GIC_START + 20)
-#define IRQ_EB11MP_PMU_SCU0     (IRQ_EB_GIC_START + 21)
-#define IRQ_EB11MP_PMU_SCU1     (IRQ_EB_GIC_START + 22)
-#define IRQ_EB11MP_PMU_SCU2     (IRQ_EB_GIC_START + 23)
-#define IRQ_EB11MP_PMU_SCU3     (IRQ_EB_GIC_START + 24)
-#define IRQ_EB11MP_PMU_SCU4     (IRQ_EB_GIC_START + 25)
-#define IRQ_EB11MP_PMU_SCU5     (IRQ_EB_GIC_START + 26)
-#define IRQ_EB11MP_PMU_SCU6     (IRQ_EB_GIC_START + 27)
-#define IRQ_EB11MP_PMU_SCU7     (IRQ_EB_GIC_START + 28)
-#define IRQ_EB11MP_L220_EVENT   (IRQ_EB_GIC_START + 29)
-#define IRQ_EB11MP_L220_SLAVE   (IRQ_EB_GIC_START + 30)
-#define IRQ_EB11MP_L220_DECODE  (IRQ_EB_GIC_START + 31)
-#define IRQ_EB11MP_UART2        -1
-#define IRQ_EB11MP_UART3        -1
-#define IRQ_EB11MP_CLCD         -1
-#define IRQ_EB11MP_DMA          -1
-#define IRQ_EB11MP_WDOG         -1
-#define IRQ_EB11MP_GPIO0        -1
-#define IRQ_EB11MP_GPIO1        -1
-#define IRQ_EB11MP_GPIO2        -1
-#define IRQ_EB11MP_SCI          -1
-#define IRQ_EB11MP_SSP          -1
-#define NR_GIC_EB11MP           2
-/*
- * Only define NR_IRQS if less than NR_IRQS_EB
- */
-#define NR_IRQS_EB              (IRQ_EB_GIC_START + 96)
-#if defined(CONFIG_MACH_REALVIEW_EB) \
-        && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
-#undef NR_IRQS
-#define NR_IRQS                 NR_IRQS_EB
-#endif
-#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \
-        && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
-#undef MAX_GIC_NR
-#define MAX_GIC_NR              NR_GIC_EB11MP
-#endif
 /*
 * Core tile identification (REALVIEW_SYS_PROCID)
 */
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 858eea7b1adc..98f8e7eeacc2 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -32,6 +32,8 @@
 #define REALVIEW_PB1176_SDRAM67_BASE            0x70000000 /* SDRAM banks 6 and 7 */
 #define REALVIEW_PB1176_FLASH_BASE              0x30000000
 #define REALVIEW_PB1176_FLASH_SIZE              SZ_64M
+#define REALVIEW_PB1176_SEC_FLASH_BASE          0x3C000000 /* Secure flash */
+#define REALVIEW_PB1176_SEC_FLASH_SIZE          SZ_64M
 #define REALVIEW_PB1176_TIMER0_1_BASE           0x10104000 /* Timer 0 and 1 */
 #define REALVIEW_PB1176_TIMER2_3_BASE           0x10105000 /* Timer 2 and 3 */
@@ -71,82 +73,4 @@
 #define REALVIEW_PB1176_GIC_DIST_BASE           0x10041000 /* GIC distributor, on FPGA */
 #define REALVIEW_PB1176_L220_BASE               0x10110000 /* L220 registers */
-/*
- * Irqs
- */
-#define IRQ_DC1176_GIC_START                    32
-#define IRQ_PB1176_GIC_START                    64
-/*
- * ARM1176 DevChip interrupt sources (primary GIC)
- */
-#define IRQ_DC1176_WATCHDOG     (IRQ_DC1176_GIC_START + 0)      /* Watchdog timer */
-#define IRQ_DC1176_SOFTINT      (IRQ_DC1176_GIC_START + 1)      /* Software interrupt */
-#define IRQ_DC1176_COMMRx       (IRQ_DC1176_GIC_START + 2)      /* Debug Comm Rx interrupt */
-#define IRQ_DC1176_COMMTx       (IRQ_DC1176_GIC_START + 3)      /* Debug Comm Tx interrupt */
-#define IRQ_DC1176_TIMER0       (IRQ_DC1176_GIC_START + 8)      /* Timer 0 */
-#define IRQ_DC1176_TIMER1       (IRQ_DC1176_GIC_START + 9)      /* Timer 1 */
-#define IRQ_DC1176_TIMER2       (IRQ_DC1176_GIC_START + 10)     /* Timer 2 */
-#define IRQ_DC1176_APC          (IRQ_DC1176_GIC_START + 11)
-#define IRQ_DC1176_IEC          (IRQ_DC1176_GIC_START + 12)
-#define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
-#define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
-#define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
-#define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
-#define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
-#define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
-#define IRQ_DC1176_UART3        (IRQ_DC1176_GIC_START + 21)     /* UART 3 on development chip */
-#define IRQ_DC1176_PB_IRQ2      (IRQ_DC1176_GIC_START + 30)     /* tile GIC */
-#define IRQ_DC1176_PB_IRQ1      (IRQ_DC1176_GIC_START + 31)     /* main GIC */
-/*
- * RealView PB1176 interrupt sources (secondary GIC)
- */
-#define IRQ_PB1176_MMCI0A       (IRQ_PB1176_GIC_START + 1)      /* Multimedia Card 0A */
-#define IRQ_PB1176_MMCI0B       (IRQ_PB1176_GIC_START + 2)      /* Multimedia Card 0A */
-#define IRQ_PB1176_KMI0         (IRQ_PB1176_GIC_START + 3)      /* Keyboard/Mouse port 0 */
-#define IRQ_PB1176_KMI1         (IRQ_PB1176_GIC_START + 4)      /* Keyboard/Mouse port 1 */
-#define IRQ_PB1176_SCI          (IRQ_PB1176_GIC_START + 5)
-#define IRQ_PB1176_UART4        (IRQ_PB1176_GIC_START + 6)      /* UART 4 on baseboard */
-#define IRQ_PB1176_CHARLCD      (IRQ_PB1176_GIC_START + 7)      /* Character LCD */
-#define IRQ_PB1176_GPIO1        (IRQ_PB1176_GIC_START + 8)
-#define IRQ_PB1176_GPIO2        (IRQ_PB1176_GIC_START + 9)
-#define IRQ_PB1176_ETH          (IRQ_PB1176_GIC_START + 10)     /* Ethernet controller */
-#define IRQ_PB1176_USB          (IRQ_PB1176_GIC_START + 11)     /* USB controller */
-#define IRQ_PB1176_PISMO        (IRQ_PB1176_GIC_START + 16)
-#define IRQ_PB1176_AACI         (IRQ_PB1176_GIC_START + 19)     /* Audio Codec */
-#define IRQ_PB1176_TIMER0_1     (IRQ_PB1176_GIC_START + 22)
-#define IRQ_PB1176_TIMER2_3     (IRQ_PB1176_GIC_START + 23)
-#define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
-#define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
-#define IRQ_PB1176_GPIO0        -1
-#define IRQ_PB1176_SSP          -1
-#define IRQ_PB1176_SCTL         -1
-#define NR_GIC_PB1176           2
-/*
- * Only define NR_IRQS if less than NR_IRQS_PB1176
- */
-#define NR_IRQS_PB1176          (IRQ_DC1176_GIC_START + 96)
-#if defined(CONFIG_MACH_REALVIEW_PB1176)
-#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
-#undef NR_IRQS
-#define NR_IRQS                 NR_IRQS_PB1176
-#endif
-#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
-#undef MAX_GIC_NR
-#define MAX_GIC_NR              NR_GIC_PB1176
-#endif
-#endif  /* CONFIG_MACH_REALVIEW_PB1176 */
 #endif  /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h
index 53ea0e7a1267..f0d68e0fea01 100644
--- a/arch/arm/mach-realview/include/mach/board-pb11mp.h
+++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h
@@ -81,105 +81,4 @@
 #define REALVIEW_TC11MP_GIC_DIST_BASE           0x1F001000      /* Test chip interrupt controller distributor */
 #define REALVIEW_TC11MP_L220_BASE               0x1F002000      /* L220 registers */
-/*
- * Irqs
- */
-#define IRQ_TC11MP_GIC_START                    32
-#define IRQ_PB11MP_GIC_START                    64
-/*
- * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
- */
-#define IRQ_TC11MP_AACI         (IRQ_TC11MP_GIC_START + 0)
-#define IRQ_TC11MP_TIMER0_1     (IRQ_TC11MP_GIC_START + 1)
-#define IRQ_TC11MP_TIMER2_3     (IRQ_TC11MP_GIC_START + 2)
-#define IRQ_TC11MP_USB          (IRQ_TC11MP_GIC_START + 3)
-#define IRQ_TC11MP_UART0        (IRQ_TC11MP_GIC_START + 4)
-#define IRQ_TC11MP_UART1        (IRQ_TC11MP_GIC_START + 5)
-#define IRQ_TC11MP_RTC          (IRQ_TC11MP_GIC_START + 6)
-#define IRQ_TC11MP_KMI0         (IRQ_TC11MP_GIC_START + 7)
-#define IRQ_TC11MP_KMI1         (IRQ_TC11MP_GIC_START + 8)
-#define IRQ_TC11MP_ETH          (IRQ_TC11MP_GIC_START + 9)
-#define IRQ_TC11MP_PB_IRQ1      (IRQ_TC11MP_GIC_START + 10)             /* main GIC */
-#define IRQ_TC11MP_PB_IRQ2      (IRQ_TC11MP_GIC_START + 11)             /* tile GIC */
-#define IRQ_TC11MP_PB_FIQ1      (IRQ_TC11MP_GIC_START + 12)             /* main GIC */
-#define IRQ_TC11MP_PB_FIQ2      (IRQ_TC11MP_GIC_START + 13)             /* tile GIC */
-#define IRQ_TC11MP_MMCI0A       (IRQ_TC11MP_GIC_START + 14)
-#define IRQ_TC11MP_MMCI0B       (IRQ_TC11MP_GIC_START + 15)
-#define IRQ_TC11MP_PMU_CPU0     (IRQ_TC11MP_GIC_START + 17)
-#define IRQ_TC11MP_PMU_CPU1     (IRQ_TC11MP_GIC_START + 18)
-#define IRQ_TC11MP_PMU_CPU2     (IRQ_TC11MP_GIC_START + 19)
-#define IRQ_TC11MP_PMU_CPU3     (IRQ_TC11MP_GIC_START + 20)
-#define IRQ_TC11MP_PMU_SCU0     (IRQ_TC11MP_GIC_START + 21)
-#define IRQ_TC11MP_PMU_SCU1     (IRQ_TC11MP_GIC_START + 22)
-#define IRQ_TC11MP_PMU_SCU2     (IRQ_TC11MP_GIC_START + 23)
-#define IRQ_TC11MP_PMU_SCU3     (IRQ_TC11MP_GIC_START + 24)
-#define IRQ_TC11MP_PMU_SCU4     (IRQ_TC11MP_GIC_START + 25)
-#define IRQ_TC11MP_PMU_SCU5     (IRQ_TC11MP_GIC_START + 26)
-#define IRQ_TC11MP_PMU_SCU6     (IRQ_TC11MP_GIC_START + 27)
-#define IRQ_TC11MP_PMU_SCU7     (IRQ_TC11MP_GIC_START + 28)
-#define IRQ_TC11MP_L220_EVENT   (IRQ_TC11MP_GIC_START + 29)
-#define IRQ_TC11MP_L220_SLAVE   (IRQ_TC11MP_GIC_START + 30)
-#define IRQ_TC11MP_L220_DECODE  (IRQ_TC11MP_GIC_START + 31)
-/*
- * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
- */
-#define IRQ_PB11MP_WATCHDOG     (IRQ_PB11MP_GIC_START + 0)      /* Watchdog timer */
-#define IRQ_PB11MP_SOFT         (IRQ_PB11MP_GIC_START + 1)      /* Software interrupt */
-#define IRQ_PB11MP_COMMRx       (IRQ_PB11MP_GIC_START + 2)      /* Debug Comm Rx interrupt */
-#define IRQ_PB11MP_COMMTx       (IRQ_PB11MP_GIC_START + 3)      /* Debug Comm Tx interrupt */
-#define IRQ_PB11MP_GPIO0        (IRQ_PB11MP_GIC_START + 6)      /* GPIO 0 */
-#define IRQ_PB11MP_GPIO1        (IRQ_PB11MP_GIC_START + 7)      /* GPIO 1 */
-#define IRQ_PB11MP_GPIO2        (IRQ_PB11MP_GIC_START + 8)      /* GPIO 2 */
-                                                                /* 9 reserved */
-#define IRQ_PB11MP_RTC_GIC1     (IRQ_PB11MP_GIC_START + 10)     /* Real Time Clock */
-#define IRQ_PB11MP_SSP          (IRQ_PB11MP_GIC_START + 11)     /* Synchronous Serial Port */
-#define IRQ_PB11MP_UART0_GIC1   (IRQ_PB11MP_GIC_START + 12)     /* UART 0 on development chip */
-#define IRQ_PB11MP_UART1_GIC1   (IRQ_PB11MP_GIC_START + 13)     /* UART 1 on development chip */
-#define IRQ_PB11MP_UART2        (IRQ_PB11MP_GIC_START + 14)     /* UART 2 on development chip */
-#define IRQ_PB11MP_UART3        (IRQ_PB11MP_GIC_START + 15)     /* UART 3 on development chip */
-#define IRQ_PB11MP_SCI          (IRQ_PB11MP_GIC_START + 16)     /* Smart Card Interface */
-#define IRQ_PB11MP_MMCI0A_GIC1  (IRQ_PB11MP_GIC_START + 17)     /* Multimedia Card 0A */
-#define IRQ_PB11MP_MMCI0B_GIC1  (IRQ_PB11MP_GIC_START + 18)     /* Multimedia Card 0B */
-#define IRQ_PB11MP_AACI_GIC1    (IRQ_PB11MP_GIC_START + 19)     /* Audio Codec */
-#define IRQ_PB11MP_KMI0_GIC1    (IRQ_PB11MP_GIC_START + 20)     /* Keyboard/Mouse port 0 */
-#define IRQ_PB11MP_KMI1_GIC1    (IRQ_PB11MP_GIC_START + 21)     /* Keyboard/Mouse port 1 */
-#define IRQ_PB11MP_CHARLCD      (IRQ_PB11MP_GIC_START + 22)     /* Character LCD */
-#define IRQ_PB11MP_CLCD         (IRQ_PB11MP_GIC_START + 23)     /* CLCD controller */
-#define IRQ_PB11MP_DMAC         (IRQ_PB11MP_GIC_START + 24)     /* DMA controller */
-#define IRQ_PB11MP_PWRFAIL      (IRQ_PB11MP_GIC_START + 25)     /* Power failure */
-#define IRQ_PB11MP_PISMO        (IRQ_PB11MP_GIC_START + 26)     /* PISMO interface */
-#define IRQ_PB11MP_DoC          (IRQ_PB11MP_GIC_START + 27)     /* Disk on Chip memory controller */
-#define IRQ_PB11MP_ETH_GIC1     (IRQ_PB11MP_GIC_START + 28)     /* Ethernet controller */
-#define IRQ_PB11MP_USB_GIC1     (IRQ_PB11MP_GIC_START + 29)     /* USB controller */
-#define IRQ_PB11MP_TSPEN        (IRQ_PB11MP_GIC_START + 30)     /* Touchscreen pen */
-#define IRQ_PB11MP_TSKPAD       (IRQ_PB11MP_GIC_START + 31)     /* Touchscreen keypad */
-#define IRQ_PB11MP_SMC          -1
-#define IRQ_PB11MP_SCTL         -1
-#define NR_GIC_PB11MP           2
-/*
- * Only define NR_IRQS if less than NR_IRQS_PB11MP
- */
-#define NR_IRQS_PB11MP          (IRQ_TC11MP_GIC_START + 96)
-#if defined(CONFIG_MACH_REALVIEW_PB11MP)
-#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
-#undef NR_IRQS
-#define NR_IRQS                 NR_IRQS_PB11MP
-#endif
-#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
-#undef MAX_GIC_NR
-#define MAX_GIC_NR              NR_GIC_PB11MP
-#endif
-#endif  /* CONFIG_MACH_REALVIEW_PB11MP */
 #endif  /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h
index 307f97b16e5b..4dfc67a4f45f 100644
--- a/arch/arm/mach-realview/include/mach/board-pba8.h
+++ b/arch/arm/mach-realview/include/mach/board-pba8.h
@@ -70,81 +70,4 @@
 #define REALVIEW_PBA8_PCI_IO_SIZE               0x1000          /* 4 Kb */
 #define REALVIEW_PBA8_PCI_MEM_SIZE              0x20000000      /* 512 MB */
-/*
- * Irqs
- */
-#define IRQ_PBA8_GIC_START                      32
-/* L220
-#define IRQ_PBA8_L220_EVENT     (IRQ_PBA8_GIC_START + 29)
-#define IRQ_PBA8_L220_SLAVE     (IRQ_PBA8_GIC_START + 30)
-#define IRQ_PBA8_L220_DECODE    (IRQ_PBA8_GIC_START + 31)
-*/
-/*
- * PB-A8 on-board gic irq sources
- */
-#define IRQ_PBA8_WATCHDOG       (IRQ_PBA8_GIC_START + 0)        /* Watchdog timer */
-#define IRQ_PBA8_SOFT           (IRQ_PBA8_GIC_START + 1)        /* Software interrupt */
-#define IRQ_PBA8_COMMRx         (IRQ_PBA8_GIC_START + 2)        /* Debug Comm Rx interrupt */
-#define IRQ_PBA8_COMMTx         (IRQ_PBA8_GIC_START + 3)        /* Debug Comm Tx interrupt */
-#define IRQ_PBA8_TIMER0_1       (IRQ_PBA8_GIC_START + 4)        /* Timer 0/1 (default timer) */
-#define IRQ_PBA8_TIMER2_3       (IRQ_PBA8_GIC_START + 5)        /* Timer 2/3 */
-#define IRQ_PBA8_GPIO0          (IRQ_PBA8_GIC_START + 6)        /* GPIO 0 */
-#define IRQ_PBA8_GPIO1          (IRQ_PBA8_GIC_START + 7)        /* GPIO 1 */
-#define IRQ_PBA8_GPIO2          (IRQ_PBA8_GIC_START + 8)        /* GPIO 2 */
-                                                                /* 9 reserved */
-#define IRQ_PBA8_RTC            (IRQ_PBA8_GIC_START + 10)       /* Real Time Clock */
-#define IRQ_PBA8_SSP            (IRQ_PBA8_GIC_START + 11)       /* Synchronous Serial Port */
-#define IRQ_PBA8_UART0          (IRQ_PBA8_GIC_START + 12)       /* UART 0 on development chip */
-#define IRQ_PBA8_UART1          (IRQ_PBA8_GIC_START + 13)       /* UART 1 on development chip */
-#define IRQ_PBA8_UART2          (IRQ_PBA8_GIC_START + 14)       /* UART 2 on development chip */
-#define IRQ_PBA8_UART3          (IRQ_PBA8_GIC_START + 15)       /* UART 3 on development chip */
-#define IRQ_PBA8_SCI            (IRQ_PBA8_GIC_START + 16)       /* Smart Card Interface */
-#define IRQ_PBA8_MMCI0A         (IRQ_PBA8_GIC_START + 17)       /* Multimedia Card 0A */
-#define IRQ_PBA8_MMCI0B         (IRQ_PBA8_GIC_START + 18)       /* Multimedia Card 0B */
-#define IRQ_PBA8_AACI           (IRQ_PBA8_GIC_START + 19)       /* Audio Codec */
-#define IRQ_PBA8_KMI0           (IRQ_PBA8_GIC_START + 20)       /* Keyboard/Mouse port 0 */
-#define IRQ_PBA8_KMI1           (IRQ_PBA8_GIC_START + 21)       /* Keyboard/Mouse port 1 */
-#define IRQ_PBA8_CHARLCD        (IRQ_PBA8_GIC_START + 22)       /* Character LCD */
-#define IRQ_PBA8_CLCD           (IRQ_PBA8_GIC_START + 23)       /* CLCD controller */
-#define IRQ_PBA8_DMAC           (IRQ_PBA8_GIC_START + 24)       /* DMA controller */
-#define IRQ_PBA8_PWRFAIL        (IRQ_PBA8_GIC_START + 25)       /* Power failure */
-#define IRQ_PBA8_PISMO          (IRQ_PBA8_GIC_START + 26)       /* PISMO interface */
-#define IRQ_PBA8_DoC            (IRQ_PBA8_GIC_START + 27)       /* Disk on Chip memory controller */
-#define IRQ_PBA8_ETH            (IRQ_PBA8_GIC_START + 28)       /* Ethernet controller */
-#define IRQ_PBA8_USB            (IRQ_PBA8_GIC_START + 29)       /* USB controller */
-#define IRQ_PBA8_TSPEN          (IRQ_PBA8_GIC_START + 30)       /* Touchscreen pen */
-#define IRQ_PBA8_TSKPAD         (IRQ_PBA8_GIC_START + 31)       /* Touchscreen keypad */
-/* ... */
-#define IRQ_PBA8_PCI0           (IRQ_PBA8_GIC_START + 50)
-#define IRQ_PBA8_PCI1           (IRQ_PBA8_GIC_START + 51)
-#define IRQ_PBA8_PCI2           (IRQ_PBA8_GIC_START + 52)
-#define IRQ_PBA8_PCI3           (IRQ_PBA8_GIC_START + 53)
-#define IRQ_PBA8_SMC            -1
-#define IRQ_PBA8_SCTL           -1
-#define NR_GIC_PBA8             1
-/*
- * Only define NR_IRQS if less than NR_IRQS_PBA8
- */
-#define NR_IRQS_PBA8            (IRQ_PBA8_GIC_START + 64)
-#if defined(CONFIG_MACH_REALVIEW_PBA8)
-#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8)
-#undef NR_IRQS
-#define NR_IRQS                 NR_IRQS_PBA8
-#endif
-#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8)
-#undef MAX_GIC_NR
-#define MAX_GIC_NR              NR_GIC_PBA8
-#endif
-#endif  /* CONFIG_MACH_REALVIEW_PBA8 */
 #endif  /* __ASM_ARCH_BOARD_PBA8_H */
diff --git a/arch/arm/mach-realview/include/mach/board-pbx.h b/arch/arm/mach-realview/include/mach/board-pbx.h
new file mode 100644
index 000000000000..848bfff6d8f1
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/board-pbx.h
@@ -0,0 +1,108 @@
+/*
+ * arch/arm/mach-realview/include/mach/board-pbx.h
+ *
+ * Copyright (C) 2009 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_BOARD_PBX_H
+#define __ASM_ARCH_BOARD_PBX_H
+#include <mach/platform.h>
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PBX_UART0_BASE                 0x10009000      /* UART 0 */
+#define REALVIEW_PBX_UART1_BASE                 0x1000A000      /* UART 1 */
+#define REALVIEW_PBX_UART2_BASE                 0x1000B000      /* UART 2 */
+#define REALVIEW_PBX_UART3_BASE                 0x1000C000      /* UART 3 */
+#define REALVIEW_PBX_SSP_BASE                   0x1000D000      /* Synchronous Serial Port */
+#define REALVIEW_PBX_WATCHDOG0_BASE             0x1000F000      /* Watchdog 0 */
+#define REALVIEW_PBX_WATCHDOG_BASE              0x10010000      /* watchdog interface */
+#define REALVIEW_PBX_TIMER0_1_BASE              0x10011000      /* Timer 0 and 1 */
+#define REALVIEW_PBX_TIMER2_3_BASE              0x10012000      /* Timer 2 and 3 */
+#define REALVIEW_PBX_GPIO0_BASE                 0x10013000      /* GPIO port 0 */
+#define REALVIEW_PBX_RTC_BASE                   0x10017000      /* Real Time Clock */
+#define REALVIEW_PBX_TIMER4_5_BASE              0x10018000      /* Timer 4/5 */
+#define REALVIEW_PBX_TIMER6_7_BASE              0x10019000      /* Timer 6/7 */
+#define REALVIEW_PBX_SCTL_BASE                  0x1001A000      /* System Controller */
+#define REALVIEW_PBX_CLCD_BASE                  0x10020000      /* CLCD */
+#define REALVIEW_PBX_ONB_SRAM_BASE              0x10060000      /* On-board SRAM */
+#define REALVIEW_PBX_DMC_BASE                   0x100E0000      /* DMC configuration */
+#define REALVIEW_PBX_SMC_BASE                   0x100E1000      /* SMC configuration */
+#define REALVIEW_PBX_CAN_BASE                   0x100E2000      /* CAN bus */
+#define REALVIEW_PBX_GIC_CPU_BASE               0x1E000000      /* Generic interrupt controller CPU interface */
+#define REALVIEW_PBX_FLASH0_BASE                0x40000000
+#define REALVIEW_PBX_FLASH0_SIZE                SZ_64M
+#define REALVIEW_PBX_FLASH1_BASE                0x44000000
+#define REALVIEW_PBX_FLASH1_SIZE                SZ_64M
+#define REALVIEW_PBX_ETH_BASE                   0x4E000000      /* Ethernet */
+#define REALVIEW_PBX_USB_BASE                   0x4F000000      /* USB */
+#define REALVIEW_PBX_GIC_DIST_BASE              0x1E001000      /* Generic interrupt controller distributor */
+#define REALVIEW_PBX_LT_BASE                    0xC0000000      /* Logic Tile expansion */
+#define REALVIEW_PBX_SDRAM6_BASE                0x70000000      /* SDRAM bank 6 256MB */
+#define REALVIEW_PBX_SDRAM7_BASE                0x80000000      /* SDRAM bank 7 256MB */
+/*
+ * Tile-specific addresses
+ */
+#define REALVIEW_PBX_TILE_SCU_BASE              0x1F000000      /* SCU registers */
+#define REALVIEW_PBX_TILE_GIC_CPU_BASE          0x1F000100      /* Private Generic interrupt controller CPU interface */
+#define REALVIEW_PBX_TILE_TWD_BASE              0x1F000600
+#define REALVIEW_PBX_TILE_TWD_PERCPU_BASE       0x1F000700
+#define REALVIEW_PBX_TILE_TWD_SIZE              0x00000100
+#define REALVIEW_PBX_TILE_GIC_DIST_BASE         0x1F001000      /* Private Generic interrupt controller distributor */
+#define REALVIEW_PBX_TILE_L220_BASE             0x1F002000      /* L220 registers */
+#define REALVIEW_PBX_SYS_PLD_CTRL1              0x74
+/*
+ * PBX PCI regions
+ */
+#define REALVIEW_PBX_PCI_BASE                   0x90040000      /* PCI-X Unit base */
+#define REALVIEW_PBX_PCI_IO_BASE                0x90050000      /* IO Region on AHB */
+#define REALVIEW_PBX_PCI_MEM_BASE               0xA0000000      /* MEM Region on AHB */
+#define REALVIEW_PBX_PCI_BASE_SIZE              0x10000         /* 16 Kb */
+#define REALVIEW_PBX_PCI_IO_SIZE                0x1000          /* 4 Kb */
+#define REALVIEW_PBX_PCI_MEM_SIZE               0x20000000      /* 512 MB */
+/*
+ * Core tile identification (REALVIEW_SYS_PROCID)
+ */
+#define REALVIEW_PBX_PROC_MASK          0xFF000000
+#define REALVIEW_PBX_PROC_ARM7TDMI      0x00000000
+#define REALVIEW_PBX_PROC_ARM9          0x02000000
+#define REALVIEW_PBX_PROC_ARM11         0x04000000
+#define REALVIEW_PBX_PROC_ARM11MP       0x06000000
+#define REALVIEW_PBX_PROC_A9MP          0x0C000000
+#define REALVIEW_PBX_PROC_A8            0x0E000000
+#define check_pbx_proc(proc_type)                                            \
+        ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_PBX_PROC_MASK) \
+        == proc_type)
+#ifdef CONFIG_MACH_REALVIEW_PBX
+#define core_tile_pbx11mp()     check_pbx_proc(REALVIEW_PBX_PROC_ARM11MP)
+#define core_tile_pbxa9mp()     check_pbx_proc(REALVIEW_PBX_PROC_A9MP)
+#define core_tile_pbxa8()       check_pbx_proc(REALVIEW_PBX_PROC_A8)
+#else
+#define core_tile_pbx11mp()     0
+#define core_tile_pbxa9mp()     0
+#define core_tile_pbxa8()       0
+#endif
+#endif  /* __ASM_ARCH_BOARD_PBX_H */
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index 92dbcb9e1792..932d8af18062 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -12,7 +12,8 @@
 #if defined(CONFIG_MACH_REALVIEW_EB) || \
    defined(CONFIG_MACH_REALVIEW_PB11MP) || \
-    defined(CONFIG_MACH_REALVIEW_PBA8)
+    defined(CONFIG_MACH_REALVIEW_PBA8) || \
+    defined(CONFIG_MACH_REALVIEW_PBX)
 #ifndef DEBUG_LL_UART_OFFSET
 #define DEBUG_LL_UART_OFFSET    0x00009000
 #elif DEBUG_LL_UART_OFFSET != 0x00009000
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
new file mode 100644
index 000000000000..204d5378f309
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -0,0 +1,129 @@
+/*
+ * arch/arm/mach-realview/include/mach/irqs-eb.h
+ *
+ * Copyright (C) 2007 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_IRQS_EB_H
+#define __MACH_IRQS_EB_H
+#define IRQ_EB_GIC_START        32
+/*
+ * RealView EB interrupt sources
+ */
+#define IRQ_EB_WDOG             (IRQ_EB_GIC_START + 0)          /* Watchdog timer */
+#define IRQ_EB_SOFT             (IRQ_EB_GIC_START + 1)          /* Software interrupt */
+#define IRQ_EB_COMMRx           (IRQ_EB_GIC_START + 2)          /* Debug Comm Rx interrupt */
+#define IRQ_EB_COMMTx           (IRQ_EB_GIC_START + 3)          /* Debug Comm Tx interrupt */
+#define IRQ_EB_TIMER0_1         (IRQ_EB_GIC_START + 4)          /* Timer 0 and 1 */
+#define IRQ_EB_TIMER2_3         (IRQ_EB_GIC_START + 5)          /* Timer 2 and 3 */
+#define IRQ_EB_GPIO0            (IRQ_EB_GIC_START + 6)          /* GPIO 0 */
+#define IRQ_EB_GPIO1            (IRQ_EB_GIC_START + 7)          /* GPIO 1 */
+#define IRQ_EB_GPIO2            (IRQ_EB_GIC_START + 8)          /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_EB_RTC              (IRQ_EB_GIC_START + 10)         /* Real Time Clock */
+#define IRQ_EB_SSP              (IRQ_EB_GIC_START + 11)         /* Synchronous Serial Port */
+#define IRQ_EB_UART0            (IRQ_EB_GIC_START + 12)         /* UART 0 on development chip */
+#define IRQ_EB_UART1            (IRQ_EB_GIC_START + 13)         /* UART 1 on development chip */
+#define IRQ_EB_UART2            (IRQ_EB_GIC_START + 14)         /* UART 2 on development chip */
+#define IRQ_EB_UART3            (IRQ_EB_GIC_START + 15)         /* UART 3 on development chip */
+#define IRQ_EB_SCI              (IRQ_EB_GIC_START + 16)         /* Smart Card Interface */
+#define IRQ_EB_MMCI0A           (IRQ_EB_GIC_START + 17)         /* Multimedia Card 0A */
+#define IRQ_EB_MMCI0B           (IRQ_EB_GIC_START + 18)         /* Multimedia Card 0B */
+#define IRQ_EB_AACI             (IRQ_EB_GIC_START + 19)         /* Audio Codec */
+#define IRQ_EB_KMI0             (IRQ_EB_GIC_START + 20)         /* Keyboard/Mouse port 0 */
+#define IRQ_EB_KMI1             (IRQ_EB_GIC_START + 21)         /* Keyboard/Mouse port 1 */
+#define IRQ_EB_CHARLCD          (IRQ_EB_GIC_START + 22)         /* Character LCD */
+#define IRQ_EB_CLCD             (IRQ_EB_GIC_START + 23)         /* CLCD controller */
+#define IRQ_EB_DMA              (IRQ_EB_GIC_START + 24)         /* DMA controller */
+#define IRQ_EB_PWRFAIL          (IRQ_EB_GIC_START + 25)         /* Power failure */
+#define IRQ_EB_PISMO            (IRQ_EB_GIC_START + 26)         /* PISMO interface */
+#define IRQ_EB_DoC              (IRQ_EB_GIC_START + 27)         /* Disk on Chip memory controller */
+#define IRQ_EB_ETH              (IRQ_EB_GIC_START + 28)         /* Ethernet controller */
+#define IRQ_EB_USB              (IRQ_EB_GIC_START + 29)         /* USB controller */
+#define IRQ_EB_TSPEN            (IRQ_EB_GIC_START + 30)         /* Touchscreen pen */
+#define IRQ_EB_TSKPAD           (IRQ_EB_GIC_START + 31)         /* Touchscreen keypad */
+/*
+ * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
+ */
+#define IRQ_EB11MP_AACI         (IRQ_EB_GIC_START + 0)
+#define IRQ_EB11MP_TIMER0_1     (IRQ_EB_GIC_START + 1)
+#define IRQ_EB11MP_TIMER2_3     (IRQ_EB_GIC_START + 2)
+#define IRQ_EB11MP_USB          (IRQ_EB_GIC_START + 3)
+#define IRQ_EB11MP_UART0        (IRQ_EB_GIC_START + 4)
+#define IRQ_EB11MP_UART1        (IRQ_EB_GIC_START + 5)
+#define IRQ_EB11MP_RTC          (IRQ_EB_GIC_START + 6)
+#define IRQ_EB11MP_KMI0         (IRQ_EB_GIC_START + 7)
+#define IRQ_EB11MP_KMI1         (IRQ_EB_GIC_START + 8)
+#define IRQ_EB11MP_ETH          (IRQ_EB_GIC_START + 9)
+#define IRQ_EB11MP_EB_IRQ1      (IRQ_EB_GIC_START + 10)         /* main GIC */
+#define IRQ_EB11MP_EB_IRQ2      (IRQ_EB_GIC_START + 11)         /* tile GIC */
+#define IRQ_EB11MP_EB_FIQ1      (IRQ_EB_GIC_START + 12)         /* main GIC */
+#define IRQ_EB11MP_EB_FIQ2      (IRQ_EB_GIC_START + 13)         /* tile GIC */
+#define IRQ_EB11MP_MMCI0A       (IRQ_EB_GIC_START + 14)
+#define IRQ_EB11MP_MMCI0B       (IRQ_EB_GIC_START + 15)
+#define IRQ_EB11MP_PMU_CPU0     (IRQ_EB_GIC_START + 17)
+#define IRQ_EB11MP_PMU_CPU1     (IRQ_EB_GIC_START + 18)
+#define IRQ_EB11MP_PMU_CPU2     (IRQ_EB_GIC_START + 19)
+#define IRQ_EB11MP_PMU_CPU3     (IRQ_EB_GIC_START + 20)
+#define IRQ_EB11MP_PMU_SCU0     (IRQ_EB_GIC_START + 21)
+#define IRQ_EB11MP_PMU_SCU1     (IRQ_EB_GIC_START + 22)
+#define IRQ_EB11MP_PMU_SCU2     (IRQ_EB_GIC_START + 23)
+#define IRQ_EB11MP_PMU_SCU3     (IRQ_EB_GIC_START + 24)
+#define IRQ_EB11MP_PMU_SCU4     (IRQ_EB_GIC_START + 25)
+#define IRQ_EB11MP_PMU_SCU5     (IRQ_EB_GIC_START + 26)
+#define IRQ_EB11MP_PMU_SCU6     (IRQ_EB_GIC_START + 27)
+#define IRQ_EB11MP_PMU_SCU7     (IRQ_EB_GIC_START + 28)
+#define IRQ_EB11MP_L220_EVENT   (IRQ_EB_GIC_START + 29)
+#define IRQ_EB11MP_L220_SLAVE   (IRQ_EB_GIC_START + 30)
+#define IRQ_EB11MP_L220_DECODE  (IRQ_EB_GIC_START + 31)
+#define IRQ_EB11MP_UART2        -1
+#define IRQ_EB11MP_UART3        -1
+#define IRQ_EB11MP_CLCD         -1
+#define IRQ_EB11MP_DMA          -1
+#define IRQ_EB11MP_WDOG         -1
+#define IRQ_EB11MP_GPIO0        -1
+#define IRQ_EB11MP_GPIO1        -1
+#define IRQ_EB11MP_GPIO2        -1
+#define IRQ_EB11MP_SCI          -1
+#define IRQ_EB11MP_SSP          -1
+#define NR_GIC_EB11MP           2
+/*
+ * Only define NR_IRQS if less than NR_IRQS_EB
+ */
+#define NR_IRQS_EB              (IRQ_EB_GIC_START + 96)
+#if defined(CONFIG_MACH_REALVIEW_EB) \
+        && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_EB
+#endif
+#if defined(CONFIG_REALVIEW_EB_ARM11MP) || defined(CONFIG_REALVIEW_EB_A9MP) \
+        && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_EB11MP
+#endif
+#endif  /* __MACH_IRQS_EB_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
new file mode 100644
index 000000000000..2410d4f8ddd3
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -0,0 +1,99 @@
+/*
+ * arch/arm/mach-realview/include/mach/irqs-pb1176.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_IRQS_PB1176_H
+#define __MACH_IRQS_PB1176_H
+#define IRQ_DC1176_GIC_START                    32
+#define IRQ_PB1176_GIC_START                    64
+/*
+ * ARM1176 DevChip interrupt sources (primary GIC)
+ */
+#define IRQ_DC1176_WATCHDOG     (IRQ_DC1176_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_DC1176_SOFTINT      (IRQ_DC1176_GIC_START + 1)      /* Software interrupt */
+#define IRQ_DC1176_COMMRx       (IRQ_DC1176_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_DC1176_COMMTx       (IRQ_DC1176_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_DC1176_TIMER0       (IRQ_DC1176_GIC_START + 8)      /* Timer 0 */
+#define IRQ_DC1176_TIMER1       (IRQ_DC1176_GIC_START + 9)      /* Timer 1 */
+#define IRQ_DC1176_TIMER2       (IRQ_DC1176_GIC_START + 10)     /* Timer 2 */
+#define IRQ_DC1176_APC          (IRQ_DC1176_GIC_START + 11)
+#define IRQ_DC1176_IEC          (IRQ_DC1176_GIC_START + 12)
+#define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
+#define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
+#define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
+#define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
+#define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
+#define IRQ_DC1176_UART3        (IRQ_DC1176_GIC_START + 21)     /* UART 3 on development chip */
+#define IRQ_DC1176_PB_IRQ2      (IRQ_DC1176_GIC_START + 30)     /* tile GIC */
+#define IRQ_DC1176_PB_IRQ1      (IRQ_DC1176_GIC_START + 31)     /* main GIC */
+/*
+ * RealView PB1176 interrupt sources (secondary GIC)
+ */
+#define IRQ_PB1176_MMCI0A       (IRQ_PB1176_GIC_START + 1)      /* Multimedia Card 0A */
+#define IRQ_PB1176_MMCI0B       (IRQ_PB1176_GIC_START + 2)      /* Multimedia Card 0A */
+#define IRQ_PB1176_KMI0         (IRQ_PB1176_GIC_START + 3)      /* Keyboard/Mouse port 0 */
+#define IRQ_PB1176_KMI1         (IRQ_PB1176_GIC_START + 4)      /* Keyboard/Mouse port 1 */
+#define IRQ_PB1176_SCI          (IRQ_PB1176_GIC_START + 5)
+#define IRQ_PB1176_UART4        (IRQ_PB1176_GIC_START + 6)      /* UART 4 on baseboard */
+#define IRQ_PB1176_CHARLCD      (IRQ_PB1176_GIC_START + 7)      /* Character LCD */
+#define IRQ_PB1176_GPIO1        (IRQ_PB1176_GIC_START + 8)
+#define IRQ_PB1176_GPIO2        (IRQ_PB1176_GIC_START + 9)
+#define IRQ_PB1176_ETH          (IRQ_PB1176_GIC_START + 10)     /* Ethernet controller */
+#define IRQ_PB1176_USB          (IRQ_PB1176_GIC_START + 11)     /* USB controller */
+#define IRQ_PB1176_PISMO        (IRQ_PB1176_GIC_START + 16)
+#define IRQ_PB1176_AACI         (IRQ_PB1176_GIC_START + 19)     /* Audio Codec */
+#define IRQ_PB1176_TIMER0_1     (IRQ_PB1176_GIC_START + 22)
+#define IRQ_PB1176_TIMER2_3     (IRQ_PB1176_GIC_START + 23)
+#define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
+#define IRQ_PB1176_GPIO0        -1
+#define IRQ_PB1176_SSP          -1
+#define IRQ_PB1176_SCTL         -1
+#define NR_GIC_PB1176           2
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB1176
+ */
+#define NR_IRQS_PB1176          (IRQ_DC1176_GIC_START + 96)
+#if defined(CONFIG_MACH_REALVIEW_PB1176)
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB1176
+#endif
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB1176
+#endif
+#endif  /* CONFIG_MACH_REALVIEW_PB1176 */
+#endif  /* __MACH_IRQS_PB1176_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb11mp.h b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h
new file mode 100644
index 000000000000..34e255add21e
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pb11mp.h
@@ -0,0 +1,122 @@
+/*
+ * arch/arm/mach-realview/include/mach/irqs-pb11mp.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_IRQS_PB11MP_H
+#define __MACH_IRQS_PB11MP_H
+#define IRQ_TC11MP_GIC_START                    32
+#define IRQ_PB11MP_GIC_START                    64
+/*
+ * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
+ */
+#define IRQ_TC11MP_AACI         (IRQ_TC11MP_GIC_START + 0)
+#define IRQ_TC11MP_TIMER0_1     (IRQ_TC11MP_GIC_START + 1)
+#define IRQ_TC11MP_TIMER2_3     (IRQ_TC11MP_GIC_START + 2)
+#define IRQ_TC11MP_USB          (IRQ_TC11MP_GIC_START + 3)
+#define IRQ_TC11MP_UART0        (IRQ_TC11MP_GIC_START + 4)
+#define IRQ_TC11MP_UART1        (IRQ_TC11MP_GIC_START + 5)
+#define IRQ_TC11MP_RTC          (IRQ_TC11MP_GIC_START + 6)
+#define IRQ_TC11MP_KMI0         (IRQ_TC11MP_GIC_START + 7)
+#define IRQ_TC11MP_KMI1         (IRQ_TC11MP_GIC_START + 8)
+#define IRQ_TC11MP_ETH          (IRQ_TC11MP_GIC_START + 9)
+#define IRQ_TC11MP_PB_IRQ1      (IRQ_TC11MP_GIC_START + 10)             /* main GIC */
+#define IRQ_TC11MP_PB_IRQ2      (IRQ_TC11MP_GIC_START + 11)             /* tile GIC */
+#define IRQ_TC11MP_PB_FIQ1      (IRQ_TC11MP_GIC_START + 12)             /* main GIC */
+#define IRQ_TC11MP_PB_FIQ2      (IRQ_TC11MP_GIC_START + 13)             /* tile GIC */
+#define IRQ_TC11MP_MMCI0A       (IRQ_TC11MP_GIC_START + 14)
+#define IRQ_TC11MP_MMCI0B       (IRQ_TC11MP_GIC_START + 15)
+#define IRQ_TC11MP_PMU_CPU0     (IRQ_TC11MP_GIC_START + 17)
+#define IRQ_TC11MP_PMU_CPU1     (IRQ_TC11MP_GIC_START + 18)
+#define IRQ_TC11MP_PMU_CPU2     (IRQ_TC11MP_GIC_START + 19)
+#define IRQ_TC11MP_PMU_CPU3     (IRQ_TC11MP_GIC_START + 20)
+#define IRQ_TC11MP_PMU_SCU0     (IRQ_TC11MP_GIC_START + 21)
+#define IRQ_TC11MP_PMU_SCU1     (IRQ_TC11MP_GIC_START + 22)
+#define IRQ_TC11MP_PMU_SCU2     (IRQ_TC11MP_GIC_START + 23)
+#define IRQ_TC11MP_PMU_SCU3     (IRQ_TC11MP_GIC_START + 24)
+#define IRQ_TC11MP_PMU_SCU4     (IRQ_TC11MP_GIC_START + 25)
+#define IRQ_TC11MP_PMU_SCU5     (IRQ_TC11MP_GIC_START + 26)
+#define IRQ_TC11MP_PMU_SCU6     (IRQ_TC11MP_GIC_START + 27)
+#define IRQ_TC11MP_PMU_SCU7     (IRQ_TC11MP_GIC_START + 28)
+#define IRQ_TC11MP_L220_EVENT   (IRQ_TC11MP_GIC_START + 29)
+#define IRQ_TC11MP_L220_SLAVE   (IRQ_TC11MP_GIC_START + 30)
+#define IRQ_TC11MP_L220_DECODE  (IRQ_TC11MP_GIC_START + 31)
+/*
+ * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
+ */
+#define IRQ_PB11MP_WATCHDOG     (IRQ_PB11MP_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_PB11MP_SOFT         (IRQ_PB11MP_GIC_START + 1)      /* Software interrupt */
+#define IRQ_PB11MP_COMMRx       (IRQ_PB11MP_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_PB11MP_COMMTx       (IRQ_PB11MP_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_PB11MP_GPIO0        (IRQ_PB11MP_GIC_START + 6)      /* GPIO 0 */
+#define IRQ_PB11MP_GPIO1        (IRQ_PB11MP_GIC_START + 7)      /* GPIO 1 */
+#define IRQ_PB11MP_GPIO2        (IRQ_PB11MP_GIC_START + 8)      /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_PB11MP_RTC_GIC1     (IRQ_PB11MP_GIC_START + 10)     /* Real Time Clock */
+#define IRQ_PB11MP_SSP          (IRQ_PB11MP_GIC_START + 11)     /* Synchronous Serial Port */
+#define IRQ_PB11MP_UART0_GIC1   (IRQ_PB11MP_GIC_START + 12)     /* UART 0 on development chip */
+#define IRQ_PB11MP_UART1_GIC1   (IRQ_PB11MP_GIC_START + 13)     /* UART 1 on development chip */
+#define IRQ_PB11MP_UART2        (IRQ_PB11MP_GIC_START + 14)     /* UART 2 on development chip */
+#define IRQ_PB11MP_UART3        (IRQ_PB11MP_GIC_START + 15)     /* UART 3 on development chip */
+#define IRQ_PB11MP_SCI          (IRQ_PB11MP_GIC_START + 16)     /* Smart Card Interface */
+#define IRQ_PB11MP_MMCI0A_GIC1  (IRQ_PB11MP_GIC_START + 17)     /* Multimedia Card 0A */
+#define IRQ_PB11MP_MMCI0B_GIC1  (IRQ_PB11MP_GIC_START + 18)     /* Multimedia Card 0B */
+#define IRQ_PB11MP_AACI_GIC1    (IRQ_PB11MP_GIC_START + 19)     /* Audio Codec */
+#define IRQ_PB11MP_KMI0_GIC1    (IRQ_PB11MP_GIC_START + 20)     /* Keyboard/Mouse port 0 */
+#define IRQ_PB11MP_KMI1_GIC1    (IRQ_PB11MP_GIC_START + 21)     /* Keyboard/Mouse port 1 */
+#define IRQ_PB11MP_CHARLCD      (IRQ_PB11MP_GIC_START + 22)     /* Character LCD */
+#define IRQ_PB11MP_CLCD         (IRQ_PB11MP_GIC_START + 23)     /* CLCD controller */
+#define IRQ_PB11MP_DMAC         (IRQ_PB11MP_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB11MP_PWRFAIL      (IRQ_PB11MP_GIC_START + 25)     /* Power failure */
+#define IRQ_PB11MP_PISMO        (IRQ_PB11MP_GIC_START + 26)     /* PISMO interface */
+#define IRQ_PB11MP_DoC          (IRQ_PB11MP_GIC_START + 27)     /* Disk on Chip memory controller */
+#define IRQ_PB11MP_ETH_GIC1     (IRQ_PB11MP_GIC_START + 28)     /* Ethernet controller */
+#define IRQ_PB11MP_USB_GIC1     (IRQ_PB11MP_GIC_START + 29)     /* USB controller */
+#define IRQ_PB11MP_TSPEN        (IRQ_PB11MP_GIC_START + 30)     /* Touchscreen pen */
+#define IRQ_PB11MP_TSKPAD       (IRQ_PB11MP_GIC_START + 31)     /* Touchscreen keypad */
+#define IRQ_PB11MP_SMC          -1
+#define IRQ_PB11MP_SCTL         -1
+#define NR_GIC_PB11MP           2
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB11MP
+ */
+#define NR_IRQS_PB11MP          (IRQ_TC11MP_GIC_START + 96)
+#if defined(CONFIG_MACH_REALVIEW_PB11MP)
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB11MP
+#endif
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB11MP
+#endif
+#endif  /* CONFIG_MACH_REALVIEW_PB11MP */
+#endif  /* __MACH_IRQS_PB11MP_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pba8.h b/arch/arm/mach-realview/include/mach/irqs-pba8.h
new file mode 100644
index 000000000000..86792a9f2ab6
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pba8.h
@@ -0,0 +1,98 @@
+/*
+ * arch/arm/mach-realview/include/mach/irqs-pba8.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_IRQS_PBA8_H
+#define __MACH_IRQS_PBA8_H
+#define IRQ_PBA8_GIC_START                      32
+/* L220
+#define IRQ_PBA8_L220_EVENT     (IRQ_PBA8_GIC_START + 29)
+#define IRQ_PBA8_L220_SLAVE     (IRQ_PBA8_GIC_START + 30)
+#define IRQ_PBA8_L220_DECODE    (IRQ_PBA8_GIC_START + 31)
+*/
+/*
+ * PB-A8 on-board gic irq sources
+ */
+#define IRQ_PBA8_WATCHDOG       (IRQ_PBA8_GIC_START + 0)        /* Watchdog timer */
+#define IRQ_PBA8_SOFT           (IRQ_PBA8_GIC_START + 1)        /* Software interrupt */
+#define IRQ_PBA8_COMMRx         (IRQ_PBA8_GIC_START + 2)        /* Debug Comm Rx interrupt */
+#define IRQ_PBA8_COMMTx         (IRQ_PBA8_GIC_START + 3)        /* Debug Comm Tx interrupt */
+#define IRQ_PBA8_TIMER0_1       (IRQ_PBA8_GIC_START + 4)        /* Timer 0/1 (default timer) */
+#define IRQ_PBA8_TIMER2_3       (IRQ_PBA8_GIC_START + 5)        /* Timer 2/3 */
+#define IRQ_PBA8_GPIO0          (IRQ_PBA8_GIC_START + 6)        /* GPIO 0 */
+#define IRQ_PBA8_GPIO1          (IRQ_PBA8_GIC_START + 7)        /* GPIO 1 */
+#define IRQ_PBA8_GPIO2          (IRQ_PBA8_GIC_START + 8)        /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_PBA8_RTC            (IRQ_PBA8_GIC_START + 10)       /* Real Time Clock */
+#define IRQ_PBA8_SSP            (IRQ_PBA8_GIC_START + 11)       /* Synchronous Serial Port */
+#define IRQ_PBA8_UART0          (IRQ_PBA8_GIC_START + 12)       /* UART 0 on development chip */
+#define IRQ_PBA8_UART1          (IRQ_PBA8_GIC_START + 13)       /* UART 1 on development chip */
+#define IRQ_PBA8_UART2          (IRQ_PBA8_GIC_START + 14)       /* UART 2 on development chip */
+#define IRQ_PBA8_UART3          (IRQ_PBA8_GIC_START + 15)       /* UART 3 on development chip */
+#define IRQ_PBA8_SCI            (IRQ_PBA8_GIC_START + 16)       /* Smart Card Interface */
+#define IRQ_PBA8_MMCI0A         (IRQ_PBA8_GIC_START + 17)       /* Multimedia Card 0A */
+#define IRQ_PBA8_MMCI0B         (IRQ_PBA8_GIC_START + 18)       /* Multimedia Card 0B */
+#define IRQ_PBA8_AACI           (IRQ_PBA8_GIC_START + 19)       /* Audio Codec */
+#define IRQ_PBA8_KMI0           (IRQ_PBA8_GIC_START + 20)       /* Keyboard/Mouse port 0 */
+#define IRQ_PBA8_KMI1           (IRQ_PBA8_GIC_START + 21)       /* Keyboard/Mouse port 1 */
+#define IRQ_PBA8_CHARLCD        (IRQ_PBA8_GIC_START + 22)       /* Character LCD */
+#define IRQ_PBA8_CLCD           (IRQ_PBA8_GIC_START + 23)       /* CLCD controller */
+#define IRQ_PBA8_DMAC           (IRQ_PBA8_GIC_START + 24)       /* DMA controller */
+#define IRQ_PBA8_PWRFAIL        (IRQ_PBA8_GIC_START + 25)       /* Power failure */
+#define IRQ_PBA8_PISMO          (IRQ_PBA8_GIC_START + 26)       /* PISMO interface */
+#define IRQ_PBA8_DoC            (IRQ_PBA8_GIC_START + 27)       /* Disk on Chip memory controller */
+#define IRQ_PBA8_ETH            (IRQ_PBA8_GIC_START + 28)       /* Ethernet controller */
+#define IRQ_PBA8_USB            (IRQ_PBA8_GIC_START + 29)       /* USB controller */
+#define IRQ_PBA8_TSPEN          (IRQ_PBA8_GIC_START + 30)       /* Touchscreen pen */
+#define IRQ_PBA8_TSKPAD         (IRQ_PBA8_GIC_START + 31)       /* Touchscreen keypad */
+/* ... */
+#define IRQ_PBA8_PCI0           (IRQ_PBA8_GIC_START + 50)
+#define IRQ_PBA8_PCI1           (IRQ_PBA8_GIC_START + 51)
+#define IRQ_PBA8_PCI2           (IRQ_PBA8_GIC_START + 52)
+#define IRQ_PBA8_PCI3           (IRQ_PBA8_GIC_START + 53)
+#define IRQ_PBA8_SMC            -1
+#define IRQ_PBA8_SCTL           -1
+#define NR_GIC_PBA8             1
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PBA8
+ */
+#define NR_IRQS_PBA8            (IRQ_PBA8_GIC_START + 64)
+#if defined(CONFIG_MACH_REALVIEW_PBA8)
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBA8)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PBA8
+#endif
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBA8)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PBA8
+#endif
+#endif  /* CONFIG_MACH_REALVIEW_PBA8 */
+#endif  /* __MACH_IRQS_PBA8_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs-pbx.h b/arch/arm/mach-realview/include/mach/irqs-pbx.h
new file mode 100644
index 000000000000..deaad4302b17
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/irqs-pbx.h
@@ -0,0 +1,115 @@
+/*
+ * arch/arm/mach-realview/include/mach/irqs-pbx.h
+ *
+ * Copyright (C) 2009 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __MACH_IRQS_PBX_H
+#define __MACH_IRQS_PBX_H
+#define IRQ_PBX_GIC_START                       32
+/* L220
+#define IRQ_PBX_L220_EVENT      (IRQ_PBX_GIC_START + 29)
+#define IRQ_PBX_L220_SLAVE      (IRQ_PBX_GIC_START + 30)
+#define IRQ_PBX_L220_DECODE     (IRQ_PBX_GIC_START + 31)
+*/
+/*
+ * PBX on-board gic irq sources
+ */
+#define IRQ_PBX_WATCHDOG        (IRQ_PBX_GIC_START + 0) /* Watchdog timer */
+#define IRQ_PBX_SOFT            (IRQ_PBX_GIC_START + 1) /* Software interrupt */
+#define IRQ_PBX_COMMRx          (IRQ_PBX_GIC_START + 2) /* Debug Comm Rx interrupt */
+#define IRQ_PBX_COMMTx          (IRQ_PBX_GIC_START + 3) /* Debug Comm Tx interrupt */
+#define IRQ_PBX_TIMER0_1        (IRQ_PBX_GIC_START + 4) /* Timer 0/1 (default timer) */
+#define IRQ_PBX_TIMER2_3        (IRQ_PBX_GIC_START + 5) /* Timer 2/3 */
+#define IRQ_PBX_GPIO0           (IRQ_PBX_GIC_START + 6) /* GPIO 0 */
+#define IRQ_PBX_GPIO1           (IRQ_PBX_GIC_START + 7) /* GPIO 1 */
+#define IRQ_PBX_GPIO2           (IRQ_PBX_GIC_START + 8) /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_PBX_RTC             (IRQ_PBX_GIC_START + 10)        /* Real Time Clock */
+#define IRQ_PBX_SSP             (IRQ_PBX_GIC_START + 11)        /* Synchronous Serial Port */
+#define IRQ_PBX_UART0           (IRQ_PBX_GIC_START + 12)        /* UART 0 on development chip */
+#define IRQ_PBX_UART1           (IRQ_PBX_GIC_START + 13)        /* UART 1 on development chip */
+#define IRQ_PBX_UART2           (IRQ_PBX_GIC_START + 14)        /* UART 2 on development chip */
+#define IRQ_PBX_UART3           (IRQ_PBX_GIC_START + 15)        /* UART 3 on development chip */
+#define IRQ_PBX_SCI             (IRQ_PBX_GIC_START + 16)        /* Smart Card Interface */
+#define IRQ_PBX_MMCI0A          (IRQ_PBX_GIC_START + 17)        /* Multimedia Card 0A */
+#define IRQ_PBX_MMCI0B          (IRQ_PBX_GIC_START + 18)        /* Multimedia Card 0B */
+#define IRQ_PBX_AACI            (IRQ_PBX_GIC_START + 19)        /* Audio Codec */
+#define IRQ_PBX_KMI0            (IRQ_PBX_GIC_START + 20)        /* Keyboard/Mouse port 0 */
+#define IRQ_PBX_KMI1            (IRQ_PBX_GIC_START + 21)        /* Keyboard/Mouse port 1 */
+#define IRQ_PBX_CHARLCD         (IRQ_PBX_GIC_START + 22)        /* Character LCD */
+#define IRQ_PBX_CLCD            (IRQ_PBX_GIC_START + 23)        /* CLCD controller */
+#define IRQ_PBX_DMAC            (IRQ_PBX_GIC_START + 24)        /* DMA controller */
+#define IRQ_PBX_PWRFAIL         (IRQ_PBX_GIC_START + 25)        /* Power failure */
+#define IRQ_PBX_PISMO           (IRQ_PBX_GIC_START + 26)        /* PISMO interface */
+#define IRQ_PBX_DoC             (IRQ_PBX_GIC_START + 27)        /* Disk on Chip memory controller */
+#define IRQ_PBX_ETH             (IRQ_PBX_GIC_START + 28)        /* Ethernet controller */
+#define IRQ_PBX_USB             (IRQ_PBX_GIC_START + 29)        /* USB controller */
+#define IRQ_PBX_TSPEN           (IRQ_PBX_GIC_START + 30)        /* Touchscreen pen */
+#define IRQ_PBX_TSKPAD          (IRQ_PBX_GIC_START + 31)        /* Touchscreen keypad */
+#define IRQ_PBX_PMU_SCU0        (IRQ_PBX_GIC_START + 32)        /* SCU PMU Interrupts (11mp) */
+#define IRQ_PBX_PMU_SCU1        (IRQ_PBX_GIC_START + 33)
+#define IRQ_PBX_PMU_SCU2        (IRQ_PBX_GIC_START + 34)
+#define IRQ_PBX_PMU_SCU3        (IRQ_PBX_GIC_START + 35)
+#define IRQ_PBX_PMU_SCU4        (IRQ_PBX_GIC_START + 36)
+#define IRQ_PBX_PMU_SCU5        (IRQ_PBX_GIC_START + 37)
+#define IRQ_PBX_PMU_SCU6        (IRQ_PBX_GIC_START + 38)
+#define IRQ_PBX_PMU_SCU7        (IRQ_PBX_GIC_START + 39)
+#define IRQ_PBX_WATCHDOG1       (IRQ_PBX_GIC_START + 40)        /* Watchdog1 timer */
+#define IRQ_PBX_TIMER4_5        (IRQ_PBX_GIC_START + 41)        /* Timer 0/1 (default timer) */
+#define IRQ_PBX_TIMER6_7        (IRQ_PBX_GIC_START + 42)        /* Timer 2/3 */
+/* ... */
+#define IRQ_PBX_PMU_CPU3        (IRQ_PBX_GIC_START + 44)        /* CPU PMU Interrupts */
+#define IRQ_PBX_PMU_CPU2        (IRQ_PBX_GIC_START + 45)
+#define IRQ_PBX_PMU_CPU1        (IRQ_PBX_GIC_START + 46)
+#define IRQ_PBX_PMU_CPU0        (IRQ_PBX_GIC_START + 47)
+/* ... */
+#define IRQ_PBX_PCI0            (IRQ_PBX_GIC_START + 50)
+#define IRQ_PBX_PCI1            (IRQ_PBX_GIC_START + 51)
+#define IRQ_PBX_PCI2            (IRQ_PBX_GIC_START + 52)
+#define IRQ_PBX_PCI3            (IRQ_PBX_GIC_START + 53)
+#define IRQ_PBX_SMC             -1
+#define IRQ_PBX_SCTL            -1
+#define NR_GIC_PBX              1
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PBX
+ */
+#define NR_IRQS_PBX             (IRQ_PBX_GIC_START + 96)
+#if defined(CONFIG_MACH_REALVIEW_PBX)
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PBX)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PBX
+#endif
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PBX)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PBX
+#endif
+#endif  /* CONFIG_MACH_REALVIEW_PBX */
+#endif  /* __MACH_IRQS_PBX_H */
diff --git a/arch/arm/mach-realview/include/mach/irqs.h b/arch/arm/mach-realview/include/mach/irqs.h
index fe5cb987aa21..78854f2fa323 100644
--- a/arch/arm/mach-realview/include/mach/irqs.h
+++ b/arch/arm/mach-realview/include/mach/irqs.h
@@ -22,10 +22,11 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
-#include <mach/board-eb.h>
+#include <mach/irqs-eb.h>
-#include <mach/board-pb11mp.h>
+#include <mach/irqs-pb11mp.h>
-#include <mach/board-pb1176.h>
+#include <mach/irqs-pb1176.h>
-#include <mach/board-pba8.h>
+#include <mach/irqs-pba8.h>
+#include <mach/irqs-pbx.h>
 #define IRQ_LOCALTIMER          29
 #define IRQ_LOCALWDOG           30
diff --git a/arch/arm/mach-realview/include/mach/scu.h b/arch/arm/mach-realview/include/mach/scu.h
deleted file mode 100644
index d55802d645af..000000000000
--- a/arch/arm/mach-realview/include/mach/scu.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASMARM_ARCH_SCU_H
-#define __ASMARM_ARCH_SCU_H
-/*
- * SCU registers
- */
-#define SCU_CTRL                0x00
-#define SCU_CONFIG              0x04
-#define SCU_CPU_STATUS          0x08
-#define SCU_INVALIDATE          0x0c
-#define SCU_FPGA_REVISION       0x10
-#endif
diff --git a/arch/arm/mach-realview/include/mach/uncompress.h b/arch/arm/mach-realview/include/mach/uncompress.h
index 415d634d52ab..83050378ffd2 100644
--- a/arch/arm/mach-realview/include/mach/uncompress.h
+++ b/arch/arm/mach-realview/include/mach/uncompress.h
@@ -24,6 +24,7 @@
 #include <mach/board-pb11mp.h>
 #include <mach/board-pb1176.h>
 #include <mach/board-pba8.h>
+#include <mach/board-pbx.h>
 #define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
 #define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
@@ -43,6 +44,8 @@ static inline unsigned long get_uart_base(void)
                return REALVIEW_PB1176_UART0_BASE;
        else if (machine_is_realview_pba8())
                return REALVIEW_PBA8_UART0_BASE;
+        else if (machine_is_realview_pbx())
+                return REALVIEW_PBX_UART0_BASE;
        else
                return 0;
 }
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index 1c01d13460f0..60b4e111f459 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -9,196 +9,18 @@
 * published by the Free Software Foundation.
 */
 #include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/device.h>
 #include <linux/smp.h>
-#include <linux/jiffies.h>
-#include <linux/percpu.h>
 #include <linux/clockchips.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/hardware/arm_twd.h>
-#include <asm/hardware/gic.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/smp_twd.h>
-static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
+#include <asm/localtimer.h>
-/*
- * Used on SMP for either the local timer or IPI_TIMER
- */
-void local_timer_interrupt(void)
-{
-        struct clock_event_device *clk = &__get_cpu_var(local_clockevent);
-        clk->event_handler(clk);
-}
-#ifdef CONFIG_LOCAL_TIMERS
-/* set up by the platform code */
-void __iomem *twd_base;
-static unsigned long mpcore_timer_rate;
-static void local_timer_set_mode(enum clock_event_mode mode,
-                                 struct clock_event_device *clk)
-{
-        unsigned long ctrl;
-        switch(mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                /* timer load already set up */
-                ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
-                        | TWD_TIMER_CONTROL_PERIODIC;
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* period set, and timer enabled in 'next_event' hook */
-                ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        default:
-                ctrl = 0;
-        }
-        __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
-}
-static int local_timer_set_next_event(unsigned long evt,
-                                      struct clock_event_device *unused)
-{
-        unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
-        __raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
-        __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, twd_base + TWD_TIMER_CONTROL);
-        return 0;
-}
-/*
- * local_timer_ack: checks for a local timer interrupt.
- *
- * If a local timer interrupt has occurred, acknowledge and return 1.
- * Otherwise, return 0.
- */
-int local_timer_ack(void)
-{
-        if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
-                __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
-                return 1;
-        }
-        return 0;
-}
-static void __cpuinit twd_calibrate_rate(void)
-{
-        unsigned long load, count;
-        u64 waitjiffies;
-        /*
-         * If this is the first time round, we need to work out how fast
-         * the timer ticks
-         */
-        if (mpcore_timer_rate == 0) {
-                printk("Calibrating local timer... ");
-                /* Wait for a tick to start */
-                waitjiffies = get_jiffies_64() + 1;
-                while (get_jiffies_64() < waitjiffies)
-                        udelay(10);
-                /* OK, now the tick has started, let's get the timer going */
-                waitjiffies += 5;
-                                 /* enable, no interrupt or reload */
-                __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
-                                 /* maximum value */
-                __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
-                while (get_jiffies_64() < waitjiffies)
-                        udelay(10);
-                count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
-                mpcore_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
-                printk("%lu.%02luMHz.\n", mpcore_timer_rate / 1000000,
-                        (mpcore_timer_rate / 100000) % 100);
-        }
-        load = mpcore_timer_rate / HZ;
-        __raw_writel(load, twd_base + TWD_TIMER_LOAD);
-}
 /*
 * Setup the local clock events for a CPU.
 */
-void __cpuinit local_timer_setup(void)
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        unsigned int cpu = smp_processor_id();
-        struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
-        unsigned long flags;
-        twd_calibrate_rate();
-        clk->name               = "local_timer";
-        clk->features           = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        clk->rating             = 350;
-        clk->set_mode           = local_timer_set_mode;
-        clk->set_next_event     = local_timer_set_next_event;
-        clk->irq                = IRQ_LOCALTIMER;
-        clk->cpumask            = cpumask_of(cpu);
-        clk->shift              = 20;
-        clk->mult               = div_sc(mpcore_timer_rate, NSEC_PER_SEC, clk->shift);
-        clk->max_delta_ns       = clockevent_delta2ns(0xffffffff, clk);
-        clk->min_delta_ns       = clockevent_delta2ns(0xf, clk);
-        /* Make sure our local interrupt controller has this enabled */
-        local_irq_save(flags);
-        get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER);
-        local_irq_restore(flags);
-        clockevents_register_device(clk);
-}
-/*
- * take a local timer down
- */
-void __cpuexit local_timer_stop(void)
 {
-        __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+        evt->irq = IRQ_LOCALTIMER;
+        twd_timer_setup(evt);
 }
-#else   /* CONFIG_LOCAL_TIMERS */
-static void dummy_timer_set_mode(enum clock_event_mode mode,
-                                 struct clock_event_device *clk)
-{
-}
-void __cpuinit local_timer_setup(void)
-{
-        unsigned int cpu = smp_processor_id();
-        struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
-        clk->name               = "dummy_timer";
-        clk->features           = CLOCK_EVT_FEAT_ONESHOT |
-                                  CLOCK_EVT_FEAT_PERIODIC |
-                                  CLOCK_EVT_FEAT_DUMMY;
-        clk->rating             = 400;
-        clk->mult               = 1;
-        clk->set_mode           = dummy_timer_set_mode;
-        clk->broadcast          = smp_timer_broadcast;
-        clk->cpumask            = cpumask_of(cpu);
-        clockevents_register_device(clk);
-}
-#endif  /* !CONFIG_LOCAL_TIMERS */
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 30a9c68591f6..ac0e83f1cc3a 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -19,10 +19,12 @@
 #include <asm/cacheflush.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
+#include <asm/localtimer.h>
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
-#include <mach/scu.h>
+#include <mach/board-pbx.h>
+#include <asm/smp_scu.h>
 #include "core.h"
@@ -40,35 +42,19 @@ static void __iomem *scu_base_addr(void)
                return __io_address(REALVIEW_EB11MP_SCU_BASE);
        else if (machine_is_realview_pb11mp())
                return __io_address(REALVIEW_TC11MP_SCU_BASE);
+        else if (machine_is_realview_pbx() &&
+                 (core_tile_pbx11mp() || core_tile_pbxa9mp()))
+                return __io_address(REALVIEW_PBX_TILE_SCU_BASE);
        else
                return (void __iomem *)0;
 }
-static unsigned int __init get_core_count(void)
+static inline unsigned int get_core_count(void)
 {
-        unsigned int ncores;
        void __iomem *scu_base = scu_base_addr();
+        if (scu_base)
-        if (scu_base) {
+                return scu_get_core_count(scu_base);
-                ncores = __raw_readl(scu_base + SCU_CONFIG);
+        return 1;
-                ncores = (ncores & 0x03) + 1;
-        } else
-                ncores = 1;
-        return ncores;
-}
-/*
- * Setup the SCU
- */
-static void scu_enable(void)
-{
-        u32 scu_ctrl;
-        void __iomem *scu_base = scu_base_addr();
-        scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
-        scu_ctrl |= 1;
-        __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
 }
 static DEFINE_SPINLOCK(boot_lock);
@@ -184,7 +170,7 @@ void __init smp_init_cpus(void)
        unsigned int i, ncores = get_core_count();
        for (i = 0; i < ncores; i++)
-                cpu_set(i, cpu_possible_map);
+                set_cpu_possible(i, true);
 }
 void __init smp_prepare_cpus(unsigned int max_cpus)
@@ -217,19 +203,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
        if (max_cpus > ncores)
                max_cpus = ncores;
-#if defined(CONFIG_LOCAL_TIMERS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
-        /*
-         * Enable the local timer or broadcast device for the boot CPU.
-         */
-        local_timer_setup();
-#endif
        /*
         * Initialise the present map, which describes the set of CPUs
         * actually populated at the present time.
         */
        for (i = 0; i < max_cpus; i++)
-                cpu_set(i, cpu_present_map);
+                set_cpu_present(i, true);
        /*
         * Initialise the SCU if there are more than one CPU and let
@@ -239,7 +218,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         * WFI
         */
        if (max_cpus > 1) {
-                scu_enable();
+                /*
+                 * Enable the local timer or broadcast device for the
+                 * boot CPU, but only if we have more than one CPU.
+                 */
+                percpu_timer_setup();
+                scu_enable(scu_base_addr());
                poke_milo();
        }
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index c20fbef122b3..8dfa44e08a94 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -32,6 +32,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/hardware/icst307.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/localtimer.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index a64b84a7a3df..25efe71a67c7 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -203,11 +203,23 @@ static struct amba_device *amba_devs[] __initdata = {
 /*
 * RealView PB1176 platform devices
 */
-static struct resource realview_pb1176_flash_resource = {
+static struct resource realview_pb1176_flash_resources[] = {
-        .start                  = REALVIEW_PB1176_FLASH_BASE,
+        [0] = {
-        .end                    = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
+                .start          = REALVIEW_PB1176_FLASH_BASE,
-        .flags                  = IORESOURCE_MEM,
+                .end            = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = REALVIEW_PB1176_SEC_FLASH_BASE,
+                .end            = REALVIEW_PB1176_SEC_FLASH_BASE + REALVIEW_PB1176_SEC_FLASH_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
 };
+#ifdef CONFIG_REALVIEW_PB1176_SECURE_FLASH
+#define PB1176_FLASH_BLOCKS     2
+#else
+#define PB1176_FLASH_BLOCKS     1
+#endif
 static struct resource realview_pb1176_smsc911x_resources[] = {
        [0] = {
@@ -271,7 +283,8 @@ static void __init realview_pb1176_init(void)
        l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
 #endif
-        realview_flash_register(&realview_pb1176_flash_resource, 1);
+        realview_flash_register(realview_pb1176_flash_resources,
+                                PB1176_FLASH_BLOCKS);
        realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
        platform_device_register(&realview_i2c_device);
        realview_usb_register(realview_pb1176_isp1761_resources);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index ea1e60eca359..dc4b16943907 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -32,6 +32,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/hardware/icst307.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/localtimer.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
new file mode 100644
index 000000000000..1fe294d0bf9d
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -0,0 +1,335 @@
+/*
+ *  arch/arm/mach-realview/realview_pbx.c
+ *
+ *  Copyright (C) 2009 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+#include <linux/io.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/board-pbx.h>
+#include <mach/irqs.h>
+#include "core.h"
+static struct map_desc realview_pbx_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_SYS_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SYS_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_SCTL_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SCTL_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_TIMER0_1_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_TIMER0_1_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_TIMER2_3_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_TIMER2_3_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+#ifdef CONFIG_PCI
+        {
+                .virtual        = PCIX_UNIT_BASE,
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_PCI_BASE),
+                .length         = REALVIEW_PBX_PCI_BASE_SIZE,
+                .type           = MT_DEVICE,
+        },
+#endif
+#ifdef CONFIG_DEBUG_LL
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_UART0_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_UART0_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+#endif
+};
+static struct map_desc realview_local_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_L220_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_L220_BASE),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        }
+};
+static void __init realview_pbx_map_io(void)
+{
+        iotable_init(realview_pbx_io_desc, ARRAY_SIZE(realview_pbx_io_desc));
+        if (core_tile_pbx11mp() || core_tile_pbxa9mp())
+                iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc));
+}
+/*
+ * RealView PBXCore AMBA devices
+ */
+#define GPIO2_IRQ               { IRQ_PBX_GPIO2, NO_IRQ }
+#define GPIO2_DMA               { 0, 0 }
+#define GPIO3_IRQ               { IRQ_PBX_GPIO3, NO_IRQ }
+#define GPIO3_DMA               { 0, 0 }
+#define AACI_IRQ                { IRQ_PBX_AACI, NO_IRQ }
+#define AACI_DMA                { 0x80, 0x81 }
+#define MMCI0_IRQ               { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
+#define MMCI0_DMA               { 0x84, 0 }
+#define KMI0_IRQ                { IRQ_PBX_KMI0, NO_IRQ }
+#define KMI0_DMA                { 0, 0 }
+#define KMI1_IRQ                { IRQ_PBX_KMI1, NO_IRQ }
+#define KMI1_DMA                { 0, 0 }
+#define PBX_SMC_IRQ             { NO_IRQ, NO_IRQ }
+#define PBX_SMC_DMA             { 0, 0 }
+#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
+#define MPMC_DMA                { 0, 0 }
+#define PBX_CLCD_IRQ            { IRQ_PBX_CLCD, NO_IRQ }
+#define PBX_CLCD_DMA            { 0, 0 }
+#define DMAC_IRQ                { IRQ_PBX_DMAC, NO_IRQ }
+#define DMAC_DMA                { 0, 0 }
+#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
+#define SCTL_DMA                { 0, 0 }
+#define PBX_WATCHDOG_IRQ        { IRQ_PBX_WATCHDOG, NO_IRQ }
+#define PBX_WATCHDOG_DMA        { 0, 0 }
+#define PBX_GPIO0_IRQ           { IRQ_PBX_GPIO0, NO_IRQ }
+#define PBX_GPIO0_DMA           { 0, 0 }
+#define GPIO1_IRQ               { IRQ_PBX_GPIO1, NO_IRQ }
+#define GPIO1_DMA               { 0, 0 }
+#define PBX_RTC_IRQ             { IRQ_PBX_RTC, NO_IRQ }
+#define PBX_RTC_DMA             { 0, 0 }
+#define SCI_IRQ                 { IRQ_PBX_SCI, NO_IRQ }
+#define SCI_DMA                 { 7, 6 }
+#define PBX_UART0_IRQ           { IRQ_PBX_UART0, NO_IRQ }
+#define PBX_UART0_DMA           { 15, 14 }
+#define PBX_UART1_IRQ           { IRQ_PBX_UART1, NO_IRQ }
+#define PBX_UART1_DMA           { 13, 12 }
+#define PBX_UART2_IRQ           { IRQ_PBX_UART2, NO_IRQ }
+#define PBX_UART2_DMA           { 11, 10 }
+#define PBX_UART3_IRQ           { IRQ_PBX_UART3, NO_IRQ }
+#define PBX_UART3_DMA           { 0x86, 0x87 }
+#define PBX_SSP_IRQ             { IRQ_PBX_SSP, NO_IRQ }
+#define PBX_SSP_DMA             { 9, 8 }
+/* FPGA Primecells */
+AMBA_DEVICE(aaci,       "fpga:04",      AACI,           NULL);
+AMBA_DEVICE(mmc0,       "fpga:05",      MMCI0,          &realview_mmc0_plat_data);
+AMBA_DEVICE(kmi0,       "fpga:06",      KMI0,           NULL);
+AMBA_DEVICE(kmi1,       "fpga:07",      KMI1,           NULL);
+AMBA_DEVICE(uart3,      "fpga:09",      PBX_UART3,      NULL);
+/* DevChip Primecells */
+AMBA_DEVICE(smc,        "dev:00",       PBX_SMC,        NULL);
+AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
+AMBA_DEVICE(wdog,       "dev:e1",       PBX_WATCHDOG,   NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PBX_GPIO0,      NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(rtc,        "dev:e8",       PBX_RTC,        NULL);
+AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
+AMBA_DEVICE(uart0,      "dev:f1",       PBX_UART0,      NULL);
+AMBA_DEVICE(uart1,      "dev:f2",       PBX_UART1,      NULL);
+AMBA_DEVICE(uart2,      "dev:f3",       PBX_UART2,      NULL);
+AMBA_DEVICE(ssp0,       "dev:f4",       PBX_SSP,        NULL);
+/* Primecells on the NEC ISSP chip */
+AMBA_DEVICE(clcd,       "issp:20",      PBX_CLCD,       &clcd_plat_data);
+AMBA_DEVICE(dmac,       "issp:30",      DMAC,           NULL);
+static struct amba_device *amba_devs[] __initdata = {
+        &dmac_device,
+        &uart0_device,
+        &uart1_device,
+        &uart2_device,
+        &uart3_device,
+        &smc_device,
+        &clcd_device,
+        &sctl_device,
+        &wdog_device,
+        &gpio0_device,
+        &gpio1_device,
+        &gpio2_device,
+        &rtc_device,
+        &sci0_device,
+        &ssp0_device,
+        &aaci_device,
+        &mmc0_device,
+        &kmi0_device,
+        &kmi1_device,
+};
+/*
+ * RealView PB-X platform devices
+ */
+static struct resource realview_pbx_flash_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PBX_FLASH0_BASE,
+                .end            = REALVIEW_PBX_FLASH0_BASE + REALVIEW_PBX_FLASH0_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = REALVIEW_PBX_FLASH1_BASE,
+                .end            = REALVIEW_PBX_FLASH1_BASE + REALVIEW_PBX_FLASH1_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct resource realview_pbx_smsc911x_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PBX_ETH_BASE,
+                .end            = REALVIEW_PBX_ETH_BASE + SZ_64K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_PBX_ETH,
+                .end            = IRQ_PBX_ETH,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct resource realview_pbx_isp1761_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PBX_USB_BASE,
+                .end            = REALVIEW_PBX_USB_BASE + SZ_128K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_PBX_USB,
+                .end            = IRQ_PBX_USB,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static void __init gic_init_irq(void)
+{
+        /* ARM PBX on-board GIC */
+        if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
+                gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
+                gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
+                              29);
+                gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
+        } else {
+                gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
+                gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
+                              IRQ_PBX_GIC_START);
+                gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
+        }
+}
+static void __init realview_pbx_timer_init(void)
+{
+        timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE);
+        timer1_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE) + 0x20;
+        timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
+        timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
+#ifdef CONFIG_LOCAL_TIMERS
+        if (core_tile_pbx11mp() || core_tile_pbxa9mp())
+                twd_base = __io_address(REALVIEW_PBX_TILE_TWD_BASE);
+#endif
+        realview_timer_init(IRQ_PBX_TIMER0_1);
+}
+static struct sys_timer realview_pbx_timer = {
+        .init           = realview_pbx_timer_init,
+};
+static void __init realview_pbx_init(void)
+{
+        int i;
+#ifdef CONFIG_CACHE_L2X0
+        if (core_tile_pbxa9mp()) {
+                void __iomem *l2x0_base =
+                        __io_address(REALVIEW_PBX_TILE_L220_BASE);
+                /* set RAM latencies to 1 cycle for eASIC */
+                writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+                writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
+                /* 16KB way size, 8-way associativity, parity disabled
+                 * Bits:  .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
+                l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
+        }
+#endif
+        realview_flash_register(realview_pbx_flash_resources,
+                                ARRAY_SIZE(realview_pbx_flash_resources));
+        realview_eth_register(NULL, realview_pbx_smsc911x_resources);
+        platform_device_register(&realview_i2c_device);
+        platform_device_register(&realview_cf_device);
+        realview_usb_register(realview_pbx_isp1761_resources);
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+#ifdef CONFIG_LEDS
+        leds_event = realview_leds_event;
+#endif
+}
+MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .phys_io        = REALVIEW_PBX_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x00000100,
+        .map_io         = realview_pbx_map_io,
+        .init_irq       = gic_init_irq,
+        .timer          = &realview_pbx_timer,
+        .init_machine   = realview_pbx_init,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
index 7a7ed4174c8c..6c68e78f3595 100644
--- a/arch/arm/mach-s3c2400/gpio.c
+++ b/arch/arm/mach-s3c2400/gpio.c
@@ -33,10 +33,10 @@
 int s3c2400_gpio_getirq(unsigned int pin)
 {
-        if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7)
+        if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
-                return -1;  /* not valid interrupts */
+                return -EINVAL;  /* not valid interrupts */
-        return (pin - S3C2410_GPE0) + IRQ_EINT0;
+        return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
 }
 EXPORT_SYMBOL(s3c2400_gpio_getirq);
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 63a30d1dd425..41bb65d5b91f 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -59,6 +59,7 @@ config ARCH_H1940
        bool "IPAQ H1940"
        select CPU_S3C2410
        select PM_H1940 if PM
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the HP IPAQ H1940
@@ -70,6 +71,7 @@ config PM_H1940
 config MACH_N30
        bool "Acer N30 family"
        select CPU_S3C2410
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you want suppt for the Acer N30, Acer N35,
          Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
@@ -82,6 +84,7 @@ config ARCH_BAST
        select MACH_BAST_IDE
        select S3C24XX_DCLK
        select ISA
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Simtec Electronics EB2410ITX
          development board (also known as BAST)
@@ -89,6 +92,7 @@ config ARCH_BAST
 config MACH_OTOM
        bool "NexVision OTOM Board"
        select CPU_S3C2410
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Nex Vision OTOM board
@@ -96,6 +100,7 @@ config MACH_AML_M5900
        bool "AML M5900 Series"
        select CPU_S3C2410
        select PM_SIMTEC if PM
+        select S3C_DEV_USB_HOST
        help
           Say Y here if you are using the American Microsystems M5900 Series
           <http://www.amltd.com>
@@ -111,6 +116,7 @@ config BAST_PC104_IRQ
 config MACH_TCT_HAMMER
        bool "TCT Hammer Board"
        select CPU_S3C2410
+        select S3C_DEV_USB_HOST
        help
           Say Y here if you are using the TinCanTools Hammer Board
           <http://www.tincantools.com>
@@ -122,12 +128,14 @@ config MACH_VR1000
        select SIMTEC_NOR
        select MACH_BAST_IDE
        select CPU_S3C2410
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Thorcom VR1000 board.
 config MACH_QT2410
        bool "QT2410"
        select CPU_S3C2410
+        select S3C_DEV_USB_HOST
        help
           Say Y here if you are using the Armzone QT2410
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 440c014e24b3..dbf96e60d992 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -17,14 +17,16 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
+#include <mach/map.h>
 #include <mach/dma.h>
 #include <plat/cpu.h>
-#include <plat/dma.h>
+#include <plat/dma-plat.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
+#include <plat/regs-dma.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 36a3132f39e7..7974afca297c 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
        unsigned long flags;
        unsigned long val;
-        if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
+        if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
-                return -1;
+                return -EINVAL;
        config &= 0xff;
-        pin -= S3C2410_GPG8;
+        pin -= S3C2410_GPG(8);
        reg += pin & ~3;
        local_irq_save(flags);
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 5a6bc56f186b..5aabf117cbb0 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -16,6 +16,8 @@
 #include <linux/string.h>
 #include <linux/ctype.h>
 #include <linux/leds.h>
+#include <linux/gpio.h>
 #include <mach/regs-gpio.h>
 #include <mach/hardware.h>
 #include <mach/h1940-latch.h>
@@ -41,9 +43,9 @@ static void h1940bt_enable(int on)
                h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
                /* Reset the chip */
                mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH1, 1);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH1, 0);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
                state = 1;
        }
@@ -52,9 +54,9 @@ static void h1940bt_enable(int on)
                led_trigger_event(bt_led_trigger, 0);
 #endif
-                s3c2410_gpio_setpin(S3C2410_GPH1, 1);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH1, 0);
+                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
                mdelay(10);
                h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
@@ -87,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
 static int __init h1940bt_probe(struct platform_device *pdev)
 {
        /* Configures BT serial port GPIOs */
-        s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
-        s3c2410_gpio_pullup(S3C2410_GPH0, 1);
+        s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_pullup(S3C2410_GPH1, 1);
+        s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH2, 1);
+        s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH3, 1);
+        s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
 #ifdef CONFIG_LEDS_H1940
        led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 13358ce2128c..c3a2629e0ded 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -3,7 +3,7 @@
 * Copyright (C) 2003,2004,2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
- * Samsung S3C241XX DMA support
+ * Samsung S3C24XX DMA support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -13,8 +13,8 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
+#include <plat/dma.h>
 #include <linux/sysdev.h>
-#include <mach/hardware.h>
 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
@@ -55,9 +55,9 @@ enum dma_ch {
 /* we have 4 dma channels */
 #ifndef CONFIG_CPU_S3C2443
-#define S3C2410_DMA_CHANNELS            (4)
+#define S3C_DMA_CHANNELS                (4)
 #else
-#define S3C2410_DMA_CHANNELS            (6)
+#define S3C_DMA_CHANNELS                (6)
 #endif
 /* types */
@@ -68,7 +68,6 @@ enum s3c2410_dma_state {
        S3C2410_DMA_PAUSED
 };
 /* enum s3c2410_dma_loadst
 *
 * This represents the state of the DMA engine, wrt to the loaded / running
@@ -104,32 +103,6 @@ enum s3c2410_dma_loadst {
        S3C2410_DMALOAD_1LOADED_1RUNNING,
 };
-enum s3c2410_dma_buffresult {
-        S3C2410_RES_OK,
-        S3C2410_RES_ERR,
-        S3C2410_RES_ABORT
-};
-enum s3c2410_dmasrc {
-        S3C2410_DMASRC_HW,              /* source is memory */
-        S3C2410_DMASRC_MEM              /* source is hardware */
-};
-/* enum s3c2410_chan_op
- *
- * operation codes passed to the DMA code by the user, and also used
- * to inform the current channel owner of any changes to the system state
-*/
-enum s3c2410_chan_op {
-        S3C2410_DMAOP_START,
-        S3C2410_DMAOP_STOP,
-        S3C2410_DMAOP_PAUSE,
-        S3C2410_DMAOP_RESUME,
-        S3C2410_DMAOP_FLUSH,
-        S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
-        S3C2410_DMAOP_STARTED,          /* indicate channel started */
-};
 /* flags */
@@ -139,17 +112,14 @@ enum s3c2410_chan_op {
 /* dma buffer */
-struct s3c2410_dma_client {
+struct s3c2410_dma_buf;
-        char                *name;
-};
-/* s3c2410_dma_buf_s
+/* s3c2410_dma_buf
 *
 * internally used buffer structure to describe a queued or running
 * buffer.
 */
-struct s3c2410_dma_buf;
 struct s3c2410_dma_buf {
        struct s3c2410_dma_buf  *next;
        int                      magic;         /* magic */
@@ -161,20 +131,6 @@ struct s3c2410_dma_buf {
 /* [1] is this updated for both recv/send modes? */
-struct s3c2410_dma_chan;
-/* s3c2410_dma_cbfn_t
- *
- * buffer callback routine type
-*/
-typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
-                                   void *buf, int size,
-                                   enum s3c2410_dma_buffresult result);
-typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
-                                   enum s3c2410_chan_op );
 struct s3c2410_dma_stats {
        unsigned long           loads;
        unsigned long           timeout_longest;
@@ -206,10 +162,10 @@ struct s3c2410_dma_chan {
        /* channel configuration */
        enum s3c2410_dmasrc      source;
+        enum dma_ch              req_ch;
        unsigned long            dev_addr;
        unsigned long            load_timeout;
        unsigned int             flags;         /* channel flags */
-        unsigned int             hw_cfg;        /* last hw config */
        struct s3c24xx_dma_map  *map;           /* channel hw maps */
@@ -236,213 +192,6 @@ struct s3c2410_dma_chan {
        struct sys_device       dev;
 };
-/* the currently allocated channel information */
-extern struct s3c2410_dma_chan s3c2410_chans[];
-/* note, we don't really use dma_device_t at the moment */
 typedef unsigned long dma_device_t;
-/* functions --------------------------------------------------------------- */
-/* s3c2410_dma_request
- *
- * request a dma channel exclusivley
-*/
-extern int s3c2410_dma_request(unsigned int channel,
-                               struct s3c2410_dma_client *, void *dev);
-/* s3c2410_dma_ctrl
- *
- * change the state of the dma channel
-*/
-extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
-/* s3c2410_dma_setflags
- *
- * set the channel's flags to a given state
-*/
-extern int s3c2410_dma_setflags(unsigned int channel,
-                                unsigned int flags);
-/* s3c2410_dma_free
- *
- * free the dma channel (will also abort any outstanding operations)
-*/
-extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
-/* s3c2410_dma_enqueue
- *
- * place the given buffer onto the queue of operations for the channel.
- * The buffer must be allocated from dma coherent memory, or the Dcache/WB
- * drained before the buffer is given to the DMA system.
-*/
-extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
-                               dma_addr_t data, int size);
-/* s3c2410_dma_config
- *
- * configure the dma channel
-*/
-extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
-/* s3c2410_dma_devconfig
- *
- * configure the device we're talking to
-*/
-extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
-                                 int hwcfg, unsigned long devaddr);
-/* s3c2410_dma_getposition
- *
- * get the position that the dma transfer is currently at
-*/
-extern int s3c2410_dma_getposition(unsigned int channel,
-                                   dma_addr_t *src, dma_addr_t *dest);
-extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
-extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
-/* DMA Register definitions */
-#define S3C2410_DMA_DISRC       (0x00)
-#define S3C2410_DMA_DISRCC      (0x04)
-#define S3C2410_DMA_DIDST       (0x08)
-#define S3C2410_DMA_DIDSTC      (0x0C)
-#define S3C2410_DMA_DCON        (0x10)
-#define S3C2410_DMA_DSTAT       (0x14)
-#define S3C2410_DMA_DCSRC       (0x18)
-#define S3C2410_DMA_DCDST       (0x1C)
-#define S3C2410_DMA_DMASKTRIG   (0x20)
-#define S3C2412_DMA_DMAREQSEL   (0x24)
-#define S3C2443_DMA_DMAREQSEL   (0x24)
-#define S3C2410_DISRCC_INC      (1<<0)
-#define S3C2410_DISRCC_APB      (1<<1)
-#define S3C2410_DMASKTRIG_STOP   (1<<2)
-#define S3C2410_DMASKTRIG_ON     (1<<1)
-#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
-#define S3C2410_DCON_DEMAND     (0<<31)
-#define S3C2410_DCON_HANDSHAKE  (1<<31)
-#define S3C2410_DCON_SYNC_PCLK  (0<<30)
-#define S3C2410_DCON_SYNC_HCLK  (1<<30)
-#define S3C2410_DCON_INTREQ     (1<<29)
-#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
-#define S3C2410_DCON_CH0_UART0  (1<<24)
-#define S3C2410_DCON_CH0_SDI    (2<<24)
-#define S3C2410_DCON_CH0_TIMER  (3<<24)
-#define S3C2410_DCON_CH0_USBEP1 (4<<24)
-#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
-#define S3C2410_DCON_CH1_UART1  (1<<24)
-#define S3C2410_DCON_CH1_I2SSDI (2<<24)
-#define S3C2410_DCON_CH1_SPI    (3<<24)
-#define S3C2410_DCON_CH1_USBEP2 (4<<24)
-#define S3C2410_DCON_CH2_I2SSDO (0<<24)
-#define S3C2410_DCON_CH2_I2SSDI (1<<24)
-#define S3C2410_DCON_CH2_SDI    (2<<24)
-#define S3C2410_DCON_CH2_TIMER  (3<<24)
-#define S3C2410_DCON_CH2_USBEP3 (4<<24)
-#define S3C2410_DCON_CH3_UART2  (0<<24)
-#define S3C2410_DCON_CH3_SDI    (1<<24)
-#define S3C2410_DCON_CH3_SPI    (2<<24)
-#define S3C2410_DCON_CH3_TIMER  (3<<24)
-#define S3C2410_DCON_CH3_USBEP4 (4<<24)
-#define S3C2410_DCON_SRCSHIFT   (24)
-#define S3C2410_DCON_SRCMASK    (7<<24)
-#define S3C2410_DCON_BYTE       (0<<20)
-#define S3C2410_DCON_HALFWORD   (1<<20)
-#define S3C2410_DCON_WORD       (2<<20)
-#define S3C2410_DCON_AUTORELOAD (0<<22)
-#define S3C2410_DCON_NORELOAD   (1<<22)
-#define S3C2410_DCON_HWTRIG     (1<<23)
-#ifdef CONFIG_CPU_S3C2440
-#define S3C2440_DIDSTC_CHKINT   (1<<2)
-#define S3C2440_DCON_CH0_I2SSDO (5<<24)
-#define S3C2440_DCON_CH0_PCMIN  (6<<24)
-#define S3C2440_DCON_CH1_PCMOUT (5<<24)
-#define S3C2440_DCON_CH1_SDI    (6<<24)
-#define S3C2440_DCON_CH2_PCMIN  (5<<24)
-#define S3C2440_DCON_CH2_MICIN  (6<<24)
-#define S3C2440_DCON_CH3_MICIN  (5<<24)
-#define S3C2440_DCON_CH3_PCMOUT (6<<24)
-#endif
-#ifdef CONFIG_CPU_S3C2412
-#define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
-#define S3C2412_DMAREQSEL_HW            (1)
-#define S3C2412_DMAREQSEL_SPI0TX        S3C2412_DMAREQSEL_SRC(0)
-#define S3C2412_DMAREQSEL_SPI0RX        S3C2412_DMAREQSEL_SRC(1)
-#define S3C2412_DMAREQSEL_SPI1TX        S3C2412_DMAREQSEL_SRC(2)
-#define S3C2412_DMAREQSEL_SPI1RX        S3C2412_DMAREQSEL_SRC(3)
-#define S3C2412_DMAREQSEL_I2STX         S3C2412_DMAREQSEL_SRC(4)
-#define S3C2412_DMAREQSEL_I2SRX         S3C2412_DMAREQSEL_SRC(5)
-#define S3C2412_DMAREQSEL_TIMER         S3C2412_DMAREQSEL_SRC(9)
-#define S3C2412_DMAREQSEL_SDI           S3C2412_DMAREQSEL_SRC(10)
-#define S3C2412_DMAREQSEL_USBEP1        S3C2412_DMAREQSEL_SRC(13)
-#define S3C2412_DMAREQSEL_USBEP2        S3C2412_DMAREQSEL_SRC(14)
-#define S3C2412_DMAREQSEL_USBEP3        S3C2412_DMAREQSEL_SRC(15)
-#define S3C2412_DMAREQSEL_USBEP4        S3C2412_DMAREQSEL_SRC(16)
-#define S3C2412_DMAREQSEL_XDREQ0        S3C2412_DMAREQSEL_SRC(17)
-#define S3C2412_DMAREQSEL_XDREQ1        S3C2412_DMAREQSEL_SRC(18)
-#define S3C2412_DMAREQSEL_UART0_0       S3C2412_DMAREQSEL_SRC(19)
-#define S3C2412_DMAREQSEL_UART0_1       S3C2412_DMAREQSEL_SRC(20)
-#define S3C2412_DMAREQSEL_UART1_0       S3C2412_DMAREQSEL_SRC(21)
-#define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
-#define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
-#define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
-#endif
-#define S3C2443_DMAREQSEL_SRC(x)        ((x)<<1)
-#define S3C2443_DMAREQSEL_HW            (1)
-#define S3C2443_DMAREQSEL_SPI0TX        S3C2443_DMAREQSEL_SRC(0)
-#define S3C2443_DMAREQSEL_SPI0RX        S3C2443_DMAREQSEL_SRC(1)
-#define S3C2443_DMAREQSEL_SPI1TX        S3C2443_DMAREQSEL_SRC(2)
-#define S3C2443_DMAREQSEL_SPI1RX        S3C2443_DMAREQSEL_SRC(3)
-#define S3C2443_DMAREQSEL_I2STX         S3C2443_DMAREQSEL_SRC(4)
-#define S3C2443_DMAREQSEL_I2SRX         S3C2443_DMAREQSEL_SRC(5)
-#define S3C2443_DMAREQSEL_TIMER         S3C2443_DMAREQSEL_SRC(9)
-#define S3C2443_DMAREQSEL_SDI           S3C2443_DMAREQSEL_SRC(10)
-#define S3C2443_DMAREQSEL_XDREQ0        S3C2443_DMAREQSEL_SRC(17)
-#define S3C2443_DMAREQSEL_XDREQ1        S3C2443_DMAREQSEL_SRC(18)
-#define S3C2443_DMAREQSEL_UART0_0       S3C2443_DMAREQSEL_SRC(19)
-#define S3C2443_DMAREQSEL_UART0_1       S3C2443_DMAREQSEL_SRC(20)
-#define S3C2443_DMAREQSEL_UART1_0       S3C2443_DMAREQSEL_SRC(21)
-#define S3C2443_DMAREQSEL_UART1_1       S3C2443_DMAREQSEL_SRC(22)
-#define S3C2443_DMAREQSEL_UART2_0       S3C2443_DMAREQSEL_SRC(23)
-#define S3C2443_DMAREQSEL_UART2_1       S3C2443_DMAREQSEL_SRC(24)
-#define S3C2443_DMAREQSEL_UART3_0       S3C2443_DMAREQSEL_SRC(25)
-#define S3C2443_DMAREQSEL_UART3_1       S3C2443_DMAREQSEL_SRC(26)
-#define S3C2443_DMAREQSEL_PCMOUT        S3C2443_DMAREQSEL_SRC(27)
-#define S3C2443_DMAREQSEL_PCMIN         S3C2443_DMAREQSEL_SRC(28)
-#define S3C2443_DMAREQSEL_MICIN         S3C2443_DMAREQSEL_SRC(29)
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
index 6c9fbb99ef14..8fe192081d3a 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
 {
        struct s3c_gpio_chip *chip;
-        if (pin > S3C2410_GPG10)
+        if (pin > S3C2410_GPG(10))
                return NULL;
        chip = &s3c24xx_gpios[pin/32];
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
new file mode 100644
index 000000000000..801dff13858d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -0,0 +1,103 @@
+/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+ *
+ * Copyright (c) 2003,2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* These functions are in the to-be-removed category and it is strongly
+ * encouraged not to use these in new code. They will be marked deprecated
+ * very soon.
+ *
+ * Most of the functionality can be either replaced by the gpiocfg calls
+ * for the s3c platform or by the generic GPIOlib API.
+*/
+/* external functions for GPIO support
+ *
+ * These allow various different clients to access the same GPIO
+ * registers without conflicting. If your driver only owns the entire
+ * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
+*/
+/* s3c2410_gpio_cfgpin
+ *
+ * set the configuration of the given pin to the value passed.
+ *
+ * eg:
+ *    s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
+ *    s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
+*/
+extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
+extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
+/* s3c2410_gpio_getirq
+ *
+ * turn the given pin number into the corresponding IRQ number
+ *
+ * returns:
+ *      < 0 = no interrupt for this pin
+ *      >=0 = interrupt number for the pin
+*/
+extern int s3c2410_gpio_getirq(unsigned int pin);
+#ifdef CONFIG_CPU_S3C2400
+extern int s3c2400_gpio_getirq(unsigned int pin);
+#endif /* CONFIG_CPU_S3C2400 */
+/* s3c2410_gpio_irqfilter
+ *
+ * set the irq filtering on the given pin
+ *
+ * on = 0 => disable filtering
+ *      1 => enable filtering
+ *
+ * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
+ *          width of filter (0 through 63)
+ *
+ *
+*/
+extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
+                                  unsigned int config);
+/* s3c2410_gpio_pullup
+ *
+ * configure the pull-up control on the given pin
+ *
+ * to = 1 => disable the pull-up
+ *      0 => enable the pull-up
+ *
+ * eg;
+ *
+ *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
+ *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
+*/
+extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+/* s3c2410_gpio_getpull
+ *
+ * Read the state of the pull-up on a given pin
+ *
+ * return:
+ *      < 0 => error code
+ *        0 => enabled
+ *        1 => disabled
+*/
+extern int s3c2410_gpio_getpull(unsigned int pin);
+extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index ce1ec69806a1..2edbb9c88ab3 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -11,6 +11,9 @@
 * published by the Free Software Foundation.
 */
+#ifndef __MACH_GPIONRS_H
+#define __MACH_GPIONRS_H
 #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
 #define S3C2410_GPIO_BANKA   (32*0)
@@ -21,3 +24,70 @@
 #define S3C2410_GPIO_BANKF   (32*5)
 #define S3C2410_GPIO_BANKG   (32*6)
 #define S3C2410_GPIO_BANKH   (32*7)
+/* GPIO bank sizes */
+#define S3C2410_GPIO_A_NR       (32)
+#define S3C2410_GPIO_B_NR       (32)
+#define S3C2410_GPIO_C_NR       (32)
+#define S3C2410_GPIO_D_NR       (32)
+#define S3C2410_GPIO_E_NR       (32)
+#define S3C2410_GPIO_F_NR       (32)
+#define S3C2410_GPIO_G_NR       (32)
+#define S3C2410_GPIO_H_NR       (32)
+#if CONFIG_S3C_GPIO_SPACE != 0
+#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
+#endif
+#define S3C2410_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
+#ifndef __ASSEMBLY__
+enum s3c_gpio_number {
+        S3C2410_GPIO_A_START = 0,
+        S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
+        S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
+        S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
+        S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
+        S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
+        S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
+        S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
+};
+#endif /* __ASSEMBLY__ */
+/* S3C2410 GPIO number definitions. */
+#define S3C2410_GPA(_nr)        (S3C2410_GPIO_A_START + (_nr))
+#define S3C2410_GPB(_nr)        (S3C2410_GPIO_B_START + (_nr))
+#define S3C2410_GPC(_nr)        (S3C2410_GPIO_C_START + (_nr))
+#define S3C2410_GPD(_nr)        (S3C2410_GPIO_D_START + (_nr))
+#define S3C2410_GPE(_nr)        (S3C2410_GPIO_E_START + (_nr))
+#define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
+#define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
+#define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
+/* compatibility until drivers can be modified */
+#define S3C2410_GPA0    S3C2410_GPA(0)
+#define S3C2410_GPA1    S3C2410_GPA(1)
+#define S3C2410_GPA3    S3C2410_GPA(3)
+#define S3C2410_GPA7    S3C2410_GPA(7)
+#define S3C2410_GPE0    S3C2410_GPE(0)
+#define S3C2410_GPE1    S3C2410_GPE(1)
+#define S3C2410_GPE2    S3C2410_GPE(2)
+#define S3C2410_GPE3    S3C2410_GPE(3)
+#define S3C2410_GPE4    S3C2410_GPE(4)
+#define S3C2410_GPE5    S3C2410_GPE(5)
+#define S3C2410_GPE6    S3C2410_GPE(6)
+#define S3C2410_GPE7    S3C2410_GPE(7)
+#define S3C2410_GPE8    S3C2410_GPE(8)
+#define S3C2410_GPE9    S3C2410_GPE(9)
+#define S3C2410_GPE10   S3C2410_GPE(10)
+#define S3C2410_GPH10   S3C2410_GPH(10)
+#endif /* __MACH_GPIONRS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index 51a88cf9526b..15f0b3e7ce69 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -24,5 +24,6 @@
 #include <asm-generic/gpio.h>
 #include <mach/gpio-nrs.h>
+#include <mach/gpio-fns.h>
 #define S3C_GPIO_END    (S3C2410_GPIO_BANKH + 32)
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h
index 74d5a1a4024c..aef5631eac58 100644
--- a/arch/arm/mach-s3c2410/include/mach/hardware.h
+++ b/arch/arm/mach-s3c2410/include/mach/hardware.h
@@ -15,101 +15,6 @@
 #ifndef __ASSEMBLY__
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-/* s3c2410_gpio_cfgpin
- *
- * set the configuration of the given pin to the value passed.
- *
- * eg:
- *    s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
- *    s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
-*/
-extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *      < 0 = no interrupt for this pin
- *      >=0 = interrupt number for the pin
-*/
-extern int s3c2410_gpio_getirq(unsigned int pin);
-/* s3c2410_gpio_irq2pin
- *
- * turn the given irq number into the corresponding GPIO number
- *
- * returns:
- *      < 0 = no pin
- *      >=0 = gpio pin number
-*/
-extern int s3c2410_gpio_irq2pin(unsigned int irq);
-#ifdef CONFIG_CPU_S3C2400
-extern int s3c2400_gpio_getirq(unsigned int pin);
-#endif /* CONFIG_CPU_S3C2400 */
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                  unsigned int config);
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB0, 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE8, 0);
-*/
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-/* s3c2410_gpio_getpull
- *
- * Read the state of the pull-up on a given pin
- *
- * return:
- *      < 0 => error code
- *        0 => enabled
- *        1 => disabled
-*/
-extern int s3c2410_gpio_getpull(unsigned int pin);
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
 extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
 #ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 255fdfeaf957..e99b212cb1ca 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -84,7 +84,6 @@
 #define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
 #define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
 #define S3C24XX_PA_DMA      S3C2410_PA_DMA
 #define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
 #define S3C24XX_PA_LCD      S3C2410_PA_LCD
@@ -102,6 +101,7 @@
 #define S3C_PA_IIC          S3C2410_PA_IIC
 #define S3C_PA_UART         S3C24XX_PA_UART
+#define S3C_PA_USBHOST  S3C2410_PA_USBHOST
 #define S3C_PA_HSMMC0       S3C2443_PA_HSMMC
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 35a03df473fc..b278d0c45ccf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -69,104 +69,58 @@
 #define S3C2400_GPACON     S3C2410_GPIOREG(0x00)
 #define S3C2400_GPADAT     S3C2410_GPIOREG(0x04)
-#define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
-#define S3C2410_GPA0_OUT     (0<<0)
 #define S3C2410_GPA0_ADDR0   (1<<0)
-#define S3C2410_GPA1         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
-#define S3C2410_GPA1_OUT     (0<<1)
 #define S3C2410_GPA1_ADDR16  (1<<1)
-#define S3C2410_GPA2         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
-#define S3C2410_GPA2_OUT     (0<<2)
 #define S3C2410_GPA2_ADDR17  (1<<2)
-#define S3C2410_GPA3         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
-#define S3C2410_GPA3_OUT     (0<<3)
 #define S3C2410_GPA3_ADDR18  (1<<3)
-#define S3C2410_GPA4         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
-#define S3C2410_GPA4_OUT     (0<<4)
 #define S3C2410_GPA4_ADDR19  (1<<4)
-#define S3C2410_GPA5         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
-#define S3C2410_GPA5_OUT     (0<<5)
 #define S3C2410_GPA5_ADDR20  (1<<5)
-#define S3C2410_GPA6         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
-#define S3C2410_GPA6_OUT     (0<<6)
 #define S3C2410_GPA6_ADDR21  (1<<6)
-#define S3C2410_GPA7         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
-#define S3C2410_GPA7_OUT     (0<<7)
 #define S3C2410_GPA7_ADDR22  (1<<7)
-#define S3C2410_GPA8         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
-#define S3C2410_GPA8_OUT     (0<<8)
 #define S3C2410_GPA8_ADDR23  (1<<8)
-#define S3C2410_GPA9         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
-#define S3C2410_GPA9_OUT     (0<<9)
 #define S3C2410_GPA9_ADDR24  (1<<9)
-#define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
-#define S3C2410_GPA10_OUT    (0<<10)
 #define S3C2410_GPA10_ADDR25 (1<<10)
 #define S3C2400_GPA10_SCKE   (1<<10)
-#define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
-#define S3C2410_GPA11_OUT    (0<<11)
 #define S3C2410_GPA11_ADDR26 (1<<11)
 #define S3C2400_GPA11_nCAS0  (1<<11)
-#define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
-#define S3C2410_GPA12_OUT    (0<<12)
 #define S3C2410_GPA12_nGCS1  (1<<12)
 #define S3C2400_GPA12_nCAS1  (1<<12)
-#define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
-#define S3C2410_GPA13_OUT    (0<<13)
 #define S3C2410_GPA13_nGCS2  (1<<13)
 #define S3C2400_GPA13_nGCS1  (1<<13)
-#define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
-#define S3C2410_GPA14_OUT    (0<<14)
 #define S3C2410_GPA14_nGCS3  (1<<14)
 #define S3C2400_GPA14_nGCS2  (1<<14)
-#define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
-#define S3C2410_GPA15_OUT    (0<<15)
 #define S3C2410_GPA15_nGCS4  (1<<15)
 #define S3C2400_GPA15_nGCS3  (1<<15)
-#define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
-#define S3C2410_GPA16_OUT    (0<<16)
 #define S3C2410_GPA16_nGCS5  (1<<16)
 #define S3C2400_GPA16_nGCS4  (1<<16)
-#define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
-#define S3C2410_GPA17_OUT    (0<<17)
 #define S3C2410_GPA17_CLE    (1<<17)
 #define S3C2400_GPA17_nGCS5  (1<<17)
-#define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
-#define S3C2410_GPA18_OUT    (0<<18)
 #define S3C2410_GPA18_ALE    (1<<18)
-#define S3C2410_GPA19        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
-#define S3C2410_GPA19_OUT    (0<<19)
 #define S3C2410_GPA19_nFWE   (1<<19)
-#define S3C2410_GPA20        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
-#define S3C2410_GPA20_OUT    (0<<20)
 #define S3C2410_GPA20_nFRE   (1<<20)
-#define S3C2410_GPA21        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
-#define S3C2410_GPA21_OUT    (0<<21)
 #define S3C2410_GPA21_nRSTOUT (1<<21)
-#define S3C2410_GPA22        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
-#define S3C2410_GPA22_OUT    (0<<22)
 #define S3C2410_GPA22_nFCE   (1<<22)
 /* 0x08 and 0x0c are reserved on S3C2410 */
@@ -194,107 +148,69 @@
 /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
-#define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
-#define S3C2410_GPB0_INP     (0x00 << 0)
-#define S3C2410_GPB0_OUTP    (0x01 << 0)
 #define S3C2410_GPB0_TOUT0   (0x02 << 0)
 #define S3C2400_GPB0_DATA16  (0x02 << 0)
-#define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
-#define S3C2410_GPB1_INP     (0x00 << 2)
-#define S3C2410_GPB1_OUTP    (0x01 << 2)
 #define S3C2410_GPB1_TOUT1   (0x02 << 2)
 #define S3C2400_GPB1_DATA17  (0x02 << 2)
-#define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
-#define S3C2410_GPB2_INP     (0x00 << 4)
-#define S3C2410_GPB2_OUTP    (0x01 << 4)
 #define S3C2410_GPB2_TOUT2   (0x02 << 4)
 #define S3C2400_GPB2_DATA18  (0x02 << 4)
 #define S3C2400_GPB2_TCLK1   (0x03 << 4)
-#define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
-#define S3C2410_GPB3_INP     (0x00 << 6)
-#define S3C2410_GPB3_OUTP    (0x01 << 6)
 #define S3C2410_GPB3_TOUT3   (0x02 << 6)
 #define S3C2400_GPB3_DATA19  (0x02 << 6)
 #define S3C2400_GPB3_TXD1    (0x03 << 6)
-#define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
-#define S3C2410_GPB4_INP     (0x00 << 8)
-#define S3C2410_GPB4_OUTP    (0x01 << 8)
 #define S3C2410_GPB4_TCLK0   (0x02 << 8)
 #define S3C2400_GPB4_DATA20  (0x02 << 8)
 #define S3C2410_GPB4_MASK    (0x03 << 8)
 #define S3C2400_GPB4_RXD1    (0x03 << 8)
 #define S3C2400_GPB4_MASK    (0x03 << 8)
-#define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
-#define S3C2410_GPB5_INP     (0x00 << 10)
-#define S3C2410_GPB5_OUTP    (0x01 << 10)
 #define S3C2410_GPB5_nXBACK  (0x02 << 10)
 #define S3C2443_GPB5_XBACK   (0x03 << 10)
 #define S3C2400_GPB5_DATA21  (0x02 << 10)
 #define S3C2400_GPB5_nCTS1   (0x03 << 10)
-#define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
-#define S3C2410_GPB6_INP     (0x00 << 12)
-#define S3C2410_GPB6_OUTP    (0x01 << 12)
 #define S3C2410_GPB6_nXBREQ  (0x02 << 12)
 #define S3C2443_GPB6_XBREQ   (0x03 << 12)
 #define S3C2400_GPB6_DATA22  (0x02 << 12)
 #define S3C2400_GPB6_nRTS1   (0x03 << 12)
-#define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
-#define S3C2410_GPB7_INP     (0x00 << 14)
-#define S3C2410_GPB7_OUTP    (0x01 << 14)
 #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
 #define S3C2443_GPB7_XDACK1  (0x03 << 14)
 #define S3C2400_GPB7_DATA23  (0x02 << 14)
-#define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
-#define S3C2410_GPB8_INP     (0x00 << 16)
-#define S3C2410_GPB8_OUTP    (0x01 << 16)
 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
 #define S3C2400_GPB8_DATA24  (0x02 << 16)
-#define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
-#define S3C2410_GPB9_INP     (0x00 << 18)
-#define S3C2410_GPB9_OUTP    (0x01 << 18)
 #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
 #define S3C2443_GPB9_XDACK0  (0x03 << 18)
 #define S3C2400_GPB9_DATA25  (0x02 << 18)
 #define S3C2400_GPB9_I2SSDI  (0x03 << 18)
-#define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
-#define S3C2410_GPB10_INP    (0x00 << 20)
-#define S3C2410_GPB10_OUTP   (0x01 << 20)
 #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
 #define S3C2443_GPB10_XDREQ0 (0x03 << 20)
 #define S3C2400_GPB10_DATA26 (0x02 << 20)
 #define S3C2400_GPB10_nSS    (0x03 << 20)
-#define S3C2400_GPB11        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
 #define S3C2400_GPB11_INP    (0x00 << 22)
 #define S3C2400_GPB11_OUTP   (0x01 << 22)
 #define S3C2400_GPB11_DATA27 (0x02 << 22)
-#define S3C2400_GPB12        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
 #define S3C2400_GPB12_INP    (0x00 << 24)
 #define S3C2400_GPB12_OUTP   (0x01 << 24)
 #define S3C2400_GPB12_DATA28 (0x02 << 24)
-#define S3C2400_GPB13        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
 #define S3C2400_GPB13_INP    (0x00 << 26)
 #define S3C2400_GPB13_OUTP   (0x01 << 26)
 #define S3C2400_GPB13_DATA29 (0x02 << 26)
-#define S3C2400_GPB14        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
 #define S3C2400_GPB14_INP    (0x00 << 28)
 #define S3C2400_GPB14_OUTP   (0x01 << 28)
 #define S3C2400_GPB14_DATA30 (0x02 << 28)
-#define S3C2400_GPB15        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
 #define S3C2400_GPB15_INP    (0x00 << 30)
 #define S3C2400_GPB15_OUTP   (0x01 << 30)
 #define S3C2400_GPB15_DATA31 (0x02 << 30)
@@ -315,99 +231,51 @@
 #define S3C2400_GPCDAT     S3C2410_GPIOREG(0x18)
 #define S3C2400_GPCUP      S3C2410_GPIOREG(0x1C)
-#define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
-#define S3C2410_GPC0_INP        (0x00 << 0)
-#define S3C2410_GPC0_OUTP       (0x01 << 0)
 #define S3C2410_GPC0_LEND       (0x02 << 0)
 #define S3C2400_GPC0_VD0        (0x02 << 0)
-#define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
-#define S3C2410_GPC1_INP        (0x00 << 2)
-#define S3C2410_GPC1_OUTP       (0x01 << 2)
 #define S3C2410_GPC1_VCLK       (0x02 << 2)
 #define S3C2400_GPC1_VD1        (0x02 << 2)
-#define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
-#define S3C2410_GPC2_INP        (0x00 << 4)
-#define S3C2410_GPC2_OUTP       (0x01 << 4)
 #define S3C2410_GPC2_VLINE      (0x02 << 4)
 #define S3C2400_GPC2_VD2        (0x02 << 4)
-#define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
-#define S3C2410_GPC3_INP        (0x00 << 6)
-#define S3C2410_GPC3_OUTP       (0x01 << 6)
 #define S3C2410_GPC3_VFRAME     (0x02 << 6)
 #define S3C2400_GPC3_VD3        (0x02 << 6)
-#define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
-#define S3C2410_GPC4_INP        (0x00 << 8)
-#define S3C2410_GPC4_OUTP       (0x01 << 8)
 #define S3C2410_GPC4_VM         (0x02 << 8)
 #define S3C2400_GPC4_VD4        (0x02 << 8)
-#define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
-#define S3C2410_GPC5_INP        (0x00 << 10)
-#define S3C2410_GPC5_OUTP       (0x01 << 10)
 #define S3C2410_GPC5_LCDVF0     (0x02 << 10)
 #define S3C2400_GPC5_VD5        (0x02 << 10)
-#define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
-#define S3C2410_GPC6_INP        (0x00 << 12)
-#define S3C2410_GPC6_OUTP       (0x01 << 12)
 #define S3C2410_GPC6_LCDVF1     (0x02 << 12)
 #define S3C2400_GPC6_VD6        (0x02 << 12)
-#define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
-#define S3C2410_GPC7_INP        (0x00 << 14)
-#define S3C2410_GPC7_OUTP       (0x01 << 14)
 #define S3C2410_GPC7_LCDVF2     (0x02 << 14)
 #define S3C2400_GPC7_VD7        (0x02 << 14)
-#define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
-#define S3C2410_GPC8_INP        (0x00 << 16)
-#define S3C2410_GPC8_OUTP       (0x01 << 16)
 #define S3C2410_GPC8_VD0        (0x02 << 16)
 #define S3C2400_GPC8_VD8        (0x02 << 16)
-#define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
-#define S3C2410_GPC9_INP        (0x00 << 18)
-#define S3C2410_GPC9_OUTP       (0x01 << 18)
 #define S3C2410_GPC9_VD1        (0x02 << 18)
 #define S3C2400_GPC9_VD9        (0x02 << 18)
-#define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
-#define S3C2410_GPC10_INP       (0x00 << 20)
-#define S3C2410_GPC10_OUTP      (0x01 << 20)
 #define S3C2410_GPC10_VD2       (0x02 << 20)
 #define S3C2400_GPC10_VD10      (0x02 << 20)
-#define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
-#define S3C2410_GPC11_INP       (0x00 << 22)
-#define S3C2410_GPC11_OUTP      (0x01 << 22)
 #define S3C2410_GPC11_VD3       (0x02 << 22)
 #define S3C2400_GPC11_VD11      (0x02 << 22)
-#define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
-#define S3C2410_GPC12_INP       (0x00 << 24)
-#define S3C2410_GPC12_OUTP      (0x01 << 24)
 #define S3C2410_GPC12_VD4       (0x02 << 24)
 #define S3C2400_GPC12_VD12      (0x02 << 24)
-#define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
-#define S3C2410_GPC13_INP       (0x00 << 26)
-#define S3C2410_GPC13_OUTP      (0x01 << 26)
 #define S3C2410_GPC13_VD5       (0x02 << 26)
 #define S3C2400_GPC13_VD13      (0x02 << 26)
-#define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
-#define S3C2410_GPC14_INP       (0x00 << 28)
-#define S3C2410_GPC14_OUTP      (0x01 << 28)
 #define S3C2410_GPC14_VD6       (0x02 << 28)
 #define S3C2400_GPC14_VD14      (0x02 << 28)
-#define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
-#define S3C2410_GPC15_INP       (0x00 << 30)
-#define S3C2410_GPC15_OUTP      (0x01 << 30)
 #define S3C2410_GPC15_VD7       (0x02 << 30)
 #define S3C2400_GPC15_VD15      (0x02 << 30)
@@ -432,99 +300,51 @@
 #define S3C2400_GPDDAT     S3C2410_GPIOREG(0x24)
 #define S3C2400_GPDUP      S3C2410_GPIOREG(0x28)
-#define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
-#define S3C2410_GPD0_INP        (0x00 << 0)
-#define S3C2410_GPD0_OUTP       (0x01 << 0)
 #define S3C2410_GPD0_VD8        (0x02 << 0)
 #define S3C2400_GPD0_VFRAME     (0x02 << 0)
 #define S3C2442_GPD0_nSPICS1    (0x03 << 0)
-#define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
-#define S3C2410_GPD1_INP        (0x00 << 2)
-#define S3C2410_GPD1_OUTP       (0x01 << 2)
 #define S3C2410_GPD1_VD9        (0x02 << 2)
 #define S3C2400_GPD1_VM         (0x02 << 2)
 #define S3C2442_GPD1_SPICLK1    (0x03 << 2)
-#define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
-#define S3C2410_GPD2_INP        (0x00 << 4)
-#define S3C2410_GPD2_OUTP       (0x01 << 4)
 #define S3C2410_GPD2_VD10       (0x02 << 4)
 #define S3C2400_GPD2_VLINE      (0x02 << 4)
-#define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
-#define S3C2410_GPD3_INP        (0x00 << 6)
-#define S3C2410_GPD3_OUTP       (0x01 << 6)
 #define S3C2410_GPD3_VD11       (0x02 << 6)
 #define S3C2400_GPD3_VCLK       (0x02 << 6)
-#define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
-#define S3C2410_GPD4_INP        (0x00 << 8)
-#define S3C2410_GPD4_OUTP       (0x01 << 8)
 #define S3C2410_GPD4_VD12       (0x02 << 8)
 #define S3C2400_GPD4_LEND       (0x02 << 8)
-#define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
-#define S3C2410_GPD5_INP        (0x00 << 10)
-#define S3C2410_GPD5_OUTP       (0x01 << 10)
 #define S3C2410_GPD5_VD13       (0x02 << 10)
 #define S3C2400_GPD5_TOUT0      (0x02 << 10)
-#define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
-#define S3C2410_GPD6_INP        (0x00 << 12)
-#define S3C2410_GPD6_OUTP       (0x01 << 12)
 #define S3C2410_GPD6_VD14       (0x02 << 12)
 #define S3C2400_GPD6_TOUT1      (0x02 << 12)
-#define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
-#define S3C2410_GPD7_INP        (0x00 << 14)
-#define S3C2410_GPD7_OUTP       (0x01 << 14)
 #define S3C2410_GPD7_VD15       (0x02 << 14)
 #define S3C2400_GPD7_TOUT2      (0x02 << 14)
-#define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
-#define S3C2410_GPD8_INP        (0x00 << 16)
-#define S3C2410_GPD8_OUTP       (0x01 << 16)
 #define S3C2410_GPD8_VD16       (0x02 << 16)
 #define S3C2400_GPD8_TOUT3      (0x02 << 16)
-#define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
-#define S3C2410_GPD9_INP        (0x00 << 18)
-#define S3C2410_GPD9_OUTP       (0x01 << 18)
 #define S3C2410_GPD9_VD17       (0x02 << 18)
 #define S3C2400_GPD9_TCLK0      (0x02 << 18)
 #define S3C2410_GPD9_MASK       (0x03 << 18)
-#define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
-#define S3C2410_GPD10_INP       (0x00 << 20)
-#define S3C2410_GPD10_OUTP      (0x01 << 20)
 #define S3C2410_GPD10_VD18      (0x02 << 20)
 #define S3C2400_GPD10_nWAIT     (0x02 << 20)
-#define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
-#define S3C2410_GPD11_INP       (0x00 << 22)
-#define S3C2410_GPD11_OUTP      (0x01 << 22)
 #define S3C2410_GPD11_VD19      (0x02 << 22)
-#define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
-#define S3C2410_GPD12_INP       (0x00 << 24)
-#define S3C2410_GPD12_OUTP      (0x01 << 24)
 #define S3C2410_GPD12_VD20      (0x02 << 24)
-#define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
-#define S3C2410_GPD13_INP       (0x00 << 26)
-#define S3C2410_GPD13_OUTP      (0x01 << 26)
 #define S3C2410_GPD13_VD21      (0x02 << 26)
-#define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
-#define S3C2410_GPD14_INP       (0x00 << 28)
-#define S3C2410_GPD14_OUTP      (0x01 << 28)
 #define S3C2410_GPD14_VD22      (0x02 << 28)
 #define S3C2410_GPD14_nSS1      (0x03 << 28)
-#define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
-#define S3C2410_GPD15_INP       (0x00 << 30)
-#define S3C2410_GPD15_OUTP      (0x01 << 30)
 #define S3C2410_GPD15_VD23      (0x02 << 30)
 #define S3C2410_GPD15_nSS0      (0x03 << 30)
@@ -550,34 +370,22 @@
 #define S3C2400_GPEDAT     S3C2410_GPIOREG(0x30)
 #define S3C2400_GPEUP      S3C2410_GPIOREG(0x34)
-#define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
-#define S3C2410_GPE0_INP       (0x00 << 0)
-#define S3C2410_GPE0_OUTP      (0x01 << 0)
 #define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
 #define S3C2443_GPE0_AC_nRESET (0x03 << 0)
 #define S3C2400_GPE0_EINT0     (0x02 << 0)
 #define S3C2410_GPE0_MASK      (0x03 << 0)
-#define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
-#define S3C2410_GPE1_INP       (0x00 << 2)
-#define S3C2410_GPE1_OUTP      (0x01 << 2)
 #define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
 #define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
 #define S3C2400_GPE1_EINT1     (0x02 << 2)
 #define S3C2400_GPE1_nSS       (0x03 << 2)
 #define S3C2410_GPE1_MASK      (0x03 << 2)
-#define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
-#define S3C2410_GPE2_INP       (0x00 << 4)
-#define S3C2410_GPE2_OUTP      (0x01 << 4)
 #define S3C2410_GPE2_CDCLK     (0x02 << 4)
 #define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
 #define S3C2400_GPE2_EINT2     (0x02 << 4)
 #define S3C2400_GPE2_I2SSDI    (0x03 << 4)
-#define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
-#define S3C2410_GPE3_INP       (0x00 << 6)
-#define S3C2410_GPE3_OUTP      (0x01 << 6)
 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
 #define S3C2443_GPE3_AC_SDI    (0x03 << 6)
 #define S3C2400_GPE3_EINT3     (0x02 << 6)
@@ -585,9 +393,6 @@
 #define S3C2410_GPE3_nSS0      (0x03 << 6)
 #define S3C2410_GPE3_MASK      (0x03 << 6)
-#define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
-#define S3C2410_GPE4_INP       (0x00 << 8)
-#define S3C2410_GPE4_OUTP      (0x01 << 8)
 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
 #define S3C2443_GPE4_AC_SDO    (0x03 << 8)
 #define S3C2400_GPE4_EINT4     (0x02 << 8)
@@ -595,81 +400,48 @@
 #define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 #define S3C2410_GPE4_MASK      (0x03 << 8)
-#define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
-#define S3C2410_GPE5_INP       (0x00 << 10)
-#define S3C2410_GPE5_OUTP      (0x01 << 10)
 #define S3C2410_GPE5_SDCLK     (0x02 << 10)
 #define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
 #define S3C2400_GPE5_EINT5     (0x02 << 10)
 #define S3C2400_GPE5_TCLK1     (0x03 << 10)
-#define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
-#define S3C2410_GPE6_INP       (0x00 << 12)
-#define S3C2410_GPE6_OUTP      (0x01 << 12)
 #define S3C2410_GPE6_SDCMD     (0x02 << 12)
 #define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
 #define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
 #define S3C2400_GPE6_EINT6     (0x02 << 12)
-#define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
-#define S3C2410_GPE7_INP       (0x00 << 14)
-#define S3C2410_GPE7_OUTP      (0x01 << 14)
 #define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 #define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
 #define S3C2443_GPE7_AC_SDI    (0x03 << 14)
 #define S3C2400_GPE7_EINT7     (0x02 << 14)
-#define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
-#define S3C2410_GPE8_INP       (0x00 << 16)
-#define S3C2410_GPE8_OUTP      (0x01 << 16)
 #define S3C2410_GPE8_SDDAT1    (0x02 << 16)
 #define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
 #define S3C2443_GPE8_AC_SDO    (0x03 << 16)
 #define S3C2400_GPE8_nXDACK0   (0x02 << 16)
-#define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
-#define S3C2410_GPE9_INP       (0x00 << 18)
-#define S3C2410_GPE9_OUTP      (0x01 << 18)
 #define S3C2410_GPE9_SDDAT2    (0x02 << 18)
 #define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
 #define S3C2443_GPE9_AC_SYNC   (0x03 << 18)
 #define S3C2400_GPE9_nXDACK1   (0x02 << 18)
 #define S3C2400_GPE9_nXBACK    (0x03 << 18)
-#define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
-#define S3C2410_GPE10_INP      (0x00 << 20)
-#define S3C2410_GPE10_OUTP     (0x01 << 20)
 #define S3C2410_GPE10_SDDAT3   (0x02 << 20)
 #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
 #define S3C2443_GPE10_AC_nRESET (0x03 << 20)
 #define S3C2400_GPE10_nXDREQ0  (0x02 << 20)
-#define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
-#define S3C2410_GPE11_INP      (0x00 << 22)
-#define S3C2410_GPE11_OUTP     (0x01 << 22)
 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
 #define S3C2400_GPE11_nXDREQ1  (0x02 << 22)
 #define S3C2400_GPE11_nXBREQ   (0x03 << 22)
-#define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
-#define S3C2410_GPE12_INP      (0x00 << 24)
-#define S3C2410_GPE12_OUTP     (0x01 << 24)
 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
-#define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
-#define S3C2410_GPE13_INP      (0x00 << 26)
-#define S3C2410_GPE13_OUTP     (0x01 << 26)
 #define S3C2410_GPE13_SPICLK0  (0x02 << 26)
-#define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
-#define S3C2410_GPE14_INP      (0x00 << 28)
-#define S3C2410_GPE14_OUTP     (0x01 << 28)
 #define S3C2410_GPE14_IICSCL   (0x02 << 28)
 #define S3C2410_GPE14_MASK     (0x03 << 28)
-#define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
-#define S3C2410_GPE15_INP      (0x00 << 30)
-#define S3C2410_GPE15_OUTP     (0x01 << 30)
 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 #define S3C2410_GPE15_MASK     (0x03 << 30)
@@ -705,55 +477,31 @@
 #define S3C2400_GPFDAT     S3C2410_GPIOREG(0x3C)
 #define S3C2400_GPFUP      S3C2410_GPIOREG(0x40)
-#define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
-#define S3C2410_GPF0_INP    (0x00 << 0)
-#define S3C2410_GPF0_OUTP   (0x01 << 0)
 #define S3C2410_GPF0_EINT0  (0x02 << 0)
 #define S3C2400_GPF0_RXD0   (0x02 << 0)
-#define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
-#define S3C2410_GPF1_INP    (0x00 << 2)
-#define S3C2410_GPF1_OUTP   (0x01 << 2)
 #define S3C2410_GPF1_EINT1  (0x02 << 2)
 #define S3C2400_GPF1_RXD1   (0x02 << 2)
 #define S3C2400_GPF1_IICSDA (0x03 << 2)
-#define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
-#define S3C2410_GPF2_INP    (0x00 << 4)
-#define S3C2410_GPF2_OUTP   (0x01 << 4)
 #define S3C2410_GPF2_EINT2  (0x02 << 4)
 #define S3C2400_GPF2_TXD0   (0x02 << 4)
-#define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
-#define S3C2410_GPF3_INP    (0x00 << 6)
-#define S3C2410_GPF3_OUTP   (0x01 << 6)
 #define S3C2410_GPF3_EINT3  (0x02 << 6)
 #define S3C2400_GPF3_TXD1   (0x02 << 6)
 #define S3C2400_GPF3_IICSCL (0x03 << 6)
-#define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
-#define S3C2410_GPF4_INP    (0x00 << 8)
-#define S3C2410_GPF4_OUTP   (0x01 << 8)
 #define S3C2410_GPF4_EINT4  (0x02 << 8)
 #define S3C2400_GPF4_nRTS0  (0x02 << 8)
 #define S3C2400_GPF4_nXBACK (0x03 << 8)
-#define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
-#define S3C2410_GPF5_INP    (0x00 << 10)
-#define S3C2410_GPF5_OUTP   (0x01 << 10)
 #define S3C2410_GPF5_EINT5  (0x02 << 10)
 #define S3C2400_GPF5_nCTS0  (0x02 << 10)
 #define S3C2400_GPF5_nXBREQ (0x03 << 10)
-#define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
-#define S3C2410_GPF6_INP    (0x00 << 12)
-#define S3C2410_GPF6_OUTP   (0x01 << 12)
 #define S3C2410_GPF6_EINT6  (0x02 << 12)
 #define S3C2400_GPF6_CLKOUT (0x02 << 12)
-#define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
-#define S3C2410_GPF7_INP    (0x00 << 14)
-#define S3C2410_GPF7_OUTP   (0x01 << 14)
 #define S3C2410_GPF7_EINT7  (0x02 << 14)
 #define S3C2410_GPF_PUPDIS(x)  (1<<(x))
@@ -778,117 +526,69 @@
 #define S3C2400_GPGDAT     S3C2410_GPIOREG(0x48)
 #define S3C2400_GPGUP      S3C2410_GPIOREG(0x4C)
-#define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
-#define S3C2410_GPG0_INP      (0x00 << 0)
-#define S3C2410_GPG0_OUTP     (0x01 << 0)
 #define S3C2410_GPG0_EINT8    (0x02 << 0)
 #define S3C2400_GPG0_I2SLRCK  (0x02 << 0)
-#define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
-#define S3C2410_GPG1_INP      (0x00 << 2)
-#define S3C2410_GPG1_OUTP     (0x01 << 2)
 #define S3C2410_GPG1_EINT9    (0x02 << 2)
 #define S3C2400_GPG1_I2SSCLK  (0x02 << 2)
-#define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
-#define S3C2410_GPG2_INP      (0x00 << 4)
-#define S3C2410_GPG2_OUTP     (0x01 << 4)
 #define S3C2410_GPG2_EINT10   (0x02 << 4)
 #define S3C2410_GPG2_nSS0     (0x03 << 4)
 #define S3C2400_GPG2_CDCLK    (0x02 << 4)
-#define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
-#define S3C2410_GPG3_INP      (0x00 << 6)
-#define S3C2410_GPG3_OUTP     (0x01 << 6)
 #define S3C2410_GPG3_EINT11   (0x02 << 6)
 #define S3C2410_GPG3_nSS1     (0x03 << 6)
 #define S3C2400_GPG3_I2SSDO   (0x02 << 6)
 #define S3C2400_GPG3_I2SSDI   (0x03 << 6)
-#define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
-#define S3C2410_GPG4_INP      (0x00 << 8)
-#define S3C2410_GPG4_OUTP     (0x01 << 8)
 #define S3C2410_GPG4_EINT12   (0x02 << 8)
 #define S3C2400_GPG4_MMCCLK   (0x02 << 8)
 #define S3C2400_GPG4_I2SSDI   (0x03 << 8)
 #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
 #define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
-#define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
-#define S3C2410_GPG5_INP      (0x00 << 10)
-#define S3C2410_GPG5_OUTP     (0x01 << 10)
 #define S3C2410_GPG5_EINT13   (0x02 << 10)
 #define S3C2400_GPG5_MMCCMD   (0x02 << 10)
 #define S3C2400_GPG5_IICSDA   (0x03 << 10)
 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10)      /* not s3c2443 */
-#define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
-#define S3C2410_GPG6_INP      (0x00 << 12)
-#define S3C2410_GPG6_OUTP     (0x01 << 12)
 #define S3C2410_GPG6_EINT14   (0x02 << 12)
 #define S3C2400_GPG6_MMCDAT   (0x02 << 12)
 #define S3C2400_GPG6_IICSCL   (0x03 << 12)
 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
-#define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
-#define S3C2410_GPG7_INP      (0x00 << 14)
-#define S3C2410_GPG7_OUTP     (0x01 << 14)
 #define S3C2410_GPG7_EINT15   (0x02 << 14)
 #define S3C2410_GPG7_SPICLK1  (0x03 << 14)
 #define S3C2400_GPG7_SPIMISO  (0x02 << 14)
 #define S3C2400_GPG7_IICSDA   (0x03 << 14)
-#define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
-#define S3C2410_GPG8_INP      (0x00 << 16)
-#define S3C2410_GPG8_OUTP     (0x01 << 16)
 #define S3C2410_GPG8_EINT16   (0x02 << 16)
 #define S3C2400_GPG8_SPIMOSI  (0x02 << 16)
 #define S3C2400_GPG8_IICSCL   (0x03 << 16)
-#define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
-#define S3C2410_GPG9_INP      (0x00 << 18)
-#define S3C2410_GPG9_OUTP     (0x01 << 18)
 #define S3C2410_GPG9_EINT17   (0x02 << 18)
 #define S3C2400_GPG9_SPICLK   (0x02 << 18)
 #define S3C2400_GPG9_MMCCLK   (0x03 << 18)
-#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
-#define S3C2410_GPG10_INP     (0x00 << 20)
-#define S3C2410_GPG10_OUTP    (0x01 << 20)
 #define S3C2410_GPG10_EINT18  (0x02 << 20)
-#define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
-#define S3C2410_GPG11_INP     (0x00 << 22)
-#define S3C2410_GPG11_OUTP    (0x01 << 22)
 #define S3C2410_GPG11_EINT19  (0x02 << 22)
 #define S3C2410_GPG11_TCLK1   (0x03 << 22)
 #define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
-#define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
-#define S3C2410_GPG12_INP     (0x00 << 24)
-#define S3C2410_GPG12_OUTP    (0x01 << 24)
 #define S3C2410_GPG12_EINT20  (0x02 << 24)
 #define S3C2410_GPG12_XMON    (0x03 << 24)
 #define S3C2442_GPG12_nSPICS0 (0x03 << 24)
 #define S3C2443_GPG12_nINPACK (0x03 << 24)
-#define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
-#define S3C2410_GPG13_INP     (0x00 << 26)
-#define S3C2410_GPG13_OUTP    (0x01 << 26)
 #define S3C2410_GPG13_EINT21  (0x02 << 26)
 #define S3C2410_GPG13_nXPON   (0x03 << 26)
 #define S3C2443_GPG13_CF_nREG (0x03 << 26)
-#define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
-#define S3C2410_GPG14_INP     (0x00 << 28)
-#define S3C2410_GPG14_OUTP    (0x01 << 28)
 #define S3C2410_GPG14_EINT22  (0x02 << 28)
 #define S3C2410_GPG14_YMON    (0x03 << 28)
 #define S3C2443_GPG14_CF_RESET (0x03 << 28)
-#define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
-#define S3C2410_GPG15_INP     (0x00 << 30)
-#define S3C2410_GPG15_OUTP    (0x01 << 30)
 #define S3C2410_GPG15_EINT23  (0x02 << 30)
 #define S3C2410_GPG15_nYPON   (0x03 << 30)
 #define S3C2443_GPG15_CF_PWR  (0x03 << 30)
@@ -907,62 +607,29 @@
 #define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
-#define S3C2410_GPH0        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
-#define S3C2410_GPH0_INP    (0x00 << 0)
-#define S3C2410_GPH0_OUTP   (0x01 << 0)
 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
-#define S3C2410_GPH1        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
-#define S3C2410_GPH1_INP    (0x00 << 2)
-#define S3C2410_GPH1_OUTP   (0x01 << 2)
 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
-#define S3C2410_GPH2        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
-#define S3C2410_GPH2_INP    (0x00 << 4)
-#define S3C2410_GPH2_OUTP   (0x01 << 4)
 #define S3C2410_GPH2_TXD0   (0x02 << 4)
-#define S3C2410_GPH3        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
-#define S3C2410_GPH3_INP    (0x00 << 6)
-#define S3C2410_GPH3_OUTP   (0x01 << 6)
 #define S3C2410_GPH3_RXD0   (0x02 << 6)
-#define S3C2410_GPH4        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
-#define S3C2410_GPH4_INP    (0x00 << 8)
-#define S3C2410_GPH4_OUTP   (0x01 << 8)
 #define S3C2410_GPH4_TXD1   (0x02 << 8)
-#define S3C2410_GPH5        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
-#define S3C2410_GPH5_INP    (0x00 << 10)
-#define S3C2410_GPH5_OUTP   (0x01 << 10)
 #define S3C2410_GPH5_RXD1   (0x02 << 10)
-#define S3C2410_GPH6        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
-#define S3C2410_GPH6_INP    (0x00 << 12)
-#define S3C2410_GPH6_OUTP   (0x01 << 12)
 #define S3C2410_GPH6_TXD2   (0x02 << 12)
 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
-#define S3C2410_GPH7        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
-#define S3C2410_GPH7_INP    (0x00 << 14)
-#define S3C2410_GPH7_OUTP   (0x01 << 14)
 #define S3C2410_GPH7_RXD2   (0x02 << 14)
 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
-#define S3C2410_GPH8        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
-#define S3C2410_GPH8_INP    (0x00 << 16)
-#define S3C2410_GPH8_OUTP   (0x01 << 16)
 #define S3C2410_GPH8_UCLK   (0x02 << 16)
-#define S3C2410_GPH9          S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
-#define S3C2410_GPH9_INP      (0x00 << 18)
-#define S3C2410_GPH9_OUTP     (0x01 << 18)
 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
-#define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
-#define S3C2410_GPH10_INP     (0x00 << 20)
-#define S3C2410_GPH10_OUTP    (0x01 << 20)
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 /* The S3C2412 and S3C2413 move the GPJ register set to after
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index b8687f71c304..6faadcee7729 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -11,21 +11,13 @@
 */
 #include <mach/hardware.h>
-#include <linux/io.h>
+#include <plat/watchdog-reset.h>
-#include <plat/regs-watchdog.h>
-#include <mach/regs-clock.h>
-#include <linux/clk.h>
-#include <linux/err.h>
 extern void (*s3c24xx_reset_hook)(void);
 static void
 arch_reset(char mode, const char *cmd)
 {
-        struct clk *wdtclk;
        if (mode == 's') {
                cpu_reset(0);
        }
@@ -33,31 +25,7 @@ arch_reset(char mode, const char *cmd)
        if (s3c24xx_reset_hook)
                s3c24xx_reset_hook();
-        printk("arch_reset: attempting watchdog reset\n");
+        arch_wdt_reset();
-        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
-        wdtclk = clk_get(NULL, "watchdog");
-        if (!IS_ERR(wdtclk)) {
-                clk_enable(wdtclk);
-        } else
-                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
-        /* put initial values into count and data */
-        __raw_writel(0x80, S3C2410_WTCNT);
-        __raw_writel(0x80, S3C2410_WTDAT);
-        /* set the watchdog to go and reset... */
-        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
-        /* wait for reset to assert... */
-        mdelay(500);
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
        /* we'll take a jump through zero as a poor second */
        cpu_reset(0);
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 6d6995afeb43..06a84adfb13f 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -32,6 +32,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/proc_fs.h>
@@ -224,8 +225,8 @@ static void amlm5900_init_pm(void)
        } else {
                enable_irq_wake(IRQ_EINT9);
                /* configure the suspend/resume status pin */
-                s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP);
+                s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
-                s3c2410_gpio_pullup(S3C2410_GPF2, 0);
+                s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
        }
 }
 static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 8637dea5e150..ce3baba2cd7f 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
@@ -212,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
 {
        /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA21, 1);
+        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
        return 0;
 }
 static int bast_pm_resume(struct sys_device *sd)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
        return 0;
 }
@@ -591,8 +592,6 @@ static void __init bast_map_io(void)
        s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
-        usb_simtec_init();
 }
 static void __init bast_init(void)
@@ -607,6 +606,7 @@ static void __init bast_init(void)
        i2c_register_board_info(0, bast_i2c_devs,
                                ARRAY_SIZE(bast_i2c_devs));
+        usb_simtec_init();
        nor_simtec_init();
 }
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 7a7c4da4c256..d9cd5ddecf4a 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
        .udc_command            = h1940_udc_pullup,
-        .vbus_pin               = S3C2410_GPG5,
+        .vbus_pin               = S3C2410_GPG(5),
        .vbus_pin_inverted      = 1,
 };
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 2b83f8707710..0f6ed61af415 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -19,6 +19,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
@@ -85,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 {
        switch (cmd) {
        case S3C2410_UDC_P_ENABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB3, 1);
+                s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
                break;
        case S3C2410_UDC_P_DISABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB3, 0);
+                s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
                break;
        case S3C2410_UDC_P_RESET :
                break;
@@ -99,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
        .udc_command            = n30_udc_pullup,
-        .vbus_pin               = S3C2410_GPG1,
+        .vbus_pin               = S3C2410_GPG(1),
        .vbus_pin_inverted      = 0,
 };
 static struct gpio_keys_button n30_buttons[] = {
        {
-                .gpio           = S3C2410_GPF0,
+                .gpio           = S3C2410_GPF(0),
                .code           = KEY_POWER,
                .desc           = "Power",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG9,
+                .gpio           = S3C2410_GPG(9),
                .code           = KEY_UP,
                .desc           = "Thumbwheel Up",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG8,
+                .gpio           = S3C2410_GPG(8),
                .code           = KEY_DOWN,
                .desc           = "Thumbwheel Down",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG7,
+                .gpio           = S3C2410_GPG(7),
                .code           = KEY_ENTER,
                .desc           = "Thumbwheel Press",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF7,
+                .gpio           = S3C2410_GPF(7),
                .code           = KEY_HOMEPAGE,
                .desc           = "Home",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF6,
+                .gpio           = S3C2410_GPF(6),
                .code           = KEY_CALENDAR,
                .desc           = "Calendar",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF5,
+                .gpio           = S3C2410_GPF(5),
                .code           = KEY_ADDRESSBOOK,
                .desc           = "Contacts",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF4,
+                .gpio           = S3C2410_GPF(4),
                .code           = KEY_MAIL,
                .desc           = "Mail",
                .active_low     = 0,
@@ -169,73 +170,73 @@ static struct platform_device n30_button_device = {
 static struct gpio_keys_button n35_buttons[] = {
        {
-                .gpio           = S3C2410_GPF0,
+                .gpio           = S3C2410_GPF(0),
                .code           = KEY_POWER,
                .desc           = "Power",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG9,
+                .gpio           = S3C2410_GPG(9),
                .code           = KEY_UP,
                .desc           = "Joystick Up",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG8,
+                .gpio           = S3C2410_GPG(8),
                .code           = KEY_DOWN,
                .desc           = "Joystick Down",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG6,
+                .gpio           = S3C2410_GPG(6),
                .code           = KEY_DOWN,
                .desc           = "Joystick Left",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG5,
+                .gpio           = S3C2410_GPG(5),
                .code           = KEY_DOWN,
                .desc           = "Joystick Right",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG7,
+                .gpio           = S3C2410_GPG(7),
                .code           = KEY_ENTER,
                .desc           = "Joystick Press",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF7,
+                .gpio           = S3C2410_GPF(7),
                .code           = KEY_HOMEPAGE,
                .desc           = "Home",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF6,
+                .gpio           = S3C2410_GPF(6),
                .code           = KEY_CALENDAR,
                .desc           = "Calendar",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF5,
+                .gpio           = S3C2410_GPF(5),
                .code           = KEY_ADDRESSBOOK,
                .desc           = "Contacts",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF4,
+                .gpio           = S3C2410_GPF(4),
                .code           = KEY_MAIL,
                .desc           = "Mail",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPF3,
+                .gpio           = S3C2410_GPF(3),
                .code           = SW_RADIO,
                .desc           = "GPS Antenna",
                .active_low     = 0,
        },
        {
-                .gpio           = S3C2410_GPG2,
+                .gpio           = S3C2410_GPG(2),
                .code           = SW_HEADPHONE_INSERT,
                .desc           = "Headphone",
                .active_low     = 0,
@@ -259,7 +260,7 @@ static struct platform_device n35_button_device = {
 /* This is the bluetooth LED on the device. */
 static struct s3c24xx_led_platdata n30_blue_led_pdata = {
        .name           = "blue_led",
-        .gpio           = S3C2410_GPG6,
+        .gpio           = S3C2410_GPG(6),
        .def_trigger    = "",
 };
@@ -270,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
 static struct s3c24xx_led_platdata n30_warning_led_pdata = {
        .name           = "warning_led",
        .flags          = S3C24XX_LEDF_ACTLOW,
-        .gpio           = S3C2410_GPD9,
+        .gpio           = S3C2410_GPD(9),
        .def_trigger    = "",
 };
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 9f1ba9b63f70..2cc9849eb448 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -27,6 +27,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/sysdev.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
@@ -198,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
 /* LED */
 static struct s3c24xx_led_platdata qt2410_pdata_led = {
-        .gpio           = S3C2410_GPB0,
+        .gpio           = S3C2410_GPB(0),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .name           = "led",
        .def_trigger    = "timer",
@@ -218,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
 {
        switch (cs) {
        case BITBANG_CS_ACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB5, 0);
+                s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
                break;
        case BITBANG_CS_INACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB5, 1);
+                s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
                break;
        }
 }
 static struct s3c2410_spigpio_info spi_gpio_cfg = {
-        .pin_clk        = S3C2410_GPG7,
+        .pin_clk        = S3C2410_GPG(7),
-        .pin_mosi       = S3C2410_GPG6,
+        .pin_mosi       = S3C2410_GPG(6),
-        .pin_miso       = S3C2410_GPG5,
+        .pin_miso       = S3C2410_GPG(5),
        .chip_select    = &spi_gpio_cs,
 };
@@ -346,13 +347,13 @@ static void __init qt2410_machine_init(void)
        }
        s3c24xx_fb_set_platdata(&qt2410_fb_info);
-        s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB0, 1);
+        s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
        s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
        s3c_i2c0_set_platdata(NULL);
-        s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
        platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
        s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 61a1ea9c5c5c..1628cc773a2c 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -18,6 +18,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/dm9000.h>
 #include <linux/i2c.h>
@@ -277,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
 static struct s3c24xx_led_platdata vr1000_led1_pdata = {
        .name           = "led1",
-        .gpio           = S3C2410_GPB0,
+        .gpio           = S3C2410_GPB(0),
        .def_trigger    = "",
 };
 static struct s3c24xx_led_platdata vr1000_led2_pdata = {
        .name           = "led2",
-        .gpio           = S3C2410_GPB1,
+        .gpio           = S3C2410_GPB(1),
        .def_trigger    = "",
 };
 static struct s3c24xx_led_platdata vr1000_led3_pdata = {
        .name           = "led3",
-        .gpio           = S3C2410_GPB2,
+        .gpio           = S3C2410_GPB(2),
        .def_trigger    = "",
 };
@@ -355,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
 static void vr1000_power_off(void)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB9, 1);
+        s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
 }
 static void __init vr1000_map_io(void)
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 87fc481d92d4..143e08a599d4 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -25,6 +25,7 @@
 #include <linux/errno.h>
 #include <linux/time.h>
 #include <linux/sysdev.h>
+#include <linux/gpio.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -76,7 +77,7 @@ static void s3c2410_pm_prepare(void)
        }
        if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF2, 1);
+                s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
 }
@@ -91,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
        __raw_writel(tmp, S3C2410_GSTATUS2);
        if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF2, 0);
+                s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
        return 0;
 }
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 8331e8d97e20..6cd9377ddb82 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -18,9 +18,11 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
+#include <linux/gpio.h>
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/gpio.h>
 #include <linux/io.h>
 #include <asm/mach/arch.h>
@@ -29,7 +31,6 @@
 #include <mach/bast-map.h>
 #include <mach/bast-irq.h>
-#include <mach/regs-gpio.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -53,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
        power_state[port] = to;
        if (power_state[0] && power_state[1])
-                s3c2410_gpio_setpin(S3C2410_GPB4, 0);
+                gpio_set_value(S3C2410_GPB(4), 0);
        else
-                s3c2410_gpio_setpin(S3C2410_GPB4, 1);
+                gpio_set_value(S3C2410_GPB(4), 1);
 }
 static irqreturn_t
@@ -63,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
 {
        struct s3c2410_hcd_info *info = pw;
-        if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) {
+        if (gpio_get_value(S3C2410_GPG(10)) == 0) {
                pr_debug("usb_simtec: over-current irq (oc detected)\n");
                s3c2410_usb_report_oc(info, 3);
        } else {
@@ -106,10 +107,27 @@ static struct s3c2410_hcd_info usb_simtec_info = {
 int usb_simtec_init(void)
 {
+        int ret;
        printk("USB Power Control, (c) 2004 Simtec Electronics\n");
-        s3c_device_usb.dev.platform_data = &usb_simtec_info;
-        s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP);
+        ret = gpio_request(S3C2410_GPB(4), "USB power control");
-        s3c2410_gpio_setpin(S3C2410_GPB4, 1);
+        if (ret < 0) {
+                pr_err("%s: failed to get GPB4\n", __func__);
+                return ret;
+        }
+        ret = gpio_request(S3C2410_GPG(10), "USB overcurrent");
+        if (ret < 0) {
+                pr_err("%s: failed to get GPG10\n", __func__);
+                gpio_free(S3C2410_GPB(4));
+                return ret;
+        }
+        /* turn power on */
+        gpio_direction_output(S3C2410_GPB(4), 1);
+        gpio_direction_input(S3C2410_GPG(10));
+        s3c_device_usb.dev.platform_data = &usb_simtec_info;
        return 0;
 }
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index ca99564ae4b5..63586ffd0ae7 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -38,6 +38,7 @@ menu "S3C2412 Machines"
 config MACH_JIVE
        bool "Logitech Jive"
        select CPU_S3C2412
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Logitech Jive.
@@ -50,6 +51,7 @@ config MACH_SMDK2413
        select CPU_S3C2412
        select MACH_S3C2413
        select MACH_SMDK
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using an SMDK2413
@@ -72,6 +74,7 @@ config MACH_SMDK2412
 config MACH_VSTMS
        bool "VMSTMS"
        select CPU_S3C2412
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using an VSTMS board
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 9e3478506c6f..f8d16fc10bc6 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -20,12 +20,13 @@
 #include <mach/dma.h>
-#include <plat/dma.h>
+#include <plat/dma-plat.h>
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
+#include <plat/regs-dma.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 8f0d37d43b43..8df506eac903 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
@@ -356,8 +357,8 @@ static void jive_lcm_reset(unsigned int set)
 {
        printk(KERN_DEBUG "%s(%d)\n", __func__, set);
-        s3c2410_gpio_setpin(S3C2410_GPG13, set);
+        s3c2410_gpio_setpin(S3C2410_GPG(13), set);
-        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
 }
 #undef LCD_UPPER_MARGIN
@@ -390,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = {
 static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
+        s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
 }
 static struct s3c2410_spigpio_info jive_lcd_spi = {
        .bus_num        = 1,
-        .pin_clk        = S3C2410_GPG8,
+        .pin_clk        = S3C2410_GPG(8),
-        .pin_mosi       = S3C2410_GPB8,
+        .pin_mosi       = S3C2410_GPB(8),
        .num_chipselect = 1,
        .chip_select    = jive_lcd_spi_chipselect,
 };
@@ -412,13 +413,13 @@ static struct platform_device jive_device_lcdspi = {
 static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
+        s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
 }
 static struct s3c2410_spigpio_info jive_wm8750_spi = {
        .bus_num        = 2,
-        .pin_clk        = S3C2410_GPB4,
+        .pin_clk        = S3C2410_GPB(4),
-        .pin_mosi       = S3C2410_GPB9,
+        .pin_mosi       = S3C2410_GPB(9),
        .num_chipselect = 1,
        .chip_select    = jive_wm8750_chipselect,
 };
@@ -479,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = {
 };
 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
-        .vbus_pin       = S3C2410_GPG1,         /* detect is on GPG1 */
+        .vbus_pin       = S3C2410_GPG(1),               /* detect is on GPG1 */
 };
 /* Jive power management device */
@@ -529,8 +530,8 @@ static void jive_power_off(void)
 {
        printk(KERN_INFO "powering system down...\n");
-        s3c2410_gpio_setpin(S3C2410_GPC5, 1);
+        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
 }
 static void __init jive_machine_init(void)
@@ -634,22 +635,22 @@ static void __init jive_machine_init(void)
        /* initialise the spi */
-        s3c2410_gpio_setpin(S3C2410_GPG13, 0);
+        s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB7, 1);
+        s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB6, 0);
+        s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPG8, 1);
+        s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
        /* initialise the WM8750 spi */
-        s3c2410_gpio_setpin(S3C2410_GPH10, 1);
+        s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
        /* Turn off suspend on both USB ports, and switch the
         * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index eba66aa6bd20..9a5e43419722 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -17,6 +17,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -84,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
        switch (cmd)
        {
                case S3C2410_UDC_P_ENABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF2, 1);
+                        s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
                        break;
                case S3C2410_UDC_P_DISABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF2, 0);
+                        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
                        break;
                case S3C2410_UDC_P_RESET :
                        break;
@@ -134,8 +135,8 @@ static void __init smdk2413_machine_init(void)
 {       /* Turn off suspend on both USB ports, and switch the
         * selectable USB port to USB device mode. */
-        s3c2410_gpio_setpin(S3C2410_GPF2, 0);
+        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
                              S3C2410_MISCCR_USBSUSPND0 |
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index cde5ae9a4340..5df73cbf2b40 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -33,6 +33,7 @@ config MACH_ANUBIS
        select PM_SIMTEC if PM
        select HAVE_PATA_PLATFORM
        select S3C24XX_GPIO_EXTRA64
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Simtec Electronics ANUBIS
          development system
@@ -43,6 +44,7 @@ config MACH_OSIRIS
        select S3C24XX_DCLK
        select PM_SIMTEC if PM
        select S3C24XX_GPIO_EXTRA128
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Simtec IM2440D20 module, also
          known as the Osiris.
@@ -58,12 +60,14 @@ config ARCH_S3C2440
        bool "SMDK2440"
        select CPU_S3C2440
        select MACH_SMDK
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the SMDK2440.
 config MACH_NEXCODER_2440
        bool "NexVision NEXCODER 2440 Light Board"
        select CPU_S3C2440
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
@@ -76,6 +80,7 @@ config SMDK2440_CPU2440
 config MACH_AT2440EVB
        bool "Avantech AT2440EVB development board"
        select CPU_S3C2440
+        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the AT2440EVB development board
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 69b6cf34df47..e08e081430f0 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -17,14 +17,16 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
+#include <mach/map.h>
 #include <mach/dma.h>
-#include <plat/dma.h>
+#include <plat/dma-plat.h>
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
+#include <plat/regs-dma.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 9c6abf9fb540..68f3870991bf 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -15,6 +15,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
@@ -468,7 +469,7 @@ static void __init anubis_map_io(void)
                anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
        } else {
                /* ensure that the GPIO is setup */
-                s3c2410_gpio_setpin(S3C2410_GPA0, 1);
+                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
        }
 }
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 315c42e31278..dfc7010935da 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = {
 };
 static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
-        .gpio_detect    = S3C2410_GPG10,
+        .gpio_detect    = S3C2410_GPG(10),
 };
 /* 7" LCD panel */
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 7aeaa972d7f5..d43edede590e 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -18,6 +18,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/string.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
@@ -120,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = {
 static void __init nexcoder_sensorboard_init(void)
 {
        // Initialize SCCB bus
-        s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL
+        s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
-        s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA
+        s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
-        s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
        // Power up the sensor board
-        s3c2410_gpio_setpin(S3C2410_GPF1, 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN
+        s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
-        s3c2410_gpio_setpin(S3C2410_GPF2, 0);
+        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN
+        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
 }
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index c8a46685ce38..cba064b49a64 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -15,6 +15,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/device.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
@@ -291,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
        __raw_writeb(tmp, OSIRIS_VA_CTRL0);
        /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA21, 1);
+        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
        return 0;
 }
@@ -304,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd)
        __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
-        s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
+        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
        return 0;
 }
@@ -384,7 +385,7 @@ static void __init osiris_map_io(void)
                osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
        } else {
                /* write-protect line to the NAND */
-                s3c2410_gpio_setpin(S3C2410_GPA0, 1);
+                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
        }
        /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 8430e5829186..397f3b5c0b47 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -20,12 +20,13 @@
 #include <mach/dma.h>
-#include <plat/dma.h>
+#include <plat/dma-plat.h>
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-ac97.h>
+#include <plat/regs-dma.h>
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig
index 6da82b5c09ba..f5af212066c3 100644
--- a/arch/arm/mach-s3c6400/Kconfig
+++ b/arch/arm/mach-s3c6400/Kconfig
@@ -5,4 +5,27 @@
 #
 # Licensed under GPLv2
-# Currently nothing here, this will be added later
+# Configuration options for the S3C6410 CPU
+config CPU_S3C6400
+        bool
+        select CPU_S3C6400_INIT
+        select CPU_S3C6400_CLOCK
+        help
+          Enable S3C6400 CPU support
+config S3C6400_SETUP_SDHCI
+        bool
+        help
+          Internal configuration for default SDHCI
+          setup for S3C6400.
+# S36400 Macchine support
+config MACH_SMDK6400
+       bool "SMDK6400"
+        select CPU_S3C6400
+        select S3C_DEV_HSMMC
+        select S3C6400_SETUP_SDHCI
+        help
+          Machine support for the Samsung SMDK6400
diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile
index 8f397db25b87..df1ce4aa03e5 100644
--- a/arch/arm/mach-s3c6400/Makefile
+++ b/arch/arm/mach-s3c6400/Makefile
@@ -12,4 +12,12 @@ obj-				:=
 # Core support for S3C6400 system
-obj-n                           += blank.o
+obj-$(CONFIG_CPU_S3C6400)       += s3c6400.o
+# setup support
+obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o
+# Machine support
+obj-$(CONFIG_MACH_SMDK6400)     += mach-smdk6400.o
diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h
index 9771ac2cb07e..1067619f0ba0 100644
--- a/arch/arm/mach-s3c6400/include/mach/dma.h
+++ b/arch/arm/mach-s3c6400/include/mach/dma.h
@@ -11,6 +11,63 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
-/* currently nothing here, placeholder */
+#define S3C_DMA_CHANNELS        (16)
+/* see mach-s3c2410/dma.h for notes on dma channel numbers */
+/* Note, for the S3C64XX architecture we keep the DMACH_
+ * defines in the order they are allocated to [S]DMA0/[S]DMA1
+ * so that is easy to do DHACH_ -> DMA controller conversion
+ */
+enum dma_ch {
+        /* DMA0/SDMA0 */
+        DMACH_UART0 = 0,
+        DMACH_UART0_SRC2,
+        DMACH_UART1,
+        DMACH_UART1_SRC2,
+        DMACH_UART2,
+        DMACH_UART2_SRC2,
+        DMACH_UART3,
+        DMACH_UART3_SRC2,
+        DMACH_PCM0_TX,
+        DMACH_PCM0_RX,
+        DMACH_I2S0_OUT,
+        DMACH_I2S0_IN,
+        DMACH_SPI0_TX,
+        DMACH_SPI0_RX,
+        DMACH_HSI_I2SV40_TX,
+        DMACH_HSI_I2SV40_RX,
+        /* DMA1/SDMA1 */
+        DMACH_PCM1_TX = 16,
+        DMACH_PCM1_RX,
+        DMACH_I2S1_OUT,
+        DMACH_I2S1_IN,
+        DMACH_SPI1_TX,
+        DMACH_SPI1_RX,
+        DMACH_AC97_PCMOUT,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_MICIN,
+        DMACH_PWM,
+        DMACH_IRDA,
+        DMACH_EXTERNAL,
+        DMACH_RES1,
+        DMACH_RES2,
+        DMACH_SECURITY_RX,      /* SDMA1 only */
+        DMACH_SECURITY_TX,      /* SDMA1 only */
+        DMACH_MAX               /* the end */
+};
+static __inline__ int s3c_dma_has_circular(void)
+{
+        /* we will be supporting ciruclar buffers as soon as we have DMA
+         * engine support.
+         */
+        return 1;
+}
+#define S3C2410_DMAF_CIRCULAR           (1 << 0)
+#include <plat/dma.h>
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 8199972ed5bd..5057d9948d35 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -39,6 +39,8 @@
 #define S3C_VA_UART3            S3C_VA_UARTx(3)
 #define S3C64XX_PA_FB           (0x77100000)
+#define S3C64XX_PA_USB_HSOTG    (0x7C000000)
+#define S3C64XX_PA_WATCHDOG     (0x7E004000)
 #define S3C64XX_PA_SYSCON       (0x7E00F000)
 #define S3C64XX_PA_IIS0         (0x7F002000)
 #define S3C64XX_PA_IIS1         (0x7F003000)
@@ -57,6 +59,8 @@
 #define S3C64XX_PA_MODEM        (0x74108000)
 #define S3C64XX_VA_MODEM        S3C_ADDR(0x00600000)
+#define S3C64XX_PA_USBHOST      (0x74300000)
 /* place VICs close together */
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x00)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
@@ -69,5 +73,7 @@
 #define S3C_PA_IIC              S3C64XX_PA_IIC0
 #define S3C_PA_IIC1             S3C64XX_PA_IIC1
 #define S3C_PA_FB               S3C64XX_PA_FB
+#define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
+#define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
 #endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
new file mode 100644
index 000000000000..a6c7f4eb3a1b
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - clock register compatibility with s3c24xx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <plat/regs-clock.h>
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h
index 090cfd969bc7..2e58cb7a7147 100644
--- a/arch/arm/mach-s3c6400/include/mach/system.h
+++ b/arch/arm/mach-s3c6400/include/mach/system.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
+#include <plat/watchdog-reset.h>
 static void arch_idle(void)
 {
        /* nothing here yet */
@@ -18,7 +20,11 @@ static void arch_idle(void)
 static void arch_reset(char mode, const char *cmd)
 {
-        /* nothing here yet */
+        if (mode != 's')
+                arch_wdt_reset();
+        /* if all else fails, or mode was for soft, jump to 0 */
+        cpu_reset(0);
 }
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c6400/mach-smdk6400.c
new file mode 100644
index 000000000000..ab19285389a7
--- /dev/null
+++ b/arch/arm/mach-s3c6400/mach-smdk6400.c
@@ -0,0 +1,96 @@
+/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+#include <plat/s3c6400.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+};
+static struct map_desc smdk6400_iodesc[] = {};
+static void __init smdk6400_map_io(void)
+{
+        s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
+}
+static struct platform_device *smdk6400_devices[] __initdata = {
+        &s3c_device_hsmmc1,
+        &s3c_device_i2c0,
+};
+static struct i2c_board_info i2c_devs[] __initdata = {
+        { I2C_BOARD_INFO("wm8753", 0x1A), },
+        { I2C_BOARD_INFO("24c08", 0x50), },
+};
+static void __init smdk6400_machine_init(void)
+{
+        i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs));
+        platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
+}
+MACHINE_START(SMDK6400, "SMDK6400")
+        /* Maintainer: Ben Dooks <ben@fluff.org> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6400_init_irq,
+        .map_io         = smdk6400_map_io,
+        .init_machine   = smdk6400_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
new file mode 100644
index 000000000000..1ece887d90bb
--- /dev/null
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -0,0 +1,89 @@
+/* linux/arch/arm/mach-s3c6410/cpu.c
+ *
+ * Copyright 2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <plat/cpu-freq.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/iic-core.h>
+#include <plat/s3c6400.h>
+void __init s3c6400_map_io(void)
+{
+        /* setup SDHCI */
+        s3c6400_default_sdhci0();
+        s3c6400_default_sdhci1();
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+}
+void __init s3c6400_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s3c64xx_register_clocks();
+        s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK);
+        s3c6400_setup_clocks();
+}
+void __init s3c6400_init_irq(void)
+{
+        /* VIC0 does not have IRQS 5..7,
+         * VIC1 is fully populated. */
+        s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
+}
+struct sysdev_class s3c6400_sysclass = {
+        .name   = "s3c6400-core",
+};
+static struct sys_device s3c6400_sysdev = {
+        .cls    = &s3c6400_sysclass,
+};
+static int __init s3c6400_core_init(void)
+{
+        return sysdev_class_register(&s3c6400_sysclass);
+}
+core_initcall(s3c6400_core_init);
+int __init s3c6400_init(void)
+{
+        printk("S3C6400: Initialising architecture\n");
+        return sysdev_register(&s3c6400_sysdev);
+}
diff --git a/arch/arm/mach-s3c6400/setup-sdhci.c b/arch/arm/mach-s3c6400/setup-sdhci.c
new file mode 100644
index 000000000000..b93dafbee1f4
--- /dev/null
+++ b/arch/arm/mach-s3c6400/setup-sdhci.c
@@ -0,0 +1,63 @@
+/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+char *s3c6400_hsmmc_clksrcs[4] = {
+        [0] = "hsmmc",
+        [1] = "hsmmc",
+        [2] = "mmc_bus",
+        /* [3] = "48m", - note not succesfully used yet */
+};
+void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
+                                  void __iomem *r,
+                                  struct mmc_ios *ios,
+                                  struct mmc_card *card)
+{
+        u32 ctrl2, ctrl3;
+        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+                  S3C_SDHCI_CTRL2_ENFBCLKRX |
+                  S3C_SDHCI_CTRL2_DFCNT_NONE |
+                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+        if (ios->clock < 25 * 1000000)
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+                         S3C_SDHCI_CTRL3_FCSEL2 |
+                         S3C_SDHCI_CTRL3_FCSEL1 |
+                         S3C_SDHCI_CTRL3_FCSEL0);
+        else
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+        printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
+        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
index 1d5010070027..e63aac7f4e5a 100644
--- a/arch/arm/mach-s3c6410/Kconfig
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -16,9 +16,18 @@ config CPU_S3C6410
 config S3C6410_SETUP_SDHCI
        bool
+        select S3C64XX_SETUP_SDHCI_GPIO
        help
          Internal helper functions for S3C6410 based SDHCI systems
+config MACH_ANW6410
+        bool "A&W6410"
+        select CPU_S3C6410
+        select S3C_DEV_FB
+        select S3C64XX_SETUP_FB_24BPP
+        help
+          Machine support for the A&W6410
 config MACH_SMDK6410
        bool "SMDK6410"
        select CPU_S3C6410
@@ -26,6 +35,8 @@ config MACH_SMDK6410
        select S3C_DEV_HSMMC1
        select S3C_DEV_I2C1
        select S3C_DEV_FB
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_USB_HSOTG
        select S3C6410_SETUP_SDHCI
        select S3C64XX_SETUP_I2C1
        select S3C64XX_SETUP_FB_24BPP
@@ -60,3 +71,29 @@ config SMDK6410_SD_CH1
          channels 0 and 1 are the same.
 endchoice
+config SMDK6410_WM1190_EV1
+        bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
+        depends on MACH_SMDK6410
+        select REGULATOR
+        select REGULATOR_WM8350
+        select MFD_WM8350_I2C
+        select MFD_WM8350_CONFIG_MODE_0
+        select MFD_WM8350_CONFIG_MODE_3
+        select MFD_WM8352_CONFIG_MODE_0
+        help
+          The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
+          and audio daughtercard for the Samsung SMDK6410 reference
+          platform.  Enabling this option will build support for this
+          module into the kernel.  The presence of the module will be
+          detected at runtime so the the resulting kernel can be used
+          with or without the 1190-EV1 fitted.
+config MACH_NCP
+        bool "NCP"
+        select CPU_S3C6410
+        select S3C_DEV_I2C1
+        select S3C_DEV_HSMMC1
+        select S3C64XX_SETUP_I2C1
+        help
+          Machine support for the Samsung NCP
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
index 2cd4f189036b..6f9deac88612 100644
--- a/arch/arm/mach-s3c6410/Makefile
+++ b/arch/arm/mach-s3c6410/Makefile
@@ -20,4 +20,8 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI)	+= setup-sdhci.o
 # machine support
+obj-$(CONFIG_MACH_ANW6410)      += mach-anw6410.o
 obj-$(CONFIG_MACH_SMDK6410)     += mach-smdk6410.o
+obj-$(CONFIG_MACH_NCP)          += mach-ncp.o
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index 6a73ca6b7a3a..ade904de8895 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -31,6 +31,7 @@
 #include <plat/cpu-freq.h>
 #include <plat/regs-serial.h>
+#include <plat/regs-clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
@@ -68,7 +69,7 @@ void __init s3c6410_init_clocks(int xtal)
        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
        s3c24xx_register_baseclocks(xtal);
        s3c64xx_register_clocks();
-        s3c6400_register_clocks();
+        s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
        s3c6400_setup_clocks();
 }
diff --git a/arch/arm/mach-s3c6410/mach-anw6410.c b/arch/arm/mach-s3c6410/mach-anw6410.c
new file mode 100644
index 000000000000..661cca63de25
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-anw6410.c
@@ -0,0 +1,245 @@
+/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ * Copyright 2009 Kwangwoo Lee
+ *      Kwangwoo Lee <kwangwoo.lee@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/dm9000.h>
+#include <video/platform_lcd.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <plat/regs-serial.h>
+#include <plat/iic.h>
+#include <plat/fb.h>
+#include <plat/s3c6410.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-modem.h>
+/* DM9000 */
+#define ANW6410_PA_DM9000       (0x18000000)
+/* A hardware buffer to control external devices is mapped at 0x30000000.
+ * It can not be read. So current status must be kept in anw6410_extdev_status.
+ */
+#define ANW6410_VA_EXTDEV       S3C_ADDR(0x02000000)
+#define ANW6410_PA_EXTDEV       (0x30000000)
+#define ANW6410_EN_DM9000       (1<<11)
+#define ANW6410_EN_LCD          (1<<14)
+static __u32 anw6410_extdev_status;
+static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+};
+/* framebuffer and LCD setup. */
+static void __init anw6410_lcd_mode_set(void)
+{
+        u32 tmp;
+        /* set the LCD type */
+        tmp = __raw_readl(S3C64XX_SPCON);
+        tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+        tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+        __raw_writel(tmp, S3C64XX_SPCON);
+        /* remove the LCD bypass */
+        tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+        tmp &= ~MIFPCON_LCD_BYPASS;
+        __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+/* GPF1 = LCD panel power
+ * GPF4 = LCD backlight control
+ */
+static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power) {
+                anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
+                __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
+                gpio_direction_output(S3C64XX_GPF(1), 1);
+                gpio_direction_output(S3C64XX_GPF(4), 1);
+        } else {
+                anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
+                __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
+                gpio_direction_output(S3C64XX_GPF(1), 0);
+                gpio_direction_output(S3C64XX_GPF(4), 0);
+        }
+}
+static struct plat_lcd_data anw6410_lcd_power_data = {
+        .set_power      = anw6410_lcd_power_set,
+};
+static struct platform_device anw6410_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &anw6410_lcd_power_data,
+};
+static struct s3c_fb_pd_win anw6410_fb_win0 = {
+        /* this is to ensure we use win0 */
+        .win_mode       = {
+                .pixclock       = 41094,
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
+static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
+        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
+        .win[0]         = &anw6410_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+/* DM9000AEP 10/100 ethernet controller */
+static void __init anw6410_dm9000_enable(void)
+{
+        anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
+        __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
+}
+static struct resource anw6410_dm9000_resource[] = {
+        [0] = {
+                .start = ANW6410_PA_DM9000,
+                .end   = ANW6410_PA_DM9000 + 3,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = ANW6410_PA_DM9000 + 4,
+                .end   = ANW6410_PA_DM9000 + 4 + 500,
+                .flags = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start = IRQ_EINT(15),
+                .end   = IRQ_EINT(15),
+                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+        },
+};
+static struct dm9000_plat_data anw6410_dm9000_pdata = {
+        .flags    = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
+        /* dev_addr can be set to provide hwaddr. */
+};
+static struct platform_device anw6410_device_eth = {
+        .name   = "dm9000",
+        .id     = -1,
+        .num_resources  = ARRAY_SIZE(anw6410_dm9000_resource),
+        .resource       = anw6410_dm9000_resource,
+        .dev    = {
+                .platform_data  = &anw6410_dm9000_pdata,
+        },
+};
+static struct map_desc anw6410_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)ANW6410_VA_EXTDEV,
+                .pfn            = __phys_to_pfn(ANW6410_PA_EXTDEV),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct platform_device *anw6410_devices[] __initdata = {
+        &s3c_device_fb,
+        &anw6410_lcd_powerdev,
+        &anw6410_device_eth,
+};
+static void __init anw6410_map_io(void)
+{
+        s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
+        anw6410_lcd_mode_set();
+}
+static void __init anw6410_machine_init(void)
+{
+        s3c_fb_set_platdata(&anw6410_lcd_pdata);
+        gpio_request(S3C64XX_GPF(1), "panel power");
+        gpio_request(S3C64XX_GPF(4), "LCD backlight");
+        anw6410_dm9000_enable();
+        platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
+}
+MACHINE_START(ANW6410, "A&W6410")
+        /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6410_init_irq,
+        .map_io         = anw6410_map_io,
+        .init_machine   = anw6410_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c6410/mach-ncp.c
new file mode 100644
index 000000000000..6030636f8548
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-ncp.c
@@ -0,0 +1,107 @@
+/*
+ * linux/arch/arm/mach-s3c6410/mach-ncp.c
+ *
+ * Copyright (C) 2008-2009 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <video/platform_lcd.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <plat/regs-serial.h>
+#include <plat/iic.h>
+#include <plat/fb.h>
+#include <plat/s3c6410.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
+        /* REVISIT: NCP uses only serial 1, 2 */
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+};
+static struct platform_device *ncp_devices[] __initdata = {
+        &s3c_device_hsmmc1,
+        &s3c_device_i2c0,
+};
+struct map_desc ncp_iodesc[] = {};
+static void __init ncp_map_io(void)
+{
+        s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
+}
+static void __init ncp_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
+}
+MACHINE_START(NCP, "NCP")
+        /* Maintainer: Samsung Electronics */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6410_init_irq,
+        .map_io         = ncp_map_io,
+        .init_machine   = ncp_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 7f473e47e4f1..bc9a7dea567f 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -24,6 +24,12 @@
 #include <linux/fb.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
+#include <linux/smsc911x.h>
+#ifdef CONFIG_SMDK6410_WM1190_EV1
+#include <linux/mfd/wm8350/core.h>
+#include <linux/mfd/wm8350/pmic.h>
+#endif
 #include <video/platform_lcd.h>
@@ -39,8 +45,12 @@
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
+#include <plat/regs-modem.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-sys.h>
 #include <plat/iic.h>
 #include <plat/fb.h>
+#include <plat/gpio-cfg.h>
 #include <plat/s3c6410.h>
 #include <plat/clock.h>
@@ -129,6 +139,37 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 };
+static struct resource smdk6410_smsc911x_resources[] = {
+        [0] = {
+                .start = 0x18000000,
+                .end   = 0x18000000 + SZ_64K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = S3C_EINT(10),
+                .end   = S3C_EINT(10),
+                .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
+        },
+};
+static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
+        .irq_polarity  = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type      = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags         = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+        .phy_interface = PHY_INTERFACE_MODE_MII,
+};
+static struct platform_device smdk6410_smsc911x = {
+        .name          = "smsc911x",
+        .id            = -1,
+        .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
+        .resource      = &smdk6410_smsc911x_resources[0],
+        .dev = {
+                .platform_data = &smdk6410_smsc911x_pdata,
+        },
+};
 static struct map_desc smdk6410_iodesc[] = {};
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -141,12 +182,155 @@ static struct platform_device *smdk6410_devices[] __initdata = {
        &s3c_device_i2c0,
        &s3c_device_i2c1,
        &s3c_device_fb,
+        &s3c_device_usb,
+        &s3c_device_usb_hsotg,
        &smdk6410_lcd_powerdev,
+        &smdk6410_smsc911x,
+};
+#ifdef CONFIG_SMDK6410_WM1190_EV1
+/* S3C64xx internal logic & PLL */
+static struct regulator_init_data wm8350_dcdc1_data = {
+        .constraints = {
+                .name = "PVDD_INT/PVDD_PLL",
+                .min_uV = 1200000,
+                .max_uV = 1200000,
+                .always_on = 1,
+                .apply_uV = 1,
+        },
+};
+/* Memory */
+static struct regulator_init_data wm8350_dcdc3_data = {
+        .constraints = {
+                .name = "PVDD_MEM",
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+                .always_on = 1,
+                .state_mem = {
+                         .uV = 1800000,
+                         .mode = REGULATOR_MODE_NORMAL,
+                         .enabled = 1,
+                 },
+                .initial_state = PM_SUSPEND_MEM,
+        },
+};
+/* USB, EXT, PCM, ADC/DAC, USB, MMC */
+static struct regulator_init_data wm8350_dcdc4_data = {
+        .constraints = {
+                .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+                .always_on = 1,
+        },
+};
+/* ARM core */
+static struct regulator_consumer_supply dcdc6_consumers[] = {
+        {
+                .supply = "vddarm",
+        }
+};
+static struct regulator_init_data wm8350_dcdc6_data = {
+        .constraints = {
+                .name = "PVDD_ARM",
+                .min_uV = 1000000,
+                .max_uV = 1300000,
+                .always_on = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
+        .consumer_supplies = dcdc6_consumers,
 };
+/* Alive */
+static struct regulator_init_data wm8350_ldo1_data = {
+        .constraints = {
+                .name = "PVDD_ALIVE",
+                .min_uV = 1200000,
+                .max_uV = 1200000,
+                .always_on = 1,
+                .apply_uV = 1,
+        },
+};
+/* OTG */
+static struct regulator_init_data wm8350_ldo2_data = {
+        .constraints = {
+                .name = "PVDD_OTG",
+                .min_uV = 3300000,
+                .max_uV = 3300000,
+                .always_on = 1,
+        },
+};
+/* LCD */
+static struct regulator_init_data wm8350_ldo3_data = {
+        .constraints = {
+                .name = "PVDD_LCD",
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+                .always_on = 1,
+        },
+};
+/* OTGi/1190-EV1 HPVDD & AVDD */
+static struct regulator_init_data wm8350_ldo4_data = {
+        .constraints = {
+                .name = "PVDD_OTGI/HPVDD/AVDD",
+                .min_uV = 1200000,
+                .max_uV = 1200000,
+                .apply_uV = 1,
+                .always_on = 1,
+        },
+};
+static struct {
+        int regulator;
+        struct regulator_init_data *initdata;
+} wm1190_regulators[] = {
+        { WM8350_DCDC_1, &wm8350_dcdc1_data },
+        { WM8350_DCDC_3, &wm8350_dcdc3_data },
+        { WM8350_DCDC_4, &wm8350_dcdc4_data },
+        { WM8350_DCDC_6, &wm8350_dcdc6_data },
+        { WM8350_LDO_1, &wm8350_ldo1_data },
+        { WM8350_LDO_2, &wm8350_ldo2_data },
+        { WM8350_LDO_3, &wm8350_ldo3_data },
+        { WM8350_LDO_4, &wm8350_ldo4_data },
+};
+static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
+{
+        int i;
+        /* Instantiate the regulators */
+        for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
+                wm8350_register_regulator(wm8350,
+                                          wm1190_regulators[i].regulator,
+                                          wm1190_regulators[i].initdata);
+        return 0;
+}
+static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
+        .init = smdk6410_wm8350_init,
+        .irq_high = 1,
+};
+#endif
 static struct i2c_board_info i2c_devs0[] __initdata = {
        { I2C_BOARD_INFO("24c08", 0x50), },
        { I2C_BOARD_INFO("wm8580", 0x1b), },
+#ifdef CONFIG_SMDK6410_WM1190_EV1
+        { I2C_BOARD_INFO("wm8350", 0x1a),
+          .platform_data = &smdk6410_wm8350_pdata,
+          .irq = S3C_EINT(12),
+        },
+#endif
 };
 static struct i2c_board_info i2c_devs1[] __initdata = {
@@ -155,9 +339,23 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
 static void __init smdk6410_map_io(void)
 {
+        u32 tmp;
        s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+        /* set the LCD type */
+        tmp = __raw_readl(S3C64XX_SPCON);
+        tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+        tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+        __raw_writel(tmp, S3C64XX_SPCON);
+        /* remove the lcd bypass */
+        tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+        tmp &= ~MIFPCON_LCD_BYPASS;
+        __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
 }
 static void __init smdk6410_machine_init(void)
diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
index 0b5788bd5985..20666f3bd478 100644
--- a/arch/arm/mach-s3c6410/setup-sdhci.c
+++ b/arch/arm/mach-s3c6410/setup-sdhci.c
@@ -21,8 +21,6 @@
 #include <linux/mmc/card.h>
 #include <linux/mmc/host.h>
-#include <mach/gpio.h>
-#include <plat/gpio-cfg.h>
 #include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
@@ -35,22 +33,6 @@ char *s3c6410_hsmmc_clksrcs[4] = {
        /* [3] = "48m", - note not succesfully used yet */
 };
-void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-        unsigned int gpio;
-        unsigned int end;
-        end = S3C64XX_GPG(2 + width);
-        /* Set all the necessary GPG pins to special-function 0 */
-        for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
-        s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
-}
 void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
                                    void __iomem *r,
@@ -84,19 +66,3 @@ void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
 }
-void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-        unsigned int gpio;
-        unsigned int end;
-        end = S3C64XX_GPH(2 + width);
-        /* Set all the necessary GPG pins to special-function 0 */
-        for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
-        s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c
deleted file mode 100644
index 444f266ecc06..000000000000
--- a/arch/arm/mach-sa1100/collie_pm.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Based on spitz_pm.c and sharp code.
- *
- * Copyright (C) 2001  SHARP
- * Copyright 2005 Pavel Machek <pavel@suse.cz>
- *
- * Distribute under GPLv2.
- *
- * Li-ion batteries are angry beasts, and they like to explode. This driver is not finished,
- * and sometimes charges them when it should not. If it makes angry lithium to come your way...
- * ...well, you have been warned.
- *
- * Actually, this should be quite safe, it seems sharp leaves charger enabled by default,
- * and my collie did not explode (yet).
- */
-#include <linux/module.h>
-#include <linux/stat.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <asm/hardware/scoop.h>
-#include <mach/dma.h>
-#include <mach/collie.h>
-#include <asm/mach/sharpsl_param.h>
-#include <asm/hardware/sharpsl_pm.h>
-#include "../drivers/mfd/ucb1x00.h"
-static struct ucb1x00 *ucb;
-static int ad_revise;
-#define ADCtoPower(x)          ((330 * x * 2) / 1024)
-static void collie_charger_init(void)
-{
-        int err;
-        if (sharpsl_param.adadj != -1)
-                ad_revise = sharpsl_param.adadj;
-        /* Register interrupt handler. */
-        if ((err = request_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr, IRQF_DISABLED,
-                               "ACIN", sharpsl_ac_isr))) {
-                printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_AC_IN);
-                return;
-        }
-        if ((err = request_irq(COLLIE_IRQ_GPIO_CO, sharpsl_chrg_full_isr, IRQF_DISABLED,
-                               "CO", sharpsl_chrg_full_isr))) {
-                free_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr);
-                printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_CO);
-                return;
-        }
-        gpio_request(COLLIE_GPIO_CHARGE_ON, "charge on");
-        gpio_direction_output(COLLIE_GPIO_CHARGE_ON, 1);
-        ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON |
-                                   COLLIE_TC35143_GPIO_BBAT_ON);
-        return;
-}
-static void collie_measure_temp(int on)
-{
-        if (on)
-                ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
-        else
-                ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
-}
-static void collie_charge(int on)
-{
-        /* Zaurus seems to contain LTC1731; it should know when to
-         * stop charging itself, so setting charge on should be
-         * relatively harmless (as long as it is not done too often).
-         */
-        gpio_set_value(COLLIE_GPIO_CHARGE_ON, on);
-}
-static void collie_discharge(int on)
-{
-}
-static void collie_discharge1(int on)
-{
-}
-static void collie_presuspend(void)
-{
-}
-static void collie_postsuspend(void)
-{
-}
-static int collie_should_wakeup(unsigned int resume_on_alarm)
-{
-        return 0;
-}
-static unsigned long collie_charger_wakeup(void)
-{
-        return 0;
-}
-int collie_read_backup_battery(void)
-{
-        int voltage;
-        ucb1x00_adc_enable(ucb);
-        ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_BBAT_ON, 0);
-        voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
-        ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
-        ucb1x00_adc_disable(ucb);
-        printk("Backup battery = %d(%d)\n", ADCtoPower(voltage), voltage);
-        return ADCtoPower(voltage);
-}
-int collie_read_main_battery(void)
-{
-        int voltage, voltage_rev, voltage_volts;
-        ucb1x00_adc_enable(ucb);
-        ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
-        ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_MBAT_ON, 0);
-        mdelay(1);
-        voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
-        ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON);
-        ucb1x00_adc_disable(ucb);
-        voltage_rev = voltage + ((ad_revise * voltage) / 652);
-        voltage_volts = ADCtoPower(voltage_rev);
-        printk("Main battery = %d(%d)\n", voltage_volts, voltage);
-        if (voltage != -1)
-                return voltage_volts;
-        else
-                return voltage;
-}
-int collie_read_temp(void)
-{
-        int voltage;
-        /* According to Sharp, temp must be > 973, main battery must be < 465,
-           FIXME: sharpsl_pm.c has both conditions negated? FIXME: values
-           are way out of range? */
-        ucb1x00_adc_enable(ucb);
-        ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
-        /* >1010 = battery removed, 460 = 22C ?, higher = lower temp ? */
-        voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD0, UCB_SYNC);
-        ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
-        ucb1x00_adc_disable(ucb);
-        printk("Battery temp = %d\n", voltage);
-        return voltage;
-}
-static unsigned long read_devdata(int which)
-{
-        switch (which) {
-        case SHARPSL_BATT_VOLT:
-                return collie_read_main_battery();
-        case SHARPSL_BATT_TEMP:
-                return collie_read_temp();
-        case SHARPSL_ACIN_VOLT:
-                return 500;
-        case SHARPSL_STATUS_ACIN: {
-                int ret = GPLR & COLLIE_GPIO_AC_IN;
-                printk("AC status = %d\n", ret);
-                return ret;
-        }
-        case SHARPSL_STATUS_FATAL: {
-                int ret = GPLR & COLLIE_GPIO_MAIN_BAT_LOW;
-                printk("Fatal bat = %d\n", ret);
-                return ret;
-        }
-        default:
-                return ~0;
-        }
-}
-struct battery_thresh collie_battery_levels_acin[] = {
-        { 420, 100},
-        { 417,  95},
-        { 415,  90},
-        { 413,  80},
-        { 411,  75},
-        { 408,  70},
-        { 406,  60},
-        { 403,  50},
-        { 398,  40},
-        { 391,  25},
-        {  10,   5},
-        {   0,   0},
-};
-struct battery_thresh collie_battery_levels[] = {
-        { 394, 100},
-        { 390,  95},
-        { 380,  90},
-        { 370,  80},
-        { 368,  75},    /* From sharp code: battery high with frontlight */
-        { 366,  70},    /* 60..90 -- fake values invented by me for testing */
-        { 364,  60},
-        { 362,  50},
-        { 360,  40},
-        { 358,  25},    /* From sharp code: battery low with frontlight */
-        { 356,   5},    /* From sharp code: battery verylow with frontlight */
-        {   0,   0},
-};
-struct sharpsl_charger_machinfo collie_pm_machinfo = {
-        .init             = collie_charger_init,
-        .read_devdata     = read_devdata,
-        .discharge        = collie_discharge,
-        .discharge1       = collie_discharge1,
-        .charge           = collie_charge,
-        .measure_temp     = collie_measure_temp,
-        .presuspend       = collie_presuspend,
-        .postsuspend      = collie_postsuspend,
-        .charger_wakeup   = collie_charger_wakeup,
-        .should_wakeup    = collie_should_wakeup,
-        .bat_levels       = 12,
-        .bat_levels_noac  = collie_battery_levels,
-        .bat_levels_acin  = collie_battery_levels_acin,
-        .status_high_acin = 368,
-        .status_low_acin  = 358,
-        .status_high_noac = 368,
-        .status_low_noac  = 358,
-        .charge_on_volt   = 350,        /* spitz uses 2.90V, but lets play it safe. */
-        .charge_on_temp   = 550,
-        .charge_acin_high = 550,        /* collie does not seem to have sensor for this, anyway */
-        .charge_acin_low  = 450,        /* ignored, too */
-        .fatal_acin_volt  = 356,
-        .fatal_noacin_volt = 356,
-        .batfull_irq = 1,               /* We do not want periodical charge restarts */
-};
-static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev)
-{
-        sharpsl_pm.machinfo = &collie_pm_machinfo;
-        ucb = pdev->ucb;
-        return 0;
-}
-static struct ucb1x00_driver collie_pm_ucb_driver = {
-        .add    = collie_pm_ucb_add,
-};
-static struct platform_device *collie_pm_device;
-static int __init collie_pm_init(void)
-{
-        int ret;
-        collie_pm_device = platform_device_alloc("sharpsl-pm", -1);
-        if (!collie_pm_device)
-                return -ENOMEM;
-        collie_pm_device->dev.platform_data = &collie_pm_machinfo;
-        ret = platform_device_add(collie_pm_device);
-        if (ret)
-                platform_device_put(collie_pm_device);
-        if (!ret)
-                ret = ucb1x00_register_driver(&collie_pm_ucb_driver);
-        return ret;
-}
-static void __exit collie_pm_exit(void)
-{
-        ucb1x00_unregister_driver(&collie_pm_ucb_driver);
-        platform_device_unregister(collie_pm_device);
-}
-module_init(collie_pm_init);
-module_exit(collie_pm_exit);
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index 28cf36967977..506a5e5a9ad5 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -54,7 +54,7 @@ EXPORT_SYMBOL(jornada_ssp_reverse);
 * timeout after <timeout> rounds. Needs mcu running before its called.
 *
 * returns : %mcu output on success
- *         : %-ETIMEOUT on timeout
+ *         : %-ETIMEDOUT on timeout
 */
 int jornada_ssp_byte(u8 byte)
 {
@@ -82,7 +82,7 @@ EXPORT_SYMBOL(jornada_ssp_byte);
 * jornada_ssp_inout - decide if input is command or trading byte
 *
 * returns : (jornada_ssp_byte(byte)) on success
- *         : %-ETIMEOUT on timeout failure
+ *         : %-ETIMEDOUT on timeout failure
 */
 int jornada_ssp_inout(u8 byte)
 {
diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile
new file mode 100644
index 000000000000..d156f76b379f
--- /dev/null
+++ b/arch/arm/mach-stmp378x/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
+obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot
new file mode 100644
index 000000000000..1568ad404d59
--- /dev/null
+++ b/arch/arm/mach-stmp378x/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x40008000
+params_phys-y   := 0x40000100
+initrd_phys-y   := 0x40800000
diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..731a92286da2
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
@@ -0,0 +1,35 @@
+/*
+ * Low-level IRQ helper macros for Freescale STMP378X
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \base, #0xf0000000      @ vm address of IRQ controller
+                ldr     \irqnr, [\base, #0x70]  @ HW_ICOLL_STAT
+                cmp     \irqnr, #0x7f
+                moveqs  \irqnr, #0              @ Zero flag set for no IRQ
+                .endm
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h
new file mode 100644
index 000000000000..cc59673becdd
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/irqs.h
@@ -0,0 +1,95 @@
+/*
+ * Freescale STMP378X interrupts
+ *
+ * Copyright (C) 2005 Sigmatel Inc
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#define IRQ_DEBUG_UART                  0
+#define IRQ_COMMS_RX                    1
+#define IRQ_COMMS_TX                    1
+#define IRQ_SSP2_ERROR                  2
+#define IRQ_VDD5V                       3
+#define IRQ_HEADPHONE_SHORT             4
+#define IRQ_DAC_DMA                     5
+#define IRQ_DAC_ERROR                   6
+#define IRQ_ADC_DMA                     7
+#define IRQ_ADC_ERROR                   8
+#define IRQ_SPDIF_DMA                   9
+#define IRQ_SAIF2_DMA                   9
+#define IRQ_SPDIF_ERROR                 10
+#define IRQ_SAIF1_IRQ                   10
+#define IRQ_SAIF2_IRQ                   10
+#define IRQ_USB_CTRL                    11
+#define IRQ_USB_WAKEUP                  12
+#define IRQ_GPMI_DMA                    13
+#define IRQ_SSP1_DMA                    14
+#define IRQ_SSP_ERROR                   15
+#define IRQ_GPIO0                       16
+#define IRQ_GPIO1                       17
+#define IRQ_GPIO2                       18
+#define IRQ_SAIF1_DMA                   19
+#define IRQ_SSP2_DMA                    20
+#define IRQ_ECC8_IRQ                    21
+#define IRQ_RTC_ALARM                   22
+#define IRQ_UARTAPP_TX_DMA              23
+#define IRQ_UARTAPP_INTERNAL            24
+#define IRQ_UARTAPP_RX_DMA              25
+#define IRQ_I2C_DMA                     26
+#define IRQ_I2C_ERROR                   27
+#define IRQ_TIMER0                      28
+#define IRQ_TIMER1                      29
+#define IRQ_TIMER2                      30
+#define IRQ_TIMER3                      31
+#define IRQ_BATT_BRNOUT                 32
+#define IRQ_VDDD_BRNOUT                 33
+#define IRQ_VDDIO_BRNOUT                34
+#define IRQ_VDD18_BRNOUT                35
+#define IRQ_TOUCH_DETECT                36
+#define IRQ_LRADC_CH0                   37
+#define IRQ_LRADC_CH1                   38
+#define IRQ_LRADC_CH2                   39
+#define IRQ_LRADC_CH3                   40
+#define IRQ_LRADC_CH4                   41
+#define IRQ_LRADC_CH5                   42
+#define IRQ_LRADC_CH6                   43
+#define IRQ_LRADC_CH7                   44
+#define IRQ_LCDIF_DMA                   45
+#define IRQ_LCDIF_ERROR                 46
+#define IRQ_DIGCTL_DEBUG_TRAP           47
+#define IRQ_RTC_1MSEC                   48
+#define IRQ_DRI_DMA                     49
+#define IRQ_DRI_ATTENTION               50
+#define IRQ_GPMI_ATTENTION              51
+#define IRQ_IR                          52
+#define IRQ_DCP_VMI                     53
+#define IRQ_DCP                         54
+#define IRQ_BCH                         56
+#define IRQ_PXP                         57
+#define IRQ_UARTAPP2_TX_DMA             58
+#define IRQ_UARTAPP2_INTERNAL           59
+#define IRQ_UARTAPP2_RX_DMA             60
+#define IRQ_VDAC_DETECT                 61
+#define IRQ_VDD5V_DROOP                 64
+#define IRQ_DCDC4P2_BO                  65
+#define NR_REAL_IRQS    128
+#define NR_IRQS         (NR_REAL_IRQS + 32 * 3)
+/* All interrupts are FIQ capable */
+#define FIQ_START               IRQ_DEBUG_UART
+/* Hard disk IRQ is a GPMI attention IRQ */
+#define IRQ_HARDDISK            IRQ_GPMI_ATTENTION
diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h
new file mode 100644
index 000000000000..93f952d35969
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/pins.h
@@ -0,0 +1,151 @@
+/*
+ * Freescale STMP378X SoC pin multiplexing
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_PINS_H
+#define __ASM_ARCH_PINS_H
+/*
+ * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
+ * interface  this pin belongs to.
+ */
+/* Bank 0 */
+#define PINID_GPMI_D00          STMP3XXX_PINID(0, 0)
+#define PINID_GPMI_D01          STMP3XXX_PINID(0, 1)
+#define PINID_GPMI_D02          STMP3XXX_PINID(0, 2)
+#define PINID_GPMI_D03          STMP3XXX_PINID(0, 3)
+#define PINID_GPMI_D04          STMP3XXX_PINID(0, 4)
+#define PINID_GPMI_D05          STMP3XXX_PINID(0, 5)
+#define PINID_GPMI_D06          STMP3XXX_PINID(0, 6)
+#define PINID_GPMI_D07          STMP3XXX_PINID(0, 7)
+#define PINID_GPMI_D08          STMP3XXX_PINID(0, 8)
+#define PINID_GPMI_D09          STMP3XXX_PINID(0, 9)
+#define PINID_GPMI_D10          STMP3XXX_PINID(0, 10)
+#define PINID_GPMI_D11          STMP3XXX_PINID(0, 11)
+#define PINID_GPMI_D12          STMP3XXX_PINID(0, 12)
+#define PINID_GPMI_D13          STMP3XXX_PINID(0, 13)
+#define PINID_GPMI_D14          STMP3XXX_PINID(0, 14)
+#define PINID_GPMI_D15          STMP3XXX_PINID(0, 15)
+#define PINID_GPMI_CLE          STMP3XXX_PINID(0, 16)
+#define PINID_GPMI_ALE          STMP3XXX_PINID(0, 17)
+#define PINID_GMPI_CE2N         STMP3XXX_PINID(0, 18)
+#define PINID_GPMI_RDY0         STMP3XXX_PINID(0, 19)
+#define PINID_GPMI_RDY1         STMP3XXX_PINID(0, 20)
+#define PINID_GPMI_RDY2         STMP3XXX_PINID(0, 21)
+#define PINID_GPMI_RDY3         STMP3XXX_PINID(0, 22)
+#define PINID_GPMI_WPN          STMP3XXX_PINID(0, 23)
+#define PINID_GPMI_WRN          STMP3XXX_PINID(0, 24)
+#define PINID_GPMI_RDN          STMP3XXX_PINID(0, 25)
+#define PINID_AUART1_CTS        STMP3XXX_PINID(0, 26)
+#define PINID_AUART1_RTS        STMP3XXX_PINID(0, 27)
+#define PINID_AUART1_RX         STMP3XXX_PINID(0, 28)
+#define PINID_AUART1_TX         STMP3XXX_PINID(0, 29)
+#define PINID_I2C_SCL           STMP3XXX_PINID(0, 30)
+#define PINID_I2C_SDA           STMP3XXX_PINID(0, 31)
+/* Bank 1 */
+#define PINID_LCD_D00           STMP3XXX_PINID(1, 0)
+#define PINID_LCD_D01           STMP3XXX_PINID(1, 1)
+#define PINID_LCD_D02           STMP3XXX_PINID(1, 2)
+#define PINID_LCD_D03           STMP3XXX_PINID(1, 3)
+#define PINID_LCD_D04           STMP3XXX_PINID(1, 4)
+#define PINID_LCD_D05           STMP3XXX_PINID(1, 5)
+#define PINID_LCD_D06           STMP3XXX_PINID(1, 6)
+#define PINID_LCD_D07           STMP3XXX_PINID(1, 7)
+#define PINID_LCD_D08           STMP3XXX_PINID(1, 8)
+#define PINID_LCD_D09           STMP3XXX_PINID(1, 9)
+#define PINID_LCD_D10           STMP3XXX_PINID(1, 10)
+#define PINID_LCD_D11           STMP3XXX_PINID(1, 11)
+#define PINID_LCD_D12           STMP3XXX_PINID(1, 12)
+#define PINID_LCD_D13           STMP3XXX_PINID(1, 13)
+#define PINID_LCD_D14           STMP3XXX_PINID(1, 14)
+#define PINID_LCD_D15           STMP3XXX_PINID(1, 15)
+#define PINID_LCD_D16           STMP3XXX_PINID(1, 16)
+#define PINID_LCD_D17           STMP3XXX_PINID(1, 17)
+#define PINID_LCD_RESET         STMP3XXX_PINID(1, 18)
+#define PINID_LCD_RS            STMP3XXX_PINID(1, 19)
+#define PINID_LCD_WR            STMP3XXX_PINID(1, 20)
+#define PINID_LCD_CS            STMP3XXX_PINID(1, 21)
+#define PINID_LCD_DOTCK         STMP3XXX_PINID(1, 22)
+#define PINID_LCD_ENABLE        STMP3XXX_PINID(1, 23)
+#define PINID_LCD_HSYNC         STMP3XXX_PINID(1, 24)
+#define PINID_LCD_VSYNC         STMP3XXX_PINID(1, 25)
+#define PINID_PWM0              STMP3XXX_PINID(1, 26)
+#define PINID_PWM1              STMP3XXX_PINID(1, 27)
+#define PINID_PWM2              STMP3XXX_PINID(1, 28)
+#define PINID_PWM3              STMP3XXX_PINID(1, 29)
+#define PINID_PWM4              STMP3XXX_PINID(1, 30)
+/* Bank 2 */
+#define PINID_SSP1_CMD          STMP3XXX_PINID(2, 0)
+#define PINID_SSP1_DETECT       STMP3XXX_PINID(2, 1)
+#define PINID_SSP1_DATA0        STMP3XXX_PINID(2, 2)
+#define PINID_SSP1_DATA1        STMP3XXX_PINID(2, 3)
+#define PINID_SSP1_DATA2        STMP3XXX_PINID(2, 4)
+#define PINID_SSP1_DATA3        STMP3XXX_PINID(2, 5)
+#define PINID_SSP1_SCK          STMP3XXX_PINID(2, 6)
+#define PINID_ROTARYA           STMP3XXX_PINID(2, 7)
+#define PINID_ROTARYB           STMP3XXX_PINID(2, 8)
+#define PINID_EMI_A00           STMP3XXX_PINID(2, 9)
+#define PINID_EMI_A01           STMP3XXX_PINID(2, 10)
+#define PINID_EMI_A02           STMP3XXX_PINID(2, 11)
+#define PINID_EMI_A03           STMP3XXX_PINID(2, 12)
+#define PINID_EMI_A04           STMP3XXX_PINID(2, 13)
+#define PINID_EMI_A05           STMP3XXX_PINID(2, 14)
+#define PINID_EMI_A06           STMP3XXX_PINID(2, 15)
+#define PINID_EMI_A07           STMP3XXX_PINID(2, 16)
+#define PINID_EMI_A08           STMP3XXX_PINID(2, 17)
+#define PINID_EMI_A09           STMP3XXX_PINID(2, 18)
+#define PINID_EMI_A10           STMP3XXX_PINID(2, 19)
+#define PINID_EMI_A11           STMP3XXX_PINID(2, 20)
+#define PINID_EMI_A12           STMP3XXX_PINID(2, 21)
+#define PINID_EMI_BA0           STMP3XXX_PINID(2, 22)
+#define PINID_EMI_BA1           STMP3XXX_PINID(2, 23)
+#define PINID_EMI_CASN          STMP3XXX_PINID(2, 24)
+#define PINID_EMI_CE0N          STMP3XXX_PINID(2, 25)
+#define PINID_EMI_CE1N          STMP3XXX_PINID(2, 26)
+#define PINID_GPMI_CE1N         STMP3XXX_PINID(2, 27)
+#define PINID_GPMI_CE0N         STMP3XXX_PINID(2, 28)
+#define PINID_EMI_CKE           STMP3XXX_PINID(2, 29)
+#define PINID_EMI_RASN          STMP3XXX_PINID(2, 30)
+#define PINID_EMI_WEN           STMP3XXX_PINID(2, 31)
+/* Bank 3 */
+#define PINID_EMI_D00           STMP3XXX_PINID(3, 0)
+#define PINID_EMI_D01           STMP3XXX_PINID(3, 1)
+#define PINID_EMI_D02           STMP3XXX_PINID(3, 2)
+#define PINID_EMI_D03           STMP3XXX_PINID(3, 3)
+#define PINID_EMI_D04           STMP3XXX_PINID(3, 4)
+#define PINID_EMI_D05           STMP3XXX_PINID(3, 5)
+#define PINID_EMI_D06           STMP3XXX_PINID(3, 6)
+#define PINID_EMI_D07           STMP3XXX_PINID(3, 7)
+#define PINID_EMI_D08           STMP3XXX_PINID(3, 8)
+#define PINID_EMI_D09           STMP3XXX_PINID(3, 9)
+#define PINID_EMI_D10           STMP3XXX_PINID(3, 10)
+#define PINID_EMI_D11           STMP3XXX_PINID(3, 11)
+#define PINID_EMI_D12           STMP3XXX_PINID(3, 12)
+#define PINID_EMI_D13           STMP3XXX_PINID(3, 13)
+#define PINID_EMI_D14           STMP3XXX_PINID(3, 14)
+#define PINID_EMI_D15           STMP3XXX_PINID(3, 15)
+#define PINID_EMI_DQM0          STMP3XXX_PINID(3, 16)
+#define PINID_EMI_DQM1          STMP3XXX_PINID(3, 17)
+#define PINID_EMI_DQS0          STMP3XXX_PINID(3, 18)
+#define PINID_EMI_DQS1          STMP3XXX_PINID(3, 19)
+#define PINID_EMI_CLK           STMP3XXX_PINID(3, 20)
+#define PINID_EMI_CLKN          STMP3XXX_PINID(3, 21)
+#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
new file mode 100644
index 000000000000..dbcf85b6ac2a
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
@@ -0,0 +1,101 @@
+/*
+ * stmp378x: APBH register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_APBH
+#define _MACH_REGS_APBH
+#define REGS_APBH_BASE  (STMP3XXX_REGS_BASE + 0x4000)
+#define REGS_APBH_PHYS  0x80004000
+#define REGS_APBH_SIZE  0x2000
+#define HW_APBH_CTRL0           0x0
+#define BM_APBH_CTRL0_RESET_CHANNEL     0x00FF0000
+#define BP_APBH_CTRL0_RESET_CHANNEL     16
+#define BM_APBH_CTRL0_CLKGATE   0x40000000
+#define BM_APBH_CTRL0_SFTRST    0x80000000
+#define HW_APBH_CTRL1           0x10
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ  0x00000001
+#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ  0
+#define HW_APBH_CTRL2           0x20
+#define HW_APBH_DEVSEL          0x30
+#define HW_APBH_CH0_NXTCMDAR    (0x50 + 0 * 0x70)
+#define HW_APBH_CH1_NXTCMDAR    (0x50 + 1 * 0x70)
+#define HW_APBH_CH2_NXTCMDAR    (0x50 + 2 * 0x70)
+#define HW_APBH_CH3_NXTCMDAR    (0x50 + 3 * 0x70)
+#define HW_APBH_CH4_NXTCMDAR    (0x50 + 4 * 0x70)
+#define HW_APBH_CH5_NXTCMDAR    (0x50 + 5 * 0x70)
+#define HW_APBH_CH6_NXTCMDAR    (0x50 + 6 * 0x70)
+#define HW_APBH_CH7_NXTCMDAR    (0x50 + 7 * 0x70)
+#define HW_APBH_CH8_NXTCMDAR    (0x50 + 8 * 0x70)
+#define HW_APBH_CH9_NXTCMDAR    (0x50 + 9 * 0x70)
+#define HW_APBH_CH10_NXTCMDAR   (0x50 + 10 * 0x70)
+#define HW_APBH_CH11_NXTCMDAR   (0x50 + 11 * 0x70)
+#define HW_APBH_CH12_NXTCMDAR   (0x50 + 12 * 0x70)
+#define HW_APBH_CH13_NXTCMDAR   (0x50 + 13 * 0x70)
+#define HW_APBH_CH14_NXTCMDAR   (0x50 + 14 * 0x70)
+#define HW_APBH_CH15_NXTCMDAR   (0x50 + 15 * 0x70)
+#define HW_APBH_CHn_NXTCMDAR    0x50
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER     0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE       1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ        2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE       3
+#define BM_APBH_CHn_CMD_COMMAND 0x00000003
+#define BP_APBH_CHn_CMD_COMMAND 0
+#define BM_APBH_CHn_CMD_CHAIN   0x00000004
+#define BM_APBH_CHn_CMD_IRQONCMPLT      0x00000008
+#define BM_APBH_CHn_CMD_NANDLOCK        0x00000010
+#define BM_APBH_CHn_CMD_NANDWAIT4READY  0x00000020
+#define BM_APBH_CHn_CMD_SEMAPHORE       0x00000040
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD     0x00000080
+#define BM_APBH_CHn_CMD_CMDWORDS        0x0000F000
+#define BP_APBH_CHn_CMD_CMDWORDS        12
+#define BM_APBH_CHn_CMD_XFER_COUNT      0xFFFF0000
+#define BP_APBH_CHn_CMD_XFER_COUNT      16
+#define HW_APBH_CH0_SEMA        (0x80 + 0 * 0x70)
+#define HW_APBH_CH1_SEMA        (0x80 + 1 * 0x70)
+#define HW_APBH_CH2_SEMA        (0x80 + 2 * 0x70)
+#define HW_APBH_CH3_SEMA        (0x80 + 3 * 0x70)
+#define HW_APBH_CH4_SEMA        (0x80 + 4 * 0x70)
+#define HW_APBH_CH5_SEMA        (0x80 + 5 * 0x70)
+#define HW_APBH_CH6_SEMA        (0x80 + 6 * 0x70)
+#define HW_APBH_CH7_SEMA        (0x80 + 7 * 0x70)
+#define HW_APBH_CH8_SEMA        (0x80 + 8 * 0x70)
+#define HW_APBH_CH9_SEMA        (0x80 + 9 * 0x70)
+#define HW_APBH_CH10_SEMA       (0x80 + 10 * 0x70)
+#define HW_APBH_CH11_SEMA       (0x80 + 11 * 0x70)
+#define HW_APBH_CH12_SEMA       (0x80 + 12 * 0x70)
+#define HW_APBH_CH13_SEMA       (0x80 + 13 * 0x70)
+#define HW_APBH_CH14_SEMA       (0x80 + 14 * 0x70)
+#define HW_APBH_CH15_SEMA       (0x80 + 15 * 0x70)
+#define HW_APBH_CHn_SEMA        0x80
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
+#define BM_APBH_CHn_SEMA_PHORE  0x00FF0000
+#define BP_APBH_CHn_SEMA_PHORE  16
+#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
new file mode 100644
index 000000000000..3b934a4d27f0
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
@@ -0,0 +1,119 @@
+/*
+ * stmp378x: APBX register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_APBX
+#define _MACH_REGS_APBX
+#define REGS_APBX_BASE  (STMP3XXX_REGS_BASE + 0x24000)
+#define REGS_APBX_PHYS  0x80024000
+#define REGS_APBX_SIZE  0x2000
+#define HW_APBX_CTRL0           0x0
+#define BM_APBX_CTRL0_CLKGATE   0x40000000
+#define BM_APBX_CTRL0_SFTRST    0x80000000
+#define HW_APBX_CTRL1           0x10
+#define HW_APBX_CTRL2           0x20
+#define HW_APBX_CHANNEL_CTRL    0x30
+#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL      0xFFFF0000
+#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL      16
+#define HW_APBX_DEVSEL          0x40
+#define HW_APBX_CH0_NXTCMDAR    (0x110 + 0 * 0x70)
+#define HW_APBX_CH1_NXTCMDAR    (0x110 + 1 * 0x70)
+#define HW_APBX_CH2_NXTCMDAR    (0x110 + 2 * 0x70)
+#define HW_APBX_CH3_NXTCMDAR    (0x110 + 3 * 0x70)
+#define HW_APBX_CH4_NXTCMDAR    (0x110 + 4 * 0x70)
+#define HW_APBX_CH5_NXTCMDAR    (0x110 + 5 * 0x70)
+#define HW_APBX_CH6_NXTCMDAR    (0x110 + 6 * 0x70)
+#define HW_APBX_CH7_NXTCMDAR    (0x110 + 7 * 0x70)
+#define HW_APBX_CH8_NXTCMDAR    (0x110 + 8 * 0x70)
+#define HW_APBX_CH9_NXTCMDAR    (0x110 + 9 * 0x70)
+#define HW_APBX_CH10_NXTCMDAR   (0x110 + 10 * 0x70)
+#define HW_APBX_CH11_NXTCMDAR   (0x110 + 11 * 0x70)
+#define HW_APBX_CH12_NXTCMDAR   (0x110 + 12 * 0x70)
+#define HW_APBX_CH13_NXTCMDAR   (0x110 + 13 * 0x70)
+#define HW_APBX_CH14_NXTCMDAR   (0x110 + 14 * 0x70)
+#define HW_APBX_CH15_NXTCMDAR   (0x110 + 15 * 0x70)
+#define HW_APBX_CHn_NXTCMDAR    0x110
+#define BM_APBX_CHn_CMD_COMMAND 0x00000003
+#define BP_APBX_CHn_CMD_COMMAND 0
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER     0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE       1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ        2
+#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE       3
+#define BM_APBX_CHn_CMD_CHAIN   0x00000004
+#define BM_APBX_CHn_CMD_IRQONCMPLT      0x00000008
+#define BM_APBX_CHn_CMD_SEMAPHORE       0x00000040
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD     0x00000080
+#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
+#define BM_APBX_CHn_CMD_CMDWORDS        0x0000F000
+#define BP_APBX_CHn_CMD_CMDWORDS        12
+#define BM_APBX_CHn_CMD_XFER_COUNT      0xFFFF0000
+#define BP_APBX_CHn_CMD_XFER_COUNT      16
+#define HW_APBX_CH0_BAR         (0x130 + 0 * 0x70)
+#define HW_APBX_CH1_BAR         (0x130 + 1 * 0x70)
+#define HW_APBX_CH2_BAR         (0x130 + 2 * 0x70)
+#define HW_APBX_CH3_BAR         (0x130 + 3 * 0x70)
+#define HW_APBX_CH4_BAR         (0x130 + 4 * 0x70)
+#define HW_APBX_CH5_BAR         (0x130 + 5 * 0x70)
+#define HW_APBX_CH6_BAR         (0x130 + 6 * 0x70)
+#define HW_APBX_CH7_BAR         (0x130 + 7 * 0x70)
+#define HW_APBX_CH8_BAR         (0x130 + 8 * 0x70)
+#define HW_APBX_CH9_BAR         (0x130 + 9 * 0x70)
+#define HW_APBX_CH10_BAR                (0x130 + 10 * 0x70)
+#define HW_APBX_CH11_BAR                (0x130 + 11 * 0x70)
+#define HW_APBX_CH12_BAR                (0x130 + 12 * 0x70)
+#define HW_APBX_CH13_BAR                (0x130 + 13 * 0x70)
+#define HW_APBX_CH14_BAR                (0x130 + 14 * 0x70)
+#define HW_APBX_CH15_BAR                (0x130 + 15 * 0x70)
+#define HW_APBX_CHn_BAR         0x130
+#define HW_APBX_CH0_SEMA        (0x140 + 0 * 0x70)
+#define HW_APBX_CH1_SEMA        (0x140 + 1 * 0x70)
+#define HW_APBX_CH2_SEMA        (0x140 + 2 * 0x70)
+#define HW_APBX_CH3_SEMA        (0x140 + 3 * 0x70)
+#define HW_APBX_CH4_SEMA        (0x140 + 4 * 0x70)
+#define HW_APBX_CH5_SEMA        (0x140 + 5 * 0x70)
+#define HW_APBX_CH6_SEMA        (0x140 + 6 * 0x70)
+#define HW_APBX_CH7_SEMA        (0x140 + 7 * 0x70)
+#define HW_APBX_CH8_SEMA        (0x140 + 8 * 0x70)
+#define HW_APBX_CH9_SEMA        (0x140 + 9 * 0x70)
+#define HW_APBX_CH10_SEMA       (0x140 + 10 * 0x70)
+#define HW_APBX_CH11_SEMA       (0x140 + 11 * 0x70)
+#define HW_APBX_CH12_SEMA       (0x140 + 12 * 0x70)
+#define HW_APBX_CH13_SEMA       (0x140 + 13 * 0x70)
+#define HW_APBX_CH14_SEMA       (0x140 + 14 * 0x70)
+#define HW_APBX_CH15_SEMA       (0x140 + 15 * 0x70)
+#define HW_APBX_CHn_SEMA        0x140
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
+#define BM_APBX_CHn_SEMA_PHORE  0x00FF0000
+#define BP_APBX_CHn_SEMA_PHORE  16
+#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
new file mode 100644
index 000000000000..641ac6126f83
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
@@ -0,0 +1,63 @@
+/*
+ * stmp378x: AUDIOIN register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_AUDIOIN_BASE       (STMP3XXX_REGS_BASE + 0x4C000)
+#define REGS_AUDIOIN_PHYS       0x8004C000
+#define REGS_AUDIOIN_SIZE       0x2000
+#define HW_AUDIOIN_CTRL         0x0
+#define BM_AUDIOIN_CTRL_RUN     0x00000001
+#define BP_AUDIOIN_CTRL_RUN     0
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x00000002
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x00000004
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x00000008
+#define BM_AUDIOIN_CTRL_WORD_LENGTH     0x00000020
+#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
+#define BM_AUDIOIN_CTRL_SFTRST  0x80000000
+#define HW_AUDIOIN_STAT         0x10
+#define HW_AUDIOIN_ADCSRR       0x20
+#define HW_AUDIOIN_ADCVOLUME    0x30
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT       0x000000FF
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT       0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT        0x00FF0000
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT        16
+#define HW_AUDIOIN_ADCDEBUG     0x40
+#define HW_AUDIOIN_ADCVOL       0x50
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT    0x0000000F
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT    0
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT  0x00000030
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT  4
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT     0x00000F00
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT     8
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT   0x00003000
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT   12
+#define BM_AUDIOIN_ADCVOL_MUTE  0x01000000
+#define HW_AUDIOIN_MICLINE      0x60
+#define HW_AUDIOIN_ANACLKCTRL   0x70
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE   0x80000000
+#define HW_AUDIOIN_DATA         0x80
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
new file mode 100644
index 000000000000..f533e23694a0
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
@@ -0,0 +1,104 @@
+/*
+ * stmp378x: AUDIOOUT register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_AUDIOOUT_BASE      (STMP3XXX_REGS_BASE + 0x48000)
+#define REGS_AUDIOOUT_PHYS      0x80048000
+#define REGS_AUDIOOUT_SIZE      0x2000
+#define HW_AUDIOOUT_CTRL        0x0
+#define BM_AUDIOOUT_CTRL_RUN    0x00000001
+#define BP_AUDIOOUT_CTRL_RUN    0
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x00000002
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x00000004
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x00000008
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH    0x00000040
+#define BM_AUDIOOUT_CTRL_CLKGATE        0x40000000
+#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
+#define HW_AUDIOOUT_STAT        0x10
+#define HW_AUDIOOUT_DACSRR      0x20
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC     0x00001FFF
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC     0
+#define BM_AUDIOOUT_DACSRR_SRC_INT      0x001F0000
+#define BP_AUDIOOUT_DACSRR_SRC_INT      16
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD     0x07000000
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD     24
+#define BM_AUDIOOUT_DACSRR_BASEMULT     0x70000000
+#define BP_AUDIOOUT_DACSRR_BASEMULT     28
+#define HW_AUDIOOUT_DACVOLUME   0x30
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT        0x00000100
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD    0x02000000
+#define HW_AUDIOOUT_DACDEBUG    0x40
+#define HW_AUDIOOUT_HPVOL       0x50
+#define BM_AUDIOOUT_HPVOL_MUTE  0x01000000
+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD   0x02000000
+#define HW_AUDIOOUT_PWRDN       0x70
+#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x00000001
+#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
+#define BM_AUDIOOUT_PWRDN_CAPLESS       0x00000010
+#define BM_AUDIOOUT_PWRDN_ADC   0x00000100
+#define BM_AUDIOOUT_PWRDN_DAC   0x00001000
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x00010000
+#define BM_AUDIOOUT_PWRDN_SPEAKER       0x01000000
+#define HW_AUDIOOUT_REFCTRL     0x80
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL     0x000000F0
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL     4
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL  0x00000F00
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL  8
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG     0x00001000
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC     0x00002000
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL   0x00030000
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL   16
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR     0x00080000
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ     0x00700000
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ     20
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x01000000
+#define BM_AUDIOOUT_REFCTRL_RAISE_REF   0x02000000
+#define HW_AUDIOOUT_ANACTRL     0x90
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB  0x00000010
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
+#define HW_AUDIOOUT_TEST        0xA0
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ      0x00C00000
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ      22
+#define HW_AUDIOOUT_BISTCTRL    0xB0
+#define HW_AUDIOOUT_BISTSTAT0   0xC0
+#define HW_AUDIOOUT_BISTSTAT1   0xD0
+#define HW_AUDIOOUT_ANACLKCTRL  0xE0
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE  0x80000000
+#define HW_AUDIOOUT_DATA        0xF0
+#define HW_AUDIOOUT_SPEAKERCTRL 0x100
+#define BM_AUDIOOUT_SPEAKERCTRL_MUTE    0x01000000
+#define HW_AUDIOOUT_VERSION     0x200
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
new file mode 100644
index 000000000000..532d24650717
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
@@ -0,0 +1,56 @@
+/*
+ * stmp378x: BCH register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_BCH_BASE   (STMP3XXX_REGS_BASE + 0xA000)
+#define REGS_BCH_PHYS   0x8000A000
+#define REGS_BCH_SIZE   0x2000
+#define HW_BCH_CTRL             0x0
+#define BM_BCH_CTRL_COMPLETE_IRQ        0x00000001
+#define BP_BCH_CTRL_COMPLETE_IRQ        0
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN     0x00000100
+#define HW_BCH_STATUS0          0x10
+#define BM_BCH_STATUS0_UNCORRECTABLE    0x00000004
+#define BM_BCH_STATUS0_CORRECTED        0x00000008
+#define BM_BCH_STATUS0_STATUS_BLK0      0x0000FF00
+#define BP_BCH_STATUS0_STATUS_BLK0      8
+#define BM_BCH_STATUS0_COMPLETED_CE     0x000F0000
+#define BP_BCH_STATUS0_COMPLETED_CE     16
+#define HW_BCH_LAYOUTSELECT     0x70
+#define HW_BCH_FLASH0LAYOUT0    0x80
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH0LAYOUT0_ECC0       0x0000F000
+#define BP_BCH_FLASH0LAYOUT0_ECC0       12
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE  0x00FF0000
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE  16
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS    0xFF000000
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS    24
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH0LAYOUT1_ECCN       0x0000F000
+#define BP_BCH_FLASH0LAYOUT1_ECCN       12
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE  0xFFFF0000
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE  16
+#define HW_BCH_BLOCKNAME        0x150
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
new file mode 100644
index 000000000000..7c546afd57a3
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
@@ -0,0 +1,88 @@
+/*
+ * stmp378x: CLKCTRL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_CLKCTRL
+#define _MACH_REGS_CLKCTRL
+#define REGS_CLKCTRL_BASE       (STMP3XXX_REGS_BASE + 0x40000)
+#define REGS_CLKCTRL_PHYS       0x80040000
+#define REGS_CLKCTRL_SIZE       0x2000
+#define HW_CLKCTRL_PLLCTRL0     0x0
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
+#define HW_CLKCTRL_CPU          0x20
+#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
+#define BP_CLKCTRL_CPU_DIV_CPU  0
+#define HW_CLKCTRL_HBUS         0x30
+#define BM_CLKCTRL_HBUS_DIV     0x0000001F
+#define BP_CLKCTRL_HBUS_DIV     0
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
+#define HW_CLKCTRL_XBUS         0x40
+#define HW_CLKCTRL_XTAL         0x50
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
+#define HW_CLKCTRL_PIX          0x60
+#define BM_CLKCTRL_PIX_DIV      0x00000FFF
+#define BP_CLKCTRL_PIX_DIV      0
+#define BM_CLKCTRL_PIX_CLKGATE  0x80000000
+#define HW_CLKCTRL_SSP          0x70
+#define HW_CLKCTRL_GPMI         0x80
+#define HW_CLKCTRL_SPDIF        0x90
+#define HW_CLKCTRL_EMI          0xA0
+#define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
+#define BP_CLKCTRL_EMI_DIV_EMI  0
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL    0x20000000
+#define HW_CLKCTRL_IR           0xB0
+#define HW_CLKCTRL_SAIF         0xC0
+#define HW_CLKCTRL_TV           0xD0
+#define HW_CLKCTRL_ETM          0xE0
+#define HW_CLKCTRL_FRAC         0xF0
+#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
+#define BP_CLKCTRL_FRAC_EMIFRAC 8
+#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
+#define BP_CLKCTRL_FRAC_PIXFRAC 16
+#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x00800000
+#define HW_CLKCTRL_FRAC1        0x100
+#define HW_CLKCTRL_CLKSEQ       0x110
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX    0x00000002
+#define HW_CLKCTRL_RESET        0x120
+#define BM_CLKCTRL_RESET_DIG    0x00000001
+#define BP_CLKCTRL_RESET_DIG    0
+#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
new file mode 100644
index 000000000000..fdedd00c0e28
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
@@ -0,0 +1,87 @@
+/*
+ * stmp378x: DCP register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_DCP_BASE   (STMP3XXX_REGS_BASE + 0x28000)
+#define REGS_DCP_PHYS   0x80028000
+#define REGS_DCP_SIZE   0x2000
+#define HW_DCP_CTRL             0x0
+#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE    0x000000FF
+#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE    0
+#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING      0x00400000
+#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES      0x00800000
+#define BM_DCP_CTRL_CLKGATE     0x40000000
+#define BM_DCP_CTRL_SFTRST      0x80000000
+#define HW_DCP_STAT             0x10
+#define BM_DCP_STAT_IRQ         0x0000000F
+#define BP_DCP_STAT_IRQ         0
+#define HW_DCP_CHANNELCTRL      0x20
+#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL       0x000000FF
+#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL       0
+#define HW_DCP_CONTEXT          0x50
+#define BM_DCP_PACKET1_INTERRUPT        0x00000001
+#define BP_DCP_PACKET1_INTERRUPT        0
+#define BM_DCP_PACKET1_DECR_SEMAPHORE   0x00000002
+#define BM_DCP_PACKET1_CHAIN    0x00000004
+#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
+#define BM_DCP_PACKET1_ENABLE_CIPHER    0x00000020
+#define BM_DCP_PACKET1_ENABLE_HASH      0x00000040
+#define BM_DCP_PACKET1_CIPHER_ENCRYPT   0x00000100
+#define BM_DCP_PACKET1_CIPHER_INIT      0x00000200
+#define BM_DCP_PACKET1_OTP_KEY  0x00000400
+#define BM_DCP_PACKET1_PAYLOAD_KEY      0x00000800
+#define BM_DCP_PACKET1_HASH_INIT        0x00001000
+#define BM_DCP_PACKET1_HASH_TERM        0x00002000
+#define BM_DCP_PACKET2_CIPHER_SELECT    0x0000000F
+#define BP_DCP_PACKET2_CIPHER_SELECT    0
+#define BM_DCP_PACKET2_CIPHER_MODE      0x000000F0
+#define BP_DCP_PACKET2_CIPHER_MODE      4
+#define BM_DCP_PACKET2_KEY_SELECT       0x0000FF00
+#define BP_DCP_PACKET2_KEY_SELECT       8
+#define BM_DCP_PACKET2_HASH_SELECT      0x000F0000
+#define BP_DCP_PACKET2_HASH_SELECT      16
+#define BM_DCP_PACKET2_CIPHER_CFG       0xFF000000
+#define BP_DCP_PACKET2_CIPHER_CFG       24
+#define HW_DCP_CH0CMDPTR        (0x100 + 0 * 0x40)
+#define HW_DCP_CH1CMDPTR        (0x100 + 1 * 0x40)
+#define HW_DCP_CH2CMDPTR        (0x100 + 2 * 0x40)
+#define HW_DCP_CH3CMDPTR        (0x100 + 3 * 0x40)
+#define HW_DCP_CHnCMDPTR        0x100
+#define HW_DCP_CH0SEMA          (0x110 + 0 * 0x40)
+#define HW_DCP_CH1SEMA          (0x110 + 1 * 0x40)
+#define HW_DCP_CH2SEMA          (0x110 + 2 * 0x40)
+#define HW_DCP_CH3SEMA          (0x110 + 3 * 0x40)
+#define HW_DCP_CHnSEMA          0x110
+#define BM_DCP_CHnSEMA_INCREMENT        0x000000FF
+#define BP_DCP_CHnSEMA_INCREMENT        0
+#define HW_DCP_CH0STAT          (0x120 + 0 * 0x40)
+#define HW_DCP_CH1STAT          (0x120 + 1 * 0x40)
+#define HW_DCP_CH2STAT          (0x120 + 2 * 0x40)
+#define HW_DCP_CH3STAT          (0x120 + 3 * 0x40)
+#define HW_DCP_CHnSTAT          0x120
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
new file mode 100644
index 000000000000..5293005523b3
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
@@ -0,0 +1,38 @@
+/*
+ * stmp378x: DIGCTL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_DIGCTL_BASE        (STMP3XXX_REGS_BASE + 0x1C000)
+#define REGS_DIGCTL_PHYS        0x8001C000
+#define REGS_DIGCTL_SIZE        0x2000
+#define HW_DIGCTL_CTRL          0x0
+#define BM_DIGCTL_CTRL_USB_CLKGATE      0x00000004
+#define HW_DIGCTL_ARMCACHE      0x2B0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x00000003
+#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
+#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x00000030
+#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
+#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x00000300
+#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
+#define BM_DIGCTL_ARMCACHE_DRTY_SS      0x00003000
+#define BP_DIGCTL_ARMCACHE_DRTY_SS      12
+#define BM_DIGCTL_ARMCACHE_VALID_SS     0x00030000
+#define BP_DIGCTL_ARMCACHE_VALID_SS     16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
new file mode 100644
index 000000000000..02851431677c
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
@@ -0,0 +1,27 @@
+/*
+ * stmp378x: DRAM register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_DRAM_BASE  (STMP3XXX_REGS_BASE + 0xE0000)
+#define REGS_DRAM_PHYS  0x800E0000
+#define REGS_DRAM_SIZE  0x2000
+#define HW_DRAM_CTL06           0x18
+#define HW_DRAM_CTL08           0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
new file mode 100644
index 000000000000..da25f7e397e5
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
@@ -0,0 +1,45 @@
+/*
+ * stmp378x: DRI register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_DRI_BASE   (STMP3XXX_REGS_BASE + 0x74000)
+#define REGS_DRI_PHYS   0x80074000
+#define REGS_DRI_SIZE   0x2000
+#define HW_DRI_CTRL             0x0
+#define BM_DRI_CTRL_RUN         0x00000001
+#define BP_DRI_CTRL_RUN         0
+#define BM_DRI_CTRL_ATTENTION_IRQ       0x00000002
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
+#define BM_DRI_CTRL_OVERFLOW_IRQ        0x00000008
+#define BM_DRI_CTRL_ATTENTION_IRQ_EN    0x00000200
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN      0x00000400
+#define BM_DRI_CTRL_OVERFLOW_IRQ_EN     0x00000800
+#define BM_DRI_CTRL_REACQUIRE_PHASE     0x00008000
+#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
+#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
+#define BM_DRI_CTRL_ENABLE_INPUTS       0x20000000
+#define BM_DRI_CTRL_CLKGATE     0x40000000
+#define BM_DRI_CTRL_SFTRST      0x80000000
+#define HW_DRI_TIMING           0x10
+#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL    0x000000FF
+#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL    0
+#define BM_DRI_TIMING_PILOT_REP_RATE    0x000F0000
+#define BP_DRI_TIMING_PILOT_REP_RATE    16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
new file mode 100644
index 000000000000..cc353bec331b
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
@@ -0,0 +1,39 @@
+/*
+ * stmp378x: ECC8 register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_ECC8_BASE  (STMP3XXX_REGS_BASE + 0x8000)
+#define REGS_ECC8_PHYS  0x80008000
+#define REGS_ECC8_SIZE  0x2000
+#define HW_ECC8_CTRL            0x0
+#define BM_ECC8_CTRL_COMPLETE_IRQ       0x00000001
+#define BP_ECC8_CTRL_COMPLETE_IRQ       0
+#define BM_ECC8_CTRL_COMPLETE_IRQ_EN    0x00000100
+#define BM_ECC8_CTRL_AHBM_SFTRST        0x20000000
+#define HW_ECC8_STATUS0         0x10
+#define BM_ECC8_STATUS0_UNCORRECTABLE   0x00000004
+#define BM_ECC8_STATUS0_CORRECTED       0x00000008
+#define BM_ECC8_STATUS0_STATUS_AUX      0x00000F00
+#define BP_ECC8_STATUS0_STATUS_AUX      8
+#define BM_ECC8_STATUS0_COMPLETED_CE    0x000F0000
+#define BP_ECC8_STATUS0_COMPLETED_CE    16
+#define HW_ECC8_STATUS1         0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
new file mode 100644
index 000000000000..98773fc33d7b
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
@@ -0,0 +1,25 @@
+/*
+ * stmp378x: EMI register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_EMI_BASE   (STMP3XXX_REGS_BASE + 0x20000)
+#define REGS_EMI_PHYS   0x80020000
+#define REGS_EMI_SIZE   0x2000
+#define HW_EMI_STAT             0x10
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
new file mode 100644
index 000000000000..2cc8bbe91687
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
@@ -0,0 +1,78 @@
+/*
+ * stmp378x: GPMI register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_GPMI_BASE  (STMP3XXX_REGS_BASE + 0xC000)
+#define REGS_GPMI_PHYS  0x8000C000
+#define REGS_GPMI_SIZE  0x2000
+#define HW_GPMI_CTRL0           0x0
+#define BM_GPMI_CTRL0_XFER_COUNT        0x0000FFFF
+#define BP_GPMI_CTRL0_XFER_COUNT        0
+#define BM_GPMI_CTRL0_CS        0x00300000
+#define BP_GPMI_CTRL0_CS        20
+#define BM_GPMI_CTRL0_LOCK_CS   0x00400000
+#define BM_GPMI_CTRL0_WORD_LENGTH       0x00800000
+#define BM_GPMI_CTRL0_ADDRESS      0x000E0000
+#define BP_GPMI_CTRL0_ADDRESS      17
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA  0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE   0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE   0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT      0x00010000
+#define BM_GPMI_CTRL0_COMMAND_MODE      0x03000000
+#define BP_GPMI_CTRL0_COMMAND_MODE      24
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE           0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_RUN       0x20000000
+#define BM_GPMI_CTRL0_CLKGATE   0x40000000
+#define BM_GPMI_CTRL0_SFTRST    0x80000000
+#define BM_GPMI_ECCCTRL_BUFFER_MASK     0x000001FF
+#define BP_GPMI_ECCCTRL_BUFFER_MASK     0
+#define BM_GPMI_ECCCTRL_ENABLE_ECC      0x00001000
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT                   0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT                   1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT                   2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT                   3
+#define HW_GPMI_CTRL1           0x60
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BP_GPMI_CTRL1_GPMI_MODE 0
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY       0x00000004
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ       0x00000200
+#define BM_GPMI_CTRL1_DEV_IRQ   0x00000400
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_BCH_MODE  0x00040000
+#define HW_GPMI_TIMING0         0x70
+#define BM_GPMI_TIMING0_DATA_SETUP      0x000000FF
+#define BP_GPMI_TIMING0_DATA_SETUP      0
+#define BM_GPMI_TIMING0_DATA_HOLD       0x0000FF00
+#define BP_GPMI_TIMING0_DATA_HOLD       8
+#define BM_GPMI_TIMING0_ADDRESS_SETUP   0x00FF0000
+#define BP_GPMI_TIMING0_ADDRESS_SETUP   16
+#define HW_GPMI_TIMING1         0x80
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xFFFF0000
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
new file mode 100644
index 000000000000..13a234c99433
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
@@ -0,0 +1,55 @@
+/*
+ * stmp378x: I2C register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_I2C_BASE   (STMP3XXX_REGS_BASE + 0x58000)
+#define REGS_I2C_PHYS   0x80058000
+#define REGS_I2C_SIZE   0x2000
+#define HW_I2C_CTRL0            0x0
+#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
+#define BP_I2C_CTRL0_XFER_COUNT 0
+#define BM_I2C_CTRL0_DIRECTION  0x00010000
+#define BM_I2C_CTRL0_MASTER_MODE        0x00020000
+#define BM_I2C_CTRL0_PRE_SEND_START     0x00080000
+#define BM_I2C_CTRL0_POST_SEND_STOP     0x00100000
+#define BM_I2C_CTRL0_RETAIN_CLOCK       0x00200000
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST   0x02000000
+#define BM_I2C_CTRL0_CLKGATE    0x40000000
+#define BM_I2C_CTRL0_SFTRST     0x80000000
+#define HW_I2C_TIMING0          0x10
+#define HW_I2C_TIMING1          0x20
+#define HW_I2C_TIMING2          0x30
+#define HW_I2C_CTRL1            0x40
+#define BM_I2C_CTRL1_SLAVE_IRQ  0x00000001
+#define BP_I2C_CTRL1_SLAVE_IRQ  0
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ     0x00000002
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ    0x00000004
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ     0x00000008
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ     0x00000010
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ   0x00000020
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ      0x00000040
+#define BM_I2C_CTRL1_BUS_FREE_IRQ       0x00000080
+#define BM_I2C_CTRL1_CLR_GOT_A_NAK      0x10000000
+#define HW_I2C_VERSION          0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
new file mode 100644
index 000000000000..f996e80f40e7
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
@@ -0,0 +1,45 @@
+/*
+ * stmp378x: ICOLL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_ICOLL
+#define _MACH_REGS_ICOLL
+#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
+#define REGS_ICOLL_PHYS 0x80000000
+#define REGS_ICOLL_SIZE 0x2000
+#define HW_ICOLL_VECTOR         0x0
+#define HW_ICOLL_LEVELACK       0x10
+#define BM_ICOLL_LEVELACK_IRQLEVELACK   0x0000000F
+#define BP_ICOLL_LEVELACK_IRQLEVELACK   0
+#define HW_ICOLL_CTRL           0x20
+#define BM_ICOLL_CTRL_CLKGATE   0x40000000
+#define BM_ICOLL_CTRL_SFTRST    0x80000000
+#define HW_ICOLL_STAT           0x70
+#define HW_ICOLL_INTERRUPTn     0x120
+#define HW_ICOLL_INTERRUPTn     0x120
+#define BM_ICOLL_INTERRUPTn_ENABLE      0x00000004
+#endif
diff --git a/arch/arm/mach-imx/include/mach/memory.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
index a93df7cba694..a5b4ef10fab8 100644
--- a/arch/arm/mach-imx/include/mach/memory.h
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
@@ -1,8 +1,8 @@
 /*
- *  arch/arm/mach-imx/include/mach/memory.h
+ * stmp378x: IR register definitions
 *
- *  Copyright (C) 1999 ARM Limited
+ * Copyright (c) 2008 Freescale Semiconductor
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -16,11 +16,8 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef __ASM_ARCH_MMU_H
+#define REGS_IR_BASE    (STMP3XXX_REGS_BASE + 0x78000)
-#define __ASM_ARCH_MMU_H
+#define REGS_IR_PHYS    0x80078000
+#define REGS_IR_SIZE    0x2000
-#define PHYS_OFFSET     UL(0x08000000)
-#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
new file mode 100644
index 000000000000..9cdbef4badc3
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
@@ -0,0 +1,195 @@
+/*
+ * stmp378x: LCDIF register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
+#define REGS_LCDIF_PHYS 0x80030000
+#define REGS_LCDIF_SIZE 0x2000
+#define HW_LCDIF_CTRL           0x0
+#define BM_LCDIF_CTRL_RUN       0x00000001
+#define BP_LCDIF_CTRL_RUN       0
+#define BM_LCDIF_CTRL_LCDIF_MASTER      0x00000020
+#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC       0x00000080
+#define BM_LCDIF_CTRL_WORD_LENGTH       0x00000300
+#define BP_LCDIF_CTRL_WORD_LENGTH       8
+#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
+#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
+#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE        0x0000C000
+#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE        14
+#define BM_LCDIF_CTRL_DATA_SELECT       0x00010000
+#define BM_LCDIF_CTRL_DOTCLK_MODE       0x00020000
+#define BM_LCDIF_CTRL_VSYNC_MODE        0x00040000
+#define BM_LCDIF_CTRL_BYPASS_COUNT      0x00080000
+#define BM_LCDIF_CTRL_DVI_MODE  0x00100000
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS    0x03E00000
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS    21
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR    0x04000000
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE       0x08000000
+#define BM_LCDIF_CTRL_CLKGATE   0x40000000
+#define BM_LCDIF_CTRL_SFTRST    0x80000000
+#define HW_LCDIF_CTRL1          0x10
+#define BM_LCDIF_CTRL1_RESET    0x00000001
+#define BP_LCDIF_CTRL1_RESET    0
+#define BM_LCDIF_CTRL1_MODE86   0x00000002
+#define BM_LCDIF_CTRL1_BUSY_ENABLE      0x00000004
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ   0x00000100
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ       0x00000200
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ    0x00000400
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ     0x00000800
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN        0x00001000
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT      0x000F0000
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT      16
+#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
+#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW     0x01000000
+#define HW_LCDIF_TRANSFER_COUNT 0x20
+#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
+#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
+#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
+#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
+#define HW_LCDIF_CUR_BUF        0x30
+#define HW_LCDIF_NEXT_BUF       0x40
+#define HW_LCDIF_TIMING         0x60
+#define HW_LCDIF_VDCTRL0        0x70
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH      0x0003FFFF
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH      0
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT      0x00200000
+#define BM_LCDIF_VDCTRL0_ENABLE_POL     0x01000000
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL     0x02000000
+#define BM_LCDIF_VDCTRL0_HSYNC_POL      0x04000000
+#define BM_LCDIF_VDCTRL0_VSYNC_POL      0x08000000
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB      0x20000000
+#define HW_LCDIF_VDCTRL1        0x80
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD   0xFFFFFFFF
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD   0
+#define HW_LCDIF_VDCTRL2        0x90
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD   0x0003FFFF
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD   0
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      0xFF000000
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      24
+#define HW_LCDIF_VDCTRL3        0xA0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0x0000FFFF
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0x0FFF0000
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    16
+#define HW_LCDIF_VDCTRL4        0xB0
+#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT        0x0003FFFF
+#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT        0
+#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON        0x00040000
+#define HW_LCDIF_DVICTRL0       0xC0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT   0x000003FF
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT   0
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT        0x000FFC00
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT        10
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT  0x7FF00000
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT  20
+#define HW_LCDIF_DVICTRL1       0xD0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
+#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
+#define BM_LCDIF_DVICTRL1_F1_END_LINE   0x000FFC00
+#define BP_LCDIF_DVICTRL1_F1_END_LINE   10
+#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
+#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
+#define HW_LCDIF_DVICTRL2       0xE0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE     0x000003FF
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE     0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE   0x000FFC00
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE   10
+#define BM_LCDIF_DVICTRL2_F2_END_LINE   0x3FF00000
+#define BP_LCDIF_DVICTRL2_F2_END_LINE   20
+#define HW_LCDIF_DVICTRL3       0xF0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE     0x000003FF
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE     0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE   0x03FF0000
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE   16
+#define HW_LCDIF_DVICTRL4       0x100
+#define BM_LCDIF_DVICTRL4_H_FILL_CNT    0x000000FF
+#define BP_LCDIF_DVICTRL4_H_FILL_CNT    0
+#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
+#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
+#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
+#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
+#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE  0xFF000000
+#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE  24
+#define HW_LCDIF_CSC_COEFF0     0x110
+#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER        0x00000003
+#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER        0
+#define BM_LCDIF_CSC_COEFF0_C0  0x03FF0000
+#define BP_LCDIF_CSC_COEFF0_C0  16
+#define HW_LCDIF_CSC_COEFF1     0x120
+#define BM_LCDIF_CSC_COEFF1_C1  0x000003FF
+#define BP_LCDIF_CSC_COEFF1_C1  0
+#define BM_LCDIF_CSC_COEFF1_C2  0x03FF0000
+#define BP_LCDIF_CSC_COEFF1_C2  16
+#define HW_LCDIF_CSC_COEFF2     0x130
+#define BM_LCDIF_CSC_COEFF2_C3  0x000003FF
+#define BP_LCDIF_CSC_COEFF2_C3  0
+#define BM_LCDIF_CSC_COEFF2_C4  0x03FF0000
+#define BP_LCDIF_CSC_COEFF2_C4  16
+#define HW_LCDIF_CSC_COEFF3     0x140
+#define BM_LCDIF_CSC_COEFF3_C5  0x000003FF
+#define BP_LCDIF_CSC_COEFF3_C5  0
+#define BM_LCDIF_CSC_COEFF3_C6  0x03FF0000
+#define BP_LCDIF_CSC_COEFF3_C6  16
+#define HW_LCDIF_CSC_COEFF4     0x150
+#define BM_LCDIF_CSC_COEFF4_C7  0x000003FF
+#define BP_LCDIF_CSC_COEFF4_C7  0
+#define BM_LCDIF_CSC_COEFF4_C8  0x03FF0000
+#define BP_LCDIF_CSC_COEFF4_C8  16
+#define HW_LCDIF_CSC_OFFSET     0x160
+#define BM_LCDIF_CSC_OFFSET_Y_OFFSET    0x000001FF
+#define BP_LCDIF_CSC_OFFSET_Y_OFFSET    0
+#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
+#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
+#define HW_LCDIF_CSC_LIMIT      0x170
+#define BM_LCDIF_CSC_LIMIT_Y_MAX        0x000000FF
+#define BP_LCDIF_CSC_LIMIT_Y_MAX        0
+#define BM_LCDIF_CSC_LIMIT_Y_MIN        0x0000FF00
+#define BP_LCDIF_CSC_LIMIT_Y_MIN        8
+#define BM_LCDIF_CSC_LIMIT_CBCR_MAX     0x00FF0000
+#define BP_LCDIF_CSC_LIMIT_CBCR_MAX     16
+#define BM_LCDIF_CSC_LIMIT_CBCR_MIN     0xFF000000
+#define BP_LCDIF_CSC_LIMIT_CBCR_MIN     24
+#define HW_LCDIF_STAT           0x1D0
+#define BM_LCDIF_STAT_TXFIFO_EMPTY      0x04000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
new file mode 100644
index 000000000000..cb8cb06f8277
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
@@ -0,0 +1,99 @@
+/*
+ * stmp378x: LRADC register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
+#define REGS_LRADC_PHYS 0x80050000
+#define REGS_LRADC_SIZE 0x2000
+#define HW_LRADC_CTRL0          0x0
+#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
+#define BP_LRADC_CTRL0_SCHEDULE 0
+#define BM_LRADC_CTRL0_XPLUS_ENABLE     0x00010000
+#define BM_LRADC_CTRL0_YPLUS_ENABLE     0x00020000
+#define BM_LRADC_CTRL0_XMINUS_ENABLE    0x00040000
+#define BM_LRADC_CTRL0_YMINUS_ENABLE    0x00080000
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x00100000
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
+#define BM_LRADC_CTRL0_CLKGATE  0x40000000
+#define BM_LRADC_CTRL0_SFTRST   0x80000000
+#define HW_LRADC_CTRL1          0x10
+#define BM_LRADC_CTRL1_LRADC0_IRQ       0x00000001
+#define BP_LRADC_CTRL1_LRADC0_IRQ       0
+#define BM_LRADC_CTRL1_LRADC5_IRQ       0x00000020
+#define BM_LRADC_CTRL1_LRADC6_IRQ       0x00000040
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN    0x00010000
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN    0x00200000
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN      0x01000000
+#define HW_LRADC_CTRL2          0x20
+#define BM_LRADC_CTRL2_BL_BRIGHTNESS    0x001F0000
+#define BP_LRADC_CTRL2_BL_BRIGHTNESS    16
+#define BM_LRADC_CTRL2_BL_MUX_SELECT    0x00200000
+#define BM_LRADC_CTRL2_BL_ENABLE        0x00400000
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO    0xFF000000
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO    24
+#define HW_LRADC_CTRL3          0x30
+#define BM_LRADC_CTRL3_CYCLE_TIME       0x00000300
+#define BP_LRADC_CTRL3_CYCLE_TIME       8
+#define HW_LRADC_STATUS         0x40
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x00000001
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
+#define HW_LRADC_CH0            (0x50 + 0 * 0x10)
+#define HW_LRADC_CH1            (0x50 + 1 * 0x10)
+#define HW_LRADC_CH2            (0x50 + 2 * 0x10)
+#define HW_LRADC_CH3            (0x50 + 3 * 0x10)
+#define HW_LRADC_CH4            (0x50 + 4 * 0x10)
+#define HW_LRADC_CH5            (0x50 + 5 * 0x10)
+#define HW_LRADC_CH6            (0x50 + 6 * 0x10)
+#define HW_LRADC_CH7            (0x50 + 7 * 0x10)
+#define HW_LRADC_CHn            0x50
+#define BM_LRADC_CHn_VALUE      0x0003FFFF
+#define BP_LRADC_CHn_VALUE      0
+#define BM_LRADC_CHn_NUM_SAMPLES        0x1F000000
+#define BP_LRADC_CHn_NUM_SAMPLES        24
+#define BM_LRADC_CHn_ACCUMULATE 0x20000000
+#define HW_LRADC_DELAY0         (0xD0 + 0 * 0x10)
+#define HW_LRADC_DELAY1         (0xD0 + 1 * 0x10)
+#define HW_LRADC_DELAY2         (0xD0 + 2 * 0x10)
+#define HW_LRADC_DELAY3         (0xD0 + 3 * 0x10)
+#define HW_LRADC_DELAYn         0xD0
+#define BM_LRADC_DELAYn_DELAY   0x000007FF
+#define BP_LRADC_DELAYn_DELAY   0
+#define BM_LRADC_DELAYn_LOOP_COUNT      0x0000F800
+#define BP_LRADC_DELAYn_LOOP_COUNT      11
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS  0x000F0000
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS  16
+#define BM_LRADC_DELAYn_KICK    0x00100000
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS  0xFF000000
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS  24
+#define HW_LRADC_CTRL4          0x140
+#define BM_LRADC_CTRL4_LRADC6SELECT     0x0F000000
+#define BP_LRADC_CTRL4_LRADC6SELECT     24
+#define BM_LRADC_CTRL4_LRADC7SELECT     0xF0000000
+#define BP_LRADC_CTRL4_LRADC7SELECT     28
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
new file mode 100644
index 000000000000..f0af64d9937e
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
@@ -0,0 +1,40 @@
+/*
+ * stmp378x: OCOTP register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
+#define REGS_OCOTP_PHYS 0x8002C000
+#define REGS_OCOTP_SIZE 0x2000
+#define HW_OCOTP_CTRL           0x0
+#define BM_OCOTP_CTRL_BUSY      0x00000100
+#define BM_OCOTP_CTRL_ERROR     0x00000200
+#define BM_OCOTP_CTRL_RD_BANK_OPEN      0x00001000
+#define BM_OCOTP_CTRL_RELOAD_SHADOWS    0x00002000
+#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
+#define BP_OCOTP_CTRL_WR_UNLOCK 16
+#define HW_OCOTP_DATA           0x10
+#define HW_OCOTP_CUST0          (0x20 + 0 * 0x10)
+#define HW_OCOTP_CUST1          (0x20 + 1 * 0x10)
+#define HW_OCOTP_CUST2          (0x20 + 2 * 0x10)
+#define HW_OCOTP_CUST3          (0x20 + 3 * 0x10)
+#define HW_OCOTP_CUSTn          0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
new file mode 100644
index 000000000000..50d90ea1b136
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
@@ -0,0 +1,90 @@
+/*
+ * stmp378x: PINCTRL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_PINCTRL
+#define _MACH_REGS_PINCTRL
+#define REGS_PINCTRL_BASE       (STMP3XXX_REGS_BASE + 0x18000)
+#define REGS_PINCTRL_PHYS       0x80018000
+#define REGS_PINCTRL_SIZE       0x2000
+#define HW_PINCTRL_MUXSEL0      0x100
+#define HW_PINCTRL_MUXSEL1      0x110
+#define HW_PINCTRL_MUXSEL2      0x120
+#define HW_PINCTRL_MUXSEL3      0x130
+#define HW_PINCTRL_MUXSEL4      0x140
+#define HW_PINCTRL_MUXSEL5      0x150
+#define HW_PINCTRL_MUXSEL6      0x160
+#define HW_PINCTRL_MUXSEL7      0x170
+#define HW_PINCTRL_DRIVE0       0x200
+#define HW_PINCTRL_DRIVE1       0x210
+#define HW_PINCTRL_DRIVE2       0x220
+#define HW_PINCTRL_DRIVE3       0x230
+#define HW_PINCTRL_DRIVE4       0x240
+#define HW_PINCTRL_DRIVE5       0x250
+#define HW_PINCTRL_DRIVE6       0x260
+#define HW_PINCTRL_DRIVE7       0x270
+#define HW_PINCTRL_DRIVE8       0x280
+#define HW_PINCTRL_DRIVE9       0x290
+#define HW_PINCTRL_DRIVE10      0x2A0
+#define HW_PINCTRL_DRIVE11      0x2B0
+#define HW_PINCTRL_DRIVE12      0x2C0
+#define HW_PINCTRL_DRIVE13      0x2D0
+#define HW_PINCTRL_DRIVE14      0x2E0
+#define HW_PINCTRL_PULL0        0x400
+#define HW_PINCTRL_PULL1        0x410
+#define HW_PINCTRL_PULL2        0x420
+#define HW_PINCTRL_PULL3        0x430
+#define HW_PINCTRL_DOUT0        0x500
+#define HW_PINCTRL_DOUT1        0x510
+#define HW_PINCTRL_DOUT2        0x520
+#define HW_PINCTRL_DIN0         0x600
+#define HW_PINCTRL_DIN1         0x610
+#define HW_PINCTRL_DIN2         0x620
+#define HW_PINCTRL_DOE0         0x700
+#define HW_PINCTRL_DOE1         0x710
+#define HW_PINCTRL_DOE2         0x720
+#define HW_PINCTRL_PIN2IRQ0     0x800
+#define HW_PINCTRL_PIN2IRQ1     0x810
+#define HW_PINCTRL_PIN2IRQ2     0x820
+#define HW_PINCTRL_IRQEN0       0x900
+#define HW_PINCTRL_IRQEN1       0x910
+#define HW_PINCTRL_IRQEN2       0x920
+#define HW_PINCTRL_IRQLEVEL0    0xA00
+#define HW_PINCTRL_IRQLEVEL1    0xA10
+#define HW_PINCTRL_IRQLEVEL2    0xA20
+#define HW_PINCTRL_IRQPOL0      0xB00
+#define HW_PINCTRL_IRQPOL1      0xB10
+#define HW_PINCTRL_IRQPOL2      0xB20
+#define HW_PINCTRL_IRQSTAT0     0xC00
+#define HW_PINCTRL_IRQSTAT1     0xC10
+#define HW_PINCTRL_IRQSTAT2     0xC20
+#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h
new file mode 100644
index 000000000000..e454c830f076
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-power.h
@@ -0,0 +1,63 @@
+/*
+ * stmp378x: POWER register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_POWER
+#define _MACH_REGS_POWER
+#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
+#define REGS_POWER_PHYS 0x80044000
+#define REGS_POWER_SIZE 0x2000
+#define HW_POWER_CTRL           0x0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO      0x00000001
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO      0
+#define BM_POWER_CTRL_ENIRQ_PSWITCH     0x00020000
+#define BM_POWER_CTRL_PSWITCH_IRQ       0x00100000
+#define BM_POWER_CTRL_CLKGATE   0x40000000
+#define HW_POWER_5VCTRL         0x10
+#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT    0x00000040
+#define HW_POWER_MINPWR         0x20
+#define HW_POWER_CHARGE         0x30
+#define HW_POWER_VDDDCTRL       0x40
+#define HW_POWER_VDDACTRL       0x50
+#define HW_POWER_VDDIOCTRL      0x60
+#define BM_POWER_VDDIOCTRL_TRG  0x0000001F
+#define BP_POWER_VDDIOCTRL_TRG  0
+#define HW_POWER_STS            0xC0
+#define BM_POWER_STS_VBUSVALID  0x00000002
+#define BM_POWER_STS_BVALID     0x00000004
+#define BM_POWER_STS_AVALID     0x00000008
+#define BM_POWER_STS_DC_OK      0x00000200
+#define HW_POWER_RESET          0x100
+#define HW_POWER_DEBUG          0x110
+#define BM_POWER_DEBUG_BVALIDPIOLOCK    0x00000002
+#define BM_POWER_DEBUG_AVALIDPIOLOCK    0x00000004
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
+#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
new file mode 100644
index 000000000000..0d0f9e56ec77
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
@@ -0,0 +1,53 @@
+/*
+ * stmp378x: PWM register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_PWM_BASE   (STMP3XXX_REGS_BASE + 0x64000)
+#define REGS_PWM_PHYS   0x80064000
+#define REGS_PWM_SIZE   0x2000
+#define HW_PWM_CTRL             0x0
+#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
+#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE        0x00000020
+#define HW_PWM_ACTIVE0          (0x10 + 0 * 0x20)
+#define HW_PWM_ACTIVE1          (0x10 + 1 * 0x20)
+#define HW_PWM_ACTIVE2          (0x10 + 2 * 0x20)
+#define HW_PWM_ACTIVE3          (0x10 + 3 * 0x20)
+#define HW_PWM_ACTIVEn          0x10
+#define BM_PWM_ACTIVEn_ACTIVE   0x0000FFFF
+#define BP_PWM_ACTIVEn_ACTIVE   0
+#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
+#define BP_PWM_ACTIVEn_INACTIVE 16
+#define HW_PWM_PERIOD0          (0x20 + 0 * 0x20)
+#define HW_PWM_PERIOD1          (0x20 + 1 * 0x20)
+#define HW_PWM_PERIOD2          (0x20 + 2 * 0x20)
+#define HW_PWM_PERIOD3          (0x20 + 3 * 0x20)
+#define HW_PWM_PERIODn          0x20
+#define BM_PWM_PERIODn_PERIOD   0x0000FFFF
+#define BP_PWM_PERIODn_PERIOD   0
+#define BM_PWM_PERIODn_ACTIVE_STATE     0x00030000
+#define BP_PWM_PERIODn_ACTIVE_STATE     16
+#define BM_PWM_PERIODn_INACTIVE_STATE   0x000C0000
+#define BP_PWM_PERIODn_INACTIVE_STATE   18
+#define BM_PWM_PERIODn_CDIV     0x00700000
+#define BP_PWM_PERIODn_CDIV     20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
new file mode 100644
index 000000000000..54d297896de8
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
@@ -0,0 +1,140 @@
+/*
+ * stmp378x: PXP register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_PXP_BASE   (STMP3XXX_REGS_BASE + 0x2A000)
+#define REGS_PXP_PHYS   0x8002A000
+#define REGS_PXP_SIZE   0x2000
+#define HW_PXP_CTRL             0x0
+#define BM_PXP_CTRL_ENABLE      0x00000001
+#define BP_PXP_CTRL_ENABLE      0
+#define BM_PXP_CTRL_IRQ_ENABLE  0x00000002
+#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT   0x000000F0
+#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT   4
+#define BM_PXP_CTRL_ROTATE      0x00000300
+#define BP_PXP_CTRL_ROTATE      8
+#define BM_PXP_CTRL_HFLIP       0x00000400
+#define BM_PXP_CTRL_VFLIP       0x00000800
+#define BM_PXP_CTRL_S0_FORMAT   0x0000F000
+#define BP_PXP_CTRL_S0_FORMAT   12
+#define BM_PXP_CTRL_SCALE       0x00040000
+#define BM_PXP_CTRL_CROP        0x00080000
+#define HW_PXP_STAT             0x10
+#define BM_PXP_STAT_IRQ         0x00000001
+#define BP_PXP_STAT_IRQ         0
+#define HW_PXP_RGBBUF           0x20
+#define HW_PXP_RGBSIZE          0x40
+#define BM_PXP_RGBSIZE_HEIGHT   0x00000FFF
+#define BP_PXP_RGBSIZE_HEIGHT   0
+#define BM_PXP_RGBSIZE_WIDTH    0x00FFF000
+#define BP_PXP_RGBSIZE_WIDTH    12
+#define HW_PXP_S0BUF            0x50
+#define HW_PXP_S0UBUF           0x60
+#define HW_PXP_S0VBUF           0x70
+#define HW_PXP_S0PARAM          0x80
+#define BM_PXP_S0PARAM_HEIGHT   0x000000FF
+#define BP_PXP_S0PARAM_HEIGHT   0
+#define BM_PXP_S0PARAM_WIDTH    0x0000FF00
+#define BP_PXP_S0PARAM_WIDTH    8
+#define BM_PXP_S0PARAM_YBASE    0x00FF0000
+#define BP_PXP_S0PARAM_YBASE    16
+#define BM_PXP_S0PARAM_XBASE    0xFF000000
+#define BP_PXP_S0PARAM_XBASE    24
+#define HW_PXP_S0BACKGROUND     0x90
+#define HW_PXP_S0CROP           0xA0
+#define BM_PXP_S0CROP_HEIGHT    0x000000FF
+#define BP_PXP_S0CROP_HEIGHT    0
+#define BM_PXP_S0CROP_WIDTH     0x0000FF00
+#define BP_PXP_S0CROP_WIDTH     8
+#define BM_PXP_S0CROP_YBASE     0x00FF0000
+#define BP_PXP_S0CROP_YBASE     16
+#define BM_PXP_S0CROP_XBASE     0xFF000000
+#define BP_PXP_S0CROP_XBASE     24
+#define HW_PXP_S0SCALE          0xB0
+#define BM_PXP_S0SCALE_XSCALE   0x00003FFF
+#define BP_PXP_S0SCALE_XSCALE   0
+#define BM_PXP_S0SCALE_YSCALE   0x3FFF0000
+#define BP_PXP_S0SCALE_YSCALE   16
+#define HW_PXP_CSCCOEFF0        0xD0
+#define HW_PXP_CSCCOEFF1        0xE0
+#define HW_PXP_CSCCOEFF2        0xF0
+#define HW_PXP_S0COLORKEYLOW    0x180
+#define HW_PXP_S0COLORKEYHIGH   0x190
+#define HW_PXP_OL0              (0x200 + 0 * 0x40)
+#define HW_PXP_OL1              (0x200 + 1 * 0x40)
+#define HW_PXP_OL2              (0x200 + 2 * 0x40)
+#define HW_PXP_OL3              (0x200 + 3 * 0x40)
+#define HW_PXP_OL4              (0x200 + 4 * 0x40)
+#define HW_PXP_OL5              (0x200 + 5 * 0x40)
+#define HW_PXP_OL6              (0x200 + 6 * 0x40)
+#define HW_PXP_OL7              (0x200 + 7 * 0x40)
+#define HW_PXP_OLn              0x200
+#define HW_PXP_OL0SIZE          (0x210 + 0 * 0x40)
+#define HW_PXP_OL1SIZE          (0x210 + 1 * 0x40)
+#define HW_PXP_OL2SIZE          (0x210 + 2 * 0x40)
+#define HW_PXP_OL3SIZE          (0x210 + 3 * 0x40)
+#define HW_PXP_OL4SIZE          (0x210 + 4 * 0x40)
+#define HW_PXP_OL5SIZE          (0x210 + 5 * 0x40)
+#define HW_PXP_OL6SIZE          (0x210 + 6 * 0x40)
+#define HW_PXP_OL7SIZE          (0x210 + 7 * 0x40)
+#define HW_PXP_OLnSIZE          0x210
+#define BM_PXP_OLnSIZE_HEIGHT   0x000000FF
+#define BP_PXP_OLnSIZE_HEIGHT   0
+#define BM_PXP_OLnSIZE_WIDTH    0x0000FF00
+#define BP_PXP_OLnSIZE_WIDTH    8
+#define HW_PXP_OL0PARAM         (0x220 + 0 * 0x40)
+#define HW_PXP_OL1PARAM         (0x220 + 1 * 0x40)
+#define HW_PXP_OL2PARAM         (0x220 + 2 * 0x40)
+#define HW_PXP_OL3PARAM         (0x220 + 3 * 0x40)
+#define HW_PXP_OL4PARAM         (0x220 + 4 * 0x40)
+#define HW_PXP_OL5PARAM         (0x220 + 5 * 0x40)
+#define HW_PXP_OL6PARAM         (0x220 + 6 * 0x40)
+#define HW_PXP_OL7PARAM         (0x220 + 7 * 0x40)
+#define HW_PXP_OLnPARAM         0x220
+#define BM_PXP_OLnPARAM_ENABLE  0x00000001
+#define BP_PXP_OLnPARAM_ENABLE  0
+#define BM_PXP_OLnPARAM_ALPHA_CNTL      0x00000006
+#define BP_PXP_OLnPARAM_ALPHA_CNTL      1
+#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
+#define BM_PXP_OLnPARAM_FORMAT  0x000000F0
+#define BP_PXP_OLnPARAM_FORMAT  4
+#define BM_PXP_OLnPARAM_ALPHA   0x0000FF00
+#define BP_PXP_OLnPARAM_ALPHA   8
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..b8dbd6742d98
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
@@ -0,0 +1,59 @@
+/*
+ * stmp378x: RTC register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_RTC_BASE   (STMP3XXX_REGS_BASE + 0x5C000)
+#define REGS_RTC_PHYS   0x8005C000
+#define REGS_RTC_SIZE   0x2000
+#define HW_RTC_CTRL             0x0
+#define BM_RTC_CTRL_ALARM_IRQ_EN        0x00000001
+#define BP_RTC_CTRL_ALARM_IRQ_EN        0
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN      0x00000002
+#define BM_RTC_CTRL_ALARM_IRQ   0x00000004
+#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
+#define BM_RTC_CTRL_WATCHDOGEN  0x00000010
+#define HW_RTC_STAT             0x10
+#define BM_RTC_STAT_NEW_REGS    0x0000FF00
+#define BP_RTC_STAT_NEW_REGS    8
+#define BM_RTC_STAT_STALE_REGS  0x00FF0000
+#define BP_RTC_STAT_STALE_REGS  16
+#define BM_RTC_STAT_RTC_PRESENT 0x80000000
+#define HW_RTC_SECONDS          0x30
+#define HW_RTC_ALARM            0x40
+#define HW_RTC_WATCHDOG         0x50
+#define HW_RTC_PERSISTENT0      0x60
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN        0x00000002
+#define BM_RTC_PERSISTENT0_ALARM_EN     0x00000004
+#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      0x00000010
+#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      0x00000020
+#define BM_RTC_PERSISTENT0_ALARM_WAKE   0x00000080
+#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
+#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
+#define HW_RTC_PERSISTENT1      0x70
+#define BM_RTC_PERSISTENT1_GENERAL      0xFFFFFFFF
+#define BP_RTC_PERSISTENT1_GENERAL      0
+#define HW_RTC_VERSION          0xD0
diff --git a/arch/arm/mach-imx/include/mach/vmalloc.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
index 7d7cb0bde3e8..6df41762c2a3 100644
--- a/arch/arm/mach-imx/include/mach/vmalloc.h
+++ b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
@@ -1,7 +1,8 @@
 /*
- *  arch/arm/mach-imx/include/mach/vmalloc.h
+ * stmp378x: SAIF register definitions
 *
- *  Copyright (C) 2000 Russell King.
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -15,6 +16,6 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define REGS_SAIF_SIZE  0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
new file mode 100644
index 000000000000..801539848c28
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
@@ -0,0 +1,49 @@
+/*
+ * stmp378x: SPDIF register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
+#define REGS_SPDIF_PHYS 0x80054000
+#define REGS_SPDIF_SIZE 0x2000
+#define HW_SPDIF_CTRL           0x0
+#define BM_SPDIF_CTRL_RUN       0x00000001
+#define BP_SPDIF_CTRL_RUN       0
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ        0x00000008
+#define BM_SPDIF_CTRL_WORD_LENGTH       0x00000010
+#define BM_SPDIF_CTRL_CLKGATE   0x40000000
+#define BM_SPDIF_CTRL_SFTRST    0x80000000
+#define HW_SPDIF_STAT           0x10
+#define HW_SPDIF_FRAMECTRL      0x20
+#define HW_SPDIF_SRR            0x30
+#define BM_SPDIF_SRR_RATE       0x000FFFFF
+#define BP_SPDIF_SRR_RATE       0
+#define BM_SPDIF_SRR_BASEMULT   0x70000000
+#define BP_SPDIF_SRR_BASEMULT   28
+#define HW_SPDIF_DEBUG          0x40
+#define HW_SPDIF_DATA           0x50
+#define HW_SPDIF_VERSION        0x60
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
new file mode 100644
index 000000000000..28aacf0f58ed
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
@@ -0,0 +1,102 @@
+/*
+ * stmp378x: SSP register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_SSP1_BASE  (STMP3XXX_REGS_BASE + 0x10000)
+#define REGS_SSP1_PHYS  0x80010000
+#define REGS_SSP2_BASE  (STMP3XXX_REGS_BASE + 0x34000)
+#define REGS_SSP2_PHYS  0x80034000
+#define REGS_SSP_SIZE   0x2000
+#define HW_SSP_CTRL0            0x0
+#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
+#define BP_SSP_CTRL0_XFER_COUNT 0
+#define BM_SSP_CTRL0_ENABLE     0x00010000
+#define BM_SSP_CTRL0_GET_RESP   0x00020000
+#define BM_SSP_CTRL0_LONG_RESP  0x00080000
+#define BM_SSP_CTRL0_WAIT_FOR_CMD       0x00100000
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ       0x00200000
+#define BM_SSP_CTRL0_BUS_WIDTH  0x00C00000
+#define BP_SSP_CTRL0_BUS_WIDTH  22
+#define BM_SSP_CTRL0_DATA_XFER  0x01000000
+#define BM_SSP_CTRL0_READ       0x02000000
+#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
+#define BM_SSP_CTRL0_LOCK_CS    0x08000000
+#define BM_SSP_CTRL0_RUN        0x20000000
+#define BM_SSP_CTRL0_CLKGATE    0x40000000
+#define BM_SSP_CTRL0_SFTRST     0x80000000
+#define HW_SSP_CMD0             0x10
+#define BM_SSP_CMD0_CMD         0x000000FF
+#define BP_SSP_CMD0_CMD         0
+#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
+#define BP_SSP_CMD0_BLOCK_COUNT 8
+#define BM_SSP_CMD0_BLOCK_SIZE  0x000F0000
+#define BP_SSP_CMD0_BLOCK_SIZE  16
+#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
+#define BM_SSP_CMD1_CMD_ARG     0xFFFFFFFF
+#define BP_SSP_CMD1_CMD_ARG     0
+#define HW_SSP_TIMING           0x50
+#define BM_SSP_TIMING_CLOCK_RATE        0x000000FF
+#define BP_SSP_TIMING_CLOCK_RATE        0
+#define BM_SSP_TIMING_CLOCK_DIVIDE      0x0000FF00
+#define BP_SSP_TIMING_CLOCK_DIVIDE      8
+#define BM_SSP_TIMING_TIMEOUT   0xFFFF0000
+#define BP_SSP_TIMING_TIMEOUT   16
+#define HW_SSP_CTRL1            0x60
+#define BM_SSP_CTRL1_SSP_MODE   0x0000000F
+#define BP_SSP_CTRL1_SSP_MODE   0
+#define BM_SSP_CTRL1_WORD_LENGTH        0x000000F0
+#define BP_SSP_CTRL1_WORD_LENGTH        4
+#define BM_SSP_CTRL1_POLARITY   0x00000200
+#define BM_SSP_CTRL1_PHASE      0x00000400
+#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ   0x00008000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x00010000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ   0x00020000
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ  0x00200000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN    0x00400000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ       0x00800000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x01000000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ   0x02000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x04000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ   0x08000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN    0x10000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ       0x20000000
+#define BM_SSP_CTRL1_SDIO_IRQ   0x80000000
+#define HW_SSP_DATA             0x70
+#define HW_SSP_SDRESP0          0x80
+#define HW_SSP_SDRESP1          0x90
+#define HW_SSP_SDRESP2          0xA0
+#define HW_SSP_SDRESP3          0xB0
+#define HW_SSP_STATUS           0xC0
+#define BM_SSP_STATUS_FIFO_EMPTY        0x00000020
+#define BM_SSP_STATUS_TIMEOUT   0x00001000
+#define BM_SSP_STATUS_RESP_TIMEOUT      0x00004000
+#define BM_SSP_STATUS_RESP_ERR  0x00008000
+#define BM_SSP_STATUS_RESP_CRC_ERR      0x00010000
+#define BM_SSP_STATUS_CARD_DETECT       0x10000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
new file mode 100644
index 000000000000..08343a8b5566
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
@@ -0,0 +1,23 @@
+/*
+ * stmp378x: SYDMA register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
+#define REGS_SYDMA_PHYS 0x80026000
+#define REGS_SYDMA_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
new file mode 100644
index 000000000000..b5527957c67f
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
@@ -0,0 +1,68 @@
+/*
+ * stmp378x: TIMROT register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_TIMROT
+#define _MACH_REGS_TIMROT
+#define REGS_TIMROT_BASE        (STMP3XXX_REGS_BASE + 0x68000)
+#define REGS_TIMROT_PHYS        0x80068000
+#define REGS_TIMROT_SIZE        0x2000
+#define HW_TIMROT_ROTCTRL       0x0
+#define BM_TIMROT_ROTCTRL_SELECT_A      0x00000007
+#define BP_TIMROT_ROTCTRL_SELECT_A      0
+#define BM_TIMROT_ROTCTRL_SELECT_B      0x00000070
+#define BP_TIMROT_ROTCTRL_SELECT_B      4
+#define BM_TIMROT_ROTCTRL_POLARITY_A    0x00000100
+#define BM_TIMROT_ROTCTRL_POLARITY_B    0x00000200
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE    0x00000C00
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE    10
+#define BM_TIMROT_ROTCTRL_RELATIVE      0x00001000
+#define BM_TIMROT_ROTCTRL_DIVIDER       0x003F0000
+#define BP_TIMROT_ROTCTRL_DIVIDER       16
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
+#define BM_TIMROT_ROTCTRL_CLKGATE       0x40000000
+#define BM_TIMROT_ROTCTRL_SFTRST        0x80000000
+#define HW_TIMROT_ROTCOUNT      0x10
+#define BM_TIMROT_ROTCOUNT_UPDOWN       0x0000FFFF
+#define BP_TIMROT_ROTCOUNT_UPDOWN       0
+#define HW_TIMROT_TIMCTRL0      (0x20 + 0 * 0x20)
+#define HW_TIMROT_TIMCTRL1      (0x20 + 1 * 0x20)
+#define HW_TIMROT_TIMCTRL2      (0x20 + 2 * 0x20)
+#define HW_TIMROT_TIMCTRLn      0x20
+#define BM_TIMROT_TIMCTRLn_SELECT       0x0000000F
+#define BP_TIMROT_TIMCTRLn_SELECT       0
+#define BM_TIMROT_TIMCTRLn_PRESCALE     0x00000030
+#define BP_TIMROT_TIMCTRLn_PRESCALE     4
+#define BM_TIMROT_TIMCTRLn_RELOAD       0x00000040
+#define BM_TIMROT_TIMCTRLn_UPDATE       0x00000080
+#define BM_TIMROT_TIMCTRLn_IRQ_EN       0x00004000
+#define BM_TIMROT_TIMCTRLn_IRQ  0x00008000
+#define HW_TIMROT_TIMCOUNT0     (0x30 + 0 * 0x20)
+#define HW_TIMROT_TIMCOUNT1     (0x30 + 1 * 0x20)
+#define HW_TIMROT_TIMCOUNT2     (0x30 + 2 * 0x20)
+#define HW_TIMROT_TIMCOUNTn     0x30
+#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
new file mode 100644
index 000000000000..7f895cb34350
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
@@ -0,0 +1,67 @@
+/*
+ * stmp378x: TVENC register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
+#define REGS_TVENC_PHYS 0x80038000
+#define REGS_TVENC_SIZE 0x2000
+#define HW_TVENC_CTRL           0x0
+#define BM_TVENC_CTRL_CLKGATE   0x40000000
+#define BM_TVENC_CTRL_SFTRST    0x80000000
+#define HW_TVENC_CONFIG         0x10
+#define BM_TVENC_CONFIG_ENCD_MODE       0x00000007
+#define BP_TVENC_CONFIG_ENCD_MODE       0
+#define BM_TVENC_CONFIG_SYNC_MODE       0x00000070
+#define BP_TVENC_CONFIG_SYNC_MODE       4
+#define BM_TVENC_CONFIG_FSYNC_PHS       0x00000200
+#define BM_TVENC_CONFIG_CGAIN   0x0000C000
+#define BP_TVENC_CONFIG_CGAIN   14
+#define BM_TVENC_CONFIG_YGAIN_SEL       0x00030000
+#define BP_TVENC_CONFIG_YGAIN_SEL       16
+#define BM_TVENC_CONFIG_PAL_SHAPE       0x00100000
+#define HW_TVENC_SYNCOFFSET     0x30
+#define HW_TVENC_COLORSUB0      0xC0
+#define HW_TVENC_COLORBURST     0x140
+#define BM_TVENC_COLORBURST_PBA 0x00FF0000
+#define BP_TVENC_COLORBURST_PBA 16
+#define BM_TVENC_COLORBURST_NBA 0xFF000000
+#define BP_TVENC_COLORBURST_NBA 24
+#define HW_TVENC_MACROVISION0   0x150
+#define HW_TVENC_MACROVISION1   0x160
+#define HW_TVENC_MACROVISION2   0x170
+#define HW_TVENC_MACROVISION3   0x180
+#define HW_TVENC_MACROVISION4   0x190
+#define HW_TVENC_DACCTRL        0x1A0
+#define BM_TVENC_DACCTRL_RVAL   0x00000070
+#define BP_TVENC_DACCTRL_RVAL   4
+#define BM_TVENC_DACCTRL_DUMP_TOVDD1    0x00000100
+#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
+#define BM_TVENC_DACCTRL_GAINUP 0x00040000
+#define BM_TVENC_DACCTRL_GAINDN 0x00080000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
new file mode 100644
index 000000000000..a251e68bb3a1
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
@@ -0,0 +1,87 @@
+/*
+ * stmp378x: UARTAPP register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_UARTAPP1_BASE      (STMP3XXX_REGS_BASE + 0x6C000)
+#define REGS_UARTAPP1_PHYS      0x8006C000
+#define REGS_UARTAPP2_BASE      (STMP3XXX_REGS_BASE + 0x6E000)
+#define REGS_UARTAPP2_PHYS      0x8006E000
+#define REGS_UARTAPP_SIZE       0x2000
+#define HW_UARTAPP_CTRL0        0x0
+#define BM_UARTAPP_CTRL0_XFER_COUNT     0x0000FFFF
+#define BP_UARTAPP_CTRL0_XFER_COUNT     0
+#define BM_UARTAPP_CTRL0_RXTIMEOUT      0x07FF0000
+#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x08000000
+#define BM_UARTAPP_CTRL0_RUN    0x20000000
+#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
+#define BM_UARTAPP_CTRL1_XFER_COUNT     0x0000FFFF
+#define BP_UARTAPP_CTRL1_XFER_COUNT     0
+#define BM_UARTAPP_CTRL1_RUN    0x10000000
+#define HW_UARTAPP_CTRL2        0x20
+#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
+#define BP_UARTAPP_CTRL2_UARTEN 0
+#define BM_UARTAPP_CTRL2_TXE    0x00000100
+#define BM_UARTAPP_CTRL2_RXE    0x00000200
+#define BM_UARTAPP_CTRL2_RTS    0x00000800
+#define BM_UARTAPP_CTRL2_RTSEN  0x00004000
+#define BM_UARTAPP_CTRL2_CTSEN  0x00008000
+#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
+#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
+#define BM_UARTAPP_CTRL2_DMAONERR       0x04000000
+#define HW_UARTAPP_LINECTRL     0x30
+#define BM_UARTAPP_LINECTRL_BRK 0x00000001
+#define BP_UARTAPP_LINECTRL_BRK 0
+#define BM_UARTAPP_LINECTRL_PEN 0x00000002
+#define BM_UARTAPP_LINECTRL_EPS 0x00000004
+#define BM_UARTAPP_LINECTRL_STP2        0x00000008
+#define BM_UARTAPP_LINECTRL_FEN 0x00000010
+#define BM_UARTAPP_LINECTRL_WLEN        0x00000060
+#define BP_UARTAPP_LINECTRL_WLEN        5
+#define BM_UARTAPP_LINECTRL_SPS 0x00000080
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC        0x00003F00
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC        8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
+#define HW_UARTAPP_INTR         0x50
+#define BM_UARTAPP_INTR_CTSMIS  0x00000002
+#define BM_UARTAPP_INTR_RTIS    0x00000040
+#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
+#define BM_UARTAPP_INTR_RXIEN   0x00100000
+#define BM_UARTAPP_INTR_RTIEN   0x00400000
+#define HW_UARTAPP_DATA         0x60
+#define HW_UARTAPP_STAT         0x70
+#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
+#define BP_UARTAPP_STAT_RXCOUNT 0
+#define BM_UARTAPP_STAT_FERR    0x00010000
+#define BM_UARTAPP_STAT_PERR    0x00020000
+#define BM_UARTAPP_STAT_BERR    0x00040000
+#define BM_UARTAPP_STAT_OERR    0x00080000
+#define BM_UARTAPP_STAT_RXFE    0x01000000
+#define BM_UARTAPP_STAT_TXFF    0x02000000
+#define BM_UARTAPP_STAT_TXFE    0x08000000
+#define BM_UARTAPP_STAT_CTS     0x10000000
+#define HW_UARTAPP_VERSION      0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
new file mode 100644
index 000000000000..b810deb552a9
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
@@ -0,0 +1,268 @@
+/*
+ * stmp378x: UARTDBG register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_UARTDBG_BASE       (STMP3XXX_REGS_BASE + 0x70000)
+#define REGS_UARTDBG_PHYS       0x80070000
+#define REGS_UARTDBG_SIZE       0x2000
+#define HW_UARTDBGDR 0x00000000
+#define BP_UARTDBGDR_UNAVAILABLE      16
+#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGDR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
+#define BP_UARTDBGDR_RESERVED      12
+#define BM_UARTDBGDR_RESERVED 0x0000F000
+#define BF_UARTDBGDR_RESERVED(v)  \
+        (((v) << 12) & BM_UARTDBGDR_RESERVED)
+#define BM_UARTDBGDR_OE 0x00000800
+#define BM_UARTDBGDR_BE 0x00000400
+#define BM_UARTDBGDR_PE 0x00000200
+#define BM_UARTDBGDR_FE 0x00000100
+#define BP_UARTDBGDR_DATA      0
+#define BM_UARTDBGDR_DATA 0x000000FF
+#define BF_UARTDBGDR_DATA(v)  \
+        (((v) << 0) & BM_UARTDBGDR_DATA)
+#define HW_UARTDBGRSR_ECR 0x00000004
+#define BP_UARTDBGRSR_ECR_UNAVAILABLE      8
+#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
+        (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
+#define BP_UARTDBGRSR_ECR_EC      4
+#define BM_UARTDBGRSR_ECR_EC 0x000000F0
+#define BF_UARTDBGRSR_ECR_EC(v)  \
+        (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
+#define BM_UARTDBGRSR_ECR_OE 0x00000008
+#define BM_UARTDBGRSR_ECR_BE 0x00000004
+#define BM_UARTDBGRSR_ECR_PE 0x00000002
+#define BM_UARTDBGRSR_ECR_FE 0x00000001
+#define HW_UARTDBGFR 0x00000018
+#define BP_UARTDBGFR_UNAVAILABLE      16
+#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGFR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
+#define BP_UARTDBGFR_RESERVED      9
+#define BM_UARTDBGFR_RESERVED 0x0000FE00
+#define BF_UARTDBGFR_RESERVED(v)  \
+        (((v) << 9) & BM_UARTDBGFR_RESERVED)
+#define BM_UARTDBGFR_RI 0x00000100
+#define BM_UARTDBGFR_TXFE 0x00000080
+#define BM_UARTDBGFR_RXFF 0x00000040
+#define BM_UARTDBGFR_TXFF 0x00000020
+#define BM_UARTDBGFR_RXFE 0x00000010
+#define BM_UARTDBGFR_BUSY 0x00000008
+#define BM_UARTDBGFR_DCD 0x00000004
+#define BM_UARTDBGFR_DSR 0x00000002
+#define BM_UARTDBGFR_CTS 0x00000001
+#define HW_UARTDBGILPR 0x00000020
+#define BP_UARTDBGILPR_UNAVAILABLE      8
+#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGILPR_UNAVAILABLE(v) \
+        (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
+#define BP_UARTDBGILPR_ILPDVSR      0
+#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
+#define BF_UARTDBGILPR_ILPDVSR(v)  \
+        (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
+#define HW_UARTDBGIBRD 0x00000024
+#define BP_UARTDBGIBRD_UNAVAILABLE      16
+#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
+#define BP_UARTDBGIBRD_BAUD_DIVINT      0
+#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
+#define BF_UARTDBGIBRD_BAUD_DIVINT(v)  \
+        (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
+#define HW_UARTDBGFBRD 0x00000028
+#define BP_UARTDBGFBRD_UNAVAILABLE      8
+#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
+        (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
+#define BP_UARTDBGFBRD_RESERVED      6
+#define BM_UARTDBGFBRD_RESERVED 0x000000C0
+#define BF_UARTDBGFBRD_RESERVED(v)  \
+        (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
+#define BP_UARTDBGFBRD_BAUD_DIVFRAC      0
+#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
+#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v)  \
+        (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
+#define HW_UARTDBGLCR_H 0x0000002c
+#define BP_UARTDBGLCR_H_UNAVAILABLE      16
+#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
+#define BP_UARTDBGLCR_H_RESERVED      8
+#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
+#define BF_UARTDBGLCR_H_RESERVED(v)  \
+        (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
+#define BM_UARTDBGLCR_H_SPS 0x00000080
+#define BP_UARTDBGLCR_H_WLEN      5
+#define BM_UARTDBGLCR_H_WLEN 0x00000060
+#define BF_UARTDBGLCR_H_WLEN(v)  \
+        (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
+#define BM_UARTDBGLCR_H_FEN 0x00000010
+#define BM_UARTDBGLCR_H_STP2 0x00000008
+#define BM_UARTDBGLCR_H_EPS 0x00000004
+#define BM_UARTDBGLCR_H_PEN 0x00000002
+#define BM_UARTDBGLCR_H_BRK 0x00000001
+#define HW_UARTDBGCR 0x00000030
+#define BP_UARTDBGCR_UNAVAILABLE      16
+#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGCR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
+#define BM_UARTDBGCR_CTSEN 0x00008000
+#define BM_UARTDBGCR_RTSEN 0x00004000
+#define BM_UARTDBGCR_OUT2 0x00002000
+#define BM_UARTDBGCR_OUT1 0x00001000
+#define BM_UARTDBGCR_RTS 0x00000800
+#define BM_UARTDBGCR_DTR 0x00000400
+#define BM_UARTDBGCR_RXE 0x00000200
+#define BM_UARTDBGCR_TXE 0x00000100
+#define BM_UARTDBGCR_LBE 0x00000080
+#define BP_UARTDBGCR_RESERVED      3
+#define BM_UARTDBGCR_RESERVED 0x00000078
+#define BF_UARTDBGCR_RESERVED(v)  \
+        (((v) << 3) & BM_UARTDBGCR_RESERVED)
+#define BM_UARTDBGCR_SIRLP 0x00000004
+#define BM_UARTDBGCR_SIREN 0x00000002
+#define BM_UARTDBGCR_UARTEN 0x00000001
+#define HW_UARTDBGIFLS 0x00000034
+#define BP_UARTDBGIFLS_UNAVAILABLE      16
+#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
+#define BP_UARTDBGIFLS_RESERVED      6
+#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
+#define BF_UARTDBGIFLS_RESERVED(v)  \
+        (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
+#define BP_UARTDBGIFLS_RXIFLSEL      3
+#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
+#define BF_UARTDBGIFLS_RXIFLSEL(v)  \
+        (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
+#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY      0x0
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF       0x2
+#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5       0x5
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6       0x6
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7       0x7
+#define BP_UARTDBGIFLS_TXIFLSEL      0
+#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
+#define BF_UARTDBGIFLS_TXIFLSEL(v)  \
+        (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
+#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY    0x0
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF       0x2
+#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5       0x5
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6       0x6
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7       0x7
+#define HW_UARTDBGIMSC 0x00000038
+#define BP_UARTDBGIMSC_UNAVAILABLE      16
+#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
+#define BP_UARTDBGIMSC_RESERVED      11
+#define BM_UARTDBGIMSC_RESERVED 0x0000F800
+#define BF_UARTDBGIMSC_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
+#define BM_UARTDBGIMSC_OEIM 0x00000400
+#define BM_UARTDBGIMSC_BEIM 0x00000200
+#define BM_UARTDBGIMSC_PEIM 0x00000100
+#define BM_UARTDBGIMSC_FEIM 0x00000080
+#define BM_UARTDBGIMSC_RTIM 0x00000040
+#define BM_UARTDBGIMSC_TXIM 0x00000020
+#define BM_UARTDBGIMSC_RXIM 0x00000010
+#define BM_UARTDBGIMSC_DSRMIM 0x00000008
+#define BM_UARTDBGIMSC_DCDMIM 0x00000004
+#define BM_UARTDBGIMSC_CTSMIM 0x00000002
+#define BM_UARTDBGIMSC_RIMIM 0x00000001
+#define HW_UARTDBGRIS 0x0000003c
+#define BP_UARTDBGRIS_UNAVAILABLE      16
+#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGRIS_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
+#define BP_UARTDBGRIS_RESERVED      11
+#define BM_UARTDBGRIS_RESERVED 0x0000F800
+#define BF_UARTDBGRIS_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGRIS_RESERVED)
+#define BM_UARTDBGRIS_OERIS 0x00000400
+#define BM_UARTDBGRIS_BERIS 0x00000200
+#define BM_UARTDBGRIS_PERIS 0x00000100
+#define BM_UARTDBGRIS_FERIS 0x00000080
+#define BM_UARTDBGRIS_RTRIS 0x00000040
+#define BM_UARTDBGRIS_TXRIS 0x00000020
+#define BM_UARTDBGRIS_RXRIS 0x00000010
+#define BM_UARTDBGRIS_DSRRMIS 0x00000008
+#define BM_UARTDBGRIS_DCDRMIS 0x00000004
+#define BM_UARTDBGRIS_CTSRMIS 0x00000002
+#define BM_UARTDBGRIS_RIRMIS 0x00000001
+#define HW_UARTDBGMIS 0x00000040
+#define BP_UARTDBGMIS_UNAVAILABLE      16
+#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGMIS_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
+#define BP_UARTDBGMIS_RESERVED      11
+#define BM_UARTDBGMIS_RESERVED 0x0000F800
+#define BF_UARTDBGMIS_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGMIS_RESERVED)
+#define BM_UARTDBGMIS_OEMIS 0x00000400
+#define BM_UARTDBGMIS_BEMIS 0x00000200
+#define BM_UARTDBGMIS_PEMIS 0x00000100
+#define BM_UARTDBGMIS_FEMIS 0x00000080
+#define BM_UARTDBGMIS_RTMIS 0x00000040
+#define BM_UARTDBGMIS_TXMIS 0x00000020
+#define BM_UARTDBGMIS_RXMIS 0x00000010
+#define BM_UARTDBGMIS_DSRMMIS 0x00000008
+#define BM_UARTDBGMIS_DCDMMIS 0x00000004
+#define BM_UARTDBGMIS_CTSMMIS 0x00000002
+#define BM_UARTDBGMIS_RIMMIS 0x00000001
+#define HW_UARTDBGICR 0x00000044
+#define BP_UARTDBGICR_UNAVAILABLE      16
+#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGICR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
+#define BP_UARTDBGICR_RESERVED      11
+#define BM_UARTDBGICR_RESERVED 0x0000F800
+#define BF_UARTDBGICR_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGICR_RESERVED)
+#define BM_UARTDBGICR_OEIC 0x00000400
+#define BM_UARTDBGICR_BEIC 0x00000200
+#define BM_UARTDBGICR_PEIC 0x00000100
+#define BM_UARTDBGICR_FEIC 0x00000080
+#define BM_UARTDBGICR_RTIC 0x00000040
+#define BM_UARTDBGICR_TXIC 0x00000020
+#define BM_UARTDBGICR_RXIC 0x00000010
+#define BM_UARTDBGICR_DSRMIC 0x00000008
+#define BM_UARTDBGICR_DCDMIC 0x00000004
+#define BM_UARTDBGICR_CTSMIC 0x00000002
+#define BM_UARTDBGICR_RIMIC 0x00000001
+#define HW_UARTDBGDMACR 0x00000048
+#define BP_UARTDBGDMACR_UNAVAILABLE      16
+#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
+#define BP_UARTDBGDMACR_RESERVED      3
+#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
+#define BF_UARTDBGDMACR_RESERVED(v)  \
+        (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
+#define BM_UARTDBGDMACR_DMAONERR 0x00000004
+#define BM_UARTDBGDMACR_TXDMAE 0x00000002
+#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
new file mode 100644
index 000000000000..25112c1aa608
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
@@ -0,0 +1,40 @@
+/*
+ * stmp378x: USBCTRL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_USBCTRL_BASE       (STMP3XXX_REGS_BASE + 0x80000)
+#define REGS_USBCTRL_PHYS       0x80080000
+#define REGS_USBCTRL_SIZE       0x2000
+#define HW_USBCTRL_USBCMD       0x140
+#define BM_USBCTRL_USBCMD_RS    0x00000001
+#define BP_USBCTRL_USBCMD_RS    0
+#define BM_USBCTRL_USBCMD_RST   0x00000002
+#define HW_USBCTRL_USBINTR      0x148
+#define BM_USBCTRL_USBINTR_UE   0x00000001
+#define BP_USBCTRL_USBINTR_UE   0
+#define HW_USBCTRL_PORTSC1      0x184
+#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
+#define HW_USBCTRL_OTGSC        0x1A4
+#define BM_USBCTRL_OTGSC_ID     0x00000100
+#define BM_USBCTRL_OTGSC_IDIS   0x00010000
+#define BM_USBCTRL_OTGSC_IDIE   0x01000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
new file mode 100644
index 000000000000..11f3b732dc92
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
@@ -0,0 +1,37 @@
+/*
+ * stmp378x: USBPHY register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_USBPHY_BASE        (STMP3XXX_REGS_BASE + 0x7C000)
+#define REGS_USBPHY_PHYS        0x8007C000
+#define REGS_USBPHY_SIZE        0x2000
+#define HW_USBPHY_PWD           0x0
+#define HW_USBPHY_CTRL          0x30
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x00000002
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x00000010
+#define BM_USBPHY_CTRL_ENOTGIDDETECT    0x00000080
+#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN   0x00000800
+#define BM_USBPHY_CTRL_CLKGATE  0x40000000
+#define BM_USBPHY_CTRL_SFTRST   0x80000000
+#define HW_USBPHY_STATUS        0x40
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS       0x00000040
+#define BM_USBPHY_STATUS_OTGID_STATUS   0x00000100
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
new file mode 100644
index 000000000000..ddd49a760fd4
--- /dev/null
+++ b/arch/arm/mach-stmp378x/stmp378x.c
@@ -0,0 +1,299 @@
+/*
+ * Freescale STMP378X platform support
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <asm/dma.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/pins.h>
+#include <mach/pinmux.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
+#include <mach/system.h>
+#include <mach/platform.h>
+#include <mach/stmp3xxx.h>
+#include <mach/regs-icoll.h>
+#include <mach/regs-apbh.h>
+#include <mach/regs-apbx.h>
+#include <mach/regs-pxp.h>
+#include <mach/regs-i2c.h>
+#include "stmp378x.h"
+/*
+ * IRQ handling
+ */
+static void stmp378x_ack_irq(unsigned int irq)
+{
+        /* Tell ICOLL to release IRQ line */
+        __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
+        /* ACK current interrupt */
+        __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
+                        REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
+        /* Barrier */
+        (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
+}
+static void stmp378x_mask_irq(unsigned int irq)
+{
+        /* IRQ disable */
+        stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
+                        REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
+}
+static void stmp378x_unmask_irq(unsigned int irq)
+{
+        /* IRQ enable */
+        stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
+                      REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
+}
+static struct irq_chip stmp378x_chip = {
+        .ack    = stmp378x_ack_irq,
+        .mask   = stmp378x_mask_irq,
+        .unmask = stmp378x_unmask_irq,
+};
+void __init stmp378x_init_irq(void)
+{
+        stmp3xxx_init_irq(&stmp378x_chip);
+}
+/*
+ * DMA interrupt handling
+ */
+void stmp3xxx_arch_dma_enable_interrupt(int channel)
+{
+        void __iomem *c1, *c2;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
+                c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
+                break;
+        case STMP3XXX_BUS_APBX:
+                c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
+                c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
+                break;
+        default:
+                return;
+        }
+        stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
+        stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
+void stmp3xxx_arch_dma_clear_interrupt(int channel)
+{
+        void __iomem *c1, *c2;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
+                c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
+                break;
+        case STMP3XXX_BUS_APBX:
+                c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
+                c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
+                break;
+        default:
+                return;
+        }
+        stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
+        stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
+int stmp3xxx_arch_dma_is_interrupt(int channel)
+{
+        int r = 0;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
+                        (1 << STMP3XXX_DMA_CHANNEL(channel));
+                break;
+        case STMP3XXX_BUS_APBX:
+                r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
+                        (1 << STMP3XXX_DMA_CHANNEL(channel));
+                break;
+        }
+        return r;
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
+void stmp3xxx_arch_dma_reset_channel(int channel)
+{
+        unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+        void __iomem *c0;
+        u32 mask;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
+                mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
+                break;
+        case STMP3XXX_BUS_APBX:
+                c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
+                mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
+                break;
+        default:
+                return;
+        }
+        /* Reset channel and wait for it to complete */
+        stmp3xxx_setl(mask, c0);
+        while (__raw_readl(c0) & mask)
+                cpu_relax();
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
+void stmp3xxx_arch_dma_freeze(int channel)
+{
+        unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+        u32 mask = 1 << chbit;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
+                break;
+        case STMP3XXX_BUS_APBX:
+                stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
+                break;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
+void stmp3xxx_arch_dma_unfreeze(int channel)
+{
+        unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+        u32 mask = 1 << chbit;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
+                break;
+        case STMP3XXX_BUS_APBX:
+                stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
+                break;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
+/*
+ * The registers are all very closely mapped, so we might as well map them all
+ * with a single mapping
+ *
+ * Logical      Physical
+ * f0000000     80000000        On-chip registers
+ * f1000000     00000000        32k on-chip SRAM
+ */
+static struct map_desc stmp378x_io_desc[] __initdata = {
+        {
+                .virtual        = (u32)STMP3XXX_REGS_BASE,
+                .pfn            = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
+                .length         = STMP3XXX_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = (u32)STMP3XXX_OCRAM_BASE,
+                .pfn            = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
+                .length         = STMP3XXX_OCRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+static u64 common_dmamask = DMA_BIT_MASK(32);
+/*
+ * devices that are present only on stmp378x, not on all 3xxx boards:
+ *      PxP
+ *      I2C
+ */
+static struct resource pxp_resource[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+                .start  = REGS_PXP_PHYS,
+                .end    = REGS_PXP_PHYS + REGS_PXP_SIZE,
+        }, {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_PXP,
+                .end    = IRQ_PXP,
+        },
+};
+struct platform_device stmp378x_pxp = {
+        .name           = "stmp3xxx-pxp",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &common_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(pxp_resource),
+        .resource       = pxp_resource,
+};
+static struct resource i2c_resources[] = {
+        {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_I2C_ERROR,
+                .end = IRQ_I2C_ERROR,
+        }, {
+                .flags = IORESOURCE_MEM,
+                .start = REGS_I2C_PHYS,
+                .end = REGS_I2C_PHYS + REGS_I2C_SIZE,
+        }, {
+                .flags = IORESOURCE_DMA,
+                .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
+                .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
+        },
+};
+struct platform_device stmp378x_i2c = {
+        .name = "i2c_stmp3xxx",
+        .id = 0,
+        .dev    = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource = i2c_resources,
+        .num_resources = ARRAY_SIZE(i2c_resources),
+};
+void __init stmp378x_map_io(void)
+{
+        iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
+}
diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h
new file mode 100644
index 000000000000..0dc15b3c891f
--- /dev/null
+++ b/arch/arm/mach-stmp378x/stmp378x.h
@@ -0,0 +1,25 @@
+/*
+ * Freescale STMP37XX/STMP378X internal functions and data declarations
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_STMP378X_H
+#define __MACH_STMP378X_H
+void stmp378x_map_io(void);
+void stmp378x_init_irq(void);
+extern struct platform_device stmp378x_pxp, stmp378x_i2c;
+#endif /* __MACH_STMP378X_COMMON_H */
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
new file mode 100644
index 000000000000..90d8fe6f10fe
--- /dev/null
+++ b/arch/arm/mach-stmp378x/stmp378x_devb.c
@@ -0,0 +1,334 @@
+/*
+ * Freescale STMP378X development board support
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/spi/spi.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/pins.h>
+#include <mach/pinmux.h>
+#include <mach/platform.h>
+#include <mach/stmp3xxx.h>
+#include <mach/mmc.h>
+#include <mach/gpmi.h>
+#include "stmp378x.h"
+static struct platform_device *devices[] = {
+        &stmp3xxx_dbguart,
+        &stmp3xxx_appuart,
+        &stmp3xxx_watchdog,
+        &stmp3xxx_touchscreen,
+        &stmp3xxx_rtc,
+        &stmp3xxx_keyboard,
+        &stmp3xxx_framebuffer,
+        &stmp3xxx_backlight,
+        &stmp3xxx_rotdec,
+        &stmp3xxx_persistent,
+        &stmp3xxx_dcp_bootstream,
+        &stmp3xxx_dcp,
+        &stmp3xxx_battery,
+        &stmp378x_pxp,
+        &stmp378x_i2c,
+};
+static struct pin_desc i2c_pins_desc[] = {
+        { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+};
+static struct pin_group i2c_pins = {
+        .pins           = i2c_pins_desc,
+        .nr_pins        = ARRAY_SIZE(i2c_pins_desc),
+};
+static struct pin_desc dbguart_pins_0[] = {
+        { PINID_PWM0, PIN_FUN3, },
+        { PINID_PWM1, PIN_FUN3, },
+};
+static struct pin_group dbguart_pins[] = {
+        [0] = {
+                .pins           = dbguart_pins_0,
+                .nr_pins        = ARRAY_SIZE(dbguart_pins_0),
+        },
+};
+static int dbguart_pins_control(int id, int request)
+{
+        int r = 0;
+        if (request)
+                r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
+        else
+                stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
+        return r;
+}
+static struct pin_desc appuart_pins_0[] = {
+        { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+};
+static struct pin_desc appuart_pins_1[] = {
+#if 0 /* enable these when second appuart will be connected */
+        { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+#endif
+};
+static struct pin_desc mmc_pins_desc[] = {
+        { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
+        { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
+        { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
+        { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
+        { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
+        { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
+        { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
+};
+static struct pin_group mmc_pins = {
+        .pins           = mmc_pins_desc,
+        .nr_pins        = ARRAY_SIZE(mmc_pins_desc),
+};
+static int stmp3xxxmmc_get_wp(void)
+{
+        return gpio_get_value(PINID_PWM4);
+}
+static int stmp3xxxmmc_hw_init_ssp1(void)
+{
+        int ret;
+        ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
+        if (ret)
+                goto out;
+        /* Configure write protect GPIO pin */
+        ret = gpio_request(PINID_PWM4, "mmc wp");
+        if (ret)
+                goto out_wp;
+        gpio_direction_input(PINID_PWM4);
+        /* Configure POWER pin as gpio to drive power to MMC slot */
+        ret = gpio_request(PINID_PWM3, "mmc power");
+        if (ret)
+                goto out_power;
+        gpio_direction_output(PINID_PWM3, 0);
+        mdelay(100);
+        return 0;
+out_power:
+        gpio_free(PINID_PWM4);
+out_wp:
+        stmp3xxx_release_pin_group(&mmc_pins, "mmc");
+out:
+        return ret;
+}
+static void stmp3xxxmmc_hw_release_ssp1(void)
+{
+        gpio_free(PINID_PWM3);
+        gpio_free(PINID_PWM4);
+        stmp3xxx_release_pin_group(&mmc_pins, "mmc");
+}
+static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
+{
+        stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
+}
+static unsigned long
+stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
+{
+        struct clk *ssp, *parent;
+        char *p;
+        long r;
+        ssp = clk_get(NULL, "ssp");
+        /* using SSP1, no timeout, clock rate 1 */
+        writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
+               BF(0xFFFF, SSP_TIMING_TIMEOUT),
+               base + HW_SSP_TIMING);
+        p = (hz > 1000000) ? "io" : "osc_24M";
+        parent = clk_get(NULL, p);
+        clk_set_parent(ssp, parent);
+        r = clk_set_rate(ssp, 2 * hz / 1000);
+        clk_put(parent);
+        clk_put(ssp);
+        return hz;
+}
+static struct stmp3xxxmmc_platform_data mmc_data = {
+        .hw_init        = stmp3xxxmmc_hw_init_ssp1,
+        .hw_release     = stmp3xxxmmc_hw_release_ssp1,
+        .get_wp         = stmp3xxxmmc_get_wp,
+        .cmd_pullup     = stmp3xxxmmc_cmd_pullup_ssp1,
+        .setclock       = stmp3xxxmmc_setclock_ssp1,
+};
+static struct pin_group appuart_pins[] = {
+        [0] = {
+                .pins           = appuart_pins_0,
+                .nr_pins        = ARRAY_SIZE(appuart_pins_0),
+        },
+        [1] = {
+                .pins           = appuart_pins_1,
+                .nr_pins        = ARRAY_SIZE(appuart_pins_1),
+        },
+};
+static struct pin_desc ssp1_pins_desc[] = {
+        { PINID_SSP1_SCK,       PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
+        { PINID_SSP1_CMD,       PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
+        { PINID_SSP1_DATA0,     PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
+        { PINID_SSP1_DATA3,     PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
+};
+static struct pin_desc ssp2_pins_desc[] = {
+        { PINID_GPMI_WRN,       PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
+        { PINID_GPMI_RDY1,      PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
+        { PINID_GPMI_D00,       PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
+        { PINID_GPMI_D03,       PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
+};
+static struct pin_group ssp1_pins = {
+        .pins = ssp1_pins_desc,
+        .nr_pins = ARRAY_SIZE(ssp1_pins_desc),
+};
+static struct pin_group ssp2_pins = {
+        .pins = ssp1_pins_desc,
+        .nr_pins = ARRAY_SIZE(ssp2_pins_desc),
+};
+static struct pin_desc gpmi_pins_desc[] = {
+        { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
+        { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
+        { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
+        { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
+};
+static struct pin_group gpmi_pins = {
+        .pins           = gpmi_pins_desc,
+        .nr_pins        = ARRAY_SIZE(gpmi_pins_desc),
+};
+static struct mtd_partition gpmi_partitions[] = {
+        [0] = {
+                .name   = "boot",
+                .size   = 10 * SZ_1M,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "data",
+                .size   = MTDPART_SIZ_FULL,
+                .offset = MTDPART_OFS_APPEND,
+        },
+};
+static struct gpmi_platform_data gpmi_data = {
+        .pins = &gpmi_pins,
+        .nr_parts = ARRAY_SIZE(gpmi_partitions),
+        .parts = gpmi_partitions,
+        .part_types = { "cmdline", NULL },
+};
+static struct spi_board_info spi_board_info[] __initdata = {
+#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+        {
+                .modalias       = "enc28j60",
+                .max_speed_hz   = 6 * 1000 * 1000,
+                .bus_num        = 1,
+                .chip_select    = 0,
+                .platform_data  = NULL,
+        },
+#endif
+};
+static void __init stmp378x_devb_init(void)
+{
+        stmp3xxx_pinmux_init(NR_REAL_IRQS);
+        /* init stmp3xxx platform */
+        stmp3xxx_init();
+        stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
+        stmp3xxx_appuart.dev.platform_data = appuart_pins;
+        stmp3xxx_mmc.dev.platform_data = &mmc_data;
+        stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
+        stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
+        stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
+        stmp378x_i2c.dev.platform_data = &i2c_pins;
+        /* register spi devices */
+        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+        /* add board's devices */
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        /* add devices selected by command line ssp1= and ssp2= options */
+        stmp3xxx_ssp1_device_register();
+        stmp3xxx_ssp2_device_register();
+}
+MACHINE_START(STMP378X, "STMP378X")
+        .phys_io        = 0x80000000,
+        .io_pg_offst    = ((0xf0000000) >> 18) & 0xfffc,
+        .boot_params    = 0x40000100,
+        .map_io         = stmp378x_map_io,
+        .init_irq       = stmp378x_init_irq,
+        .timer          = &stmp3xxx_timer,
+        .init_machine   = stmp378x_devb_init,
+MACHINE_END
diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile
new file mode 100644
index 000000000000..57deffd09fbf
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o
+obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o
diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot
new file mode 100644
index 000000000000..1568ad404d59
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x40008000
+params_phys-y   := 0x40000100
+initrd_phys-y   := 0x40800000
diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..fed2787b6c34
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
+/*
+ * Low-level IRQ helper macros for Freescale STMP37XX
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \base, #0xf0000000      @ vm address of IRQ controller
+                ldr     \irqnr, [\base, #0x30]  @ HW_ICOLL_STAT
+                cmp     \irqnr, #0x3f
+                movne   \irqstat, #0            @ Ack this IRQ
+                strne   \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
+                moveqs  \irqnr, #0              @ Zero flag set for no IRQ
+                .endm
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h
new file mode 100644
index 000000000000..98f12938550d
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/irqs.h
@@ -0,0 +1,99 @@
+/*
+ * Freescale STMP37XX interrupts
+ *
+ * Copyright (C) 2005 Sigmatel Inc
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef _ASM_ARCH_IRQS_H
+#define _ASM_ARCH_IRQS_H
+#define IRQ_DEBUG_UART           0
+#define IRQ_COMMS_RX               1
+#define IRQ_COMMS_TX               1
+#define IRQ_SSP2_ERROR           2
+#define IRQ_VDD5V                     3
+#define IRQ_HEADPHONE_SHORT         4
+#define IRQ_DAC_DMA                 5
+#define IRQ_DAC_ERROR             6
+#define IRQ_ADC_DMA                 7
+#define IRQ_ADC_ERROR             8
+#define IRQ_SPDIF_DMA             9
+#define IRQ_SAIF2_DMA             9
+#define IRQ_SPDIF_ERROR         10
+#define IRQ_SAIF1_IRQ             10
+#define IRQ_SAIF2_IRQ             10
+#define IRQ_USB_CTRL               11
+#define IRQ_USB_WAKEUP           12
+#define IRQ_GPMI_DMA               13
+#define IRQ_SSP1_DMA               14
+#define IRQ_SSP_ERROR             15
+#define IRQ_GPIO0                     16
+#define IRQ_GPIO1                     17
+#define IRQ_GPIO2                     18
+#define IRQ_SAIF1_DMA             19
+#define IRQ_SSP2_DMA               20
+#define IRQ_ECC8_IRQ               21
+#define IRQ_RTC_ALARM             22
+#define IRQ_UARTAPP_TX_DMA           23
+#define IRQ_UARTAPP_INTERNAL       24
+#define IRQ_UARTAPP_RX_DMA           25
+#define IRQ_I2C_DMA                 26
+#define IRQ_I2C_ERROR             27
+#define IRQ_TIMER0                   28
+#define IRQ_TIMER1                   29
+#define IRQ_TIMER2                   30
+#define IRQ_TIMER3                   31
+#define IRQ_BATT_BRNOUT         32
+#define IRQ_VDDD_BRNOUT         33
+#define IRQ_VDDIO_BRNOUT               34
+#define IRQ_VDD18_BRNOUT               35
+#define IRQ_TOUCH_DETECT               36
+#define IRQ_LRADC_CH0             37
+#define IRQ_LRADC_CH1             38
+#define IRQ_LRADC_CH2             39
+#define IRQ_LRADC_CH3             40
+#define IRQ_LRADC_CH4             41
+#define IRQ_LRADC_CH5             42
+#define IRQ_LRADC_CH6             43
+#define IRQ_LRADC_CH7             44
+#define IRQ_LCDIF_DMA             45
+#define IRQ_LCDIF_ERROR         46
+#define IRQ_DIGCTL_DEBUG_TRAP     47
+#define IRQ_RTC_1MSEC             48
+#define IRQ_DRI_DMA                 49
+#define IRQ_DRI_ATTENTION             50
+#define IRQ_GPMI_ATTENTION           51
+#define IRQ_IR                   52
+#define IRQ_DCP_VMI                 53
+#define IRQ_DCP                 54
+#define IRQ_RESERVED_55         55
+#define IRQ_RESERVED_56         56
+#define IRQ_RESERVED_57         57
+#define IRQ_RESERVED_58         58
+#define IRQ_RESERVED_59         59
+#define SW_IRQ_60                     60
+#define SW_IRQ_61                     61
+#define SW_IRQ_62                     62
+#define SW_IRQ_63                     63
+#define NR_REAL_IRQS            64
+#define NR_IRQS                 (NR_REAL_IRQS + 32 * 3)
+/* TIMER and BRNOUT are FIQ capable */
+#define FIQ_START                       IRQ_TIMER0
+/* Hard disk IRQ is a GPMI attention IRQ */
+#define IRQ_HARDDISK            IRQ_GPMI_ATTENTION
+#endif /* _ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h
new file mode 100644
index 000000000000..d56de0c471d8
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/pins.h
@@ -0,0 +1,147 @@
+/*
+ * Freescale STMP37XX SoC pin multiplexing
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_PINS_H
+#define __ASM_ARCH_PINS_H
+/*
+ * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
+ * interface  this pin belongs to.
+ */
+/* Bank 0 */
+#define PINID_GPMI_D00          STMP3XXX_PINID(0, 0)
+#define PINID_GPMI_D01          STMP3XXX_PINID(0, 1)
+#define PINID_GPMI_D02          STMP3XXX_PINID(0, 2)
+#define PINID_GPMI_D03          STMP3XXX_PINID(0, 3)
+#define PINID_GPMI_D04          STMP3XXX_PINID(0, 4)
+#define PINID_GPMI_D05          STMP3XXX_PINID(0, 5)
+#define PINID_GPMI_D06          STMP3XXX_PINID(0, 6)
+#define PINID_GPMI_D07          STMP3XXX_PINID(0, 7)
+#define PINID_GPMI_D08          STMP3XXX_PINID(0, 8)
+#define PINID_GPMI_D09          STMP3XXX_PINID(0, 9)
+#define PINID_GPMI_D10          STMP3XXX_PINID(0, 10)
+#define PINID_GPMI_D11          STMP3XXX_PINID(0, 11)
+#define PINID_GPMI_D12          STMP3XXX_PINID(0, 12)
+#define PINID_GPMI_D13          STMP3XXX_PINID(0, 13)
+#define PINID_GPMI_D14          STMP3XXX_PINID(0, 14)
+#define PINID_GPMI_D15          STMP3XXX_PINID(0, 15)
+#define PINID_GPMI_A0           STMP3XXX_PINID(0, 16)
+#define PINID_GPMI_A1           STMP3XXX_PINID(0, 17)
+#define PINID_GPMI_A2           STMP3XXX_PINID(0, 18)
+#define PINID_GPMI_RDY0         STMP3XXX_PINID(0, 19)
+#define PINID_GPMI_RDY2         STMP3XXX_PINID(0, 20)
+#define PINID_GPMI_RDY3         STMP3XXX_PINID(0, 21)
+#define PINID_GPMI_RESETN       STMP3XXX_PINID(0, 22)
+#define PINID_GPMI_IRQ          STMP3XXX_PINID(0, 23)
+#define PINID_GPMI_WRN          STMP3XXX_PINID(0, 24)
+#define PINID_GPMI_RDN          STMP3XXX_PINID(0, 25)
+#define PINID_UART2_CTS         STMP3XXX_PINID(0, 26)
+#define PINID_UART2_RTS         STMP3XXX_PINID(0, 27)
+#define PINID_UART2_RX          STMP3XXX_PINID(0, 28)
+#define PINID_UART2_TX          STMP3XXX_PINID(0, 29)
+/* Bank 1 */
+#define PINID_LCD_D00           STMP3XXX_PINID(1, 0)
+#define PINID_LCD_D01           STMP3XXX_PINID(1, 1)
+#define PINID_LCD_D02           STMP3XXX_PINID(1, 2)
+#define PINID_LCD_D03           STMP3XXX_PINID(1, 3)
+#define PINID_LCD_D04           STMP3XXX_PINID(1, 4)
+#define PINID_LCD_D05           STMP3XXX_PINID(1, 5)
+#define PINID_LCD_D06           STMP3XXX_PINID(1, 6)
+#define PINID_LCD_D07           STMP3XXX_PINID(1, 7)
+#define PINID_LCD_D08           STMP3XXX_PINID(1, 8)
+#define PINID_LCD_D09           STMP3XXX_PINID(1, 9)
+#define PINID_LCD_D10           STMP3XXX_PINID(1, 10)
+#define PINID_LCD_D11           STMP3XXX_PINID(1, 11)
+#define PINID_LCD_D12           STMP3XXX_PINID(1, 12)
+#define PINID_LCD_D13           STMP3XXX_PINID(1, 13)
+#define PINID_LCD_D14           STMP3XXX_PINID(1, 14)
+#define PINID_LCD_D15           STMP3XXX_PINID(1, 15)
+#define PINID_LCD_RESET         STMP3XXX_PINID(1, 16)
+#define PINID_LCD_RS            STMP3XXX_PINID(1, 17)
+#define PINID_LCD_WR_RWN        STMP3XXX_PINID(1, 18)
+#define PINID_LCD_RD_E          STMP3XXX_PINID(1, 19)
+#define PINID_LCD_CS            STMP3XXX_PINID(1, 20)
+#define PINID_LCD_BUSY          STMP3XXX_PINID(1, 21)
+#define PINID_SSP1_CMD          STMP3XXX_PINID(1, 22)
+#define PINID_SSP1_SCK          STMP3XXX_PINID(1, 23)
+#define PINID_SSP1_DATA0        STMP3XXX_PINID(1, 24)
+#define PINID_SSP1_DATA1        STMP3XXX_PINID(1, 25)
+#define PINID_SSP1_DATA2        STMP3XXX_PINID(1, 26)
+#define PINID_SSP1_DATA3        STMP3XXX_PINID(1, 27)
+#define PINID_SSP1_DETECT       STMP3XXX_PINID(1, 28)
+/* Bank 2 */
+#define PINID_PWM0              STMP3XXX_PINID(2, 0)
+#define PINID_PWM1              STMP3XXX_PINID(2, 1)
+#define PINID_PWM2              STMP3XXX_PINID(2, 2)
+#define PINID_PWM3              STMP3XXX_PINID(2, 3)
+#define PINID_PWM4              STMP3XXX_PINID(2, 4)
+#define PINID_I2C_SCL           STMP3XXX_PINID(2, 5)
+#define PINID_I2C_SDA           STMP3XXX_PINID(2, 6)
+#define PINID_ROTTARYA          STMP3XXX_PINID(2, 7)
+#define PINID_ROTTARYB          STMP3XXX_PINID(2, 8)
+#define PINID_EMI_CKE           STMP3XXX_PINID(2, 9)
+#define PINID_EMI_RASN          STMP3XXX_PINID(2, 10)
+#define PINID_EMI_CASN          STMP3XXX_PINID(2, 11)
+#define PINID_EMI_CE0N          STMP3XXX_PINID(2, 12)
+#define PINID_EMI_CE1N          STMP3XXX_PINID(2, 13)
+#define PINID_EMI_CE2N          STMP3XXX_PINID(2, 14)
+#define PINID_EMI_CE3N          STMP3XXX_PINID(2, 15)
+#define PINID_EMI_A00           STMP3XXX_PINID(2, 16)
+#define PINID_EMI_A01           STMP3XXX_PINID(2, 17)
+#define PINID_EMI_A02           STMP3XXX_PINID(2, 18)
+#define PINID_EMI_A03           STMP3XXX_PINID(2, 19)
+#define PINID_EMI_A04           STMP3XXX_PINID(2, 20)
+#define PINID_EMI_A05           STMP3XXX_PINID(2, 21)
+#define PINID_EMI_A06           STMP3XXX_PINID(2, 22)
+#define PINID_EMI_A07           STMP3XXX_PINID(2, 23)
+#define PINID_EMI_A08           STMP3XXX_PINID(2, 24)
+#define PINID_EMI_A09           STMP3XXX_PINID(2, 25)
+#define PINID_EMI_A10           STMP3XXX_PINID(2, 26)
+#define PINID_EMI_A11           STMP3XXX_PINID(2, 27)
+#define PINID_EMI_A12           STMP3XXX_PINID(2, 28)
+#define PINID_EMI_A13           STMP3XXX_PINID(2, 29)
+#define PINID_EMI_A14           STMP3XXX_PINID(2, 30)
+#define PINID_EMI_WEN           STMP3XXX_PINID(2, 31)
+/* Bank 3 */
+#define PINID_EMI_D00           STMP3XXX_PINID(3, 0)
+#define PINID_EMI_D01           STMP3XXX_PINID(3, 1)
+#define PINID_EMI_D02           STMP3XXX_PINID(3, 2)
+#define PINID_EMI_D03           STMP3XXX_PINID(3, 3)
+#define PINID_EMI_D04           STMP3XXX_PINID(3, 4)
+#define PINID_EMI_D05           STMP3XXX_PINID(3, 5)
+#define PINID_EMI_D06           STMP3XXX_PINID(3, 6)
+#define PINID_EMI_D07           STMP3XXX_PINID(3, 7)
+#define PINID_EMI_D08           STMP3XXX_PINID(3, 8)
+#define PINID_EMI_D09           STMP3XXX_PINID(3, 9)
+#define PINID_EMI_D10           STMP3XXX_PINID(3, 10)
+#define PINID_EMI_D11           STMP3XXX_PINID(3, 11)
+#define PINID_EMI_D12           STMP3XXX_PINID(3, 12)
+#define PINID_EMI_D13           STMP3XXX_PINID(3, 13)
+#define PINID_EMI_D14           STMP3XXX_PINID(3, 14)
+#define PINID_EMI_D15           STMP3XXX_PINID(3, 15)
+#define PINID_EMI_DQS0          STMP3XXX_PINID(3, 16)
+#define PINID_EMI_DQS1          STMP3XXX_PINID(3, 17)
+#define PINID_EMI_DQM0          STMP3XXX_PINID(3, 18)
+#define PINID_EMI_DQM1          STMP3XXX_PINID(3, 19)
+#define PINID_EMI_CLK           STMP3XXX_PINID(3, 20)
+#define PINID_EMI_CLKN          STMP3XXX_PINID(3, 21)
+#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
new file mode 100644
index 000000000000..a323aa9a21f2
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
@@ -0,0 +1,97 @@
+/*
+ * stmp37xx: APBH register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_APBH
+#define _MACH_REGS_APBH
+#define REGS_APBH_BASE  (STMP3XXX_REGS_BASE + 0x4000)
+#define HW_APBH_CTRL0           0x0
+#define BM_APBH_CTRL0_RESET_CHANNEL     0x00FF0000
+#define BP_APBH_CTRL0_RESET_CHANNEL     16
+#define BM_APBH_CTRL0_CLKGATE   0x40000000
+#define BM_APBH_CTRL0_SFTRST    0x80000000
+#define HW_APBH_CTRL1           0x10
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ  0x00000001
+#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ  0
+#define HW_APBH_DEVSEL          0x20
+#define HW_APBH_CH0_NXTCMDAR    (0x50 + 0 * 0x70)
+#define HW_APBH_CH1_NXTCMDAR    (0x50 + 1 * 0x70)
+#define HW_APBH_CH2_NXTCMDAR    (0x50 + 2 * 0x70)
+#define HW_APBH_CH3_NXTCMDAR    (0x50 + 3 * 0x70)
+#define HW_APBH_CH4_NXTCMDAR    (0x50 + 4 * 0x70)
+#define HW_APBH_CH5_NXTCMDAR    (0x50 + 5 * 0x70)
+#define HW_APBH_CH6_NXTCMDAR    (0x50 + 6 * 0x70)
+#define HW_APBH_CH7_NXTCMDAR    (0x50 + 7 * 0x70)
+#define HW_APBH_CH8_NXTCMDAR    (0x50 + 8 * 0x70)
+#define HW_APBH_CH9_NXTCMDAR    (0x50 + 9 * 0x70)
+#define HW_APBH_CH10_NXTCMDAR   (0x50 + 10 * 0x70)
+#define HW_APBH_CH11_NXTCMDAR   (0x50 + 11 * 0x70)
+#define HW_APBH_CH12_NXTCMDAR   (0x50 + 12 * 0x70)
+#define HW_APBH_CH13_NXTCMDAR   (0x50 + 13 * 0x70)
+#define HW_APBH_CH14_NXTCMDAR   (0x50 + 14 * 0x70)
+#define HW_APBH_CH15_NXTCMDAR   (0x50 + 15 * 0x70)
+#define HW_APBH_CHn_NXTCMDAR    0x50
+#define BM_APBH_CHn_CMD_MODE            0x00000003
+#define BP_APBH_CHn_CMD_MODE            0x00000001
+#define BV_APBH_CHn_CMD_MODE_NOOP                0
+#define BV_APBH_CHn_CMD_MODE_WRITE               1
+#define BV_APBH_CHn_CMD_MODE_READ                2
+#define BV_APBH_CHn_CMD_MODE_SENSE               3
+#define BM_APBH_CHn_CMD_CHAIN           0x00000004
+#define BM_APBH_CHn_CMD_IRQONCMPLT      0x00000008
+#define BM_APBH_CHn_CMD_NANDLOCK        0x00000010
+#define BM_APBH_CHn_CMD_NANDWAIT4READY  0x00000020
+#define BM_APBH_CHn_CMD_SEMAPHORE       0x00000040
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD     0x00000080
+#define BM_APBH_CHn_CMD_CMDWORDS        0x0000F000
+#define BP_APBH_CHn_CMD_CMDWORDS        12
+#define BM_APBH_CHn_CMD_XFER_COUNT      0xFFFF0000
+#define BP_APBH_CHn_CMD_XFER_COUNT      16
+#define HW_APBH_CH0_SEMA        (0x80 + 0 * 0x70)
+#define HW_APBH_CH1_SEMA        (0x80 + 1 * 0x70)
+#define HW_APBH_CH2_SEMA        (0x80 + 2 * 0x70)
+#define HW_APBH_CH3_SEMA        (0x80 + 3 * 0x70)
+#define HW_APBH_CH4_SEMA        (0x80 + 4 * 0x70)
+#define HW_APBH_CH5_SEMA        (0x80 + 5 * 0x70)
+#define HW_APBH_CH6_SEMA        (0x80 + 6 * 0x70)
+#define HW_APBH_CH7_SEMA        (0x80 + 7 * 0x70)
+#define HW_APBH_CH8_SEMA        (0x80 + 8 * 0x70)
+#define HW_APBH_CH9_SEMA        (0x80 + 9 * 0x70)
+#define HW_APBH_CH10_SEMA       (0x80 + 10 * 0x70)
+#define HW_APBH_CH11_SEMA       (0x80 + 11 * 0x70)
+#define HW_APBH_CH12_SEMA       (0x80 + 12 * 0x70)
+#define HW_APBH_CH13_SEMA       (0x80 + 13 * 0x70)
+#define HW_APBH_CH14_SEMA       (0x80 + 14 * 0x70)
+#define HW_APBH_CH15_SEMA       (0x80 + 15 * 0x70)
+#define HW_APBH_CHn_SEMA        0x80
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
+#define BM_APBH_CHn_SEMA_PHORE  0x00FF0000
+#define BP_APBH_CHn_SEMA_PHORE  16
+#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
new file mode 100644
index 000000000000..6d080cd5b702
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
@@ -0,0 +1,113 @@
+/*
+ * stmp37xx: APBX register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_APBX
+#define _MACH_REGS_APBX
+#define REGS_APBX_BASE  (STMP3XXX_REGS_BASE + 0x24000)
+#define HW_APBX_CTRL0           0x0
+#define BM_APBX_CTRL0_RESET_CHANNEL     0x00FF0000
+#define BP_APBX_CTRL0_RESET_CHANNEL     16
+#define BM_APBX_CTRL0_CLKGATE   0x40000000
+#define BM_APBX_CTRL0_SFTRST    0x80000000
+#define HW_APBX_CTRL1           0x10
+#define HW_APBX_DEVSEL          0x20
+#define HW_APBX_CH0_NXTCMDAR    (0x50 + 0 * 0x70)
+#define HW_APBX_CH1_NXTCMDAR    (0x50 + 1 * 0x70)
+#define HW_APBX_CH2_NXTCMDAR    (0x50 + 2 * 0x70)
+#define HW_APBX_CH3_NXTCMDAR    (0x50 + 3 * 0x70)
+#define HW_APBX_CH4_NXTCMDAR    (0x50 + 4 * 0x70)
+#define HW_APBX_CH5_NXTCMDAR    (0x50 + 5 * 0x70)
+#define HW_APBX_CH6_NXTCMDAR    (0x50 + 6 * 0x70)
+#define HW_APBX_CH7_NXTCMDAR    (0x50 + 7 * 0x70)
+#define HW_APBX_CH8_NXTCMDAR    (0x50 + 8 * 0x70)
+#define HW_APBX_CH9_NXTCMDAR    (0x50 + 9 * 0x70)
+#define HW_APBX_CH10_NXTCMDAR   (0x50 + 10 * 0x70)
+#define HW_APBX_CH11_NXTCMDAR   (0x50 + 11 * 0x70)
+#define HW_APBX_CH12_NXTCMDAR   (0x50 + 12 * 0x70)
+#define HW_APBX_CH13_NXTCMDAR   (0x50 + 13 * 0x70)
+#define HW_APBX_CH14_NXTCMDAR   (0x50 + 14 * 0x70)
+#define HW_APBX_CH15_NXTCMDAR   (0x50 + 15 * 0x70)
+#define HW_APBX_CHn_NXTCMDAR    0x50
+#define BM_APBX_CHn_CMD_MODE            0x00000003
+#define BP_APBX_CHn_CMD_MODE            0x00000001
+#define BV_APBX_CHn_CMD_MODE_NOOP                0
+#define BV_APBX_CHn_CMD_MODE_WRITE               1
+#define BV_APBX_CHn_CMD_MODE_READ                2
+#define BV_APBX_CHn_CMD_MODE_SENSE               3
+#define BM_APBX_CHn_CMD_COMMAND 0x00000003
+#define BP_APBX_CHn_CMD_COMMAND 0
+#define BM_APBX_CHn_CMD_CHAIN   0x00000004
+#define BM_APBX_CHn_CMD_IRQONCMPLT      0x00000008
+#define BM_APBX_CHn_CMD_SEMAPHORE       0x00000040
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD     0x00000080
+#define BM_APBX_CHn_CMD_CMDWORDS        0x0000F000
+#define BP_APBX_CHn_CMD_CMDWORDS        12
+#define BM_APBX_CHn_CMD_XFER_COUNT      0xFFFF0000
+#define BP_APBX_CHn_CMD_XFER_COUNT      16
+#define HW_APBX_CH0_BAR         (0x70 + 0 * 0x70)
+#define HW_APBX_CH1_BAR         (0x70 + 1 * 0x70)
+#define HW_APBX_CH2_BAR         (0x70 + 2 * 0x70)
+#define HW_APBX_CH3_BAR         (0x70 + 3 * 0x70)
+#define HW_APBX_CH4_BAR         (0x70 + 4 * 0x70)
+#define HW_APBX_CH5_BAR         (0x70 + 5 * 0x70)
+#define HW_APBX_CH6_BAR         (0x70 + 6 * 0x70)
+#define HW_APBX_CH7_BAR         (0x70 + 7 * 0x70)
+#define HW_APBX_CH8_BAR         (0x70 + 8 * 0x70)
+#define HW_APBX_CH9_BAR         (0x70 + 9 * 0x70)
+#define HW_APBX_CH10_BAR                (0x70 + 10 * 0x70)
+#define HW_APBX_CH11_BAR                (0x70 + 11 * 0x70)
+#define HW_APBX_CH12_BAR                (0x70 + 12 * 0x70)
+#define HW_APBX_CH13_BAR                (0x70 + 13 * 0x70)
+#define HW_APBX_CH14_BAR                (0x70 + 14 * 0x70)
+#define HW_APBX_CH15_BAR                (0x70 + 15 * 0x70)
+#define HW_APBX_CHn_BAR         0x70
+#define HW_APBX_CH0_SEMA        (0x80 + 0 * 0x70)
+#define HW_APBX_CH1_SEMA        (0x80 + 1 * 0x70)
+#define HW_APBX_CH2_SEMA        (0x80 + 2 * 0x70)
+#define HW_APBX_CH3_SEMA        (0x80 + 3 * 0x70)
+#define HW_APBX_CH4_SEMA        (0x80 + 4 * 0x70)
+#define HW_APBX_CH5_SEMA        (0x80 + 5 * 0x70)
+#define HW_APBX_CH6_SEMA        (0x80 + 6 * 0x70)
+#define HW_APBX_CH7_SEMA        (0x80 + 7 * 0x70)
+#define HW_APBX_CH8_SEMA        (0x80 + 8 * 0x70)
+#define HW_APBX_CH9_SEMA        (0x80 + 9 * 0x70)
+#define HW_APBX_CH10_SEMA       (0x80 + 10 * 0x70)
+#define HW_APBX_CH11_SEMA       (0x80 + 11 * 0x70)
+#define HW_APBX_CH12_SEMA       (0x80 + 12 * 0x70)
+#define HW_APBX_CH13_SEMA       (0x80 + 13 * 0x70)
+#define HW_APBX_CH14_SEMA       (0x80 + 14 * 0x70)
+#define HW_APBX_CH15_SEMA       (0x80 + 15 * 0x70)
+#define HW_APBX_CHn_SEMA        0x80
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
+#define BM_APBX_CHn_SEMA_PHORE  0x00FF0000
+#define BP_APBX_CHn_SEMA_PHORE  16
+#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
new file mode 100644
index 000000000000..3b511f947a53
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
@@ -0,0 +1,61 @@
+/*
+ * stmp37xx: AUDIOIN register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_AUDIOIN_BASE       (STMP3XXX_REGS_BASE + 0x4C000)
+#define HW_AUDIOIN_CTRL         0x0
+#define BM_AUDIOIN_CTRL_RUN     0x00000001
+#define BP_AUDIOIN_CTRL_RUN     0
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x00000002
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x00000004
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x00000008
+#define BM_AUDIOIN_CTRL_WORD_LENGTH     0x00000020
+#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
+#define BM_AUDIOIN_CTRL_SFTRST  0x80000000
+#define HW_AUDIOIN_STAT         0x10
+#define HW_AUDIOIN_ADCSRR       0x20
+#define HW_AUDIOIN_ADCVOLUME    0x30
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT       0x000000FF
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT       0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT        0x00FF0000
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT        16
+#define HW_AUDIOIN_ADCDEBUG     0x40
+#define HW_AUDIOIN_ADCVOL       0x50
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT    0x0000000F
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT    0
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT  0x00000030
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT  4
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT     0x00000F00
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT     8
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT   0x00003000
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT   12
+#define BM_AUDIOIN_ADCVOL_MUTE  0x01000000
+#define HW_AUDIOIN_MICLINE      0x60
+#define HW_AUDIOIN_ANACLKCTRL   0x70
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE   0x80000000
+#define HW_AUDIOIN_DATA         0x80
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
new file mode 100644
index 000000000000..ca1942b8a3e9
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
@@ -0,0 +1,111 @@
+/*
+ * stmp37xx: AUDIOOUT register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_AUDIOOUT_BASE      (STMP3XXX_REGS_BASE + 0x48000)
+#define HW_AUDIOOUT_CTRL        0x0
+#define BM_AUDIOOUT_CTRL_RUN    0x00000001
+#define BP_AUDIOOUT_CTRL_RUN    0
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x00000002
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x00000004
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x00000008
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH    0x00000040
+#define BM_AUDIOOUT_CTRL_CLKGATE        0x40000000
+#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
+#define HW_AUDIOOUT_STAT        0x10
+#define HW_AUDIOOUT_DACSRR      0x20
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC     0x00001FFF
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC     0
+#define BM_AUDIOOUT_DACSRR_SRC_INT      0x001F0000
+#define BP_AUDIOOUT_DACSRR_SRC_INT      16
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD     0x07000000
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD     24
+#define BM_AUDIOOUT_DACSRR_BASEMULT     0x70000000
+#define BP_AUDIOOUT_DACSRR_BASEMULT     28
+#define HW_AUDIOOUT_DACVOLUME   0x30
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT        0x00000100
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD    0x02000000
+#define HW_AUDIOOUT_DACDEBUG    0x40
+#define HW_AUDIOOUT_HPVOL       0x50
+#define BM_AUDIOOUT_HPVOL_MUTE  0x01000000
+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD   0x02000000
+#define HW_AUDIOOUT_PWRDN       0x70
+#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x00000001
+#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
+#define BM_AUDIOOUT_PWRDN_CAPLESS       0x00000010
+#define BM_AUDIOOUT_PWRDN_ADC   0x00000100
+#define BM_AUDIOOUT_PWRDN_DAC   0x00001000
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x00010000
+#define BM_AUDIOOUT_PWRDN_LINEOUT       0x01000000
+#define HW_AUDIOOUT_REFCTRL     0x80
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL     0x000000F0
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL     4
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL  0x00000F00
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL  8
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG     0x00001000
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC     0x00002000
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL   0x00030000
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL   16
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR     0x00080000
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ     0x00700000
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ     20
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x01000000
+#define BM_AUDIOOUT_REFCTRL_RAISE_REF   0x02000000
+#define HW_AUDIOOUT_ANACTRL     0x90
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB  0x00000010
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
+#define HW_AUDIOOUT_TEST        0xA0
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ      0x00C00000
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ      22
+#define HW_AUDIOOUT_BISTCTRL    0xB0
+#define HW_AUDIOOUT_BISTSTAT0   0xC0
+#define HW_AUDIOOUT_BISTSTAT1   0xD0
+#define HW_AUDIOOUT_ANACLKCTRL  0xE0
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE  0x80000000
+#define HW_AUDIOOUT_DATA        0xF0
+#define HW_AUDIOOUT_LINEOUTCTRL 0x100
+#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT       0x0000001F
+#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT       0
+#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT        0x00001F00
+#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT        8
+#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP      0x00007000
+#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP      12
+#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL        0x00F00000
+#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL        20
+#define BM_AUDIOOUT_LINEOUTCTRL_MUTE    0x01000000
+#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD  0x02000000
+#define HW_AUDIOOUT_VERSION     0x200
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
new file mode 100644
index 000000000000..47f5c92fdaf6
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
@@ -0,0 +1,72 @@
+/*
+ * stmp37xx: CLKCTRL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_CLKCTRL
+#define _MACH_REGS_CLKCTRL
+#define REGS_CLKCTRL_BASE       (STMP3XXX_REGS_BASE + 0x40000)
+#define HW_CLKCTRL_PLLCTRL0     0x0
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
+#define HW_CLKCTRL_CPU          0x20
+#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
+#define BP_CLKCTRL_CPU_DIV_CPU  0
+#define HW_CLKCTRL_HBUS         0x30
+#define BM_CLKCTRL_HBUS_DIV     0x0000001F
+#define BP_CLKCTRL_HBUS_DIV     0
+#define HW_CLKCTRL_XBUS         0x40
+#define HW_CLKCTRL_XTAL         0x50
+#define HW_CLKCTRL_PIX          0x60
+#define BM_CLKCTRL_PIX_DIV      0x00007FFF
+#define BP_CLKCTRL_PIX_DIV      0
+#define BM_CLKCTRL_PIX_CLKGATE  0x80000000
+#define HW_CLKCTRL_SSP          0x70
+#define HW_CLKCTRL_GPMI         0x80
+#define HW_CLKCTRL_SPDIF        0x90
+#define HW_CLKCTRL_EMI          0xA0
+#define HW_CLKCTRL_IR           0xB0
+#define HW_CLKCTRL_SAIF         0xC0
+#define HW_CLKCTRL_FRAC         0xD0
+#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
+#define BP_CLKCTRL_FRAC_EMIFRAC 8
+#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
+#define BP_CLKCTRL_FRAC_PIXFRAC 16
+#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x00800000
+#define HW_CLKCTRL_CLKSEQ       0xE0
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX    0x00000002
+#define HW_CLKCTRL_RESET        0xF0
+#define BM_CLKCTRL_RESET_DIG    0x00000001
+#define BP_CLKCTRL_RESET_DIG    0
+#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
new file mode 100644
index 000000000000..ba1bbe265c20
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
@@ -0,0 +1,24 @@
+/*
+ * stmp37xx: DIGCTL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_DIGCTL_BASE        (STMP3XXX_REGS_BASE + 0x1C000)
+#define HW_DIGCTL_CTRL          0x0
+#define BM_DIGCTL_CTRL_USB_CLKGATE      0x00000004
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
new file mode 100644
index 000000000000..3b6d990a3af5
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
@@ -0,0 +1,37 @@
+/*
+ * stmp37xx: ECC8 register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_ECC8_BASE  (STMP3XXX_REGS_BASE + 0x8000)
+#define HW_ECC8_CTRL            0x0
+#define BM_ECC8_CTRL_COMPLETE_IRQ       0x00000001
+#define BP_ECC8_CTRL_COMPLETE_IRQ       0
+#define BM_ECC8_CTRL_COMPLETE_IRQ_EN    0x00000100
+#define BM_ECC8_CTRL_AHBM_SFTRST        0x20000000
+#define HW_ECC8_STATUS0         0x10
+#define BM_ECC8_STATUS0_UNCORRECTABLE   0x00000004
+#define BM_ECC8_STATUS0_CORRECTED       0x00000008
+#define BM_ECC8_STATUS0_STATUS_AUX      0x00000F00
+#define BP_ECC8_STATUS0_STATUS_AUX      8
+#define BM_ECC8_STATUS0_COMPLETED_CE    0x000F0000
+#define BP_ECC8_STATUS0_COMPLETED_CE    16
+#define HW_ECC8_STATUS1         0x20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
new file mode 100644
index 000000000000..f2b304f54490
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
@@ -0,0 +1,63 @@
+/*
+ * stmp37xx: GPMI register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_GPMI_BASE  (STMP3XXX_REGS_BASE + 0xC000)
+#define REGS_GPMI_PHYS  0x8000C000
+#define REGS_GPMI_SIZE  0x2000
+#define HW_GPMI_CTRL0           0x0
+#define BM_GPMI_CTRL0_XFER_COUNT        0x0000FFFF
+#define BP_GPMI_CTRL0_XFER_COUNT        0
+#define BM_GPMI_CTRL0_CS        0x00300000
+#define BP_GPMI_CTRL0_CS        20
+#define BM_GPMI_CTRL0_LOCK_CS   0x00400000
+#define BM_GPMI_CTRL0_WORD_LENGTH       0x00800000
+#define BM_GPMI_CTRL0_COMMAND_MODE      0x03000000
+#define BP_GPMI_CTRL0_COMMAND_MODE      24
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE           0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ             0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY   0x3
+#define BM_GPMI_CTRL0_RUN       0x20000000
+#define BM_GPMI_CTRL0_CLKGATE   0x40000000
+#define BM_GPMI_CTRL0_SFTRST    0x80000000
+#define BM_GPMI_ECCCTRL_ENABLE_ECC      0x00001000
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define HW_GPMI_CTRL1           0x60
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
+#define BP_GPMI_CTRL1_GPMI_MODE 0
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY       0x00000004
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ       0x00000200
+#define BM_GPMI_CTRL1_DEV_IRQ   0x00000400
+#define BM_GPMI_CTRL1_DSAMPLE_TIME      0x00007000
+#define BP_GPMI_CTRL1_DSAMPLE_TIME      12
+#define HW_GPMI_TIMING0         0x70
+#define BM_GPMI_TIMING0_DATA_SETUP      0x000000FF
+#define BP_GPMI_TIMING0_DATA_SETUP      0
+#define BM_GPMI_TIMING0_DATA_HOLD       0x0000FF00
+#define BP_GPMI_TIMING0_DATA_HOLD       8
+#define HW_GPMI_TIMING1         0x80
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xFFFF0000
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
new file mode 100644
index 000000000000..35882a9b8bc5
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
@@ -0,0 +1,55 @@
+/*
+ * stmp37xx: I2C register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_I2C_BASE   (STMP3XXX_REGS_BASE + 0x58000)
+#define REGS_I2C_PHYS   0x80058000
+#define REGS_I2C_SIZE   0x2000
+#define HW_I2C_CTRL0            0x0
+#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
+#define BP_I2C_CTRL0_XFER_COUNT 0
+#define BM_I2C_CTRL0_DIRECTION  0x00010000
+#define BM_I2C_CTRL0_MASTER_MODE        0x00020000
+#define BM_I2C_CTRL0_PRE_SEND_START     0x00080000
+#define BM_I2C_CTRL0_POST_SEND_STOP     0x00100000
+#define BM_I2C_CTRL0_RETAIN_CLOCK       0x00200000
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST   0x02000000
+#define BM_I2C_CTRL0_CLKGATE    0x40000000
+#define BM_I2C_CTRL0_SFTRST     0x80000000
+#define HW_I2C_TIMING0          0x10
+#define HW_I2C_TIMING1          0x20
+#define HW_I2C_TIMING2          0x30
+#define HW_I2C_CTRL1            0x40
+#define BM_I2C_CTRL1_SLAVE_IRQ  0x00000001
+#define BP_I2C_CTRL1_SLAVE_IRQ  0
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ     0x00000002
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ    0x00000004
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ     0x00000008
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ     0x00000010
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ   0x00000020
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ      0x00000040
+#define BM_I2C_CTRL1_BUS_FREE_IRQ       0x00000080
+#define BM_I2C_CTRL1_CLR_GOT_A_NAK      0x10000000
+#define HW_I2C_VERSION          0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
new file mode 100644
index 000000000000..3b7c92239e20
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
@@ -0,0 +1,43 @@
+/*
+ * stmp37xx: ICOLL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_ICOLL
+#define _MACH_REGS_ICOLL
+#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
+#define HW_ICOLL_VECTOR         0x0
+#define HW_ICOLL_LEVELACK       0x10
+#define HW_ICOLL_CTRL           0x20
+#define BM_ICOLL_CTRL_CLKGATE   0x40000000
+#define BM_ICOLL_CTRL_SFTRST    0x80000000
+#define HW_ICOLL_STAT           0x30
+#define HW_ICOLL_PRIORITY0      (0x60 + 0 * 0x10)
+#define HW_ICOLL_PRIORITY1      (0x60 + 1 * 0x10)
+#define HW_ICOLL_PRIORITY2      (0x60 + 2 * 0x10)
+#define HW_ICOLL_PRIORITY3      (0x60 + 3 * 0x10)
+#define HW_ICOLL_PRIORITYn      0x60
+#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
new file mode 100644
index 000000000000..72514e8b0737
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
@@ -0,0 +1,89 @@
+/*
+ * stmp37xx: LCDIF register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
+#define REGS_LCDIF_PHYS 0x80030000
+#define REGS_LCDIF_SIZE 0x2000
+#define HW_LCDIF_CTRL           0x0
+#define BM_LCDIF_CTRL_COUNT     0x0000FFFF
+#define BP_LCDIF_CTRL_COUNT     0
+#define BM_LCDIF_CTRL_RUN       0x00010000
+#define BM_LCDIF_CTRL_WORD_LENGTH       0x00020000
+#define BM_LCDIF_CTRL_DATA_SELECT       0x00040000
+#define BM_LCDIF_CTRL_DOTCLK_MODE       0x00080000
+#define BM_LCDIF_CTRL_VSYNC_MODE        0x00100000
+#define BM_LCDIF_CTRL_DATA_SWIZZLE      0x00600000
+#define BP_LCDIF_CTRL_DATA_SWIZZLE      21
+#define BM_LCDIF_CTRL_BYPASS_COUNT      0x00800000
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS    0x06000000
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS    25
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR    0x08000000
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE       0x10000000
+#define BM_LCDIF_CTRL_CLKGATE   0x40000000
+#define BM_LCDIF_CTRL_SFTRST    0x80000000
+#define HW_LCDIF_CTRL1          0x10
+#define BM_LCDIF_CTRL1_RESET    0x00000001
+#define BP_LCDIF_CTRL1_RESET    0
+#define BM_LCDIF_CTRL1_MODE86   0x00000002
+#define BM_LCDIF_CTRL1_BUSY_ENABLE      0x00000004
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ   0x00000100
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ       0x00000200
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ    0x00000400
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ     0x00000800
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN        0x00001000
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT      0x000F0000
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT      16
+#define HW_LCDIF_TIMING         0x20
+#define HW_LCDIF_VDCTRL0        0x30
+#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
+#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT      0x00200000
+#define BM_LCDIF_VDCTRL0_ENABLE_POL     0x01000000
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL     0x02000000
+#define BM_LCDIF_VDCTRL0_HSYNC_POL      0x04000000
+#define BM_LCDIF_VDCTRL0_VSYNC_POL      0x08000000
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB      0x20000000
+#define HW_LCDIF_VDCTRL1        0x40
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD   0x000FFFFF
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD   0
+#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      0xFFF00000
+#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      20
+#define HW_LCDIF_VDCTRL2        0x50
+#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
+#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD   0x007FF800
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD   11
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      0xFF800000
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      23
+#define HW_LCDIF_VDCTRL3        0x60
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0x000001FF
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0x00FFF000
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    12
+#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON        0x01000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
new file mode 100644
index 000000000000..cc7b4702d1cd
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
@@ -0,0 +1,97 @@
+/*
+ * stmp37xx: LRADC register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
+#define HW_LRADC_CTRL0          0x0
+#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
+#define BP_LRADC_CTRL0_SCHEDULE 0
+#define BM_LRADC_CTRL0_XPLUS_ENABLE     0x00010000
+#define BM_LRADC_CTRL0_YPLUS_ENABLE     0x00020000
+#define BM_LRADC_CTRL0_XMINUS_ENABLE    0x00040000
+#define BM_LRADC_CTRL0_YMINUS_ENABLE    0x00080000
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x00100000
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
+#define BM_LRADC_CTRL0_CLKGATE  0x40000000
+#define BM_LRADC_CTRL0_SFTRST   0x80000000
+#define HW_LRADC_CTRL1          0x10
+#define BM_LRADC_CTRL1_LRADC0_IRQ       0x00000001
+#define BP_LRADC_CTRL1_LRADC0_IRQ       0
+#define BM_LRADC_CTRL1_LRADC5_IRQ       0x00000020
+#define BM_LRADC_CTRL1_LRADC6_IRQ       0x00000040
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN    0x00010000
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN    0x00200000
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN      0x01000000
+#define HW_LRADC_CTRL2          0x20
+#define BM_LRADC_CTRL2_BL_BRIGHTNESS    0x001F0000
+#define BP_LRADC_CTRL2_BL_BRIGHTNESS    16
+#define BM_LRADC_CTRL2_BL_MUX_SELECT    0x00200000
+#define BM_LRADC_CTRL2_BL_ENABLE        0x00400000
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO    0xFF000000
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO    24
+#define HW_LRADC_CTRL3          0x30
+#define BM_LRADC_CTRL3_CYCLE_TIME       0x00000300
+#define BP_LRADC_CTRL3_CYCLE_TIME       8
+#define HW_LRADC_STATUS         0x40
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x00000001
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
+#define HW_LRADC_CH0            (0x50 + 0 * 0x10)
+#define HW_LRADC_CH1            (0x50 + 1 * 0x10)
+#define HW_LRADC_CH2            (0x50 + 2 * 0x10)
+#define HW_LRADC_CH3            (0x50 + 3 * 0x10)
+#define HW_LRADC_CH4            (0x50 + 4 * 0x10)
+#define HW_LRADC_CH5            (0x50 + 5 * 0x10)
+#define HW_LRADC_CH6            (0x50 + 6 * 0x10)
+#define HW_LRADC_CH7            (0x50 + 7 * 0x10)
+#define HW_LRADC_CHn            0x50
+#define BM_LRADC_CHn_VALUE      0x0003FFFF
+#define BP_LRADC_CHn_VALUE      0
+#define BM_LRADC_CHn_NUM_SAMPLES        0x1F000000
+#define BP_LRADC_CHn_NUM_SAMPLES        24
+#define BM_LRADC_CHn_ACCUMULATE 0x20000000
+#define HW_LRADC_DELAY0         (0xD0 + 0 * 0x10)
+#define HW_LRADC_DELAY1         (0xD0 + 1 * 0x10)
+#define HW_LRADC_DELAY2         (0xD0 + 2 * 0x10)
+#define HW_LRADC_DELAY3         (0xD0 + 3 * 0x10)
+#define HW_LRADC_DELAYn         0xD0
+#define BM_LRADC_DELAYn_DELAY   0x000007FF
+#define BP_LRADC_DELAYn_DELAY   0
+#define BM_LRADC_DELAYn_LOOP_COUNT      0x0000F800
+#define BP_LRADC_DELAYn_LOOP_COUNT      11
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS  0x000F0000
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS  16
+#define BM_LRADC_DELAYn_KICK    0x00100000
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS  0xFF000000
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS  24
+#define HW_LRADC_CTRL4          0x140
+#define BM_LRADC_CTRL4_LRADC6SELECT     0x0F000000
+#define BP_LRADC_CTRL4_LRADC6SELECT     24
+#define BM_LRADC_CTRL4_LRADC7SELECT     0xF0000000
+#define BP_LRADC_CTRL4_LRADC7SELECT     28
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
new file mode 100644
index 000000000000..d5efce2388c7
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
@@ -0,0 +1,88 @@
+/*
+ * stmp37xx: PINCTRL register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_PINCTRL
+#define _MACH_REGS_PINCTRL
+#define REGS_PINCTRL_BASE       (STMP3XXX_REGS_BASE + 0x18000)
+#define HW_PINCTRL_MUXSEL0      0x100
+#define HW_PINCTRL_MUXSEL1      0x110
+#define HW_PINCTRL_MUXSEL2      0x120
+#define HW_PINCTRL_MUXSEL3      0x130
+#define HW_PINCTRL_MUXSEL4      0x140
+#define HW_PINCTRL_MUXSEL5      0x150
+#define HW_PINCTRL_MUXSEL6      0x160
+#define HW_PINCTRL_MUXSEL7      0x170
+#define HW_PINCTRL_DRIVE0       0x200
+#define HW_PINCTRL_DRIVE1       0x210
+#define HW_PINCTRL_DRIVE2       0x220
+#define HW_PINCTRL_DRIVE3       0x230
+#define HW_PINCTRL_DRIVE4       0x240
+#define HW_PINCTRL_DRIVE5       0x250
+#define HW_PINCTRL_DRIVE6       0x260
+#define HW_PINCTRL_DRIVE7       0x270
+#define HW_PINCTRL_DRIVE8       0x280
+#define HW_PINCTRL_DRIVE9       0x290
+#define HW_PINCTRL_DRIVE10      0x2A0
+#define HW_PINCTRL_DRIVE11      0x2B0
+#define HW_PINCTRL_DRIVE12      0x2C0
+#define HW_PINCTRL_DRIVE13      0x2D0
+#define HW_PINCTRL_DRIVE14      0x2E0
+#define HW_PINCTRL_PULL0        0x300
+#define HW_PINCTRL_PULL1        0x310
+#define HW_PINCTRL_PULL2        0x320
+#define HW_PINCTRL_PULL3        0x330
+#define HW_PINCTRL_DOUT0        0x400
+#define HW_PINCTRL_DOUT1        0x410
+#define HW_PINCTRL_DOUT2        0x420
+#define HW_PINCTRL_DIN0         0x500
+#define HW_PINCTRL_DIN1         0x510
+#define HW_PINCTRL_DIN2         0x520
+#define HW_PINCTRL_DOE0         0x600
+#define HW_PINCTRL_DOE1         0x610
+#define HW_PINCTRL_DOE2         0x620
+#define HW_PINCTRL_PIN2IRQ0     0x700
+#define HW_PINCTRL_PIN2IRQ1     0x710
+#define HW_PINCTRL_PIN2IRQ2     0x720
+#define HW_PINCTRL_IRQEN0       0x800
+#define HW_PINCTRL_IRQEN1       0x810
+#define HW_PINCTRL_IRQEN2       0x820
+#define HW_PINCTRL_IRQLEVEL0    0x900
+#define HW_PINCTRL_IRQLEVEL1    0x910
+#define HW_PINCTRL_IRQLEVEL2    0x920
+#define HW_PINCTRL_IRQPOL0      0xA00
+#define HW_PINCTRL_IRQPOL1      0xA10
+#define HW_PINCTRL_IRQPOL2      0xA20
+#define HW_PINCTRL_IRQSTAT0     0xB00
+#define HW_PINCTRL_IRQSTAT1     0xB10
+#define HW_PINCTRL_IRQSTAT2     0xB20
+#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
new file mode 100644
index 000000000000..0e733d74a229
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
@@ -0,0 +1,56 @@
+/*
+ * stmp37xx: POWER register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_POWER
+#define _MACH_REGS_POWER
+#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
+#define HW_POWER_CTRL           0x0
+#define BM_POWER_CTRL_CLKGATE   0x40000000
+#define HW_POWER_5VCTRL         0x10
+#define HW_POWER_MINPWR         0x20
+#define HW_POWER_CHARGE         0x30
+#define HW_POWER_VDDDCTRL       0x40
+#define HW_POWER_VDDACTRL       0x50
+#define HW_POWER_VDDIOCTRL      0x60
+#define BM_POWER_VDDIOCTRL_TRG  0x0000001F
+#define BP_POWER_VDDIOCTRL_TRG  0
+#define HW_POWER_STS            0xB0
+#define BM_POWER_STS_VBUSVALID  0x00000002
+#define BM_POWER_STS_BVALID     0x00000004
+#define BM_POWER_STS_AVALID     0x00000008
+#define BM_POWER_STS_DC_OK      0x00000100
+#define HW_POWER_RESET          0xE0
+#define HW_POWER_DEBUG          0xF0
+#define BM_POWER_DEBUG_BVALIDPIOLOCK    0x00000002
+#define BM_POWER_DEBUG_AVALIDPIOLOCK    0x00000004
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
+#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
new file mode 100644
index 000000000000..15966a1b62e0
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
@@ -0,0 +1,51 @@
+/*
+ * stmp37xx: PWM register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_PWM_BASE   (STMP3XXX_REGS_BASE + 0x64000)
+#define HW_PWM_CTRL             0x0
+#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
+#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE        0x00000020
+#define HW_PWM_ACTIVE0          (0x10 + 0 * 0x20)
+#define HW_PWM_ACTIVE1          (0x10 + 1 * 0x20)
+#define HW_PWM_ACTIVE2          (0x10 + 2 * 0x20)
+#define HW_PWM_ACTIVE3          (0x10 + 3 * 0x20)
+#define HW_PWM_ACTIVEn          0x10
+#define BM_PWM_ACTIVEn_ACTIVE   0x0000FFFF
+#define BP_PWM_ACTIVEn_ACTIVE   0
+#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
+#define BP_PWM_ACTIVEn_INACTIVE 16
+#define HW_PWM_PERIOD0          (0x20 + 0 * 0x20)
+#define HW_PWM_PERIOD1          (0x20 + 1 * 0x20)
+#define HW_PWM_PERIOD2          (0x20 + 2 * 0x20)
+#define HW_PWM_PERIOD3          (0x20 + 3 * 0x20)
+#define HW_PWM_PERIODn          0x20
+#define BM_PWM_PERIODn_PERIOD   0x0000FFFF
+#define BP_PWM_PERIODn_PERIOD   0
+#define BM_PWM_PERIODn_ACTIVE_STATE     0x00030000
+#define BP_PWM_PERIODn_ACTIVE_STATE     16
+#define BM_PWM_PERIODn_INACTIVE_STATE   0x000C0000
+#define BP_PWM_PERIODn_INACTIVE_STATE   18
+#define BM_PWM_PERIODn_CDIV     0x00700000
+#define BP_PWM_PERIODn_CDIV     20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..fac40edc38a1
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
@@ -0,0 +1,57 @@
+/*
+ * stmp37xx: RTC register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_RTC_BASE   (STMP3XXX_REGS_BASE + 0x5C000)
+#define REGS_RTC_PHYS   0x8005C000
+#define REGS_RTC_SIZE   0x2000
+#define HW_RTC_CTRL             0x0
+#define BM_RTC_CTRL_ALARM_IRQ_EN        0x00000001
+#define BP_RTC_CTRL_ALARM_IRQ_EN        0
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN      0x00000002
+#define BM_RTC_CTRL_ALARM_IRQ   0x00000004
+#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
+#define BM_RTC_CTRL_WATCHDOGEN  0x00000010
+#define HW_RTC_STAT             0x10
+#define BM_RTC_STAT_NEW_REGS    0x0000FF00
+#define BP_RTC_STAT_NEW_REGS    8
+#define BM_RTC_STAT_STALE_REGS  0x00FF0000
+#define BP_RTC_STAT_STALE_REGS  16
+#define BM_RTC_STAT_RTC_PRESENT 0x80000000
+#define HW_RTC_SECONDS          0x30
+#define HW_RTC_ALARM            0x40
+#define HW_RTC_WATCHDOG         0x50
+#define HW_RTC_PERSISTENT0      0x60
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN        0x00000002
+#define BM_RTC_PERSISTENT0_ALARM_EN     0x00000004
+#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      0x00000010
+#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      0x00000020
+#define BM_RTC_PERSISTENT0_ALARM_WAKE   0x00000080
+#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
+#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
+#define HW_RTC_PERSISTENT1      0x70
+#define HW_RTC_VERSION          0xD0
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
new file mode 100644
index 000000000000..cbde891a06c2
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
@@ -0,0 +1,101 @@
+/*
+ * stmp37xx: SSP register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_SSP_BASE   (STMP3XXX_REGS_BASE + 0x10000)
+#define REGS_SSP1_PHYS  0x80010000
+#define REGS_SSP2_PHYS  0x80034000
+#define REGS_SSP_SIZE   0x2000
+#define HW_SSP_CTRL0            0x0
+#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
+#define BP_SSP_CTRL0_XFER_COUNT 0
+#define BM_SSP_CTRL0_ENABLE     0x00010000
+#define BM_SSP_CTRL0_GET_RESP   0x00020000
+#define BM_SSP_CTRL0_LONG_RESP  0x00080000
+#define BM_SSP_CTRL0_WAIT_FOR_CMD       0x00100000
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ       0x00200000
+#define BM_SSP_CTRL0_BUS_WIDTH  0x00C00000
+#define BP_SSP_CTRL0_BUS_WIDTH  22
+#define BM_SSP_CTRL0_DATA_XFER  0x01000000
+#define BM_SSP_CTRL0_READ       0x02000000
+#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
+#define BM_SSP_CTRL0_LOCK_CS    0x08000000
+#define BM_SSP_CTRL0_RUN        0x20000000
+#define BM_SSP_CTRL0_CLKGATE    0x40000000
+#define BM_SSP_CTRL0_SFTRST     0x80000000
+#define HW_SSP_CMD0             0x10
+#define BM_SSP_CMD0_CMD         0x000000FF
+#define BP_SSP_CMD0_CMD         0
+#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
+#define BP_SSP_CMD0_BLOCK_COUNT 8
+#define BM_SSP_CMD0_BLOCK_SIZE  0x000F0000
+#define BP_SSP_CMD0_BLOCK_SIZE  16
+#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
+#define BM_SSP_CMD1_CMD_ARG     0xFFFFFFFF
+#define BP_SSP_CMD1_CMD_ARG     0
+#define HW_SSP_TIMING           0x50
+#define BM_SSP_TIMING_CLOCK_RATE        0x000000FF
+#define BP_SSP_TIMING_CLOCK_RATE        0
+#define BM_SSP_TIMING_CLOCK_DIVIDE      0x0000FF00
+#define BP_SSP_TIMING_CLOCK_DIVIDE      8
+#define BM_SSP_TIMING_TIMEOUT   0xFFFF0000
+#define BP_SSP_TIMING_TIMEOUT   16
+#define HW_SSP_CTRL1            0x60
+#define BM_SSP_CTRL1_SSP_MODE   0x0000000F
+#define BP_SSP_CTRL1_SSP_MODE   0
+#define BM_SSP_CTRL1_WORD_LENGTH        0x000000F0
+#define BP_SSP_CTRL1_WORD_LENGTH        4
+#define BM_SSP_CTRL1_POLARITY   0x00000200
+#define BM_SSP_CTRL1_PHASE      0x00000400
+#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ   0x00008000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x00010000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ   0x00020000
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ  0x00200000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN    0x00400000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ       0x00800000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x01000000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ   0x02000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x04000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ   0x08000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN    0x10000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ       0x20000000
+#define BM_SSP_CTRL1_SDIO_IRQ   0x80000000
+#define HW_SSP_DATA             0x70
+#define HW_SSP_SDRESP0          0x80
+#define HW_SSP_SDRESP1          0x90
+#define HW_SSP_SDRESP2          0xA0
+#define HW_SSP_SDRESP3          0xB0
+#define HW_SSP_STATUS           0xC0
+#define BM_SSP_STATUS_FIFO_EMPTY        0x00000020
+#define BM_SSP_STATUS_TIMEOUT   0x00001000
+#define BM_SSP_STATUS_RESP_TIMEOUT      0x00004000
+#define BM_SSP_STATUS_RESP_ERR  0x00008000
+#define BM_SSP_STATUS_RESP_CRC_ERR      0x00010000
+#define BM_SSP_STATUS_CARD_DETECT       0x10000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
new file mode 100644
index 000000000000..4af0f6edfa78
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
@@ -0,0 +1,49 @@
+/*
+ * stmp37xx: TIMROT register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _MACH_REGS_TIMROT
+#define _MACH_REGS_TIMROT
+#define REGS_TIMROT_BASE        (STMP3XXX_REGS_BASE + 0x68000)
+#define HW_TIMROT_ROTCTRL       0x0
+#define BM_TIMROT_ROTCTRL_CLKGATE       0x40000000
+#define BM_TIMROT_ROTCTRL_SFTRST        0x80000000
+#define HW_TIMROT_TIMCTRL0      (0x20 + 0 * 0x20)
+#define HW_TIMROT_TIMCTRL1      (0x20 + 1 * 0x20)
+#define HW_TIMROT_TIMCTRL2      (0x20 + 2 * 0x20)
+#define HW_TIMROT_TIMCTRLn      0x20
+#define BM_TIMROT_TIMCTRLn_SELECT       0x0000000F
+#define BP_TIMROT_TIMCTRLn_SELECT       0
+#define BM_TIMROT_TIMCTRLn_PRESCALE     0x00000030
+#define BP_TIMROT_TIMCTRLn_PRESCALE     4
+#define BM_TIMROT_TIMCTRLn_RELOAD       0x00000040
+#define BM_TIMROT_TIMCTRLn_UPDATE       0x00000080
+#define BM_TIMROT_TIMCTRLn_IRQ_EN       0x00004000
+#define BM_TIMROT_TIMCTRLn_IRQ  0x00008000
+#define HW_TIMROT_TIMCOUNT0     (0x30 + 0 * 0x20)
+#define HW_TIMROT_TIMCOUNT1     (0x30 + 1 * 0x20)
+#define HW_TIMROT_TIMCOUNT2     (0x30 + 2 * 0x20)
+#define HW_TIMROT_TIMCOUNTn     0x30
+#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
new file mode 100644
index 000000000000..0594275d860c
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
@@ -0,0 +1,85 @@
+/*
+ * stmp37xx: UARTAPP register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_UARTAPP_BASE       (STMP3XXX_REGS_BASE + 0x6C000)
+#define REGS_UARTAPP1_PHYS      0x8006C000
+#define REGS_UARTAPP_SIZE       0x2000
+#define HW_UARTAPP_CTRL0        0x0
+#define BM_UARTAPP_CTRL0_XFER_COUNT     0x0000FFFF
+#define BP_UARTAPP_CTRL0_XFER_COUNT     0
+#define BM_UARTAPP_CTRL0_RXTIMEOUT      0x07FF0000
+#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x08000000
+#define BM_UARTAPP_CTRL0_RUN    0x20000000
+#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
+#define BM_UARTAPP_CTRL1_XFER_COUNT     0x0000FFFF
+#define BP_UARTAPP_CTRL1_XFER_COUNT     0
+#define BM_UARTAPP_CTRL1_RUN    0x10000000
+#define HW_UARTAPP_CTRL2        0x20
+#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
+#define BP_UARTAPP_CTRL2_UARTEN 0
+#define BM_UARTAPP_CTRL2_TXE    0x00000100
+#define BM_UARTAPP_CTRL2_RXE    0x00000200
+#define BM_UARTAPP_CTRL2_RTS    0x00000800
+#define BM_UARTAPP_CTRL2_RTSEN  0x00004000
+#define BM_UARTAPP_CTRL2_CTSEN  0x00008000
+#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
+#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
+#define BM_UARTAPP_CTRL2_DMAONERR       0x04000000
+#define HW_UARTAPP_LINECTRL     0x30
+#define BM_UARTAPP_LINECTRL_BRK 0x00000001
+#define BP_UARTAPP_LINECTRL_BRK 0
+#define BM_UARTAPP_LINECTRL_PEN 0x00000002
+#define BM_UARTAPP_LINECTRL_EPS 0x00000004
+#define BM_UARTAPP_LINECTRL_STP2        0x00000008
+#define BM_UARTAPP_LINECTRL_FEN 0x00000010
+#define BM_UARTAPP_LINECTRL_WLEN        0x00000060
+#define BP_UARTAPP_LINECTRL_WLEN        5
+#define BM_UARTAPP_LINECTRL_SPS 0x00000080
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC        0x00003F00
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC        8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
+#define HW_UARTAPP_INTR         0x50
+#define BM_UARTAPP_INTR_CTSMIS  0x00000002
+#define BM_UARTAPP_INTR_RTIS    0x00000040
+#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
+#define BM_UARTAPP_INTR_RXIEN   0x00100000
+#define BM_UARTAPP_INTR_RTIEN   0x00400000
+#define HW_UARTAPP_DATA         0x60
+#define HW_UARTAPP_STAT         0x70
+#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
+#define BP_UARTAPP_STAT_RXCOUNT 0
+#define BM_UARTAPP_STAT_FERR    0x00010000
+#define BM_UARTAPP_STAT_PERR    0x00020000
+#define BM_UARTAPP_STAT_BERR    0x00040000
+#define BM_UARTAPP_STAT_OERR    0x00080000
+#define BM_UARTAPP_STAT_RXFE    0x01000000
+#define BM_UARTAPP_STAT_TXFF    0x02000000
+#define BM_UARTAPP_STAT_TXFE    0x08000000
+#define BM_UARTAPP_STAT_CTS     0x10000000
+#define HW_UARTAPP_VERSION      0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
new file mode 100644
index 000000000000..b810deb552a9
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
@@ -0,0 +1,268 @@
+/*
+ * stmp378x: UARTDBG register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_UARTDBG_BASE       (STMP3XXX_REGS_BASE + 0x70000)
+#define REGS_UARTDBG_PHYS       0x80070000
+#define REGS_UARTDBG_SIZE       0x2000
+#define HW_UARTDBGDR 0x00000000
+#define BP_UARTDBGDR_UNAVAILABLE      16
+#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGDR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
+#define BP_UARTDBGDR_RESERVED      12
+#define BM_UARTDBGDR_RESERVED 0x0000F000
+#define BF_UARTDBGDR_RESERVED(v)  \
+        (((v) << 12) & BM_UARTDBGDR_RESERVED)
+#define BM_UARTDBGDR_OE 0x00000800
+#define BM_UARTDBGDR_BE 0x00000400
+#define BM_UARTDBGDR_PE 0x00000200
+#define BM_UARTDBGDR_FE 0x00000100
+#define BP_UARTDBGDR_DATA      0
+#define BM_UARTDBGDR_DATA 0x000000FF
+#define BF_UARTDBGDR_DATA(v)  \
+        (((v) << 0) & BM_UARTDBGDR_DATA)
+#define HW_UARTDBGRSR_ECR 0x00000004
+#define BP_UARTDBGRSR_ECR_UNAVAILABLE      8
+#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
+        (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
+#define BP_UARTDBGRSR_ECR_EC      4
+#define BM_UARTDBGRSR_ECR_EC 0x000000F0
+#define BF_UARTDBGRSR_ECR_EC(v)  \
+        (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
+#define BM_UARTDBGRSR_ECR_OE 0x00000008
+#define BM_UARTDBGRSR_ECR_BE 0x00000004
+#define BM_UARTDBGRSR_ECR_PE 0x00000002
+#define BM_UARTDBGRSR_ECR_FE 0x00000001
+#define HW_UARTDBGFR 0x00000018
+#define BP_UARTDBGFR_UNAVAILABLE      16
+#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGFR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
+#define BP_UARTDBGFR_RESERVED      9
+#define BM_UARTDBGFR_RESERVED 0x0000FE00
+#define BF_UARTDBGFR_RESERVED(v)  \
+        (((v) << 9) & BM_UARTDBGFR_RESERVED)
+#define BM_UARTDBGFR_RI 0x00000100
+#define BM_UARTDBGFR_TXFE 0x00000080
+#define BM_UARTDBGFR_RXFF 0x00000040
+#define BM_UARTDBGFR_TXFF 0x00000020
+#define BM_UARTDBGFR_RXFE 0x00000010
+#define BM_UARTDBGFR_BUSY 0x00000008
+#define BM_UARTDBGFR_DCD 0x00000004
+#define BM_UARTDBGFR_DSR 0x00000002
+#define BM_UARTDBGFR_CTS 0x00000001
+#define HW_UARTDBGILPR 0x00000020
+#define BP_UARTDBGILPR_UNAVAILABLE      8
+#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGILPR_UNAVAILABLE(v) \
+        (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
+#define BP_UARTDBGILPR_ILPDVSR      0
+#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
+#define BF_UARTDBGILPR_ILPDVSR(v)  \
+        (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
+#define HW_UARTDBGIBRD 0x00000024
+#define BP_UARTDBGIBRD_UNAVAILABLE      16
+#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
+#define BP_UARTDBGIBRD_BAUD_DIVINT      0
+#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
+#define BF_UARTDBGIBRD_BAUD_DIVINT(v)  \
+        (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
+#define HW_UARTDBGFBRD 0x00000028
+#define BP_UARTDBGFBRD_UNAVAILABLE      8
+#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
+#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
+        (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
+#define BP_UARTDBGFBRD_RESERVED      6
+#define BM_UARTDBGFBRD_RESERVED 0x000000C0
+#define BF_UARTDBGFBRD_RESERVED(v)  \
+        (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
+#define BP_UARTDBGFBRD_BAUD_DIVFRAC      0
+#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
+#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v)  \
+        (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
+#define HW_UARTDBGLCR_H 0x0000002c
+#define BP_UARTDBGLCR_H_UNAVAILABLE      16
+#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
+#define BP_UARTDBGLCR_H_RESERVED      8
+#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
+#define BF_UARTDBGLCR_H_RESERVED(v)  \
+        (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
+#define BM_UARTDBGLCR_H_SPS 0x00000080
+#define BP_UARTDBGLCR_H_WLEN      5
+#define BM_UARTDBGLCR_H_WLEN 0x00000060
+#define BF_UARTDBGLCR_H_WLEN(v)  \
+        (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
+#define BM_UARTDBGLCR_H_FEN 0x00000010
+#define BM_UARTDBGLCR_H_STP2 0x00000008
+#define BM_UARTDBGLCR_H_EPS 0x00000004
+#define BM_UARTDBGLCR_H_PEN 0x00000002
+#define BM_UARTDBGLCR_H_BRK 0x00000001
+#define HW_UARTDBGCR 0x00000030
+#define BP_UARTDBGCR_UNAVAILABLE      16
+#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGCR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
+#define BM_UARTDBGCR_CTSEN 0x00008000
+#define BM_UARTDBGCR_RTSEN 0x00004000
+#define BM_UARTDBGCR_OUT2 0x00002000
+#define BM_UARTDBGCR_OUT1 0x00001000
+#define BM_UARTDBGCR_RTS 0x00000800
+#define BM_UARTDBGCR_DTR 0x00000400
+#define BM_UARTDBGCR_RXE 0x00000200
+#define BM_UARTDBGCR_TXE 0x00000100
+#define BM_UARTDBGCR_LBE 0x00000080
+#define BP_UARTDBGCR_RESERVED      3
+#define BM_UARTDBGCR_RESERVED 0x00000078
+#define BF_UARTDBGCR_RESERVED(v)  \
+        (((v) << 3) & BM_UARTDBGCR_RESERVED)
+#define BM_UARTDBGCR_SIRLP 0x00000004
+#define BM_UARTDBGCR_SIREN 0x00000002
+#define BM_UARTDBGCR_UARTEN 0x00000001
+#define HW_UARTDBGIFLS 0x00000034
+#define BP_UARTDBGIFLS_UNAVAILABLE      16
+#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
+#define BP_UARTDBGIFLS_RESERVED      6
+#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
+#define BF_UARTDBGIFLS_RESERVED(v)  \
+        (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
+#define BP_UARTDBGIFLS_RXIFLSEL      3
+#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
+#define BF_UARTDBGIFLS_RXIFLSEL(v)  \
+        (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
+#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY      0x0
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF       0x2
+#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5       0x5
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6       0x6
+#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7       0x7
+#define BP_UARTDBGIFLS_TXIFLSEL      0
+#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
+#define BF_UARTDBGIFLS_TXIFLSEL(v)  \
+        (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
+#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY    0x0
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER    0x1
+#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF       0x2
+#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
+#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS  0x4
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5       0x5
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6       0x6
+#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7       0x7
+#define HW_UARTDBGIMSC 0x00000038
+#define BP_UARTDBGIMSC_UNAVAILABLE      16
+#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
+#define BP_UARTDBGIMSC_RESERVED      11
+#define BM_UARTDBGIMSC_RESERVED 0x0000F800
+#define BF_UARTDBGIMSC_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
+#define BM_UARTDBGIMSC_OEIM 0x00000400
+#define BM_UARTDBGIMSC_BEIM 0x00000200
+#define BM_UARTDBGIMSC_PEIM 0x00000100
+#define BM_UARTDBGIMSC_FEIM 0x00000080
+#define BM_UARTDBGIMSC_RTIM 0x00000040
+#define BM_UARTDBGIMSC_TXIM 0x00000020
+#define BM_UARTDBGIMSC_RXIM 0x00000010
+#define BM_UARTDBGIMSC_DSRMIM 0x00000008
+#define BM_UARTDBGIMSC_DCDMIM 0x00000004
+#define BM_UARTDBGIMSC_CTSMIM 0x00000002
+#define BM_UARTDBGIMSC_RIMIM 0x00000001
+#define HW_UARTDBGRIS 0x0000003c
+#define BP_UARTDBGRIS_UNAVAILABLE      16
+#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGRIS_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
+#define BP_UARTDBGRIS_RESERVED      11
+#define BM_UARTDBGRIS_RESERVED 0x0000F800
+#define BF_UARTDBGRIS_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGRIS_RESERVED)
+#define BM_UARTDBGRIS_OERIS 0x00000400
+#define BM_UARTDBGRIS_BERIS 0x00000200
+#define BM_UARTDBGRIS_PERIS 0x00000100
+#define BM_UARTDBGRIS_FERIS 0x00000080
+#define BM_UARTDBGRIS_RTRIS 0x00000040
+#define BM_UARTDBGRIS_TXRIS 0x00000020
+#define BM_UARTDBGRIS_RXRIS 0x00000010
+#define BM_UARTDBGRIS_DSRRMIS 0x00000008
+#define BM_UARTDBGRIS_DCDRMIS 0x00000004
+#define BM_UARTDBGRIS_CTSRMIS 0x00000002
+#define BM_UARTDBGRIS_RIRMIS 0x00000001
+#define HW_UARTDBGMIS 0x00000040
+#define BP_UARTDBGMIS_UNAVAILABLE      16
+#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGMIS_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
+#define BP_UARTDBGMIS_RESERVED      11
+#define BM_UARTDBGMIS_RESERVED 0x0000F800
+#define BF_UARTDBGMIS_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGMIS_RESERVED)
+#define BM_UARTDBGMIS_OEMIS 0x00000400
+#define BM_UARTDBGMIS_BEMIS 0x00000200
+#define BM_UARTDBGMIS_PEMIS 0x00000100
+#define BM_UARTDBGMIS_FEMIS 0x00000080
+#define BM_UARTDBGMIS_RTMIS 0x00000040
+#define BM_UARTDBGMIS_TXMIS 0x00000020
+#define BM_UARTDBGMIS_RXMIS 0x00000010
+#define BM_UARTDBGMIS_DSRMMIS 0x00000008
+#define BM_UARTDBGMIS_DCDMMIS 0x00000004
+#define BM_UARTDBGMIS_CTSMMIS 0x00000002
+#define BM_UARTDBGMIS_RIMMIS 0x00000001
+#define HW_UARTDBGICR 0x00000044
+#define BP_UARTDBGICR_UNAVAILABLE      16
+#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGICR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
+#define BP_UARTDBGICR_RESERVED      11
+#define BM_UARTDBGICR_RESERVED 0x0000F800
+#define BF_UARTDBGICR_RESERVED(v)  \
+        (((v) << 11) & BM_UARTDBGICR_RESERVED)
+#define BM_UARTDBGICR_OEIC 0x00000400
+#define BM_UARTDBGICR_BEIC 0x00000200
+#define BM_UARTDBGICR_PEIC 0x00000100
+#define BM_UARTDBGICR_FEIC 0x00000080
+#define BM_UARTDBGICR_RTIC 0x00000040
+#define BM_UARTDBGICR_TXIC 0x00000020
+#define BM_UARTDBGICR_RXIC 0x00000010
+#define BM_UARTDBGICR_DSRMIC 0x00000008
+#define BM_UARTDBGICR_DCDMIC 0x00000004
+#define BM_UARTDBGICR_CTSMIC 0x00000002
+#define BM_UARTDBGICR_RIMIC 0x00000001
+#define HW_UARTDBGDMACR 0x00000048
+#define BP_UARTDBGDMACR_UNAVAILABLE      16
+#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
+#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
+        (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
+#define BP_UARTDBGDMACR_RESERVED      3
+#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
+#define BF_UARTDBGDMACR_RESERVED(v)  \
+        (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
+#define BM_UARTDBGDMACR_DMAONERR 0x00000004
+#define BM_UARTDBGDMACR_TXDMAE 0x00000002
+#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-imx/include/mach/io.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
index 9e197ae4590f..9145e22df32c 100644
--- a/arch/arm/mach-imx/include/mach/io.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
@@ -1,7 +1,8 @@
 /*
- *  arch/arm/mach-imxads/include/mach/io.h
+ * stmp37xx: USBCTL register definitions
 *
- *  Copyright (C) 1999 ARM Limited
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -15,14 +16,7 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
-#ifndef __ASM_ARM_ARCH_IO_H
+#define REGS_USBCTL_BASE        (STMP3XXX_REGS_BASE + 0x80000)
-#define __ASM_ARM_ARCH_IO_H
+#define REGS_USBCTL_PHYS        0x80000
-#define IO_SPACE_LIMIT 0xffffffff
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-#endif
diff --git a/arch/arm/mach-imx/include/mach/timex.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
index e22ba789546c..1a2ae9cbdfed 100644
--- a/arch/arm/mach-imx/include/mach/timex.h
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
@@ -1,7 +1,8 @@
 /*
- *  linux/include/asm-arm/imx/timex.h
+ * stmp37xx: USBCTRL register definitions
 *
- *  Copyright (C) 1999 ARM Limited
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -15,12 +16,7 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
+#define REGS_USBCTRL_BASE       (STMP3XXX_REGS_BASE + 0x80000)
-#ifndef __ASM_ARCH_TIMEX_H
+#define REGS_USBCTRL_PHYS       0x80080000
-#define __ASM_ARCH_TIMEX_H
-#define CLOCK_TICK_RATE         (16000000)
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
new file mode 100644
index 000000000000..b7fce0fbc560
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
@@ -0,0 +1,37 @@
+/*
+ * stmp37xx: USBPHY register definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#define REGS_USBPHY_BASE        (STMP3XXX_REGS_BASE + 0x7C000)
+#define HW_USBPHY_PWD           0x0
+#define HW_USBPHY_CTRL          0x30
+#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT        0x00000001
+#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT        0
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x00000002
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x00000010
+#define BM_USBPHY_CTRL_ENOTGIDDETECT    0x00000080
+#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN   0x00000800
+#define BM_USBPHY_CTRL_CLKGATE  0x40000000
+#define BM_USBPHY_CTRL_SFTRST   0x80000000
+#define HW_USBPHY_STATUS        0x40
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS       0x00000040
+#define BM_USBPHY_STATUS_OTGID_STATUS   0x00000100
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c
new file mode 100644
index 000000000000..8c7d6fb191a3
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/stmp37xx.c
@@ -0,0 +1,219 @@
+/*
+ * Freescale STMP37XX platform support
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/stmp3xxx.h>
+#include <mach/dma.h>
+#include <mach/platform.h>
+#include <mach/regs-icoll.h>
+#include <mach/regs-apbh.h>
+#include <mach/regs-apbx.h>
+#include "stmp37xx.h"
+/*
+ * IRQ handling
+ */
+static void stmp37xx_ack_irq(unsigned int irq)
+{
+        /* Disable IRQ */
+        stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
+                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
+        /* ACK current interrupt */
+        __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
+        /* Barrier */
+        (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
+}
+static void stmp37xx_mask_irq(unsigned int irq)
+{
+        /* IRQ disable */
+        stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
+                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
+}
+static void stmp37xx_unmask_irq(unsigned int irq)
+{
+        /* IRQ enable */
+        stmp3xxx_setl(0x04 << ((irq % 4) * 8),
+                REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
+}
+static struct irq_chip stmp37xx_chip = {
+        .ack    = stmp37xx_ack_irq,
+        .mask   = stmp37xx_mask_irq,
+        .unmask = stmp37xx_unmask_irq,
+};
+void __init stmp37xx_init_irq(void)
+{
+        stmp3xxx_init_irq(&stmp37xx_chip);
+}
+/*
+ * DMA interrupt handling
+ */
+void stmp3xxx_arch_dma_enable_interrupt(int channel)
+{
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
+                        REGS_APBH_BASE + HW_APBH_CTRL1);
+                break;
+        case STMP3XXX_BUS_APBX:
+                stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
+                        REGS_APBX_BASE + HW_APBX_CTRL1);
+                break;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
+void stmp3xxx_arch_dma_clear_interrupt(int channel)
+{
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
+                                REGS_APBH_BASE + HW_APBH_CTRL1);
+                break;
+        case STMP3XXX_BUS_APBX:
+                stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
+                                REGS_APBX_BASE + HW_APBX_CTRL1);
+                break;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
+int stmp3xxx_arch_dma_is_interrupt(int channel)
+{
+        int r = 0;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
+                        (1 << STMP3XXX_DMA_CHANNEL(channel));
+                break;
+        case STMP3XXX_BUS_APBX:
+                r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
+                        (1 << STMP3XXX_DMA_CHANNEL(channel));
+                break;
+        }
+        return r;
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
+void stmp3xxx_arch_dma_reset_channel(int channel)
+{
+        unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                /* Reset channel and wait for it to complete */
+                stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
+                        REGS_APBH_BASE + HW_APBH_CTRL0);
+                while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
+                       (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
+                                cpu_relax();
+                break;
+        case STMP3XXX_BUS_APBX:
+                stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
+                        REGS_APBX_BASE + HW_APBX_CTRL0);
+                while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
+                       (chbit << BP_APBX_CTRL0_RESET_CHANNEL))
+                                cpu_relax();
+                break;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
+void stmp3xxx_arch_dma_freeze(int channel)
+{
+        unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
+                break;
+        case STMP3XXX_BUS_APBX:
+                stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
+                break;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
+void stmp3xxx_arch_dma_unfreeze(int channel)
+{
+        unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
+                break;
+        case STMP3XXX_BUS_APBX:
+                stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
+                break;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
+/*
+ * The registers are all very closely mapped, so we might as well map them all
+ * with a single mapping
+ *
+ * Logical      Physical
+ * f0000000     80000000        On-chip registers
+ * f1000000     00000000        32k on-chip SRAM
+ */
+static struct map_desc stmp37xx_io_desc[] __initdata = {
+        {
+                .virtual        = (u32)STMP3XXX_REGS_BASE,
+                .pfn            = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = (u32)STMP3XXX_OCRAM_BASE,
+                .pfn            = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
+                .length         = STMP3XXX_OCRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+void __init stmp37xx_map_io(void)
+{
+        iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
+}
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h
new file mode 100644
index 000000000000..0b75fb796a64
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/stmp37xx.h
@@ -0,0 +1,24 @@
+/*
+ * Freescale STMP37XX/STMP378X internal functions and data declarations
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_STMP37XX_H
+#define __MACH_STMP37XX_H
+void stmp37xx_map_io(void);
+void stmp37xx_init_irq(void);
+#endif /* __MACH_STMP37XX_H */
diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
new file mode 100644
index 000000000000..394f21ab59e6
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
@@ -0,0 +1,101 @@
+/*
+ * Freescale STMP37XX development board support
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/stmp3xxx.h>
+#include <mach/pins.h>
+#include <mach/pinmux.h>
+#include "stmp37xx.h"
+/*
+ * List of STMP37xx development board specific devices
+ */
+static struct platform_device *stmp37xx_devb_devices[] = {
+        &stmp3xxx_dbguart,
+        &stmp3xxx_appuart,
+};
+static struct pin_desc dbguart_pins_0[] = {
+        { PINID_PWM0, PIN_FUN3, },
+        { PINID_PWM1, PIN_FUN3, },
+};
+struct pin_desc appuart_pins_0[] = {
+        { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+        { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
+};
+static struct pin_group appuart_pins[] = {
+        [0] = {
+                .pins           = appuart_pins_0,
+                .nr_pins        = ARRAY_SIZE(appuart_pins_0),
+        },
+        /* 37xx has the only app uart */
+};
+static struct pin_group dbguart_pins[] = {
+        [0] = {
+                .pins           = dbguart_pins_0,
+                .nr_pins        = ARRAY_SIZE(dbguart_pins_0),
+        },
+};
+static int dbguart_pins_control(int id, int request)
+{
+        int r = 0;
+        if (request)
+                r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
+        else
+                stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
+        return r;
+}
+static void __init stmp37xx_devb_init(void)
+{
+        stmp3xxx_pinmux_init(NR_REAL_IRQS);
+        /* Init STMP3xxx platform */
+        stmp3xxx_init();
+        stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
+        stmp3xxx_appuart.dev.platform_data = appuart_pins;
+        /* Add STMP37xx development board devices */
+        platform_add_devices(stmp37xx_devb_devices,
+                        ARRAY_SIZE(stmp37xx_devb_devices));
+}
+MACHINE_START(STMP37XX, "STMP37XX")
+        .phys_io        = 0x80000000,
+        .io_pg_offst    = ((0xf0000000) >> 18) & 0xfffc,
+        .boot_params    = 0x40000100,
+        .map_io         = stmp37xx_map_io,
+        .init_irq       = stmp37xx_init_irq,
+        .timer          = &stmp3xxx_timer,
+        .init_machine   = stmp37xx_devb_init,
+MACHINE_END
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
new file mode 100644
index 000000000000..337b9aabce49
--- /dev/null
+++ b/arch/arm/mach-u300/Kconfig
@@ -0,0 +1,105 @@
+if ARCH_U300
+menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
+comment "ST-Ericsson Mobile Platform Products"
+config MACH_U300
+        bool "U300"
+comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
+choice
+        prompt "U300/U330/U335/U365 system type"
+        default MACH_U300_BS2X
+        ---help---
+        You need to select the target system, i.e. the
+        U300/U330/U335/U365 board that you want to compile your kernel
+        for.
+config MACH_U300_BS2X
+        bool "S26/S26/B25/B26 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S26/S25 test products. (Also works on
+                B26/B25 big boards.)
+config MACH_U300_BS330
+        bool "S330/B330 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S330/B330 test products.
+config MACH_U300_BS335
+        bool "S335/B335 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S335/B335 test products.
+config MACH_U300_BS365
+        bool "S365/B365 Test Products"
+        depends on MACH_U300
+        help
+                Select this if you're developing on the
+                S365/B365 test products.
+endchoice
+choice
+        prompt "Memory configuration"
+        default MACH_U300_SINGLE_RAM
+        ---help---
+        You have to config the kernel according to the physical memory
+        configuration.
+config MACH_U300_SINGLE_RAM
+        bool "Single RAM"
+        help
+                Select this if you want support for Single RAM phones.
+config MACH_U300_DUAL_RAM
+        bool "Dual RAM"
+        help
+                Select this if you want support for Dual RAM phones.
+                This is two RAM memorys on different EMIFs.
+endchoice
+config U300_DEBUG
+        bool "Debug support for U300"
+        depends on PM
+        help
+                Debug support for U300 in sysfs, procfs etc.
+config MACH_U300_SEMI_IS_SHARED
+        bool "The SEMI is used by both the access and application side"
+        depends on MACH_U300
+        help
+                This makes it possible to use the SEMI (Shared External
+                Memory Interface) from both from access and application
+                side.
+comment "All the settings below must match the bootloader's settings"
+config MACH_U300_ACCESS_MEM_SIZE
+       int "Access CPU memory allocation"
+       range 7 25
+       depends on MACH_U300_SINGLE_RAM
+       default 13
+       help
+                How much memory in MiB that the Access side CPU has allocated
+config MACH_U300_2MB_ALIGNMENT_FIX
+       bool "2MiB alignment fix"
+       depends on MACH_U300_SINGLE_RAM
+       default y
+       help
+                If yes and the Access side CPU has allocated an odd size in
+                MiB, this fix gives you one MiB extra that would otherwise be
+                lost due to Linux 2 MiB alignment policy.
+endmenu
+endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
new file mode 100644
index 000000000000..24950e0df4b4
--- /dev/null
+++ b/arch/arm/mach-u300/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile for the linux kernel, U300 machine.
+#
+obj-y           := core.o clock.o timer.o gpio.o padmux.o
+obj-m           :=
+obj-n           :=
+obj-            :=
+obj-$(CONFIG_ARCH_U300)           += u300.o
+obj-$(CONFIG_MMC)                 += mmc.o
diff --git a/arch/arm/mach-u300/Makefile.boot b/arch/arm/mach-u300/Makefile.boot
new file mode 100644
index 000000000000..6fbfc6ea2d35
--- /dev/null
+++ b/arch/arm/mach-u300/Makefile.boot
@@ -0,0 +1,15 @@
+# Note: the following conditions must always be true:
+#   ZRELADDR == virt_to_phys(TEXTADDR)
+#   PARAMS_PHYS must be within 4MB of ZRELADDR
+#   INITRD_PHYS must be in RAM
+ifdef CONFIG_MACH_U300_SINGLE_RAM
+     zreladdr-y := 0x28E08000
+  params_phys-y := 0x28E00100
+else
+     zreladdr-y := 0x48008000
+  params_phys-y := 0x48000100
+endif
+# This isn't used.
+#initrd_phys-y  := 0x29800000
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
new file mode 100644
index 000000000000..5cd04d6751b3
--- /dev/null
+++ b/arch/arm/mach-u300/clock.c
@@ -0,0 +1,1487 @@
+/*
+ *
+ * arch/arm/mach-u300/clock.c
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Define clocks in the app platform.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ *
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/io.h>
+#include <asm/clkdev.h>
+#include <mach/hardware.h>
+#include <mach/syscon.h>
+#include "clock.h"
+/*
+ * TODO:
+ * - move all handling of the CCR register into this file and create
+ *   a spinlock for the CCR register
+ * - switch to the clkdevice lookup mechanism that maps clocks to
+ *   device ID:s instead when it becomes available in kernel 2.6.29.
+ * - implement rate get/set for all clocks that need it.
+ */
+/*
+ * Syscon clock I/O registers lock so clock requests don't collide
+ * NOTE: this is a local lock only used to lock access to clock and
+ * reset registers in syscon.
+ */
+static DEFINE_SPINLOCK(syscon_clkreg_lock);
+static DEFINE_SPINLOCK(syscon_resetreg_lock);
+/*
+ * The clocking hierarchy currently looks like this.
+ * NOTE: the idea is NOT to show how the clocks are routed on the chip!
+ * The ideas is to show dependencies, so a clock higher up in the
+ * hierarchy has to be on in order for another clock to be on. Now,
+ * both CPU and DMA can actually be on top of the hierarchy, and that
+ * is not modeled currently. Instead we have the backbone AMBA bus on
+ * top. This bus cannot be programmed in any way but conceptually it
+ * needs to be active for the bridges and devices to transport data.
+ *
+ * Please be aware that a few clocks are hw controlled, which mean that
+ * the hw itself can turn on/off or change the rate of the clock when
+ * needed!
+ *
+ *  AMBA bus
+ *  |
+ *  +- CPU
+ *  +- NANDIF NAND Flash interface
+ *  +- SEMI Shared Memory interface
+ *  +- ISP Image Signal Processor (U335 only)
+ *  +- CDS (U335 only)
+ *  +- DMA Direct Memory Access Controller
+ *  +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
+ *  +- APEX
+ *  +- VIDEO_ENC AVE2/3 Video Encoder
+ *  +- XGAM Graphics Accelerator Controller
+ *  +- AHB
+ *  |
+ *  +- ahb:0 AHB Bridge
+ *  |  |
+ *  |  +- ahb:1 INTCON Interrupt controller
+ *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
+ *  |  +- ahb:4 EMIF   External Memory interface
+ *  |
+ *  +- fast:0 FAST bridge
+ *  |  |
+ *  |  +- fast:1 MMCSD MMC/SD card reader controller
+ *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
+ *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
+ *  |  +- fast:4 I2C0  I2C channel 0 controller
+ *  |  +- fast:5 I2C1  I2C channel 1 controller
+ *  |  +- fast:6 SPI   SPI controller
+ *  |  +- fast:7 UART1 Secondary UART (U335 only)
+ *  |
+ *  +- slow:0 SLOW bridge
+ *     |
+ *     +- slow:1 SYSCON (not possible to control)
+ *     +- slow:2 WDOG Watchdog
+ *     +- slow:3 UART0 primary UART
+ *     +- slow:4 TIMER_APP Application timer - used in Linux
+ *     +- slow:5 KEYPAD controller
+ *     +- slow:6 GPIO controller
+ *     +- slow:7 RTC controller
+ *     +- slow:8 BT Bus Tracer (not used currently)
+ *     +- slow:9 EH Event Handler (not used currently)
+ *     +- slow:a TIMER_ACC Access style timer (not used currently)
+ *     +- slow:b PPM (U335 only, what is that?)
+ */
+/*
+ * Reset control functions. We remember if a block has been
+ * taken out of reset and don't remove the reset assertion again
+ * and vice versa. Currently we only remove resets so the
+ * enablement function is defined out.
+ */
+static void syscon_block_reset_enable(struct clk *clk)
+{
+        u16 val;
+        unsigned long iflags;
+        /* Not all blocks support resetting */
+        if (!clk->res_reg || !clk->res_mask)
+                return;
+        spin_lock_irqsave(&syscon_resetreg_lock, iflags);
+        val = readw(clk->res_reg);
+        val |= clk->res_mask;
+        writew(val, clk->res_reg);
+        spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
+        clk->reset = true;
+}
+static void syscon_block_reset_disable(struct clk *clk)
+{
+        u16 val;
+        unsigned long iflags;
+        /* Not all blocks support resetting */
+        if (!clk->res_reg || !clk->res_mask)
+                return;
+        spin_lock_irqsave(&syscon_resetreg_lock, iflags);
+        val = readw(clk->res_reg);
+        val &= ~clk->res_mask;
+        writew(val, clk->res_reg);
+        spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
+        clk->reset = false;
+}
+int __clk_get(struct clk *clk)
+{
+        u16 val;
+        /* The MMC and MSPRO clocks need some special set-up */
+        if (!strcmp(clk->name, "MCLK")) {
+                /* Set default MMC clock divisor to 18.9 MHz */
+                writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
+                val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
+                /* Disable the MMC feedback clock */
+                val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
+                /* Disable MSPRO frequency */
+                val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
+                writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
+        }
+        if (!strcmp(clk->name, "MSPRO")) {
+                val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
+                /* Disable the MMC feedback clock */
+                val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
+                /* Enable MSPRO frequency */
+                val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
+                writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
+        }
+        return 1;
+}
+EXPORT_SYMBOL(__clk_get);
+void __clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(__clk_put);
+static void syscon_clk_disable(struct clk *clk)
+{
+        unsigned long iflags;
+        /* Don't touch the hardware controlled clocks */
+        if (clk->hw_ctrld)
+                return;
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+static void syscon_clk_enable(struct clk *clk)
+{
+        unsigned long iflags;
+        /* Don't touch the hardware controlled clocks */
+        if (clk->hw_ctrld)
+                return;
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+static u16 syscon_clk_get_rate(void)
+{
+        u16 val;
+        unsigned long iflags;
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+        return val;
+}
+#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
+static void enable_i2s0_vcxo(void)
+{
+        u16 val;
+        unsigned long iflags;
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        /* Set I2S0 to use the VCXO 26 MHz clock */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val |= U300_SYSCON_CCR_TURN_VCXO_ON;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+static void enable_i2s1_vcxo(void)
+{
+        u16 val;
+        unsigned long iflags;
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        /* Set I2S1 to use the VCXO 26 MHz clock */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val |= U300_SYSCON_CCR_TURN_VCXO_ON;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+static void disable_i2s0_vcxo(void)
+{
+        u16 val;
+        unsigned long iflags;
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        /* Disable I2S0 use of the VCXO 26 MHz clock */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        /* Deactivate VCXO if noone else is using VCXO */
+        if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
+                val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+static void disable_i2s1_vcxo(void)
+{
+        u16 val;
+        unsigned long iflags;
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        /* Disable I2S1 use of the VCXO 26 MHz clock */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        /* Deactivate VCXO if noone else is using VCXO */
+        if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
+                val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
+static void syscon_clk_rate_set_mclk(unsigned long rate)
+{
+        u16 val;
+        u32 reg;
+        unsigned long iflags;
+        switch (rate) {
+        case 18900000:
+                val = 0x0054;
+                break;
+        case 20800000:
+                val = 0x0044;
+                break;
+        case 23100000:
+                val = 0x0043;
+                break;
+        case 26000000:
+                val = 0x0033;
+                break;
+        case 29700000:
+                val = 0x0032;
+                break;
+        case 34700000:
+                val = 0x0022;
+                break;
+        case 41600000:
+                val = 0x0021;
+                break;
+        case 52000000:
+                val = 0x0011;
+                break;
+        case 104000000:
+                val = 0x0000;
+                break;
+        default:
+                printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
+                       rate);
+                return;
+        }
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
+                ~U300_SYSCON_MMF0R_MASK;
+        writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+void syscon_clk_rate_set_cpuclk(unsigned long rate)
+{
+        u16 val;
+        unsigned long iflags;
+        switch (rate) {
+        case 13000000:
+                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
+                break;
+        case 52000000:
+                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
+                break;
+        case 104000000:
+                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
+                break;
+        case 208000000:
+                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
+                break;
+        default:
+                return;
+        }
+        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
+        val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
+                ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
+}
+EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
+void clk_disable(struct clk *clk)
+{
+        unsigned long iflags;
+        spin_lock_irqsave(&clk->lock, iflags);
+        if (clk->usecount > 0 && !(--clk->usecount)) {
+                /* some blocks lack clocking registers and cannot be disabled */
+                if (clk->disable)
+                        clk->disable(clk);
+                if (likely((u32)clk->parent))
+                        clk_disable(clk->parent);
+        }
+#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
+        if (unlikely(!strcmp(clk->name, "I2S0")))
+                disable_i2s0_vcxo();
+        if (unlikely(!strcmp(clk->name, "I2S1")))
+                disable_i2s1_vcxo();
+#endif
+        spin_unlock_irqrestore(&clk->lock, iflags);
+}
+EXPORT_SYMBOL(clk_disable);
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+        unsigned long iflags;
+        spin_lock_irqsave(&clk->lock, iflags);
+        if (clk->usecount++ == 0) {
+                if (likely((u32)clk->parent))
+                        ret = clk_enable(clk->parent);
+                if (unlikely(ret != 0))
+                        clk->usecount--;
+                else {
+                        /* remove reset line (we never enable reset again) */
+                        syscon_block_reset_disable(clk);
+                        /* clocks without enable function are always on */
+                        if (clk->enable)
+                                clk->enable(clk);
+#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
+                        if (unlikely(!strcmp(clk->name, "I2S0")))
+                                enable_i2s0_vcxo();
+                        if (unlikely(!strcmp(clk->name, "I2S1")))
+                                enable_i2s1_vcxo();
+#endif
+                }
+        }
+        spin_unlock_irqrestore(&clk->lock, iflags);
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+/* Returns the clock rate in Hz */
+static unsigned long clk_get_rate_cpuclk(struct clk *clk)
+{
+        u16 val;
+        val = syscon_clk_get_rate();
+        switch (val) {
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
+                return 13000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
+                return 52000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
+                return 104000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
+                return 208000000;
+        default:
+                break;
+        }
+        return clk->rate;
+}
+static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
+{
+        u16 val;
+        val = syscon_clk_get_rate();
+        switch (val) {
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
+                return 6500000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
+                return 26000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
+                return 52000000;
+        default:
+                break;
+        }
+        return clk->rate;
+}
+static unsigned long clk_get_rate_emif_clk(struct clk *clk)
+{
+        u16 val;
+        val = syscon_clk_get_rate();
+        switch (val) {
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
+                return 13000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
+                return 52000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
+                return 104000000;
+        default:
+                break;
+        }
+        return clk->rate;
+}
+static unsigned long clk_get_rate_xgamclk(struct clk *clk)
+{
+        u16 val;
+        val = syscon_clk_get_rate();
+        switch (val) {
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
+                return 6500000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
+                return 26000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
+                return 52000000;
+        default:
+                break;
+        }
+        return clk->rate;
+}
+static unsigned long clk_get_rate_mclk(struct clk *clk)
+{
+        u16 val;
+        val = syscon_clk_get_rate();
+        switch (val) {
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
+                /*
+                 * Here, the 208 MHz PLL gets shut down and the always
+                 * on 13 MHz PLL used for RTC etc kicks into use
+                 * instead.
+                 */
+                return 13000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
+        {
+                /*
+                 * This clock is under program control. The register is
+                 * divided in two nybbles, bit 7-4 gives cycles-1 to count
+                 * high, bit 3-0 gives cycles-1 to count low. Distribute
+                 * these with no more than 1 cycle difference between
+                 * low and high and add low and high to get the actual
+                 * divisor. The base PLL is 208 MHz. Writing 0x00 will
+                 * divide by 1 and 1 so the highest frequency possible
+                 * is 104 MHz.
+                 *
+                 * e.g. 0x54 =>
+                 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
+                 */
+                u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
+                        U300_SYSCON_MMF0R_MASK;
+                switch (val) {
+                case 0x0054:
+                        return 18900000;
+                case 0x0044:
+                        return 20800000;
+                case 0x0043:
+                        return 23100000;
+                case 0x0033:
+                        return 26000000;
+                case 0x0032:
+                        return 29700000;
+                case 0x0022:
+                        return 34700000;
+                case 0x0021:
+                        return 41600000;
+                case 0x0011:
+                        return 52000000;
+                case 0x0000:
+                        return 104000000;
+                default:
+                        break;
+                }
+        }
+        default:
+                break;
+        }
+        return clk->rate;
+}
+static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
+{
+        u16 val;
+        val = syscon_clk_get_rate();
+        switch (val) {
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
+                return 13000000;
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
+        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
+                return 26000000;
+        default:
+                break;
+        }
+        return clk->rate;
+}
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+        else
+                return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
+{
+        if (rate >= 18900000)
+                return 18900000;
+        if (rate >= 20800000)
+                return 20800000;
+        if (rate >= 23100000)
+                return 23100000;
+        if (rate >= 26000000)
+                return 26000000;
+        if (rate >= 29700000)
+                return 29700000;
+        if (rate >= 34700000)
+                return 34700000;
+        if (rate >= 41600000)
+                return 41600000;
+        if (rate >= 52000000)
+                return 52000000;
+        return -EINVAL;
+}
+static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
+{
+        if (rate >= 13000000)
+                return 13000000;
+        if (rate >= 52000000)
+                return 52000000;
+        if (rate >= 104000000)
+                return 104000000;
+        if (rate >= 208000000)
+                return 208000000;
+        return -EINVAL;
+}
+/*
+ * This adjusts a requested rate to the closest exact rate
+ * a certain clock can provide. For a fixed clock it's
+ * mostly clk->rate.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */
+        /* Else default to fixed value */
+        if (clk->round_rate) {
+                return (long) clk->round_rate(clk, rate);
+        } else {
+                printk(KERN_ERR "clock: Failed to round rate of %s\n",
+                       clk->name);
+        }
+        return (long) clk->rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
+{
+        syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
+        return 0;
+}
+static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
+{
+        syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
+        return 0;
+}
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        /* TODO: set for EMIFCLK and AHBCLK */
+        /* Else assume the clock is fixed and fail */
+        if (clk->set_rate) {
+                return clk->set_rate(clk, rate);
+        } else {
+                printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
+                       clk->name, rate);
+                return -EINVAL;
+        }
+}
+EXPORT_SYMBOL(clk_set_rate);
+/*
+ * Clock definitions. The clock parents are set to respective
+ * bridge and the clock framework makes sure that the clocks have
+ * parents activated and are brought out of reset when in use.
+ *
+ * Clocks that have hw_ctrld = true are hw controlled, and the hw
+ * can by itself turn these clocks on and off.
+ * So in other words, we don't really have to care about them.
+ */
+static struct clk amba_clk = {
+        .name       = "AMBA",
+        .rate       = 52000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = false,
+};
+/*
+ * These blocks are connected directly to the AMBA bus
+ * with no bridge.
+ */
+static struct clk cpu_clk = {
+        .name       = "CPU",
+        .parent     = &amba_clk,
+        .rate       = 208000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_CPU_RESET_EN,
+        .set_rate   = clk_set_rate_cpuclk,
+        .get_rate   = clk_get_rate_cpuclk,
+        .round_rate = clk_round_rate_cpuclk,
+};
+static struct clk nandif_clk = {
+        .name       = "NANDIF",
+        .parent     = &amba_clk,
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_NANDIF_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk semi_clk = {
+        .name       = "SEMI",
+        .parent     = &amba_clk,
+        .rate       = 0, /* FIXME */
+        /* It is not possible to reset SEMI */
+        .hw_ctrld   = false,
+        .reset      = false,
+        .clk_val    = U300_SYSCON_SBCER_SEMI_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+#ifdef CONFIG_MACH_U300_BS335
+static struct clk isp_clk = {
+        .name       = "ISP",
+        .parent     = &amba_clk,
+        .rate       = 0, /* FIXME */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_ISP_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_ISP_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk cds_clk = {
+        .name       = "CDS",
+        .parent     = &amba_clk,
+        .rate       = 0, /* FIXME */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_CDS_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_CDS_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+#endif
+static struct clk dma_clk = {
+        .name       = "DMA",
+        .parent     = &amba_clk,
+        .rate       = 52000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_DMAC_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_DMAC_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk aaif_clk = {
+        .name       = "AAIF",
+        .parent     = &amba_clk,
+        .rate       = 52000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_AAIF_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_AAIF_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk apex_clk = {
+        .name       = "APEX",
+        .parent     = &amba_clk,
+        .rate       = 0, /* FIXME */
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_APEX_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_APEX_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk video_enc_clk = {
+        .name       = "VIDEO_ENC",
+        .parent     = &amba_clk,
+        .rate       = 208000000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = false,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        /* This has XGAM in the name but refers to the video encoder */
+        .res_mask   = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk xgam_clk = {
+        .name       = "XGAMCLK",
+        .parent     = &amba_clk,
+        .rate       = 52000000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_XGAM_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_XGAM_CLK_EN,
+        .get_rate   = clk_get_rate_xgamclk,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+/* This clock is used to activate the video encoder */
+static struct clk ahb_clk = {
+        .name       = "AHB",
+        .parent     = &amba_clk,
+        .rate       = 52000000, /* this varies! */
+        .hw_ctrld   = false, /* This one is set to false due to HW bug */
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_AHB_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_AHB_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_ahb_clk,
+};
+/*
+ * Clocks on the AHB bridge
+ */
+static struct clk ahb_subsys_clk = {
+        .name       = "AHB_SUBSYS",
+        .parent     = &amba_clk,
+        .rate       = 52000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = false,
+        .clk_val    = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_ahb_clk,
+};
+static struct clk intcon_clk = {
+        .name       = "INTCON",
+        .parent     = &ahb_subsys_clk,
+        .rate       = 52000000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_INTCON_RESET_EN,
+        /* INTCON can be reset but not clock-gated */
+};
+static struct clk mspro_clk = {
+        .name       = "MSPRO",
+        .parent     = &ahb_subsys_clk,
+        .rate       = 0, /* FIXME */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_MSPRO_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_MSPRO_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk emif_clk = {
+        .name       = "EMIF",
+        .parent     = &ahb_subsys_clk,
+        .rate       = 104000000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
+        .res_mask   = U300_SYSCON_RRR_EMIF_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_EMIF_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_emif_clk,
+};
+/*
+ * Clocks on the FAST bridge
+ */
+static struct clk fast_clk = {
+        .name       = "FAST_BRIDGE",
+        .parent     = &amba_clk,
+        .rate       = 13000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk mmcsd_clk = {
+        .name       = "MCLK",
+        .parent     = &fast_clk,
+        .rate       = 18900000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_MMC_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_MMC_CLK_EN,
+        .get_rate   = clk_get_rate_mclk,
+        .set_rate   = clk_set_rate_mclk,
+        .round_rate = clk_round_rate_mclk,
+        .disable    = syscon_clk_disable,
+        .enable     = syscon_clk_enable,
+};
+static struct clk i2s0_clk = {
+        .name       = "i2s0",
+        .parent     = &fast_clk,
+        .rate       = 26000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_i2s_i2c_spi,
+};
+static struct clk i2s1_clk = {
+        .name       = "i2s1",
+        .parent     = &fast_clk,
+        .rate       = 26000000, /* this varies! */
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_i2s_i2c_spi,
+};
+static struct clk i2c0_clk = {
+        .name       = "I2C0",
+        .parent     = &fast_clk,
+        .rate       = 26000000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_I2C0_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_i2s_i2c_spi,
+};
+static struct clk i2c1_clk = {
+        .name       = "I2C1",
+        .parent     = &fast_clk,
+        .rate       = 26000000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_I2C1_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_i2s_i2c_spi,
+};
+static struct clk spi_clk = {
+        .name       = "SPI",
+        .parent     = &fast_clk,
+        .rate       = 26000000, /* this varies! */
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_SPI_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_SPI_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+        .get_rate   = clk_get_rate_i2s_i2c_spi,
+};
+#ifdef CONFIG_MACH_U300_BS335
+static struct clk uart1_clk = {
+        .name       = "UART1",
+        .parent     = &fast_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
+        .res_mask   = U300_SYSCON_RFR_UART1_RESET_ENABLE,
+        .clk_val    = U300_SYSCON_SBCER_UART1_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+#endif
+/*
+ * Clocks on the SLOW bridge
+ */
+static struct clk slow_clk = {
+        .name       = "SLOW_BRIDGE",
+        .parent     = &amba_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+/* TODO: implement SYSCON clock? */
+static struct clk wdog_clk = {
+        .name       = "WDOG",
+        .parent     = &slow_clk,
+        .hw_ctrld   = false,
+        .rate       = 32768,
+        .reset      = false,
+        /* This is always on, cannot be enabled/disabled or reset */
+};
+/* This one is hardwired to PLL13 */
+static struct clk uart_clk = {
+        .name       = "UARTCLK",
+        .parent     = &slow_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_UART_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_UART_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk keypad_clk = {
+        .name       = "KEYPAD",
+        .parent     = &slow_clk,
+        .rate       = 32768,
+        .hw_ctrld   = false,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_KEYPAD_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk gpio_clk = {
+        .name       = "GPIO",
+        .parent     = &slow_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_GPIO_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_GPIO_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk rtc_clk = {
+        .name       = "RTC",
+        .parent     = &slow_clk,
+        .rate       = 32768,
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_RTC_RESET_EN,
+        /* This clock is always on, cannot be enabled/disabled */
+};
+static struct clk bustr_clk = {
+        .name       = "BUSTR",
+        .parent     = &slow_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_BTR_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_BTR_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk evhist_clk = {
+        .name       = "EVHIST",
+        .parent     = &slow_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_EH_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_EH_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk timer_clk = {
+        .name       = "TIMER",
+        .parent     = &slow_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+static struct clk app_timer_clk = {
+        .name       = "TIMER_APP",
+        .parent     = &slow_clk,
+        .rate       = 13000000,
+        .hw_ctrld   = true,
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_APP_TMR_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+#ifdef CONFIG_MACH_U300_BS335
+static struct clk ppm_clk = {
+        .name       = "PPM",
+        .parent     = &slow_clk,
+        .rate       = 0, /* FIXME */
+        .hw_ctrld   = true, /* TODO: Look up if it is hw ctrld or not */
+        .reset      = true,
+        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
+        .res_mask   = U300_SYSCON_RSR_PPM_RESET_EN,
+        .clk_val    = U300_SYSCON_SBCER_PPM_CLK_EN,
+        .enable     = syscon_clk_enable,
+        .disable    = syscon_clk_disable,
+};
+#endif
+#define DEF_LOOKUP(devid, clkref)               \
+        {                                       \
+        .dev_id = devid,                        \
+        .clk = clkref,                          \
+        }
+/*
+ * Here we only define clocks that are meaningful to
+ * look up through clockdevice.
+ */
+static struct clk_lookup lookups[] = {
+        /* Connected directly to the AMBA bus */
+        DEF_LOOKUP("amba", &amba_clk),
+        DEF_LOOKUP("cpu", &cpu_clk),
+        DEF_LOOKUP("nandif", &nandif_clk),
+        DEF_LOOKUP("semi", &semi_clk),
+#ifdef CONFIG_MACH_U300_BS335
+        DEF_LOOKUP("isp", &isp_clk),
+        DEF_LOOKUP("cds", &cds_clk),
+#endif
+        DEF_LOOKUP("dma", &dma_clk),
+        DEF_LOOKUP("aaif", &aaif_clk),
+        DEF_LOOKUP("apex", &apex_clk),
+        DEF_LOOKUP("video_enc", &video_enc_clk),
+        DEF_LOOKUP("xgam", &xgam_clk),
+        DEF_LOOKUP("ahb", &ahb_clk),
+        /* AHB bridge clocks */
+        DEF_LOOKUP("ahb", &ahb_subsys_clk),
+        DEF_LOOKUP("intcon", &intcon_clk),
+        DEF_LOOKUP("mspro", &mspro_clk),
+        DEF_LOOKUP("pl172", &emif_clk),
+        /* FAST bridge clocks */
+        DEF_LOOKUP("fast", &fast_clk),
+        DEF_LOOKUP("mmci", &mmcsd_clk),
+        /*
+         * The .0 and .1 identifiers on these comes from the platform device
+         * .id field and are assigned when the platform devices are registered.
+         */
+        DEF_LOOKUP("i2s.0", &i2s0_clk),
+        DEF_LOOKUP("i2s.1", &i2s1_clk),
+        DEF_LOOKUP("stddci2c.0", &i2c0_clk),
+        DEF_LOOKUP("stddci2c.1", &i2c1_clk),
+        DEF_LOOKUP("pl022", &spi_clk),
+#ifdef CONFIG_MACH_U300_BS335
+        DEF_LOOKUP("uart1", &uart1_clk),
+#endif
+        /* SLOW bridge clocks */
+        DEF_LOOKUP("slow", &slow_clk),
+        DEF_LOOKUP("wdog", &wdog_clk),
+        DEF_LOOKUP("uart0", &uart_clk),
+        DEF_LOOKUP("apptimer", &app_timer_clk),
+        DEF_LOOKUP("keypad", &keypad_clk),
+        DEF_LOOKUP("u300-gpio", &gpio_clk),
+        DEF_LOOKUP("rtc0", &rtc_clk),
+        DEF_LOOKUP("bustr", &bustr_clk),
+        DEF_LOOKUP("evhist", &evhist_clk),
+        DEF_LOOKUP("timer", &timer_clk),
+#ifdef CONFIG_MACH_U300_BS335
+        DEF_LOOKUP("ppm", &ppm_clk),
+#endif
+};
+static void __init clk_register(void)
+{
+        int i;
+        /* Register the lookups */
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+}
+/*
+ * These are the clocks for cells registered as primecell drivers
+ * on the AMBA bus. These must be on during AMBA device registration
+ * since the bus probe will attempt to read magic configuration
+ * registers for these devices. If they are deactivated these probes
+ * will fail.
+ *
+ *
+ * Please note that on emif, both RAM and NAND is connected in dual
+ * RAM phones. On single RAM phones, ram is on semi and NAND on emif.
+ *
+ */
+void u300_clock_primecells(void)
+{
+        clk_enable(&intcon_clk);
+        clk_enable(&uart_clk);
+#ifdef CONFIG_MACH_U300_BS335
+        clk_enable(&uart1_clk);
+#endif
+        clk_enable(&spi_clk);
+        clk_enable(&mmcsd_clk);
+}
+EXPORT_SYMBOL(u300_clock_primecells);
+void u300_unclock_primecells(void)
+{
+        clk_disable(&intcon_clk);
+        clk_disable(&uart_clk);
+#ifdef CONFIG_MACH_U300_BS335
+        clk_disable(&uart1_clk);
+#endif
+        clk_disable(&spi_clk);
+        clk_disable(&mmcsd_clk);
+}
+EXPORT_SYMBOL(u300_unclock_primecells);
+/*
+ * The interrupt controller is enabled before the clock API is registered.
+ */
+void u300_enable_intcon_clock(void)
+{
+        clk_enable(&intcon_clk);
+}
+EXPORT_SYMBOL(u300_enable_intcon_clock);
+/*
+ * The timer is enabled before the clock API is registered.
+ */
+void u300_enable_timer_clock(void)
+{
+        clk_enable(&app_timer_clk);
+}
+EXPORT_SYMBOL(u300_enable_timer_clock);
+#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
+/*
+ * The following makes it possible to view the status (especially
+ * reference count and reset status) for the clocks in the platform
+ * by looking into the special file <debugfs>/u300_clocks
+ */
+/* A list of all clocks in the platform */
+static struct clk *clks[] = {
+        /* Top node clock for the AMBA bus */
+        &amba_clk,
+        /* Connected directly to the AMBA bus */
+        &cpu_clk,
+        &nandif_clk,
+        &semi_clk,
+#ifdef CONFIG_MACH_U300_BS335
+        &isp_clk,
+        &cds_clk,
+#endif
+        &dma_clk,
+        &aaif_clk,
+        &apex_clk,
+        &video_enc_clk,
+        &xgam_clk,
+        &ahb_clk,
+        /* AHB bridge clocks */
+        &ahb_subsys_clk,
+        &intcon_clk,
+        &mspro_clk,
+        &emif_clk,
+        /* FAST bridge clocks */
+        &fast_clk,
+        &mmcsd_clk,
+        &i2s0_clk,
+        &i2s1_clk,
+        &i2c0_clk,
+        &i2c1_clk,
+        &spi_clk,
+#ifdef CONFIG_MACH_U300_BS335
+        &uart1_clk,
+#endif
+        /* SLOW bridge clocks */
+        &slow_clk,
+        &wdog_clk,
+        &uart_clk,
+        &app_timer_clk,
+        &keypad_clk,
+        &gpio_clk,
+        &rtc_clk,
+        &bustr_clk,
+        &evhist_clk,
+        &timer_clk,
+#ifdef CONFIG_MACH_U300_BS335
+        &ppm_clk,
+#endif
+};
+static int u300_clocks_show(struct seq_file *s, void *data)
+{
+        struct clk *clk;
+        int i;
+        seq_printf(s, "CLOCK           DEVICE          RESET STATE\t" \
+                   "ACTIVE\tUSERS\tHW CTRL FREQ\n");
+        seq_printf(s, "---------------------------------------------" \
+                   "-----------------------------------------\n");
+        for (i = 0; i < ARRAY_SIZE(clks); i++) {
+                clk = clks[i];
+                if (clk != ERR_PTR(-ENOENT)) {
+                        /* Format clock and device name nicely */
+                        char cdp[33];
+                        int chars;
+                        chars = snprintf(&cdp[0], 17, "%s", clk->name);
+                        while (chars < 16) {
+                                cdp[chars] = ' ';
+                                chars++;
+                        }
+                        chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
+                                         dev_name(clk->dev) : "N/A");
+                        while (chars < 16) {
+                                cdp[chars+16] = ' ';
+                                chars++;
+                        }
+                        cdp[32] = '\0';
+                        if (clk->get_rate)
+                                seq_printf(s,
+                                           "%s%s\t%s\t%d\t%s\t%lu Hz\n",
+                                           &cdp[0],
+                                           clk->reset ?
+                                           "ASSERTED" : "RELEASED",
+                                           clk->usecount ? "ON" : "OFF",
+                                           clk->usecount,
+                                           clk->hw_ctrld  ? "YES" : "NO ",
+                                           clk->get_rate(clk));
+                        else
+                                seq_printf(s,
+                                           "%s%s\t%s\t%d\t%s\t" \
+                                           "(unknown rate)\n",
+                                           &cdp[0],
+                                           clk->reset ?
+                                           "ASSERTED" : "RELEASED",
+                                           clk->usecount ? "ON" : "OFF",
+                                           clk->usecount,
+                                           clk->hw_ctrld  ? "YES" : "NO ");
+                }
+        }
+        return 0;
+}
+static int u300_clocks_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, u300_clocks_show, NULL);
+}
+static const struct file_operations u300_clocks_operations = {
+        .open           = u300_clocks_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+static void init_clk_read_procfs(void)
+{
+        /* Expose a simple debugfs interface to view all clocks */
+        (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
+                                   NULL, NULL, &u300_clocks_operations);
+}
+#else
+static inline void init_clk_read_procfs(void)
+{
+}
+#endif
+static int __init u300_clock_init(void)
+{
+        u16 val;
+        /*
+         * FIXME: shall all this powermanagement stuff really live here???
+         */
+        /* Set system to run at PLL208, max performance, a known state. */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        /* Wait for the PLL208 to lock if not locked in yet */
+        while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
+                 U300_SYSCON_CSR_PLL208_LOCK_IND));
+        /* Power management enable */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+        val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+        clk_register();
+        init_clk_read_procfs();
+        /*
+         * Some of these may be on when we boot the system so make sure they
+         * are turned OFF.
+         */
+        syscon_block_reset_enable(&timer_clk);
+        timer_clk.disable(&timer_clk);
+        /*
+         * These shall be turned on by default when we boot the system
+         * so make sure they are ON. (Adding CPU here is a bit too much.)
+         * These clocks will be claimed by drivers later.
+         */
+        syscon_block_reset_disable(&semi_clk);
+        syscon_block_reset_disable(&emif_clk);
+        semi_clk.enable(&semi_clk);
+        emif_clk.enable(&emif_clk);
+        return 0;
+}
+/* initialize clocking early to be available later in the boot */
+core_initcall(u300_clock_init);
diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h
new file mode 100644
index 000000000000..fc6d9ccfe7e3
--- /dev/null
+++ b/arch/arm/mach-u300/clock.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-u300/include/mach/clock.h
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * Adopted to ST-Ericsson U300 platforms by
+ * Jonas Aaberg <jonas.aberg@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __MACH_CLOCK_H
+#define __MACH_CLOCK_H
+#include <linux/clk.h>
+struct clk {
+        struct list_head node;
+        struct module *owner;
+        struct device *dev;
+        const char *name;
+        struct clk *parent;
+        spinlock_t lock;
+        unsigned long rate;
+        bool reset;
+        __u16 clk_val;
+        __s8 usecount;
+        __u32 res_reg;
+        __u16 res_mask;
+        bool hw_ctrld;
+        void (*recalc) (struct clk *);
+        int (*set_rate) (struct clk *, unsigned long);
+        unsigned long (*get_rate) (struct clk *);
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        void (*init) (struct clk *);
+        void (*enable) (struct clk *);
+        void (*disable) (struct clk *);
+};
+void u300_clock_primecells(void);
+void u300_unclock_primecells(void);
+void u300_enable_intcon_clock(void);
+void u300_enable_timer_clock(void);
+#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
new file mode 100644
index 000000000000..89b3ccf35e1b
--- /dev/null
+++ b/arch/arm/mach-u300/core.c
@@ -0,0 +1,649 @@
+/*
+ *
+ * arch/arm/mach-u300/core.c
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Core platform support, IRQ handling and device definitions.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/termios.h>
+#include <linux/amba/bus.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/syscon.h>
+#include "clock.h"
+#include "mmc.h"
+/*
+ * Static I/O mappings that are needed for booting the U300 platforms. The
+ * only things we need are the areas where we find the timer, syscon and
+ * intcon, since the remaining device drivers will map their own memory
+ * physical to virtual as the need arise.
+ */
+static struct map_desc u300_io_desc[] __initdata = {
+        {
+                .virtual        = U300_SLOW_PER_VIRT_BASE,
+                .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = U300_AHB_PER_VIRT_BASE,
+                .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
+                .length         = SZ_32K,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = U300_FAST_PER_VIRT_BASE,
+                .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
+                .length         = SZ_32K,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = 0xffff2000, /* TCM memory */
+                .pfn            = __phys_to_pfn(0xffff2000),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        },
+        /*
+         * This overlaps with the IRQ vectors etc at 0xffff0000, so these
+         * may have to be moved to 0x00000000 in order to use the ROM.
+         */
+        /*
+        {
+                .virtual        = U300_BOOTROM_VIRT_BASE,
+                .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
+                .length         = SZ_64K,
+                .type           = MT_ROM,
+        },
+        */
+};
+void __init u300_map_io(void)
+{
+        iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
+}
+/*
+ * Declaration of devices found on the U300 board and
+ * their respective memory locations.
+ */
+static struct amba_device uart0_device = {
+        .dev = {
+                .init_name = "uart0", /* Slow device at 0x3000 offset */
+                .platform_data = NULL,
+        },
+        .res = {
+                .start = U300_UART0_BASE,
+                .end   = U300_UART0_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = { IRQ_U300_UART0, NO_IRQ },
+};
+/* The U335 have an additional UART1 on the APP CPU */
+#ifdef CONFIG_MACH_U300_BS335
+static struct amba_device uart1_device = {
+        .dev = {
+                .init_name = "uart1", /* Fast device at 0x7000 offset */
+                .platform_data = NULL,
+        },
+        .res = {
+                .start = U300_UART1_BASE,
+                .end   = U300_UART1_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = { IRQ_U300_UART1, NO_IRQ },
+};
+#endif
+static struct amba_device pl172_device = {
+        .dev = {
+                .init_name = "pl172", /* AHB device at 0x4000 offset */
+                .platform_data = NULL,
+        },
+        .res = {
+                .start = U300_EMIF_CFG_BASE,
+                .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+/*
+ * Everything within this next ifdef deals with external devices connected to
+ * the APP SPI bus.
+ */
+static struct amba_device pl022_device = {
+        .dev = {
+                .coherent_dma_mask = ~0,
+                .init_name = "pl022", /* Fast device at 0x6000 offset */
+        },
+        .res = {
+                .start = U300_SPI_BASE,
+                .end   = U300_SPI_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_U300_SPI, NO_IRQ },
+        /*
+         * This device has a DMA channel but the Linux driver does not use
+         * it currently.
+         */
+};
+static struct amba_device mmcsd_device = {
+        .dev = {
+                .init_name = "mmci", /* Fast device at 0x1000 offset */
+                .platform_data = NULL, /* Added later */
+        },
+        .res = {
+                .start = U300_MMCSD_BASE,
+                .end   = U300_MMCSD_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
+        /*
+         * This device has a DMA channel but the Linux driver does not use
+         * it currently.
+         */
+};
+/*
+ * The order of device declaration may be important, since some devices
+ * have dependencies on other devices being initialized first.
+ */
+static struct amba_device *amba_devs[] __initdata = {
+        &uart0_device,
+#ifdef CONFIG_MACH_U300_BS335
+        &uart1_device,
+#endif
+        &pl022_device,
+        &pl172_device,
+        &mmcsd_device,
+};
+/* Here follows a list of all hw resources that the platform devices
+ * allocate. Note, clock dependencies are not included
+ */
+static struct resource gpio_resources[] = {
+        {
+                .start = U300_GPIO_BASE,
+                .end   = (U300_GPIO_BASE + SZ_4K - 1),
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "gpio0",
+                .start = IRQ_U300_GPIO_PORT0,
+                .end   = IRQ_U300_GPIO_PORT0,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "gpio1",
+                .start = IRQ_U300_GPIO_PORT1,
+                .end   = IRQ_U300_GPIO_PORT1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "gpio2",
+                .start = IRQ_U300_GPIO_PORT2,
+                .end   = IRQ_U300_GPIO_PORT2,
+                .flags = IORESOURCE_IRQ,
+        },
+#ifdef U300_COH901571_3
+        {
+                .name  = "gpio3",
+                .start = IRQ_U300_GPIO_PORT3,
+                .end   = IRQ_U300_GPIO_PORT3,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "gpio4",
+                .start = IRQ_U300_GPIO_PORT4,
+                .end   = IRQ_U300_GPIO_PORT4,
+                .flags = IORESOURCE_IRQ,
+        },
+#ifdef CONFIG_MACH_U300_BS335
+        {
+                .name  = "gpio5",
+                .start = IRQ_U300_GPIO_PORT5,
+                .end   = IRQ_U300_GPIO_PORT5,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "gpio6",
+                .start = IRQ_U300_GPIO_PORT6,
+                .end   = IRQ_U300_GPIO_PORT6,
+                .flags = IORESOURCE_IRQ,
+        },
+#endif /* CONFIG_MACH_U300_BS335 */
+#endif /* U300_COH901571_3 */
+};
+static struct resource keypad_resources[] = {
+        {
+                .start = U300_KEYPAD_BASE,
+                .end   = U300_KEYPAD_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "coh901461-press",
+                .start = IRQ_U300_KEYPAD_KEYBF,
+                .end   = IRQ_U300_KEYPAD_KEYBF,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "coh901461-release",
+                .start = IRQ_U300_KEYPAD_KEYBR,
+                .end   = IRQ_U300_KEYPAD_KEYBR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct resource rtc_resources[] = {
+        {
+                .start = U300_RTC_BASE,
+                .end   = U300_RTC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_U300_RTC,
+                .end   = IRQ_U300_RTC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+/*
+ * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
+ * but these are not yet used by the driver.
+ */
+static struct resource fsmc_resources[] = {
+        {
+                .start = U300_NAND_IF_PHYS_BASE,
+                .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+static struct resource i2c0_resources[] = {
+        {
+                .start = U300_I2C0_BASE,
+                .end   = U300_I2C0_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_U300_I2C0,
+                .end   = IRQ_U300_I2C0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct resource i2c1_resources[] = {
+        {
+                .start = U300_I2C1_BASE,
+                .end   = U300_I2C1_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_U300_I2C1,
+                .end   = IRQ_U300_I2C1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct resource wdog_resources[] = {
+        {
+                .start = U300_WDOG_BASE,
+                .end   = U300_WDOG_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_U300_WDOG,
+                .end   = IRQ_U300_WDOG,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+/* TODO: These should be protected by suitable #ifdef's */
+static struct resource ave_resources[] = {
+        {
+                .name  = "AVE3e I/O Area",
+                .start = U300_VIDEOENC_BASE,
+                .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "AVE3e IRQ0",
+                .start = IRQ_U300_VIDEO_ENC_0,
+                .end   = IRQ_U300_VIDEO_ENC_0,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "AVE3e IRQ1",
+                .start = IRQ_U300_VIDEO_ENC_1,
+                .end   = IRQ_U300_VIDEO_ENC_1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name  = "AVE3e Physmem Area",
+                .start = 0, /* 0 will be remapped to reserved memory */
+                .end   = SZ_1M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        /*
+         * The AVE3e requires two regions of 256MB that it considers
+         * "invisible". The hardware will not be able to access these
+         * adresses, so they should never point to system RAM.
+         */
+        {
+                .name  = "AVE3e Reserved 0",
+                .start = 0xd0000000,
+                .end   = 0xd0000000 + SZ_256M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "AVE3e Reserved 1",
+                .start = 0xe0000000,
+                .end   = 0xe0000000 + SZ_256M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+static struct platform_device wdog_device = {
+        .name = "wdog",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(wdog_resources),
+        .resource = wdog_resources,
+};
+static struct platform_device i2c0_device = {
+        .name = "stddci2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(i2c0_resources),
+        .resource = i2c0_resources,
+};
+static struct platform_device i2c1_device = {
+        .name = "stddci2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(i2c1_resources),
+        .resource = i2c1_resources,
+};
+static struct platform_device gpio_device = {
+        .name = "u300-gpio",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(gpio_resources),
+        .resource = gpio_resources,
+};
+static struct platform_device keypad_device = {
+        .name = "keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(keypad_resources),
+        .resource = keypad_resources,
+};
+static struct platform_device rtc_device = {
+        .name = "rtc0",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(rtc_resources),
+        .resource = rtc_resources,
+};
+static struct platform_device fsmc_device = {
+        .name = "nandif",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(fsmc_resources),
+        .resource = fsmc_resources,
+};
+static struct platform_device ave_device = {
+        .name = "video_enc",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(ave_resources),
+        .resource = ave_resources,
+};
+/*
+ * Notice that AMBA devices are initialized before platform devices.
+ *
+ */
+static struct platform_device *platform_devs[] __initdata = {
+        &i2c0_device,
+        &i2c1_device,
+        &keypad_device,
+        &rtc_device,
+        &gpio_device,
+        &fsmc_device,
+        &wdog_device,
+        &ave_device
+};
+/*
+ * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
+ * together so some interrupts are connected to the first one and some
+ * to the second one.
+ */
+void __init u300_init_irq(void)
+{
+        u32 mask[2] = {0, 0};
+        int i;
+        for (i = 0; i < NR_IRQS; i++)
+                set_bit(i, (unsigned long *) &mask[0]);
+        u300_enable_intcon_clock();
+        vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], 0);
+        vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], 0);
+}
+/*
+ * U300 platforms peripheral handling
+ */
+struct db_chip {
+        u16 chipid;
+        const char *name;
+};
+/*
+ * This is a list of the Digital Baseband chips used in the U300 platform.
+ */
+static struct db_chip db_chips[] __initdata = {
+        {
+                .chipid = 0xb800,
+                .name = "DB3000",
+        },
+        {
+                .chipid = 0xc000,
+                .name = "DB3100",
+        },
+        {
+                .chipid = 0xc800,
+                .name = "DB3150",
+        },
+        {
+                .chipid = 0xd800,
+                .name = "DB3200",
+        },
+        {
+                .chipid = 0xe000,
+                .name = "DB3250",
+        },
+        {
+                .chipid = 0xe800,
+                .name = "DB3210",
+        },
+        {
+                .chipid = 0xf000,
+                .name = "DB3350 P1x",
+        },
+        {
+                .chipid = 0xf100,
+                .name = "DB3350 P2x",
+        },
+        {
+                .chipid = 0x0000, /* List terminator */
+                .name = NULL,
+        }
+};
+static void u300_init_check_chip(void)
+{
+        u16 val;
+        struct db_chip *chip;
+        const char *chipname;
+        const char unknown[] = "UNKNOWN";
+        /* Read out and print chip ID */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+        /* This is in funky bigendian order... */
+        val = (val & 0xFFU) << 8 | (val >> 8);
+        chip = db_chips;
+        chipname = unknown;
+        for ( ; chip->chipid; chip++) {
+                if (chip->chipid == (val & 0xFF00U)) {
+                        chipname = chip->name;
+                        break;
+                }
+        }
+        printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
+               "(chip ID 0x%04x)\n", chipname, val);
+#ifdef CONFIG_MACH_U300_BS26
+        if ((val & 0xFF00U) != 0xc800) {
+                printk(KERN_ERR "Platform configured for BS25/BS26 " \
+                       "with DB3150 but %s detected, expect problems!",
+                       chipname);
+        }
+#endif
+#ifdef CONFIG_MACH_U300_BS330
+        if ((val & 0xFF00U) != 0xd800) {
+                printk(KERN_ERR "Platform configured for BS330 " \
+                       "with DB3200 but %s detected, expect problems!",
+                       chipname);
+        }
+#endif
+#ifdef CONFIG_MACH_U300_BS335
+        if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
+                printk(KERN_ERR "Platform configured for BS365 " \
+                       " with DB3350 but %s detected, expect problems!",
+                       chipname);
+        }
+#endif
+#ifdef CONFIG_MACH_U300_BS365
+        if ((val & 0xFF00U) != 0xe800) {
+                printk(KERN_ERR "Platform configured for BS365 " \
+                       "with DB3210 but %s detected, expect problems!",
+                       chipname);
+        }
+#endif
+}
+/*
+ * Some devices and their resources require reserved physical memory from
+ * the end of the available RAM. This function traverses the list of devices
+ * and assigns actual adresses to these.
+ */
+static void __init u300_assign_physmem(void)
+{
+        unsigned long curr_start = __pa(high_memory);
+        int i, j;
+        for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
+                for (j = 0; j < platform_devs[i]->num_resources; j++) {
+                        struct resource *const res =
+                          &platform_devs[i]->resource[j];
+                        if (IORESOURCE_MEM == res->flags &&
+                                     0 == res->start) {
+                                res->start  = curr_start;
+                                res->end   += curr_start;
+                                curr_start += (res->end - res->start + 1);
+                                printk(KERN_INFO "core.c: Mapping RAM " \
+                                       "%#x-%#x to device %s:%s\n",
+                                        res->start, res->end,
+                                       platform_devs[i]->name, res->name);
+                        }
+                }
+        }
+}
+void __init u300_init_devices(void)
+{
+        int i;
+        u16 val;
+        /* Check what platform we run and print some status information */
+        u300_init_check_chip();
+        /* Set system to run at PLL208, max performance, a known state. */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
+        /* Wait for the PLL208 to lock if not locked in yet */
+        while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
+                 U300_SYSCON_CSR_PLL208_LOCK_IND));
+        /* Register the AMBA devices in the AMBA bus abstraction layer */
+        u300_clock_primecells();
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+        u300_unclock_primecells();
+        u300_assign_physmem();
+        /* Register the platform devices */
+        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
+        /*
+         * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
+         * both subsystems are requesting this mode.
+         * If we not share the Acc SDRAM, this is never the case. Therefore
+         * enable it here from the App side.
+         */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
+                U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
+#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
+}
+static int core_module_init(void)
+{
+        /*
+         * This needs to be initialized later: it needs the input framework
+         * to be initialized first.
+         */
+        return mmc_init(&mmcsd_device);
+}
+module_init(core_module_init);
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
new file mode 100644
index 000000000000..308cdb197a92
--- /dev/null
+++ b/arch/arm/mach-u300/gpio.c
@@ -0,0 +1,703 @@
+/*
+ *
+ * arch/arm/mach-u300/gpio.c
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * U300 GPIO module.
+ * This can driver either of the two basic GPIO cores
+ * available in the U300 platforms:
+ * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
+ * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
+ * Notice that you also have inline macros in <asm-arch/gpio.h>
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ *
+ */
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+/* Need access to SYSCON registers for PADmuxing */
+#include <mach/syscon.h>
+#include "padmux.h"
+/* Reference to GPIO block clock */
+static struct clk *clk;
+/* Memory resource */
+static struct resource *memres;
+static void __iomem *virtbase;
+static struct device *gpiodev;
+struct u300_gpio_port {
+        const char *name;
+        int irq;
+        int number;
+};
+static struct u300_gpio_port gpio_ports[] = {
+        {
+                .name = "gpio0",
+                .number = 0,
+        },
+        {
+                .name = "gpio1",
+                .number = 1,
+        },
+        {
+                .name = "gpio2",
+                .number = 2,
+        },
+#ifdef U300_COH901571_3
+        {
+                .name = "gpio3",
+                .number = 3,
+        },
+        {
+                .name = "gpio4",
+                .number = 4,
+        },
+#ifdef CONFIG_MACH_U300_BS335
+        {
+                .name = "gpio5",
+                .number = 5,
+        },
+        {
+                .name = "gpio6",
+                .number = 6,
+        },
+#endif
+#endif
+};
+#ifdef U300_COH901571_3
+/* Default input value */
+#define DEFAULT_OUTPUT_LOW   0
+#define DEFAULT_OUTPUT_HIGH  1
+/* GPIO Pull-Up status */
+#define DISABLE_PULL_UP  0
+#define ENABLE_PULL_UP  1
+#define GPIO_NOT_USED 0
+#define GPIO_IN       1
+#define GPIO_OUT      2
+struct u300_gpio_configuration_data {
+        unsigned char pin_usage;
+        unsigned char default_output_value;
+        unsigned char pull_up;
+};
+/* Initial configuration */
+const struct u300_gpio_configuration_data
+u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
+#ifdef CONFIG_MACH_U300_BS335
+        /* Port 0, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_HIGH,  DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        },
+        /* Port 1, pins 0-7 */
+        {
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_HIGH,  DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        },
+        /* Port 2, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
+        },
+        /* Port 3, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        },
+        /* Port 4, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        },
+        /* Port 5, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        },
+        /* Port 6, pind 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        }
+#endif
+#ifdef CONFIG_MACH_U300_BS365
+        /* Port 0, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        },
+        /* Port 1, pins 0-7 */
+        {
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_HIGH,  DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
+        },
+        /* Port 2, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
+        },
+        /* Port 3, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
+        },
+        /* Port 4, pins 0-7 */
+        {
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                /* These 4 pins doesn't exist on DB3210 */
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
+                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
+        }
+#endif
+};
+#endif
+/* No users == we can power down GPIO */
+static int gpio_users;
+struct gpio_struct {
+        int (*callback)(void *);
+        void *data;
+        int users;
+};
+static struct gpio_struct gpio_pin[U300_GPIO_MAX];
+/*
+ * Let drivers register callback in order to get notified when there is
+ * an interrupt on the gpio pin
+ */
+int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
+{
+        if (gpio_pin[gpio].callback)
+                dev_warn(gpiodev, "%s: WARNING: callback already "
+                         "registered for gpio pin#%d\n", __func__, gpio);
+        gpio_pin[gpio].callback = func;
+        gpio_pin[gpio].data = data;
+        return 0;
+}
+EXPORT_SYMBOL(gpio_register_callback);
+int gpio_unregister_callback(unsigned gpio)
+{
+        if (!gpio_pin[gpio].callback)
+                dev_warn(gpiodev, "%s: WARNING: callback already "
+                         "unregistered for gpio pin#%d\n", __func__, gpio);
+        gpio_pin[gpio].callback = NULL;
+        gpio_pin[gpio].data = NULL;
+        return 0;
+}
+EXPORT_SYMBOL(gpio_unregister_callback);
+int gpio_request(unsigned gpio, const char *label)
+{
+        if (gpio_pin[gpio].users)
+                return -EINVAL;
+        else
+                gpio_pin[gpio].users++;
+        gpio_users++;
+        return 0;
+}
+EXPORT_SYMBOL(gpio_request);
+void gpio_free(unsigned gpio)
+{
+        gpio_users--;
+        gpio_pin[gpio].users--;
+        if (unlikely(gpio_pin[gpio].users < 0)) {
+                dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
+                         gpio);
+                gpio_pin[gpio].users = 0;
+        }
+        return;
+}
+EXPORT_SYMBOL(gpio_free);
+/* This returns zero or nonzero */
+int gpio_get_value(unsigned gpio)
+{
+        return readl(virtbase + U300_GPIO_PXPDIR +
+          PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
+}
+EXPORT_SYMBOL(gpio_get_value);
+/*
+ * We hope that the compiler will optimize away the unused branch
+ * in case "value" is a constant
+ */
+void gpio_set_value(unsigned gpio, int value)
+{
+        u32 val;
+        unsigned long flags;
+        local_irq_save(flags);
+        if (value) {
+                /* set */
+                val = readl(virtbase + U300_GPIO_PXPDOR +
+                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
+                  & (1 << (gpio & 0x07));
+                writel(val | (1 << (gpio & 0x07)), virtbase +
+                  U300_GPIO_PXPDOR +
+                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
+        } else {
+                /* clear */
+                val = readl(virtbase + U300_GPIO_PXPDOR +
+                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
+                  & (1 << (gpio & 0x07));
+                writel(val & ~(1 << (gpio & 0x07)), virtbase +
+                  U300_GPIO_PXPDOR +
+                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
+        }
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_set_value);
+int gpio_direction_input(unsigned gpio)
+{
+        unsigned long flags;
+        u32 val;
+        if (gpio > U300_GPIO_MAX)
+                return -EINVAL;
+        local_irq_save(flags);
+        val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        /* Mask out this pin*/
+        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
+        /* This is not needed since it sets the bits to zero.*/
+        /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
+        writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(gpio_direction_input);
+int gpio_direction_output(unsigned gpio, int value)
+{
+        unsigned long flags;
+        u32 val;
+        if (gpio > U300_GPIO_MAX)
+                return -EINVAL;
+        local_irq_save(flags);
+        val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        /* Mask out this pin */
+        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
+        /*
+         * FIXME: configure for push/pull, open drain or open source per pin
+         * in setup. The current driver will only support push/pull.
+         */
+        val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
+                        << ((gpio & 0x07) << 1));
+        writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        gpio_set_value(gpio, value);
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(gpio_direction_output);
+/*
+ * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
+ */
+void enable_irq_on_gpio_pin(unsigned gpio, int edge)
+{
+        u32 val;
+        unsigned long flags;
+        local_irq_save(flags);
+        val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        val |= (1 << (gpio & 0x07));
+        writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        if (edge)
+                val |= (1 << (gpio & 0x07));
+        else
+                val &= ~(1 << (gpio & 0x07));
+        writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(enable_irq_on_gpio_pin);
+void disable_irq_on_gpio_pin(unsigned gpio)
+{
+        u32 val;
+        unsigned long flags;
+        local_irq_save(flags);
+        val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        val &= ~(1 << (gpio & 0x07));
+        writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
+                                U300_GPIO_PORTX_SPACING);
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(disable_irq_on_gpio_pin);
+/* Enable (value == 0) or disable (value == 1) internal pullup */
+void gpio_pullup(unsigned gpio, int value)
+{
+        u32 val;
+        unsigned long flags;
+        local_irq_save(flags);
+        if (value) {
+                val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
+                                        U300_GPIO_PORTX_SPACING);
+                writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
+                                PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
+        } else {
+                val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
+                                        U300_GPIO_PORTX_SPACING);
+                writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
+                                PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
+        }
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_pullup);
+static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
+{
+        struct u300_gpio_port *port = dev_id;
+        u32 val;
+        int pin;
+        /* Read event register */
+        val = readl(virtbase + U300_GPIO_PXIEV + port->number *
+                                U300_GPIO_PORTX_SPACING);
+        /* Mask with enable register */
+        val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
+                                U300_GPIO_PORTX_SPACING);
+        /* Mask relevant bits */
+        val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
+        /* ACK IRQ (clear event) */
+        writel(val, virtbase + U300_GPIO_PXIEV + port->number *
+                                U300_GPIO_PORTX_SPACING);
+        /* Print message */
+        while (val != 0) {
+                unsigned gpio;
+                pin = __ffs(val);
+                /* mask off this pin */
+                val &= ~(1 << pin);
+                gpio = (port->number << 3) + pin;
+                if (gpio_pin[gpio].callback)
+                        (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
+                else
+                        dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n",
+                               gpio);
+        }
+        return IRQ_HANDLED;
+}
+static void gpio_set_initial_values(void)
+{
+#ifdef U300_COH901571_3
+        int i, j;
+        unsigned long flags;
+        u32 val;
+        /* Write default values to all pins */
+        for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
+                val = 0;
+                for (j = 0; j < 8; j++)
+                        val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
+                local_irq_save(flags);
+                writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
+                local_irq_restore(flags);
+        }
+        /*
+         * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
+         * to output and 'GPIO_IN' to input for each port. And initalize
+         * default value on outputs.
+         */
+        for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
+                for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
+                        local_irq_save(flags);
+                        val = readl(virtbase + U300_GPIO_PXPCR +
+                                         i * U300_GPIO_PORTX_SPACING);
+                        /* Mask out this pin */
+                        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
+                        if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
+                                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
+                        writel(val, virtbase + U300_GPIO_PXPCR +
+                                         i * U300_GPIO_PORTX_SPACING);
+                        local_irq_restore(flags);
+                }
+        }
+        /* Enable or disable the internal pull-ups in the GPIO ASIC block */
+        for (i = 0; i < U300_GPIO_MAX; i++) {
+                val = 0;
+                for (j = 0; j < 8; j++)
+                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j;
+                local_irq_save(flags);
+                writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
+                local_irq_restore(flags);
+        }
+#endif
+}
+static int __init gpio_probe(struct platform_device *pdev)
+{
+        u32 val;
+        int err = 0;
+        int i;
+        int num_irqs;
+        gpiodev = &pdev->dev;
+        memset(gpio_pin, 0, sizeof(gpio_pin));
+        /* Get GPIO clock */
+        clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(clk)) {
+                err = PTR_ERR(clk);
+                dev_err(gpiodev, "could not get GPIO clock\n");
+                goto err_no_clk;
+        }
+        err = clk_enable(clk);
+        if (err) {
+                dev_err(gpiodev, "could not enable GPIO clock\n");
+                goto err_no_clk_enable;
+        }
+        memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!memres)
+                goto err_no_resource;
+        if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
+            == NULL) {
+                err = -ENODEV;
+                goto err_no_ioregion;
+        }
+        virtbase = ioremap(memres->start, resource_size(memres));
+        if (!virtbase) {
+                err = -ENOMEM;
+                goto err_no_ioremap;
+        }
+        dev_info(gpiodev, "remapped 0x%08x to %p\n",
+                 memres->start, virtbase);
+#ifdef U300_COH901335
+        dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n");
+        /* Turn on the GPIO block */
+        writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
+#endif
+#ifdef U300_COH901571_3
+        dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n");
+        val = readl(virtbase + U300_GPIO_CR);
+        dev_info(gpiodev, "COH901571/3 block version: %d, " \
+               "number of cores: %d\n",
+               ((val & 0x0000FE00) >> 9),
+               ((val & 0x000001FC) >> 2));
+        writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
+#endif
+        /* Set up some padmuxing here */
+#ifdef CONFIG_MMC
+        pmx_set_mission_mode_mmc();
+#endif
+#ifdef CONFIG_SPI_PL022
+        pmx_set_mission_mode_spi();
+#endif
+        gpio_set_initial_values();
+        for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
+                gpio_ports[num_irqs].irq =
+                        platform_get_irq_byname(pdev,
+                                                gpio_ports[num_irqs].name);
+                err = request_irq(gpio_ports[num_irqs].irq,
+                                  gpio_irq_handler, IRQF_DISABLED,
+                                  gpio_ports[num_irqs].name,
+                                  &gpio_ports[num_irqs]);
+                if (err) {
+                        dev_err(gpiodev, "cannot allocate IRQ for %s!\n",
+                                gpio_ports[num_irqs].name);
+                        goto err_no_irq;
+                }
+                /* Turns off PortX_irq_force */
+                writel(0x0, virtbase + U300_GPIO_PXIFR +
+                                 num_irqs * U300_GPIO_PORTX_SPACING);
+        }
+        return 0;
+ err_no_irq:
+        for (i = 0; i < num_irqs; i++)
+                free_irq(gpio_ports[i].irq, &gpio_ports[i]);
+        iounmap(virtbase);
+ err_no_ioremap:
+        release_mem_region(memres->start, memres->end - memres->start);
+ err_no_ioregion:
+ err_no_resource:
+        clk_disable(clk);
+ err_no_clk_enable:
+        clk_put(clk);
+ err_no_clk:
+        dev_info(gpiodev, "module ERROR:%d\n", err);
+        return err;
+}
+static int __exit gpio_remove(struct platform_device *pdev)
+{
+        int i;
+        /* Turn off the GPIO block */
+        writel(0x00000000U, virtbase + U300_GPIO_CR);
+        for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
+                free_irq(gpio_ports[i].irq, &gpio_ports[i]);
+        iounmap(virtbase);
+        release_mem_region(memres->start, memres->end - memres->start);
+        clk_disable(clk);
+        clk_put(clk);
+        return 0;
+}
+static struct platform_driver gpio_driver = {
+        .driver         = {
+                .name   = "u300-gpio",
+        },
+        .remove         = __exit_p(gpio_remove),
+};
+static int __init u300_gpio_init(void)
+{
+        return platform_driver_probe(&gpio_driver, gpio_probe);
+}
+static void __exit u300_gpio_exit(void)
+{
+        platform_driver_unregister(&gpio_driver);
+}
+arch_initcall(u300_gpio_init);
+module_exit(u300_gpio_exit);
+MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
+#ifdef U300_COH901571_3
+MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
+#endif
+#ifdef U300_COH901335
+MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
+#endif
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
new file mode 100644
index 000000000000..92e3cc872c66
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+int __clk_get(struct clk *clk);
+void __clk_put(struct clk *clk);
+#endif
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
new file mode 100644
index 000000000000..f3a1cbbeeab3
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ *
+ * arch-arm/mach-u300/include/mach/debug-macro.S
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Debugging macro include header.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <mach/hardware.h>
+        .macro  addruart,rx
+        /* If we move the adress using MMU, use this. */
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @ MMU enabled?
+        ldreq   \rx,      = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
+        ldrne   \rx,      = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
+        orr     \rx, \rx, #0x00003000
+        .endm
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
new file mode 100644
index 000000000000..20731ae39d38
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/entry-macro.S
@@ -0,0 +1,40 @@
+/*
+ *
+ * arch-arm/mach-u300/include/mach/entry-macro.S
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Low-level IRQ helper macros for ST-Ericsson U300
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/vic.h>
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON0_BASE
+        ldr     \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
+        mov     \irqnr, #0
+        teq     \irqstat, #0
+        bne     1002f
+1001:   ldr     \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON1_BASE
+        ldr     \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
+        mov     \irqnr, #32
+        teq     \irqstat, #0
+        beq     1003f
+1002:   tst     \irqstat, #1
+        bne     1003f
+        add     \irqnr, \irqnr, #1
+        movs    \irqstat, \irqstat, lsr #1
+        bne     1002b
+1003:           /* EQ will be set if no irqs pending */
+        .endm
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
new file mode 100644
index 000000000000..c8174128d7eb
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -0,0 +1,290 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/gpio.h
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * GPIO block resgister definitions and inline macros for
+ * U300 GPIO COH 901 335 or COH 901 571/3
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#ifndef __MACH_U300_GPIO_H
+#define __MACH_U300_GPIO_H
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+/* Switch type depending on platform/chip variant */
+#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
+#define U300_COH901335
+#endif
+#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
+#define U300_COH901571_3
+#endif
+/* Get base address for regs here */
+#include "u300-regs.h"
+/* IRQ numbers */
+#include "irqs.h"
+/*
+ * This is the GPIO block definitions. GPIO (General Purpose I/O) can be
+ * used for anything, and often is. The event/enable etc figures are for
+ * the lowermost pin (pin 0 on each port), shift this left to match your
+ * pin if you're gonna use these values.
+ */
+#ifdef U300_COH901335
+#define U300_GPIO_PORTX_SPACING                         (0x1C)
+/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
+#define U300_GPIO_PXPDIR                                (0x00)
+#define U300_GPIO_PXPDOR                                (0x00)
+/* Port X Pin Config Register 32bit (R/W) */
+#define U300_GPIO_PXPCR                                 (0x04)
+#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
+#define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
+#define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
+#define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
+#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
+#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
+#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
+/* Port X Interrupt Event Register 32bit (R/W) */
+#define U300_GPIO_PXIEV                                 (0x08)
+#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK              (0x000000FFUL)
+#define U300_GPIO_PXIEV_IRQ_EVENT                       (0x00000001UL)
+/* Port X Interrupt Enable Register 32bit (R/W) */
+#define U300_GPIO_PXIEN                                 (0x0C)
+#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK             (0x000000FFUL)
+#define U300_GPIO_PXIEN_IRQ_ENABLE                      (0x00000001UL)
+/* Port X Interrupt Force Register 32bit (R/W) */
+#define U300_GPIO_PXIFR                                 (0x10)
+#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK              (0x000000FFUL)
+#define U300_GPIO_PXIFR_IRQ_FORCE                       (0x00000001UL)
+/* Port X Interrupt Config Register 32bit (R/W) */
+#define U300_GPIO_PXICR                                 (0x14)
+#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
+#define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
+#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
+#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
+/* Port X Pull-up Enable Register 32bit (R/W) */
+#define U300_GPIO_PXPER                                 (0x18)
+#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
+#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
+/* Control Register 32bit (R/W) */
+#define U300_GPIO_CR                                    (0x54)
+#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE                 (0x00000001UL)
+/* three ports of 8 bits each = GPIO pins 0..23 */
+#define U300_GPIO_NUM_PORTS 3
+#define U300_GPIO_PINS_PER_PORT 8
+#define U300_GPIO_MAX   (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
+#endif
+#ifdef U300_COH901571_3
+/*
+ * Control Register 32bit (R/W)
+ * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
+ * gives the number of GPIO pins.
+ * bit 8-2  (mask 0x000001FC) contains the core version ID.
+ */
+#define U300_GPIO_CR                                    (0x00)
+#define U300_GPIO_CR_SYNC_SEL_ENABLE                    (0x00000002UL)
+#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE                 (0x00000001UL)
+#define U300_GPIO_PORTX_SPACING                         (0x30)
+/* Port X Pin Data INPUT Register 32bit (R/W) */
+#define U300_GPIO_PXPDIR                                (0x04)
+/* Port X Pin Data OUTPUT Register 32bit (R/W) */
+#define U300_GPIO_PXPDOR                                (0x08)
+/* Port X Pin Config Register 32bit (R/W) */
+#define U300_GPIO_PXPCR                                 (0x0C)
+#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
+#define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
+#define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
+#define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
+#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
+#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
+#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
+/* Port X Pull-up Enable Register 32bit (R/W) */
+#define U300_GPIO_PXPER                                 (0x10)
+#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
+#define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
+/* Port X Interrupt Event Register 32bit (R/W) */
+#define U300_GPIO_PXIEV                                 (0x14)
+#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK              (0x000000FFUL)
+#define U300_GPIO_PXIEV_IRQ_EVENT                       (0x00000001UL)
+/* Port X Interrupt Enable Register 32bit (R/W) */
+#define U300_GPIO_PXIEN                                 (0x18)
+#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK             (0x000000FFUL)
+#define U300_GPIO_PXIEN_IRQ_ENABLE                      (0x00000001UL)
+/* Port X Interrupt Force Register 32bit (R/W) */
+#define U300_GPIO_PXIFR                                 (0x1C)
+#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK              (0x000000FFUL)
+#define U300_GPIO_PXIFR_IRQ_FORCE                       (0x00000001UL)
+/* Port X Interrupt Config Register 32bit (R/W) */
+#define U300_GPIO_PXICR                                 (0x20)
+#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
+#define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
+#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
+#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
+#ifdef CONFIG_MACH_U300_BS335
+/* seven ports of 8 bits each = GPIO pins 0..55 */
+#define U300_GPIO_NUM_PORTS 7
+#else
+/* five ports of 8 bits each = GPIO pins 0..39 */
+#define U300_GPIO_NUM_PORTS 5
+#endif
+#define U300_GPIO_PINS_PER_PORT 8
+#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
+#endif
+/*
+ * Individual pin assignments for the B26/S26. Notice that the
+ * actual usage of these pins depends on the PAD MUX settings, that
+ * is why the same number can potentially appear several times.
+ * In the reference design each pin is only used for one purpose.
+ * These were determined by inspecting the B26/S26 schematic:
+ * 2/1911-ROA 128 1603
+ */
+#ifdef CONFIG_MACH_U300_BS2X
+#define U300_GPIO_PIN_UART_RX           0
+#define U300_GPIO_PIN_UART_TX           1
+#define U300_GPIO_PIN_GPIO02            2  /* Unrouted */
+#define U300_GPIO_PIN_GPIO03            3  /* Unrouted */
+#define U300_GPIO_PIN_CAM_SLEEP         4
+#define U300_GPIO_PIN_CAM_REG_EN        5
+#define U300_GPIO_PIN_GPIO06            6  /* Unrouted */
+#define U300_GPIO_PIN_GPIO07            7  /* Unrouted */
+#define U300_GPIO_PIN_GPIO08            8  /* Service point SP2321 */
+#define U300_GPIO_PIN_GPIO09            9  /* Service point SP2322 */
+#define U300_GPIO_PIN_PHFSENSE          10 /* Headphone jack sensing */
+#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
+#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
+#define U300_GPIO_PIN_FLIPSENSE         13 /* Mechanical flip sensing */
+#define U300_GPIO_PIN_GPIO14            14 /* DSP JTAG Port RTCK */
+#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
+#define U300_GPIO_PIN_GPIO16            16 /* Unrouted */
+#define U300_GPIO_PIN_GPIO17            17 /* Unrouted */
+#define U300_GPIO_PIN_GPIO18            18 /* Unrouted */
+#define U300_GPIO_PIN_GPIO19            19 /* Unrouted */
+#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
+#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
+#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
+#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
+#endif
+/*
+ * Individual pin assignments for the B330/S330 and B365/S365.
+ * Notice that the actual usage of these pins depends on the
+ * PAD MUX settings, that is why the same number can potentially
+ * appear several times. In the reference design each pin is only
+ * used for one purpose. These were determined by inspecting the
+ * S365 schematic.
+ */
+#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
+    defined(CONFIG_MACH_U300_BS335)
+#define U300_GPIO_PIN_UART_RX           0
+#define U300_GPIO_PIN_UART_TX           1
+#define U300_GPIO_PIN_UART_CTS          2
+#define U300_GPIO_PIN_UART_RTS          3
+#define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
+#define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
+#define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
+#define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
+#define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
+#define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
+#define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
+#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
+#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
+#define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
+#define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
+#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
+#define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
+#define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
+#define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
+#define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
+#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
+#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
+#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
+#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
+#define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
+#define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
+#define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
+#define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
+#define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
+#define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
+#define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
+#define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
+#define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
+#define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
+#define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
+#define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
+#define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
+#define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
+#define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
+#define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
+#define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
+#define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
+#define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
+#define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
+#define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
+#define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
+#define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
+#define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
+#define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
+#define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
+#define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
+#define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
+#define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
+#define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
+#define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
+#endif
+#endif
+/* translates a pin number to a port number */
+#define PIN_TO_PORT(val) (val >> 3)
+/* These can be found in arch/arm/mach-u300/gpio.c */
+extern int gpio_request(unsigned gpio, const char *label);
+extern void gpio_free(unsigned gpio);
+extern int gpio_direction_input(unsigned gpio);
+extern int gpio_direction_output(unsigned gpio, int value);
+extern int gpio_register_callback(unsigned gpio,
+                                  int (*func)(void *arg),
+                                  void *);
+extern int gpio_unregister_callback(unsigned gpio);
+extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
+extern void disable_irq_on_gpio_pin(unsigned gpio);
+extern void gpio_pullup(unsigned gpio, int value);
+extern int gpio_get_value(unsigned gpio);
+extern void gpio_set_value(unsigned gpio, int value);
+/* wrappers to sleep-enable the previous two functions */
+static inline unsigned gpio_to_irq(unsigned gpio)
+{
+        return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
+}
+static inline unsigned irq_to_gpio(unsigned irq)
+{
+        /*
+         * FIXME: This is no 1-1 mapping at all, it points to the
+         * whole block of 8 pins.
+         */
+        return (irq - IRQ_U300_GPIO_PORT0) << 3;
+}
+#endif
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
new file mode 100644
index 000000000000..b99d4ce0ac2b
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/hardware.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-u300/include/mach/hardware.h
+ */
+#include <asm/sizes.h>
+#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
new file mode 100644
index 000000000000..5d6b4c13b3a0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/io.h
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Dummy IO map for being able to use writew()/readw(),
+ * writel()/readw() and similar accessor functions.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+#endif
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
new file mode 100644
index 000000000000..a6867b12773e
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -0,0 +1,114 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/irqs.h
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * IRQ channel definitions for the U300 platforms.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+#define IRQ_U300_INTCON0_START          0
+#define IRQ_U300_INTCON1_START          32
+/* These are on INTCON0 - 30 lines */
+#define IRQ_U300_IRQ0_EXT               0
+#define IRQ_U300_IRQ1_EXT               1
+#define IRQ_U300_DMA                    2
+#define IRQ_U300_VIDEO_ENC_0            3
+#define IRQ_U300_VIDEO_ENC_1            4
+#define IRQ_U300_AAIF_RX                5
+#define IRQ_U300_AAIF_TX                6
+#define IRQ_U300_AAIF_VGPIO             7
+#define IRQ_U300_AAIF_WAKEUP            8
+#define IRQ_U300_PCM_I2S0_FRAME         9
+#define IRQ_U300_PCM_I2S0_FIFO          10
+#define IRQ_U300_PCM_I2S1_FRAME         11
+#define IRQ_U300_PCM_I2S1_FIFO          12
+#define IRQ_U300_XGAM_GAMCON            13
+#define IRQ_U300_XGAM_CDI               14
+#define IRQ_U300_XGAM_CDICON            15
+#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
+/* MMIACC not used on the DB3210 or DB3350 chips */
+#define IRQ_U300_XGAM_MMIACC            16
+#endif
+#define IRQ_U300_XGAM_PDI               17
+#define IRQ_U300_XGAM_PDICON            18
+#define IRQ_U300_XGAM_GAMEACC           19
+#define IRQ_U300_XGAM_MCIDCT            20
+#define IRQ_U300_APEX                   21
+#define IRQ_U300_UART0                  22
+#define IRQ_U300_SPI                    23
+#define IRQ_U300_TIMER_APP_OS           24
+#define IRQ_U300_TIMER_APP_DD           25
+#define IRQ_U300_TIMER_APP_GP1          26
+#define IRQ_U300_TIMER_APP_GP2          27
+#define IRQ_U300_TIMER_OS               28
+#define IRQ_U300_TIMER_MS               29
+#define IRQ_U300_KEYPAD_KEYBF           30
+#define IRQ_U300_KEYPAD_KEYBR           31
+/* These are on INTCON1 - 32 lines */
+#define IRQ_U300_GPIO_PORT0             32
+#define IRQ_U300_GPIO_PORT1             33
+#define IRQ_U300_GPIO_PORT2             34
+#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
+    defined(CONFIG_MACH_U300_BS335)
+/* These are for DB3150, DB3200 and DB3350 */
+#define IRQ_U300_WDOG                   35
+#define IRQ_U300_EVHIST                 36
+#define IRQ_U300_MSPRO                  37
+#define IRQ_U300_MMCSD_MCIINTR0         38
+#define IRQ_U300_MMCSD_MCIINTR1         39
+#define IRQ_U300_I2C0                   40
+#define IRQ_U300_I2C1                   41
+#define IRQ_U300_RTC                    42
+#define IRQ_U300_NFIF                   43
+#define IRQ_U300_NFIF2                  44
+#endif
+/* DB3150 and DB3200 have only 45 IRQs */
+#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
+#define U300_NR_IRQS                    45
+#endif
+/* The DB3350-specific interrupt lines */
+#ifdef CONFIG_MACH_U300_BS335
+#define IRQ_U300_ISP_F0                 45
+#define IRQ_U300_ISP_F1                 46
+#define IRQ_U300_ISP_F2                 47
+#define IRQ_U300_ISP_F3                 48
+#define IRQ_U300_ISP_F4                 49
+#define IRQ_U300_GPIO_PORT3             50
+#define IRQ_U300_SYSCON_PLL_LOCK        51
+#define IRQ_U300_UART1                  52
+#define IRQ_U300_GPIO_PORT4             53
+#define IRQ_U300_GPIO_PORT5             54
+#define IRQ_U300_GPIO_PORT6             55
+#define U300_NR_IRQS                    56
+#endif
+/* The DB3210-specific interrupt lines */
+#ifdef CONFIG_MACH_U300_BS365
+#define IRQ_U300_GPIO_PORT3             35
+#define IRQ_U300_GPIO_PORT4             36
+#define IRQ_U300_WDOG                   37
+#define IRQ_U300_EVHIST                 38
+#define IRQ_U300_MSPRO                  39
+#define IRQ_U300_MMCSD_MCIINTR0         40
+#define IRQ_U300_MMCSD_MCIINTR1         41
+#define IRQ_U300_I2C0                   42
+#define IRQ_U300_I2C1                   43
+#define IRQ_U300_RTC                    44
+#define IRQ_U300_NFIF                   45
+#define IRQ_U300_NFIF2                  46
+#define IRQ_U300_SYSCON_PLL_LOCK        47
+#define U300_NR_IRQS                    48
+#endif
+#define NR_IRQS U300_NR_IRQS
+#endif
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
new file mode 100644
index 000000000000..bf134bcc129d
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -0,0 +1,42 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/memory.h
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Memory virtual/physical mapping constants.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ */
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+#ifdef CONFIG_MACH_U300_DUAL_RAM
+#define PHYS_OFFSET             UL(0x48000000)
+#define BOOT_PARAMS_OFFSET      (PHYS_OFFSET + 0x100)
+#else
+#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
+#define PHYS_OFFSET (0x28000000 + \
+             (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
+             (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
+#else
+#define PHYS_OFFSET (0x28000000 + \
+             (CONFIG_MACH_U300_ACCESS_MEM_SIZE +        \
+             (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
+#endif
+#define BOOT_PARAMS_OFFSET (0x28000000 + \
+            (CONFIG_MACH_U300_ACCESS_MEM_SIZE +         \
+            (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100)
+#endif
+/*
+ * We enable a real big DMA buffer if need be.
+ */
+#define CONSISTENT_DMA_SIZE SZ_4M
+#endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
new file mode 100644
index 000000000000..77d9210a82e2
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/platform.h
@@ -0,0 +1,19 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/platform.h
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Basic platform init and mapping functions.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#ifndef __ASSEMBLY__
+void u300_map_io(void);
+void u300_init_irq(void);
+void u300_init_devices(void);
+extern struct sys_timer u300_timer;
+#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
new file mode 100644
index 000000000000..1c90d1b1ccb6
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -0,0 +1,644 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/syscon.h
+ *
+ *
+ * Copyright (C) 2008 ST-Ericsson AB
+ *
+ * Author: Rickard Andersson <rickard.andersson@stericsson.com>
+ */
+#ifndef __MACH_SYSCON_H
+#define __MACH_SYSCON_H
+/*
+ * All register defines for SYSCON registers that concerns individual
+ * block clocks and reset lines are registered here. This is because
+ * we don't want any other file to try to fool around with this stuff.
+ */
+/* APP side SYSCON registers */
+/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
+/* CLK Control Register 16bit (R/W) */
+#define U300_SYSCON_CCR                                         (0x0000)
+#define U300_SYSCON_CCR_I2S1_USE_VCXO                           (0x0040)
+#define U300_SYSCON_CCR_I2S0_USE_VCXO                           (0x0020)
+#define U300_SYSCON_CCR_TURN_VCXO_ON                            (0x0008)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK                 (0x0007)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER            (0x04)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW                  (0x03)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE         (0x02)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH                 (0x01)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST                 (0x00)
+/* CLK Status Register 16bit (R/W) */
+#define U300_SYSCON_CSR                                         (0x0004)
+#define U300_SYSCON_CSR_PLL208_LOCK_IND                         (0x0002)
+#define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
+/* Reset lines for SLOW devices 16bit (R/W) */
+#define U300_SYSCON_RSR                                         (0x0014)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
+#endif
+#define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
+#define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
+#define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
+#define U300_SYSCON_RSR_KEYPAD_RESET_EN                         (0x0020)
+#define U300_SYSCON_RSR_GPIO_RESET_EN                           (0x0010)
+#define U300_SYSCON_RSR_EH_RESET_EN                             (0x0008)
+#define U300_SYSCON_RSR_BTR_RESET_EN                            (0x0004)
+#define U300_SYSCON_RSR_UART_RESET_EN                           (0x0002)
+#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
+/* Reset lines for FAST devices 16bit (R/W) */
+#define U300_SYSCON_RFR                                         (0x0018)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
+#endif
+#define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
+#define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
+#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
+#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE                   (0x0008)
+#define U300_SYSCON_RFR_I2C1_RESET_ENABLE                       (0x0004)
+#define U300_SYSCON_RFR_I2C0_RESET_ENABLE                       (0x0002)
+#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
+/* Reset lines for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_RRR                                         (0x001c)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
+#define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
+#endif
+#define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
+#define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
+#define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
+#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN                   (0x0080)
+#define U300_SYSCON_RRR_NANDIF_RESET_EN                         (0x0040)
+#define U300_SYSCON_RRR_EMIF_RESET_EN                           (0x0020)
+#define U300_SYSCON_RRR_DMAC_RESET_EN                           (0x0010)
+#define U300_SYSCON_RRR_CPU_RESET_EN                            (0x0008)
+#define U300_SYSCON_RRR_APEX_RESET_EN                           (0x0004)
+#define U300_SYSCON_RRR_AHB_RESET_EN                            (0x0002)
+#define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
+/* Clock enable for SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CESR                                        (0x0020)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
+#endif
+#define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
+#define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
+#define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
+#define U300_SYSCON_CESR_GPIO_CLK_EN                            (0x0010)
+#define U300_SYSCON_CESR_EH_CLK_EN                              (0x0008)
+#define U300_SYSCON_CESR_BTR_CLK_EN                             (0x0004)
+#define U300_SYSCON_CESR_UART_CLK_EN                            (0x0002)
+#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
+/* Clock enable for FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CEFR                                        (0x0024)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
+#endif
+#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
+#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
+#define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
+#define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
+#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
+/* Clock enable for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CERR                                        (0x0028)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
+#define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
+#endif
+#define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
+#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
+#define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
+#define U300_SYSCON_CERR_XGAM_CLK_EN                            (0x0100)
+#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN                       (0x0080)
+#define U300_SYSCON_CERR_NANDIF_CLK_EN                          (0x0040)
+#define U300_SYSCON_CERR_EMIF_CLK_EN                            (0x0020)
+#define U300_SYSCON_CERR_DMAC_CLK_EN                            (0x0010)
+#define U300_SYSCON_CERR_CPU_CLK_EN                             (0x0008)
+#define U300_SYSCON_CERR_APEX_CLK_EN                            (0x0004)
+#define U300_SYSCON_CERR_AHB_CLK_EN                             (0x0002)
+#define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
+/* Single block clock enable 16bit (-/W) */
+#define U300_SYSCON_SBCER                                       (0x002c)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
+#endif
+#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
+#define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
+#define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
+#define U300_SYSCON_SBCER_GPIO_CLK_EN                           (0x0004)
+#define U300_SYSCON_SBCER_EH_CLK_EN                             (0x0003)
+#define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
+#define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
+#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
+#endif
+#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
+#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
+#define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
+#define U300_SYSCON_SBCER_MMC_CLK_EN                            (0x0015)
+#define U300_SYSCON_SBCER_I2S1_CLK_EN                           (0x0014)
+#define U300_SYSCON_SBCER_I2S0_CLK_EN                           (0x0013)
+#define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
+#define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
+#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
+#define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
+#endif
+#define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
+#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
+#define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
+#define U300_SYSCON_SBCER_XGAM_CLK_EN                           (0x0028)
+#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN                      (0x0027)
+#define U300_SYSCON_SBCER_NANDIF_CLK_EN                         (0x0026)
+#define U300_SYSCON_SBCER_EMIF_CLK_EN                           (0x0025)
+#define U300_SYSCON_SBCER_DMAC_CLK_EN                           (0x0024)
+#define U300_SYSCON_SBCER_CPU_CLK_EN                            (0x0023)
+#define U300_SYSCON_SBCER_APEX_CLK_EN                           (0x0022)
+#define U300_SYSCON_SBCER_AHB_CLK_EN                            (0x0021)
+#define U300_SYSCON_SBCER_AAIF_CLK_EN                           (0x0020)
+/* Single block clock disable 16bit (-/W) */
+#define U300_SYSCON_SBCDR                                       (0x0030)
+/* Same values as above for SBCER */
+/* Clock force SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CFSR                                        (0x003c)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
+#endif
+#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
+#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
+#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
+#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN                      (0x0010)
+#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN                        (0x0008)
+#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN                       (0x0004)
+#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN                      (0x0002)
+#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN               (0x0001)
+/* Clock force FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CFFR                                        (0x40)
+/* Values not defined. Define if you want to use them. */
+/* Clock force the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CFRR                                        (0x44)
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
+#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
+#endif
+#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
+#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
+#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
+#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN                      (0x0100)
+#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN                 (0x0080)
+#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN                    (0x0040)
+#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN                      (0x0020)
+#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN                      (0x0010)
+#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN                       (0x0008)
+#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN                      (0x0004)
+#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN                       (0x0002)
+#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN                      (0x0001)
+/* PLL208 Frequency Control 16bit (R/W) */
+#define U300_SYSCON_PFCR                                        (0x48)
+#define U300_SYSCON_PFCR_DPLL_MULT_NUM                          (0x000F)
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR                                        (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
+/*
+ * All other clocking registers moved to clock.c!
+ */
+/* Reset Out 16bit (R/W) */
+#define U300_SYSCON_RCR                                         (0x6c)
+#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE                   (0x0001)
+/* EMIF Slew Rate Control 16bit (R/W) */
+#define U300_SYSCON_SRCLR                                       (0x70)
+#define U300_SYSCON_SRCLR_MASK                                  (0x03FF)
+#define U300_SYSCON_SRCLR_VALUE                                 (0x03FF)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B                       (0x0200)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A                       (0x0100)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B                       (0x0080)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A                       (0x0040)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B                       (0x0020)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A                       (0x0010)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B                       (0x0008)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A                       (0x0004)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B                       (0x0002)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A                       (0x0001)
+/* EMIF Clock Control Register 16bit (R/W) */
+#define U300_SYSCON_ECCR                                        (0x0078)
+#define U300_SYSCON_ECCR_MASK                                   (0x000F)
+#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE         (0x0008)
+#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
+#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
+#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
+/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
+#define U300_SYSCON_PMC1LR                                      (0x007C)
+#define U300_SYSCON_PMC1LR_MASK                                 (0xFFFF)
+#define U300_SYSCON_PMC1LR_CDI_MASK                             (0xC000)
+#define U300_SYSCON_PMC1LR_CDI_CDI                              (0x0000)
+#define U300_SYSCON_PMC1LR_CDI_EMIF                             (0x4000)
+#define U300_SYSCON_PMC1LR_CDI_GPIO                             (0x8000)
+#define U300_SYSCON_PMC1LR_CDI_WCDMA                            (0xC000)
+#define U300_SYSCON_PMC1LR_PDI_MASK                             (0x3000)
+#define U300_SYSCON_PMC1LR_PDI_PDI                              (0x0000)
+#define U300_SYSCON_PMC1LR_PDI_EGG                              (0x1000)
+#define U300_SYSCON_PMC1LR_PDI_WCDMA                            (0x3000)
+#define U300_SYSCON_PMC1LR_MMCSD_MASK                           (0x0C00)
+#define U300_SYSCON_PMC1LR_MMCSD_MMCSD                          (0x0000)
+#define U300_SYSCON_PMC1LR_MMCSD_MSPRO                          (0x0400)
+#define U300_SYSCON_PMC1LR_MMCSD_DSP                            (0x0800)
+#define U300_SYSCON_PMC1LR_MMCSD_WCDMA                          (0x0C00)
+#define U300_SYSCON_PMC1LR_ETM_MASK                             (0x0300)
+#define U300_SYSCON_PMC1LR_ETM_ACC                              (0x0000)
+#define U300_SYSCON_PMC1LR_ETM_APP                              (0x0100)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK                      (0x00C0)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC                    (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF                      (0x0040)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM                     (0x0080)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB                (0x00C0)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK                      (0x0030)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC                    (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF                      (0x0010)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM                     (0x0020)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI                      (0x0030)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK                      (0x000C)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC                    (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF                      (0x0004)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM                     (0x0008)
+#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI                      (0x000C)
+#define U300_SYSCON_PMC1LR_EMIF_1_MASK                          (0x0003)
+#define U300_SYSCON_PMC1LR_EMIF_1_STATIC                        (0x0000)
+#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0                        (0x0001)
+#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1                        (0x0002)
+#define U300_SYSCON_PMC1LR_EMIF_1                               (0x0003)
+/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
+#define U300_SYSCON_PMC1HR                                      (0x007E)
+#define U300_SYSCON_PMC1HR_MASK                                 (0xFFFF)
+#define U300_SYSCON_PMC1HR_MISC_2_MASK                          (0xC000)
+#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO                      (0x0000)
+#define U300_SYSCON_PMC1HR_MISC_2_MSPRO                         (0x4000)
+#define U300_SYSCON_PMC1HR_MISC_2_DSP                           (0x8000)
+#define U300_SYSCON_PMC1HR_MISC_2_AAIF                          (0xC000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK                      (0x3000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO                  (0x0000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF                      (0x1000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP                       (0x2000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF                      (0x3000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK                      (0x0C00)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO                  (0x0000)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC                       (0x0400)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP                       (0x0800)
+#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF                      (0x0C00)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK                    (0x0300)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO                (0x0000)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI                     (0x0100)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF                    (0x0300)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK                    (0x00C0)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO                (0x0000)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI                     (0x0040)
+#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF                    (0x00C0)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK                       (0x0030)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO                   (0x0000)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI                        (0x0010)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP                        (0x0020)
+#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF                       (0x0030)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK                     (0x000C)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO                 (0x0000)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0                    (0x0004)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS                  (0x0008)
+#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF                     (0x000C)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK                     (0x0003)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO                 (0x0000)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0                    (0x0001)
+#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF                     (0x0003)
+/* Step one for killing the applications system 16bit (-/W) */
+#define U300_SYSCON_KA1R                                        (0x0080)
+#define U300_SYSCON_KA1R_MASK                                   (0xFFFF)
+#define U300_SYSCON_KA1R_VALUE                                  (0xFFFF)
+/* Step two for killing the application system 16bit (-/W) */
+#define U300_SYSCON_KA2R                                        (0x0084)
+#define U300_SYSCON_KA2R_MASK                                   (0xFFFF)
+#define U300_SYSCON_KA2R_VALUE                                  (0xFFFF)
+/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
+#define U300_SYSCON_MMF0R                                       (0x90)
+#define U300_SYSCON_MMF0R_MASK                                  (0x00FF)
+#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK                      (0x00F0)
+#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK                       (0x000F)
+/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
+#define U300_SYSCON_MMF1R                                       (0x94)
+#define U300_SYSCON_MMF1R_MASK                                  (0x00FF)
+#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK                      (0x00F0)
+#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK                       (0x000F)
+/* AAIF control register 16 bit (R/W) */
+#define U300_SYSCON_AAIFCR                                      (0x98)
+#define U300_SYSCON_AAIFCR_MASK                                 (0x0003)
+#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK                       (0x0003)
+#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL                 (0x0000)
+#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING                 (0x0001)
+#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT                 (0x0002)
+#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT                 (0x0003)
+/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
+#define U300_SYSCON_MMCR                                        (0x9C)
+#define U300_SYSCON_MMCR_MASK                                   (0x0003)
+#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE                  (0x0002)
+#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE                   (0x0001)
+/* TODO: More SYSCON registers missing */
+#define U300_SYSCON_PMC3R                                       (0x10c)
+#define U300_SYSCON_PMC3R_APP_MISC_11_MASK                      (0xc000)
+#define U300_SYSCON_PMC3R_APP_MISC_11_SPI                       (0x4000)
+#define U300_SYSCON_PMC3R_APP_MISC_10_MASK                      (0x3000)
+#define U300_SYSCON_PMC3R_APP_MISC_10_SPI                       (0x1000)
+/* TODO: Missing other configs, I just added the SPI stuff */
+/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
+#define U300_SYSCON_S0CCR                                       (0x120)
+#define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
+#define U300_SYSCON_S0CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S0CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S0CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S0CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S0CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
+#define U300_SYSCON_S1CCR                                       (0x124)
+#define U300_SYSCON_S1CCR_FIELD_MASK                            (0x43FF)
+#define U300_SYSCON_S1CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S1CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S1CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S1CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S1CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
+#define U300_SYSCON_S2CCR                                       (0x128)
+#define U300_SYSCON_S2CCR_FIELD_MASK                            (0xC3FF)
+#define U300_SYSCON_S2CCR_CLK_STEAL                             (0x8000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S2CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S2CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S2CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S2CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
+#define U300_SYSCON_MCR                                         (0x12c)
+#define U300_SYSCON_MCR_FIELD_MASK                              (0x00FF)
+#define U300_SYSCON_MCR_PMGEN_CR_4_MASK                         (0x00C0)
+#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO                         (0x0000)
+#define U300_SYSCON_MCR_PMGEN_CR_4_SPI                          (0x0040)
+#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF                         (0x00C0)
+#define U300_SYSCON_MCR_PMGEN_CR_2_MASK                         (0x0030)
+#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO                         (0x0000)
+#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC                (0x0010)
+#define U300_SYSCON_MCR_PMGEN_CR_2_DSP                          (0x0020)
+#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF                         (0x0030)
+#define U300_SYSCON_MCR_PMGEN_CR_0_MASK                         (0x000C)
+#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1              (0x0000)
+#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2              (0x0004)
+#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3              (0x0008)
+#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM                 (0x000C)
+#define U300_SYSCON_MCR_PM1G_MODE_ENABLE                        (0x0002)
+#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE                       (0x0001)
+/* Clock activity observability register 0 */
+#define U300_SYSCON_C0OAR                                       (0x140)
+#define U300_SYSCON_C0OAR_MASK                                  (0xFFFF)
+#define U300_SYSCON_C0OAR_VALUE                                 (0xFFFF)
+#define U300_SYSCON_C0OAR_BT_H_CLK                              (0x8000)
+#define U300_SYSCON_C0OAR_ASPB_P_CLK                            (0x4000)
+#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK                        (0x2000)
+#define U300_SYSCON_C0OAR_APP_SEMI_CLK                          (0x1000)
+#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK                     (0x0800)
+#define U300_SYSCON_C0OAR_APP_I2S1_CLK                          (0x0400)
+#define U300_SYSCON_C0OAR_APP_I2S0_CLK                          (0x0200)
+#define U300_SYSCON_C0OAR_APP_CPU_CLK                           (0x0100)
+#define U300_SYSCON_C0OAR_APP_52_CLK                            (0x0080)
+#define U300_SYSCON_C0OAR_APP_208_CLK                           (0x0040)
+#define U300_SYSCON_C0OAR_APP_104_CLK                           (0x0020)
+#define U300_SYSCON_C0OAR_APEX_CLK                              (0x0010)
+#define U300_SYSCON_C0OAR_AHPB_M_H_CLK                          (0x0008)
+#define U300_SYSCON_C0OAR_AHB_CLK                               (0x0004)
+#define U300_SYSCON_C0OAR_AFPB_P_CLK                            (0x0002)
+#define U300_SYSCON_C0OAR_AAIF_CLK                              (0x0001)
+/* Clock activity observability register 1 */
+#define U300_SYSCON_C1OAR                                       (0x144)
+#define U300_SYSCON_C1OAR_MASK                                  (0x3FFE)
+#define U300_SYSCON_C1OAR_VALUE                                 (0x3FFE)
+#define U300_SYSCON_C1OAR_NFIF_F_CLK                            (0x2000)
+#define U300_SYSCON_C1OAR_MSPRO_CLK                             (0x1000)
+#define U300_SYSCON_C1OAR_MMC_P_CLK                             (0x0800)
+#define U300_SYSCON_C1OAR_MMC_CLK                               (0x0400)
+#define U300_SYSCON_C1OAR_KP_P_CLK                              (0x0200)
+#define U300_SYSCON_C1OAR_I2C1_P_CLK                            (0x0100)
+#define U300_SYSCON_C1OAR_I2C0_P_CLK                            (0x0080)
+#define U300_SYSCON_C1OAR_GPIO_CLK                              (0x0040)
+#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK                         (0x0020)
+#define U300_SYSCON_C1OAR_EMIF_H_CLK                            (0x0010)
+#define U300_SYSCON_C1OAR_EVHIST_CLK                            (0x0008)
+#define U300_SYSCON_C1OAR_PPM_CLK                               (0x0004)
+#define U300_SYSCON_C1OAR_DMA_CLK                               (0x0002)
+/* Clock activity observability register 2 */
+#define U300_SYSCON_C2OAR                                       (0x148)
+#define U300_SYSCON_C2OAR_MASK                                  (0x0FFF)
+#define U300_SYSCON_C2OAR_VALUE                                 (0x0FFF)
+#define U300_SYSCON_C2OAR_XGAM_CDI_CLK                          (0x0800)
+#define U300_SYSCON_C2OAR_XGAM_CLK                              (0x0400)
+#define U300_SYSCON_C2OAR_VC_H_CLK                              (0x0200)
+#define U300_SYSCON_C2OAR_VC_CLK                                (0x0100)
+#define U300_SYSCON_C2OAR_UA_P_CLK                              (0x0080)
+#define U300_SYSCON_C2OAR_TMR1_CLK                              (0x0040)
+#define U300_SYSCON_C2OAR_TMR0_CLK                              (0x0020)
+#define U300_SYSCON_C2OAR_SPI_P_CLK                             (0x0010)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK                     (0x0008)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK                          (0x0004)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK                     (0x0002)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK                          (0x0001)
+/* Chip ID register 16bit (R/-) */
+#define U300_SYSCON_CIDR                                        (0x400)
+/* Video IRQ clear 16bit (R/W) */
+#define U300_SYSCON_VICR                                        (0x404)
+#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE                (0x0002)
+#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE                (0x0001)
+/* SMCR */
+#define U300_SYSCON_SMCR                                        (0x4d0)
+#define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
+#define U300_SYSCON_CSDR                                        (0x4f0)
+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
+/* PRINT_CONTROL Print Control 16bit (R/-) */
+#define U300_SYSCON_PCR                                         (0x4f8)
+#define U300_SYSCON_PCR_SERV_IND                                (0x0001)
+/* BOOT_CONTROL 16bit (R/-) */
+#define U300_SYSCON_BCR                                         (0x4fc)
+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
+/* CPU clock defines */
+/**
+ * CPU high frequency in MHz
+ */
+#define SYSCON_CPU_CLOCK_HIGH    208
+/**
+ * CPU medium frequency in MHz
+ */
+#define SYSCON_CPU_CLOCK_MEDIUM  104
+/**
+ * CPU low frequency in MHz
+ */
+#define SYSCON_CPU_CLOCK_LOW      13
+/* EMIF clock defines */
+/**
+ * EMIF high frequency in MHz
+ */
+#define SYSCON_EMIF_CLOCK_HIGH   104
+/**
+ * EMIF medium frequency in MHz
+ */
+#define SYSCON_EMIF_CLOCK_MEDIUM 104
+/**
+ * EMIF low frequency in MHz
+ */
+#define SYSCON_EMIF_CLOCK_LOW     13
+/* AHB clock defines */
+/**
+ * AHB high frequency in MHz
+ */
+#define SYSCON_AHB_CLOCK_HIGH     52
+/**
+ * AHB medium frequency in MHz
+ */
+#define SYSCON_AHB_CLOCK_MEDIUM   52
+/**
+ * AHB low frequency in MHz
+ */
+#define SYSCON_AHB_CLOCK_LOW       7  /* i.e 13/2=6.5MHz */
+enum syscon_busmaster {
+  SYSCON_BM_DMAC,
+  SYSCON_BM_XGAM,
+  SYSCON_BM_VIDEO_ENC
+};
+/*
+ * Note that this array must match the order of the array "clk_reg"
+ * in syscon.c
+ */
+enum syscon_clk {
+  SYSCON_CLKCONTROL_SLOW_BRIDGE,
+  SYSCON_CLKCONTROL_UART,
+  SYSCON_CLKCONTROL_BTR,
+  SYSCON_CLKCONTROL_EH,
+  SYSCON_CLKCONTROL_GPIO,
+  SYSCON_CLKCONTROL_KEYPAD,
+  SYSCON_CLKCONTROL_APP_TIMER,
+  SYSCON_CLKCONTROL_ACC_TIMER,
+  SYSCON_CLKCONTROL_FAST_BRIDGE,
+  SYSCON_CLKCONTROL_I2C0,
+  SYSCON_CLKCONTROL_I2C1,
+  SYSCON_CLKCONTROL_I2S0,
+  SYSCON_CLKCONTROL_I2S1,
+  SYSCON_CLKCONTROL_MMC,
+  SYSCON_CLKCONTROL_SPI,
+  SYSCON_CLKCONTROL_I2S0_CORE,
+  SYSCON_CLKCONTROL_I2S1_CORE,
+  SYSCON_CLKCONTROL_AAIF,
+  SYSCON_CLKCONTROL_AHB,
+  SYSCON_CLKCONTROL_APEX,
+  SYSCON_CLKCONTROL_CPU,
+  SYSCON_CLKCONTROL_DMA,
+  SYSCON_CLKCONTROL_EMIF,
+  SYSCON_CLKCONTROL_NAND_IF,
+  SYSCON_CLKCONTROL_VIDEO_ENC,
+  SYSCON_CLKCONTROL_XGAM,
+  SYSCON_CLKCONTROL_SEMI,
+  SYSCON_CLKCONTROL_AHB_SUBSYS,
+  SYSCON_CLKCONTROL_MSPRO
+};
+enum syscon_sysclk_mode {
+  SYSCON_SYSCLK_DISABLED,
+  SYSCON_SYSCLK_M_CLK,
+  SYSCON_SYSCLK_ACC_FSM,
+  SYSCON_SYSCLK_PLL60_48,
+  SYSCON_SYSCLK_PLL60_60,
+  SYSCON_SYSCLK_ACC_PLL208,
+  SYSCON_SYSCLK_APP_PLL13,
+  SYSCON_SYSCLK_APP_FSM,
+  SYSCON_SYSCLK_RTC,
+  SYSCON_SYSCLK_APP_PLL208
+};
+enum syscon_sysclk_req {
+  SYSCON_SYSCLKREQ_DISABLED,
+  SYSCON_SYSCLKREQ_ACTIVE_LOW
+};
+enum syscon_clk_mode {
+  SYSCON_CLKMODE_OFF,
+  SYSCON_CLKMODE_DEFAULT,
+  SYSCON_CLKMODE_LOW,
+  SYSCON_CLKMODE_MEDIUM,
+  SYSCON_CLKMODE_HIGH,
+  SYSCON_CLKMODE_PERMANENT,
+  SYSCON_CLKMODE_ON,
+};
+enum syscon_call_mode {
+  SYSCON_CLKCALL_NOWAIT,
+  SYSCON_CLKCALL_WAIT,
+};
+int syscon_dc_on(bool keep_power_on);
+int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
+                                      bool active);
+bool syscon_get_busmaster_active_state(void);
+int syscon_set_sleep_mask(enum syscon_clk,
+                          bool sleep_ctrl);
+int syscon_config_sysclk(u32 sysclk,
+                         enum syscon_sysclk_mode sysclkmode,
+                         bool inverse,
+                         u32 divisor,
+                         enum syscon_sysclk_req sysclkreq);
+bool syscon_can_turn_off_semi_clock(void);
+/* This function is restricted to core.c */
+int syscon_request_normal_power(bool req);
+/* This function is restricted to be used by platform_speed.c */
+int syscon_speed_request(enum syscon_call_mode wait_mode,
+                         enum syscon_clk_mode req_clk_mode);
+#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
new file mode 100644
index 000000000000..8daf13634ce0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/system.h
@@ -0,0 +1,42 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/system.h
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * System shutdown and reset functions.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/hardware/vic.h>
+#include <asm/irq.h>
+/* Forward declare this function from the watchdog */
+void coh901327_watchdog_reset(void);
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static void arch_reset(char mode, const char *cmd)
+{
+        switch (mode) {
+        case 's':
+        case 'h':
+                printk(KERN_CRIT "RESET: shutting down/rebooting system\n");
+                /* Disable interrupts */
+                local_irq_disable();
+#ifdef CONFIG_COH901327_WATCHDOG
+                coh901327_watchdog_reset();
+#endif
+                break;
+        default:
+                /* Do nothing */
+                break;
+        }
+        /* Wait for system do die/reset. */
+        while (1);
+}
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
new file mode 100644
index 000000000000..f233b72633f6
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/timex.h
@@ -0,0 +1,17 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/timex.h
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Platform tick rate definition.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+/* This is for the APP OS GP1 (General Purpose 1) timer */
+#define CLOCK_TICK_RATE         1000000
+#endif
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
new file mode 100644
index 000000000000..88333dfb19fc
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -0,0 +1,187 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/u300-regs.h
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Basic register address definitions in physical memory and
+ * some block defintions for core devices like the timer.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#ifndef __MACH_U300_REGS_H
+#define __MACH_U300_REGS_H
+/*
+ * These are the large blocks of memory allocated for I/O.
+ * the defines are used for setting up the I/O memory mapping.
+ */
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE         0x80000000
+#define U300_NAND_CS0_VIRT_BASE         0xff040000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE          0x9f800000
+#define U300_NAND_IF_VIRT_BASE          0xff030000
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE          0xa0000000
+#define U300_AHB_PER_VIRT_BASE          0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE         0xc0000000
+#define U300_FAST_PER_VIRT_BASE         0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE         0xc0010000
+#define U300_SLOW_PER_VIRT_BASE         0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE          0xffff0000
+#define U300_BOOTROM_VIRT_BASE          0xffff0000
+/* SEMI config base */
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_SEMI_CONFIG_BASE           0x2FFE0000
+#else
+#define U300_SEMI_CONFIG_BASE           0x30000000
+#endif
+/*
+ * All the following peripherals are specified at their PHYSICAL address,
+ * so if you need to access them (in the kernel), you MUST use the macros
+ * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST()
+ * etc.
+ */
+/*
+ * AHB peripherals
+ */
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE              (U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE              (U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
+/*
+ * FAST peripherals
+ */
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
+#ifdef CONFIG_MACH_U300_BS335
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE                 (U300_SLOW_PER_PHYS_BASE+0x7000)
+#endif
+/*
+ * SLOW peripherals
+ */
+/* SLOW bridge control */
+#define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
+/* SYSCON */
+#define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE               (U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE            (U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
+/*
+ * REST peripherals
+ */
+/* ISP (image signal processor) is only available in U335 */
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_ISP_BASE                   (0xA0008000)
+#endif
+/* DMA Controller base */
+#define U300_DMAC_BASE                  (0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE                   (0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE                  (0xc0030000)
+/* Video Encoder Base */
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_VIDEOENC_BASE              (0xc0080000)
+#else
+#define U300_VIDEOENC_BASE              (0xc0040000)
+#endif
+/* XGAM Base */
+#define U300_XGAM_BASE                  (0xd0000000)
+/*
+ * Virtual accessor macros for static devices
+ */
+#endif
diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-u300/include/mach/uncompress.h
index 46d4ca91af79..29acb718acf7 100644
--- a/arch/arm/mach-imx/include/mach/system.h
+++ b/arch/arm/mach-u300/include/mach/uncompress.h
@@ -1,8 +1,7 @@
 /*
- *  arch/arm/mach-imxads/include/mach/system.h
+ * arch/arm/mach-u300/include/mach/uncompress.h
 *
- *  Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -18,23 +17,30 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_SYSTEM_H
+#define AMBA_UART_DR    (*(volatile unsigned char *)0xc0013000)
-#define __ASM_ARCH_SYSTEM_H
+#define AMBA_UART_LCRH  (*(volatile unsigned char *)0xc001302C)
+#define AMBA_UART_CR    (*(volatile unsigned char *)0xc0013030)
+#define AMBA_UART_FR    (*(volatile unsigned char *)0xc0013018)
-static void
+/*
-arch_idle(void)
+ * This does not append a newline
+ */
+static inline void putc(int c)
 {
-        /*
+        while (AMBA_UART_FR & (1 << 5))
-         * This should do all the clock switching
+                barrier();
-         * and wait for interrupt tricks
-         */
+        AMBA_UART_DR = c;
-        cpu_do_idle();
 }
-static inline void
+static inline void flush(void)
-arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        while (AMBA_UART_FR & (1 << 3))
+                barrier();
 }
-#endif
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
new file mode 100644
index 000000000000..b00c51a66fbe
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/vmalloc.h
@@ -0,0 +1,12 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/vmalloc.h
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Virtual memory allocations
+ * End must be above the I/O registers and on an even 2MiB boundary.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#define VMALLOC_END     0xfe800000
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
new file mode 100644
index 000000000000..3138d3955c9e
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.c
@@ -0,0 +1,216 @@
+/*
+ *
+ * arch/arm/mach-u300/mmc.c
+ *
+ *
+ * Copyright (C) 2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ * Author: Johan Lundin <johan.lundin@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ */
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/mmc/host.h>
+#include <linux/input.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
+#include <linux/gpio.h>
+#include <asm/mach/mmc.h>
+#include "mmc.h"
+struct mmci_card_event {
+        struct input_dev *mmc_input;
+        int mmc_inserted;
+        struct work_struct workq;
+        struct mmc_platform_data mmc0_plat_data;
+};
+static unsigned int mmc_status(struct device *dev)
+{
+        struct mmci_card_event *mmci_card = container_of(
+                dev->platform_data,
+                struct mmci_card_event, mmc0_plat_data);
+        return mmci_card->mmc_inserted;
+}
+/*
+ * Here follows a large chunk of code which will only be enabled if you
+ * have both the AB3100 chip mounted and the MMC subsystem activated.
+ */
+static u32 mmc_translate_vdd(struct device *dev, unsigned int voltage)
+{
+        int v;
+        /*
+         * MMC Spec:
+         * bit 7:       1.70 - 1.95V
+         * bit 8 - 14:  2.0 - 2.6V
+         * bit 15 - 23: 2.7 - 3.6V
+         *
+         * ab3100 voltages:
+         * 000 - 2.85V
+         * 001 - 2.75V
+         * 010 - 1.8V
+         * 011 - 1.5V
+         */
+        switch (voltage) {
+        case 8:
+                v = 3;
+                break;
+        case 9:
+        case 10:
+        case 11:
+        case 12:
+        case 13:
+        case 14:
+        case 15:
+                v = 1;
+                break;
+        case 16:
+                v = 1;
+                break;
+        case 17:
+        case 18:
+        case 19:
+        case 20:
+        case 21:
+        case 22:
+        case 23:
+        case 24:
+                v = 0;
+                break;
+        default:
+                v = 0;
+                break;
+        }
+        /* PL180 voltage register bits */
+        return v << 2;
+}
+static int mmci_callback(void *data)
+{
+        struct mmci_card_event *mmci_card = data;
+        disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD);
+        schedule_work(&mmci_card->workq);
+        return 0;
+}
+static ssize_t gpio_show(struct device *dev, struct device_attribute *attr,
+                  char *buf)
+{
+        struct mmci_card_event *mmci_card = container_of(
+                dev->platform_data,
+                struct mmci_card_event, mmc0_plat_data);
+        return sprintf(buf, "%d\n", !mmci_card->mmc_inserted);
+}
+static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL);
+static void _mmci_callback(struct work_struct *ws)
+{
+        struct mmci_card_event *mmci_card = container_of(
+                ws,
+                struct mmci_card_event, workq);
+        mdelay(20);
+        mmci_card->mmc_inserted = !!gpio_get_value(U300_GPIO_PIN_MMC_CD);
+        input_report_switch(mmci_card->mmc_input, KEY_INSERT,
+                            !mmci_card->mmc_inserted);
+        input_sync(mmci_card->mmc_input);
+        pr_debug("MMC/SD card was %s\n",
+                 mmci_card->mmc_inserted ? "removed" : "inserted");
+        enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, !mmci_card->mmc_inserted);
+}
+int __devinit mmc_init(struct amba_device *adev)
+{
+        struct mmci_card_event *mmci_card;
+        struct device *mmcsd_device = &adev->dev;
+        int ret = 0;
+        mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL);
+        if (!mmci_card)
+                return -ENOMEM;
+        /* Nominally 2.85V on our platform */
+        mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29;
+        mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd;
+        mmci_card->mmc0_plat_data.status = mmc_status;
+        mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
+        INIT_WORK(&mmci_card->workq, _mmci_callback);
+        ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection");
+        if (ret) {
+                printk(KERN_CRIT "Could not allocate MMC card detection " \
+                       "GPIO pin\n");
+                goto out;
+        }
+        ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD);
+        if (ret) {
+                printk(KERN_CRIT "Invalid GPIO pin requested\n");
+                goto out;
+        }
+        ret = sysfs_create_file(&mmcsd_device->kobj,
+                               &dev_attr_mmc_inserted.attr);
+        if (ret)
+                goto out;
+        mmci_card->mmc_input = input_allocate_device();
+        if (!mmci_card->mmc_input) {
+                printk(KERN_CRIT "Could not allocate MMC input device\n");
+                return -ENOMEM;
+        }
+        mmci_card->mmc_input->name = "MMC insert notification";
+        mmci_card->mmc_input->id.bustype = BUS_HOST;
+        mmci_card->mmc_input->id.vendor = 0;
+        mmci_card->mmc_input->id.product = 0;
+        mmci_card->mmc_input->id.version = 0x0100;
+        mmci_card->mmc_input->dev.parent = mmcsd_device;
+        input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT);
+        /*
+         * Since this must always be compiled into the kernel, this input
+         * is never unregistered or free:ed.
+         */
+        ret = input_register_device(mmci_card->mmc_input);
+        if (ret) {
+                input_free_device(mmci_card->mmc_input);
+                goto out;
+        }
+        input_set_drvdata(mmci_card->mmc_input, mmci_card);
+        ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback,
+                                     mmci_card);
+        schedule_work(&mmci_card->workq);
+        printk(KERN_INFO "Registered MMC insert/remove notification\n");
+out:
+        return ret;
+}
diff --git a/arch/arm/mach-u300/mmc.h b/arch/arm/mach-u300/mmc.h
new file mode 100644
index 000000000000..92b85125abb3
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.h
@@ -0,0 +1,18 @@
+/*
+ *
+ * arch/arm/mach-u300/mmc.h
+ *
+ *
+ * Copyright (C) 2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ */
+#ifndef MMC_H
+#define MMC_H
+#include <linux/amba/bus.h>
+int __devinit mmc_init(struct amba_device *adev);
+#endif
diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c
new file mode 100644
index 000000000000..f3664564f086
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.c
@@ -0,0 +1,58 @@
+/*
+ *
+ * arch/arm/mach-u300/padmux.c
+ *
+ *
+ * Copyright (C) 2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * U300 PADMUX functions
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ *
+ */
+#include <linux/io.h>
+#include <linux/err.h>
+#include <mach/u300-regs.h>
+#include <mach/syscon.h>
+#include "padmux.h"
+/* Set the PAD MUX to route the MMC reader correctly to GPIO0. */
+void pmx_set_mission_mode_mmc(void)
+{
+        u16 val;
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1LR);
+        val &= ~U300_SYSCON_PMC1LR_MMCSD_MASK;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1LR);
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
+        val &= ~U300_SYSCON_PMC1HR_APP_GPIO_1_MASK;
+        val |= U300_SYSCON_PMC1HR_APP_GPIO_1_MMC;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
+}
+void pmx_set_mission_mode_spi(void)
+{
+        u16 val;
+        /* Set up padmuxing so the SPI port and its chipselects are active */
+        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
+        /*
+         * Activate the SPI port (disable the use of these pins for generic
+         * GPIO, DSP, AAIF
+         */
+        val &= ~U300_SYSCON_PMC1HR_APP_SPI_2_MASK;
+        val |= U300_SYSCON_PMC1HR_APP_SPI_2_SPI;
+        /*
+         * Use GPIO pin SPI CS1 for CS1 actually (it can be used for other
+         * things also)
+         */
+        val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK;
+        val |= U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI;
+        /*
+         * Use GPIO pin SPI CS2 for CS2 actually (it can be used for other
+         * things also)
+         */
+        val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK;
+        val |= U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI;
+        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
+}
diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h
new file mode 100644
index 000000000000..8c2099ac5046
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.h
@@ -0,0 +1,19 @@
+/*
+ *
+ * arch/arm/mach-u300/padmux.h
+ *
+ *
+ * Copyright (C) 2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * U300 PADMUX API
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ *
+ */
+#ifndef __MACH_U300_PADMUX_H
+#define __MACH_U300_PADMUX_H
+void pmx_set_mission_mode_mmc(void);
+void pmx_set_mission_mode_spi(void);
+#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
new file mode 100644
index 000000000000..cce53204880e
--- /dev/null
+++ b/arch/arm/mach-u300/timer.c
@@ -0,0 +1,422 @@
+/*
+ *
+ * arch/arm/mach-u300/timer.c
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Timer COH 901 328, runs the OS timer interrupt.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+/* Generic stuff */
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+#include "clock.h"
+/*
+ * APP side special timer registers
+ * This timer contains four timers which can fire an interrupt each.
+ * OS (operating system) timer @ 32768 Hz
+ * DD (device driver) timer @ 1 kHz
+ * GP1 (general purpose 1) timer @ 1MHz
+ * GP2 (general purpose 2) timer @ 1MHz
+ */
+/* Reset OS Timer 32bit (-/W) */
+#define U300_TIMER_APP_ROST                                     (0x0000)
+#define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
+/* Enable OS Timer 32bit (-/W) */
+#define U300_TIMER_APP_EOST                                     (0x0004)
+#define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
+/* Disable OS Timer 32bit (-/W) */
+#define U300_TIMER_APP_DOST                                     (0x0008)
+#define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
+/* OS Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SOSTM                                    (0x000c)
+#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
+/* OS Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_OSTS                                     (0x0010)
+#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
+#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
+#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
+#define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
+#define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
+#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
+#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
+#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
+#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
+/* OS Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_OSTCC                                    (0x0014)
+/* OS Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_OSTTC                                    (0x0018)
+/* OS Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_OSTIE                                    (0x001c)
+#define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
+#define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
+/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_OSTIA                                    (0x0020)
+#define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
+/* Reset DD Timer 32bit (-/W) */
+#define U300_TIMER_APP_RDDT                                     (0x0040)
+#define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
+/* Enable DD Timer 32bit (-/W) */
+#define U300_TIMER_APP_EDDT                                     (0x0044)
+#define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
+/* Disable DD Timer 32bit (-/W) */
+#define U300_TIMER_APP_DDDT                                     (0x0048)
+#define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
+/* DD Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SDDTM                                    (0x004c)
+#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
+/* DD Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_DDTS                                     (0x0050)
+#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
+#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
+#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
+#define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
+#define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
+#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
+#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
+#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
+#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
+/* DD Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_DDTCC                                    (0x0054)
+/* DD Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_DDTTC                                    (0x0058)
+/* DD Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_DDTIE                                    (0x005c)
+#define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
+#define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
+/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_DDTIA                                    (0x0060)
+#define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
+/* Reset GP1 Timer 32bit (-/W) */
+#define U300_TIMER_APP_RGPT1                                    (0x0080)
+#define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
+/* Enable GP1 Timer 32bit (-/W) */
+#define U300_TIMER_APP_EGPT1                                    (0x0084)
+#define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
+/* Disable GP1 Timer 32bit (-/W) */
+#define U300_TIMER_APP_DGPT1                                    (0x0088)
+#define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
+/* GP1 Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SGPT1M                                   (0x008c)
+#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
+#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
+/* GP1 Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT1S                                    (0x0090)
+#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
+#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
+#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
+#define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
+#define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
+#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
+#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
+#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
+/* GP1 Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT1CC                                   (0x0094)
+/* GP1 Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_GPT1TC                                   (0x0098)
+/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT1IE                                   (0x009c)
+#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
+#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
+/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT1IA                                   (0x00a0)
+#define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
+/* Reset GP2 Timer 32bit (-/W) */
+#define U300_TIMER_APP_RGPT2                                    (0x00c0)
+#define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
+/* Enable GP2 Timer 32bit (-/W) */
+#define U300_TIMER_APP_EGPT2                                    (0x00c4)
+#define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
+/* Disable GP2 Timer 32bit (-/W) */
+#define U300_TIMER_APP_DGPT2                                    (0x00c8)
+#define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
+/* GP2 Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SGPT2M                                   (0x00cc)
+#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
+#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
+/* GP2 Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT2S                                    (0x00d0)
+#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
+#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
+#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
+#define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
+#define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
+#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
+#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
+#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
+/* GP2 Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT2CC                                   (0x00d4)
+/* GP2 Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_GPT2TC                                   (0x00d8)
+/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT2IE                                   (0x00dc)
+#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
+#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
+/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT2IA                                   (0x00e0)
+#define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
+/* Clock request control register - all four timers */
+#define U300_TIMER_APP_CRC                                      (0x100)
+#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
+#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
+#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
+/*
+ * The u300_set_mode() function is always called first, if we
+ * have oneshot timer active, the oneshot scheduling function
+ * u300_set_next_event() is called immediately after.
+ */
+static void u300_set_mode(enum clock_event_mode mode,
+                          struct clock_event_device *evt)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* Disable interrupts on GPT1 */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                /* Disable GP1 while we're reprogramming it. */
+                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                /*
+                 * Set the periodic mode to a certain number of ticks per
+                 * jiffy.
+                 */
+                writel(TICKS_PER_JIFFY,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                /*
+                 * Set continuous mode, so the timer keeps triggering
+                 * interrupts.
+                 */
+                writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                /* Enable timer interrupts */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                /* Then enable the OS timer again */
+                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* Just break; here? */
+                /*
+                 * The actual event will be programmed by the next event hook,
+                 * so we just set a dummy value somewhere at the end of the
+                 * universe here.
+                 */
+                /* Disable interrupts on GPT1 */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                /* Disable GP1 while we're reprogramming it. */
+                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                /*
+                 * Expire far in the future, u300_set_next_event() will be
+                 * called soon...
+                 */
+                writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                /* We run one shot per tick here! */
+                writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                /* Enable interrupts for this timer */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                /* Enable timer */
+                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                /* Disable interrupts on GP1 */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                /* Disable GP1 */
+                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                /* Ignore this call */
+                break;
+        }
+}
+/*
+ * The app timer in one shot mode obviously has to be reprogrammed
+ * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
+ * the interrupt disable + timer disable commands with a reset command,
+ * it will fail miserably. Apparently (and I found this the hard way)
+ * the timer is very sensitive to the instruction order, though you don't
+ * get that impression from the data sheet.
+ */
+static int u300_set_next_event(unsigned long cycles,
+                               struct clock_event_device *evt)
+{
+        /* Disable interrupts on GPT1 */
+        writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+        /* Disable GP1 while we're reprogramming it. */
+        writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+               U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+        /* Reset the General Purpose timer 1. */
+        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
+               U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+        /* IRQ in n * cycles */
+        writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+        /*
+         * We run one shot per tick here! (This is necessary to reconfigure,
+         * the timer will tilt if you don't!)
+         */
+        writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
+               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+        /* Enable timer interrupts */
+        writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
+               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+        /* Then enable the OS timer again */
+        writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
+               U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+        return 0;
+}
+/* Use general purpose timer 1 as clock event */
+static struct clock_event_device clockevent_u300_1mhz = {
+        .name           = "GPT1",
+        .rating         = 300, /* Reasonably fast and accurate clock event */
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
+        .shift          = 22,
+        .set_next_event = u300_set_next_event,
+        .set_mode       = u300_set_mode,
+};
+/* Clock event timer interrupt handler */
+static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &clockevent_u300_1mhz;
+        /* ACK/Clear timer IRQ for the APP GPT1 Timer */
+        writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+static struct irqaction u300_timer_irq = {
+        .name           = "U300 Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = u300_timer_interrupt,
+};
+/* Use general purpose timer 2 as clock source */
+static cycle_t u300_get_cycles(struct clocksource *cs)
+{
+        return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+}
+static struct clocksource clocksource_u300_1mhz = {
+        .name           = "GPT2",
+        .rating         = 300, /* Reasonably fast and accurate clock source */
+        .read           = u300_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32), /* 32 bits */
+        /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
+        .shift          = 22,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+/*
+ * This sets up the system timers, clock source and clock event.
+ */
+static void __init u300_timer_init(void)
+{
+        u300_enable_timer_clock();
+        /*
+         * Disable the "OS" and "DD" timers - these are designed for Symbian!
+         * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
+         */
+        writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
+        writel(U300_TIMER_APP_ROST_TIMER_RESET,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
+        writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
+        writel(U300_TIMER_APP_RDDT_TIMER_RESET,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
+        writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
+        /* Reset the General Purpose timer 1. */
+        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+        /* Set up the IRQ handler */
+        setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
+        /* Reset the General Purpose timer 2 */
+        writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
+        /* Set this timer to run around forever */
+        writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
+        /* Set continuous mode so it wraps around */
+        writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
+               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
+        /* Disable timer interrupts */
+        writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
+        /* Then enable the GP2 timer to use as a free running us counter */
+        writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
+                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
+        /* This is a pure microsecond clock source */
+        clocksource_u300_1mhz.mult =
+                clocksource_khz2mult(1000, clocksource_u300_1mhz.shift);
+        if (clocksource_register(&clocksource_u300_1mhz))
+                printk(KERN_ERR "timer: failed to initialize clock "
+                       "source %s\n", clocksource_u300_1mhz.name);
+        clockevent_u300_1mhz.mult =
+                div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift);
+        /* 32bit counter, so 32bits delta is max */
+        clockevent_u300_1mhz.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
+        /* This timer is slow enough to set for 1 cycle == 1 MHz */
+        clockevent_u300_1mhz.min_delta_ns =
+                clockevent_delta2ns(1, &clockevent_u300_1mhz);
+        clockevent_u300_1mhz.cpumask = cpumask_of(0);
+        clockevents_register_device(&clockevent_u300_1mhz);
+        /*
+         * TODO: init and register the rest of the timers too, they can be
+         * used by hrtimers!
+         */
+}
+/*
+ * Very simple system timer that only register the clock event and
+ * clock source.
+ */
+struct sys_timer u300_timer = {
+        .init           = u300_timer_init,
+};
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
new file mode 100644
index 000000000000..d2a0b8847a18
--- /dev/null
+++ b/arch/arm/mach-u300/u300.c
@@ -0,0 +1,55 @@
+/*
+ *
+ * arch/arm/mach-u300/u300.c
+ *
+ *
+ * Copyright (C) 2006-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Platform machine definition.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include <mach/memory.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+static void __init u300_init_machine(void)
+{
+        u300_init_devices();
+}
+#ifdef CONFIG_MACH_U300_BS2X
+#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
+#endif
+#ifdef CONFIG_MACH_U300_BS330
+#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
+#endif
+#ifdef CONFIG_MACH_U300_BS335
+#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
+#endif
+#ifdef CONFIG_MACH_U300_BS365
+#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
+#endif
+MACHINE_START(U300, MACH_U300_STRING)
+        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
+        .phys_io        = U300_AHB_PER_PHYS_BASE,
+        .io_pg_offst    = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = BOOT_PARAMS_OFFSET,
+        .map_io         = u300_map_io,
+        .init_irq       = u300_init_irq,
+        .timer          = &u300_timer,
+        .init_machine   = u300_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index b3bebcc5623b..69214fc8bd19 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -116,7 +116,7 @@ void __init versatile_init_irq(void)
 {
        unsigned int i;
-        vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
+        vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
        set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
diff --git a/arch/arm/mach-w90x900/Makefile b/arch/arm/mach-w90x900/Makefile
index 0c0c1d63f1c7..d50c94f4dbdf 100644
--- a/arch/arm/mach-w90x900/Makefile
+++ b/arch/arm/mach-w90x900/Makefile
@@ -4,7 +4,7 @@
 # Object file lists.
-obj-y                           := irq.o time.o
+obj-y                           := irq.o time.o mfp-w90p910.o gpio.o clock.o
 # W90X900 CPU support files
diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
new file mode 100644
index 000000000000..f420613cd395
--- /dev/null
+++ b/arch/arm/mach-w90x900/clock.c
@@ -0,0 +1,77 @@
+/*
+ * linux/arch/arm/mach-w90x900/clock.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include "clock.h"
+static DEFINE_SPINLOCK(clocks_lock);
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (clk->enabled++ == 0)
+                (clk->enable)(clk, 1);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+        WARN_ON(clk->enabled == 0);
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (--clk->enabled == 0)
+                (clk->enable)(clk, 0);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+void w90x900_clk_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->cken;
+        unsigned long clken;
+        clken = __raw_readl(W90X900_VA_CLKPWR);
+        if (enable)
+                clken |= clocks;
+        else
+                clken &= ~clocks;
+        __raw_writel(clken, W90X900_VA_CLKPWR);
+}
+void clks_register(struct clk_lookup *clks, size_t num)
+{
+        int i;
+        for (i = 0; i < num; i++)
+                clkdev_add(&clks[i]);
+}
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h
new file mode 100644
index 000000000000..4f27bda76d56
--- /dev/null
+++ b/arch/arm/mach-w90x900/clock.h
@@ -0,0 +1,36 @@
+/*
+ * linux/arch/arm/mach-w90x900/clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+#include <asm/clkdev.h>
+void w90x900_clk_enable(struct clk *clk, int enable);
+void clks_register(struct clk_lookup *clks, size_t num);
+struct clk {
+        unsigned long           cken;
+        unsigned int            enabled;
+        void                    (*enable)(struct clk *, int enable);
+};
+#define DEFINE_CLK(_name, _ctrlbit)                     \
+struct clk clk_##_name = {                              \
+                .enable = w90x900_clk_enable,           \
+                .cken   = (1 << _ctrlbit),              \
+        }
+#define DEF_CLKLOOK(_clk, _devname, _conname)           \
+        {                                               \
+                .clk            = _clk,                 \
+                .dev_id         = _devname,             \
+                .con_id         = _conname,             \
+        }
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h
index de29ddcb9459..57b5dbabeb41 100644
--- a/arch/arm/mach-w90x900/cpu.h
+++ b/arch/arm/mach-w90x900/cpu.h
@@ -41,7 +41,7 @@ struct sys_timer;
 extern void w90x900_init_irq(void);
 extern void w90p910_init_io(struct map_desc *mach_desc, int size);
 extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no);
-extern void w90p910_init_clocks(int xtal);
+extern void w90p910_init_clocks(void);
 extern void w90p910_map_io(struct map_desc *mach_desc, int size);
 extern struct platform_device w90p910_serial_device;
 extern struct sys_timer w90x900_timer;
diff --git a/arch/arm/mach-w90x900/gpio.c b/arch/arm/mach-w90x900/gpio.c
new file mode 100644
index 000000000000..c72e0dfa1825
--- /dev/null
+++ b/arch/arm/mach-w90x900/gpio.c
@@ -0,0 +1,154 @@
+/*
+ * linux/arch/arm/mach-w90p910/gpio.c
+ *
+ * Generic w90p910 GPIO handling
+ *
+ *  Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#define GPIO_BASE               (W90X900_VA_GPIO)
+#define GPIO_DIR                (0x04)
+#define GPIO_OUT                (0x08)
+#define GPIO_IN                 (0x0C)
+#define GROUPINERV              (0x10)
+#define GPIO_GPIO(Nb)           (0x00000001 << (Nb))
+#define to_w90p910_gpio_chip(c) container_of(c, struct w90p910_gpio_chip, chip)
+#define W90P910_GPIO_CHIP(name, base_gpio, nr_gpio)                     \
+        {                                                               \
+                .chip = {                                               \
+                        .label            = name,                       \
+                        .direction_input  = w90p910_dir_input,          \
+                        .direction_output = w90p910_dir_output,         \
+                        .get              = w90p910_gpio_get,           \
+                        .set              = w90p910_gpio_set,           \
+                        .base             = base_gpio,                  \
+                        .ngpio            = nr_gpio,                    \
+                }                                                       \
+        }
+struct w90p910_gpio_chip {
+        struct gpio_chip        chip;
+        void __iomem            *regbase;       /* Base of group register*/
+        spinlock_t              gpio_lock;
+};
+static int w90p910_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        void __iomem *pio = w90p910_gpio->regbase + GPIO_IN;
+        unsigned int regval;
+        regval = __raw_readl(pio);
+        regval &= GPIO_GPIO(offset);
+        return (regval != 0);
+}
+static void w90p910_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        void __iomem *pio = w90p910_gpio->regbase + GPIO_OUT;
+        unsigned int regval;
+        unsigned long flags;
+        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        regval = __raw_readl(pio);
+        if (val)
+                regval |= GPIO_GPIO(offset);
+        else
+                regval &= ~GPIO_GPIO(offset);
+        __raw_writel(regval, pio);
+        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+}
+static int w90p910_dir_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR;
+        unsigned int regval;
+        unsigned long flags;
+        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        regval = __raw_readl(pio);
+        regval &= ~GPIO_GPIO(offset);
+        __raw_writel(regval, pio);
+        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        return 0;
+}
+static int w90p910_dir_output(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        void __iomem *outreg = w90p910_gpio->regbase + GPIO_OUT;
+        void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR;
+        unsigned int regval;
+        unsigned long flags;
+        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        regval = __raw_readl(pio);
+        regval |= GPIO_GPIO(offset);
+        __raw_writel(regval, pio);
+        regval = __raw_readl(outreg);
+        if (val)
+                regval |= GPIO_GPIO(offset);
+        else
+                regval &= ~GPIO_GPIO(offset);
+        __raw_writel(regval, outreg);
+        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        return 0;
+}
+static struct w90p910_gpio_chip w90p910_gpio[] = {
+        W90P910_GPIO_CHIP("GROUPC", 0, 16),
+        W90P910_GPIO_CHIP("GROUPD", 16, 10),
+        W90P910_GPIO_CHIP("GROUPE", 26, 14),
+        W90P910_GPIO_CHIP("GROUPF", 40, 10),
+        W90P910_GPIO_CHIP("GROUPG", 50, 17),
+        W90P910_GPIO_CHIP("GROUPH", 67, 8),
+        W90P910_GPIO_CHIP("GROUPI", 75, 17),
+};
+void __init w90p910_init_gpio(int nr_group)
+{
+        unsigned        i;
+        struct w90p910_gpio_chip *gpio_chip;
+        for (i = 0; i < nr_group; i++) {
+                gpio_chip = &w90p910_gpio[i];
+                spin_lock_init(&gpio_chip->gpio_lock);
+                gpio_chip->regbase = GPIO_BASE + i * GROUPINERV;
+                gpiochip_add(&gpio_chip->chip);
+        }
+}
diff --git a/arch/arm/mach-w90x900/include/mach/clkdev.h b/arch/arm/mach-w90x900/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
diff --git a/arch/arm/mach-w90x900/include/mach/gpio.h b/arch/arm/mach-w90x900/include/mach/gpio.h
new file mode 100644
index 000000000000..034da3e390c9
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * linux/arch/arm/mach-w90p910/include/mach/gpio.h
+ *
+ * Generic w90p910 GPIO handling
+ *
+ *  Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_W90P910_GPIO_H
+#define __ASM_ARCH_W90P910_GPIO_H
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm-generic/gpio.h>
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return gpio;
+}
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq;
+}
+#endif
diff --git a/arch/arm/mach-w90x900/include/mach/irqs.h b/arch/arm/mach-w90x900/include/mach/irqs.h
index 1c583f9cbcde..9d5cba3a509f 100644
--- a/arch/arm/mach-w90x900/include/mach/irqs.h
+++ b/arch/arm/mach-w90x900/include/mach/irqs.h
@@ -1,8 +1,7 @@
 /*
 * arch/arm/mach-w90x900/include/mach/irqs.h
 *
- * Copyright (c) 2008 Nuvoton technology corporation
+ * Copyright (c) 2008 Nuvoton technology corporation.
- * All rights reserved.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
@@ -10,8 +9,7 @@
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation;version 2 of the License.
- * (at your option) any later version.
 *
 */
@@ -31,6 +29,11 @@
 /* Main cpu interrupts */
 #define IRQ_WDT         W90X900_IRQ(1)
+#define IRQ_GROUP0      W90X900_IRQ(2)
+#define IRQ_GROUP1      W90X900_IRQ(3)
+#define IRQ_ACTL        W90X900_IRQ(4)
+#define IRQ_LCD         W90X900_IRQ(5)
+#define IRQ_RTC         W90X900_IRQ(6)
 #define IRQ_UART0       W90X900_IRQ(7)
 #define IRQ_UART1       W90X900_IRQ(8)
 #define IRQ_UART2       W90X900_IRQ(9)
@@ -39,7 +42,45 @@
 #define IRQ_TIMER0      W90X900_IRQ(12)
 #define IRQ_TIMER1      W90X900_IRQ(13)
 #define IRQ_T_INT_GROUP W90X900_IRQ(14)
+#define IRQ_USBH        W90X900_IRQ(15)
+#define IRQ_EMCTX       W90X900_IRQ(16)
+#define IRQ_EMCRX       W90X900_IRQ(17)
+#define IRQ_GDMAGROUP   W90X900_IRQ(18)
+#define IRQ_DMAC        W90X900_IRQ(19)
+#define IRQ_FMI         W90X900_IRQ(20)
+#define IRQ_USBD        W90X900_IRQ(21)
+#define IRQ_ATAPI       W90X900_IRQ(22)
+#define IRQ_G2D         W90X900_IRQ(23)
+#define IRQ_PCI         W90X900_IRQ(24)
+#define IRQ_SCGROUP     W90X900_IRQ(25)
+#define IRQ_I2CGROUP    W90X900_IRQ(26)
+#define IRQ_SSP         W90X900_IRQ(27)
+#define IRQ_PWM         W90X900_IRQ(28)
+#define IRQ_KPI         W90X900_IRQ(29)
+#define IRQ_P2SGROUP    W90X900_IRQ(30)
 #define IRQ_ADC         W90X900_IRQ(31)
 #define NR_IRQS         (IRQ_ADC+1)
+/*for irq group*/
+#define IRQ_PS2_PORT0   0x10000000
+#define IRQ_PS2_PORT1   0x20000000
+#define IRQ_I2C_LINE0   0x04000000
+#define IRQ_I2C_LINE1   0x08000000
+#define IRQ_SC_CARD0    0x01000000
+#define IRQ_SC_CARD1    0x02000000
+#define IRQ_GDMA_CH0    0x00100000
+#define IRQ_GDMA_CH1    0x00200000
+#define IRQ_TIMER2      0x00010000
+#define IRQ_TIMER3      0x00020000
+#define IRQ_TIMER4      0x00040000
+#define IRQ_GROUP0_IRQ0 0x00000001
+#define IRQ_GROUP0_IRQ1 0x00000002
+#define IRQ_GROUP0_IRQ2 0x00000004
+#define IRQ_GROUP0_IRQ3 0x00000008
+#define IRQ_GROUP1_IRQ4 0x00000010
+#define IRQ_GROUP1_IRQ5 0x00000020
+#define IRQ_GROUP1_IRQ6 0x00000040
+#define IRQ_GROUP1_IRQ7 0x00000080
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-w90x900/include/mach/map.h b/arch/arm/mach-w90x900/include/mach/map.h
index 79320ebe614b..1a2095304117 100644
--- a/arch/arm/mach-w90x900/include/mach/map.h
+++ b/arch/arm/mach-w90x900/include/mach/map.h
@@ -1,8 +1,7 @@
 /*
 * arch/arm/mach-w90x900/include/mach/map.h
 *
- * Copyright (c) 2008 Nuvoton technology corporation
+ * Copyright (c) 2008 Nuvoton technology corporation.
- * All rights reserved.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
@@ -10,8 +9,7 @@
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation;version 2 of the License.
- * (at your option) any later version.
 *
 */
@@ -34,7 +32,6 @@
 * interrupt controller is the first thing we put in, to make
 * the assembly code for the irq detection easier
 */
 #define W90X900_VA_IRQ          W90X900_ADDR(0x00000000)
 #define W90X900_PA_IRQ          (0xB8002000)
 #define W90X900_SZ_IRQ          SZ_4K
@@ -44,33 +41,117 @@
 #define W90X900_SZ_GCR          SZ_4K
 /* Clock and Power management */
 #define W90X900_VA_CLKPWR       (W90X900_VA_GCR+0x200)
 #define W90X900_PA_CLKPWR       (0xB0000200)
 #define W90X900_SZ_CLKPWR       SZ_4K
 /* EBI management */
 #define W90X900_VA_EBI          W90X900_ADDR(0x00001000)
 #define W90X900_PA_EBI          (0xB0001000)
 #define W90X900_SZ_EBI          SZ_4K
 /* UARTs */
 #define W90X900_VA_UART         W90X900_ADDR(0x08000000)
 #define W90X900_PA_UART         (0xB8000000)
 #define W90X900_SZ_UART         SZ_4K
 /* Timers */
 #define W90X900_VA_TIMER        W90X900_ADDR(0x08001000)
 #define W90X900_PA_TIMER        (0xB8001000)
 #define W90X900_SZ_TIMER        SZ_4K
 /* GPIO ports */
 #define W90X900_VA_GPIO         W90X900_ADDR(0x08003000)
 #define W90X900_PA_GPIO         (0xB8003000)
 #define W90X900_SZ_GPIO         SZ_4K
+/* GDMA control */
+#define W90X900_VA_GDMA         W90X900_ADDR(0x00004000)
+#define W90X900_PA_GDMA         (0xB0004000)
+#define W90X900_SZ_GDMA         SZ_4K
+/* USB host controller*/
+#define W90X900_VA_USBEHCIHOST  W90X900_ADDR(0x00005000)
+#define W90X900_PA_USBEHCIHOST  (0xB0005000)
+#define W90X900_SZ_USBEHCIHOST  SZ_4K
+#define W90X900_VA_USBOHCIHOST  W90X900_ADDR(0x00007000)
+#define W90X900_PA_USBOHCIHOST  (0xB0007000)
+#define W90X900_SZ_USBOHCIHOST  SZ_4K
+/* I2C hardware controller */
+#define W90X900_VA_I2C          W90X900_ADDR(0x08006000)
+#define W90X900_PA_I2C          (0xB8006000)
+#define W90X900_SZ_I2C          SZ_4K
+/* Keypad Interface*/
+#define W90X900_VA_KPI          W90X900_ADDR(0x08008000)
+#define W90X900_PA_KPI          (0xB8008000)
+#define W90X900_SZ_KPI          SZ_4K
+/* Smart card host*/
+#define W90X900_VA_SC           W90X900_ADDR(0x08005000)
+#define W90X900_PA_SC           (0xB8005000)
+#define W90X900_SZ_SC           SZ_4K
+/* LCD controller*/
+#define W90X900_VA_LCD          W90X900_ADDR(0x00008000)
+#define W90X900_PA_LCD          (0xB0008000)
+#define W90X900_SZ_LCD          SZ_4K
+/* 2D controller*/
+#define W90X900_VA_GE           W90X900_ADDR(0x0000B000)
+#define W90X900_PA_GE           (0xB000B000)
+#define W90X900_SZ_GE           SZ_4K
+/* ATAPI */
+#define W90X900_VA_ATAPI        W90X900_ADDR(0x0000A000)
+#define W90X900_PA_ATAPI        (0xB000A000)
+#define W90X900_SZ_ATAPI        SZ_4K
+/* ADC */
+#define W90X900_VA_ADC          W90X900_ADDR(0x0800A000)
+#define W90X900_PA_ADC          (0xB800A000)
+#define W90X900_SZ_ADC          SZ_4K
+/* PS2 Interface*/
+#define W90X900_VA_PS2          W90X900_ADDR(0x08009000)
+#define W90X900_PA_PS2          (0xB8009000)
+#define W90X900_SZ_PS2          SZ_4K
+/* RTC */
+#define W90X900_VA_RTC          W90X900_ADDR(0x08004000)
+#define W90X900_PA_RTC          (0xB8004000)
+#define W90X900_SZ_RTC          SZ_4K
+/* Pulse Width Modulation(PWM) Registers */
+#define W90X900_VA_PWM          W90X900_ADDR(0x08007000)
+#define W90X900_PA_PWM          (0xB8007000)
+#define W90X900_SZ_PWM          SZ_4K
+/* Audio Controller controller */
+#define W90X900_VA_ACTL         W90X900_ADDR(0x00009000)
+#define W90X900_PA_ACTL         (0xB0009000)
+#define W90X900_SZ_ACTL         SZ_4K
+/* DMA controller */
+#define W90X900_VA_DMA          W90X900_ADDR(0x0000c000)
+#define W90X900_PA_DMA          (0xB000c000)
+#define W90X900_SZ_DMA          SZ_4K
+/* FMI controller */
+#define W90X900_VA_FMI          W90X900_ADDR(0x0000d000)
+#define W90X900_PA_FMI          (0xB000d000)
+#define W90X900_SZ_FMI          SZ_4K
+/* USB Device port */
+#define W90X900_VA_USBDEV       W90X900_ADDR(0x00006000)
+#define W90X900_PA_USBDEV       (0xB0006000)
+#define W90X900_SZ_USBDEV       SZ_4K
+/* External MAC control*/
+#define W90X900_VA_EMC          W90X900_ADDR(0x00003000)
+#define W90X900_PA_EMC          (0xB0003000)
+#define W90X900_SZ_EMC          SZ_4K
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-w90x900/include/mach/regs-clock.h b/arch/arm/mach-w90x900/include/mach/regs-clock.h
new file mode 100644
index 000000000000..f10b6a8dc069
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-clock.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H
+/* Clock Control Registers  */
+#define CLK_BA          W90X900_VA_CLKPWR
+#define REG_CLKEN       (CLK_BA + 0x00)
+#define REG_CLKSEL      (CLK_BA + 0x04)
+#define REG_CLKDIV      (CLK_BA + 0x08)
+#define REG_PLLCON0     (CLK_BA + 0x0C)
+#define REG_PLLCON1     (CLK_BA + 0x10)
+#define REG_PMCON       (CLK_BA + 0x14)
+#define REG_IRQWAKECON  (CLK_BA + 0x18)
+#define REG_IRQWAKEFLAG (CLK_BA + 0x1C)
+#define REG_IPSRST      (CLK_BA + 0x20)
+#define REG_CLKEN1      (CLK_BA + 0x24)
+#define REG_CLKDIV1     (CLK_BA + 0x28)
+#endif /*  __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-w90x900/include/mach/regs-usb.h b/arch/arm/mach-w90x900/include/mach/regs-usb.h
new file mode 100644
index 000000000000..ab74b0c2480b
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-usb.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/regs-usb.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+#ifndef __ASM_ARCH_REGS_USB_H
+#define __ASM_ARCH_REGS_USB_H
+/* usb Control Registers  */
+#define USBH_BA         W90X900_VA_USBEHCIHOST
+#define USBD_BA         W90X900_VA_USBDEV
+#define USBO_BA         W90X900_VA_USBOHCIHOST
+/* USB Host Control Registers */
+#define REG_UPSCR0      (USBH_BA+0x064)
+#define REG_UPSCR1      (USBH_BA+0x068)
+#define REG_USBPCR0     (USBH_BA+0x0C4)
+#define REG_USBPCR1     (USBH_BA+0x0C8)
+/* USBH OHCI Control Registers */
+#define REG_OpModEn     (USBO_BA+0x204)
+/*This bit controls the polarity of over
+*current flag from external power IC.
+*/
+#define OCALow          0x08
+#endif /*  __ASM_ARCH_REGS_USB_H */
diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c
index 726ff6798a56..7a62bd348e80 100644
--- a/arch/arm/mach-w90x900/mach-w90p910evb.c
+++ b/arch/arm/mach-w90x900/mach-w90p910evb.c
@@ -3,15 +3,13 @@
 *
 * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
 *
- * Copyright (C) 2008 Nuvoton technology corporation
+ * Copyright (C) 2008 Nuvoton technology corporation.
- * All rights reserved.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
+ * published by the Free Software Foundation;version 2 of the License.
- * the License, or (at your option) any later version.
 *
 */
@@ -80,6 +78,156 @@ static struct platform_device w90p910_flash_device = {
        .num_resources  =       ARRAY_SIZE(w90p910_flash_resources),
 };
+/* USB EHCI Host Controller */
+static struct resource w90x900_usb_ehci_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBEHCIHOST,
+                .end   = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 w90x900_device_usb_ehci_dmamask = 0xffffffffUL;
+struct platform_device w90x900_device_usb_ehci = {
+        .name             = "w90x900-ehci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(w90x900_usb_ehci_resource),
+        .resource         = w90x900_usb_ehci_resource,
+        .dev              = {
+                .dma_mask = &w90x900_device_usb_ehci_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+EXPORT_SYMBOL(w90x900_device_usb_ehci);
+/* USB OHCI Host Controller */
+static struct resource w90x900_usb_ohci_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBOHCIHOST,
+                .end   = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 w90x900_device_usb_ohci_dmamask = 0xffffffffUL;
+struct platform_device w90x900_device_usb_ohci = {
+        .name             = "w90x900-ohci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(w90x900_usb_ohci_resource),
+        .resource         = w90x900_usb_ohci_resource,
+        .dev              = {
+                .dma_mask = &w90x900_device_usb_ohci_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+EXPORT_SYMBOL(w90x900_device_usb_ohci);
+/*TouchScreen controller*/
+static struct resource w90x900_ts_resource[] = {
+        [0] = {
+                .start = W90X900_PA_ADC,
+                .end   = W90X900_PA_ADC + W90X900_SZ_ADC-1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_ADC,
+                .end   = IRQ_ADC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device w90x900_device_ts = {
+        .name           = "w90x900-ts",
+        .id             = -1,
+        .resource       = w90x900_ts_resource,
+        .num_resources  = ARRAY_SIZE(w90x900_ts_resource),
+};
+EXPORT_SYMBOL(w90x900_device_ts);
+/* RTC controller*/
+static struct resource w90x900_rtc_resource[] = {
+        [0] = {
+                .start = W90X900_PA_RTC,
+                .end   = W90X900_PA_RTC + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_RTC,
+                .end   = IRQ_RTC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device w90x900_device_rtc = {
+        .name           = "w90x900-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(w90x900_rtc_resource),
+        .resource       = w90x900_rtc_resource,
+};
+EXPORT_SYMBOL(w90x900_device_rtc);
+/* KPI controller*/
+static struct resource w90x900_kpi_resource[] = {
+        [0] = {
+                .start = W90X900_PA_KPI,
+                .end   = W90X900_PA_KPI + W90X900_SZ_KPI - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_KPI,
+                .end   = IRQ_KPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+struct platform_device w90x900_device_kpi = {
+        .name           = "w90x900-kpi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(w90x900_kpi_resource),
+        .resource       = w90x900_kpi_resource,
+};
+EXPORT_SYMBOL(w90x900_device_kpi);
+/* USB Device (Gadget)*/
+static struct resource w90x900_usbgadget_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBDEV,
+                .end   = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBD,
+                .end   = IRQ_USBD,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+struct platform_device w90x900_device_usbgadget = {
+        .name           = "w90x900-usbgadget",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(w90x900_usbgadget_resource),
+        .resource       = w90x900_usbgadget_resource,
+};
+EXPORT_SYMBOL(w90x900_device_usbgadget);
 static struct map_desc w90p910_iodesc[] __initdata = {
 };
@@ -88,12 +236,18 @@ static struct map_desc w90p910_iodesc[] __initdata = {
 static struct platform_device *w90p910evb_dev[] __initdata = {
        &w90p910_serial_device,
        &w90p910_flash_device,
+        &w90x900_device_usb_ehci,
+        &w90x900_device_usb_ohci,
+        &w90x900_device_ts,
+        &w90x900_device_rtc,
+        &w90x900_device_kpi,
+        &w90x900_device_usbgadget,
 };
 static void __init w90p910evb_map_io(void)
 {
        w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc));
-        w90p910_init_clocks(0);
+        w90p910_init_clocks();
 }
 static void __init w90p910evb_init(void)
diff --git a/arch/arm/mach-w90x900/mfp-w90p910.c b/arch/arm/mach-w90x900/mfp-w90p910.c
new file mode 100644
index 000000000000..a3520fefb5e7
--- /dev/null
+++ b/arch/arm/mach-w90x900/mfp-w90p910.c
@@ -0,0 +1,116 @@
+/*
+ * linux/arch/arm/mach-w90x900/mfp-w90p910.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#define REG_MFSEL       (W90X900_VA_GCR + 0xC)
+#define GPSELF          (0x01 << 1)
+#define GPSELC          (0x03 << 2)
+#define ENKPI           (0x02 << 2)
+#define ENNAND          (0x01 << 2)
+#define GPSELEI0        (0x01 << 26)
+#define GPSELEI1        (0x01 << 27)
+static DECLARE_MUTEX(mfp_sem);
+void mfp_set_groupf(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+        BUG_ON(!dev);
+        down(&mfp_sem);
+        dev_id = dev_name(dev);
+        mfpen = __raw_readl(REG_MFSEL);
+        if (strcmp(dev_id, "w90p910-emc") == 0)
+                mfpen |= GPSELF;/*enable mac*/
+        else
+                mfpen &= ~GPSELF;/*GPIOF[9:0]*/
+        __raw_writel(mfpen, REG_MFSEL);
+        up(&mfp_sem);
+}
+EXPORT_SYMBOL(mfp_set_groupf);
+void mfp_set_groupc(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+        BUG_ON(!dev);
+        down(&mfp_sem);
+        dev_id = dev_name(dev);
+        mfpen = __raw_readl(REG_MFSEL);
+        if (strcmp(dev_id, "w90p910-lcd") == 0)
+                mfpen |= GPSELC;/*enable lcd*/
+        else if (strcmp(dev_id, "w90p910-kpi") == 0) {
+                        mfpen &= (~GPSELC);/*enable kpi*/
+                        mfpen |= ENKPI;
+                } else if (strcmp(dev_id, "w90p910-nand") == 0) {
+                                mfpen &= (~GPSELC);/*enable nand*/
+                                mfpen |= ENNAND;
+                        } else
+                                mfpen &= (~GPSELC);/*GPIOC[14:0]*/
+        __raw_writel(mfpen, REG_MFSEL);
+        up(&mfp_sem);
+}
+EXPORT_SYMBOL(mfp_set_groupc);
+void mfp_set_groupi(struct device *dev, int gpio)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+        BUG_ON(!dev);
+        down(&mfp_sem);
+        dev_id = dev_name(dev);
+        mfpen = __raw_readl(REG_MFSEL);
+        if (strcmp(dev_id, "w90p910-wdog") == 0)
+                mfpen |= GPSELEI1;/*enable wdog*/
+                else if (strcmp(dev_id, "w90p910-atapi") == 0)
+                        mfpen |= GPSELEI0;/*enable atapi*/
+        __raw_writel(mfpen, REG_MFSEL);
+        up(&mfp_sem);
+}
+EXPORT_SYMBOL(mfp_set_groupi);
diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c
index 2bcbaa681b99..1c97e4930b7a 100644
--- a/arch/arm/mach-w90x900/w90p910.c
+++ b/arch/arm/mach-w90x900/w90p910.c
@@ -3,8 +3,7 @@
 *
 * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
 *
- * Copyright (c) 2008 Nuvoton technology corporation
+ * Copyright (c) 2008 Nuvoton technology corporation.
- * All rights reserved.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
@@ -12,8 +11,7 @@
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation;version 2 of the License.
- * (at your option) any later version.
 *
 */
@@ -36,6 +34,7 @@
 #include <mach/regs-serial.h>
 #include "cpu.h"
+#include "clock.h"
 /* Initial IO mappings */
@@ -45,9 +44,52 @@ static struct map_desc w90p910_iodesc[] __initdata = {
        IODESC_ENT(UART),
        IODESC_ENT(TIMER),
        IODESC_ENT(EBI),
+        IODESC_ENT(USBEHCIHOST),
+        IODESC_ENT(USBOHCIHOST),
+        IODESC_ENT(ADC),
+        IODESC_ENT(RTC),
+        IODESC_ENT(KPI),
+        IODESC_ENT(USBDEV),
        /*IODESC_ENT(LCD),*/
 };
+/* Initial clock declarations. */
+static DEFINE_CLK(lcd, 0);
+static DEFINE_CLK(audio, 1);
+static DEFINE_CLK(fmi, 4);
+static DEFINE_CLK(dmac, 5);
+static DEFINE_CLK(atapi, 6);
+static DEFINE_CLK(emc, 7);
+static DEFINE_CLK(usbd, 8);
+static DEFINE_CLK(usbh, 9);
+static DEFINE_CLK(g2d, 10);;
+static DEFINE_CLK(pwm, 18);
+static DEFINE_CLK(ps2, 24);
+static DEFINE_CLK(kpi, 25);
+static DEFINE_CLK(wdt, 26);
+static DEFINE_CLK(gdma, 27);
+static DEFINE_CLK(adc, 28);
+static DEFINE_CLK(usi, 29);
+static struct clk_lookup w90p910_clkregs[] = {
+        DEF_CLKLOOK(&clk_lcd, "w90p910-lcd", NULL),
+        DEF_CLKLOOK(&clk_audio, "w90p910-audio", NULL),
+        DEF_CLKLOOK(&clk_fmi, "w90p910-fmi", NULL),
+        DEF_CLKLOOK(&clk_dmac, "w90p910-dmac", NULL),
+        DEF_CLKLOOK(&clk_atapi, "w90p910-atapi", NULL),
+        DEF_CLKLOOK(&clk_emc, "w90p910-emc", NULL),
+        DEF_CLKLOOK(&clk_usbd, "w90p910-usbd", NULL),
+        DEF_CLKLOOK(&clk_usbh, "w90p910-usbh", NULL),
+        DEF_CLKLOOK(&clk_g2d, "w90p910-g2d", NULL),
+        DEF_CLKLOOK(&clk_pwm, "w90p910-pwm", NULL),
+        DEF_CLKLOOK(&clk_ps2, "w90p910-ps2", NULL),
+        DEF_CLKLOOK(&clk_kpi, "w90p910-kpi", NULL),
+        DEF_CLKLOOK(&clk_wdt, "w90p910-wdt", NULL),
+        DEF_CLKLOOK(&clk_gdma, "w90p910-gdma", NULL),
+        DEF_CLKLOOK(&clk_adc, "w90p910-adc", NULL),
+        DEF_CLKLOOK(&clk_usi, "w90p910-usi", NULL),
+};
 /* Initial serial platform data */
 struct plat_serial8250_port w90p910_uart_data[] = {
@@ -77,8 +119,9 @@ void __init w90p910_map_io(struct map_desc *mach_desc, int mach_size)
 /*Init W90P910 clock*/
-void __init w90p910_init_clocks(int xtal)
+void __init w90p910_init_clocks(void)
 {
+        clks_register(w90p910_clkregs, ARRAY_SIZE(w90p910_clkregs));
 }
 static int __init w90p910_init_cpu(void)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 20979564e7ee..83c025e72ceb 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -391,7 +391,7 @@ config CPU_FEROCEON_OLD_ID
 # ARMv6
 config CPU_V6
-        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
+        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
        select CPU_32v6
        select CPU_ABRT_EV6
        select CPU_PABRT_NOIFAR
@@ -416,7 +416,7 @@ config CPU_32v6K
 # ARMv7
 config CPU_V7
-        bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
+        bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
        select CPU_32v6K
        select CPU_32v7
        select CPU_ABRT_EV7
@@ -639,10 +639,23 @@ config CPU_BIG_ENDIAN
          port must properly enable any big-endian related features
          of your chipset/board/processor.
+config CPU_ENDIAN_BE8
+        bool
+        depends on CPU_BIG_ENDIAN
+        default CPU_V6 || CPU_V7
+        help
+          Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
+config CPU_ENDIAN_BE32
+        bool
+        depends on CPU_BIG_ENDIAN
+        default !CPU_ENDIAN_BE8
+        help
+          Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
 config CPU_HIGH_VECTOR
        depends on !MMU && CPU_CP15 && !CPU_ARM740T
        bool "Select the High exception vector"
-        default n
        help
          Say Y here to select high exception vector(0xFFFF0000~).
          The exception vector can be vary depending on the platform
@@ -726,7 +739,6 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 config OUTER_CACHE
        bool
-        default n
 config CACHE_FEROCEON_L2
        bool "Enable the Feroceon L2 cache controller"
@@ -739,7 +751,6 @@ config CACHE_FEROCEON_L2
 config CACHE_FEROCEON_L2_WRITETHROUGH
        bool "Force Feroceon L2 cache write through"
        depends on CACHE_FEROCEON_L2
-        default n
        help
          Say Y here to use the Feroceon L2 cache in writethrough mode.
          Unless you specifically require this, say N for writeback mode.
@@ -747,7 +758,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31
+                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX
        default y
        select OUTER_CACHE
        help
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 6f7e70907e44..f332df7f0d37 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -37,6 +37,9 @@ ENTRY(v6_early_abort)
        movne   pc, lr
        do_thumb_abort
        ldreq   r3, [r2]                        @ read aborted ARM instruction
+#ifdef CONFIG_CPU_ENDIAN_BE8
+        reveq   r3, r3
+#endif
        do_ldrd_abort
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 9f88dd3be601..0ab75c60f7cf 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -110,6 +110,12 @@ static int remap_area_pages(unsigned long start, unsigned long pfn,
        return err;
 }
+int ioremap_page(unsigned long virt, unsigned long phys,
+                 const struct mem_type *mtype)
+{
+        return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype);
+}
+EXPORT_SYMBOL(ioremap_page);
 void __check_kvm_seq(struct mm_struct *mm)
 {
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e6344ece00ce..fdaa9bb87c16 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -255,6 +255,7 @@ const struct mem_type *get_mem_type(unsigned int type)
 {
        return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 }
+EXPORT_SYMBOL(get_mem_type);
 /*
 * Adjust the PMD section entries according to the CPU in use.
@@ -839,6 +840,20 @@ void __init reserve_node_zero(pg_data_t *pgdat)
                reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
                                BOOTMEM_EXCLUSIVE);
+        /*
+         * U300 - This platform family can share physical memory
+         * between two ARM cpus, one running Linux and the other
+         * running another OS.
+         */
+        if (machine_is_u300()) {
+#ifdef CONFIG_MACH_U300_SINGLE_RAM
+#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) &&    \
+        CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
+                res_size = 0x00100000;
+#endif
+#endif
+        }
 #ifdef CONFIG_SA1111
        /*
         * Because of the SA1111 DMA bug, we want to preserve our
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 087e239704df..524ddae92595 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -170,6 +170,9 @@ __v6_setup:
 #endif /* CONFIG_MMU */
        adr     r5, v6_crval
        ldmia   r5, {r5, r6}
+#ifdef CONFIG_CPU_ENDIAN_BE8
+        orr     r6, r6, #1 << 25                @ big-endian page tables
+#endif
        mrc     p15, 0, r0, c1, c0, 0           @ read control register
        bic     r0, r0, r5                      @ clear bits them
        orr     r0, r0, r6                      @ set them
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index a08d9d2380d3..180a08d03a03 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,17 +19,23 @@
 #include "proc-macros.S"
-#define TTB_C           (1 << 0)
 #define TTB_S           (1 << 1)
 #define TTB_RGN_NC      (0 << 3)
 #define TTB_RGN_OC_WBWA (1 << 3)
 #define TTB_RGN_OC_WT   (2 << 3)
 #define TTB_RGN_OC_WB   (3 << 3)
+#define TTB_NOS         (1 << 5)
+#define TTB_IRGN_NC     ((0 << 0) | (0 << 6))
+#define TTB_IRGN_WBWA   ((0 << 0) | (1 << 6))
+#define TTB_IRGN_WT     ((1 << 0) | (0 << 6))
+#define TTB_IRGN_WB     ((1 << 0) | (1 << 6))
 #ifndef CONFIG_SMP
-#define TTB_FLAGS       TTB_C|TTB_RGN_OC_WB             @ mark PTWs cacheable, outer WB
+/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
+#define TTB_FLAGS       TTB_IRGN_WB|TTB_RGN_OC_WB
 #else
-#define TTB_FLAGS       TTB_C|TTB_S|TTB_RGN_OC_WBWA     @ mark PTWs cacheable and shared, outer WBWA
+/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
+#define TTB_FLAGS       TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
 #endif
 ENTRY(cpu_v7_proc_init)
@@ -176,8 +182,8 @@ cpu_v7_name:
 */
 __v7_setup:
 #ifdef CONFIG_SMP
-        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
+        mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode and
-        orr     r0, r0, #(0x1 << 6)
+        orr     r0, r0, #(1 << 6) | (1 << 0)    @ TLB ops broadcasting
        mcr     p15, 0, r0, c1, c0, 1
 #endif
        adr     r12, __v7_setup_stack           @ the local stack
@@ -227,12 +233,43 @@ __v7_setup:
        mov     r10, #0x1f                      @ domains 0, 1 = manager
        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 #endif
-        ldr     r5, =0xff0aa1a8
+        /*
-        ldr     r6, =0x40e040e0
+         * Memory region attributes with SCTLR.TRE=1
+         *
+         *   n = TEX[0],C,B
+         *   TR = PRRR[2n+1:2n]         - memory type
+         *   IR = NMRR[2n+1:2n]         - inner cacheable property
+         *   OR = NMRR[2n+17:2n+16]     - outer cacheable property
+         *
+         *                      n       TR      IR      OR
+         *   UNCACHED           000     00
+         *   BUFFERABLE         001     10      00      00
+         *   WRITETHROUGH       010     10      10      10
+         *   WRITEBACK          011     10      11      11
+         *   reserved           110
+         *   WRITEALLOC         111     10      01      01
+         *   DEV_SHARED         100     01
+         *   DEV_NONSHARED      100     01
+         *   DEV_WC             001     10
+         *   DEV_CACHED         011     10
+         *
+         * Other attributes:
+         *
+         *   DS0 = PRRR[16] = 0         - device shareable property
+         *   DS1 = PRRR[17] = 1         - device shareable property
+         *   NS0 = PRRR[18] = 0         - normal shareable property
+         *   NS1 = PRRR[19] = 1         - normal shareable property
+         *   NOS = PRRR[24+n] = 1       - not outer shareable
+         */
+        ldr     r5, =0xff0a81a8                 @ PRRR
+        ldr     r6, =0x40e040e0                 @ NMRR
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
        adr     r5, v7_crval
        ldmia   r5, {r5, r6}
+#ifdef CONFIG_CPU_ENDIAN_BE8
+        orr     r6, r6, #1 << 25                @ big-endian page tables
+#endif
        mrc     p15, 0, r0, c1, c0, 0           @ read control register
        bic     r0, r0, r5                      @ clear bits them
        orr     r0, r0, r6                      @ set them
@@ -240,14 +277,14 @@ __v7_setup:
 ENDPROC(__v7_setup)
        /*   AT
-         *  TFR   EV X F   I D LR
+         *  TFR   EV X F   I D LR    S
-         * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
+         * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
         * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
-         *    1    0 110       0011 1.00 .111 1101 < we want
+         *    1    0 110       0011 1100 .111 1101 < we want
         */
        .type   v7_crval, #object
 v7_crval:
-        crval   clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
+        crval   clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
 __v7_setup_stack:
        .space  4 * 11                          @ 11 registers
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index b637e7380ab7..a26a605b73bd 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -42,9 +42,11 @@ ENTRY(v7wbi_flush_user_tlb_range)
        mov     r1, r1, lsl #PAGE_SHIFT
        vma_vm_flags r2, r2                     @ get vma->vm_flags
 1:
-        mcr     p15, 0, r0, c8, c6, 1           @ TLB invalidate D MVA (was 1)
+#ifdef CONFIG_SMP
-        tst     r2, #VM_EXEC                    @ Executable area ?
+        mcr     p15, 0, r0, c8, c3, 1           @ TLB invalidate U MVA (shareable) 
-        mcrne   p15, 0, r0, c8, c5, 1           @ TLB invalidate I MVA (was 1)
+#else
+        mcr     p15, 0, r0, c8, c7, 1           @ TLB invalidate U MVA
+#endif
        add     r0, r0, #PAGE_SZ
        cmp     r0, r1
        blo     1b
@@ -69,8 +71,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
        mov     r0, r0, lsl #PAGE_SHIFT
        mov     r1, r1, lsl #PAGE_SHIFT
 1:
-        mcr     p15, 0, r0, c8, c6, 1           @ TLB invalidate D MVA
+#ifdef CONFIG_SMP
-        mcr     p15, 0, r0, c8, c5, 1           @ TLB invalidate I MVA
+        mcr     p15, 0, r0, c8, c3, 1           @ TLB invalidate U MVA (shareable)
+#else
+        mcr     p15, 0, r0, c8, c7, 1           @ TLB invalidate U MVA
+#endif
        add     r0, r0, #PAGE_SZ
        cmp     r0, r1
        blo     1b
@@ -87,5 +92,5 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
        .long   v7wbi_flush_user_tlb_range
        .long   v7wbi_flush_kern_tlb_range
-        .long   v6wbi_tlb_flags
+        .long   v7wbi_tlb_flags
        .size   v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c
index 853d42bb8682..4ce0f9801e2e 100644
--- a/arch/arm/oprofile/op_model_mpcore.c
+++ b/arch/arm/oprofile/op_model_mpcore.c
@@ -41,6 +41,7 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
+#include <mach/board-eb.h>
 #include <asm/system.h>
 #include "op_counter.h"
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 17d0e9906d5f..8986b7412235 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -48,7 +48,14 @@ config MXC_IRQ_PRIOR
 config MXC_PWM
        tristate "Enable PWM driver"
        depends on ARCH_MXC
+        select HAVE_PWM
        help
          Enable support for the i.MX PWM controller(s).
+config ARCH_HAS_RNGA
+        bool
+        depends on ARCH_MXC
+config ARCH_MXC_IOMUX_V3
+        bool
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 055406312b69..e3212c8ff421 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -7,4 +7,5 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
 obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
+obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 89e95798cc3b..7506d963be4b 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -64,6 +64,8 @@ static void gpio_unmask_irq(u32 irq)
        _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
 }
+static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
 static int gpio_set_irq_type(u32 irq, u32 type)
 {
        u32 gpio = irq_to_gpio(irq);
@@ -72,6 +74,7 @@ static int gpio_set_irq_type(u32 irq, u32 type)
        int edge;
        void __iomem *reg = port->base;
+        port->both_edges &= ~(1 << (gpio & 31));
        switch (type) {
        case IRQ_TYPE_EDGE_RISING:
                edge = GPIO_INT_RISE_EDGE;
@@ -79,13 +82,24 @@ static int gpio_set_irq_type(u32 irq, u32 type)
        case IRQ_TYPE_EDGE_FALLING:
                edge = GPIO_INT_FALL_EDGE;
                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                val = mxc_gpio_get(&port->chip, gpio & 31);
+                if (val) {
+                        edge = GPIO_INT_LOW_LEV;
+                        pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
+                } else {
+                        edge = GPIO_INT_HIGH_LEV;
+                        pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
+                }
+                port->both_edges |= 1 << (gpio & 31);
+                break;
        case IRQ_TYPE_LEVEL_LOW:
                edge = GPIO_INT_LOW_LEV;
                break;
        case IRQ_TYPE_LEVEL_HIGH:
                edge = GPIO_INT_HIGH_LEV;
                break;
-        default:        /* this includes IRQ_TYPE_EDGE_BOTH */
+        default:
                return -EINVAL;
        }
@@ -98,6 +112,34 @@ static int gpio_set_irq_type(u32 irq, u32 type)
        return 0;
 }
+static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
+{
+        void __iomem *reg = port->base;
+        u32 bit, val;
+        int edge;
+        reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
+        bit = gpio & 0xf;
+        val = __raw_readl(reg);
+        edge = (val >> (bit << 1)) & 3;
+        val &= ~(0x3 << (bit << 1));
+        switch (edge) {
+        case GPIO_INT_HIGH_LEV:
+                edge = GPIO_INT_LOW_LEV;
+                pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
+                break;
+        case GPIO_INT_LOW_LEV:
+                edge = GPIO_INT_HIGH_LEV;
+                pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
+                break;
+        default:
+                pr_err("mxc: invalid configuration for GPIO %d: %x\n",
+                       gpio, edge);
+                return;
+        }
+        __raw_writel(val | (edge << (bit << 1)), reg);
+}
 /* handle n interrupts in one status register */
 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 {
@@ -105,11 +147,16 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
        gpio_irq_no = port->virtual_irq_start;
        for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
+                u32 gpio = irq_to_gpio(gpio_irq_no);
                if ((irq_stat & 1) == 0)
                        continue;
                BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
+                if (port->both_edges & (1 << (gpio & 31)))
+                        mxc_flip_edge(port, gpio);
                irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
                                &irq_desc[gpio_irq_no]);
        }
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
new file mode 100644
index 000000000000..8769e910e559
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>.
+ * All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
+#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
+#include <mach/hardware.h>
+/* mandatory for CONFIG_DEBUG_LL */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
new file mode 100644
index 000000000000..06701df74c42
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
+/*
+ * MXC UART EVB board level configurations
+ */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+/*
+ * Memory-mapped I/O on MX21ADS base board
+ */
+#define MX21ADS_MMIO_BASE_ADDR   0xF5000000
+#define MX21ADS_MMIO_SIZE        SZ_16M
+#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
+                (MX21ADS_MMIO_BASE_ADDR + (offset))
+#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
+#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
+#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
+#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
+/* MX21ADS_IO_REG bit definitions */
+#define MX21ADS_IO_SD_WP        0x0001 /* read */
+#define MX21ADS_IO_TP6          0x0001 /* write */
+#define MX21ADS_IO_SW_SEL       0x0002 /* read */
+#define MX21ADS_IO_TP7          0x0002 /* write */
+#define MX21ADS_IO_RESET_E_UART 0x0004
+#define MX21ADS_IO_RESET_BASE   0x0008
+#define MX21ADS_IO_CSI_CTL2     0x0010
+#define MX21ADS_IO_CSI_CTL1     0x0020
+#define MX21ADS_IO_CSI_CTL0     0x0040
+#define MX21ADS_IO_UART1_EN     0x0080
+#define MX21ADS_IO_UART4_EN     0x0100
+#define MX21ADS_IO_LCDON        0x0200
+#define MX21ADS_IO_IRDA_EN      0x0400
+#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
+#define MX21ADS_IO_IRDA_MD0_B   0x1000
+#define MX21ADS_IO_IRDA_MD1     0x2000
+#define MX21ADS_IO_LED4_ON      0x4000
+#define MX21ADS_IO_LED3_ON      0x8000
+#endif                          /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
new file mode 100644
index 000000000000..a870f8ea2443
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
+#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
+/* mandatory for CONFIG_DEBUG_LL */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
new file mode 100644
index 000000000000..552b55d714d8
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
+#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
+/* mandatory for CONFIG_DEBUG_LL */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 318c72ada13d..06e6895f7f65 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -114,7 +114,7 @@
 #define MXC_MAX_EXP_IO_LINES    16
-/* mandatory for CONFIG_LL_DEBUG */
+/* mandatory for CONFIG_DEBUG_LL */
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
new file mode 100644
index 000000000000..78cf31e22e4d
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * Based on code for mobots boards,
+ *   Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
+#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
+/* mandatory for CONFIG_LL_DEBUG */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
+#ifndef __ASSEMBLY__
+enum mx31lilly_boards {
+        MX31LILLY_NOBOARD       = 0,
+        MX31LILLY_DB            = 1,
+};
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ */
+extern void mx31lilly_db_init(void);
+#endif
+#endif /* __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index e4e5cf5ad7db..52fbdf2d6f26 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -11,28 +11,8 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
 #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-#define MXC_MAX_EXP_IO_LINES    16
-/*
- * Memory Size parameters
- */
-/*
- * Size of SDRAM memory
- */
-#define SDRAM_MEM_SIZE          SZ_128M
-/*
- * Size of MBX buffer memory
- */
-#define MXC_MBX_MEM_SIZE        SZ_16M
-/*
- * Size of memory available to kernel
- */
-#define MEM_SIZE                (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index f8aef1babb75..303fd2434a21 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -19,7 +19,7 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
 #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
-/* mandatory for CONFIG_LL_DEBUG */
+/* mandatory for CONFIG_DEBUG_LL */
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
index 2b6b316d0f51..519bab3eb28b 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
@@ -11,9 +11,54 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
-/* mandatory for CONFIG_LL_DEBUG */
+/* mandatory for CONFIG_DEBUG_LL */
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+/* Definitions for components on the Debug board */
+/* Base address of CPLD controller on the Debug board */
+#define DEBUG_BASE_ADDRESS              CS5_IO_ADDRESS(CS5_BASE_ADDR)
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR               CS5_BASE_ADDR
+/* CPLD config and interrupt base address */
+#define CPLD_ADDR                       (DEBUG_BASE_ADDRESS + 0x20000)
+/* LED switchs */
+#define CPLD_LED_REG                    (CPLD_ADDR + 0x00)
+/* buttons */
+#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08)
+/* status, interrupt */
+#define CPLD_INT_STATUS_REG             (CPLD_ADDR + 0x10)
+#define CPLD_INT_MASK_REG               (CPLD_ADDR + 0x38)
+#define CPLD_INT_RESET_REG              (CPLD_ADDR + 0x20)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER1_REG          (CPLD_ADDR + 0x40)
+#define CPLD_MAGIC_NUMBER2_REG          (CPLD_ADDR + 0x48)
+/* CPLD code version */
+#define CPLD_CODE_VER_REG               (CPLD_ADDR + 0x50)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER3_REG          (CPLD_ADDR + 0x58)
+/* module reset register */
+#define CPLD_MODULE_RESET_REG           (CPLD_ADDR + 0x60)
+/* CPU ID and Personality ID */
+#define CPLD_MCU_BOARD_ID_REG           (CPLD_ADDR + 0x68)
+/* CPLD IRQ line for external uart, external ethernet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+#define EXPIO_INT_ENET          (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_XUART_A       (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_XUART_B       (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_BUTTON_A      (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_BUTTON_B      (MXC_EXP_IO_BASE + 4)
+#define MXC_MAX_EXP_IO_LINES    16
 #endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
new file mode 100644
index 000000000000..1111037d6d9d
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
+#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
+/* mandatory for CONFIG_DEBUG_LL */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
index 82232ba3c8fc..f0a1fa1938a2 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h
@@ -19,7 +19,7 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
 #define __ASM_ARCH_MXC_BOARD_PCM037_H__
-/* mandatory for CONFIG_LL_DEBUG */
+/* mandatory for CONFIG_DEBUG_LL */
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 750c62afd90f..4fcd7499e092 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -19,7 +19,7 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
 #define __ASM_ARCH_MXC_BOARD_PCM038_H__
-/* mandatory for CONFIG_LL_DEBUG */
+/* mandatory for CONFIG_DEBUG_LL */
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
new file mode 100644
index 000000000000..15fbdf16abcd
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-pcm043.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
+#define __ASM_ARCH_MXC_BOARD_PCM043_H__
+/* mandatory for CONFIG_LL_DEBUG */
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
index 4ff762dd45cf..04033ec637d2 100644
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -11,7 +11,7 @@
 #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
 #define __ASM_ARCH_MXC_BOARD_QONG_H__
-/* mandatory for CONFIG_LL_DEBUG */
+/* mandatory for CONFIG_DEBUG_LL */
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index b2f9b72644db..02c3cd004db3 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -14,7 +14,11 @@
 struct platform_device;
 struct clk;
-extern void mxc_map_io(void);
+extern void mx1_map_io(void);
+extern void mx21_map_io(void);
+extern void mx27_map_io(void);
+extern void mx31_map_io(void);
+extern void mx35_map_io(void);
 extern void mxc_init_irq(void);
 extern void mxc_timer_init(struct clk *timer_clk);
 extern int mx1_clocks_init(unsigned long fref);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 4f773148bc20..bbc5f6753cfb 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -25,6 +25,9 @@
 #ifdef CONFIG_MACH_MX27ADS
 #include <mach/board-mx27ads.h>
 #endif
+#ifdef CONFIG_MACH_MX21ADS
+#include <mach/board-mx21ads.h>
+#endif
 #ifdef CONFIG_MACH_PCM038
 #include <mach/board-pcm038.h>
 #endif
@@ -34,6 +37,21 @@
 #ifdef CONFIG_MACH_QONG
 #include <mach/board-qong.h>
 #endif
+#ifdef CONFIG_MACH_PCM043
+#include <mach/board-pcm043.h>
+#endif
+#ifdef CONFIG_MACH_MX27_3DS
+#include <mach/board-mx27pdk.h>
+#endif
+#ifdef CONFIG_MACH_ARMADILLO5X0
+#include <mach/board-armadillo5x0.h>
+#endif
+#ifdef CONFIG_MACH_MX35_3DS
+#include <mach/board-mx35pdk.h>
+#endif
+#ifdef CONFIG_MACH_MX27LITE
+#include <mach/board-mx27lite.h>
+#endif
                .macro  addruart,rx
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index ea509f1090fb..894d2f87c856 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -35,6 +35,7 @@ struct mxc_gpio_port {
        int irq;
        int virtual_irq_start;
        struct gpio_chip chip;
+        u32 both_edges;
 };
 int mxc_gpio_init(struct mxc_gpio_port*, int);
diff --git a/arch/arm/plat-mxc/include/mach/imx-uart.h b/arch/arm/plat-mxc/include/mach/imx-uart.h
index f9bd17dd8dd7..4adec9b154dd 100644
--- a/arch/arm/plat-mxc/include/mach/imx-uart.h
+++ b/arch/arm/plat-mxc/include/mach/imx-uart.h
@@ -24,7 +24,7 @@
 struct imxuart_platform_data {
        int (*init)(struct platform_device *pdev);
-        int (*exit)(struct platform_device *pdev);
+        void (*exit)(struct platform_device *pdev);
        unsigned int flags;
        void (*irda_enable)(int enable);
        unsigned int irda_inv_rx:1;
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 762a7b0430e2..9f0101157ec1 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -76,8 +76,8 @@ struct imx_fb_platform_data {
        u_char * fixed_screen_cpu;
        dma_addr_t fixed_screen_dma;
-        int (*init)(struct platform_device*);
+        int (*init)(struct platform_device *);
-        int (*exit)(struct platform_device*);
+        void (*exit)(struct platform_device *);
        void (*lcd_power)(int);
        void (*backlight_power)(int);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 57e927a1fd3a..27f8d1b2bc6b 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -114,7 +114,7 @@ enum iomux_gp_func {
 *      - setups the iomux according to the configuration
 *      - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
 */
-int mxc_iomux_setup_pin(const unsigned int pin, const char *label);
+int mxc_iomux_alloc_pin(const unsigned int pin, const char *label);
 /*
 * setups mutliple pins
 * convenient way to call the above function with tables
@@ -633,6 +633,40 @@ enum iomux_pins {
 #define MX31_PIN_USBOTG_DIR__USBOTG_DIR        IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_NXT__USBOTG_NXT        IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_STP__USBOTG_STP        IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DCD_DTE1__I2C2_SDA     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_RI_DTE1__I2C2_SCL      IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_ATA_CS0__GPIO3_26      IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_ATA_CS1__GPIO3_27      IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_PC_PWRON__SD2_DATA3    IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_VS1__SD2_DATA2      IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_READY__SD2_DATA1    IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_WAIT_B__SD2_DATA0   IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_CD2_B__SD2_CLK      IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_PC_CD1_B__SD2_CMD      IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_ATA_DIOR__GPIO3_28     IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_ATA_DIOW__GPIO3_29     IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D4__CSI_D4         IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D5__CSI_D5         IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D6__CSI_D6         IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D7__CSI_D7         IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D8__CSI_D8         IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D9__CSI_D9         IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D10__CSI_D10       IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D11__CSI_D11       IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D12__CSI_D12       IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D13__CSI_D13       IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D14__CSI_D14       IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_D15__CSI_D15       IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_HSYNC__CSI_HSYNC   IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_MCLK__CSI_MCLK     IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSI_VSYNC__CSI_VSYNC   IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
new file mode 100644
index 000000000000..00b0ac1db225
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -0,0 +1,1267 @@
+/*
+ * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option, NO_PAD_CTRL) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_IOMUX_MX35_H__
+#define __MACH_IOMUX_MX35_H__
+#include <mach/iomux-v3.h>
+/*
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named
+ * GPIO_<unit>_<num> see also iomux-v3.h
+ */
+/*                                                                        PAD    MUX   ALT INPSE PATH */
+#define MX35_PAD_CAPTURE__GPT_CAPIN1                            IOMUX_PAD(0x328, 0x004, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CAPTURE__GPT_CMPOUT2                           IOMUX_PAD(0x328, 0x004, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CAPTURE__CSPI2_SS1                             IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL)
+#define MX35_PAD_CAPTURE__EPIT1_EPITO                           IOMUX_PAD(0x328, 0x004, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CAPTURE__CCM_CLK32K                            IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL)
+#define MX35_PAD_CAPTURE__GPIO1_4                               IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL)
+#define MX35_PAD_COMPARE__GPT_CMPOUT1                           IOMUX_PAD(0x32c, 0x008, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_COMPARE__GPT_CAPIN2                            IOMUX_PAD(0x32c, 0x008, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_COMPARE__GPT_CMPOUT3                           IOMUX_PAD(0x32c, 0x008, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_COMPARE__EPIT2_EPITO                           IOMUX_PAD(0x32c, 0x008, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_COMPARE__GPIO1_5                               IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL)
+#define MX35_PAD_COMPARE__SDMA_EXTDMA_2                         IOMUX_PAD(0x32c, 0x008, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_WDOG_RST__WDOG_WDOG_B                          IOMUX_PAD(0x330, 0x00c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE                     IOMUX_PAD(0x330, 0x00c, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_WDOG_RST__GPIO1_6                              IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_0__GPIO1_0                               IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY                          IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_0__OWIRE_LINE                            IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0                         IOMUX_PAD(0x334, 0x010, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_1__GPIO1_1                               IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_1__PWM_PWMO                              IOMUX_PAD(0x338, 0x014, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_1__CSPI1_SS2                             IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT                     IOMUX_PAD(0x338, 0x014, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1                         IOMUX_PAD(0x338, 0x014, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO2_0__GPIO2_0                               IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK                    IOMUX_PAD(0x33c, 0x018, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO3_0__GPIO3_0                               IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL)
+#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK                     IOMUX_PAD(0x340, 0x01c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B                     IOMUX_PAD(0x344, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_POR_B__CCM_POR_B                               IOMUX_PAD(0x348, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CLKO__CCM_CLKO                                 IOMUX_PAD(0x34c, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CLKO__GPIO1_8                                  IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL)
+#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0                    IOMUX_PAD(0x350, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1                    IOMUX_PAD(0x354, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0                      IOMUX_PAD(0x358, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1                      IOMUX_PAD(0x35c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26              IOMUX_PAD(0x360, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_VSTBY__CCM_VSTBY                               IOMUX_PAD(0x364, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_VSTBY__GPIO1_7                                 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL)
+#define MX35_PAD_A0__EMI_EIM_DA_L_0                             IOMUX_PAD(0x368, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A1__EMI_EIM_DA_L_1                             IOMUX_PAD(0x36c, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A2__EMI_EIM_DA_L_2                             IOMUX_PAD(0x370, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A3__EMI_EIM_DA_L_3                             IOMUX_PAD(0x374, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A4__EMI_EIM_DA_L_4                             IOMUX_PAD(0x378, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A5__EMI_EIM_DA_L_5                             IOMUX_PAD(0x37c, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A6__EMI_EIM_DA_L_6                             IOMUX_PAD(0x380, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A7__EMI_EIM_DA_L_7                             IOMUX_PAD(0x384, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A8__EMI_EIM_DA_H_8                             IOMUX_PAD(0x388, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A9__EMI_EIM_DA_H_9                             IOMUX_PAD(0x38c, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A10__EMI_EIM_DA_H_10                           IOMUX_PAD(0x390, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_MA10__EMI_MA10                                 IOMUX_PAD(0x394, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A11__EMI_EIM_DA_H_11                           IOMUX_PAD(0x398, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A12__EMI_EIM_DA_H_12                           IOMUX_PAD(0x39c, 0x05c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A13__EMI_EIM_DA_H_13                           IOMUX_PAD(0x3a0, 0x060, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A14__EMI_EIM_DA_H2_14                          IOMUX_PAD(0x3a4, 0x064, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A15__EMI_EIM_DA_H2_15                          IOMUX_PAD(0x3a8, 0x068, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A16__EMI_EIM_A_16                              IOMUX_PAD(0x3ac, 0x06c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A17__EMI_EIM_A_17                              IOMUX_PAD(0x3b0, 0x070, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A18__EMI_EIM_A_18                              IOMUX_PAD(0x3b4, 0x074, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A19__EMI_EIM_A_19                              IOMUX_PAD(0x3b8, 0x078, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A20__EMI_EIM_A_20                              IOMUX_PAD(0x3bc, 0x07c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A21__EMI_EIM_A_21                              IOMUX_PAD(0x3c0, 0x080, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A22__EMI_EIM_A_22                              IOMUX_PAD(0x3c4, 0x084, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A23__EMI_EIM_A_23                              IOMUX_PAD(0x3c8, 0x088, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A24__EMI_EIM_A_24                              IOMUX_PAD(0x3cc, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_A25__EMI_EIM_A_25                              IOMUX_PAD(0x3d0, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDBA1__EMI_EIM_SDBA1                           IOMUX_PAD(0x3d4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDBA0__EMI_EIM_SDBA0                           IOMUX_PAD(0x3d8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD0__EMI_DRAM_D_0                              IOMUX_PAD(0x3dc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1__EMI_DRAM_D_1                              IOMUX_PAD(0x3e0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2__EMI_DRAM_D_2                              IOMUX_PAD(0x3e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD3__EMI_DRAM_D_3                              IOMUX_PAD(0x3e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD4__EMI_DRAM_D_4                              IOMUX_PAD(0x3ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD5__EMI_DRAM_D_5                              IOMUX_PAD(0x3f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD6__EMI_DRAM_D_6                              IOMUX_PAD(0x3f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD7__EMI_DRAM_D_7                              IOMUX_PAD(0x3f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD8__EMI_DRAM_D_8                              IOMUX_PAD(0x3fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD9__EMI_DRAM_D_9                              IOMUX_PAD(0x400, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD10__EMI_DRAM_D_10                            IOMUX_PAD(0x404, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD11__EMI_DRAM_D_11                            IOMUX_PAD(0x408, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD12__EMI_DRAM_D_12                            IOMUX_PAD(0x40c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD13__EMI_DRAM_D_13                            IOMUX_PAD(0x410, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD14__EMI_DRAM_D_14                            IOMUX_PAD(0x414, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD15__EMI_DRAM_D_15                            IOMUX_PAD(0x418, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD16__EMI_DRAM_D_16                            IOMUX_PAD(0x41c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD17__EMI_DRAM_D_17                            IOMUX_PAD(0x420, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD18__EMI_DRAM_D_18                            IOMUX_PAD(0x424, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD19__EMI_DRAM_D_19                            IOMUX_PAD(0x428, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD20__EMI_DRAM_D_20                            IOMUX_PAD(0x42c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD21__EMI_DRAM_D_21                            IOMUX_PAD(0x430, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD22__EMI_DRAM_D_22                            IOMUX_PAD(0x434, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD23__EMI_DRAM_D_23                            IOMUX_PAD(0x438, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD24__EMI_DRAM_D_24                            IOMUX_PAD(0x43c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD25__EMI_DRAM_D_25                            IOMUX_PAD(0x440, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD26__EMI_DRAM_D_26                            IOMUX_PAD(0x444, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD27__EMI_DRAM_D_27                            IOMUX_PAD(0x448, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD28__EMI_DRAM_D_28                            IOMUX_PAD(0x44c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD29__EMI_DRAM_D_29                            IOMUX_PAD(0x450, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD30__EMI_DRAM_D_30                            IOMUX_PAD(0x454, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD31__EMI_DRAM_D_31                            IOMUX_PAD(0x458, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_DQM0__EMI_DRAM_DQM_0                           IOMUX_PAD(0x45c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_DQM1__EMI_DRAM_DQM_1                           IOMUX_PAD(0x460, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_DQM2__EMI_DRAM_DQM_2                           IOMUX_PAD(0x464, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_DQM3__EMI_DRAM_DQM_3                           IOMUX_PAD(0x468, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_EB0__EMI_EIM_EB0_B                             IOMUX_PAD(0x46c, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_EB1__EMI_EIM_EB1_B                             IOMUX_PAD(0x470, 0x098, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_OE__EMI_EIM_OE                                 IOMUX_PAD(0x474, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS0__EMI_EIM_CS0                               IOMUX_PAD(0x478, 0x0a0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS1__EMI_EIM_CS1                               IOMUX_PAD(0x47c, 0x0a4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS1__EMI_NANDF_CE3                             IOMUX_PAD(0x47c, 0x0a4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS2__EMI_EIM_CS2                               IOMUX_PAD(0x480, 0x0a8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS3__EMI_EIM_CS3                               IOMUX_PAD(0x484, 0x0ac, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS4__EMI_EIM_CS4                               IOMUX_PAD(0x488, 0x0b0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS4__EMI_DTACK_B                               IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL)
+#define MX35_PAD_CS4__EMI_NANDF_CE1                             IOMUX_PAD(0x488, 0x0b0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS4__GPIO1_20                                  IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL)
+#define MX35_PAD_CS5__EMI_EIM_CS5                               IOMUX_PAD(0x48c, 0x0b4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS5__CSPI2_SS2                                 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL)
+#define MX35_PAD_CS5__CSPI1_SS2                                 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL)
+#define MX35_PAD_CS5__EMI_NANDF_CE2                             IOMUX_PAD(0x48c, 0x0b4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CS5__GPIO1_21                                  IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL)
+#define MX35_PAD_NF_CE0__EMI_NANDF_CE0                          IOMUX_PAD(0x490, 0x0b8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NF_CE0__GPIO1_22                               IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL)
+#define MX35_PAD_ECB__EMI_EIM_ECB                               IOMUX_PAD(0x494, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LBA__EMI_EIM_LBA                               IOMUX_PAD(0x498, 0x0bc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_BCLK__EMI_EIM_BCLK                             IOMUX_PAD(0x49c, 0x0c0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RW__EMI_EIM_RW                                 IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RAS__EMI_DRAM_RAS                              IOMUX_PAD(0x4a4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CAS__EMI_DRAM_CAS                              IOMUX_PAD(0x4a8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDWE__EMI_DRAM_SDWE                            IOMUX_PAD(0x4ac, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0                       IOMUX_PAD(0x4b0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1                       IOMUX_PAD(0x4b4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK                          IOMUX_PAD(0x4b8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0                         IOMUX_PAD(0x4bc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1                         IOMUX_PAD(0x4c0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2                         IOMUX_PAD(0x4c4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3                         IOMUX_PAD(0x4c8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B                         IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3                   IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC                     IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFWE_B__GPIO2_18                               IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0                     IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B                         IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR                      IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK                         IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFRE_B__GPIO2_19                               IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1                     IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFALE__EMI_NANDF_ALE                           IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFALE__USB_TOP_USBH2_STP                       IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFALE__IPU_DISPB_CS0                           IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFALE__GPIO2_20                                IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2                      IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFCLE__EMI_NANDF_CLE                           IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT                       IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS                        IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFCLE__GPIO2_21                                IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3                      IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B                         IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7                   IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFWP_B__IPU_DISPB_WR                           IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFWP_B__GPIO2_22                               IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL                       IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFRB__EMI_NANDF_RB                             IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFRB__IPU_DISPB_RD                             IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_NFRB__GPIO2_23                                 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL)
+#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK                         IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D15__EMI_EIM_D_15                              IOMUX_PAD(0x4e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D14__EMI_EIM_D_14                              IOMUX_PAD(0x4e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D13__EMI_EIM_D_13                              IOMUX_PAD(0x4ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D12__EMI_EIM_D_12                              IOMUX_PAD(0x4f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D11__EMI_EIM_D_11                              IOMUX_PAD(0x4f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D10__EMI_EIM_D_10                              IOMUX_PAD(0x4f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D9__EMI_EIM_D_9                                IOMUX_PAD(0x4fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D8__EMI_EIM_D_8                                IOMUX_PAD(0x500, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D7__EMI_EIM_D_7                                IOMUX_PAD(0x504, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D6__EMI_EIM_D_6                                IOMUX_PAD(0x508, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D5__EMI_EIM_D_5                                IOMUX_PAD(0x50c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D4__EMI_EIM_D_4                                IOMUX_PAD(0x510, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3__EMI_EIM_D_3                                IOMUX_PAD(0x514, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D2__EMI_EIM_D_2                                IOMUX_PAD(0x518, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D1__EMI_EIM_D_1                                IOMUX_PAD(0x51c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D0__EMI_EIM_D_0                                IOMUX_PAD(0x520, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D8__IPU_CSI_D_8                            IOMUX_PAD(0x524, 0x0e0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D8__KPP_COL_0                              IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D8__GPIO1_20                               IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13                  IOMUX_PAD(0x524, 0x0e0, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D9__IPU_CSI_D_9                            IOMUX_PAD(0x528, 0x0e4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D9__KPP_COL_1                              IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D9__GPIO1_21                               IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14                  IOMUX_PAD(0x528, 0x0e4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D10__IPU_CSI_D_10                          IOMUX_PAD(0x52c, 0x0e8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D10__KPP_COL_2                             IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D10__GPIO1_22                              IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15                 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D11__IPU_CSI_D_11                          IOMUX_PAD(0x530, 0x0ec, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D11__KPP_COL_3                             IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D11__GPIO1_23                              IOMUX_PAD(0x530, 0x0ec, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D12__IPU_CSI_D_12                          IOMUX_PAD(0x534, 0x0f0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D12__KPP_ROW_0                             IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D12__GPIO1_24                              IOMUX_PAD(0x534, 0x0f0, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D13__IPU_CSI_D_13                          IOMUX_PAD(0x538, 0x0f4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D13__KPP_ROW_1                             IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D13__GPIO1_25                              IOMUX_PAD(0x538, 0x0f4, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D14__IPU_CSI_D_14                          IOMUX_PAD(0x53c, 0x0f8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D14__KPP_ROW_2                             IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D14__GPIO1_26                              IOMUX_PAD(0x53c, 0x0f8, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D15__IPU_CSI_D_15                          IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D15__KPP_ROW_3                             IOMUX_PAD(0x540, 0x0fc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_D15__GPIO1_27                              IOMUX_PAD(0x540, 0x0fc, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK                         IOMUX_PAD(0x544, 0x100, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_MCLK__GPIO1_28                             IOMUX_PAD(0x544, 0x100, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC                       IOMUX_PAD(0x548, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_VSYNC__GPIO1_29                            IOMUX_PAD(0x548, 0x104, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC                       IOMUX_PAD(0x54c, 0x108, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_HSYNC__GPIO1_30                            IOMUX_PAD(0x54c, 0x108, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK                     IOMUX_PAD(0x550, 0x10c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSI_PIXCLK__GPIO1_31                           IOMUX_PAD(0x550, 0x10c, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C1_CLK__I2C1_SCL                             IOMUX_PAD(0x554, 0x110, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C1_CLK__GPIO2_24                             IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL)
+#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK                      IOMUX_PAD(0x554, 0x110, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C1_DAT__I2C1_SDA                             IOMUX_PAD(0x558, 0x114, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C1_DAT__GPIO2_25                             IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_CLK__I2C2_SCL                             IOMUX_PAD(0x55c, 0x118, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_CLK__CAN1_TXCAN                           IOMUX_PAD(0x55c, 0x118, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR                    IOMUX_PAD(0x55c, 0x118, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_CLK__GPIO2_26                             IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2              IOMUX_PAD(0x55c, 0x118, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_DAT__I2C2_SDA                             IOMUX_PAD(0x560, 0x11c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_DAT__CAN1_RXCAN                           IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC                     IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_DAT__GPIO2_27                             IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL)
+#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3              IOMUX_PAD(0x560, 0x11c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD                         IOMUX_PAD(0x564, 0x120, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXD4__GPIO2_28                                IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL)
+#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0                IOMUX_PAD(0x564, 0x120, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD                         IOMUX_PAD(0x568, 0x124, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SRXD4__GPIO2_29                                IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL)
+#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1                IOMUX_PAD(0x568, 0x124, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC                          IOMUX_PAD(0x56c, 0x128, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCK4__GPIO2_30                                 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL)
+#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2                 IOMUX_PAD(0x56c, 0x128, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS                       IOMUX_PAD(0x570, 0x12c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXFS4__GPIO2_31                               IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL)
+#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3               IOMUX_PAD(0x570, 0x12c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD                         IOMUX_PAD(0x574, 0x130, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1                        IOMUX_PAD(0x574, 0x130, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXD5__CSPI2_MOSI                              IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL)
+#define MX35_PAD_STXD5__GPIO1_0                                 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL)
+#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4                IOMUX_PAD(0x574, 0x130, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD                         IOMUX_PAD(0x578, 0x134, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1                         IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL)
+#define MX35_PAD_SRXD5__CSPI2_MISO                              IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL)
+#define MX35_PAD_SRXD5__GPIO1_1                                 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL)
+#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5                IOMUX_PAD(0x578, 0x134, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC                          IOMUX_PAD(0x57c, 0x138, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK                       IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL)
+#define MX35_PAD_SCK5__CSPI2_SCLK                               IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SCK5__GPIO1_2                                  IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL)
+#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6                 IOMUX_PAD(0x57c, 0x138, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS                       IOMUX_PAD(0x580, 0x13c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_STXFS5__CSPI2_RDY                              IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL)
+#define MX35_PAD_STXFS5__GPIO1_3                                IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL)
+#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7               IOMUX_PAD(0x580, 0x13c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCKR__ESAI_SCKR                                IOMUX_PAD(0x584, 0x140, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCKR__GPIO1_4                                  IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL)
+#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10                    IOMUX_PAD(0x584, 0x140, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FSR__ESAI_FSR                                  IOMUX_PAD(0x588, 0x144, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FSR__GPIO1_5                                   IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL)
+#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11                     IOMUX_PAD(0x588, 0x144, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_HCKR__ESAI_HCKR                                IOMUX_PAD(0x58c, 0x148, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS                         IOMUX_PAD(0x58c, 0x148, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_HCKR__CSPI2_SS0                                IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL)
+#define MX35_PAD_HCKR__IPU_FLASH_STROBE                         IOMUX_PAD(0x58c, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_HCKR__GPIO1_6                                  IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL)
+#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12                    IOMUX_PAD(0x58c, 0x148, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCKT__ESAI_SCKT                                IOMUX_PAD(0x590, 0x14c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SCKT__GPIO1_7                                  IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL)
+#define MX35_PAD_SCKT__IPU_CSI_D_0                              IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL)
+#define MX35_PAD_SCKT__KPP_ROW_2                                IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL)
+#define MX35_PAD_FST__ESAI_FST                                  IOMUX_PAD(0x594, 0x150, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FST__GPIO1_8                                   IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL)
+#define MX35_PAD_FST__IPU_CSI_D_1                               IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL)
+#define MX35_PAD_FST__KPP_ROW_3                                 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL)
+#define MX35_PAD_HCKT__ESAI_HCKT                                IOMUX_PAD(0x598, 0x154, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC                          IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL)
+#define MX35_PAD_HCKT__GPIO1_9                                  IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL)
+#define MX35_PAD_HCKT__IPU_CSI_D_2                              IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL)
+#define MX35_PAD_HCKT__KPP_COL_3                                IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0                          IOMUX_PAD(0x59c, 0x158, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC                       IOMUX_PAD(0x59c, 0x158, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX5_RX0__CSPI2_SS2                             IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX5_RX0__CAN2_TXCAN                            IOMUX_PAD(0x59c, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX5_RX0__UART2_DTR                             IOMUX_PAD(0x59c, 0x158, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX5_RX0__GPIO1_10                              IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0              IOMUX_PAD(0x59c, 0x158, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1                          IOMUX_PAD(0x5a0, 0x15c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS                      IOMUX_PAD(0x5a0, 0x15c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__CSPI2_SS3                             IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__CAN2_RXCAN                            IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__UART2_DSR                             IOMUX_PAD(0x5a0, 0x15c, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__GPIO1_11                              IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__IPU_CSI_D_3                           IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX4_RX1__KPP_ROW_0                             IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2                          IOMUX_PAD(0x5a4, 0x160, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX3_RX2__I2C3_SCL                              IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1                         IOMUX_PAD(0x5a4, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX3_RX2__GPIO1_12                              IOMUX_PAD(0x5a4, 0x160, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX3_RX2__IPU_CSI_D_4                           IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX3_RX2__KPP_ROW_1                             IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3                          IOMUX_PAD(0x5a8, 0x164, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX2_RX3__I2C3_SDA                              IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2                         IOMUX_PAD(0x5a8, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX2_RX3__GPIO1_13                              IOMUX_PAD(0x5a8, 0x164, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX2_RX3__IPU_CSI_D_5                           IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX2_RX3__KPP_COL_0                             IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX1__ESAI_TX1                                  IOMUX_PAD(0x5ac, 0x168, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX1__CCM_PMIC_RDY                              IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX1__CSPI1_SS2                                 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL)
+#define MX35_PAD_TX1__EMI_NANDF_CE3                             IOMUX_PAD(0x5ac, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX1__UART2_RI                                  IOMUX_PAD(0x5ac, 0x168, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX1__GPIO1_14                                  IOMUX_PAD(0x5ac, 0x168, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX1__IPU_CSI_D_6                               IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX1__KPP_COL_1                                 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX0__ESAI_TX0                                  IOMUX_PAD(0x5b0, 0x16c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK                        IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX0__CSPI1_SS3                                 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX0__EMI_DTACK_B                               IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL)
+#define MX35_PAD_TX0__UART2_DCD                                 IOMUX_PAD(0x5b0, 0x16c, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX0__GPIO1_15                                  IOMUX_PAD(0x5b0, 0x16c, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TX0__IPU_CSI_D_7                               IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL)
+#define MX35_PAD_TX0__KPP_COL_2                                 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI                         IOMUX_PAD(0x5b4, 0x170, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_MOSI__GPIO1_16                           IOMUX_PAD(0x5b4, 0x170, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2                IOMUX_PAD(0x5b4, 0x170, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_MISO__CSPI1_MISO                         IOMUX_PAD(0x5b8, 0x174, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_MISO__GPIO1_17                           IOMUX_PAD(0x5b8, 0x174, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3                IOMUX_PAD(0x5b8, 0x174, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS0__CSPI1_SS0                           IOMUX_PAD(0x5bc, 0x178, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS0__OWIRE_LINE                          IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS0__CSPI2_SS3                           IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS0__GPIO1_18                            IOMUX_PAD(0x5bc, 0x178, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4                 IOMUX_PAD(0x5bc, 0x178, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS1__CSPI1_SS1                           IOMUX_PAD(0x5c0, 0x17c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS1__PWM_PWMO                            IOMUX_PAD(0x5c0, 0x17c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS1__CCM_CLK32K                          IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS1__GPIO1_19                            IOMUX_PAD(0x5c0, 0x17c, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29                        IOMUX_PAD(0x5c0, 0x17c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5                 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK                         IOMUX_PAD(0x5c4, 0x180, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SCLK__GPIO3_4                            IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30                       IOMUX_PAD(0x5c4, 0x180, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1           IOMUX_PAD(0x5c4, 0x180, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY                       IOMUX_PAD(0x5c8, 0x184, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5                         IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31                    IOMUX_PAD(0x5c8, 0x184, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2        IOMUX_PAD(0x5c8, 0x184, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RXD1__UART1_RXD_MUX                            IOMUX_PAD(0x5cc, 0x188, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RXD1__CSPI2_MOSI                               IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL)
+#define MX35_PAD_RXD1__KPP_COL_4                                IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL)
+#define MX35_PAD_RXD1__GPIO3_6                                  IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL)
+#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16                    IOMUX_PAD(0x5cc, 0x188, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TXD1__UART1_TXD_MUX                            IOMUX_PAD(0x5d0, 0x18c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TXD1__CSPI2_MISO                               IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL)
+#define MX35_PAD_TXD1__KPP_COL_5                                IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL)
+#define MX35_PAD_TXD1__GPIO3_7                                  IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL)
+#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17                    IOMUX_PAD(0x5d0, 0x18c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__UART1_RTS                                IOMUX_PAD(0x5d4, 0x190, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__CSPI2_SCLK                               IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__I2C3_SCL                                 IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__IPU_CSI_D_0                              IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__KPP_COL_6                                IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__GPIO3_8                                  IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__EMI_NANDF_CE1                            IOMUX_PAD(0x5d4, 0x190, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18                    IOMUX_PAD(0x5d4, 0x190, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__UART1_CTS                                IOMUX_PAD(0x5d8, 0x194, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__CSPI2_RDY                                IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__I2C3_SDA                                 IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__IPU_CSI_D_1                              IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__KPP_COL_7                                IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__GPIO3_9                                  IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__EMI_NANDF_CE2                            IOMUX_PAD(0x5d8, 0x194, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19                    IOMUX_PAD(0x5d8, 0x194, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RXD2__UART2_RXD_MUX                            IOMUX_PAD(0x5dc, 0x198, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RXD2__KPP_ROW_4                                IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL)
+#define MX35_PAD_RXD2__GPIO3_10                                 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL)
+#define MX35_PAD_TXD2__UART2_TXD_MUX                            IOMUX_PAD(0x5e0, 0x19c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK                       IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL)
+#define MX35_PAD_TXD2__KPP_ROW_5                                IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL)
+#define MX35_PAD_TXD2__GPIO3_11                                 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__UART2_RTS                                IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1                          IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__CAN2_RXCAN                               IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__IPU_CSI_D_2                              IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__KPP_ROW_6                                IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__GPIO3_12                                 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC                          IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RTS2__UART3_RXD_MUX                            IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__UART2_CTS                                IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1                         IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__CAN2_TXCAN                               IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__IPU_CSI_D_3                              IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__KPP_ROW_7                                IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__GPIO3_13                                 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS                         IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CTS2__UART3_TXD_MUX                            IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_RTCK__ARM11P_TOP_RTCK                          IOMUX_PAD(0x5ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TCK__SJC_TCK                                   IOMUX_PAD(0x5f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TMS__SJC_TMS                                   IOMUX_PAD(0x5f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TDI__SJC_TDI                                   IOMUX_PAD(0x5f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TDO__SJC_TDO                                   IOMUX_PAD(0x5fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TRSTB__SJC_TRSTB                               IOMUX_PAD(0x600, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_DE_B__SJC_DE_B                                 IOMUX_PAD(0x604, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SJC_MOD__SJC_MOD                               IOMUX_PAD(0x608, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR                 IOMUX_PAD(0x60c, 0x1a8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR                  IOMUX_PAD(0x60c, 0x1a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_USBOTG_PWR__GPIO3_14                           IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL)
+#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC                   IOMUX_PAD(0x610, 0x1ac, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC                    IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL)
+#define MX35_PAD_USBOTG_OC__GPIO3_15                            IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD0__IPU_DISPB_DAT_0                           IOMUX_PAD(0x614, 0x1b0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD0__GPIO2_0                                   IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL)
+#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0                      IOMUX_PAD(0x614, 0x1b0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD1__IPU_DISPB_DAT_1                           IOMUX_PAD(0x618, 0x1b4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD1__GPIO2_1                                   IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1                      IOMUX_PAD(0x618, 0x1b4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD2__IPU_DISPB_DAT_2                           IOMUX_PAD(0x61c, 0x1b8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD2__GPIO2_2                                   IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2                      IOMUX_PAD(0x61c, 0x1b8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD3__IPU_DISPB_DAT_3                           IOMUX_PAD(0x620, 0x1bc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD3__GPIO2_3                                   IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3                      IOMUX_PAD(0x620, 0x1bc, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD4__IPU_DISPB_DAT_4                           IOMUX_PAD(0x624, 0x1c0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD4__GPIO2_4                                   IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4                      IOMUX_PAD(0x624, 0x1c0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD5__IPU_DISPB_DAT_5                           IOMUX_PAD(0x628, 0x1c4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD5__GPIO2_5                                   IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5                      IOMUX_PAD(0x628, 0x1c4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD6__IPU_DISPB_DAT_6                           IOMUX_PAD(0x62c, 0x1c8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD6__GPIO2_6                                   IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6                      IOMUX_PAD(0x62c, 0x1c8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD7__IPU_DISPB_DAT_7                           IOMUX_PAD(0x630, 0x1cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD7__GPIO2_7                                   IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7                      IOMUX_PAD(0x630, 0x1cc, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD8__IPU_DISPB_DAT_8                           IOMUX_PAD(0x634, 0x1d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD8__GPIO2_8                                   IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8                      IOMUX_PAD(0x634, 0x1d0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD9__IPU_DISPB_DAT_9                           IOMUX_PAD(0x638, 0x1d4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD9__GPIO2_9                                   IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4  0, NO_PAD_CTRL)
+#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9                      IOMUX_PAD(0x638, 0x1d4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD10__IPU_DISPB_DAT_10                         IOMUX_PAD(0x63c, 0x1d8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD10__GPIO2_10                                 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10                    IOMUX_PAD(0x63c, 0x1d8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD11__IPU_DISPB_DAT_11                         IOMUX_PAD(0x640, 0x1dc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD11__GPIO2_11                                 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11                    IOMUX_PAD(0x640, 0x1dc, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4                       IOMUX_PAD(0x640, 0x1dc, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD12__IPU_DISPB_DAT_12                         IOMUX_PAD(0x644, 0x1e0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD12__GPIO2_12                                 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12                    IOMUX_PAD(0x644, 0x1e0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5                       IOMUX_PAD(0x644, 0x1e0, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD13__IPU_DISPB_DAT_13                         IOMUX_PAD(0x648, 0x1e4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD13__GPIO2_13                                 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13                    IOMUX_PAD(0x648, 0x1e4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6                       IOMUX_PAD(0x648, 0x1e4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD14__IPU_DISPB_DAT_14                         IOMUX_PAD(0x64c, 0x1e8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD14__GPIO2_14                                 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0          IOMUX_PAD(0x64c, 0x1e8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7                       IOMUX_PAD(0x64c, 0x1e8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD15__IPU_DISPB_DAT_15                         IOMUX_PAD(0x650, 0x1ec, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD15__GPIO2_15                                 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1          IOMUX_PAD(0x650, 0x1ec, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8                       IOMUX_PAD(0x650, 0x1ec, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD16__IPU_DISPB_DAT_16                         IOMUX_PAD(0x654, 0x1f0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC                      IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD16__GPIO2_16                                 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2          IOMUX_PAD(0x654, 0x1f0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9                       IOMUX_PAD(0x654, 0x1f0, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD17__IPU_DISPB_DAT_17                         IOMUX_PAD(0x658, 0x1f4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD17__IPU_DISPB_CS2                            IOMUX_PAD(0x658, 0x1f4, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD17__GPIO2_17                                 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3          IOMUX_PAD(0x658, 0x1f4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10                      IOMUX_PAD(0x658, 0x1f4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD18__IPU_DISPB_DAT_18                         IOMUX_PAD(0x65c, 0x1f8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC                       IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL)
+#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC                      IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL)
+#define MX35_PAD_LD18__ESDHC3_CMD                               IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3                    IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD18__GPIO3_24                                 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4          IOMUX_PAD(0x65c, 0x1f8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11                      IOMUX_PAD(0x65c, 0x1f8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__IPU_DISPB_DAT_19                         IOMUX_PAD(0x660, 0x1fc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__IPU_DISPB_BCLK                           IOMUX_PAD(0x660, 0x1fc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__IPU_DISPB_CS1                            IOMUX_PAD(0x660, 0x1fc, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__ESDHC3_CLK                               IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR                       IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__GPIO3_25                                 IOMUX_PAD(0x660, 0x1fc, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5          IOMUX_PAD(0x660, 0x1fc, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12                      IOMUX_PAD(0x660, 0x1fc, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD20__IPU_DISPB_DAT_20                         IOMUX_PAD(0x664, 0x200, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD20__IPU_DISPB_CS0                            IOMUX_PAD(0x664, 0x200, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD20__IPU_DISPB_SD_CLK                         IOMUX_PAD(0x664, 0x200, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD20__ESDHC3_DAT0                              IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD20__GPIO3_26                                 IOMUX_PAD(0x664, 0x200, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3            IOMUX_PAD(0x664, 0x200, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13                      IOMUX_PAD(0x664, 0x200, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__IPU_DISPB_DAT_21                         IOMUX_PAD(0x668, 0x204, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__IPU_DISPB_PAR_RS                         IOMUX_PAD(0x668, 0x204, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__IPU_DISPB_SER_RS                         IOMUX_PAD(0x668, 0x204, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__ESDHC3_DAT1                              IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__USB_TOP_USBOTG_STP                       IOMUX_PAD(0x668, 0x204, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__GPIO3_27                                 IOMUX_PAD(0x668, 0x204, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL             IOMUX_PAD(0x668, 0x204, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14                      IOMUX_PAD(0x668, 0x204, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__IPU_DISPB_DAT_22                         IOMUX_PAD(0x66c, 0x208, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__IPU_DISPB_WR                             IOMUX_PAD(0x66c, 0x208, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__IPU_DISPB_SD_D_I                         IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__ESDHC3_DAT2                              IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT                       IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__GPIO3_28                                 IOMUX_PAD(0x66c, 0x208, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR                     IOMUX_PAD(0x66c, 0x208, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD22__ARM11P_TOP_TRCTL                         IOMUX_PAD(0x66c, 0x208, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD23__IPU_DISPB_DAT_23                         IOMUX_PAD(0x670, 0x20c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD23__IPU_DISPB_RD                             IOMUX_PAD(0x670, 0x20c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO                        IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL)
+#define MX35_PAD_LD23__ESDHC3_DAT3                              IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7                    IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL)
+#define MX35_PAD_LD23__GPIO3_29                                 IOMUX_PAD(0x670, 0x20c, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS                 IOMUX_PAD(0x670, 0x20c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_LD23__ARM11P_TOP_TRCLK                         IOMUX_PAD(0x670, 0x20c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC                   IOMUX_PAD(0x674, 0x210, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO                    IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL)
+#define MX35_PAD_D3_HSYNC__GPIO3_30                             IOMUX_PAD(0x674, 0x210, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE            IOMUX_PAD(0x674, 0x210, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15                  IOMUX_PAD(0x674, 0x210, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK                   IOMUX_PAD(0x678, 0x214, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK                   IOMUX_PAD(0x678, 0x214, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_FPSHIFT__GPIO3_31                           IOMUX_PAD(0x678, 0x214, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0      IOMUX_PAD(0x678, 0x214, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16                IOMUX_PAD(0x678, 0x214, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY                     IOMUX_PAD(0x67c, 0x218, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O                      IOMUX_PAD(0x67c, 0x218, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_DRDY__GPIO1_0                               IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL)
+#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1         IOMUX_PAD(0x67c, 0x218, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17                   IOMUX_PAD(0x67c, 0x218, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR                      IOMUX_PAD(0x680, 0x21c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CONTRAST__GPIO1_1                              IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL)
+#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2        IOMUX_PAD(0x680, 0x21c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18                  IOMUX_PAD(0x680, 0x21c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC                   IOMUX_PAD(0x684, 0x220, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1                        IOMUX_PAD(0x684, 0x220, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_VSYNC__GPIO1_2                              IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL)
+#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD                     IOMUX_PAD(0x684, 0x220, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19                  IOMUX_PAD(0x684, 0x220, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV                       IOMUX_PAD(0x688, 0x224, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS                       IOMUX_PAD(0x688, 0x224, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_REV__GPIO1_3                                IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL)
+#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB                     IOMUX_PAD(0x688, 0x224, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20                    IOMUX_PAD(0x688, 0x224, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS                       IOMUX_PAD(0x68c, 0x228, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_CLS__IPU_DISPB_CS2                          IOMUX_PAD(0x68c, 0x228, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_CLS__GPIO1_4                                IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL)
+#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0                IOMUX_PAD(0x68c, 0x228, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21                    IOMUX_PAD(0x68c, 0x228, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL                       IOMUX_PAD(0x690, 0x22c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC                    IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL)
+#define MX35_PAD_D3_SPL__GPIO1_5                                IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL)
+#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1                IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22                    IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__ESDHC1_CMD                            IOMUX_PAD(0x694, 0x230, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__MSHC_SCLK                             IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC                    IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4                 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__GPIO1_6                               IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL                      IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__ESDHC1_CLK                            IOMUX_PAD(0x698, 0x234, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__MSHC_BS                               IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK                        IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5                 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__GPIO1_7                               IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK                      IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0                         IOMUX_PAD(0x69c, 0x238, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__MSHC_DATA_0                         IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0                       IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6               IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__GPIO1_8                             IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23                 IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1                         IOMUX_PAD(0x6a0, 0x23c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__MSHC_DATA_1                         IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS                    IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0               IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__GPIO1_9                             IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24                 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2                         IOMUX_PAD(0x6a4, 0x240, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__MSHC_DATA_2                         IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR                        IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1               IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__GPIO1_10                            IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25                 IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3                         IOMUX_PAD(0x6a8, 0x244, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__MSHC_DATA_3                         IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD                        IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2               IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__GPIO1_11                            IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26                 IOMUX_PAD(0x6a8, 0x244, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__ESDHC2_CMD                            IOMUX_PAD(0x6ac, 0x248, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__I2C3_SCL                              IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__ESDHC1_DAT4                           IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__IPU_CSI_D_2                           IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4                  IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__GPIO2_0                               IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1                      IOMUX_PAD(0x6ac, 0x248, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC                   IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__ESDHC2_CLK                            IOMUX_PAD(0x6b0, 0x24c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__I2C3_SDA                              IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__ESDHC1_DAT5                           IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__IPU_CSI_D_3                           IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5                  IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__GPIO2_1                               IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1                       IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL)
+#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2                         IOMUX_PAD(0x6b0, 0x24c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0                         IOMUX_PAD(0x6b4, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX                       IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6                         IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4                         IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6                IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA0__GPIO2_2                             IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK                  IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1                         IOMUX_PAD(0x6b8, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX                       IOMUX_PAD(0x6b8, 0x254, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7                         IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5                         IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0                IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA1__GPIO2_3                             IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2                         IOMUX_PAD(0x6bc, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA2__UART3_RTS                           IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA2__CAN1_RXCAN                          IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6                         IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1                IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA2__GPIO2_4                             IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3                         IOMUX_PAD(0x6c0, 0x25c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA3__UART3_CTS                           IOMUX_PAD(0x6c0, 0x25c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA3__CAN1_TXCAN                          IOMUX_PAD(0x6c0, 0x25c, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7                         IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2                IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD2_DATA3__GPIO2_5                             IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS0__ATA_CS0                               IOMUX_PAD(0x6c4, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS0__CSPI1_SS3                             IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1                         IOMUX_PAD(0x6c4, 0x260, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS0__GPIO2_6                               IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS0__IPU_DIAGB_0                           IOMUX_PAD(0x6c4, 0x260, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0             IOMUX_PAD(0x6c4, 0x260, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS1__ATA_CS1                               IOMUX_PAD(0x6c8, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2                         IOMUX_PAD(0x6c8, 0x264, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS1__CSPI2_SS0                             IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS1__GPIO2_7                               IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS1__IPU_DIAGB_1                           IOMUX_PAD(0x6c8, 0x264, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1             IOMUX_PAD(0x6c8, 0x264, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__ATA_DIOR                             IOMUX_PAD(0x6cc, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0                          IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR                   IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0                        IOMUX_PAD(0x6cc, 0x268, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__CSPI2_SS1                            IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__GPIO2_8                              IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2                          IOMUX_PAD(0x6cc, 0x268, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2            IOMUX_PAD(0x6cc, 0x268, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__ATA_DIOW                             IOMUX_PAD(0x6d0, 0x26c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1                          IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP                   IOMUX_PAD(0x6d0, 0x26c, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1                        IOMUX_PAD(0x6d0, 0x26c, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__CSPI2_MOSI                           IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__GPIO2_9                              IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3                          IOMUX_PAD(0x6d0, 0x26c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3            IOMUX_PAD(0x6d0, 0x26c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMACK__ATA_DMACK                           IOMUX_PAD(0x6d4, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2                         IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT                  IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMACK__CSPI2_MISO                          IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMACK__GPIO2_10                            IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4                         IOMUX_PAD(0x6d4, 0x270, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0           IOMUX_PAD(0x6d4, 0x270, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__ATA_RESET_B                       IOMUX_PAD(0x6d8, 0x274, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3                       IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0             IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O                  IOMUX_PAD(0x6d8, 0x274, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__CSPI2_RDY                         IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__GPIO2_11                          IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5                       IOMUX_PAD(0x6d8, 0x274, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1         IOMUX_PAD(0x6d8, 0x274, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__ATA_IORDY                           IOMUX_PAD(0x6dc, 0x278, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4                         IOMUX_PAD(0x6dc, 0x278, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1               IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO                   IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4                         IOMUX_PAD(0x6dc, 0x278, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__GPIO2_12                            IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6                         IOMUX_PAD(0x6dc, 0x278, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2           IOMUX_PAD(0x6dc, 0x278, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__ATA_DATA_0                          IOMUX_PAD(0x6e0, 0x27c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5                         IOMUX_PAD(0x6e0, 0x27c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2               IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC                 IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5                         IOMUX_PAD(0x6e0, 0x27c, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__GPIO2_13                            IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7                         IOMUX_PAD(0x6e0, 0x27c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3           IOMUX_PAD(0x6e0, 0x27c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__ATA_DATA_1                          IOMUX_PAD(0x6e4, 0x280, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6                         IOMUX_PAD(0x6e4, 0x280, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3               IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK                    IOMUX_PAD(0x6e4, 0x280, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6                         IOMUX_PAD(0x6e4, 0x280, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__GPIO2_14                            IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8                         IOMUX_PAD(0x6e4, 0x280, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27                 IOMUX_PAD(0x6e4, 0x280, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__ATA_DATA_2                          IOMUX_PAD(0x6e8, 0x284, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7                         IOMUX_PAD(0x6e8, 0x284, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4               IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS                    IOMUX_PAD(0x6e8, 0x284, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7                         IOMUX_PAD(0x6e8, 0x284, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__GPIO2_15                            IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9                         IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28                 IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ATA_DATA_3                          IOMUX_PAD(0x6e8, 0x288, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ESDHC3_CLK                          IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__CSPI2_SCLK                          IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__GPIO2_16                            IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        IOMUX_PAD(0x6e8, 0x288, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 IOMUX_PAD(0x6e8, 0x288, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA4__ATA_DATA_4                          IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA4__ESDHC3_CMD                          IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6               IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA4__GPIO2_17                            IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11                        IOMUX_PAD(0x6f0, 0x28c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30                 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA5__ATA_DATA_5                          IOMUX_PAD(0x6f4, 0x290, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7               IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA5__GPIO2_18                            IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12                        IOMUX_PAD(0x6f4, 0x290, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31                 IOMUX_PAD(0x6f4, 0x290, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA6__ATA_DATA_6                          IOMUX_PAD(0x6f8, 0x294, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA6__CAN1_TXCAN                          IOMUX_PAD(0x6f8, 0x294, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA6__UART1_DTR                           IOMUX_PAD(0x6f8, 0x294, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD                     IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA6__GPIO2_19                            IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13                        IOMUX_PAD(0x6f8, 0x294, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA7__ATA_DATA_7                          IOMUX_PAD(0x6fc, 0x298, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA7__CAN1_RXCAN                          IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA7__UART1_DSR                           IOMUX_PAD(0x6fc, 0x298, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD                     IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA7__GPIO2_20                            IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14                        IOMUX_PAD(0x6fc, 0x298, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA8__ATA_DATA_8                          IOMUX_PAD(0x700, 0x29c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA8__UART3_RTS                           IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA8__UART1_RI                            IOMUX_PAD(0x700, 0x29c, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC                     IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA8__GPIO2_21                            IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15                        IOMUX_PAD(0x700, 0x29c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA9__ATA_DATA_9                          IOMUX_PAD(0x704, 0x2a0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA9__UART3_CTS                           IOMUX_PAD(0x704, 0x2a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA9__UART1_DCD                           IOMUX_PAD(0x704, 0x2a0, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS                    IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA9__GPIO2_22                            IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16                        IOMUX_PAD(0x704, 0x2a0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA10__ATA_DATA_10                        IOMUX_PAD(0x708, 0x2a4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX                      IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC                    IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA10__GPIO2_23                           IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17                       IOMUX_PAD(0x708, 0x2a4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA11__ATA_DATA_11                        IOMUX_PAD(0x70c, 0x2a8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX                      IOMUX_PAD(0x70c, 0x2a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS                   IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA11__GPIO2_24                           IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18                       IOMUX_PAD(0x70c, 0x2a8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA12__ATA_DATA_12                        IOMUX_PAD(0x710, 0x2ac, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA12__I2C3_SCL                           IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA12__GPIO2_25                           IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19                       IOMUX_PAD(0x710, 0x2ac, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA13__ATA_DATA_13                        IOMUX_PAD(0x714, 0x2b0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA13__I2C3_SDA                           IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA13__GPIO2_26                           IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20                       IOMUX_PAD(0x714, 0x2b0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA14__ATA_DATA_14                        IOMUX_PAD(0x718, 0x2b4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0                        IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA14__KPP_ROW_0                          IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA14__GPIO2_27                           IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21                       IOMUX_PAD(0x718, 0x2b4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA15__ATA_DATA_15                        IOMUX_PAD(0x71c, 0x2b8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1                        IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA15__KPP_ROW_1                          IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA15__GPIO2_28                           IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22                       IOMUX_PAD(0x71c, 0x2b8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_INTRQ__ATA_INTRQ                           IOMUX_PAD(0x720, 0x2bc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2                         IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL)
+#define MX35_PAD_ATA_INTRQ__KPP_ROW_2                           IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_INTRQ__GPIO2_29                            IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23                        IOMUX_PAD(0x720, 0x2bc, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN                     IOMUX_PAD(0x724, 0x2c0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3                       IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL)
+#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3                         IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_BUFF_EN__GPIO2_30                          IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24                      IOMUX_PAD(0x724, 0x2c0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMARQ__ATA_DMARQ                           IOMUX_PAD(0x728, 0x2c4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4                         IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMARQ__KPP_COL_0                           IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMARQ__GPIO2_31                            IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25                        IOMUX_PAD(0x728, 0x2c4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4                  IOMUX_PAD(0x728, 0x2c4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA0__ATA_DA_0                              IOMUX_PAD(0x72c, 0x2c8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA0__IPU_CSI_D_5                           IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA0__KPP_COL_1                             IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA0__GPIO3_0                               IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA0__IPU_DIAGB_26                          IOMUX_PAD(0x72c, 0x2c8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5                    IOMUX_PAD(0x72c, 0x2c8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA1__ATA_DA_1                              IOMUX_PAD(0x730, 0x2cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA1__IPU_CSI_D_6                           IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA1__KPP_COL_2                             IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA1__GPIO3_1                               IOMUX_PAD(0x730, 0x2cc, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA1__IPU_DIAGB_27                          IOMUX_PAD(0x730, 0x2cc, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6                    IOMUX_PAD(0x730, 0x2cc, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA2__ATA_DA_2                              IOMUX_PAD(0x734, 0x2d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA2__IPU_CSI_D_7                           IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA2__KPP_COL_3                             IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA2__GPIO3_2                               IOMUX_PAD(0x734, 0x2d0, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA2__IPU_DIAGB_28                          IOMUX_PAD(0x734, 0x2d0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7                    IOMUX_PAD(0x734, 0x2d0, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_MLB_CLK__MLB_MLBCLK                            IOMUX_PAD(0x738, 0x2d4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_MLB_CLK__GPIO3_3                               IOMUX_PAD(0x738, 0x2d4, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_MLB_DAT__MLB_MLBDAT                            IOMUX_PAD(0x73c, 0x2d8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_MLB_DAT__GPIO3_4                               IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL)
+#define MX35_PAD_MLB_SIG__MLB_MLBSIG                            IOMUX_PAD(0x740, 0x2dc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_MLB_SIG__GPIO3_5                               IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK                         IOMUX_PAD(0x744, 0x2e0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4                        IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX                      IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR                  IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI                         IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__GPIO3_6                            IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC                IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0               IOMUX_PAD(0x744, 0x2e0, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK                         IOMUX_PAD(0x748, 0x2e4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5                        IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX                      IOMUX_PAD(0x748, 0x2e4, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP                  IOMUX_PAD(0x748, 0x2e4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO                         IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__GPIO3_7                            IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I                   IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1               IOMUX_PAD(0x748, 0x2e4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__FEC_RX_DV                           IOMUX_PAD(0x74c, 0x2e8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6                         IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__UART3_RTS                           IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT                   IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK                          IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__GPIO3_8                             IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK                    IOMUX_PAD(0x74c, 0x2e8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2                IOMUX_PAD(0x74c, 0x2e8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__FEC_COL                               IOMUX_PAD(0x750, 0x2ec, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__ESDHC1_DAT7                           IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__UART3_CTS                             IOMUX_PAD(0x750, 0x2ec, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0                  IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__CSPI2_RDY                             IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__GPIO3_9                               IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS                      IOMUX_PAD(0x750, 0x2ec, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3                  IOMUX_PAD(0x750, 0x2ec, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0                        IOMUX_PAD(0x754, 0x2f0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__PWM_PWMO                           IOMUX_PAD(0x754, 0x2f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__UART3_DTR                          IOMUX_PAD(0x754, 0x2f0, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1               IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__CSPI2_SS0                          IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__GPIO3_10                           IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1                      IOMUX_PAD(0x754, 0x2f0, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4               IOMUX_PAD(0x754, 0x2f0, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0                        IOMUX_PAD(0x758, 0x2f4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1                   IOMUX_PAD(0x758, 0x2f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__UART3_DSR                          IOMUX_PAD(0x758, 0x2f4, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2               IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__CSPI2_SS1                          IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__GPIO3_11                           IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0                      IOMUX_PAD(0x758, 0x2f4, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5               IOMUX_PAD(0x758, 0x2f4, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_EN__FEC_TX_EN                           IOMUX_PAD(0x75c, 0x2f8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1                     IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_EN__UART3_RI                            IOMUX_PAD(0x75c, 0x2f8, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3                IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_EN__GPIO3_12                            IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS                    IOMUX_PAD(0x75c, 0x2f8, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6                IOMUX_PAD(0x75c, 0x2f8, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDC__FEC_MDC                               IOMUX_PAD(0x760, 0x2fc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDC__CAN2_TXCAN                            IOMUX_PAD(0x760, 0x2fc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDC__UART3_DCD                             IOMUX_PAD(0x760, 0x2fc, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4                  IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDC__GPIO3_13                              IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDC__IPU_DISPB_WR                          IOMUX_PAD(0x760, 0x2fc, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7                  IOMUX_PAD(0x760, 0x2fc, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDIO__FEC_MDIO                             IOMUX_PAD(0x764, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDIO__CAN2_RXCAN                           IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5                 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDIO__GPIO3_14                             IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD                         IOMUX_PAD(0x764, 0x300, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8                 IOMUX_PAD(0x764, 0x300, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR                         IOMUX_PAD(0x768, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE                         IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK                 IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6               IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_ERR__GPIO3_15                           IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC                 IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9               IOMUX_PAD(0x768, 0x304, 7, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR                         IOMUX_PAD(0x76c, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0                        IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7               IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_ERR__KPP_COL_4                          IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_ERR__GPIO3_16                           IOMUX_PAD(0x76c, 0x308, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO                  IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL)
+#define MX35_PAD_FEC_CRS__FEC_CRS                               IOMUX_PAD(0x770, 0x30c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_CRS__IPU_CSI_D_1                           IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR                     IOMUX_PAD(0x770, 0x30c, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_CRS__KPP_COL_5                             IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_CRS__GPIO3_17                              IOMUX_PAD(0x770, 0x30c, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE                      IOMUX_PAD(0x770, 0x30c, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1                        IOMUX_PAD(0x774, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2                        IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC                    IOMUX_PAD(0x774, 0x310, 2, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC                   IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA1__KPP_COL_6                          IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA1__GPIO3_18                           IOMUX_PAD(0x774, 0x310, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0                      IOMUX_PAD(0x774, 0x310, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1                        IOMUX_PAD(0x778, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3                        IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS                   IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA1__KPP_COL_7                          IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA1__GPIO3_19                           IOMUX_PAD(0x778, 0x314, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1                      IOMUX_PAD(0x778, 0x314, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2                        IOMUX_PAD(0x77c, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4                        IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD                    IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA2__KPP_ROW_4                          IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA2__GPIO3_20                           IOMUX_PAD(0x77c, 0x318, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2                        IOMUX_PAD(0x780, 0x31c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5                        IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD                    IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA2__KPP_ROW_5                          IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA2__GPIO3_21                           IOMUX_PAD(0x780, 0x31c, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3                        IOMUX_PAD(0x784, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6                        IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC                    IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA3__KPP_ROW_6                          IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_RDATA3__GPIO3_22                           IOMUX_PAD(0x784, 0x320, 6, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3                        IOMUX_PAD(0x788, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7                        IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS                   IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA3__KPP_ROW_7                          IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL)
+#define MX35_PAD_FEC_TDATA3__GPIO3_23                           IOMUX_PAD(0x788, 0x324, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK                     IOMUX_PAD(0x78c, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#define MX35_PAD_TEST_MODE__TCU_TEST_MODE                       IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL)
+#endif /* __MACH_IOMUX_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
new file mode 100644
index 000000000000..7cd84547658f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                      <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_IOMUX_V3_H__
+#define __MACH_IOMUX_V3_H__
+/*
+ *      build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ *   things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ *   (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ *   (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named
+ * GPIO_<unit>_<num>
+ *
+ */
+struct pad_desc {
+        unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */
+        unsigned mux_mode:8;
+        unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */
+#define NO_PAD_CTRL     (1 << 16)
+        unsigned pad_ctrl:17;
+        unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */
+        unsigned select_input:3;
+};
+#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \
+                _select_input, _pad_ctrl)                               \
+                {                                                       \
+                        .mux_ctrl_ofs     = _mux_ctrl_ofs,              \
+                        .mux_mode         = _mux_mode,                  \
+                        .pad_ctrl_ofs     = _pad_ctrl_ofs,              \
+                        .pad_ctrl         = _pad_ctrl,                  \
+                        .select_input_ofs = _select_input_ofs,          \
+                        .select_input     = _select_input,              \
+                }
+/*
+ * Use to set PAD control
+ */
+#define PAD_CTL_DRIVE_VOLTAGE_3_3_V     0
+#define PAD_CTL_DRIVE_VOLTAGE_1_8_V     1
+#define PAD_CTL_NO_HYSTERESIS           0
+#define PAD_CTL_HYSTERESIS              1
+#define PAD_CTL_PULL_DISABLED           0x0
+#define PAD_CTL_PULL_KEEPER             0xa
+#define PAD_CTL_PULL_DOWN_100K          0xc
+#define PAD_CTL_PULL_UP_47K             0xd
+#define PAD_CTL_PULL_UP_100K            0xe
+#define PAD_CTL_PULL_UP_22K             0xf
+#define PAD_CTL_OUTPUT_CMOS             0
+#define PAD_CTL_OUTPUT_OPEN_DRAIN       1
+#define PAD_CTL_DRIVE_STRENGTH_NORM     0
+#define PAD_CTL_DRIVE_STRENGTH_HIGH     1
+#define PAD_CTL_DRIVE_STRENGTH_MAX      2
+#define PAD_CTL_SLEW_RATE_SLOW          0
+#define PAD_CTL_SLEW_RATE_FAST          1
+/*
+ * setups a single pad:
+ *      - reserves the pad so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ */
+int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
+/*
+ * setups mutliple pads
+ * convenient way to call the above function with tables
+ */
+int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
+/*
+ * releases a single pad:
+ *      - make it available for a future use by another driver
+ *      - DOES NOT reconfigure the IOMUX in its reset state
+ */
+void mxc_iomux_v3_release_pad(struct pad_desc *pad);
+/*
+ * releases multiple pads
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
+#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index eca37d09f3f8..6065e00176ed 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -32,4 +32,12 @@
 #define CONSISTENT_DMA_SIZE SZ_4M
 #endif /* CONFIG_MX1_VIDEO */
+#if defined(CONFIG_MX3_VIDEO)
+/*
+ * Increase size of DMA-consistent memory region.
+ * This is required for mx3 camera driver to capture at least two QXGA frames.
+ */
+#define CONSISTENT_DMA_SIZE SZ_8M
+#endif /* CONFIG_MX3_VIDEO */
 #endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index b92e02324d8e..1000bf330bcd 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -179,7 +179,7 @@
 #define DMA_REQ_UART1_T         30
 #define DMA_REQ_UART1_R         31
-/* mandatory for CONFIG_LL_DEBUG */
+/* mandatory for CONFIG_DEBUG_LL */
 #define MXC_LL_UART_PADDR       UART1_BASE_ADDR
 #define MXC_LL_UART_VADDR       IO_ADDRESS(UART1_BASE_ADDR)
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 3878c6085d5c..b559a4bb5769 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -48,6 +48,9 @@
 #define CS4_SIZE                SZ_32M
 #define CS5_BASE_ADDR           0xB6000000
+#define CS5_BASE_ADDR_VIRT      0xF6000000
+#define CS5_SIZE                SZ_32M
 #define PCMCIA_MEM_BASE_ADDR    0xBC000000
 /*
@@ -191,6 +194,9 @@
 #define CS4_IO_ADDRESS(x)  \
        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+#define CS5_IO_ADDRESS(x)  \
+        (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
 #define X_MEMC_IO_ADDRESS(x)  \
        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h
deleted file mode 100644
index 6c19a134744b..000000000000
--- a/arch/arm/plat-mxc/include/mach/mxc_timer.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * mxc_timer.h
- *
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-#ifndef __PLAT_MXC_TIMER_H
-#define __PLAT_MXC_TIMER_H
-#include <linux/clk.h>
-#include <mach/hardware.h>
-#ifdef CONFIG_ARCH_MX1
-#define TIMER_BASE              IO_ADDRESS(TIM1_BASE_ADDR)
-#define TIMER_INTERRUPT         TIM1_INT
-#define TCTL_VAL                TCTL_CLK_PCLK1
-#define TCTL_IRQEN              (1<<4)
-#define TCTL_FRR                (1<<8)
-#define TCTL_CLK_PCLK1          (1<<1)
-#define TCTL_CLK_PCLK1_4        (2<<1)
-#define TCTL_CLK_TIN            (3<<1)
-#define TCTL_CLK_32             (4<<1)
-#define MXC_TCTL   0x00
-#define MXC_TPRER  0x04
-#define MXC_TCMP   0x08
-#define MXC_TCR    0x0c
-#define MXC_TCN    0x10
-#define MXC_TSTAT  0x14
-#define TSTAT_CAPT              (1<<1)
-#define TSTAT_COMP              (1<<0)
-static inline void gpt_irq_disable(void)
-{
-        unsigned int tmp;
-        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
-        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
-}
-static inline void gpt_irq_enable(void)
-{
-        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
-                                TIMER_BASE + MXC_TCTL);
-}
-static void gpt_irq_acknowledge(void)
-{
-        __raw_writel(0, TIMER_BASE + MXC_TSTAT);
-}
-#endif /* CONFIG_ARCH_MX1 */
-#ifdef CONFIG_ARCH_MX2
-#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
-#define TIMER_INTERRUPT         MXC_INT_GPT1
-#define MXC_TCTL   0x00
-#define TCTL_VAL                TCTL_CLK_PCLK1
-#define TCTL_CLK_PCLK1          (1<<1)
-#define TCTL_CLK_PCLK1_4        (2<<1)
-#define TCTL_IRQEN              (1<<4)
-#define TCTL_FRR                (1<<8)
-#define MXC_TPRER  0x04
-#define MXC_TCMP   0x08
-#define MXC_TCR    0x0c
-#define MXC_TCN    0x10
-#define MXC_TSTAT  0x14
-#define TSTAT_CAPT              (1<<1)
-#define TSTAT_COMP              (1<<0)
-static inline void gpt_irq_disable(void)
-{
-        unsigned int tmp;
-        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
-        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
-}
-static inline void gpt_irq_enable(void)
-{
-        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
-                                TIMER_BASE + MXC_TCTL);
-}
-static void gpt_irq_acknowledge(void)
-{
-        __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
-}
-#endif /* CONFIG_ARCH_MX2 */
-#ifdef CONFIG_ARCH_MX3
-#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
-#define TIMER_INTERRUPT         MXC_INT_GPT
-#define MXC_TCTL   0x00
-#define TCTL_VAL                (TCTL_CLK_IPG | TCTL_WAITEN)
-#define TCTL_CLK_IPG            (1<<6)
-#define TCTL_FRR                (1<<9)
-#define TCTL_WAITEN             (1<<3)
-#define MXC_TPRER  0x04
-#define MXC_TSTAT  0x08
-#define TSTAT_OF1               (1<<0)
-#define TSTAT_OF2               (1<<1)
-#define TSTAT_OF3               (1<<2)
-#define TSTAT_IF1               (1<<3)
-#define TSTAT_IF2               (1<<4)
-#define TSTAT_ROV               (1<<5)
-#define MXC_IR     0x0c
-#define MXC_TCMP   0x10
-#define MXC_TCMP2  0x14
-#define MXC_TCMP3  0x18
-#define MXC_TCR    0x1c
-#define MXC_TCN    0x24
-static inline void gpt_irq_disable(void)
-{
-        __raw_writel(0, TIMER_BASE + MXC_IR);
-}
-static inline void gpt_irq_enable(void)
-{
-        __raw_writel(1<<0, TIMER_BASE + MXC_IR);
-}
-static inline void gpt_irq_acknowledge(void)
-{
-        __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
-}
-#endif /* CONFIG_ARCH_MX3 */
-#define TCTL_SWR                (1<<15)
-#define TCTL_CC                 (1<<10)
-#define TCTL_OM                 (1<<9)
-#define TCTL_CAP_RIS            (1<<6)
-#define TCTL_CAP_FAL            (2<<6)
-#define TCTL_CAP_RIS_FAL        (3<<6)
-#define TCTL_CAP_ENA            (1<<5)
-#define TCTL_TEN                (1<<0)
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/usb.h b/arch/arm/plat-mxc/include/mach/usb.h
index 2dacb3086f1c..be273371f34a 100644
--- a/arch/arm/plat-mxc/include/mach/usb.h
+++ b/arch/arm/plat-mxc/include/mach/usb.h
@@ -17,7 +17,7 @@
 struct imxusb_platform_data {
        int (*init)(struct device *);
-        int (*exit)(struct device *);
+        void (*exit)(struct device *);
 };
 #endif /* __ASM_ARCH_MXC_USB */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
new file mode 100644
index 000000000000..77a078f9513f
--- /dev/null
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <asm/mach/map.h>
+#include <mach/iomux-v3.h>
+#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
+static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
+/*
+ * setups a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ */
+int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
+{
+        unsigned int pad_ofs = pad->pad_ctrl_ofs;
+        if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
+                return -EBUSY;
+        if (pad->mux_ctrl_ofs)
+                __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs);
+        if (pad->select_input_ofs)
+                __raw_writel(pad->select_input,
+                                IOMUX_BASE + pad->select_input_ofs);
+        if (!(pad->pad_ctrl & NO_PAD_CTRL))
+                __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs);
+        return 0;
+}
+EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
+int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
+{
+        struct pad_desc *p = pad_list;
+        int i;
+        int ret;
+        for (i = 0; i < count; i++) {
+                ret = mxc_iomux_v3_setup_pad(p);
+                if (ret)
+                        goto setup_error;
+                p++;
+        }
+        return 0;
+setup_error:
+        mxc_iomux_v3_release_multiple_pads(pad_list, i);
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
+void mxc_iomux_v3_release_pad(struct pad_desc *pad)
+{
+        unsigned int pad_ofs = pad->pad_ctrl_ofs;
+        clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
+}
+EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
+void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
+{
+        struct pad_desc *p = pad_list;
+        int i;
+        for (i = 0; i < count; i++) {
+                mxc_iomux_v3_release_pad(p);
+                p++;
+        }
+}
+EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 0fb68a531f55..8aee76304f8f 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -24,31 +24,27 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL            0x00    /* int control reg */
-#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK             0x04    /* int mask reg */
-#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM           0x08    /* int enable number reg */
-#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM          0x0C    /* int disable number reg */
-#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH         0x10    /* int enable reg high */
-#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL         0x14    /* int enable reg low */
-#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH           0x18    /* int type reg high */
-#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL           0x1C    /* int type reg low */
-#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
-#define AVIC_NIPRIORITY(x)      (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
+#define AVIC_NIVECSR            0x40    /* norm int vector/status */
-#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR            0x44    /* fast int vector/status */
-#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH            0x48    /* int source reg high */
-#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL            0x4C    /* int source reg low */
-#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH            0x50    /* int force reg high */
-#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL            0x54    /* int force reg low */
-#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH             0x58    /* norm int pending high */
-#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL             0x5C    /* norm int pending low */
-#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH             0x60    /* fast int pending high */
-#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL             0x64    /* fast int pending low */
-#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
+static void __iomem *avic_base;
-#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
-#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
-#define IIM_PROD_REV_SH         3
-#define IIM_PROD_REV_LEN        5
 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -59,11 +55,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio)
        if (irq >= MXC_INTERNAL_IRQS)
                return -EINVAL;;
-        temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
+        temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
        temp &= ~mask;
        temp |= prio & mask;
-        __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
+        __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
        return 0;
 #else
@@ -81,12 +77,12 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
                return -EINVAL;
        if (irq < MXC_INTERNAL_IRQS / 2) {
-                irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
+                irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
-                __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
+                __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
        } else {
                irq -= MXC_INTERNAL_IRQS / 2;
-                irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
+                irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
-                __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
+                __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
        }
        return 0;
@@ -97,13 +93,13 @@ EXPORT_SYMBOL(mxc_set_irq_fiq);
 /* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
-        __raw_writel(irq, AVIC_INTDISNUM);
+        __raw_writel(irq, avic_base + AVIC_INTDISNUM);
 }
 /* Enable interrupt number "irq" in the AVIC */
 static void mxc_unmask_irq(unsigned int irq)
 {
-        __raw_writel(irq, AVIC_INTENNUM);
+        __raw_writel(irq, avic_base + AVIC_INTENNUM);
 }
 static struct irq_chip mxc_avic_chip = {
@@ -121,19 +117,21 @@ void __init mxc_init_irq(void)
 {
        int i;
+        avic_base = IO_ADDRESS(AVIC_BASE_ADDR);
        /* put the AVIC into the reset value with
         * all interrupts disabled
         */
-        __raw_writel(0, AVIC_INTCNTL);
+        __raw_writel(0, avic_base + AVIC_INTCNTL);
-        __raw_writel(0x1f, AVIC_NIMASK);
+        __raw_writel(0x1f, avic_base + AVIC_NIMASK);
        /* disable all interrupts */
-        __raw_writel(0, AVIC_INTENABLEH);
+        __raw_writel(0, avic_base + AVIC_INTENABLEH);
-        __raw_writel(0, AVIC_INTENABLEL);
+        __raw_writel(0, avic_base + AVIC_INTENABLEL);
        /* all IRQ no FIQ */
-        __raw_writel(0, AVIC_INTTYPEH);
+        __raw_writel(0, avic_base + AVIC_INTTYPEH);
-        __raw_writel(0, AVIC_INTTYPEL);
+        __raw_writel(0, avic_base + AVIC_INTTYPEL);
        for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
                set_irq_chip(i, &mxc_avic_chip);
                set_irq_handler(i, handle_level_irq);
@@ -142,7 +140,7 @@ void __init mxc_init_irq(void)
        /* Set default priority value (0) for all IRQ's */
        for (i = 0; i < 8; i++)
-                __raw_writel(0, AVIC_NIPRIORITY(i));
+                __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
        /* init architectures chained interrupt handler */
        mxc_register_gpios();
@@ -154,3 +152,4 @@ void __init mxc_init_irq(void)
        printk(KERN_INFO "MXC IRQ initialized\n");
 }
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 9bffbc507cc2..ae34198a79dd 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -15,65 +15,26 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/pwm.h>
+#include <mach/hardware.h>
+/* i.MX1 and i.MX21 share the same PWM function block: */
+#define MX1_PWMC    0x00   /* PWM Control Register */
+#define MX1_PWMS    0x04   /* PWM Sample Register */
+#define MX1_PWMP    0x08   /* PWM Period Register */
+/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
+#define MX3_PWMCR                 0x00    /* PWM Control Register */
+#define MX3_PWMSAR                0x0C    /* PWM Sample Register */
+#define MX3_PWMPR                 0x10    /* PWM Period Register */
+#define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
+#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define MX3_PWMCR_EN              (1 << 0)
-#if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21
-#define PWM_VER_1
-#define PWMCR   0x00    /* PWM Control Register         */
-#define PWMSR   0x04    /* PWM Sample Register          */
-#define PWMPR   0x08    /* PWM Period Register          */
-#define PWMCNR  0x0C    /* PWM Counter Register         */
-#define PWMCR_HCTR              (1 << 18)               /* Halfword FIFO Data Swapping  */
-#define PWMCR_BCTR              (1 << 17)               /* Byte FIFO Data Swapping      */
-#define PWMCR_SWR               (1 << 16)               /* Software Reset               */
-#define PWMCR_CLKSRC_PERCLK     (0 << 15)               /* PERCLK Clock Source          */
-#define PWMCR_CLKSRC_CLK32      (1 << 15)               /* 32KHz Clock Source           */
-#define PWMCR_PRESCALER(x)      (((x - 1) & 0x7F) << 8) /* PRESCALER                    */
-#define PWMCR_IRQ               (1 << 7)                /* Interrupt Request            */
-#define PWMCR_IRQEN             (1 << 6)                /* Interrupt Request Enable     */
-#define PWMCR_FIFOAV            (1 << 5)                /* FIFO Available               */
-#define PWMCR_EN                (1 << 4)                /* Enables/Disables the PWM     */
-#define PWMCR_REPEAT(x)         (((x) & 0x03) << 2)     /* Sample Repeats               */
-#define PWMCR_DIV(x)            (((x) & 0x03) << 0)     /* Clock divider 2/4/8/16       */
-#define MAX_DIV                 (128 * 16)
-#endif
-#if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31
-#define PWM_VER_2
-#define PWMCR   0x00    /* PWM Control Register         */
-#define PWMSR   0x04    /* PWM Status Register          */
-#define PWMIR   0x08    /* PWM Interrupt Register       */
-#define PWMSAR  0x0C    /* PWM Sample Register          */
-#define PWMPR   0x10    /* PWM Period Register          */
-#define PWMCNR  0x14    /* PWM Counter Register         */
-#define PWMCR_EN                (1 << 0)                /* Enables/Disables the PWM     */
-#define PWMCR_REPEAT(x)         (((x) & 0x03) << 1)     /* Sample Repeats               */
-#define PWMCR_SWR               (1 << 3)                /* Software Reset               */
-#define PWMCR_PRESCALER(x)      (((x - 1) & 0xFFF) << 4)/* PRESCALER                    */
-#define PWMCR_CLKSRC(x)         (((x) & 0x3) << 16)
-#define PWMCR_CLKSRC_OFF        (0 << 16)
-#define PWMCR_CLKSRC_IPG        (1 << 16)
-#define PWMCR_CLKSRC_IPG_HIGH   (2 << 16)
-#define PWMCR_CLKSRC_CLK32      (3 << 16)
-#define PWMCR_POUTC
-#define PWMCR_HCTR              (1 << 20)               /* Halfword FIFO Data Swapping  */
-#define PWMCR_BCTR              (1 << 21)               /* Byte FIFO Data Swapping      */
-#define PWMCR_DBGEN             (1 << 22)               /* Debug Mode                   */
-#define PWMCR_WAITEN            (1 << 23)               /* Wait Mode                    */
-#define PWMCR_DOZEN             (1 << 24)               /* Doze Mode                    */
-#define PWMCR_STOPEN            (1 << 25)               /* Stop Mode                    */
-#define PWMCR_FWM(x)            (((x) & 0x3) << 26)     /* FIFO Water Mark              */
-#define MAX_DIV 4096
-#endif
-#define PWMS_SAMPLE(x)          ((x) & 0xFFFF)          /* Contains a two-sample word   */
-#define PWMP_PERIOD(x)          ((x) & 0xFFFF)          /* Represents the PWM's period  */
-#define PWMC_COUNTER(x)         ((x) & 0xFFFF)          /* Represents the current count value   */
 struct pwm_device {
        struct list_head        node;
@@ -91,32 +52,52 @@ struct pwm_device {
 int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 {
-        unsigned long long c;
-        unsigned long period_cycles, duty_cycles, prescale;
        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
                return -EINVAL;
-        c = clk_get_rate(pwm->clk);
+        if (cpu_is_mx27() || cpu_is_mx3()) {
-        c = c * period_ns;
+                unsigned long long c;
-        do_div(c, 1000000000);
+                unsigned long period_cycles, duty_cycles, prescale;
-        period_cycles = c;
+                c = clk_get_rate(pwm->clk);
+                c = c * period_ns;
-        prescale = period_cycles / 0x10000 + 1;
+                do_div(c, 1000000000);
+                period_cycles = c;
-        period_cycles /= prescale;
-        c = (unsigned long long)period_cycles * duty_ns;
+                prescale = period_cycles / 0x10000 + 1;
-        do_div(c, period_ns);
-        duty_cycles = c;
+                period_cycles /= prescale;
+                c = (unsigned long long)period_cycles * duty_ns;
-#ifdef PWM_VER_2
+                do_div(c, period_ns);
-        writel(duty_cycles, pwm->mmio_base + PWMSAR);
+                duty_cycles = c;
-        writel(period_cycles, pwm->mmio_base + PWMPR);
-        writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN,
+                writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
-                        pwm->mmio_base + PWMCR);
+                writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
-#elif defined PWM_VER_1
+                writel(MX3_PWMCR_PRESCALER(prescale - 1) |
-#error PWM not yet working on MX1 / MX21
+                        MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN,
-#endif
+                        pwm->mmio_base + MX3_PWMCR);
+        } else if (cpu_is_mx1() || cpu_is_mx21()) {
+                /* The PWM subsystem allows for exact frequencies. However,
+                 * I cannot connect a scope on my device to the PWM line and
+                 * thus cannot provide the program the PWM controller
+                 * exactly. Instead, I'm relying on the fact that the
+                 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
+                 * function group already. So I'll just modify the PWM sample
+                 * register to follow the ratio of duty_ns vs. period_ns
+                 * accordingly.
+                 *
+                 * This is good enought for programming the brightness of
+                 * the LCD backlight.
+                 *
+                 * The real implementation would divide PERCLK[0] first by
+                 * both the prescaler (/1 .. /128) and then by CLKSEL
+                 * (/2 .. /16).
+                 */
+                u32 max = readl(pwm->mmio_base + MX1_PWMP);
+                u32 p = max * duty_ns / period_ns;
+                writel(max - p, pwm->mmio_base + MX1_PWMS);
+        } else {
+                BUG();
+        }
        return 0;
 }
@@ -297,4 +278,3 @@ module_exit(mxc_pwm_exit);
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index dab3357196fb..88fb3a57e029 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -29,22 +29,85 @@
 #include <mach/hardware.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
-#include <mach/mxc_timer.h>
+/* defines common for all i.MX */
+#define MXC_TCTL                0x00
+#define MXC_TCTL_TEN            (1 << 0)
+#define MXC_TPRER               0x04
+/* MX1, MX21, MX27 */
+#define MX1_2_TCTL_CLK_PCLK1    (1 << 1)
+#define MX1_2_TCTL_IRQEN        (1 << 4)
+#define MX1_2_TCTL_FRR          (1 << 8)
+#define MX1_2_TCMP              0x08
+#define MX1_2_TCN               0x10
+#define MX1_2_TSTAT             0x14
+/* MX21, MX27 */
+#define MX2_TSTAT_CAPT          (1 << 1)
+#define MX2_TSTAT_COMP          (1 << 0)
+/* MX31, MX35 */
+#define MX3_TCTL_WAITEN         (1 << 3)
+#define MX3_TCTL_CLK_IPG        (1 << 6)
+#define MX3_TCTL_FRR            (1 << 9)
+#define MX3_IR                  0x0c
+#define MX3_TSTAT               0x08
+#define MX3_TSTAT_OF1           (1 << 0)
+#define MX3_TCN                 0x24
+#define MX3_TCMP                0x10
 static struct clock_event_device clockevent_mxc;
 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
-/* clock source */
+static void __iomem *timer_base;
-static cycle_t mxc_get_cycles(struct clocksource *cs)
+static inline void gpt_irq_disable(void)
 {
-        return __raw_readl(TIMER_BASE + MXC_TCN);
+        unsigned int tmp;
+        if (cpu_is_mx3())
+                __raw_writel(0, timer_base + MX3_IR);
+        else {
+                tmp = __raw_readl(timer_base + MXC_TCTL);
+                __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
+        }
+}
+static inline void gpt_irq_enable(void)
+{
+        if (cpu_is_mx3())
+                __raw_writel(1<<0, timer_base + MX3_IR);
+        else {
+                __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
+                        timer_base + MXC_TCTL);
+        }
+}
+static void gpt_irq_acknowledge(void)
+{
+        if (cpu_is_mx1())
+                __raw_writel(0, timer_base + MX1_2_TSTAT);
+        if (cpu_is_mx2())
+                __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
+        if (cpu_is_mx3())
+                __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
+}
+static cycle_t mx1_2_get_cycles(struct clocksource *cs)
+{
+        return __raw_readl(timer_base + MX1_2_TCN);
+}
+static cycle_t mx3_get_cycles(struct clocksource *cs)
+{
+        return __raw_readl(timer_base + MX3_TCN);
 }
 static struct clocksource clocksource_mxc = {
        .name           = "mxc_timer1",
        .rating         = 200,
-        .read           = mxc_get_cycles,
+        .read           = mx1_2_get_cycles,
        .mask           = CLOCKSOURCE_MASK(32),
        .shift          = 20,
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
@@ -54,6 +117,9 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
        unsigned int c = clk_get_rate(timer_clk);
+        if (cpu_is_mx3())
+                clocksource_mxc.read = mx3_get_cycles;
        clocksource_mxc.mult = clocksource_hz2mult(c,
                                        clocksource_mxc.shift);
        clocksource_register(&clocksource_mxc);
@@ -63,15 +129,29 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
 /* clock event */
-static int mxc_set_next_event(unsigned long evt,
+static int mx1_2_set_next_event(unsigned long evt,
                              struct clock_event_device *unused)
 {
        unsigned long tcmp;
-        tcmp = __raw_readl(TIMER_BASE + MXC_TCN) + evt;
+        tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
-        __raw_writel(tcmp, TIMER_BASE + MXC_TCMP);
-        return (int)(tcmp - __raw_readl(TIMER_BASE + MXC_TCN)) < 0 ?
+        __raw_writel(tcmp, timer_base + MX1_2_TCMP);
+        return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
+                                -ETIME : 0;
+}
+static int mx3_set_next_event(unsigned long evt,
+                              struct clock_event_device *unused)
+{
+        unsigned long tcmp;
+        tcmp = __raw_readl(timer_base + MX3_TCN) + evt;
+        __raw_writel(tcmp, timer_base + MX3_TCMP);
+        return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ?
                                -ETIME : 0;
 }
@@ -100,8 +180,13 @@ static void mxc_set_mode(enum clock_event_mode mode,
        if (mode != clockevent_mode) {
                /* Set event time into far-far future */
-                __raw_writel(__raw_readl(TIMER_BASE + MXC_TCN) - 3,
+                if (cpu_is_mx3())
-                                TIMER_BASE + MXC_TCMP);
+                        __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
+                                        timer_base + MX3_TCMP);
+                else
+                        __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
+                                        timer_base + MX1_2_TCMP);
                /* Clear pending interrupt */
                gpt_irq_acknowledge();
        }
@@ -148,7 +233,10 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
        struct clock_event_device *evt = &clockevent_mxc;
        uint32_t tstat;
-        tstat = __raw_readl(TIMER_BASE + MXC_TSTAT);
+        if (cpu_is_mx3())
+                tstat = __raw_readl(timer_base + MX3_TSTAT);
+        else
+                tstat = __raw_readl(timer_base + MX1_2_TSTAT);
        gpt_irq_acknowledge();
@@ -168,7 +256,7 @@ static struct clock_event_device clockevent_mxc = {
        .features       = CLOCK_EVT_FEAT_ONESHOT,
        .shift          = 32,
        .set_mode       = mxc_set_mode,
-        .set_next_event = mxc_set_next_event,
+        .set_next_event = mx1_2_set_next_event,
        .rating         = 200,
 };
@@ -176,6 +264,9 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 {
        unsigned int c = clk_get_rate(timer_clk);
+        if (cpu_is_mx3())
+                clockevent_mxc.set_next_event = mx3_set_next_event;
        clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
                                        clockevent_mxc.shift);
        clockevent_mxc.max_delta_ns =
@@ -192,23 +283,47 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 void __init mxc_timer_init(struct clk *timer_clk)
 {
+        uint32_t tctl_val;
+        int irq;
        clk_enable(timer_clk);
+        if (cpu_is_mx1()) {
+#ifdef CONFIG_ARCH_MX1
+                timer_base = IO_ADDRESS(TIM1_BASE_ADDR);
+                irq = TIM1_INT;
+#endif
+        } else if (cpu_is_mx2()) {
+#ifdef CONFIG_ARCH_MX2
+                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
+                irq = MXC_INT_GPT1;
+#endif
+        } else if (cpu_is_mx3()) {
+#ifdef CONFIG_ARCH_MX3
+                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
+                irq = MXC_INT_GPT;
+#endif
+        } else
+                BUG();
        /*
         * Initialise to a known state (all timers off, and timing reset)
         */
-        __raw_writel(0, TIMER_BASE + MXC_TCTL);
-        __raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */
-        __raw_writel(TCTL_FRR | /* free running */
+        __raw_writel(0, timer_base + MXC_TCTL);
-                     TCTL_VAL | /* set clocksource and arch specific bits */
+        __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
-                     TCTL_TEN,  /* start the timer */
-                     TIMER_BASE + MXC_TCTL);
+        if (cpu_is_mx3())
+                tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
+        else
+                tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
+        __raw_writel(tctl_val, timer_base + MXC_TCTL);
        /* init and register the timer to the framework */
        mxc_clocksource_init(timer_clk);
        mxc_clockevent_init(timer_clk);
        /* Make irqs happen */
-        setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
+        setup_irq(irq, &mxc_timer_irq);
 }
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 9dd68fafb374..efe85d095190 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -23,6 +23,11 @@ config ARCH_OMAP3
        select CPU_V7
        select COMMON_CLKDEV
+config ARCH_OMAP4
+        bool "TI OMAP4"
+        select CPU_V7
+        select ARM_GIC
 endchoice
 comment "OMAP Feature Selections"
@@ -40,7 +45,6 @@ config OMAP_DEBUG_LEDS
 config OMAP_DEBUG_POWERDOMAIN
        bool "Emit debug messages from powerdomain layer"
        depends on ARCH_OMAP2 || ARCH_OMAP3
-        default n
        help
          Say Y here if you want to compile in powerdomain layer
          debugging messages for OMAP2/3.   These messages can
@@ -52,7 +56,6 @@ config OMAP_DEBUG_POWERDOMAIN
 config OMAP_DEBUG_CLOCKDOMAIN
        bool "Emit debug messages from clockdomain layer"
        depends on ARCH_OMAP2 || ARCH_OMAP3
-        default n
        help
          Say Y here if you want to compile in clockdomain layer
          debugging messages for OMAP2/3.   These messages can
@@ -110,11 +113,13 @@ config OMAP_MCBSP
 config OMAP_MBOX_FWK
        tristate "Mailbox framework support"
        depends on ARCH_OMAP
-        default n
        help
          Say Y here if you want to use OMAP Mailbox framework support for
          DSP, IVA1.0 and IVA2 in OMAP1/2/3.
+config OMAP_IOMMU
+        tristate
 choice
        prompt "System timer"
        default OMAP_MPU_TIMER
@@ -128,13 +133,13 @@ config OMAP_MPU_TIMER
 config OMAP_32K_TIMER
        bool "Use 32KHz timer"
-        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
+        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
        help
          Select this option if you want to enable the OMAP 32KHz timer.
          This timer saves power compared to the OMAP_MPU_TIMER, and has
          support for no tick during idle. The 32KHz timer provides less
          intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
-          currently only available for OMAP16XX, 24XX and 34XX.
+          currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
 endchoice
@@ -149,7 +154,7 @@ config OMAP_32K_TIMER_HZ
 config OMAP_DM_TIMER
        bool "Use dual-mode timer"
-        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
+        depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX || ARCH_OMAP4
        help
         Select this option if you want to use OMAP Dual-Mode timers.
@@ -171,7 +176,7 @@ endchoice
 config OMAP_SERIAL_WAKE
        bool "Enable wake-up events for serial ports"
-        depends on OMAP_MUX
+        depends on ARCH_OMAP1 && OMAP_MUX
        default y
        help
          Select this option if you want to have your system wake up
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 04a100cfb8e5..a83279523958 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -13,6 +13,7 @@ obj-  :=
 obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o
 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 29efc279287a..e8c327a45a55 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -36,10 +36,40 @@ static struct clk_functions *arch_clock;
 * Standard clock functions defined in include/linux/clk.h
 *-------------------------------------------------------------------------*/
+/* This functions is moved to arch/arm/common/clkdev.c. For OMAP4 since
+ * clock framework is not up , it is defined here to avoid rework in
+ * every driver. Also dummy prcm reset function is added */
+/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */
+#if defined(CONFIG_ARCH_OMAP4)
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        return NULL;
+}
+EXPORT_SYMBOL(clk_get);
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+void omap2_clk_prepare_for_reboot(void)
+{
+}
+EXPORT_SYMBOL(omap2_clk_prepare_for_reboot);
+void omap_prcm_arch_reset(char mode)
+{
+}
+EXPORT_SYMBOL(omap_prcm_arch_reset);
+#endif
 int clk_enable(struct clk *clk)
 {
        unsigned long flags;
        int ret = 0;
+        if (cpu_is_omap44xx())
+                /* OMAP4 clk framework not supported yet */
+                return 0;
        if (clk == NULL || IS_ERR(clk))
                return -EINVAL;
@@ -140,6 +170,9 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
        unsigned long flags;
        int ret = -EINVAL;
+        if (cpu_is_omap44xx())
+        /* OMAP4 clk framework not supported yet */
+                return 0;
        if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
                return ret;
@@ -240,13 +273,13 @@ void recalculate_root_clocks(void)
 }
 /**
- * clk_init_one - initialize any fields in the struct clk before clk init
+ * clk_preinit - initialize any fields in the struct clk before clk init
 * @clk: struct clk * to initialize
 *
 * Initialize any struct clk fields needed before normal clk initialization
 * can run.  No return value.
 */
-void clk_init_one(struct clk *clk)
+void clk_preinit(struct clk *clk)
 {
        INIT_LIST_HEAD(&clk->children);
 }
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 433021f3d7cc..ebcf006406f9 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -2,6 +2,10 @@
 * linux/arch/arm/plat-omap/common.c
 *
 * Code common to all OMAP machines.
+ * The file is created by Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -11,7 +15,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/delay.h>
-#include <linux/pm.h>
 #include <linux/console.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
@@ -175,25 +178,70 @@ console_initcall(omap_add_serial_console);
 * but systems won't necessarily want to spend resources that way.
 */
-#if defined(CONFIG_ARCH_OMAP16XX)
+#define OMAP16XX_TIMER_32K_SYNCHRONIZED         0xfffbc410
-#define TIMER_32K_SYNCHRONIZED          0xfffbc410
-#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-#define TIMER_32K_SYNCHRONIZED          (OMAP2_32KSYNCT_BASE + 0x10)
-#endif
-#ifdef  TIMER_32K_SYNCHRONIZED
+#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
 #include <linux/clocksource.h>
-static cycle_t omap_32k_read(struct clocksource *cs)
+#ifdef CONFIG_ARCH_OMAP16XX
+static cycle_t omap16xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED);
+}
+#else
+#define omap16xx_32k_read       NULL
+#endif
+#ifdef CONFIG_ARCH_OMAP2420
+static cycle_t omap2420_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10);
+}
+#else
+#define omap2420_32k_read       NULL
+#endif
+#ifdef CONFIG_ARCH_OMAP2430
+static cycle_t omap2430_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10);
+}
+#else
+#define omap2430_32k_read       NULL
+#endif
+#ifdef CONFIG_ARCH_OMAP34XX
+static cycle_t omap34xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
+}
+#else
+#define omap34xx_32k_read       NULL
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+static cycle_t omap44xx_32k_read(struct clocksource *cs)
 {
-        return omap_readl(TIMER_32K_SYNCHRONIZED);
+        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10);
+}
+#else
+#define omap44xx_32k_read       NULL
+#endif
+/*
+ * Kernel assumes that sched_clock can be called early but may not have
+ * things ready yet.
+ */
+static cycle_t omap_32k_read_dummy(struct clocksource *cs)
+{
+        return 0;
 }
 static struct clocksource clocksource_32k = {
        .name           = "32k_counter",
        .rating         = 250,
-        .read           = omap_32k_read,
+        .read           = omap_32k_read_dummy,
        .mask           = CLOCKSOURCE_MASK(32),
        .shift          = 10,
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
@@ -207,7 +255,7 @@ unsigned long long sched_clock(void)
 {
        unsigned long long ret;
-        ret = (unsigned long long)omap_32k_read(&clocksource_32k);
+        ret = (unsigned long long)clocksource_32k.read(&clocksource_32k);
        ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
        return ret;
 }
@@ -220,6 +268,19 @@ static int __init omap_init_clocksource_32k(void)
        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
                struct clk *sync_32k_ick;
+                if (cpu_is_omap16xx())
+                        clocksource_32k.read = omap16xx_32k_read;
+                else if (cpu_is_omap2420())
+                        clocksource_32k.read = omap2420_32k_read;
+                else if (cpu_is_omap2430())
+                        clocksource_32k.read = omap2430_32k_read;
+                else if (cpu_is_omap34xx())
+                        clocksource_32k.read = omap34xx_32k_read;
+                else if (cpu_is_omap44xx())
+                        clocksource_32k.read = omap44xx_32k_read;
+                else
+                        return -ENODEV;
                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
                if (sync_32k_ick)
                        clk_enable(sync_32k_ick);
@@ -234,15 +295,13 @@ static int __init omap_init_clocksource_32k(void)
 }
 arch_initcall(omap_init_clocksource_32k);
-#endif  /* TIMER_32K_SYNCHRONIZED */
+#endif  /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
 /* Global address base setup code */
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-static struct omap_globals *omap2_globals;
+static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
-static void __init __omap2_set_globals(void)
 {
        omap2_set_globals_tap(omap2_globals);
        omap2_set_globals_sdrc(omap2_globals);
@@ -266,8 +325,7 @@ static struct omap_globals omap242x_globals = {
 void __init omap2_set_globals_242x(void)
 {
-        omap2_globals = &omap242x_globals;
+        __omap2_set_globals(&omap242x_globals);
-        __omap2_set_globals();
 }
 #endif
@@ -285,8 +343,7 @@ static struct omap_globals omap243x_globals = {
 void __init omap2_set_globals_243x(void)
 {
-        omap2_globals = &omap243x_globals;
+        __omap2_set_globals(&omap243x_globals);
-        __omap2_set_globals();
 }
 #endif
@@ -304,8 +361,23 @@ static struct omap_globals omap343x_globals = {
 void __init omap2_set_globals_343x(void)
 {
-        omap2_globals = &omap343x_globals;
+        __omap2_set_globals(&omap343x_globals);
-        __omap2_set_globals();
+}
+#endif
+#if defined(CONFIG_ARCH_OMAP4)
+static struct omap_globals omap4_globals = {
+        .class  = OMAP443X_CLASS,
+        .tap    = OMAP2_IO_ADDRESS(0x4830a000),
+        .ctrl   = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE),
+        .prm    = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE),
+        .cm     = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE),
+};
+void __init omap2_set_globals_443x(void)
+{
+        omap2_set_globals_tap(&omap4_globals);
+        omap2_set_globals_control(&omap4_globals);
 }
 #endif
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 87fb7ff41794..a64b692a1bfe 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -311,6 +311,8 @@ static void omap_init_wdt(void)
                wdt_resources[0].start = 0x49016000; /* WDT2 */
        else if (cpu_is_omap343x())
                wdt_resources[0].start = 0x48314000; /* WDT2 */
+        else if (cpu_is_omap44xx())
+                wdt_resources[0].start = 0x4a314000;
        else
                return;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fc8c045ad5d..def14ec265b3 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -10,6 +10,9 @@
 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * Support functions for the OMAP internal DMA channels.
 *
 * This program is free software; you can redistribute it and/or modify
@@ -310,41 +313,62 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 {
-        u16 w;
        BUG_ON(omap_dma_in_1510_mode());
-        if (cpu_class_is_omap2()) {
+        if (cpu_class_is_omap1()) {
-                REVISIT_24XX();
+                u16 w;
-                return;
-        }
-        w = dma_read(CCR2(lch));
+                w = dma_read(CCR2(lch));
-        w &= ~0x03;
+                w &= ~0x03;
-        switch (mode) {
+                switch (mode) {
-        case OMAP_DMA_CONSTANT_FILL:
+                case OMAP_DMA_CONSTANT_FILL:
-                w |= 0x01;
+                        w |= 0x01;
-                break;
+                        break;
-        case OMAP_DMA_TRANSPARENT_COPY:
+                case OMAP_DMA_TRANSPARENT_COPY:
-                w |= 0x02;
+                        w |= 0x02;
-                break;
+                        break;
-        case OMAP_DMA_COLOR_DIS:
+                case OMAP_DMA_COLOR_DIS:
-                break;
+                        break;
-        default:
+                default:
-                BUG();
+                        BUG();
+                }
+                dma_write(w, CCR2(lch));
+                w = dma_read(LCH_CTRL(lch));
+                w &= ~0x0f;
+                /* Default is channel type 2D */
+                if (mode) {
+                        dma_write((u16)color, COLOR_L(lch));
+                        dma_write((u16)(color >> 16), COLOR_U(lch));
+                        w |= 1;         /* Channel type G */
+                }
+                dma_write(w, LCH_CTRL(lch));
        }
-        dma_write(w, CCR2(lch));
-        w = dma_read(LCH_CTRL(lch));
+        if (cpu_class_is_omap2()) {
-        w &= ~0x0f;
+                u32 val;
-        /* Default is channel type 2D */
-        if (mode) {
+                val = dma_read(CCR(lch));
-                dma_write((u16)color, COLOR_L(lch));
+                val &= ~((1 << 17) | (1 << 16));
-                dma_write((u16)(color >> 16), COLOR_U(lch));
-                w |= 1;         /* Channel type G */
+                switch (mode) {
+                case OMAP_DMA_CONSTANT_FILL:
+                        val |= 1 << 16;
+                        break;
+                case OMAP_DMA_TRANSPARENT_COPY:
+                        val |= 1 << 17;
+                        break;
+                case OMAP_DMA_COLOR_DIS:
+                        break;
+                default:
+                        BUG();
+                }
+                dma_write(val, CCR(lch));
+                color &= 0xffffff;
+                dma_write(color, COLOR(lch));
        }
-        dma_write(w, LCH_CTRL(lch));
 }
 EXPORT_SYMBOL(omap_set_dma_color_mode);
@@ -851,7 +875,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
        }
        l = dma_read(CCR(lch));
        l &= ~((1 << 6) | (1 << 26));
-        if (cpu_is_omap2430() || cpu_is_omap34xx())
+        if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
                l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
        else
                l |= ((read_prio & 0x1) << 6);
@@ -1199,7 +1223,7 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
 *           Failure: -EINVAL/-ENOMEM
 */
 int omap_request_dma_chain(int dev_id, const char *dev_name,
-                           void (*callback) (int chain_id, u16 ch_status,
+                           void (*callback) (int lch, u16 ch_status,
                                             void *data),
                           int *chain_id, int no_of_chans, int chain_mode,
                           struct omap_dma_channel_params params)
@@ -1823,7 +1847,8 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 #define omap1_dma_irq_handler   NULL
 #endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                        defined(CONFIG_ARCH_OMAP4)
 static int omap2_dma_handle_ch(int ch)
 {
@@ -2318,6 +2343,9 @@ static int __init omap_init_dma(void)
        } else if (cpu_is_omap34xx()) {
                omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+        } else if (cpu_is_omap44xx()) {
+                omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
+                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
        } else {
                pr_err("DMA init failed for unsupported omap\n");
                return -ENODEV;
@@ -2416,12 +2444,18 @@ static int __init omap_init_dma(void)
                }
        }
-        if (cpu_is_omap2430() || cpu_is_omap34xx())
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
                omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
                                DMA_DEFAULT_FIFO_DEPTH, 0);
-        if (cpu_class_is_omap2())
+        if (cpu_class_is_omap2()) {
-                setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
+                int irq;
+                if (cpu_is_omap44xx())
+                        irq = INT_44XX_SDMA_IRQ0;
+                else
+                        irq = INT_24XX_SDMA_IRQ0;
+                setup_irq(irq, &omap24xx_dma_irq);
+        }
        /* FIXME: Update LCD DMA to work on 24xx */
        if (cpu_class_is_omap1()) {
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 55bb99631292..7f50b6103dee 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -7,6 +7,9 @@
 * OMAP2 support by Juha Yrjola
 * API improvements and OMAP2 clock framework support by Timo Teras
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
@@ -150,7 +153,8 @@
 struct omap_dm_timer {
        unsigned long phys_base;
        int irq;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                        defined(CONFIG_ARCH_OMAP4)
        struct clk *iclk, *fclk;
 #endif
        void __iomem *io_base;
@@ -169,6 +173,9 @@ struct omap_dm_timer {
 #define omap3_dm_timers                 NULL
 #define omap3_dm_source_names           NULL
 #define omap3_dm_source_clocks          NULL
+#define omap4_dm_timers                 NULL
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
 static struct omap_dm_timer omap1_dm_timers[] = {
        { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
@@ -191,6 +198,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
 #define omap3_dm_timers                 NULL
 #define omap3_dm_source_names           NULL
 #define omap3_dm_source_clocks          NULL
+#define omap4_dm_timers                 NULL
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
 static struct omap_dm_timer omap2_dm_timers[] = {
        { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
@@ -214,7 +224,7 @@ static const char *omap2_dm_source_names[] __initdata = {
        NULL
 };
-static struct clk **omap2_dm_source_clocks[3];
+static struct clk *omap2_dm_source_clocks[3];
 static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
 #elif defined(CONFIG_ARCH_OMAP3)
@@ -225,6 +235,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
 #define omap2_dm_timers                 NULL
 #define omap2_dm_source_names           NULL
 #define omap2_dm_source_clocks          NULL
+#define omap4_dm_timers                 NULL
+#define omap4_dm_source_names           NULL
+#define omap4_dm_source_clocks          NULL
 static struct omap_dm_timer omap3_dm_timers[] = {
        { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
@@ -247,9 +260,43 @@ static const char *omap3_dm_source_names[] __initdata = {
        NULL
 };
-static struct clk **omap3_dm_source_clocks[2];
+static struct clk *omap3_dm_source_clocks[2];
 static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
+#elif defined(CONFIG_ARCH_OMAP4)
+#define omap_dm_clk_enable(x)           clk_enable(x)
+#define omap_dm_clk_disable(x)          clk_disable(x)
+#define omap1_dm_timers                 NULL
+#define omap2_dm_timers                 NULL
+#define omap2_dm_source_names           NULL
+#define omap2_dm_source_clocks          NULL
+#define omap3_dm_timers                 NULL
+#define omap3_dm_source_names           NULL
+#define omap3_dm_source_clocks          NULL
+static struct omap_dm_timer omap4_dm_timers[] = {
+        { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 },
+        { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 },
+        { .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 },
+        { .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 },
+        { .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 },
+        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 },
+        { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 },
+        { .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 },
+        { .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 },
+        { .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 },
+        { .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 },
+        { .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 },
+};
+static const char *omap4_dm_source_names[] __initdata = {
+        "sys_ck",
+        "omap_32k_fck",
+        NULL
+};
+static struct clk *omap4_dm_source_clocks[2];
+static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
 #else
 #error OMAP architecture not supported!
@@ -257,7 +304,7 @@ static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
 #endif
 static struct omap_dm_timer *dm_timers;
-static char **dm_source_names;
+static const char **dm_source_names;
 static struct clk **dm_source_clocks;
 static spinlock_t dm_timer_lock;
@@ -459,7 +506,8 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
-#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
+#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                                defined(CONFIG_ARCH_OMAP4)
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
@@ -705,12 +753,16 @@ int __init omap_dm_timer_init(void)
                dm_timers = omap1_dm_timers;
        else if (cpu_is_omap24xx()) {
                dm_timers = omap2_dm_timers;
-                dm_source_names = (char **)omap2_dm_source_names;
+                dm_source_names = omap2_dm_source_names;
-                dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
+                dm_source_clocks = omap2_dm_source_clocks;
        } else if (cpu_is_omap34xx()) {
                dm_timers = omap3_dm_timers;
-                dm_source_names = (char **)omap3_dm_source_names;
+                dm_source_names = omap3_dm_source_names;
-                dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
+                dm_source_clocks = omap3_dm_source_clocks;
+        } else if (cpu_is_omap44xx()) {
+                dm_timers = omap4_dm_timers;
+                dm_source_names = omap4_dm_source_names;
+                dm_source_clocks = omap4_dm_source_clocks;
        }
        if (cpu_class_is_omap2())
@@ -723,7 +775,8 @@ int __init omap_dm_timer_init(void)
        for (i = 0; i < dm_timer_count; i++) {
                timer = &dm_timers[i];
                timer->io_base = IO_ADDRESS(timer->phys_base);
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                                        defined(CONFIG_ARCH_OMAP4)
                if (cpu_class_is_omap2()) {
                        char clk_name[16];
                        sprintf(clk_name, "gpt%d_ick", i + 1);
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index ee0b21f5b094..7fd89ba8d3b5 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -6,6 +6,9 @@
 * Copyright (C) 2003-2005 Nokia Corporation
 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -146,6 +149,16 @@
 #define OMAP34XX_GPIO5_BASE             IO_ADDRESS(0x49056000)
 #define OMAP34XX_GPIO6_BASE             IO_ADDRESS(0x49058000)
+/*
+ * OMAP44XX  specific GPIO registers
+ */
+#define OMAP44XX_GPIO1_BASE             IO_ADDRESS(0x4a310000)
+#define OMAP44XX_GPIO2_BASE             IO_ADDRESS(0x48055000)
+#define OMAP44XX_GPIO3_BASE             IO_ADDRESS(0x48057000)
+#define OMAP44XX_GPIO4_BASE             IO_ADDRESS(0x48059000)
+#define OMAP44XX_GPIO5_BASE             IO_ADDRESS(0x4805B000)
+#define OMAP44XX_GPIO6_BASE             IO_ADDRESS(0x4805D000)
 #define OMAP_MPUIO_VBASE                IO_ADDRESS(OMAP_MPUIO_BASE)
 struct gpio_bank {
@@ -153,11 +166,13 @@ struct gpio_bank {
        u16 irq;
        u16 virtual_irq_start;
        int method;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||  \
+                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
        u32 suspend_wakeup;
        u32 saved_wakeup;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
        u32 non_wakeup_gpios;
        u32 enabled_non_wakeup_gpios;
@@ -251,6 +266,24 @@ static struct gpio_bank gpio_bank_34xx[6] = {
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+static struct gpio_bank gpio_bank_44xx[6] = {
+        { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,       \
+                METHOD_GPIO_24XX },
+        { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,  \
+                METHOD_GPIO_24XX },
+        { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,  \
+                METHOD_GPIO_24XX },
+        { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,  \
+                METHOD_GPIO_24XX },
+        { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
+                METHOD_GPIO_24XX },
+        { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
+                METHOD_GPIO_24XX },
+};
+#endif
 static struct gpio_bank *gpio_bank;
 static int gpio_bank_count;
@@ -273,7 +306,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
        }
        if (cpu_is_omap24xx())
                return &gpio_bank[gpio >> 5];
-        if (cpu_is_omap34xx())
+        if (cpu_is_omap34xx() || cpu_is_omap44xx())
                return &gpio_bank[gpio >> 5];
        BUG();
        return NULL;
@@ -285,7 +318,7 @@ static inline int get_gpio_index(int gpio)
                return gpio & 0x1f;
        if (cpu_is_omap24xx())
                return gpio & 0x1f;
-        if (cpu_is_omap34xx())
+        if (cpu_is_omap34xx() || cpu_is_omap44xx())
                return gpio & 0x1f;
        return gpio & 0x0f;
 }
@@ -307,7 +340,7 @@ static inline int gpio_valid(int gpio)
                return 0;
        if (cpu_is_omap24xx() && gpio < 128)
                return 0;
-        if (cpu_is_omap34xx() && gpio < 192)
+        if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
                return 0;
        return -1;
 }
@@ -353,7 +386,8 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                reg += OMAP850_GPIO_DIR_CONTROL;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_OE;
                break;
@@ -425,7 +459,8 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                        l &= ~(1 << gpio);
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                if (enable)
                        reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -476,7 +511,8 @@ static int __omap_get_gpio_datain(int gpio)
                reg += OMAP850_GPIO_DATA_INPUT;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_DATAIN;
                break;
@@ -520,7 +556,7 @@ void omap_set_gpio_debounce(int gpio, int enable)
        else
                goto done;
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
                if (enable)
                        clk_enable(bank->dbck);
                else
@@ -550,7 +586,8 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                                                int trigger)
 {
@@ -660,7 +697,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
                        goto bad;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                set_24xx_gpio_triggering(bank, gpio, trigger);
                break;
@@ -745,7 +783,8 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                reg += OMAP850_GPIO_INT_STATUS;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_IRQSTATUS1;
                break;
@@ -814,7 +853,8 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                inv = 1;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_IRQENABLE1;
                mask = 0xffffffff;
@@ -887,7 +927,8 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                        l |= gpio_mask;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                if (enable)
                        reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -932,7 +973,8 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
                spin_unlock_irqrestore(&bank->lock, flags);
                return 0;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                if (bank->non_wakeup_gpios & (1 << gpio)) {
                        printk(KERN_ERR "Unable to modify wakeup on "
@@ -1017,7 +1059,8 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
                __raw_writel(1 << offset, reg);
        }
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
        if (bank->method == METHOD_GPIO_24XX) {
                /* Disable wake-up during idle for dynamic tick */
                void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -1069,7 +1112,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
        if (bank->method == METHOD_GPIO_850)
                isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
        if (bank->method == METHOD_GPIO_24XX)
                isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
 #endif
@@ -1346,7 +1390,7 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
 /*---------------------------------------------------------------------*/
 static int initialized;
-#if !defined(CONFIG_ARCH_OMAP3)
+#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
 static struct clk * gpio_ick;
 #endif
@@ -1359,7 +1403,7 @@ static struct clk * gpio5_ick;
 static struct clk * gpio5_fck;
 #endif
-#if defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
@@ -1419,8 +1463,8 @@ static int __init _omap_gpio_init(void)
        }
 #endif
-#if defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
                for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
                        sprintf(clk_name, "gpio%d_ick", i + 1);
                        gpio_iclks[i] = clk_get(NULL, clk_name);
@@ -1497,6 +1541,17 @@ static int __init _omap_gpio_init(void)
                        (rev >> 4) & 0x0f, rev & 0x0f);
        }
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        if (cpu_is_omap44xx()) {
+                int rev;
+                gpio_bank_count = OMAP34XX_NR_GPIOS;
+                gpio_bank = gpio_bank_44xx;
+                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+                printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
+                        (rev >> 4) & 0x0f, rev & 0x0f);
+        }
+#endif
        for (i = 0; i < gpio_bank_count; i++) {
                int j, gpio_count = 16;
@@ -1520,7 +1575,8 @@ static int __init _omap_gpio_init(void)
                        gpio_count = 32; /* 730 has 32-bit GPIOs */
                }
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
                if (bank->method == METHOD_GPIO_24XX) {
                        static const u32 non_wakeup_gpios[] = {
                                0xe203ffc0, 0x08700040
@@ -1577,7 +1633,7 @@ static int __init _omap_gpio_init(void)
                set_irq_chained_handler(bank->irq, gpio_irq_handler);
                set_irq_data(bank->irq, bank);
-                if (cpu_is_omap34xx()) {
+                if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
                        sprintf(clk_name, "gpio%d_dbck", i + 1);
                        bank->dbck = clk_get(NULL, clk_name);
                        if (IS_ERR(bank->dbck))
@@ -1599,7 +1655,8 @@ static int __init _omap_gpio_init(void)
        return 0;
 }
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
+                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
 {
        int i;
@@ -1622,7 +1679,8 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                        break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
                case METHOD_GPIO_24XX:
                        wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
@@ -1663,7 +1721,8 @@ static int omap_gpio_resume(struct sys_device *dev)
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                        break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
                case METHOD_GPIO_24XX:
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
@@ -1695,7 +1754,8 @@ static struct sys_device omap_gpio_device = {
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
 static int workaround_enabled;
@@ -1711,7 +1771,8 @@ void omap2_gpio_prepare_for_retention(void)
                if (!(bank->enabled_non_wakeup_gpios))
                        continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                                defined(CONFIG_ARCH_OMAP4)
                bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
                l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
@@ -1720,7 +1781,8 @@ void omap2_gpio_prepare_for_retention(void)
                bank->saved_risingdetect = l2;
                l1 &= ~bank->enabled_non_wakeup_gpios;
                l2 &= ~bank->enabled_non_wakeup_gpios;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
                __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
 #endif
@@ -1745,7 +1807,8 @@ void omap2_gpio_resume_after_retention(void)
                if (!(bank->enabled_non_wakeup_gpios))
                        continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
                __raw_writel(bank->saved_fallingdetect,
                                 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                __raw_writel(bank->saved_risingdetect,
@@ -1755,14 +1818,16 @@ void omap2_gpio_resume_after_retention(void)
                 * state.  If so, generate an IRQ by software.  This is
                 * horribly racy, but it's the best we can do to work around
                 * this silicon bug. */
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
 #endif
                l ^= bank->saved_datain;
                l &= bank->non_wakeup_gpios;
                if (l) {
                        u32 old0, old1;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
                        old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                        old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
                        __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
@@ -1798,7 +1863,8 @@ static int __init omap_gpio_sysinit(void)
        mpuio_init();
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
+                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
                if (ret == 0) {
                        ret = sysdev_class_register(&omap_gpio_sysclass);
@@ -1887,7 +1953,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
                        irqstat = irq_desc[irq].status;
 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||   \
-                defined(CONFIG_ARCH_OMAP34XX)
+                defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
                        if (is_in && ((bank->suspend_wakeup & mask)
                                        || irqstat & IRQ_TYPE_SENSE_MASK)) {
                                char    *trigger = NULL;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a303071d5e36..8b848391f0c8 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -5,7 +5,7 @@
 *
 * Copyright (C) 2007 Nokia Corporation.
 *
- * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
+ * Contact: Jarkko Nikula <jhnikula@gmail.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 073a2c5569f0..f9f65e1ba3f1 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -22,7 +22,8 @@ struct clkops {
        void                    (*disable)(struct clk *);
 };
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                defined(CONFIG_ARCH_OMAP4)
 struct clksel_rate {
        u32                     val;
@@ -51,7 +52,7 @@ struct dpll_data {
        u8                      max_divider;
        u32                     max_tolerance;
        u16                     max_multiplier;
-#  if defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
        u8                      modes;
        void __iomem            *autoidle_reg;
        void __iomem            *idlest_reg;
@@ -83,7 +84,8 @@ struct clk {
        void                    (*init)(struct clk *);
        __u8                    enable_bit;
        __s8                    usecount;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                defined(CONFIG_ARCH_OMAP4)
        u8                      fixed_div;
        void __iomem            *clksel_reg;
        u32                     clksel_mask;
@@ -119,7 +121,7 @@ struct clk_functions {
 extern unsigned int mpurate;
 extern int clk_init(struct clk_functions *custom_clocks);
-extern void clk_init_one(struct clk *clk);
+extern void clk_preinit(struct clk *clk);
 extern int clk_register(struct clk *clk);
 extern void clk_reparent(struct clk *child, struct clk *parent);
 extern void clk_unregister(struct clk *clk);
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index 0ecf36deb17b..fdeab421b4dc 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -33,8 +33,6 @@ struct sys_timer;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
-extern void omap_serial_init(void);
-extern void omap_serial_enable_clocks(int enable);
 #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
                                 struct i2c_board_info const *info,
@@ -62,6 +60,7 @@ struct omap_globals {
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_343x(void);
+void omap2_set_globals_443x(void);
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index 269147f3836f..8140dbccb7bc 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -1,9 +1,9 @@
 /*
 * arch/arm/plat-omap/include/mach/control.h
 *
- * OMAP2/3 System Control Module definitions
+ * OMAP2/3/4 System Control Module definitions
 *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -144,6 +144,10 @@
 #define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02b0)
 #define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02b4)
+/* 34xx D2D idle-related pins, handled by PM core */
+#define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
+#define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 /*
 * REVISIT: This list of registers is not comprehensive - there are more
 * that should be added.
@@ -189,8 +193,18 @@
 #define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
 #define OMAP2_PBIASLITEVMODE0           (1 << 0)
+/* CONTROL_IVA2_BOOTMOD bits */
+#define OMAP3_IVA2_BOOTMOD_SHIFT        0
+#define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
+#define OMAP3_IVA2_BOOTMOD_IDLE         (0x1 << 0)
+/* CONTROL_PADCONF_X bits */
+#define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
+#define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                defined(CONFIG_ARCH_OMAP4)
 extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 98b144252364..fc60c4ebcc28 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -5,8 +5,12 @@
 *
 * Copyright (C) 2004, 2008 Nokia Corporation
 *
+ * Copyright (C) 2009 Texas Instruments.
+ *
 * Written by Tony Lindgren <tony.lindgren@nokia.com>
 *
+ * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
@@ -155,6 +159,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_omap44xx()               0
+#define cpu_is_omap443x()               0
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -348,12 +354,21 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define cpu_is_omap3430()              is_omap3430()
 #endif
+# if defined(CONFIG_ARCH_OMAP4)
+# undef cpu_is_omap44xx
+# undef cpu_is_omap443x
+# define cpu_is_omap44xx()              1
+# define cpu_is_omap443x()              1
+# endif
 /* Macros to detect if we have OMAP1 or OMAP2 */
 #define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
                                cpu_is_omap16xx())
-#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx())
+#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
+                                cpu_is_omap44xx())
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                        defined(CONFIG_ARCH_OMAP4)
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
@@ -370,6 +385,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP3430_REV_ES3_0      0x34303034
 #define OMAP3430_REV_ES3_1      0x34304034
+#define OMAP443X_CLASS          0x44300034
 /*
 * omap_chip bits
 *
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
index 1b11f5c6a2d9..ac24050e3416 100644
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -36,7 +36,7 @@
                add     \rx, \rx, #0x00004000   @ UART 3
 #endif
-#elif   CONFIG_ARCH_OMAP3
+#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
                moveq   \rx, #0x48000000        @ physical base address
                movne   \rx, #0xd8000000        @ virtual base
                orr     \rx, \rx, #0x0006a000
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 54fe9665b182..8c1eae88737e 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -48,6 +48,7 @@
 /* Hardware registers for omap2 and omap3 */
 #define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
 #define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
+#define OMAP44XX_DMA4_BASE              (L4_44XX_BASE + 0x56000)
 #define OMAP_DMA4_REVISION              0x00
 #define OMAP_DMA4_GCR                   0x78
@@ -144,6 +145,7 @@
 #define OMAP_DMA4_CSSA_U(n)             0
 #define OMAP_DMA4_CDSA_L(n)             0
 #define OMAP_DMA4_CDSA_U(n)             0
+#define OMAP1_DMA_COLOR(n)              0
 /*----------------------------------------------------------------------------*/
@@ -531,7 +533,7 @@ extern int omap_get_dma_index(int lch, int *ei, int *fi);
 /* Chaining APIs */
 #ifndef CONFIG_ARCH_OMAP1
 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
-                                  void (*callback) (int chain_id, u16 ch_status,
+                                  void (*callback) (int lch, u16 ch_status,
                                                    void *data),
                                  int *chain_id, int no_of_chans,
                                  int chain_mode,
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index 2276f89671d8..56426ed45ef4 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -3,6 +3,9 @@
 *
 * Low-level IRQ helper macros for OMAP-based platforms
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
@@ -10,6 +13,7 @@
 #include <mach/hardware.h>
 #include <mach/io.h>
 #include <mach/irqs.h>
+#include <asm/hardware/gic.h>
 #if defined(CONFIG_ARCH_OMAP1)
@@ -56,15 +60,21 @@
                .endm
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
-#if defined(CONFIG_ARCH_OMAP24XX)
 #include <mach/omap24xx.h>
-#endif
-#if defined(CONFIG_ARCH_OMAP34XX)
 #include <mach/omap34xx.h>
-#endif
+/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
+#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
+#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP24XX_IC_BASE)
+#elif defined(CONFIG_ARCH_OMAP34XX)
+#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
+#endif
+#if defined(CONFIG_ARCH_OMAP4)
+#include <mach/omap44xx.h>
+#endif
 #define INTCPS_SIR_IRQ_OFFSET   0x0040          /* Active interrupt offset */
 #define ACTIVEIRQ_MASK          0x7f            /* Active interrupt bits */
@@ -77,6 +87,7 @@
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
+#ifndef CONFIG_ARCH_OMAP4
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                ldr     \base, =OMAP2_VA_IC_BASE
                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
@@ -92,6 +103,68 @@
                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
                .endm
+#else
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an
+                 * interrupt if it's between 30 and 1020.  The test_for_ipi
+                 * routine below will pick up on IPIs.
+                 * A simple read from the controller will tell us the number
+                 * of the highest priority enabled interrupt.
+                 * We then just need to check whether it is in the
+                 * valid range for an IRQ (30-1020 inclusive).
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+                ldr     \tmp, =1021
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt
+                 * on the controller, since this requires the original irqstat
+                 * value which we won't easily be able to recreate later.
+                 */
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                it      cc
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                it      cs
+                cmpcs   \irqnr, \irqnr
+                .endm
+                /* As above, this assumes that irqstat and base are preserved */
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                itt     eq
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
+#endif
                .macro  irq_prio_table
                .endm
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
new file mode 100644
index 000000000000..b64fbee4d567
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
+#define GPMC_TIMINGS_SMC91C96   (1 << 4)
+#define GPMC_MUX_ADD_DATA       (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
+#define GPMC_READ_MON           (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
+#define GPMC_WRITE_MON          (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
+struct omap_smc91x_platform_data {
+        int     cs;
+        int     gpio_irq;
+        int     gpio_pwrdwn;
+        int     gpio_reset;
+        int     wait_pin;       /* Optional GPMC_CONFIG1_WAITPINSELECT */
+        u32     flags;
+        int     (*retime)(void);
+};
+#if defined(CONFIG_SMC91X) || \
+        defined(CONFIG_SMC91X_MODULE)
+extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
+#else
+#define board_smc91x_data       NULL
+static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
+{
+}
+#endif
+#endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 3dc423ed3e80..26c1fbff08aa 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -285,5 +285,6 @@
 #include "omap16xx.h"
 #include "omap24xx.h"
 #include "omap34xx.h"
+#include "omap44xx.h"
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/mach/hwa742.h
index 577f492f2d3c..886248d32b49 100644
--- a/arch/arm/plat-omap/include/mach/hwa742.h
+++ b/arch/arm/plat-omap/include/mach/hwa742.h
@@ -2,10 +2,6 @@
 #define _HWA742_H
 struct hwa742_platform_data {
-        void            (*power_up)(struct device *dev);
-        void            (*power_down)(struct device *dev);
-        unsigned long   (*get_clock_rate)(struct device *dev);
        unsigned        te_connected:1;
 };
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 0610d7e2b3d7..3b2814720569 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -6,6 +6,9 @@
 * Copied from arch/arm/mach-sa1100/include/mach/io.h
 * Copyright (C) 1997-1999 Russell King
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
@@ -157,6 +160,40 @@
 #define DSP_MMU_34XX_VIRT       0xe2000000
 #define DSP_MMU_34XX_SIZE       SZ_4K
+#elif defined(CONFIG_ARCH_OMAP4)
+/* We map both L3 and L4 on OMAP4 */
+#define L3_44XX_PHYS            L3_44XX_BASE
+#define L3_44XX_VIRT            0xd4000000
+#define L3_44XX_SIZE            SZ_1M
+#define L4_44XX_PHYS            L4_44XX_BASE
+#define L4_44XX_VIRT            0xda000000
+#define L4_44XX_SIZE            SZ_4M
+#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE
+#define L4_WK_44XX_VIRT         0xda300000
+#define L4_WK_44XX_SIZE         SZ_1M
+#define L4_PER_44XX_PHYS        L4_PER_44XX_BASE
+#define L4_PER_44XX_VIRT        0xd8000000
+#define L4_PER_44XX_SIZE        SZ_4M
+#define L4_EMU_44XX_PHYS        L4_EMU_44XX_BASE
+#define L4_EMU_44XX_VIRT        0xe4000000
+#define L4_EMU_44XX_SIZE        SZ_64M
+#define OMAP44XX_GPMC_PHYS      OMAP44XX_GPMC_BASE
+#define OMAP44XX_GPMC_VIRT      0xe0000000
+#define OMAP44XX_GPMC_SIZE      SZ_1M
+#define IO_OFFSET               0x90000000
+#define __IO_ADDRESS(pa)        ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define __OMAP2_IO_ADDRESS(pa)  ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
 #endif
 #define IO_ADDRESS(pa)          IOMEM(__IO_ADDRESS(pa))
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h
new file mode 100644
index 000000000000..769b00b4c34a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu.h
@@ -0,0 +1,168 @@
+/*
+ * omap iommu: main structures
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_IOMMU_H
+#define __MACH_IOMMU_H
+struct iotlb_entry {
+        u32 da;
+        u32 pa;
+        u32 pgsz, prsvd, valid;
+        union {
+                u16 ap;
+                struct {
+                        u32 endian, elsz, mixed;
+                };
+        };
+};
+struct iommu {
+        const char      *name;
+        struct module   *owner;
+        struct clk      *clk;
+        void __iomem    *regbase;
+        struct device   *dev;
+        unsigned int    refcount;
+        struct mutex    iommu_lock;     /* global for this whole object */
+        /*
+         * We don't change iopgd for a situation like pgd for a task,
+         * but share it globally for each iommu.
+         */
+        u32             *iopgd;
+        spinlock_t      page_table_lock; /* protect iopgd */
+        int             nr_tlb_entries;
+        struct list_head        mmap;
+        struct mutex            mmap_lock; /* protect mmap */
+        int (*isr)(struct iommu *obj);
+        void *ctx; /* iommu context: registres saved area */
+};
+struct cr_regs {
+        union {
+                struct {
+                        u16 cam_l;
+                        u16 cam_h;
+                };
+                u32 cam;
+        };
+        union {
+                struct {
+                        u16 ram_l;
+                        u16 ram_h;
+                };
+                u32 ram;
+        };
+};
+struct iotlb_lock {
+        short base;
+        short vict;
+};
+/* architecture specific functions */
+struct iommu_functions {
+        unsigned long   version;
+        int (*enable)(struct iommu *obj);
+        void (*disable)(struct iommu *obj);
+        u32 (*fault_isr)(struct iommu *obj, u32 *ra);
+        void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
+        void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
+        struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
+        int (*cr_valid)(struct cr_regs *cr);
+        u32 (*cr_to_virt)(struct cr_regs *cr);
+        void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
+        ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
+        u32 (*get_pte_attr)(struct iotlb_entry *e);
+        void (*save_ctx)(struct iommu *obj);
+        void (*restore_ctx)(struct iommu *obj);
+        ssize_t (*dump_ctx)(struct iommu *obj, char *buf);
+};
+struct iommu_platform_data {
+        const char *name;
+        const char *clk_name;
+        const int nr_tlb_entries;
+};
+#if defined(CONFIG_ARCH_OMAP1)
+#error "iommu for this processor not implemented yet"
+#else
+#include <mach/iommu2.h>
+#endif
+/*
+ * utilities for super page(16MB, 1MB, 64KB and 4KB)
+ */
+#define iopgsz_max(bytes)                       \
+        (((bytes) >= SZ_16M) ? SZ_16M :         \
+         ((bytes) >= SZ_1M)  ? SZ_1M  :         \
+         ((bytes) >= SZ_64K) ? SZ_64K :         \
+         ((bytes) >= SZ_4K)  ? SZ_4K  : 0)
+#define bytes_to_iopgsz(bytes)                          \
+        (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :       \
+         ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :       \
+         ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :       \
+         ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
+#define iopgsz_to_bytes(iopgsz)                         \
+        (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M :      \
+         ((iopgsz) == MMU_CAM_PGSZ_1M)  ? SZ_1M  :      \
+         ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K :      \
+         ((iopgsz) == MMU_CAM_PGSZ_4K)  ? SZ_4K  : 0)
+#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
+/*
+ * global functions
+ */
+extern u32 iommu_arch_version(void);
+extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
+extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
+extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void flush_iotlb_page(struct iommu *obj, u32 da);
+extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
+extern void flush_iotlb_all(struct iommu *obj);
+extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
+extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
+extern struct iommu *iommu_get(const char *name);
+extern void iommu_put(struct iommu *obj);
+extern void iommu_save_ctx(struct iommu *obj);
+extern void iommu_restore_ctx(struct iommu *obj);
+extern int install_iommu_arch(const struct iommu_functions *ops);
+extern void uninstall_iommu_arch(const struct iommu_functions *ops);
+extern int foreach_iommu_device(void *data,
+                                int (*fn)(struct device *, void *));
+extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf);
+extern size_t dump_tlb_entries(struct iommu *obj, char *buf);
+#endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h
new file mode 100644
index 000000000000..10ad05f410e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu2.h
@@ -0,0 +1,96 @@
+/*
+ * omap iommu: omap2 architecture specific definitions
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_IOMMU2_H
+#define __MACH_IOMMU2_H
+#include <linux/io.h>
+/*
+ * MMU Register offsets
+ */
+#define MMU_REVISION            0x00
+#define MMU_SYSCONFIG           0x10
+#define MMU_SYSSTATUS           0x14
+#define MMU_IRQSTATUS           0x18
+#define MMU_IRQENABLE           0x1c
+#define MMU_WALKING_ST          0x40
+#define MMU_CNTL                0x44
+#define MMU_FAULT_AD            0x48
+#define MMU_TTB                 0x4c
+#define MMU_LOCK                0x50
+#define MMU_LD_TLB              0x54
+#define MMU_CAM                 0x58
+#define MMU_RAM                 0x5c
+#define MMU_GFLUSH              0x60
+#define MMU_FLUSH_ENTRY         0x64
+#define MMU_READ_CAM            0x68
+#define MMU_READ_RAM            0x6c
+#define MMU_EMU_FAULT_AD        0x70
+#define MMU_REG_SIZE            256
+/*
+ * MMU Register bit definitions
+ */
+#define MMU_LOCK_BASE_SHIFT     10
+#define MMU_LOCK_BASE_MASK      (0x1f << MMU_LOCK_BASE_SHIFT)
+#define MMU_LOCK_BASE(x)        \
+        ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
+#define MMU_LOCK_VICT_SHIFT     4
+#define MMU_LOCK_VICT_MASK      (0x1f << MMU_LOCK_VICT_SHIFT)
+#define MMU_LOCK_VICT(x)        \
+        ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
+#define MMU_CAM_VATAG_SHIFT     12
+#define MMU_CAM_VATAG_MASK \
+        ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
+#define MMU_CAM_P               (1 << 3)
+#define MMU_CAM_V               (1 << 2)
+#define MMU_CAM_PGSZ_MASK       3
+#define MMU_CAM_PGSZ_1M         (0 << 0)
+#define MMU_CAM_PGSZ_64K        (1 << 0)
+#define MMU_CAM_PGSZ_4K         (2 << 0)
+#define MMU_CAM_PGSZ_16M        (3 << 0)
+#define MMU_RAM_PADDR_SHIFT     12
+#define MMU_RAM_PADDR_MASK \
+        ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
+#define MMU_RAM_ENDIAN_SHIFT    9
+#define MMU_RAM_ENDIAN_MASK     (1 << MMU_RAM_ENDIAN_SHIFT)
+#define MMU_RAM_ENDIAN_BIG      (1 << MMU_RAM_ENDIAN_SHIFT)
+#define MMU_RAM_ENDIAN_LITTLE   (0 << MMU_RAM_ENDIAN_SHIFT)
+#define MMU_RAM_ELSZ_SHIFT      7
+#define MMU_RAM_ELSZ_MASK       (3 << MMU_RAM_ELSZ_SHIFT)
+#define MMU_RAM_ELSZ_8          (0 << MMU_RAM_ELSZ_SHIFT)
+#define MMU_RAM_ELSZ_16         (1 << MMU_RAM_ELSZ_SHIFT)
+#define MMU_RAM_ELSZ_32         (2 << MMU_RAM_ELSZ_SHIFT)
+#define MMU_RAM_ELSZ_NONE       (3 << MMU_RAM_ELSZ_SHIFT)
+#define MMU_RAM_MIXED_SHIFT     6
+#define MMU_RAM_MIXED_MASK      (1 << MMU_RAM_MIXED_SHIFT)
+#define MMU_RAM_MIXED           MMU_RAM_MIXED_MASK
+/*
+ * register accessors
+ */
+static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
+{
+        return __raw_readl(obj->regbase + offs);
+}
+static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
+{
+        __raw_writel(val, obj->regbase + offs);
+}
+#endif /* __MACH_IOMMU2_H */
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h
new file mode 100644
index 000000000000..bdc7ce5d7a4a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iovmm.h
@@ -0,0 +1,94 @@
+/*
+ * omap iommu: simple virtual address space management
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __IOMMU_MMAP_H
+#define __IOMMU_MMAP_H
+struct iovm_struct {
+        struct iommu            *iommu; /* iommu object which this belongs to */
+        u32                     da_start; /* area definition */
+        u32                     da_end;
+        u32                     flags; /* IOVMF_: see below */
+        struct list_head        list; /* linked in ascending order */
+        const struct sg_table   *sgt; /* keep 'page' <-> 'da' mapping */
+        void                    *va; /* mpu side mapped address */
+};
+/*
+ * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
+ *
+ * lower 16 bit is used for h/w and upper 16 bit is for s/w.
+ */
+#define IOVMF_SW_SHIFT          16
+#define IOVMF_HW_SIZE           (1 << IOVMF_SW_SHIFT)
+#define IOVMF_HW_MASK           (IOVMF_HW_SIZE - 1)
+#define IOVMF_SW_MASK           (~IOVMF_HW_MASK)UL
+/*
+ * iovma: h/w flags derived from cam and ram attribute
+ */
+#define IOVMF_CAM_MASK          (~((1 << 10) - 1))
+#define IOVMF_RAM_MASK          (~IOVMF_CAM_MASK)
+#define IOVMF_PGSZ_MASK         (3 << 0)
+#define IOVMF_PGSZ_1M           MMU_CAM_PGSZ_1M
+#define IOVMF_PGSZ_64K          MMU_CAM_PGSZ_64K
+#define IOVMF_PGSZ_4K           MMU_CAM_PGSZ_4K
+#define IOVMF_PGSZ_16M          MMU_CAM_PGSZ_16M
+#define IOVMF_ENDIAN_MASK       (1 << 9)
+#define IOVMF_ENDIAN_BIG        MMU_RAM_ENDIAN_BIG
+#define IOVMF_ENDIAN_LITTLE     MMU_RAM_ENDIAN_LITTLE
+#define IOVMF_ELSZ_MASK         (3 << 7)
+#define IOVMF_ELSZ_8            MMU_RAM_ELSZ_8
+#define IOVMF_ELSZ_16           MMU_RAM_ELSZ_16
+#define IOVMF_ELSZ_32           MMU_RAM_ELSZ_32
+#define IOVMF_ELSZ_NONE         MMU_RAM_ELSZ_NONE
+#define IOVMF_MIXED_MASK        (1 << 6)
+#define IOVMF_MIXED             MMU_RAM_MIXED
+/*
+ * iovma: s/w flags, used for mapping and umapping internally.
+ */
+#define IOVMF_MMIO              (1 << IOVMF_SW_SHIFT)
+#define IOVMF_ALLOC             (2 << IOVMF_SW_SHIFT)
+#define IOVMF_ALLOC_MASK        (3 << IOVMF_SW_SHIFT)
+/* "superpages" is supported just with physically linear pages */
+#define IOVMF_DISCONT           (1 << (2 + IOVMF_SW_SHIFT))
+#define IOVMF_LINEAR            (2 << (2 + IOVMF_SW_SHIFT))
+#define IOVMF_LINEAR_MASK       (3 << (2 + IOVMF_SW_SHIFT))
+#define IOVMF_DA_FIXED          (1 << (4 + IOVMF_SW_SHIFT))
+#define IOVMF_DA_ANON           (2 << (4 + IOVMF_SW_SHIFT))
+#define IOVMF_DA_MASK           (3 << (4 + IOVMF_SW_SHIFT))
+extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
+extern u32 iommu_vmap(struct iommu *obj, u32 da,
+                        const struct sg_table *sgt, u32 flags);
+extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
+extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
+                           u32 flags);
+extern void iommu_vfree(struct iommu *obj, const u32 da);
+extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
+                        u32 flags);
+extern void iommu_kunmap(struct iommu *obj, u32 da);
+extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
+                           u32 flags);
+extern void iommu_kfree(struct iommu *obj, u32 da);
+extern void *da_to_va(struct iommu *obj, u32 da);
+#endif /* __IOMMU_MMAP_H */
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 7f57ee66f364..fb7cb7723990 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -4,6 +4,9 @@
 *  Copyright (C) Greg Lonnon 2001
 *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
@@ -422,6 +425,94 @@
 #define INT_34XX_BENCH_MPU_EMUL 3
+#define IRQ_GIC_START           32
+#define INT_44XX_LOCALTIMER_IRQ 29
+#define INT_44XX_LOCALWDT_IRQ   30
+#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
+#define INT_44XX_SSM_ABORT_IRQ  (6 + IRQ_GIC_START)
+#define INT_44XX_SYS_NIRQ       (7 + IRQ_GIC_START)
+#define INT_44XX_D2D_FW_IRQ     (8 + IRQ_GIC_START)
+#define INT_44XX_PRCM_MPU_IRQ   (11 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ0      (12 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ1      (13 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ2      (14 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ3      (15 + IRQ_GIC_START)
+#define INT_44XX_ISS_IRQ        (24 + IRQ_GIC_START)
+#define INT_44XX_DSS_IRQ        (25 + IRQ_GIC_START)
+#define INT_44XX_MAIL_U0_MPU    (26 + IRQ_GIC_START)
+#define INT_44XX_DSP_MMU        (28 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER1       (37 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER2       (38 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER3       (39 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER4       (40 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER5       (41 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER6       (42 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER7       (43 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER8       (44 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER9       (45 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER10      (46 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER11      (47 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER12      (95 + IRQ_GIC_START)
+#define INT_44XX_SHA1MD5        (51 + IRQ_GIC_START)
+#define INT_44XX_I2C1_IRQ       (56 + IRQ_GIC_START)
+#define INT_44XX_I2C2_IRQ       (57 + IRQ_GIC_START)
+#define INT_44XX_HDQ_IRQ        (58 + IRQ_GIC_START)
+#define INT_44XX_SPI1_IRQ       (65 + IRQ_GIC_START)
+#define INT_44XX_SPI2_IRQ       (66 + IRQ_GIC_START)
+#define INT_44XX_HSI_1_IRQ0     (67 + IRQ_GIC_START)
+#define INT_44XX_HSI_2_IRQ1     (68 + IRQ_GIC_START)
+#define INT_44XX_HSI_1_DMAIRQ   (71 + IRQ_GIC_START)
+#define INT_44XX_UART1_IRQ      (72 + IRQ_GIC_START)
+#define INT_44XX_UART2_IRQ      (73 + IRQ_GIC_START)
+#define INT_44XX_UART3_IRQ      (74 + IRQ_GIC_START)
+#define INT_44XX_UART4_IRQ      (70 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_NISO   (76 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_ISO    (77 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_HGEN   (78 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_HSOF   (79 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_OTG    (80 + IRQ_GIC_START)
+#define INT_44XX_MCBSP4_IRQ_TX  (81 + IRQ_GIC_START)
+#define INT_44XX_MCBSP4_IRQ_RX  (82 + IRQ_GIC_START)
+#define INT_44XX_MMC_IRQ        (83 + IRQ_GIC_START)
+#define INT_44XX_MMC2_IRQ       (86 + IRQ_GIC_START)
+#define INT_44XX_MCBSP2_IRQ_TX  (89 + IRQ_GIC_START)
+#define INT_44XX_MCBSP2_IRQ_RX  (90 + IRQ_GIC_START)
+#define INT_44XX_SPI3_IRQ       (91 + IRQ_GIC_START)
+#define INT_44XX_SPI5_IRQ       (69 + IRQ_GIC_START)
+#define INT_44XX_MCBSP5_IRQ     (16 + IRQ_GIC_START)
+#define INT_44xX_MCBSP1_IRQ     (17 + IRQ_GIC_START)
+#define INT_44XX_MCBSP2_IRQ     (22 + IRQ_GIC_START)
+#define INT_44XX_MCBSP3_IRQ     (23 + IRQ_GIC_START)
+#define INT_44XX_MCBSP4_IRQ     (27 + IRQ_GIC_START)
+#define INT_44XX_HS_USB_MC      (92 + IRQ_GIC_START)
+#define INT_44XX_HS_USB_DMA     (93 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK1     (29 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK2     (30 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK3     (31 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK4     (32 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK5     (33 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK6     (34 + IRQ_GIC_START)
+#define INT_44XX_USIM_IRQ       (35 + IRQ_GIC_START)
+#define INT_44XX_WDT3_IRQ       (36 + IRQ_GIC_START)
+#define INT_44XX_SPI4_IRQ       (48 + IRQ_GIC_START)
+#define INT_44XX_SHA1MD52_IRQ   (49 + IRQ_GIC_START)
+#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
+#define INT_44XX_SHA1MD51_IRQ   (51 + IRQ_GIC_START)
+#define INT_44XX_RNG_IRQ        (52 + IRQ_GIC_START)
+#define INT_44XX_I2C3_IRQ       (61 + IRQ_GIC_START)
+#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
+#define INT_44XX_PBIAS_IRQ      (75 + IRQ_GIC_START)
+#define INT_44XX_OHCI_IRQ       (76 + IRQ_GIC_START)
+#define INT_44XX_EHCI_IRQ       (77 + IRQ_GIC_START)
+#define INT_44XX_TLL_IRQ        (78 + IRQ_GIC_START)
+#define INT_44XX_PARTHASH_IRQ   (79 + IRQ_GIC_START)
+#define INT_44XX_MMC3_IRQ       (94 + IRQ_GIC_START)
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
 * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES     192
@@ -467,6 +558,7 @@
 #ifndef __ASSEMBLY__
 extern void omap_init_irq(void);
+extern int omap_irq_pending(void);
 #endif
 #include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/mach/keypad.h
index 232923aaf61d..45ea3ae3c995 100644
--- a/arch/arm/plat-omap/include/mach/keypad.h
+++ b/arch/arm/plat-omap/include/mach/keypad.h
@@ -33,7 +33,11 @@ struct omap_kp_platform_data {
 #define GROUP_3         (3 << 16)
 #define GROUP_MASK      GROUP_3
+#define KEY_PERSISTENT          0x00800000
+#define KEYNUM_MASK             0x00EFFFFF
 #define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
+#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
+                                                KEY_PERSISTENT)
 #endif
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index 99ed564d9277..9ad41dc484c1 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -38,7 +38,8 @@
 */
 #if defined(CONFIG_ARCH_OMAP1)
 #define PHYS_OFFSET             UL(0x10000000)
-#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                        defined(CONFIG_ARCH_OMAP4)
 #define PHYS_OFFSET             UL(0x80000000)
 #endif
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index 24335d4932f5..696edfc145a6 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -85,23 +85,5 @@
 #define OMAP24XX_SEC_AES_BASE   (OMAP24XX_SEC_BASE + 0x6000)
 #define OMAP24XX_SEC_PKA_BASE   (OMAP24XX_SEC_BASE + 0x8000)
-#if defined(CONFIG_ARCH_OMAP2420)
-#define OMAP2_32KSYNCT_BASE     OMAP2420_32KSYNCT_BASE
-#define OMAP2_PRCM_BASE         OMAP2420_PRCM_BASE
-#define OMAP2_CM_BASE           OMAP2420_CM_BASE
-#define OMAP2_PRM_BASE          OMAP2420_PRM_BASE
-#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
-#elif defined(CONFIG_ARCH_OMAP2430)
-#define OMAP2_32KSYNCT_BASE     OMAP2430_32KSYNCT_BASE
-#define OMAP2_PRCM_BASE         OMAP2430_PRCM_BASE
-#define OMAP2_CM_BASE           OMAP2430_CM_BASE
-#define OMAP2_PRM_BASE          OMAP2430_PRM_BASE
-#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
-#endif
 #endif /* __ASM_ARCH_OMAP24XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h
index ab640151d3ec..f8d186a73712 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/mach/omap34xx.h
@@ -31,13 +31,9 @@
 #define L4_34XX_BASE            0x48000000
 #define L4_WK_34XX_BASE         0x48300000
-#define L4_WK_OMAP_BASE         L4_WK_34XX_BASE
 #define L4_PER_34XX_BASE        0x49000000
-#define L4_PER_OMAP_BASE        L4_PER_34XX_BASE
 #define L4_EMU_34XX_BASE        0x54000000
-#define L4_EMU_BASE             L4_EMU_34XX_BASE
 #define L3_34XX_BASE            0x68000000
-#define L3_OMAP_BASE            L3_34XX_BASE
 #define OMAP3430_32KSYNCT_BASE  0x48320000
 #define OMAP3430_CM_BASE        0x48004800
@@ -83,15 +79,6 @@
 #define OMAP34XX_MAILBOX_BASE           (L4_34XX_BASE + 0x94000)
-#if defined(CONFIG_ARCH_OMAP3430)
-#define OMAP2_32KSYNCT_BASE             OMAP3430_32KSYNCT_BASE
-#define OMAP2_CM_BASE                   OMAP3430_CM_BASE
-#define OMAP2_PRM_BASE                  OMAP3430_PRM_BASE
-#define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
-#endif
 #define OMAP34XX_DSP_BASE       0x58000000
 #define OMAP34XX_DSP_MEM_BASE   (OMAP34XX_DSP_BASE + 0x0)
 #define OMAP34XX_DSP_IPI_BASE   (OMAP34XX_DSP_BASE + 0x1000000)
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h
new file mode 100644
index 000000000000..15dec7f1c7c0
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap44xx.h
@@ -0,0 +1,46 @@
+/*:
+ * Address mappings and base address for OMAP4 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP44XX_H
+#define __ASM_ARCH_OMAP44XX_H
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_44XX_BASE                    0x4a000000
+#define L4_WK_44XX_BASE                 0x4a300000
+#define L4_PER_44XX_BASE                0x48000000
+#define L4_EMU_44XX_BASE                0x54000000
+#define L3_44XX_BASE                    0x44000000
+#define OMAP4430_32KSYNCT_BASE          0x4a304000
+#define OMAP4430_CM_BASE                0x4a004000
+#define OMAP4430_PRM_BASE               0x48306000
+#define OMAP44XX_GPMC_BASE              0x50000000
+#define OMAP443X_SCM_BASE               0x4a002000
+#define OMAP443X_CTRL_BASE              OMAP443X_SCM_BASE
+#define OMAP44XX_IC_BASE                0x48200000
+#define OMAP44XX_IVA_INTC_BASE          0x40000000
+#define IRQ_SIR_IRQ                     0x0040
+#define OMAP44XX_GIC_DIST_BASE          0x48241000
+#define OMAP44XX_GIC_CPU_BASE           0x48240100
+#define OMAP44XX_VA_GIC_CPU_BASE        IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
+#define OMAP44XX_SCU_BASE               0x48240000
+#define OMAP44XX_VA_SCU_BASE            IO_ADDRESS(OMAP44XX_SCU_BASE)
+#define OMAP44XX_LOCAL_TWD_BASE         0x48240600
+#define OMAP44XX_VA_LOCAL_TWD_BASE      IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
+#define OMAP44XX_LOCAL_TWD_SIZE         0x00000100
+#define OMAP44XX_WKUPGEN_BASE           0x48281000
+#define OMAP44XX_VA_WKUPGEN_BASE        IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
+#endif /* __ASM_ARCH_OMAP44XX_H */
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h
index 4649d302c263..72f433d7d827 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/mach/onenand.h
@@ -9,8 +9,12 @@
 * published by the Free Software Foundation.
 */
+#include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#define ONENAND_SYNC_READ       (1 << 0)
+#define ONENAND_SYNC_READWRITE  (1 << 1)
 struct omap_onenand_platform_data {
        int                     cs;
        int                     gpio_irq;
@@ -18,8 +22,22 @@ struct omap_onenand_platform_data {
        int                     nr_parts;
        int                     (*onenand_setup)(void __iomem *, int freq);
        int                     dma_channel;
+        u8                      flags;
 };
-int omap2_onenand_rephase(void);
 #define ONENAND_MAX_PARTITIONS 8
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
+#else
+#define board_onenand_data      NULL
+static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
+{
+}
+#endif
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 8a676a04be48..13abd02d1527 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -1,5 +1,8 @@
 /*
- *  arch/arm/plat-omap/include/mach/serial.h
+ * arch/arm/plat-omap/include/mach/serial.h
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -15,19 +18,28 @@
 #define OMAP_UART1_BASE         0xfffb0000
 #define OMAP_UART2_BASE         0xfffb0800
 #define OMAP_UART3_BASE         0xfffb9800
+#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP2)
 /* OMAP2 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x4806e000
+#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP3)
 /* OMAP3 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x49020000
+#define OMAP_MAX_NR_PORTS       3
+#elif defined(CONFIG_ARCH_OMAP4)
+/* OMAP4 serial ports */
+#define OMAP_UART1_BASE         0x4806a000
+#define OMAP_UART2_BASE         0x4806c000
+#define OMAP_UART3_BASE         0x48020000
+#define OMAP_UART4_BASE         0x4806e000
+#define OMAP_MAX_NR_PORTS       4
 #endif
-#define OMAP_MAX_NR_PORTS       3
 #define OMAP1510_BASE_BAUD      (12000000/16)
 #define OMAP16XX_BASE_BAUD      (48000000/16)
 #define OMAP24XX_BASE_BAUD      (48000000/16)
@@ -40,4 +52,13 @@
                        __ret;                                          \
                        })
+#ifndef __ASSEMBLER__
+extern void omap_serial_init(void);
+extern int omap_uart_can_sleep(void);
+extern void omap_uart_check_wakeup(void);
+extern void omap_uart_prepare_suspend(void);
+extern void omap_uart_prepare_idle(int num);
+extern void omap_uart_resume_idle(int num);
+#endif
 #endif
diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/mach/smp.h
new file mode 100644
index 000000000000..dcaa8fde7063
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/smp.h
@@ -0,0 +1,51 @@
+/*
+ * OMAP4 machine specific smp.h
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Author:
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Interface functions needed for the SMP. This file is based on arm
+ * realview smp platform.
+ * Copyright (c) 2003 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_SMP_H
+#define OMAP_ARCH_SMP_H
+#include <asm/hardware/gic.h>
+/*
+ * set_event() is used to wake up secondary core from wfe using sev. ROM
+ * code puts the second core into wfe(standby).
+ *
+ */
+#define set_event()     __asm__ __volatile__ ("sev" : : : "memory")
+/* Needed for secondary core boot */
+extern void omap_secondary_startup(void);
+/*
+ * We use Soft IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+        gic_raise_softirq(mask, 1);
+}
+/*
+ * Read MPIDR: Multiprocessor affinity register
+ */
+#define hard_smp_processor_id()                 \
+        ({                                              \
+                unsigned int cpunum;                    \
+                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
+                        : "=r" (cpunum));               \
+                cpunum &= 0x0F;                         \
+        })
+#endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index ab35d622dcf5..dca7c16ae903 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
                                     u32 sdrc_actim_ctrla,
-                                     u32 sdrc_actim_ctrlb, u32 m2);
+                                     u32 sdrc_actim_ctrlb, u32 m2,
+                                     u32 unlock_dll);
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
                                          u32 sdrc_actim_ctrla,
-                                          u32 sdrc_actim_ctrlb, u32 m2);
+                                          u32 sdrc_actim_ctrlb, u32 m2,
+                                          u32 unlock_dll);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 #endif
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
index 69f0ceed500b..f337e1761e2c 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/mach/usb.h
@@ -27,13 +27,7 @@
 #define UDC_BASE                        OMAP2_UDC_BASE
 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
-#ifdef CONFIG_USB_MUSB_SOC
 extern void usb_musb_init(void);
-#else
-static inline void usb_musb_init(void)
-{
-}
-#endif
 #endif
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
index dc104cd96197..b97dfafeebda 100644
--- a/arch/arm/plat-omap/include/mach/vmalloc.h
+++ b/arch/arm/plat-omap/include/mach/vmalloc.h
@@ -17,5 +17,5 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       (PAGE_OFFSET + 0x18000000)
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index af326efc1ad3..9b42d72d96cf 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -1,3 +1,14 @@
+/*
+ * Common io.c file
+ * This file is created by Russell King <rmk+kernel@arm.linux.org.uk>
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/mm.h>
@@ -7,6 +18,7 @@
 #include <mach/omap16xx.h>
 #include <mach/omap24xx.h>
 #include <mach/omap34xx.h>
+#include <mach/omap44xx.h>
 #define BETWEEN(p,st,sz)        ((p) >= (st) && (p) < ((st) + (sz)))
 #define XLATE(p,pst,vst)        ((void __iomem *)((p) - (pst) + (vst)))
@@ -92,7 +104,22 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                        return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
        }
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        if (cpu_is_omap44xx()) {
+                if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE))
+                        return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
+                if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
+                        return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
+                if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
+                        return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
+                if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
+                        return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
+                if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
+                        return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
+                if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
+                        return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
+        }
+#endif
        return __arm_ioremap(p, size, type);
 }
 EXPORT_SYMBOL(omap_ioremap);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
new file mode 100644
index 000000000000..4cf449fa2cb5
--- /dev/null
+++ b/arch/arm/plat-omap/iommu.c
@@ -0,0 +1,996 @@
+/*
+ * omap iommu: tlb and pagetable primitives
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
+ *              Paul Mundt and Toshihiro Kobayashi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <asm/cacheflush.h>
+#include <mach/iommu.h>
+#include "iopgtable.h"
+/* accommodate the difference between omap1 and omap2/3 */
+static const struct iommu_functions *arch_iommu;
+static struct platform_driver omap_iommu_driver;
+static struct kmem_cache *iopte_cachep;
+/**
+ * install_iommu_arch - Install archtecure specific iommu functions
+ * @ops:        a pointer to architecture specific iommu functions
+ *
+ * There are several kind of iommu algorithm(tlb, pagetable) among
+ * omap series. This interface installs such an iommu algorighm.
+ **/
+int install_iommu_arch(const struct iommu_functions *ops)
+{
+        if (arch_iommu)
+                return -EBUSY;
+        arch_iommu = ops;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(install_iommu_arch);
+/**
+ * uninstall_iommu_arch - Uninstall archtecure specific iommu functions
+ * @ops:        a pointer to architecture specific iommu functions
+ *
+ * This interface uninstalls the iommu algorighm installed previously.
+ **/
+void uninstall_iommu_arch(const struct iommu_functions *ops)
+{
+        if (arch_iommu != ops)
+                pr_err("%s: not your arch\n", __func__);
+        arch_iommu = NULL;
+}
+EXPORT_SYMBOL_GPL(uninstall_iommu_arch);
+/**
+ * iommu_save_ctx - Save registers for pm off-mode support
+ * @obj:        target iommu
+ **/
+void iommu_save_ctx(struct iommu *obj)
+{
+        arch_iommu->save_ctx(obj);
+}
+EXPORT_SYMBOL_GPL(iommu_save_ctx);
+/**
+ * iommu_restore_ctx - Restore registers for pm off-mode support
+ * @obj:        target iommu
+ **/
+void iommu_restore_ctx(struct iommu *obj)
+{
+        arch_iommu->restore_ctx(obj);
+}
+EXPORT_SYMBOL_GPL(iommu_restore_ctx);
+/**
+ * iommu_arch_version - Return running iommu arch version
+ **/
+u32 iommu_arch_version(void)
+{
+        return arch_iommu->version;
+}
+EXPORT_SYMBOL_GPL(iommu_arch_version);
+static int iommu_enable(struct iommu *obj)
+{
+        int err;
+        if (!obj)
+                return -EINVAL;
+        clk_enable(obj->clk);
+        err = arch_iommu->enable(obj);
+        clk_disable(obj->clk);
+        return err;
+}
+static void iommu_disable(struct iommu *obj)
+{
+        if (!obj)
+                return;
+        clk_enable(obj->clk);
+        arch_iommu->disable(obj);
+        clk_disable(obj->clk);
+}
+/*
+ *      TLB operations
+ */
+void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
+{
+        BUG_ON(!cr || !e);
+        arch_iommu->cr_to_e(cr, e);
+}
+EXPORT_SYMBOL_GPL(iotlb_cr_to_e);
+static inline int iotlb_cr_valid(struct cr_regs *cr)
+{
+        if (!cr)
+                return -EINVAL;
+        return arch_iommu->cr_valid(cr);
+}
+static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj,
+                                             struct iotlb_entry *e)
+{
+        if (!e)
+                return NULL;
+        return arch_iommu->alloc_cr(obj, e);
+}
+u32 iotlb_cr_to_virt(struct cr_regs *cr)
+{
+        return arch_iommu->cr_to_virt(cr);
+}
+EXPORT_SYMBOL_GPL(iotlb_cr_to_virt);
+static u32 get_iopte_attr(struct iotlb_entry *e)
+{
+        return arch_iommu->get_pte_attr(e);
+}
+static u32 iommu_report_fault(struct iommu *obj, u32 *da)
+{
+        return arch_iommu->fault_isr(obj, da);
+}
+static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
+{
+        u32 val;
+        val = iommu_read_reg(obj, MMU_LOCK);
+        l->base = MMU_LOCK_BASE(val);
+        l->vict = MMU_LOCK_VICT(val);
+        BUG_ON(l->base != 0); /* Currently no preservation is used */
+}
+static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
+{
+        u32 val;
+        BUG_ON(l->base != 0); /* Currently no preservation is used */
+        val = (l->base << MMU_LOCK_BASE_SHIFT);
+        val |= (l->vict << MMU_LOCK_VICT_SHIFT);
+        iommu_write_reg(obj, val, MMU_LOCK);
+}
+static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr)
+{
+        arch_iommu->tlb_read_cr(obj, cr);
+}
+static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr)
+{
+        arch_iommu->tlb_load_cr(obj, cr);
+        iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
+        iommu_write_reg(obj, 1, MMU_LD_TLB);
+}
+/**
+ * iotlb_dump_cr - Dump an iommu tlb entry into buf
+ * @obj:        target iommu
+ * @cr:         contents of cam and ram register
+ * @buf:        output buffer
+ **/
+static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
+                                    char *buf)
+{
+        BUG_ON(!cr || !buf);
+        return arch_iommu->dump_cr(obj, cr, buf);
+}
+/**
+ * load_iotlb_entry - Set an iommu tlb entry
+ * @obj:        target iommu
+ * @e:          an iommu tlb entry info
+ **/
+int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
+{
+        int i;
+        int err = 0;
+        struct iotlb_lock l;
+        struct cr_regs *cr;
+        if (!obj || !obj->nr_tlb_entries || !e)
+                return -EINVAL;
+        clk_enable(obj->clk);
+        for (i = 0; i < obj->nr_tlb_entries; i++) {
+                struct cr_regs tmp;
+                iotlb_lock_get(obj, &l);
+                l.vict = i;
+                iotlb_lock_set(obj, &l);
+                iotlb_read_cr(obj, &tmp);
+                if (!iotlb_cr_valid(&tmp))
+                        break;
+        }
+        if (i == obj->nr_tlb_entries) {
+                dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
+                err = -EBUSY;
+                goto out;
+        }
+        cr = iotlb_alloc_cr(obj, e);
+        if (IS_ERR(cr)) {
+                clk_disable(obj->clk);
+                return PTR_ERR(cr);
+        }
+        iotlb_load_cr(obj, cr);
+        kfree(cr);
+        /* increment victim for next tlb load */
+        if (++l.vict == obj->nr_tlb_entries)
+                l.vict = 0;
+        iotlb_lock_set(obj, &l);
+out:
+        clk_disable(obj->clk);
+        return err;
+}
+EXPORT_SYMBOL_GPL(load_iotlb_entry);
+/**
+ * flush_iotlb_page - Clear an iommu tlb entry
+ * @obj:        target iommu
+ * @da:         iommu device virtual address
+ *
+ * Clear an iommu tlb entry which includes 'da' address.
+ **/
+void flush_iotlb_page(struct iommu *obj, u32 da)
+{
+        struct iotlb_lock l;
+        int i;
+        clk_enable(obj->clk);
+        for (i = 0; i < obj->nr_tlb_entries; i++) {
+                struct cr_regs cr;
+                u32 start;
+                size_t bytes;
+                iotlb_lock_get(obj, &l);
+                l.vict = i;
+                iotlb_lock_set(obj, &l);
+                iotlb_read_cr(obj, &cr);
+                if (!iotlb_cr_valid(&cr))
+                        continue;
+                start = iotlb_cr_to_virt(&cr);
+                bytes = iopgsz_to_bytes(cr.cam & 3);
+                if ((start <= da) && (da < start + bytes)) {
+                        dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
+                                __func__, start, da, bytes);
+                        iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
+                }
+        }
+        clk_disable(obj->clk);
+        if (i == obj->nr_tlb_entries)
+                dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
+}
+EXPORT_SYMBOL_GPL(flush_iotlb_page);
+/**
+ * flush_iotlb_range - Clear an iommu tlb entries
+ * @obj:        target iommu
+ * @start:      iommu device virtual address(start)
+ * @end:        iommu device virtual address(end)
+ *
+ * Clear an iommu tlb entry which includes 'da' address.
+ **/
+void flush_iotlb_range(struct iommu *obj, u32 start, u32 end)
+{
+        u32 da = start;
+        while (da < end) {
+                flush_iotlb_page(obj, da);
+                /* FIXME: Optimize for multiple page size */
+                da += IOPTE_SIZE;
+        }
+}
+EXPORT_SYMBOL_GPL(flush_iotlb_range);
+/**
+ * flush_iotlb_all - Clear all iommu tlb entries
+ * @obj:        target iommu
+ **/
+void flush_iotlb_all(struct iommu *obj)
+{
+        struct iotlb_lock l;
+        clk_enable(obj->clk);
+        l.base = 0;
+        l.vict = 0;
+        iotlb_lock_set(obj, &l);
+        iommu_write_reg(obj, 1, MMU_GFLUSH);
+        clk_disable(obj->clk);
+}
+EXPORT_SYMBOL_GPL(flush_iotlb_all);
+#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
+ssize_t iommu_dump_ctx(struct iommu *obj, char *buf)
+{
+        ssize_t bytes;
+        if (!obj || !buf)
+                return -EINVAL;
+        clk_enable(obj->clk);
+        bytes = arch_iommu->dump_ctx(obj, buf);
+        clk_disable(obj->clk);
+        return bytes;
+}
+EXPORT_SYMBOL_GPL(iommu_dump_ctx);
+static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs)
+{
+        int i;
+        struct iotlb_lock saved, l;
+        struct cr_regs *p = crs;
+        clk_enable(obj->clk);
+        iotlb_lock_get(obj, &saved);
+        memcpy(&l, &saved, sizeof(saved));
+        for (i = 0; i < obj->nr_tlb_entries; i++) {
+                struct cr_regs tmp;
+                iotlb_lock_get(obj, &l);
+                l.vict = i;
+                iotlb_lock_set(obj, &l);
+                iotlb_read_cr(obj, &tmp);
+                if (!iotlb_cr_valid(&tmp))
+                        continue;
+                *p++ = tmp;
+        }
+        iotlb_lock_set(obj, &saved);
+        clk_disable(obj->clk);
+        return  p - crs;
+}
+/**
+ * dump_tlb_entries - dump cr arrays to given buffer
+ * @obj:        target iommu
+ * @buf:        output buffer
+ **/
+size_t dump_tlb_entries(struct iommu *obj, char *buf)
+{
+        int i, n;
+        struct cr_regs *cr;
+        char *p = buf;
+        cr = kcalloc(obj->nr_tlb_entries, sizeof(*cr), GFP_KERNEL);
+        if (!cr)
+                return 0;
+        n = __dump_tlb_entries(obj, cr);
+        for (i = 0; i < n; i++)
+                p += iotlb_dump_cr(obj, cr + i, p);
+        kfree(cr);
+        return p - buf;
+}
+EXPORT_SYMBOL_GPL(dump_tlb_entries);
+int foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
+{
+        return driver_for_each_device(&omap_iommu_driver.driver,
+                                      NULL, data, fn);
+}
+EXPORT_SYMBOL_GPL(foreach_iommu_device);
+#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
+/*
+ *      H/W pagetable operations
+ */
+static void flush_iopgd_range(u32 *first, u32 *last)
+{
+        /* FIXME: L2 cache should be taken care of if it exists */
+        do {
+                asm("mcr        p15, 0, %0, c7, c10, 1 @ flush_pgd"
+                    : : "r" (first));
+                first += L1_CACHE_BYTES / sizeof(*first);
+        } while (first <= last);
+}
+static void flush_iopte_range(u32 *first, u32 *last)
+{
+        /* FIXME: L2 cache should be taken care of if it exists */
+        do {
+                asm("mcr        p15, 0, %0, c7, c10, 1 @ flush_pte"
+                    : : "r" (first));
+                first += L1_CACHE_BYTES / sizeof(*first);
+        } while (first <= last);
+}
+static void iopte_free(u32 *iopte)
+{
+        /* Note: freed iopte's must be clean ready for re-use */
+        kmem_cache_free(iopte_cachep, iopte);
+}
+static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da)
+{
+        u32 *iopte;
+        /* a table has already existed */
+        if (*iopgd)
+                goto pte_ready;
+        /*
+         * do the allocation outside the page table lock
+         */
+        spin_unlock(&obj->page_table_lock);
+        iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
+        spin_lock(&obj->page_table_lock);
+        if (!*iopgd) {
+                if (!iopte)
+                        return ERR_PTR(-ENOMEM);
+                *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
+                flush_iopgd_range(iopgd, iopgd);
+                dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
+        } else {
+                /* We raced, free the reduniovant table */
+                iopte_free(iopte);
+        }
+pte_ready:
+        iopte = iopte_offset(iopgd, da);
+        dev_vdbg(obj->dev,
+                 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
+                 __func__, da, iopgd, *iopgd, iopte, *iopte);
+        return iopte;
+}
+static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot)
+{
+        u32 *iopgd = iopgd_offset(obj, da);
+        *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
+        flush_iopgd_range(iopgd, iopgd);
+        return 0;
+}
+static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot)
+{
+        u32 *iopgd = iopgd_offset(obj, da);
+        int i;
+        for (i = 0; i < 16; i++)
+                *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
+        flush_iopgd_range(iopgd, iopgd + 15);
+        return 0;
+}
+static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot)
+{
+        u32 *iopgd = iopgd_offset(obj, da);
+        u32 *iopte = iopte_alloc(obj, iopgd, da);
+        if (IS_ERR(iopte))
+                return PTR_ERR(iopte);
+        *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
+        flush_iopte_range(iopte, iopte);
+        dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
+                 __func__, da, pa, iopte, *iopte);
+        return 0;
+}
+static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot)
+{
+        u32 *iopgd = iopgd_offset(obj, da);
+        u32 *iopte = iopte_alloc(obj, iopgd, da);
+        int i;
+        if (IS_ERR(iopte))
+                return PTR_ERR(iopte);
+        for (i = 0; i < 16; i++)
+                *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
+        flush_iopte_range(iopte, iopte + 15);
+        return 0;
+}
+static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e)
+{
+        int (*fn)(struct iommu *, u32, u32, u32);
+        u32 prot;
+        int err;
+        if (!obj || !e)
+                return -EINVAL;
+        switch (e->pgsz) {
+        case MMU_CAM_PGSZ_16M:
+                fn = iopgd_alloc_super;
+                break;
+        case MMU_CAM_PGSZ_1M:
+                fn = iopgd_alloc_section;
+                break;
+        case MMU_CAM_PGSZ_64K:
+                fn = iopte_alloc_large;
+                break;
+        case MMU_CAM_PGSZ_4K:
+                fn = iopte_alloc_page;
+                break;
+        default:
+                fn = NULL;
+                BUG();
+                break;
+        }
+        prot = get_iopte_attr(e);
+        spin_lock(&obj->page_table_lock);
+        err = fn(obj, e->da, e->pa, prot);
+        spin_unlock(&obj->page_table_lock);
+        return err;
+}
+/**
+ * iopgtable_store_entry - Make an iommu pte entry
+ * @obj:        target iommu
+ * @e:          an iommu tlb entry info
+ **/
+int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e)
+{
+        int err;
+        flush_iotlb_page(obj, e->da);
+        err = iopgtable_store_entry_core(obj, e);
+#ifdef PREFETCH_IOTLB
+        if (!err)
+                load_iotlb_entry(obj, e);
+#endif
+        return err;
+}
+EXPORT_SYMBOL_GPL(iopgtable_store_entry);
+/**
+ * iopgtable_lookup_entry - Lookup an iommu pte entry
+ * @obj:        target iommu
+ * @da:         iommu device virtual address
+ * @ppgd:       iommu pgd entry pointer to be returned
+ * @ppte:       iommu pte entry pointer to be returned
+ **/
+void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
+{
+        u32 *iopgd, *iopte = NULL;
+        iopgd = iopgd_offset(obj, da);
+        if (!*iopgd)
+                goto out;
+        if (*iopgd & IOPGD_TABLE)
+                iopte = iopte_offset(iopgd, da);
+out:
+        *ppgd = iopgd;
+        *ppte = iopte;
+}
+EXPORT_SYMBOL_GPL(iopgtable_lookup_entry);
+static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
+{
+        size_t bytes;
+        u32 *iopgd = iopgd_offset(obj, da);
+        int nent = 1;
+        if (!*iopgd)
+                return 0;
+        if (*iopgd & IOPGD_TABLE) {
+                int i;
+                u32 *iopte = iopte_offset(iopgd, da);
+                bytes = IOPTE_SIZE;
+                if (*iopte & IOPTE_LARGE) {
+                        nent *= 16;
+                        /* rewind to the 1st entry */
+                        iopte = (u32 *)((u32)iopte & IOLARGE_MASK);
+                }
+                bytes *= nent;
+                memset(iopte, 0, nent * sizeof(*iopte));
+                flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
+                /*
+                 * do table walk to check if this table is necessary or not
+                 */
+                iopte = iopte_offset(iopgd, 0);
+                for (i = 0; i < PTRS_PER_IOPTE; i++)
+                        if (iopte[i])
+                                goto out;
+                iopte_free(iopte);
+                nent = 1; /* for the next L1 entry */
+        } else {
+                bytes = IOPGD_SIZE;
+                if (*iopgd & IOPGD_SUPER) {
+                        nent *= 16;
+                        /* rewind to the 1st entry */
+                        iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK);
+                }
+                bytes *= nent;
+        }
+        memset(iopgd, 0, nent * sizeof(*iopgd));
+        flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
+out:
+        return bytes;
+}
+/**
+ * iopgtable_clear_entry - Remove an iommu pte entry
+ * @obj:        target iommu
+ * @da:         iommu device virtual address
+ **/
+size_t iopgtable_clear_entry(struct iommu *obj, u32 da)
+{
+        size_t bytes;
+        spin_lock(&obj->page_table_lock);
+        bytes = iopgtable_clear_entry_core(obj, da);
+        flush_iotlb_page(obj, da);
+        spin_unlock(&obj->page_table_lock);
+        return bytes;
+}
+EXPORT_SYMBOL_GPL(iopgtable_clear_entry);
+static void iopgtable_clear_entry_all(struct iommu *obj)
+{
+        int i;
+        spin_lock(&obj->page_table_lock);
+        for (i = 0; i < PTRS_PER_IOPGD; i++) {
+                u32 da;
+                u32 *iopgd;
+                da = i << IOPGD_SHIFT;
+                iopgd = iopgd_offset(obj, da);
+                if (!*iopgd)
+                        continue;
+                if (*iopgd & IOPGD_TABLE)
+                        iopte_free(iopte_offset(iopgd, 0));
+                *iopgd = 0;
+                flush_iopgd_range(iopgd, iopgd);
+        }
+        flush_iotlb_all(obj);
+        spin_unlock(&obj->page_table_lock);
+}
+/*
+ *      Device IOMMU generic operations
+ */
+static irqreturn_t iommu_fault_handler(int irq, void *data)
+{
+        u32 stat, da;
+        u32 *iopgd, *iopte;
+        int err = -EIO;
+        struct iommu *obj = data;
+        if (!obj->refcount)
+                return IRQ_NONE;
+        /* Dynamic loading TLB or PTE */
+        if (obj->isr)
+                err = obj->isr(obj);
+        if (!err)
+                return IRQ_HANDLED;
+        clk_enable(obj->clk);
+        stat = iommu_report_fault(obj, &da);
+        clk_disable(obj->clk);
+        if (!stat)
+                return IRQ_HANDLED;
+        iopgd = iopgd_offset(obj, da);
+        if (!(*iopgd & IOPGD_TABLE)) {
+                dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
+                        da, iopgd, *iopgd);
+                return IRQ_NONE;
+        }
+        iopte = iopte_offset(iopgd, da);
+        dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
+                __func__, da, iopgd, *iopgd, iopte, *iopte);
+        return IRQ_NONE;
+}
+static int device_match_by_alias(struct device *dev, void *data)
+{
+        struct iommu *obj = to_iommu(dev);
+        const char *name = data;
+        pr_debug("%s: %s %s\n", __func__, obj->name, name);
+        return strcmp(obj->name, name) == 0;
+}
+/**
+ * iommu_get - Get iommu handler
+ * @name:       target iommu name
+ **/
+struct iommu *iommu_get(const char *name)
+{
+        int err = -ENOMEM;
+        struct device *dev;
+        struct iommu *obj;
+        dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
+                                 device_match_by_alias);
+        if (!dev)
+                return ERR_PTR(-ENODEV);
+        obj = to_iommu(dev);
+        mutex_lock(&obj->iommu_lock);
+        if (obj->refcount++ == 0) {
+                err = iommu_enable(obj);
+                if (err)
+                        goto err_enable;
+                flush_iotlb_all(obj);
+        }
+        if (!try_module_get(obj->owner))
+                goto err_module;
+        mutex_unlock(&obj->iommu_lock);
+        dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
+        return obj;
+err_module:
+        if (obj->refcount == 1)
+                iommu_disable(obj);
+err_enable:
+        obj->refcount--;
+        mutex_unlock(&obj->iommu_lock);
+        return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(iommu_get);
+/**
+ * iommu_put - Put back iommu handler
+ * @obj:        target iommu
+ **/
+void iommu_put(struct iommu *obj)
+{
+        if (!obj && IS_ERR(obj))
+                return;
+        mutex_lock(&obj->iommu_lock);
+        if (--obj->refcount == 0)
+                iommu_disable(obj);
+        module_put(obj->owner);
+        mutex_unlock(&obj->iommu_lock);
+        dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
+}
+EXPORT_SYMBOL_GPL(iommu_put);
+/*
+ *      OMAP Device MMU(IOMMU) detection
+ */
+static int __devinit omap_iommu_probe(struct platform_device *pdev)
+{
+        int err = -ENODEV;
+        void *p;
+        int irq;
+        struct iommu *obj;
+        struct resource *res;
+        struct iommu_platform_data *pdata = pdev->dev.platform_data;
+        if (pdev->num_resources != 2)
+                return -EINVAL;
+        obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
+        if (!obj)
+                return -ENOMEM;
+        obj->clk = clk_get(&pdev->dev, pdata->clk_name);
+        if (IS_ERR(obj->clk))
+                goto err_clk;
+        obj->nr_tlb_entries = pdata->nr_tlb_entries;
+        obj->name = pdata->name;
+        obj->dev = &pdev->dev;
+        obj->ctx = (void *)obj + sizeof(*obj);
+        mutex_init(&obj->iommu_lock);
+        mutex_init(&obj->mmap_lock);
+        spin_lock_init(&obj->page_table_lock);
+        INIT_LIST_HEAD(&obj->mmap);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                err = -ENODEV;
+                goto err_mem;
+        }
+        obj->regbase = ioremap(res->start, resource_size(res));
+        if (!obj->regbase) {
+                err = -ENOMEM;
+                goto err_mem;
+        }
+        res = request_mem_region(res->start, resource_size(res),
+                                 dev_name(&pdev->dev));
+        if (!res) {
+                err = -EIO;
+                goto err_mem;
+        }
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0) {
+                err = -ENODEV;
+                goto err_irq;
+        }
+        err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
+                          dev_name(&pdev->dev), obj);
+        if (err < 0)
+                goto err_irq;
+        platform_set_drvdata(pdev, obj);
+        p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE));
+        if (!p) {
+                err = -ENOMEM;
+                goto err_pgd;
+        }
+        memset(p, 0, IOPGD_TABLE_SIZE);
+        clean_dcache_area(p, IOPGD_TABLE_SIZE);
+        obj->iopgd = p;
+        BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE));
+        dev_info(&pdev->dev, "%s registered\n", obj->name);
+        return 0;
+err_pgd:
+        free_irq(irq, obj);
+err_irq:
+        release_mem_region(res->start, resource_size(res));
+        iounmap(obj->regbase);
+err_mem:
+        clk_put(obj->clk);
+err_clk:
+        kfree(obj);
+        return err;
+}
+static int __devexit omap_iommu_remove(struct platform_device *pdev)
+{
+        int irq;
+        struct resource *res;
+        struct iommu *obj = platform_get_drvdata(pdev);
+        platform_set_drvdata(pdev, NULL);
+        iopgtable_clear_entry_all(obj);
+        free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE));
+        irq = platform_get_irq(pdev, 0);
+        free_irq(irq, obj);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(res->start, resource_size(res));
+        iounmap(obj->regbase);
+        clk_put(obj->clk);
+        dev_info(&pdev->dev, "%s removed\n", obj->name);
+        kfree(obj);
+        return 0;
+}
+static struct platform_driver omap_iommu_driver = {
+        .probe  = omap_iommu_probe,
+        .remove = __devexit_p(omap_iommu_remove),
+        .driver = {
+                .name   = "omap-iommu",
+        },
+};
+static void iopte_cachep_ctor(void *iopte)
+{
+        clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
+}
+static int __init omap_iommu_init(void)
+{
+        struct kmem_cache *p;
+        const unsigned long flags = SLAB_HWCACHE_ALIGN;
+        size_t align = 1 << 10; /* L2 pagetable alignement */
+        p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
+                              iopte_cachep_ctor);
+        if (!p)
+                return -ENOMEM;
+        iopte_cachep = p;
+        return platform_driver_register(&omap_iommu_driver);
+}
+module_init(omap_iommu_init);
+static void __exit omap_iommu_exit(void)
+{
+        kmem_cache_destroy(iopte_cachep);
+        platform_driver_unregister(&omap_iommu_driver);
+}
+module_exit(omap_iommu_exit);
+MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
+MODULE_ALIAS("platform:omap-iommu");
+MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
new file mode 100644
index 000000000000..37dac434c7a1
--- /dev/null
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -0,0 +1,72 @@
+/*
+ * omap iommu: pagetable definitions
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PLAT_OMAP_IOMMU_H
+#define __PLAT_OMAP_IOMMU_H
+#define IOPGD_SHIFT             20
+#define IOPGD_SIZE              (1 << IOPGD_SHIFT)
+#define IOPGD_MASK              (~(IOPGD_SIZE - 1))
+#define IOSECTION_MASK          IOPGD_MASK
+#define PTRS_PER_IOPGD          (1 << (32 - IOPGD_SHIFT))
+#define IOPGD_TABLE_SIZE        (PTRS_PER_IOPGD * sizeof(u32))
+#define IOSUPER_SIZE            (IOPGD_SIZE << 4)
+#define IOSUPER_MASK            (~(IOSUPER_SIZE - 1))
+#define IOPTE_SHIFT             12
+#define IOPTE_SIZE              (1 << IOPTE_SHIFT)
+#define IOPTE_MASK              (~(IOPTE_SIZE - 1))
+#define IOPAGE_MASK             IOPTE_MASK
+#define PTRS_PER_IOPTE          (1 << (IOPGD_SHIFT - IOPTE_SHIFT))
+#define IOPTE_TABLE_SIZE        (PTRS_PER_IOPTE * sizeof(u32))
+#define IOLARGE_SIZE            (IOPTE_SIZE << 4)
+#define IOLARGE_MASK            (~(IOLARGE_SIZE - 1))
+#define IOPGD_TABLE             (1 << 0)
+#define IOPGD_SECTION           (2 << 0)
+#define IOPGD_SUPER             (1 << 18 | 2 << 0)
+#define IOPTE_SMALL             (2 << 0)
+#define IOPTE_LARGE             (1 << 0)
+#define iopgd_index(da)         (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
+#define iopgd_offset(obj, da)   ((obj)->iopgd + iopgd_index(da))
+#define iopte_paddr(iopgd)      (*iopgd & ~((1 << 10) - 1))
+#define iopte_vaddr(iopgd)      ((u32 *)phys_to_virt(iopte_paddr(iopgd)))
+#define iopte_index(da)         (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
+#define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da))
+static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
+                                   u32 flags)
+{
+        memset(e, 0, sizeof(*e));
+        e->da           = da;
+        e->pa           = pa;
+        e->valid        = 1;
+        /* FIXME: add OMAP1 support */
+        e->pgsz         = flags & MMU_CAM_PGSZ_MASK;
+        e->endian       = flags & MMU_RAM_ENDIAN_MASK;
+        e->elsz         = flags & MMU_RAM_ELSZ_MASK;
+        e->mixed        = flags & MMU_RAM_MIXED_MASK;
+        return iopgsz_to_bytes(e->pgsz);
+}
+#define to_iommu(dev)                                                   \
+        (struct iommu *)platform_get_drvdata(to_platform_device(dev))
+#endif /* __PLAT_OMAP_IOMMU_H */
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
new file mode 100644
index 000000000000..2fce2c151a95
--- /dev/null
+++ b/arch/arm/plat-omap/iovmm.c
@@ -0,0 +1,896 @@
+/*
+ * omap iommu: simple virtual address space management
+ *
+ * Copyright (C) 2008-2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/vmalloc.h>
+#include <linux/device.h>
+#include <linux/scatterlist.h>
+#include <asm/cacheflush.h>
+#include <asm/mach/map.h>
+#include <mach/iommu.h>
+#include <mach/iovmm.h>
+#include "iopgtable.h"
+/*
+ * A device driver needs to create address mappings between:
+ *
+ * - iommu/device address
+ * - physical address
+ * - mpu virtual address
+ *
+ * There are 4 possible patterns for them:
+ *
+ *    |iova/                      mapping               iommu_          page
+ *    | da      pa      va      (d)-(p)-(v)             function        type
+ *  ---------------------------------------------------------------------------
+ *  1 | c       c       c        1 - 1 - 1        _kmap() / _kunmap()   s
+ *  2 | c       c,a     c        1 - 1 - 1      _kmalloc()/ _kfree()    s
+ *  3 | c       d       c        1 - n - 1        _vmap() / _vunmap()   s
+ *  4 | c       d,a     c        1 - n - 1      _vmalloc()/ _vfree()    n*
+ *
+ *
+ *      'iova': device iommu virtual address
+ *      'da':   alias of 'iova'
+ *      'pa':   physical address
+ *      'va':   mpu virtual address
+ *
+ *      'c':    contiguous memory area
+ *      'd':    dicontiguous memory area
+ *      'a':    anonymous memory allocation
+ *      '()':   optional feature
+ *
+ *      'n':    a normal page(4KB) size is used.
+ *      's':    multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used.
+ *
+ *      '*':    not yet, but feasible.
+ */
+static struct kmem_cache *iovm_area_cachep;
+/* return total bytes of sg buffers */
+static size_t sgtable_len(const struct sg_table *sgt)
+{
+        unsigned int i, total = 0;
+        struct scatterlist *sg;
+        if (!sgt)
+                return 0;
+        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+                size_t bytes;
+                bytes = sg_dma_len(sg);
+                if (!iopgsz_ok(bytes)) {
+                        pr_err("%s: sg[%d] not iommu pagesize(%x)\n",
+                               __func__, i, bytes);
+                        return 0;
+                }
+                total += bytes;
+        }
+        return total;
+}
+#define sgtable_ok(x)   (!!sgtable_len(x))
+/*
+ * calculate the optimal number sg elements from total bytes based on
+ * iommu superpages
+ */
+static unsigned int sgtable_nents(size_t bytes)
+{
+        int i;
+        unsigned int nr_entries;
+        const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
+        if (!IS_ALIGNED(bytes, PAGE_SIZE)) {
+                pr_err("%s: wrong size %08x\n", __func__, bytes);
+                return 0;
+        }
+        nr_entries = 0;
+        for (i = 0; i < ARRAY_SIZE(pagesize); i++) {
+                if (bytes >= pagesize[i]) {
+                        nr_entries += (bytes / pagesize[i]);
+                        bytes %= pagesize[i];
+                }
+        }
+        BUG_ON(bytes);
+        return nr_entries;
+}
+/* allocate and initialize sg_table header(a kind of 'superblock') */
+static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
+{
+        unsigned int nr_entries;
+        int err;
+        struct sg_table *sgt;
+        if (!bytes)
+                return ERR_PTR(-EINVAL);
+        if (!IS_ALIGNED(bytes, PAGE_SIZE))
+                return ERR_PTR(-EINVAL);
+        /* FIXME: IOVMF_DA_FIXED should support 'superpages' */
+        if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) {
+                nr_entries = sgtable_nents(bytes);
+                if (!nr_entries)
+                        return ERR_PTR(-EINVAL);
+        } else
+                nr_entries =  bytes / PAGE_SIZE;
+        sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+        if (!sgt)
+                return ERR_PTR(-ENOMEM);
+        err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL);
+        if (err)
+                return ERR_PTR(err);
+        pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries);
+        return sgt;
+}
+/* free sg_table header(a kind of superblock) */
+static void sgtable_free(struct sg_table *sgt)
+{
+        if (!sgt)
+                return;
+        sg_free_table(sgt);
+        kfree(sgt);
+        pr_debug("%s: sgt:%p\n", __func__, sgt);
+}
+/* map 'sglist' to a contiguous mpu virtual area and return 'va' */
+static void *vmap_sg(const struct sg_table *sgt)
+{
+        u32 va;
+        size_t total;
+        unsigned int i;
+        struct scatterlist *sg;
+        struct vm_struct *new;
+        const struct mem_type *mtype;
+        mtype = get_mem_type(MT_DEVICE);
+        if (!mtype)
+                return ERR_PTR(-EINVAL);
+        total = sgtable_len(sgt);
+        if (!total)
+                return ERR_PTR(-EINVAL);
+        new = __get_vm_area(total, VM_IOREMAP, VMALLOC_START, VMALLOC_END);
+        if (!new)
+                return ERR_PTR(-ENOMEM);
+        va = (u32)new->addr;
+        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+                size_t bytes;
+                u32 pa;
+                int err;
+                pa = sg_phys(sg);
+                bytes = sg_dma_len(sg);
+                BUG_ON(bytes != PAGE_SIZE);
+                err = ioremap_page(va,  pa, mtype);
+                if (err)
+                        goto err_out;
+                va += bytes;
+        }
+        flush_cache_vmap(new->addr, total);
+        return new->addr;
+err_out:
+        WARN_ON(1); /* FIXME: cleanup some mpu mappings */
+        vunmap(new->addr);
+        return ERR_PTR(-EAGAIN);
+}
+static inline void vunmap_sg(const void *va)
+{
+        vunmap(va);
+}
+static struct iovm_struct *__find_iovm_area(struct iommu *obj, const u32 da)
+{
+        struct iovm_struct *tmp;
+        list_for_each_entry(tmp, &obj->mmap, list) {
+                if ((da >= tmp->da_start) && (da < tmp->da_end)) {
+                        size_t len;
+                        len = tmp->da_end - tmp->da_start;
+                        dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n",
+                                __func__, tmp->da_start, da, tmp->da_end, len,
+                                tmp->flags);
+                        return tmp;
+                }
+        }
+        return NULL;
+}
+/**
+ * find_iovm_area  -  find iovma which includes @da
+ * @da:         iommu device virtual address
+ *
+ * Find the existing iovma starting at @da
+ */
+struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da)
+{
+        struct iovm_struct *area;
+        mutex_lock(&obj->mmap_lock);
+        area = __find_iovm_area(obj, da);
+        mutex_unlock(&obj->mmap_lock);
+        return area;
+}
+EXPORT_SYMBOL_GPL(find_iovm_area);
+/*
+ * This finds the hole(area) which fits the requested address and len
+ * in iovmas mmap, and returns the new allocated iovma.
+ */
+static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
+                                           size_t bytes, u32 flags)
+{
+        struct iovm_struct *new, *tmp;
+        u32 start, prev_end, alignement;
+        if (!obj || !bytes)
+                return ERR_PTR(-EINVAL);
+        start = da;
+        alignement = PAGE_SIZE;
+        if (flags & IOVMF_DA_ANON) {
+                /*
+                 * Reserve the first page for NULL
+                 */
+                start = PAGE_SIZE;
+                if (flags & IOVMF_LINEAR)
+                        alignement = iopgsz_max(bytes);
+                start = roundup(start, alignement);
+        }
+        tmp = NULL;
+        if (list_empty(&obj->mmap))
+                goto found;
+        prev_end = 0;
+        list_for_each_entry(tmp, &obj->mmap, list) {
+                if ((prev_end <= start) && (start + bytes < tmp->da_start))
+                        goto found;
+                if (flags & IOVMF_DA_ANON)
+                        start = roundup(tmp->da_end, alignement);
+                prev_end = tmp->da_end;
+        }
+        if ((start >= prev_end) && (ULONG_MAX - start >= bytes))
+                goto found;
+        dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
+                __func__, da, bytes, flags);
+        return ERR_PTR(-EINVAL);
+found:
+        new = kmem_cache_zalloc(iovm_area_cachep, GFP_KERNEL);
+        if (!new)
+                return ERR_PTR(-ENOMEM);
+        new->iommu = obj;
+        new->da_start = start;
+        new->da_end = start + bytes;
+        new->flags = flags;
+        /*
+         * keep ascending order of iovmas
+         */
+        if (tmp)
+                list_add_tail(&new->list, &tmp->list);
+        else
+                list_add(&new->list, &obj->mmap);
+        dev_dbg(obj->dev, "%s: found %08x-%08x-%08x(%x) %08x\n",
+                __func__, new->da_start, start, new->da_end, bytes, flags);
+        return new;
+}
+static void free_iovm_area(struct iommu *obj, struct iovm_struct *area)
+{
+        size_t bytes;
+        BUG_ON(!obj || !area);
+        bytes = area->da_end - area->da_start;
+        dev_dbg(obj->dev, "%s: %08x-%08x(%x) %08x\n",
+                __func__, area->da_start, area->da_end, bytes, area->flags);
+        list_del(&area->list);
+        kmem_cache_free(iovm_area_cachep, area);
+}
+/**
+ * da_to_va - convert (d) to (v)
+ * @obj:        objective iommu
+ * @da:         iommu device virtual address
+ * @va:         mpu virtual address
+ *
+ * Returns mpu virtual addr which corresponds to a given device virtual addr
+ */
+void *da_to_va(struct iommu *obj, u32 da)
+{
+        void *va = NULL;
+        struct iovm_struct *area;
+        mutex_lock(&obj->mmap_lock);
+        area = __find_iovm_area(obj, da);
+        if (!area) {
+                dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da);
+                goto out;
+        }
+        va = area->va;
+        mutex_unlock(&obj->mmap_lock);
+out:
+        return va;
+}
+EXPORT_SYMBOL_GPL(da_to_va);
+static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va)
+{
+        unsigned int i;
+        struct scatterlist *sg;
+        void *va = _va;
+        void *va_end;
+        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+                struct page *pg;
+                const size_t bytes = PAGE_SIZE;
+                /*
+                 * iommu 'superpage' isn't supported with 'iommu_vmalloc()'
+                 */
+                pg = vmalloc_to_page(va);
+                BUG_ON(!pg);
+                sg_set_page(sg, pg, bytes, 0);
+                va += bytes;
+        }
+        va_end = _va + PAGE_SIZE * i;
+        flush_cache_vmap(_va, va_end);
+}
+static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
+{
+        /*
+         * Actually this is not necessary at all, just exists for
+         * consistency of the code readibility.
+         */
+        BUG_ON(!sgt);
+}
+static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
+{
+        unsigned int i;
+        struct scatterlist *sg;
+        void *va;
+        va = phys_to_virt(pa);
+        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+                size_t bytes;
+                bytes = iopgsz_max(len);
+                BUG_ON(!iopgsz_ok(bytes));
+                sg_set_buf(sg, phys_to_virt(pa), bytes);
+                /*
+                 * 'pa' is cotinuous(linear).
+                 */
+                pa += bytes;
+                len -= bytes;
+        }
+        BUG_ON(len);
+        clean_dcache_area(va, len);
+}
+static inline void sgtable_drain_kmalloc(struct sg_table *sgt)
+{
+        /*
+         * Actually this is not necessary at all, just exists for
+         * consistency of the code readibility
+         */
+        BUG_ON(!sgt);
+}
+/* create 'da' <-> 'pa' mapping from 'sgt' */
+static int map_iovm_area(struct iommu *obj, struct iovm_struct *new,
+                         const struct sg_table *sgt, u32 flags)
+{
+        int err;
+        unsigned int i, j;
+        struct scatterlist *sg;
+        u32 da = new->da_start;
+        if (!obj || !new || !sgt)
+                return -EINVAL;
+        BUG_ON(!sgtable_ok(sgt));
+        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
+                u32 pa;
+                int pgsz;
+                size_t bytes;
+                struct iotlb_entry e;
+                pa = sg_phys(sg);
+                bytes = sg_dma_len(sg);
+                flags &= ~IOVMF_PGSZ_MASK;
+                pgsz = bytes_to_iopgsz(bytes);
+                if (pgsz < 0)
+                        goto err_out;
+                flags |= pgsz;
+                pr_debug("%s: [%d] %08x %08x(%x)\n", __func__,
+                         i, da, pa, bytes);
+                iotlb_init_entry(&e, da, pa, flags);
+                err = iopgtable_store_entry(obj, &e);
+                if (err)
+                        goto err_out;
+                da += bytes;
+        }
+        return 0;
+err_out:
+        da = new->da_start;
+        for_each_sg(sgt->sgl, sg, i, j) {
+                size_t bytes;
+                bytes = iopgtable_clear_entry(obj, da);
+                BUG_ON(!iopgsz_ok(bytes));
+                da += bytes;
+        }
+        return err;
+}
+/* release 'da' <-> 'pa' mapping */
+static void unmap_iovm_area(struct iommu *obj, struct iovm_struct *area)
+{
+        u32 start;
+        size_t total = area->da_end - area->da_start;
+        BUG_ON((!total) || !IS_ALIGNED(total, PAGE_SIZE));
+        start = area->da_start;
+        while (total > 0) {
+                size_t bytes;
+                bytes = iopgtable_clear_entry(obj, start);
+                if (bytes == 0)
+                        bytes = PAGE_SIZE;
+                else
+                        dev_dbg(obj->dev, "%s: unmap %08x(%x) %08x\n",
+                                __func__, start, bytes, area->flags);
+                BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE));
+                total -= bytes;
+                start += bytes;
+        }
+        BUG_ON(total);
+}
+/* template function for all unmapping */
+static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da,
+                                      void (*fn)(const void *), u32 flags)
+{
+        struct sg_table *sgt = NULL;
+        struct iovm_struct *area;
+        if (!IS_ALIGNED(da, PAGE_SIZE)) {
+                dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da);
+                return NULL;
+        }
+        mutex_lock(&obj->mmap_lock);
+        area = __find_iovm_area(obj, da);
+        if (!area) {
+                dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da);
+                goto out;
+        }
+        if ((area->flags & flags) != flags) {
+                dev_err(obj->dev, "%s: wrong flags(%08x)\n", __func__,
+                        area->flags);
+                goto out;
+        }
+        sgt = (struct sg_table *)area->sgt;
+        unmap_iovm_area(obj, area);
+        fn(area->va);
+        dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", __func__,
+                area->da_start, da, area->da_end,
+                area->da_end - area->da_start, area->flags);
+        free_iovm_area(obj, area);
+out:
+        mutex_unlock(&obj->mmap_lock);
+        return sgt;
+}
+static u32 map_iommu_region(struct iommu *obj, u32 da,
+              const struct sg_table *sgt, void *va, size_t bytes, u32 flags)
+{
+        int err = -ENOMEM;
+        struct iovm_struct *new;
+        mutex_lock(&obj->mmap_lock);
+        new = alloc_iovm_area(obj, da, bytes, flags);
+        if (IS_ERR(new)) {
+                err = PTR_ERR(new);
+                goto err_alloc_iovma;
+        }
+        new->va = va;
+        new->sgt = sgt;
+        if (map_iovm_area(obj, new, sgt, new->flags))
+                goto err_map;
+        mutex_unlock(&obj->mmap_lock);
+        dev_dbg(obj->dev, "%s: da:%08x(%x) flags:%08x va:%p\n",
+                __func__, new->da_start, bytes, new->flags, va);
+        return new->da_start;
+err_map:
+        free_iovm_area(obj, new);
+err_alloc_iovma:
+        mutex_unlock(&obj->mmap_lock);
+        return err;
+}
+static inline u32 __iommu_vmap(struct iommu *obj, u32 da,
+                 const struct sg_table *sgt, void *va, size_t bytes, u32 flags)
+{
+        return map_iommu_region(obj, da, sgt, va, bytes, flags);
+}
+/**
+ * iommu_vmap  -  (d)-(p)-(v) address mapper
+ * @obj:        objective iommu
+ * @sgt:        address of scatter gather table
+ * @flags:      iovma and page property
+ *
+ * Creates 1-n-1 mapping with given @sgt and returns @da.
+ * All @sgt element must be io page size aligned.
+ */
+u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
+                 u32 flags)
+{
+        size_t bytes;
+        void *va;
+        if (!obj || !obj->dev || !sgt)
+                return -EINVAL;
+        bytes = sgtable_len(sgt);
+        if (!bytes)
+                return -EINVAL;
+        bytes = PAGE_ALIGN(bytes);
+        va = vmap_sg(sgt);
+        if (IS_ERR(va))
+                return PTR_ERR(va);
+        flags &= IOVMF_HW_MASK;
+        flags |= IOVMF_DISCONT;
+        flags |= IOVMF_MMIO;
+        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+        da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
+        if (IS_ERR_VALUE(da))
+                vunmap_sg(va);
+        return da;
+}
+EXPORT_SYMBOL_GPL(iommu_vmap);
+/**
+ * iommu_vunmap  -  release virtual mapping obtained by 'iommu_vmap()'
+ * @obj:        objective iommu
+ * @da:         iommu device virtual address
+ *
+ * Free the iommu virtually contiguous memory area starting at
+ * @da, which was returned by 'iommu_vmap()'.
+ */
+struct sg_table *iommu_vunmap(struct iommu *obj, u32 da)
+{
+        struct sg_table *sgt;
+        /*
+         * 'sgt' is allocated before 'iommu_vmalloc()' is called.
+         * Just returns 'sgt' to the caller to free
+         */
+        sgt = unmap_vm_area(obj, da, vunmap_sg, IOVMF_DISCONT | IOVMF_MMIO);
+        if (!sgt)
+                dev_dbg(obj->dev, "%s: No sgt\n", __func__);
+        return sgt;
+}
+EXPORT_SYMBOL_GPL(iommu_vunmap);
+/**
+ * iommu_vmalloc  -  (d)-(p)-(v) address allocator and mapper
+ * @obj:        objective iommu
+ * @da:         contiguous iommu virtual memory
+ * @bytes:      allocation size
+ * @flags:      iovma and page property
+ *
+ * Allocate @bytes linearly and creates 1-n-1 mapping and returns
+ * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
+ */
+u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
+{
+        void *va;
+        struct sg_table *sgt;
+        if (!obj || !obj->dev || !bytes)
+                return -EINVAL;
+        bytes = PAGE_ALIGN(bytes);
+        va = vmalloc(bytes);
+        if (!va)
+                return -ENOMEM;
+        sgt = sgtable_alloc(bytes, flags);
+        if (IS_ERR(sgt)) {
+                da = PTR_ERR(sgt);
+                goto err_sgt_alloc;
+        }
+        sgtable_fill_vmalloc(sgt, va);
+        flags &= IOVMF_HW_MASK;
+        flags |= IOVMF_DISCONT;
+        flags |= IOVMF_ALLOC;
+        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+        da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
+        if (IS_ERR_VALUE(da))
+                goto err_iommu_vmap;
+        return da;
+err_iommu_vmap:
+        sgtable_drain_vmalloc(sgt);
+        sgtable_free(sgt);
+err_sgt_alloc:
+        vfree(va);
+        return da;
+}
+EXPORT_SYMBOL_GPL(iommu_vmalloc);
+/**
+ * iommu_vfree  -  release memory allocated by 'iommu_vmalloc()'
+ * @obj:        objective iommu
+ * @da:         iommu device virtual address
+ *
+ * Frees the iommu virtually continuous memory area starting at
+ * @da, as obtained from 'iommu_vmalloc()'.
+ */
+void iommu_vfree(struct iommu *obj, const u32 da)
+{
+        struct sg_table *sgt;
+        sgt = unmap_vm_area(obj, da, vfree, IOVMF_DISCONT | IOVMF_ALLOC);
+        if (!sgt)
+                dev_dbg(obj->dev, "%s: No sgt\n", __func__);
+        sgtable_free(sgt);
+}
+EXPORT_SYMBOL_GPL(iommu_vfree);
+static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
+                          size_t bytes, u32 flags)
+{
+        struct sg_table *sgt;
+        sgt = sgtable_alloc(bytes, flags);
+        if (IS_ERR(sgt))
+                return PTR_ERR(sgt);
+        sgtable_fill_kmalloc(sgt, pa, bytes);
+        da = map_iommu_region(obj, da, sgt, va, bytes, flags);
+        if (IS_ERR_VALUE(da)) {
+                sgtable_drain_kmalloc(sgt);
+                sgtable_free(sgt);
+        }
+        return da;
+}
+/**
+ * iommu_kmap  -  (d)-(p)-(v) address mapper
+ * @obj:        objective iommu
+ * @da:         contiguous iommu virtual memory
+ * @pa:         contiguous physical memory
+ * @flags:      iovma and page property
+ *
+ * Creates 1-1-1 mapping and returns @da again, which can be
+ * adjusted if 'IOVMF_DA_ANON' is set.
+ */
+u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
+                 u32 flags)
+{
+        void *va;
+        if (!obj || !obj->dev || !bytes)
+                return -EINVAL;
+        bytes = PAGE_ALIGN(bytes);
+        va = ioremap(pa, bytes);
+        if (!va)
+                return -ENOMEM;
+        flags &= IOVMF_HW_MASK;
+        flags |= IOVMF_LINEAR;
+        flags |= IOVMF_MMIO;
+        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+        da = __iommu_kmap(obj, da, pa, va, bytes, flags);
+        if (IS_ERR_VALUE(da))
+                iounmap(va);
+        return da;
+}
+EXPORT_SYMBOL_GPL(iommu_kmap);
+/**
+ * iommu_kunmap  -  release virtual mapping obtained by 'iommu_kmap()'
+ * @obj:        objective iommu
+ * @da:         iommu device virtual address
+ *
+ * Frees the iommu virtually contiguous memory area starting at
+ * @da, which was passed to and was returned by'iommu_kmap()'.
+ */
+void iommu_kunmap(struct iommu *obj, u32 da)
+{
+        struct sg_table *sgt;
+        typedef void (*func_t)(const void *);
+        sgt = unmap_vm_area(obj, da, (func_t)__iounmap,
+                            IOVMF_LINEAR | IOVMF_MMIO);
+        if (!sgt)
+                dev_dbg(obj->dev, "%s: No sgt\n", __func__);
+        sgtable_free(sgt);
+}
+EXPORT_SYMBOL_GPL(iommu_kunmap);
+/**
+ * iommu_kmalloc  -  (d)-(p)-(v) address allocator and mapper
+ * @obj:        objective iommu
+ * @da:         contiguous iommu virtual memory
+ * @bytes:      bytes for allocation
+ * @flags:      iovma and page property
+ *
+ * Allocate @bytes linearly and creates 1-1-1 mapping and returns
+ * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
+ */
+u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
+{
+        void *va;
+        u32 pa;
+        if (!obj || !obj->dev || !bytes)
+                return -EINVAL;
+        bytes = PAGE_ALIGN(bytes);
+        va = kmalloc(bytes, GFP_KERNEL | GFP_DMA);
+        if (!va)
+                return -ENOMEM;
+        pa = virt_to_phys(va);
+        flags &= IOVMF_HW_MASK;
+        flags |= IOVMF_LINEAR;
+        flags |= IOVMF_ALLOC;
+        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+        da = __iommu_kmap(obj, da, pa, va, bytes, flags);
+        if (IS_ERR_VALUE(da))
+                kfree(va);
+        return da;
+}
+EXPORT_SYMBOL_GPL(iommu_kmalloc);
+/**
+ * iommu_kfree  -  release virtual mapping obtained by 'iommu_kmalloc()'
+ * @obj:        objective iommu
+ * @da:         iommu device virtual address
+ *
+ * Frees the iommu virtually contiguous memory area starting at
+ * @da, which was passed to and was returned by'iommu_kmalloc()'.
+ */
+void iommu_kfree(struct iommu *obj, u32 da)
+{
+        struct sg_table *sgt;
+        sgt = unmap_vm_area(obj, da, kfree, IOVMF_LINEAR | IOVMF_ALLOC);
+        if (!sgt)
+                dev_dbg(obj->dev, "%s: No sgt\n", __func__);
+        sgtable_free(sgt);
+}
+EXPORT_SYMBOL_GPL(iommu_kfree);
+static int __init iovmm_init(void)
+{
+        const unsigned long flags = SLAB_HWCACHE_ALIGN;
+        struct kmem_cache *p;
+        p = kmem_cache_create("iovm_area_cache", sizeof(struct iovm_struct), 0,
+                              flags, NULL);
+        if (!p)
+                return -ENOMEM;
+        iovm_area_cachep = p;
+        return 0;
+}
+module_init(iovmm_init);
+static void __exit iovmm_exit(void)
+{
+        kmem_cache_destroy(iovm_area_cachep);
+}
+module_exit(iovmm_exit);
+MODULE_DESCRIPTION("omap iommu: simple virtual address space management");
+MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 28b0a824b8cf..efa0e0111f38 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -91,11 +91,20 @@ static void omap_mcbsp_dump_reg(u8 id)
 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 {
        struct omap_mcbsp *mcbsp_tx = dev_id;
+        u16 irqst_spcr2;
-        dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
+        irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
-                OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
+        dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
-        complete(&mcbsp_tx->tx_irq_completion);
+        if (irqst_spcr2 & XSYNC_ERR) {
+                dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
+                        irqst_spcr2);
+                /* Writing zero to XSYNC_ERR clears the IRQ */
+                OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
+                        irqst_spcr2 & ~(XSYNC_ERR));
+        } else {
+                complete(&mcbsp_tx->tx_irq_completion);
+        }
        return IRQ_HANDLED;
 }
@@ -103,11 +112,20 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 {
        struct omap_mcbsp *mcbsp_rx = dev_id;
+        u16 irqst_spcr1;
-        dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
+        irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
-                OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
+        dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
-        complete(&mcbsp_rx->rx_irq_completion);
+        if (irqst_spcr1 & RSYNC_ERR) {
+                dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
+                        irqst_spcr1);
+                /* Writing zero to RSYNC_ERR clears the IRQ */
+                OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
+                        irqst_spcr1 & ~(RSYNC_ERR));
+        } else {
+                complete(&mcbsp_rx->tx_irq_completion);
+        }
        return IRQ_HANDLED;
 }
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 80b040fd5ca7..8d329fb20740 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -54,6 +54,9 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
 {
        struct pin_config *reg;
+        if (cpu_is_omap44xx())
+                return 0;
        if (mux_cfg == NULL) {
                printk(KERN_ERR "Pin mux table not initialized\n");
                return -ENODEV;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index fa5297d643d3..a5b9bcd6b108 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,6 +6,9 @@
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -38,12 +41,14 @@
 #define OMAP1_SRAM_VA           VMALLOC_END
 #define OMAP2_SRAM_PA           0x40200000
 #define OMAP2_SRAM_PUB_PA       0x4020f800
-#define OMAP2_SRAM_VA           VMALLOC_END
+#define OMAP2_SRAM_VA           0xe3000000
-#define OMAP2_SRAM_PUB_VA       (VMALLOC_END + 0x800)
+#define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
 #define OMAP3_SRAM_PA           0x40200000
 #define OMAP3_SRAM_VA           0xd7000000
 #define OMAP3_SRAM_PUB_PA       0x40208000
 #define OMAP3_SRAM_PUB_VA       0xd7008000
+#define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
+#define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -87,6 +92,10 @@ static int is_sram_locked(void)
 {
        int type = 0;
+        if (cpu_is_omap44xx())
+                /* Not yet supported */
+                return 0;
        if (cpu_is_omap242x())
                type = omap_rev() & OMAP2_DEVICETYPE_MASK;
@@ -135,6 +144,10 @@ void __init omap_detect_sram(void)
                                omap_sram_base = OMAP3_SRAM_VA;
                                omap_sram_start = OMAP3_SRAM_PA;
                                omap_sram_size = 0x10000; /* 64K */
+                        } else if (cpu_is_omap44xx()) {
+                                omap_sram_base = OMAP4_SRAM_VA;
+                                omap_sram_start = OMAP4_SRAM_PA;
+                                omap_sram_size = 0x8000; /* 32K */
                        } else {
                                omap_sram_base = OMAP2_SRAM_VA;
                                omap_sram_start = OMAP2_SRAM_PA;
@@ -201,8 +214,23 @@ void __init omap_map_sram(void)
                base = OMAP3_SRAM_PA;
                base = ROUND_DOWN(base, PAGE_SIZE);
                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+                /*
+                 * SRAM must be marked as non-cached on OMAP3 since the
+                 * CORE DPLL M2 divider change code (in SRAM) runs with the
+                 * SDRAM controller disabled, and if it is marked cached,
+                 * the ARM may attempt to write cache lines back to SDRAM
+                 * which will cause the system to hang.
+                 */
+                omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
        }
+        if (cpu_is_omap44xx()) {
+                omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
+                base = OMAP4_SRAM_PA;
+                base = ROUND_DOWN(base, PAGE_SIZE);
+                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+        }
        omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
        iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
@@ -242,20 +270,13 @@ void * omap_sram_push(void * start, unsigned long size)
        return (void *)omap_sram_ceil;
 }
-static void omap_sram_error(void)
-{
-        panic("Uninitialized SRAM function\n");
-}
 #ifdef CONFIG_ARCH_OMAP1
 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 {
-        if (!_omap_sram_reprogram_clock)
+        BUG_ON(!_omap_sram_reprogram_clock);
-                omap_sram_error();
        _omap_sram_reprogram_clock(dpllctl, ckctl);
 }
@@ -280,9 +301,7 @@ static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
                   u32 base_cs, u32 force_unlock)
 {
-        if (!_omap2_sram_ddr_init)
+        BUG_ON(!_omap2_sram_ddr_init);
-                omap_sram_error();
        _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
                             base_cs, force_unlock);
 }
@@ -292,9 +311,7 @@ static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 {
-        if (!_omap2_sram_reprogram_sdrc)
+        BUG_ON(!_omap2_sram_reprogram_sdrc);
-                omap_sram_error();
        _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 }
@@ -302,9 +319,7 @@ static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 {
-        if (!_omap2_set_prcm)
+        BUG_ON(!_omap2_set_prcm);
-                omap_sram_error();
        return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 }
 #endif
@@ -356,16 +371,15 @@ static inline int omap243x_sram_init(void)
 static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
                                              u32 sdrc_actim_ctrla,
                                              u32 sdrc_actim_ctrlb,
-                                              u32 m2);
+                                              u32 m2, u32 unlock_dll);
 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-                              u32 sdrc_actim_ctrlb, u32 m2)
+                              u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
 {
-        if (!_omap3_sram_configure_core_dpll)
+        BUG_ON(!_omap3_sram_configure_core_dpll);
-                omap_sram_error();
        return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
                                               sdrc_actim_ctrla,
-                                               sdrc_actim_ctrlb, m2);
+                                               sdrc_actim_ctrlb, m2,
+                                               unlock_dll);
 }
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
@@ -406,6 +420,8 @@ int __init omap_sram_init(void)
                omap243x_sram_init();
        else if (cpu_is_omap34xx())
                omap34xx_sram_init();
+        else if (cpu_is_omap44xx())
+                omap34xx_sram_init(); /* FIXME: */
        return 0;
 }
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 32eb9e33bebb..e814803d4741 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -15,10 +15,9 @@
 #include <linux/spinlock.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
-#include <asm/gpio.h>
+#include <linux/gpio.h>
 static DEFINE_SPINLOCK(gpio_lock);
-static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
 static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
 static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
@@ -46,82 +45,54 @@ static void __set_level(unsigned pin, int high)
        writel(u, GPIO_OUT(pin));
 }
+static inline void __set_blinking(unsigned pin, int blink)
-/*
- * GENERIC_GPIO primitives.
- */
-int gpio_direction_input(unsigned pin)
 {
-        unsigned long flags;
+        u32 u;
-        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_input)) {
-                pr_debug("%s: invalid GPIO %d\n", __func__, pin);
-                return -EINVAL;
-        }
-        spin_lock_irqsave(&gpio_lock, flags);
-        /*
-         * Some callers might not have used gpio_request(),
-         * so flag this pin as requested now.
-         */
-        if (gpio_label[pin] == NULL)
-                gpio_label[pin] = "?";
-        /*
+        u = readl(GPIO_BLINK_EN(pin));
-         * Configure GPIO direction.
+        if (blink)
-         */
+                u |= 1 << (pin & 31);
-        __set_direction(pin, 1);
+        else
+                u &= ~(1 << (pin & 31));
+        writel(u, GPIO_BLINK_EN(pin));
+}
-        spin_unlock_irqrestore(&gpio_lock, flags);
+static inline int orion_gpio_is_valid(unsigned pin, int mode)
+{
+        if (pin < GPIO_MAX) {
+                if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input))
+                        goto err_out;
+                if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output))
+                        goto err_out;
+                return true;
+        }
-        return 0;
+err_out:
+        pr_debug("%s: invalid GPIO %d\n", __func__, pin);
+        return false;
 }
-EXPORT_SYMBOL(gpio_direction_input);
-int gpio_direction_output(unsigned pin, int value)
+/*
+ * GENERIC_GPIO primitives.
+ */
+static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 {
        unsigned long flags;
-        u32 u;
-        if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_output)) {
+        if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK))
-                pr_debug("%s: invalid GPIO %d\n", __func__, pin);
                return -EINVAL;
-        }
        spin_lock_irqsave(&gpio_lock, flags);
-        /*
+        /* Configure GPIO direction. */
-         * Some callers might not have used gpio_request(),
+        __set_direction(pin, 1);
-         * so flag this pin as requested now.
-         */
-        if (gpio_label[pin] == NULL)
-                gpio_label[pin] = "?";
-        /*
-         * Disable blinking.
-         */
-        u = readl(GPIO_BLINK_EN(pin));
-        u &= ~(1 << (pin & 31));
-        writel(u, GPIO_BLINK_EN(pin));
-        /*
-         * Configure GPIO output value.
-         */
-        __set_level(pin, value);
-        /*
-         * Configure GPIO direction.
-         */
-        __set_direction(pin, 0);
        spin_unlock_irqrestore(&gpio_lock, flags);
        return 0;
 }
-EXPORT_SYMBOL(gpio_direction_output);
-int gpio_get_value(unsigned pin)
+static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin)
 {
        int val;
@@ -132,83 +103,75 @@ int gpio_get_value(unsigned pin)
        return (val >> (pin & 31)) & 1;
 }
-EXPORT_SYMBOL(gpio_get_value);
-void gpio_set_value(unsigned pin, int value)
+static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
+        int value)
 {
        unsigned long flags;
-        u32 u;
+        if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
+                return -EINVAL;
        spin_lock_irqsave(&gpio_lock, flags);
-        /*
+        /* Disable blinking. */
-         * Disable blinking.
+        __set_blinking(pin, 0);
-         */
-        u = readl(GPIO_BLINK_EN(pin));
-        u &= ~(1 << (pin & 31));
-        writel(u, GPIO_BLINK_EN(pin));
-        /*
+        /* Configure GPIO output value. */
-         * Configure GPIO output value.
-         */
        __set_level(pin, value);
+        /* Configure GPIO direction. */
+        __set_direction(pin, 0);
        spin_unlock_irqrestore(&gpio_lock, flags);
+        return 0;
 }
-EXPORT_SYMBOL(gpio_set_value);
-int gpio_request(unsigned pin, const char *label)
+static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin,
+        int value)
 {
        unsigned long flags;
-        int ret;
-        if (pin >= GPIO_MAX ||
-            !(test_bit(pin, gpio_valid_input) ||
-              test_bit(pin, gpio_valid_output))) {
-                pr_debug("%s: invalid GPIO %d\n", __func__, pin);
-                return -EINVAL;
-        }
        spin_lock_irqsave(&gpio_lock, flags);
-        if (gpio_label[pin] == NULL) {
-                gpio_label[pin] = label ? label : "?";
-                ret = 0;
-        } else {
-                pr_debug("%s: GPIO %d already used as %s\n",
-                         __func__, pin, gpio_label[pin]);
-                ret = -EBUSY;
-        }
-        spin_unlock_irqrestore(&gpio_lock, flags);
-        return ret;
+        /* Configure GPIO output value. */
+        __set_level(pin, value);
+        spin_unlock_irqrestore(&gpio_lock, flags);
 }
-EXPORT_SYMBOL(gpio_request);
-void gpio_free(unsigned pin)
+static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
 {
-        if (pin >= GPIO_MAX ||
+        if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) ||
-            !(test_bit(pin, gpio_valid_input) ||
+            orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
-              test_bit(pin, gpio_valid_output))) {
+                return 0;
-                pr_debug("%s: invalid GPIO %d\n", __func__, pin);
+        return -EINVAL;
-                return;
-        }
-        if (gpio_label[pin] == NULL)
-                pr_warning("%s: GPIO %d already freed\n", __func__, pin);
-        else
-                gpio_label[pin] = NULL;
 }
-EXPORT_SYMBOL(gpio_free);
+static struct gpio_chip orion_gpiochip = {
+        .label                  = "orion_gpio",
+        .direction_input        = orion_gpio_direction_input,
+        .get                    = orion_gpio_get_value,
+        .direction_output       = orion_gpio_direction_output,
+        .set                    = orion_gpio_set_value,
+        .request                = orion_gpio_request,
+        .base                   = 0,
+        .ngpio                  = GPIO_MAX,
+        .can_sleep              = 0,
+};
+void __init orion_gpio_init(void)
+{
+        gpiochip_add(&orion_gpiochip);
+}
 /*
 * Orion-specific GPIO API extensions.
 */
 void __init orion_gpio_set_unused(unsigned pin)
 {
-        /*
+        /* Configure as output, drive low. */
-         * Configure as output, drive low.
-         */
        __set_level(pin, 0);
        __set_direction(pin, 0);
 }
@@ -230,21 +193,14 @@ void __init orion_gpio_set_valid(unsigned pin, int mode)
 void orion_gpio_set_blink(unsigned pin, int blink)
 {
        unsigned long flags;
-        u32 u;
        spin_lock_irqsave(&gpio_lock, flags);
-        /*
+        /* Set output value to zero. */
-         * Set output value to zero.
-         */
        __set_level(pin, 0);
-        u = readl(GPIO_BLINK_EN(pin));
+        /* Set blinking. */
-        if (blink)
+        __set_blinking(pin, blink);
-                u |= 1 << (pin & 31);
-        else
-                u &= ~(1 << (pin & 31));
-        writel(u, GPIO_BLINK_EN(pin));
        spin_unlock_irqrestore(&gpio_lock, flags);
 }
@@ -368,7 +324,7 @@ static int gpio_irq_set_type(u32 irq, u32 type)
 }
 struct irq_chip orion_gpio_irq_chip = {
-        .name           = "orion_gpio",
+        .name           = "orion_gpio_irq",
        .ack            = gpio_irq_ack,
        .mask           = gpio_irq_mask,
        .unmask         = gpio_irq_unmask,
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 33f6c6aec185..9646a94ed3d0 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -14,12 +14,9 @@
 /*
 * GENERIC_GPIO primitives.
 */
-int gpio_request(unsigned pin, const char *label);
+#define gpio_get_value  __gpio_get_value
-void gpio_free(unsigned pin);
+#define gpio_set_value  __gpio_set_value
-int gpio_direction_input(unsigned pin);
+#define gpio_cansleep   __gpio_cansleep
-int gpio_direction_output(unsigned pin, int value);
-int gpio_get_value(unsigned pin);
-void gpio_set_value(unsigned pin, int value);
 /*
 * Orion-specific GPIO API extensions.
@@ -27,11 +24,13 @@ void gpio_set_value(unsigned pin, int value);
 void orion_gpio_set_unused(unsigned pin);
 void orion_gpio_set_blink(unsigned pin, int blink);
-#define GPIO_BIDI_OK            (1 << 0)
+#define GPIO_INPUT_OK           (1 << 0)
-#define GPIO_INPUT_OK           (1 << 1)
+#define GPIO_OUTPUT_OK          (1 << 1)
-#define GPIO_OUTPUT_OK          (1 << 2)
 void orion_gpio_set_valid(unsigned pin, int mode);
+/* Initialize gpiolib. */
+void __init orion_gpio_init(void);
 /*
 * GPIO interrupt handling.
 */
diff --git a/arch/arm/plat-orion/include/plat/orion5x_wdt.h b/arch/arm/plat-orion/include/plat/orion_wdt.h
index 3c9cf6a305ef..665c362a2fba 100644
--- a/arch/arm/plat-orion/include/plat/orion5x_wdt.h
+++ b/arch/arm/plat-orion/include/plat/orion_wdt.h
@@ -1,15 +1,15 @@
 /*
- * arch/arm/plat-orion/include/plat/orion5x_wdt.h
+ * arch/arm/plat-orion/include/plat/orion_wdt.h
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#ifndef __PLAT_ORION5X_WDT_H
+#ifndef __PLAT_ORION_WDT_H
-#define __PLAT_ORION5X_WDT_H
+#define __PLAT_ORION_WDT_H
-struct orion5x_wdt_platform_data {
+struct orion_wdt_platform_data {
        u32     tclk;           /* no <linux/clk.h> support yet */
 };
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index de8a001fc3a9..715a30177f28 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -12,11 +12,15 @@
 */
 #include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/cnt32_to_63.h>
+#include <linux/timer.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
 #include <mach/bridge-regs.h>
+#include <mach/hardware.h>
 /*
 * Number of timer ticks per jiffy.
@@ -39,6 +43,56 @@ static u32 ticks_per_jiffy;
 /*
+ * Orion's sched_clock implementation. It has a resolution of
+ * at least 7.5ns (133MHz TCLK) and a maximum value of 834 days.
+ *
+ * Because the hardware timer period is quite short (21 secs if
+ * 200MHz TCLK) and because cnt32_to_63() needs to be called at
+ * least once per half period to work properly, a kernel timer is
+ * set up to ensure this requirement is always met.
+ */
+#define TCLK2NS_SCALE_FACTOR 8
+static unsigned long tclk2ns_scale;
+unsigned long long sched_clock(void)
+{
+        unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL));
+        return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR;
+}
+static struct timer_list cnt32_to_63_keepwarm_timer;
+static void cnt32_to_63_keepwarm(unsigned long data)
+{
+        mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
+        (void) sched_clock();
+}
+static void __init setup_sched_clock(unsigned long tclk)
+{
+        unsigned long long v;
+        unsigned long data;
+        v = NSEC_PER_SEC;
+        v <<= TCLK2NS_SCALE_FACTOR;
+        v += tclk/2;
+        do_div(v, tclk);
+        /*
+         * We want an even value to automatically clear the top bit
+         * returned by cnt32_to_63() without an additional run time
+         * instruction. So if the LSB is 1 then round it up.
+         */
+        if (v & 1)
+                v++;
+        tclk2ns_scale = v;
+        data = (0xffffffffUL / tclk / 2 - 2) * HZ;
+        setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data);
+        mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
+}
+/*
 * Clocksource handling.
 */
 static cycle_t orion_clksrc_read(struct clocksource *cs)
@@ -176,6 +230,10 @@ void __init orion_time_init(unsigned int irq, unsigned int tclk)
        ticks_per_jiffy = (tclk + HZ/2) / HZ;
+        /*
+         * Set scale and timer for sched_clock
+         */
+        setup_sched_clock(tclk);
        /*
         * Setup free-running clocksource timer (interrupts
@@ -190,7 +248,6 @@ void __init orion_time_init(unsigned int irq, unsigned int tclk)
        orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
        clocksource_register(&orion_clksrc);
        /*
         * Setup clockevent timer (interrupt-driven.)
         */
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index 8f2c4c7fbd48..0264bfb0ca4f 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -7,3 +7,5 @@ obj-y	:= dma.o
 obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
 obj-$(CONFIG_PXA3xx)            += mfp.o
 obj-$(CONFIG_ARCH_MMP)          += mfp.o
+obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/mach-pxa/include/mach/i2c.h b/arch/arm/plat-pxa/include/plat/i2c.h
index 1a9f65e6ec0f..1a9f65e6ec0f 100644
--- a/arch/arm/mach-pxa/include/mach/i2c.h
+++ b/arch/arm/plat-pxa/include/plat/i2c.h
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
index fcdd374437a8..a9eabdcfa163 100644
--- a/arch/arm/mach-pxa/pwm.c
+++ b/arch/arm/plat-pxa/pwm.c
@@ -21,6 +21,19 @@
 #include <asm/div64.h>
+#define HAS_SECONDARY_PWM       0x10
+#define PWM_ID_BASE(d)          ((d) & 0xf)
+static const struct platform_device_id pwm_id_table[] = {
+        /*   PWM    has_secondary_pwm? */
+        { "pxa25x-pwm", 0 },
+        { "pxa27x-pwm", 0 | HAS_SECONDARY_PWM },
+        { "pxa168-pwm", 1 },
+        { "pxa910-pwm", 1 },
+        { },
+};
+MODULE_DEVICE_TABLE(platform, pwm_id_table);
 /* PWM registers and bits definitions */
 #define PWMCR           (0x00)
 #define PWMDCR          (0x04)
@@ -31,7 +44,8 @@
 struct pwm_device {
        struct list_head        node;
-        struct platform_device *pdev;
+        struct pwm_device       *secondary;
+        struct platform_device  *pdev;
        const char      *label;
        struct clk      *clk;
@@ -159,17 +173,17 @@ static inline void __add_pwm(struct pwm_device *pwm)
        mutex_unlock(&pwm_lock);
 }
-static struct pwm_device *pwm_probe(struct platform_device *pdev,
+static int __devinit pwm_probe(struct platform_device *pdev)
-                unsigned int pwm_id, struct pwm_device *parent_pwm)
 {
-        struct pwm_device *pwm;
+        struct platform_device_id *id = platform_get_device_id(pdev);
+        struct pwm_device *pwm, *secondary = NULL;
        struct resource *r;
        int ret = 0;
        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
        if (pwm == NULL) {
                dev_err(&pdev->dev, "failed to allocate memory\n");
-                return ERR_PTR(-ENOMEM);
+                return -ENOMEM;
        }
        pwm->clk = clk_get(&pdev->dev, NULL);
@@ -180,16 +194,9 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev,
        pwm->clk_enabled = 0;
        pwm->use_count = 0;
-        pwm->pwm_id = pwm_id;
+        pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id;
        pwm->pdev = pdev;
-        if (parent_pwm != NULL) {
-                /* registers for the second PWM has offset of 0x10 */
-                pwm->mmio_base = parent_pwm->mmio_base + 0x10;
-                __add_pwm(pwm);
-                return pwm;
-        }
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (r == NULL) {
                dev_err(&pdev->dev, "no memory resource defined\n");
@@ -211,9 +218,27 @@ static struct pwm_device *pwm_probe(struct platform_device *pdev,
                goto err_free_mem;
        }
+        if (id->driver_data & HAS_SECONDARY_PWM) {
+                secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+                if (secondary == NULL) {
+                        ret = -ENOMEM;
+                        goto err_free_mem;
+                }
+                *secondary = *pwm;
+                pwm->secondary = secondary;
+                /* registers for the second PWM has offset of 0x10 */
+                secondary->mmio_base = pwm->mmio_base + 0x10;
+                secondary->pwm_id = pdev->id + 2;
+        }
        __add_pwm(pwm);
+        if (secondary)
+                __add_pwm(secondary);
        platform_set_drvdata(pdev, pwm);
-        return pwm;
+        return 0;
 err_free_mem:
        release_mem_region(r->start, r->end - r->start + 1);
@@ -221,32 +246,7 @@ err_free_clk:
        clk_put(pwm->clk);
 err_free:
        kfree(pwm);
-        return ERR_PTR(ret);
+        return ret;
-}
-static int __devinit pxa25x_pwm_probe(struct platform_device *pdev)
-{
-        struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL);
-        if (IS_ERR(pwm))
-                return PTR_ERR(pwm);
-        return 0;
-}
-static int __devinit pxa27x_pwm_probe(struct platform_device *pdev)
-{
-        struct pwm_device *pwm;
-        pwm = pwm_probe(pdev, pdev->id, NULL);
-        if (IS_ERR(pwm))
-                return PTR_ERR(pwm);
-        pwm = pwm_probe(pdev, pdev->id + 2, pwm);
-        if (IS_ERR(pwm))
-                return PTR_ERR(pwm);
-        return 0;
 }
 static int __devexit pwm_remove(struct platform_device *pdev)
@@ -259,6 +259,12 @@ static int __devexit pwm_remove(struct platform_device *pdev)
                return -ENODEV;
        mutex_lock(&pwm_lock);
+        if (pwm->secondary) {
+                list_del(&pwm->secondary->node);
+                kfree(pwm->secondary);
+        }
        list_del(&pwm->node);
        mutex_unlock(&pwm_lock);
@@ -272,46 +278,25 @@ static int __devexit pwm_remove(struct platform_device *pdev)
        return 0;
 }
-static struct platform_driver pxa25x_pwm_driver = {
+static struct platform_driver pwm_driver = {
        .driver         = {
                .name   = "pxa25x-pwm",
+                .owner  = THIS_MODULE,
        },
-        .probe          = pxa25x_pwm_probe,
+        .probe          = pwm_probe,
-        .remove         = __devexit_p(pwm_remove),
-};
-static struct platform_driver pxa27x_pwm_driver = {
-        .driver         = {
-                .name   = "pxa27x-pwm",
-        },
-        .probe          = pxa27x_pwm_probe,
        .remove         = __devexit_p(pwm_remove),
+        .id_table       = pwm_id_table,
 };
 static int __init pwm_init(void)
 {
-        int ret = 0;
+        return platform_driver_register(&pwm_driver);
-        ret = platform_driver_register(&pxa25x_pwm_driver);
-        if (ret) {
-                printk(KERN_ERR "failed to register pxa25x_pwm_driver\n");
-                return ret;
-        }
-        ret = platform_driver_register(&pxa27x_pwm_driver);
-        if (ret) {
-                printk(KERN_ERR "failed to register pxa27x_pwm_driver\n");
-                return ret;
-        }
-        return ret;
 }
 arch_initcall(pwm_init);
 static void __exit pwm_exit(void)
 {
-        platform_driver_unregister(&pxa25x_pwm_driver);
+        platform_driver_unregister(&pwm_driver);
-        platform_driver_unregister(&pxa27x_pwm_driver);
 }
 module_exit(pwm_exit);
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index de9383814e5e..935c7558469b 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -71,6 +71,15 @@ config S3C2410_PM_DEBUG
          Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
          for more information.
+config S3C_PM_DEBUG_LED_SMDK
+       bool "SMDK LED suspend/resume debugging"
+       depends on PM && (MACH_SMDK6410)
+       help
+         Say Y here to enable the use of the SMDK LEDs on the baseboard
+         for debugging of the state of the suspend and resume process.
+         Note, this currently only works for S3C64XX based SMDK boards.
 config S3C2410_PM_CHECK
        bool "S3C2410 PM Suspend Memory CRC"
        depends on PM && CRC32
@@ -150,6 +159,13 @@ config S3C_GPIO_CFG_S3C64XX
          Internal configuration to enable S3C64XX style GPIO configuration
          functions.
+# DMA
+config S3C_DMA
+        bool
+        help
+          Internal configuration for S3C DMA core
 # device definitions to compile in
 config S3C_DEV_HSMMC
@@ -172,4 +188,14 @@ config S3C_DEV_FB
        help
          Compile in platform device definition for framebuffer
+config S3C_DEV_USB_HOST
+        bool
+        help
+          Compile in platform device definition for USB host.
+config S3C_DEV_USB_HSOTG
+        bool
+        help
+          Compile in platform device definition for USB high-speed OtG
 endif
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 8d7815d25a51..610651455a78 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -18,9 +18,14 @@ obj-y				+= pwm-clock.o
 obj-y                           += gpio.o
 obj-y                           += gpio-config.o
+# DMA support
+obj-$(CONFIG_S3C_DMA)           += dma.o
 # PM support
 obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM)                += pm-gpio.o
 obj-$(CONFIG_S3C2410_PM_CHECK)  += pm-check.o
 # devices
@@ -30,3 +35,5 @@ obj-$(CONFIG_S3C_DEV_HSMMC1)	+= dev-hsmmc1.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
+obj-$(CONFIG_S3C_DEV_USB_HOST)  += dev-usb.o
+obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
diff --git a/arch/arm/plat-s3c/dev-usb-hsotg.c b/arch/arm/plat-s3c/dev-usb-hsotg.c
new file mode 100644
index 000000000000..e2f604b51c86
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-usb-hsotg.c
@@ -0,0 +1,41 @@
+/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for USB high-speed UDC/OtG block
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/devs.h>
+static struct resource s3c_usb_hsotg_resources[] = {
+        [0] = {
+                .start  = S3C_PA_USB_HSOTG,
+                .end    = S3C_PA_USB_HSOTG + 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_OTG,
+                .end    = IRQ_OTG,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device s3c_device_usb_hsotg = {
+        .name           = "s3c-hsotg",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s3c_usb_hsotg_resources),
+        .resource       = s3c_usb_hsotg_resources,
+};
diff --git a/arch/arm/plat-s3c/dev-usb.c b/arch/arm/plat-s3c/dev-usb.c
new file mode 100644
index 000000000000..2ee85abed6d9
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-usb.c
@@ -0,0 +1,50 @@
+/* linux/arch/arm/plat-s3c/dev-usb.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for USB host
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/devs.h>
+static struct resource s3c_usb_resource[] = {
+        [0] = {
+                .start = S3C_PA_USBHOST,
+                .end   = S3C_PA_USBHOST + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 s3c_device_usb_dmamask = 0xffffffffUL;
+struct platform_device s3c_device_usb = {
+        .name             = "s3c2410-ohci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_usb_resource),
+        .resource         = s3c_usb_resource,
+        .dev              = {
+                .dma_mask = &s3c_device_usb_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+EXPORT_SYMBOL(s3c_device_usb);
diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c
new file mode 100644
index 000000000000..c9db75c06af5
--- /dev/null
+++ b/arch/arm/plat-s3c/dma.c
@@ -0,0 +1,86 @@
+/* linux/arch/arm/plat-s3c/dma.c
+ *
+ * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C DMA core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+struct s3c2410_dma_buf;
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+#include <plat/dma-plat.h>
+/* dma channel state information */
+struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
+struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
+/* s3c_dma_lookup_channel
+ *
+ * change the dma channel number given into a real dma channel id
+*/
+struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
+{
+        if (channel & DMACH_LOW_LEVEL)
+                return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
+        else
+                return s3c_dma_chan_map[channel];
+}
+/* do we need to protect the settings of the fields from
+ * irq?
+*/
+int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        if (chan == NULL)
+                return -EINVAL;
+        pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
+        chan->op_fn = rtn;
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_set_opfn);
+int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        if (chan == NULL)
+                return -EINVAL;
+        pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
+        chan->callback_fn = rtn;
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
+int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        if (chan == NULL)
+                return -EINVAL;
+        chan->flags = flags;
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_setflags);
diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
index d71dd6d9ce5c..260fdc6ad685 100644
--- a/arch/arm/plat-s3c/gpio.c
+++ b/arch/arm/plat-s3c/gpio.c
@@ -16,7 +16,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
-#include <plat/gpio-core.h>
+#include <mach/gpio-core.h>
 #ifdef CONFIG_S3C_GPIO_TRACK
 struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
@@ -140,6 +140,15 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
        if (!gc->get)
                gc->get = s3c_gpiolib_get;
+#ifdef CONFIG_PM
+        if (chip->pm != NULL) {
+                if (!chip->pm->save || !chip->pm->resume)
+                        printk(KERN_ERR "gpio: %s has missing PM functions\n",
+                               gc->label);
+        } else
+                printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
+#endif
        /* gpiochip_add() prints own failure message on error. */
        ret = gpiochip_add(gc);
        if (ret >= 0)
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h
index 43df2a404b0b..d847bd476b6c 100644
--- a/arch/arm/plat-s3c/include/plat/adc.h
+++ b/arch/arm/plat-s3c/include/plat/adc.h
@@ -19,10 +19,12 @@ struct s3c_adc_client;
 extern int s3c_adc_start(struct s3c_adc_client *client,
                         unsigned int channel, unsigned int nr_samples);
-extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
+extern struct s3c_adc_client *
-                                               void (*select)(unsigned selected),
+        s3c_adc_register(struct platform_device *pdev,
-                                               void (*conv)(unsigned d0, unsigned d1),
+                         void (*select)(unsigned selected),
-                                               unsigned int is_ts);
+                         void (*conv)(unsigned d0, unsigned d1,
+                                      unsigned *samples_left),
+                         unsigned int is_ts);
 extern void s3c_adc_release(struct s3c_adc_client *client);
diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h
index a10622eed43a..d86af84b5b8c 100644
--- a/arch/arm/plat-s3c/include/plat/clock.h
+++ b/arch/arm/plat-s3c/include/plat/clock.h
@@ -50,6 +50,7 @@ extern struct clk clk_xtal;
 extern struct clk clk_ext;
 /* S3C64XX specific clocks */
+extern struct clk clk_h2;
 extern struct clk clk_27m;
 extern struct clk clk_48m;
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index e62ae0fcfe56..be541cbba070 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -69,3 +69,6 @@ extern struct sysdev_class s3c2412_sysclass;
 extern struct sysdev_class s3c2440_sysclass;
 extern struct sysdev_class s3c2442_sysclass;
 extern struct sysdev_class s3c2443_sysclass;
+extern struct sysdev_class s3c6410_sysclass;
+extern struct sysdev_class s3c64xx_sysclass;
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index 26f0cec3ac04..a0b6768fddcf 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -45,6 +45,7 @@ extern struct platform_device s3c_device_spi1;
 extern struct platform_device s3c_device_nand;
 extern struct platform_device s3c_device_usbgadget;
+extern struct platform_device s3c_device_usb_hsotg;
 /* s3c2440 specific devices */
diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-s3c/include/plat/dma-core.h
new file mode 100644
index 000000000000..32ff2a92cb3c
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma-core.h
@@ -0,0 +1,22 @@
+/* arch/arm/plat-s3c/include/plat/dma.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung S3C DMA core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
+extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
+/* the currently allocated channel information */
+extern struct s3c2410_dma_chan s3c2410_chans[];
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h
new file mode 100644
index 000000000000..34dba98f08e1
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma.h
@@ -0,0 +1,127 @@
+/* arch/arm/plat-s3c/include/plat/dma.h
+ *
+ * Copyright (C) 2003,2004,2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+enum s3c2410_dma_buffresult {
+        S3C2410_RES_OK,
+        S3C2410_RES_ERR,
+        S3C2410_RES_ABORT
+};
+enum s3c2410_dmasrc {
+        S3C2410_DMASRC_HW,              /* source is memory */
+        S3C2410_DMASRC_MEM              /* source is hardware */
+};
+/* enum s3c2410_chan_op
+ *
+ * operation codes passed to the DMA code by the user, and also used
+ * to inform the current channel owner of any changes to the system state
+*/
+enum s3c2410_chan_op {
+        S3C2410_DMAOP_START,
+        S3C2410_DMAOP_STOP,
+        S3C2410_DMAOP_PAUSE,
+        S3C2410_DMAOP_RESUME,
+        S3C2410_DMAOP_FLUSH,
+        S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
+        S3C2410_DMAOP_STARTED,          /* indicate channel started */
+};
+struct s3c2410_dma_client {
+        char                *name;
+};
+struct s3c2410_dma_chan;
+/* s3c2410_dma_cbfn_t
+ *
+ * buffer callback routine type
+*/
+typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
+                                   void *buf, int size,
+                                   enum s3c2410_dma_buffresult result);
+typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
+                                   enum s3c2410_chan_op );
+/* s3c2410_dma_request
+ *
+ * request a dma channel exclusivley
+*/
+extern int s3c2410_dma_request(unsigned int channel,
+                               struct s3c2410_dma_client *, void *dev);
+/* s3c2410_dma_ctrl
+ *
+ * change the state of the dma channel
+*/
+extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
+/* s3c2410_dma_setflags
+ *
+ * set the channel's flags to a given state
+*/
+extern int s3c2410_dma_setflags(unsigned int channel,
+                                unsigned int flags);
+/* s3c2410_dma_free
+ *
+ * free the dma channel (will also abort any outstanding operations)
+*/
+extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
+/* s3c2410_dma_enqueue
+ *
+ * place the given buffer onto the queue of operations for the channel.
+ * The buffer must be allocated from dma coherent memory, or the Dcache/WB
+ * drained before the buffer is given to the DMA system.
+*/
+extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
+                               dma_addr_t data, int size);
+/* s3c2410_dma_config
+ *
+ * configure the dma channel
+*/
+extern int s3c2410_dma_config(unsigned int channel, int xferunit);
+/* s3c2410_dma_devconfig
+ *
+ * configure the device we're talking to
+*/
+extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
+                                 unsigned long devaddr);
+/* s3c2410_dma_getposition
+ *
+ * get the position that the dma transfer is currently at
+*/
+extern int s3c2410_dma_getposition(unsigned int channel,
+                                   dma_addr_t *src, dma_addr_t *dest);
+extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
+extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h
index 2fc60a580ac8..32af612767aa 100644
--- a/arch/arm/plat-s3c/include/plat/gpio-core.h
+++ b/arch/arm/plat-s3c/include/plat/gpio-core.h
@@ -20,6 +20,18 @@
 * specific code.
 */
+struct s3c_gpio_chip;
+/**
+ * struct s3c_gpio_pm - power management (suspend/resume) information
+ * @save: Routine to save the state of the GPIO block
+ * @resume: Routine to resume the GPIO block.
+ */
+struct s3c_gpio_pm {
+        void (*save)(struct s3c_gpio_chip *chip);
+        void (*resume)(struct s3c_gpio_chip *chip);
+};
 struct s3c_gpio_cfg;
 /**
@@ -27,6 +39,7 @@ struct s3c_gpio_cfg;
 * @chip: The chip structure to be exported via gpiolib.
 * @base: The base pointer to the gpio configuration registers.
 * @config: special function and pull-resistor control information.
+ * @pm_save: Save information for suspend/resume support.
 *
 * This wrapper provides the necessary information for the Samsung
 * specific gpios being registered with gpiolib.
@@ -34,7 +47,11 @@ struct s3c_gpio_cfg;
 struct s3c_gpio_chip {
        struct gpio_chip        chip;
        struct s3c_gpio_cfg     *config;
+        struct s3c_gpio_pm      *pm;
        void __iomem            *base;
+#ifdef CONFIG_PM
+        u32                     pm_save[4];
+#endif
 };
 static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
@@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
 static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
 #endif
+#ifdef CONFIG_PM
+extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
+#define __gpio_pm(x) x
+#else
+#define s3c_gpio_pm_1bit NULL
+#define s3c_gpio_pm_2bit NULL
+#define s3c_gpio_pm_4bit NULL
+#define __gpio_pm(x) NULL
+#endif /* CONFIG_PM */
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h
index 3779775133a9..7a797192fcf3 100644
--- a/arch/arm/plat-s3c/include/plat/pm.h
+++ b/arch/arm/plat-s3c/include/plat/pm.h
@@ -44,6 +44,8 @@ extern void (*pm_cpu_sleep)(void);
 extern unsigned long s3c_pm_flags;
+extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
 /* from sleep.S */
 extern int  s3c_cpu_save(unsigned long *saveblk);
@@ -88,6 +90,7 @@ struct pm_uart_save {
        u32     ufcon;
        u32     umcon;
        u32     ubrdiv;
+        u32     udivslot;
 };
 /* helper functions to save/restore lists of registers. */
@@ -124,6 +127,18 @@ extern void s3c_pm_dbg(const char *msg, ...);
 #define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
 #endif
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+/**
+ * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
+ * @set: set bits for the state of the LEDs
+ * @clear: clear bits for the state of the LEDs.
+ */
+extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
+#else
+static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
+#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
 /* suspend memory checking */
 #ifdef CONFIG_S3C2410_PM_CHECK
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index 487d7d2a7e1d..66af75a5cdd1 100644
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -189,6 +189,11 @@
 #define S3C2443_DIVSLOT           (0x2C)
+/* S3C64XX interrupt registers. */
+#define S3C64XX_UINTP           0x30
+#define S3C64XX_UINTSP          0x34
+#define S3C64XX_UINTM           0x38
 #ifndef __ASSEMBLY__
 /* struct s3c24xx_uart_clksrc
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..36a85f5000c8
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
+/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - USB2.0 Highspeed/OtG device PHY registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* Note, this is a seperate header file as some of the clock framework
+ * needs to touch this if the clk_48m is used as the USB OHCI or other
+ * peripheral source.
+*/
+#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
+#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
+/* S3C64XX_PA_USB_HSPHY */
+#define S3C_HSOTG_PHYREG(x)     ((x) + S3C_VA_USB_HSPHY)
+#define S3C_PHYPWR                              S3C_HSOTG_PHYREG(0x00)
+#define SRC_PHYPWR_OTG_DISABLE                  (1 << 4)
+#define SRC_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
+#define SRC_PHYPWR_FORCE_SUSPEND                (1 << 1)
+#define S3C_PHYCLK                              S3C_HSOTG_PHYREG(0x04)
+#define S3C_PHYCLK_MODE_USB11                   (1 << 6)
+#define S3C_PHYCLK_EXT_OSC                      (1 << 5)
+#define S3C_PHYCLK_CLK_FORCE                    (1 << 4)
+#define S3C_PHYCLK_ID_PULL                      (1 << 2)
+#define S3C_PHYCLK_CLKSEL_MASK                  (0x3 << 0)
+#define S3C_PHYCLK_CLKSEL_SHIFT                 (0)
+#define S3C_PHYCLK_CLKSEL_48M                   (0x0 << 0)
+#define S3C_PHYCLK_CLKSEL_12M                   (0x2 << 0)
+#define S3C_PHYCLK_CLKSEL_24M                   (0x3 << 0)
+#define S3C_RSTCON                              S3C_HSOTG_PHYREG(0x08)
+#define S3C_RSTCON_PHYCLK                       (1 << 2)
+#define S3C_RSTCON_HCLK                         (1 << 2)
+#define S3C_RSTCON_PHY                          (1 << 0)
+#define S3C_PHYTUNE                             S3C_HSOTG_PHYREG(0x20)
+#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
new file mode 100644
index 000000000000..8d18d9d4d148
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
@@ -0,0 +1,377 @@
+/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - USB2.0 Highspeed/OtG device block registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
+#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
+#define S3C_HSOTG_REG(x) (x)
+#define S3C_GOTGCTL                             S3C_HSOTG_REG(0x000)
+#define S3C_GOTGCTL_BSESVLD                     (1 << 19)
+#define S3C_GOTGCTL_ASESVLD                     (1 << 18)
+#define S3C_GOTGCTL_DBNC_SHORT                  (1 << 17)
+#define S3C_GOTGCTL_CONID_B                     (1 << 16)
+#define S3C_GOTGCTL_DEVHNPEN                    (1 << 11)
+#define S3C_GOTGCTL_HSSETHNPEN                  (1 << 10)
+#define S3C_GOTGCTL_HNPREQ                      (1 << 9)
+#define S3C_GOTGCTL_HSTNEGSCS                   (1 << 8)
+#define S3C_GOTGCTL_SESREQ                      (1 << 1)
+#define S3C_GOTGCTL_SESREQSCS                   (1 << 0)
+#define S3C_GOTGINT                             S3C_HSOTG_REG(0x004)
+#define S3C_GOTGINT_DbnceDone                   (1 << 19)
+#define S3C_GOTGINT_ADevTOUTChg                 (1 << 18)
+#define S3C_GOTGINT_HstNegDet                   (1 << 17)
+#define S3C_GOTGINT_HstnegSucStsChng            (1 << 9)
+#define S3C_GOTGINT_SesReqSucStsChng            (1 << 8)
+#define S3C_GOTGINT_SesEndDet                   (1 << 2)
+#define S3C_GAHBCFG                             S3C_HSOTG_REG(0x008)
+#define S3C_GAHBCFG_PTxFEmpLvl                  (1 << 8)
+#define S3C_GAHBCFG_NPTxFEmpLvl                 (1 << 7)
+#define S3C_GAHBCFG_DMAEn                       (1 << 5)
+#define S3C_GAHBCFG_HBstLen_MASK                (0xf << 1)
+#define S3C_GAHBCFG_HBstLen_SHIFT               (1)
+#define S3C_GAHBCFG_HBstLen_Single              (0x0 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr                (0x1 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr4               (0x3 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr8               (0x5 << 1)
+#define S3C_GAHBCFG_HBstLen_Incr16              (0x7 << 1)
+#define S3C_GAHBCFG_GlblIntrEn                  (1 << 0)
+#define S3C_GUSBCFG                             S3C_HSOTG_REG(0x00C)
+#define S3C_GUSBCFG_PHYLPClkSel                 (1 << 15)
+#define S3C_GUSBCFG_HNPCap                      (1 << 9)
+#define S3C_GUSBCFG_SRPCap                      (1 << 8)
+#define S3C_GUSBCFG_PHYIf16                     (1 << 3)
+#define S3C_GUSBCFG_TOutCal_MASK                (0x7 << 0)
+#define S3C_GUSBCFG_TOutCal_SHIFT               (0)
+#define S3C_GUSBCFG_TOutCal_LIMIT               (0x7)
+#define S3C_GUSBCFG_TOutCal(_x)                 ((_x) << 0)
+#define S3C_GRSTCTL                             S3C_HSOTG_REG(0x010)
+#define S3C_GRSTCTL_AHBIdle                     (1 << 31)
+#define S3C_GRSTCTL_DMAReq                      (1 << 30)
+#define S3C_GRSTCTL_TxFNum_MASK                 (0x1f << 6)
+#define S3C_GRSTCTL_TxFNum_SHIFT                (6)
+#define S3C_GRSTCTL_TxFNum_LIMIT                (0x1f)
+#define S3C_GRSTCTL_TxFNum(_x)                  ((_x) << 6)
+#define S3C_GRSTCTL_TxFFlsh                     (1 << 5)
+#define S3C_GRSTCTL_RxFFlsh                     (1 << 4)
+#define S3C_GRSTCTL_INTknQFlsh                  (1 << 3)
+#define S3C_GRSTCTL_FrmCntrRst                  (1 << 2)
+#define S3C_GRSTCTL_HSftRst                     (1 << 1)
+#define S3C_GRSTCTL_CSftRst                     (1 << 0)
+#define S3C_GINTSTS                             S3C_HSOTG_REG(0x014)
+#define S3C_GINTMSK                             S3C_HSOTG_REG(0x018)
+#define S3C_GINTSTS_WkUpInt                     (1 << 31)
+#define S3C_GINTSTS_SessReqInt                  (1 << 30)
+#define S3C_GINTSTS_DisconnInt                  (1 << 29)
+#define S3C_GINTSTS_ConIDStsChng                (1 << 28)
+#define S3C_GINTSTS_PTxFEmp                     (1 << 26)
+#define S3C_GINTSTS_HChInt                      (1 << 25)
+#define S3C_GINTSTS_PrtInt                      (1 << 24)
+#define S3C_GINTSTS_FetSusp                     (1 << 22)
+#define S3C_GINTSTS_incompIP                    (1 << 21)
+#define S3C_GINTSTS_IncomplSOIN                 (1 << 20)
+#define S3C_GINTSTS_OEPInt                      (1 << 19)
+#define S3C_GINTSTS_IEPInt                      (1 << 18)
+#define S3C_GINTSTS_EPMis                       (1 << 17)
+#define S3C_GINTSTS_EOPF                        (1 << 15)
+#define S3C_GINTSTS_ISOutDrop                   (1 << 14)
+#define S3C_GINTSTS_EnumDone                    (1 << 13)
+#define S3C_GINTSTS_USBRst                      (1 << 12)
+#define S3C_GINTSTS_USBSusp                     (1 << 11)
+#define S3C_GINTSTS_ErlySusp                    (1 << 10)
+#define S3C_GINTSTS_GOUTNakEff                  (1 << 7)
+#define S3C_GINTSTS_GINNakEff                   (1 << 6)
+#define S3C_GINTSTS_NPTxFEmp                    (1 << 5)
+#define S3C_GINTSTS_RxFLvl                      (1 << 4)
+#define S3C_GINTSTS_SOF                         (1 << 3)
+#define S3C_GINTSTS_OTGInt                      (1 << 2)
+#define S3C_GINTSTS_ModeMis                     (1 << 1)
+#define S3C_GINTSTS_CurMod_Host                 (1 << 0)
+#define S3C_GRXSTSR                             S3C_HSOTG_REG(0x01C)
+#define S3C_GRXSTSP                             S3C_HSOTG_REG(0x020)
+#define S3C_GRXSTS_FN_MASK                      (0x7f << 25)
+#define S3C_GRXSTS_FN_SHIFT                     (25)
+#define S3C_GRXSTS_PktSts_MASK                  (0xf << 17)
+#define S3C_GRXSTS_PktSts_SHIFT                 (17)
+#define S3C_GRXSTS_PktSts_GlobalOutNAK          (0x1 << 17)
+#define S3C_GRXSTS_PktSts_OutRX                 (0x2 << 17)
+#define S3C_GRXSTS_PktSts_OutDone               (0x3 << 17)
+#define S3C_GRXSTS_PktSts_SetupDone             (0x4 << 17)
+#define S3C_GRXSTS_PktSts_SetupRX               (0x6 << 17)
+#define S3C_GRXSTS_DPID_MASK                    (0x3 << 15)
+#define S3C_GRXSTS_DPID_SHIFT                   (15)
+#define S3C_GRXSTS_ByteCnt_MASK                 (0x7ff << 4)
+#define S3C_GRXSTS_ByteCnt_SHIFT                (4)
+#define S3C_GRXSTS_EPNum_MASK                   (0xf << 0)
+#define S3C_GRXSTS_EPNum_SHIFT                  (0)
+#define S3C_GRXFSIZ                             S3C_HSOTG_REG(0x024)
+#define S3C_GNPTXFSIZ                           S3C_HSOTG_REG(0x028)
+#define S3C_GNPTXFSIZ_NPTxFDep_MASK             (0xffff << 16)
+#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT            (16)
+#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT            (0xffff)
+#define S3C_GNPTXFSIZ_NPTxFDep(_x)              ((_x) << 16)
+#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK          (0xffff << 0)
+#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT         (0)
+#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT         (0xffff)
+#define S3C_GNPTXFSIZ_NPTxFStAddr(_x)           ((_x) << 0)
+#define S3C_GNPTXSTS                            S3C_HSOTG_REG(0x02C)
+#define S3C_GNPTXSTS_NPtxQTop_MASK              (0x7f << 24)
+#define S3C_GNPTXSTS_NPtxQTop_SHIFT             (24)
+#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK         (0xff << 16)
+#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT        (16)
+#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v)      (((_v) >> 16) & 0xff)
+#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK         (0xffff << 0)
+#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT        (0)
+#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v)      (((_v) >> 0) & 0xffff)
+#define S3C_HPTXFSIZ                            S3C_HSOTG_REG(0x100)
+#define S3C_DPTXFSIZn(_a)                       S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
+#define S3C_DPTXFSIZn_DPTxFSize_MASK            (0xffff << 16)
+#define S3C_DPTXFSIZn_DPTxFSize_SHIFT           (16)
+#define S3C_DPTXFSIZn_DPTxFSize_GET(_v)         (((_v) >> 16) & 0xffff)
+#define S3C_DPTXFSIZn_DPTxFSize_LIMIT           (0xffff)
+#define S3C_DPTXFSIZn_DPTxFSize(_x)             ((_x) << 16)
+#define S3C_DPTXFSIZn_DPTxFStAddr_MASK          (0xffff << 0)
+#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT         (0)
+/* Device mode registers */
+#define S3C_DCFG                                S3C_HSOTG_REG(0x800)
+#define S3C_DCFG_EPMisCnt_MASK                  (0x1f << 18)
+#define S3C_DCFG_EPMisCnt_SHIFT                 (18)
+#define S3C_DCFG_EPMisCnt_LIMIT                 (0x1f)
+#define S3C_DCFG_EPMisCnt(_x)                   ((_x) << 18)
+#define S3C_DCFG_PerFrInt_MASK                  (0x3 << 11)
+#define S3C_DCFG_PerFrInt_SHIFT                 (11)
+#define S3C_DCFG_PerFrInt_LIMIT                 (0x3)
+#define S3C_DCFG_PerFrInt(_x)                   ((_x) << 11)
+#define S3C_DCFG_DevAddr_MASK                   (0x7f << 4)
+#define S3C_DCFG_DevAddr_SHIFT                  (4)
+#define S3C_DCFG_DevAddr_LIMIT                  (0x7f)
+#define S3C_DCFG_DevAddr(_x)                    ((_x) << 4)
+#define S3C_DCFG_NZStsOUTHShk                   (1 << 2)
+#define S3C_DCFG_DevSpd_MASK                    (0x3 << 0)
+#define S3C_DCFG_DevSpd_SHIFT                   (0)
+#define S3C_DCFG_DevSpd_HS                      (0x0 << 0)
+#define S3C_DCFG_DevSpd_FS                      (0x1 << 0)
+#define S3C_DCFG_DevSpd_LS                      (0x2 << 0)
+#define S3C_DCFG_DevSpd_FS48                    (0x3 << 0)
+#define S3C_DCTL                                S3C_HSOTG_REG(0x804)
+#define S3C_DCTL_PWROnPrgDone                   (1 << 11)
+#define S3C_DCTL_CGOUTNak                       (1 << 10)
+#define S3C_DCTL_SGOUTNak                       (1 << 9)
+#define S3C_DCTL_CGNPInNAK                      (1 << 8)
+#define S3C_DCTL_SGNPInNAK                      (1 << 7)
+#define S3C_DCTL_TstCtl_MASK                    (0x7 << 4)
+#define S3C_DCTL_TstCtl_SHIFT                   (4)
+#define S3C_DCTL_GOUTNakSts                     (1 << 3)
+#define S3C_DCTL_GNPINNakSts                    (1 << 2)
+#define S3C_DCTL_SftDiscon                      (1 << 1)
+#define S3C_DCTL_RmtWkUpSig                     (1 << 0)
+#define S3C_DSTS                                S3C_HSOTG_REG(0x808)
+#define S3C_DSTS_SOFFN_MASK                     (0x3fff << 8)
+#define S3C_DSTS_SOFFN_SHIFT                    (8)
+#define S3C_DSTS_SOFFN_LIMIT                    (0x3fff)
+#define S3C_DSTS_SOFFN(_x)                      ((_x) << 8)
+#define S3C_DSTS_ErraticErr                     (1 << 3)
+#define S3C_DSTS_EnumSpd_MASK                   (0x3 << 1)
+#define S3C_DSTS_EnumSpd_SHIFT                  (1)
+#define S3C_DSTS_EnumSpd_HS                     (0x0 << 1)
+#define S3C_DSTS_EnumSpd_FS                     (0x1 << 1)
+#define S3C_DSTS_EnumSpd_LS                     (0x2 << 1)
+#define S3C_DSTS_EnumSpd_FS48                   (0x3 << 1)
+#define S3C_DSTS_SuspSts                        (1 << 0)
+#define S3C_DIEPMSK                             S3C_HSOTG_REG(0x810)
+#define S3C_DIEPMSK_INEPNakEffMsk               (1 << 6)
+#define S3C_DIEPMSK_INTknEPMisMsk               (1 << 5)
+#define S3C_DIEPMSK_INTknTXFEmpMsk              (1 << 4)
+#define S3C_DIEPMSK_TimeOUTMsk                  (1 << 3)
+#define S3C_DIEPMSK_AHBErrMsk                   (1 << 2)
+#define S3C_DIEPMSK_EPDisbldMsk                 (1 << 1)
+#define S3C_DIEPMSK_XferComplMsk                (1 << 0)
+#define S3C_DOEPMSK                             S3C_HSOTG_REG(0x814)
+#define S3C_DOEPMSK_Back2BackSetup              (1 << 6)
+#define S3C_DOEPMSK_OUTTknEPdisMsk              (1 << 4)
+#define S3C_DOEPMSK_SetupMsk                    (1 << 3)
+#define S3C_DOEPMSK_AHBErrMsk                   (1 << 2)
+#define S3C_DOEPMSK_EPDisbldMsk                 (1 << 1)
+#define S3C_DOEPMSK_XferComplMsk                (1 << 0)
+#define S3C_DAINT                               S3C_HSOTG_REG(0x818)
+#define S3C_DAINTMSK                            S3C_HSOTG_REG(0x81C)
+#define S3C_DAINT_OutEP_SHIFT                   (16)
+#define S3C_DAINT_OutEP(x)                      (1 << ((x) + 16))
+#define S3C_DAINT_InEP(x)                       (1 << (x))
+#define S3C_DTKNQR1                             S3C_HSOTG_REG(0x820)
+#define S3C_DTKNQR2                             S3C_HSOTG_REG(0x824)
+#define S3C_DTKNQR3                             S3C_HSOTG_REG(0x830)
+#define S3C_DTKNQR4                             S3C_HSOTG_REG(0x834)
+#define S3C_DVBUSDIS                            S3C_HSOTG_REG(0x828)
+#define S3C_DVBUSPULSE                          S3C_HSOTG_REG(0x82C)
+#define S3C_DIEPCTL0                            S3C_HSOTG_REG(0x900)
+#define S3C_DOEPCTL0                            S3C_HSOTG_REG(0xB00)
+#define S3C_DIEPCTL(_a)                         S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
+#define S3C_DOEPCTL(_a)                         S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
+/* EP0 specialness:
+ * bits[29..28] - reserved (no SetD0PID, SetD1PID)
+ * bits[25..22] - should always be zero, this isn't a periodic endpoint
+ * bits[10..0] - MPS setting differenct for EP0
+*/
+#define S3C_D0EPCTL_MPS_MASK                    (0x3 << 0)
+#define S3C_D0EPCTL_MPS_SHIFT                   (0)
+#define S3C_D0EPCTL_MPS_64                      (0x0 << 0)
+#define S3C_D0EPCTL_MPS_32                      (0x1 << 0)
+#define S3C_D0EPCTL_MPS_16                      (0x2 << 0)
+#define S3C_D0EPCTL_MPS_8                       (0x3 << 0)
+#define S3C_DxEPCTL_EPEna                       (1 << 31)
+#define S3C_DxEPCTL_EPDis                       (1 << 30)
+#define S3C_DxEPCTL_SetD1PID                    (1 << 29)
+#define S3C_DxEPCTL_SetOddFr                    (1 << 29)
+#define S3C_DxEPCTL_SetD0PID                    (1 << 28)
+#define S3C_DxEPCTL_SetEvenFr                   (1 << 28)
+#define S3C_DxEPCTL_SNAK                        (1 << 27)
+#define S3C_DxEPCTL_CNAK                        (1 << 26)
+#define S3C_DxEPCTL_TxFNum_MASK                 (0xf << 22)
+#define S3C_DxEPCTL_TxFNum_SHIFT                (22)
+#define S3C_DxEPCTL_TxFNum_LIMIT                (0xf)
+#define S3C_DxEPCTL_TxFNum(_x)                  ((_x) << 22)
+#define S3C_DxEPCTL_Stall                       (1 << 21)
+#define S3C_DxEPCTL_Snp                         (1 << 20)
+#define S3C_DxEPCTL_EPType_MASK                 (0x3 << 18)
+#define S3C_DxEPCTL_EPType_SHIFT                (18)
+#define S3C_DxEPCTL_EPType_Control              (0x0 << 18)
+#define S3C_DxEPCTL_EPType_Iso                  (0x1 << 18)
+#define S3C_DxEPCTL_EPType_Bulk                 (0x2 << 18)
+#define S3C_DxEPCTL_EPType_Intterupt            (0x3 << 18)
+#define S3C_DxEPCTL_NAKsts                      (1 << 17)
+#define S3C_DxEPCTL_DPID                        (1 << 16)
+#define S3C_DxEPCTL_EOFrNum                     (1 << 16)
+#define S3C_DxEPCTL_USBActEp                    (1 << 15)
+#define S3C_DxEPCTL_NextEp_MASK                 (0xf << 11)
+#define S3C_DxEPCTL_NextEp_SHIFT                (11)
+#define S3C_DxEPCTL_NextEp_LIMIT                (0xf)
+#define S3C_DxEPCTL_NextEp(_x)                  ((_x) << 11)
+#define S3C_DxEPCTL_MPS_MASK                    (0x7ff << 0)
+#define S3C_DxEPCTL_MPS_SHIFT                   (0)
+#define S3C_DxEPCTL_MPS_LIMIT                   (0x7ff)
+#define S3C_DxEPCTL_MPS(_x)                     ((_x) << 0)
+#define S3C_DIEPINT(_a)                         S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
+#define S3C_DOEPINT(_a)                         S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
+#define S3C_DxEPINT_INEPNakEff                  (1 << 6)
+#define S3C_DxEPINT_Back2BackSetup              (1 << 6)
+#define S3C_DxEPINT_INTknEPMis                  (1 << 5)
+#define S3C_DxEPINT_INTknTXFEmp                 (1 << 4)
+#define S3C_DxEPINT_OUTTknEPdis                 (1 << 4)
+#define S3C_DxEPINT_Timeout                     (1 << 3)
+#define S3C_DxEPINT_Setup                       (1 << 3)
+#define S3C_DxEPINT_AHBErr                      (1 << 2)
+#define S3C_DxEPINT_EPDisbld                    (1 << 1)
+#define S3C_DxEPINT_XferCompl                   (1 << 0)
+#define S3C_DIEPTSIZ0                           S3C_HSOTG_REG(0x910)
+#define S3C_DIEPTSIZ0_PktCnt_MASK               (0x3 << 19)
+#define S3C_DIEPTSIZ0_PktCnt_SHIFT              (19)
+#define S3C_DIEPTSIZ0_PktCnt_LIMIT              (0x3)
+#define S3C_DIEPTSIZ0_PktCnt(_x)                ((_x) << 19)
+#define S3C_DIEPTSIZ0_XferSize_MASK             (0x7f << 0)
+#define S3C_DIEPTSIZ0_XferSize_SHIFT            (0)
+#define S3C_DIEPTSIZ0_XferSize_LIMIT            (0x7f)
+#define S3C_DIEPTSIZ0_XferSize(_x)              ((_x) << 0)
+#define DOEPTSIZ0                               S3C_HSOTG_REG(0xB10)
+#define S3C_DOEPTSIZ0_SUPCnt_MASK               (0x3 << 29)
+#define S3C_DOEPTSIZ0_SUPCnt_SHIFT              (29)
+#define S3C_DOEPTSIZ0_SUPCnt_LIMIT              (0x3)
+#define S3C_DOEPTSIZ0_SUPCnt(_x)                ((_x) << 29)
+#define S3C_DOEPTSIZ0_PktCnt                    (1 << 19)
+#define S3C_DOEPTSIZ0_XferSize_MASK             (0x7f << 0)
+#define S3C_DOEPTSIZ0_XferSize_SHIFT            (0)
+#define S3C_DIEPTSIZ(_a)                        S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
+#define S3C_DOEPTSIZ(_a)                        S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
+#define S3C_DxEPTSIZ_MC_MASK                    (0x3 << 29)
+#define S3C_DxEPTSIZ_MC_SHIFT                   (29)
+#define S3C_DxEPTSIZ_MC_LIMIT                   (0x3)
+#define S3C_DxEPTSIZ_MC(_x)                     ((_x) << 29)
+#define S3C_DxEPTSIZ_PktCnt_MASK                (0x3ff << 19)
+#define S3C_DxEPTSIZ_PktCnt_SHIFT               (19)
+#define S3C_DxEPTSIZ_PktCnt_GET(_v)             (((_v) >> 19) & 0x3ff)
+#define S3C_DxEPTSIZ_PktCnt_LIMIT               (0x3ff)
+#define S3C_DxEPTSIZ_PktCnt(_x)                 ((_x) << 19)
+#define S3C_DxEPTSIZ_XferSize_MASK              (0x7ffff << 0)
+#define S3C_DxEPTSIZ_XferSize_SHIFT             (0)
+#define S3C_DxEPTSIZ_XferSize_GET(_v)           (((_v) >> 0) & 0x7ffff)
+#define S3C_DxEPTSIZ_XferSize_LIMIT             (0x7ffff)
+#define S3C_DxEPTSIZ_XferSize(_x)               ((_x) << 0)
+#define S3C_DIEPDMA(_a)                         S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
+#define S3C_DOEPDMA(_a)                         S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
+#define S3C_EPFIFO(_a)                          S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
+#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index c4ca3920ca4b..f615308ccdfb 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -67,12 +67,52 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
 /* Helper function availablity */
+extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+/* S3C6400 SDHCI setup */
+#ifdef CONFIG_S3C6400_SETUP_SDHCI
+extern char *s3c6400_hsmmc_clksrcs[4];
+#ifdef CONFIG_S3C_DEV_HSMMC
+extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
+                                         void __iomem *r,
+                                         struct mmc_ios *ios,
+                                         struct mmc_card *card);
+static inline void s3c6400_default_sdhci0(void)
+{
+        s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6400_default_sdhci0(void) { }
+#endif  /* CONFIG_S3C_DEV_HSMMC */
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s3c6400_default_sdhci1(void)
+{
+        s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6400_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+#else
+static inline void s3c6400_default_sdhci0(void) { }
+static inline void s3c6400_default_sdhci1(void) { }
+#endif /* CONFIG_S3C6400_SETUP_SDHCI */
+/* S3C6410 SDHCI setup */
 #ifdef CONFIG_S3C6410_SETUP_SDHCI
 extern char *s3c6410_hsmmc_clksrcs[4];
-extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
-extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
                                           void __iomem *r,
                                           struct mmc_ios *ios,
@@ -82,7 +122,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
 static inline void s3c6410_default_sdhci0(void)
 {
        s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
-        s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
        s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
 }
 #else
@@ -93,7 +133,7 @@ static inline void s3c6410_default_sdhci0(void) { }
 static inline void s3c6410_default_sdhci1(void)
 {
        s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
-        s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
        s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
 }
 #else
diff --git a/arch/arm/plat-s3c/include/plat/udc-hs.h b/arch/arm/plat-s3c/include/plat/udc-hs.h
new file mode 100644
index 000000000000..dd04db043109
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/udc-hs.h
@@ -0,0 +1,29 @@
+/* arch/arm/plat-s3c/include/plat/udc-hs.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C USB2.0 High-speed / OtG platform information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+enum s3c_hostg_dmamode {
+        S3C_HSOTG_DMA_NONE,     /* do not use DMA at-all */
+        S3C_HSOTG_DMA_ONLY,     /* always use DMA */
+        S3C_HSOTG_DMA_DRV,      /* DMA is chosen by driver */
+};
+/**
+ * struct s3c_hsotg_plat - platform data for high-speed otg/udc
+ * @dma: Whether to use DMA or not.
+ * @is_osc: The clock source is an oscillator, not a crystal
+ */
+struct s3c_hsotg_plat {
+        enum s3c_hostg_dmamode  dma;
+        unsigned int            is_osc : 1;
+};
diff --git a/arch/arm/plat-s3c/include/plat/watchdog-reset.h b/arch/arm/plat-s3c/include/plat/watchdog-reset.h
new file mode 100644
index 000000000000..54b762acb5a0
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/watchdog-reset.h
@@ -0,0 +1,49 @@
+/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System define for arch_reset() function
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <plat/regs-watchdog.h>
+#include <mach/map.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+static inline void arch_wdt_reset(void)
+{
+        struct clk *wdtclk;
+        printk("arch_reset: attempting watchdog reset\n");
+        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
+        wdtclk = clk_get(NULL, "watchdog");
+        if (!IS_ERR(wdtclk)) {
+                clk_enable(wdtclk);
+        } else
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+        /* put initial values into count and data */
+        __raw_writel(0x80, S3C2410_WTCNT);
+        __raw_writel(0x80, S3C2410_WTDAT);
+        /* set the watchdog to go and reset... */
+        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
+                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
+        /* wait for reset to assert... */
+        mdelay(500);
+        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+}
diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-s3c/pm-gpio.c
new file mode 100644
index 000000000000..cfd326a8b693
--- /dev/null
+++ b/arch/arm/plat-s3c/pm-gpio.c
@@ -0,0 +1,380 @@
+/* linux/arch/arm/plat-s3c/pm-gpio.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO PM code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/gpio-core.h>
+#include <plat/pm.h>
+/* PM GPIO helpers */
+#define OFFS_CON        (0x00)
+#define OFFS_DAT        (0x04)
+#define OFFS_UP         (0x08)
+static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+}
+static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon = __raw_readl(base + OFFS_CON);
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpcon = chip->pm_save[0];
+        u32 gps_gpdat = chip->pm_save[1];
+        u32 gpcon;
+        /* GPACON only has one bit per control / data and no PULLUPs.
+         * GPACON[x] = 0 => Output, 1 => SFN */
+        /* first set all SFN bits to SFN */
+        gpcon = old_gpcon | gps_gpcon;
+        __raw_writel(gpcon, base + OFFS_CON);
+        /* now set all the other bits */
+        __raw_writel(gps_gpdat, base + OFFS_DAT);
+        __raw_writel(gps_gpcon, base + OFFS_CON);
+        S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+                  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+struct s3c_gpio_pm s3c_gpio_pm_1bit = {
+        .save   = s3c_gpio_pm_1bit_save,
+        .resume = s3c_gpio_pm_1bit_resume,
+};
+static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+        chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+}
+/* Test whether the given masked+shifted bits of an GPIO configuration
+ * are one of the SFN (special function) modes. */
+static inline int is_sfn(unsigned long con)
+{
+        return con >= 2;
+}
+/* Test if the given masked+shifted GPIO configuration is an input */
+static inline int is_in(unsigned long con)
+{
+        return con == 0;
+}
+/* Test if the given masked+shifted GPIO configuration is an output */
+static inline int is_out(unsigned long con)
+{
+        return con == 1;
+}
+/**
+ * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
+ * @chip: The chip information to resume.
+ *
+ * Restore one of the GPIO banks that was saved during suspend. This is
+ * not as simple as once thought, due to the possibility of glitches
+ * from the order that the CON and DAT registers are set in.
+ *
+ * The three states the pin can be are {IN,OUT,SFN} which gives us 9
+ * combinations of changes to check. Three of these, if the pin stays
+ * in the same configuration can be discounted. This leaves us with
+ * the following:
+ *
+ * { IN => OUT }  Change DAT first
+ * { IN => SFN }  Change CON first
+ * { OUT => SFN } Change CON first, so new data will not glitch
+ * { OUT => IN }  Change CON first, so new data will not glitch
+ * { SFN => IN }  Change CON first
+ * { SFN => OUT } Change DAT first, so new data will not glitch [1]
+ *
+ * We do not currently deal with the UP registers as these control
+ * weak resistors, so a small delay in change should not need to bring
+ * these into the calculations.
+ *
+ * [1] this assumes that writing to a pin DAT whilst in SFN will set the
+ *     state for when it is next output.
+ */
+static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon = __raw_readl(base + OFFS_CON);
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpcon = chip->pm_save[0];
+        u32 gps_gpdat = chip->pm_save[1];
+        u32 gpcon, old, new, mask;
+        u32 change_mask = 0x0;
+        int nr;
+        /* restore GPIO pull-up settings */
+        __raw_writel(chip->pm_save[2], base + OFFS_UP);
+        /* Create a change_mask of all the items that need to have
+         * their CON value changed before their DAT value, so that
+         * we minimise the work between the two settings.
+         */
+        for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
+                old = (old_gpcon & mask) >> nr;
+                new = (gps_gpcon & mask) >> nr;
+                /* If there is no change, then skip */
+                if (old == new)
+                        continue;
+                /* If both are special function, then skip */
+                if (is_sfn(old) && is_sfn(new))
+                        continue;
+                /* Change is IN => OUT, do not change now */
+                if (is_in(old) && is_out(new))
+                        continue;
+                /* Change is SFN => OUT, do not change now */
+                if (is_sfn(old) && is_out(new))
+                        continue;
+                /* We should now be at the case of IN=>SFN,
+                 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+                change_mask |= mask;
+        }
+        /* Write the new CON settings */
+        gpcon = old_gpcon & ~change_mask;
+        gpcon |= gps_gpcon & change_mask;
+        __raw_writel(gpcon, base + OFFS_CON);
+        /* Now change any items that require DAT,CON */
+        __raw_writel(gps_gpdat, base + OFFS_DAT);
+        __raw_writel(gps_gpcon, base + OFFS_CON);
+        S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+                  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+struct s3c_gpio_pm s3c_gpio_pm_2bit = {
+        .save   = s3c_gpio_pm_2bit_save,
+        .resume = s3c_gpio_pm_2bit_resume,
+};
+#ifdef CONFIG_ARCH_S3C64XX
+static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
+{
+        chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
+        chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
+        chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+        if (chip->chip.ngpio > 8)
+                chip->pm_save[0] = __raw_readl(chip->base - 4);
+}
+static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
+{
+        u32 old, new, mask;
+        u32 change_mask = 0x0;
+        int nr;
+        for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
+                old = (old_gpcon & mask) >> nr;
+                new = (gps_gpcon & mask) >> nr;
+                /* If there is no change, then skip */
+                if (old == new)
+                        continue;
+                /* If both are special function, then skip */
+                if (is_sfn(old) && is_sfn(new))
+                        continue;
+                /* Change is IN => OUT, do not change now */
+                if (is_in(old) && is_out(new))
+                        continue;
+                /* Change is SFN => OUT, do not change now */
+                if (is_sfn(old) && is_out(new))
+                        continue;
+                /* We should now be at the case of IN=>SFN,
+                 * OUT=>SFN, OUT=>IN, SFN=>IN. */
+                change_mask |= mask;
+        }
+        return change_mask;
+}
+static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
+{
+        void __iomem *con = chip->base + (index * 4);
+        u32 old_gpcon = __raw_readl(con);
+        u32 gps_gpcon = chip->pm_save[index + 1];
+        u32 gpcon, mask;
+        mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
+        gpcon = old_gpcon & ~mask;
+        gpcon |= gps_gpcon & mask;
+        __raw_writel(gpcon, con);
+}
+static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
+{
+        void __iomem *base = chip->base;
+        u32 old_gpcon[2];
+        u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+        u32 gps_gpdat = chip->pm_save[2];
+        /* First, modify the CON settings */
+        old_gpcon[0] = 0;
+        old_gpcon[1] = __raw_readl(base + OFFS_CON);
+        s3c_gpio_pm_4bit_con(chip, 0);
+        if (chip->chip.ngpio > 8) {
+                old_gpcon[0] = __raw_readl(base - 4);
+                s3c_gpio_pm_4bit_con(chip, -1);
+        }
+        /* Now change the configurations that require DAT,CON */
+        __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+        __raw_writel(chip->pm_save[1], base + OFFS_CON);
+        if (chip->chip.ngpio > 8)
+                __raw_writel(chip->pm_save[0], base - 4);
+        __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+        __raw_writel(chip->pm_save[3], base + OFFS_UP);
+        if (chip->chip.ngpio > 8) {
+                S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
+                          chip->chip.label, old_gpcon[0], old_gpcon[1],
+                          __raw_readl(base - 4),
+                          __raw_readl(base + OFFS_CON),
+                          old_gpdat, gps_gpdat);
+        } else
+                S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
+                          chip->chip.label, old_gpcon[1],
+                          __raw_readl(base + OFFS_CON),
+                          old_gpdat, gps_gpdat);
+}
+struct s3c_gpio_pm s3c_gpio_pm_4bit = {
+        .save   = s3c_gpio_pm_4bit_save,
+        .resume = s3c_gpio_pm_4bit_resume,
+};
+#endif /* CONFIG_ARCH_S3C64XX */
+/**
+ * s3c_pm_save_gpio() - save gpio chip data for suspend
+ * @ourchip: The chip for suspend.
+ */
+static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
+{
+        struct s3c_gpio_pm *pm = ourchip->pm;
+        if (pm == NULL || pm->save == NULL)
+                S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+        else
+                pm->save(ourchip);
+}
+/**
+ * s3c_pm_save_gpios() - Save the state of the GPIO banks.
+ *
+ * For all the GPIO banks, save the state of each one ready for going
+ * into a suspend mode.
+ */
+void s3c_pm_save_gpios(void)
+{
+        struct s3c_gpio_chip *ourchip;
+        unsigned int gpio_nr;
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                if (!ourchip)
+                        continue;
+                s3c_pm_save_gpio(ourchip);
+                S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
+                          ourchip->chip.label,
+                          ourchip->pm_save[0],
+                          ourchip->pm_save[1],
+                          ourchip->pm_save[2],
+                          ourchip->pm_save[3]);
+                gpio_nr += ourchip->chip.ngpio;
+                gpio_nr += CONFIG_S3C_GPIO_SPACE;
+        }
+}
+/**
+ * s3c_pm_resume_gpio() - restore gpio chip data after suspend
+ * @ourchip: The suspended chip.
+ */
+static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
+{
+        struct s3c_gpio_pm *pm = ourchip->pm;
+        if (pm == NULL || pm->resume == NULL)
+                S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+        else
+                pm->resume(ourchip);
+}
+void s3c_pm_restore_gpios(void)
+{
+        struct s3c_gpio_chip *ourchip;
+        unsigned int gpio_nr;
+        for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                if (!ourchip)
+                        continue;
+                s3c_pm_resume_gpio(ourchip);
+                gpio_nr += ourchip->chip.ngpio;
+                gpio_nr += CONFIG_S3C_GPIO_SPACE;
+        }
+}
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c
index 061182ca66e3..8d97db2c7a0d 100644
--- a/arch/arm/plat-s3c/pm.c
+++ b/arch/arm/plat-s3c/pm.c
@@ -21,11 +21,10 @@
 #include <asm/cacheflush.h>
 #include <mach/hardware.h>
+#include <mach/map.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-mem.h>
 #include <mach/regs-irq.h>
 #include <asm/irq.h>
@@ -70,6 +69,8 @@ static inline void s3c_pm_debug_init(void)
 /* Save the UART configurations if we are configured for debug. */
+unsigned char pm_uart_udivslot;
 #ifdef CONFIG_S3C2410_PM_DEBUG
 struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
@@ -83,6 +84,12 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
        save->ufcon = __raw_readl(regs + S3C2410_UFCON);
        save->umcon = __raw_readl(regs + S3C2410_UMCON);
        save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+        if (pm_uart_udivslot)
+                save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+        S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
+                  uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
 }
 static void s3c_pm_save_uarts(void)
@@ -98,11 +105,16 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
 {
        void __iomem *regs = S3C_VA_UARTx(uart);
+        s3c_pm_arch_update_uart(regs, save);
        __raw_writel(save->ulcon, regs + S3C2410_ULCON);
        __raw_writel(save->ucon,  regs + S3C2410_UCON);
        __raw_writel(save->ufcon, regs + S3C2410_UFCON);
        __raw_writel(save->umcon, regs + S3C2410_UMCON);
        __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+        if (pm_uart_udivslot)
+                __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
 }
 static void s3c_pm_restore_uarts(void)
@@ -313,6 +325,9 @@ static int s3c_pm_enter(suspend_state_t state)
        S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
+        /* LEDs should now be 1110 */
+        s3c_pm_debug_smdkled(1 << 1, 0);
        s3c_pm_check_restore();
        /* ok, let's return from sleep */
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 2c8a2f5d75ff..5b0bc914f58e 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -71,6 +71,7 @@ config PM_SIMTEC
 config S3C2410_DMA
        bool "S3C2410 DMA support"
        depends on ARCH_S3C2410
+        select S3C_DMA
        help
          S3C2410 DMA support. This is needed for drivers like sound which
          use the S3C2410's DMA system to move data to and from the
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
index 91adfa71c172..ee1baf11ad9e 100644
--- a/arch/arm/plat-s3c24xx/adc.c
+++ b/arch/arm/plat-s3c24xx/adc.c
@@ -45,7 +45,8 @@ struct s3c_adc_client {
        unsigned char            channel;
        void    (*select_cb)(unsigned selected);
-        void    (*convert_cb)(unsigned val1, unsigned val2);
+        void    (*convert_cb)(unsigned val1, unsigned val2,
+                              unsigned *samples_left);
 };
 struct adc_device {
@@ -158,7 +159,8 @@ static void s3c_adc_default_select(unsigned select)
 struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
                                        void (*select)(unsigned int selected),
-                                        void (*conv)(unsigned d0, unsigned d1),
+                                        void (*conv)(unsigned d0, unsigned d1,
+                                                     unsigned *samples_left),
                                        unsigned int is_ts)
 {
        struct s3c_adc_client *client;
@@ -227,9 +229,10 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
        data1 = readl(adc->regs + S3C2410_ADCDAT1);
        adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
-        (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff);
+        client->nr_samples--;
+        (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
-        if (--client->nr_samples > 0) {
+        if (client->nr_samples > 0) {
                /* fire another conversion for this */
                client->select_cb(1);
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 1a8347cec20a..aa119863c5ce 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -18,6 +18,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/sysdev.h>
 #include <linux/platform_device.h>
@@ -47,27 +48,27 @@
 /* LED devices */
 static struct s3c24xx_led_platdata smdk_pdata_led4 = {
-        .gpio           = S3C2410_GPF4,
+        .gpio           = S3C2410_GPF(4),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .name           = "led4",
        .def_trigger    = "timer",
 };
 static struct s3c24xx_led_platdata smdk_pdata_led5 = {
-        .gpio           = S3C2410_GPF5,
+        .gpio           = S3C2410_GPF(5),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .name           = "led5",
        .def_trigger    = "nand-disk",
 };
 static struct s3c24xx_led_platdata smdk_pdata_led6 = {
-        .gpio           = S3C2410_GPF6,
+        .gpio           = S3C2410_GPF(6),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .name           = "led6",
 };
 static struct s3c24xx_led_platdata smdk_pdata_led7 = {
-        .gpio           = S3C2410_GPF7,
+        .gpio           = S3C2410_GPF(7),
        .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
        .name           = "led7",
 };
@@ -184,15 +185,15 @@ void __init smdk_machine_init(void)
 {
        /* Configure the LEDs (even if we have no LED support)*/
-        s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP);
+        s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPF4, 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF5, 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF6, 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF7, 1);
+        s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
        if (machine_is_smdk2443())
                smdk_nand_info.twrph0 = 50;
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 16ac01d9b8ab..4eb378c89a39 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -136,36 +136,6 @@ struct platform_device *s3c24xx_uart_src[4] = {
 struct platform_device *s3c24xx_uart_devs[4] = {
 };
-/* USB Host Controller */
-static struct resource s3c_usb_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_USBHOST,
-                .end   = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_USBH,
-                .end   = IRQ_USBH,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-static u64 s3c_device_usb_dmamask = 0xffffffffUL;
-struct platform_device s3c_device_usb = {
-        .name             = "s3c2410-ohci",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s3c_usb_resource),
-        .resource         = s3c_usb_resource,
-        .dev              = {
-                .dma_mask = &s3c_device_usb_dmamask,
-                .coherent_dma_mask = 0xffffffffUL
-        }
-};
-EXPORT_SYMBOL(s3c_device_usb);
 /* LCD Controller */
 static struct resource s3c_lcd_resource[] = {
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 07326f632361..196b19123653 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -31,10 +31,10 @@
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
 #include <mach/map.h>
-#include <plat/dma.h>
+#include <plat/dma-plat.h>
+#include <plat/regs-dma.h>
 /* io map for dma */
 static void __iomem *dma_base;
@@ -44,8 +44,6 @@ static int dma_channels;
 static struct s3c24xx_dma_selection dma_sel;
-/* dma channel state information */
-struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
 /* debugging functions */
@@ -135,21 +133,6 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
 #define dbg_showchan(chan) do { } while(0)
 #endif /* CONFIG_S3C2410_DMA_DEBUG */
-static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
-/* lookup_dma_channel
- *
- * change the dma channel number given into a real dma channel id
-*/
-static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
-{
-        if (channel & DMACH_LOW_LEVEL)
-                return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
-        else
-                return dma_chan_map[channel];
-}
 /* s3c2410_dma_stats_timeout
 *
 * Update DMA stats from timeout info
@@ -214,8 +197,6 @@ s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
        return 0;
 }
 /* s3c2410_dma_loadbuffer
 *
 * load a buffer, and update the channel state
@@ -453,7 +434,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
 int s3c2410_dma_enqueue(unsigned int channel, void *id,
                        dma_addr_t data, int size)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
        struct s3c2410_dma_buf *buf;
        unsigned long flags;
@@ -804,7 +785,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
 int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
        unsigned long flags;
        if (chan == NULL)
@@ -836,7 +817,7 @@ int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
        chan->irq_claimed = 0;
        if (!(channel & DMACH_LOW_LEVEL))
-                dma_chan_map[channel] = NULL;
+                s3c_dma_chan_map[channel] = NULL;
        local_irq_restore(flags);
@@ -995,7 +976,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
 int
 s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
        if (chan == NULL)
                return -EINVAL;
@@ -1038,14 +1019,13 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
 /* s3c2410_dma_config
 *
 * xfersize:     size of unit in bytes (1,2,4)
- * dcon:         base value of the DCONx register
 */
 int s3c2410_dma_config(unsigned int channel,
-                       int xferunit,
+                       int xferunit)
-                       int dcon)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned int dcon;
        pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
                 __func__, channel, xferunit, dcon);
@@ -1055,10 +1035,33 @@ int s3c2410_dma_config(unsigned int channel,
        pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
-        dcon |= chan->dcon & dma_sel.dcon_mask;
+        dcon = chan->dcon & dma_sel.dcon_mask;
        pr_debug("%s: New dcon is %08x\n", __func__, dcon);
+        switch (chan->req_ch) {
+        case DMACH_I2S_IN:
+        case DMACH_I2S_OUT:
+        case DMACH_PCM_IN:
+        case DMACH_PCM_OUT:
+        case DMACH_MIC_IN:
+        default:
+                dcon |= S3C2410_DCON_HANDSHAKE;
+                dcon |= S3C2410_DCON_SYNC_PCLK;
+                break;
+        case DMACH_SDI:
+                /* note, ensure if need HANDSHAKE or not */
+                dcon |= S3C2410_DCON_SYNC_PCLK;
+                break;
+        case DMACH_XD0:
+        case DMACH_XD1:
+                dcon |= S3C2410_DCON_HANDSHAKE;
+                dcon |= S3C2410_DCON_SYNC_HCLK;
+                break;
+        }
        switch (xferunit) {
        case 1:
                dcon |= S3C2410_DCON_BYTE;
@@ -1090,58 +1093,6 @@ int s3c2410_dma_config(unsigned int channel,
 EXPORT_SYMBOL(s3c2410_dma_config);
-int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
-{
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
-        if (chan == NULL)
-                return -EINVAL;
-        pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
-        chan->flags = flags;
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_setflags);
-/* do we need to protect the settings of the fields from
- * irq?
-*/
-int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
-{
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
-        if (chan == NULL)
-                return -EINVAL;
-        pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
-        chan->op_fn = rtn;
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_set_opfn);
-int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
-{
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
-        if (chan == NULL)
-                return -EINVAL;
-        pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
-        chan->callback_fn = rtn;
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
 /* s3c2410_dma_devconfig
 *
@@ -1150,29 +1101,38 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
 * source:    S3C2410_DMASRC_HW: source is hardware
 *            S3C2410_DMASRC_MEM: source is memory
 *
- * hwcfg:     the value for xxxSTCn register,
- *            bit 0: 0=increment pointer, 1=leave pointer
- *            bit 1: 0=source is AHB, 1=source is APB
- *
 * devaddr:   physical address of the source
 */
 int s3c2410_dma_devconfig(int channel,
                          enum s3c2410_dmasrc source,
-                          int hwcfg,
                          unsigned long devaddr)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned int hwcfg;
        if (chan == NULL)
                return -EINVAL;
-        pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
+        pr_debug("%s: source=%d, devaddr=%08lx\n",
-                 __func__, (int)source, hwcfg, devaddr);
+                 __func__, (int)source, devaddr);
        chan->source = source;
        chan->dev_addr = devaddr;
-        chan->hw_cfg = hwcfg;
+        switch (chan->req_ch) {
+        case DMACH_XD0:
+        case DMACH_XD1:
+                hwcfg = 0; /* AHB */
+                break;
+        default:
+                hwcfg = S3C2410_DISRCC_APB;
+        }
+        /* always assume our peripheral desintation is a fixed
+         * address in memory. */
+         hwcfg |= S3C2410_DISRCC_INC;
        switch (source) {
        case S3C2410_DMASRC_HW:
@@ -1219,7 +1179,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
 int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
 {
-        struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
        if (chan == NULL)
                return -EINVAL;
@@ -1278,8 +1238,8 @@ static int s3c2410_dma_resume(struct sys_device *dev)
        printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
-        s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
+        s3c2410_dma_config(no, cp->xfer_unit);
-        s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
+        s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
        /* re-select the dma source for this channel */
@@ -1476,7 +1436,8 @@ static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
 found:
        dmach = &s3c2410_chans[ch];
        dmach->map = ch_map;
-        dma_chan_map[channel] = dmach;
+        dmach->req_ch = channel;
+        s3c_dma_chan_map[channel] = dmach;
        /* select the channel */
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 4a899c279eb5..95df059b5a1d 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -183,35 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
 int s3c2410_gpio_getirq(unsigned int pin)
 {
-        if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
+        if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
-                return -1;      /* not valid interrupts */
+                return -EINVAL; /* not valid interrupts */
-        if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
+        if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
-                return -1;      /* not valid pin */
+                return -EINVAL; /* not valid pin */
-        if (pin < S3C2410_GPF4)
+        if (pin < S3C2410_GPF(4))
-                return (pin - S3C2410_GPF0) + IRQ_EINT0;
+                return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
-        if (pin < S3C2410_GPG0)
+        if (pin < S3C2410_GPG(0))
-                return (pin - S3C2410_GPF4) + IRQ_EINT4;
+                return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
-        return (pin - S3C2410_GPG0) + IRQ_EINT8;
+        return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
 }
 EXPORT_SYMBOL(s3c2410_gpio_getirq);
-int s3c2410_gpio_irq2pin(unsigned int irq)
-{
-        if (irq >= IRQ_EINT0 && irq <= IRQ_EINT3)
-                return S3C2410_GPF0 + (irq - IRQ_EINT0);
-        if (irq >= IRQ_EINT4 && irq <= IRQ_EINT7)
-                return S3C2410_GPF4 + (irq - IRQ_EINT4);
-        if (irq >= IRQ_EINT8 && irq <= IRQ_EINT23)
-                return S3C2410_GPG0 + (irq - IRQ_EINT8);
-        return -EINVAL;
-}
-EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 5c0491bf738b..6d7a961d3269 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/sysdev.h>
 #include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -22,6 +23,7 @@
 #include <mach/gpio-core.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <plat/pm.h>
 #include <mach/regs-gpio.h>
@@ -77,9 +79,10 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
 struct s3c_gpio_chip s3c24xx_gpios[] = {
        [0] = {
-                .base   = S3C24XX_GPIO_BASE(S3C2410_GPA0),
+                .base   = S3C2410_GPACON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
                .chip   = {
-                        .base                   = S3C2410_GPA0,
+                        .base                   = S3C2410_GPA(0),
                        .owner                  = THIS_MODULE,
                        .label                  = "GPIOA",
                        .ngpio                  = 24,
@@ -88,45 +91,50 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                },
        },
        [1] = {
-                .base   = S3C24XX_GPIO_BASE(S3C2410_GPB0),
+                .base   = S3C2410_GPBCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                .chip   = {
-                        .base                   = S3C2410_GPB0,
+                        .base                   = S3C2410_GPB(0),
                        .owner                  = THIS_MODULE,
                        .label                  = "GPIOB",
                        .ngpio                  = 16,
                },
        },
        [2] = {
-                .base   = S3C24XX_GPIO_BASE(S3C2410_GPC0),
+                .base   = S3C2410_GPCCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                .chip   = {
-                        .base                   = S3C2410_GPC0,
+                        .base                   = S3C2410_GPC(0),
                        .owner                  = THIS_MODULE,
                        .label                  = "GPIOC",
                        .ngpio                  = 16,
                },
        },
        [3] = {
-                .base   = S3C24XX_GPIO_BASE(S3C2410_GPD0),
+                .base   = S3C2410_GPDCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                .chip   = {
-                        .base                   = S3C2410_GPD0,
+                        .base                   = S3C2410_GPD(0),
                        .owner                  = THIS_MODULE,
                        .label                  = "GPIOD",
                        .ngpio                  = 16,
                },
        },
        [4] = {
-                .base   = S3C24XX_GPIO_BASE(S3C2410_GPE0),
+                .base   = S3C2410_GPECON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                .chip   = {
-                        .base                   = S3C2410_GPE0,
+                        .base                   = S3C2410_GPE(0),
                        .label                  = "GPIOE",
                        .owner                  = THIS_MODULE,
                        .ngpio                  = 16,
                },
        },
        [5] = {
-                .base   = S3C24XX_GPIO_BASE(S3C2410_GPF0),
+                .base   = S3C2410_GPFCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                .chip   = {
-                        .base                   = S3C2410_GPF0,
+                        .base                   = S3C2410_GPF(0),
                        .owner                  = THIS_MODULE,
                        .label                  = "GPIOF",
                        .ngpio                  = 8,
@@ -134,14 +142,24 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                },
        },
        [6] = {
-                .base   = S3C24XX_GPIO_BASE(S3C2410_GPG0),
+                .base   = S3C2410_GPGCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
                .chip   = {
-                        .base                   = S3C2410_GPG0,
+                        .base                   = S3C2410_GPG(0),
                        .owner                  = THIS_MODULE,
                        .label                  = "GPIOG",
-                        .ngpio                  = 10,
+                        .ngpio                  = 16,
                        .to_irq                 = s3c24xx_gpiolib_bankg_toirq,
                },
+        }, {
+                .base   = S3C2410_GPHCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPH(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOH",
+                        .ngpio                  = 11,
+                },
        },
 };
@@ -156,4 +174,4 @@ static __init int s3c24xx_gpiolib_init(void)
        return 0;
 }
-arch_initcall(s3c24xx_gpiolib_init);
+core_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/include/plat/dma.h b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
index c78efe316fc8..9565ead1bc9b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/dma.h
+/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
 *
 * Copyright (C) 2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
@@ -10,8 +10,10 @@
 * published by the Free Software Foundation.
 */
+#include <plat/dma-core.h>
 extern struct sysdev_class dma_sysclass;
-extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
+extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
 #define DMA_CH_VALID            (1<<31)
 #define DMA_CH_NEVER            (1<<30)
@@ -31,8 +33,8 @@ struct s3c24xx_dma_map {
        const char              *name;
        struct s3c24xx_dma_addr  hw_addr;
-        unsigned long            channels[S3C2410_DMA_CHANNELS];
+        unsigned long            channels[S3C_DMA_CHANNELS];
-        unsigned long            channels_rx[S3C2410_DMA_CHANNELS];
+        unsigned long            channels_rx[S3C_DMA_CHANNELS];
 };
 struct s3c24xx_dma_selection {
@@ -58,7 +60,7 @@ extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
 */
 struct s3c24xx_dma_order_ch {
-        unsigned int    list[S3C2410_DMA_CHANNELS];     /* list of channels */
+        unsigned int    list[S3C_DMA_CHANNELS]; /* list of channels */
        unsigned int    flags;                          /* flags */
 };
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index eed8f78e7593..c4d133436fc7 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -58,7 +58,6 @@
 #define S3C24XX_SZ_SPI          SZ_1M
 #define S3C24XX_SZ_SDI          SZ_1M
 #define S3C24XX_SZ_NAND         SZ_1M
-#define S3C24XX_SZ_USBHOST      SZ_1M
 /* GPIO ports */
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
index c75882113e04..fb45dd9adca5 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pm-core.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
@@ -57,3 +57,8 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
        s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
                                s3c_irqwake_eintmask);
 }
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                           struct pm_uart_save *save)
+{
+}
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
new file mode 100644
index 000000000000..3bc0a216df97
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -0,0 +1,145 @@
+/* arch/arm/mach-s3c2410/include/mach/dma.h
+ *
+ * Copyright (C) 2003,2004,2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C24XX DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* DMA Register definitions */
+#define S3C2410_DMA_DISRC               (0x00)
+#define S3C2410_DMA_DISRCC              (0x04)
+#define S3C2410_DMA_DIDST               (0x08)
+#define S3C2410_DMA_DIDSTC              (0x0C)
+#define S3C2410_DMA_DCON                (0x10)
+#define S3C2410_DMA_DSTAT               (0x14)
+#define S3C2410_DMA_DCSRC               (0x18)
+#define S3C2410_DMA_DCDST               (0x1C)
+#define S3C2410_DMA_DMASKTRIG           (0x20)
+#define S3C2412_DMA_DMAREQSEL           (0x24)
+#define S3C2443_DMA_DMAREQSEL           (0x24)
+#define S3C2410_DISRCC_INC              (1<<0)
+#define S3C2410_DISRCC_APB              (1<<1)
+#define S3C2410_DMASKTRIG_STOP          (1<<2)
+#define S3C2410_DMASKTRIG_ON            (1<<1)
+#define S3C2410_DMASKTRIG_SWTRIG        (1<<0)
+#define S3C2410_DCON_DEMAND             (0<<31)
+#define S3C2410_DCON_HANDSHAKE          (1<<31)
+#define S3C2410_DCON_SYNC_PCLK          (0<<30)
+#define S3C2410_DCON_SYNC_HCLK          (1<<30)
+#define S3C2410_DCON_INTREQ             (1<<29)
+#define S3C2410_DCON_CH0_XDREQ0         (0<<24)
+#define S3C2410_DCON_CH0_UART0          (1<<24)
+#define S3C2410_DCON_CH0_SDI            (2<<24)
+#define S3C2410_DCON_CH0_TIMER          (3<<24)
+#define S3C2410_DCON_CH0_USBEP1         (4<<24)
+#define S3C2410_DCON_CH1_XDREQ1         (0<<24)
+#define S3C2410_DCON_CH1_UART1          (1<<24)
+#define S3C2410_DCON_CH1_I2SSDI         (2<<24)
+#define S3C2410_DCON_CH1_SPI            (3<<24)
+#define S3C2410_DCON_CH1_USBEP2         (4<<24)
+#define S3C2410_DCON_CH2_I2SSDO         (0<<24)
+#define S3C2410_DCON_CH2_I2SSDI         (1<<24)
+#define S3C2410_DCON_CH2_SDI            (2<<24)
+#define S3C2410_DCON_CH2_TIMER          (3<<24)
+#define S3C2410_DCON_CH2_USBEP3         (4<<24)
+#define S3C2410_DCON_CH3_UART2          (0<<24)
+#define S3C2410_DCON_CH3_SDI            (1<<24)
+#define S3C2410_DCON_CH3_SPI            (2<<24)
+#define S3C2410_DCON_CH3_TIMER          (3<<24)
+#define S3C2410_DCON_CH3_USBEP4         (4<<24)
+#define S3C2410_DCON_SRCSHIFT           (24)
+#define S3C2410_DCON_SRCMASK            (7<<24)
+#define S3C2410_DCON_BYTE               (0<<20)
+#define S3C2410_DCON_HALFWORD           (1<<20)
+#define S3C2410_DCON_WORD               (2<<20)
+#define S3C2410_DCON_AUTORELOAD         (0<<22)
+#define S3C2410_DCON_NORELOAD           (1<<22)
+#define S3C2410_DCON_HWTRIG             (1<<23)
+#ifdef CONFIG_CPU_S3C2440
+#define S3C2440_DIDSTC_CHKINT           (1<<2)
+#define S3C2440_DCON_CH0_I2SSDO         (5<<24)
+#define S3C2440_DCON_CH0_PCMIN          (6<<24)
+#define S3C2440_DCON_CH1_PCMOUT         (5<<24)
+#define S3C2440_DCON_CH1_SDI            (6<<24)
+#define S3C2440_DCON_CH2_PCMIN          (5<<24)
+#define S3C2440_DCON_CH2_MICIN          (6<<24)
+#define S3C2440_DCON_CH3_MICIN          (5<<24)
+#define S3C2440_DCON_CH3_PCMOUT         (6<<24)
+#endif
+#ifdef CONFIG_CPU_S3C2412
+#define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
+#define S3C2412_DMAREQSEL_HW            (1)
+#define S3C2412_DMAREQSEL_SPI0TX        S3C2412_DMAREQSEL_SRC(0)
+#define S3C2412_DMAREQSEL_SPI0RX        S3C2412_DMAREQSEL_SRC(1)
+#define S3C2412_DMAREQSEL_SPI1TX        S3C2412_DMAREQSEL_SRC(2)
+#define S3C2412_DMAREQSEL_SPI1RX        S3C2412_DMAREQSEL_SRC(3)
+#define S3C2412_DMAREQSEL_I2STX         S3C2412_DMAREQSEL_SRC(4)
+#define S3C2412_DMAREQSEL_I2SRX         S3C2412_DMAREQSEL_SRC(5)
+#define S3C2412_DMAREQSEL_TIMER         S3C2412_DMAREQSEL_SRC(9)
+#define S3C2412_DMAREQSEL_SDI           S3C2412_DMAREQSEL_SRC(10)
+#define S3C2412_DMAREQSEL_USBEP1        S3C2412_DMAREQSEL_SRC(13)
+#define S3C2412_DMAREQSEL_USBEP2        S3C2412_DMAREQSEL_SRC(14)
+#define S3C2412_DMAREQSEL_USBEP3        S3C2412_DMAREQSEL_SRC(15)
+#define S3C2412_DMAREQSEL_USBEP4        S3C2412_DMAREQSEL_SRC(16)
+#define S3C2412_DMAREQSEL_XDREQ0        S3C2412_DMAREQSEL_SRC(17)
+#define S3C2412_DMAREQSEL_XDREQ1        S3C2412_DMAREQSEL_SRC(18)
+#define S3C2412_DMAREQSEL_UART0_0       S3C2412_DMAREQSEL_SRC(19)
+#define S3C2412_DMAREQSEL_UART0_1       S3C2412_DMAREQSEL_SRC(20)
+#define S3C2412_DMAREQSEL_UART1_0       S3C2412_DMAREQSEL_SRC(21)
+#define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
+#define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
+#define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
+#endif
+#define S3C2443_DMAREQSEL_SRC(x)        ((x)<<1)
+#define S3C2443_DMAREQSEL_HW            (1)
+#define S3C2443_DMAREQSEL_SPI0TX        S3C2443_DMAREQSEL_SRC(0)
+#define S3C2443_DMAREQSEL_SPI0RX        S3C2443_DMAREQSEL_SRC(1)
+#define S3C2443_DMAREQSEL_SPI1TX        S3C2443_DMAREQSEL_SRC(2)
+#define S3C2443_DMAREQSEL_SPI1RX        S3C2443_DMAREQSEL_SRC(3)
+#define S3C2443_DMAREQSEL_I2STX         S3C2443_DMAREQSEL_SRC(4)
+#define S3C2443_DMAREQSEL_I2SRX         S3C2443_DMAREQSEL_SRC(5)
+#define S3C2443_DMAREQSEL_TIMER         S3C2443_DMAREQSEL_SRC(9)
+#define S3C2443_DMAREQSEL_SDI           S3C2443_DMAREQSEL_SRC(10)
+#define S3C2443_DMAREQSEL_XDREQ0        S3C2443_DMAREQSEL_SRC(17)
+#define S3C2443_DMAREQSEL_XDREQ1        S3C2443_DMAREQSEL_SRC(18)
+#define S3C2443_DMAREQSEL_UART0_0       S3C2443_DMAREQSEL_SRC(19)
+#define S3C2443_DMAREQSEL_UART0_1       S3C2443_DMAREQSEL_SRC(20)
+#define S3C2443_DMAREQSEL_UART1_0       S3C2443_DMAREQSEL_SRC(21)
+#define S3C2443_DMAREQSEL_UART1_1       S3C2443_DMAREQSEL_SRC(22)
+#define S3C2443_DMAREQSEL_UART2_0       S3C2443_DMAREQSEL_SRC(23)
+#define S3C2443_DMAREQSEL_UART2_1       S3C2443_DMAREQSEL_SRC(24)
+#define S3C2443_DMAREQSEL_UART3_0       S3C2443_DMAREQSEL_SRC(25)
+#define S3C2443_DMAREQSEL_UART3_1       S3C2443_DMAREQSEL_SRC(26)
+#define S3C2443_DMAREQSEL_PCMOUT        S3C2443_DMAREQSEL_SRC(27)
+#define S3C2443_DMAREQSEL_PCMIN         S3C2443_DMAREQSEL_SRC(28)
+#define S3C2443_DMAREQSEL_MICIN         S3C2443_DMAREQSEL_SRC(29)
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 062a29339a91..56e5253ca02c 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -30,6 +30,7 @@
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
+#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
@@ -75,43 +76,10 @@ static struct sleep_save core_save[] = {
        SAVE_ITEM(S3C2410_CLKSLOW),
 };
-static struct gpio_sleep {
-        void __iomem    *base;
-        unsigned int     gpcon;
-        unsigned int     gpdat;
-        unsigned int     gpup;
-} gpio_save[] = {
-        [0] = {
-                .base   = S3C2410_GPACON,
-        },
-        [1] = {
-                .base   = S3C2410_GPBCON,
-        },
-        [2] = {
-                .base   = S3C2410_GPCCON,
-        },
-        [3] = {
-                .base   = S3C2410_GPDCON,
-        },
-        [4] = {
-                .base   = S3C2410_GPECON,
-        },
-        [5] = {
-                .base   = S3C2410_GPFCON,
-        },
-        [6] = {
-                .base   = S3C2410_GPGCON,
-        },
-        [7] = {
-                .base   = S3C2410_GPHCON,
-        },
-};
 static struct sleep_save misc_save[] = {
        SAVE_ITEM(S3C2410_DCLKCON),
 };
 /* s3c_pm_check_resume_pin
 *
 * check to see if the pin is configured correctly for sleep mode, and
@@ -156,195 +124,15 @@ void s3c_pm_configure_extint(void)
         * and then configure it as an input if it is not
        */
-        for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
+        for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
-                s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
+                s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
-        }
-        for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
-                s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
        }
-}
-/* offsets for CON/DAT/UP registers */
-#define OFFS_CON        (S3C2410_GPACON - S3C2410_GPACON)
-#define OFFS_DAT        (S3C2410_GPADAT - S3C2410_GPACON)
-#define OFFS_UP         (S3C2410_GPBUP  - S3C2410_GPBCON)
-/* s3c_pm_save_gpios()
- *
- * Save the state of the GPIOs
- */
-void s3c_pm_save_gpios(void)
-{
-        struct gpio_sleep *gps = gpio_save;
-        unsigned int gpio;
-        for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
-                void __iomem *base = gps->base;
-                gps->gpcon = __raw_readl(base + OFFS_CON);
-                gps->gpdat = __raw_readl(base + OFFS_DAT);
-                if (gpio > 0)
-                        gps->gpup = __raw_readl(base + OFFS_UP);
+        for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
+                s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
        }
 }
-/* Test whether the given masked+shifted bits of an GPIO configuration
- * are one of the SFN (special function) modes. */
-static inline int is_sfn(unsigned long con)
-{
-        return (con == 2 || con == 3);
-}
-/* Test if the given masked+shifted GPIO configuration is an input */
-static inline int is_in(unsigned long con)
-{
-        return con == 0;
-}
-/* Test if the given masked+shifted GPIO configuration is an output */
-static inline int is_out(unsigned long con)
-{
-        return con == 1;
-}
-/**
- * s3c2410_pm_restore_gpio() - restore the given GPIO bank
- * @index: The number of the GPIO bank being resumed.
- * @gps: The sleep confgiuration for the bank.
- *
- * Restore one of the GPIO banks that was saved during suspend. This is
- * not as simple as once thought, due to the possibility of glitches
- * from the order that the CON and DAT registers are set in.
- *
- * The three states the pin can be are {IN,OUT,SFN} which gives us 9
- * combinations of changes to check. Three of these, if the pin stays
- * in the same configuration can be discounted. This leaves us with
- * the following:
- *
- * { IN => OUT }  Change DAT first
- * { IN => SFN }  Change CON first
- * { OUT => SFN } Change CON first, so new data will not glitch
- * { OUT => IN }  Change CON first, so new data will not glitch
- * { SFN => IN }  Change CON first
- * { SFN => OUT } Change DAT first, so new data will not glitch [1]
- *
- * We do not currently deal with the UP registers as these control
- * weak resistors, so a small delay in change should not need to bring
- * these into the calculations.
- *
- * [1] this assumes that writing to a pin DAT whilst in SFN will set the
- *     state for when it is next output.
- */
-static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
-{
-        void __iomem *base = gps->base;
-        unsigned long gps_gpcon = gps->gpcon;
-        unsigned long gps_gpdat = gps->gpdat;
-        unsigned long old_gpcon;
-        unsigned long old_gpdat;
-        unsigned long old_gpup = 0x0;
-        unsigned long gpcon;
-        int nr;
-        old_gpcon = __raw_readl(base + OFFS_CON);
-        old_gpdat = __raw_readl(base + OFFS_DAT);
-        if (base == S3C2410_GPACON) {
-                /* GPACON only has one bit per control / data and no PULLUPs.
-                 * GPACON[x] = 0 => Output, 1 => SFN */
-                /* first set all SFN bits to SFN */
-                gpcon = old_gpcon | gps->gpcon;
-                __raw_writel(gpcon, base + OFFS_CON);
-                /* now set all the other bits */
-                __raw_writel(gps_gpdat, base + OFFS_DAT);
-                __raw_writel(gps_gpcon, base + OFFS_CON);
-        } else {
-                unsigned long old, new, mask;
-                unsigned long change_mask = 0x0;
-                old_gpup = __raw_readl(base + OFFS_UP);
-                /* Create a change_mask of all the items that need to have
-                 * their CON value changed before their DAT value, so that
-                 * we minimise the work between the two settings.
-                 */
-                for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
-                        old = (old_gpcon & mask) >> nr;
-                        new = (gps_gpcon & mask) >> nr;
-                        /* If there is no change, then skip */
-                        if (old == new)
-                                continue;
-                        /* If both are special function, then skip */
-                        if (is_sfn(old) && is_sfn(new))
-                                continue;
-                        /* Change is IN => OUT, do not change now */
-                        if (is_in(old) && is_out(new))
-                                continue;
-                        /* Change is SFN => OUT, do not change now */
-                        if (is_sfn(old) && is_out(new))
-                                continue;
-                        /* We should now be at the case of IN=>SFN,
-                         * OUT=>SFN, OUT=>IN, SFN=>IN. */
-                        change_mask |= mask;
-                }
-                /* Write the new CON settings */
-                gpcon = old_gpcon & ~change_mask;
-                gpcon |= gps_gpcon & change_mask;
-                __raw_writel(gpcon, base + OFFS_CON);
-                /* Now change any items that require DAT,CON */
-                __raw_writel(gps_gpdat, base + OFFS_DAT);
-                __raw_writel(gps_gpcon, base + OFFS_CON);
-                __raw_writel(gps->gpup, base + OFFS_UP);
-        }
-        S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
-                  index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
-}
-/** s3c2410_pm_restore_gpios()
- *
- * Restore the state of the GPIOs
- */
-void s3c_pm_restore_gpios(void)
-{
-        struct gpio_sleep *gps = gpio_save;
-        int gpio;
-        for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
-                s3c2410_pm_restore_gpio(gpio, gps);
-        }
-}
 void s3c_pm_restore_core(void)
 {
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index d62b7e7fb355..71a6accf114e 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -11,6 +11,7 @@
 */
 #include <linux/kernel.h>
+#include <linux/gpio.h>
 struct platform_device;
@@ -20,6 +21,6 @@ struct platform_device;
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
+        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
-        s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
+        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index 8b403cbb53d2..9edf7894eedd 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
                                          int enable)
 {
        if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
-                s3c2410_gpio_pullup(S3C2410_GPE11, 0);
+                s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
-                s3c2410_gpio_pullup(S3C2410_GPE13, 0);
+                s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
        } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPE11, 1);
+                s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
-                s3c2410_gpio_pullup(S3C2410_GPE12, 1);
+                s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
-                s3c2410_gpio_pullup(S3C2410_GPE13, 1);
+                s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
        }
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 8fccd4e549f0..f34d0fc69ad8 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
                                       int enable)
 {
        if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
-                s3c2410_gpio_pullup(S3C2410_GPG5, 0);
+                s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
-                s3c2410_gpio_pullup(S3C2410_GPG6, 0);
+                s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
        } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPG5, 1);
+                s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
-                s3c2410_gpio_pullup(S3C2410_GPG6, 1);
+                s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
-                s3c2410_gpio_pullup(S3C2410_GPG7, 1);
+                s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
        }
 }
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index 54375a00a7d2..5ebd8b425a54 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -19,6 +19,7 @@ config PLAT_S3C64XX
        select S3C_GPIO_PULL_UPDOWN
        select S3C_GPIO_CFG_S3C24XX
        select S3C_GPIO_CFG_S3C64XX
+        select USB_ARCH_HAS_OHCI
        help
          Base platform code for any Samsung S3C64XX device
@@ -38,6 +39,10 @@ config CPU_S3C6400_CLOCK
          Common clock support code for the S3C6400 that is shared
          by other CPUs in the series, such as the S3C6410.
+config S3C64XX_DMA
+        bool "S3C64XX DMA"
+        select S3C_DMA
 # platform specific device setup
 config S3C64XX_SETUP_I2C0
@@ -59,4 +64,9 @@ config S3C64XX_SETUP_FB_24BPP
        help
          Common setup code for S3C64XX with an 24bpp RGB display helper.
+config S3C64XX_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for S3C64XX SDHCI GPIO configurations
 endif
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 2e6d79bf8f33..2ed5df34f9ea 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -24,8 +24,19 @@ obj-y				+= gpiolib.o
 obj-$(CONFIG_CPU_S3C6400_INIT)  += s3c6400-init.o
 obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
+# PM support
+obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM)                += sleep.o
+obj-$(CONFIG_PM)                += irq-pm.o
+# DMA support
+obj-$(CONFIG_S3C64XX_DMA)       += dma.o
 # Device setup
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
+obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+\ No newline at end of file
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index ad1b9682c9c3..0bc2fa1dfc40 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -27,6 +27,12 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
+struct clk clk_h2 = {
+        .name           = "hclk2",
+        .id             = -1,
+        .rate           = 0,
+};
 struct clk clk_27m = {
        .name           = "clk_27m",
        .id             = -1,
@@ -152,6 +158,18 @@ static struct clk init_clocks_disable[] = {
                .parent         = &clk_48m,
                .enable         = s3c64xx_sclk_ctrl,
                .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
+        }, {
+                .name           = "dma0",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_DMA0,
+        }, {
+                .name           = "dma1",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
        },
 };
@@ -246,6 +264,7 @@ static struct clk *clks[] __initdata = {
        &clk_epll,
        &clk_27m,
        &clk_48m,
+        &clk_h2,
 };
 void __init s3c64xx_register_clocks(void)
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index 91f49a3a665d..b1fdd83940a6 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -101,9 +102,24 @@ static struct map_desc s3c_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
        },
 };
+struct sysdev_class s3c64xx_sysclass = {
+        .name   = "s3c64xx-core",
+};
+static struct sys_device s3c64xx_sysdev = {
+        .cls    = &s3c64xx_sysclass,
+};
 /* read cpu identification code */
 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
@@ -115,5 +131,21 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
        iotable_init(mach_desc, size);
        idcode = __raw_readl(S3C_VA_SYS + 0x118);
+        if (!idcode) {
+                /* S3C6400 has the ID register in a different place,
+                 * and needs a write before it can be read. */
+                __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
+                idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
+        }
        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
+static __init int s3c64xx_sysdev_init(void)
+{
+        sysdev_class_register(&s3c64xx_sysclass);
+        return sysdev_register(&s3c64xx_sysdev);
+}
+core_initcall(s3c64xx_sysdev_init);
diff --git a/arch/arm/plat-s3c64xx/dma.c b/arch/arm/plat-s3c64xx/dma.c
new file mode 100644
index 000000000000..67aa93dbb69e
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dma.c
@@ -0,0 +1,722 @@
+/* linux/arch/arm/plat-s3c64xx/dma.c
+ *
+ * Copyright 2009 Openmoko, Inc.
+ * Copyright 2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX DMA core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/dmapool.h>
+#include <linux/sysdev.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <mach/dma.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <plat/dma-plat.h>
+#include <plat/regs-sys.h>
+#include <asm/hardware/pl080.h>
+/* dma channel state information */
+struct s3c64xx_dmac {
+        struct sys_device        sysdev;
+        struct clk              *clk;
+        void __iomem            *regs;
+        struct s3c2410_dma_chan *channels;
+        enum dma_ch              chanbase;
+};
+/* pool to provide LLI buffers */
+static struct dma_pool *dma_pool;
+/* Debug configuration and code */
+static unsigned char debug_show_buffs = 0;
+static void dbg_showchan(struct s3c2410_dma_chan *chan)
+{
+        pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
+                 chan->number,
+                 readl(chan->regs + PL080_CH_SRC_ADDR),
+                 readl(chan->regs + PL080_CH_DST_ADDR),
+                 readl(chan->regs + PL080_CH_LLI),
+                 readl(chan->regs + PL080_CH_CONTROL),
+                 readl(chan->regs + PL080S_CH_CONTROL2),
+                 readl(chan->regs + PL080S_CH_CONFIG));
+}
+static void show_lli(struct pl080s_lli *lli)
+{
+        pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
+                 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
+                 lli->control0, lli->control1);
+}
+static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
+{
+        struct s3c64xx_dma_buff *ptr;
+        struct s3c64xx_dma_buff *end;
+        pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
+                 chan->number, chan->next, chan->curr, chan->end);
+        ptr = chan->next;
+        end = chan->end;
+        if (debug_show_buffs) {
+                for (; ptr != NULL; ptr = ptr->next) {
+                        pr_debug("DMA%d: %08x ",
+                                 chan->number, ptr->lli_dma);
+                        show_lli(ptr->lli);
+                }
+        }
+}
+/* End of Debug */
+static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
+{
+        struct s3c2410_dma_chan *chan;
+        unsigned int start, offs;
+        start = 0;
+        if (channel >= DMACH_PCM1_TX)
+                start = 8;
+        for (offs = 0; offs < 8; offs++) {
+                chan = &s3c2410_chans[start + offs];
+                if (!chan->in_use)
+                        goto found;
+        }
+        return NULL;
+found:
+        s3c_dma_chan_map[channel] = chan;
+        return chan;
+}
+int s3c2410_dma_config(unsigned int channel, int xferunit)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        if (chan == NULL)
+                return -EINVAL;
+        switch (xferunit) {
+        case 1:
+                chan->hw_width = 0;
+                break;
+        case 2:
+                chan->hw_width = 1;
+                break;
+        case 4:
+                chan->hw_width = 2;
+                break;
+        default:
+                printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
+                return -EINVAL;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_config);
+static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
+                                 struct pl080s_lli *lli,
+                                 dma_addr_t data, int size)
+{
+        dma_addr_t src, dst;
+        u32 control0, control1;
+        switch (chan->source) {
+        case S3C2410_DMASRC_HW:
+                src = chan->dev_addr;
+                dst = data;
+                control0 = PL080_CONTROL_SRC_AHB2;
+                control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
+                control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT;
+                control0 |= PL080_CONTROL_DST_INCR;
+                break;
+        case S3C2410_DMASRC_MEM:
+                src = data;
+                dst = chan->dev_addr;
+                control0 = PL080_CONTROL_DST_AHB2;
+                control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
+                control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT;
+                control0 |= PL080_CONTROL_SRC_INCR;
+                break;
+        default:
+                BUG();
+        }
+        /* note, we do not currently setup any of the burst controls */
+        control1 = size >> chan->hw_width;      /* size in no of xfers */
+        control0 |= PL080_CONTROL_PROT_SYS;     /* always in priv. mode */
+        control0 |= PL080_CONTROL_TC_IRQ_EN;    /* always fire IRQ */
+        lli->src_addr = src;
+        lli->dst_addr = dst;
+        lli->next_lli = 0;
+        lli->control0 = control0;
+        lli->control1 = control1;
+}
+static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
+                                struct pl080s_lli *lli)
+{
+        void __iomem *regs = chan->regs;
+        pr_debug("%s: LLI %p => regs\n", __func__, lli);
+        show_lli(lli);
+        writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
+        writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
+        writel(lli->next_lli, regs + PL080_CH_LLI);
+        writel(lli->control0, regs + PL080_CH_CONTROL);
+        writel(lli->control1, regs + PL080S_CH_CONTROL2);
+}
+static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
+{
+        struct s3c64xx_dmac *dmac = chan->dmac;
+        u32 config;
+        u32 bit = chan->bit;
+        dbg_showchan(chan);
+        pr_debug("%s: clearing interrupts\n", __func__);
+        /* clear interrupts */
+        writel(bit, dmac->regs + PL080_TC_CLEAR);
+        writel(bit, dmac->regs + PL080_ERR_CLEAR);
+        pr_debug("%s: starting channel\n", __func__);
+        config = readl(chan->regs + PL080S_CH_CONFIG);
+        config |= PL080_CONFIG_ENABLE;
+        pr_debug("%s: writing config %08x\n", __func__, config);
+        writel(config, chan->regs + PL080S_CH_CONFIG);
+        return 0;
+}
+static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
+{
+        u32 config;
+        int timeout;
+        pr_debug("%s: stopping channel\n", __func__);
+        dbg_showchan(chan);
+        config = readl(chan->regs + PL080S_CH_CONFIG);
+        config |= PL080_CONFIG_HALT;
+        writel(config, chan->regs + PL080S_CH_CONFIG);
+        timeout = 1000;
+        do {
+                config = readl(chan->regs + PL080S_CH_CONFIG);
+                pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
+                if (config & PL080_CONFIG_ACTIVE)
+                        udelay(10);
+                else
+                        break;
+                } while (--timeout > 0);
+        if (config & PL080_CONFIG_ACTIVE) {
+                printk(KERN_ERR "%s: channel still active\n", __func__);
+                return -EFAULT;
+        }
+        config = readl(chan->regs + PL080S_CH_CONFIG);
+        config &= ~PL080_CONFIG_ENABLE;
+        writel(config, chan->regs + PL080S_CH_CONFIG);
+        return 0;
+}
+static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
+                                         struct s3c64xx_dma_buff *buf,
+                                         enum s3c2410_dma_buffresult result)
+{
+        if (chan->callback_fn != NULL)
+                (chan->callback_fn)(chan, buf->pw, 0, result);
+}
+static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
+{
+        dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
+        kfree(buff);
+}
+static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
+{
+        struct s3c64xx_dma_buff *buff, *next;
+        u32 config;
+        dbg_showchan(chan);
+        pr_debug("%s: flushing channel\n", __func__);
+        config = readl(chan->regs + PL080S_CH_CONFIG);
+        config &= ~PL080_CONFIG_ENABLE;
+        writel(config, chan->regs + PL080S_CH_CONFIG);
+        /* dump all the buffers associated with this channel */
+        for (buff = chan->curr; buff != NULL; buff = next) {
+                next = buff->next;
+                pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
+                s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
+                s3c64xx_dma_freebuff(buff);
+        }
+        chan->curr = chan->next = chan->end = NULL;
+        return 0;
+}
+int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        WARN_ON(!chan);
+        if (!chan)
+                return -EINVAL;
+        switch (op) {
+        case S3C2410_DMAOP_START:
+                return s3c64xx_dma_start(chan);
+        case S3C2410_DMAOP_STOP:
+                return s3c64xx_dma_stop(chan);
+        case S3C2410_DMAOP_FLUSH:
+                return s3c64xx_dma_flush(chan);
+        /* belive PAUSE/RESUME are no-ops */
+        case S3C2410_DMAOP_PAUSE:
+        case S3C2410_DMAOP_RESUME:
+        case S3C2410_DMAOP_STARTED:
+        case S3C2410_DMAOP_TIMEOUT:
+                return 0;
+        }
+        return -ENOENT;
+}
+EXPORT_SYMBOL(s3c2410_dma_ctrl);
+/* s3c2410_dma_enque
+ *
+ */
+int s3c2410_dma_enqueue(unsigned int channel, void *id,
+                        dma_addr_t data, int size)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        struct s3c64xx_dma_buff *next;
+        struct s3c64xx_dma_buff *buff;
+        struct pl080s_lli *lli;
+        int ret;
+        WARN_ON(!chan);
+        if (!chan)
+                return -EINVAL;
+        buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_KERNEL);
+        if (!buff) {
+                printk(KERN_ERR "%s: no memory for buffer\n", __func__);
+                return -ENOMEM;
+        }
+        lli = dma_pool_alloc(dma_pool, GFP_KERNEL, &buff->lli_dma);
+        if (!lli) {
+                printk(KERN_ERR "%s: no memory for lli\n", __func__);
+                ret = -ENOMEM;
+                goto err_buff;
+        }
+        pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
+                 __func__, buff, data, lli, (u32)buff->lli_dma, size);
+        buff->lli = lli;
+        buff->pw = id;
+        s3c64xx_dma_fill_lli(chan, lli, data, size);
+        if ((next = chan->next) != NULL) {
+                struct s3c64xx_dma_buff *end = chan->end;
+                struct pl080s_lli *endlli = end->lli;
+                pr_debug("enquing onto channel\n");
+                end->next = buff;
+                endlli->next_lli = buff->lli_dma;
+                if (chan->flags & S3C2410_DMAF_CIRCULAR) {
+                        struct s3c64xx_dma_buff *curr = chan->curr;
+                        lli->next_lli = curr->lli_dma;
+                }
+                if (next == chan->curr) {
+                        writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
+                        chan->next = buff;
+                }
+                show_lli(endlli);
+                chan->end = buff;
+        } else {
+                pr_debug("enquing onto empty channel\n");
+                chan->curr = buff;
+                chan->next = buff;
+                chan->end = buff;
+                s3c64xx_lli_to_regs(chan, lli);
+        }
+        show_lli(lli);
+        dbg_showchan(chan);
+        dbg_showbuffs(chan);
+        return 0;
+err_buff:
+        kfree(buff);
+        return ret;
+}
+EXPORT_SYMBOL(s3c2410_dma_enqueue);
+int s3c2410_dma_devconfig(int channel,
+                          enum s3c2410_dmasrc source,
+                          unsigned long devaddr)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        u32 peripheral;
+        u32 config = 0;
+        pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
+                 __func__, channel, source, devaddr, chan);
+        WARN_ON(!chan);
+        if (!chan)
+                return -EINVAL;
+        peripheral = (chan->peripheral & 0xf);
+        chan->source = source;
+        chan->dev_addr = devaddr;
+        pr_debug("%s: peripheral %d\n", __func__, peripheral);
+        switch (source) {
+        case S3C2410_DMASRC_HW:
+                config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+                config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
+                break;
+        case S3C2410_DMASRC_MEM:
+                config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+                config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
+                break;
+        default:
+                printk(KERN_ERR "%s: bad source\n", __func__);
+                return -EINVAL;
+        }
+        /* allow TC and ERR interrupts */
+        config |= PL080_CONFIG_TC_IRQ_MASK;
+        config |= PL080_CONFIG_ERR_IRQ_MASK;
+        pr_debug("%s: config %08x\n", __func__, config);
+        writel(config, chan->regs + PL080S_CH_CONFIG);
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_devconfig);
+int s3c2410_dma_getposition(unsigned int channel,
+                            dma_addr_t *src, dma_addr_t *dst)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        WARN_ON(!chan);
+        if (!chan)
+                return -EINVAL;
+        if (src != NULL)
+                *src = readl(chan->regs + PL080_CH_SRC_ADDR);
+        if (dst != NULL)
+                *dst = readl(chan->regs + PL080_CH_DST_ADDR);
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_getposition);
+/* s3c2410_request_dma
+ *
+ * get control of an dma channel
+*/
+int s3c2410_dma_request(unsigned int channel,
+                        struct s3c2410_dma_client *client,
+                        void *dev)
+{
+        struct s3c2410_dma_chan *chan;
+        unsigned long flags;
+        pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
+                 channel, client->name, dev);
+        local_irq_save(flags);
+        chan = s3c64xx_dma_map_channel(channel);
+        if (chan == NULL) {
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+        dbg_showchan(chan);
+        chan->client = client;
+        chan->in_use = 1;
+        chan->peripheral = channel;
+        local_irq_restore(flags);
+        /* need to setup */
+        pr_debug("%s: channel initialised, %p\n", __func__, chan);
+        return chan->number | DMACH_LOW_LEVEL;
+}
+EXPORT_SYMBOL(s3c2410_dma_request);
+/* s3c2410_dma_free
+ *
+ * release the given channel back to the system, will stop and flush
+ * any outstanding transfers, and ensure the channel is ready for the
+ * next claimant.
+ *
+ * Note, although a warning is currently printed if the freeing client
+ * info is not the same as the registrant's client info, the free is still
+ * allowed to go through.
+*/
+int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
+{
+        struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
+        unsigned long flags;
+        if (chan == NULL)
+                return -EINVAL;
+        local_irq_save(flags);
+        if (chan->client != client) {
+                printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
+                       channel, chan->client, client);
+        }
+        /* sort out stopping and freeing the channel */
+        chan->client = NULL;
+        chan->in_use = 0;
+        if (!(channel & DMACH_LOW_LEVEL))
+                s3c_dma_chan_map[channel] = NULL;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(s3c2410_dma_free);
+static void s3c64xx_dma_tcirq(struct s3c64xx_dmac *dmac, int offs)
+{
+        struct s3c2410_dma_chan *chan = dmac->channels + offs;
+        /* note, we currently do not bother to work out which buffer
+         * or buffers have been completed since the last tc-irq. */
+        if (chan->callback_fn)
+                (chan->callback_fn)(chan, chan->curr->pw, 0, S3C2410_RES_OK);
+}
+static void s3c64xx_dma_errirq(struct s3c64xx_dmac *dmac, int offs)
+{
+        printk(KERN_DEBUG "%s: offs %d\n", __func__, offs);
+}
+static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
+{
+        struct s3c64xx_dmac *dmac = pw;
+        u32 tcstat, errstat;
+        u32 bit;
+        int offs;
+        tcstat = readl(dmac->regs + PL080_TC_STATUS);
+        errstat = readl(dmac->regs + PL080_ERR_STATUS);
+        for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
+                if (tcstat & bit) {
+                        writel(bit, dmac->regs + PL080_TC_CLEAR);
+                        s3c64xx_dma_tcirq(dmac, offs);
+                }
+                if (errstat & bit) {
+                        s3c64xx_dma_errirq(dmac, offs);
+                        writel(bit, dmac->regs + PL080_ERR_CLEAR);
+                }
+        }
+        return IRQ_HANDLED;
+}
+static struct sysdev_class dma_sysclass = {
+        .name           = "s3c64xx-dma",
+};
+static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
+                             int irq, unsigned int base)
+{
+        struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
+        struct s3c64xx_dmac *dmac;
+        char clkname[16];
+        void __iomem *regs;
+        void __iomem *regptr;
+        int err, ch;
+        dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
+        if (!dmac) {
+                printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
+                return -ENOMEM;
+        }
+        dmac->sysdev.id = chno / 8;
+        dmac->sysdev.cls = &dma_sysclass;
+        err = sysdev_register(&dmac->sysdev);
+        if (err) {
+                printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
+                goto err_alloc;
+        }
+        regs = ioremap(base, 0x200);
+        if (!regs) {
+                printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
+                err = -ENXIO;
+                goto err_dev;
+        }
+        snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
+        dmac->clk = clk_get(NULL, clkname);
+        if (IS_ERR(dmac->clk)) {
+                printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
+                err = PTR_ERR(dmac->clk);
+                goto err_map;
+        }
+        clk_enable(dmac->clk);
+        dmac->regs = regs;
+        dmac->chanbase = chbase;
+        dmac->channels = chptr;
+        err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
+        if (err < 0) {
+                printk(KERN_ERR "%s: failed to get irq\n", __func__);
+                goto err_clk;
+        }
+        regptr = regs + PL080_Cx_BASE(0);
+        for (ch = 0; ch < 8; ch++, chno++, chptr++) {
+                printk(KERN_INFO "%s: registering DMA %d (%p)\n",
+                       __func__, chno, regptr);
+                chptr->bit = 1 << ch;
+                chptr->number = chno;
+                chptr->dmac = dmac;
+                chptr->regs = regptr;
+                regptr += PL008_Cx_STRIDE;
+        }
+        /* for the moment, permanently enable the controller */
+        writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
+        printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
+        return 0;
+err_clk:
+        clk_disable(dmac->clk);
+        clk_put(dmac->clk);
+err_map:
+        iounmap(regs);
+err_dev:
+        sysdev_unregister(&dmac->sysdev);
+err_alloc:
+        kfree(dmac);
+        return err;
+}
+static int __init s3c64xx_dma_init(void)
+{
+        int ret;
+        printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
+        dma_pool = dma_pool_create("DMA-LLI", NULL, 32, 16, 0);
+        if (!dma_pool) {
+                printk(KERN_ERR "%s: failed to create pool\n", __func__);
+                return -ENOMEM;
+        }
+        ret = sysdev_class_register(&dma_sysclass);
+        if (ret) {
+                printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
+                return -ENOMEM;
+        }
+        /* Set all DMA configuration to be DMA, not SDMA */
+        writel(0xffffff, S3C_SYSREG(0x110));
+        /* Register standard DMA controlers */
+        s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
+        s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
+        return 0;
+}
+arch_initcall(s3c64xx_dma_init);
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index 78ee52cffc9e..da7b60ee5e67 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -385,12 +385,19 @@ static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
 {
        chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
        chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
 }
 static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
 {
        chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
        chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+}
+static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
+{
+        chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
 }
 static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
@@ -412,7 +419,8 @@ static __init int s3c64xx_gpiolib_init(void)
        s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
                            s3c64xx_gpiolib_add_4bit2);
-        s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
+        s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
+                            s3c64xx_gpiolib_add_2bit);
        return 0;
 }
diff --git a/arch/arm/plat-s3c64xx/include/plat/dma-plat.h b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
new file mode 100644
index 000000000000..0c30dd986725
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
+ *
+ * Copyright 2009 Openmoko, Inc.
+ * Copyright 2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX DMA core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
+struct s3c64xx_dma_buff;
+/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
+ * @next: Pointer to next buffer in queue or ring.
+ * @pw: Client provided identifier
+ * @lli: Pointer to hardware descriptor this buffer is associated with.
+ * @lli_dma: Hardare address of the descriptor.
+ */
+struct s3c64xx_dma_buff {
+        struct s3c64xx_dma_buff *next;
+        void                    *pw;
+        struct pl080_lli        *lli;
+        dma_addr_t               lli_dma;
+};
+struct s3c64xx_dmac;
+struct s3c2410_dma_chan {
+        unsigned char            number;      /* number of this dma channel */
+        unsigned char            in_use;      /* channel allocated */
+        unsigned char            bit;         /* bit for enable/disable/etc */
+        unsigned char            hw_width;
+        unsigned char            peripheral;
+        unsigned int             flags;
+        enum s3c2410_dmasrc      source;
+        dma_addr_t              dev_addr;
+        struct s3c2410_dma_client *client;
+        struct s3c64xx_dmac     *dmac;          /* pointer to controller */
+        void __iomem            *regs;
+        /* cdriver callbacks */
+        s3c2410_dma_cbfn_t       callback_fn;   /* buffer done callback */
+        s3c2410_dma_opfn_t       op_fn;         /* channel op callback */
+        /* buffer list and information */
+        struct s3c64xx_dma_buff *curr;          /* current dma buffer */
+        struct s3c64xx_dma_buff *next;          /* next buffer to load */
+        struct s3c64xx_dma_buff *end;           /* end of queue */
+        /* note, when channel is running in circular mode, curr is the
+         * first buffer enqueued, end is the last and curr is where the
+         * last buffer-done event is set-at. The buffers are not freed
+         * and the last buffer hardware descriptor points back to the
+         * first.
+         */
+};
+#include <plat/dma-core.h>
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
index f865bf4d709e..743a70094d04 100644
--- a/arch/arm/plat-s3c64xx/include/plat/irqs.h
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -157,6 +157,7 @@
 #define S3C_EINT(x)             ((x) + S3C_IRQ_EINT_BASE)
 #define IRQ_EINT(x)             S3C_EINT(x)
+#define IRQ_EINT_BIT(x)         ((x) - S3C_EINT(0))
 /* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
 * that they are sourced from the GPIO pins but with a different scheme for
diff --git a/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/arch/arm/plat-s3c64xx/include/plat/pm-core.h
new file mode 100644
index 000000000000..d347de3ba0dc
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h
@@ -0,0 +1,98 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <plat/regs-gpio.h>
+static inline void s3c_pm_debug_init_uart(void)
+{
+        u32 tmp = __raw_readl(S3C_PCLK_GATE);
+        /* As a note, since the S3C64XX UARTs generally have multiple
+         * clock sources, we simply enable PCLK at the moment and hope
+         * that the resume settings for the UART are suitable for the
+         * use with PCLK.
+         */
+        tmp |= S3C_CLKCON_PCLK_UART0;
+        tmp |= S3C_CLKCON_PCLK_UART1;
+        tmp |= S3C_CLKCON_PCLK_UART2;
+        tmp |= S3C_CLKCON_PCLK_UART3;
+        __raw_writel(tmp, S3C_PCLK_GATE);
+        udelay(10);
+}
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        /* VIC should have already been taken care of */
+        /* clear any pending EINT0 interrupts */
+        __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
+}
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+}
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+}
+/* make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on */
+#define s3c_irqwake_eintallow   ((1 << 28) - 1)
+#define s3c_irqwake_intallow    (0)
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                           struct pm_uart_save *save)
+{
+        u32 ucon = __raw_readl(regs + S3C2410_UCON);
+        u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+        u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+        u32 new_ucon;
+        u32 delta;
+        /* S3C64XX UART blocks only support level interrupts, so ensure that
+         * when we restore unused UART blocks we force the level interrupt
+         * settigs. */
+        save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+        /* We have a constraint on changing the clock type of the UART
+         * between UCLKx and PCLK, so ensure that when we restore UCON
+         * that the CLK field is correctly modified if the bootloader
+         * has changed anything.
+         */
+        if (ucon_clk != save_clk) {
+                new_ucon = save->ucon;
+                delta = ucon_clk ^ save_clk;
+                /* change from UCLKx => wrong PCLK,
+                 * either UCLK can be tested for by a bit-test
+                 * with UCLK0 */
+                if (ucon_clk & S3C6400_UCON_UCLK0 &&
+                    !(save_clk & S3C6400_UCON_UCLK0) &&
+                    delta & S3C6400_UCON_PCLK2) {
+                        new_ucon &= ~S3C6400_UCON_UCLK0;
+                } else if (delta == S3C6400_UCON_PCLK2) {
+                        /* as an precaution, don't change from
+                         * PCLK2 => PCLK or vice-versa */
+                        new_ucon ^= S3C6400_UCON_PCLK2;
+                }
+                S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+                          ucon, new_ucon, save->ucon);
+                save->ucon = new_ucon;
+        }
+}
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index b1082c163247..52836d41e333 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -32,6 +32,7 @@
 #define S3C_HCLK_GATE           S3C_CLKREG(0x30)
 #define S3C_PCLK_GATE           S3C_CLKREG(0x34)
 #define S3C_SCLK_GATE           S3C_CLKREG(0x38)
+#define S3C_MEM0_GATE           S3C_CLKREG(0x3C)
 /* CLKDIV0 */
 #define S3C6400_CLKDIV0_MFC_MASK        (0xf << 28)
diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
index 571eaa2e54f1..11f2e1e119b0 100644
--- a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
+++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
@@ -15,12 +15,13 @@
 /* Common init code for S3C6400 related SoCs */
 extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-extern void s3c6400_register_clocks(void);
+extern void s3c6400_register_clocks(unsigned armclk_divlimit);
 extern void s3c6400_setup_clocks(void);
 #ifdef CONFIG_CPU_S3C6400
 extern  int s3c6400_init(void);
+extern void s3c6400_init_irq(void);
 extern void s3c6400_map_io(void);
 extern void s3c6400_init_clocks(int xtal);
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index 47e5155bb13e..f81b7b818ba0 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
+#include <linux/sysdev.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
 #include <linux/io.h>
@@ -26,6 +27,7 @@
 #include <mach/map.h>
 #include <plat/cpu.h>
+#include <plat/pm.h>
 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 #define eint_irq_to_bit(irq)    (1 << eint_offset(irq))
@@ -134,6 +136,7 @@ static struct irq_chip s3c_irq_eint = {
        .mask_ack       = s3c_irq_eint_maskack,
        .ack            = s3c_irq_eint_ack,
        .set_type       = s3c_irq_eint_set_type,
+        .set_wake       = s3c_irqext_wake,
 };
 /* s3c_irq_demux_eint
diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/plat-s3c64xx/irq-pm.c
new file mode 100644
index 000000000000..ca523b5d4c17
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq-pm.c
@@ -0,0 +1,111 @@
+/* arch/arm/plat-s3c64xx/irq-pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Interrupt handling Power Management
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/serial_core.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-timer.h>
+#include <plat/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+/* We handled all the IRQ types in this code, to save having to make several
+ * small files to handle each different type separately. Having the EINT_GRP
+ * code here shouldn't be as much bloat as the IRQ table space needed when
+ * they are enabled. The added benefit is we ensure that these registers are
+ * in the same state as we suspended.
+ */
+static struct sleep_save irq_save[] = {
+        SAVE_ITEM(S3C64XX_PRIORITY),
+        SAVE_ITEM(S3C64XX_EINT0CON0),
+        SAVE_ITEM(S3C64XX_EINT0CON1),
+        SAVE_ITEM(S3C64XX_EINT0FLTCON0),
+        SAVE_ITEM(S3C64XX_EINT0FLTCON1),
+        SAVE_ITEM(S3C64XX_EINT0FLTCON2),
+        SAVE_ITEM(S3C64XX_EINT0FLTCON3),
+        SAVE_ITEM(S3C64XX_EINT0MASK),
+        SAVE_ITEM(S3C64XX_TINT_CSTAT),
+};
+static struct irq_grp_save {
+        u32     fltcon;
+        u32     con;
+        u32     mask;
+} eint_grp_save[5];
+static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
+{
+        struct irq_grp_save *grp = eint_grp_save;
+        int i;
+        S3C_PMDBG("%s: suspending IRQs\n", __func__);
+        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+                irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+                grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
+                grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
+                grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
+        }
+        return 0;
+}
+static int s3c64xx_irq_pm_resume(struct sys_device *dev)
+{
+        struct irq_grp_save *grp = eint_grp_save;
+        int i;
+        S3C_PMDBG("%s: resuming IRQs\n", __func__);
+        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+                __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+                __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
+                __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
+                __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
+        }
+        S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
+        return 0;
+}
+static struct sysdev_driver s3c64xx_irq_driver = {
+        .suspend = s3c64xx_irq_pm_suspend,
+        .resume  = s3c64xx_irq_pm_resume,
+};
+static int __init s3c64xx_irq_pm_init(void)
+{
+        return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
+}
+arch_initcall(s3c64xx_irq_pm_init);
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c
index f22edf7c2d2d..8dc5b6da9789 100644
--- a/arch/arm/plat-s3c64xx/irq.c
+++ b/arch/arm/plat-s3c64xx/irq.c
@@ -14,12 +14,14 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
+#include <linux/serial_core.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <asm/hardware/vic.h>
 #include <mach/map.h>
+#include <plat/regs-serial.h>
 #include <plat/regs-timer.h>
 #include <plat/cpu.h>
@@ -135,9 +137,6 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
 }
 /* UART interrupt registers, not worth adding to seperate include header */
-#define S3C64XX_UINTP   0x30
-#define S3C64XX_UINTSP  0x34
-#define S3C64XX_UINTM   0x38
 static void s3c_irq_uart_mask(unsigned int irq)
 {
@@ -233,8 +232,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
        /* initialise the pair of VICs */
-        vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
+        vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0);
-        vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
+        vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0);
        /* add the timer sub-irqs */
diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c
new file mode 100644
index 000000000000..07a6516a4f3c
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/pm.c
@@ -0,0 +1,175 @@
+/* linux/arch/arm/plat-s3c64xx/pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX CPU PM support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/pm.h>
+#include <plat/regs-sys.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-clock.h>
+#include <plat/regs-syscon-power.h>
+#include <plat/regs-gpio-memport.h>
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+#include <plat/gpio-bank-n.h>
+void s3c_pm_debug_smdkled(u32 set, u32 clear)
+{
+        unsigned long flags;
+        u32 reg;
+        local_irq_save(flags);
+        reg = __raw_readl(S3C64XX_GPNCON);
+        reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
+                 S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
+        reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
+               S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
+        __raw_writel(reg, S3C64XX_GPNCON);
+        reg = __raw_readl(S3C64XX_GPNDAT);
+        reg &= ~(clear << 12);
+        reg |= set << 12;
+        __raw_writel(reg, S3C64XX_GPNDAT);
+        local_irq_restore(flags);
+}
+#endif
+static struct sleep_save core_save[] = {
+        SAVE_ITEM(S3C_APLL_LOCK),
+        SAVE_ITEM(S3C_MPLL_LOCK),
+        SAVE_ITEM(S3C_EPLL_LOCK),
+        SAVE_ITEM(S3C_CLK_SRC),
+        SAVE_ITEM(S3C_CLK_DIV0),
+        SAVE_ITEM(S3C_CLK_DIV1),
+        SAVE_ITEM(S3C_CLK_DIV2),
+        SAVE_ITEM(S3C_CLK_OUT),
+        SAVE_ITEM(S3C_HCLK_GATE),
+        SAVE_ITEM(S3C_PCLK_GATE),
+        SAVE_ITEM(S3C_SCLK_GATE),
+        SAVE_ITEM(S3C_MEM0_GATE),
+        SAVE_ITEM(S3C_EPLL_CON1),
+        SAVE_ITEM(S3C_EPLL_CON0),
+        SAVE_ITEM(S3C64XX_MEM0DRVCON),
+        SAVE_ITEM(S3C64XX_MEM1DRVCON),
+#ifndef CONFIG_CPU_FREQ
+        SAVE_ITEM(S3C_APLL_CON),
+        SAVE_ITEM(S3C_MPLL_CON),
+#endif
+};
+static struct sleep_save misc_save[] = {
+        SAVE_ITEM(S3C64XX_AHB_CON0),
+        SAVE_ITEM(S3C64XX_AHB_CON1),
+        SAVE_ITEM(S3C64XX_AHB_CON2),
+        
+        SAVE_ITEM(S3C64XX_SPCON),
+        SAVE_ITEM(S3C64XX_MEM0CONSTOP),
+        SAVE_ITEM(S3C64XX_MEM1CONSTOP),
+        SAVE_ITEM(S3C64XX_MEM0CONSLP0),
+        SAVE_ITEM(S3C64XX_MEM0CONSLP1),
+        SAVE_ITEM(S3C64XX_MEM1CONSLP),
+};
+void s3c_pm_configure_extint(void)
+{
+        __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
+}
+void s3c_pm_restore_core(void)
+{
+        __raw_writel(0, S3C64XX_EINT_MASK);
+        s3c_pm_debug_smdkled(1 << 2, 0);
+        s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
+        s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
+}
+void s3c_pm_save_core(void)
+{
+        s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
+        s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
+}
+/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
+ * put the per-cpu code in here until any new cpu comes along and changes
+ * this.
+ */
+#include <plat/regs-gpio.h>
+static void s3c64xx_cpu_suspend(void)
+{
+        unsigned long tmp;
+        /* set our standby method to sleep */
+        tmp = __raw_readl(S3C64XX_PWR_CFG);
+        tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+        tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
+        __raw_writel(tmp, S3C64XX_PWR_CFG);
+        /* clear any old wakeup */
+        __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
+                     S3C64XX_WAKEUP_STAT);
+        /* set the LED state to 0110 over sleep */
+        s3c_pm_debug_smdkled(3 << 1, 0xf);
+        /* issue the standby signal into the pm unit. Note, we
+         * issue a write-buffer drain just in case */
+        tmp = 0;
+        asm("b 1f\n\t"
+            ".align 5\n\t"
+            "1:\n\t"
+            "mcr p15, 0, %0, c7, c10, 5\n\t"
+            "mcr p15, 0, %0, c7, c10, 4\n\t"
+            "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
+        /* we should never get past here */
+        panic("sleep resumed to originator?");
+}
+static void s3c64xx_pm_prepare(void)
+{
+        /* store address of resume. */
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
+        /* ensure previous wakeup state is cleared before sleeping */
+        __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
+}
+static int s3c64xx_pm_init(void)
+{
+        pm_cpu_prep = s3c64xx_pm_prepare;
+        pm_cpu_sleep = s3c64xx_cpu_suspend;
+        pm_uart_udivslot = 1;
+        return 0;
+}
+arch_initcall(s3c64xx_pm_init);
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 05b17528041e..1debc1f9f987 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -133,6 +133,65 @@ static struct clksrc_clk clk_mout_mpll = {
        .sources        = &clk_src_mpll,
 };
+static unsigned int armclk_mask;
+static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        u32 clkdiv;
+        /* divisor mask starts at bit0, so no need to shift */
+        clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
+        return rate / (clkdiv + 1);
+}
+static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
+                                                unsigned long rate)
+{
+        unsigned long parent = clk_get_rate(clk->parent);
+        u32 div;
+        if (parent < rate)
+                return rate;
+        div = (parent / rate) - 1;
+        if (div > armclk_mask)
+                div = armclk_mask;
+        return parent / (div + 1);
+}
+static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent = clk_get_rate(clk->parent);
+        u32 div;
+        u32 val;
+        if (rate < parent / (armclk_mask + 1))
+                return -EINVAL;
+        rate = clk_round_rate(clk, rate);
+        div = clk_get_rate(clk->parent) / rate;
+        val = __raw_readl(S3C_CLK_DIV0);
+        val &= armclk_mask;
+        val |= (div - 1);
+        __raw_writel(val, S3C_CLK_DIV0);
+        return 0;
+}
+static struct clk clk_arm = {
+        .name           = "armclk",
+        .id             = -1,
+        .parent         = &clk_mout_apll.clk,
+        .get_rate       = s3c64xx_clk_arm_get_rate,
+        .set_rate       = s3c64xx_clk_arm_set_rate,
+        .round_rate     = s3c64xx_clk_arm_round_rate,
+};
 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
 {
        unsigned long rate = clk_get_rate(clk->parent);
@@ -520,6 +579,33 @@ static struct clksrc_clk clk_irda = {
        .reg_divider    = S3C_CLK_DIV2,
 };
+static struct clk *clkset_camif_list[] = {
+        &clk_h2,
+};
+static struct clk_sources clkset_camif = {
+        .sources        = clkset_camif_list,
+        .nr_sources     = ARRAY_SIZE(clkset_camif_list),
+};
+static struct clksrc_clk clk_camif = {
+        .clk    = {
+                .name           = "camera",
+                .id             = -1,
+                .ctrlbit        = S3C_CLKCON_SCLK_CAM,
+                .enable         = s3c64xx_sclk_ctrl,
+                .set_parent     = s3c64xx_setparent_clksrc,
+                .get_rate       = s3c64xx_getrate_clksrc,
+                .set_rate       = s3c64xx_setrate_clksrc,
+                .round_rate     = s3c64xx_roundrate_clksrc,
+        },
+        .shift          = 0,
+        .mask           = 0,
+        .sources        = &clkset_camif,
+        .divider_shift  = S3C6400_CLKDIV0_CAM_SHIFT,
+        .reg_divider    = S3C_CLK_DIV0,
+};
 /* Clock initialisation code */
 static struct clksrc_clk *init_parents[] = {
@@ -536,6 +622,7 @@ static struct clksrc_clk *init_parents[] = {
        &clk_audio0,
        &clk_audio1,
        &clk_irda,
+        &clk_camif,
 };
 static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
@@ -608,6 +695,7 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
        clk_fout_epll.rate = epll;
        clk_fout_apll.rate = apll;
+        clk_h2.rate = hclk2;
        clk_h.rate = hclk;
        clk_p.rate = pclk;
        clk_f.rate = fclk;
@@ -635,14 +723,30 @@ static struct clk *clks[] __initdata = {
        &clk_audio0.clk,
        &clk_audio1.clk,
        &clk_irda.clk,
+        &clk_camif.clk,
+        &clk_arm,
 };
-void __init s3c6400_register_clocks(void)
+/**
+ * s3c6400_register_clocks - register clocks for s3c6400 and above
+ * @armclk_divlimit: Divisor mask for ARMCLK
+ *
+ * Register the clocks for the S3C6400 and above SoC range, such
+ * as ARMCLK and the clocks which have divider chains attached.
+ *
+ * This call does not setup the clocks, which is left to the
+ * s3c6400_setup_clocks() call which may be needed by the cpufreq
+ * or resume code to re-set the clocks if the bootloader has changed
+ * them.
+ */
+void __init s3c6400_register_clocks(unsigned armclk_divlimit)
 {
        struct clk *clkp;
        int ret;
        int ptr;
+        armclk_mask = armclk_divlimit;
        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
                clkp = clks[ptr];
                ret = s3c24xx_register_clock(clkp);
diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..5417123b0ac1
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
@@ -0,0 +1,55 @@
+/* linux/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S3C64XX_GPG(2 + width);
+        /* Set all the necessary GPG pins to special-function 0 */
+        for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
+}
+void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S3C64XX_GPH(2 + width);
+        /* Set all the necessary GPG pins to special-function 0 */
+        for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
+}
diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/plat-s3c64xx/sleep.S
new file mode 100644
index 000000000000..8e71fe90a373
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/sleep.S
@@ -0,0 +1,144 @@
+/* linux/0arch/arm/plat-s3c64xx/sleep.S
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX CPU sleep code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/map.h>
+#undef S3C64XX_VA_GPIO
+#define S3C64XX_VA_GPIO (0x0)
+#include <plat/regs-gpio.h>
+#include <plat/gpio-bank-n.h>
+#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
+        .text
+        /* s3c_cpu_save
+         *
+         * Save enough processor state to allow the restart of the pm.c
+         * code after resume.
+         *
+         * entry:
+         *      r0 = pointer to the save block
+        */
+ENTRY(s3c_cpu_save)
+        stmfd   sp!, { r4 - r12, lr }
+        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
+        mrc     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
+        mrc     p15, 0, r8, c2, c0, 2   @ Translation Table Control
+        mrc     p15, 0, r9, c1, c0, 0   @ Control register
+        mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
+        mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
+        stmia   r0, { r4 - r13 }        @ Save CP registers and SP
+        @@ save our state to ram
+        bl      s3c_pm_cb_flushcache
+        @@ call final suspend code
+        ldr     r0, =pm_cpu_sleep
+        ldr     pc, [r0]
+        
+        @@ return to the caller, after the MMU is turned on.
+        @@ restore the last bits of the stack and return.
+resume_with_mmu:
+        ldmfd   sp!, { r4 - r12, pc }   @ return, from sp from s3c_cpu_save
+        .data
+        /* the next bit is code, but it requires easy access to the
+         * s3c_sleep_save_phys data before the MMU is switched on, so
+         * we store the code that needs this variable in the .data where
+         * the value can be written to (the .text segment is RO).
+        */
+        .global s3c_sleep_save_phys
+s3c_sleep_save_phys:
+        .word   0
+        /* Sleep magic, the word before the resume entry point so that the
+         * bootloader can check for a resumeable image. */
+        .word   0x2bedf00d
+        /* s3c_cpu_reusme
+         *
+         * This is the entry point, stored by whatever method the bootloader
+         * requires to get the kernel runnign again. This code expects to be
+         * entered with no caches live and the MMU disabled. It will then
+         * restore the MMU and other basic CP registers saved and restart
+         * the kernel C code to finish the resume code.
+        */
+ENTRY(s3c_cpu_resume)
+        msr     cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+        ldr     r2, =LL_UART            /* for debug */
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+        /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
+         * as the uboot version supplied resets these to inputs during the
+         * resume checks.
+        */
+        ldr     r3, =S3C64XX_PA_GPIO
+        ldr     r0, [ r3, #S3C64XX_GPNCON ]
+        bic     r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
+                          S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
+        orr     r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
+                          S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
+        str     r0, [ r3, #S3C64XX_GPNCON ]
+        ldr     r0, [ r3, #S3C64XX_GPNDAT ]
+        bic     r0, r0, #0xf << 12                      @ GPN12..15
+        orr     r0, r0, #1 << 15                        @ GPN15
+        str     r0, [ r3, #S3C64XX_GPNDAT ]
+#endif
+        /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
+         * are thoroughly cleaned just in case the bootloader didn't do it
+         * for us. */
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        @@mcr   p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
+        @@mcr   p15, 0, r0, c7, c7, 0           @ Invalidate I + D caches
+        ldr     r0, s3c_sleep_save_phys
+        ldmia   r0, { r4 - r13 }
+        mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mcr     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
+        mcr     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
+        mcr     p15, 0, r8, c2, c0, 2   @ Translation Table Control
+        mcr     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
+        mov     r0, #0                  @ restore copro access controls
+        mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
+        mcr     p15, 0, r0, c7, c5, 4
+        ldr     r2, =resume_with_mmu
+        mcr     p15, 0, r9, c1, c0, 0           /* turn mmu back on */
+        nop
+        mov     pc, r2                          /* jump back */
+        .end
diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig
new file mode 100644
index 000000000000..2cf37c35951b
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/Kconfig
@@ -0,0 +1,37 @@
+if ARCH_STMP3XXX
+menu "Freescale STMP3xxx implementations"
+choice
+        prompt "Select STMP3xxx chip family"
+config ARCH_STMP37XX
+        bool "Freescale SMTP37xx"
+        select CPU_ARM926T
+        ---help---
+         STMP37xx refers to 3700 through 3769 chips
+config ARCH_STMP378X
+        bool "Freescale STMP378x"
+        select CPU_ARM926T
+        ---help---
+         STMP378x refers to 3780 through 3789 chips
+endchoice
+choice
+        prompt "Select STMP3xxx board type"
+config MACH_STMP37XX
+        depends on ARCH_STMP37XX
+        bool "Freescale STMP37xx development board"
+config MACH_STMP378X
+        depends on ARCH_STMP378X
+        bool "Freescale STMP378x development board"
+endchoice
+endmenu
+endif
diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile
new file mode 100644
index 000000000000..31dd518f37a5
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the linux kernel.
+#
+# Object file lists.
+obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
new file mode 100644
index 000000000000..5d2f19a09e44
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/clock.c
@@ -0,0 +1,1135 @@
+/*
+ * Clock manipulation routines for Freescale STMP37XX/STMP378X
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#define DEBUG
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/mach-types.h>
+#include <asm/clkdev.h>
+#include <mach/platform.h>
+#include <mach/regs-clkctrl.h>
+#include "clock.h"
+static DEFINE_SPINLOCK(clocks_lock);
+static struct clk osc_24M;
+static struct clk pll_clk;
+static struct clk cpu_clk;
+static struct clk hclk;
+static int propagate_rate(struct clk *);
+static inline int clk_is_busy(struct clk *clk)
+{
+        return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
+}
+static inline int clk_good(struct clk *clk)
+{
+        return clk && !IS_ERR(clk) && clk->ops;
+}
+static int std_clk_enable(struct clk *clk)
+{
+        if (clk->enable_reg) {
+                u32 clk_reg = __raw_readl(clk->enable_reg);
+                if (clk->enable_negate)
+                        clk_reg &= ~(1 << clk->enable_shift);
+                else
+                        clk_reg |= (1 << clk->enable_shift);
+                __raw_writel(clk_reg, clk->enable_reg);
+                if (clk->enable_wait)
+                        udelay(clk->enable_wait);
+                return 0;
+        } else
+                return -EINVAL;
+}
+static int std_clk_disable(struct clk *clk)
+{
+        if (clk->enable_reg) {
+                u32 clk_reg = __raw_readl(clk->enable_reg);
+                if (clk->enable_negate)
+                        clk_reg |= (1 << clk->enable_shift);
+                else
+                        clk_reg &= ~(1 << clk->enable_shift);
+                __raw_writel(clk_reg, clk->enable_reg);
+                return 0;
+        } else
+                return -EINVAL;
+}
+static int io_set_rate(struct clk *clk, u32 rate)
+{
+        u32 reg_frac, clkctrl_frac;
+        int i, ret = 0, mask = 0x1f;
+        clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
+        if (clkctrl_frac < 18 || clkctrl_frac > 35) {
+                ret = -EINVAL;
+                goto out;
+        }
+        reg_frac = __raw_readl(clk->scale_reg);
+        reg_frac &= ~(mask << clk->scale_shift);
+        __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
+                                clk->scale_reg);
+        if (clk->busy_reg) {
+                for (i = 10000; i; i--)
+                        if (!clk_is_busy(clk))
+                                break;
+                if (!i)
+                        ret = -ETIMEDOUT;
+                else
+                        ret = 0;
+        }
+out:
+        return ret;
+}
+static long io_get_rate(struct clk *clk)
+{
+        long rate = clk->parent->rate * 18;
+        int mask = 0x1f;
+        rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
+        clk->rate = rate;
+        return rate;
+}
+static long per_get_rate(struct clk *clk)
+{
+        long rate = clk->parent->rate;
+        long div;
+        const int mask = 0xff;
+        if (clk->enable_reg &&
+                        !(__raw_readl(clk->enable_reg) & clk->enable_shift))
+                clk->rate = 0;
+        else {
+                div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
+                if (div)
+                        rate /= div;
+                clk->rate = rate;
+        }
+        return clk->rate;
+}
+static int per_set_rate(struct clk *clk, u32 rate)
+{
+        int ret = -EINVAL;
+        int div = (clk->parent->rate + rate - 1) / rate;
+        u32 reg_frac;
+        const int mask = 0xff;
+        int try = 10;
+        int i = -1;
+        if (div == 0 || div > mask)
+                goto out;
+        reg_frac = __raw_readl(clk->scale_reg);
+        reg_frac &= ~(mask << clk->scale_shift);
+        while (try--) {
+                __raw_writel(reg_frac | (div << clk->scale_shift),
+                                clk->scale_reg);
+                if (clk->busy_reg) {
+                        for (i = 10000; i; i--)
+                                if (!clk_is_busy(clk))
+                                        break;
+                }
+                if (i)
+                        break;
+        }
+        if (!i)
+                ret = -ETIMEDOUT;
+        else
+                ret = 0;
+out:
+        if (ret != 0)
+                printk(KERN_ERR "%s: error %d\n", __func__, ret);
+        return ret;
+}
+static long lcdif_get_rate(struct clk *clk)
+{
+        long rate = clk->parent->rate;
+        long div;
+        const int mask = 0xff;
+        div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
+        if (div) {
+                rate /= div;
+                div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
+                        BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
+                rate /= div;
+        }
+        clk->rate = rate;
+        return rate;
+}
+static int lcdif_set_rate(struct clk *clk, u32 rate)
+{
+        int ret = 0;
+        /*
+         * On 3700, we can get most timings exact by modifying ref_pix
+         * and the divider, but keeping the phase timings at 1 (2
+         * phases per cycle).
+         *
+         * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
+         * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
+         *
+         * ns_cycle >= 2*18e3/(18*480) = 25/6
+         * ns_cycle <= 2*35e3/(18*480) = 875/108
+         *
+         * Multiply the ns_cycle by 'div' to lengthen it until it fits the
+         * bounds. This is the divider we'll use after ref_pix.
+         *
+         * 6 * ns_cycle >= 25 * div
+         * 108 * ns_cycle <= 875 * div
+         */
+        u32 ns_cycle = 1000000 / rate;
+        u32 div, reg_val;
+        u32 lowest_result = (u32) -1;
+        u32 lowest_div = 0, lowest_fracdiv = 0;
+        for (div = 1; div < 256; ++div) {
+                u32 fracdiv;
+                u32 ps_result;
+                int lower_bound = 6 * ns_cycle >= 25 * div;
+                int upper_bound = 108 * ns_cycle <= 875 * div;
+                if (!lower_bound)
+                        break;
+                if (!upper_bound)
+                        continue;
+                /*
+                 * Found a matching div. Calculate fractional divider needed,
+                 * rounded up.
+                 */
+                fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
+                                ns_cycle + 1000 * div - 1) /
+                                (1000 * div);
+                if (fracdiv < 18 || fracdiv > 35) {
+                        ret = -EINVAL;
+                        goto out;
+                }
+                /* Calculate the actual cycle time this results in */
+                ps_result = 6250 * div * fracdiv / 27;
+                /* Use the fastest result that doesn't break ns_cycle */
+                if (ps_result <= lowest_result) {
+                        lowest_result = ps_result;
+                        lowest_div = div;
+                        lowest_fracdiv = fracdiv;
+                }
+        }
+        if (div >= 256 || lowest_result == (u32) -1) {
+                ret = -EINVAL;
+                goto out;
+        }
+        pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
+                        "PIXCLK=%uMHz cycle=%u.%03uns\n",
+                        lowest_fracdiv, lowest_div,
+                        480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
+                        lowest_result / 1000, lowest_result % 1000);
+        /* Program ref_pix phase fractional divider */
+        reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
+        reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
+        reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
+        __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
+        /* Ungate PFD */
+        stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
+                        REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
+        /* Program pix divider */
+        reg_val = __raw_readl(clk->scale_reg);
+        reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
+        reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
+        __raw_writel(reg_val, clk->scale_reg);
+        /* Wait for divider update */
+        if (clk->busy_reg) {
+                int i;
+                for (i = 10000; i; i--)
+                        if (!clk_is_busy(clk))
+                                break;
+                if (!i) {
+                        ret = -ETIMEDOUT;
+                        goto out;
+                }
+        }
+        /* Switch to ref_pix source */
+        reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
+        reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
+        __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
+out:
+        return ret;
+}
+static int cpu_set_rate(struct clk *clk, u32 rate)
+{
+        u32 reg_val;
+        if (rate < 24000)
+                return -EINVAL;
+        else if (rate == 24000) {
+                /* switch to the 24M source */
+                clk_set_parent(clk, &osc_24M);
+        } else {
+                int i;
+                u32 clkctrl_cpu = 1;
+                u32 c = clkctrl_cpu;
+                u32 clkctrl_frac = 1;
+                u32 val;
+                for ( ; c < 0x40; c++) {
+                        u32 f = (pll_clk.rate*18/c + rate/2) / rate;
+                        int s1, s2;
+                        if (f < 18 || f > 35)
+                                continue;
+                        s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
+                        s2 = pll_clk.rate*18/c/f - rate;
+                        pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
+                        if (abs(s1) > abs(s2)) {
+                                clkctrl_cpu = c;
+                                clkctrl_frac = f;
+                        }
+                        if (s2 == 0)
+                                break;
+                };
+                pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
+                                clkctrl_cpu, clkctrl_frac);
+                if (c == 0x40) {
+                        int  d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
+                                rate;
+                        if (abs(d) > 100 ||
+                            clkctrl_frac < 18 || clkctrl_frac > 35)
+                                return -EINVAL;
+                }
+                /* 4.6.2 */
+                val = __raw_readl(clk->scale_reg);
+                val &= ~(0x3f << clk->scale_shift);
+                val |= clkctrl_frac;
+                clk_set_parent(clk, &osc_24M);
+                udelay(10);
+                __raw_writel(val, clk->scale_reg);
+                /* ungate */
+                __raw_writel(1<<7, clk->scale_reg + 8);
+                /* write clkctrl_cpu */
+                clk->saved_div = clkctrl_cpu;
+                reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
+                reg_val &= ~0x3F;
+                reg_val |= clkctrl_cpu;
+                __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
+                for (i = 10000; i; i--)
+                        if (!clk_is_busy(clk))
+                                break;
+                if (!i) {
+                        printk(KERN_ERR "couldn't set up CPU divisor\n");
+                        return -ETIMEDOUT;
+                }
+                clk_set_parent(clk, &pll_clk);
+                clk->saved_div = 0;
+                udelay(10);
+        }
+        return 0;
+}
+static long cpu_get_rate(struct clk *clk)
+{
+        long rate = clk->parent->rate * 18;
+        rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
+        rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
+        rate = ((rate + 9) / 10) * 10;
+        clk->rate = rate;
+        return rate;
+}
+static long cpu_round_rate(struct clk *clk, u32 rate)
+{
+        unsigned long r = 0;
+        if (rate <= 24000)
+                r = 24000;
+        else {
+                u32 clkctrl_cpu = 1;
+                u32 clkctrl_frac;
+                do {
+                        clkctrl_frac =
+                                (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
+                        if (clkctrl_frac > 35)
+                                continue;
+                        if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
+                            rate / 10)
+                                break;
+                } while (pll_clk.rate / 2  >= clkctrl_cpu++ * rate);
+                if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
+                        clkctrl_cpu--;
+                pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
+                                clkctrl_cpu, clkctrl_frac);
+                if (clkctrl_frac < 18)
+                        clkctrl_frac = 18;
+                if (clkctrl_frac > 35)
+                        clkctrl_frac = 35;
+                r = pll_clk.rate * 18;
+                r /= clkctrl_frac;
+                r /= clkctrl_cpu;
+                r = 10 * ((r + 9) / 10);
+        }
+        return r;
+}
+static long emi_get_rate(struct clk *clk)
+{
+        long rate = clk->parent->rate * 18;
+        rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
+        rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
+        clk->rate = rate;
+        return rate;
+}
+static int clkseq_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = -EINVAL;
+        int shift = 8;
+        /* bypass? */
+        if (parent == &osc_24M)
+                shift = 4;
+        if (clk->bypass_reg) {
+#ifdef CONFIG_ARCH_STMP378X
+                u32 hbus_val, cpu_val;
+                if (clk == &cpu_clk && shift == 4) {
+                        hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
+                                        HW_CLKCTRL_HBUS);
+                        cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
+                                        HW_CLKCTRL_CPU);
+                        hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
+                                      BM_CLKCTRL_HBUS_DIV);
+                        clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
+                        cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
+                        cpu_val |= 1;
+                        if (machine_is_stmp378x()) {
+                                __raw_writel(hbus_val,
+                                        REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
+                                __raw_writel(cpu_val,
+                                        REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
+                                hclk.rate = 0;
+                        }
+                } else if (clk == &cpu_clk && shift == 8) {
+                        hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
+                                                        HW_CLKCTRL_HBUS);
+                        cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
+                                                        HW_CLKCTRL_CPU);
+                        hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
+                                      BM_CLKCTRL_HBUS_DIV);
+                        hbus_val |= 2;
+                        cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
+                        if (clk->saved_div)
+                                cpu_val |= clk->saved_div;
+                        else
+                                cpu_val |= 2;
+                        if (machine_is_stmp378x()) {
+                                __raw_writel(hbus_val,
+                                        REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
+                                __raw_writel(cpu_val,
+                                        REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
+                                hclk.rate = 0;
+                        }
+                }
+#endif
+                __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
+                ret = 0;
+        }
+        return ret;
+}
+static int hbus_set_rate(struct clk *clk, u32 rate)
+{
+        u8 div = 0;
+        int is_frac = 0;
+        u32 clkctrl_hbus;
+        struct clk *parent = clk->parent;
+        pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
+                        parent->rate);
+        if (rate > parent->rate)
+                return -EINVAL;
+        if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
+            parent->rate / rate < 32) {
+                pr_debug("%s: switching to fractional mode\n", __func__);
+                is_frac = 1;
+        }
+        if (is_frac)
+                div = (32 * rate + parent->rate / 2) / parent->rate;
+        else
+                div = (parent->rate + rate - 1) / rate;
+        pr_debug("%s: div calculated is %d\n", __func__, div);
+        if (!div || div > 0x1f)
+                return -EINVAL;
+        clk_set_parent(&cpu_clk, &osc_24M);
+        udelay(10);
+        clkctrl_hbus = __raw_readl(clk->scale_reg);
+        clkctrl_hbus &= ~0x3f;
+        clkctrl_hbus |= div;
+        clkctrl_hbus |= (is_frac << 5);
+        __raw_writel(clkctrl_hbus, clk->scale_reg);
+        if (clk->busy_reg) {
+                int i;
+                for (i = 10000; i; i--)
+                        if (!clk_is_busy(clk))
+                                break;
+                if (!i) {
+                        printk(KERN_ERR "couldn't set up CPU divisor\n");
+                        return -ETIMEDOUT;
+                }
+        }
+        clk_set_parent(&cpu_clk, &pll_clk);
+        __raw_writel(clkctrl_hbus, clk->scale_reg);
+        udelay(10);
+        return 0;
+}
+static long hbus_get_rate(struct clk *clk)
+{
+        long rate = clk->parent->rate;
+        if (__raw_readl(clk->scale_reg) & 0x20) {
+                rate *= __raw_readl(clk->scale_reg) & 0x1f;
+                rate /= 32;
+        } else
+                rate /= __raw_readl(clk->scale_reg) & 0x1f;
+        clk->rate = rate;
+        return rate;
+}
+static int xbus_set_rate(struct clk *clk, u32 rate)
+{
+        u16 div = 0;
+        u32 clkctrl_xbus;
+        pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
+                        clk->parent->rate);
+        div = (clk->parent->rate + rate - 1) / rate;
+        pr_debug("%s: div calculated is %d\n", __func__, div);
+        if (!div || div > 0x3ff)
+                return -EINVAL;
+        clkctrl_xbus = __raw_readl(clk->scale_reg);
+        clkctrl_xbus &= ~0x3ff;
+        clkctrl_xbus |= div;
+        __raw_writel(clkctrl_xbus, clk->scale_reg);
+        if (clk->busy_reg) {
+                int i;
+                for (i = 10000; i; i--)
+                        if (!clk_is_busy(clk))
+                                break;
+                if (!i) {
+                        printk(KERN_ERR "couldn't set up xbus divisor\n");
+                        return -ETIMEDOUT;
+                }
+        }
+        return 0;
+}
+static long xbus_get_rate(struct clk *clk)
+{
+        long rate = clk->parent->rate;
+        rate /= __raw_readl(clk->scale_reg) & 0x3ff;
+        clk->rate = rate;
+        return rate;
+}
+/* Clock ops */
+static struct clk_ops std_ops = {
+        .enable         = std_clk_enable,
+        .disable        = std_clk_disable,
+        .get_rate       = per_get_rate,
+        .set_rate       = per_set_rate,
+        .set_parent     = clkseq_set_parent,
+};
+static struct clk_ops min_ops = {
+        .enable         = std_clk_enable,
+        .disable        = std_clk_disable,
+};
+static struct clk_ops cpu_ops = {
+        .enable         = std_clk_enable,
+        .disable        = std_clk_disable,
+        .get_rate       = cpu_get_rate,
+        .set_rate       = cpu_set_rate,
+        .round_rate     = cpu_round_rate,
+        .set_parent     = clkseq_set_parent,
+};
+static struct clk_ops io_ops = {
+        .enable         = std_clk_enable,
+        .disable        = std_clk_disable,
+        .get_rate       = io_get_rate,
+        .set_rate       = io_set_rate,
+};
+static struct clk_ops hbus_ops = {
+        .get_rate       = hbus_get_rate,
+        .set_rate       = hbus_set_rate,
+};
+static struct clk_ops xbus_ops = {
+        .get_rate       = xbus_get_rate,
+        .set_rate       = xbus_set_rate,
+};
+static struct clk_ops lcdif_ops = {
+        .enable         = std_clk_enable,
+        .disable        = std_clk_disable,
+        .get_rate       = lcdif_get_rate,
+        .set_rate       = lcdif_set_rate,
+        .set_parent     = clkseq_set_parent,
+};
+static struct clk_ops emi_ops = {
+        .get_rate       = emi_get_rate,
+};
+/* List of on-chip clocks */
+static struct clk osc_24M = {
+        .flags          = FIXED_RATE | ENABLED,
+        .rate           = 24000,
+};
+static struct clk pll_clk = {
+        .parent         = &osc_24M,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
+        .enable_shift   = 16,
+        .enable_wait    = 10,
+        .flags          = FIXED_RATE | ENABLED,
+        .rate           = 480000,
+        .ops            = &min_ops,
+};
+static struct clk cpu_clk = {
+        .parent         = &pll_clk,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
+        .scale_shift    = 0,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 7,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
+        .busy_bit       = 28,
+        .flags          = RATE_PROPAGATES | ENABLED,
+        .ops            = &cpu_ops,
+};
+static struct clk io_clk = {
+        .parent         = &pll_clk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
+        .scale_shift    = 24,
+        .flags          = RATE_PROPAGATES | ENABLED,
+        .ops            = &io_ops,
+};
+static struct clk hclk = {
+        .parent         = &cpu_clk,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 7,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
+        .busy_bit       = 29,
+        .flags          = RATE_PROPAGATES | ENABLED,
+        .ops            = &hbus_ops,
+};
+static struct clk xclk = {
+        .parent         = &osc_24M,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
+        .busy_bit       = 31,
+        .flags          = RATE_PROPAGATES | ENABLED,
+        .ops            = &xbus_ops,
+};
+static struct clk uart_clk = {
+        .parent         = &xclk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .flags          = ENABLED,
+        .ops            = &min_ops,
+};
+static struct clk audio_clk = {
+        .parent         = &xclk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
+        .enable_shift   = 30,
+        .enable_negate  = 1,
+        .ops            = &min_ops,
+};
+static struct clk pwm_clk = {
+        .parent         = &xclk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
+        .enable_shift   = 29,
+        .enable_negate  = 1,
+        .ops            = &min_ops,
+};
+static struct clk dri_clk = {
+        .parent         = &xclk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
+        .enable_shift   = 28,
+        .enable_negate  = 1,
+        .ops            = &min_ops,
+};
+static struct clk digctl_clk = {
+        .parent         = &xclk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
+        .enable_shift   = 27,
+        .enable_negate  = 1,
+        .ops            = &min_ops,
+};
+static struct clk timer_clk = {
+        .parent         = &xclk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
+        .enable_shift   = 26,
+        .enable_negate  = 1,
+        .flags          = ENABLED,
+        .ops            = &min_ops,
+};
+static struct clk lcdif_clk = {
+        .parent         = &pll_clk,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
+        .busy_bit       = 29,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 1,
+        .flags          = NEEDS_SET_PARENT,
+        .ops            = &lcdif_ops,
+};
+static struct clk ssp_clk = {
+        .parent         = &io_clk,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
+        .busy_bit       = 29,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
+        .enable_shift   = 31,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 5,
+        .enable_negate  = 1,
+        .flags          = NEEDS_SET_PARENT,
+        .ops            = &std_ops,
+};
+static struct clk gpmi_clk = {
+        .parent         = &io_clk,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
+        .busy_bit       = 29,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 4,
+        .flags          = NEEDS_SET_PARENT,
+        .ops            = &std_ops,
+};
+static struct clk spdif_clk = {
+        .parent         = &pll_clk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .ops            = &min_ops,
+};
+static struct clk emi_clk = {
+        .parent         = &pll_clk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
+        .scale_shift    = 8,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
+        .busy_bit       = 28,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 6,
+        .flags          = ENABLED,
+        .ops            = &emi_ops,
+};
+static struct clk ir_clk = {
+        .parent         = &io_clk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 3,
+        .ops            = &min_ops,
+};
+static struct clk saif_clk = {
+        .parent         = &pll_clk,
+        .scale_reg      = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
+        .busy_reg       = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
+        .busy_bit       = 29,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
+        .enable_shift   = 31,
+        .enable_negate  = 1,
+        .bypass_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
+        .bypass_shift   = 0,
+        .ops            = &std_ops,
+};
+static struct clk usb_clk = {
+        .parent         = &pll_clk,
+        .enable_reg     = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
+        .enable_shift   = 18,
+        .enable_negate  = 1,
+        .ops            = &min_ops,
+};
+/* list of all the clocks */
+static struct clk_lookup onchip_clks[] = {
+        {
+                .con_id = "osc_24M",
+                .clk = &osc_24M,
+        }, {
+                .con_id = "pll",
+                .clk = &pll_clk,
+        }, {
+                .con_id = "cpu",
+                .clk = &cpu_clk,
+        }, {
+                .con_id = "hclk",
+                .clk = &hclk,
+        }, {
+                .con_id = "xclk",
+                .clk = &xclk,
+        }, {
+                .con_id = "io",
+                .clk = &io_clk,
+        }, {
+                .con_id = "uart",
+                .clk = &uart_clk,
+        }, {
+                .con_id = "audio",
+                .clk = &audio_clk,
+        }, {
+                .con_id = "pwm",
+                .clk = &pwm_clk,
+        }, {
+                .con_id = "dri",
+                .clk = &dri_clk,
+        }, {
+                .con_id = "digctl",
+                .clk = &digctl_clk,
+        }, {
+                .con_id = "timer",
+                .clk = &timer_clk,
+        }, {
+                .con_id = "lcdif",
+                .clk = &lcdif_clk,
+        }, {
+                .con_id = "ssp",
+                .clk = &ssp_clk,
+        }, {
+                .con_id = "gpmi",
+                .clk = &gpmi_clk,
+        }, {
+                .con_id = "spdif",
+                .clk = &spdif_clk,
+        }, {
+                .con_id = "emi",
+                .clk = &emi_clk,
+        }, {
+                .con_id = "ir",
+                .clk = &ir_clk,
+        }, {
+                .con_id = "saif",
+                .clk = &saif_clk,
+        }, {
+                .con_id = "usb",
+                .clk = &usb_clk,
+        },
+};
+static int __init propagate_rate(struct clk *clk)
+{
+        struct clk_lookup *cl;
+        for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
+             cl++) {
+                if (unlikely(!clk_good(cl->clk)))
+                        continue;
+                if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
+                        cl->clk->ops->get_rate(cl->clk);
+                        if (cl->clk->flags & RATE_PROPAGATES)
+                                propagate_rate(cl->clk);
+                }
+        }
+        return 0;
+}
+/* Exported API */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (unlikely(!clk_good(clk)))
+                return 0;
+        if (clk->rate != 0)
+                return clk->rate;
+        if (clk->ops->get_rate != NULL)
+                return clk->ops->get_rate(clk);
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL(clk_get_rate);
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (unlikely(!clk_good(clk)))
+                return 0;
+        if (clk->ops->round_rate)
+                return clk->ops->round_rate(clk, rate);
+        return 0;
+}
+EXPORT_SYMBOL(clk_round_rate);
+static inline int close_enough(long rate1, long rate2)
+{
+        return rate1 && !((rate2 - rate1) * 1000 / rate1);
+}
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+        if (unlikely(!clk_good(clk)))
+                goto out;
+        if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
+                goto out;
+        else if (!close_enough(clk->rate, rate)) {
+                ret = clk->ops->set_rate(clk, rate);
+                if (ret < 0)
+                        goto out;
+                clk->rate = rate;
+                if (clk->flags & RATE_PROPAGATES)
+                        propagate_rate(clk);
+        } else
+                ret = 0;
+out:
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+int clk_enable(struct clk *clk)
+{
+        unsigned long clocks_flags;
+        if (unlikely(!clk_good(clk)))
+                return -EINVAL;
+        if (clk->parent)
+                clk_enable(clk->parent);
+        spin_lock_irqsave(&clocks_lock, clocks_flags);
+        clk->usage++;
+        if (clk->ops && clk->ops->enable)
+                clk->ops->enable(clk);
+        spin_unlock_irqrestore(&clocks_lock, clocks_flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+static void local_clk_disable(struct clk *clk)
+{
+        if (unlikely(!clk_good(clk)))
+                return;
+        if (clk->usage == 0 && clk->ops->disable)
+                clk->ops->disable(clk);
+        if (clk->parent)
+                local_clk_disable(clk->parent);
+}
+void clk_disable(struct clk *clk)
+{
+        unsigned long clocks_flags;
+        if (unlikely(!clk_good(clk)))
+                return;
+        spin_lock_irqsave(&clocks_lock, clocks_flags);
+        if ((--clk->usage) == 0 && clk->ops->disable)
+                clk->ops->disable(clk);
+        spin_unlock_irqrestore(&clocks_lock, clocks_flags);
+        if (clk->parent)
+                clk_disable(clk->parent);
+}
+EXPORT_SYMBOL(clk_disable);
+/* Some additional API */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = -ENODEV;
+        unsigned long clocks_flags;
+        if (unlikely(!clk_good(clk)))
+                goto out;
+        if (!clk->ops->set_parent)
+                goto out;
+        spin_lock_irqsave(&clocks_lock, clocks_flags);
+        ret = clk->ops->set_parent(clk, parent);
+        if (!ret) {
+                /* disable if usage count is 0 */
+                local_clk_disable(parent);
+                parent->usage += clk->usage;
+                clk->parent->usage -= clk->usage;
+                /* disable if new usage count is 0 */
+                local_clk_disable(clk->parent);
+                clk->parent = parent;
+        }
+        spin_unlock_irqrestore(&clocks_lock, clocks_flags);
+out:
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+struct clk *clk_get_parent(struct clk *clk)
+{
+        if (unlikely(!clk_good(clk)))
+                return NULL;
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+static int __init clk_init(void)
+{
+        struct clk_lookup *cl;
+        struct clk_ops *ops;
+        spin_lock_init(&clocks_lock);
+        for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
+             cl++) {
+                if (cl->clk->flags & ENABLED)
+                        clk_enable(cl->clk);
+                else
+                        local_clk_disable(cl->clk);
+                ops = cl->clk->ops;
+                if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
+                                ops && ops->set_rate)
+                        ops->set_rate(cl->clk, cl->clk->rate);
+                if (cl->clk->flags & FIXED_RATE) {
+                        if (cl->clk->flags & RATE_PROPAGATES)
+                                propagate_rate(cl->clk);
+                } else {
+                        if (ops && ops->get_rate)
+                                ops->get_rate(cl->clk);
+                }
+                if (cl->clk->flags & NEEDS_SET_PARENT) {
+                        if (ops && ops->set_parent)
+                                ops->set_parent(cl->clk, cl->clk->parent);
+                }
+                clkdev_add(cl);
+        }
+        return 0;
+}
+arch_initcall(clk_init);
diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h
new file mode 100644
index 000000000000..a6611e1a3510
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/clock.h
@@ -0,0 +1,61 @@
+/*
+ * Clock control driver for Freescale STMP37XX/STMP378X - internal header file
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
+#define __ARCH_ARM_STMX3XXX_CLOCK_H__
+#ifndef __ASSEMBLER__
+struct clk_ops {
+        int (*enable) (struct clk *);
+        int (*disable) (struct clk *);
+        long (*get_rate) (struct clk *);
+        long (*round_rate) (struct clk *, u32);
+        int (*set_rate) (struct clk *, u32);
+        int (*set_parent) (struct clk *, struct clk *);
+};
+struct clk {
+        struct clk *parent;
+        u32 rate;
+        u32 flags;
+        u8 scale_shift;
+        u8 enable_shift;
+        u8 bypass_shift;
+        u8 busy_bit;
+        s8 usage;
+        int enable_wait;
+        int enable_negate;
+        u32 saved_div;
+        void __iomem *enable_reg;
+        void __iomem *scale_reg;
+        void __iomem *bypass_reg;
+        void __iomem *busy_reg;
+        struct clk_ops *ops;
+};
+#endif /* __ASSEMBLER__ */
+/* Flags */
+#define RATE_PROPAGATES      (1<<0)
+#define NEEDS_INITIALIZATION (1<<1)
+#define PARENT_SET_RATE      (1<<2)
+#define FIXED_RATE           (1<<3)
+#define ENABLED              (1<<4)
+#define NEEDS_SET_PARENT     (1<<5)
+#endif
diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c
new file mode 100644
index 000000000000..37b8a09148a4
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/core.c
@@ -0,0 +1,128 @@
+/*
+ * Freescale STMP37XX/STMP378X core routines
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/stmp3xxx.h>
+#include <mach/platform.h>
+#include <mach/dma.h>
+#include <mach/regs-clkctrl.h>
+static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
+{
+        u32 c;
+        int timeout;
+        /* the process of software reset of IP block is done
+           in several steps:
+           - clear SFTRST and wait for block is enabled;
+           - clear clock gating (CLKGATE bit);
+           - set the SFTRST again and wait for block is in reset;
+           - clear SFTRST and wait for reset completion.
+        */
+        c = __raw_readl(hwreg);
+        c &= ~(1<<31);          /* clear SFTRST */
+        __raw_writel(c, hwreg);
+        for (timeout = 1000000; timeout > 0; timeout--)
+                /* still in SFTRST state ? */
+                if ((__raw_readl(hwreg) & (1<<31)) == 0)
+                        break;
+        if (timeout <= 0) {
+                printk(KERN_ERR"%s(%p): timeout when enabling\n",
+                                __func__, hwreg);
+                return -ETIME;
+        }
+        c = __raw_readl(hwreg);
+        c &= ~(1<<30);          /* clear CLKGATE */
+        __raw_writel(c, hwreg);
+        if (!just_enable) {
+                c = __raw_readl(hwreg);
+                c |= (1<<31);           /* now again set SFTRST */
+                __raw_writel(c, hwreg);
+                for (timeout = 1000000; timeout > 0; timeout--)
+                        /* poll until CLKGATE set */
+                        if (__raw_readl(hwreg) & (1<<30))
+                                break;
+                if (timeout <= 0) {
+                        printk(KERN_ERR"%s(%p): timeout when resetting\n",
+                                        __func__, hwreg);
+                        return -ETIME;
+                }
+                c = __raw_readl(hwreg);
+                c &= ~(1<<31);          /* clear SFTRST */
+                __raw_writel(c, hwreg);
+                for (timeout = 1000000; timeout > 0; timeout--)
+                        /* still in SFTRST state ? */
+                        if ((__raw_readl(hwreg) & (1<<31)) == 0)
+                                break;
+                if (timeout <= 0) {
+                        printk(KERN_ERR"%s(%p): timeout when enabling "
+                                        "after reset\n", __func__, hwreg);
+                        return -ETIME;
+                }
+                c = __raw_readl(hwreg);
+                c &= ~(1<<30);          /* clear CLKGATE */
+                __raw_writel(c, hwreg);
+        }
+        for (timeout = 1000000; timeout > 0; timeout--)
+                /* still in SFTRST state ? */
+                if ((__raw_readl(hwreg) & (1<<30)) == 0)
+                        break;
+        if (timeout <= 0) {
+                printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
+                                __func__, hwreg);
+                return -ETIME;
+        }
+        return 0;
+}
+int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
+{
+        int try = 10;
+        int r;
+        while (try--) {
+                r = __stmp3xxx_reset_block(hwreg, just_enable);
+                if (!r)
+                        break;
+                pr_debug("%s: try %d failed\n", __func__, 10 - try);
+        }
+        return r;
+}
+EXPORT_SYMBOL(stmp3xxx_reset_block);
+struct platform_device stmp3xxx_dbguart = {
+        .name = "stmp3xxx-dbguart",
+        .id = -1,
+};
+void __init stmp3xxx_init(void)
+{
+        /* Turn off auto-slow and other tricks */
+        stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
+        stmp3xxx_dma_init();
+}
diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c
new file mode 100644
index 000000000000..68fed4b8746a
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/devices.c
@@ -0,0 +1,389 @@
+/*
+* Freescale STMP37XX/STMP378X platform devices
+*
+* Embedded Alley Solutions, Inc <source@embeddedalley.com>
+*
+* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+*/
+/*
+* The code contained herein is licensed under the GNU General Public
+* License. You may obtain a copy of the GNU General Public License
+* Version 2 or later at the following locations:
+*
+* http://www.opensource.org/licenses/gpl-license.html
+* http://www.gnu.org/copyleft/gpl.html
+*/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <mach/dma.h>
+#include <mach/platform.h>
+#include <mach/stmp3xxx.h>
+#include <mach/regs-lcdif.h>
+#include <mach/regs-uartapp.h>
+#include <mach/regs-gpmi.h>
+#include <mach/regs-usbctrl.h>
+#include <mach/regs-ssp.h>
+#include <mach/regs-rtc.h>
+static u64 common_dmamask = DMA_BIT_MASK(32);
+static struct resource appuart_resources[] = {
+        {
+                .start = IRQ_UARTAPP_INTERNAL,
+                .end = IRQ_UARTAPP_INTERNAL,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = IRQ_UARTAPP_RX_DMA,
+                .end = IRQ_UARTAPP_RX_DMA,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = IRQ_UARTAPP_TX_DMA,
+                .end = IRQ_UARTAPP_TX_DMA,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = REGS_UARTAPP1_PHYS,
+                .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
+                .flags = IORESOURCE_MEM,
+        }, {
+                /* Rx DMA channel */
+                .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
+                .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
+                .flags = IORESOURCE_DMA,
+        }, {
+                /* Tx DMA channel */
+                .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
+                .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
+                .flags = IORESOURCE_DMA,
+        },
+};
+struct platform_device stmp3xxx_appuart = {
+        .name = "stmp3xxx-appuart",
+        .id = 0,
+        .resource = appuart_resources,
+        .num_resources = ARRAY_SIZE(appuart_resources),
+        .dev = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+struct platform_device stmp3xxx_watchdog = {
+      .name   = "stmp3xxx_wdt",
+      .id     = -1,
+};
+static struct resource ts_resource[] = {
+        {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_TOUCH_DETECT,
+                .end    = IRQ_TOUCH_DETECT,
+        }, {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_LRADC_CH5,
+                .end    = IRQ_LRADC_CH5,
+        },
+};
+struct platform_device stmp3xxx_touchscreen = {
+        .name           = "stmp3xxx_ts",
+        .id             = -1,
+        .resource       = ts_resource,
+        .num_resources  = ARRAY_SIZE(ts_resource),
+};
+/*
+* Keypad device
+*/
+struct platform_device stmp3xxx_keyboard = {
+        .name           = "stmp3xxx-keyboard",
+        .id             = -1,
+};
+static struct resource gpmi_resources[] = {
+        {
+                .flags = IORESOURCE_MEM,
+                .start = REGS_GPMI_PHYS,
+                .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
+        }, {
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_GPMI_DMA,
+                .end = IRQ_GPMI_DMA,
+        }, {
+                .flags = IORESOURCE_DMA,
+                .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
+                .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
+        },
+};
+struct platform_device stmp3xxx_gpmi = {
+        .name = "gpmi",
+        .id = -1,
+        .dev    = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource = gpmi_resources,
+        .num_resources = ARRAY_SIZE(gpmi_resources),
+};
+static struct resource mmc1_resource[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+                .start  = REGS_SSP1_PHYS,
+                .end    = REGS_SSP1_PHYS + REGS_SSP_SIZE,
+        }, {
+                .flags  = IORESOURCE_DMA,
+                .start  = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
+                .end    = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
+        }, {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_SSP1_DMA,
+                .end    = IRQ_SSP1_DMA,
+        }, {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_SSP_ERROR,
+                .end    = IRQ_SSP_ERROR,
+        },
+};
+struct platform_device stmp3xxx_mmc = {
+        .name   = "stmp3xxx-mmc",
+        .id     = 1,
+        .dev    = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource = mmc1_resource,
+        .num_resources = ARRAY_SIZE(mmc1_resource),
+};
+static struct resource usb_resources[] = {
+        {
+                .start  = REGS_USBCTRL_PHYS,
+                .end    = REGS_USBCTRL_PHYS + SZ_4K,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_USB_CTRL,
+                .end    = IRQ_USB_CTRL,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device stmp3xxx_udc = {
+        .name           = "fsl-usb2-udc",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &common_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource = usb_resources,
+        .num_resources = ARRAY_SIZE(usb_resources),
+};
+struct platform_device stmp3xxx_ehci = {
+        .name           = "fsl-ehci",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &common_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = usb_resources,
+        .num_resources  = ARRAY_SIZE(usb_resources),
+};
+static struct resource rtc_resources[] = {
+        {
+                .start  = REGS_RTC_PHYS,
+                .end    = REGS_RTC_PHYS + REGS_RTC_SIZE,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_RTC_ALARM,
+                .end    = IRQ_RTC_ALARM,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_RTC_1MSEC,
+                .end    = IRQ_RTC_1MSEC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device stmp3xxx_rtc = {
+        .name           = "stmp3xxx-rtc",
+        .id             = -1,
+        .resource       = rtc_resources,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
+};
+static struct resource ssp1_resources[] = {
+        {
+                .start  = REGS_SSP1_PHYS,
+                .end    = REGS_SSP1_PHYS + REGS_SSP_SIZE,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_SSP1_DMA,
+                .end    = IRQ_SSP1_DMA,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
+                .end    = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
+                .flags  = IORESOURCE_DMA,
+        },
+};
+static struct resource ssp2_resources[] = {
+        {
+                .start  = REGS_SSP2_PHYS,
+                .end    = REGS_SSP2_PHYS + REGS_SSP_SIZE,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_SSP2_DMA,
+                .end    = IRQ_SSP2_DMA,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
+                .end    = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
+                .flags  = IORESOURCE_DMA,
+        },
+};
+struct platform_device stmp3xxx_spi1 = {
+        .name   = "stmp3xxx_ssp",
+        .id     = 1,
+        .dev    = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource = ssp1_resources,
+        .num_resources = ARRAY_SIZE(ssp1_resources),
+};
+struct platform_device stmp3xxx_spi2 = {
+        .name   = "stmp3xxx_ssp",
+        .id     = 2,
+        .dev    = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource = ssp2_resources,
+        .num_resources = ARRAY_SIZE(ssp2_resources),
+};
+static struct resource fb_resource[] = {
+        {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_LCDIF_DMA,
+                .end    = IRQ_LCDIF_DMA,
+        }, {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_LCDIF_ERROR,
+                .end    = IRQ_LCDIF_ERROR,
+        }, {
+                .flags  = IORESOURCE_MEM,
+                .start  = REGS_LCDIF_PHYS,
+                .end    = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
+        },
+};
+struct platform_device stmp3xxx_framebuffer = {
+        .name           = "stmp3xxx-fb",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &common_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(fb_resource),
+        .resource       = fb_resource,
+};
+#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2)                 \
+        static char *cmdline_device_##name;                     \
+        static int cmdline_device_##name##_setup(char *dev)     \
+        {                                                       \
+                cmdline_device_##name = dev + 1;                \
+                return 0;                                       \
+        }                                                       \
+        __setup(#name, cmdline_device_##name##_setup);          \
+        int stmp3xxx_##name##_device_register(void)             \
+        {                                                       \
+                struct platform_device *d = NULL;               \
+                if (!cmdline_device_##name ||                   \
+                        !strcmp(cmdline_device_##name, #dev1))  \
+                                d = &stmp3xxx_##dev1;           \
+                else if (!strcmp(cmdline_device_##name, #dev2)) \
+                                d = &stmp3xxx_##dev2;           \
+                else                                            \
+                        printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
+                                #name, cmdline_device_##name);  \
+                return d ? platform_device_register(d) : -ENOENT;       \
+        }
+CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
+CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
+struct platform_device stmp3xxx_backlight = {
+        .name           = "stmp3xxx-bl",
+        .id             = -1,
+};
+struct platform_device stmp3xxx_rotdec = {
+        .name   = "stmp3xxx-rotdec",
+        .id     = -1,
+};
+struct platform_device stmp3xxx_persistent = {
+        .name                   = "stmp3xxx-persistent",
+        .id                     = -1,
+};
+struct platform_device stmp3xxx_dcp_bootstream = {
+        .name                   = "stmp3xxx-dcpboot",
+        .id                     = -1,
+        .dev    = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+static struct resource dcp_resources[] = {
+        {
+                .start = IRQ_DCP_VMI,
+                .end = IRQ_DCP_VMI,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = IRQ_DCP,
+                .end = IRQ_DCP,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device stmp3xxx_dcp = {
+        .name                   = "stmp3xxx-dcp",
+        .id                     = -1,
+        .resource               = dcp_resources,
+        .num_resources          = ARRAY_SIZE(dcp_resources),
+        .dev    = {
+                .dma_mask       = &common_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+static struct resource battery_resource[] = {
+        {
+                .flags  = IORESOURCE_IRQ,
+                .start  = IRQ_VDD5V,
+                .end    = IRQ_VDD5V,
+        },
+};
+struct platform_device stmp3xxx_battery = {
+        .name   = "stmp3xxx-battery",
+        .resource = battery_resource,
+        .num_resources = ARRAY_SIZE(battery_resource),
+};
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
new file mode 100644
index 000000000000..d2f497764dce
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/dma.c
@@ -0,0 +1,463 @@
+/*
+ * DMA helper routines for Freescale STMP37XX/STMP378X
+ *
+ * Author: dmitry pervushin <dpervushin@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/dmapool.h>
+#include <linux/sysdev.h>
+#include <linux/cpufreq.h>
+#include <asm/page.h>
+#include <mach/platform.h>
+#include <mach/dma.h>
+#include <mach/regs-apbx.h>
+#include <mach/regs-apbh.h>
+static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
+static const size_t pool_alignment = 8;
+static struct stmp3xxx_dma_user {
+        void *pool;
+        int inuse;
+        const char *name;
+} channels[MAX_DMA_CHANNELS];
+#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
+#define IS_USED(ch) (channels[ch].inuse)
+int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
+{
+        struct stmp3xxx_dma_user *user;
+        int err = 0;
+        user = channels + ch;
+        if (!IS_VALID_CHANNEL(ch)) {
+                err = -ENODEV;
+                goto out;
+        }
+        if (IS_USED(ch)) {
+                err = -EBUSY;
+                goto out;
+        }
+        /* Create a pool to allocate dma commands from */
+        user->pool = dma_pool_create(name, dev, pool_item_size,
+                                     pool_alignment, PAGE_SIZE);
+        if (user->pool == NULL) {
+                err = -ENOMEM;
+                goto out;
+        }
+        user->name = name;
+        user->inuse++;
+out:
+        return err;
+}
+EXPORT_SYMBOL(stmp3xxx_dma_request);
+int stmp3xxx_dma_release(int ch)
+{
+        struct stmp3xxx_dma_user *user = channels + ch;
+        int err = 0;
+        if (!IS_VALID_CHANNEL(ch)) {
+                err = -ENODEV;
+                goto out;
+        }
+        if (!IS_USED(ch)) {
+                err = -EBUSY;
+                goto out;
+        }
+        BUG_ON(user->pool == NULL);
+        dma_pool_destroy(user->pool);
+        user->inuse--;
+out:
+        return err;
+}
+EXPORT_SYMBOL(stmp3xxx_dma_release);
+int stmp3xxx_dma_read_semaphore(int channel)
+{
+        int sem = -1;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
+                                STMP3XXX_DMA_CHANNEL(channel) * 0x70);
+                sem &= BM_APBH_CHn_SEMA_PHORE;
+                sem >>= BP_APBH_CHn_SEMA_PHORE;
+                break;
+        case STMP3XXX_BUS_APBX:
+                sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
+                                STMP3XXX_DMA_CHANNEL(channel) * 0x70);
+                sem &= BM_APBX_CHn_SEMA_PHORE;
+                sem >>= BP_APBX_CHn_SEMA_PHORE;
+                break;
+        default:
+                BUG();
+        }
+        return sem;
+}
+EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
+int stmp3xxx_dma_allocate_command(int channel,
+                                  struct stmp3xxx_dma_descriptor *descriptor)
+{
+        struct stmp3xxx_dma_user *user = channels + channel;
+        int err = 0;
+        if (!IS_VALID_CHANNEL(channel)) {
+                err = -ENODEV;
+                goto out;
+        }
+        if (!IS_USED(channel)) {
+                err = -EBUSY;
+                goto out;
+        }
+        if (descriptor == NULL) {
+                err = -EINVAL;
+                goto out;
+        }
+        /* Allocate memory for a command from the buffer */
+        descriptor->command =
+            dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
+        /* Check it worked */
+        if (!descriptor->command) {
+                err = -ENOMEM;
+                goto out;
+        }
+        memset(descriptor->command, 0, pool_item_size);
+out:
+        WARN_ON(err);
+        return err;
+}
+EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
+int stmp3xxx_dma_free_command(int channel,
+                              struct stmp3xxx_dma_descriptor *descriptor)
+{
+        int err = 0;
+        if (!IS_VALID_CHANNEL(channel)) {
+                err = -ENODEV;
+                goto out;
+        }
+        if (!IS_USED(channel)) {
+                err = -EBUSY;
+                goto out;
+        }
+        /* Return the command memory to the pool */
+        dma_pool_free(channels[channel].pool, descriptor->command,
+                      descriptor->handle);
+        /* Initialise descriptor so we're not tempted to use it */
+        descriptor->command = NULL;
+        descriptor->handle = 0;
+        descriptor->virtual_buf_ptr = NULL;
+        descriptor->next_descr = NULL;
+        WARN_ON(err);
+out:
+        return err;
+}
+EXPORT_SYMBOL(stmp3xxx_dma_free_command);
+void stmp3xxx_dma_go(int channel,
+                     struct stmp3xxx_dma_descriptor *head, u32 semaphore)
+{
+        int ch = STMP3XXX_DMA_CHANNEL(channel);
+        void __iomem *c, *s;
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
+                s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
+                break;
+        case STMP3XXX_BUS_APBX:
+                c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
+                s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
+                break;
+        default:
+                return;
+        }
+        /* Set next command */
+        __raw_writel(head->handle, c);
+        /* Set counting semaphore (kicks off transfer). Assumes
+           peripheral has been set up correctly */
+        __raw_writel(semaphore, s);
+}
+EXPORT_SYMBOL(stmp3xxx_dma_go);
+int stmp3xxx_dma_running(int channel)
+{
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
+                        0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
+                            BM_APBH_CHn_SEMA_PHORE;
+        case STMP3XXX_BUS_APBX:
+                return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
+                        0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
+                            BM_APBX_CHn_SEMA_PHORE;
+        default:
+                BUG();
+                return 0;
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_dma_running);
+/*
+ * Circular dma chain management
+ */
+void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
+{
+        int i;
+        for (i = 0; i < chain->total_count; i++)
+                stmp3xxx_dma_free_command(
+                        STMP3XXX_DMA(chain->channel, chain->bus),
+                        &chain->chain[i]);
+}
+EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
+int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
+                            struct stmp3xxx_dma_descriptor descriptors[],
+                            unsigned items)
+{
+        int i;
+        int err = 0;
+        if (items == 0)
+                return err;
+        for (i = 0; i < items; i++) {
+                err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
+                if (err) {
+                        WARN_ON(err);
+                        /*
+                         * Couldn't allocate the whole chain.
+                         * deallocate what has been allocated
+                         */
+                        if (i) {
+                                do {
+                                        stmp3xxx_dma_free_command(ch,
+                                                                  &descriptors
+                                                                  [i]);
+                                } while (i-- >= 0);
+                        }
+                        return err;
+                }
+                /* link them! */
+                if (i > 0) {
+                        descriptors[i - 1].next_descr = &descriptors[i];
+                        descriptors[i - 1].command->next =
+                                                descriptors[i].handle;
+                }
+        }
+        /* make list circular */
+        descriptors[items - 1].next_descr = &descriptors[0];
+        descriptors[items - 1].command->next = descriptors[0].handle;
+        chain->total_count = items;
+        chain->chain = descriptors;
+        chain->free_index = 0;
+        chain->active_index = 0;
+        chain->cooked_index = 0;
+        chain->free_count = items;
+        chain->active_count = 0;
+        chain->cooked_count = 0;
+        chain->bus = STMP3XXX_DMA_BUS(ch);
+        chain->channel = STMP3XXX_DMA_CHANNEL(ch);
+        return err;
+}
+EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
+void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
+{
+        BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
+        chain->free_index = 0;
+        chain->active_index = 0;
+        chain->cooked_index = 0;
+        chain->free_count = chain->total_count;
+        chain->active_count = 0;
+        chain->cooked_count = 0;
+}
+EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
+void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
+                unsigned count)
+{
+        BUG_ON(chain->cooked_count < count);
+        chain->cooked_count -= count;
+        chain->cooked_index += count;
+        chain->cooked_index %= chain->total_count;
+        chain->free_count += count;
+}
+EXPORT_SYMBOL(stmp37xx_circ_advance_free);
+void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
+                unsigned count)
+{
+        void __iomem *c;
+        u32 mask_clr, mask;
+        BUG_ON(chain->free_count < count);
+        chain->free_count -= count;
+        chain->free_index += count;
+        chain->free_index %= chain->total_count;
+        chain->active_count += count;
+        switch (chain->bus) {
+        case STMP3XXX_BUS_APBH:
+                c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
+                mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
+                mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
+                break;
+        case STMP3XXX_BUS_APBX:
+                c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
+                mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
+                mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
+                break;
+        default:
+                BUG();
+                return;
+        }
+        /* Set counting semaphore (kicks off transfer). Assumes
+           peripheral has been set up correctly */
+        stmp3xxx_clearl(mask_clr, c);
+        stmp3xxx_setl(mask, c);
+}
+EXPORT_SYMBOL(stmp37xx_circ_advance_active);
+unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
+{
+        unsigned cooked;
+        cooked = chain->active_count -
+          stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
+        chain->active_count -= cooked;
+        chain->active_index += cooked;
+        chain->active_index %= chain->total_count;
+        chain->cooked_count += cooked;
+        return cooked;
+}
+EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
+void stmp3xxx_dma_set_alt_target(int channel, int function)
+{
+#if defined(CONFIG_ARCH_STMP37XX)
+        unsigned bits = 4;
+#elif defined(CONFIG_ARCH_STMP378X)
+        unsigned bits = 2;
+#else
+#error wrong arch
+#endif
+        int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
+        unsigned mask = (1<<bits) - 1;
+        void __iomem *c;
+        BUG_ON(function < 0 || function >= (1<<bits));
+        pr_debug("%s: channel = %d, using mask %x, "
+                 "shift = %d\n", __func__, channel, mask, shift);
+        switch (STMP3XXX_DMA_BUS(channel)) {
+        case STMP3XXX_BUS_APBH:
+                c = REGS_APBH_BASE + HW_APBH_DEVSEL;
+                break;
+        case STMP3XXX_BUS_APBX:
+                c = REGS_APBX_BASE + HW_APBX_DEVSEL;
+                break;
+        default:
+                BUG();
+        }
+        stmp3xxx_clearl(mask << shift, c);
+        stmp3xxx_setl(mask << shift, c);
+}
+EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
+void stmp3xxx_dma_suspend(void)
+{
+        stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
+        stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
+}
+void stmp3xxx_dma_resume(void)
+{
+        stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
+                        REGS_APBH_BASE + HW_APBH_CTRL0);
+        stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
+                        REGS_APBX_BASE + HW_APBX_CTRL0);
+}
+#ifdef CONFIG_CPU_FREQ
+struct dma_notifier_block {
+        struct notifier_block nb;
+        void *data;
+};
+static int dma_cpufreq_notifier(struct notifier_block *self,
+                                unsigned long phase, void *p)
+{
+        switch (phase) {
+        case CPUFREQ_POSTCHANGE:
+                stmp3xxx_dma_resume();
+                break;
+        case CPUFREQ_PRECHANGE:
+                stmp3xxx_dma_suspend();
+                break;
+        default:
+                break;
+        }
+        return NOTIFY_DONE;
+}
+static struct dma_notifier_block dma_cpufreq_nb = {
+        .nb = {
+                .notifier_call = dma_cpufreq_notifier,
+        },
+};
+#endif /* CONFIG_CPU_FREQ */
+void __init stmp3xxx_dma_init(void)
+{
+        stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
+                        REGS_APBH_BASE + HW_APBH_CTRL0);
+        stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
+                        REGS_APBX_BASE + HW_APBX_CTRL0);
+#ifdef CONFIG_CPU_FREQ
+        cpufreq_register_notifier(&dma_cpufreq_nb.nb,
+                                CPUFREQ_TRANSITION_NOTIFIER);
+#endif /* CONFIG_CPU_FREQ */
+}
diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
new file mode 100644
index 000000000000..f9c39772d7c5
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
new file mode 100644
index 000000000000..b4e205b95f2c
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
@@ -0,0 +1,33 @@
+/*
+ * Freescale STMP37XX/STMP378X CPU type detection
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_PLAT_CPU_H
+#define __ASM_PLAT_CPU_H
+#ifdef CONFIG_ARCH_STMP37XX
+#define cpu_is_stmp37xx()       (1)
+#else
+#define cpu_is_stmp37xx()       (0)
+#endif
+#ifdef CONFIG_ARCH_STMP378X
+#define cpu_is_stmp378x()       (1)
+#else
+#define cpu_is_stmp378x()       (0)
+#endif
+#endif /* __ASM_PLAT_CPU_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..fb3b969bf0a2
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
@@ -0,0 +1,42 @@
+/*
+ * Debugging macro include header
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x80000000        @ physical base address
+                addeq   \rx, \rx, #0x00070000
+                movne   \rx, #0xf0000000        @ virtual base
+                addne   \rx, \rx, #0x00070000
+                .endm
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #0]          @ data register at 0
+                .endm
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
new file mode 100644
index 000000000000..7c58557c6766
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/dma.h
@@ -0,0 +1,153 @@
+/*
+ * Freescale STMP37XX/STMP378X DMA helper interface
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_PLAT_STMP3XXX_DMA_H
+#define __ASM_PLAT_STMP3XXX_DMA_H
+#include <linux/platform_device.h>
+#include <linux/dmapool.h>
+#if !defined(MAX_PIO_WORDS)
+#define MAX_PIO_WORDS   (15)
+#endif
+#define STMP3XXX_BUS_APBH               0
+#define STMP3XXX_BUS_APBX               1
+#define STMP3XXX_DMA_MAX_CHANNEL        16
+#define STMP3XXX_DMA_BUS(dma)           ((dma) / 16)
+#define STMP3XXX_DMA_CHANNEL(dma)       ((dma) % 16)
+#define STMP3XXX_DMA(channel, bus)      ((bus) * 16 + (channel))
+#define MAX_DMA_ADDRESS                 0xffffffff
+#define MAX_DMA_CHANNELS                32
+struct stmp3xxx_dma_command {
+        u32 next;
+        u32 cmd;
+        union {
+                u32 buf_ptr;
+                u32 alternate;
+        };
+        u32 pio_words[MAX_PIO_WORDS];
+};
+struct stmp3xxx_dma_descriptor {
+        struct stmp3xxx_dma_command *command;
+        dma_addr_t handle;
+        /* The virtual address of the buffer pointer */
+        void *virtual_buf_ptr;
+        /* The next descriptor in a the DMA chain (optional) */
+        struct stmp3xxx_dma_descriptor *next_descr;
+};
+struct stmp37xx_circ_dma_chain {
+        unsigned total_count;
+        struct stmp3xxx_dma_descriptor *chain;
+        unsigned free_index;
+        unsigned free_count;
+        unsigned active_index;
+        unsigned active_count;
+        unsigned cooked_index;
+        unsigned cooked_count;
+        int bus;
+        unsigned channel;
+};
+static inline struct stmp3xxx_dma_descriptor
+    *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
+{
+        return &(chain->chain[chain->free_index]);
+}
+static inline struct stmp3xxx_dma_descriptor
+    *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
+{
+        return &(chain->chain[chain->cooked_index]);
+}
+int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
+int stmp3xxx_dma_release(int ch);
+int stmp3xxx_dma_allocate_command(int ch,
+                                  struct stmp3xxx_dma_descriptor *descriptor);
+int stmp3xxx_dma_free_command(int ch,
+                              struct stmp3xxx_dma_descriptor *descriptor);
+void stmp3xxx_dma_continue(int channel, u32 semaphore);
+void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
+                     u32 semaphore);
+int stmp3xxx_dma_running(int ch);
+int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
+                            struct stmp3xxx_dma_descriptor descriptors[],
+                            unsigned items);
+void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
+void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
+void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
+                unsigned count);
+void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
+                unsigned count);
+unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
+int stmp3xxx_dma_read_semaphore(int ch);
+void stmp3xxx_dma_init(void);
+void stmp3xxx_dma_set_alt_target(int ch, int target);
+void stmp3xxx_dma_suspend(void);
+void stmp3xxx_dma_resume(void);
+/*
+ * STMP37xx and STMP378x have different DMA control
+ * registers layout
+ */
+void stmp3xxx_arch_dma_freeze(int ch);
+void stmp3xxx_arch_dma_unfreeze(int ch);
+void stmp3xxx_arch_dma_reset_channel(int ch);
+void stmp3xxx_arch_dma_enable_interrupt(int ch);
+void stmp3xxx_arch_dma_clear_interrupt(int ch);
+int stmp3xxx_arch_dma_is_interrupt(int ch);
+static inline void stmp3xxx_dma_reset_channel(int ch)
+{
+        stmp3xxx_arch_dma_reset_channel(ch);
+}
+static inline void stmp3xxx_dma_freeze(int ch)
+{
+        stmp3xxx_arch_dma_freeze(ch);
+}
+static inline void stmp3xxx_dma_unfreeze(int ch)
+{
+        stmp3xxx_arch_dma_unfreeze(ch);
+}
+static inline void stmp3xxx_dma_enable_interrupt(int ch)
+{
+        stmp3xxx_arch_dma_enable_interrupt(ch);
+}
+static inline void stmp3xxx_dma_clear_interrupt(int ch)
+{
+        stmp3xxx_arch_dma_clear_interrupt(ch);
+}
+static inline int stmp3xxx_dma_is_interrupt(int ch)
+{
+        return stmp3xxx_arch_dma_is_interrupt(ch);
+}
+#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
new file mode 100644
index 000000000000..a8b579256170
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * Freescale STMP37XX/STMP378X GPIO interface
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_PLAT_GPIO_H
+#define __ASM_PLAT_GPIO_H
+#define ARCH_NR_GPIOS   (32 * 3)
+#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
+#define gpio_get_value(gpio) __gpio_get_value(gpio)
+#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
+#include <asm-generic/gpio.h>
+#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
new file mode 100644
index 000000000000..e166432910ad
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
@@ -0,0 +1,12 @@
+#ifndef __MACH_GPMI_H
+#include <linux/mtd/partitions.h>
+#include <mach/regs-gpmi.h>
+struct gpmi_platform_data {
+        void *pins;
+        int nr_parts;
+        struct mtd_partition *parts;
+        const char *part_types[];
+};
+#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
new file mode 100644
index 000000000000..47b8978405bc
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
@@ -0,0 +1,32 @@
+/*
+ * This file contains the hardware definitions of the Freescale STMP3XXX
+ *
+ * Copyright (C) 2005 Sigmatel Inc
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE                 0xF0000000                 /* VA of IO  */
+#define IO_SIZE                 0x00100000                 /* How much? */
+#define IO_START                0x80000000                 /* PA of IO  */
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
+#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
new file mode 100644
index 000000000000..d08b1b7f3d1c
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2005 Sigmatel Inc
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+#define __mem_isa(a)    (a)
+#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
new file mode 100644
index 000000000000..7b875a07a1a7
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/memory.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x40000000)
+#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
new file mode 100644
index 000000000000..ba81e1543761
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
@@ -0,0 +1,14 @@
+#ifndef _MACH_MMC_H
+#define _MACH_MMC_H
+#include <mach/regs-ssp.h>
+struct stmp3xxxmmc_platform_data {
+        int (*get_wp)(void);
+        unsigned long (*setclock)(void __iomem *base, unsigned long);
+        void (*cmd_pullup)(int);
+        int  (*hw_init)(void);
+        void (*hw_release)(void);
+};
+#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
new file mode 100644
index 000000000000..cc5af82279ad
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
@@ -0,0 +1,157 @@
+/*
+ * Freescale STMP37XX/STMP378X Pin Multiplexing
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __PINMUX_H
+#define __PINMUX_H
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <asm-generic/gpio.h>
+/* Pin definitions */
+#include "pins.h"
+#include <mach/pins.h>
+/*
+ * Each pin may be routed up to four different HW interfaces
+ * including GPIO
+ */
+enum pin_fun {
+        PIN_FUN1 = 0,
+        PIN_FUN2,
+        PIN_FUN3,
+        PIN_GPIO,
+};
+/*
+ * Each pin may have different output drive strength in range from
+ * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
+ */
+enum pin_strength {
+        PIN_4MA = 0,
+        PIN_8MA,
+        PIN_12MA,
+        PIN_16MA,
+        PIN_20MA,
+};
+/*
+ * Each pin can be programmed for 1.8V or 3.3V
+ */
+enum pin_voltage {
+        PIN_1_8V = 0,
+        PIN_3_3V,
+};
+/*
+ * Structure to define a group of pins and their parameters
+ */
+struct pin_desc {
+        unsigned id;
+        enum pin_fun fun;
+        enum pin_strength strength;
+        enum pin_voltage voltage;
+        unsigned pullup:1;
+};
+struct pin_group {
+        struct pin_desc *pins;
+        int nr_pins;
+};
+/* Set pin drive strength */
+void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
+                           const char *label);
+/* Set pin voltage */
+void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
+                           const char *label);
+/* Enable pull-up resistor for a pin */
+void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
+/*
+ * Request a pin ownership, only one module (identified by @label)
+ * may own a pin.
+ */
+int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
+/* Release pin */
+void stmp3xxx_release_pin(unsigned id, const char *label);
+void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
+/*
+ * Each bank is associated with a number of registers to control
+ * pin function, drive strength, voltage and pull-up reigster. The
+ * number of registers of a given type depends on the number of bits
+ * describin particular pin.
+ */
+#define HW_MUXSEL_NUM           2       /* registers per bank */
+#define HW_MUXSEL_PIN_LEN       2       /* bits per pin */
+#define HW_MUXSEL_PIN_NUM       16      /* pins per register */
+#define HW_MUXSEL_PINFUN_MASK   0x3     /* pin function mask */
+#define HW_MUXSEL_PINFUN_NUM    4       /* four options for a pin */
+#define HW_DRIVE_NUM            4       /* registers per bank */
+#define HW_DRIVE_PIN_LEN        4       /* bits per pin */
+#define HW_DRIVE_PIN_NUM        8       /* pins per register */
+#define HW_DRIVE_PINDRV_MASK    0x3     /* pin strength mask - 2 bits */
+#define HW_DRIVE_PINDRV_NUM     5       /* five possible strength values */
+#define HW_DRIVE_PINV_MASK      0x4     /* pin voltage mask - 1 bit */
+struct stmp3xxx_pinmux_bank {
+        struct gpio_chip chip;
+        /* Pins allocation map */
+        unsigned long pin_map;
+        /* Pin owner names */
+        const char *pin_labels[32];
+        /* Bank registers */
+        void __iomem *hw_muxsel[HW_MUXSEL_NUM];
+        void __iomem *hw_drive[HW_DRIVE_NUM];
+        void __iomem *hw_pull;
+        void __iomem *pin2irq,
+                *irqlevel,
+                *irqpolarity,
+                *irqen,
+                *irqstat;
+        /* HW MUXSEL register function bit values */
+        u8 functions[HW_MUXSEL_PINFUN_NUM];
+        /*
+         * HW DRIVE register strength bit values:
+         * 0xff - requested strength is not supported for this bank
+         */
+        u8 strengths[HW_DRIVE_PINDRV_NUM];
+        /* GPIO things */
+        void __iomem *hw_gpio_in,
+                     *hw_gpio_out,
+                     *hw_gpio_doe;
+        int irq, virq;
+};
+int __init stmp3xxx_pinmux_init(int virtual_irq_start);
+#endif /* __PINMUX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h
new file mode 100644
index 000000000000..c573318e1caa
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/pins.h
@@ -0,0 +1,30 @@
+/*
+ * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_PLAT_PINS_H
+#define __ASM_PLAT_PINS_H
+#define STMP3XXX_PINID(bank, pin)       (bank * 32 + pin)
+#define STMP3XXX_PINID_TO_BANK(pinid)   (pinid / 32)
+#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
+/*
+ * Special invalid pin identificator to show a pin doesn't exist
+ */
+#define PINID_NO_PIN    STMP3XXX_PINID(0xFF, 0xFF)
+#endif /* __ASM_PLAT_PINS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
new file mode 100644
index 000000000000..7007ddaa91eb
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/platform.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_PLAT_PLATFORM_H
+#define __ASM_PLAT_PLATFORM_H
+#ifndef __ASSEMBLER__
+#include <linux/io.h>
+#endif
+#include <asm/sizes.h>
+/* Virtual address where registers are mapped */
+#define STMP3XXX_REGS_PHBASE    0x80000000
+#ifdef __ASSEMBLER__
+#define STMP3XXX_REGS_BASE      0xF0000000
+#else
+#define STMP3XXX_REGS_BASE      (void __iomem *)0xF0000000
+#endif
+#define STMP3XXX_REGS_SIZE      SZ_1M
+/* Virtual address where OCRAM is mapped */
+#define STMP3XXX_OCRAM_PHBASE   0x00000000
+#ifdef __ASSEMBLER__
+#define STMP3XXX_OCRAM_BASE     0xf1000000
+#else
+#define STMP3XXX_OCRAM_BASE     (void __iomem *)0xf1000000
+#endif
+#define STMP3XXX_OCRAM_SIZE     (32 * SZ_1K)
+#ifdef CONFIG_ARCH_STMP37XX
+#define IRQ_PRIORITY_REG_RD     HW_ICOLL_PRIORITYn_RD
+#define IRQ_PRIORITY_REG_WR     HW_ICOLL_PRIORITYn_WR
+#endif
+#ifdef CONFIG_ARCH_STMP378X
+#define IRQ_PRIORITY_REG_RD     HW_ICOLL_INTERRUPTn_RD
+#define IRQ_PRIORITY_REG_WR     HW_ICOLL_INTERRUPTn_WR
+#endif
+#define HW_STMP3XXX_SET         0x04
+#define HW_STMP3XXX_CLR         0x08
+#define HW_STMP3XXX_TOG         0x0c
+#ifndef __ASSEMBLER__
+static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
+{
+        __raw_writel(v, r + HW_STMP3XXX_CLR);
+}
+static inline void stmp3xxx_setl(u32 v, void __iomem *r)
+{
+        __raw_writel(v, r + HW_STMP3XXX_SET);
+}
+#endif
+#define BF(value, field) (((value) << BP_##field) & BM_##field)
+#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
new file mode 100644
index 000000000000..2e300feaa4cf
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
@@ -0,0 +1,54 @@
+/*
+ * Freescale STMP37XX/STMP378X core structure and function declarations
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_PLAT_STMP3XXX_H
+#define __ASM_PLAT_STMP3XXX_H
+#include <linux/irq.h>
+extern struct sys_timer stmp3xxx_timer;
+void stmp3xxx_init_irq(struct irq_chip *chip);
+void stmp3xxx_init(void);
+int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
+extern struct platform_device stmp3xxx_dbguart,
+                              stmp3xxx_appuart,
+                              stmp3xxx_watchdog,
+                              stmp3xxx_touchscreen,
+                              stmp3xxx_keyboard,
+                              stmp3xxx_gpmi,
+                              stmp3xxx_mmc,
+                              stmp3xxx_udc,
+                              stmp3xxx_ehci,
+                              stmp3xxx_rtc,
+                              stmp3xxx_spi1,
+                              stmp3xxx_spi2,
+                              stmp3xxx_backlight,
+                              stmp3xxx_rotdec,
+                              stmp3xxx_dcp,
+                              stmp3xxx_dcp_bootstream,
+                              stmp3xxx_persistent,
+                              stmp3xxx_framebuffer,
+                              stmp3xxx_battery;
+int stmp3xxx_ssp1_device_register(void);
+int stmp3xxx_ssp2_device_register(void);
+struct pin_group;
+void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
+int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
+#endif /* __ASM_PLAT_STMP3XXX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
new file mode 100644
index 000000000000..28a988889319
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/system.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2005 Sigmatel Inc
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/proc-fns.h>
+#include <mach/platform.h>
+#include <mach/regs-clkctrl.h>
+#include <mach/regs-power.h>
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode, const char *cmd)
+{
+        /* Set BATTCHRG to default value */
+        __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
+        /* Set MINPWR to default value   */
+        __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
+        /* Reset digital side of chip (but not power or RTC) */
+        __raw_writel(BM_CLKCTRL_RESET_DIG,
+                        REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
+        /* Should not return */
+}
+#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h
new file mode 100644
index 000000000000..3373985d7a8e
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/timex.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/*
+ * System time clock is sourced from the 32k clock
+ */
+#define CLOCK_TICK_RATE         (32768)
diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
new file mode 100644
index 000000000000..f79f5ee56cd4
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
@@ -0,0 +1,53 @@
+/*
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_PLAT_UNCOMPRESS_H
+#define __ASM_PLAT_UNCOMPRESS_H
+/*
+ * Register includes are for when the MMU enabled; we need to define our
+ * own stuff here for pre-MMU use
+ */
+#define UARTDBG_BASE            0x80070000
+#define UART(c)                 (((volatile unsigned *)UARTDBG_BASE)[c])
+/*
+ * This does not append a newline
+ */
+static void putc(char c)
+{
+        /* Wait for TX fifo empty */
+        while ((UART(6) & (1<<7)) == 0)
+                continue;
+        /* Write byte */
+        UART(0) = c;
+        /* Wait for last bit to exit the UART */
+        while (UART(6) & (1<<3))
+                continue;
+}
+static void flush(void)
+{
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..541b880c1863
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#define VMALLOC_END       (0xF0000000)
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
new file mode 100644
index 000000000000..20de4e0401ef
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -0,0 +1,51 @@
+/*
+ * Freescale STMP37XX/STMP378X common interrupt handling code
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/sysdev.h>
+#include <mach/stmp3xxx.h>
+#include <mach/platform.h>
+#include <mach/regs-icoll.h>
+void __init stmp3xxx_init_irq(struct irq_chip *chip)
+{
+        unsigned int i, lv;
+        /* Reset the interrupt controller */
+        stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
+        /* Disable all interrupts initially */
+        for (i = 0; i < NR_REAL_IRQS; i++) {
+                chip->mask(i);
+                set_irq_chip(i, chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        }
+        /* Ensure vector is cleared */
+        for (lv = 0; lv < 4; lv++)
+                __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
+        __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
+        /* Barrier */
+        (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
+}
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
new file mode 100644
index 000000000000..d41200382208
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -0,0 +1,552 @@
+/*
+ * Freescale STMP378X/STMP378X Pin Multiplexing
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#define DEBUG
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sysdev.h>
+#include <linux/string.h>
+#include <linux/bitops.h>
+#include <linux/sysdev.h>
+#include <linux/irq.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include <mach/regs-pinctrl.h>
+#include <mach/pins.h>
+#include <mach/pinmux.h>
+#define NR_BANKS ARRAY_SIZE(pinmux_banks)
+static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
+        [0] = {
+                .hw_muxsel = {
+                        REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
+                },
+                .hw_drive = {
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
+                },
+                .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
+                .functions = { 0x0, 0x1, 0x2, 0x3 },
+                .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
+                .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
+                .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
+                .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
+                .irq = IRQ_GPIO0,
+                .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
+                .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
+                .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
+                .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
+                .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
+        },
+        [1] = {
+                .hw_muxsel = {
+                        REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
+                },
+                .hw_drive = {
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
+                },
+                .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
+                .functions = { 0x0, 0x1, 0x2, 0x3 },
+                .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
+                .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
+                .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
+                .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
+                .irq = IRQ_GPIO1,
+                .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
+                .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
+                .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
+                .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
+                .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
+        },
+        [2] = {
+               .hw_muxsel = {
+                        REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
+                },
+                .hw_drive = {
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
+                },
+                .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
+                .functions = { 0x0, 0x1, 0x2, 0x3 },
+                .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
+                .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
+                .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
+                .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
+                .irq = IRQ_GPIO2,
+                .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
+                .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
+                .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
+                .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
+                .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
+        },
+        [3] = {
+               .hw_muxsel = {
+                       REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
+                       REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
+               },
+               .hw_drive = {
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
+                        REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
+                        NULL,
+               },
+               .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
+               .functions = {0x0, 0x1, 0x2, 0x3},
+               .strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
+        },
+};
+static inline struct stmp3xxx_pinmux_bank *
+stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
+{
+        unsigned b, p;
+        b = STMP3XXX_PINID_TO_BANK(id);
+        p = STMP3XXX_PINID_TO_PINNUM(id);
+        BUG_ON(b >= NR_BANKS);
+        if (bank)
+                *bank = b;
+        if (pin)
+                *pin = p;
+        return &pinmux_banks[b];
+}
+/* Check if requested pin is owned by caller */
+static int stmp3xxx_check_pin(unsigned id, const char *label)
+{
+        unsigned pin;
+        struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
+        if (!test_bit(pin, &pm->pin_map)) {
+                printk(KERN_WARNING
+                       "%s: Accessing free pin %x, caller %s\n",
+                       __func__, id, label);
+                return -EINVAL;
+        }
+        if (label && pm->pin_labels[pin] &&
+            strcmp(label, pm->pin_labels[pin])) {
+                printk(KERN_WARNING
+                       "%s: Wrong pin owner %x, caller %s owner %s\n",
+                       __func__, id, label, pm->pin_labels[pin]);
+                return -EINVAL;
+        }
+        return 0;
+}
+void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
+                const char *label)
+{
+        struct stmp3xxx_pinmux_bank *pbank;
+        void __iomem *hwdrive;
+        u32 shift, val;
+        u32 bank, pin;
+        pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
+        pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
+                 bank, pin, strength);
+        hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
+        shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
+        val = pbank->strengths[strength];
+        if (val == 0xff) {
+                printk(KERN_WARNING
+                       "%s: strength is not supported for bank %d, caller %s",
+                       __func__, bank, label);
+                return;
+        }
+        if (stmp3xxx_check_pin(id, label))
+                return;
+        pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
+                        val << shift, hwdrive);
+        stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
+        stmp3xxx_setl(val << shift, hwdrive);
+}
+void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
+                          const char *label)
+{
+        struct stmp3xxx_pinmux_bank *pbank;
+        void __iomem *hwdrive;
+        u32 shift;
+        u32 bank, pin;
+        pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
+        pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
+                 bank, pin, voltage);
+        hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
+        shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
+        if (stmp3xxx_check_pin(id, label))
+                return;
+        pr_debug("%s: changing 0x%x bit in 0x%p register\n",
+                        __func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
+        if (voltage == PIN_1_8V)
+                stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
+        else
+                stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
+}
+void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
+{
+        struct stmp3xxx_pinmux_bank *pbank;
+        void __iomem *hwpull;
+        u32 bank, pin;
+        pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
+        pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
+                 bank, pin, enable);
+        hwpull = pbank->hw_pull;
+        if (stmp3xxx_check_pin(id, label))
+                return;
+        pr_debug("%s: changing 0x%x bit in 0x%p register\n",
+                        __func__, 1 << pin, hwpull);
+        if (enable)
+                stmp3xxx_setl(1 << pin, hwpull);
+        else
+                stmp3xxx_clearl(1 << pin, hwpull);
+}
+int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
+{
+        struct stmp3xxx_pinmux_bank *pbank;
+        u32 bank, pin;
+        int ret = 0;
+        pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
+        pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
+                 bank, pin, fun);
+        if (test_bit(pin, &pbank->pin_map)) {
+                printk(KERN_WARNING
+                       "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
+                       __func__, bank, pin, label, pbank->pin_labels[pin]);
+                return -EBUSY;
+        }
+        set_bit(pin, &pbank->pin_map);
+        pbank->pin_labels[pin] = label;
+        stmp3xxx_set_pin_type(id, fun);
+        return ret;
+}
+void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
+{
+        struct stmp3xxx_pinmux_bank *pbank;
+        void __iomem *hwmux;
+        u32 shift, val;
+        u32 bank, pin;
+        pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
+        hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
+        shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
+        val = pbank->functions[fun];
+        shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
+        pr_debug("%s: writing 0x%x to 0x%p register\n",
+                        __func__, val << shift, hwmux);
+        stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
+        stmp3xxx_setl(val << shift, hwmux);
+}
+void stmp3xxx_release_pin(unsigned id, const char *label)
+{
+        struct stmp3xxx_pinmux_bank *pbank;
+        u32 bank, pin;
+        pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
+        pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
+        if (stmp3xxx_check_pin(id, label))
+                return;
+        clear_bit(pin, &pbank->pin_map);
+        pbank->pin_labels[pin] = NULL;
+}
+int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
+{
+        struct pin_desc *pin;
+        int p;
+        int err = 0;
+        /* Allocate and configure pins */
+        for (p = 0; p < pin_group->nr_pins; p++) {
+                pr_debug("%s: #%d\n", __func__, p);
+                pin = &pin_group->pins[p];
+                err = stmp3xxx_request_pin(pin->id, pin->fun, label);
+                if (err)
+                        goto out_err;
+                stmp3xxx_pin_strength(pin->id, pin->strength, label);
+                stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
+                stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
+        }
+        return 0;
+out_err:
+        /* Release allocated pins in case of error */
+        while (--p >= 0) {
+                pr_debug("%s: releasing #%d\n", __func__, p);
+                stmp3xxx_release_pin(pin_group->pins[p].id, label);
+        }
+        return err;
+}
+EXPORT_SYMBOL(stmp3xxx_request_pin_group);
+void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
+{
+        struct pin_desc *pin;
+        int p;
+        for (p = 0; p < pin_group->nr_pins; p++) {
+                pin = &pin_group->pins[p];
+                stmp3xxx_release_pin(pin->id, label);
+        }
+}
+EXPORT_SYMBOL(stmp3xxx_release_pin_group);
+static int stmp3xxx_irq_to_gpio(int irq,
+        struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
+{
+        struct stmp3xxx_pinmux_bank *pm;
+        for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
+                if (pm->virq <= irq && irq < pm->virq + 32) {
+                        *bank = pm;
+                        *gpio = irq - pm->virq;
+                        return 0;
+                }
+        return -ENOENT;
+}
+static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
+{
+        struct stmp3xxx_pinmux_bank *pm;
+        unsigned gpio;
+        int l, p;
+        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                l = 0; p = 1; break;
+        case IRQ_TYPE_EDGE_FALLING:
+                l = 0; p = 0; break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                l = 1; p = 1; break;
+        case IRQ_TYPE_LEVEL_LOW:
+                l = 1; p = 0; break;
+        default:
+                pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
+                                __func__, type);
+                return -ENXIO;
+        }
+        if (l)
+                stmp3xxx_setl(1 << gpio, pm->irqlevel);
+        else
+                stmp3xxx_clearl(1 << gpio, pm->irqlevel);
+        if (p)
+                stmp3xxx_setl(1 << gpio, pm->irqpolarity);
+        else
+                stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
+        return 0;
+}
+static void stmp3xxx_pin_ack_irq(unsigned irq)
+{
+        u32 stat;
+        struct stmp3xxx_pinmux_bank *pm;
+        unsigned gpio;
+        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        stat = __raw_readl(pm->irqstat) & (1 << gpio);
+        stmp3xxx_clearl(stat, pm->irqstat);
+}
+static void stmp3xxx_pin_mask_irq(unsigned irq)
+{
+        struct stmp3xxx_pinmux_bank *pm;
+        unsigned gpio;
+        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        stmp3xxx_clearl(1 << gpio, pm->irqen);
+        stmp3xxx_clearl(1 << gpio, pm->pin2irq);
+}
+static void stmp3xxx_pin_unmask_irq(unsigned irq)
+{
+        struct stmp3xxx_pinmux_bank *pm;
+        unsigned gpio;
+        stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
+        stmp3xxx_setl(1 << gpio, pm->irqen);
+        stmp3xxx_setl(1 << gpio, pm->pin2irq);
+}
+static inline
+struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
+{
+        return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
+}
+static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
+        return pm->virq + offset;
+}
+static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
+        unsigned v;
+        v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
+        return v ? 1 : 0;
+}
+static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
+{
+        struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
+        if (v)
+                stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
+        else
+                stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
+}
+static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
+{
+        struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
+        stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
+        stmp3xxx_gpio_set(chip, offset, v);
+        return 0;
+}
+static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
+        stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
+        return 0;
+}
+static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
+}
+static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        stmp3xxx_release_pin(chip->base + offset, "gpio");
+}
+static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
+{
+        struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq);
+        int gpio_irq = pm->virq;
+        u32 stat = __raw_readl(pm->irqstat);
+        while (stat) {
+                if (stat & 1)
+                        irq_desc[gpio_irq].handle_irq(gpio_irq,
+                                &irq_desc[gpio_irq]);
+                gpio_irq++;
+                stat >>= 1;
+        }
+}
+static struct irq_chip gpio_irq_chip = {
+        .ack    = stmp3xxx_pin_ack_irq,
+        .mask   = stmp3xxx_pin_mask_irq,
+        .unmask = stmp3xxx_pin_unmask_irq,
+        .set_type = stmp3xxx_set_irqtype,
+};
+int __init stmp3xxx_pinmux_init(int virtual_irq_start)
+{
+        int b, r = 0;
+        struct stmp3xxx_pinmux_bank *pm;
+        int virq;
+        for (b = 0; b < 3; b++) {
+                /* only banks 0,1,2 are allowed to GPIO */
+                pm = pinmux_banks + b;
+                pm->chip.base = 32 * b;
+                pm->chip.ngpio = 32;
+                pm->chip.owner = THIS_MODULE;
+                pm->chip.can_sleep = 1;
+                pm->chip.exported = 1;
+                pm->chip.to_irq = stmp3xxx_gpio_to_irq;
+                pm->chip.direction_input = stmp3xxx_gpio_input;
+                pm->chip.direction_output = stmp3xxx_gpio_output;
+                pm->chip.get = stmp3xxx_gpio_get;
+                pm->chip.set = stmp3xxx_gpio_set;
+                pm->chip.request = stmp3xxx_gpio_request;
+                pm->chip.free = stmp3xxx_gpio_free;
+                pm->virq = virtual_irq_start + b * 32;
+                for (virq = pm->virq; virq < pm->virq; virq++) {
+                        gpio_irq_chip.mask(virq);
+                        set_irq_chip(virq, &gpio_irq_chip);
+                        set_irq_handler(virq, handle_level_irq);
+                        set_irq_flags(virq, IRQF_VALID);
+                }
+                r = gpiochip_add(&pm->chip);
+                if (r < 0)
+                        break;
+                set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq);
+                set_irq_data(pm->irq, pm);
+        }
+        return r;
+}
+MODULE_AUTHOR("Vladislav Buzov");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
new file mode 100644
index 000000000000..063c7bc0e740
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/timer.c
@@ -0,0 +1,189 @@
+/*
+ * System timer for Freescale STMP37XX/STMP378X
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/mach/time.h>
+#include <mach/stmp3xxx.h>
+#include <mach/platform.h>
+#include <mach/regs-timrot.h>
+static irqreturn_t
+stmp3xxx_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *c = dev_id;
+        /* timer 0 */
+        if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
+                        BM_TIMROT_TIMCTRLn_IRQ) {
+                stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+                                REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+                c->event_handler(c);
+        }
+        /* timer 1 */
+        else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
+                        & BM_TIMROT_TIMCTRLn_IRQ) {
+                stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+                                REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+                stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+                                REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+                __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
+        }
+        return IRQ_HANDLED;
+}
+static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
+{
+        return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
+                                & 0xFFFF0000) >> 16);
+}
+static int
+stmp3xxx_timrot_set_next_event(unsigned long delta,
+                struct clock_event_device *dev)
+{
+        /* reload the timer */
+        __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+        return 0;
+}
+static void
+stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
+                struct clock_event_device *dev)
+{
+}
+static struct clock_event_device ckevt_timrot = {
+        .name           = "timrot",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_next_event = stmp3xxx_timrot_set_next_event,
+        .set_mode       = stmp3xxx_timrot_set_mode,
+};
+static struct clocksource cksrc_stmp3xxx = {
+        .name           = "cksrc_stmp3xxx",
+        .rating         = 250,
+        .read           = stmp3xxx_clock_read,
+        .mask           = CLOCKSOURCE_MASK(16),
+        .shift          = 10,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static struct irqaction stmp3xxx_timer_irq = {
+        .name           = "stmp3xxx_timer",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = stmp3xxx_timer_interrupt,
+        .dev_id         = &ckevt_timrot,
+};
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+static void __init stmp3xxx_init_timer(void)
+{
+        cksrc_stmp3xxx.mult = clocksource_hz2mult(CLOCK_TICK_RATE,
+                                cksrc_stmp3xxx.shift);
+        ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
+                                ckevt_timrot.shift);
+        ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
+        ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
+        ckevt_timrot.cpumask = cpumask_of(0);
+        stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
+        /* clear two timers */
+        __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+        __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
+        /* configure them */
+        __raw_writel(
+                (8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
+                BM_TIMROT_TIMCTRLn_RELOAD |
+                BM_TIMROT_TIMCTRLn_UPDATE |
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+        __raw_writel(
+                (8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
+                BM_TIMROT_TIMCTRLn_RELOAD |
+                BM_TIMROT_TIMCTRLn_UPDATE |
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+        __raw_writel(CLOCK_TICK_RATE / HZ - 1,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+        __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
+        setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
+        clocksource_register(&cksrc_stmp3xxx);
+        clockevents_register_device(&ckevt_timrot);
+}
+#ifdef CONFIG_PM
+void stmp3xxx_suspend_timer(void)
+{
+        stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+        stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
+                        REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+}
+void stmp3xxx_resume_timer(void)
+{
+        stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
+                        REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+        __raw_writel(
+                8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
+                BM_TIMROT_TIMCTRLn_RELOAD |
+                BM_TIMROT_TIMCTRLn_UPDATE |
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+        __raw_writel(
+                8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
+                BM_TIMROT_TIMCTRLn_RELOAD |
+                BM_TIMROT_TIMCTRLn_UPDATE |
+                BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+        __raw_writel(CLOCK_TICK_RATE / HZ - 1,
+                        REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+        __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
+}
+#else
+#define stmp3xxx_suspend_timer  NULL
+#define stmp3xxx_resume_timer   NULL
+#endif  /* CONFIG_PM */
+struct sys_timer stmp3xxx_timer = {
+        .init           = stmp3xxx_init_timer,
+        .suspend        = stmp3xxx_suspend_timer,
+        .resume         = stmp3xxx_resume_timer,
+};
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 83c4e384b16d..1aeae38725dd 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -100,6 +100,7 @@ ENTRY(vfp_support_entry)
        beq     no_old_VFP_process
        VFPFSTMIA r4, r5                @ save the working registers
        VFPFMRX r5, FPSCR               @ current status
+#ifndef CONFIG_CPU_FEROCEON
        tst     r1, #FPEXC_EX           @ is there additional state to save?
        beq     1f
        VFPFMRX r6, FPINST              @ FPINST (only if FPEXC.EX is set)
@@ -107,6 +108,7 @@ ENTRY(vfp_support_entry)
        beq     1f
        VFPFMRX r8, FPINST2             @ FPINST2 if needed (and present)
 1:
+#endif
        stmia   r4, {r1, r5, r6, r8}    @ save FPEXC, FPSCR, FPINST, FPINST2
                                        @ and point r4 at the word at the
                                        @ start of the register dump
@@ -119,6 +121,7 @@ no_old_VFP_process:
        VFPFLDMIA r10, r5               @ reload the working registers while
                                        @ FPEXC is in a safe state
        ldmia   r10, {r1, r5, r6, r8}   @ load FPEXC, FPSCR, FPINST, FPINST2
+#ifndef CONFIG_CPU_FEROCEON
        tst     r1, #FPEXC_EX           @ is there additional state to restore?
        beq     1f
        VFPFMXR FPINST, r6              @ restore FPINST (only if FPEXC.EX is set)
@@ -126,6 +129,7 @@ no_old_VFP_process:
        beq     1f
        VFPFMXR FPINST2, r8             @ FPINST2 if needed (and present)
 1:
+#endif
        VFPFMXR FPSCR, r5               @ restore status
 check_for_exception:
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 01599c4ef726..2d7423af1197 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -253,12 +253,14 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
        }
        if (fpexc & FPEXC_EX) {
+#ifndef CONFIG_CPU_FEROCEON
                /*
                 * Asynchronous exception. The instruction is read from FPINST
                 * and the interrupted instruction has to be restarted.
                 */
                trigger = fmrx(FPINST);
                regs->ARM_pc -= 4;
+#endif
        } else if (!(fpexc & FPEXC_DEX)) {
                /*
                 * Illegal combination of bits. It can be caused by an
diff --git a/arch/avr32/kernel/init_task.c b/arch/avr32/kernel/init_task.c
index 993d56ee3cf3..57ec9f2dcd95 100644
--- a/arch/avr32/kernel/init_task.c
+++ b/arch/avr32/kernel/init_task.c
@@ -15,10 +15,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure. Must be aligned on an 8192-byte boundary.
 */
diff --git a/arch/avr32/kernel/signal.c b/arch/avr32/kernel/signal.c
index 803d7be0938f..27227561bad6 100644
--- a/arch/avr32/kernel/signal.c
+++ b/arch/avr32/kernel/signal.c
@@ -212,7 +212,7 @@ out:
        return err;
 }
-static inline void restart_syscall(struct pt_regs *regs)
+static inline void setup_syscall_restart(struct pt_regs *regs)
 {
        if (regs->r12 == -ERESTART_RESTARTBLOCK)
                regs->r8 = __NR_restart_syscall;
@@ -296,7 +296,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset, int syscall)
                        }
                        /* fall through */
                case -ERESTARTNOINTR:
-                        restart_syscall(regs);
+                        setup_syscall_restart(regs);
                }
        }
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c56fd3eb7c10..8ea0d942cdea 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -6,59 +6,65 @@
 mainmenu "Blackfin Kernel Configuration"
 config MMU
-        bool
+        def_bool n
-        default n
 config FPU
-        bool
+        def_bool n
-        default n
 config RWSEM_GENERIC_SPINLOCK
-        bool
+        def_bool y
-        default y
 config RWSEM_XCHGADD_ALGORITHM
-        bool
+        def_bool n
-        default n
 config BLACKFIN
-        bool
+        def_bool y
-        default y
+        select HAVE_FUNCTION_GRAPH_TRACER
+        select HAVE_FUNCTION_TRACER
        select HAVE_IDE
+        select HAVE_KERNEL_GZIP
+        select HAVE_KERNEL_BZIP2
+        select HAVE_KERNEL_LZMA
        select HAVE_OPROFILE
        select ARCH_WANT_OPTIONAL_GPIOLIB
+config GENERIC_BUG
+        def_bool y
+        depends on BUG
 config ZONE_DMA
-        bool
+        def_bool y
-        default y
 config GENERIC_FIND_NEXT_BIT
-        bool
+        def_bool y
-        default y
 config GENERIC_HWEIGHT
-        bool
+        def_bool y
-        default y
 config GENERIC_HARDIRQS
-        bool
+        def_bool y
-        default y
 config GENERIC_IRQ_PROBE
-        bool
+        def_bool y
-        default y
 config GENERIC_GPIO
-        bool
+        def_bool y
-        default y
 config FORCE_MAX_ZONEORDER
        int
        default "14"
 config GENERIC_CALIBRATE_DELAY
-        bool
+        def_bool y
-        default y
+config LOCKDEP_SUPPORT
+        def_bool y
+config STACKTRACE_SUPPORT
+        def_bool y
+config TRACE_IRQFLAGS_SUPPORT
+        def_bool y
 source "init/Kconfig"
@@ -408,12 +414,12 @@ comment "Clock/PLL Setup"
 config CLKIN_HZ
        int "Frequency of the crystal on the board in Hz"
+        default "10000000" if BFIN532_IP0X
        default "11059200" if BFIN533_STAMP
+        default "24576000" if PNAV10
+        default "25000000" # most people use this
        default "27000000" if BFIN533_EZKIT
-        default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
        default "30000000" if BFIN561_EZKIT
-        default "24576000" if PNAV10
-        default "10000000" if BFIN532_IP0X
        help
          The frequency of CLKIN crystal oscillator on the board in Hz.
          Warning: This value should match the crystal on the board. Otherwise,
@@ -885,7 +891,7 @@ config BFIN_GPTIMERS
          are unsure, say N.
          To compile this driver as a module, choose M here: the module
-          will be called gptimers.ko.
+          will be called gptimers.
 choice
        prompt "Uncached DMA region"
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index d54c8283825c..6f9533c3d752 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -137,7 +137,7 @@ archclean:
 INSTALL_PATH ?= /tftpboot
 boot := arch/$(ARCH)/boot
-BOOT_TARGETS = vmImage
+BOOT_TARGETS = vmImage vmImage.bz2 vmImage.gz vmImage.lzma
 PHONY += $(BOOT_TARGETS) install
 KBUILD_IMAGE := $(boot)/vmImage
@@ -150,7 +150,10 @@ install:
        $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install
 define archhelp
-  echo  '* vmImage         - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage)'
+  echo  '* vmImage         - Alias to selected kernel format (vmImage.gz by default)'
+  echo  '  vmImage.bz2     - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
+  echo  '* vmImage.gz      - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
+  echo  '  vmImage.lzma    - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
  echo  '  install         - Install kernel using'
  echo  '                     (your) ~/bin/$(CROSS_COMPILE)installkernel or'
  echo  '                     (distribution) PATH: $(CROSS_COMPILE)installkernel or'
diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore
index 3ae03994b88d..229e50808677 100644
--- a/arch/blackfin/boot/.gitignore
+++ b/arch/blackfin/boot/.gitignore
@@ -1 +1,2 @@
-+vmImage
+vmImage*
+vmlinux*
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index e028d13481a9..3ab6f23561dd 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -8,24 +8,41 @@
 MKIMAGE := $(srctree)/scripts/mkuboot.sh
-targets := vmImage
+targets := vmImage vmImage.bz2 vmImage.gz vmImage.lzma
-extra-y += vmlinux.bin vmlinux.gz
+extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
 quiet_cmd_uimage = UIMAGE  $@
      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-                   -C gzip -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
+                   -C $(2) -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
                   -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
                   -d $< $@
 $(obj)/vmlinux.bin: vmlinux FORCE
        $(call if_changed,objcopy)
-$(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
+$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
        $(call if_changed,gzip)
-$(obj)/vmImage: $(obj)/vmlinux.gz
+$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
-        $(call if_changed,uimage)
+        $(call if_changed,bzip2)
-        @$(kecho) 'Kernel: $@ is ready'
+$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,lzma)
+$(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2
+        $(call if_changed,uimage,bzip2)
+$(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
+        $(call if_changed,uimage,gzip)
+$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
+        $(call if_changed,uimage,lzma)
+suffix-$(CONFIG_KERNEL_GZIP)  := gz
+suffix-$(CONFIG_KERNEL_BZIP2) := bz2
+suffix-$(CONFIG_KERNEL_LZMA)  := lzma
+$(obj)/vmImage: $(obj)/vmImage.$(suffix-y)
+        @ln -sf $(notdir $<) $@
 install:
        sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index 7bbf44e4ddf9..b1d92f13ef96 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -90,7 +90,7 @@ static inline int atomic_test_mask(int mask, atomic_t *v)
 static inline void atomic_add(int i, atomic_t *v)
 {
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter += i;
@@ -99,7 +99,7 @@ static inline void atomic_add(int i, atomic_t *v)
 static inline void atomic_sub(int i, atomic_t *v)
 {
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter -= i;
@@ -110,7 +110,7 @@ static inline void atomic_sub(int i, atomic_t *v)
 static inline int atomic_add_return(int i, atomic_t *v)
 {
        int __temp = 0;
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter += i;
@@ -124,7 +124,7 @@ static inline int atomic_add_return(int i, atomic_t *v)
 static inline int atomic_sub_return(int i, atomic_t *v)
 {
        int __temp = 0;
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter -= i;
@@ -136,7 +136,7 @@ static inline int atomic_sub_return(int i, atomic_t *v)
 static inline void atomic_inc(volatile atomic_t *v)
 {
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter++;
@@ -145,7 +145,7 @@ static inline void atomic_inc(volatile atomic_t *v)
 static inline void atomic_dec(volatile atomic_t *v)
 {
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter--;
@@ -154,7 +154,7 @@ static inline void atomic_dec(volatile atomic_t *v)
 static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
 {
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter &= ~mask;
@@ -163,7 +163,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
 static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-        long flags;
+        unsigned long flags;
        local_irq_save_hw(flags);
        v->counter |= mask;
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index daffc0684e75..e39277ea43e8 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -31,7 +31,7 @@
 #ifndef __ASSEMBLY__
-#include <asm-generic/sections.h>
+#include <asm/sections.h>
 #include <asm/ptrace.h>
 #include <asm/user.h>
 #include <linux/linkage.h>
@@ -99,15 +99,6 @@ extern const char bfin_board_name[];
 extern unsigned long bfin_sic_iwr[];
 extern unsigned vr_wakeup;
 extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
-extern unsigned long _ramstart, _ramend, _rambase;
-extern unsigned long memory_start, memory_end, physical_mem_end;
-extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
-        _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
-        _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
-        _ebss_l2[], _l2_lma_start[];
-/* only used when MTD_UCLINUX */
-extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
 #ifdef CONFIG_BFIN_ICACHE_LOCK
 extern void cache_grab_lock(int way);
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 21b036eadab1..75fee2f7d9f2 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -109,7 +109,8 @@ static inline void clear_bit(int nr, volatile unsigned long *addr)
 static inline void change_bit(int nr, volatile unsigned long *addr)
 {
-        int mask, flags;
+        int mask;
+        unsigned long flags;
        unsigned long *ADDR = (unsigned long *)addr;
        ADDR += nr >> 5;
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
index 6d3e11b1fc57..655e49540e41 100644
--- a/arch/blackfin/include/asm/bug.h
+++ b/arch/blackfin/include/asm/bug.h
@@ -2,13 +2,58 @@
 #define _BLACKFIN_BUG_H
 #ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
-#define BUG() do { \
+#define BFIN_BUG_OPCODE 0xefcd
-        dump_bfin_trace_buffer(); \
-        printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
+#ifdef CONFIG_DEBUG_BUGVERBOSE
-        panic("BUG!"); \
-} while (0)
+#define _BUG_OR_WARN(flags)                                             \
+        asm volatile(                                                   \
+                "1:     .hword  %0\n"                                   \
+                "       .section __bug_table,\"a\",@progbits\n"         \
+                "2:     .long   1b\n"                                   \
+                "       .long   %1\n"                                   \
+                "       .short  %2\n"                                   \
+                "       .short  %3\n"                                   \
+                "       .org    2b + %4\n"                              \
+                "       .previous"                                      \
+                :                                                       \
+                : "i"(BFIN_BUG_OPCODE), "i"(__FILE__),                  \
+                  "i"(__LINE__), "i"(flags),                            \
+                  "i"(sizeof(struct bug_entry)))
+#else
+#define _BUG_OR_WARN(flags)                                             \
+        asm volatile(                                                   \
+                "1:     .hword  %0\n"                                   \
+                "       .section __bug_table,\"a\",@progbits\n"         \
+                "2:     .long   1b\n"                                   \
+                "       .short  %1\n"                                   \
+                "       .org    2b + %2\n"                              \
+                "       .previous"                                      \
+                :                                                       \
+                : "i"(BFIN_BUG_OPCODE), "i"(flags),                     \
+                  "i"(sizeof(struct bug_entry)))
+#endif /* CONFIG_DEBUG_BUGVERBOSE */
+#define BUG()                                                           \
+        do {                                                            \
+                _BUG_OR_WARN(0);                                        \
+                for (;;);                                               \
+        } while (0)
+#define WARN_ON(condition)                                                      \
+        ({                                                              \
+                int __ret_warn_on = !!(condition);                      \
+                if (unlikely(__ret_warn_on))                            \
+                        _BUG_OR_WARN(BUGFLAG_WARNING);                  \
+                unlikely(__ret_warn_on);                                \
+        })
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_WARN_ON
 #endif
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 86637814cf25..2ef669ed9222 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -34,9 +34,13 @@
 #define L1_CACHE_SHIFT_MAX      5
 #if defined(CONFIG_SMP) && \
-    !defined(CONFIG_BFIN_CACHE_COHERENT) && \
+    !defined(CONFIG_BFIN_CACHE_COHERENT)
-    defined(CONFIG_BFIN_DCACHE)
+# if defined(CONFIG_BFIN_ICACHE)
-#define __ARCH_SYNC_CORE_DCACHE
+# define __ARCH_SYNC_CORE_ICACHE
+# endif
+# if defined(CONFIG_BFIN_DCACHE)
+# define __ARCH_SYNC_CORE_DCACHE
+# endif
 #ifndef __ASSEMBLY__
 asmlinkage void __raw_smp_mark_barrier_asm(void);
 asmlinkage void __raw_smp_check_barrier_asm(void);
@@ -51,6 +55,7 @@ static inline void smp_check_barrier(void)
 }
 void resync_core_dcache(void);
+void resync_core_icache(void);
 #endif
 #endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 94697f0f6f40..5c17dee53b5d 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -37,6 +37,7 @@ extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned lo
 extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dflush_page(void *page);
 extern void blackfin_invalidate_entire_dcache(void);
+extern void blackfin_invalidate_entire_icache(void);
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
@@ -97,7 +98,7 @@ do { memcpy(dst, src, len);						\
 extern unsigned long reserved_mem_dcache_on;
 extern unsigned long reserved_mem_icache_on;
-static inline int bfin_addr_dcachable(unsigned long addr)
+static inline int bfin_addr_dcacheable(unsigned long addr)
 {
 #ifdef CONFIG_BFIN_DCACHE
        if (addr < (_ramend - DMA_UNCACHED_REGION))
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index c2594ef877f6..565b8136855e 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -34,6 +34,7 @@ struct blackfin_cpudata {
        unsigned int dmemctl;
        unsigned long loops_per_jiffy;
        unsigned long dcache_invld_count;
+        unsigned long icache_invld_count;
 };
 DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
index 40a8c178f10d..8643680f0f78 100644
--- a/arch/blackfin/include/asm/ftrace.h
+++ b/arch/blackfin/include/asm/ftrace.h
@@ -1 +1,13 @@
-/* empty */
+/*
+ * Blackfin ftrace code
+ *
+ * Copyright 2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_BFIN_FTRACE_H__
+#define __ASM_BFIN_FTRACE_H__
+#define MCOUNT_INSN_SIZE        8 /* sizeof mcount call: LINK + CALL */
+#endif
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 51d0bf5e2899..bbe1c3726b69 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,10 +35,10 @@
 #include <asm/atomic.h>
 #include <asm/traps.h>
-#define IPIPE_ARCH_STRING     "1.9-01"
+#define IPIPE_ARCH_STRING     "1.10-00"
 #define IPIPE_MAJOR_NUMBER    1
-#define IPIPE_MINOR_NUMBER    9
+#define IPIPE_MINOR_NUMBER    10
-#define IPIPE_PATCH_NUMBER    1
+#define IPIPE_PATCH_NUMBER    0
 #ifdef CONFIG_SMP
 #error "I-pipe/blackfin: SMP not implemented"
@@ -54,10 +54,11 @@ do {						\
 #define task_hijacked(p)                                                \
        ({                                                              \
-                int __x__ = ipipe_current_domain != ipipe_root_domain;  \
+                int __x__ = __ipipe_root_domain_p;                      \
-                /* We would need to clear the SYNC flag for the root domain */ \
+                __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
-                /* over the current processor in SMP mode. */           \
+                if (__x__)                                              \
-                local_irq_enable_hw(); __x__;                           \
+                        local_irq_enable_hw();                          \
+                !__x__;                                                 \
        })
 struct ipipe_domain;
@@ -179,23 +180,24 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
 #define __ipipe_run_isr(ipd, irq)                                       \
        do {                                                            \
-                if (ipd == ipipe_root_domain) {                         \
+                if (!__ipipe_pipeline_head_p(ipd))                      \
                        local_irq_enable_hw();                          \
-                        if (ipipe_virtual_irq_p(irq))                   \
+                if (ipd == ipipe_root_domain) {                         \
+                        if (unlikely(ipipe_virtual_irq_p(irq))) {       \
+                                irq_enter();                            \
                                ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
-                        else                                            \
+                                irq_exit();                             \
+                        } else                                          \
                                ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
-                        local_irq_disable_hw();                         \
                } else {                                                \
                        __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
-                        local_irq_enable_nohead(ipd);                   \
                        ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
                        /* Attempt to exit the outer interrupt level before \
                         * starting the deferred IRQ processing. */     \
-                        local_irq_disable_nohead(ipd);                  \
                        __ipipe_run_irqtail();                          \
                        __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
                }                                                       \
+                local_irq_disable_hw();                                 \
        } while (0)
 #define __ipipe_syscall_watched_p(p, sc)        \
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 7645e85a5f6f..400bdd52ce87 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -17,270 +17,17 @@
 #ifndef _BFIN_IRQ_H_
 #define _BFIN_IRQ_H_
-/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/
+#include <linux/irqflags.h>
-#include <mach/irq.h>
-#include <asm/pda.h>
-#include <asm/processor.h>
-#ifdef CONFIG_SMP
-/* Forward decl needed due to cdef inter dependencies */
-static inline uint32_t __pure bfin_dspid(void);
-# define blackfin_core_id() (bfin_dspid() & 0xff)
-# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
-#else
-extern unsigned long bfin_irq_flags;
-#endif
-#ifdef CONFIG_IPIPE
-#include <linux/ipipe_trace.h>
-void __ipipe_unstall_root(void);
+/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
+#include <mach/irq.h>
-void __ipipe_restore_root(unsigned long flags);
-#ifdef CONFIG_DEBUG_HWERR
-# define __all_masked_irq_flags 0x3f
-# define __save_and_cli_hw(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %1;" \
-                : "=&d"(x) \
-                : "d" (0x3F) \
-        )
-#else
-# define __all_masked_irq_flags 0x1f
-# define __save_and_cli_hw(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                : "=&d"(x) \
-        )
-#endif
-#define irqs_enabled_from_flags_hw(x)   ((x) != __all_masked_irq_flags)
-#define raw_irqs_disabled_flags(flags)  (!irqs_enabled_from_flags_hw(flags))
-#define local_test_iflag_hw(x)          irqs_enabled_from_flags_hw(x)
-#define local_save_flags(x)                                      \
-        do {                                                     \
-                (x) = __ipipe_test_root() ?                      \
-                        __all_masked_irq_flags : bfin_irq_flags; \
-                barrier();                                       \
-        } while (0)
-#define local_irq_save(x)                                        \
-        do {                                                     \
-                (x) = __ipipe_test_and_stall_root() ?            \
-                        __all_masked_irq_flags : bfin_irq_flags; \
-                barrier();                                       \
-        } while (0)
-static inline void local_irq_restore(unsigned long x)
-{
-        barrier();
-        __ipipe_restore_root(x == __all_masked_irq_flags);
-}
-#define local_irq_disable()                     \
-        do {                                    \
-                __ipipe_stall_root();           \
-                barrier();                      \
-        } while (0)
-static inline void local_irq_enable(void)
-{
-        barrier();
-        __ipipe_unstall_root();
-}
-#define irqs_disabled()         __ipipe_test_root()
-#define local_save_flags_hw(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %0;" \
-                : "=d"(x) \
-        )
-#define irqs_disabled_hw()                              \
-        ({                                              \
-                unsigned long flags;                    \
-                local_save_flags_hw(flags);             \
-                !irqs_enabled_from_flags_hw(flags);     \
-        })
-static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
-{
-        /* Merge virtual and real interrupt mask bits into a single
-           32bit word. */
-        return (real & ~(1 << 31)) | ((virt != 0) << 31);
-}
-static inline int raw_demangle_irq_bits(unsigned long *x)
-{
-        int virt = (*x & (1 << 31)) != 0;
-        *x &= ~(1L << 31);
-        return virt;
-}
-#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
-#define local_irq_disable_hw()                                          \
-        do {                                                            \
-                int _tmp_dummy;                                         \
-                if (!irqs_disabled_hw())                                \
-                        ipipe_trace_begin(0x80000000);                  \
-                __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : );        \
-        } while (0)
-#define local_irq_enable_hw()                                           \
-        do {                                                            \
-                if (irqs_disabled_hw())                                 \
-                        ipipe_trace_end(0x80000000);                    \
-                __asm__ __volatile__ ("sti %0;" : : "d"(bfin_irq_flags));       \
-        } while (0)
-#define local_irq_save_hw(x)                            \
-        do {                                            \
-                __save_and_cli_hw(x);                   \
-                if (local_test_iflag_hw(x))             \
-                        ipipe_trace_begin(0x80000001);  \
-        } while (0)
-#define local_irq_restore_hw(x)                         \
-        do {                                            \
-                if (local_test_iflag_hw(x)) {           \
-                        ipipe_trace_end(0x80000001);    \
-                        local_irq_enable_hw_notrace();  \
-                }                                       \
-        } while (0)
-#define local_irq_disable_hw_notrace()                                  \
-        do {                                                            \
-                int _tmp_dummy;                                         \
-                __asm__ __volatile__ ("cli %0;" : "=d" (_tmp_dummy) : );        \
-        } while (0)
-#define local_irq_enable_hw_notrace() \
-        __asm__ __volatile__( \
-                "sti %0;" \
-                : \
-                : "d"(bfin_irq_flags) \
-        )
-#define local_irq_save_hw_notrace(x) __save_and_cli_hw(x)
-#define local_irq_restore_hw_notrace(x)                 \
-        do {                                            \
-                if (local_test_iflag_hw(x))             \
-                        local_irq_enable_hw_notrace();  \
-        } while (0)
-#else /* CONFIG_IPIPE_TRACE_IRQSOFF */
-#define local_irq_enable_hw() \
-        __asm__ __volatile__( \
-                "sti %0;" \
-                : \
-                : "d"(bfin_irq_flags) \
-        )
-#define local_irq_disable_hw()                  \
-        do {                                    \
-                int _tmp_dummy;                 \
-                __asm__ __volatile__ (          \
-                        "cli %0;"               \
-                        : "=d" (_tmp_dummy));   \
-        } while (0)
-#define local_irq_restore_hw(x) \
-        do { \
-                if (irqs_enabled_from_flags_hw(x)) \
-                        local_irq_enable_hw(); \
-        } while (0)
-#define local_irq_save_hw(x)            __save_and_cli_hw(x)
-#define local_irq_disable_hw_notrace()  local_irq_disable_hw()
-#define local_irq_enable_hw_notrace()   local_irq_enable_hw()
-#define local_irq_save_hw_notrace(x)    local_irq_save_hw(x)
-#define local_irq_restore_hw_notrace(x) local_irq_restore_hw(x)
-#endif  /* CONFIG_IPIPE_TRACE_IRQSOFF */
-#else /* !CONFIG_IPIPE */
-/*
- * Interrupt configuring macros.
- */
-#define local_irq_disable() \
-        do { \
-                int __tmp_dummy; \
-                __asm__ __volatile__( \
-                        "cli %0;" \
-                        : "=d" (__tmp_dummy) \
-                ); \
-        } while (0)
-#define local_irq_enable() \
-        __asm__ __volatile__( \
-                "sti %0;" \
-                : \
-                : "d" (bfin_irq_flags) \
-        )
-#ifdef CONFIG_DEBUG_HWERR
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %1;" \
-                : "=&d" (x) \
-                : "d" (0x3F) \
-        )
-#else
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                : "=&d" (x) \
-        )
-#endif
-#define local_save_flags(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %0;" \
-                : "=d" (x) \
-        )
-#ifdef CONFIG_DEBUG_HWERR
-#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
-#else
-#define irqs_enabled_from_flags(x) ((x) != 0x1f)
-#endif
-#define local_irq_restore(x) \
-        do { \
-                if (irqs_enabled_from_flags(x)) \
-                        local_irq_enable(); \
-        } while (0)
-/* For spinlocks etc */
-#define local_irq_save(x) __save_and_cli(x)
-#define irqs_disabled()                         \
-({                                              \
-        unsigned long flags;                    \
-        local_save_flags(flags);                \
-        !irqs_enabled_from_flags(flags);        \
-})
-#define local_irq_save_hw(x)            local_irq_save(x)
-#define local_irq_restore_hw(x)         local_irq_restore(x)
-#define local_irq_enable_hw()           local_irq_enable()
-#define local_irq_disable_hw()          local_irq_disable()
-#define irqs_disabled_hw()              irqs_disabled()
-#endif /* !CONFIG_IPIPE */
+/* Xenomai IPIPE helpers */
+#define local_irq_restore_hw(x) local_irq_restore(x)
+#define local_irq_save_hw(x)    local_irq_save(x)
+#define local_irq_enable_hw(x)  local_irq_enable(x)
+#define local_irq_disable_hw(x) local_irq_disable(x)
+#define irqs_disabled_hw(x)     irqs_disabled(x)
 #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
 # define NOP_PAD_ANOMALY_05000244 "nop; nop;"
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
new file mode 100644
index 000000000000..139cba4651b1
--- /dev/null
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -0,0 +1,63 @@
+/*
+ * interface to Blackfin CEC
+ *
+ * Copyright 2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_BFIN_IRQFLAGS_H__
+#define __ASM_BFIN_IRQFLAGS_H__
+#ifdef CONFIG_SMP
+# include <asm/pda.h>
+# include <asm/processor.h>
+/* Forward decl needed due to cdef inter dependencies */
+static inline uint32_t __pure bfin_dspid(void);
+# define blackfin_core_id() (bfin_dspid() & 0xff)
+# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
+#else
+extern unsigned long bfin_irq_flags;
+#endif
+static inline void bfin_sti(unsigned long flags)
+{
+        asm volatile("sti %0;" : : "d" (flags));
+}
+static inline unsigned long bfin_cli(void)
+{
+        unsigned long flags;
+        asm volatile("cli %0;" : "=d" (flags));
+        return flags;
+}
+static inline void raw_local_irq_disable(void)
+{
+        bfin_cli();
+}
+static inline void raw_local_irq_enable(void)
+{
+        bfin_sti(bfin_irq_flags);
+}
+#define raw_local_save_flags(flags) do { (flags) = bfin_read_IMASK(); } while (0)
+#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0)
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        if (!raw_irqs_disabled_flags(flags))
+                raw_local_irq_enable();
+}
+static inline unsigned long __raw_local_irq_save(void)
+{
+        unsigned long flags = bfin_cli();
+#ifdef CONFIG_DEBUG_HWERR
+        bfin_sti(0x3f);
+#endif
+        return flags;
+}
+#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
+#endif
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h
index e215f7104974..0a88622339ee 100644
--- a/arch/blackfin/include/asm/kmap_types.h
+++ b/arch/blackfin/include/asm/kmap_types.h
@@ -1,21 +1,6 @@
 #ifndef _ASM_KMAP_TYPES_H
 #define _ASM_KMAP_TYPES_H
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
 #endif
diff --git a/arch/blackfin/include/asm/mutex-dec.h b/arch/blackfin/include/asm/mutex-dec.h
deleted file mode 100644
index 0134151656af..000000000000
--- a/arch/blackfin/include/asm/mutex-dec.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * include/asm-generic/mutex-dec.h
- *
- * Generic implementation of the mutex fastpath, based on atomic
- * decrement/increment.
- */
-#ifndef _ASM_GENERIC_MUTEX_DEC_H
-#define _ASM_GENERIC_MUTEX_DEC_H
-/**
- *  __mutex_fastpath_lock - try to take the lock by moving the count
- *                          from 1 to a 0 value
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
- *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function MUST leave the value lower than
- * 1 even when the "1" assertion wasn't true.
- */
-static inline void
-__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
-{
-        if (unlikely(atomic_dec_return(count) < 0))
-                fail_fn(count);
-        else
-                smp_mb();
-}
-/**
- *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
- *                                 from 1 to a 0 value
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
- *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns.
- */
-static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *))
-{
-        if (unlikely(atomic_dec_return(count) < 0))
-                return fail_fn(count);
-        else {
-                smp_mb();
-                return 0;
-        }
-}
-/**
- *  __mutex_fastpath_unlock - try to promote the count from 0 to 1
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 0
- *
- * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>.
- * In the failure case, this function is allowed to either set the value to
- * 1, or to set it to a value lower than 1.
- *
- * If the implementation sets it to a value of lower than 1, then the
- * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
- * to return 0 otherwise.
- */
-static inline void
-__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
-{
-        smp_mb();
-        if (unlikely(atomic_inc_return(count) <= 0))
-                fail_fn(count);
-}
-#define __mutex_slowpath_needs_to_unlock()              1
-/**
- * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
- *
- *  @count: pointer of type atomic_t
- *  @fail_fn: fallback function
- *
- * Change the count from 1 to a value lower than 1, and return 0 (failure)
- * if it wasn't 1 originally, or return 1 (success) otherwise. This function
- * MUST leave the value lower than 1 even when the "1" assertion wasn't true.
- * Additionally, if the value was < 0 originally, this function must not leave
- * it to 0 on failure.
- *
- * If the architecture has no effective trylock variant, it should call the
- * <fail_fn> spinlock-based trylock variant unconditionally.
- */
-static inline int
-__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-        /*
-         * We have two variants here. The cmpxchg based one is the best one
-         * because it never induce a false contention state.  It is included
-         * here because architectures using the inc/dec algorithms over the
-         * xchg ones are much more likely to support cmpxchg natively.
-         *
-         * If not we fall back to the spinlock based variant - that is
-         * just as efficient (and simpler) as a 'destructive' probing of
-         * the mutex state would be.
-         */
-#ifdef __HAVE_ARCH_CMPXCHG
-        if (likely(atomic_cmpxchg(count, 1, 0) == 1)) {
-                smp_mb();
-                return 1;
-        }
-        return 0;
-#else
-        return fail_fn(count);
-#endif
-}
-#endif
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 1443c3353a8c..e7fd0ecd73f7 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -4,4 +4,15 @@
 /* nothing to see, move along */
 #include <asm-generic/sections.h>
+/* only used when MTD_UCLINUX */
+extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
+extern unsigned long _ramstart, _ramend, _rambase;
+extern unsigned long memory_start, memory_end, physical_mem_end;
+extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
+        _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
+        _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
+        _ebss_l2[], _l2_lma_start[];
 #endif
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index a4c8254bec55..294dbda24164 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -35,10 +35,10 @@
 #define _BLACKFIN_SYSTEM_H
 #include <linux/linkage.h>
-#include <linux/compiler.h>
+#include <linux/irqflags.h>
 #include <mach/anomaly.h>
+#include <asm/cache.h>
 #include <asm/pda.h>
-#include <asm/processor.h>
 #include <asm/irq.h>
 /*
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index cf5066d3efd2..da35133c171d 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -380,8 +380,9 @@
 #define __NR_inotify_init1      365
 #define __NR_preadv             366
 #define __NR_pwritev            367
+#define __NR_rt_tgsigqueueinfo  368
-#define __NR_syscall            368
+#define __NR_syscall            369
 #define NR_syscalls             __NR_syscall
 /* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index fd4d4328a0f2..3731088e181b 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -15,6 +15,10 @@ else
    obj-y += time.o
 endif
+obj-$(CONFIG_FUNCTION_TRACER)        += ftrace-entry.o
+obj-$(CONFIG_FUNCTION_GRAPH_TRACER)  += ftrace.o
+CFLAGS_REMOVE_ftrace.o = -pg
 obj-$(CONFIG_IPIPE)                  += ipipe.o
 obj-$(CONFIG_IPIPE_TRACE_MCOUNT)     += mcount.o
 obj-$(CONFIG_BFIN_GPTIMERS)          += gptimers.o
@@ -23,6 +27,7 @@ obj-$(CONFIG_MODULES)                += module.o
 obj-$(CONFIG_KGDB)                   += kgdb.o
 obj-$(CONFIG_KGDB_TESTS)             += kgdb_test.o
 obj-$(CONFIG_EARLY_PRINTK)           += early_printk.o
+obj-$(CONFIG_STACKTRACE)             += stacktrace.o
 # the kgdb test puts code into L2 and without linker
 # relaxation, we need to force long calls to/from it
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 763ed84ba459..e0bf8cc06907 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -453,10 +453,10 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size)
        unsigned long src = (unsigned long)psrc;
        size_t bulk, rest;
-        if (bfin_addr_dcachable(src))
+        if (bfin_addr_dcacheable(src))
                blackfin_dcache_flush_range(src, src + size);
-        if (bfin_addr_dcachable(dst))
+        if (bfin_addr_dcacheable(dst))
                blackfin_dcache_invalidate_range(dst, dst + size);
        bulk = size & ~0xffff;
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index 53e893ff708a..aa05e638fb7c 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -103,3 +103,8 @@ EXPORT_SYMBOL(__raw_smp_mark_barrier_asm);
 EXPORT_SYMBOL(__raw_smp_check_barrier_asm);
 #endif
 #endif
+#ifdef CONFIG_FUNCTION_TRACER
+extern void _mcount(void);
+EXPORT_SYMBOL(_mcount);
+#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 87463ce87f5a..784923e52a9a 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -151,7 +151,7 @@ static noinline int dcplb_miss(unsigned int cpu)
        d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
 #ifdef CONFIG_BFIN_DCACHE
-        if (bfin_addr_dcachable(addr)) {
+        if (bfin_addr_dcacheable(addr)) {
                d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
 #ifdef CONFIG_BFIN_WT
                d_data |= CPLB_L1_AOW | CPLB_WT;
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
index 8cbb47c7b663..12b030842fdb 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
@@ -28,6 +28,7 @@
 #include <asm/cplbinit.h>
 #include <asm/cplb.h>
 #include <asm/mmu_context.h>
+#include <asm/traps.h>
 /*
 * WARNING
@@ -100,28 +101,6 @@ static inline void write_icplb_data(int cpu, int idx, unsigned long data,
 #endif
 }
-/*
- * Given the contents of the status register, return the index of the
- * CPLB that caused the fault.
- */
-static inline int faulting_cplb_index(int status)
-{
-        int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
-        return 30 - signbits;
-}
-/*
- * Given the contents of the status register and the DCPLB_DATA contents,
- * return true if a write access should be permitted.
- */
-static inline int write_permitted(int status, unsigned long data)
-{
-        if (status & FAULT_USERSUPV)
-                return !!(data & CPLB_SUPV_WR);
-        else
-                return !!(data & CPLB_USER_WR);
-}
 /* Counters to implement round-robin replacement.  */
 static int icplb_rr_index[NR_CPUS] PDT_ATTR;
 static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
@@ -245,43 +224,16 @@ MGR_ATTR static int dcplb_miss(int cpu)
        return CPLB_RELOADED;
 }
-MGR_ATTR static noinline int dcplb_protection_fault(int cpu)
-{
-        int status = bfin_read_DCPLB_STATUS();
-        nr_dcplb_prot[cpu]++;
-        if (likely(status & FAULT_RW)) {
-                int idx = faulting_cplb_index(status);
-                unsigned long regaddr = DCPLB_DATA0 + idx * 4;
-                unsigned long data = bfin_read32(regaddr);
-                /* Check if fault is to dirty a clean page */
-                if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
-                    write_permitted(status, data)) {
-                        dcplb_tbl[cpu][idx].data = data;
-                        bfin_write32(regaddr, data);
-                        return CPLB_RELOADED;
-                }
-        }
-        return CPLB_PROT_VIOL;
-}
 MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
 {
        int cause = seqstat & 0x3f;
        unsigned int cpu = smp_processor_id();
        switch (cause) {
-        case 0x2C:
+        case VEC_CPLB_I_M:
                return icplb_miss(cpu);
-        case 0x26:
+        case VEC_CPLB_M:
                return dcplb_miss(cpu);
        default:
-                if (unlikely(cause == 0x23))
-                        return dcplb_protection_fault(cpu);
                return CPLB_UNKNOWN_ERR;
        }
 }
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
index 3302719173ca..2ab56811841c 100644
--- a/arch/blackfin/kernel/early_printk.c
+++ b/arch/blackfin/kernel/early_printk.c
@@ -202,11 +202,15 @@ asmlinkage void __init init_early_exception_vectors(void)
 asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr)
 {
        /* This can happen before the uart is initialized, so initialize
-         * the UART now
+         * the UART now (but only if we are running on the processor we think
+         * we are compiled for - otherwise we write to MMRs that don't exist,
+         * and cause other problems. Nothing comes out the UART, but it does
+         * end up in the __buf_log.
         */
-        if (likely(early_console == NULL))
+        if (likely(early_console == NULL) && CPUID == bfin_cpuid())
                setup_early_printk(DEFAULT_EARLY_PORT);
+        printk(KERN_EMERG "Early panic\n");
        dump_bfin_mem(fp);
        show_regs(fp);
        dump_bfin_trace_buffer();
diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S
new file mode 100644
index 000000000000..6980b7a0615d
--- /dev/null
+++ b/arch/blackfin/kernel/ftrace-entry.S
@@ -0,0 +1,140 @@
+/*
+ * mcount and friends -- ftrace stuff
+ *
+ * Copyright (C) 2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+#include <linux/linkage.h>
+#include <asm/ftrace.h>
+.text
+/* GCC will have called us before setting up the function prologue, so we
+ * can clobber the normal scratch registers, but we need to make sure to
+ * save/restore the registers used for argument passing (R0-R2) in case
+ * the profiled function is using them.  With data registers, R3 is the
+ * only one we can blow away.  With pointer registers, we have P0-P2.
+ *
+ * Upon entry, the RETS will point to the top of the current profiled
+ * function.  And since GCC setup the frame for us, the previous function
+ * will be waiting there.  mmmm pie.
+ */
+ENTRY(__mcount)
+        /* save third function arg early so we can do testing below */
+        [--sp] = r2;
+        /* load the function pointer to the tracer */
+        p0.l = _ftrace_trace_function;
+        p0.h = _ftrace_trace_function;
+        r3 = [p0];
+        /* optional micro optimization: don't call the stub tracer */
+        r2.l = _ftrace_stub;
+        r2.h = _ftrace_stub;
+        cc = r2 == r3;
+        if ! cc jump .Ldo_trace;
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        /* if the ftrace_graph_return function pointer is not set to
+         * the ftrace_stub entry, call prepare_ftrace_return().
+         */
+        p0.l = _ftrace_graph_return;
+        p0.h = _ftrace_graph_return;
+        r3 = [p0];
+        cc = r2 == r3;
+        if ! cc jump _ftrace_graph_caller;
+        /* similarly, if the ftrace_graph_entry function pointer is not
+         * set to the ftrace_graph_entry_stub entry, ...
+         */
+        p0.l = _ftrace_graph_entry;
+        p0.h = _ftrace_graph_entry;
+        r2.l = _ftrace_graph_entry_stub;
+        r2.h = _ftrace_graph_entry_stub;
+        r3 = [p0];
+        cc = r2 == r3;
+        if ! cc jump _ftrace_graph_caller;
+#endif
+        r2 = [sp++];
+        rts;
+.Ldo_trace:
+        /* save first/second function arg and the return register */
+        [--sp] = r0;
+        [--sp] = r1;
+        [--sp] = rets;
+        /* setup the tracer function */
+        p0 = r3;
+        /* tracer(ulong frompc, ulong selfpc):
+         *  frompc: the pc that did the call to ...
+         *  selfpc: ... this location
+         * the selfpc itself will need adjusting for the mcount call
+         */
+        r1 = rets;
+        r0 = [fp + 4];
+        r1 += -MCOUNT_INSN_SIZE;
+        /* call the tracer */
+        call (p0);
+        /* restore state and get out of dodge */
+.Lfinish_trace:
+        rets = [sp++];
+        r1 = [sp++];
+        r0 = [sp++];
+        r2 = [sp++];
+.globl _ftrace_stub
+_ftrace_stub:
+        rts;
+ENDPROC(__mcount)
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+/* The prepare_ftrace_return() function is similar to the trace function
+ * except it takes a pointer to the location of the frompc.  This is so
+ * the prepare_ftrace_return() can hijack it temporarily for probing
+ * purposes.
+ */
+ENTRY(_ftrace_graph_caller)
+        /* save first/second function arg and the return register */
+        [--sp] = r0;
+        [--sp] = r1;
+        [--sp] = rets;
+        r0 = fp;
+        r1 = rets;
+        r0 += 4;
+        r1 += -MCOUNT_INSN_SIZE;
+        call _prepare_ftrace_return;
+        jump .Lfinish_trace;
+ENDPROC(_ftrace_graph_caller)
+/* Undo the rewrite caused by ftrace_graph_caller().  The common function
+ * ftrace_return_to_handler() will return the original rets so we can
+ * restore it and be on our way.
+ */
+ENTRY(_return_to_handler)
+        /* make sure original return values are saved */
+        [--sp] = p0;
+        [--sp] = r0;
+        [--sp] = r1;
+        /* get original return address */
+        call _ftrace_return_to_handler;
+        rets = r0;
+        /* anomaly 05000371 - make sure we have at least three instructions
+         * between rets setting and the return
+         */
+        r1 = [sp++];
+        r0 = [sp++];
+        p0 = [sp++];
+        rts;
+ENDPROC(_return_to_handler)
+#endif
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c
new file mode 100644
index 000000000000..905bfc40a00b
--- /dev/null
+++ b/arch/blackfin/kernel/ftrace.c
@@ -0,0 +1,42 @@
+/*
+ * ftrace graph code
+ *
+ * Copyright (C) 2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+#include <linux/ftrace.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <asm/atomic.h>
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+/*
+ * Hook the return address and push it in the stack of return addrs
+ * in current thread info.
+ */
+void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
+{
+        struct ftrace_graph_ent trace;
+        unsigned long return_hooker = (unsigned long)&return_to_handler;
+        if (unlikely(atomic_read(&current->tracing_graph_pause)))
+                return;
+        if (ftrace_push_return_trace(*parent, self_addr, &trace.depth) == -EBUSY)
+                return;
+        trace.func = self_addr;
+        /* Only trace if the calling function expects to */
+        if (!ftrace_graph_entry(&trace)) {
+                current->curr_ret_stack--;
+                return;
+        }
+        /* all is well in the world !  hijack RETS ... */
+        *parent = return_hooker;
+}
+#endif
diff --git a/arch/blackfin/kernel/init_task.c b/arch/blackfin/kernel/init_task.c
index 2c228c020978..c26c34de9f3c 100644
--- a/arch/blackfin/kernel/init_task.c
+++ b/arch/blackfin/kernel/init_task.c
@@ -35,10 +35,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial task structure.
 *
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 5fc424803a17..d8cde1fc5cb9 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -99,7 +99,7 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
         * interrupt.
         */
        m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
-        this_domain = ipipe_current_domain;
+        this_domain = __ipipe_current_domain;
        if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control)))
                head = &this_domain->p_link;
@@ -212,7 +212,9 @@ void __ipipe_unstall_root_raw(void)
 int __ipipe_syscall_root(struct pt_regs *regs)
 {
+        struct ipipe_percpu_domain_data *p;
        unsigned long flags;
+        int ret;
        /*
         * We need to run the IRQ tail hook whenever we don't
@@ -231,29 +233,31 @@ int __ipipe_syscall_root(struct pt_regs *regs)
        /*
         * This routine either returns:
         * 0 -- if the syscall is to be passed to Linux;
-         * 1 -- if the syscall should not be passed to Linux, and no
+         * >0 -- if the syscall should not be passed to Linux, and no
         * tail work should be performed;
-         * -1 -- if the syscall should not be passed to Linux but the
+         * <0 -- if the syscall should not be passed to Linux but the
         * tail work has to be performed (for handling signals etc).
         */
-        if (__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL) &&
+        if (!__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL))
-            __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs) > 0) {
+                return 0;
-                if (ipipe_root_domain_p && !in_atomic()) {
-                        /*
+        ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
-                         * Sync pending VIRQs before _TIF_NEED_RESCHED
-                         * is tested.
+        local_irq_save_hw(flags);
-                         */
-                        local_irq_save_hw(flags);
+        if (!__ipipe_root_domain_p) {
-                        if ((ipipe_root_cpudom_var(irqpend_himask) & IPIPE_IRQMASK_VIRT) != 0)
+                local_irq_restore_hw(flags);
-                                __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
-                        local_irq_restore_hw(flags);
-                        return -1;
-                }
                return 1;
        }
-        return 0;
+        p = ipipe_root_cpudom_ptr();
+        if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0)
+                __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
+        local_irq_restore_hw(flags);
+        return -ret;
 }
 unsigned long ipipe_critical_enter(void (*syncfn) (void))
@@ -329,9 +333,7 @@ asmlinkage void __ipipe_sync_root(void)
 void ___ipipe_sync_pipeline(unsigned long syncmask)
 {
-        struct ipipe_domain *ipd = ipipe_current_domain;
+        if (__ipipe_root_domain_p) {
-        if (ipd == ipipe_root_domain) {
                if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
                        return;
        }
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 80447f99c2b5..6454babdfaff 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -1098,7 +1098,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                        CPUID, bfin_cpuid());
        seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
-                "stepping\t: %d\n",
+                "stepping\t: %d ",
                cpu, cclk/1000000, sclk/1000000,
 #ifdef CONFIG_MPU
                "mpu on",
@@ -1107,7 +1107,16 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 #endif
                revid);
-        seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
+        if (bfin_revid() != bfin_compiled_revid()) {
+                if (bfin_compiled_revid() == -1)
+                        seq_printf(m, "(Compiled for Rev none)");
+                else if (bfin_compiled_revid() == 0xffff)
+                        seq_printf(m, "(Compiled for Rev any)");
+                else
+                        seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
+        }
+        seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
                cclk/1000000, cclk%1000000,
                sclk/1000000, sclk%1000000);
        seq_printf(m, "bogomips\t: %lu.%02lu\n"
@@ -1172,6 +1181,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 #ifdef __ARCH_SYNC_CORE_DCACHE
        seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);
 #endif
+#ifdef __ARCH_SYNC_CORE_ICACHE
+        seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count);
+#endif
 #ifdef CONFIG_BFIN_ICACHE_LOCK
        switch ((cpudata->imemctl >> 3) & WAYALL_L) {
        case WAY0_L:
diff --git a/arch/blackfin/kernel/stacktrace.c b/arch/blackfin/kernel/stacktrace.c
new file mode 100644
index 000000000000..30301e1eace5
--- /dev/null
+++ b/arch/blackfin/kernel/stacktrace.c
@@ -0,0 +1,53 @@
+/*
+ * Blackfin stacktrace code (mostly copied from avr32)
+ *
+ * Copyright 2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+#include <linux/thread_info.h>
+#include <linux/module.h>
+register unsigned long current_frame_pointer asm("FP");
+struct stackframe {
+        unsigned long fp;
+        unsigned long rets;
+};
+/*
+ * Save stack-backtrace addresses into a stack_trace buffer.
+ */
+void save_stack_trace(struct stack_trace *trace)
+{
+        unsigned long low, high;
+        unsigned long fp;
+        struct stackframe *frame;
+        int skip = trace->skip;
+        low = (unsigned long)task_stack_page(current);
+        high = low + THREAD_SIZE;
+        fp = current_frame_pointer;
+        while (fp >= low && fp <= (high - sizeof(*frame))) {
+                frame = (struct stackframe *)fp;
+                if (skip) {
+                        skip--;
+                } else {
+                        trace->entries[trace->nr_entries++] = frame->rets;
+                        if (trace->nr_entries >= trace->max_entries)
+                                break;
+                }
+                /*
+                 * The next frame must be at a higher address than the
+                 * current frame.
+                 */
+                low = fp + sizeof(*frame);
+                fp = frame->fp;
+        }
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index aa76dfb0226e..d279552fe9b0 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -27,6 +27,7 @@
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
+#include <linux/bug.h>
 #include <linux/uaccess.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
@@ -238,6 +239,11 @@ asmlinkage void double_fault_c(struct pt_regs *fp)
 }
+static int kernel_mode_regs(struct pt_regs *regs)
+{
+        return regs->ipend & 0xffc0;
+}
 asmlinkage void trap_c(struct pt_regs *fp)
 {
 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
@@ -246,6 +252,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
 #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
        unsigned int cpu = smp_processor_id();
 #endif
+        const char *strerror = NULL;
        int sig = 0;
        siginfo_t info;
        unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
@@ -259,27 +266,10 @@ asmlinkage void trap_c(struct pt_regs *fp)
         * double faults if the stack has become corrupt
         */
-        /* If the fault was caused by a kernel thread, or interrupt handler
+#ifndef CONFIG_KGDB
-         * we will kernel panic, so the system reboots.
+        /* IPEND is skipped if KGDB isn't enabled (see entry code) */
-         * If KGDB is enabled, don't set this for kernel breakpoints
+        fp->ipend = bfin_read_IPEND();
-        */
-        /* TODO: check to see if we are in some sort of deferred HWERR
-         * that we should be able to recover from, not kernel panic
-         */
-        if ((bfin_read_IPEND() & 0xFFC0) && (trapnr != VEC_STEP)
-#ifdef CONFIG_KGDB
-                && (trapnr != VEC_EXCPT02)
 #endif
-        ){
-                console_verbose();
-                oops_in_progress = 1;
-        } else if (current) {
-                if (current->mm == NULL) {
-                        console_verbose();
-                        oops_in_progress = 1;
-                }
-        }
        /* trap_c() will be called for exceptions. During exceptions
         * processing, the pc value should be set with retx value.
@@ -307,15 +297,15 @@ asmlinkage void trap_c(struct pt_regs *fp)
                sig = SIGTRAP;
                CHK_DEBUGGER_TRAP_MAYBE();
                /* Check if this is a breakpoint in kernel space */
-                if (fp->ipend & 0xffc0)
+                if (kernel_mode_regs(fp))
-                        return;
+                        goto traps_done;
                else
                        break;
        /* 0x03 - User Defined, userspace stack overflow */
        case VEC_EXCPT03:
                info.si_code = SEGV_STACKFLOW;
                sig = SIGSEGV;
-                verbose_printk(KERN_NOTICE EXC_0x03(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x03(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x02 - KGDB initial connection and break signal trap */
@@ -324,7 +314,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
                info.si_code = TRAP_ILLTRAP;
                sig = SIGTRAP;
                CHK_DEBUGGER_TRAP();
-                return;
+                goto traps_done;
 #endif
        /* 0x04 - User Defined */
        /* 0x05 - User Defined */
@@ -344,7 +334,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
        case VEC_EXCPT04 ... VEC_EXCPT15:
                info.si_code = ILL_ILLPARAOP;
                sig = SIGILL;
-                verbose_printk(KERN_NOTICE EXC_0x04(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x04(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x10 HW Single step, handled here */
@@ -353,15 +343,15 @@ asmlinkage void trap_c(struct pt_regs *fp)
                sig = SIGTRAP;
                CHK_DEBUGGER_TRAP_MAYBE();
                /* Check if this is a single step in kernel space */
-                if (fp->ipend & 0xffc0)
+                if (kernel_mode_regs(fp))
-                        return;
+                        goto traps_done;
                else
                        break;
        /* 0x11 - Trace Buffer Full, handled here */
        case VEC_OVFLOW:
                info.si_code = TRAP_TRACEFLOW;
                sig = SIGTRAP;
-                verbose_printk(KERN_NOTICE EXC_0x11(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x11(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x12 - Reserved, Caught by default */
@@ -381,37 +371,54 @@ asmlinkage void trap_c(struct pt_regs *fp)
        /* 0x20 - Reserved, Caught by default */
        /* 0x21 - Undefined Instruction, handled here */
        case VEC_UNDEF_I:
+#ifdef CONFIG_BUG
+                if (kernel_mode_regs(fp)) {
+                        switch (report_bug(fp->pc, fp)) {
+                        case BUG_TRAP_TYPE_NONE:
+                                break;
+                        case BUG_TRAP_TYPE_WARN:
+                                dump_bfin_trace_buffer();
+                                fp->pc += 2;
+                                goto traps_done;
+                        case BUG_TRAP_TYPE_BUG:
+                                /* call to panic() will dump trace, and it is
+                                 * off at this point, so it won't be clobbered
+                                 */
+                                panic("BUG()");
+                        }
+                }
+#endif
                info.si_code = ILL_ILLOPC;
                sig = SIGILL;
-                verbose_printk(KERN_NOTICE EXC_0x21(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x22 - Illegal Instruction Combination, handled here */
        case VEC_ILGAL_I:
                info.si_code = ILL_ILLPARAOP;
                sig = SIGILL;
-                verbose_printk(KERN_NOTICE EXC_0x22(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x22(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x23 - Data CPLB protection violation, handled here */
        case VEC_CPLB_VL:
                info.si_code = ILL_CPLB_VI;
                sig = SIGBUS;
-                verbose_printk(KERN_NOTICE EXC_0x23(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x24 - Data access misaligned, handled here */
        case VEC_MISALI_D:
                info.si_code = BUS_ADRALN;
                sig = SIGBUS;
-                verbose_printk(KERN_NOTICE EXC_0x24(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x24(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x25 - Unrecoverable Event, handled here */
        case VEC_UNCOV:
                info.si_code = ILL_ILLEXCPT;
                sig = SIGILL;
-                verbose_printk(KERN_NOTICE EXC_0x25(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x25(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
@@ -419,7 +426,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
        case VEC_CPLB_M:
                info.si_code = BUS_ADRALN;
                sig = SIGBUS;
-                verbose_printk(KERN_NOTICE EXC_0x26(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x26(KERN_NOTICE);
                break;
        /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
        case VEC_CPLB_MHIT:
@@ -427,10 +434,10 @@ asmlinkage void trap_c(struct pt_regs *fp)
                sig = SIGSEGV;
 #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
                if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START)
-                        verbose_printk(KERN_NOTICE "NULL pointer access\n");
+                        strerror = KERN_NOTICE "NULL pointer access\n";
                else
 #endif
-                        verbose_printk(KERN_NOTICE EXC_0x27(KERN_NOTICE));
+                        strerror = KERN_NOTICE EXC_0x27(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x28 - Emulation Watchpoint, handled here */
@@ -440,8 +447,8 @@ asmlinkage void trap_c(struct pt_regs *fp)
                pr_debug(EXC_0x28(KERN_DEBUG));
                CHK_DEBUGGER_TRAP_MAYBE();
                /* Check if this is a watchpoint in kernel space */
-                if (fp->ipend & 0xffc0)
+                if (kernel_mode_regs(fp))
-                        return;
+                        goto traps_done;
                else
                        break;
 #ifdef CONFIG_BF535
@@ -449,7 +456,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
        case VEC_ISTRU_VL:      /* ADSP-BF535 only (MH) */
                info.si_code = BUS_OPFETCH;
                sig = SIGBUS;
-                verbose_printk(KERN_NOTICE "BF535: VEC_ISTRU_VL\n");
+                strerror = KERN_NOTICE "BF535: VEC_ISTRU_VL\n";
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
 #else
@@ -459,21 +466,21 @@ asmlinkage void trap_c(struct pt_regs *fp)
        case VEC_MISALI_I:
                info.si_code = BUS_ADRALN;
                sig = SIGBUS;
-                verbose_printk(KERN_NOTICE EXC_0x2A(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x2A(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x2B - Instruction CPLB protection violation, handled here */
        case VEC_CPLB_I_VL:
                info.si_code = ILL_CPLB_VI;
                sig = SIGBUS;
-                verbose_printk(KERN_NOTICE EXC_0x2B(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x2B(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
        case VEC_CPLB_I_M:
                info.si_code = ILL_CPLB_MISS;
                sig = SIGBUS;
-                verbose_printk(KERN_NOTICE EXC_0x2C(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x2C(KERN_NOTICE);
                break;
        /* 0x2D - Instruction CPLB Multiple Hits, handled here */
        case VEC_CPLB_I_MHIT:
@@ -481,17 +488,17 @@ asmlinkage void trap_c(struct pt_regs *fp)
                sig = SIGSEGV;
 #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
                if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START)
-                        verbose_printk(KERN_NOTICE "Jump to NULL address\n");
+                        strerror = KERN_NOTICE "Jump to NULL address\n";
                else
 #endif
-                        verbose_printk(KERN_NOTICE EXC_0x2D(KERN_NOTICE));
+                        strerror = KERN_NOTICE EXC_0x2D(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x2E - Illegal use of Supervisor Resource, handled here */
        case VEC_ILL_RES:
                info.si_code = ILL_PRVOPC;
                sig = SIGILL;
-                verbose_printk(KERN_NOTICE EXC_0x2E(KERN_NOTICE));
+                strerror = KERN_NOTICE EXC_0x2E(KERN_NOTICE);
                CHK_DEBUGGER_TRAP_MAYBE();
                break;
        /* 0x2F - Reserved, Caught by default */
@@ -519,17 +526,17 @@ asmlinkage void trap_c(struct pt_regs *fp)
                case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
                        info.si_code = BUS_ADRALN;
                        sig = SIGBUS;
-                        verbose_printk(KERN_NOTICE HWC_x2(KERN_NOTICE));
+                        strerror = KERN_NOTICE HWC_x2(KERN_NOTICE);
                        break;
                /* External Memory Addressing Error */
                case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
                        info.si_code = BUS_ADRERR;
                        sig = SIGBUS;
-                        verbose_printk(KERN_NOTICE HWC_x3(KERN_NOTICE));
+                        strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
                        break;
                /* Performance Monitor Overflow */
                case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
-                        verbose_printk(KERN_NOTICE HWC_x12(KERN_NOTICE));
+                        strerror = KERN_NOTICE HWC_x12(KERN_NOTICE);
                        break;
                /* RAISE 5 instruction */
                case (SEQSTAT_HWERRCAUSE_RAISE_5):
@@ -546,7 +553,6 @@ asmlinkage void trap_c(struct pt_regs *fp)
         * if we get here we hit a reserved one, so panic
         */
        default:
-                oops_in_progress = 1;
                info.si_code = ILL_ILLPARAOP;
                sig = SIGILL;
                verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
@@ -557,6 +563,16 @@ asmlinkage void trap_c(struct pt_regs *fp)
        BUG_ON(sig == 0);
+        /* If the fault was caused by a kernel thread, or interrupt handler
+         * we will kernel panic, so the system reboots.
+         */
+        if (kernel_mode_regs(fp) || (current && !current->mm)) {
+                console_verbose();
+                oops_in_progress = 1;
+                if (strerror)
+                        verbose_printk(strerror);
+        }
        if (sig != SIGTRAP) {
                dump_bfin_process(fp);
                dump_bfin_mem(fp);
@@ -606,8 +622,8 @@ asmlinkage void trap_c(struct pt_regs *fp)
        if (ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8))
                fp->pc = SAFE_USER_INSTRUCTION;
+ traps_done:
        trace_buffer_restore(j);
-        return;
 }
 /* Typical exception handling routines  */
@@ -792,6 +808,18 @@ void dump_bfin_trace_buffer(void)
 }
 EXPORT_SYMBOL(dump_bfin_trace_buffer);
+#ifdef CONFIG_BUG
+int is_valid_bugaddr(unsigned long addr)
+{
+        unsigned short opcode;
+        if (!get_instruction(&opcode, (unsigned short *)addr))
+                return 0;
+        return opcode == BFIN_BUG_OPCODE;
+}
+#endif
 /*
 * Checks to see if the address pointed to is either a
 * 16-bit CALL instruction, or a 32-bit CALL instruction
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 8b67167cb4f4..6ac307ca0d80 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -54,6 +54,7 @@ SECTIONS
                SCHED_TEXT
 #endif
                LOCK_TEXT
+                IRQENTRY_TEXT
                KPROBES_TEXT
                *(.text.*)
                *(.fixup)
@@ -166,6 +167,20 @@ SECTIONS
        }
        PERCPU(4)
        SECURITY_INIT
+        /* we have to discard exit text and such at runtime, not link time, to
+         * handle embedded cross-section references (alt instructions, bug
+         * table, eh_frame, etc...)
+         */
+        .exit.text :
+        {
+                EXIT_TEXT
+        }
+        .exit.data :
+        {
+                EXIT_DATA
+        }
        .init.ramfs :
        {
                . = ALIGN(4);
@@ -264,8 +279,6 @@ SECTIONS
        /DISCARD/ :
        {
-                EXIT_TEXT
-                EXIT_DATA
                *(.exitcall.exit)
        }
 }
diff --git a/arch/blackfin/lib/checksum.c b/arch/blackfin/lib/checksum.c
index 762a7f02970a..cd605e7d8518 100644
--- a/arch/blackfin/lib/checksum.c
+++ b/arch/blackfin/lib/checksum.c
@@ -116,6 +116,7 @@ __sum16 ip_compute_csum(const void *buff, int len)
 {
        return (__force __sum16)~do_csum(buff, len);
 }
+EXPORT_SYMBOL(ip_compute_csum);
 /*
 * copy from fs while checksumming, otherwise like csum_partial
@@ -130,6 +131,7 @@ csum_partial_copy_from_user(const void __user *src, void *dst,
        memcpy(dst, (__force void *)src, len);
        return csum_partial(dst, len, sum);
 }
+EXPORT_SYMBOL(csum_partial_copy_from_user);
 /*
 * copy from ds while checksumming, otherwise like csum_partial
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index 62bba09bcce6..1382f0382359 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -246,7 +246,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
                .bus_num = 0, /* Framework bus number */
-                .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
+                .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
                .mode = SPI_MODE_3,
@@ -369,6 +369,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI0,
                .end   = CH_SPI0,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
                .flags = IORESOURCE_IRQ,
        },
 };
@@ -399,6 +404,11 @@ static struct resource bfin_spi1_resource[] = {
        [1] = {
                .start = CH_SPI1,
                .end   = CH_SPI1,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
                .flags = IORESOURCE_IRQ,
        },
 };
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 6d6f9effa0bb..1eaf27ff722e 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -664,6 +664,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        },
 };
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 1435c5d38cd5..9f9c0005dcf1 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -467,6 +467,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        },
 };
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 147edd1eb1ad..3e5b7db6b065 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -723,6 +723,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        },
 };
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 895f213ea454..38cf8ffd6d74 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -266,6 +266,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 0765872a8ada..9ecdc361fa6d 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -162,6 +162,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index a727e538fa28..1443e92d8b62 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -160,6 +160,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 842f1c9c2393..89a5ec4ca048 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -196,6 +196,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index e19c565ade16..a68ade8a3ca2 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -299,6 +299,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index 4fee19673127..2a87d1cfcd06 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -182,8 +182,13 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
-        }
+        },
 };
 /* SPI controller data */
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 3c159819e555..399f81da7b93 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -184,6 +184,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        },
 };
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 26707ce39f29..838240f151f5 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -398,8 +398,13 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
-        }
+        },
 };
 /* SPI controller data */
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index dfb5036f8a6b..ff7228caa7da 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -1345,7 +1345,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 #if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
        {
                I2C_BOARD_INFO("pmic-adp5520", 0x32),
-                .irq = IRQ_PF7,
+                .irq = IRQ_PG0,
                .platform_data = (void *)&adp5520_pdev_data,
        },
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 280574591201..e523e6e610d0 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -182,6 +182,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index e37cb9378884..57695b4c3c09 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -352,6 +352,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI0,
                .end   = CH_SPI0,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
                .flags = IORESOURCE_IRQ,
        }
 };
@@ -366,6 +371,11 @@ static struct resource bfin_spi1_resource[] = {
        [1] = {
                .start = CH_SPI1,
                .end   = CH_SPI1,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index f53ad682530b..f5a3c30a41bd 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -612,6 +612,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI0,
                .end   = CH_SPI0,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
                .flags = IORESOURCE_IRQ,
        }
 };
@@ -626,6 +631,11 @@ static struct resource bfin_spi1_resource[] = {
        [1] = {
                .start = CH_SPI1,
                .end   = CH_SPI1,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index add5a17452ce..805a57b5e650 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -396,6 +396,8 @@ static struct platform_device bfin_sir3_device = {
 #endif
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#include <linux/smsc911x.h>
 static struct resource smsc911x_resources[] = {
        {
                .name = "smsc911x-memory",
@@ -409,11 +411,22 @@ static struct resource smsc911x_resources[] = {
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
        },
 };
+static struct smsc911x_platform_config smsc911x_config = {
+        .flags = SMSC911X_USE_32BIT,
+        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .phy_interface = PHY_INTERFACE_MODE_MII,
+};
 static struct platform_device smsc911x_device = {
        .name = "smsc911x",
        .id = 0,
        .num_resources = ARRAY_SIZE(smsc911x_resources),
        .resource = smsc911x_resources,
+        .dev = {
+                .platform_data = &smsc911x_config,
+        },
 };
 #endif
@@ -741,6 +754,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI0,
                .end   = CH_SPI0,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI0,
+                .end   = IRQ_SPI0,
                .flags = IORESOURCE_IRQ,
        }
 };
@@ -755,6 +773,11 @@ static struct resource bfin_spi1_resource[] = {
        [1] = {
                .start = CH_SPI1,
                .end   = CH_SPI1,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI1,
+                .end   = IRQ_SPI1,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 0dd9685e5d53..0c9d72c5f5ba 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -177,8 +177,13 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
-        }
+        },
 };
 /* SPI controller data */
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 0e2178a1aec5..b5ef7ff7b7bd 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -304,6 +304,11 @@ static struct resource bfin_spi0_resource[] = {
        [1] = {
                .start = CH_SPI,
                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
                .flags = IORESOURCE_IRQ,
        }
 };
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
index e6ab1f815123..b59ce3cb3807 100644
--- a/arch/blackfin/mach-common/cache-c.c
+++ b/arch/blackfin/mach-common/cache-c.c
@@ -16,9 +16,21 @@
 void blackfin_invalidate_entire_dcache(void)
 {
        u32 dmem = bfin_read_DMEM_CONTROL();
-        SSYNC();
        bfin_write_DMEM_CONTROL(dmem & ~0xc);
        SSYNC();
        bfin_write_DMEM_CONTROL(dmem);
        SSYNC();
 }
+/* Invalidate the Entire Instruction cache by
+ * clearing IMC bit
+ */
+void blackfin_invalidate_entire_icache(void)
+{
+        u32 imem = bfin_read_IMEM_CONTROL();
+        bfin_write_IMEM_CONTROL(imem & ~0x4);
+        SSYNC();
+        bfin_write_IMEM_CONTROL(imem);
+        SSYNC();
+}
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index da0558ad1b1a..31fa313e81cf 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -42,6 +42,7 @@
 #include <asm/thread_info.h>  /* TIF_NEED_RESCHED */
 #include <asm/asm-offsets.h>
 #include <asm/trace.h>
+#include <asm/traps.h>
 #include <asm/context.S>
@@ -84,13 +85,15 @@ ENTRY(_ex_workaround_261)
        if !cc jump _bfin_return_from_exception;
        /* fall through */
        R7 = P4;
-        R6 = 0x26;      /* Data CPLB Miss */
+        R6 = VEC_CPLB_M;        /* Data CPLB Miss */
        cc = R6 == R7;
        if cc jump _ex_dcplb_miss (BP);
-        R6 = 0x23;      /* Data CPLB Miss */
+#ifdef CONFIG_MPU
+        R6 = VEC_CPLB_VL;       /* Data CPLB Violation */
        cc = R6 == R7;
        if cc jump _ex_dcplb_viol (BP);
-        /* Handle 0x23 Data CPLB Protection Violation
+#endif
+        /* Handle Data CPLB Protection Violation
         * and Data CPLB Multiple Hits - Linux Trap Zero
         */
        jump _ex_trap_c;
@@ -270,7 +273,7 @@ ENTRY(_bfin_return_from_exception)
        r6.l = lo(SEQSTAT_EXCAUSE);
        r6.h = hi(SEQSTAT_EXCAUSE);
        r7 = r7 & r6;
-        r6 = 0x25;
+        r6 = VEC_UNCOV;
        CC = R7 == R6;
        if CC JUMP _double_fault;
 #endif
@@ -1605,6 +1608,7 @@ ENTRY(_sys_call_table)
        .long _sys_inotify_init1        /* 365 */
        .long _sys_preadv
        .long _sys_pwritev
+        .long _sys_rt_tgsigqueueinfo
        .rept NR_syscalls-(.-_sys_call_table)/4
        .long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 3b8ebaee77f2..61840059dfac 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -144,7 +144,7 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
 static irqreturn_t ipi_handler(int irq, void *dev_instance)
 {
-        struct ipi_message *msg, *mg;
+        struct ipi_message *msg;
        struct ipi_message_queue *msg_queue;
        unsigned int cpu = smp_processor_id();
@@ -154,7 +154,8 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance)
        msg_queue->count++;
        spin_lock(&msg_queue->lock);
-        list_for_each_entry_safe(msg, mg, &msg_queue->head, list) {
+        while (!list_empty(&msg_queue->head)) {
+                msg = list_entry(msg_queue->head.next, typeof(*msg), list);
                list_del(&msg->list);
                switch (msg->type) {
                case BFIN_IPI_RESCHEDULE:
@@ -221,7 +222,7 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
        for_each_cpu_mask(cpu, callmap) {
                msg_queue = &per_cpu(ipi_msg_queue, cpu);
                spin_lock_irqsave(&msg_queue->lock, flags);
-                list_add(&msg->list, &msg_queue->head);
+                list_add_tail(&msg->list, &msg_queue->head);
                spin_unlock_irqrestore(&msg_queue->lock, flags);
                platform_send_ipi_cpu(cpu);
        }
@@ -261,7 +262,7 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
        msg_queue = &per_cpu(ipi_msg_queue, cpu);
        spin_lock_irqsave(&msg_queue->lock, flags);
-        list_add(&msg->list, &msg_queue->head);
+        list_add_tail(&msg->list, &msg_queue->head);
        spin_unlock_irqrestore(&msg_queue->lock, flags);
        platform_send_ipi_cpu(cpu);
@@ -292,7 +293,7 @@ void smp_send_reschedule(int cpu)
        msg_queue = &per_cpu(ipi_msg_queue, cpu);
        spin_lock_irqsave(&msg_queue->lock, flags);
-        list_add(&msg->list, &msg_queue->head);
+        list_add_tail(&msg->list, &msg_queue->head);
        spin_unlock_irqrestore(&msg_queue->lock, flags);
        platform_send_ipi_cpu(cpu);
@@ -320,7 +321,7 @@ void smp_send_stop(void)
        for_each_cpu_mask(cpu, callmap) {
                msg_queue = &per_cpu(ipi_msg_queue, cpu);
                spin_lock_irqsave(&msg_queue->lock, flags);
-                list_add(&msg->list, &msg_queue->head);
+                list_add_tail(&msg->list, &msg_queue->head);
                spin_unlock_irqrestore(&msg_queue->lock, flags);
                platform_send_ipi_cpu(cpu);
        }
@@ -468,6 +469,17 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end)
 }
 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
+#ifdef __ARCH_SYNC_CORE_ICACHE
+void resync_core_icache(void)
+{
+        unsigned int cpu = get_cpu();
+        blackfin_invalidate_entire_icache();
+        ++per_cpu(cpu_data, cpu).icache_invld_count;
+        put_cpu();
+}
+EXPORT_SYMBOL(resync_core_icache);
+#endif
 #ifdef __ARCH_SYNC_CORE_DCACHE
 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
diff --git a/arch/cris/include/asm/kmap_types.h b/arch/cris/include/asm/kmap_types.h
index 492988cb9077..d2d643c4ea59 100644
--- a/arch/cris/include/asm/kmap_types.h
+++ b/arch/cris/include/asm/kmap_types.h
@@ -5,21 +5,6 @@
 * is actually used on cris. 
 */
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
 #endif
diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c
index 4df0b320d524..51dcd04d2777 100644
--- a/arch/cris/kernel/process.c
+++ b/arch/cris/kernel/process.c
@@ -38,10 +38,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/frv/kernel/init_task.c b/arch/frv/kernel/init_task.c
index 29429a8b7f6a..1d3df1d9495c 100644
--- a/arch/frv/kernel/init_task.c
+++ b/arch/frv/kernel/init_task.c
@@ -12,10 +12,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/h8300/include/asm/kmap_types.h b/arch/h8300/include/asm/kmap_types.h
index 1ec8a3427120..be12a7160116 100644
--- a/arch/h8300/include/asm/kmap_types.h
+++ b/arch/h8300/include/asm/kmap_types.h
@@ -1,21 +1,6 @@
 #ifndef _ASM_H8300_KMAP_TYPES_H
 #define _ASM_H8300_KMAP_TYPES_H
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
 #endif
diff --git a/arch/h8300/kernel/init_task.c b/arch/h8300/kernel/init_task.c
index cb5dc552da97..089c65ed6eb3 100644
--- a/arch/h8300/kernel/init_task.c
+++ b/arch/h8300/kernel/init_task.c
@@ -14,10 +14,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial task structure.
 *
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index 56ceb68eb99d..fe63b2dc9d07 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -1131,7 +1131,7 @@ sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp
 #ifdef CONFIG_NUMA
        {
                struct page *page;
-                page = alloc_pages_node(ioc->node == MAX_NUMNODES ?
+                page = alloc_pages_exact_node(ioc->node == MAX_NUMNODES ?
                                        numa_node_id() : ioc->node, flags,
                                        get_order(size));
diff --git a/arch/ia64/include/asm/kmap_types.h b/arch/ia64/include/asm/kmap_types.h
index 5d1658aa2b3b..05d5f9996105 100644
--- a/arch/ia64/include/asm/kmap_types.h
+++ b/arch/ia64/include/asm/kmap_types.h
@@ -1,30 +1,12 @@
 #ifndef _ASM_IA64_KMAP_TYPES_H
 #define _ASM_IA64_KMAP_TYPES_H
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
+#define  __WITH_KM_FENCE
-#else
-# define D(n)
 #endif
-enum km_type {
+#include <asm-generic/kmap_types.h>
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-#undef D
+#undef __WITH_KM_FENCE
 #endif /* _ASM_IA64_KMAP_TYPES_H */
diff --git a/arch/ia64/kernel/init_task.c b/arch/ia64/kernel/init_task.c
index 5b0e830c6f33..c475fc281be7 100644
--- a/arch/ia64/kernel/init_task.c
+++ b/arch/ia64/kernel/init_task.c
@@ -19,10 +19,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial task structure.
 *
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 8f33a8840422..5b17bd402275 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -1829,8 +1829,7 @@ ia64_mca_cpu_init(void *cpu_data)
                        data = mca_bootmem();
                        first_time = 0;
                } else
-                        data = page_address(alloc_pages_node(numa_node_id(),
+                        data = __get_free_pages(GFP_KERNEL, get_order(sz));
-                                        GFP_KERNEL, get_order(sz)));
                if (!data)
                        panic("Could not allocate MCA memory for cpu %d\n",
                                        cpu);
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 8a06dc480594..bdc176cb5e85 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -5595,7 +5595,7 @@ pfm_interrupt_handler(int irq, void *arg)
                (*pfm_alt_intr_handler->handler)(irq, arg, regs);
        }
-        put_cpu_no_resched();
+        put_cpu();
        return IRQ_HANDLED;
 }
diff --git a/arch/ia64/kernel/uncached.c b/arch/ia64/kernel/uncached.c
index 8eff8c1d40a6..6ba72ab42fcc 100644
--- a/arch/ia64/kernel/uncached.c
+++ b/arch/ia64/kernel/uncached.c
@@ -98,7 +98,8 @@ static int uncached_add_chunk(struct uncached_pool *uc_pool, int nid)
        /* attempt to allocate a granule's worth of cached memory pages */
-        page = alloc_pages_node(nid, GFP_KERNEL | __GFP_ZERO | GFP_THISNODE,
+        page = alloc_pages_exact_node(nid,
+                                GFP_KERNEL | __GFP_ZERO | GFP_THISNODE,
                                IA64_GRANULE_SHIFT-PAGE_SHIFT);
        if (!page) {
                mutex_unlock(&uc_pool->add_chunk_mutex);
diff --git a/arch/ia64/mm/extable.c b/arch/ia64/mm/extable.c
index e95d5ad9285d..c99a41e29fe8 100644
--- a/arch/ia64/mm/extable.c
+++ b/arch/ia64/mm/extable.c
@@ -8,7 +8,7 @@
 #include <linux/sort.h>
 #include <asm/uaccess.h>
-#include <asm/module.h>
+#include <linux/module.h>
 static int cmp_ex(const void *a, const void *b)
 {
@@ -55,7 +55,7 @@ void sort_extable (struct exception_table_entry *start,
 static inline unsigned long ex_to_addr(const struct exception_table_entry *x)
 {
-        return (unsigned long)&x->insn + x->insn;
+        return (unsigned long)&x->addr + x->addr;
 }
 #ifdef CONFIG_MODULES
diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c
index d876423e4e75..98b684928e12 100644
--- a/arch/ia64/sn/pci/pci_dma.c
+++ b/arch/ia64/sn/pci/pci_dma.c
@@ -90,7 +90,8 @@ static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
         */
        node = pcibus_to_node(pdev->bus);
        if (likely(node >=0)) {
-                struct page *p = alloc_pages_node(node, flags, get_order(size));
+                struct page *p = alloc_pages_exact_node(node,
+                                                flags, get_order(size));
                if (likely(p))
                        cpuaddr = page_address(p);
diff --git a/arch/m32r/include/asm/kmap_types.h b/arch/m32r/include/asm/kmap_types.h
index fa94dc6410ea..4cdb5e3a06bf 100644
--- a/arch/m32r/include/asm/kmap_types.h
+++ b/arch/m32r/include/asm/kmap_types.h
@@ -2,28 +2,11 @@
 #define __M32R_KMAP_TYPES_H
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
+#define  __WITH_KM_FENCE
-#else
-# define D(n)
 #endif
-enum km_type {
+#include <asm-generic/kmap_types.h>
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-#undef D
+#undef __WITH_KM_FENCE
 #endif /* __M32R_KMAP_TYPES_H */
diff --git a/arch/m32r/kernel/init_task.c b/arch/m32r/kernel/init_task.c
index 016885c6f260..fce57e5d3f91 100644
--- a/arch/m32r/kernel/init_task.c
+++ b/arch/m32r/kernel/init_task.c
@@ -13,10 +13,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
index 7daf897292cf..b7a78ad429b7 100644
--- a/arch/m32r/mm/discontig.c
+++ b/arch/m32r/mm/discontig.c
@@ -154,9 +154,9 @@ unsigned long __init zone_sizes_init(void)
         *  Use all area of internal RAM.
         *  see __alloc_pages()
         */
-        NODE_DATA(1)->node_zones->pages_min = 0;
+        NODE_DATA(1)->node_zones->watermark[WMARK_MIN] = 0;
-        NODE_DATA(1)->node_zones->pages_low = 0;
+        NODE_DATA(1)->node_zones->watermark[WMARK_LOW] = 0;
-        NODE_DATA(1)->node_zones->pages_high = 0;
+        NODE_DATA(1)->node_zones->watermark[WMARK_HIGH] = 0;
        return holes;
 }
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
index 98138b4e9220..922fdfdadeaa 100644
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ b/arch/m32r/platforms/m32104ut/setup.c
@@ -63,7 +63,7 @@ static void shutdown_m32104ut_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type m32104ut_irq_type =
+static struct irq_chip m32104ut_irq_type =
 {
        .typename = "M32104UT-IRQ",
        .startup = startup_m32104ut_irq,
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
index 77b0ae9379e9..9c1bc7487c1e 100644
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -69,7 +69,7 @@ static void shutdown_m32700ut_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type m32700ut_irq_type =
+static struct irq_chip m32700ut_irq_type =
 {
        .typename = "M32700UT-IRQ",
        .startup = startup_m32700ut_irq,
@@ -146,7 +146,7 @@ static void shutdown_m32700ut_pld_irq(unsigned int irq)
        outw(PLD_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type m32700ut_pld_irq_type =
+static struct irq_chip m32700ut_pld_irq_type =
 {
        .typename = "M32700UT-PLD-IRQ",
        .startup = startup_m32700ut_pld_irq,
@@ -215,7 +215,7 @@ static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
        outw(PLD_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type m32700ut_lanpld_irq_type =
+static struct irq_chip m32700ut_lanpld_irq_type =
 {
        .typename = "M32700UT-PLD-LAN-IRQ",
        .startup = startup_m32700ut_lanpld_irq,
@@ -284,7 +284,7 @@ static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
        outw(PLD_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type m32700ut_lcdpld_irq_type =
+static struct irq_chip m32700ut_lcdpld_irq_type =
 {
        .typename = "M32700UT-PLD-LCD-IRQ",
        .startup = startup_m32700ut_lcdpld_irq,
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
index 3ec087ff2214..fb4b17799b66 100644
--- a/arch/m32r/platforms/mappi/setup.c
+++ b/arch/m32r/platforms/mappi/setup.c
@@ -63,7 +63,7 @@ static void shutdown_mappi_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type mappi_irq_type =
+static struct irq_chip mappi_irq_type =
 {
        .typename = "MAPPI-IRQ",
        .startup = startup_mappi_irq,
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
index d87969c6356e..6a65eda0a056 100644
--- a/arch/m32r/platforms/mappi2/setup.c
+++ b/arch/m32r/platforms/mappi2/setup.c
@@ -70,7 +70,7 @@ static void shutdown_mappi2_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type mappi2_irq_type =
+static struct irq_chip mappi2_irq_type =
 {
        .typename = "MAPPI2-IRQ",
        .startup = startup_mappi2_irq,
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index 785b4bd6d9fd..9c337aeac94b 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -70,7 +70,7 @@ static void shutdown_mappi3_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type mappi3_irq_type =
+static struct irq_chip mappi3_irq_type =
 {
        .typename = "MAPPI3-IRQ",
        .startup = startup_mappi3_irq,
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index 6faa5db68e95..ed865741c38d 100644
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -61,7 +61,7 @@ static void shutdown_oaks32r_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type oaks32r_irq_type =
+static struct irq_chip oaks32r_irq_type =
 {
        .typename = "OAKS32R-IRQ",
        .startup = startup_oaks32r_irq,
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
index fab13fd85422..80d680657019 100644
--- a/arch/m32r/platforms/opsput/setup.c
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -70,7 +70,7 @@ static void shutdown_opsput_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type opsput_irq_type =
+static struct irq_chip opsput_irq_type =
 {
        .typename = "OPSPUT-IRQ",
        .startup = startup_opsput_irq,
@@ -147,7 +147,7 @@ static void shutdown_opsput_pld_irq(unsigned int irq)
        outw(PLD_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type opsput_pld_irq_type =
+static struct irq_chip opsput_pld_irq_type =
 {
        .typename = "OPSPUT-PLD-IRQ",
        .startup = startup_opsput_pld_irq,
@@ -216,7 +216,7 @@ static void shutdown_opsput_lanpld_irq(unsigned int irq)
        outw(PLD_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type opsput_lanpld_irq_type =
+static struct irq_chip opsput_lanpld_irq_type =
 {
        .typename = "OPSPUT-PLD-LAN-IRQ",
        .startup = startup_opsput_lanpld_irq,
@@ -285,7 +285,7 @@ static void shutdown_opsput_lcdpld_irq(unsigned int irq)
        outw(PLD_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type opsput_lcdpld_irq_type =
+static struct irq_chip opsput_lcdpld_irq_type =
 {
        "OPSPUT-PLD-LCD-IRQ",
        startup_opsput_lcdpld_irq,
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
index 89588d649eb7..757302660af8 100644
--- a/arch/m32r/platforms/usrv/setup.c
+++ b/arch/m32r/platforms/usrv/setup.c
@@ -61,7 +61,7 @@ static void shutdown_mappi_irq(unsigned int irq)
        outl(M32R_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type mappi_irq_type =
+static struct irq_chip mappi_irq_type =
 {
        .typename = "M32700-IRQ",
        .startup = startup_mappi_irq,
@@ -134,7 +134,7 @@ static void shutdown_m32700ut_pld_irq(unsigned int irq)
        outw(PLD_ICUCR_ILEVEL7, port);
 }
-static struct hw_interrupt_type m32700ut_pld_irq_type =
+static struct irq_chip m32700ut_pld_irq_type =
 {
        .typename = "USRV-PLD-IRQ",
        .startup = startup_m32700ut_pld_irq,
diff --git a/arch/m68k/include/asm/kmap_types.h b/arch/m68k/include/asm/kmap_types.h
index c843c63d3801..3413cc1390ec 100644
--- a/arch/m68k/include/asm/kmap_types.h
+++ b/arch/m68k/include/asm/kmap_types.h
@@ -1,21 +1,6 @@
 #ifndef __ASM_M68K_KMAP_TYPES_H
 #define __ASM_M68K_KMAP_TYPES_H
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
 #endif  /* __ASM_M68K_KMAP_TYPES_H */
diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c
index ec37fb56c127..72bad65dba3a 100644
--- a/arch/m68k/kernel/process.c
+++ b/arch/m68k/kernel/process.c
@@ -42,10 +42,6 @@
 */
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 union thread_union init_thread_union
 __attribute__((section(".data.init_task"), aligned(THREAD_SIZE)))
       = { INIT_THREAD_INFO(init_task) };
diff --git a/arch/m68knommu/kernel/init_task.c b/arch/m68knommu/kernel/init_task.c
index fe282de1d596..45e97a207fed 100644
--- a/arch/m68knommu/kernel/init_task.c
+++ b/arch/m68knommu/kernel/init_task.c
@@ -14,10 +14,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial task structure.
 *
diff --git a/arch/microblaze/include/asm/kmap_types.h b/arch/microblaze/include/asm/kmap_types.h
index 4d7e222f5dd7..25975252d83d 100644
--- a/arch/microblaze/include/asm/kmap_types.h
+++ b/arch/microblaze/include/asm/kmap_types.h
@@ -1,29 +1,6 @@
-/*
- * Copyright (C) 2006 Atmark Techno, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
 #ifndef _ASM_MICROBLAZE_KMAP_TYPES_H
 #define _ASM_MICROBLAZE_KMAP_TYPES_H
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR,
-};
 #endif /* _ASM_MICROBLAZE_KMAP_TYPES_H */
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 783da855a2e3..d6d35b2e5fe8 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -963,7 +963,7 @@ CONFIG_EEPROM_LEGACY=y
 CONFIG_SENSORS_PCF8574=y
 # CONFIG_PCF8575 is not set
 CONFIG_SENSORS_PCF8591=y
-CONFIG_SENSORS_MAX6875=y
+CONFIG_EEPROM_MAX6875=y
 # CONFIG_SENSORS_TSL2550 is not set
 CONFIG_I2C_DEBUG_CORE=y
 CONFIG_I2C_DEBUG_ALGO=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 8426d3b9501c..fadb351d249b 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -1849,7 +1849,7 @@ CONFIG_EEPROM_LEGACY=m
 CONFIG_SENSORS_PCF8574=m
 CONFIG_SENSORS_PCA9539=m
 CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_MAX6875=m
+CONFIG_EEPROM_MAX6875=m
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
diff --git a/arch/mips/include/asm/errno.h b/arch/mips/include/asm/errno.h
index 3c0d840e4577..a0efc73819e4 100644
--- a/arch/mips/include/asm/errno.h
+++ b/arch/mips/include/asm/errno.h
@@ -119,6 +119,8 @@
 #define EOWNERDEAD      165     /* Owner died */
 #define ENOTRECOVERABLE 166     /* State not recoverable */
+#define ERFKILL         167     /* Operation not possible due to RF-kill */
 #define EDQUOT          1133    /* Quota exceeded */
 #ifdef __KERNEL__
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
index 5dabc870b322..032ca73f181b 100644
--- a/arch/mips/include/asm/i8253.h
+++ b/arch/mips/include/asm/i8253.h
@@ -12,8 +12,6 @@
 #define PIT_CH0                 0x40
 #define PIT_CH2                 0x42
-#define PIT_TICK_RATE           1193182UL
 extern spinlock_t i8253_lock;
 extern void setup_pit_timer(void);
diff --git a/arch/mips/include/asm/kmap_types.h b/arch/mips/include/asm/kmap_types.h
index 806aae3c5338..58e91ed0388f 100644
--- a/arch/mips/include/asm/kmap_types.h
+++ b/arch/mips/include/asm/kmap_types.h
@@ -1,30 +1,12 @@
 #ifndef _ASM_KMAP_TYPES_H
 #define _ASM_KMAP_TYPES_H
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
+#define  __WITH_KM_FENCE
-#else
-# define D(n)
 #endif
-enum km_type {
+#include <asm-generic/kmap_types.h>
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-#undef D
+#undef __WITH_KM_FENCE
 #endif
diff --git a/arch/mips/kernel/init_task.c b/arch/mips/kernel/init_task.c
index 149cd914526e..5b457a40c784 100644
--- a/arch/mips/kernel/init_task.c
+++ b/arch/mips/kernel/init_task.c
@@ -11,10 +11,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/mips/sni/eisa.c b/arch/mips/sni/eisa.c
index 7396cd719900..6827feb4de96 100644
--- a/arch/mips/sni/eisa.c
+++ b/arch/mips/sni/eisa.c
@@ -38,7 +38,7 @@ int __init sni_eisa_root_init(void)
        if (!r)
                return r;
-        eisa_root_dev.dev.driver_data = &eisa_bus_root;
+        dev_set_drvdata(&eisa_root_dev.dev, &eisa_bus_root);
        if (eisa_root_register(&eisa_bus_root)) {
                /* A real bridge may have been registered before
diff --git a/arch/mn10300/include/asm/kmap_types.h b/arch/mn10300/include/asm/kmap_types.h
index 3398f9f35603..76d093b58d4f 100644
--- a/arch/mn10300/include/asm/kmap_types.h
+++ b/arch/mn10300/include/asm/kmap_types.h
@@ -1,31 +1,6 @@
-/* MN10300 kmap_atomic() slot IDs
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
 #ifndef _ASM_KMAP_TYPES_H
 #define _ASM_KMAP_TYPES_H
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
 #endif /* _ASM_KMAP_TYPES_H */
diff --git a/arch/mn10300/include/asm/ptrace.h b/arch/mn10300/include/asm/ptrace.h
index 921942ed1b03..1b0ba5e182b0 100644
--- a/arch/mn10300/include/asm/ptrace.h
+++ b/arch/mn10300/include/asm/ptrace.h
@@ -77,8 +77,6 @@ struct pt_regs {
 };
 #endif
-extern struct pt_regs *__frame; /* current frame pointer */
 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
 #define PTRACE_GETREGS            12
 #define PTRACE_SETREGS            13
@@ -90,6 +88,8 @@ extern struct pt_regs *__frame; /* current frame pointer */
 #if defined(__KERNEL__)
+extern struct pt_regs *__frame;         /* current frame pointer */
 #if !defined(__ASSEMBLY__)
 struct task_struct;
@@ -107,5 +107,4 @@ extern void user_disable_single_step(struct task_struct *);
 #define profile_pc(regs) ((regs)->pc)
 #endif  /*  __KERNEL__  */
 #endif /* _ASM_PTRACE_H */
diff --git a/arch/mn10300/include/asm/setup.h b/arch/mn10300/include/asm/setup.h
index 08356c832283..c229d1e3f999 100644
--- a/arch/mn10300/include/asm/setup.h
+++ b/arch/mn10300/include/asm/setup.h
@@ -11,7 +11,8 @@
 #ifndef _ASM_SETUP_H
 #define _ASM_SETUP_H
+#ifdef __KERNEL__
 extern void __init unit_setup(void);
 extern void __init unit_init_IRQ(void);
+#endif
 #endif /* _ASM_SETUP_H */
diff --git a/arch/mn10300/kernel/init_task.c b/arch/mn10300/kernel/init_task.c
index 5ac3566f8c98..80d423b80af3 100644
--- a/arch/mn10300/kernel/init_task.c
+++ b/arch/mn10300/kernel/init_task.c
@@ -20,9 +20,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/parisc/include/asm/errno.h b/arch/parisc/include/asm/errno.h
index e2f3ddc796be..9992abdd782d 100644
--- a/arch/parisc/include/asm/errno.h
+++ b/arch/parisc/include/asm/errno.h
@@ -120,5 +120,6 @@
 #define EOWNERDEAD      254     /* Owner died */
 #define ENOTRECOVERABLE 255     /* State not recoverable */
+#define ERFKILL         256     /* Operation not possible due to RF-kill */
 #endif
diff --git a/arch/parisc/include/asm/kmap_types.h b/arch/parisc/include/asm/kmap_types.h
index 806aae3c5338..58e91ed0388f 100644
--- a/arch/parisc/include/asm/kmap_types.h
+++ b/arch/parisc/include/asm/kmap_types.h
@@ -1,30 +1,12 @@
 #ifndef _ASM_KMAP_TYPES_H
 #define _ASM_KMAP_TYPES_H
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
+#define  __WITH_KM_FENCE
-#else
-# define D(n)
 #endif
-enum km_type {
+#include <asm-generic/kmap_types.h>
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-#undef D
+#undef __WITH_KM_FENCE
 #endif
diff --git a/arch/parisc/kernel/init_task.c b/arch/parisc/kernel/init_task.c
index 1e25a45d64c1..82974b20fc10 100644
--- a/arch/parisc/kernel/init_task.c
+++ b/arch/parisc/kernel/init_task.c
@@ -36,10 +36,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial task structure.
 *
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index cdc9a6ff4be8..9fb344d5a86a 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -42,6 +42,10 @@ config GENERIC_HARDIRQS
        bool
        default y
+config GENERIC_HARDIRQS_NO__DO_IRQ
+        bool
+        default y
 config HAVE_SETUP_PER_CPU_AREA
        def_bool PPC64
@@ -89,10 +93,6 @@ config GENERIC_HWEIGHT
        bool
        default y
-config GENERIC_CALIBRATE_DELAY
-        bool
-        default y
 config GENERIC_FIND_NEXT_BIT
        bool
        default y
@@ -125,6 +125,7 @@ config PPC
        select USE_GENERIC_SMP_HELPERS if SMP
        select HAVE_OPROFILE
        select HAVE_SYSCALL_WRAPPERS if PPC64
+        select GENERIC_ATOMIC64 if PPC32
 config EARLY_PRINTK
        bool
@@ -296,9 +297,19 @@ config IOMMU_VMERGE
 config IOMMU_HELPER
        def_bool PPC64
+config SWIOTLB
+        bool "SWIOTLB support"
+        default n
+        select IOMMU_HELPER
+        ---help---
+          Support for IO bounce buffering for systems without an IOMMU.
+          This allows us to DMA to the full physical address space on
+          platforms where the size of a physical address is larger
+          than the bus address.  Not all platforms support this.
 config PPC_NEED_DMA_SYNC_OPS
        def_bool y
-        depends on NOT_COHERENT_CACHE
+        depends on (NOT_COHERENT_CACHE || SWIOTLB)
 config HOTPLUG_CPU
        bool "Support for enabling/disabling CPUs"
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index a1098e23221f..d79a902d155a 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -41,6 +41,19 @@ config HCALL_STATS
          This option will add a small amount of overhead to all hypervisor
          calls.
+config PPC_EMULATED_STATS
+        bool "Emulated instructions tracking"
+        depends on DEBUG_FS
+        help
+          Adds code to keep track of the number of instructions that are
+          emulated by the in-kernel emulator. Counters for the various classes
+          of emulated instructions are available under
+          powerpc/emulated_instructions/ in the root of the debugfs file
+          system. Optionally (controlled by
+          powerpc/emulated_instructions/do_warn in debugfs), rate-limited
+          warnings can be printed to the console when instructions are
+          emulated.
 config CODE_PATCHING_SELFTEST
        bool "Run self-tests of the code-patching code."
        depends on DEBUG_KERNEL
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 551fc58c05cf..bc35f4e2b81c 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -142,6 +142,7 @@ head-$(CONFIG_FSL_BOOKE)	:= arch/powerpc/kernel/head_fsl_booke.o
 head-$(CONFIG_PPC64)            += arch/powerpc/kernel/entry_64.o
 head-$(CONFIG_PPC_FPU)          += arch/powerpc/kernel/fpu.o
+head-$(CONFIG_ALTIVEC)          += arch/powerpc/kernel/vector.o
 core-y                          += arch/powerpc/kernel/ \
                                   arch/powerpc/mm/ \
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 53a7a6255909..910944edd886 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -164,9 +164,21 @@
                device_type = "soc";
                compatible = "fsl,mpc8641-soc", "simple-bus";
                ranges = <0x0 0xfef00000 0x00100000>;
-                reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
+                mcm-law@0 {
+                        compatible = "fsl,mcm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                mcm@1000 {
+                        compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 1569117e5ddc..0f4c9ec2c3a6 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -163,9 +163,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xfef00000 0x00100000>;
-                reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
+                mcm-law@0 {
+                        compatible = "fsl,mcm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                mcm@1000 {
+                        compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 6582dbd36da7..217f8aa66725 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -128,9 +128,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xfef00000 0x00100000>;
-                reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
+                mcm-law@0 {
+                        compatible = "fsl,mcm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                mcm@1000 {
+                        compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index c9cfd374bffb..bdb7fc0fa332 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -56,6 +56,19 @@
                ranges = <0x00000000 0xfdf00000 0x00100000>;
                bus-frequency = <0>;                            /* Fixed by bootwrapper */
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 57c595bf1071..436c9c671dd9 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -249,6 +249,8 @@
                reg = <0xe0100000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <198000000>;
+                fsl,qe-num-riscs = <1>;
+                fsl,qe-num-snums = <28>;
                muram@10000 {
                        #address-cells = <1>;
@@ -369,7 +371,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x11 AD17 */
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 4319bd70a580..9a0952f74b81 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -221,6 +221,8 @@
                reg = <0xe0100000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <198000000>;
+                fsl,qe-num-riscs = <1>;
+                fsl,qe-num-snums = <28>;
                muram@10000 {
                        #address-cells = <1>;
@@ -327,7 +329,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x10 AD16 (USB) */
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 1ae38f0ddef8..e3eeaeda9187 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -278,7 +278,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x10 - SATA */
@@ -301,7 +300,6 @@
        };
        pci1: pci@e0008600 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x0E - MiniPCI Slot */
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 662abe1fb804..eb732115f016 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -227,7 +227,6 @@
        };
        pci0: pci@e0008600 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x0F - PCI Slot */
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index d9f0a2325fa4..a2553a6f9009 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -286,7 +286,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
@@ -348,7 +347,6 @@
        };
        pci1: pci@e0008600 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 6e34f170fa62..39ff4c829caf 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -289,6 +289,8 @@
                reg = <0xe0100000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <396000000>;
+                fsl,qe-num-riscs = <2>;
+                fsl,qe-num-snums = <28>;
                muram@10000 {
                        #address-cells = <1>;
@@ -410,7 +412,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 37b789510d68..6315d6fcc58a 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -198,6 +198,8 @@
                        clock-frequency = <0>;
                        bus-frequency = <0>;
                        brg-frequency = <0>;
+                        fsl,qe-num-riscs = <2>;
+                        fsl,qe-num-snums = <28>;
                        muram@10000 {
                                #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 963708017e6c..67bb372c9451 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -383,7 +383,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 651ff2f9db2d..a955a577db81 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -367,7 +367,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index d6f208b8297a..d266ddbfc28d 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -397,7 +397,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index b31c5041350b..e781ad2f1f8a 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -51,9 +51,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xffe00000 0x100000>;
-                reg = <0xffe00000 0x1000>;
                bus-frequency = <0>;            // Filled out by uboot.
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8536-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8536-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -321,7 +333,6 @@
        };
        pci0: pci@ffe08000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
@@ -346,7 +357,6 @@
        };
        pci1: pcie@ffe09000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -383,7 +393,6 @@
        };
        pci2: pcie@ffe0a000 {
-                cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -420,7 +429,6 @@
        };
        pci3: pcie@ffe0b000 {
-                cell-index = <3>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index ddd67be10b03..9dc292962a9a 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -55,9 +55,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <0>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8540-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,8540-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -258,7 +270,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index e45097f44fbd..9a3ad311aedf 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -55,9 +55,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8541-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,8541-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -272,7 +284,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                interrupt-map = <
@@ -344,7 +355,6 @@
        };
        pci1: pci@e0009000 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 7c6932be0197..98e94b465662 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -57,9 +57,21 @@
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;            // Filled out by uboot.
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8544-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,8544-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -274,7 +286,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
@@ -306,7 +317,6 @@
        };
        pci1: pcie@e0009000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -343,7 +353,6 @@
        };
        pci2: pcie@e000a000 {
-                cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -380,7 +389,6 @@
        };
        pci3: pcie@e000b000 {
-                cell-index = <3>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 804e90353293..475be1433fe1 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -60,9 +60,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,8548-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -328,7 +340,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x4 (PCIX Slot 2) */
@@ -478,7 +489,6 @@
        };
        pci1: pci@e0009000 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
@@ -503,7 +513,6 @@
        };
        pci2: pcie@e000a000 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 9484f0729b10..065b2f093de2 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -55,9 +55,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,8555-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -272,7 +284,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                interrupt-map = <
@@ -344,7 +355,6 @@
        };
        pci1: pci@e0009000 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index cc2acf87d02f..a5bb1ec70a5a 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -55,9 +55,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x200>;
                bus-frequency = <330000000>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,8540-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -291,7 +303,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 9d52e3b25047..00c2bbda7013 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -26,6 +26,7 @@
                serial1 = &serial1;
                pci0 = &pci0;
                pci1 = &pci1;
+                rapidio0 = &rio0;
        };
        cpus {
@@ -62,9 +63,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x1000>;
                bus-frequency = <0>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8568-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,8568-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -275,6 +288,22 @@
                        device_type = "open-pic";
                };
+                msi@41600 {
+                        compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
                par_io@e0100 {
                        reg = <0xe0100 0x100>;
                        device_type = "par_io";
@@ -349,6 +378,8 @@
                reg = <0xe0080000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <396000000>;
+                fsl,qe-num-riscs = <2>;
+                fsl,qe-num-snums = <28>;
                muram@10000 {
                        #address-cells = <1>;
@@ -459,7 +490,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x12 AD18 */
@@ -490,7 +520,6 @@
        /* PCI Express */
        pci1: pcie@e000a000 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
@@ -526,4 +555,20 @@
                                  0x0 0x800000>;
                };
        };
+        rio0: rapidio@e00c00000 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
+                reg = <0xe00c0000 0x20000>;
+                ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
+                interrupts = <48 2 /* error     */
+                              49 2 /* bell_outb */
+                              50 2 /* bell_inb  */
+                              53 2 /* msg1_tx   */
+                              54 2 /* msg1_rx   */
+                              55 2 /* msg2_tx   */
+                              56 2 /* msg2_rx   */>;
+                interrupt-parent = <&mpic>;
+        };
 };
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
new file mode 100644
index 000000000000..39c2927503cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -0,0 +1,583 @@
+/*
+ * MPC8569E MDS Device Tree Source
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/ {
+        model = "MPC8569EMDS";
+        compatible = "fsl,MPC8569EMDS";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial1;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                pci1 = &pci1;
+                rapidio0 = &rio0;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8569@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        memory {
+                device_type = "memory";
+        };
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xe0005000 0x1000>;
+                interrupts = <19 2>;
+                interrupt-parent = <&mpic>;
+                ranges = <0x0 0x0 0xfe000000 0x02000000
+                          0x1 0x0 0xf8000000 0x00008000
+                          0x2 0x0 0xf0000000 0x04000000
+                          0x3 0x0 0xfc000000 0x00008000
+                          0x4 0x0 0xf8008000 0x00008000
+                          0x5 0x0 0xf8010000 0x00008000>;
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x02000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
+                bcsr@1,0 {
+                        compatible = "fsl,mpc8569mds-bcsr";
+                        reg = <1 0 0x8000>;
+                };
+                nand@3,0 {
+                        compatible = "fsl,mpc8569-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <3 0 0x8000>;
+                };
+                pib@4,0 {
+                        compatible = "fsl,mpc8569mds-pib";
+                        reg = <4 0 0x8000>;
+                };
+                pib@5,0 {
+                        compatible = "fsl,mpc8569mds-pib";
+                        reg = <5 0 0x8000>;
+                };
+        };
+        soc@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,mpc8569-immr", "simple-bus";
+                ranges = <0x0 0xe0000000 0x100000>;
+                bus-frequency = <0>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8569-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                memory-controller@2000 {
+                        compatible = "fsl,mpc8569-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds1374";
+                                reg = <0x68>;
+                        };
+                };
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,mpc8569-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2, 512K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8569-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8569-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8569-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8569-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+                sdhci@2e000 {
+                        compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x8>;
+                        interrupt-parent = <&mpic>;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                        status = "disabled";
+                };
+                crypto@30000 {
+                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+                                "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0xbfe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+                msi@41600 {
+                        compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+                global-utilities@e0000 {
+                        compatible = "fsl,mpc8569-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+                par_io@e0100 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xe0100 0x100>;
+                        ranges = <0x0 0xe0100 0x100>;
+                        device_type = "par_io";
+                        num-ports = <7>;
+                        qe_pio_e: gpio-controller@80 {
+                                #gpio-cells = <2>;
+                                compatible = "fsl,mpc8569-qe-pario-bank",
+                                             "fsl,mpc8323-qe-pario-bank";
+                                reg = <0x80 0x18>;
+                                gpio-controller;
+                        };
+                        pio1: ucc_pin@01 {
+                                pio-map = <
+                        /* port  pin  dir  open_drain  assignment  has_irq */
+                                        0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                        0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                        0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
+                                        0x0  0x0  0x1  0x0  0x3  0x0    /* ENET1_TXD0_SER1_TXD0 */
+                                        0x0  0x1  0x1  0x0  0x3  0x0    /* ENET1_TXD1_SER1_TXD1 */
+                                        0x0  0x2  0x1  0x0  0x1  0x0    /* ENET1_TXD2_SER1_TXD2 */
+                                        0x0  0x3  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
+                                        0x0  0x6  0x2  0x0  0x3  0x0    /* ENET1_RXD0_SER1_RXD0 */
+                                        0x0  0x7  0x2  0x0  0x1  0x0    /* ENET1_RXD1_SER1_RXD1 */
+                                        0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
+                                        0x0  0x9  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
+                                        0x0  0x4  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
+                                        0x0  0xc  0x2  0x0  0x3  0x0    /* ENET1_RX_DV_SER1_CTS_B */
+                                        0x2  0x8  0x2  0x0  0x1  0x0    /* ENET1_GRXCLK */
+                                        0x2  0x14 0x1  0x0  0x2  0x0>;  /* ENET1_GTXCLK */
+                        };
+                        pio2: ucc_pin@02 {
+                                pio-map = <
+                        /* port  pin  dir  open_drain  assignment  has_irq */
+                                        0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                        0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                        0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
+                                        0x0  0xe  0x1  0x0  0x2  0x0    /* ENET2_TXD0_SER2_TXD0 */
+                                        0x0  0xf  0x1  0x0  0x2  0x0    /* ENET2_TXD1_SER2_TXD1 */
+                                        0x0  0x10 0x1  0x0  0x1  0x0    /* ENET2_TXD2_SER2_TXD2 */
+                                        0x0  0x11 0x1  0x0  0x1  0x0    /* ENET2_TXD3_SER2_TXD3 */
+                                        0x0  0x14 0x2  0x0  0x2  0x0    /* ENET2_RXD0_SER2_RXD0 */
+                                        0x0  0x15 0x2  0x0  0x1  0x0    /* ENET2_RXD1_SER2_RXD1 */
+                                        0x0  0x16 0x2  0x0  0x1  0x0    /* ENET2_RXD2_SER2_RXD2 */
+                                        0x0  0x17 0x2  0x0  0x1  0x0    /* ENET2_RXD3_SER2_RXD3 */
+                                        0x0  0x12 0x1  0x0  0x2  0x0    /* ENET2_TX_EN_SER2_RTS_B */
+                                        0x0  0x1a 0x2  0x0  0x3  0x0    /* ENET2_RX_DV_SER2_CTS_B */
+                                        0x2  0x3  0x2  0x0  0x1  0x0    /* ENET2_GRXCLK */
+                                        0x2  0x2 0x1  0x0  0x2  0x0>;   /* ENET2_GTXCLK */
+                        };
+                        pio3: ucc_pin@03 {
+                                pio-map = <
+                        /* port  pin  dir  open_drain  assignment  has_irq */
+                                        0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                        0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                        0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
+                                        0x0  0x1d 0x1  0x0  0x2  0x0    /* ENET3_TXD0_SER3_TXD0 */
+                                        0x0  0x1e 0x1  0x0  0x3  0x0    /* ENET3_TXD1_SER3_TXD1 */
+                                        0x0  0x1f 0x1  0x0  0x2  0x0    /* ENET3_TXD2_SER3_TXD2 */
+                                        0x1  0x0  0x1  0x0  0x3  0x0    /* ENET3_TXD3_SER3_TXD3 */
+                                        0x1  0x3  0x2  0x0  0x3  0x0    /* ENET3_RXD0_SER3_RXD0 */
+                                        0x1  0x4  0x2  0x0  0x1  0x0    /* ENET3_RXD1_SER3_RXD1 */
+                                        0x1  0x5  0x2  0x0  0x2  0x0    /* ENET3_RXD2_SER3_RXD2 */
+                                        0x1  0x6  0x2  0x0  0x3  0x0    /* ENET3_RXD3_SER3_RXD3 */
+                                        0x1  0x1  0x1  0x0  0x1  0x0    /* ENET3_TX_EN_SER3_RTS_B */
+                                        0x1  0x9  0x2  0x0  0x3  0x0    /* ENET3_RX_DV_SER3_CTS_B */
+                                        0x2  0x9  0x2  0x0  0x2  0x0    /* ENET3_GRXCLK */
+                                        0x2  0x19 0x1  0x0  0x2  0x0>;  /* ENET3_GTXCLK */
+                        };
+                        pio4: ucc_pin@04 {
+                                pio-map = <
+                        /* port  pin  dir  open_drain  assignment  has_irq */
+                                        0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                        0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                        0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
+                                        0x1  0xc  0x1  0x0  0x2  0x0    /* ENET4_TXD0_SER4_TXD0 */
+                                        0x1  0xd  0x1  0x0  0x2  0x0    /* ENET4_TXD1_SER4_TXD1 */
+                                        0x1  0xe  0x1  0x0  0x1  0x0    /* ENET4_TXD2_SER4_TXD2 */
+                                        0x1  0xf  0x1  0x0  0x2  0x0    /* ENET4_TXD3_SER4_TXD3 */
+                                        0x1  0x12 0x2  0x0  0x2  0x0    /* ENET4_RXD0_SER4_RXD0 */
+                                        0x1  0x13 0x2  0x0  0x1  0x0    /* ENET4_RXD1_SER4_RXD1 */
+                                        0x1  0x14 0x2  0x0  0x1  0x0    /* ENET4_RXD2_SER4_RXD2 */
+                                        0x1  0x15 0x2  0x0  0x2  0x0    /* ENET4_RXD3_SER4_RXD3 */
+                                        0x1  0x10 0x1  0x0  0x2  0x0    /* ENET4_TX_EN_SER4_RTS_B */
+                                        0x1  0x18 0x2  0x0  0x3  0x0    /* ENET4_RX_DV_SER4_CTS_B */
+                                        0x2  0x11 0x2  0x0  0x2  0x0    /* ENET4_GRXCLK */
+                                        0x2  0x18 0x1  0x0  0x2  0x0>;  /* ENET4_GTXCLK */
+                        };
+                };
+        };
+        qe@e0080000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "qe";
+                compatible = "fsl,qe";
+                ranges = <0x0 0xe0080000 0x40000>;
+                reg = <0xe0080000 0x480>;
+                brg-frequency = <0>;
+                bus-frequency = <0>;
+                fsl,qe-num-riscs = <4>;
+                fsl,qe-num-snums = <46>;
+                qeic: interrupt-controller@80 {
+                        interrupt-controller;
+                        compatible = "fsl,qe-ic";
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                        reg = <0x80 0x80>;
+                        interrupts = <46 2 46 2>; //high:30 low:30
+                        interrupt-parent = <&mpic>;
+                };
+                spi@4c0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
+                        reg = <0x4c0 0x40>;
+                        cell-index = <0>;
+                        interrupts = <2>;
+                        interrupt-parent = <&qeic>;
+                        gpios = <&qe_pio_e 30 0>;
+                        mode = "cpu-qe";
+                        serial-flash@0 {
+                                compatible = "stm,m25p40";
+                                reg = <0>;
+                                spi-max-frequency = <25000000>;
+                        };
+                };
+                spi@500 {
+                        cell-index = <1>;
+                        compatible = "fsl,spi";
+                        reg = <0x500 0x40>;
+                        interrupts = <1>;
+                        interrupt-parent = <&qeic>;
+                        mode = "cpu";
+                };
+                enet0: ucc@2000 {
+                        device_type = "network";
+                        compatible = "ucc_geth";
+                        cell-index = <1>;
+                        reg = <0x2000 0x200>;
+                        interrupts = <32>;
+                        interrupt-parent = <&qeic>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        rx-clock-name = "none";
+                        tx-clock-name = "clk12";
+                        pio-handle = <&pio1>;
+                        phy-handle = <&qe_phy0>;
+                        phy-connection-type = "rgmii-id";
+                };
+                mdio@2120 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x2120 0x18>;
+                        compatible = "fsl,ucc-mdio";
+                        qe_phy0: ethernet-phy@07 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <1 1>;
+                                reg = <0x7>;
+                                device_type = "ethernet-phy";
+                        };
+                        qe_phy1: ethernet-phy@01 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <2 1>;
+                                reg = <0x1>;
+                                device_type = "ethernet-phy";
+                        };
+                        qe_phy2: ethernet-phy@02 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <3 1>;
+                                reg = <0x2>;
+                                device_type = "ethernet-phy";
+                        };
+                        qe_phy3: ethernet-phy@03 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <4 1>;
+                                reg = <0x3>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+                enet2: ucc@2200 {
+                        device_type = "network";
+                        compatible = "ucc_geth";
+                        cell-index = <3>;
+                        reg = <0x2200 0x200>;
+                        interrupts = <34>;
+                        interrupt-parent = <&qeic>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        rx-clock-name = "none";
+                        tx-clock-name = "clk12";
+                        pio-handle = <&pio3>;
+                        phy-handle = <&qe_phy2>;
+                        phy-connection-type = "rgmii-id";
+                };
+                enet1: ucc@3000 {
+                        device_type = "network";
+                        compatible = "ucc_geth";
+                        cell-index = <2>;
+                        reg = <0x3000 0x200>;
+                        interrupts = <33>;
+                        interrupt-parent = <&qeic>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        rx-clock-name = "none";
+                        tx-clock-name = "clk17";
+                        pio-handle = <&pio2>;
+                        phy-handle = <&qe_phy1>;
+                        phy-connection-type = "rgmii-id";
+                };
+                enet3: ucc@3200 {
+                        device_type = "network";
+                        compatible = "ucc_geth";
+                        cell-index = <4>;
+                        reg = <0x3200 0x200>;
+                        interrupts = <35>;
+                        interrupt-parent = <&qeic>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        rx-clock-name = "none";
+                        tx-clock-name = "clk17";
+                        pio-handle = <&pio4>;
+                        phy-handle = <&qe_phy3>;
+                        phy-connection-type = "rgmii-id";
+                };
+                muram@10000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,qe-muram", "fsl,cpm-muram";
+                        ranges = <0x0 0x10000 0x20000>;
+                        data-only@0 {
+                                compatible = "fsl,qe-muram-data",
+                                             "fsl,cpm-muram-data";
+                                reg = <0x0 0x20000>;
+                        };
+                };
+        };
+        /* PCI Express */
+        pci1: pcie@e000a000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe000a000 0x1000>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 (PEX) */
+                        00000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        00000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        00000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+                interrupt-parent = <&mpic>;
+                interrupts = <26 2>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
+                clock-frequency = <33333333>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x10000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x800000>;
+                };
+        };
+        rio0: rapidio@e00c00000 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
+                reg = <0xe00c0000 0x20000>;
+                ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
+                interrupts = <48 2 /* error     */
+                              49 2 /* bell_outb */
+                              50 2 /* bell_inb  */
+                              53 2 /* msg1_tx   */
+                              54 2 /* msg1_rx   */
+                              55 2 /* msg2_tx   */
+                              56 2 /* msg2_rx   */>;
+                interrupt-parent = <&mpic>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 6e79a4169088..cafc1285c140 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -182,9 +182,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0 0xffe00000 0x100000>;
-                reg = <0 0xffe00000 0 0x1000>;  // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8572-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -514,7 +526,6 @@
        };
        pci0: pcie@ffe08000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -724,7 +735,6 @@
        };
        pci1: pcie@ffe09000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -761,7 +771,6 @@
        };
        pci2: pcie@ffe0a000 {
-                cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
index dbd81a764742..f6365db3b97d 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -182,9 +182,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xf 0xffe00000 0x100000>;
-                reg = <0xf 0xffe00000 0 0x1000>;        // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8572-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -514,7 +526,6 @@
        };
        pci0: pcie@fffe08000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -522,7 +533,7 @@
                #address-cells = <3>;
                reg = <0xf 0xffe08000 0 0x1000>;
                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
@@ -649,8 +660,8 @@
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0xc0000000
+                        ranges = <0x2000000 0x0 0xe0000000
-                                  0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
                                  0x1000000 0x0 0x0
@@ -660,8 +671,8 @@
                                reg = <0x0 0x0 0x0 0x0 0x0>;
                                #size-cells = <2>;
                                #address-cells = <3>;
-                                ranges = <0x2000000 0x0 0xc0000000
+                                ranges = <0x2000000 0x0 0xe0000000
-                                          0x2000000 0x0 0xc0000000
+                                          0x2000000 0x0 0xe0000000
                                          0x0 0x20000000
                                          0x1000000 0x0 0x0
@@ -724,7 +735,6 @@
        };
        pci1: pcie@fffe09000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -732,7 +742,7 @@
                #address-cells = <3>;
                reg = <0xf 0xffe09000 0 0x1000>;
                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
@@ -750,8 +760,8 @@
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0xc0000000
+                        ranges = <0x2000000 0x0 0xe0000000
-                                  0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
                                  0x1000000 0x0 0x0
@@ -761,7 +771,6 @@
        };
        pci2: pcie@fffe0a000 {
-                cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -769,7 +778,7 @@
                #address-cells = <3>;
                reg = <0xf 0xffe0a000 0 0x1000>;
                bus-range = <0 255>;
-                ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
@@ -787,8 +796,8 @@
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                        ranges = <0x2000000 0x0 0xc0000000
+                        ranges = <0x2000000 0x0 0xe0000000
-                                  0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
                                  0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 2bc0c7189653..5bd1011fde96 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -59,9 +59,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xffe00000 0x100000>;
-                reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8572-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -238,7 +250,6 @@
        };
        pci0: pcie@ffe08000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -448,7 +459,6 @@
        };
        pci1: pcie@ffe09000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index 159cb3a875f0..0efc3456e297 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -58,7 +58,6 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xffe00000 0x100000>;
-                reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
                L2: l2-cache-controller@20000 {
@@ -196,7 +195,6 @@
        };
        pci2: pcie@ffe0a000 {
-                cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 1bd3ebe11437..cfc2c60d1f5f 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -112,9 +112,21 @@
                device_type = "soc";
                compatible = "fsl,mpc8610-immr", "simple-bus";
                ranges = <0x0 0xe0000000 0x00100000>;
-                reg = <0xe0000000 0x1000>;
                bus-frequency = <0>;
+                mcm-law@0 {
+                        compatible = "fsl,mcm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                mcm@1000 {
+                        compatible = "fsl,mpc8610-mcm", "fsl,mcm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -316,7 +328,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8610-pci";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -346,7 +357,6 @@
        };
        pci1: pcie@e000a000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index d72beb192460..848320e4d3c4 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -114,9 +114,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x00000000 0xffe00000 0x00100000>;
-                reg = <0xffe00000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
+                mcm-law@0 {
+                        compatible = "fsl,mcm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                mcm@1000 {
+                        compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -357,7 +369,6 @@
        };
        pci0: pcie@ffe08000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -566,7 +577,6 @@
        };
        pci1: pcie@ffe09000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
new file mode 100644
index 000000000000..8be8e701e1d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
@@ -0,0 +1,609 @@
+/*
+ * MPC8641 HPCN Device Tree Source
+ *
+ * Copyright 2008-2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/ {
+        model = "MPC8641HPCN";
+        compatible = "fsl,mpc8641hpcn";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,8641@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <32768>;         // L1, 32K
+                        i-cache-size = <32768>;         // L1, 32K
+                        timebase-frequency = <0>;       // 33 MHz, from uboot
+                        bus-frequency = <0>;            // From uboot
+                        clock-frequency = <0>;          // From uboot
+                };
+                PowerPC,8641@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <32768>;         // L1, 32K
+                        i-cache-size = <32768>;         // L1, 32K
+                        timebase-frequency = <0>;       // 33 MHz, from uboot
+                        bus-frequency = <0>;            // From uboot
+                        clock-frequency = <0>;          // From uboot
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x00000000 0x0 0x40000000>;  // 1G at 0x0
+        };
+        localbus@fffe05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8641-localbus", "simple-bus";
+                reg = <0x0f 0xffe05000 0x0 0x1000>;
+                interrupts = <19 2>;
+                interrupt-parent = <&mpic>;
+                ranges = <0 0 0xf 0xef800000 0x00800000
+                          2 0 0xf 0xffdf8000 0x00008000
+                          3 0 0xf 0xffdf0000 0x00008000>;
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x00800000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@0 {
+                                label = "kernel";
+                                reg = <0x00000000 0x00300000>;
+                        };
+                        partition@300000 {
+                                label = "firmware b";
+                                reg = <0x00300000 0x00100000>;
+                                read-only;
+                        };
+                        partition@400000 {
+                                label = "fs";
+                                reg = <0x00400000 0x00300000>;
+                        };
+                        partition@700000 {
+                                label = "firmware a";
+                                reg = <0x00700000 0x00100000>;
+                                read-only;
+                        };
+                };
+        };
+        soc8641@fffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
+                bus-frequency = <0>;
+                mcm-law@0 {
+                        compatible = "fsl,mcm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                mcm@1000 {
+                        compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8641-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8641-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8641-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8641-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+                                phy0: ethernet-phy@0 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 1>;
+                                        reg = <0>;
+                                        device_type = "ethernet-phy";
+                                };
+                                phy1: ethernet-phy@1 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 1>;
+                                        reg = <1>;
+                                        device_type = "ethernet-phy";
+                                };
+                                phy2: ethernet-phy@2 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 1>;
+                                        reg = <2>;
+                                        device_type = "ethernet-phy";
+                                };
+                                phy3: ethernet-phy@3 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 1>;
+                                        reg = <3>;
+                                        device_type = "ethernet-phy";
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+                enet2: ethernet@26000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <2>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        ranges = <0x0 0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi2>;
+                        phy-handle = <&phy2>;
+                        phy-connection-type = "rgmii-id";
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+                                tbi2: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+                enet3: ethernet@27000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <3>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x27000 0x1000>;
+                        ranges = <0x0 0x27000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <37 2 38 2 39 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi3>;
+                        phy-handle = <&phy3>;
+                        phy-connection-type = "rgmii-id";
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+                                tbi3: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <28 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+                global-utilities@e0000 {
+                        compatible = "fsl,mpc8641-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+        pci0: pcie@fffe08000 {
+                cell-index = <0>;
+                compatible = "fsl,mpc8641-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0x0f 0xffe08000 0x0 0x1000>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <24 2>;
+                interrupt-map-mask = <0xff00 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x11 func 0 - PCI slot 1 */
+                        0x8800 0 0 1 &mpic 2 1
+                        0x8800 0 0 2 &mpic 3 1
+                        0x8800 0 0 3 &mpic 4 1
+                        0x8800 0 0 4 &mpic 1 1
+                        /* IDSEL 0x11 func 1 - PCI slot 1 */
+                        0x8900 0 0 1 &mpic 2 1
+                        0x8900 0 0 2 &mpic 3 1
+                        0x8900 0 0 3 &mpic 4 1
+                        0x8900 0 0 4 &mpic 1 1
+                        /* IDSEL 0x11 func 2 - PCI slot 1 */
+                        0x8a00 0 0 1 &mpic 2 1
+                        0x8a00 0 0 2 &mpic 3 1
+                        0x8a00 0 0 3 &mpic 4 1
+                        0x8a00 0 0 4 &mpic 1 1
+                        /* IDSEL 0x11 func 3 - PCI slot 1 */
+                        0x8b00 0 0 1 &mpic 2 1
+                        0x8b00 0 0 2 &mpic 3 1
+                        0x8b00 0 0 3 &mpic 4 1
+                        0x8b00 0 0 4 &mpic 1 1
+                        /* IDSEL 0x11 func 4 - PCI slot 1 */
+                        0x8c00 0 0 1 &mpic 2 1
+                        0x8c00 0 0 2 &mpic 3 1
+                        0x8c00 0 0 3 &mpic 4 1
+                        0x8c00 0 0 4 &mpic 1 1
+                        /* IDSEL 0x11 func 5 - PCI slot 1 */
+                        0x8d00 0 0 1 &mpic 2 1
+                        0x8d00 0 0 2 &mpic 3 1
+                        0x8d00 0 0 3 &mpic 4 1
+                        0x8d00 0 0 4 &mpic 1 1
+                        /* IDSEL 0x11 func 6 - PCI slot 1 */
+                        0x8e00 0 0 1 &mpic 2 1
+                        0x8e00 0 0 2 &mpic 3 1
+                        0x8e00 0 0 3 &mpic 4 1
+                        0x8e00 0 0 4 &mpic 1 1
+                        /* IDSEL 0x11 func 7 - PCI slot 1 */
+                        0x8f00 0 0 1 &mpic 2 1
+                        0x8f00 0 0 2 &mpic 3 1
+                        0x8f00 0 0 3 &mpic 4 1
+                        0x8f00 0 0 4 &mpic 1 1
+                        /* IDSEL 0x12 func 0 - PCI slot 2 */
+                        0x9000 0 0 1 &mpic 3 1
+                        0x9000 0 0 2 &mpic 4 1
+                        0x9000 0 0 3 &mpic 1 1
+                        0x9000 0 0 4 &mpic 2 1
+                        /* IDSEL 0x12 func 1 - PCI slot 2 */
+                        0x9100 0 0 1 &mpic 3 1
+                        0x9100 0 0 2 &mpic 4 1
+                        0x9100 0 0 3 &mpic 1 1
+                        0x9100 0 0 4 &mpic 2 1
+                        /* IDSEL 0x12 func 2 - PCI slot 2 */
+                        0x9200 0 0 1 &mpic 3 1
+                        0x9200 0 0 2 &mpic 4 1
+                        0x9200 0 0 3 &mpic 1 1
+                        0x9200 0 0 4 &mpic 2 1
+                        /* IDSEL 0x12 func 3 - PCI slot 2 */
+                        0x9300 0 0 1 &mpic 3 1
+                        0x9300 0 0 2 &mpic 4 1
+                        0x9300 0 0 3 &mpic 1 1
+                        0x9300 0 0 4 &mpic 2 1
+                        /* IDSEL 0x12 func 4 - PCI slot 2 */
+                        0x9400 0 0 1 &mpic 3 1
+                        0x9400 0 0 2 &mpic 4 1
+                        0x9400 0 0 3 &mpic 1 1
+                        0x9400 0 0 4 &mpic 2 1
+                        /* IDSEL 0x12 func 5 - PCI slot 2 */
+                        0x9500 0 0 1 &mpic 3 1
+                        0x9500 0 0 2 &mpic 4 1
+                        0x9500 0 0 3 &mpic 1 1
+                        0x9500 0 0 4 &mpic 2 1
+                        /* IDSEL 0x12 func 6 - PCI slot 2 */
+                        0x9600 0 0 1 &mpic 3 1
+                        0x9600 0 0 2 &mpic 4 1
+                        0x9600 0 0 3 &mpic 1 1
+                        0x9600 0 0 4 &mpic 2 1
+                        /* IDSEL 0x12 func 7 - PCI slot 2 */
+                        0x9700 0 0 1 &mpic 3 1
+                        0x9700 0 0 2 &mpic 4 1
+                        0x9700 0 0 3 &mpic 1 1
+                        0x9700 0 0 4 &mpic 2 1
+                        // IDSEL 0x1c  USB
+                        0xe000 0 0 1 &i8259 12 2
+                        0xe100 0 0 2 &i8259 9 2
+                        0xe200 0 0 3 &i8259 10 2
+                        0xe300 0 0 4 &i8259 11 2
+                        // IDSEL 0x1d  Audio
+                        0xe800 0 0 1 &i8259 6 2
+                        // IDSEL 0x1e Legacy
+                        0xf000 0 0 1 &i8259 7 2
+                        0xf100 0 0 1 &i8259 7 2
+                        // IDSEL 0x1f IDE/SATA
+                        0xf800 0 0 1 &i8259 14 2
+                        0xf900 0 0 1 &i8259 5 2
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0x0 0xe0000000
+                                  0x02000000 0x0 0xe0000000
+                                  0x0 0x20000000
+                                  0x01000000 0x0 0x00000000
+                                  0x01000000 0x0 0x00000000
+                                  0x0 0x00010000>;
+                        uli1575@0 {
+                                reg = <0 0 0 0 0>;
+                                #size-cells = <2>;
+                                #address-cells = <3>;
+                                ranges = <0x02000000 0x0 0xe0000000
+                                          0x02000000 0x0 0xe0000000
+                                          0x0 0x20000000
+                                          0x01000000 0x0 0x00000000
+                                          0x01000000 0x0 0x00000000
+                                          0x0 0x00010000>;
+                                isa@1e {
+                                        device_type = "isa";
+                                        #interrupt-cells = <2>;
+                                        #size-cells = <1>;
+                                        #address-cells = <2>;
+                                        reg = <0xf000 0 0 0 0>;
+                                        ranges = <1 0 0x01000000 0 0
+                                                  0x00001000>;
+                                        interrupt-parent = <&i8259>;
+                                        i8259: interrupt-controller@20 {
+                                                reg = <1 0x20 2
+                                                       1 0xa0 2
+                                                       1 0x4d0 2>;
+                                                interrupt-controller;
+                                                device_type = "interrupt-controller";
+                                                #address-cells = <0>;
+                                                #interrupt-cells = <2>;
+                                                compatible = "chrp,iic";
+                                                interrupts = <9 2>;
+                                                interrupt-parent = <&mpic>;
+                                        };
+                                        i8042@60 {
+                                                #size-cells = <0>;
+                                                #address-cells = <1>;
+                                                reg = <1 0x60 1 1 0x64 1>;
+                                                interrupts = <1 3 12 3>;
+                                                interrupt-parent =
+                                                        <&i8259>;
+                                                keyboard@0 {
+                                                        reg = <0>;
+                                                        compatible = "pnpPNP,303";
+                                                };
+                                                mouse@1 {
+                                                        reg = <1>;
+                                                        compatible = "pnpPNP,f03";
+                                                };
+                                        };
+                                        rtc@70 {
+                                                compatible =
+                                                        "pnpPNP,b00";
+                                                reg = <1 0x70 2>;
+                                        };
+                                        gpio@400 {
+                                                reg = <1 0x400 0x80>;
+                                        };
+                                };
+                        };
+                };
+        };
+        pci1: pcie@fffe09000 {
+                cell-index = <1>;
+                compatible = "fsl,mpc8641-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0x0f 0xffe09000 0x0 0x1000>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0x0000 0 0 1 &mpic 4 1
+                        0x0000 0 0 2 &mpic 5 1
+                        0x0000 0 0 3 &mpic 6 1
+                        0x0000 0 0 4 &mpic 7 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0x0 0xe0000000
+                                  0x02000000 0x0 0xe0000000
+                                  0x0 0x20000000
+                                  0x01000000 0x0 0x00000000
+                                  0x01000000 0x0 0x00000000
+                                  0x0 0x00010000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
new file mode 100644
index 000000000000..11019142813c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -0,0 +1,704 @@
+/*
+ * P2020 DS Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/ {
+        model = "fsl,P2020";
+        compatible = "fsl,P2020DS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                PowerPC,P2020@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+                PowerPC,P2020@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+        memory {
+                device_type = "memory";
+        };
+        localbus@ffe05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,elbc", "simple-bus";
+                reg = <0 0xffe05000 0 0x1000>;
+                interrupts = <19 2>;
+                interrupt-parent = <&mpic>;
+                ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
+                          0x1 0x0 0x0 0xe0000000 0x08000000
+                          0x2 0x0 0x0 0xffa00000 0x00040000
+                          0x3 0x0 0x0 0xffdf0000 0x00008000
+                          0x4 0x0 0x0 0xffa40000 0x00040000
+                          0x5 0x0 0x0 0xffa80000 0x00040000
+                          0x6 0x0 0x0 0xffac0000 0x00040000>;
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                        ramdisk@0 {
+                                reg = <0x0 0x03000000>;
+                                read-only;
+                        };
+                        diagnostic@3000000 {
+                                reg = <0x03000000 0x00e00000>;
+                                read-only;
+                        };
+                        dink@3e00000 {
+                                reg = <0x03e00000 0x00200000>;
+                                read-only;
+                        };
+                        kernel@4000000 {
+                                reg = <0x04000000 0x00400000>;
+                                read-only;
+                        };
+                        jffs2@4400000 {
+                                reg = <0x04400000 0x03b00000>;
+                        };
+                        dtb@7f00000 {
+                                reg = <0x07f00000 0x00080000>;
+                                read-only;
+                        };
+                        u-boot@7f80000 {
+                                reg = <0x07f80000 0x00080000>;
+                                read-only;
+                        };
+                };
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x2 0x0 0x40000>;
+                        u-boot@0 {
+                                reg = <0x0 0x02000000>;
+                                read-only;
+                        };
+                        jffs2@2000000 {
+                                reg = <0x02000000 0x10000000>;
+                        };
+                        ramdisk@12000000 {
+                                reg = <0x12000000 0x08000000>;
+                                read-only;
+                        };
+                        kernel@1a000000 {
+                                reg = <0x1a000000 0x04000000>;
+                        };
+                        dtb@1e000000 {
+                                reg = <0x1e000000 0x01000000>;
+                                read-only;
+                        };
+                        empty@1f000000 {
+                                reg = <0x1f000000 0x21000000>;
+                        };
+                };
+                nand@4,0 {
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x4 0x0 0x40000>;
+                };
+                nand@5,0 {
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x5 0x0 0x40000>;
+                };
+                nand@6,0 {
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x6 0x0 0x40000>;
+                };
+        };
+        soc@ffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,p2020-immr", "simple-bus";
+                ranges = <0x0 0 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,p2020-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                memory-controller@2000 {
+                        compatible = "fsl,p2020-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+                spi@7000 {
+                        compatible = "fsl,espi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <59 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+                dma@c300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0xc300 0x4>;
+                        ranges = <0x0 0xc100 0x200>;
+                        cell-index = <1>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <76 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <77 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <78 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <79 2>;
+                        };
+                };
+                gpio: gpio-controller@f000 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8572-gpio";
+                        reg = <0xf000 0x100>;
+                        interrupts = <47 0x2>;
+                        interrupt-parent = <&mpic>;
+                        gpio-controller;
+                };
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,p2020-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x80000>; // L2, 512k
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+                usb@22000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x22000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+                                phy0: ethernet-phy@0 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <3 1>;
+                                        reg = <0x0>;
+                                };
+                                phy1: ethernet-phy@1 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <3 1>;
+                                        reg = <0x1>;
+                                };
+                                phy2: ethernet-phy@2 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <3 1>;
+                                        reg = <0x2>;
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+                enet2: ethernet@26000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <2>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        ranges = <0x0 0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi2>;
+                        phy-handle = <&phy2>;
+                        phy-connection-type = "rgmii-id";
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+                                tbi2: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+                sdhci@2e000 {
+                        compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        interrupt-parent = <&mpic>;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                };
+                crypto@30000 {
+                        compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+                                     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0xbfe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+                msi@41600 {
+                        compatible = "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,p2020-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+        pci0: pcie@ffe08000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe08000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <24 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x8 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x9 0x1
+                        0000 0x0 0x0 0x3 &mpic 0xa 0x1
+                        0000 0x0 0x0 0x4 &mpic 0xb 0x1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                };
+        };
+        pci1: pcie@ffe09000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe09000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                interrupt-map = <
+                        // IDSEL 0x11 func 0 - PCI slot 1
+                        0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 1 - PCI slot 1
+                        0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 2 - PCI slot 1
+                        0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 3 - PCI slot 1
+                        0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 4 - PCI slot 1
+                        0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 5 - PCI slot 1
+                        0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 6 - PCI slot 1
+                        0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x11 func 7 - PCI slot 1
+                        0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
+                        0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
+                        // IDSEL 0x1d  Audio
+                        0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+                        // IDSEL 0x1e Legacy
+                        0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                        0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+                        // IDSEL 0x1f IDE/SATA
+                        0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                        0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                        uli1575@0 {
+                                reg = <0x0 0x0 0x0 0x0 0x0>;
+                                #size-cells = <2>;
+                                #address-cells = <3>;
+                                ranges = <0x2000000 0x0 0xa0000000
+                                          0x2000000 0x0 0xa0000000
+                                          0x0 0x20000000
+                                          0x1000000 0x0 0x0
+                                          0x1000000 0x0 0x0
+                                          0x0 0x10000>;
+                                isa@1e {
+                                        device_type = "isa";
+                                        #interrupt-cells = <2>;
+                                        #size-cells = <1>;
+                                        #address-cells = <2>;
+                                        reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                        ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                                  0x1000>;
+                                        interrupt-parent = <&i8259>;
+                                        i8259: interrupt-controller@20 {
+                                                reg = <0x1 0x20 0x2
+                                                       0x1 0xa0 0x2
+                                                       0x1 0x4d0 0x2>;
+                                                interrupt-controller;
+                                                device_type = "interrupt-controller";
+                                                #address-cells = <0>;
+                                                #interrupt-cells = <2>;
+                                                compatible = "chrp,iic";
+                                                interrupts = <4 1>;
+                                                interrupt-parent = <&mpic>;
+                                        };
+                                        i8042@60 {
+                                                #size-cells = <0>;
+                                                #address-cells = <1>;
+                                                reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                                interrupts = <1 3 12 3>;
+                                                interrupt-parent =
+                                                        <&i8259>;
+                                                keyboard@0 {
+                                                        reg = <0x0>;
+                                                        compatible = "pnpPNP,303";
+                                                };
+                                                mouse@1 {
+                                                        reg = <0x1>;
+                                                        compatible = "pnpPNP,f03";
+                                                };
+                                        };
+                                        rtc@70 {
+                                                compatible = "pnpPNP,b00";
+                                                reg = <0x1 0x70 0x2>;
+                                        };
+                                        gpio@400 {
+                                                reg = <0x1 0x400 0x80>;
+                                        };
+                                };
+                        };
+                };
+        };
+        pci2: pcie@ffe0a000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0 0xffe0a000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <26 2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index a36dbbc48694..5fb6f6684b0e 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -278,7 +278,6 @@
        };
        pci0: pci@e0008500 {
-                cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index b1f1416ac998..9eefe00ed253 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -151,10 +151,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x00000000 0xe0000000 0x00100000>;
-                reg = <0xe0000000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
                compatible = "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -350,7 +362,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x01 (PCI-X slot) @66MHz */
@@ -380,7 +391,6 @@
        };
        pci2: pcie@e000a000 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index c4564b81e473..239d57a55cf4 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -57,9 +57,21 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xff700000 0x00100000>;
-                reg = <0xff700000 0x00100000>;
                clock-frequency = <0>;
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8560-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -296,7 +308,6 @@
        };
        pci0: pci@ff708000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
index e3e914e78caa..ee5538feb455 100644
--- a/arch/powerpc/boot/dts/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -126,9 +126,21 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x00000000 0xf8000000 0x00100000>;
-                reg = <0xf8000000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
+                mcm-law@0 {
+                        compatible = "fsl,mcm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                mcm@1000 {
+                        compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -371,7 +383,6 @@
        };
        pci0: pcie@f8008000 {
-                cell-index = <0>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
@@ -410,7 +421,6 @@
        };
        pci1: pcie@f8009000 {
-                cell-index = <1>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 43cc68bd3192..739dd0da2416 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -199,6 +199,28 @@
                                        };
                                };
+                                ndfc@3,0 {
+                                        compatible = "ibm,ndfc";
+                                        reg = <0x00000003 0x00000000 0x00002000>;
+                                        ccr = <0x00001000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+                                                partition@0 {
+                                                        label = "u-boot";
+                                                        reg = <0x00000000 0x00084000>;
+                                                };
+                                                partition@84000 {
+                                                        label = "user";
+                                                        reg = <0x00000000 0x01f7c000>;
+                                                };
+                                        };
+                                };
                        };
                        UART0: serial@ef600300 {
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index 7a6ae75a1e57..feb4ef6bd144 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -55,10 +55,22 @@
                device_type = "soc";
                ranges = <0x00000000 0xe0000000 0x00100000>;
-                reg = <0xe0000000 0x00001000>;  // CCSRBAR 1M
                bus-frequency = <0>;            // Filled in by U-Boot
                compatible = "fsl,mpc8544-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8544-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8544-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -314,7 +326,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index ea6b15152de3..b670d03fbcd9 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -52,10 +52,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0 0xfdf00000 0x100000>;
-                reg = <0xfdf00000 0x1000>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8560-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -251,7 +263,6 @@
        };
        pci0: pci@fdf08000 {
-                cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index b6f1fc6eb960..71347537b83e 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -54,10 +54,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8540-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8540-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -266,7 +278,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index fa6a3d54a8a5..b30f63753d41 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -53,10 +53,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8541-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8541-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -288,7 +300,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 00f7ed7a2455..61f25e15fd66 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -55,10 +55,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xa0000000 0x100000>;
-                reg = <0xa0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
                compatible = "fsl,mpc8548-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -419,7 +431,6 @@
        };
        pci0: pci@a0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
@@ -441,7 +452,6 @@
        };
        pci1: pcie@a000a000 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 (PEX) */
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 673e4a778ac8..025759c7c955 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -55,10 +55,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
                compatible = "fsl,mpc8548-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <10>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -419,7 +431,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
@@ -441,7 +452,6 @@
        };
        pci1: pcie@e000a000 {
-                cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 (PEX) */
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 6a99f1eef7ad..95e287381836 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -53,10 +53,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8555-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -288,7 +300,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index b6c2d71defd3..ff70580a8f4c 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -55,10 +55,22 @@
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-                reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8560-immr", "simple-bus";
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+                ecm@1000 {
+                        compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
@@ -359,7 +371,6 @@
        };
        pci0: pci@e0008000 {
-                cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts
new file mode 100644
index 000000000000..81a8dc2c6365
--- /dev/null
+++ b/arch/powerpc/boot/dts/virtex440-ml510.dts
@@ -0,0 +1,465 @@
+/*
+ * Xilinx ML510 Reference Design support
+ *
+ * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
+ * The reference design contains a bug which prevent PCI DMA from working
+ * properly.  A description of the bug is given in the plbv46_pci section. It
+ * needs to be fixed by the user until Xilinx updates their reference design.
+ *
+ * Copyright 2009, Roderick Colenbrander
+ */
+/dts-v1/;
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
+        dcr-parent = <&ppc440_0>;
+        DDR2_SDRAM_DIMM0: memory@0 {
+                device_type = "memory";
+                reg = < 0x0 0x20000000 >;
+        } ;
+        alias {
+                ethernet0 = &Hard_Ethernet_MAC;
+                serial0 = &RS232_Uart_1;
+        } ;
+        chosen {
+                bootargs = "console=ttyS0 root=/dev/ram";
+                linux,stdout-path = "/plb@0/serial@83e00000";
+        } ;
+        cpus {
+                #address-cells = <1>;
+                #cpus = <0x1>;
+                #size-cells = <0>;
+                ppc440_0: cpu@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clock-frequency = <300000000>;
+                        compatible = "PowerPC,440", "ibm,ppc440";
+                        d-cache-line-size = <0x20>;
+                        d-cache-size = <0x8000>;
+                        dcr-access-method = "native";
+                        dcr-controller ;
+                        device_type = "cpu";
+                        i-cache-line-size = <0x20>;
+                        i-cache-size = <0x8000>;
+                        model = "PowerPC,440";
+                        reg = <0>;
+                        timebase-frequency = <300000000>;
+                        xlnx,apu-control = <0x2000>;
+                        xlnx,apu-udi-0 = <0x0>;
+                        xlnx,apu-udi-1 = <0x0>;
+                        xlnx,apu-udi-10 = <0x0>;
+                        xlnx,apu-udi-11 = <0x0>;
+                        xlnx,apu-udi-12 = <0x0>;
+                        xlnx,apu-udi-13 = <0x0>;
+                        xlnx,apu-udi-14 = <0x0>;
+                        xlnx,apu-udi-15 = <0x0>;
+                        xlnx,apu-udi-2 = <0x0>;
+                        xlnx,apu-udi-3 = <0x0>;
+                        xlnx,apu-udi-4 = <0x0>;
+                        xlnx,apu-udi-5 = <0x0>;
+                        xlnx,apu-udi-6 = <0x0>;
+                        xlnx,apu-udi-7 = <0x0>;
+                        xlnx,apu-udi-8 = <0x0>;
+                        xlnx,apu-udi-9 = <0x0>;
+                        xlnx,dcr-autolock-enable = <0x1>;
+                        xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
+                        xlnx,dcu-rd-noncache-plb-prio = <0x0>;
+                        xlnx,dcu-rd-touch-plb-prio = <0x0>;
+                        xlnx,dcu-rd-urgent-plb-prio = <0x0>;
+                        xlnx,dcu-wr-flush-plb-prio = <0x0>;
+                        xlnx,dcu-wr-store-plb-prio = <0x0>;
+                        xlnx,dcu-wr-urgent-plb-prio = <0x0>;
+                        xlnx,dma0-control = <0x0>;
+                        xlnx,dma0-plb-prio = <0x0>;
+                        xlnx,dma0-rxchannelctrl = <0x1010000>;
+                        xlnx,dma0-rxirqtimer = <0x3ff>;
+                        xlnx,dma0-txchannelctrl = <0x1010000>;
+                        xlnx,dma0-txirqtimer = <0x3ff>;
+                        xlnx,dma1-control = <0x0>;
+                        xlnx,dma1-plb-prio = <0x0>;
+                        xlnx,dma1-rxchannelctrl = <0x1010000>;
+                        xlnx,dma1-rxirqtimer = <0x3ff>;
+                        xlnx,dma1-txchannelctrl = <0x1010000>;
+                        xlnx,dma1-txirqtimer = <0x3ff>;
+                        xlnx,dma2-control = <0x0>;
+                        xlnx,dma2-plb-prio = <0x0>;
+                        xlnx,dma2-rxchannelctrl = <0x1010000>;
+                        xlnx,dma2-rxirqtimer = <0x3ff>;
+                        xlnx,dma2-txchannelctrl = <0x1010000>;
+                        xlnx,dma2-txirqtimer = <0x3ff>;
+                        xlnx,dma3-control = <0x0>;
+                        xlnx,dma3-plb-prio = <0x0>;
+                        xlnx,dma3-rxchannelctrl = <0x1010000>;
+                        xlnx,dma3-rxirqtimer = <0x3ff>;
+                        xlnx,dma3-txchannelctrl = <0x1010000>;
+                        xlnx,dma3-txirqtimer = <0x3ff>;
+                        xlnx,endian-reset = <0x0>;
+                        xlnx,generate-plb-timespecs = <0x1>;
+                        xlnx,icu-rd-fetch-plb-prio = <0x0>;
+                        xlnx,icu-rd-spec-plb-prio = <0x0>;
+                        xlnx,icu-rd-touch-plb-prio = <0x0>;
+                        xlnx,interconnect-imask = <0xffffffff>;
+                        xlnx,mplb-allow-lock-xfer = <0x1>;
+                        xlnx,mplb-arb-mode = <0x0>;
+                        xlnx,mplb-awidth = <0x20>;
+                        xlnx,mplb-counter = <0x500>;
+                        xlnx,mplb-dwidth = <0x80>;
+                        xlnx,mplb-max-burst = <0x8>;
+                        xlnx,mplb-native-dwidth = <0x80>;
+                        xlnx,mplb-p2p = <0x0>;
+                        xlnx,mplb-prio-dcur = <0x2>;
+                        xlnx,mplb-prio-dcuw = <0x3>;
+                        xlnx,mplb-prio-icu = <0x4>;
+                        xlnx,mplb-prio-splb0 = <0x1>;
+                        xlnx,mplb-prio-splb1 = <0x0>;
+                        xlnx,mplb-read-pipe-enable = <0x1>;
+                        xlnx,mplb-sync-tattribute = <0x0>;
+                        xlnx,mplb-wdog-enable = <0x1>;
+                        xlnx,mplb-write-pipe-enable = <0x1>;
+                        xlnx,mplb-write-post-enable = <0x1>;
+                        xlnx,num-dma = <0x0>;
+                        xlnx,pir = <0xf>;
+                        xlnx,ppc440mc-addr-base = <0x0>;
+                        xlnx,ppc440mc-addr-high = <0x1fffffff>;
+                        xlnx,ppc440mc-arb-mode = <0x0>;
+                        xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
+                        xlnx,ppc440mc-control = <0xf810008f>;
+                        xlnx,ppc440mc-max-burst = <0x8>;
+                        xlnx,ppc440mc-prio-dcur = <0x2>;
+                        xlnx,ppc440mc-prio-dcuw = <0x3>;
+                        xlnx,ppc440mc-prio-icu = <0x4>;
+                        xlnx,ppc440mc-prio-splb0 = <0x1>;
+                        xlnx,ppc440mc-prio-splb1 = <0x0>;
+                        xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
+                        xlnx,ppcdm-asyncmode = <0x0>;
+                        xlnx,ppcds-asyncmode = <0x0>;
+                        xlnx,user-reset = <0x0>;
+                } ;
+        } ;
+        plb_v46_0: plb@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
+                ranges ;
+                FLASH: flash@fc000000 {
+                        bank-width = <2>;
+                        compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
+                        reg = < 0xfc000000 0x2000000 >;
+                        xlnx,family = "virtex5";
+                        xlnx,include-datawidth-matching-0 = <0x1>;
+                        xlnx,include-datawidth-matching-1 = <0x0>;
+                        xlnx,include-datawidth-matching-2 = <0x0>;
+                        xlnx,include-datawidth-matching-3 = <0x0>;
+                        xlnx,include-negedge-ioregs = <0x0>;
+                        xlnx,include-plb-ipif = <0x1>;
+                        xlnx,include-wrbuf = <0x1>;
+                        xlnx,max-mem-width = <0x10>;
+                        xlnx,mch-native-dwidth = <0x20>;
+                        xlnx,mch-plb-clk-period-ps = <0x2710>;
+                        xlnx,mch-splb-awidth = <0x20>;
+                        xlnx,mch0-accessbuf-depth = <0x10>;
+                        xlnx,mch0-protocol = <0x0>;
+                        xlnx,mch0-rddatabuf-depth = <0x10>;
+                        xlnx,mch1-accessbuf-depth = <0x10>;
+                        xlnx,mch1-protocol = <0x0>;
+                        xlnx,mch1-rddatabuf-depth = <0x10>;
+                        xlnx,mch2-accessbuf-depth = <0x10>;
+                        xlnx,mch2-protocol = <0x0>;
+                        xlnx,mch2-rddatabuf-depth = <0x10>;
+                        xlnx,mch3-accessbuf-depth = <0x10>;
+                        xlnx,mch3-protocol = <0x0>;
+                        xlnx,mch3-rddatabuf-depth = <0x10>;
+                        xlnx,mem0-width = <0x10>;
+                        xlnx,mem1-width = <0x20>;
+                        xlnx,mem2-width = <0x20>;
+                        xlnx,mem3-width = <0x20>;
+                        xlnx,num-banks-mem = <0x1>;
+                        xlnx,num-channels = <0x2>;
+                        xlnx,priority-mode = <0x0>;
+                        xlnx,synch-mem-0 = <0x0>;
+                        xlnx,synch-mem-1 = <0x0>;
+                        xlnx,synch-mem-2 = <0x0>;
+                        xlnx,synch-mem-3 = <0x0>;
+                        xlnx,synch-pipedelay-0 = <0x2>;
+                        xlnx,synch-pipedelay-1 = <0x2>;
+                        xlnx,synch-pipedelay-2 = <0x2>;
+                        xlnx,synch-pipedelay-3 = <0x2>;
+                        xlnx,tavdv-ps-mem-0 = <0x1adb0>;
+                        xlnx,tavdv-ps-mem-1 = <0x3a98>;
+                        xlnx,tavdv-ps-mem-2 = <0x3a98>;
+                        xlnx,tavdv-ps-mem-3 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-0 = <0x1adb0>;
+                        xlnx,tcedv-ps-mem-1 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-2 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-3 = <0x3a98>;
+                        xlnx,thzce-ps-mem-0 = <0x88b8>;
+                        xlnx,thzce-ps-mem-1 = <0x1b58>;
+                        xlnx,thzce-ps-mem-2 = <0x1b58>;
+                        xlnx,thzce-ps-mem-3 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-0 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-1 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-2 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-3 = <0x1b58>;
+                        xlnx,tlzwe-ps-mem-0 = <0x88b8>;
+                        xlnx,tlzwe-ps-mem-1 = <0x0>;
+                        xlnx,tlzwe-ps-mem-2 = <0x0>;
+                        xlnx,tlzwe-ps-mem-3 = <0x0>;
+                        xlnx,twc-ps-mem-0 = <0x1adb0>;
+                        xlnx,twc-ps-mem-1 = <0x3a98>;
+                        xlnx,twc-ps-mem-2 = <0x3a98>;
+                        xlnx,twc-ps-mem-3 = <0x3a98>;
+                        xlnx,twp-ps-mem-0 = <0x11170>;
+                        xlnx,twp-ps-mem-1 = <0x2ee0>;
+                        xlnx,twp-ps-mem-2 = <0x2ee0>;
+                        xlnx,twp-ps-mem-3 = <0x2ee0>;
+                        xlnx,xcl0-linesize = <0x4>;
+                        xlnx,xcl0-writexfer = <0x1>;
+                        xlnx,xcl1-linesize = <0x4>;
+                        xlnx,xcl1-writexfer = <0x1>;
+                        xlnx,xcl2-linesize = <0x4>;
+                        xlnx,xcl2-writexfer = <0x1>;
+                        xlnx,xcl3-linesize = <0x4>;
+                        xlnx,xcl3-writexfer = <0x1>;
+                } ;
+                Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "xlnx,compound";
+                        ethernet@81c00000 {
+                                compatible = "xlnx,xps-ll-temac-1.01.b";
+                                device_type = "network";
+                                interrupt-parent = <&xps_intc_0>;
+                                interrupts = < 8 2 >;
+                                llink-connected = <&Hard_Ethernet_MAC_fifo>;
+                                local-mac-address = [ 02 00 00 00 00 00 ];
+                                reg = < 0x81c00000 0x40 >;
+                                xlnx,bus2core-clk-ratio = <0x1>;
+                                xlnx,phy-type = <0x3>;
+                                xlnx,phyaddr = <0x1>;
+                                xlnx,rxcsum = <0x0>;
+                                xlnx,rxfifo = <0x8000>;
+                                xlnx,temac-type = <0x0>;
+                                xlnx,txcsum = <0x0>;
+                                xlnx,txfifo = <0x8000>;
+                        } ;
+                } ;
+                Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
+                        compatible = "xlnx,xps-ll-fifo-1.01.a";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 6 2 >;
+                        reg = < 0x81a00000 0x10000 >;
+                        xlnx,family = "virtex5";
+                } ;
+                IIC_EEPROM: i2c@81600000 {
+                        compatible = "xlnx,xps-iic-2.00.a";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 9 2 >;
+                        reg = < 0x81600000 0x10000 >;
+                        xlnx,clk-freq = <0x5f5e100>;
+                        xlnx,family = "virtex5";
+                        xlnx,gpo-width = <0x1>;
+                        xlnx,iic-freq = <0x186a0>;
+                        xlnx,scl-inertial-delay = <0x5>;
+                        xlnx,sda-inertial-delay = <0x5>;
+                        xlnx,ten-bit-adr = <0x0>;
+                } ;
+                LCD_OPTIONAL: gpio@81420000 {
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        reg = < 0x81420000 0x10000 >;
+                        xlnx,all-inputs = <0x0>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,dout-default = <0x0>;
+                        xlnx,dout-default-2 = <0x0>;
+                        xlnx,family = "virtex5";
+                        xlnx,gpio-width = <0xb>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-bidir = <0x1>;
+                        xlnx,is-bidir-2 = <0x1>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xffffffff>;
+                        xlnx,tri-default-2 = <0xffffffff>;
+                } ;
+                LEDs_4Bit: gpio@81400000 {
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        reg = < 0x81400000 0x10000 >;
+                        xlnx,all-inputs = <0x0>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,dout-default = <0x0>;
+                        xlnx,dout-default-2 = <0x0>;
+                        xlnx,family = "virtex5";
+                        xlnx,gpio-width = <0x4>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-bidir = <0x1>;
+                        xlnx,is-bidir-2 = <0x1>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xffffffff>;
+                        xlnx,tri-default-2 = <0xffffffff>;
+                } ;
+                RS232_Uart_1: serial@83e00000 {
+                        clock-frequency = <100000000>;
+                        compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
+                        current-speed = <9600>;
+                        device_type = "serial";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 11 2 >;
+                        reg = < 0x83e00000 0x10000 >;
+                        reg-offset = <0x1003>;
+                        reg-shift = <2>;
+                        xlnx,family = "virtex5";
+                        xlnx,has-external-rclk = <0x0>;
+                        xlnx,has-external-xin = <0x0>;
+                        xlnx,is-a-16550 = <0x1>;
+                } ;
+                SPI_EEPROM: xps-spi@feff8000 {
+                        compatible = "xlnx,xps-spi-2.00.b";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 10 2 >;
+                        reg = < 0xfeff8000 0x80 >;
+                        xlnx,family = "virtex5";
+                        xlnx,fifo-exist = <0x1>;
+                        xlnx,num-ss-bits = <0x1>;
+                        xlnx,num-transfer-bits = <0x8>;
+                        xlnx,sck-ratio = <0x80>;
+                } ;
+                SysACE_CompactFlash: sysace@83600000 {
+                        compatible = "xlnx,xps-sysace-1.00.a";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 7 2 >;
+                        reg = < 0x83600000 0x10000 >;
+                        xlnx,family = "virtex5";
+                        xlnx,mem-width = <0x10>;
+                } ;
+                plbv46_pci_0: plbv46-pci@85e00000 {
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "xlnx,plbv46-pci-1.03.a";
+                        device_type = "pci";
+                        reg = < 0x85e00000 0x10000 >;
+                        /*
+                         * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
+                         * 0 which means that a read/write to the memory mapped
+                         * i/o region (which starts at 0xa0000000) for pci
+                         * bar 0 on the plb side translates to 0.
+                         * It is important to set this value to 0xa0000000, so
+                         * that inbound and outbound pci transactions work
+                         * properly including DMA.
+                         */
+                        ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
+                                  0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                /* IRQ mapping for pci slots and ALI M1533
+                                 * periperhals. In total there are 5 interrupt
+                                 * lines connected to a xps_intc controller.
+                                 * Four of them are PCI IRQ A, B, C, D and
+                                 * which correspond to respectively xpx_intc
+                                 * 5, 4, 3 and 2.  The fifth interrupt line is
+                                 * connected to the south bridge and this one
+                                 * uses irq 1 and is active high instead of
+                                 * active low.
+                                 *
+                                 * The M1533 contains various peripherals
+                                 * including AC97 audio, a modem, USB, IDE and
+                                 * some power management stuff. The modem
+                                 * isn't connected on the ML510 and the power
+                                 * management core also isn't used.
+                                 */
+                                /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
+                                0x3000 0 0 1 &xps_intc_0 3 2
+                                0x3000 0 0 2 &xps_intc_0 2 2
+                                0x3000 0 0 3 &xps_intc_0 5 2
+                                0x3000 0 0 4 &xps_intc_0 4 2
+                                /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
+                                /*
+                                0x11800 0 0 1 &xps_intc_0 5 0 2
+                                0x11800 0 0 2 &xps_intc_0 4 0 2
+                                0x11800 0 0 3 &xps_intc_0 3 0 2
+                                0x11800 0 0 4 &xps_intc_0 2 0 2
+                                */
+                                /* According to the datasheet + schematic
+                                 * ABCD [FPGA] of slot 5 is mapped to DABC.
+                                 * Testing showed that at least A maps to B,
+                                 * the mapping of the other pins is a guess
+                                 * and for that reason the lines have been
+                                 * commented out.
+                                 */
+                                /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
+                                0x2800 0 0 1 &xps_intc_0 4 2
+                                /*
+                                0x2800 0 0 2 &xps_intc_0 3 2
+                                0x2800 0 0 3 &xps_intc_0 2 2
+                                0x2800 0 0 4 &xps_intc_0 5 2
+                                */
+                                /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
+                                /*
+                                0x11000 0 0 1 &xps_intc_0 4 0 2
+                                0x11000 0 0 2 &xps_intc_0 3 0 2
+                                0x11000 0 0 3 &xps_intc_0 2 0 2
+                                0x11000 0 0 4 &xps_intc_0 5 0 2
+                                */
+                                /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
+                                0x0800 0 0 1 &i8259 7 2
+                                /* IDSEL 0x1b / dev=11, bus=0 / IDE */
+                                0x5800 0 0 1 &i8259 14 2
+                                /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
+                                0x7800 0 0 1 &i8259 7 2
+                        >;
+                        ali_m1533 {
+                                #size-cells = <1>;
+                                #address-cells = <2>;
+                                i8259: interrupt-controller@20 {
+                                        reg = <1 0x20 2
+                                                        1 0xa0 2
+                                                        1 0x4d0 2>;
+                                        interrupt-controller;
+                                        device_type = "interrupt-controller";
+                                        #address-cells = <0>;
+                                        #interrupt-cells = <2>;
+                                        compatible = "chrp,iic";
+                                        /* south bridge irq is active high */
+                                        interrupts = <1 3>;
+                                        interrupt-parent = <&xps_intc_0>;
+                                };
+                        };
+                } ;
+                xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
+                        compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
+                        reg = < 0xffff0000 0x10000 >;
+                        xlnx,family = "virtex5";
+                } ;
+                xps_intc_0: interrupt-controller@81800000 {
+                        #interrupt-cells = <0x2>;
+                        compatible = "xlnx,xps-intc-1.00.a";
+                        interrupt-controller ;
+                        reg = < 0x81800000 0x10000 >;
+                        xlnx,num-intr-inputs = <0xc>;
+                } ;
+                xps_tft_0: tft@86e00000 {
+                        compatible = "xlnx,xps-tft-1.00.a";
+                        reg = < 0x86e00000 0x10000 >;
+                        xlnx,dcr-splb-slave-if = <0x1>;
+                        xlnx,default-tft-base-addr = <0x0>;
+                        xlnx,family = "virtex5";
+                        xlnx,i2c-slave-addr = <0x76>;
+                        xlnx,mplb-awidth = <0x20>;
+                        xlnx,mplb-dwidth = <0x80>;
+                        xlnx,mplb-native-dwidth = <0x40>;
+                        xlnx,mplb-smallest-slave = <0x20>;
+                        xlnx,tft-interface = <0x1>;
+                } ;
+        } ;
+}  ;
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index 7e183ff9a317..01bfb56bbe80 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -1,7 +1,7 @@
 /*
 * Device Tree Source for PIKA Warp
 *
- * Copyright (c) 2008 PIKA Technologies
+ * Copyright (c) 2008-2009 PIKA Technologies
 *   Sean MacLennan <smaclennan@pikatech.com>
 *
 * This file is licensed under the terms of the GNU General Public
@@ -158,7 +158,7 @@
                                        partition@0 {
                                                label = "splash";
-                                                reg = <0x00000000 0x00020000>;
+                                                reg = <0x00000000 0x00010000>;
                                        };
                                        partition@300000 {
                                                label = "fpga";
@@ -244,28 +244,27 @@
                        };
                        GPIO0: gpio@ef600b00 {
-                                compatible = "ibm,gpio-440ep";
+                                compatible = "ibm,ppc4xx-gpio";
                                reg = <0xef600b00 0x00000048>;
                                #gpio-cells = <2>;
                                gpio-controller;
                        };
                        GPIO1: gpio@ef600c00 {
-                                compatible = "ibm,gpio-440ep";
+                                compatible = "ibm,ppc4xx-gpio";
                                reg = <0xef600c00 0x00000048>;
                                #gpio-cells = <2>;
                                gpio-controller;
+                        };
-                                led@31 {
+                        power-leds {
-                                        compatible = "linux,gpio-led";
+                                compatible = "gpio-leds";
-                                        linux,name = ":green:";
+                                green {
-                                        gpios = <&GPIO1 31 0>;
+                                        gpios = <&GPIO1 0 0>;
-                                };              
+                                        default-state = "on";
-        
+                                };
-                                led@30 {        
+                                red {
-                                        compatible = "linux,gpio-led";
+                                        gpios = <&GPIO1 1 0>;
-                                        linux,name = ":red:";
-                                        gpios = <&GPIO1 30 0>;
                                };
                        };
diff --git a/arch/powerpc/boot/install.sh b/arch/powerpc/boot/install.sh
index 51b2387bdba0..98312d169c85 100644
--- a/arch/powerpc/boot/install.sh
+++ b/arch/powerpc/boot/install.sh
@@ -18,6 +18,9 @@
 #   $5 and more - kernel boot files; zImage*, uImage, cuImage.*, etc.
 #
+# Bail with error code if anything goes wrong
+set -e
 # User may have a custom install script
 if [ -x ~/bin/${CROSS_COMPILE}installkernel ]; then exec ~/bin/${CROSS_COMPILE}installkernel "$@"; fi
diff --git a/arch/powerpc/configs/40x/acadia_defconfig b/arch/powerpc/configs/40x/acadia_defconfig
index a32ec8d323a0..173a5bb77ca1 100644
--- a/arch/powerpc/configs/40x/acadia_defconfig
+++ b/arch/powerpc/configs/40x/acadia_defconfig
@@ -252,7 +252,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/40x/ep405_defconfig b/arch/powerpc/configs/40x/ep405_defconfig
index 4e9d85f39da0..e9b8495cde0c 100644
--- a/arch/powerpc/configs/40x/ep405_defconfig
+++ b/arch/powerpc/configs/40x/ep405_defconfig
@@ -254,7 +254,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig
index 9917a09bad3a..865725effe93 100644
--- a/arch/powerpc/configs/40x/kilauea_defconfig
+++ b/arch/powerpc/configs/40x/kilauea_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc2
+# Linux kernel version: 2.6.30-rc7
-# Tue Jan 20 08:17:52 2009
+# Wed Jun  3 10:18:16 2009
 #
 # CONFIG_PPC64 is not set
@@ -27,6 +27,7 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -49,10 +50,12 @@ CONFIG_PPC_UDBG_16550=y
 # CONFIG_GENERIC_TBSYNC is not set
 CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
 # CONFIG_DEFAULT_UIMAGE is not set
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_DCR_MMIO is not set
 CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
@@ -67,9 +70,19 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_GROUP_SCHED=y
@@ -84,22 +97,24 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_STRIP_GENERATED=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -109,10 +124,12 @@ CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
@@ -120,6 +137,7 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -132,7 +150,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
 CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -148,11 +165,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_FREEZER is not set
 CONFIG_PPC4xx_PCI_EXPRESS=y
@@ -170,7 +182,7 @@ CONFIG_KILAUEA=y
 # CONFIG_MAKALU is not set
 # CONFIG_WALNUT is not set
 # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set
-# CONFIG_PPC40x_SIMPLE is not set
+CONFIG_PPC40x_SIMPLE=y
 CONFIG_405EX=y
 # CONFIG_IPIC is not set
 # CONFIG_MPIC is not set
@@ -228,9 +240,12 @@ CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
@@ -252,9 +267,10 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HAS_RAPIDIO is not set
@@ -272,14 +288,12 @@ CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_TASK_SIZE=0xc0000000
-CONFIG_CONSISTENT_START=0xff100000
 CONFIG_CONSISTENT_SIZE=0x00200000
 CONFIG_NET=y
 #
 # Networking options
 #
-CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -329,6 +343,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
@@ -341,7 +356,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
@@ -445,7 +459,6 @@ CONFIG_MTD_PHYSMAP_OF=y
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_QINFO_PROBE is not set
 #
 # UBI - Unsorted block images
@@ -498,6 +511,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_I2O is not set
 # CONFIG_MACINTOSH_DRIVERS is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -512,6 +526,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 CONFIG_IBM_NEW_EMAC=y
@@ -540,7 +556,6 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -678,6 +693,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_EDAC is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
@@ -706,6 +722,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -749,6 +770,7 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -760,7 +782,6 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -776,6 +797,7 @@ CONFIG_SUNRPC=y
 CONFIG_MSDOS_PARTITION=y
 # CONFIG_NLS is not set
 # CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
@@ -790,11 +812,12 @@ CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
 #
 # Kernel hacking
@@ -812,6 +835,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -841,9 +867,12 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
 #
 # Tracers
@@ -851,17 +880,21 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
 # CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PPC_EMULATED_STATS is not set
 # CONFIG_CODE_PATCHING_SELFTEST is not set
 # CONFIG_FTR_FIXUP_SELFTEST is not set
 # CONFIG_MSI_BITMAP_SELFTEST is not set
@@ -892,10 +925,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_TEST is not set
@@ -964,6 +999,7 @@ CONFIG_CRYPTO_DES=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
@@ -972,5 +1008,6 @@ CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_PPC4XX is not set
 # CONFIG_PPC_CLOCK is not set
 # CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/40x/makalu_defconfig b/arch/powerpc/configs/40x/makalu_defconfig
index 58bf2ac2e0dd..146747547873 100644
--- a/arch/powerpc/configs/40x/makalu_defconfig
+++ b/arch/powerpc/configs/40x/makalu_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc2
+# Linux kernel version: 2.6.30-rc7
-# Tue Jan 20 08:17:53 2009
+# Wed Jun  3 09:11:02 2009
 #
 # CONFIG_PPC64 is not set
@@ -27,6 +27,7 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -49,10 +50,12 @@ CONFIG_PPC_UDBG_16550=y
 # CONFIG_GENERIC_TBSYNC is not set
 CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
 # CONFIG_DEFAULT_UIMAGE is not set
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_DCR_MMIO is not set
 CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
@@ -67,9 +70,19 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_GROUP_SCHED=y
@@ -84,22 +97,24 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_STRIP_GENERATED=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -109,10 +124,12 @@ CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
@@ -120,6 +137,7 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -132,7 +150,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
 CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -148,11 +165,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_FREEZER is not set
 CONFIG_PPC4xx_PCI_EXPRESS=y
@@ -170,7 +182,7 @@ CONFIG_PPC4xx_PCI_EXPRESS=y
 CONFIG_MAKALU=y
 # CONFIG_WALNUT is not set
 # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set
-# CONFIG_PPC40x_SIMPLE is not set
+CONFIG_PPC40x_SIMPLE=y
 CONFIG_405EX=y
 # CONFIG_IPIC is not set
 # CONFIG_MPIC is not set
@@ -228,9 +240,12 @@ CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
@@ -252,9 +267,10 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HAS_RAPIDIO is not set
@@ -272,14 +288,12 @@ CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_TASK_SIZE=0xc0000000
-CONFIG_CONSISTENT_START=0xff100000
 CONFIG_CONSISTENT_SIZE=0x00200000
 CONFIG_NET=y
 #
 # Networking options
 #
-CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -329,6 +343,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
@@ -341,7 +356,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
@@ -445,7 +459,6 @@ CONFIG_MTD_PHYSMAP_OF=y
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_QINFO_PROBE is not set
 #
 # UBI - Unsorted block images
@@ -498,6 +511,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_I2O is not set
 # CONFIG_MACINTOSH_DRIVERS is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -512,6 +526,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 CONFIG_IBM_NEW_EMAC=y
@@ -540,7 +556,6 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -678,6 +693,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_EDAC is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
@@ -706,6 +722,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -749,6 +770,7 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -760,7 +782,6 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -776,6 +797,7 @@ CONFIG_SUNRPC=y
 CONFIG_MSDOS_PARTITION=y
 # CONFIG_NLS is not set
 # CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
@@ -790,11 +812,12 @@ CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
 #
 # Kernel hacking
@@ -812,6 +835,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -841,9 +867,12 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
 #
 # Tracers
@@ -851,17 +880,21 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
 # CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PPC_EMULATED_STATS is not set
 # CONFIG_CODE_PATCHING_SELFTEST is not set
 # CONFIG_FTR_FIXUP_SELFTEST is not set
 # CONFIG_MSI_BITMAP_SELFTEST is not set
@@ -892,10 +925,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_TEST is not set
@@ -964,6 +999,7 @@ CONFIG_CRYPTO_DES=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
@@ -972,5 +1008,6 @@ CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_PPC4XX is not set
 # CONFIG_PPC_CLOCK is not set
 # CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig
index f5698f962e58..416e79ac0711 100644
--- a/arch/powerpc/configs/40x/virtex_defconfig
+++ b/arch/powerpc/configs/40x/virtex_defconfig
@@ -258,7 +258,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/arches_defconfig b/arch/powerpc/configs/44x/arches_defconfig
index 1d72b0ac3f25..f7fd32c09424 100644
--- a/arch/powerpc/configs/44x/arches_defconfig
+++ b/arch/powerpc/configs/44x/arches_defconfig
@@ -258,7 +258,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/bamboo_defconfig b/arch/powerpc/configs/44x/bamboo_defconfig
index 959bdc43a491..e57f1e4c1795 100644
--- a/arch/powerpc/configs/44x/bamboo_defconfig
+++ b/arch/powerpc/configs/44x/bamboo_defconfig
@@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig
index f9a08ee49b96..5e85412eb9fa 100644
--- a/arch/powerpc/configs/44x/canyonlands_defconfig
+++ b/arch/powerpc/configs/44x/canyonlands_defconfig
@@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
@@ -716,7 +716,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multimedia drivers
 #
-CONFIG_DAB=y
+# CONFIG_DAB is not set
 # CONFIG_USB_DABUSB is not set
 #
@@ -725,7 +725,7 @@ CONFIG_DAB=y
 # CONFIG_AGP is not set
 # CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
diff --git a/arch/powerpc/configs/44x/ebony_defconfig b/arch/powerpc/configs/44x/ebony_defconfig
index be64aa644d15..b652f7dcab5a 100644
--- a/arch/powerpc/configs/44x/ebony_defconfig
+++ b/arch/powerpc/configs/44x/ebony_defconfig
@@ -261,7 +261,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig
index f67250b24ec5..c23a4ef13e45 100644
--- a/arch/powerpc/configs/44x/katmai_defconfig
+++ b/arch/powerpc/configs/44x/katmai_defconfig
@@ -256,7 +256,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/rainier_defconfig b/arch/powerpc/configs/44x/rainier_defconfig
index 9348c12bd7a6..b25fad1343dc 100644
--- a/arch/powerpc/configs/44x/rainier_defconfig
+++ b/arch/powerpc/configs/44x/rainier_defconfig
@@ -260,7 +260,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/redwood_defconfig b/arch/powerpc/configs/44x/redwood_defconfig
index e665433762ba..ed31d4f17b5a 100644
--- a/arch/powerpc/configs/44x/redwood_defconfig
+++ b/arch/powerpc/configs/44x/redwood_defconfig
@@ -265,7 +265,7 @@ CONFIG_PCIEAER=y
 # CONFIG_PCIEASPM is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/sam440ep_defconfig b/arch/powerpc/configs/44x/sam440ep_defconfig
index 70d5c3fa3283..e14e89a5e06b 100644
--- a/arch/powerpc/configs/44x/sam440ep_defconfig
+++ b/arch/powerpc/configs/44x/sam440ep_defconfig
@@ -262,7 +262,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
diff --git a/arch/powerpc/configs/44x/sequoia_defconfig b/arch/powerpc/configs/44x/sequoia_defconfig
index a921fe3c3711..6400aae04dda 100644
--- a/arch/powerpc/configs/44x/sequoia_defconfig
+++ b/arch/powerpc/configs/44x/sequoia_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc2
+# Linux kernel version: 2.6.29
-# Tue Jan 20 08:22:45 2009
+# Tue Apr  7 17:04:52 2009
 #
 # CONFIG_PPC64 is not set
@@ -57,6 +57,7 @@ CONFIG_GENERIC_BUG=y
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_DCR_MMIO is not set
 CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
@@ -74,6 +75,15 @@ CONFIG_POSIX_MQUEUE=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_GROUP_SCHED=y
@@ -88,8 +98,12 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
@@ -99,10 +113,8 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -112,10 +124,12 @@ CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
@@ -123,6 +137,7 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -135,7 +150,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
 CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -151,11 +165,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_FREEZER is not set
 # CONFIG_PPC4xx_PCI_EXPRESS is not set
@@ -176,6 +185,7 @@ CONFIG_SEQUOIA=y
 # CONFIG_ARCHES is not set
 # CONFIG_CANYONLANDS is not set
 # CONFIG_GLACIER is not set
+# CONFIG_REDWOOD is not set
 # CONFIG_YOSEMITE is not set
 # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
 CONFIG_PPC44x_SIMPLE=y
@@ -238,9 +248,13 @@ CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_STDBINUTILS=y
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 CONFIG_CMDLINE_BOOL=y
@@ -262,9 +276,10 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HAS_RAPIDIO is not set
@@ -278,18 +293,16 @@ CONFIG_PCI_LEGACY=y
 # Default settings for advanced configuration options are used
 #
 CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_LOWMEM_CAM_NUM=3
 CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_TASK_SIZE=0xc0000000
-CONFIG_CONSISTENT_START=0xff100000
-CONFIG_CONSISTENT_SIZE=0x00200000
 CONFIG_NET=y
 #
 # Networking options
 #
-CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -339,6 +352,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
@@ -351,7 +365,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
@@ -448,14 +461,23 @@ CONFIG_MTD_PHYSMAP_OF=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_NDFC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
 # CONFIG_MTD_ONENAND is not set
 #
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_QINFO_PROBE is not set
 #
 # UBI - Unsorted block images
@@ -483,12 +505,16 @@ CONFIG_BLK_DEV_RAM_SIZE=35000
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_SGI_IOC4 is not set
 # CONFIG_TIFM_CORE is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
 # CONFIG_HP_ILO is not set
 # CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -515,6 +541,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_I2O is not set
 # CONFIG_MACINTOSH_DRIVERS is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -529,6 +556,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 CONFIG_IBM_NEW_EMAC=y
@@ -568,6 +597,7 @@ CONFIG_NETDEV_1000=y
 # CONFIG_QLA3XXX is not set
 # CONFIG_ATL1 is not set
 # CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
 # CONFIG_JME is not set
 CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
@@ -577,6 +607,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
 # CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
 # CONFIG_MYRI10GE is not set
 # CONFIG_NETXEN_NIC is not set
 # CONFIG_NIU is not set
@@ -586,6 +617,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
+# CONFIG_BE2NET is not set
 # CONFIG_TR is not set
 #
@@ -593,7 +625,6 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -734,7 +765,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 #
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 # CONFIG_USB_GADGET is not set
@@ -750,6 +781,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 # CONFIG_EDAC is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
@@ -778,6 +810,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -842,7 +879,6 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -858,6 +894,7 @@ CONFIG_SUNRPC=y
 CONFIG_MSDOS_PARTITION=y
 # CONFIG_NLS is not set
 # CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
@@ -873,11 +910,12 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
 #
 # Kernel hacking
@@ -924,9 +962,12 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
 #
 # Tracers
@@ -934,17 +975,20 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
 # CONFIG_TRACE_BRANCH_PROFILING is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
 # CONFIG_CODE_PATCHING_SELFTEST is not set
 # CONFIG_FTR_FIXUP_SELFTEST is not set
 # CONFIG_MSI_BITMAP_SELFTEST is not set
@@ -952,20 +996,7 @@ CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_IRQSTACKS is not set
 # CONFIG_VIRQ_DEBUG is not set
 # CONFIG_BDI_SWITCH is not set
-CONFIG_PPC_EARLY_DEBUG=y
+# CONFIG_PPC_EARLY_DEBUG is not set
-# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
-# CONFIG_PPC_EARLY_DEBUG_G5 is not set
-# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set
-# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set
-# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
-# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
-# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set
-# CONFIG_PPC_EARLY_DEBUG_BEAT is not set
-CONFIG_PPC_EARLY_DEBUG_44x=y
-# CONFIG_PPC_EARLY_DEBUG_40x is not set
-# CONFIG_PPC_EARLY_DEBUG_CPM is not set
-CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0xef600300
-CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x1
 #
 # Security options
@@ -988,10 +1019,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_TEST is not set
@@ -1060,6 +1093,7 @@ CONFIG_CRYPTO_DES=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
 #
@@ -1068,5 +1102,6 @@ CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_PPC4XX is not set
 # CONFIG_PPC_CLOCK is not set
 # CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/44x/taishan_defconfig b/arch/powerpc/configs/44x/taishan_defconfig
index 826700872d26..ef32cc4f82eb 100644
--- a/arch/powerpc/configs/44x/taishan_defconfig
+++ b/arch/powerpc/configs/44x/taishan_defconfig
@@ -260,7 +260,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig
index 1bf0a63614b1..2518b8568c70 100644
--- a/arch/powerpc/configs/44x/virtex5_defconfig
+++ b/arch/powerpc/configs/44x/virtex5_defconfig
@@ -263,7 +263,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index 7d044dfd9236..12dc7c409616 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -1808,7 +1808,7 @@ CONFIG_PCF8575=m
 CONFIG_SENSORS_PCA9539=m
 CONFIG_SENSORS_PCF8591=m
 # CONFIG_TPS65010 is not set
-CONFIG_SENSORS_MAX6875=m
+CONFIG_EEPROM_MAX6875=m
 CONFIG_SENSORS_TSL2550=m
 CONFIG_MCU_MPC8349EMITX=m
 # CONFIG_I2C_DEBUG_CORE is not set
diff --git a/arch/powerpc/include/asm/8253pit.h b/arch/powerpc/include/asm/8253pit.h
index b70d6e53b303..a71c9c1455a7 100644
--- a/arch/powerpc/include/asm/8253pit.h
+++ b/arch/powerpc/include/asm/8253pit.h
@@ -1,10 +1,3 @@
-#ifndef _ASM_POWERPC_8253PIT_H
-#define _ASM_POWERPC_8253PIT_H
 /*
 * 8253/8254 Programmable Interval Timer
 */
-#define PIT_TICK_RATE   1193182UL
-#endif  /* _ASM_POWERPC_8253PIT_H */
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index b7d2d07b6f96..4012483b1899 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -470,6 +470,9 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+#else  /* __powerpc64__ */
+#include <asm-generic/atomic64.h>
 #endif /* __powerpc64__ */
 #include <asm-generic/atomic-long.h>
diff --git a/arch/powerpc/include/asm/cpm2.h b/arch/powerpc/include/asm/cpm2.h
index 0f5e8ff59a85..990ff191da8b 100644
--- a/arch/powerpc/include/asm/cpm2.h
+++ b/arch/powerpc/include/asm/cpm2.h
@@ -14,10 +14,6 @@
 #include <asm/cpm.h>
 #include <sysdev/fsl_soc.h>
-#ifdef CONFIG_PPC_85xx
-#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
-#endif
 /* CPM Command register.
 */
 #define CPM_CR_RST      ((uint)0x80000000)
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index cb448d68452c..3d9e887c3c0c 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -15,9 +15,18 @@
 #include <linux/scatterlist.h>
 #include <linux/dma-attrs.h>
 #include <asm/io.h>
+#include <asm/swiotlb.h>
 #define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
+/* Some dma direct funcs must be visible for use in other dma_ops */
+extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t flag);
+extern void dma_direct_free_coherent(struct device *dev, size_t size,
+                                     void *vaddr, dma_addr_t dma_handle);
+extern unsigned long get_dma_direct_offset(struct device *dev);
 #ifdef CONFIG_NOT_COHERENT_CACHE
 /*
 * DMA-consistent mapping functions for PowerPCs that don't support
@@ -78,6 +87,8 @@ struct dma_mapping_ops {
                                dma_addr_t dma_address, size_t size,
                                enum dma_data_direction direction,
                                struct dma_attrs *attrs);
+        int             (*addr_needs_map)(struct device *dev, dma_addr_t addr,
+                                size_t size);
 #ifdef CONFIG_PPC_NEED_DMA_SYNC_OPS
        void            (*sync_single_range_for_cpu)(struct device *hwdev,
                                dma_addr_t dma_handle, unsigned long offset,
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index d6b4a12cdeff..014a624f4c8e 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -256,11 +256,11 @@ do {								\
 * even if we have an executable stack.
 */
 # define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
-                (exec_stk != EXSTACK_DISABLE_X) : 0)
+                (exec_stk == EXSTACK_DEFAULT) : 0)
 #else 
 # define SET_PERSONALITY(ex) \
  set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
-# define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X)
+# define elf_read_implies_exec(ex, exec_stk) (exec_stk == EXSTACK_DEFAULT)
 #endif /* __powerpc64__ */
 extern int dcache_bsize;
diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h
new file mode 100644
index 000000000000..9154e8526732
--- /dev/null
+++ b/arch/powerpc/include/asm/emulated_ops.h
@@ -0,0 +1,73 @@
+/*
+ *  Copyright 2007 Sony Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.
+ *  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _ASM_POWERPC_EMULATED_OPS_H
+#define _ASM_POWERPC_EMULATED_OPS_H
+#include <asm/atomic.h>
+#ifdef CONFIG_PPC_EMULATED_STATS
+struct ppc_emulated_entry {
+        const char *name;
+        atomic_t val;
+};
+extern struct ppc_emulated {
+#ifdef CONFIG_ALTIVEC
+        struct ppc_emulated_entry altivec;
+#endif
+        struct ppc_emulated_entry dcba;
+        struct ppc_emulated_entry dcbz;
+        struct ppc_emulated_entry fp_pair;
+        struct ppc_emulated_entry isel;
+        struct ppc_emulated_entry mcrxr;
+        struct ppc_emulated_entry mfpvr;
+        struct ppc_emulated_entry multiple;
+        struct ppc_emulated_entry popcntb;
+        struct ppc_emulated_entry spe;
+        struct ppc_emulated_entry string;
+        struct ppc_emulated_entry unaligned;
+#ifdef CONFIG_MATH_EMULATION
+        struct ppc_emulated_entry math;
+#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
+        struct ppc_emulated_entry 8xx;
+#endif
+#ifdef CONFIG_VSX
+        struct ppc_emulated_entry vsx;
+#endif
+} ppc_emulated;
+extern u32 ppc_warn_emulated;
+extern void ppc_warn_emulated_print(const char *type);
+#define PPC_WARN_EMULATED(type)                                          \
+        do {                                                             \
+                atomic_inc(&ppc_emulated.type.val);                      \
+                if (ppc_warn_emulated)                                   \
+                        ppc_warn_emulated_print(ppc_emulated.type.name); \
+        } while (0)
+#else /* !CONFIG_PPC_EMULATED_STATS */
+#define PPC_WARN_EMULATED(type) do { } while (0)
+#endif /* !CONFIG_PPC_EMULATED_STATS */
+#endif /* _ASM_POWERPC_EMULATED_OPS_H */
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
index e4094a5cb05b..cbd4dfa4bce2 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -8,8 +8,6 @@
 * 2 of the License, or (at your option) any later version.
 */
-#ifdef __ASSEMBLY__
 /*
 * Feature section common macros
 *
@@ -23,10 +21,12 @@
 /* 64 bits kernel, 32 bits code (ie. vdso32) */
 #define FTR_ENTRY_LONG          .llong
 #define FTR_ENTRY_OFFSET        .long 0xffffffff; .long
+#elif defined(CONFIG_PPC64)
+#define FTR_ENTRY_LONG          .llong
+#define FTR_ENTRY_OFFSET        .llong
 #else
-/* 64 bit kernel 64 bit code, or 32 bit kernel 32 bit code */
+#define FTR_ENTRY_LONG          .long
-#define FTR_ENTRY_LONG          PPC_LONG
+#define FTR_ENTRY_OFFSET        .long
-#define FTR_ENTRY_OFFSET        PPC_LONG
 #endif
 #define START_FTR_SECTION(label)        label##1:
@@ -141,6 +141,21 @@ label##5:					       	\
 #define ALT_FW_FTR_SECTION_END_IFCLR(msk)       \
        ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
+#ifndef __ASSEMBLY__
+#define ASM_MMU_FTR_IF(section_if, section_else, msk, val)      \
+        stringify_in_c(BEGIN_MMU_FTR_SECTION)                   \
+        section_if "; "                                         \
+        stringify_in_c(MMU_FTR_SECTION_ELSE)                    \
+        section_else "; "                                       \
+        stringify_in_c(ALT_MMU_FTR_SECTION_END((msk), (val)))
+#define ASM_MMU_FTR_IFSET(section_if, section_else, msk)        \
+        ASM_MMU_FTR_IF(section_if, section_else, (msk), (msk))
+#define ASM_MMU_FTR_IFCLR(section_if, section_else, msk)        \
+        ASM_MMU_FTR_IF(section_if, section_else, (msk), 0)
 #endif /* __ASSEMBLY__ */
 /* LWSYNC feature sections */
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 53512374e1c9..b7f8f4a87cc0 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -80,7 +80,7 @@ static inline void local_irq_disable(void)
        __asm__ __volatile__("wrteei 0": : :"memory");
 #else
        unsigned long msr;
-        __asm__ __volatile__("": : :"memory");
        msr = mfmsr();
        SET_MSR_EE(msr & ~MSR_EE);
 #endif
@@ -92,7 +92,7 @@ static inline void local_irq_enable(void)
        __asm__ __volatile__("wrteei 1": : :"memory");
 #else
        unsigned long msr;
-        __asm__ __volatile__("": : :"memory");
        msr = mfmsr();
        SET_MSR_EE(msr | MSR_EE);
 #endif
@@ -108,7 +108,6 @@ static inline void local_irq_save_ptr(unsigned long *flags)
 #else
        SET_MSR_EE(msr & ~MSR_EE);
 #endif
-        __asm__ __volatile__("": : :"memory");
 }
 #define local_save_flags(flags) ((flags) = mfmsr())
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 7464c0daddd1..7ead7c16fb7c 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -35,6 +35,16 @@
 #define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
 #define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
+/* Cell page table entries */
+#define CBE_IOPTE_PP_W          0x8000000000000000ul /* protection: write */
+#define CBE_IOPTE_PP_R          0x4000000000000000ul /* protection: read */
+#define CBE_IOPTE_M             0x2000000000000000ul /* coherency required */
+#define CBE_IOPTE_SO_R          0x1000000000000000ul /* ordering: writes */
+#define CBE_IOPTE_SO_RW         0x1800000000000000ul /* ordering: r & w */
+#define CBE_IOPTE_RPN_Mask      0x07fffffffffff000ul /* RPN */
+#define CBE_IOPTE_H             0x0000000000000800ul /* cache hint */
+#define CBE_IOPTE_IOID_Mask     0x00000000000007fful /* ioid */
 /* Boot time flags */
 extern int iommu_is_off;
 extern int iommu_force_on;
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index d2a65e8ca6ae..f78f65c38f05 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -20,6 +20,11 @@
 #define _ASM_POWERPC_LPPACA_H
 #ifdef __KERNEL__
+/* These definitions relate to hypervisors that only exist when using
+ * a server type processor
+ */
+#ifdef CONFIG_PPC_BOOK3S
 //=============================================================================
 //
 //      This control block contains the data that is shared between the
@@ -158,5 +163,6 @@ struct slb_shadow {
 extern struct slb_shadow slb_shadow[];
+#endif /* CONFIG_PPC_BOOK3S */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 0efdb1dfdc5f..11d1fc3a8962 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -110,6 +110,10 @@ struct machdep_calls {
        void            (*show_percpuinfo)(struct seq_file *m, int i);
        void            (*init_IRQ)(void);
+        /* Return an irq, or NO_IRQ to indicate there are none pending.
+         * If for some reason there is no irq, but the interrupt
+         * shouldn't be counted as spurious, return NO_IRQ_IGNORE. */
        unsigned int    (*get_irq)(void);
 #ifdef CONFIG_KEXEC
        void            (*kexec_cpu_down)(int crash_shutdown, int secondary);
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index cbf154387091..fb57ded592f9 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -52,6 +52,11 @@
 */
 #define MMU_FTR_NEED_DTLB_SW_LRU        ASM_CONST(0x00200000)
+/* This indicates that the processor uses the ISA 2.06 server tlbie
+ * mnemonics
+ */
+#define MMU_FTR_TLBIE_206               ASM_CONST(0x00400000)
 #ifndef __ASSEMBLY__
 #include <asm/cputable.h>
@@ -69,10 +74,10 @@ extern void early_init_mmu_secondary(void);
 #endif /* !__ASSEMBLY__ */
-#ifdef CONFIG_PPC64
+#if defined(CONFIG_PPC_STD_MMU_64)
 /* 64-bit classic hash table MMU */
 #  include <asm/mmu-hash64.h>
-#elif defined(CONFIG_PPC_STD_MMU)
+#elif defined(CONFIG_PPC_STD_MMU_32)
 /* 32-bit classic hash table MMU */
 #  include <asm/mmu-hash32.h>
 #elif defined(CONFIG_40x)
diff --git a/arch/powerpc/include/asm/mpc86xx.h b/arch/powerpc/include/asm/mpc86xx.h
deleted file mode 100644
index 15f650f987e7..000000000000
--- a/arch/powerpc/include/asm/mpc86xx.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * MPC86xx definitions
- *
- * Author: Jeff Brown
- *
- * Copyright 2004 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_POWERPC_MPC86xx_H__
-#define __ASM_POWERPC_MPC86xx_H__
-#include <asm/mmu.h>
-#ifdef CONFIG_PPC_86xx
-#define CPU0_BOOT_RELEASE 0x01000000
-#define CPU1_BOOT_RELEASE 0x02000000
-#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
-#define MCM_PORT_CONFIG_OFFSET 0x1010
-/* Offset from CCSRBAR */
-#define MPC86xx_MCM_OFFSET      (0x00000)
-#define MPC86xx_MCM_SIZE        (0x02000)
-#endif /* CONFIG_PPC_86xx */
-#endif /* __ASM_POWERPC_MPC86xx_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 6ef055723019..c8a3cbfe02ff 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -43,6 +43,7 @@ struct task_struct;
 * processor.
 */
 struct paca_struct {
+#ifdef CONFIG_PPC_BOOK3S
        /*
         * Because hw_cpu_id, unlike other paca fields, is accessed
         * routinely from other CPUs (from the IRQ code), we stick to
@@ -51,7 +52,7 @@ struct paca_struct {
         */
        struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
+#endif /* CONFIG_PPC_BOOK3S */
        /*
         * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 
         * load lock_token and paca_index with a single lwz
@@ -64,13 +65,16 @@ struct paca_struct {
        u64 kernel_toc;                 /* Kernel TOC address */
        u64 kernelbase;                 /* Base address of kernel */
        u64 kernel_msr;                 /* MSR while running in kernel */
+#ifdef CONFIG_PPC_STD_MMU_64
        u64 stab_real;                  /* Absolute address of segment table */
        u64 stab_addr;                  /* Virtual address of segment table */
+#endif /* CONFIG_PPC_STD_MMU_64 */
        void *emergency_sp;             /* pointer to emergency stack */
        u64 data_offset;                /* per cpu data offset */
        s16 hw_cpu_id;                  /* Physical processor number */
        u8 cpu_start;                   /* At startup, processor spins until */
                                        /* this becomes non-zero. */
+#ifdef CONFIG_PPC_STD_MMU_64
        struct slb_shadow *slb_shadow_ptr;
        /*
@@ -81,11 +85,13 @@ struct paca_struct {
        u64 exmc[10];           /* used for machine checks */
        u64 exslb[10];          /* used for SLB/segment table misses
                                 * on the linear mapping */
+        /* SLB related definitions */
-        mm_context_t context;
        u16 vmalloc_sllp;
        u16 slb_cache_ptr;
        u16 slb_cache[SLB_CACHE_ENTRIES];
+#endif /* CONFIG_PPC_STD_MMU_64 */
+        mm_context_t context;
        /*
         * then miscellaneous read-write fields
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 32cbf16f10ea..4940662ee87e 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -231,6 +231,11 @@ extern void copy_user_page(void *to, void *from, unsigned long vaddr,
                struct page *p);
 extern int page_is_ram(unsigned long pfn);
+#ifdef CONFIG_PPC_SMLPAR
+void arch_free_page(struct page *page, int order);
+#define HAVE_ARCH_FREE_PAGE
+#endif
 struct vm_area_struct;
 typedef struct page *pgtable_t;
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 84007afabdb5..4c61fa0b8d75 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -86,17 +86,12 @@ struct pci_controller {
        void *io_base_alloc;
 #endif
        resource_size_t io_base_phys;
-#ifndef CONFIG_PPC64
        resource_size_t pci_io_size;
-#endif
        /* Some machines (PReP) have a non 1:1 mapping of
         * the PCI memory space in the CPU bus space
         */
        resource_size_t pci_mem_offset;
-#ifdef CONFIG_PPC64
-        unsigned long pci_io_size;
-#endif
        /* Some machines have a special region to forward the ISA
         * "memory" cycles such as VGA memory regions. Left to 0
@@ -140,10 +135,12 @@ struct pci_controller {
        struct resource io_resource;
        struct resource mem_resources[3];
        int global_number;              /* PCI domain number */
+        resource_size_t dma_window_base_cur;
+        resource_size_t dma_window_size;
 #ifdef CONFIG_PPC64
        unsigned long buid;
-        unsigned long dma_window_base_cur;
-        unsigned long dma_window_size;
        void *private_data;
 #endif  /* CONFIG_PPC64 */
@@ -185,7 +182,6 @@ extern int early_find_capability(struct pci_controller *hose, int bus,
 extern void setup_indirect_pci(struct pci_controller* hose,
                               resource_size_t cfg_addr,
                               resource_size_t cfg_data, u32 flags);
-extern void setup_grackle(struct pci_controller *hose);
 #else   /* CONFIG_PPC64 */
 /*
@@ -221,6 +217,7 @@ struct pci_dn {
 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
+extern void * update_dn_pci_info(struct device_node *dn, void *data);
 /* Get a device_node from a pci_dev.  This code must be fast except
 * in the case where the sysdata is incorrect and needs to be fixed
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index c40db05f21e0..8cd083c61503 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -31,9 +31,11 @@
 #error TASK_SIZE_USER64 exceeds pagetable range
 #endif
+#ifdef CONFIG_PPC_STD_MMU_64
 #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
 #error TASK_SIZE_USER64 exceeds user VSID range
 #endif
+#endif
 /*
 * Define the address range of the vmalloc VM area.
@@ -199,8 +201,11 @@ static inline unsigned long pte_update(struct mm_struct *mm,
        if (!huge)
                assert_pte_locked(mm, addr);
+#ifdef CONFIG_PPC_STD_MMU_64
        if (old & _PAGE_HASHPTE)
                hpte_need_flush(mm, addr, ptep, old, huge);
+#endif
        return old;
 }
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 640ccbbc0977..b74f16d45cb4 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -25,6 +25,7 @@
 #define PPC_INST_LSWI                   0x7c0004aa
 #define PPC_INST_LSWX                   0x7c00042a
 #define PPC_INST_LWSYNC                 0x7c2004ac
+#define PPC_INST_LXVD2X                 0x7c000698
 #define PPC_INST_MCRXR                  0x7c000400
 #define PPC_INST_MCRXR_MASK             0xfc0007fe
 #define PPC_INST_MFSPR_PVR              0x7c1f42a6
@@ -43,14 +44,18 @@
 #define PPC_INST_STSWI                  0x7c0005aa
 #define PPC_INST_STSWX                  0x7c00052a
+#define PPC_INST_STXVD2X                0x7c000798
+#define PPC_INST_TLBIE                  0x7c000264
 #define PPC_INST_TLBILX                 0x7c000024
 #define PPC_INST_WAIT                   0x7c00007c
 /* macros to insert fields into opcodes */
-#define __PPC_RA(a)     ((a & 0x1f) << 16)
+#define __PPC_RA(a)     (((a) & 0x1f) << 16)
-#define __PPC_RB(b)     ((b & 0x1f) << 11)
+#define __PPC_RB(b)     (((b) & 0x1f) << 11)
-#define __PPC_T_TLB(t)  ((t & 0x3) << 21)
+#define __PPC_RS(s)     (((s) & 0x1f) << 21)
-#define __PPC_WC(w)     ((w & 0x3) << 21)
+#define __PPC_XS(s)     ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
+#define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
+#define __PPC_WC(w)     (((w) & 0x3) << 21)
 /* Deal with instructions that older assemblers aren't aware of */
 #define PPC_DCBAL(a, b)         stringify_in_c(.long PPC_INST_DCBAL | \
@@ -69,5 +74,17 @@
 #define PPC_TLBILX_VA(a, b)     PPC_TLBILX(3, a, b)
 #define PPC_WAIT(w)             stringify_in_c(.long PPC_INST_WAIT | \
                                        __PPC_WC(w))
+#define PPC_TLBIE(lp,a)         stringify_in_c(.long PPC_INST_TLBIE | \
+                                               __PPC_RB(a) | __PPC_RS(lp))
+/*
+ * Define what the VSX XX1 form instructions will look like, then add
+ * the 128 bit load store instructions based on that.
+ */
+#define VSX_XX1(s, a, b)        (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
+#define STXVD2X(s, a, b)        stringify_in_c(.long PPC_INST_STXVD2X | \
+                                               VSX_XX1((s), (a), (b)))
+#define LXVD2X(s, a, b)         stringify_in_c(.long PPC_INST_LXVD2X | \
+                                               VSX_XX1((s), (a), (b)))
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 384d90c9c272..f9729529c20d 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -76,16 +76,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR);					\
                                REST_10GPRS(22, base)
 #endif
-/*
- * Define what the VSX XX1 form instructions will look like, then add
- * the 128 bit load store instructions based on that.
- */
-#define VSX_XX1(xs, ra, rb)     (((xs) & 0x1f) << 21 | ((ra) << 16) |  \
-                                 ((rb) << 11) | (((xs) >> 5)))
-#define STXVD2X(xs, ra, rb)     .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
-#define LXVD2X(xs, ra, rb)      .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h
index cdb6fd814de8..7f065e178ec4 100644
--- a/arch/powerpc/include/asm/ps3.h
+++ b/arch/powerpc/include/asm/ps3.h
@@ -53,6 +53,13 @@ enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void);
 extern u64 ps3_os_area_get_rtc_diff(void);
 extern void ps3_os_area_set_rtc_diff(u64 rtc_diff);
+struct ps3_os_area_flash_ops {
+        ssize_t (*read)(void *buf, size_t count, loff_t pos);
+        ssize_t (*write)(const void *buf, size_t count, loff_t pos);
+};
+extern void ps3_os_area_flash_register(const struct ps3_os_area_flash_ops *ops);
 /* dma routines */
 enum ps3_dma_page_size {
@@ -418,15 +425,15 @@ static inline struct ps3_system_bus_driver *
 * @data: Data to set
 */
-static inline void ps3_system_bus_set_driver_data(
+static inline void ps3_system_bus_set_drvdata(
        struct ps3_system_bus_device *dev, void *data)
 {
-        dev->core.driver_data = data;
+        dev_set_drvdata(&dev->core, data);
 }
-static inline void *ps3_system_bus_get_driver_data(
+static inline void *ps3_system_bus_get_drvdata(
        struct ps3_system_bus_device *dev)
 {
-        return dev->core.driver_data;
+        return dev_get_drvdata(&dev->core);
 }
 /* These two need global scope for get_dma_ops(). */
@@ -520,7 +527,4 @@ void ps3_sync_irq(int node);
 u32 ps3_get_hw_thread_id(int cpu);
 u64 ps3_get_spe_id(void *arg);
-/* mutex synchronizing GPU accesses and video mode changes */
-extern struct mutex ps3_gpu_mutex;
 #endif
diff --git a/arch/powerpc/include/asm/ps3gpu.h b/arch/powerpc/include/asm/ps3gpu.h
new file mode 100644
index 000000000000..b2b89591907c
--- /dev/null
+++ b/arch/powerpc/include/asm/ps3gpu.h
@@ -0,0 +1,86 @@
+/*
+ *  PS3 GPU declarations.
+ *
+ *  Copyright 2009 Sony Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.
+ *  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _ASM_POWERPC_PS3GPU_H
+#define _ASM_POWERPC_PS3GPU_H
+#include <linux/mutex.h>
+#include <asm/lv1call.h>
+#define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC    0x101
+#define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP    0x102
+#define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP        0x600
+#define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT         0x601
+#define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC    0x602
+#define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE        0x603
+#define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION       (1ULL << 32)
+#define L1GPU_DISPLAY_SYNC_HSYNC                1
+#define L1GPU_DISPLAY_SYNC_VSYNC                2
+/* mutex synchronizing GPU accesses and video mode changes */
+extern struct mutex ps3_gpu_mutex;
+static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
+                                       u64 ddr_offset)
+{
+        return lv1_gpu_context_attribute(context_handle,
+                                         L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
+                                         head, ddr_offset, 0, 0);
+}
+static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
+                                       u64 ddr_offset)
+{
+        return lv1_gpu_context_attribute(context_handle,
+                                         L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
+                                         head, ddr_offset, 0, 0);
+}
+static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
+                                   u64 xdr_size, u64 ioif_offset)
+{
+        return lv1_gpu_context_attribute(context_handle,
+                                         L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
+                                         xdr_lpar, xdr_size, ioif_offset, 0);
+}
+static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
+                                  u64 ioif_offset, u64 sync_width, u64 pitch)
+{
+        return lv1_gpu_context_attribute(context_handle,
+                                         L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
+                                         ddr_offset, ioif_offset, sync_width,
+                                         pitch);
+}
+static inline int lv1_gpu_fb_close(u64 context_handle)
+{
+        return lv1_gpu_context_attribute(context_handle,
+                                         L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0,
+                                         0, 0, 0);
+}
+#endif /* _ASM_POWERPC_PS3GPU_H */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index c9c678fb2538..8c341490cfc5 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -135,7 +135,9 @@ do {									      \
 * These are defined as per linux/ptrace.h, which see.
 */
 #define arch_has_single_step()  (1)
+#define arch_has_block_step()   (!cpu_has_feature(CPU_FTR_601))
 extern void user_enable_single_step(struct task_struct *);
+extern void user_enable_block_step(struct task_struct *);
 extern void user_disable_single_step(struct task_struct *);
 #endif /* __ASSEMBLY__ */
@@ -288,4 +290,6 @@ extern void user_disable_single_step(struct task_struct *);
 #define PPC_PTRACE_PEEKUSR_3264  0x91
 #define PPC_PTRACE_POKEUSR_3264  0x90
+#define PTRACE_SINGLEBLOCK      0x100   /* resume execution until next branch */
 #endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 2701753d9937..157c5ca581c8 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -22,7 +22,7 @@
 #include <asm/cpm.h>
 #include <asm/immap_qe.h>
-#define QE_NUM_OF_SNUM  28
+#define QE_NUM_OF_SNUM  256     /* There are 256 serial number in QE */
 #define QE_NUM_OF_BRGS  16
 #define QE_NUM_OF_PORTS 1024
@@ -152,6 +152,9 @@ unsigned int qe_get_brg_clk(void);
 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
 int qe_get_snum(void);
 void qe_put_snum(u8 snum);
+unsigned int qe_get_num_of_risc(void);
+unsigned int qe_get_num_of_snums(void);
 /* we actually use cpm_muram implementation, define this for convenience */
 #define qe_muram_init cpm_muram_init
 #define qe_muram_alloc cpm_muram_alloc
@@ -231,12 +234,16 @@ struct qe_bd {
 #define QE_ALIGNMENT_OF_PRAM    64
 /* RISC allocation */
-enum qe_risc_allocation {
+#define QE_RISC_ALLOCATION_RISC1        0x1  /* RISC 1 */
-        QE_RISC_ALLOCATION_RISC1 = 1,   /* RISC 1 */
+#define QE_RISC_ALLOCATION_RISC2        0x2  /* RISC 2 */
-        QE_RISC_ALLOCATION_RISC2 = 2,   /* RISC 2 */
+#define QE_RISC_ALLOCATION_RISC3        0x4  /* RISC 3 */
-        QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3  /* Dynamically choose
+#define QE_RISC_ALLOCATION_RISC4        0x8  /* RISC 4 */
-                                                   RISC 1 or RISC 2 */
+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2      (QE_RISC_ALLOCATION_RISC1 | \
-};
+                                                 QE_RISC_ALLOCATION_RISC2)
+#define QE_RISC_ALLOCATION_FOUR_RISCS   (QE_RISC_ALLOCATION_RISC1 | \
+                                         QE_RISC_ALLOCATION_RISC2 | \
+                                         QE_RISC_ALLOCATION_RISC3 | \
+                                         QE_RISC_ALLOCATION_RISC4)
 /* QE extended filtering Table Lookup Key Size */
 enum qe_fltr_tbl_lookup_key_size {
@@ -668,6 +675,8 @@ struct ucc_slow_pram {
 #define UCC_GETH_UPSMR_RMM      0x00001000
 #define UCC_GETH_UPSMR_CAM      0x00000400
 #define UCC_GETH_UPSMR_BRO      0x00000200
+#define UCC_GETH_UPSMR_SMM      0x00000080
+#define UCC_GETH_UPSMR_SGMM     0x00000020
 /* UCC Transmit On Demand Register (UTODR) */
 #define UCC_SLOW_TOD    0x8000
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index fb359b0a6937..a3c28e46947c 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -745,11 +745,11 @@
                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
 #ifdef CONFIG_PPC64
 #define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
-                                     : : "r" (v))
+                                     : : "r" (v) : "memory")
 #define mtmsrd(v)       __mtmsrd((v), 0)
 #define mtmsr(v)        mtmsrd(v)
 #else
-#define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
+#define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v) : "memory")
 #endif
 #define mfspr(rn)       ({unsigned long rval; \
diff --git a/arch/powerpc/include/asm/scatterlist.h b/arch/powerpc/include/asm/scatterlist.h
index fcf7d55afe45..912bf597870f 100644
--- a/arch/powerpc/include/asm/scatterlist.h
+++ b/arch/powerpc/include/asm/scatterlist.h
@@ -21,7 +21,7 @@ struct scatterlist {
        unsigned int offset;
        unsigned int length;
-        /* For TCE support */
+        /* For TCE or SWIOTLB support */
        dma_addr_t dma_address;
        u32 dma_length;
 };
@@ -34,11 +34,7 @@ struct scatterlist {
 * is 0.
 */
 #define sg_dma_address(sg)      ((sg)->dma_address)
-#ifdef __powerpc64__
 #define sg_dma_len(sg)          ((sg)->dma_length)
-#else
-#define sg_dma_len(sg)          ((sg)->length)
-#endif
 #ifdef __powerpc64__
 #define ISA_DMA_THRESHOLD       (~0UL)
diff --git a/arch/powerpc/include/asm/swiotlb.h b/arch/powerpc/include/asm/swiotlb.h
new file mode 100644
index 000000000000..30891d6e2bc1
--- /dev/null
+++ b/arch/powerpc/include/asm/swiotlb.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2009 Becky Bruce, Freescale Semiconductor
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __ASM_SWIOTLB_H
+#define __ASM_SWIOTLB_H
+#include <linux/swiotlb.h>
+extern struct dma_mapping_ops swiotlb_dma_ops;
+extern struct dma_mapping_ops swiotlb_pci_dma_ops;
+int swiotlb_arch_address_needs_mapping(struct device *, dma_addr_t,
+                                       size_t size);
+static inline void dma_mark_clean(void *addr, size_t size) {}
+extern unsigned int ppc_swiotlb_enable;
+int __init swiotlb_setup_bus_notifier(void);
+#endif /* __ASM_SWIOTLB_H */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index a0b92de51c7e..370600ca2765 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -325,3 +325,4 @@ SYSCALL(inotify_init1)
 SYSCALL_SPU(perf_counter_open)
 COMPAT_SYS_SPU(preadv)
 COMPAT_SYS_SPU(pwritev)
+COMPAT_SYS(rt_tgsigqueueinfo)
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index 2b2420a49884..bb8e006a47c6 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -211,7 +211,7 @@ extern struct task_struct *_switch(struct thread_struct *prev,
 extern unsigned int rtas_data;
 extern int mem_init_done;       /* set on boot once kmalloc can be called */
-extern int init_bootmem_done;   /* set on !NUMA once bootmem is available */
+extern int init_bootmem_done;   /* set once bootmem is available */
 extern phys_addr_t memory_limit;
 extern unsigned long klimit;
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 4badac2d11d1..cef080bfc607 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -344,10 +344,11 @@
 #define __NR_perf_counter_open  319
 #define __NR_preadv             320
 #define __NR_pwritev            321
+#define __NR_rt_tgsigqueueinfo  322
 #ifdef __KERNEL__
-#define __NR_syscalls           322
+#define __NR_syscalls           323
 #define __NR__exit __NR_exit
 #define NR_syscalls     __NR_syscalls
diff --git a/arch/powerpc/include/asm/xilinx_pci.h b/arch/powerpc/include/asm/xilinx_pci.h
new file mode 100644
index 000000000000..7a8275caf6af
--- /dev/null
+++ b/arch/powerpc/include/asm/xilinx_pci.h
@@ -0,0 +1,21 @@
+/*
+ * Xilinx pci external definitions
+ *
+ * Copyright 2009 Roderick Colenbrander
+ * Copyright 2009 Secret Lab Technologies Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef INCLUDE_XILINX_PCI
+#define INCLUDE_XILINX_PCI
+#ifdef CONFIG_XILINX_PCI
+extern void __init xilinx_pci_init(void);
+#else
+static inline void __init xilinx_pci_init(void) { return; }
+#endif
+#endif /* INCLUDE_XILINX_PCI */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index a2c683403c2b..612b0c4dc26d 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -36,7 +36,7 @@ obj-$(CONFIG_PPC64)		+= setup_64.o sys_ppc32.o \
                                   firmware.o nvram_64.o
 obj64-$(CONFIG_RELOCATABLE)     += reloc_64.o
 obj-$(CONFIG_PPC64)             += vdso64/
-obj-$(CONFIG_ALTIVEC)           += vecemu.o vector.o
+obj-$(CONFIG_ALTIVEC)           += vecemu.o
 obj-$(CONFIG_PPC_970_NAP)       += idle_power4.o
 obj-$(CONFIG_PPC_OF)            += of_device.o of_platform.o prom_parse.o
 obj-$(CONFIG_PPC_CLOCK)         += clock.o
@@ -82,6 +82,7 @@ obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_KPROBES)           += kprobes.o
 obj-$(CONFIG_PPC_UDBG_16550)    += legacy_serial.o udbg_16550.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
+obj-$(CONFIG_SWIOTLB)           += dma-swiotlb.o
 pci64-$(CONFIG_PPC64)           += pci_dn.o isa-bridge.o
 obj-$(CONFIG_PCI)               += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \
@@ -111,6 +112,7 @@ obj-y				+= ppc_save_regs.o
 endif
 extra-$(CONFIG_PPC_FPU)         += fpu.o
+extra-$(CONFIG_ALTIVEC)         += vector.o
 extra-$(CONFIG_PPC64)           += entry_64.o
 extra-y                         += systbl_chk.i
@@ -123,6 +125,7 @@ PHONY += systbl_chk
 systbl_chk: $(src)/systbl_chk.sh $(obj)/systbl_chk.i
        $(call cmd,systbl_chk)
+ifeq ($(CONFIG_PPC_OF_BOOT_TRAMPOLINE),y)
 $(obj)/built-in.o:              prom_init_check
 quiet_cmd_prom_init_check = CALL    $<
@@ -131,5 +134,6 @@ quiet_cmd_prom_init_check = CALL    $<
 PHONY += prom_init_check
 prom_init_check: $(src)/prom_init_check.sh $(obj)/prom_init.o
        $(call cmd,prom_init_check)
+endif
 clean-files := vmlinux.lds
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 5ffcfaa77d6a..a5b632e52fae 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -24,6 +24,7 @@
 #include <asm/system.h>
 #include <asm/cache.h>
 #include <asm/cputable.h>
+#include <asm/emulated_ops.h>
 struct aligninfo {
        unsigned char len;
@@ -730,8 +731,10 @@ int fix_alignment(struct pt_regs *regs)
        areg = dsisr & 0x1f;            /* register to update */
 #ifdef CONFIG_SPE
-        if ((instr >> 26) == 0x4)
+        if ((instr >> 26) == 0x4) {
+                PPC_WARN_EMULATED(spe);
                return emulate_spe(regs, reg, instr);
+        }
 #endif
        instr = (dsisr >> 10) & 0x7f;
@@ -783,23 +786,28 @@ int fix_alignment(struct pt_regs *regs)
                        flags |= SPLT;
                        nb = 8;
                }
+                PPC_WARN_EMULATED(vsx);
                return emulate_vsx(addr, reg, areg, regs, flags, nb);
        }
 #endif
        /* A size of 0 indicates an instruction we don't support, with
         * the exception of DCBZ which is handled as a special case here
         */
-        if (instr == DCBZ)
+        if (instr == DCBZ) {
+                PPC_WARN_EMULATED(dcbz);
                return emulate_dcbz(regs, addr);
+        }
        if (unlikely(nb == 0))
                return 0;
        /* Load/Store Multiple instructions are handled in their own
         * function
         */
-        if (flags & M)
+        if (flags & M) {
+                PPC_WARN_EMULATED(multiple);
                return emulate_multiple(regs, addr, reg, nb,
                                        flags, instr, swiz);
+        }
        /* Verify the address of the operand */
        if (unlikely(user_mode(regs) &&
@@ -816,8 +824,12 @@ int fix_alignment(struct pt_regs *regs)
        }
        /* Special case for 16-byte FP loads and stores */
-        if (nb == 16)
+        if (nb == 16) {
+                PPC_WARN_EMULATED(fp_pair);
                return emulate_fp_pair(addr, reg, flags);
+        }
+        PPC_WARN_EMULATED(unaligned);
        /* If we are loading, get the data from user space, else
         * get it from register values
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index e981d1ce1914..561b64652311 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -122,8 +122,6 @@ int main(void)
        DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack));
        DEFINE(PACACURRENT, offsetof(struct paca_struct, __current));
        DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr));
-        DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real));
-        DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr));
        DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr));
        DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1));
        DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc));
@@ -132,35 +130,30 @@ int main(void)
        DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
        DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
        DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_counter_pending));
-        DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
-        DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
        DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
-        DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
 #ifdef CONFIG_PPC_MM_SLICES
        DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
                                            context.low_slices_psize));
        DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct,
                                            context.high_slices_psize));
        DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
+#endif /* CONFIG_PPC_MM_SLICES */
+#ifdef CONFIG_PPC_STD_MMU_64
+        DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real));
+        DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr));
+        DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
+        DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
+        DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
+#ifdef CONFIG_PPC_MM_SLICES
        DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp));
 #else
        DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, context.sllp));
 #endif /* CONFIG_PPC_MM_SLICES */
        DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
        DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
        DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb));
-        DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
        DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr));
-        DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
-        DEFINE(PACA_STARTPURR, offsetof(struct paca_struct, startpurr));
-        DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr));
-        DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
-        DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
        DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr));
-        DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset));
-        DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
        DEFINE(SLBSHADOW_STACKVSID,
               offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid));
        DEFINE(SLBSHADOW_STACKESID,
@@ -170,6 +163,15 @@ int main(void)
        DEFINE(LPPACAANYINT, offsetof(struct lppaca, int_dword.any_int));
        DEFINE(LPPACADECRINT, offsetof(struct lppaca, int_dword.fields.decr_int));
        DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area));
+#endif /* CONFIG_PPC_STD_MMU_64 */
+        DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
+        DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
+        DEFINE(PACA_STARTPURR, offsetof(struct paca_struct, startpurr));
+        DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr));
+        DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
+        DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
+        DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset));
+        DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
 #endif /* CONFIG_PPC64 */
        /* RTAS */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 3e33fb933d99..4a24a2fc4574 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -427,7 +427,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER7 (architected)",
                .cpu_features           = CPU_FTRS_POWER7,
                .cpu_user_features      = COMMON_USER_POWER7,
-                .mmu_features           = MMU_FTR_HPTE_TABLE,
+                .mmu_features           = MMU_FTR_HPTE_TABLE |
+                        MMU_FTR_TLBIE_206,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .machine_check          = machine_check_generic,
@@ -441,7 +442,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER7 (raw)",
                .cpu_features           = CPU_FTRS_POWER7,
                .cpu_user_features      = COMMON_USER_POWER7,
-                .mmu_features           = MMU_FTR_HPTE_TABLE,
+                .mmu_features           = MMU_FTR_HPTE_TABLE |
+                        MMU_FTR_TLBIE_206,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 6,
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
new file mode 100644
index 000000000000..68ccf11e4f19
--- /dev/null
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -0,0 +1,163 @@
+/*
+ * Contains routines needed to support swiotlb for ppc.
+ *
+ * Copyright (C) 2009 Becky Bruce, Freescale Semiconductor
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/dma-mapping.h>
+#include <linux/pfn.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <asm/machdep.h>
+#include <asm/swiotlb.h>
+#include <asm/dma.h>
+#include <asm/abs_addr.h>
+int swiotlb __read_mostly;
+unsigned int ppc_swiotlb_enable;
+void *swiotlb_bus_to_virt(struct device *hwdev, dma_addr_t addr)
+{
+        unsigned long pfn = PFN_DOWN(swiotlb_bus_to_phys(hwdev, addr));
+        void *pageaddr = page_address(pfn_to_page(pfn));
+        if (pageaddr != NULL)
+                return pageaddr + (addr % PAGE_SIZE);
+        return NULL;
+}
+dma_addr_t swiotlb_phys_to_bus(struct device *hwdev, phys_addr_t paddr)
+{
+        return paddr + get_dma_direct_offset(hwdev);
+}
+phys_addr_t swiotlb_bus_to_phys(struct device *hwdev, dma_addr_t baddr)
+{
+        return baddr - get_dma_direct_offset(hwdev);
+}
+/*
+ * Determine if an address needs bounce buffering via swiotlb.
+ * Going forward I expect the swiotlb code to generalize on using
+ * a dma_ops->addr_needs_map, and this function will move from here to the
+ * generic swiotlb code.
+ */
+int
+swiotlb_arch_address_needs_mapping(struct device *hwdev, dma_addr_t addr,
+                                   size_t size)
+{
+        struct dma_mapping_ops *dma_ops = get_dma_ops(hwdev);
+        BUG_ON(!dma_ops);
+        return dma_ops->addr_needs_map(hwdev, addr, size);
+}
+/*
+ * Determine if an address is reachable by a pci device, or if we must bounce.
+ */
+static int
+swiotlb_pci_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size)
+{
+        u64 mask = dma_get_mask(hwdev);
+        dma_addr_t max;
+        struct pci_controller *hose;
+        struct pci_dev *pdev = to_pci_dev(hwdev);
+        hose = pci_bus_to_host(pdev->bus);
+        max = hose->dma_window_base_cur + hose->dma_window_size;
+        /* check that we're within mapped pci window space */
+        if ((addr + size > max) | (addr < hose->dma_window_base_cur))
+                return 1;
+        return !is_buffer_dma_capable(mask, addr, size);
+}
+static int
+swiotlb_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size)
+{
+        return !is_buffer_dma_capable(dma_get_mask(hwdev), addr, size);
+}
+/*
+ * At the moment, all platforms that use this code only require
+ * swiotlb to be used if we're operating on HIGHMEM.  Since
+ * we don't ever call anything other than map_sg, unmap_sg,
+ * map_page, and unmap_page on highmem, use normal dma_ops
+ * for everything else.
+ */
+struct dma_mapping_ops swiotlb_dma_ops = {
+        .alloc_coherent = dma_direct_alloc_coherent,
+        .free_coherent = dma_direct_free_coherent,
+        .map_sg = swiotlb_map_sg_attrs,
+        .unmap_sg = swiotlb_unmap_sg_attrs,
+        .dma_supported = swiotlb_dma_supported,
+        .map_page = swiotlb_map_page,
+        .unmap_page = swiotlb_unmap_page,
+        .addr_needs_map = swiotlb_addr_needs_map,
+        .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu,
+        .sync_single_range_for_device = swiotlb_sync_single_range_for_device,
+        .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+        .sync_sg_for_device = swiotlb_sync_sg_for_device
+};
+struct dma_mapping_ops swiotlb_pci_dma_ops = {
+        .alloc_coherent = dma_direct_alloc_coherent,
+        .free_coherent = dma_direct_free_coherent,
+        .map_sg = swiotlb_map_sg_attrs,
+        .unmap_sg = swiotlb_unmap_sg_attrs,
+        .dma_supported = swiotlb_dma_supported,
+        .map_page = swiotlb_map_page,
+        .unmap_page = swiotlb_unmap_page,
+        .addr_needs_map = swiotlb_pci_addr_needs_map,
+        .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu,
+        .sync_single_range_for_device = swiotlb_sync_single_range_for_device,
+        .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+        .sync_sg_for_device = swiotlb_sync_sg_for_device
+};
+static int ppc_swiotlb_bus_notify(struct notifier_block *nb,
+                                  unsigned long action, void *data)
+{
+        struct device *dev = data;
+        /* We are only intereted in device addition */
+        if (action != BUS_NOTIFY_ADD_DEVICE)
+                return 0;
+        /* May need to bounce if the device can't address all of DRAM */
+        if (dma_get_mask(dev) < lmb_end_of_DRAM())
+                set_dma_ops(dev, &swiotlb_dma_ops);
+        return NOTIFY_DONE;
+}
+static struct notifier_block ppc_swiotlb_plat_bus_notifier = {
+        .notifier_call = ppc_swiotlb_bus_notify,
+        .priority = 0,
+};
+static struct notifier_block ppc_swiotlb_of_bus_notifier = {
+        .notifier_call = ppc_swiotlb_bus_notify,
+        .priority = 0,
+};
+int __init swiotlb_setup_bus_notifier(void)
+{
+        bus_register_notifier(&platform_bus_type,
+                              &ppc_swiotlb_plat_bus_notifier);
+        bus_register_notifier(&of_platform_bus_type,
+                              &ppc_swiotlb_of_bus_notifier);
+        return 0;
+}
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 6b02793dc75b..20a60d661ba8 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -19,7 +19,7 @@
 * default the offset is PCI_DRAM_OFFSET.
 */
-static unsigned long get_dma_direct_offset(struct device *dev)
+unsigned long get_dma_direct_offset(struct device *dev)
 {
        if (dev)
                return (unsigned long)dev->archdata.dma_data;
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
new file mode 100644
index 000000000000..eb898112e577
--- /dev/null
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -0,0 +1,978 @@
+/*
+ * This file contains the 64-bit "server" PowerPC variant
+ * of the low level exception handling including exception
+ * vectors, exception return, part of the slb and stab
+ * handling and other fixed offset specific things.
+ *
+ * This file is meant to be #included from head_64.S due to
+ * position dependant assembly.
+ *
+ * Most of this originates from head_64.S and thus has the same
+ * copyright history.
+ *
+ */
+/*
+ * We layout physical memory as follows:
+ * 0x0000 - 0x00ff : Secondary processor spin code
+ * 0x0100 - 0x2fff : pSeries Interrupt prologs
+ * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
+ * 0x6000 - 0x6fff : Initial (CPU0) segment table
+ * 0x7000 - 0x7fff : FWNMI data area
+ * 0x8000 -        : Early init and support code
+ */
+/*
+ *   SPRG Usage
+ *
+ *   Register   Definition
+ *
+ *   SPRG0      reserved for hypervisor
+ *   SPRG1      temp - used to save gpr
+ *   SPRG2      temp - used to save gpr
+ *   SPRG3      virt addr of paca
+ */
+/*
+ * This is the start of the interrupt handlers for pSeries
+ * This code runs with relocation off.
+ * Code from here to __end_interrupts gets copied down to real
+ * address 0x100 when we are running a relocatable kernel.
+ * Therefore any relative branches in this section must only
+ * branch to labels in this section.
+ */
+        . = 0x100
+        .globl __start_interrupts
+__start_interrupts:
+        STD_EXCEPTION_PSERIES(0x100, system_reset)
+        . = 0x200
+_machine_check_pSeries:
+        HMT_MEDIUM
+        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
+        . = 0x300
+        .globl data_access_pSeries
+data_access_pSeries:
+        HMT_MEDIUM
+        mtspr   SPRN_SPRG1,r13
+BEGIN_FTR_SECTION
+        mtspr   SPRN_SPRG2,r12
+        mfspr   r13,SPRN_DAR
+        mfspr   r12,SPRN_DSISR
+        srdi    r13,r13,60
+        rlwimi  r13,r12,16,0x20
+        mfcr    r12
+        cmpwi   r13,0x2c
+        beq     do_stab_bolted_pSeries
+        mtcrf   0x80,r12
+        mfspr   r12,SPRN_SPRG2
+END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
+        . = 0x380
+        .globl data_access_slb_pSeries
+data_access_slb_pSeries:
+        HMT_MEDIUM
+        mtspr   SPRN_SPRG1,r13
+        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        std     r3,PACA_EXSLB+EX_R3(r13)
+        mfspr   r3,SPRN_DAR
+        std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
+        mfcr    r9
+#ifdef __DISABLED__
+        /* Keep that around for when we re-implement dynamic VSIDs */
+        cmpdi   r3,0
+        bge     slb_miss_user_pseries
+#endif /* __DISABLED__ */
+        std     r10,PACA_EXSLB+EX_R10(r13)
+        std     r11,PACA_EXSLB+EX_R11(r13)
+        std     r12,PACA_EXSLB+EX_R12(r13)
+        mfspr   r10,SPRN_SPRG1
+        std     r10,PACA_EXSLB+EX_R13(r13)
+        mfspr   r12,SPRN_SRR1           /* and SRR1 */
+#ifndef CONFIG_RELOCATABLE
+        b       .slb_miss_realmode
+#else
+        /*
+         * We can't just use a direct branch to .slb_miss_realmode
+         * because the distance from here to there depends on where
+         * the kernel ends up being put.
+         */
+        mfctr   r11
+        ld      r10,PACAKBASE(r13)
+        LOAD_HANDLER(r10, .slb_miss_realmode)
+        mtctr   r10
+        bctr
+#endif
+        STD_EXCEPTION_PSERIES(0x400, instruction_access)
+        . = 0x480
+        .globl instruction_access_slb_pSeries
+instruction_access_slb_pSeries:
+        HMT_MEDIUM
+        mtspr   SPRN_SPRG1,r13
+        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        std     r3,PACA_EXSLB+EX_R3(r13)
+        mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
+        std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
+        mfcr    r9
+#ifdef __DISABLED__
+        /* Keep that around for when we re-implement dynamic VSIDs */
+        cmpdi   r3,0
+        bge     slb_miss_user_pseries
+#endif /* __DISABLED__ */
+        std     r10,PACA_EXSLB+EX_R10(r13)
+        std     r11,PACA_EXSLB+EX_R11(r13)
+        std     r12,PACA_EXSLB+EX_R12(r13)
+        mfspr   r10,SPRN_SPRG1
+        std     r10,PACA_EXSLB+EX_R13(r13)
+        mfspr   r12,SPRN_SRR1           /* and SRR1 */
+#ifndef CONFIG_RELOCATABLE
+        b       .slb_miss_realmode
+#else
+        mfctr   r11
+        ld      r10,PACAKBASE(r13)
+        LOAD_HANDLER(r10, .slb_miss_realmode)
+        mtctr   r10
+        bctr
+#endif
+        MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
+        STD_EXCEPTION_PSERIES(0x600, alignment)
+        STD_EXCEPTION_PSERIES(0x700, program_check)
+        STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
+        MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
+        STD_EXCEPTION_PSERIES(0xa00, trap_0a)
+        STD_EXCEPTION_PSERIES(0xb00, trap_0b)
+        . = 0xc00
+        .globl  system_call_pSeries
+system_call_pSeries:
+        HMT_MEDIUM
+BEGIN_FTR_SECTION
+        cmpdi   r0,0x1ebe
+        beq-    1f
+END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
+        mr      r9,r13
+        mfspr   r13,SPRN_SPRG3
+        mfspr   r11,SPRN_SRR0
+        ld      r12,PACAKBASE(r13)
+        ld      r10,PACAKMSR(r13)
+        LOAD_HANDLER(r12, system_call_entry)
+        mtspr   SPRN_SRR0,r12
+        mfspr   r12,SPRN_SRR1
+        mtspr   SPRN_SRR1,r10
+        rfid
+        b       .       /* prevent speculative execution */
+/* Fast LE/BE switch system call */
+1:      mfspr   r12,SPRN_SRR1
+        xori    r12,r12,MSR_LE
+        mtspr   SPRN_SRR1,r12
+        rfid            /* return to userspace */
+        b       .
+        STD_EXCEPTION_PSERIES(0xd00, single_step)
+        STD_EXCEPTION_PSERIES(0xe00, trap_0e)
+        /* We need to deal with the Altivec unavailable exception
+         * here which is at 0xf20, thus in the middle of the
+         * prolog code of the PerformanceMonitor one. A little
+         * trickery is thus necessary
+         */
+        . = 0xf00
+        b       performance_monitor_pSeries
+        . = 0xf20
+        b       altivec_unavailable_pSeries
+        . = 0xf40
+        b       vsx_unavailable_pSeries
+#ifdef CONFIG_CBE_RAS
+        HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
+#endif /* CONFIG_CBE_RAS */
+        STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
+#ifdef CONFIG_CBE_RAS
+        HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
+#endif /* CONFIG_CBE_RAS */
+        STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
+#ifdef CONFIG_CBE_RAS
+        HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
+#endif /* CONFIG_CBE_RAS */
+        . = 0x3000
+/*** pSeries interrupt support ***/
+        /* moved from 0xf00 */
+        STD_EXCEPTION_PSERIES(., performance_monitor)
+        STD_EXCEPTION_PSERIES(., altivec_unavailable)
+        STD_EXCEPTION_PSERIES(., vsx_unavailable)
+/*
+ * An interrupt came in while soft-disabled; clear EE in SRR1,
+ * clear paca->hard_enabled and return.
+ */
+masked_interrupt:
+        stb     r10,PACAHARDIRQEN(r13)
+        mtcrf   0x80,r9
+        ld      r9,PACA_EXGEN+EX_R9(r13)
+        mfspr   r10,SPRN_SRR1
+        rldicl  r10,r10,48,1            /* clear MSR_EE */
+        rotldi  r10,r10,16
+        mtspr   SPRN_SRR1,r10
+        ld      r10,PACA_EXGEN+EX_R10(r13)
+        mfspr   r13,SPRN_SPRG1
+        rfid
+        b       .
+        .align  7
+do_stab_bolted_pSeries:
+        mtcrf   0x80,r12
+        mfspr   r12,SPRN_SPRG2
+        EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
+#ifdef CONFIG_PPC_PSERIES
+/*
+ * Vectors for the FWNMI option.  Share common code.
+ */
+        .globl system_reset_fwnmi
+      .align 7
+system_reset_fwnmi:
+        HMT_MEDIUM
+        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
+        .globl machine_check_fwnmi
+      .align 7
+machine_check_fwnmi:
+        HMT_MEDIUM
+        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
+#endif /* CONFIG_PPC_PSERIES */
+#ifdef __DISABLED__
+/*
+ * This is used for when the SLB miss handler has to go virtual,
+ * which doesn't happen for now anymore but will once we re-implement
+ * dynamic VSIDs for shared page tables
+ */
+slb_miss_user_pseries:
+        std     r10,PACA_EXGEN+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R11(r13)
+        std     r12,PACA_EXGEN+EX_R12(r13)
+        mfspr   r10,SPRG1
+        ld      r11,PACA_EXSLB+EX_R9(r13)
+        ld      r12,PACA_EXSLB+EX_R3(r13)
+        std     r10,PACA_EXGEN+EX_R13(r13)
+        std     r11,PACA_EXGEN+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R3(r13)
+        clrrdi  r12,r13,32
+        mfmsr   r10
+        mfspr   r11,SRR0                        /* save SRR0 */
+        ori     r12,r12,slb_miss_user_common@l  /* virt addr of handler */
+        ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
+        mtspr   SRR0,r12
+        mfspr   r12,SRR1                        /* and SRR1 */
+        mtspr   SRR1,r10
+        rfid
+        b       .                               /* prevent spec. execution */
+#endif /* __DISABLED__ */
+        .align  7
+        .globl  __end_interrupts
+__end_interrupts:
+/*
+ * Code from here down to __end_handlers is invoked from the
+ * exception prologs above.  Because the prologs assemble the
+ * addresses of these handlers using the LOAD_HANDLER macro,
+ * which uses an addi instruction, these handlers must be in
+ * the first 32k of the kernel image.
+ */
+/*** Common interrupt handlers ***/
+        STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
+        /*
+         * Machine check is different because we use a different
+         * save area: PACA_EXMC instead of PACA_EXGEN.
+         */
+        .align  7
+        .globl machine_check_common
+machine_check_common:
+        EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
+        FINISH_NAP
+        DISABLE_INTS
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .machine_check_exception
+        b       .ret_from_except
+        STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
+        STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
+        STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
+        STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
+        STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
+        STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
+        STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
+#ifdef CONFIG_ALTIVEC
+        STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
+#else
+        STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
+#endif
+#ifdef CONFIG_CBE_RAS
+        STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
+        STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
+        STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
+#endif /* CONFIG_CBE_RAS */
+        .align  7
+system_call_entry:
+        b       system_call_common
+/*
+ * Here we have detected that the kernel stack pointer is bad.
+ * R9 contains the saved CR, r13 points to the paca,
+ * r10 contains the (bad) kernel stack pointer,
+ * r11 and r12 contain the saved SRR0 and SRR1.
+ * We switch to using an emergency stack, save the registers there,
+ * and call kernel_bad_stack(), which panics.
+ */
+bad_stack:
+        ld      r1,PACAEMERGSP(r13)
+        subi    r1,r1,64+INT_FRAME_SIZE
+        std     r9,_CCR(r1)
+        std     r10,GPR1(r1)
+        std     r11,_NIP(r1)
+        std     r12,_MSR(r1)
+        mfspr   r11,SPRN_DAR
+        mfspr   r12,SPRN_DSISR
+        std     r11,_DAR(r1)
+        std     r12,_DSISR(r1)
+        mflr    r10
+        mfctr   r11
+        mfxer   r12
+        std     r10,_LINK(r1)
+        std     r11,_CTR(r1)
+        std     r12,_XER(r1)
+        SAVE_GPR(0,r1)
+        SAVE_GPR(2,r1)
+        SAVE_4GPRS(3,r1)
+        SAVE_2GPRS(7,r1)
+        SAVE_10GPRS(12,r1)
+        SAVE_10GPRS(22,r1)
+        lhz     r12,PACA_TRAP_SAVE(r13)
+        std     r12,_TRAP(r1)
+        addi    r11,r1,INT_FRAME_SIZE
+        std     r11,0(r1)
+        li      r12,0
+        std     r12,0(r11)
+        ld      r2,PACATOC(r13)
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .kernel_bad_stack
+        b       1b
+/*
+ * Here r13 points to the paca, r9 contains the saved CR,
+ * SRR0 and SRR1 are saved in r11 and r12,
+ * r9 - r13 are saved in paca->exgen.
+ */
+        .align  7
+        .globl data_access_common
+data_access_common:
+        mfspr   r10,SPRN_DAR
+        std     r10,PACA_EXGEN+EX_DAR(r13)
+        mfspr   r10,SPRN_DSISR
+        stw     r10,PACA_EXGEN+EX_DSISR(r13)
+        EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
+        ld      r3,PACA_EXGEN+EX_DAR(r13)
+        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
+        li      r5,0x300
+        b       .do_hash_page           /* Try to handle as hpte fault */
+        .align  7
+        .globl instruction_access_common
+instruction_access_common:
+        EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
+        ld      r3,_NIP(r1)
+        andis.  r4,r12,0x5820
+        li      r5,0x400
+        b       .do_hash_page           /* Try to handle as hpte fault */
+/*
+ * Here is the common SLB miss user that is used when going to virtual
+ * mode for SLB misses, that is currently not used
+ */
+#ifdef __DISABLED__
+        .align  7
+        .globl  slb_miss_user_common
+slb_miss_user_common:
+        mflr    r10
+        std     r3,PACA_EXGEN+EX_DAR(r13)
+        stw     r9,PACA_EXGEN+EX_CCR(r13)
+        std     r10,PACA_EXGEN+EX_LR(r13)
+        std     r11,PACA_EXGEN+EX_SRR0(r13)
+        bl      .slb_allocate_user
+        ld      r10,PACA_EXGEN+EX_LR(r13)
+        ld      r3,PACA_EXGEN+EX_R3(r13)
+        lwz     r9,PACA_EXGEN+EX_CCR(r13)
+        ld      r11,PACA_EXGEN+EX_SRR0(r13)
+        mtlr    r10
+        beq-    slb_miss_fault
+        andi.   r10,r12,MSR_RI          /* check for unrecoverable exception */
+        beq-    unrecov_user_slb
+        mfmsr   r10
+.machine push
+.machine "power4"
+        mtcrf   0x80,r9
+.machine pop
+        clrrdi  r10,r10,2               /* clear RI before setting SRR0/1 */
+        mtmsrd  r10,1
+        mtspr   SRR0,r11
+        mtspr   SRR1,r12
+        ld      r9,PACA_EXGEN+EX_R9(r13)
+        ld      r10,PACA_EXGEN+EX_R10(r13)
+        ld      r11,PACA_EXGEN+EX_R11(r13)
+        ld      r12,PACA_EXGEN+EX_R12(r13)
+        ld      r13,PACA_EXGEN+EX_R13(r13)
+        rfid
+        b       .
+slb_miss_fault:
+        EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
+        ld      r4,PACA_EXGEN+EX_DAR(r13)
+        li      r5,0
+        std     r4,_DAR(r1)
+        std     r5,_DSISR(r1)
+        b       handle_page_fault
+unrecov_user_slb:
+        EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
+        DISABLE_INTS
+        bl      .save_nvgprs
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .unrecoverable_exception
+        b       1b
+#endif /* __DISABLED__ */
+/*
+ * r13 points to the PACA, r9 contains the saved CR,
+ * r12 contain the saved SRR1, SRR0 is still ready for return
+ * r3 has the faulting address
+ * r9 - r13 are saved in paca->exslb.
+ * r3 is saved in paca->slb_r3
+ * We assume we aren't going to take any exceptions during this procedure.
+ */
+_GLOBAL(slb_miss_realmode)
+        mflr    r10
+#ifdef CONFIG_RELOCATABLE
+        mtctr   r11
+#endif
+        stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
+        std     r10,PACA_EXSLB+EX_LR(r13)       /* save LR */
+        bl      .slb_allocate_realmode
+        /* All done -- return from exception. */
+        ld      r10,PACA_EXSLB+EX_LR(r13)
+        ld      r3,PACA_EXSLB+EX_R3(r13)
+        lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
+#ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
+        ld      r11,PACALPPACAPTR(r13)
+        ld      r11,LPPACASRR0(r11)             /* get SRR0 value */
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+#endif /* CONFIG_PPC_ISERIES */
+        mtlr    r10
+        andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
+        beq-    2f
+.machine        push
+.machine        "power4"
+        mtcrf   0x80,r9
+        mtcrf   0x01,r9         /* slb_allocate uses cr0 and cr7 */
+.machine        pop
+#ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
+        mtspr   SPRN_SRR0,r11
+        mtspr   SPRN_SRR1,r12
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+#endif /* CONFIG_PPC_ISERIES */
+        ld      r9,PACA_EXSLB+EX_R9(r13)
+        ld      r10,PACA_EXSLB+EX_R10(r13)
+        ld      r11,PACA_EXSLB+EX_R11(r13)
+        ld      r12,PACA_EXSLB+EX_R12(r13)
+        ld      r13,PACA_EXSLB+EX_R13(r13)
+        rfid
+        b       .       /* prevent speculative execution */
+2:
+#ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
+        b       unrecov_slb
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+#endif /* CONFIG_PPC_ISERIES */
+        mfspr   r11,SPRN_SRR0
+        ld      r10,PACAKBASE(r13)
+        LOAD_HANDLER(r10,unrecov_slb)
+        mtspr   SPRN_SRR0,r10
+        ld      r10,PACAKMSR(r13)
+        mtspr   SPRN_SRR1,r10
+        rfid
+        b       .
+unrecov_slb:
+        EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
+        DISABLE_INTS
+        bl      .save_nvgprs
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .unrecoverable_exception
+        b       1b
+        .align  7
+        .globl hardware_interrupt_common
+        .globl hardware_interrupt_entry
+hardware_interrupt_common:
+        EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
+        FINISH_NAP
+hardware_interrupt_entry:
+        DISABLE_INTS
+BEGIN_FTR_SECTION
+        bl      .ppc64_runlatch_on
+END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .do_IRQ
+        b       .ret_from_except_lite
+#ifdef CONFIG_PPC_970_NAP
+power4_fixup_nap:
+        andc    r9,r9,r10
+        std     r9,TI_LOCAL_FLAGS(r11)
+        ld      r10,_LINK(r1)           /* make idle task do the */
+        std     r10,_NIP(r1)            /* equivalent of a blr */
+        blr
+#endif
+        .align  7
+        .globl alignment_common
+alignment_common:
+        mfspr   r10,SPRN_DAR
+        std     r10,PACA_EXGEN+EX_DAR(r13)
+        mfspr   r10,SPRN_DSISR
+        stw     r10,PACA_EXGEN+EX_DSISR(r13)
+        EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
+        ld      r3,PACA_EXGEN+EX_DAR(r13)
+        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
+        std     r3,_DAR(r1)
+        std     r4,_DSISR(r1)
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ENABLE_INTS
+        bl      .alignment_exception
+        b       .ret_from_except
+        .align  7
+        .globl program_check_common
+program_check_common:
+        EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ENABLE_INTS
+        bl      .program_check_exception
+        b       .ret_from_except
+        .align  7
+        .globl fp_unavailable_common
+fp_unavailable_common:
+        EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
+        bne     1f                      /* if from user, just load it up */
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ENABLE_INTS
+        bl      .kernel_fp_unavailable_exception
+        BUG_OPCODE
+1:      bl      .load_up_fpu
+        b       fast_exception_return
+        .align  7
+        .globl altivec_unavailable_common
+altivec_unavailable_common:
+        EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
+#ifdef CONFIG_ALTIVEC
+BEGIN_FTR_SECTION
+        beq     1f
+        bl      .load_up_altivec
+        b       fast_exception_return
+1:
+END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
+#endif
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ENABLE_INTS
+        bl      .altivec_unavailable_exception
+        b       .ret_from_except
+        .align  7
+        .globl vsx_unavailable_common
+vsx_unavailable_common:
+        EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
+#ifdef CONFIG_VSX
+BEGIN_FTR_SECTION
+        bne     .load_up_vsx
+1:
+END_FTR_SECTION_IFSET(CPU_FTR_VSX)
+#endif
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ENABLE_INTS
+        bl      .vsx_unavailable_exception
+        b       .ret_from_except
+        .align  7
+        .globl  __end_handlers
+__end_handlers:
+/*
+ * Return from an exception with minimal checks.
+ * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
+ * If interrupts have been enabled, or anything has been
+ * done that might have changed the scheduling status of
+ * any task or sent any task a signal, you should use
+ * ret_from_except or ret_from_except_lite instead of this.
+ */
+fast_exc_return_irq:                    /* restores irq state too */
+        ld      r3,SOFTE(r1)
+        TRACE_AND_RESTORE_IRQ(r3);
+        ld      r12,_MSR(r1)
+        rldicl  r4,r12,49,63            /* get MSR_EE to LSB */
+        stb     r4,PACAHARDIRQEN(r13)   /* restore paca->hard_enabled */
+        b       1f
+        .globl  fast_exception_return
+fast_exception_return:
+        ld      r12,_MSR(r1)
+1:      ld      r11,_NIP(r1)
+        andi.   r3,r12,MSR_RI           /* check if RI is set */
+        beq-    unrecov_fer
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+        andi.   r3,r12,MSR_PR
+        beq     2f
+        ACCOUNT_CPU_USER_EXIT(r3, r4)
+2:
+#endif
+        ld      r3,_CCR(r1)
+        ld      r4,_LINK(r1)
+        ld      r5,_CTR(r1)
+        ld      r6,_XER(r1)
+        mtcr    r3
+        mtlr    r4
+        mtctr   r5
+        mtxer   r6
+        REST_GPR(0, r1)
+        REST_8GPRS(2, r1)
+        mfmsr   r10
+        rldicl  r10,r10,48,1            /* clear EE */
+        rldicr  r10,r10,16,61           /* clear RI (LE is 0 already) */
+        mtmsrd  r10,1
+        mtspr   SPRN_SRR1,r12
+        mtspr   SPRN_SRR0,r11
+        REST_4GPRS(10, r1)
+        ld      r1,GPR1(r1)
+        rfid
+        b       .       /* prevent speculative execution */
+unrecov_fer:
+        bl      .save_nvgprs
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .unrecoverable_exception
+        b       1b
+/*
+ * Hash table stuff
+ */
+        .align  7
+_STATIC(do_hash_page)
+        std     r3,_DAR(r1)
+        std     r4,_DSISR(r1)
+        andis.  r0,r4,0xa450            /* weird error? */
+        bne-    handle_page_fault       /* if not, try to insert a HPTE */
+BEGIN_FTR_SECTION
+        andis.  r0,r4,0x0020            /* Is it a segment table fault? */
+        bne-    do_ste_alloc            /* If so handle it */
+END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+        /*
+         * On iSeries, we soft-disable interrupts here, then
+         * hard-enable interrupts so that the hash_page code can spin on
+         * the hash_table_lock without problems on a shared processor.
+         */
+        DISABLE_INTS
+        /*
+         * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
+         * and will clobber volatile registers when irq tracing is enabled
+         * so we need to reload them. It may be possible to be smarter here
+         * and move the irq tracing elsewhere but let's keep it simple for
+         * now
+         */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        ld      r3,_DAR(r1)
+        ld      r4,_DSISR(r1)
+        ld      r5,_TRAP(r1)
+        ld      r12,_MSR(r1)
+        clrrdi  r5,r5,4
+#endif /* CONFIG_TRACE_IRQFLAGS */
+        /*
+         * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
+         * accessing a userspace segment (even from the kernel). We assume
+         * kernel addresses always have the high bit set.
+         */
+        rlwinm  r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
+        rotldi  r0,r3,15                /* Move high bit into MSR_PR posn */
+        orc     r0,r12,r0               /* MSR_PR | ~high_bit */
+        rlwimi  r4,r0,32-13,30,30       /* becomes _PAGE_USER access bit */
+        ori     r4,r4,1                 /* add _PAGE_PRESENT */
+        rlwimi  r4,r5,22+2,31-2,31-2    /* Set _PAGE_EXEC if trap is 0x400 */
+        /*
+         * r3 contains the faulting address
+         * r4 contains the required access permissions
+         * r5 contains the trap number
+         *
+         * at return r3 = 0 for success
+         */
+        bl      .hash_page              /* build HPTE if possible */
+        cmpdi   r3,0                    /* see if hash_page succeeded */
+BEGIN_FW_FTR_SECTION
+        /*
+         * If we had interrupts soft-enabled at the point where the
+         * DSI/ISI occurred, and an interrupt came in during hash_page,
+         * handle it now.
+         * We jump to ret_from_except_lite rather than fast_exception_return
+         * because ret_from_except_lite will check for and handle pending
+         * interrupts if necessary.
+         */
+        beq     13f
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+BEGIN_FW_FTR_SECTION
+        /*
+         * Here we have interrupts hard-disabled, so it is sufficient
+         * to restore paca->{soft,hard}_enable and get out.
+         */
+        beq     fast_exc_return_irq     /* Return from exception on success */
+END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
+        /* For a hash failure, we don't bother re-enabling interrupts */
+        ble-    12f
+        /*
+         * hash_page couldn't handle it, set soft interrupt enable back
+         * to what it was before the trap.  Note that .raw_local_irq_restore
+         * handles any interrupts pending at this point.
+         */
+        ld      r3,SOFTE(r1)
+        TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
+        bl      .raw_local_irq_restore
+        b       11f
+/* Here we have a page fault that hash_page can't handle. */
+handle_page_fault:
+        ENABLE_INTS
+11:     ld      r4,_DAR(r1)
+        ld      r5,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .do_page_fault
+        cmpdi   r3,0
+        beq+    13f
+        bl      .save_nvgprs
+        mr      r5,r3
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        lwz     r4,_DAR(r1)
+        bl      .bad_page_fault
+        b       .ret_from_except
+13:     b       .ret_from_except_lite
+/* We have a page fault that hash_page could handle but HV refused
+ * the PTE insertion
+ */
+12:     bl      .save_nvgprs
+        mr      r5,r3
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ld      r4,_DAR(r1)
+        bl      .low_hash_fault
+        b       .ret_from_except
+        /* here we have a segment miss */
+do_ste_alloc:
+        bl      .ste_allocate           /* try to insert stab entry */
+        cmpdi   r3,0
+        bne-    handle_page_fault
+        b       fast_exception_return
+/*
+ * r13 points to the PACA, r9 contains the saved CR,
+ * r11 and r12 contain the saved SRR0 and SRR1.
+ * r9 - r13 are saved in paca->exslb.
+ * We assume we aren't going to take any exceptions during this procedure.
+ * We assume (DAR >> 60) == 0xc.
+ */
+        .align  7
+_GLOBAL(do_stab_bolted)
+        stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
+        std     r11,PACA_EXSLB+EX_SRR0(r13)     /* save SRR0 in exc. frame */
+        /* Hash to the primary group */
+        ld      r10,PACASTABVIRT(r13)
+        mfspr   r11,SPRN_DAR
+        srdi    r11,r11,28
+        rldimi  r10,r11,7,52    /* r10 = first ste of the group */
+        /* Calculate VSID */
+        /* This is a kernel address, so protovsid = ESID */
+        ASM_VSID_SCRAMBLE(r11, r9, 256M)
+        rldic   r9,r11,12,16    /* r9 = vsid << 12 */
+        /* Search the primary group for a free entry */
+1:      ld      r11,0(r10)      /* Test valid bit of the current ste    */
+        andi.   r11,r11,0x80
+        beq     2f
+        addi    r10,r10,16
+        andi.   r11,r10,0x70
+        bne     1b
+        /* Stick for only searching the primary group for now.          */
+        /* At least for now, we use a very simple random castout scheme */
+        /* Use the TB as a random number ;  OR in 1 to avoid entry 0    */
+        mftb    r11
+        rldic   r11,r11,4,57    /* r11 = (r11 << 4) & 0x70 */
+        ori     r11,r11,0x10
+        /* r10 currently points to an ste one past the group of interest */
+        /* make it point to the randomly selected entry                 */
+        subi    r10,r10,128
+        or      r10,r10,r11     /* r10 is the entry to invalidate       */
+        isync                   /* mark the entry invalid               */
+        ld      r11,0(r10)
+        rldicl  r11,r11,56,1    /* clear the valid bit */
+        rotldi  r11,r11,8
+        std     r11,0(r10)
+        sync
+        clrrdi  r11,r11,28      /* Get the esid part of the ste         */
+        slbie   r11
+2:      std     r9,8(r10)       /* Store the vsid part of the ste       */
+        eieio
+        mfspr   r11,SPRN_DAR            /* Get the new esid                     */
+        clrrdi  r11,r11,28      /* Permits a full 32b of ESID           */
+        ori     r11,r11,0x90    /* Turn on valid and kp                 */
+        std     r11,0(r10)      /* Put new entry back into the stab     */
+        sync
+        /* All done -- return from exception. */
+        lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
+        ld      r11,PACA_EXSLB+EX_SRR0(r13)     /* get saved SRR0 */
+        andi.   r10,r12,MSR_RI
+        beq-    unrecov_slb
+        mtcrf   0x80,r9                 /* restore CR */
+        mfmsr   r10
+        clrrdi  r10,r10,2
+        mtmsrd  r10,1
+        mtspr   SPRN_SRR0,r11
+        mtspr   SPRN_SRR1,r12
+        ld      r9,PACA_EXSLB+EX_R9(r13)
+        ld      r10,PACA_EXSLB+EX_R10(r13)
+        ld      r11,PACA_EXSLB+EX_R11(r13)
+        ld      r12,PACA_EXSLB+EX_R12(r13)
+        ld      r13,PACA_EXSLB+EX_R13(r13)
+        rfid
+        b       .       /* prevent speculative execution */
+/*
+ * Space for CPU0's segment table.
+ *
+ * On iSeries, the hypervisor must fill in at least one entry before
+ * we get control (with relocate on).  The address is given to the hv
+ * as a page number (see xLparMap below), so this must be at a
+ * fixed address (the linker can't compute (u64)&initial_stab >>
+ * PAGE_SHIFT).
+ */
+        . = STAB0_OFFSET        /* 0x6000 */
+        .globl initial_stab
+initial_stab:
+        .space  4096
+#ifdef CONFIG_PPC_PSERIES
+/*
+ * Data area reserved for FWNMI option.
+ * This address (0x7000) is fixed by the RPA.
+ */
+        .= 0x7000
+        .globl fwnmi_data_area
+fwnmi_data_area:
+#endif /* CONFIG_PPC_PSERIES */
+        /* iSeries does not use the FWNMI stuff, so it is safe to put
+         * this here, even if we later allow kernels that will boot on
+         * both pSeries and iSeries */
+#ifdef CONFIG_PPC_ISERIES
+        . = LPARMAP_PHYS
+        .globl xLparMap
+xLparMap:
+        .quad   HvEsidsToMap            /* xNumberEsids */
+        .quad   HvRangesToMap           /* xNumberRanges */
+        .quad   STAB0_PAGE              /* xSegmentTableOffs */
+        .zero   40                      /* xRsvd */
+        /* xEsids (HvEsidsToMap entries of 2 quads) */
+        .quad   PAGE_OFFSET_ESID        /* xKernelEsid */
+        .quad   PAGE_OFFSET_VSID        /* xKernelVsid */
+        .quad   VMALLOC_START_ESID      /* xKernelEsid */
+        .quad   VMALLOC_START_VSID      /* xKernelVsid */
+        /* xRanges (HvRangesToMap entries of 3 quads) */
+        .quad   HvPagesToMap            /* xPages */
+        .quad   0                       /* xOffset */
+        .quad   PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
+#endif /* CONFIG_PPC_ISERIES */
+#ifdef CONFIG_PPC_PSERIES
+        . = 0x8000
+#endif /* CONFIG_PPC_PSERIES */
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index 2d182f119d1d..1b12696cca06 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -23,25 +23,14 @@
 #include <asm/code-patching.h>
 #include <asm/ftrace.h>
-#ifdef CONFIG_PPC32
-# define GET_ADDR(addr) addr
-#else
-/* PowerPC64's functions are data that points to the functions */
-# define GET_ADDR(addr) (*(unsigned long *)addr)
-#endif
 #ifdef CONFIG_DYNAMIC_FTRACE
-static unsigned int ftrace_nop_replace(void)
-{
-        return PPC_INST_NOP;
-}
 static unsigned int
 ftrace_call_replace(unsigned long ip, unsigned long addr, int link)
 {
        unsigned int op;
-        addr = GET_ADDR(addr);
+        addr = ppc_function_entry((void *)addr);
        /* if (link) set op to 'bl' else 'b' */
        op = create_branch((unsigned int *)ip, addr, link ? 1 : 0);
@@ -49,14 +38,6 @@ ftrace_call_replace(unsigned long ip, unsigned long addr, int link)
        return op;
 }
-#ifdef CONFIG_PPC64
-# define _ASM_ALIGN     " .align 3 "
-# define _ASM_PTR       " .llong "
-#else
-# define _ASM_ALIGN     " .align 2 "
-# define _ASM_PTR       " .long "
-#endif
 static int
 ftrace_modify_code(unsigned long ip, unsigned int old, unsigned int new)
 {
@@ -197,7 +178,7 @@ __ftrace_make_nop(struct module *mod,
        ptr = ((unsigned long)jmp[0] << 32) + jmp[1];
        /* This should match what was called */
-        if (ptr != GET_ADDR(addr)) {
+        if (ptr != ppc_function_entry((void *)addr)) {
                printk(KERN_ERR "addr does not match %lx\n", ptr);
                return -EINVAL;
        }
@@ -328,7 +309,7 @@ int ftrace_make_nop(struct module *mod,
        if (test_24bit_addr(ip, addr)) {
                /* within range */
                old = ftrace_call_replace(ip, addr, 1);
-                new = ftrace_nop_replace();
+                new = PPC_INST_NOP;
                return ftrace_modify_code(ip, old, new);
        }
@@ -466,7 +447,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
         */
        if (test_24bit_addr(ip, addr)) {
                /* within range */
-                old = ftrace_nop_replace();
+                old = PPC_INST_NOP;
                new = ftrace_call_replace(ip, addr, 1);
                return ftrace_modify_code(ip, old, new);
        }
@@ -570,7 +551,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
                return_hooker = (unsigned long)&mod_return_to_handler;
 #endif
-        return_hooker = GET_ADDR(return_hooker);
+        return_hooker = ppc_function_entry((void *)return_hooker);
        /*
         * Protect against fault, even if it shouldn't
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index c01467f952d3..48469463f89e 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -733,9 +733,11 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
 AltiVecUnavailable:
        EXCEPTION_PROLOG
 #ifdef CONFIG_ALTIVEC
-        bne     load_up_altivec         /* if from user, just load it up */
+        beq     1f
+        bl      load_up_altivec         /* if from user, just load it up */
+        b       fast_exception_return
 #endif /* CONFIG_ALTIVEC */
-        addi    r3,r1,STACK_FRAME_OVERHEAD
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
        EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
 PerformanceMonitor:
@@ -743,101 +745,6 @@ PerformanceMonitor:
        addi    r3,r1,STACK_FRAME_OVERHEAD
        EXC_XFER_STD(0xf00, performance_monitor_exception)
-#ifdef CONFIG_ALTIVEC
-/* Note that the AltiVec support is closely modeled after the FP
- * support.  Changes to one are likely to be applicable to the
- * other!  */
-load_up_altivec:
-/*
- * Disable AltiVec for the task which had AltiVec previously,
- * and save its AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- * On SMP we know the AltiVec units are free, since we give it up every
- * switch.  -- Kumar
- */
-        mfmsr   r5
-        oris    r5,r5,MSR_VEC@h
-        MTMSRD(r5)                      /* enable use of AltiVec now */
-        isync
-/*
- * For SMP, we don't do lazy AltiVec switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another.  Instead we call giveup_altivec in switch_to.
- */
-#ifndef CONFIG_SMP
-        tophys(r6,0)
-        addis   r3,r6,last_task_used_altivec@ha
-        lwz     r4,last_task_used_altivec@l(r3)
-        cmpwi   0,r4,0
-        beq     1f
-        add     r4,r4,r6
-        addi    r4,r4,THREAD    /* want THREAD of last_task_used_altivec */
-        SAVE_32VRS(0,r10,r4)
-        mfvscr  vr0
-        li      r10,THREAD_VSCR
-        stvx    vr0,r10,r4
-        lwz     r5,PT_REGS(r4)
-        add     r5,r5,r6
-        lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-        lis     r10,MSR_VEC@h
-        andc    r4,r4,r10       /* disable altivec for previous task */
-        stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
-        /* enable use of AltiVec after return */
-        oris    r9,r9,MSR_VEC@h
-        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
-        li      r4,1
-        li      r10,THREAD_VSCR
-        stw     r4,THREAD_USED_VR(r5)
-        lvx     vr0,r10,r5
-        mtvscr  vr0
-        REST_32VRS(0,r10,r5)
-#ifndef CONFIG_SMP
-        subi    r4,r5,THREAD
-        sub     r4,r4,r6
-        stw     r4,last_task_used_altivec@l(r3)
-#endif /* CONFIG_SMP */
-        /* restore registers and return */
-        /* we haven't used ctr or xer or lr */
-        b       fast_exception_return
-/*
- * giveup_altivec(tsk)
- * Disable AltiVec for the task given as the argument,
- * and save the AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- */
-        .globl  giveup_altivec
-giveup_altivec:
-        mfmsr   r5
-        oris    r5,r5,MSR_VEC@h
-        SYNC
-        MTMSRD(r5)                      /* enable use of AltiVec now */
-        isync
-        cmpwi   0,r3,0
-        beqlr-                          /* if no previous owner, done */
-        addi    r3,r3,THREAD            /* want THREAD of task */
-        lwz     r5,PT_REGS(r3)
-        cmpwi   0,r5,0
-        SAVE_32VRS(0, r4, r3)
-        mfvscr  vr0
-        li      r4,THREAD_VSCR
-        stvx    vr0,r4,r3
-        beq     1f
-        lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-        lis     r3,MSR_VEC@h
-        andc    r4,r4,r3                /* disable AltiVec for previous task */
-        stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
-        li      r5,0
-        lis     r4,last_task_used_altivec@ha
-        stw     r5,last_task_used_altivec@l(r4)
-#endif /* CONFIG_SMP */
-        blr
-#endif /* CONFIG_ALTIVEC */
 /*
 * This code is jumped to from the startup code to copy
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 50ef505b8fb6..012505ebd9f9 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -12,8 +12,9 @@
 *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
 *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
 *
- *  This file contains the low-level support and setup for the
+ *  This file contains the entry point for the 64-bit kernel along
- *  PowerPC-64 platform, including trap and interrupt dispatch.
+ *  with some early initialization code common to all 64-bit powerpc
+ *  variants.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
@@ -38,36 +39,25 @@
 #include <asm/exception.h>
 #include <asm/irqflags.h>
-/*
+/* The physical memory is layed out such that the secondary processor
- * We layout physical memory as follows:
+ * spin code sits at 0x0000...0x00ff. On server, the vectors follow
- * 0x0000 - 0x00ff : Secondary processor spin code
+ * using the layout described in exceptions-64s.S
- * 0x0100 - 0x2fff : pSeries Interrupt prologs
- * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
- * 0x6000 - 0x6fff : Initial (CPU0) segment table
- * 0x7000 - 0x7fff : FWNMI data area
- * 0x8000 -        : Early init and support code
- */
-/*
- *   SPRG Usage
- *
- *   Register   Definition
- *
- *   SPRG0      reserved for hypervisor
- *   SPRG1      temp - used to save gpr
- *   SPRG2      temp - used to save gpr
- *   SPRG3      virt addr of paca
 */
 /*
 * Entering into this code we make the following assumptions:
- *  For pSeries:
+ *
+ *  For pSeries or server processors:
 *   1. The MMU is off & open firmware is running in real mode.
 *   2. The kernel is entered at __start
 *
 *  For iSeries:
 *   1. The MMU is on (as it always is for iSeries)
 *   2. The kernel is entered at system_reset_iSeries
+ *
+ *  For Book3E processors:
+ *   1. The MMU is on running in AS0 in a state defined in ePAPR
+ *   2. The kernel is entered at __start
 */
        .text
@@ -166,1065 +156,14 @@ exception_marker:
        .text
 /*
- * This is the start of the interrupt handlers for pSeries
+ * On server, we include the exception vectors code here as it
- * This code runs with relocation off.
+ * relies on absolute addressing which is only possible within
- * Code from here to __end_interrupts gets copied down to real
+ * this compilation unit
- * address 0x100 when we are running a relocatable kernel.
- * Therefore any relative branches in this section must only
- * branch to labels in this section.
- */
-        . = 0x100
-        .globl __start_interrupts
-__start_interrupts:
-        STD_EXCEPTION_PSERIES(0x100, system_reset)
-        . = 0x200
-_machine_check_pSeries:
-        HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
-        EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
-        . = 0x300
-        .globl data_access_pSeries
-data_access_pSeries:
-        HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
-BEGIN_FTR_SECTION
-        mtspr   SPRN_SPRG2,r12
-        mfspr   r13,SPRN_DAR
-        mfspr   r12,SPRN_DSISR
-        srdi    r13,r13,60
-        rlwimi  r13,r12,16,0x20
-        mfcr    r12
-        cmpwi   r13,0x2c
-        beq     do_stab_bolted_pSeries
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
-        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
-        . = 0x380
-        .globl data_access_slb_pSeries
-data_access_slb_pSeries:
-        HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
-        std     r3,PACA_EXSLB+EX_R3(r13)
-        mfspr   r3,SPRN_DAR
-        std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
-        mfcr    r9
-#ifdef __DISABLED__
-        /* Keep that around for when we re-implement dynamic VSIDs */
-        cmpdi   r3,0
-        bge     slb_miss_user_pseries
-#endif /* __DISABLED__ */
-        std     r10,PACA_EXSLB+EX_R10(r13)
-        std     r11,PACA_EXSLB+EX_R11(r13)
-        std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
-        std     r10,PACA_EXSLB+EX_R13(r13)
-        mfspr   r12,SPRN_SRR1           /* and SRR1 */
-#ifndef CONFIG_RELOCATABLE
-        b       .slb_miss_realmode
-#else
-        /*
-         * We can't just use a direct branch to .slb_miss_realmode
-         * because the distance from here to there depends on where
-         * the kernel ends up being put.
-         */
-        mfctr   r11
-        ld      r10,PACAKBASE(r13)
-        LOAD_HANDLER(r10, .slb_miss_realmode)
-        mtctr   r10
-        bctr
-#endif
-        STD_EXCEPTION_PSERIES(0x400, instruction_access)
-        . = 0x480
-        .globl instruction_access_slb_pSeries
-instruction_access_slb_pSeries:
-        HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
-        std     r3,PACA_EXSLB+EX_R3(r13)
-        mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
-        std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
-        mfcr    r9
-#ifdef __DISABLED__
-        /* Keep that around for when we re-implement dynamic VSIDs */
-        cmpdi   r3,0
-        bge     slb_miss_user_pseries
-#endif /* __DISABLED__ */
-        std     r10,PACA_EXSLB+EX_R10(r13)
-        std     r11,PACA_EXSLB+EX_R11(r13)
-        std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
-        std     r10,PACA_EXSLB+EX_R13(r13)
-        mfspr   r12,SPRN_SRR1           /* and SRR1 */
-#ifndef CONFIG_RELOCATABLE
-        b       .slb_miss_realmode
-#else
-        mfctr   r11
-        ld      r10,PACAKBASE(r13)
-        LOAD_HANDLER(r10, .slb_miss_realmode)
-        mtctr   r10
-        bctr
-#endif
-        MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
-        STD_EXCEPTION_PSERIES(0x600, alignment)
-        STD_EXCEPTION_PSERIES(0x700, program_check)
-        STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
-        MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
-        STD_EXCEPTION_PSERIES(0xa00, trap_0a)
-        STD_EXCEPTION_PSERIES(0xb00, trap_0b)
-        . = 0xc00
-        .globl  system_call_pSeries
-system_call_pSeries:
-        HMT_MEDIUM
-BEGIN_FTR_SECTION
-        cmpdi   r0,0x1ebe
-        beq-    1f
-END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
-        mr      r9,r13
-        mfspr   r13,SPRN_SPRG3
-        mfspr   r11,SPRN_SRR0
-        ld      r12,PACAKBASE(r13)
-        ld      r10,PACAKMSR(r13)
-        LOAD_HANDLER(r12, system_call_entry)
-        mtspr   SPRN_SRR0,r12
-        mfspr   r12,SPRN_SRR1
-        mtspr   SPRN_SRR1,r10
-        rfid
-        b       .       /* prevent speculative execution */
-/* Fast LE/BE switch system call */
-1:      mfspr   r12,SPRN_SRR1
-        xori    r12,r12,MSR_LE
-        mtspr   SPRN_SRR1,r12
-        rfid            /* return to userspace */
-        b       .
-        STD_EXCEPTION_PSERIES(0xd00, single_step)
-        STD_EXCEPTION_PSERIES(0xe00, trap_0e)
-        /* We need to deal with the Altivec unavailable exception
-         * here which is at 0xf20, thus in the middle of the
-         * prolog code of the PerformanceMonitor one. A little
-         * trickery is thus necessary
-         */
-        . = 0xf00
-        b       performance_monitor_pSeries
-        . = 0xf20
-        b       altivec_unavailable_pSeries
-        . = 0xf40
-        b       vsx_unavailable_pSeries
-#ifdef CONFIG_CBE_RAS
-        HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
-#endif /* CONFIG_CBE_RAS */
-        STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
-#ifdef CONFIG_CBE_RAS
-        HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
-#endif /* CONFIG_CBE_RAS */
-        STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
-#ifdef CONFIG_CBE_RAS
-        HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
-#endif /* CONFIG_CBE_RAS */
-        . = 0x3000
-/*** pSeries interrupt support ***/
-        /* moved from 0xf00 */
-        STD_EXCEPTION_PSERIES(., performance_monitor)
-        STD_EXCEPTION_PSERIES(., altivec_unavailable)
-        STD_EXCEPTION_PSERIES(., vsx_unavailable)
-/*
- * An interrupt came in while soft-disabled; clear EE in SRR1,
- * clear paca->hard_enabled and return.
- */
-masked_interrupt:
-        stb     r10,PACAHARDIRQEN(r13)
-        mtcrf   0x80,r9
-        ld      r9,PACA_EXGEN+EX_R9(r13)
-        mfspr   r10,SPRN_SRR1
-        rldicl  r10,r10,48,1            /* clear MSR_EE */
-        rotldi  r10,r10,16
-        mtspr   SPRN_SRR1,r10
-        ld      r10,PACA_EXGEN+EX_R10(r13)
-        mfspr   r13,SPRN_SPRG1
-        rfid
-        b       .
-        .align  7
-do_stab_bolted_pSeries:
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-        EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
-#ifdef CONFIG_PPC_PSERIES
-/*
- * Vectors for the FWNMI option.  Share common code.
- */
-        .globl system_reset_fwnmi
-      .align 7
-system_reset_fwnmi:
-        HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
-        EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
-        .globl machine_check_fwnmi
-      .align 7
-machine_check_fwnmi:
-        HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
-        EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
-#endif /* CONFIG_PPC_PSERIES */
-#ifdef __DISABLED__
-/*
- * This is used for when the SLB miss handler has to go virtual,
- * which doesn't happen for now anymore but will once we re-implement
- * dynamic VSIDs for shared page tables
- */
-slb_miss_user_pseries:
-        std     r10,PACA_EXGEN+EX_R10(r13)
-        std     r11,PACA_EXGEN+EX_R11(r13)
-        std     r12,PACA_EXGEN+EX_R12(r13)
-        mfspr   r10,SPRG1
-        ld      r11,PACA_EXSLB+EX_R9(r13)
-        ld      r12,PACA_EXSLB+EX_R3(r13)
-        std     r10,PACA_EXGEN+EX_R13(r13)
-        std     r11,PACA_EXGEN+EX_R9(r13)
-        std     r12,PACA_EXGEN+EX_R3(r13)
-        clrrdi  r12,r13,32
-        mfmsr   r10
-        mfspr   r11,SRR0                        /* save SRR0 */
-        ori     r12,r12,slb_miss_user_common@l  /* virt addr of handler */
-        ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
-        mtspr   SRR0,r12
-        mfspr   r12,SRR1                        /* and SRR1 */
-        mtspr   SRR1,r10
-        rfid
-        b       .                               /* prevent spec. execution */
-#endif /* __DISABLED__ */
-        .align  7
-        .globl  __end_interrupts
-__end_interrupts:
-/*
- * Code from here down to __end_handlers is invoked from the
- * exception prologs above.  Because the prologs assemble the
- * addresses of these handlers using the LOAD_HANDLER macro,
- * which uses an addi instruction, these handlers must be in
- * the first 32k of the kernel image.
- */
-/*** Common interrupt handlers ***/
-        STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
-        /*
-         * Machine check is different because we use a different
-         * save area: PACA_EXMC instead of PACA_EXGEN.
-         */
-        .align  7
-        .globl machine_check_common
-machine_check_common:
-        EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
-        FINISH_NAP
-        DISABLE_INTS
-        bl      .save_nvgprs
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .machine_check_exception
-        b       .ret_from_except
-        STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
-        STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
-        STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
-        STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
-        STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
-        STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
-        STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
-#ifdef CONFIG_ALTIVEC
-        STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
-#else
-        STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
-#endif
-#ifdef CONFIG_CBE_RAS
-        STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
-        STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
-        STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
-#endif /* CONFIG_CBE_RAS */
-        .align  7
-system_call_entry:
-        b       system_call_common
-/*
- * Here we have detected that the kernel stack pointer is bad.
- * R9 contains the saved CR, r13 points to the paca,
- * r10 contains the (bad) kernel stack pointer,
- * r11 and r12 contain the saved SRR0 and SRR1.
- * We switch to using an emergency stack, save the registers there,
- * and call kernel_bad_stack(), which panics.
- */
-bad_stack:
-        ld      r1,PACAEMERGSP(r13)
-        subi    r1,r1,64+INT_FRAME_SIZE
-        std     r9,_CCR(r1)
-        std     r10,GPR1(r1)
-        std     r11,_NIP(r1)
-        std     r12,_MSR(r1)
-        mfspr   r11,SPRN_DAR
-        mfspr   r12,SPRN_DSISR
-        std     r11,_DAR(r1)
-        std     r12,_DSISR(r1)
-        mflr    r10
-        mfctr   r11
-        mfxer   r12
-        std     r10,_LINK(r1)
-        std     r11,_CTR(r1)
-        std     r12,_XER(r1)
-        SAVE_GPR(0,r1)
-        SAVE_GPR(2,r1)
-        SAVE_4GPRS(3,r1)
-        SAVE_2GPRS(7,r1)
-        SAVE_10GPRS(12,r1)
-        SAVE_10GPRS(22,r1)
-        lhz     r12,PACA_TRAP_SAVE(r13)
-        std     r12,_TRAP(r1)
-        addi    r11,r1,INT_FRAME_SIZE
-        std     r11,0(r1)
-        li      r12,0
-        std     r12,0(r11)
-        ld      r2,PACATOC(r13)
-1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .kernel_bad_stack
-        b       1b
-/*
- * Here r13 points to the paca, r9 contains the saved CR,
- * SRR0 and SRR1 are saved in r11 and r12,
- * r9 - r13 are saved in paca->exgen.
- */
-        .align  7
-        .globl data_access_common
-data_access_common:
-        mfspr   r10,SPRN_DAR
-        std     r10,PACA_EXGEN+EX_DAR(r13)
-        mfspr   r10,SPRN_DSISR
-        stw     r10,PACA_EXGEN+EX_DSISR(r13)
-        EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
-        ld      r3,PACA_EXGEN+EX_DAR(r13)
-        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
-        li      r5,0x300
-        b       .do_hash_page           /* Try to handle as hpte fault */
-        .align  7
-        .globl instruction_access_common
-instruction_access_common:
-        EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
-        ld      r3,_NIP(r1)
-        andis.  r4,r12,0x5820
-        li      r5,0x400
-        b       .do_hash_page           /* Try to handle as hpte fault */
-/*
- * Here is the common SLB miss user that is used when going to virtual
- * mode for SLB misses, that is currently not used
- */
-#ifdef __DISABLED__
-        .align  7
-        .globl  slb_miss_user_common
-slb_miss_user_common:
-        mflr    r10
-        std     r3,PACA_EXGEN+EX_DAR(r13)
-        stw     r9,PACA_EXGEN+EX_CCR(r13)
-        std     r10,PACA_EXGEN+EX_LR(r13)
-        std     r11,PACA_EXGEN+EX_SRR0(r13)
-        bl      .slb_allocate_user
-        ld      r10,PACA_EXGEN+EX_LR(r13)
-        ld      r3,PACA_EXGEN+EX_R3(r13)
-        lwz     r9,PACA_EXGEN+EX_CCR(r13)
-        ld      r11,PACA_EXGEN+EX_SRR0(r13)
-        mtlr    r10
-        beq-    slb_miss_fault
-        andi.   r10,r12,MSR_RI          /* check for unrecoverable exception */
-        beq-    unrecov_user_slb
-        mfmsr   r10
-.machine push
-.machine "power4"
-        mtcrf   0x80,r9
-.machine pop
-        clrrdi  r10,r10,2               /* clear RI before setting SRR0/1 */
-        mtmsrd  r10,1
-        mtspr   SRR0,r11
-        mtspr   SRR1,r12
-        ld      r9,PACA_EXGEN+EX_R9(r13)
-        ld      r10,PACA_EXGEN+EX_R10(r13)
-        ld      r11,PACA_EXGEN+EX_R11(r13)
-        ld      r12,PACA_EXGEN+EX_R12(r13)
-        ld      r13,PACA_EXGEN+EX_R13(r13)
-        rfid
-        b       .
-slb_miss_fault:
-        EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
-        ld      r4,PACA_EXGEN+EX_DAR(r13)
-        li      r5,0
-        std     r4,_DAR(r1)
-        std     r5,_DSISR(r1)
-        b       handle_page_fault
-unrecov_user_slb:
-        EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
-        DISABLE_INTS
-        bl      .save_nvgprs
-1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
-        b       1b
-#endif /* __DISABLED__ */
-/*
- * r13 points to the PACA, r9 contains the saved CR,
- * r12 contain the saved SRR1, SRR0 is still ready for return
- * r3 has the faulting address
- * r9 - r13 are saved in paca->exslb.
- * r3 is saved in paca->slb_r3
- * We assume we aren't going to take any exceptions during this procedure.
- */
-_GLOBAL(slb_miss_realmode)
-        mflr    r10
-#ifdef CONFIG_RELOCATABLE
-        mtctr   r11
-#endif
-        stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
-        std     r10,PACA_EXSLB+EX_LR(r13)       /* save LR */
-        bl      .slb_allocate_realmode
-        /* All done -- return from exception. */
-        ld      r10,PACA_EXSLB+EX_LR(r13)
-        ld      r3,PACA_EXSLB+EX_R3(r13)
-        lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        ld      r11,PACALPPACAPTR(r13)
-        ld      r11,LPPACASRR0(r11)             /* get SRR0 value */
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
-        mtlr    r10
-        andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
-        beq-    2f
-.machine        push
-.machine        "power4"
-        mtcrf   0x80,r9
-        mtcrf   0x01,r9         /* slb_allocate uses cr0 and cr7 */
-.machine        pop
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        mtspr   SPRN_SRR0,r11
-        mtspr   SPRN_SRR1,r12
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
-        ld      r9,PACA_EXSLB+EX_R9(r13)
-        ld      r10,PACA_EXSLB+EX_R10(r13)
-        ld      r11,PACA_EXSLB+EX_R11(r13)
-        ld      r12,PACA_EXSLB+EX_R12(r13)
-        ld      r13,PACA_EXSLB+EX_R13(r13)
-        rfid
-        b       .       /* prevent speculative execution */
-2:
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        b       unrecov_slb
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
-        mfspr   r11,SPRN_SRR0
-        ld      r10,PACAKBASE(r13)
-        LOAD_HANDLER(r10,unrecov_slb)
-        mtspr   SPRN_SRR0,r10
-        ld      r10,PACAKMSR(r13)
-        mtspr   SPRN_SRR1,r10
-        rfid
-        b       .
-unrecov_slb:
-        EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
-        DISABLE_INTS
-        bl      .save_nvgprs
-1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
-        b       1b
-        .align  7
-        .globl hardware_interrupt_common
-        .globl hardware_interrupt_entry
-hardware_interrupt_common:
-        EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
-        FINISH_NAP
-hardware_interrupt_entry:
-        DISABLE_INTS
-BEGIN_FTR_SECTION
-        bl      .ppc64_runlatch_on
-END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_IRQ
-        b       .ret_from_except_lite
-#ifdef CONFIG_PPC_970_NAP
-power4_fixup_nap:
-        andc    r9,r9,r10
-        std     r9,TI_LOCAL_FLAGS(r11)
-        ld      r10,_LINK(r1)           /* make idle task do the */
-        std     r10,_NIP(r1)            /* equivalent of a blr */
-        blr
-#endif
-        .align  7
-        .globl alignment_common
-alignment_common:
-        mfspr   r10,SPRN_DAR
-        std     r10,PACA_EXGEN+EX_DAR(r13)
-        mfspr   r10,SPRN_DSISR
-        stw     r10,PACA_EXGEN+EX_DSISR(r13)
-        EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
-        ld      r3,PACA_EXGEN+EX_DAR(r13)
-        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
-        std     r3,_DAR(r1)
-        std     r4,_DSISR(r1)
-        bl      .save_nvgprs
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
-        bl      .alignment_exception
-        b       .ret_from_except
-        .align  7
-        .globl program_check_common
-program_check_common:
-        EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
-        bl      .save_nvgprs
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
-        bl      .program_check_exception
-        b       .ret_from_except
-        .align  7
-        .globl fp_unavailable_common
-fp_unavailable_common:
-        EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
-        bne     1f                      /* if from user, just load it up */
-        bl      .save_nvgprs
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
-        bl      .kernel_fp_unavailable_exception
-        BUG_OPCODE
-1:      bl      .load_up_fpu
-        b       fast_exception_return
-        .align  7
-        .globl altivec_unavailable_common
-altivec_unavailable_common:
-        EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
-#ifdef CONFIG_ALTIVEC
-BEGIN_FTR_SECTION
-        beq     1f
-        bl      .load_up_altivec
-        b       fast_exception_return
-1:
-END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
-#endif
-        bl      .save_nvgprs
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
-        bl      .altivec_unavailable_exception
-        b       .ret_from_except
-        .align  7
-        .globl vsx_unavailable_common
-vsx_unavailable_common:
-        EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
-#ifdef CONFIG_VSX
-BEGIN_FTR_SECTION
-        bne     .load_up_vsx
-1:
-END_FTR_SECTION_IFSET(CPU_FTR_VSX)
-#endif
-        bl      .save_nvgprs
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
-        bl      .vsx_unavailable_exception
-        b       .ret_from_except
-        .align  7
-        .globl  __end_handlers
-__end_handlers:
-/*
- * Return from an exception with minimal checks.
- * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
- * If interrupts have been enabled, or anything has been
- * done that might have changed the scheduling status of
- * any task or sent any task a signal, you should use
- * ret_from_except or ret_from_except_lite instead of this.
 */
-fast_exc_return_irq:                    /* restores irq state too */
+#ifdef CONFIG_PPC_BOOK3S
-        ld      r3,SOFTE(r1)
+#include "exceptions-64s.S"
-        TRACE_AND_RESTORE_IRQ(r3);
-        ld      r12,_MSR(r1)
-        rldicl  r4,r12,49,63            /* get MSR_EE to LSB */
-        stb     r4,PACAHARDIRQEN(r13)   /* restore paca->hard_enabled */
-        b       1f
-        .globl  fast_exception_return
-fast_exception_return:
-        ld      r12,_MSR(r1)
-1:      ld      r11,_NIP(r1)
-        andi.   r3,r12,MSR_RI           /* check if RI is set */
-        beq-    unrecov_fer
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
-        andi.   r3,r12,MSR_PR
-        beq     2f
-        ACCOUNT_CPU_USER_EXIT(r3, r4)
-2:
 #endif
-        ld      r3,_CCR(r1)
-        ld      r4,_LINK(r1)
-        ld      r5,_CTR(r1)
-        ld      r6,_XER(r1)
-        mtcr    r3
-        mtlr    r4
-        mtctr   r5
-        mtxer   r6
-        REST_GPR(0, r1)
-        REST_8GPRS(2, r1)
-        mfmsr   r10
-        rldicl  r10,r10,48,1            /* clear EE */
-        rldicr  r10,r10,16,61           /* clear RI (LE is 0 already) */
-        mtmsrd  r10,1
-        mtspr   SPRN_SRR1,r12
-        mtspr   SPRN_SRR0,r11
-        REST_4GPRS(10, r1)
-        ld      r1,GPR1(r1)
-        rfid
-        b       .       /* prevent speculative execution */
-unrecov_fer:
-        bl      .save_nvgprs
-1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
-        b       1b
-#ifdef CONFIG_ALTIVEC
-/*
- * load_up_altivec(unused, unused, tsk)
- * Disable VMX for the task which had it previously,
- * and save its vector registers in its thread_struct.
- * Enables the VMX for use in the kernel on return.
- * On SMP we know the VMX is free, since we give it up every
- * switch (ie, no lazy save of the vector registers).
- * On entry: r13 == 'current' && last_task_used_altivec != 'current'
- */
-_STATIC(load_up_altivec)
-        mfmsr   r5                      /* grab the current MSR */
-        oris    r5,r5,MSR_VEC@h
-        mtmsrd  r5                      /* enable use of VMX now */
-        isync
-/*
- * For SMP, we don't do lazy VMX switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another.  Instead we call giveup_altvec in switch_to.
- * VRSAVE isn't dealt with here, that is done in the normal context
- * switch code. Note that we could rely on vrsave value to eventually
- * avoid saving all of the VREGs here...
- */
-#ifndef CONFIG_SMP
-        ld      r3,last_task_used_altivec@got(r2)
-        ld      r4,0(r3)
-        cmpdi   0,r4,0
-        beq     1f
-        /* Save VMX state to last_task_used_altivec's THREAD struct */
-        addi    r4,r4,THREAD
-        SAVE_32VRS(0,r5,r4)
-        mfvscr  vr0
-        li      r10,THREAD_VSCR
-        stvx    vr0,r10,r4
-        /* Disable VMX for last_task_used_altivec */
-        ld      r5,PT_REGS(r4)
-        ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-        lis     r6,MSR_VEC@h
-        andc    r4,r4,r6
-        std     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
-        /* Hack: if we get an altivec unavailable trap with VRSAVE
-         * set to all zeros, we assume this is a broken application
-         * that fails to set it properly, and thus we switch it to
-         * all 1's
-         */
-        mfspr   r4,SPRN_VRSAVE
-        cmpdi   0,r4,0
-        bne+    1f
-        li      r4,-1
-        mtspr   SPRN_VRSAVE,r4
-1:
-        /* enable use of VMX after return */
-        ld      r4,PACACURRENT(r13)
-        addi    r5,r4,THREAD            /* Get THREAD */
-        oris    r12,r12,MSR_VEC@h
-        std     r12,_MSR(r1)
-        li      r4,1
-        li      r10,THREAD_VSCR
-        stw     r4,THREAD_USED_VR(r5)
-        lvx     vr0,r10,r5
-        mtvscr  vr0
-        REST_32VRS(0,r4,r5)
-#ifndef CONFIG_SMP
-        /* Update last_task_used_math to 'current' */
-        subi    r4,r5,THREAD            /* Back to 'current' */
-        std     r4,0(r3)
-#endif /* CONFIG_SMP */
-        /* restore registers and return */
-        blr
-#endif /* CONFIG_ALTIVEC */
-#ifdef CONFIG_VSX
-/*
- * load_up_vsx(unused, unused, tsk)
- * Disable VSX for the task which had it previously,
- * and save its vector registers in its thread_struct.
- * Reuse the fp and vsx saves, but first check to see if they have
- * been saved already.
- * On entry: r13 == 'current' && last_task_used_vsx != 'current'
- */
-_STATIC(load_up_vsx)
-/* Load FP and VSX registers if they haven't been done yet */
-        andi.   r5,r12,MSR_FP
-        beql+   load_up_fpu             /* skip if already loaded */
-        andis.  r5,r12,MSR_VEC@h
-        beql+   load_up_altivec         /* skip if already loaded */
-#ifndef CONFIG_SMP
-        ld      r3,last_task_used_vsx@got(r2)
-        ld      r4,0(r3)
-        cmpdi   0,r4,0
-        beq     1f
-        /* Disable VSX for last_task_used_vsx */
-        addi    r4,r4,THREAD
-        ld      r5,PT_REGS(r4)
-        ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-        lis     r6,MSR_VSX@h
-        andc    r6,r4,r6
-        std     r6,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
-        ld      r4,PACACURRENT(r13)
-        addi    r4,r4,THREAD            /* Get THREAD */
-        li      r6,1
-        stw     r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
-        /* enable use of VSX after return */
-        oris    r12,r12,MSR_VSX@h
-        std     r12,_MSR(r1)
-#ifndef CONFIG_SMP
-        /* Update last_task_used_math to 'current' */
-        ld      r4,PACACURRENT(r13)
-        std     r4,0(r3)
-#endif /* CONFIG_SMP */
-        b       fast_exception_return
-#endif /* CONFIG_VSX */
-/*
- * Hash table stuff
- */
-        .align  7
-_STATIC(do_hash_page)
-        std     r3,_DAR(r1)
-        std     r4,_DSISR(r1)
-        andis.  r0,r4,0xa450            /* weird error? */
-        bne-    handle_page_fault       /* if not, try to insert a HPTE */
-BEGIN_FTR_SECTION
-        andis.  r0,r4,0x0020            /* Is it a segment table fault? */
-        bne-    do_ste_alloc            /* If so handle it */
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
-        /*
-         * On iSeries, we soft-disable interrupts here, then
-         * hard-enable interrupts so that the hash_page code can spin on
-         * the hash_table_lock without problems on a shared processor.
-         */
-        DISABLE_INTS
-        /*
-         * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
-         * and will clobber volatile registers when irq tracing is enabled
-         * so we need to reload them. It may be possible to be smarter here
-         * and move the irq tracing elsewhere but let's keep it simple for
-         * now
-         */
-#ifdef CONFIG_TRACE_IRQFLAGS
-        ld      r3,_DAR(r1)
-        ld      r4,_DSISR(r1)
-        ld      r5,_TRAP(r1)
-        ld      r12,_MSR(r1)
-        clrrdi  r5,r5,4
-#endif /* CONFIG_TRACE_IRQFLAGS */
-        /*
-         * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
-         * accessing a userspace segment (even from the kernel). We assume
-         * kernel addresses always have the high bit set.
-         */
-        rlwinm  r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
-        rotldi  r0,r3,15                /* Move high bit into MSR_PR posn */
-        orc     r0,r12,r0               /* MSR_PR | ~high_bit */
-        rlwimi  r4,r0,32-13,30,30       /* becomes _PAGE_USER access bit */
-        ori     r4,r4,1                 /* add _PAGE_PRESENT */
-        rlwimi  r4,r5,22+2,31-2,31-2    /* Set _PAGE_EXEC if trap is 0x400 */
-        /*
-         * r3 contains the faulting address
-         * r4 contains the required access permissions
-         * r5 contains the trap number
-         *
-         * at return r3 = 0 for success
-         */
-        bl      .hash_page              /* build HPTE if possible */
-        cmpdi   r3,0                    /* see if hash_page succeeded */
-BEGIN_FW_FTR_SECTION
-        /*
-         * If we had interrupts soft-enabled at the point where the
-         * DSI/ISI occurred, and an interrupt came in during hash_page,
-         * handle it now.
-         * We jump to ret_from_except_lite rather than fast_exception_return
-         * because ret_from_except_lite will check for and handle pending
-         * interrupts if necessary.
-         */
-        beq     13f
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-BEGIN_FW_FTR_SECTION
-        /*
-         * Here we have interrupts hard-disabled, so it is sufficient
-         * to restore paca->{soft,hard}_enable and get out.
-         */
-        beq     fast_exc_return_irq     /* Return from exception on success */
-END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
-        /* For a hash failure, we don't bother re-enabling interrupts */
-        ble-    12f
-        /*
-         * hash_page couldn't handle it, set soft interrupt enable back
-         * to what it was before the trap.  Note that .raw_local_irq_restore
-         * handles any interrupts pending at this point.
-         */
-        ld      r3,SOFTE(r1)
-        TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
-        bl      .raw_local_irq_restore
-        b       11f
-/* Here we have a page fault that hash_page can't handle. */
-handle_page_fault:
-        ENABLE_INTS
-11:     ld      r4,_DAR(r1)
-        ld      r5,_DSISR(r1)
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_page_fault
-        cmpdi   r3,0
-        beq+    13f
-        bl      .save_nvgprs
-        mr      r5,r3
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        lwz     r4,_DAR(r1)
-        bl      .bad_page_fault
-        b       .ret_from_except
-13:     b       .ret_from_except_lite
-/* We have a page fault that hash_page could handle but HV refused
- * the PTE insertion
- */
-12:     bl      .save_nvgprs
-        mr      r5,r3
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        ld      r4,_DAR(r1)
-        bl      .low_hash_fault
-        b       .ret_from_except
-        /* here we have a segment miss */
-do_ste_alloc:
-        bl      .ste_allocate           /* try to insert stab entry */
-        cmpdi   r3,0
-        bne-    handle_page_fault
-        b       fast_exception_return
-/*
- * r13 points to the PACA, r9 contains the saved CR,
- * r11 and r12 contain the saved SRR0 and SRR1.
- * r9 - r13 are saved in paca->exslb.
- * We assume we aren't going to take any exceptions during this procedure.
- * We assume (DAR >> 60) == 0xc.
- */
-        .align  7
-_GLOBAL(do_stab_bolted)
-        stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
-        std     r11,PACA_EXSLB+EX_SRR0(r13)     /* save SRR0 in exc. frame */
-        /* Hash to the primary group */
-        ld      r10,PACASTABVIRT(r13)
-        mfspr   r11,SPRN_DAR
-        srdi    r11,r11,28
-        rldimi  r10,r11,7,52    /* r10 = first ste of the group */
-        /* Calculate VSID */
-        /* This is a kernel address, so protovsid = ESID */
-        ASM_VSID_SCRAMBLE(r11, r9, 256M)
-        rldic   r9,r11,12,16    /* r9 = vsid << 12 */
-        /* Search the primary group for a free entry */
-1:      ld      r11,0(r10)      /* Test valid bit of the current ste    */
-        andi.   r11,r11,0x80
-        beq     2f
-        addi    r10,r10,16
-        andi.   r11,r10,0x70
-        bne     1b
-        /* Stick for only searching the primary group for now.          */
-        /* At least for now, we use a very simple random castout scheme */
-        /* Use the TB as a random number ;  OR in 1 to avoid entry 0    */
-        mftb    r11
-        rldic   r11,r11,4,57    /* r11 = (r11 << 4) & 0x70 */
-        ori     r11,r11,0x10
-        /* r10 currently points to an ste one past the group of interest */
-        /* make it point to the randomly selected entry                 */
-        subi    r10,r10,128
-        or      r10,r10,r11     /* r10 is the entry to invalidate       */
-        isync                   /* mark the entry invalid               */
-        ld      r11,0(r10)
-        rldicl  r11,r11,56,1    /* clear the valid bit */
-        rotldi  r11,r11,8
-        std     r11,0(r10)
-        sync
-        clrrdi  r11,r11,28      /* Get the esid part of the ste         */
-        slbie   r11
-2:      std     r9,8(r10)       /* Store the vsid part of the ste       */
-        eieio
-        mfspr   r11,SPRN_DAR            /* Get the new esid                     */
-        clrrdi  r11,r11,28      /* Permits a full 32b of ESID           */
-        ori     r11,r11,0x90    /* Turn on valid and kp                 */
-        std     r11,0(r10)      /* Put new entry back into the stab     */
-        sync
-        /* All done -- return from exception. */
-        lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
-        ld      r11,PACA_EXSLB+EX_SRR0(r13)     /* get saved SRR0 */
-        andi.   r10,r12,MSR_RI
-        beq-    unrecov_slb
-        mtcrf   0x80,r9                 /* restore CR */
-        mfmsr   r10
-        clrrdi  r10,r10,2
-        mtmsrd  r10,1
-        mtspr   SPRN_SRR0,r11
-        mtspr   SPRN_SRR1,r12
-        ld      r9,PACA_EXSLB+EX_R9(r13)
-        ld      r10,PACA_EXSLB+EX_R10(r13)
-        ld      r11,PACA_EXSLB+EX_R11(r13)
-        ld      r12,PACA_EXSLB+EX_R12(r13)
-        ld      r13,PACA_EXSLB+EX_R13(r13)
-        rfid
-        b       .       /* prevent speculative execution */
-/*
- * Space for CPU0's segment table.
- *
- * On iSeries, the hypervisor must fill in at least one entry before
- * we get control (with relocate on).  The address is given to the hv
- * as a page number (see xLparMap below), so this must be at a
- * fixed address (the linker can't compute (u64)&initial_stab >>
- * PAGE_SHIFT).
- */
-        . = STAB0_OFFSET        /* 0x6000 */
-        .globl initial_stab
-initial_stab:
-        .space  4096
-#ifdef CONFIG_PPC_PSERIES
-/*
- * Data area reserved for FWNMI option.
- * This address (0x7000) is fixed by the RPA.
- */
-        .= 0x7000
-        .globl fwnmi_data_area
-fwnmi_data_area:
-#endif /* CONFIG_PPC_PSERIES */
-        /* iSeries does not use the FWNMI stuff, so it is safe to put
-         * this here, even if we later allow kernels that will boot on
-         * both pSeries and iSeries */
-#ifdef CONFIG_PPC_ISERIES
-        . = LPARMAP_PHYS
-        .globl xLparMap
-xLparMap:
-        .quad   HvEsidsToMap            /* xNumberEsids */
-        .quad   HvRangesToMap           /* xNumberRanges */
-        .quad   STAB0_PAGE              /* xSegmentTableOffs */
-        .zero   40                      /* xRsvd */
-        /* xEsids (HvEsidsToMap entries of 2 quads) */
-        .quad   PAGE_OFFSET_ESID        /* xKernelEsid */
-        .quad   PAGE_OFFSET_VSID        /* xKernelVsid */
-        .quad   VMALLOC_START_ESID      /* xKernelEsid */
-        .quad   VMALLOC_START_VSID      /* xKernelVsid */
-        /* xRanges (HvRangesToMap entries of 3 quads) */
-        .quad   HvPagesToMap            /* xPages */
-        .quad   0                       /* xOffset */
-        .quad   PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
-#endif /* CONFIG_PPC_ISERIES */
-#ifdef CONFIG_PPC_PSERIES
-        . = 0x8000
-#endif /* CONFIG_PPC_PSERIES */
 /*
 * On pSeries and most other platforms, secondary processors spin
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 95f39f1e68d4..5f9febc8d143 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -256,7 +256,7 @@ label:
         * off DE in the DSRR1 value and clearing the debug status.           \
         */                                                                   \
        mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
-        andis.  r10,r10,DBSR_IC@h;                                            \
+        andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
        beq+    2f;                                                           \
                                                                              \
        lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
@@ -271,7 +271,7 @@ label:
                                                                              \
        /* here it looks like we got an inappropriate debug exception. */     \
 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CDRR1 value */     \
-        lis     r10,DBSR_IC@h;          /* clear the IC event */              \
+        lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
        mtspr   SPRN_DBSR,r10;                                                \
        /* restore state and get out */                                       \
        lwz     r10,_CCR(r11);                                                \
@@ -309,7 +309,7 @@ label:
         * off DE in the CSRR1 value and clearing the debug status.           \
         */                                                                   \
        mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
-        andis.  r10,r10,DBSR_IC@h;                                            \
+        andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
        beq+    2f;                                                           \
                                                                              \
        lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
@@ -317,14 +317,14 @@ label:
        cmplw   r12,r10;                                                      \
        blt+    2f;                     /* addr below exception vectors */    \
                                                                              \
-        lis     r10,DebugCrit@h;                                                      \
+        lis     r10,DebugCrit@h;                                              \
        ori     r10,r10,DebugCrit@l;                                          \
        cmplw   r12,r10;                                                      \
        bgt+    2f;                     /* addr above exception vectors */    \
                                                                              \
        /* here it looks like we got an inappropriate debug exception. */     \
 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CSRR1 value */     \
-        lis     r10,DBSR_IC@h;          /* clear the IC event */              \
+        lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
        mtspr   SPRN_DBSR,r10;                                                \
        /* restore state and get out */                                       \
        lwz     r10,_CCR(r11);                                                \
diff --git a/arch/powerpc/kernel/init_task.c b/arch/powerpc/kernel/init_task.c
index 688b329800bd..ffc4253fef55 100644
--- a/arch/powerpc/kernel/init_task.c
+++ b/arch/powerpc/kernel/init_task.c
@@ -9,10 +9,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 844d3f882a15..f7f376ea7b17 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -118,6 +118,7 @@ notrace void raw_local_irq_restore(unsigned long en)
        if (!en)
                return;
+#ifdef CONFIG_PPC_STD_MMU_64
        if (firmware_has_feature(FW_FEATURE_ISERIES)) {
                /*
                 * Do we need to disable preemption here?  Not really: in the
@@ -135,6 +136,7 @@ notrace void raw_local_irq_restore(unsigned long en)
                if (local_paca->lppaca_ptr->int_dword.any_int)
                        iseries_handle_interrupts();
        }
+#endif /* CONFIG_PPC_STD_MMU_64 */
        if (test_perf_counter_pending()) {
                clear_perf_counter_pending();
@@ -254,77 +256,84 @@ void fixup_irqs(cpumask_t map)
 }
 #endif
-void do_IRQ(struct pt_regs *regs)
-{
-        struct pt_regs *old_regs = set_irq_regs(regs);
-        unsigned int irq;
 #ifdef CONFIG_IRQSTACKS
+static inline void handle_one_irq(unsigned int irq)
+{
        struct thread_info *curtp, *irqtp;
-#endif
+        unsigned long saved_sp_limit;
+        struct irq_desc *desc;
-        irq_enter();
+        /* Switch to the irq stack to handle this */
+        curtp = current_thread_info();
+        irqtp = hardirq_ctx[smp_processor_id()];
+        if (curtp == irqtp) {
+                /* We're already on the irq stack, just handle it */
+                generic_handle_irq(irq);
+                return;
+        }
+        desc = irq_desc + irq;
+        saved_sp_limit = current->thread.ksp_limit;
+        irqtp->task = curtp->task;
+        irqtp->flags = 0;
+        /* Copy the softirq bits in preempt_count so that the
+         * softirq checks work in the hardirq context. */
+        irqtp->preempt_count = (irqtp->preempt_count & ~SOFTIRQ_MASK) |
+                               (curtp->preempt_count & SOFTIRQ_MASK);
+        current->thread.ksp_limit = (unsigned long)irqtp +
+                _ALIGN_UP(sizeof(struct thread_info), 16);
+        call_handle_irq(irq, desc, irqtp, desc->handle_irq);
+        current->thread.ksp_limit = saved_sp_limit;
+        irqtp->task = NULL;
+        /* Set any flag that may have been set on the
+         * alternate stack
+         */
+        if (irqtp->flags)
+                set_bits(irqtp->flags, &curtp->flags);
+}
+#else
+static inline void handle_one_irq(unsigned int irq)
+{
+        generic_handle_irq(irq);
+}
+#endif
+static inline void check_stack_overflow(void)
+{
 #ifdef CONFIG_DEBUG_STACKOVERFLOW
-        /* Debugging check for stack overflow: is there less than 2KB free? */
+        long sp;
-        {
-                long sp;
-                sp = __get_SP() & (THREAD_SIZE-1);
+        sp = __get_SP() & (THREAD_SIZE-1);
-                if (unlikely(sp < (sizeof(struct thread_info) + 2048))) {
+        /* check for stack overflow: is there less than 2KB free? */
-                        printk("do_IRQ: stack overflow: %ld\n",
+        if (unlikely(sp < (sizeof(struct thread_info) + 2048))) {
-                                sp - sizeof(struct thread_info));
+                printk("do_IRQ: stack overflow: %ld\n",
-                        dump_stack();
+                        sp - sizeof(struct thread_info));
-                }
+                dump_stack();
        }
 #endif
+}
-        /*
+void do_IRQ(struct pt_regs *regs)
-         * Every platform is required to implement ppc_md.get_irq.
+{
-         * This function will either return an irq number or NO_IRQ to
+        struct pt_regs *old_regs = set_irq_regs(regs);
-         * indicate there are no more pending.
+        unsigned int irq;
-         * The value NO_IRQ_IGNORE is for buggy hardware and means that this
-         * IRQ has already been handled. -- Tom
-         */
-        irq = ppc_md.get_irq();
-        if (irq != NO_IRQ && irq != NO_IRQ_IGNORE) {
+        irq_enter();
-#ifdef CONFIG_IRQSTACKS
-                /* Switch to the irq stack to handle this */
-                curtp = current_thread_info();
-                irqtp = hardirq_ctx[smp_processor_id()];
-                if (curtp != irqtp) {
-                        struct irq_desc *desc = irq_desc + irq;
-                        void *handler = desc->handle_irq;
-                        unsigned long saved_sp_limit = current->thread.ksp_limit;
-                        if (handler == NULL)
-                                handler = &__do_IRQ;
-                        irqtp->task = curtp->task;
-                        irqtp->flags = 0;
-                        /* Copy the softirq bits in preempt_count so that the
-                         * softirq checks work in the hardirq context.
-                         */
-                        irqtp->preempt_count =
-                                (irqtp->preempt_count & ~SOFTIRQ_MASK) |
-                                (curtp->preempt_count & SOFTIRQ_MASK);
-                        current->thread.ksp_limit = (unsigned long)irqtp +
+        check_stack_overflow();
-                                _ALIGN_UP(sizeof(struct thread_info), 16);
-                        call_handle_irq(irq, desc, irqtp, handler);
-                        current->thread.ksp_limit = saved_sp_limit;
-                        irqtp->task = NULL;
+        irq = ppc_md.get_irq();
-                        /* Set any flag that may have been set on the
+        if (irq != NO_IRQ && irq != NO_IRQ_IGNORE)
-                         * alternate stack
+                handle_one_irq(irq);
-                         */
+        else if (irq != NO_IRQ_IGNORE)
-                        if (irqtp->flags)
-                                set_bits(irqtp->flags, &curtp->flags);
-                } else
-#endif
-                        generic_handle_irq(irq);
-        } else if (irq != NO_IRQ_IGNORE)
                /* That's not SMP safe ... but who cares ? */
                ppc_spurious_interrupts++;
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index 78b3f7840ade..2419cc706ff1 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -169,6 +169,9 @@ struct hvcall_ppp_data {
        u8      unallocated_weight;
        u16     active_procs_in_pool;
        u16     active_system_procs;
+        u16     phys_platform_procs;
+        u32     max_proc_cap_avail;
+        u32     entitled_proc_cap_avail;
 };
 /*
@@ -190,13 +193,18 @@ struct hvcall_ppp_data {
 *            XX - Unallocated Variable Processor Capacity Weight.
 *              XXXX - Active processors in Physical Processor Pool.
 *                  XXXX  - Processors active on platform.
+ *  R8 (QQQQRRRRRRSSSSSS). if ibm,partition-performance-parameters-level >= 1
+ *      XXXX - Physical platform procs allocated to virtualization.
+ *          XXXXXX - Max procs capacity % available to the partitions pool.
+ *                XXXXXX - Entitled procs capacity % available to the
+ *                         partitions pool.
 */
 static unsigned int h_get_ppp(struct hvcall_ppp_data *ppp_data)
 {
        unsigned long rc;
-        unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
+        unsigned long retbuf[PLPAR_HCALL9_BUFSIZE];
-        rc = plpar_hcall(H_GET_PPP, retbuf);
+        rc = plpar_hcall9(H_GET_PPP, retbuf);
        ppp_data->entitlement = retbuf[0];
        ppp_data->unallocated_entitlement = retbuf[1];
@@ -210,6 +218,10 @@ static unsigned int h_get_ppp(struct hvcall_ppp_data *ppp_data)
        ppp_data->active_procs_in_pool = (retbuf[3] >> 2 * 8) & 0xffff;
        ppp_data->active_system_procs = retbuf[3] & 0xffff;
+        ppp_data->phys_platform_procs = retbuf[4] >> 6 * 8;
+        ppp_data->max_proc_cap_avail = (retbuf[4] >> 3 * 8) & 0xffffff;
+        ppp_data->entitled_proc_cap_avail = retbuf[4] & 0xffffff;
        return rc;
 }
@@ -234,6 +246,8 @@ static unsigned h_pic(unsigned long *pool_idle_time,
 static void parse_ppp_data(struct seq_file *m)
 {
        struct hvcall_ppp_data ppp_data;
+        struct device_node *root;
+        const int *perf_level;
        int rc;
        rc = h_get_ppp(&ppp_data);
@@ -267,6 +281,28 @@ static void parse_ppp_data(struct seq_file *m)
        seq_printf(m, "capped=%d\n", ppp_data.capped);
        seq_printf(m, "unallocated_capacity=%lld\n",
                   ppp_data.unallocated_entitlement);
+        /* The last bits of information returned from h_get_ppp are only
+         * valid if the ibm,partition-performance-parameters-level
+         * property is >= 1.
+         */
+        root = of_find_node_by_path("/");
+        if (root) {
+                perf_level = of_get_property(root,
+                                "ibm,partition-performance-parameters-level",
+                                             NULL);
+                if (perf_level && (*perf_level >= 1)) {
+                        seq_printf(m,
+                            "physical_procs_allocated_to_virtualization=%d\n",
+                                   ppp_data.phys_platform_procs);
+                        seq_printf(m, "max_proc_capacity_available=%d\n",
+                                   ppp_data.max_proc_cap_avail);
+                        seq_printf(m, "entitled_proc_capacity_available=%d\n",
+                                   ppp_data.entitled_proc_cap_avail);
+                }
+                of_node_put(root);
+        }
 }
 /**
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index b9530b2395a2..a5cf9c1356a6 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -457,98 +457,6 @@ _GLOBAL(disable_kernel_fp)
        isync
        blr
-#ifdef CONFIG_ALTIVEC
-#if 0 /* this has no callers for now */
-/*
- * disable_kernel_altivec()
- * Disable the VMX.
- */
-_GLOBAL(disable_kernel_altivec)
-        mfmsr   r3
-        rldicl  r0,r3,(63-MSR_VEC_LG),1
-        rldicl  r3,r0,(MSR_VEC_LG+1),0
-        mtmsrd  r3                      /* disable use of VMX now */
-        isync
-        blr
-#endif /* 0 */
-/*
- * giveup_altivec(tsk)
- * Disable VMX for the task given as the argument,
- * and save the vector registers in its thread_struct.
- * Enables the VMX for use in the kernel on return.
- */
-_GLOBAL(giveup_altivec)
-        mfmsr   r5
-        oris    r5,r5,MSR_VEC@h
-        mtmsrd  r5                      /* enable use of VMX now */
-        isync
-        cmpdi   0,r3,0
-        beqlr-                          /* if no previous owner, done */
-        addi    r3,r3,THREAD            /* want THREAD of task */
-        ld      r5,PT_REGS(r3)
-        cmpdi   0,r5,0
-        SAVE_32VRS(0,r4,r3)
-        mfvscr  vr0
-        li      r4,THREAD_VSCR
-        stvx    vr0,r4,r3
-        beq     1f
-        ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-#ifdef CONFIG_VSX
-BEGIN_FTR_SECTION
-        lis     r3,(MSR_VEC|MSR_VSX)@h
-FTR_SECTION_ELSE
-        lis     r3,MSR_VEC@h
-ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
-#else
-        lis     r3,MSR_VEC@h
-#endif
-        andc    r4,r4,r3                /* disable FP for previous task */
-        std     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
-        li      r5,0
-        ld      r4,last_task_used_altivec@got(r2)
-        std     r5,0(r4)
-#endif /* CONFIG_SMP */
-        blr
-#endif /* CONFIG_ALTIVEC */
-#ifdef CONFIG_VSX
-/*
- * __giveup_vsx(tsk)
- * Disable VSX for the task given as the argument.
- * Does NOT save vsx registers.
- * Enables the VSX for use in the kernel on return.
- */
-_GLOBAL(__giveup_vsx)
-        mfmsr   r5
-        oris    r5,r5,MSR_VSX@h
-        mtmsrd  r5                      /* enable use of VSX now */
-        isync
-        cmpdi   0,r3,0
-        beqlr-                          /* if no previous owner, done */
-        addi    r3,r3,THREAD            /* want THREAD of task */
-        ld      r5,PT_REGS(r3)
-        cmpdi   0,r5,0
-        beq     1f
-        ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-        lis     r3,MSR_VSX@h
-        andc    r4,r4,r3                /* disable VSX for previous task */
-        std     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
-        li      r5,0
-        ld      r4,last_task_used_vsx@got(r2)
-        std     r5,0(r4)
-#endif /* CONFIG_SMP */
-        blr
-#endif /* CONFIG_VSX */
 /* kexec_wait(phys_cpu)
 *
 * wait for the flag to change, indicating this kernel is going away but
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index c744b327bcab..e9962c7f8a09 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -18,6 +18,8 @@
 * field correctly */
 extern unsigned long __toc_start;
+#ifdef CONFIG_PPC_BOOK3S
 /*
 * The structure which the hypervisor knows about - this structure
 * should not cross a page boundary.  The vpa_init/register_vpa call
@@ -41,6 +43,10 @@ struct lppaca lppaca[] = {
        },
 };
+#endif /* CONFIG_PPC_BOOK3S */
+#ifdef CONFIG_PPC_STD_MMU_64
 /*
 * 3 persistent SLBs are registered here.  The buffer will be zero
 * initially, hence will all be invaild until we actually write them.
@@ -52,6 +58,8 @@ struct slb_shadow slb_shadow[] __cacheline_aligned = {
        },
 };
+#endif /* CONFIG_PPC_STD_MMU_64 */
 /* The Paca is an array with one entry per processor.  Each contains an
 * lppaca, which contains the information shared between the
 * hypervisor and Linux.
@@ -77,15 +85,19 @@ void __init initialise_pacas(void)
        for (cpu = 0; cpu < NR_CPUS; cpu++) {
                struct paca_struct *new_paca = &paca[cpu];
+#ifdef CONFIG_PPC_BOOK3S
                new_paca->lppaca_ptr = &lppaca[cpu];
+#endif
                new_paca->lock_token = 0x8000;
                new_paca->paca_index = cpu;
                new_paca->kernel_toc = kernel_toc;
                new_paca->kernelbase = (unsigned long) _stext;
                new_paca->kernel_msr = MSR_KERNEL;
                new_paca->hw_cpu_id = 0xffff;
-                new_paca->slb_shadow_ptr = &slb_shadow[cpu];
                new_paca->__current = &init_task;
+#ifdef CONFIG_PPC_STD_MMU_64
+                new_paca->slb_shadow_ptr = &slb_shadow[cpu];
+#endif /* CONFIG_PPC_STD_MMU_64 */
        }
 }
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 4fee63cb53ff..5a56e97c5ac0 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1505,7 +1505,7 @@ void __init pcibios_resource_survey(void)
 * rest of the code later, for now, keep it as-is as our main
 * resource allocation function doesn't deal with sub-trees yet.
 */
-void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
+void pcibios_claim_one_bus(struct pci_bus *bus)
 {
        struct pci_dev *dev;
        struct pci_bus *child_bus;
@@ -1533,7 +1533,6 @@ void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
        list_for_each_entry(child_bus, &bus->children, node)
                pcibios_claim_one_bus(child_bus);
 }
-EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
 /* pcibios_finish_adding_to_bus
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index d473634e39e3..3ae1c666ff92 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -33,7 +33,6 @@ int pcibios_assign_bus_offset = 1;
 void pcibios_make_OF_bus_map(void);
-static void fixup_broken_pcnet32(struct pci_dev* dev);
 static void fixup_cpc710_pci64(struct pci_dev* dev);
 #ifdef CONFIG_PPC_OF
 static u8* pci_to_OF_bus_map;
@@ -72,16 +71,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_res
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 
 static void
-fixup_broken_pcnet32(struct pci_dev* dev)
-{
-        if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
-                dev->vendor = PCI_VENDOR_ID_AMD;
-                pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
-        }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID,                     fixup_broken_pcnet32);
-static void
 fixup_cpc710_pci64(struct pci_dev* dev)
 {
        /* Hide the PCI64 BARs from the kernel as their content doesn't
@@ -447,14 +436,6 @@ static int __init pcibios_init(void)
 subsys_initcall(pcibios_init);
-/* the next one is stolen from the alpha port... */
-void __init
-pcibios_update_irq(struct pci_dev *dev, int irq)
-{
-        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-        /* XXX FIXME - update OF device tree node interrupt property */
-}
 static struct pci_controller*
 pci_bus_to_hose(int bus)
 {
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 96edb6f8babb..9e8902fa14c7 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -43,16 +43,6 @@ unsigned long pci_probe_only = 1;
 unsigned long pci_io_base = ISA_IO_BASE;
 EXPORT_SYMBOL(pci_io_base);
-static void fixup_broken_pcnet32(struct pci_dev* dev)
-{
-        if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
-                dev->vendor = PCI_VENDOR_ID_AMD;
-                pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
-        }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
 {
        const u32 *prop;
@@ -430,6 +420,9 @@ int pcibios_unmap_io_space(struct pci_bus *bus)
         * so flushing the hash table is the only sane way to make sure
         * that no hash entries are covering that removed bridge area
         * while still allowing other busses overlapping those pages
+         *
+         * Note: If we ever support P2P hotplug on Book3E, we'll have
+         * to do an appropriate TLB flush here too
         */
        if (bus->self) {
                struct resource *res = bus->resource[0];
@@ -437,8 +430,10 @@ int pcibios_unmap_io_space(struct pci_bus *bus)
                pr_debug("IO unmapping for PCI-PCI bridge %s\n",
                         pci_name(bus->self));
+#ifdef CONFIG_PPC_STD_MMU_64
                __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
                                         res->end + _IO_BASE + 1);
+#endif
                return 0;
        }
@@ -511,7 +506,7 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
        pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
        pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
                 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
-        pr_debug("  size=0x%016lx (alloc=0x%016lx)\n",
+        pr_debug("  size=0x%016llx (alloc=0x%016lx)\n",
                 hose->pci_io_size, size_page);
        /* Establish the mapping */
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 1c67de52e3ce..d5e36e5dc7c2 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -27,7 +27,6 @@
 #include <asm/io.h>
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
-#include <asm/pSeries_reconfig.h>
 #include <asm/ppc-pci.h>
 #include <asm/firmware.h>
@@ -35,7 +34,7 @@
 * Traverse_func that inits the PCI fields of the device node.
 * NOTE: this *must* be done before read/write config to the device.
 */
-static void * __devinit update_dn_pci_info(struct device_node *dn, void *data)
+void * __devinit update_dn_pci_info(struct device_node *dn, void *data)
 {
        struct pci_controller *phb = data;
        const int *type =
@@ -184,29 +183,6 @@ struct device_node *fetch_dev_dn(struct pci_dev *dev)
 }
 EXPORT_SYMBOL(fetch_dev_dn);
-static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
-{
-        struct device_node *np = node;
-        struct pci_dn *pci = NULL;
-        int err = NOTIFY_OK;
-        switch (action) {
-        case PSERIES_RECONFIG_ADD:
-                pci = np->parent->data;
-                if (pci)
-                        update_dn_pci_info(np, pci->phb);
-                break;
-        default:
-                err = NOTIFY_DONE;
-                break;
-        }
-        return err;
-}
-static struct notifier_block pci_dn_reconfig_nb = {
-        .notifier_call = pci_dn_reconfig_notifier,
-};
 /** 
 * pci_devs_phb_init - Initialize phbs and pci devs under them.
 * 
@@ -223,6 +199,4 @@ void __init pci_devs_phb_init(void)
        /* This must be done first so the device nodes have valid pci info! */
        list_for_each_entry_safe(phb, tmp, &hose_list, list_node)
                pci_devs_phb_init_dynamic(phb);
-        pSeries_reconfig_notifier_register(&pci_dn_reconfig_nb);
 }
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 7b44a33f03c2..3e7135bbe40f 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -650,7 +650,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
        p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
                                _ALIGN_UP(sizeof(struct thread_info), 16);
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_STD_MMU_64
        if (cpu_has_feature(CPU_FTR_SLB)) {
                unsigned long sp_vsid;
                unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index ce01ff2474da..d4405b95bfaa 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -585,7 +585,7 @@ static void __init check_cpu_pa_features(unsigned long node)
                      ibm_pa_features, ARRAY_SIZE(ibm_pa_features));
 }
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_STD_MMU_64
 static void __init check_cpu_slb_size(unsigned long node)
 {
        u32 *slb_size_ptr;
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 2f0e64b53642..ef6f64950e9b 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -44,10 +44,7 @@
 #include <asm/sections.h>
 #include <asm/machdep.h>
-#ifdef CONFIG_LOGO_LINUX_CLUT224
 #include <linux/linux_logo.h>
-extern const struct linux_logo logo_linux_clut224;
-#endif
 /*
 * Properties whose value is longer than this get excluded from our
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 3635be61f899..9fa2c7dcd05a 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -704,15 +704,34 @@ void user_enable_single_step(struct task_struct *task)
        if (regs != NULL) {
 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+                task->thread.dbcr0 &= ~DBCR0_BT;
                task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
                regs->msr |= MSR_DE;
 #else
+                regs->msr &= ~MSR_BE;
                regs->msr |= MSR_SE;
 #endif
        }
        set_tsk_thread_flag(task, TIF_SINGLESTEP);
 }
+void user_enable_block_step(struct task_struct *task)
+{
+        struct pt_regs *regs = task->thread.regs;
+        if (regs != NULL) {
+#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+                task->thread.dbcr0 &= ~DBCR0_IC;
+                task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
+                regs->msr |= MSR_DE;
+#else
+                regs->msr &= ~MSR_SE;
+                regs->msr |= MSR_BE;
+#endif
+        }
+        set_tsk_thread_flag(task, TIF_SINGLESTEP);
+}
 void user_disable_single_step(struct task_struct *task)
 {
        struct pt_regs *regs = task->thread.regs;
@@ -726,10 +745,10 @@ void user_disable_single_step(struct task_struct *task)
        if (regs != NULL) {
 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
-                task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_IDM);
+                task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
                regs->msr &= ~MSR_DE;
 #else
-                regs->msr &= ~MSR_SE;
+                regs->msr &= ~(MSR_SE | MSR_BE);
 #endif
        }
        clear_tsk_thread_flag(task, TIF_SINGLESTEP);
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 8869001ab5d7..54e66da8f743 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -93,10 +93,7 @@ static int rtas_pci_read_config(struct pci_bus *bus,
 {
        struct device_node *busdn, *dn;
-        if (bus->self)
+        busdn = pci_bus_to_OF_node(bus);
-                busdn = pci_device_to_OF_node(bus->self);
-        else
-                busdn = bus->sysdata;   /* must be a phb */
        /* Search only direct children of the bus */
        for (dn = busdn->child; dn; dn = dn->sibling) {
@@ -140,10 +137,7 @@ static int rtas_pci_write_config(struct pci_bus *bus,
 {
        struct device_node *busdn, *dn;
-        if (bus->self)
+        busdn = pci_bus_to_OF_node(bus);
-                busdn = pci_device_to_OF_node(bus->self);
-        else
-                busdn = bus->sysdata;   /* must be a phb */
        /* Search only direct children of the bus */
        for (dn = busdn->child; dn; dn = dn->sibling) {
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 9e1ca745d8f0..1d154248cf40 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -39,6 +39,7 @@
 #include <asm/serial.h>
 #include <asm/udbg.h>
 #include <asm/mmu_context.h>
+#include <asm/swiotlb.h>
 #include "setup.h"
@@ -332,6 +333,11 @@ void __init setup_arch(char **cmdline_p)
                ppc_md.setup_arch();
        if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
+#ifdef CONFIG_SWIOTLB
+        if (ppc_swiotlb_enable)
+                swiotlb_init();
+#endif
        paging_init();
        /* Initialize the MMU context management stuff */
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index c410c606955d..1f6816003ebe 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -61,6 +61,7 @@
 #include <asm/xmon.h>
 #include <asm/udbg.h>
 #include <asm/kexec.h>
+#include <asm/swiotlb.h>
 #include "setup.h"
@@ -417,12 +418,14 @@ void __init setup_system(void)
        if (ppc64_caches.iline_size != 0x80)
                printk("ppc64_caches.icache_line_size = 0x%x\n",
                       ppc64_caches.iline_size);
+#ifdef CONFIG_PPC_STD_MMU_64
        if (htab_address)
                printk("htab_address                  = 0x%p\n", htab_address);
        printk("htab_hash_mask                = 0x%lx\n", htab_hash_mask);
+#endif /* CONFIG_PPC_STD_MMU_64 */
        if (PHYSICAL_START > 0)
-                printk("physical_start                = 0x%lx\n",
+                printk("physical_start                = 0x%llx\n",
-                       PHYSICAL_START);
+                       (unsigned long long)PHYSICAL_START);
        printk("-----------------------------------------------------\n");
        DBG(" <- setup_system()\n");
@@ -511,8 +514,9 @@ void __init setup_arch(char **cmdline_p)
        irqstack_early_init();
        emergency_stack_init();
+#ifdef CONFIG_PPC_STD_MMU_64
        stabs_alloc();
+#endif
        /* set up the bootmem stuff with available memory */
        do_init_bootmem();
        sparse_init();
@@ -524,6 +528,11 @@ void __init setup_arch(char **cmdline_p)
        if (ppc_md.setup_arch)
                ppc_md.setup_arch();
+#ifdef CONFIG_SWIOTLB
+        if (ppc_swiotlb_enable)
+                swiotlb_init();
+#endif
        paging_init();
        ppc64_boot_msg(0x15, "Setup Done");
 }
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 48571ac56fb7..15391c2ab013 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -52,6 +52,7 @@
 #include <linux/jiffies.h>
 #include <linux/posix-timers.h>
 #include <linux/irq.h>
+#include <linux/delay.h>
 #include <asm/io.h>
 #include <asm/processor.h>
@@ -109,7 +110,7 @@ static void decrementer_set_mode(enum clock_event_mode mode,
 static struct clock_event_device decrementer_clockevent = {
       .name           = "decrementer",
       .rating         = 200,
-       .shift          = 16,
+       .shift          = 0,     /* To be filled in */
       .mult           = 0,     /* To be filled in */
       .irq            = 0,
       .set_next_event = decrementer_set_next_event,
@@ -843,6 +844,22 @@ static void decrementer_set_mode(enum clock_event_mode mode,
                decrementer_set_next_event(DECREMENTER_MAX, dev);
 }
+static void __init setup_clockevent_multiplier(unsigned long hz)
+{
+        u64 mult, shift = 32;
+        while (1) {
+                mult = div_sc(hz, NSEC_PER_SEC, shift);
+                if (mult && (mult >> 32UL) == 0UL)
+                        break;
+                shift--;
+        }
+        decrementer_clockevent.shift = shift;
+        decrementer_clockevent.mult = mult;
+}
 static void register_decrementer_clockevent(int cpu)
 {
        struct clock_event_device *dec = &per_cpu(decrementers, cpu).event;
@@ -860,8 +877,7 @@ static void __init init_decrementer_clockevent(void)
 {
        int cpu = smp_processor_id();
-        decrementer_clockevent.mult = div_sc(ppc_tb_freq, NSEC_PER_SEC,
+        setup_clockevent_multiplier(ppc_tb_freq);
-                                             decrementer_clockevent.shift);
        decrementer_clockevent.max_delta_ns =
                clockevent_delta2ns(DECREMENTER_MAX, &decrementer_clockevent);
        decrementer_clockevent.min_delta_ns =
@@ -1128,6 +1144,15 @@ void div128_by_32(u64 dividend_high, u64 dividend_low,
 }
+/* We don't need to calibrate delay, we use the CPU timebase for that */
+void calibrate_delay(void)
+{
+        /* Some generic code (such as spinlock debug) use loops_per_jiffy
+         * as the number of __delay(1) in a jiffy, so make it so
+         */
+        loops_per_jiffy = tb_ticks_per_jiffy;
+}
 static int __init rtc_init(void)
 {
        struct platform_device *pdev;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 678fbff0d206..6f0ae1a9bfae 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -33,7 +33,9 @@
 #include <linux/backlight.h>
 #include <linux/bug.h>
 #include <linux/kdebug.h>
+#include <linux/debugfs.h>
+#include <asm/emulated_ops.h>
 #include <asm/pgtable.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
@@ -757,36 +759,44 @@ static int emulate_instruction(struct pt_regs *regs)
        /* Emulate the mfspr rD, PVR. */
        if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
+                PPC_WARN_EMULATED(mfpvr);
                rd = (instword >> 21) & 0x1f;
                regs->gpr[rd] = mfspr(SPRN_PVR);
                return 0;
        }
        /* Emulating the dcba insn is just a no-op.  */
-        if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA)
+        if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
+                PPC_WARN_EMULATED(dcba);
                return 0;
+        }
        /* Emulate the mcrxr insn.  */
        if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
                int shift = (instword >> 21) & 0x1c;
                unsigned long msk = 0xf0000000UL >> shift;
+                PPC_WARN_EMULATED(mcrxr);
                regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
                regs->xer &= ~0xf0000000UL;
                return 0;
        }
        /* Emulate load/store string insn. */
-        if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING)
+        if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
+                PPC_WARN_EMULATED(string);
                return emulate_string_inst(regs, instword);
+        }
        /* Emulate the popcntb (Population Count Bytes) instruction. */
        if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
+                PPC_WARN_EMULATED(popcntb);
                return emulate_popcntb_inst(regs, instword);
        }
        /* Emulate isel (Integer Select) instruction */
        if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
+                PPC_WARN_EMULATED(isel);
                return emulate_isel(regs, instword);
        }
@@ -984,6 +994,8 @@ void SoftwareEmulation(struct pt_regs *regs)
 #ifdef CONFIG_MATH_EMULATION
        errcode = do_mathemu(regs);
+        if (errcode >= 0)
+                PPC_WARN_EMULATED(math);
        switch (errcode) {
        case 0:
@@ -1005,6 +1017,9 @@ void SoftwareEmulation(struct pt_regs *regs)
 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
        errcode = Soft_emulate_8xx(regs);
+        if (errcode >= 0)
+                PPC_WARN_EMULATED(8xx);
        switch (errcode) {
        case 0:
                emulate_single_step(regs);
@@ -1026,7 +1041,34 @@ void SoftwareEmulation(struct pt_regs *regs)
 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
 {
-        if (debug_status & DBSR_IC) {   /* instruction completion */
+        /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
+         * on server, it stops on the target of the branch. In order to simulate
+         * the server behaviour, we thus restart right away with a single step
+         * instead of stopping here when hitting a BT
+         */
+        if (debug_status & DBSR_BT) {
+                regs->msr &= ~MSR_DE;
+                /* Disable BT */
+                mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
+                /* Clear the BT event */
+                mtspr(SPRN_DBSR, DBSR_BT);
+                /* Do the single step trick only when coming from userspace */
+                if (user_mode(regs)) {
+                        current->thread.dbcr0 &= ~DBCR0_BT;
+                        current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
+                        regs->msr |= MSR_DE;
+                        return;
+                }
+                if (notify_die(DIE_SSTEP, "block_step", regs, 5,
+                               5, SIGTRAP) == NOTIFY_STOP) {
+                        return;
+                }
+                if (debugger_sstep(regs))
+                        return;
+        } else if (debug_status & DBSR_IC) {    /* Instruction complete */
                regs->msr &= ~MSR_DE;
                /* Disable instruction completion */
@@ -1042,9 +1084,8 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
                if (debugger_sstep(regs))
                        return;
-                if (user_mode(regs)) {
+                if (user_mode(regs))
-                        current->thread.dbcr0 &= ~DBCR0_IC;
+                        current->thread.dbcr0 &= ~(DBCR0_IC);
-                }
                _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
        } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
@@ -1088,6 +1129,7 @@ void altivec_assist_exception(struct pt_regs *regs)
        flush_altivec_to_thread(current);
+        PPC_WARN_EMULATED(altivec);
        err = emulate_altivec(regs);
        if (err == 0) {
                regs->nip += 4;         /* skip emulated instruction */
@@ -1286,3 +1328,79 @@ void kernel_bad_stack(struct pt_regs *regs)
 void __init trap_init(void)
 {
 }
+#ifdef CONFIG_PPC_EMULATED_STATS
+#define WARN_EMULATED_SETUP(type)       .type = { .name = #type }
+struct ppc_emulated ppc_emulated = {
+#ifdef CONFIG_ALTIVEC
+        WARN_EMULATED_SETUP(altivec),
+#endif
+        WARN_EMULATED_SETUP(dcba),
+        WARN_EMULATED_SETUP(dcbz),
+        WARN_EMULATED_SETUP(fp_pair),
+        WARN_EMULATED_SETUP(isel),
+        WARN_EMULATED_SETUP(mcrxr),
+        WARN_EMULATED_SETUP(mfpvr),
+        WARN_EMULATED_SETUP(multiple),
+        WARN_EMULATED_SETUP(popcntb),
+        WARN_EMULATED_SETUP(spe),
+        WARN_EMULATED_SETUP(string),
+        WARN_EMULATED_SETUP(unaligned),
+#ifdef CONFIG_MATH_EMULATION
+        WARN_EMULATED_SETUP(math),
+#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
+        WARN_EMULATED_SETUP(8xx),
+#endif
+#ifdef CONFIG_VSX
+        WARN_EMULATED_SETUP(vsx),
+#endif
+};
+u32 ppc_warn_emulated;
+void ppc_warn_emulated_print(const char *type)
+{
+        if (printk_ratelimit())
+                pr_warning("%s used emulated %s instruction\n", current->comm,
+                           type);
+}
+static int __init ppc_warn_emulated_init(void)
+{
+        struct dentry *dir, *d;
+        unsigned int i;
+        struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
+        if (!powerpc_debugfs_root)
+                return -ENODEV;
+        dir = debugfs_create_dir("emulated_instructions",
+                                 powerpc_debugfs_root);
+        if (!dir)
+                return -ENOMEM;
+        d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
+                               &ppc_warn_emulated);
+        if (!d)
+                goto fail;
+        for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
+                d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
+                                       (u32 *)&entries[i].val.counter);
+                if (!d)
+                        goto fail;
+        }
+        return 0;
+fail:
+        debugfs_remove_recursive(dir);
+        return -ENOMEM;
+}
+device_initcall(ppc_warn_emulated_init);
+#endif /* CONFIG_PPC_EMULATED_STATS */
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index 49ac3d6e1399..ef36cbbc5882 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -1,5 +1,215 @@
+#include <asm/processor.h>
 #include <asm/ppc_asm.h>
 #include <asm/reg.h>
+#include <asm/asm-offsets.h>
+#include <asm/cputable.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
+/*
+ * load_up_altivec(unused, unused, tsk)
+ * Disable VMX for the task which had it previously,
+ * and save its vector registers in its thread_struct.
+ * Enables the VMX for use in the kernel on return.
+ * On SMP we know the VMX is free, since we give it up every
+ * switch (ie, no lazy save of the vector registers).
+ */
+_GLOBAL(load_up_altivec)
+        mfmsr   r5                      /* grab the current MSR */
+        oris    r5,r5,MSR_VEC@h
+        MTMSRD(r5)                      /* enable use of AltiVec now */
+        isync
+/*
+ * For SMP, we don't do lazy VMX switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another.  Instead we call giveup_altvec in switch_to.
+ * VRSAVE isn't dealt with here, that is done in the normal context
+ * switch code. Note that we could rely on vrsave value to eventually
+ * avoid saving all of the VREGs here...
+ */
+#ifndef CONFIG_SMP
+        LOAD_REG_ADDRBASE(r3, last_task_used_altivec)
+        toreal(r3)
+        PPC_LL  r4,ADDROFF(last_task_used_altivec)(r3)
+        PPC_LCMPI       0,r4,0
+        beq     1f
+        /* Save VMX state to last_task_used_altivec's THREAD struct */
+        toreal(r4)
+        addi    r4,r4,THREAD
+        SAVE_32VRS(0,r5,r4)
+        mfvscr  vr0
+        li      r10,THREAD_VSCR
+        stvx    vr0,r10,r4
+        /* Disable VMX for last_task_used_altivec */
+        PPC_LL  r5,PT_REGS(r4)
+        toreal(r5)
+        PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+        lis     r10,MSR_VEC@h
+        andc    r4,r4,r10
+        PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+        /* Hack: if we get an altivec unavailable trap with VRSAVE
+         * set to all zeros, we assume this is a broken application
+         * that fails to set it properly, and thus we switch it to
+         * all 1's
+         */
+        mfspr   r4,SPRN_VRSAVE
+        cmpdi   0,r4,0
+        bne+    1f
+        li      r4,-1
+        mtspr   SPRN_VRSAVE,r4
+1:
+        /* enable use of VMX after return */
+#ifdef CONFIG_PPC32
+        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
+        oris    r9,r9,MSR_VEC@h
+#else
+        ld      r4,PACACURRENT(r13)
+        addi    r5,r4,THREAD            /* Get THREAD */
+        oris    r12,r12,MSR_VEC@h
+        std     r12,_MSR(r1)
+#endif
+        li      r4,1
+        li      r10,THREAD_VSCR
+        stw     r4,THREAD_USED_VR(r5)
+        lvx     vr0,r10,r5
+        mtvscr  vr0
+        REST_32VRS(0,r4,r5)
+#ifndef CONFIG_SMP
+        /* Update last_task_used_math to 'current' */
+        subi    r4,r5,THREAD            /* Back to 'current' */
+        fromreal(r4)
+        PPC_STL r4,ADDROFF(last_task_used_math)(r3)
+#endif /* CONFIG_SMP */
+        /* restore registers and return */
+        blr
+/*
+ * giveup_altivec(tsk)
+ * Disable VMX for the task given as the argument,
+ * and save the vector registers in its thread_struct.
+ * Enables the VMX for use in the kernel on return.
+ */
+_GLOBAL(giveup_altivec)
+        mfmsr   r5
+        oris    r5,r5,MSR_VEC@h
+        SYNC
+        MTMSRD(r5)                      /* enable use of VMX now */
+        isync
+        PPC_LCMPI       0,r3,0
+        beqlr-                          /* if no previous owner, done */
+        addi    r3,r3,THREAD            /* want THREAD of task */
+        PPC_LL  r5,PT_REGS(r3)
+        PPC_LCMPI       0,r5,0
+        SAVE_32VRS(0,r4,r3)
+        mfvscr  vr0
+        li      r4,THREAD_VSCR
+        stvx    vr0,r4,r3
+        beq     1f
+        PPC_LL  r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+#ifdef CONFIG_VSX
+BEGIN_FTR_SECTION
+        lis     r3,(MSR_VEC|MSR_VSX)@h
+FTR_SECTION_ELSE
+        lis     r3,MSR_VEC@h
+ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
+#else
+        lis     r3,MSR_VEC@h
+#endif
+        andc    r4,r4,r3                /* disable FP for previous task */
+        PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+        li      r5,0
+        LOAD_REG_ADDRBASE(r4,last_task_used_altivec)
+        PPC_STL r5,ADDROFF(last_task_used_altivec)(r4)
+#endif /* CONFIG_SMP */
+        blr
+#ifdef CONFIG_VSX
+#ifdef CONFIG_PPC32
+#error This asm code isn't ready for 32-bit kernels
+#endif
+/*
+ * load_up_vsx(unused, unused, tsk)
+ * Disable VSX for the task which had it previously,
+ * and save its vector registers in its thread_struct.
+ * Reuse the fp and vsx saves, but first check to see if they have
+ * been saved already.
+ */
+_GLOBAL(load_up_vsx)
+/* Load FP and VSX registers if they haven't been done yet */
+        andi.   r5,r12,MSR_FP
+        beql+   load_up_fpu             /* skip if already loaded */
+        andis.  r5,r12,MSR_VEC@h
+        beql+   load_up_altivec         /* skip if already loaded */
+#ifndef CONFIG_SMP
+        ld      r3,last_task_used_vsx@got(r2)
+        ld      r4,0(r3)
+        cmpdi   0,r4,0
+        beq     1f
+        /* Disable VSX for last_task_used_vsx */
+        addi    r4,r4,THREAD
+        ld      r5,PT_REGS(r4)
+        ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+        lis     r6,MSR_VSX@h
+        andc    r6,r4,r6
+        std     r6,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+        ld      r4,PACACURRENT(r13)
+        addi    r4,r4,THREAD            /* Get THREAD */
+        li      r6,1
+        stw     r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
+        /* enable use of VSX after return */
+        oris    r12,r12,MSR_VSX@h
+        std     r12,_MSR(r1)
+#ifndef CONFIG_SMP
+        /* Update last_task_used_math to 'current' */
+        ld      r4,PACACURRENT(r13)
+        std     r4,0(r3)
+#endif /* CONFIG_SMP */
+        b       fast_exception_return
+/*
+ * __giveup_vsx(tsk)
+ * Disable VSX for the task given as the argument.
+ * Does NOT save vsx registers.
+ * Enables the VSX for use in the kernel on return.
+ */
+_GLOBAL(__giveup_vsx)
+        mfmsr   r5
+        oris    r5,r5,MSR_VSX@h
+        mtmsrd  r5                      /* enable use of VSX now */
+        isync
+        cmpdi   0,r3,0
+        beqlr-                          /* if no previous owner, done */
+        addi    r3,r3,THREAD            /* want THREAD of task */
+        ld      r5,PT_REGS(r3)
+        cmpdi   0,r5,0
+        beq     1f
+        ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+        lis     r3,MSR_VSX@h
+        andc    r4,r4,r3                /* disable VSX for previous task */
+        std     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+        li      r5,0
+        ld      r4,last_task_used_vsx@got(r2)
+        std     r5,0(r4)
+#endif /* CONFIG_SMP */
+        blr
+#endif /* CONFIG_VSX */
 /*
 * The routines below are in assembler so we can closely control the
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index b746f4ca4209..c4bcf072cb3c 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -11,10 +11,11 @@ obj-y				:= fault.o mem.o pgtable.o gup.o \
                                   pgtable_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_PPC_MMU_NOHASH)    += mmu_context_nohash.o tlb_nohash.o \
                                   tlb_nohash_low.o
-hash-$(CONFIG_PPC_NATIVE)       := hash_native_64.o
+obj-$(CONFIG_PPC64)             += mmap_64.o
-obj-$(CONFIG_PPC64)             += hash_utils_64.o \
+hash64-$(CONFIG_PPC_NATIVE)     := hash_native_64.o
+obj-$(CONFIG_PPC_STD_MMU_64)    += hash_utils_64.o \
                                   slb_low.o slb.o stab.o \
-                                   mmap_64.o $(hash-y)
+                                   mmap_64.o $(hash64-y)
 obj-$(CONFIG_PPC_STD_MMU_32)    += ppc_mmu_32.o
 obj-$(CONFIG_PPC_STD_MMU)       += hash_low_$(CONFIG_WORD_SIZE).o \
                                   tlb_hash$(CONFIG_WORD_SIZE).o \
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 34e5c0b219b9..056d23a1b105 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -27,6 +27,7 @@
 #include <asm/cputable.h>
 #include <asm/udbg.h>
 #include <asm/kexec.h>
+#include <asm/ppc-opcode.h>
 #ifdef DEBUG_LOW
 #define DBG_LOW(fmt...) udbg_printf(fmt)
@@ -49,14 +50,21 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
        case MMU_PAGE_4K:
                va &= ~0xffful;
                va |= ssize << 8;
-                asm volatile("tlbie %0,0" : : "r" (va) : "memory");
+                asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),
+                                               %2)
+                             : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+                             : "memory");
                break;
        default:
                penc = mmu_psize_defs[psize].penc;
                va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
                va |= penc << 12;
                va |= ssize << 8;
-                asm volatile("tlbie %0,1" : : "r" (va) : "memory");
+                va |= 1; /* L */
+                asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),
+                                               %2)
+                             : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+                             : "memory");
                break;
        }
 }
@@ -80,6 +88,7 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
                va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
                va |= penc << 12;
                va |= ssize << 8;
+                va |= 1; /* L */
                asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
                             : : "r"(va) : "memory");
                break;
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index 3e6a6543f53a..68a821add28d 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -66,6 +66,7 @@
 #include "mmu_decl.h"
+#ifdef CONFIG_PPC_STD_MMU_64
 #if PGTABLE_RANGE > USER_VSID_RANGE
 #warning Limited user VSID range means pagetable space is wasted
 #endif
@@ -73,6 +74,7 @@
 #if (TASK_SIZE_USER64 < PGTABLE_RANGE) && (TASK_SIZE_USER64 < USER_VSID_RANGE)
 #warning TASK_SIZE is smaller than it needs to be.
 #endif
+#endif /* CONFIG_PPC_STD_MMU_64 */
 phys_addr_t memstart_addr = ~0;
 phys_addr_t kernstart_addr;
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index 030d0005b4d2..8343986809c0 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -46,7 +46,7 @@ static unsigned int next_context, nr_free_contexts;
 static unsigned long *context_map;
 static unsigned long *stale_map[NR_CPUS];
 static struct mm_struct **context_mm;
-static spinlock_t context_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_SPINLOCK(context_lock);
 #define CTX_MAP_SIZE    \
        (sizeof(unsigned long) * (last_context / BITS_PER_LONG + 1))
@@ -73,7 +73,6 @@ static unsigned int steal_context_smp(unsigned int id)
        struct mm_struct *mm;
        unsigned int cpu, max;
- again:
        max = last_context - first_context;
        /* Attempt to free next_context first and then loop until we manage */
@@ -108,7 +107,9 @@ static unsigned int steal_context_smp(unsigned int id)
        spin_unlock(&context_lock);
        cpu_relax();
        spin_lock(&context_lock);
-        goto again;
+        /* This will cause the caller to try again */
+        return MMU_NO_CONTEXT;
 }
 #endif  /* CONFIG_SMP */
@@ -194,6 +195,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
                WARN_ON(prev->context.active < 1);
                prev->context.active--;
        }
+ again:
 #endif /* CONFIG_SMP */
        /* If we already have a valid assigned context, skip all that */
@@ -212,7 +215,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 #ifdef CONFIG_SMP
                if (num_online_cpus() > 1) {
                        id = steal_context_smp(id);
-                        goto stolen;
+                        if (id == MMU_NO_CONTEXT)
+                                goto again;
                }
 #endif /* CONFIG_SMP */
                id = steal_context_up(id);
@@ -272,6 +276,7 @@ int init_new_context(struct task_struct *t, struct mm_struct *mm)
 */
 void destroy_context(struct mm_struct *mm)
 {
+        unsigned long flags;
        unsigned int id;
        if (mm->context.id == MMU_NO_CONTEXT)
@@ -279,18 +284,18 @@ void destroy_context(struct mm_struct *mm)
        WARN_ON(mm->context.active != 0);
-        spin_lock(&context_lock);
+        spin_lock_irqsave(&context_lock, flags);
        id = mm->context.id;
        if (id != MMU_NO_CONTEXT) {
                __clear_bit(id, context_map);
                mm->context.id = MMU_NO_CONTEXT;
 #ifdef DEBUG_MAP_CONSISTENCY
                mm->context.active = 0;
-                context_mm[id] = NULL;
 #endif
+                context_mm[id] = NULL;
                nr_free_contexts++;
        }
-        spin_unlock(&context_lock);
+        spin_unlock_irqrestore(&context_lock, flags);
 }
 #ifdef CONFIG_SMP
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 9047145095aa..b037d95eeadc 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -981,6 +981,8 @@ void __init do_init_bootmem(void)
                mark_reserved_regions_for_nid(nid);
                sparse_memory_present_with_active_regions(nid);
        }
+        init_bootmem_done = 1;
 }
 void __init paging_init(void)
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 89497fb04280..3b52c80e5e33 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -2,7 +2,7 @@
 * PowerPC64 SLB support.
 *
 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
- * Based on earlier code writteh by:
+ * Based on earlier code written by:
 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
 *    Copyright (c) 2001 Dave Engebretsen
 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
diff --git a/arch/powerpc/oprofile/op_model_fsl_emb.c b/arch/powerpc/oprofile/op_model_fsl_emb.c
index 91596f6ba1f4..62312abffa28 100644
--- a/arch/powerpc/oprofile/op_model_fsl_emb.c
+++ b/arch/powerpc/oprofile/op_model_fsl_emb.c
@@ -228,20 +228,6 @@ static void pmc_stop_ctrs(void)
        mtpmr(PMRN_PMGC0, pmgc0);
 }
-static void dump_pmcs(void)
-{
-        printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0));
-        printk("pmc\t\tpmlca\t\tpmlcb\n");
-        printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0),
-                        mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0));
-        printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1),
-                        mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1));
-        printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2),
-                        mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2));
-        printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3),
-                        mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
-}
 static int fsl_emb_cpu_setup(struct op_counter_config *ctr)
 {
        int i;
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index f39c953d5353..a6e43cb6f825 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -45,6 +45,7 @@ config KILAUEA
        depends on 40x
        default n
        select 405EX
+        select PPC40x_SIMPLE
        select PPC4xx_PCI_EXPRESS
        help
          This option enables support for the AMCC PPC405EX evaluation board.
@@ -56,6 +57,7 @@ config MAKALU
        select 405EX
        select PCI
        select PPC4xx_PCI_EXPRESS
+        select PPC40x_SIMPLE
        help
          This option enables support for the AMCC PPC405EX board.
diff --git a/arch/powerpc/platforms/40x/Makefile b/arch/powerpc/platforms/40x/Makefile
index 9bab76a652a6..56e89004c468 100644
--- a/arch/powerpc/platforms/40x/Makefile
+++ b/arch/powerpc/platforms/40x/Makefile
@@ -1,6 +1,4 @@
-obj-$(CONFIG_KILAUEA)                           += kilauea.o
 obj-$(CONFIG_HCU4)                              += hcu4.o
-obj-$(CONFIG_MAKALU)                            += makalu.o
 obj-$(CONFIG_WALNUT)                            += walnut.o
 obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD)       += virtex.o
 obj-$(CONFIG_EP405)                             += ep405.o
diff --git a/arch/powerpc/platforms/40x/kilauea.c b/arch/powerpc/platforms/40x/kilauea.c
deleted file mode 100644
index fd7d934dac8b..000000000000
--- a/arch/powerpc/platforms/40x/kilauea.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Kilauea board specific routines
- *
- * Copyright 2007-2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * Based on the Walnut code by
- * Josh Boyer <jwboyer@linux.vnet.ibm.com>
- * Copyright 2007 IBM Corporation
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/time.h>
-#include <asm/uic.h>
-#include <asm/pci-bridge.h>
-#include <asm/ppc4xx.h>
-static __initdata struct of_device_id kilauea_of_bus[] = {
-        { .compatible = "ibm,plb4", },
-        { .compatible = "ibm,opb", },
-        { .compatible = "ibm,ebc", },
-        {},
-};
-static int __init kilauea_device_probe(void)
-{
-        of_platform_bus_probe(NULL, kilauea_of_bus, NULL);
-        return 0;
-}
-machine_device_initcall(kilauea, kilauea_device_probe);
-static int __init kilauea_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-        if (!of_flat_dt_is_compatible(root, "amcc,kilauea"))
-                return 0;
-        ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
-        return 1;
-}
-define_machine(kilauea) {
-        .name                           = "Kilauea",
-        .probe                          = kilauea_probe,
-        .progress                       = udbg_progress,
-        .init_IRQ                       = uic_init_tree,
-        .get_irq                        = uic_get_irq,
-        .restart                        = ppc4xx_reset_system,
-        .calibrate_decr                 = generic_calibrate_decr,
-};
diff --git a/arch/powerpc/platforms/40x/makalu.c b/arch/powerpc/platforms/40x/makalu.c
deleted file mode 100644
index a6a1d6017b71..000000000000
--- a/arch/powerpc/platforms/40x/makalu.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Makalu board specific routines
- *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * Based on the Walnut code by
- * Josh Boyer <jwboyer@linux.vnet.ibm.com>
- * Copyright 2007 IBM Corporation
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/udbg.h>
-#include <asm/time.h>
-#include <asm/uic.h>
-#include <asm/pci-bridge.h>
-#include <asm/ppc4xx.h>
-static __initdata struct of_device_id makalu_of_bus[] = {
-        { .compatible = "ibm,plb4", },
-        { .compatible = "ibm,opb", },
-        { .compatible = "ibm,ebc", },
-        {},
-};
-static int __init makalu_device_probe(void)
-{
-        of_platform_bus_probe(NULL, makalu_of_bus, NULL);
-        return 0;
-}
-machine_device_initcall(makalu, makalu_device_probe);
-static int __init makalu_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-        if (!of_flat_dt_is_compatible(root, "amcc,makalu"))
-                return 0;
-        ppc_pci_flags = PPC_PCI_REASSIGN_ALL_RSRC;
-        return 1;
-}
-define_machine(makalu) {
-        .name                           = "Makalu",
-        .probe                          = makalu_probe,
-        .progress                       = udbg_progress,
-        .init_IRQ                       = uic_init_tree,
-        .get_irq                        = uic_get_irq,
-        .restart                        = ppc4xx_reset_system,
-        .calibrate_decr                 = generic_calibrate_decr,
-};
diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c
index f40ac9b8f99f..5fd5a5974001 100644
--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
@@ -51,7 +51,10 @@ machine_device_initcall(ppc40x_simple, ppc40x_device_probe);
 * board.c file for it rather than adding it to this list.
 */
 static char *board[] __initdata = {
-        "amcc,acadia"
+        "amcc,acadia",
+        "amcc,haleakala",
+        "amcc,kilauea",
+        "amcc,makalu"
 };
 static int __init ppc40x_probe(void)
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
index fc7fb001276c..d0fc6866b00c 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -14,6 +14,7 @@
 #include <asm/prom.h>
 #include <asm/time.h>
 #include <asm/xilinx_intc.h>
+#include <asm/xilinx_pci.h>
 #include <asm/ppc4xx.h>
 static struct of_device_id xilinx_of_bus_ids[] __initdata = {
@@ -47,6 +48,7 @@ static int __init virtex_probe(void)
 define_machine(virtex) {
        .name                   = "Xilinx Virtex",
        .probe                  = virtex_probe,
+        .setup_arch             = xilinx_pci_init,
        .init_IRQ               = xilinx_intc_init_tree,
        .get_irq                = xilinx_intc_get_irq,
        .restart                = ppc4xx_reset_system,
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 0d83a6a0397d..90e3192611a4 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -156,7 +156,7 @@ config YOSEMITE
 #         This option enables support for the IBM PPC440GX evaluation board.
 config XILINX_VIRTEX440_GENERIC_BOARD
-        bool "Generic Xilinx Virtex 440 board"
+        bool "Generic Xilinx Virtex 5 FXT board support"
        depends on 44x
        default n
        select XILINX_VIRTEX_5_FXT
@@ -171,6 +171,17 @@ config XILINX_VIRTEX440_GENERIC_BOARD
          Most Virtex 5 designs should use this unless it needs to do some
          special configuration at board probe time.
+config XILINX_ML510
+        bool "Xilinx ML510 extra support"
+        depends on XILINX_VIRTEX440_GENERIC_BOARD
+        select PPC_PCI_CHOICE
+        select XILINX_PCI if PCI
+        select PPC_INDIRECT_PCI if PCI
+        select PPC_I8259 if PCI
+        help
+          This option enables extra support for features on the Xilinx ML510
+          board.  The ML510 has a PCI bus with ALI south bridge.
 config PPC44x_SIMPLE
        bool "Simple PowerPC 44x board support"
        depends on 44x
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 01f51daace13..ee6185aeaa3b 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_EBONY)	+= ebony.o
 obj-$(CONFIG_SAM440EP)  += sam440ep.o
 obj-$(CONFIG_WARP)      += warp.o
 obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
+obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c
index 68637faf70ae..cf96ccaa760c 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -16,6 +16,7 @@
 #include <asm/prom.h>
 #include <asm/time.h>
 #include <asm/xilinx_intc.h>
+#include <asm/xilinx_pci.h>
 #include <asm/reg.h>
 #include <asm/ppc4xx.h>
 #include "44x.h"
@@ -53,6 +54,7 @@ static int __init virtex_probe(void)
 define_machine(virtex) {
        .name                   = "Xilinx Virtex440",
        .probe                  = virtex_probe,
+        .setup_arch             = xilinx_pci_init,
        .init_IRQ               = xilinx_intc_init_tree,
        .get_irq                = xilinx_intc_get_irq,
        .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c b/arch/powerpc/platforms/44x/virtex_ml510.c
new file mode 100644
index 000000000000..ba4a6e388a46
--- /dev/null
+++ b/arch/powerpc/platforms/44x/virtex_ml510.c
@@ -0,0 +1,29 @@
+#include <asm/i8259.h>
+#include <linux/pci.h>
+#include "44x.h"
+/**
+ * ml510_ail_quirk
+ */
+static void __devinit ml510_ali_quirk(struct pci_dev *dev)
+{
+        /* Enable the IDE controller */
+        pci_write_config_byte(dev, 0x58, 0x4c);
+        /* Assign irq 14 to the primary ide channel */
+        pci_write_config_byte(dev, 0x44, 0x0d);
+        /* Assign irq 15 to the secondary ide channel */
+        pci_write_config_byte(dev, 0x75, 0x0f);
+        /* Set the ide controller in native mode */
+        pci_write_config_byte(dev, 0x09, 0xff);
+        /* INTB = disabled, INTA = disabled */
+        pci_write_config_byte(dev, 0x48, 0x00);
+        /* INTD = disabled, INTC = disabled */
+        pci_write_config_byte(dev, 0x4a, 0x00);
+        /* Audio = INT7, Modem = disabled. */
+        pci_write_config_byte(dev, 0x4b, 0x60);
+        /* USB = INT7 */
+        pci_write_config_byte(dev, 0x74, 0x06);
+}
+DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
diff --git a/arch/powerpc/platforms/44x/warp.c b/arch/powerpc/platforms/44x/warp.c
index 960edf89be51..c5118802a281 100644
--- a/arch/powerpc/platforms/44x/warp.c
+++ b/arch/powerpc/platforms/44x/warp.c
@@ -1,7 +1,7 @@
 /*
 * PIKA Warp(tm) board specific routines
 *
- * Copyright (c) 2008 PIKA Technologies
+ * Copyright (c) 2008-2009 PIKA Technologies
 *   Sean MacLennan <smaclennan@pikatech.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
@@ -15,6 +15,7 @@
 #include <linux/i2c.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
+#include <linux/of_gpio.h>
 #include <asm/machdep.h>
 #include <asm/prom.h>
@@ -23,6 +24,7 @@
 #include <asm/uic.h>
 #include <asm/ppc4xx.h>
 static __initdata struct of_device_id warp_of_bus[] = {
        { .compatible = "ibm,plb4", },
        { .compatible = "ibm,opb", },
@@ -55,6 +57,8 @@ define_machine(warp) {
 };
+static u32 post_info;
 /* I am not sure this is the best place for this... */
 static int __init warp_post_info(void)
 {
@@ -77,21 +81,21 @@ static int __init warp_post_info(void)
        iounmap(fpga);
-        if (post1 || post2)
+        if (post1 || post2) {
                printk(KERN_INFO "Warp POST %08x %08x\n", post1, post2);
-        else
+                post_info = 1;
+        } else
                printk(KERN_INFO "Warp POST OK\n");
        return 0;
 }
-machine_late_initcall(warp, warp_post_info);
 #ifdef CONFIG_SENSORS_AD7414
 static LIST_HEAD(dtm_shutdown_list);
 static void __iomem *dtm_fpga;
-static void __iomem *gpio_base;
+static unsigned green_led, red_led;
 struct dtm_shutdown {
@@ -134,14 +138,17 @@ int pika_dtm_unregister_shutdown(void (*func)(void *arg), void *arg)
 static irqreturn_t temp_isr(int irq, void *context)
 {
        struct dtm_shutdown *shutdown;
+        int value = 1;
        local_irq_disable();
+        gpio_set_value(green_led, 0);
        /* Run through the shutdown list. */
        list_for_each_entry(shutdown, &dtm_shutdown_list, list)
                shutdown->func(shutdown->arg);
-        printk(KERN_EMERG "\n\nCritical Temperature Shutdown\n");
+        printk(KERN_EMERG "\n\nCritical Temperature Shutdown\n\n");
        while (1) {
                if (dtm_fpga) {
@@ -149,52 +156,34 @@ static irqreturn_t temp_isr(int irq, void *context)
                        out_be32(dtm_fpga + 0x14, reset);
                }
-                if (gpio_base) {
+                gpio_set_value(red_led, value);
-                        unsigned leds = in_be32(gpio_base);
+                value ^= 1;
-                        /* green off, red toggle */
-                        leds &= ~0x80000000;
-                        leds ^=  0x40000000;
-                        out_be32(gpio_base, leds);
-                }
                mdelay(500);
        }
 }
 static int pika_setup_leds(void)
 {
-        struct device_node *np;
+        struct device_node *np, *child;
-        const u32 *gpios;
-        int len;
-        np = of_find_compatible_node(NULL, NULL, "linux,gpio-led");
+        np = of_find_compatible_node(NULL, NULL, "gpio-leds");
        if (!np) {
-                printk(KERN_ERR __FILE__ ": Unable to find gpio-led\n");
+                printk(KERN_ERR __FILE__ ": Unable to find leds\n");
-                return -ENOENT;
-        }
-        gpios = of_get_property(np, "gpios", &len);
-        of_node_put(np);
-        if (!gpios || len < 4) {
-                printk(KERN_ERR __FILE__
-                       ": Unable to get gpios property (%d)\n", len);
                return -ENOENT;
        }
-        np = of_find_node_by_phandle(gpios[0]);
+        for_each_child_of_node(np, child)
-        if (!np) {
+                if (strcmp(child->name, "green") == 0) {
-                printk(KERN_ERR __FILE__ ": Unable to find gpio\n");
+                        green_led = of_get_gpio(child, 0);
-                return -ENOENT;
+                        /* Turn back on the green LED */
-        }
+                        gpio_set_value(green_led, 1);
+                } else if (strcmp(child->name, "red") == 0) {
+                        red_led = of_get_gpio(child, 0);
+                        /* Set based on post */
+                        gpio_set_value(red_led, post_info);
+                }
-        gpio_base = of_iomap(np, 0);
        of_node_put(np);
-        if (!gpio_base) {
-                printk(KERN_ERR __FILE__ ": Unable to map gpio");
-                return -ENOMEM;
-        }
        return 0;
 }
@@ -270,10 +259,10 @@ static int pika_dtm_thread(void __iomem *fpga)
        }
 found_it:
-        i2c_put_adapter(adap);
        pika_setup_critical_temp(client);
+        i2c_put_adapter(adap);
        printk(KERN_INFO "PIKA DTM thread running.\n");
        while (!kthread_should_stop()) {
@@ -311,6 +300,9 @@ static int __init pika_dtm_start(void)
        if (dtm_fpga == NULL)
                return -ENOENT;
+        /* Must get post info before thread starts. */
+        warp_post_info();
        dtm_thread = kthread_run(pika_dtm_thread, dtm_fpga, "pika-dtm");
        if (IS_ERR(dtm_thread)) {
                iounmap(dtm_fpga);
@@ -333,6 +325,8 @@ int pika_dtm_unregister_shutdown(void (*func)(void *arg), void *arg)
        return 0;
 }
+machine_late_initcall(warp, warp_post_info);
 #endif
 EXPORT_SYMBOL(pika_dtm_register_shutdown);
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c
index a2068faef6ea..bcc69e1f77c1 100644
--- a/arch/powerpc/platforms/52xx/efika.c
+++ b/arch/powerpc/platforms/52xx/efika.c
@@ -34,7 +34,7 @@
 static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
                            int len, u32 * val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
            | (((bus->number - hose->first_busno) & 0xff) << 16)
            | (hose->global_number << 24);
@@ -49,7 +49,7 @@ static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
 static int rtas_write_config(struct pci_bus *bus, unsigned int devfn,
                             int offset, int len, u32 val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
            | (((bus->number - hose->first_busno) & 0xff) << 16)
            | (hose->global_number << 24);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
index 87ff522f28b5..dd43114e9684 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pci.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
@@ -107,7 +107,7 @@ static int
 mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                int offset, int len, u32 *val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        u32 value;
        if (ppc_md.pci_exclude_device)
@@ -164,7 +164,7 @@ static int
 mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                                int offset, int len, u32 val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        u32 value, mask;
        if (ppc_md.pci_exclude_device)
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 0eb6d7f62241..51fcae41f08a 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -14,6 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/fsl_devices.h>
 #include <linux/mdio-bitbang.h>
+#include <linux/of_mdio.h>
 #include <linux/of_platform.h>
 #include <asm/io.h>
@@ -115,7 +116,7 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev,
        struct mii_bus *bus;
        struct resource res;
        struct device_node *node;
-        int ret, i;
+        int ret;
        node = of_get_parent(ofdev->node);
        of_node_put(node);
@@ -130,17 +131,13 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev,
        if (!bus)
                return -ENOMEM;
-        bus->phy_mask = 0;
        bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
-        for (i = 0; i < PHY_MAX_ADDR; i++)
-                bus->irq[i] = -1;
        bus->name = "ep8248e-mdio-bitbang";
        bus->parent = &ofdev->dev;
        snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
-        return mdiobus_register(bus);
+        return of_mdiobus_register(bus, ofdev->node);
 }
 static int ep8248e_mdio_remove(struct of_device *ofdev)
diff --git a/arch/powerpc/platforms/82xx/pq2ads.h b/arch/powerpc/platforms/82xx/pq2ads.h
index 984db42cc8e7..6cf0f97486e2 100644
--- a/arch/powerpc/platforms/82xx/pq2ads.h
+++ b/arch/powerpc/platforms/82xx/pq2ads.h
@@ -24,10 +24,6 @@
 #include <linux/seq_file.h>
-/* Backword-compatibility stuff for the drivers */
-#define CPM_MAP_ADDR            ((uint)0xf0000000)
-#define CPM_IRQ_OFFSET 0
 /* The ADS8260 has 16, 32-bit wide control/status registers, accessed
 * only on word boundaries.
 * Not all are used (yet), or are interesting to us (yet).
@@ -44,14 +40,5 @@
 #define BCSR3_FETHIEN2          ((uint)0x10000000)      /* 0 == enable*/
 #define BCSR3_FETH2_RST         ((uint)0x80000000)      /* 0 == reset */
-/* cpm serial driver works with constants below */
-#define SIU_INT_SMC1            ((uint)0x04+CPM_IRQ_OFFSET)
-#define SIU_INT_SMC2            ((uint)0x05+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC1            ((uint)0x28+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC2            ((uint)0x29+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC3            ((uint)0x2a+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC4            ((uint)0x2b+CPM_IRQ_OFFSET)
 #endif /* __MACH_ADS8260_DEFS */
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 7f066adc068c..43d385cedcd7 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -34,6 +34,7 @@ config MPC85xx_MDS
        bool "Freescale MPC85xx MDS"
        select DEFAULT_UIMAGE
        select PHYLIB
+        select HAS_RAPIDIO
        help
          This option enables support for the MPC85xx MDS board
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index de66de7a9ca2..53d5851a6c97 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -163,7 +163,8 @@ static void __init mpc85xx_ds_setup_arch(void)
 #ifdef CONFIG_PCI
        for_each_node_by_type(np, "pci") {
                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
+                    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
+                    of_device_is_compatible(np, "fsl,p2020-pcie")) {
                        struct resource rsrc;
                        of_address_to_resource(np, 0, &rsrc);
                        if ((rsrc.start & 0xfffff) == primary_phb_addr)
@@ -195,9 +196,9 @@ static int __init mpc8544_ds_probe(void)
                primary_phb_addr = 0xb000;
 #endif
                return 1;
-        } else {
-                return 0;
        }
+        return 0;
 }
 static struct of_device_id __initdata mpc85xxds_ids[] = {
@@ -214,6 +215,7 @@ static int __init mpc85xxds_publish_devices(void)
 }
 machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
 machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
+machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
 /*
 * Called very early, device-tree isn't unflattened
@@ -227,9 +229,26 @@ static int __init mpc8572_ds_probe(void)
                primary_phb_addr = 0x8000;
 #endif
                return 1;
-        } else {
-                return 0;
        }
+        return 0;
+}
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p2020_ds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+        if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
+#ifdef CONFIG_PCI
+                primary_phb_addr = 0x9000;
+#endif
+                return 1;
+        }
+        return 0;
 }
 define_machine(mpc8544_ds) {
@@ -259,3 +278,17 @@ define_machine(mpc8572_ds) {
        .calibrate_decr         = generic_calibrate_decr,
        .progress               = udbg_progress,
 };
+define_machine(p2020_ds) {
+        .name                   = "P2020 DS",
+        .probe                  = p2020_ds_probe,
+        .setup_arch             = mpc85xx_ds_setup_arch,
+        .init_IRQ               = mpc85xx_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 7dd029034aec..b2c0a4319973 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -206,23 +206,24 @@ static void __init mpc85xx_mds_setup_arch(void)
        }
        if (bcsr_regs) {
+                if (machine_is(mpc8568_mds)) {
 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
-                /* Turn off UCC1 & UCC2 */
+                        /* Turn off UCC1 & UCC2 */
-                clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                        clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+                        clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
-                /* Mode is RGMII, all bits clear */
+                        /* Mode is RGMII, all bits clear */
-                clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+                        clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
-                                         BCSR_UCC2_MODE_MSK);
+                                                 BCSR_UCC2_MODE_MSK);
-                /* Turn UCC1 & UCC2 on */
-                setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+                        /* Turn UCC1 & UCC2 on */
+                        setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                        setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+                }
                iounmap(bcsr_regs);
        }
 #endif  /* CONFIG_QUICC_ENGINE */
@@ -257,7 +258,8 @@ static int __init board_fixups(void)
        return 0;
 }
-machine_arch_initcall(mpc85xx_mds, board_fixups);
+machine_arch_initcall(mpc8568_mds, board_fixups);
+machine_arch_initcall(mpc8569_mds, board_fixups);
 static struct of_device_id mpc85xx_ids[] = {
        { .type = "soc", },
@@ -276,7 +278,8 @@ static int __init mpc85xx_publish_devices(void)
        return 0;
 }
-machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices);
+machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
+machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
 static void __init mpc85xx_mds_pic_init(void)
 {
@@ -321,8 +324,8 @@ static int __init mpc85xx_mds_probe(void)
        return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 }
-define_machine(mpc85xx_mds) {
+define_machine(mpc8568_mds) {
-        .name           = "MPC85xx MDS",
+        .name           = "MPC8568 MDS",
        .probe          = mpc85xx_mds_probe,
        .setup_arch     = mpc85xx_mds_setup_arch,
        .init_IRQ       = mpc85xx_mds_pic_init,
@@ -334,3 +337,24 @@ define_machine(mpc85xx_mds) {
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 #endif
 };
+static int __init mpc8569_mds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+        return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
+}
+define_machine(mpc8569_mds) {
+        .name           = "MPC8569 MDS",
+        .probe          = mpc8569_mds_probe,
+        .setup_arch     = mpc85xx_mds_setup_arch,
+        .init_IRQ       = mpc85xx_mds_pic_init,
+        .get_irq        = mpic_get_irq,
+        .restart        = fsl_rstcr_restart,
+        .calibrate_decr = generic_calibrate_decr,
+        .progress       = udbg_progress,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+};
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index d79104669cdc..2efa052975e6 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -28,7 +28,6 @@
 #include <asm/time.h>
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
-#include <asm/mpc86xx.h>
 #include <asm/prom.h>
 #include <mm/mmu_decl.h>
 #include <asm/udbg.h>
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index af14f852d747..90754e752bd8 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -28,7 +28,6 @@
 #include <asm/time.h>
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
-#include <asm/mpc86xx.h>
 #include <asm/prom.h>
 #include <mm/mmu_decl.h>
 #include <asm/udbg.h>
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index ea2360639652..72b31a6010a0 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -28,7 +28,6 @@
 #include <asm/time.h>
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
-#include <asm/mpc86xx.h>
 #include <asm/prom.h>
 #include <mm/mmu_decl.h>
 #include <asm/udbg.h>
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 3f49a6f893a3..51eec0cd5519 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -28,7 +28,6 @@
 #include <asm/time.h>
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
-#include <asm/mpc86xx.h>
 #include <asm/prom.h>
 #include <mm/mmu_decl.h>
 #include <asm/udbg.h>
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index c4ec49b5f7f8..7e9e83c04a8a 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -24,7 +24,6 @@
 #include <asm/time.h>
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
-#include <asm/mpc86xx.h>
 #include <asm/prom.h>
 #include <mm/mmu_decl.h>
 #include <asm/udbg.h>
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
index 014e26cda08d..d84bbb508ee7 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
@@ -20,7 +20,6 @@
 #include <asm/pgtable.h>
 #include <asm/pci-bridge.h>
 #include <asm/mpic.h>
-#include <asm/mpc86xx.h>
 #include <asm/cacheflush.h>
 #include <sysdev/fsl_soc.h>
@@ -30,6 +29,11 @@
 extern void __secondary_start_mpc86xx(void);
 extern unsigned long __secondary_hold_acknowledge;
+#define MCM_PORT_CONFIG_OFFSET  0x10
+/* Offset from CCSRBAR */
+#define MPC86xx_MCM_OFFSET      (0x1000)
+#define MPC86xx_MCM_SIZE        (0x1000)
 static void __init
 smp_86xx_release_core(int nr)
@@ -48,6 +52,8 @@ smp_86xx_release_core(int nr)
        pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2));
        pcr |= 1 << (nr + 24);
        out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr);
+        iounmap(mcm_vaddr);
 }
diff --git a/arch/powerpc/platforms/86xx/sbc8641d.c b/arch/powerpc/platforms/86xx/sbc8641d.c
index 2886a36fc085..51c8f331b671 100644
--- a/arch/powerpc/platforms/86xx/sbc8641d.c
+++ b/arch/powerpc/platforms/86xx/sbc8641d.c
@@ -25,7 +25,6 @@
 #include <asm/time.h>
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
-#include <asm/mpc86xx.h>
 #include <asm/prom.h>
 #include <mm/mmu_decl.h>
 #include <asm/udbg.h>
diff --git a/arch/powerpc/platforms/8xx/mpc885ads.h b/arch/powerpc/platforms/8xx/mpc885ads.h
index a5076668bad6..19412f76fa3b 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads.h
+++ b/arch/powerpc/platforms/8xx/mpc885ads.h
@@ -17,10 +17,6 @@
 #include <sysdev/fsl_soc.h>
-#define MPC8xx_CPM_OFFSET       (0x9c0)
-#define CPM_MAP_ADDR            (get_immrbase() + MPC8xx_CPM_OFFSET)
-#define CPM_IRQ_OFFSET          16     // for compability with cpm_uart driver
 /* Bits of interest in the BCSRs.
 */
 #define BCSR1_ETHEN             ((uint)0x20000000)
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index e3e87078d03f..04a8061045c4 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -329,4 +329,8 @@ config MCU_MPC8349EMITX
          also register MCU GPIOs with the generic GPIO API, so you'll able
          to use MCU pins as GPIOs.
+config XILINX_PCI
+        bool "Xilinx PCI host bridge support"
+        depends on PCI && XILINX_VIRTEX
 endmenu
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 732ee93a8e98..cca6b4fc719a 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -10,7 +10,6 @@ menu "Processor support"
 choice
        prompt "Processor Type"
        depends on PPC32
-        default 6xx
        help
          There are five families of 32 bit PowerPC chips supported.
          The most common ones are the desktop and server CPUs (601, 603,
@@ -22,7 +21,7 @@ choice
          If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
-config 6xx
+config PPC_BOOK3S
        bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
        select PPC_FPU
@@ -58,13 +57,11 @@ config E200
 endchoice
-# Until we have a choice of exclusive CPU types on 64-bit, we always
-# use PPC_BOOK3S. On 32-bit, this is equivalent to 6xx which is
-# "classic" MMU
 config PPC_BOOK3S
-       def_bool y
+        default y
-       depends on PPC64 || 6xx
+        depends on PPC64
+        select PPC_FPU
 config POWER4_ONLY
        bool "Optimize for POWER4"
@@ -75,6 +72,10 @@ config POWER4_ONLY
          The resulting binary will not work on POWER3 or RS64 processors
          when compiled with binutils 2.15 or later.
+config 6xx
+        def_bool y
+        depends on PPC32 && PPC_BOOK3S
 config POWER3
        bool
        depends on PPC64 && PPC_BOOK3S
@@ -203,9 +204,8 @@ config SPE
          If in doubt, say Y here.
 config PPC_STD_MMU
-        bool
+        def_bool y
-        depends on 6xx || PPC64
+        depends on PPC_BOOK3S
-        default y
 config PPC_STD_MMU_32
        def_bool y
@@ -263,8 +263,8 @@ config SMP
          If you don't know what to do here, say N.
 config NR_CPUS
-        int "Maximum number of CPUs (2-1024)"
+        int "Maximum number of CPUs (2-8192)"
-        range 2 1024
+        range 2 8192
        depends on SMP
        default "32" if PPC64
        default "4"
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index 0ce45c2b42f8..c71498dbf211 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -329,7 +329,7 @@ static struct irq_host_ops msic_host_ops = {
 static int axon_msi_shutdown(struct of_device *device)
 {
-        struct axon_msic *msic = device->dev.platform_data;
+        struct axon_msic *msic = dev_get_drvdata(&device->dev);
        u32 tmp;
        pr_debug("axon_msi: disabling %s\n",
@@ -416,7 +416,7 @@ static int axon_msi_probe(struct of_device *device,
        msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
                                & MSIC_FIFO_SIZE_MASK;
-        device->dev.platform_data = msic;
+        dev_set_drvdata(&device->dev, msic);
        ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
        ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
diff --git a/arch/powerpc/platforms/cell/celleb_pci.c b/arch/powerpc/platforms/cell/celleb_pci.c
index f39a3b2a1667..00eaaa71630f 100644
--- a/arch/powerpc/platforms/cell/celleb_pci.c
+++ b/arch/powerpc/platforms/cell/celleb_pci.c
@@ -162,8 +162,7 @@ static int celleb_fake_pci_read_config(struct pci_bus *bus,
                unsigned int devfn, int where, int size, u32 *val)
 {
        char *config;
-        struct device_node *node;
+        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pci_controller *hose;
        unsigned int devno = devfn >> 3;
        unsigned int fn = devfn & 0x7;
@@ -171,8 +170,6 @@ static int celleb_fake_pci_read_config(struct pci_bus *bus,
        BUG_ON(where % size);
        pr_debug("    fake read: bus=0x%x, ", bus->number);
-        node = (struct device_node *)bus->sysdata;
-        hose = pci_find_hose_for_OF_device(node);
        config = get_fake_config_start(hose, devno, fn);
        pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
@@ -192,8 +189,7 @@ static int celleb_fake_pci_write_config(struct pci_bus *bus,
                unsigned int devfn, int where, int size, u32 val)
 {
        char *config;
-        struct device_node *node;
+        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pci_controller *hose;
        struct celleb_pci_resource *res;
        unsigned int devno = devfn >> 3;
        unsigned int fn = devfn & 0x7;
@@ -201,8 +197,6 @@ static int celleb_fake_pci_write_config(struct pci_bus *bus,
        /* allignment check */
        BUG_ON(where % size);
-        node = (struct device_node *)bus->sysdata;
-        hose = pci_find_hose_for_OF_device(node);
        config = get_fake_config_start(hose, devno, fn);
        if (!config)
diff --git a/arch/powerpc/platforms/cell/celleb_scc_epci.c b/arch/powerpc/platforms/cell/celleb_scc_epci.c
index 48ec88a38a12..05b0db3ef638 100644
--- a/arch/powerpc/platforms/cell/celleb_scc_epci.c
+++ b/arch/powerpc/platforms/cell/celleb_scc_epci.c
@@ -134,15 +134,11 @@ static int celleb_epci_read_config(struct pci_bus *bus,
 {
        PCI_IO_ADDR epci_base;
        PCI_IO_ADDR addr;
-        struct device_node *node;
+        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pci_controller *hose;
        /* allignment check */
        BUG_ON(where % size);
-        node = (struct device_node *)bus->sysdata;
-        hose = pci_find_hose_for_OF_device(node);
        if (!celleb_epci_get_epci_cfg(hose))
                return PCIBIOS_DEVICE_NOT_FOUND;
@@ -198,16 +194,11 @@ static int celleb_epci_write_config(struct pci_bus *bus,
 {
        PCI_IO_ADDR epci_base;
        PCI_IO_ADDR addr;
-        struct device_node *node;
+        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pci_controller *hose;
        /* allignment check */
        BUG_ON(where % size);
-        node = (struct device_node *)bus->sysdata;
-        hose = pci_find_hose_for_OF_device(node);
        if (!celleb_epci_get_epci_cfg(hose))
                return PCIBIOS_DEVICE_NOT_FOUND;
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
index 3e7e0f1568ef..7fca09f990ba 100644
--- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
+++ b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
@@ -366,11 +366,7 @@ static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
 static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
                                 int where, int size, unsigned int *val)
 {
-        struct device_node *dn;
+        struct pci_controller *phb = pci_bus_to_host(bus);
-        struct pci_controller *phb;
-        dn = bus->sysdata;
-        phb = pci_find_hose_for_OF_device(dn);
        if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) {
                *val = ~0;
@@ -389,11 +385,7 @@ static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
 static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
                                  int where, int size, unsigned int val)
 {
-        struct device_node *dn;
+        struct pci_controller *phb = pci_bus_to_host(bus);
-        struct pci_controller *phb;
-        dn = bus->sysdata;
-        phb = pci_find_hose_for_OF_device(dn);
        if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1)
                return PCIBIOS_DEVICE_NOT_FOUND;
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index bed4690de394..5b34fc211f35 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -100,16 +100,6 @@
 #define IOSTE_PS_1M             0x0000000000000005ul /*   - 1MB  */
 #define IOSTE_PS_16M            0x0000000000000007ul /*   - 16MB */
-/* Page table entries */
-#define IOPTE_PP_W              0x8000000000000000ul /* protection: write */
-#define IOPTE_PP_R              0x4000000000000000ul /* protection: read */
-#define IOPTE_M                 0x2000000000000000ul /* coherency required */
-#define IOPTE_SO_R              0x1000000000000000ul /* ordering: writes */
-#define IOPTE_SO_RW             0x1800000000000000ul /* ordering: r & w */
-#define IOPTE_RPN_Mask          0x07fffffffffff000ul /* RPN */
-#define IOPTE_H                 0x0000000000000800ul /* cache hint */
-#define IOPTE_IOID_Mask         0x00000000000007fful /* ioid */
 /* IOMMU sizing */
 #define IO_SEGMENT_SHIFT        28
@@ -193,19 +183,21 @@ static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
         */
        const unsigned long prot = 0xc48;
        base_pte =
-                ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R))
+                ((prot << (52 + 4 * direction)) &
-                | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask);
+                 (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) |
+                CBE_IOPTE_M | CBE_IOPTE_SO_RW |
+                (window->ioid & CBE_IOPTE_IOID_Mask);
 #else
-        base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
+        base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
-                (window->ioid & IOPTE_IOID_Mask);
+                CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask);
 #endif
        if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)))
-                base_pte &= ~IOPTE_SO_RW;
+                base_pte &= ~CBE_IOPTE_SO_RW;
        io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
        for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
-                io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask);
+                io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask);
        mb();
@@ -231,8 +223,9 @@ static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
 #else
        /* spider bridge does PCI reads after freeing - insert a mapping
         * to a scratch page instead of an invalid entry */
-        pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page)
+        pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW |
-                | (window->ioid & IOPTE_IOID_Mask);
+                __pa(window->iommu->pad_page) |
+                (window->ioid & CBE_IOPTE_IOID_Mask);
 #endif
        io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
@@ -1001,7 +994,7 @@ static void insert_16M_pte(unsigned long addr, unsigned long *ptab,
        pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n",
                  addr, ptab, segment, offset);
-        ptab[offset] = base_pte | (__pa(addr) & IOPTE_RPN_Mask);
+        ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask);
 }
 static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
@@ -1016,14 +1009,14 @@ static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
        pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
-        base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M
+        base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
-                    | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask);
+                (cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask);
        if (iommu_fixed_is_weak)
                pr_info("IOMMU: Using weak ordering for fixed mapping\n");
        else {
                pr_info("IOMMU: Using strong ordering for fixed mapping\n");
-                base_pte |= IOPTE_SO_RW;
+                base_pte |= CBE_IOPTE_SO_RW;
        }
        for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index 296b5268754e..5e0a191764fc 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -122,8 +122,8 @@ static int __init cbe_ptcal_enable_on_node(int nid, int order)
        area->nid = nid;
        area->order = order;
-        area->pages = alloc_pages_node(area->nid, GFP_KERNEL | GFP_THISNODE,
+        area->pages = alloc_pages_exact_node(area->nid, GFP_KERNEL|GFP_THISNODE,
-                                        area->order);
+                                                area->order);
        if (!area->pages) {
                printk(KERN_WARNING "%s: no page on node %d\n",
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index 9abd210d87c1..8547e86bfb42 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -752,17 +752,8 @@ static int __init init_spu_base(void)
                goto out_unregister_sysdev_class;
        }
-        if (ret > 0) {
+        if (ret > 0)
-                /*
-                 * We cannot put the forward declaration in
-                 * <linux/linux_logo.h> because of conflicting session type
-                 * conflicts for const and __initdata with different compiler
-                 * versions
-                 */
-                extern const struct linux_logo logo_spe_clut224;
                fb_append_extra_logo(&logo_spe_clut224, ret);
-        }
        mutex_lock(&spu_full_list_mutex);
        xmon_register_spus(&spu_full_list);
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 706eb5c7e2ee..24b30b6909c4 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -631,10 +631,6 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode,
        if (IS_ERR(dentry))
                goto out_dir;
-        ret = -EEXIST;
-        if (dentry->d_inode)
-                goto out_dput;
        mode &= ~current_umask();
        if (flags & SPU_CREATE_GANG)
@@ -648,8 +644,6 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode,
                fsnotify_mkdir(nd->path.dentry->d_inode, dentry);
        return ret;
-out_dput:
-        dput(dentry);
 out_dir:
        mutex_unlock(&nd->path.dentry->d_inode->i_mutex);
 out:
diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c
index f6b0c519d5a2..8f67a394b2d0 100644
--- a/arch/powerpc/platforms/chrp/pci.c
+++ b/arch/powerpc/platforms/chrp/pci.c
@@ -34,7 +34,7 @@ int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
                           int len, u32 *val)
 {
        volatile void __iomem *cfg_data;
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        if (bus->number > 7)
                return PCIBIOS_DEVICE_NOT_FOUND;
@@ -61,7 +61,7 @@ int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
                            int len, u32 val)
 {
        volatile void __iomem *cfg_data;
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        if (bus->number > 7)
                return PCIBIOS_DEVICE_NOT_FOUND;
@@ -96,7 +96,7 @@ static struct pci_ops gg2_pci_ops =
 int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
                     int len, u32 *val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
                | (((bus->number - hose->first_busno) & 0xff) << 16)
                | (hose->global_number << 24);
@@ -111,7 +111,7 @@ int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
 int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
                      int len, u32 val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
                | (((bus->number - hose->first_busno) & 0xff) << 16)
                | (hose->global_number << 24);
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index 65a35f38e062..fd23a1d4b39d 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -51,13 +51,20 @@ u8 uli_pirq_to_irq[8] = {
        ULI_8259_NONE,          /* PIRQH */
 };
+static inline bool is_quirk_valid(void)
+{
+        return (machine_is(mpc86xx_hpcn) ||
+                machine_is(mpc8544_ds) ||
+                machine_is(p2020_ds) ||
+                machine_is(mpc8572_ds));
+}
 /* Bridge */
 static void __devinit early_uli5249(struct pci_dev *dev)
 {
        unsigned char temp;
-        if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
+        if (!is_quirk_valid())
-                        !machine_is(mpc8572_ds))
                return;
        pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
@@ -80,8 +87,7 @@ static void __devinit quirk_uli1575(struct pci_dev *dev)
 {
        int i;
-        if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
+        if (!is_quirk_valid())
-                        !machine_is(mpc8572_ds))
                return;
        /*
@@ -149,8 +155,7 @@ static void __devinit quirk_final_uli1575(struct pci_dev *dev)
         * IRQ 14: Edge
         * IRQ 15: Edge
         */
-        if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
+        if (!is_quirk_valid())
-                        !machine_is(mpc8572_ds))
                return;
        outb(0xfa, 0x4d0);
@@ -176,8 +181,7 @@ static void __devinit quirk_uli5288(struct pci_dev *dev)
        unsigned char c;
        unsigned int d;
-        if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
+        if (!is_quirk_valid())
-                        !machine_is(mpc8572_ds))
                return;
        /* read/write lock */
@@ -201,8 +205,7 @@ static void __devinit quirk_uli5229(struct pci_dev *dev)
 {
        unsigned short temp;
-        if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
+        if (!is_quirk_valid())
-                        !machine_is(mpc8572_ds))
                return;
        pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
@@ -270,7 +273,6 @@ static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev)
 static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev)
 {
        unsigned char c;
-        unsigned short temp;
        if (!machine_is(mpc86xx_hpcd))
                return;
diff --git a/arch/powerpc/platforms/iseries/dt.c b/arch/powerpc/platforms/iseries/dt.c
index 4543c4bc3a56..c5a87a72057b 100644
--- a/arch/powerpc/platforms/iseries/dt.c
+++ b/arch/powerpc/platforms/iseries/dt.c
@@ -204,7 +204,8 @@ static void __init dt_prop_u32(struct iseries_flat_dt *dt, const char *name,
        dt_prop(dt, name, &data, sizeof(u32));
 }
-static void __init dt_prop_u64(struct iseries_flat_dt *dt, const char *name,
+static void __init __maybe_unused dt_prop_u64(struct iseries_flat_dt *dt,
+                                              const char *name,
                u64 data)
 {
        dt_prop(dt, name, &data, sizeof(u64));
diff --git a/arch/powerpc/platforms/iseries/iommu.c b/arch/powerpc/platforms/iseries/iommu.c
index 40219823d9b0..6c1e1011959e 100644
--- a/arch/powerpc/platforms/iseries/iommu.c
+++ b/arch/powerpc/platforms/iseries/iommu.c
@@ -177,7 +177,7 @@ static struct iommu_table *iommu_table_find(struct iommu_table * tbl)
 static void pci_dma_dev_setup_iseries(struct pci_dev *pdev)
 {
        struct iommu_table *tbl;
-        struct device_node *dn = pdev->sysdata;
+        struct device_node *dn = pci_device_to_OF_node(pdev);
        struct pci_dn *pdn = PCI_DN(dn);
        const u32 *lsn = of_get_property(dn, "linux,logical-slot-number", NULL);
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c
index 3689c2413d24..fef4d5150517 100644
--- a/arch/powerpc/platforms/iseries/mf.c
+++ b/arch/powerpc/platforms/iseries/mf.c
@@ -267,7 +267,8 @@ static struct pending_event *new_pending_event(void)
        return ev;
 }
-static int signal_vsp_instruction(struct vsp_cmd_data *vsp_cmd)
+static int __maybe_unused
+signal_vsp_instruction(struct vsp_cmd_data *vsp_cmd)
 {
        struct pending_event *ev = new_pending_event();
        int rc;
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c
index 21cddc30220b..175aac8ca7e5 100644
--- a/arch/powerpc/platforms/iseries/pci.c
+++ b/arch/powerpc/platforms/iseries/pci.c
@@ -318,6 +318,7 @@ static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
 {
        struct resource *bar_res = &dev->resource[bar_num];
        long bar_size = pci_resource_len(dev, bar_num);
+        struct device_node *dn = pci_device_to_OF_node(dev);
        /*
         * No space to allocate, quick exit, skip Allocation.
@@ -335,9 +336,9 @@ static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
         * Allocate the number of table entries needed for BAR.
         */
        while (bar_size > 0 ) {
-                iomm_table[current_iomm_table_entry] = dev->sysdata;
+                iomm_table[current_iomm_table_entry] = dn;
                ds_addr_table[current_iomm_table_entry] =
-                        iseries_ds_addr(dev->sysdata) | (bar_num << 24);
+                        iseries_ds_addr(dn) | (bar_num << 24);
                bar_size -= IOMM_TABLE_ENTRY_SIZE;
                ++current_iomm_table_entry;
        }
@@ -410,7 +411,7 @@ void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev)
        struct device_node *node;
        int i;
-        node = find_device_node(bus, pdev->devfn);
+        node = pci_device_to_OF_node(pdev);
        pr_debug("PCI: iSeries %s, pdev %p, node %p\n",
                 pci_name(pdev), pdev, node);
        if (!node) {
@@ -441,7 +442,6 @@ void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev)
                }
        }
-        pdev->sysdata = node;
        allocate_device_bars(pdev);
        iseries_device_information(pdev, bus, *sub_bus);
 }
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
index 75cc165d5bee..3bf546797cbb 100644
--- a/arch/powerpc/platforms/pasemi/gpio_mdio.c
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -29,7 +29,7 @@
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/phy.h>
-#include <linux/platform_device.h>
+#include <linux/of_mdio.h>
 #include <linux/of_platform.h>
 #define DELAY 1
@@ -39,6 +39,7 @@ static void __iomem *gpio_regs;
 struct gpio_priv {
        int mdc_pin;
        int mdio_pin;
+        int mdio_irqs[PHY_MAX_ADDR];
 };
 #define MDC_PIN(bus)    (((struct gpio_priv *)bus->priv)->mdc_pin)
@@ -218,12 +219,11 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
                                     const struct of_device_id *match)
 {
        struct device *dev = &ofdev->dev;
-        struct device_node *phy_dn, *np = ofdev->node;
+        struct device_node *np = ofdev->node;
        struct mii_bus *new_bus;
        struct gpio_priv *priv;
        const unsigned int *prop;
        int err;
-        int i;
        err = -ENOMEM;
        priv = kzalloc(sizeof(struct gpio_priv), GFP_KERNEL);
@@ -244,27 +244,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
        snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop);
        new_bus->priv = priv;
-        new_bus->phy_mask = 0;
+        new_bus->irq = priv->mdio_irqs;
-        new_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
-        if (!new_bus->irq)
-                goto out_free_bus;
-        for (i = 0; i < PHY_MAX_ADDR; i++)
-                new_bus->irq[i] = NO_IRQ;
-        for (phy_dn = of_get_next_child(np, NULL);
-             phy_dn != NULL;
-             phy_dn = of_get_next_child(np, phy_dn)) {
-                const unsigned int *ip, *regp;
-                ip = of_get_property(phy_dn, "interrupts", NULL);
-                regp = of_get_property(phy_dn, "reg", NULL);
-                if (!ip || !regp || *regp >= PHY_MAX_ADDR)
-                        continue;
-                new_bus->irq[*regp] = irq_create_mapping(NULL, *ip);
-        }
        prop = of_get_property(np, "mdc-pin", NULL);
        priv->mdc_pin = *prop;
@@ -275,7 +255,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
        new_bus->parent = dev;
        dev_set_drvdata(dev, new_bus);
-        err = mdiobus_register(new_bus);
+        err = of_mdiobus_register(new_bus, np);
        if (err != 0) {
                printk(KERN_ERR "%s: Cannot register as MDIO bus, err %d\n",
@@ -286,8 +266,6 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
        return 0;
 out_free_irq:
-        kfree(new_bus->irq);
-out_free_bus:
        kfree(new_bus);
 out_free_priv:
        kfree(priv);
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 7039d8f1d3ba..dce736349107 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -221,7 +221,7 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id)
                        continue;
                irq += __ilog2(bits);
                spin_unlock_irqrestore(&pmac_pic_lock, flags);
-                __do_IRQ(irq);
+                generic_handle_irq(irq);
                spin_lock_irqsave(&pmac_pic_lock, flags);
                rc = IRQ_HANDLED;
        }
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 45936c9ed0ec..86f69a4eb49b 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -655,7 +655,7 @@ static int __init pmac_probe(void)
 /* Move that to pci.c */
 static int pmac_pci_probe_mode(struct pci_bus *bus)
 {
-        struct device_node *node = bus->sysdata;
+        struct device_node *node = pci_bus_to_OF_node(bus);
        /* We need to use normal PCI probing for the AGP bus,
         * since the device for the AGP bridge isn't in the tree.
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 9a2b6d948610..846eb8b57fd1 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -24,6 +24,7 @@
 #include <linux/lmb.h>
 #include <asm/firmware.h>
+#include <asm/iommu.h>
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
@@ -605,9 +606,8 @@ static int dma_ioc0_map_pages(struct ps3_dma_region *r, unsigned long phys_addr,
                                       r->ioid,
                                       iopte_flag);
                if (result) {
-                        printk(KERN_WARNING "%s:%d: lv1_map_device_dma_region "
+                        pr_warning("%s:%d: lv1_put_iopte failed: %s\n",
-                                "failed: %s\n", __func__, __LINE__,
+                                   __func__, __LINE__, ps3_result(result));
-                                ps3_result(result));
                        goto fail_map;
                }
                DBG("%s: pg=%d bus=%#lx, lpar=%#lx, ioid=%#x\n", __func__,
@@ -1001,7 +1001,8 @@ static int dma_sb_region_create_linear(struct ps3_dma_region *r)
                if (len > r->len)
                        len = r->len;
                result = dma_sb_map_area(r, virt_addr, len, &tmp,
-                        IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M);
+                        CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_SO_RW |
+                        CBE_IOPTE_M);
                BUG_ON(result);
        }
@@ -1014,7 +1015,8 @@ static int dma_sb_region_create_linear(struct ps3_dma_region *r)
                else
                        len -= map.rm.size - r->offset;
                result = dma_sb_map_area(r, virt_addr, len, &tmp,
-                        IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M);
+                        CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_SO_RW |
+                        CBE_IOPTE_M);
                BUG_ON(result);
        }
diff --git a/arch/powerpc/platforms/ps3/os-area.c b/arch/powerpc/platforms/ps3/os-area.c
index cf1cd0f8c18f..d6487a9c8019 100644
--- a/arch/powerpc/platforms/ps3/os-area.c
+++ b/arch/powerpc/platforms/ps3/os-area.c
@@ -226,6 +226,44 @@ static struct property property_av_multi_out = {
        .value = &saved_params.av_multi_out,
 };
+static DEFINE_MUTEX(os_area_flash_mutex);
+static const struct ps3_os_area_flash_ops *os_area_flash_ops;
+void ps3_os_area_flash_register(const struct ps3_os_area_flash_ops *ops)
+{
+        mutex_lock(&os_area_flash_mutex);
+        os_area_flash_ops = ops;
+        mutex_unlock(&os_area_flash_mutex);
+}
+EXPORT_SYMBOL_GPL(ps3_os_area_flash_register);
+static ssize_t os_area_flash_read(void *buf, size_t count, loff_t pos)
+{
+        ssize_t res = -ENODEV;
+        mutex_lock(&os_area_flash_mutex);
+        if (os_area_flash_ops)
+                res = os_area_flash_ops->read(buf, count, pos);
+        mutex_unlock(&os_area_flash_mutex);
+        return res;
+}
+static ssize_t os_area_flash_write(const void *buf, size_t count, loff_t pos)
+{
+        ssize_t res = -ENODEV;
+        mutex_lock(&os_area_flash_mutex);
+        if (os_area_flash_ops)
+                res = os_area_flash_ops->write(buf, count, pos);
+        mutex_unlock(&os_area_flash_mutex);
+        return res;
+}
 /**
 * os_area_set_property - Add or overwrite a saved_params value to the device tree.
 *
@@ -352,12 +390,12 @@ static int db_verify(const struct os_area_db *db)
        if (memcmp(db->magic_num, OS_AREA_DB_MAGIC_NUM,
                sizeof(db->magic_num))) {
                pr_debug("%s:%d magic_num failed\n", __func__, __LINE__);
-                return -1;
+                return -EINVAL;
        }
        if (db->version != 1) {
                pr_debug("%s:%d version failed\n", __func__, __LINE__);
-                return -1;
+                return -EINVAL;
        }
        return 0;
@@ -578,59 +616,48 @@ static void os_area_db_init(struct os_area_db *db)
 *
 */
-static void __maybe_unused update_flash_db(void)
+static int update_flash_db(void)
 {
-        int result;
+        const unsigned int buf_len = 8 * OS_AREA_SEGMENT_SIZE;
-        int file;
+        struct os_area_header *header;
-        off_t offset;
        ssize_t count;
-        static const unsigned int buf_len = 8 * OS_AREA_SEGMENT_SIZE;
+        int error;
-        const struct os_area_header *header;
+        loff_t pos;
        struct os_area_db* db;
        /* Read in header and db from flash. */
-        file = sys_open("/dev/ps3flash", O_RDWR, 0);
-        if (file < 0) {
-                pr_debug("%s:%d sys_open failed\n", __func__, __LINE__);
-                goto fail_open;
-        }
        header = kmalloc(buf_len, GFP_KERNEL);
        if (!header) {
-                pr_debug("%s:%d kmalloc failed\n", __func__, __LINE__);
+                pr_debug("%s: kmalloc failed\n", __func__);
-                goto fail_malloc;
+                return -ENOMEM;
        }
-        offset = sys_lseek(file, 0, SEEK_SET);
+        count = os_area_flash_read(header, buf_len, 0);
+        if (count < 0) {
-        if (offset != 0) {
+                pr_debug("%s: os_area_flash_read failed %zd\n", __func__,
-                pr_debug("%s:%d sys_lseek failed\n", __func__, __LINE__);
+                         count);
-                goto fail_header_seek;
+                error = count;
+                goto fail;
        }
-        count = sys_read(file, (char __user *)header, buf_len);
+        pos = header->db_area_offset * OS_AREA_SEGMENT_SIZE;
+        if (count < OS_AREA_SEGMENT_SIZE || verify_header(header) ||
-        result = count < OS_AREA_SEGMENT_SIZE || verify_header(header)
+            count < pos) {
-                || count < header->db_area_offset * OS_AREA_SEGMENT_SIZE;
+                pr_debug("%s: verify_header failed\n", __func__);
-        if (result) {
-                pr_debug("%s:%d verify_header failed\n", __func__, __LINE__);
                dump_header(header);
-                goto fail_header;
+                error = -EINVAL;
+                goto fail;
        }
        /* Now got a good db offset and some maybe good db data. */
-        db = (void*)header + header->db_area_offset * OS_AREA_SEGMENT_SIZE;
+        db = (void *)header + pos;
-        result = db_verify(db);
+        error = db_verify(db);
+        if (error) {
-        if (result) {
+                pr_notice("%s: Verify of flash database failed, formatting.\n",
-                printk(KERN_NOTICE "%s:%d: Verify of flash database failed, "
+                          __func__);
-                        "formatting.\n", __func__, __LINE__);
                dump_db(db);
                os_area_db_init(db);
        }
@@ -639,29 +666,16 @@ static void __maybe_unused update_flash_db(void)
        db_set_64(db, &os_area_db_id_rtc_diff, saved_params.rtc_diff);
-        offset = sys_lseek(file, header->db_area_offset * OS_AREA_SEGMENT_SIZE,
+        count = os_area_flash_write(db, sizeof(struct os_area_db), pos);
-                SEEK_SET);
-        if (offset != header->db_area_offset * OS_AREA_SEGMENT_SIZE) {
-                pr_debug("%s:%d sys_lseek failed\n", __func__, __LINE__);
-                goto fail_db_seek;
-        }
-        count = sys_write(file, (const char __user *)db,
-                sizeof(struct os_area_db));
        if (count < sizeof(struct os_area_db)) {
-                pr_debug("%s:%d sys_write failed\n", __func__, __LINE__);
+                pr_debug("%s: os_area_flash_write failed %zd\n", __func__,
+                         count);
+                error = count < 0 ? count : -EIO;
        }
-fail_db_seek:
+fail:
-fail_header:
-fail_header_seek:
        kfree(header);
-fail_malloc:
+        return error;
-        sys_close(file);
-fail_open:
-        return;
 }
 /**
@@ -674,11 +688,11 @@ fail_open:
 static void os_area_queue_work_handler(struct work_struct *work)
 {
        struct device_node *node;
+        int error;
        pr_debug(" -> %s:%d\n", __func__, __LINE__);
        node = of_find_node_by_path("/");
        if (node) {
                os_area_set_property(node, &property_rtc_diff);
                of_node_put(node);
@@ -686,12 +700,10 @@ static void os_area_queue_work_handler(struct work_struct *work)
                pr_debug("%s:%d of_find_node_by_path failed\n",
                        __func__, __LINE__);
-#if defined(CONFIG_PS3_FLASH) || defined(CONFIG_PS3_FLASH_MODULE)
+        error = update_flash_db();
-        update_flash_db();
+        if (error)
-#else
+                pr_warning("%s: Could not update FLASH ROM\n", __func__);
-        printk(KERN_WARNING "%s:%d: No flash rom driver configured.\n",
-                __func__, __LINE__);
-#endif
        pr_debug(" <- %s:%d\n", __func__, __LINE__);
 }
@@ -808,7 +820,7 @@ u64 ps3_os_area_get_rtc_diff(void)
 {
        return saved_params.rtc_diff;
 }
-EXPORT_SYMBOL(ps3_os_area_get_rtc_diff);
+EXPORT_SYMBOL_GPL(ps3_os_area_get_rtc_diff);
 /**
 * ps3_os_area_set_rtc_diff - Set the rtc diff value.
@@ -824,7 +836,7 @@ void ps3_os_area_set_rtc_diff(u64 rtc_diff)
                os_area_queue_work();
        }
 }
-EXPORT_SYMBOL(ps3_os_area_set_rtc_diff);
+EXPORT_SYMBOL_GPL(ps3_os_area_set_rtc_diff);
 /**
 * ps3_os_area_get_av_multi_out - Returns the default video mode.
diff --git a/arch/powerpc/platforms/ps3/platform.h b/arch/powerpc/platforms/ps3/platform.h
index 136aa0637d9c..9a196a88eda7 100644
--- a/arch/powerpc/platforms/ps3/platform.h
+++ b/arch/powerpc/platforms/ps3/platform.h
@@ -232,14 +232,4 @@ int ps3_repository_read_spu_resource_id(unsigned int res_index,
 int ps3_repository_read_vuart_av_port(unsigned int *port);
 int ps3_repository_read_vuart_sysmgr_port(unsigned int *port);
-/* Page table entries */
-#define IOPTE_PP_W              0x8000000000000000ul /* protection: write */
-#define IOPTE_PP_R              0x4000000000000000ul /* protection: read */
-#define IOPTE_M                 0x2000000000000000ul /* coherency required */
-#define IOPTE_SO_R              0x1000000000000000ul /* ordering: writes */
-#define IOPTE_SO_RW             0x1800000000000000ul /* ordering: r & w */
-#define IOPTE_RPN_Mask          0x07fffffffffff000ul /* RPN */
-#define IOPTE_H                 0x0000000000000800ul /* cache hint */
-#define IOPTE_IOID_Mask         0x00000000000007fful /* ioid */
 #endif
diff --git a/arch/powerpc/platforms/ps3/setup.c b/arch/powerpc/platforms/ps3/setup.c
index 1a7b5ae0c83e..149bea2ce583 100644
--- a/arch/powerpc/platforms/ps3/setup.c
+++ b/arch/powerpc/platforms/ps3/setup.c
@@ -32,6 +32,7 @@
 #include <asm/udbg.h>
 #include <asm/prom.h>
 #include <asm/lv1call.h>
+#include <asm/ps3gpu.h>
 #include "platform.h"
diff --git a/arch/powerpc/platforms/ps3/smp.c b/arch/powerpc/platforms/ps3/smp.c
index a0927a3bacb7..f6e04bcc70ef 100644
--- a/arch/powerpc/platforms/ps3/smp.c
+++ b/arch/powerpc/platforms/ps3/smp.c
@@ -32,12 +32,6 @@
 #define DBG pr_debug
 #endif
-static irqreturn_t ipi_function_handler(int irq, void *msg)
-{
-        smp_message_recv((int)(long)msg);
-        return IRQ_HANDLED;
-}
 /**
  * ps3_ipi_virqs - a per cpu array of virqs for ipi use
  */
@@ -45,13 +39,6 @@ static irqreturn_t ipi_function_handler(int irq, void *msg)
 #define MSG_COUNT 4
 static DEFINE_PER_CPU(unsigned int, ps3_ipi_virqs[MSG_COUNT]);
-static const char *names[MSG_COUNT] = {
-        "ipi call",
-        "ipi reschedule",
-        "ipi migrate",
-        "ipi debug brk"
-};
 static void do_message_pass(int target, int msg)
 {
        int result;
@@ -119,8 +106,7 @@ static void __init ps3_smp_setup_cpu(int cpu)
                DBG("%s:%d: (%d, %d) => virq %u\n",
                        __func__, __LINE__, cpu, i, virqs[i]);
-                result = request_irq(virqs[i], ipi_function_handler,
+                result = smp_request_message_ipi(virqs[i], i);
-                        IRQF_DISABLED, names[i], (void*)(long)i);
                if (result)
                        virqs[i] = NO_IRQ;
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c
index 9a73d0238639..9fead0faf38b 100644
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -27,6 +27,7 @@
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
 #include <asm/firmware.h>
+#include <asm/iommu.h>
 #include "platform.h"
@@ -531,7 +532,8 @@ static void * ps3_alloc_coherent(struct device *_dev, size_t size,
        }
        result = ps3_dma_map(dev->d_region, virt_addr, size, dma_handle,
-                             IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M);
+                             CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
+                             CBE_IOPTE_SO_RW | CBE_IOPTE_M);
        if (result) {
                pr_debug("%s:%d: ps3_dma_map failed (%d)\n",
@@ -575,7 +577,8 @@ static dma_addr_t ps3_sb_map_page(struct device *_dev, struct page *page,
        result = ps3_dma_map(dev->d_region, (unsigned long)ptr, size,
                             &bus_addr,
-                             IOPTE_PP_R | IOPTE_PP_W | IOPTE_SO_RW | IOPTE_M);
+                             CBE_IOPTE_PP_R | CBE_IOPTE_PP_W |
+                             CBE_IOPTE_SO_RW | CBE_IOPTE_M);
        if (result) {
                pr_debug("%s:%d: ps3_dma_map failed (%d)\n",
@@ -596,16 +599,16 @@ static dma_addr_t ps3_ioc0_map_page(struct device *_dev, struct page *page,
        u64 iopte_flag;
        void *ptr = page_address(page) + offset;
-        iopte_flag = IOPTE_M;
+        iopte_flag = CBE_IOPTE_M;
        switch (direction) {
        case DMA_BIDIRECTIONAL:
-                iopte_flag |= IOPTE_PP_R | IOPTE_PP_W | IOPTE_SO_RW;
+                iopte_flag |= CBE_IOPTE_PP_R | CBE_IOPTE_PP_W | CBE_IOPTE_SO_RW;
                break;
        case DMA_TO_DEVICE:
-                iopte_flag |= IOPTE_PP_R | IOPTE_SO_R;
+                iopte_flag |= CBE_IOPTE_PP_R | CBE_IOPTE_SO_R;
                break;
        case DMA_FROM_DEVICE:
-                iopte_flag |= IOPTE_PP_W | IOPTE_SO_RW;
+                iopte_flag |= CBE_IOPTE_PP_W | CBE_IOPTE_SO_RW;
                break;
        default:
                /* not happned */
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 3ee01b4f4257..661c8e02bcba 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -388,7 +388,7 @@ static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
                while (pci->phb->dma_window_size * children > 0x80000000ul)
                        pci->phb->dma_window_size >>= 1;
-                pr_debug("No ISA/IDE, window size is 0x%lx\n",
+                pr_debug("No ISA/IDE, window size is 0x%llx\n",
                         pci->phb->dma_window_size);
                pci->phb->dma_window_base_cur = 0;
@@ -414,7 +414,7 @@ static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
        while (pci->phb->dma_window_size * children > 0x70000000ul)
                pci->phb->dma_window_size >>= 1;
-        pr_debug("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size);
+        pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
 }
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 52a80e5840e8..e3139fa5e556 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -609,3 +609,55 @@ void __init hpte_init_lpar(void)
        ppc_md.flush_hash_range = pSeries_lpar_flush_hash_range;
        ppc_md.hpte_clear_all   = pSeries_lpar_hptab_clear;
 }
+#ifdef CONFIG_PPC_SMLPAR
+#define CMO_FREE_HINT_DEFAULT 1
+static int cmo_free_hint_flag = CMO_FREE_HINT_DEFAULT;
+static int __init cmo_free_hint(char *str)
+{
+        char *parm;
+        parm = strstrip(str);
+        if (strcasecmp(parm, "no") == 0 || strcasecmp(parm, "off") == 0) {
+                printk(KERN_INFO "cmo_free_hint: CMO free page hinting is not active.\n");
+                cmo_free_hint_flag = 0;
+                return 1;
+        }
+        cmo_free_hint_flag = 1;
+        printk(KERN_INFO "cmo_free_hint: CMO free page hinting is active.\n");
+        if (strcasecmp(parm, "yes") == 0 || strcasecmp(parm, "on") == 0)
+                return 1;
+        return 0;
+}
+__setup("cmo_free_hint=", cmo_free_hint);
+static void pSeries_set_page_state(struct page *page, int order,
+                                   unsigned long state)
+{
+        int i, j;
+        unsigned long cmo_page_sz, addr;
+        cmo_page_sz = cmo_get_page_size();
+        addr = __pa((unsigned long)page_address(page));
+        for (i = 0; i < (1 << order); i++, addr += PAGE_SIZE) {
+                for (j = 0; j < PAGE_SIZE; j += cmo_page_sz)
+                        plpar_hcall_norets(H_PAGE_INIT, state, addr + j, 0);
+        }
+}
+void arch_free_page(struct page *page, int order)
+{
+        if (!cmo_free_hint_flag || !firmware_has_feature(FW_FEATURE_CMO))
+                return;
+        pSeries_set_page_state(page, order, H_PAGE_SET_UNUSED);
+}
+EXPORT_SYMBOL(arch_free_page);
+#endif
diff --git a/arch/powerpc/platforms/pseries/rtasd.c b/arch/powerpc/platforms/pseries/rtasd.c
index afad9f5ac0ac..b3cbac855924 100644
--- a/arch/powerpc/platforms/pseries/rtasd.c
+++ b/arch/powerpc/platforms/pseries/rtasd.c
@@ -19,7 +19,7 @@
 #include <linux/vmalloc.h>
 #include <linux/spinlock.h>
 #include <linux/cpu.h>
-#include <linux/delay.h>
+#include <linux/workqueue.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
@@ -387,36 +387,51 @@ static void do_event_scan(void)
        } while(error == 0);
 }
-static void do_event_scan_all_cpus(long delay)
+static void rtas_event_scan(struct work_struct *w);
+DECLARE_DELAYED_WORK(event_scan_work, rtas_event_scan);
+/*
+ * Delay should be at least one second since some machines have problems if
+ * we call event-scan too quickly.
+ */
+static unsigned long event_scan_delay = 1*HZ;
+static int first_pass = 1;
+static void rtas_event_scan(struct work_struct *w)
 {
-        int cpu;
+        unsigned int cpu;
+        do_event_scan();
        get_online_cpus();
-        cpu = first_cpu(cpu_online_map);
-        for (;;) {
+        cpu = next_cpu(smp_processor_id(), cpu_online_map);
-                set_cpus_allowed(current, cpumask_of_cpu(cpu));
+        if (cpu == NR_CPUS) {
-                do_event_scan();
+                cpu = first_cpu(cpu_online_map);
-                set_cpus_allowed(current, CPU_MASK_ALL);
+                if (first_pass) {
-                /* Drop hotplug lock, and sleep for the specified delay */
+                        first_pass = 0;
-                put_online_cpus();
+                        event_scan_delay = 30*HZ/rtas_event_scan_rate;
-                msleep_interruptible(delay);
-                get_online_cpus();
+                        if (surveillance_timeout != -1) {
+                                pr_debug("rtasd: enabling surveillance\n");
-                cpu = next_cpu(cpu, cpu_online_map);
+                                enable_surveillance(surveillance_timeout);
-                if (cpu == NR_CPUS)
+                                pr_debug("rtasd: surveillance enabled\n");
-                        break;
+                        }
+                }
        }
+        schedule_delayed_work_on(cpu, &event_scan_work,
+                __round_jiffies_relative(event_scan_delay, cpu));
        put_online_cpus();
 }
-static int rtasd(void *unused)
+static void start_event_scan(void)
 {
        unsigned int err_type;
        int rc;
-        daemonize("rtasd");
        printk(KERN_DEBUG "RTAS daemon started\n");
        pr_debug("rtasd: will sleep for %d milliseconds\n",
                 (30000 / rtas_event_scan_rate));
@@ -434,22 +449,8 @@ static int rtasd(void *unused)
                }
        }
-        /* First pass. */
+        schedule_delayed_work_on(first_cpu(cpu_online_map), &event_scan_work,
-        do_event_scan_all_cpus(1000);
+                                 event_scan_delay);
-        if (surveillance_timeout != -1) {
-                pr_debug("rtasd: enabling surveillance\n");
-                enable_surveillance(surveillance_timeout);
-                pr_debug("rtasd: surveillance enabled\n");
-        }
-        /* Delay should be at least one second since some
-         * machines have problems if we call event-scan too
-         * quickly. */
-        for (;;)
-                do_event_scan_all_cpus(30000/rtas_event_scan_rate);
-        return -EINVAL;
 }
 static int __init rtas_init(void)
@@ -487,8 +488,7 @@ static int __init rtas_init(void)
        if (!entry)
                printk(KERN_ERR "Failed to create error_log proc entry\n");
-        if (kernel_thread(rtasd, NULL, CLONE_FS) < 0)
+        start_event_scan();
-                printk(KERN_ERR "Failed to start RTAS daemon\n");
        return 0;
 }
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index ec341707e41b..8d75ea21296f 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -63,6 +63,7 @@
 #include <asm/smp.h>
 #include <asm/firmware.h>
 #include <asm/eeh.h>
+#include <asm/pSeries_reconfig.h>
 #include "plpar_wrappers.h"
 #include "pseries.h"
@@ -254,6 +255,29 @@ static void __init pseries_discover_pic(void)
               " interrupt-controller\n");
 }
+static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
+{
+        struct device_node *np = node;
+        struct pci_dn *pci = NULL;
+        int err = NOTIFY_OK;
+        switch (action) {
+        case PSERIES_RECONFIG_ADD:
+                pci = np->parent->data;
+                if (pci)
+                        update_dn_pci_info(np, pci->phb);
+                break;
+        default:
+                err = NOTIFY_DONE;
+                break;
+        }
+        return err;
+}
+static struct notifier_block pci_dn_reconfig_nb = {
+        .notifier_call = pci_dn_reconfig_notifier,
+};
 static void __init pSeries_setup_arch(void)
 {
        /* Discover PIC type and setup ppc_md accordingly */
@@ -271,6 +295,7 @@ static void __init pSeries_setup_arch(void)
        /* Find and initialize PCI host bridges */
        init_pci_config_tokens();
        find_and_init_phbs();
+        pSeries_reconfig_notifier_register(&pci_dn_reconfig_nb);
        eeh_init();
        pSeries_nvram_init();
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index b33b28a6fe12..2d1c87dd5d14 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_IPIC)		+= ipic.o
 obj-$(CONFIG_4xx)               += uic.o
 obj-$(CONFIG_4xx_SOC)           += ppc4xx_soc.o
 obj-$(CONFIG_XILINX_VIRTEX)     += xilinx_intc.o
+obj-$(CONFIG_XILINX_PCI)        += xilinx_pci.o
 obj-$(CONFIG_OF_RTC)            += of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)               += ppc4xx_pci.o
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index fd969f0e3121..eb5927212fab 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -61,7 +61,7 @@ EXPORT_SYMBOL(cpm2_immr);
 void __init cpm2_reset(void)
 {
 #ifdef CONFIG_PPC_85xx
-        cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
+        cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE);
 #else
        cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
 #endif
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index f25ce818d40a..da38a1ff97bb 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -113,8 +113,13 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
                                  struct msi_msg *msg)
 {
        struct fsl_msi *msi_data = fsl_msi;
+        struct pci_controller *hose = pci_bus_to_host(pdev->bus);
+        u32 base = 0;
-        msg->address_lo = msi_data->msi_addr_lo;
+        pci_bus_read_config_dword(hose->bus,
+                PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
+        msg->address_lo = msi_data->msi_addr_lo + base;
        msg->address_hi = msi_data->msi_addr_hi;
        msg->data = hwirq;
@@ -271,7 +276,7 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
        msi->irqhost->host_data = msi;
        msi->msi_addr_hi = 0x0;
-        msi->msi_addr_lo = res.start + features->msiir_offset;
+        msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
        rc = fsl_msi_init_allocator(msi);
        if (rc) {
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 78021d8afc53..ae88b1448018 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -23,6 +23,8 @@
 #include <linux/string.h>
 #include <linux/init.h>
 #include <linux/bootmem.h>
+#include <linux/lmb.h>
+#include <linux/log2.h>
 #include <asm/io.h>
 #include <asm/prom.h>
@@ -96,7 +98,13 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
                                  struct resource *rsrc)
 {
        struct ccsr_pci __iomem *pci;
-        int i, j, n;
+        int i, j, n, mem_log, win_idx = 2;
+        u64 mem, sz, paddr_hi = 0;
+        u64 paddr_lo = ULLONG_MAX;
+        u32 pcicsrbar = 0, pcicsrbar_sz;
+        u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
+                        PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+        char *name = hose->dn->full_name;
        pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
                    (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
@@ -117,6 +125,9 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
                if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
                        continue;
+                paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
+                paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
                n = setup_one_atmu(pci, j, &hose->mem_resources[i],
                                   hose->pci_mem_offset);
@@ -147,10 +158,105 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
                }
        }
-        /* Setup 2G inbound Memory Window @ 1 */
+        /* convert to pci address space */
-        out_be32(&pci->piw[2].pitar, 0x00000000);
+        paddr_hi -= hose->pci_mem_offset;
-        out_be32(&pci->piw[2].piwbar,0x00000000);
+        paddr_lo -= hose->pci_mem_offset;
-        out_be32(&pci->piw[2].piwar, PIWAR_2G);
+        if (paddr_hi == paddr_lo) {
+                pr_err("%s: No outbound window space\n", name);
+                return ;
+        }
+        if (paddr_lo == 0) {
+                pr_err("%s: No space for inbound window\n", name);
+                return ;
+        }
+        /* setup PCSRBAR/PEXCSRBAR */
+        early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
+        early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
+        pcicsrbar_sz = ~pcicsrbar_sz + 1;
+        if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
+                (paddr_lo > 0x100000000ull))
+                pcicsrbar = 0x100000000ull - pcicsrbar_sz;
+        else
+                pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
+        early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
+        paddr_lo = min(paddr_lo, (u64)pcicsrbar);
+        pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
+        /* Setup inbound mem window */
+        mem = lmb_end_of_DRAM();
+        sz = min(mem, paddr_lo);
+        mem_log = __ilog2_u64(sz);
+        /* PCIe can overmap inbound & outbound since RX & TX are separated */
+        if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+                /* Size window to exact size if power-of-two or one size up */
+                if ((1ull << mem_log) != mem) {
+                        if ((1ull << mem_log) > mem)
+                                pr_info("%s: Setting PCI inbound window "
+                                        "greater than memory size\n", name);
+                        mem_log++;
+                }
+                piwar |= (mem_log - 1);
+                /* Setup inbound memory window */
+                out_be32(&pci->piw[win_idx].pitar,  0x00000000);
+                out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
+                out_be32(&pci->piw[win_idx].piwar,  piwar);
+                win_idx--;
+                hose->dma_window_base_cur = 0x00000000;
+                hose->dma_window_size = (resource_size_t)sz;
+        } else {
+                u64 paddr = 0;
+                /* Setup inbound memory window */
+                out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
+                out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
+                out_be32(&pci->piw[win_idx].piwar,  (piwar | (mem_log - 1)));
+                win_idx--;
+                paddr += 1ull << mem_log;
+                sz -= 1ull << mem_log;
+                if (sz) {
+                        mem_log = __ilog2_u64(sz);
+                        piwar |= (mem_log - 1);
+                        out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
+                        out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
+                        out_be32(&pci->piw[win_idx].piwar,  piwar);
+                        win_idx--;
+                        paddr += 1ull << mem_log;
+                }
+                hose->dma_window_base_cur = 0x00000000;
+                hose->dma_window_size = (resource_size_t)paddr;
+        }
+        if (hose->dma_window_size < mem) {
+#ifndef CONFIG_SWIOTLB
+                pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
+                        "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
+                         name);
+#endif
+                /* adjusting outbound windows could reclaim space in mem map */
+                if (paddr_hi < 0xffffffffull)
+                        pr_warning("%s: WARNING: Outbound window cfg leaves "
+                                "gaps in memory map. Adjusting the memory map "
+                                "could reduce unnecessary bounce buffering.\n",
+                                name);
+                pr_info("%s: DMA window size is 0x%llx\n", name,
+                        (u64)hose->dma_window_size);
+        }
        iounmap(pci);
 }
@@ -176,19 +282,9 @@ static void __init setup_pci_cmd(struct pci_controller *hose)
        }
 }
-static void __init setup_pci_pcsrbar(struct pci_controller *hose)
-{
-#ifdef CONFIG_PCI_MSI
-        phys_addr_t immr_base;
-        immr_base = get_immrbase();
-        early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base);
-#endif
-}
 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
 {
-        struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        int i;
        if ((bus->parent == hose->bus) &&
@@ -269,8 +365,6 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
        /* Setup PEX window registers */
        setup_pci_atmu(hose, &rsrc);
-        /* Setup PEXCSRBAR */
-        setup_pci_pcsrbar(hose);
        return 0;
 }
@@ -281,6 +375,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
@@ -296,6 +392,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
 #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
@@ -324,7 +422,7 @@ struct mpc83xx_pcie_priv {
 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
                return PCIBIOS_DEVICE_NOT_FOUND;
@@ -350,7 +448,7 @@ static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
                                            unsigned int devfn, int offset)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        struct mpc83xx_pcie_priv *pcie = hose->dn->data;
        u8 bus_no = bus->number - hose->first_busno;
        u32 dev_base = bus_no << 24 | devfn << 16;
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 13f30c2a61e7..a9d8bbebed80 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -16,7 +16,11 @@
 #define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
 #define PCIE_LTSSM_L0   0x16            /* L0 state */
-#define PIWAR_2G        0xa0f5501e      /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+#define PIWAR_EN                0x80000000      /* Enable */
+#define PIWAR_PF                0x20000000      /* prefetch */
+#define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
+#define PIWAR_READ_SNOOP        0x00050000
+#define PIWAR_WRITE_SNOOP       0x00005000
 /* PCI/PCI Express outbound window reg */
 struct pci_outbound_window_regs {
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index abdb124e1e2f..39db9d1155d2 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1026,8 +1026,7 @@ int fsl_rio_setup(struct of_device *dev)
                return -EFAULT;
        }
        dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name);
-        dev_info(&dev->dev, "Regs start 0x%08x size 0x%08x\n",  regs.start,
+        dev_info(&dev->dev, "Regs: %pR\n", &regs);
-                                                regs.end - regs.start + 1);
        dt_range = of_get_property(dev->node, "ranges", &rlen);
        if (!dt_range) {
@@ -1077,8 +1076,9 @@ int fsl_rio_setup(struct of_device *dev)
        INIT_LIST_HEAD(&port->dbells);
        port->iores.start = law_start;
-        port->iores.end = law_start + law_size;
+        port->iores.end = law_start + law_size - 1;
        port->iores.flags = IORESOURCE_MEM;
+        port->iores.name = "rio_io_win";
        priv->bellirq = irq_of_parse_and_map(dev->node, 2);
        priv->txirq = irq_of_parse_and_map(dev->node, 3);
@@ -1156,14 +1156,15 @@ int fsl_rio_setup(struct of_device *dev)
                out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
        /* Configure maintenance transaction window */
-        out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000);
+        out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
-        out_be32(&priv->maint_atmu_regs->rowar, 0x80077015);
+        out_be32(&priv->maint_atmu_regs->rowar, 0x80077015);    /* 4M */
        priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
        /* Configure outbound doorbell window */
-        out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400);
+        out_be32(&priv->dbell_atmu_regs->rowbar,
-        out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);
+                        (law_start + RIO_MAINT_WIN_SIZE) >> 12);
+        out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);    /* 4k */
        fsl_rio_doorbell_init(port);
        return 0;
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 5c64ccd402e2..95dbc643c4fc 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -379,16 +379,10 @@ static int __init setup_rstcr(void)
        struct device_node *np;
        np = of_find_node_by_name(NULL, "global-utilities");
        if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) {
-                const u32 *prop = of_get_property(np, "reg", NULL);
+                rstcr = of_iomap(np, 0) + 0xb0;
-                if (prop) {
+                if (!rstcr)
-                        /* map reset control register
+                        printk (KERN_EMERG "Error: reset control register "
-                         * 0xE00B0 is offset of reset control register
+                                        "not mapped!\n");
-                         */
-                        rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff);
-                        if (!rstcr)
-                                printk (KERN_EMERG "Error: reset control "
-                                                "register not mapped!\n");
-                }
        } else
                printk (KERN_INFO "rstcr compatible register does not exist!\n");
        if (np)
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 7fd49c97501a..7ed809676642 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -24,7 +24,7 @@ static int
 indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
                     int len, u32 *val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        volatile void __iomem *cfg_data;
        u8 cfg_type = 0;
        u32 bus_no, reg;
@@ -82,7 +82,7 @@ static int
 indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
                      int len, u32 val)
 {
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        volatile void __iomem *cfg_data;
        u8 cfg_type = 0;
        u32 bus_no, reg;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 352d8c3ef526..9c3af5045495 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -613,23 +613,23 @@ static int irq_choose_cpu(unsigned int virt_irq)
 #define mpic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
 /* Find an mpic associated with a given linux interrupt */
-static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
+static struct mpic *mpic_find(unsigned int irq)
 {
-        unsigned int src = mpic_irq_to_hw(irq);
-        struct mpic *mpic;
        if (irq < NUM_ISA_INTERRUPTS)
                return NULL;
-        mpic = irq_desc[irq].chip_data;
+        return irq_desc[irq].chip_data;
+}
-        if (is_ipi)
+/* Determine if the linux irq is an IPI */
-                *is_ipi = (src >= mpic->ipi_vecs[0] &&
+static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
-                           src <= mpic->ipi_vecs[3]);
+{
+        unsigned int src = mpic_irq_to_hw(irq);
-        return mpic;
+        return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 }
 /* Convert a cpu mask from logical to physical cpu numbers. */
 static inline u32 mpic_physmask(u32 cpumask)
 {
@@ -1383,8 +1383,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable)
 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
 {
-        unsigned int is_ipi;
+        struct mpic *mpic = mpic_find(irq);
-        struct mpic *mpic = mpic_find(irq, &is_ipi);
        unsigned int src = mpic_irq_to_hw(irq);
        unsigned long flags;
        u32 reg;
@@ -1393,7 +1392,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
                return;
        spin_lock_irqsave(&mpic_lock, flags);
-        if (is_ipi) {
+        if (mpic_is_ipi(mpic, irq)) {
                reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
                        ~MPIC_VECPRI_PRIORITY_MASK;
                mpic_ipi_write(src - mpic->ipi_vecs[0],
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 6a2d473c345a..daefc93ddffe 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -1295,7 +1295,7 @@ static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port
 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
                                    int offset, int len, u32 *val)
 {
-        struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        struct ppc4xx_pciex_port *port =
                &ppc4xx_pciex_ports[hose->indirect_type];
        void __iomem *addr;
@@ -1352,7 +1352,7 @@ static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
                                     int offset, int len, u32 val)
 {
-        struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        struct ppc4xx_pciex_port *port =
                &ppc4xx_pciex_ports[hose->indirect_type];
        void __iomem *addr;
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 01bce3784b0a..b28b0e512d67 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -61,6 +61,7 @@ struct qe_immap __iomem *qe_immr;
 EXPORT_SYMBOL(qe_immr);
 static struct qe_snum snums[QE_NUM_OF_SNUM];    /* Dynamically allocated SNUMs */
+static unsigned int qe_num_of_snum;
 static phys_addr_t qebase = -1;
@@ -264,10 +265,14 @@ static void qe_snums_init(void)
                0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
                0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
                0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
-                0xD8, 0xD9, 0xE8, 0xE9,
+                0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
+                0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
+                0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
        };
-        for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+        qe_num_of_snum = qe_get_num_of_snums();
+        for (i = 0; i < qe_num_of_snum; i++) {
                snums[i].num = snum_init[i];
                snums[i].state = QE_SNUM_STATE_FREE;
        }
@@ -280,7 +285,7 @@ int qe_get_snum(void)
        int i;
        spin_lock_irqsave(&qe_lock, flags);
-        for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+        for (i = 0; i < qe_num_of_snum; i++) {
                if (snums[i].state == QE_SNUM_STATE_FREE) {
                        snums[i].state = QE_SNUM_STATE_USED;
                        snum = snums[i].num;
@@ -297,7 +302,7 @@ void qe_put_snum(u8 snum)
 {
        int i;
-        for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+        for (i = 0; i < qe_num_of_snum; i++) {
                if (snums[i].num == snum) {
                        snums[i].state = QE_SNUM_STATE_FREE;
                        break;
@@ -575,3 +580,65 @@ struct qe_firmware_info *qe_get_firmware_info(void)
 }
 EXPORT_SYMBOL(qe_get_firmware_info);
+unsigned int qe_get_num_of_risc(void)
+{
+        struct device_node *qe;
+        int size;
+        unsigned int num_of_risc = 0;
+        const u32 *prop;
+        qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!qe) {
+                /* Older devices trees did not have an "fsl,qe"
+                 * compatible property, so we need to look for
+                 * the QE node by name.
+                 */
+                qe = of_find_node_by_type(NULL, "qe");
+                if (!qe)
+                        return num_of_risc;
+        }
+        prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
+        if (prop && size == sizeof(*prop))
+                num_of_risc = *prop;
+        of_node_put(qe);
+        return num_of_risc;
+}
+EXPORT_SYMBOL(qe_get_num_of_risc);
+unsigned int qe_get_num_of_snums(void)
+{
+        struct device_node *qe;
+        int size;
+        unsigned int num_of_snums;
+        const u32 *prop;
+        num_of_snums = 28; /* The default number of snum for threads is 28 */
+        qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!qe) {
+                /* Older devices trees did not have an "fsl,qe"
+                 * compatible property, so we need to look for
+                 * the QE node by name.
+                 */
+                qe = of_find_node_by_type(NULL, "qe");
+                if (!qe)
+                        return num_of_snums;
+        }
+        prop = of_get_property(qe, "fsl,qe-num-snums", &size);
+        if (prop && size == sizeof(*prop)) {
+                num_of_snums = *prop;
+                if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
+                        /* No QE ever has fewer than 28 SNUMs */
+                        pr_err("QE: number of snum is invalid\n");
+                        return -EINVAL;
+                }
+        }
+        of_node_put(qe);
+        return num_of_snums;
+}
+EXPORT_SYMBOL(qe_get_num_of_snums);
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 24e1f5a197ae..cf244a419e96 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -63,7 +63,7 @@ tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
                           int offset, int len, u32 val)
 {
        volatile unsigned char *cfg_addr;
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        if (ppc_md.pci_exclude_device)
                if (ppc_md.pci_exclude_device(hose, bus->number, devfunc))
@@ -149,7 +149,7 @@ tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
                          int len, u32 * val)
 {
        volatile unsigned char *cfg_addr;
-        struct pci_controller *hose = bus->sysdata;
+        struct pci_controller *hose = pci_bus_to_host(bus);
        u32 temp;
        if (ppc_md.pci_exclude_device)
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index c658b413c9b4..3ee1fd37bbfc 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -25,6 +25,7 @@
 #include <linux/of.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/i8259.h>
 #include <asm/irq.h>
 /*
@@ -191,20 +192,14 @@ struct irq_host * __init
 xilinx_intc_init(struct device_node *np)
 {
        struct irq_host * irq;
-        struct resource res;
        void * regs;
-        int rc;
        /* Find and map the intc registers */
-        rc = of_address_to_resource(np, 0, &res);
+        regs = of_iomap(np, 0);
-        if (rc) {
+        if (!regs) {
-                printk(KERN_ERR __FILE__ ": of_address_to_resource() failed\n");
+                pr_err("xilinx_intc: could not map registers\n");
                return NULL;
        }
-        regs = ioremap(res.start, 32);
-        printk(KERN_INFO "Xilinx intc at 0x%08llx mapped to 0x%p\n",
-                (unsigned long long) res.start, regs);
        /* Setup interrupt controller */
        out_be32(regs + XINTC_IER, 0); /* disable all irqs */
@@ -217,6 +212,7 @@ xilinx_intc_init(struct device_node *np)
        if (!irq)
                panic(__FILE__ ": Cannot allocate IRQ host\n");
        irq->host_data = regs;
        return irq;
 }
@@ -227,23 +223,70 @@ int xilinx_intc_get_irq(void)
        return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
 }
+#if defined(CONFIG_PPC_I8259)
+/*
+ * Support code for cascading to 8259 interrupt controllers
+ */
+static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned int cascade_irq = i8259_irq();
+        if (cascade_irq)
+                generic_handle_irq(cascade_irq);
+        /* Let xilinx_intc end the interrupt */
+        desc->chip->ack(irq);
+        desc->chip->unmask(irq);
+}
+static void __init xilinx_i8259_setup_cascade(void)
+{
+        struct device_node *cascade_node;
+        int cascade_irq;
+        /* Initialize i8259 controller */
+        cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
+        if (!cascade_node)
+                return;
+        cascade_irq = irq_of_parse_and_map(cascade_node, 0);
+        if (!cascade_irq) {
+                pr_err("virtex_ml510: Failed to map cascade interrupt\n");
+                goto out;
+        }
+        i8259_init(cascade_node, 0);
+        set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
+        /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
+        /* This looks like a dirty hack to me --gcl */
+        outb(0xc0, 0x4d0);
+        outb(0xc0, 0x4d1);
+ out:
+        of_node_put(cascade_node);
+}
+#else
+static inline void xilinx_i8259_setup_cascade(void) { return; }
+#endif /* defined(CONFIG_PPC_I8259) */
+static struct of_device_id xilinx_intc_match[] __initconst = {
+        { .compatible = "xlnx,opb-intc-1.00.c", },
+        { .compatible = "xlnx,xps-intc-1.00.a", },
+        {}
+};
+/*
+ * Initialize master Xilinx interrupt controller
+ */
 void __init xilinx_intc_init_tree(void)
 {
        struct device_node *np;
        /* find top level interrupt controller */
-        for_each_compatible_node(np, NULL, "xlnx,opb-intc-1.00.c") {
+        for_each_matching_node(np, xilinx_intc_match) {
                if (!of_get_property(np, "interrupts", NULL))
                        break;
        }
-        if (!np) {
-                for_each_compatible_node(np, NULL, "xlnx,xps-intc-1.00.a") {
-                        if (!of_get_property(np, "interrupts", NULL))
-                                break;
-                }
-        }
-        /* xilinx interrupt controller needs to be top level */
        BUG_ON(!np);
        master_irqhost = xilinx_intc_init(np);
@@ -251,4 +294,6 @@ void __init xilinx_intc_init_tree(void)
        irq_set_default_host(master_irqhost);
        of_node_put(np);
+        xilinx_i8259_setup_cascade();
 }
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c
new file mode 100644
index 000000000000..1453b0eed220
--- /dev/null
+++ b/arch/powerpc/sysdev/xilinx_pci.c
@@ -0,0 +1,132 @@
+/*
+ * PCI support for Xilinx plbv46_pci soft-core which can be used on
+ * Xilinx Virtex ML410 / ML510 boards.
+ *
+ * Copyright 2009 Roderick Colenbrander
+ * Copyright 2009 Secret Lab Technologies Ltd.
+ *
+ * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
+ * by Benjamin Herrenschmidt.
+ * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include <linux/ioport.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <mm/mmu_decl.h>
+#include <asm/io.h>
+#include <asm/xilinx_pci.h>
+#define XPLB_PCI_ADDR 0x10c
+#define XPLB_PCI_DATA 0x110
+#define XPLB_PCI_BUS  0x114
+#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+static struct of_device_id xilinx_pci_match[] = {
+        { .compatible = "xlnx,plbv46-pci-1.03.a", },
+        {}
+};
+/**
+ * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
+ */
+static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
+{
+        struct pci_controller *hose;
+        int i;
+        if (dev->devfn || dev->bus->self)
+                return;
+        hose = pci_bus_to_host(dev->bus);
+        if (!hose)
+                return;
+        if (!of_match_node(xilinx_pci_match, hose->dn))
+                return;
+        /* Hide the PCI host BARs from the kernel as their content doesn't
+         * fit well in the resource management
+         */
+        for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                dev->resource[i].start = 0;
+                dev->resource[i].end = 0;
+                dev->resource[i].flags = 0;
+        }
+        dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
+                 pci_name(dev));
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
+/**
+ * xilinx_pci_exclude_device - Don't do config access for non-root bus
+ *
+ * This is a hack.  Config access to any bus other than bus 0 does not
+ * currently work on the ML510 so we prevent it here.
+ */
+static int
+xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
+{
+        return (bus != 0);
+}
+/**
+ * xilinx_pci_init - Find and register a Xilinx PCI host bridge
+ */
+void __init xilinx_pci_init(void)
+{
+        struct pci_controller *hose;
+        struct resource r;
+        void __iomem *pci_reg;
+        struct device_node *pci_node;
+        pci_node = of_find_matching_node(NULL, xilinx_pci_match);
+        if(!pci_node)
+                return;
+        if (of_address_to_resource(pci_node, 0, &r)) {
+                pr_err("xilinx-pci: cannot resolve base address\n");
+                return;
+        }
+        hose = pcibios_alloc_controller(pci_node);
+        if (!hose) {
+                pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
+                return;
+        }
+        /* Setup config space */
+        setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
+                           r.start + XPLB_PCI_DATA,
+                           PPC_INDIRECT_TYPE_SET_CFG_TYPE);
+        /* According to the xilinx plbv46_pci documentation the soft-core starts
+         * a self-init when the bus master enable bit is set. Without this bit
+         * set the pci bus can't be scanned.
+         */
+        early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
+        /* Set the max latency timer to 255 */
+        early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
+        /* Set the max bus number to 255 */
+        pci_reg = of_iomap(pci_node, 0);
+        out_8(pci_reg + XPLB_PCI_BUS, 0xff);
+        iounmap(pci_reg);
+        /* Nothing past the root bridge is working right now.  By default
+         * exclude config access to anything except bus 0 */
+        if (!ppc_md.pci_exclude_device)
+                ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
+        /* Register the host bridge with the linux kernel! */
+        pci_process_bridge_OF_ranges(hose, pci_node, 1);
+        pr_info("xilinx-pci: Registered PCI host bridge\n");
+}
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 8dfad7d9a004..e1f33a81e5e1 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -110,6 +110,7 @@ static int bsesc(void);
 static void dump(void);
 static void prdump(unsigned long, long);
 static int ppc_inst_dump(unsigned long, long, int);
+static void dump_log_buf(void);
 static void backtrace(struct pt_regs *);
 static void excprint(struct pt_regs *);
 static void prregs(struct pt_regs *);
@@ -197,6 +198,7 @@ Commands:\n\
  di    dump instructions\n\
  df    dump float values\n\
  dd    dump double values\n\
+  dl    dump the kernel log buffer\n\
  dr    dump stream of raw bytes\n\
  e     print exception information\n\
  f     flush cache\n\
@@ -2009,6 +2011,8 @@ dump(void)
                        nidump = MAX_DUMP;
                adrs += ppc_inst_dump(adrs, nidump, 1);
                last_cmd = "di\n";
+        } else if (c == 'l') {
+                dump_log_buf();
        } else if (c == 'r') {
                scanhex(&ndump);
                if (ndump == 0)
@@ -2122,6 +2126,49 @@ print_address(unsigned long addr)
        xmon_print_symbol(addr, "\t# ", "");
 }
+void
+dump_log_buf(void)
+{
+        const unsigned long size = 128;
+        unsigned long end, addr;
+        unsigned char buf[size + 1];
+        addr = 0;
+        buf[size] = '\0';
+        if (setjmp(bus_error_jmp) != 0) {
+                printf("Unable to lookup symbol __log_buf!\n");
+                return;
+        }
+        catch_memory_errors = 1;
+        sync();
+        addr = kallsyms_lookup_name("__log_buf");
+        if (! addr)
+                printf("Symbol __log_buf not found!\n");
+        else {
+                end = addr + (1 << CONFIG_LOG_BUF_SHIFT);
+                while (addr < end) {
+                        if (! mread(addr, buf, size)) {
+                                printf("Can't read memory at address 0x%lx\n", addr);
+                                break;
+                        }
+                        printf("%s", buf);
+                        if (strlen(buf) < size)
+                                break;
+                        addr += size;
+                }
+        }
+        sync();
+        /* wait a little while to see if we get a machine check */
+        __delay(200);
+        catch_memory_errors = 0;
+}
 /*
 * Memory operations - move, set, print differences
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 99dc3ded6b49..a14dba0e4d67 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -348,6 +348,9 @@ config ARCH_ENABLE_MEMORY_HOTPLUG
 config ARCH_ENABLE_MEMORY_HOTREMOVE
        def_bool y
+config ARCH_HIBERNATION_POSSIBLE
+       def_bool y if 64BIT
 source "mm/Kconfig"
 comment "I/O subsystem configuration"
@@ -592,6 +595,12 @@ config SECCOMP
 endmenu
+menu "Power Management"
+source "kernel/power/Kconfig"
+endmenu
 source "net/Kconfig"
 config PCMCIA
diff --git a/arch/s390/Makefile b/arch/s390/Makefile
index 578c61f15a4b..0ff387cebf88 100644
--- a/arch/s390/Makefile
+++ b/arch/s390/Makefile
@@ -88,7 +88,9 @@ LDFLAGS_vmlinux := -e start
 head-y          := arch/s390/kernel/head.o arch/s390/kernel/init_task.o
 core-y          += arch/s390/mm/ arch/s390/kernel/ arch/s390/crypto/ \
-                   arch/s390/appldata/ arch/s390/hypfs/ arch/s390/kvm/
+                   arch/s390/appldata/ arch/s390/hypfs/ arch/s390/kvm/ \
+                   arch/s390/power/
 libs-y          += arch/s390/lib/
 drivers-y       += drivers/s390/
 drivers-$(CONFIG_MATHEMU) += arch/s390/math-emu/
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index 1dfc7100c7ee..264528e4f58d 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -5,7 +5,7 @@
 * Exports appldata_register_ops() and appldata_unregister_ops() for the
 * data gathering modules.
 *
- * Copyright IBM Corp. 2003, 2008
+ * Copyright IBM Corp. 2003, 2009
 *
 * Author: Gerald Schaefer <gerald.schaefer@de.ibm.com>
 */
@@ -26,6 +26,8 @@
 #include <linux/notifier.h>
 #include <linux/cpu.h>
 #include <linux/workqueue.h>
+#include <linux/suspend.h>
+#include <linux/platform_device.h>
 #include <asm/appldata.h>
 #include <asm/timer.h>
 #include <asm/uaccess.h>
@@ -41,6 +43,9 @@
 #define TOD_MICRO       0x01000                 /* nr. of TOD clock units
                                                   for 1 microsecond */
+static struct platform_device *appldata_pdev;
 /*
 * /proc entries (sysctl)
 */
@@ -86,6 +91,7 @@ static atomic_t appldata_expire_count = ATOMIC_INIT(0);
 static DEFINE_SPINLOCK(appldata_timer_lock);
 static int appldata_interval = APPLDATA_CPU_INTERVAL;
 static int appldata_timer_active;
+static int appldata_timer_suspended = 0;
 /*
 * Work queue
@@ -475,6 +481,93 @@ void appldata_unregister_ops(struct appldata_ops *ops)
 /********************** module-ops management <END> **************************/
+/**************************** suspend / resume *******************************/
+static int appldata_freeze(struct device *dev)
+{
+        struct appldata_ops *ops;
+        int rc;
+        struct list_head *lh;
+        get_online_cpus();
+        spin_lock(&appldata_timer_lock);
+        if (appldata_timer_active) {
+                __appldata_vtimer_setup(APPLDATA_DEL_TIMER);
+                appldata_timer_suspended = 1;
+        }
+        spin_unlock(&appldata_timer_lock);
+        put_online_cpus();
+        mutex_lock(&appldata_ops_mutex);
+        list_for_each(lh, &appldata_ops_list) {
+                ops = list_entry(lh, struct appldata_ops, list);
+                if (ops->active == 1) {
+                        rc = appldata_diag(ops->record_nr, APPLDATA_STOP_REC,
+                                        (unsigned long) ops->data, ops->size,
+                                        ops->mod_lvl);
+                        if (rc != 0)
+                                pr_err("Stopping the data collection for %s "
+                                       "failed with rc=%d\n", ops->name, rc);
+                }
+        }
+        mutex_unlock(&appldata_ops_mutex);
+        return 0;
+}
+static int appldata_restore(struct device *dev)
+{
+        struct appldata_ops *ops;
+        int rc;
+        struct list_head *lh;
+        get_online_cpus();
+        spin_lock(&appldata_timer_lock);
+        if (appldata_timer_suspended) {
+                __appldata_vtimer_setup(APPLDATA_ADD_TIMER);
+                appldata_timer_suspended = 0;
+        }
+        spin_unlock(&appldata_timer_lock);
+        put_online_cpus();
+        mutex_lock(&appldata_ops_mutex);
+        list_for_each(lh, &appldata_ops_list) {
+                ops = list_entry(lh, struct appldata_ops, list);
+                if (ops->active == 1) {
+                        ops->callback(ops->data);       // init record
+                        rc = appldata_diag(ops->record_nr,
+                                        APPLDATA_START_INTERVAL_REC,
+                                        (unsigned long) ops->data, ops->size,
+                                        ops->mod_lvl);
+                        if (rc != 0) {
+                                pr_err("Starting the data collection for %s "
+                                       "failed with rc=%d\n", ops->name, rc);
+                        }
+                }
+        }
+        mutex_unlock(&appldata_ops_mutex);
+        return 0;
+}
+static int appldata_thaw(struct device *dev)
+{
+        return appldata_restore(dev);
+}
+static struct dev_pm_ops appldata_pm_ops = {
+        .freeze         = appldata_freeze,
+        .thaw           = appldata_thaw,
+        .restore        = appldata_restore,
+};
+static struct platform_driver appldata_pdrv = {
+        .driver = {
+                .name   = "appldata",
+                .owner  = THIS_MODULE,
+                .pm     = &appldata_pm_ops,
+        },
+};
+/************************* suspend / resume <END> ****************************/
 /******************************* init / exit *********************************/
 static void __cpuinit appldata_online_cpu(int cpu)
@@ -531,11 +624,23 @@ static struct notifier_block __cpuinitdata appldata_nb = {
 */
 static int __init appldata_init(void)
 {
-        int i;
+        int i, rc;
+        rc = platform_driver_register(&appldata_pdrv);
+        if (rc)
+                return rc;
+        appldata_pdev = platform_device_register_simple("appldata", -1, NULL,
+                                                        0);
+        if (IS_ERR(appldata_pdev)) {
+                rc = PTR_ERR(appldata_pdev);
+                goto out_driver;
+        }
        appldata_wq = create_singlethread_workqueue("appldata");
-        if (!appldata_wq)
+        if (!appldata_wq) {
-                return -ENOMEM;
+                rc = -ENOMEM;
+                goto out_device;
+        }
        get_online_cpus();
        for_each_online_cpu(i)
@@ -547,6 +652,12 @@ static int __init appldata_init(void)
        appldata_sysctl_header = register_sysctl_table(appldata_dir_table);
        return 0;
+out_device:
+        platform_device_unregister(appldata_pdev);
+out_driver:
+        platform_driver_unregister(&appldata_pdrv);
+        return rc;
 }
 __initcall(appldata_init);
diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h
index ba007d8df941..2a5419551176 100644
--- a/arch/s390/include/asm/ccwdev.h
+++ b/arch/s390/include/asm/ccwdev.h
@@ -1,11 +1,9 @@
 /*
- *  include/asm-s390/ccwdev.h
+ * Copyright  IBM Corp. 2002, 2009
- *  include/asm-s390x/ccwdev.h
 *
- *    Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ * Author(s): Arnd Bergmann <arndb@de.ibm.com>
- *    Author(s): Arnd Bergmann <arndb@de.ibm.com>
 *
- *  Interface for CCW device drivers
+ * Interface for CCW device drivers
 */
 #ifndef _S390_CCWDEV_H_
 #define _S390_CCWDEV_H_
@@ -104,6 +102,11 @@ struct ccw_device {
 * @set_offline: called when setting device offline
 * @notify: notify driver of device state changes
 * @shutdown: called at device shutdown
+ * @prepare: prepare for pm state transition
+ * @complete: undo work done in @prepare
+ * @freeze: callback for freezing during hibernation snapshotting
+ * @thaw: undo work done in @freeze
+ * @restore: callback for restoring after hibernation
 * @driver: embedded device driver structure
 * @name: device driver name
 */
@@ -116,6 +119,11 @@ struct ccw_driver {
        int (*set_offline) (struct ccw_device *);
        int (*notify) (struct ccw_device *, int);
        void (*shutdown) (struct ccw_device *);
+        int (*prepare) (struct ccw_device *);
+        void (*complete) (struct ccw_device *);
+        int (*freeze)(struct ccw_device *);
+        int (*thaw) (struct ccw_device *);
+        int (*restore)(struct ccw_device *);
        struct device_driver driver;
        char *name;
 };
@@ -184,6 +192,7 @@ extern void ccw_device_get_id(struct ccw_device *, struct ccw_dev_id *);
 #define to_ccwdrv(n) container_of(n, struct ccw_driver, driver)
 extern struct ccw_device *ccw_device_probe_console(void);
+extern int ccw_device_force_console(void);
 // FIXME: these have to go
 extern int _ccw_device_get_subchannel_number(struct ccw_device *);
diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h
index a27f68985a79..c79c1e787b86 100644
--- a/arch/s390/include/asm/ccwgroup.h
+++ b/arch/s390/include/asm/ccwgroup.h
@@ -38,6 +38,11 @@ struct ccwgroup_device {
 * @set_online: function called when device is set online
 * @set_offline: function called when device is set offline
 * @shutdown: function called when device is shut down
+ * @prepare: prepare for pm state transition
+ * @complete: undo work done in @prepare
+ * @freeze: callback for freezing during hibernation snapshotting
+ * @thaw: undo work done in @freeze
+ * @restore: callback for restoring after hibernation
 * @driver: embedded driver structure
 */
 struct ccwgroup_driver {
@@ -51,6 +56,11 @@ struct ccwgroup_driver {
        int (*set_online) (struct ccwgroup_device *);
        int (*set_offline) (struct ccwgroup_device *);
        void (*shutdown)(struct ccwgroup_device *);
+        int (*prepare) (struct ccwgroup_device *);
+        void (*complete) (struct ccwgroup_device *);
+        int (*freeze)(struct ccwgroup_device *);
+        int (*thaw) (struct ccwgroup_device *);
+        int (*restore)(struct ccwgroup_device *);
        struct device_driver driver;
 };
diff --git a/arch/s390/include/asm/kmap_types.h b/arch/s390/include/asm/kmap_types.h
index fd1574648223..94ec3ee07983 100644
--- a/arch/s390/include/asm/kmap_types.h
+++ b/arch/s390/include/asm/kmap_types.h
@@ -2,22 +2,7 @@
 #ifndef _ASM_KMAP_TYPES_H
 #define _ASM_KMAP_TYPES_H
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,    
-        KM_TYPE_NR
-};
 #endif
 #endif /* __KERNEL__ */
diff --git a/arch/s390/include/asm/suspend.h b/arch/s390/include/asm/suspend.h
new file mode 100644
index 000000000000..dc75c616eafe
--- /dev/null
+++ b/arch/s390/include/asm/suspend.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_S390_SUSPEND_H
+#define __ASM_S390_SUSPEND_H
+static inline int arch_prepare_suspend(void)
+{
+        return 0;
+}
+#endif
diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h
index 3a8b26eb1f2e..4fb83c1cdb77 100644
--- a/arch/s390/include/asm/system.h
+++ b/arch/s390/include/asm/system.h
@@ -1,11 +1,7 @@
 /*
- *  include/asm-s390/system.h
+ * Copyright IBM Corp. 1999, 2009
 *
- *  S390 version
+ * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
- *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
- *
- *  Derived from "include/asm-i386/system.h"
 */
 #ifndef __ASM_SYSTEM_H
@@ -469,6 +465,20 @@ extern psw_t sysc_restore_trace_psw;
 extern psw_t io_restore_trace_psw;
 #endif
+static inline int tprot(unsigned long addr)
+{
+        int rc = -EFAULT;
+        asm volatile(
+                "       tprot   0(%1),0\n"
+                "0:     ipm     %0\n"
+                "       srl     %0,28\n"
+                "1:\n"
+                EX_TABLE(0b,1b)
+                : "+d" (rc) : "a" (addr) : "cc");
+        return rc;
+}
 #endif /* __KERNEL__ */
 #endif
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index fb263736826c..f9b144049dc9 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -1,7 +1,7 @@
 /*
 *  arch/s390/kernel/early.c
 *
- *    Copyright IBM Corp. 2007
+ *    Copyright IBM Corp. 2007, 2009
 *    Author(s): Hongjie Yang <hongjie@us.ibm.com>,
 *               Heiko Carstens <heiko.carstens@de.ibm.com>
 */
@@ -210,7 +210,7 @@ static noinline __init void detect_machine_type(void)
                machine_flags |= MACHINE_FLAG_VM;
 }
-static __init void early_pgm_check_handler(void)
+static void early_pgm_check_handler(void)
 {
        unsigned long addr;
        const struct exception_table_entry *fixup;
@@ -222,7 +222,7 @@ static __init void early_pgm_check_handler(void)
        S390_lowcore.program_old_psw.addr = fixup->fixup | PSW_ADDR_AMODE;
 }
-static noinline __init void setup_lowcore_early(void)
+void setup_lowcore_early(void)
 {
        psw_t psw;
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index 6d227413cbe7..ec6882348520 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -62,7 +62,7 @@ __HEAD
        .org   0x100
 #
 # subroutine for loading from tape
-# Paramters:
+# Parameters:
 #  R1 = device number
 #  R2 = load address
 .Lloader:
diff --git a/arch/s390/kernel/init_task.c b/arch/s390/kernel/init_task.c
index 7db95c0b8693..fe787f9e5f3f 100644
--- a/arch/s390/kernel/init_task.c
+++ b/arch/s390/kernel/init_task.c
@@ -18,10 +18,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/s390/kernel/mem_detect.c b/arch/s390/kernel/mem_detect.c
index 9872999c66d1..559af0d07878 100644
--- a/arch/s390/kernel/mem_detect.c
+++ b/arch/s390/kernel/mem_detect.c
@@ -1,6 +1,7 @@
 /*
- *    Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008, 2009
- *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ *
+ * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
 */
 #include <linux/kernel.h>
@@ -9,20 +10,6 @@
 #include <asm/sclp.h>
 #include <asm/setup.h>
-static inline int tprot(unsigned long addr)
-{
-        int rc = -EFAULT;
-        asm volatile(
-                "       tprot   0(%1),0\n"
-                "0:     ipm     %0\n"
-                "       srl     %0,28\n"
-                "1:\n"
-                EX_TABLE(0b,1b)
-                : "+d" (rc) : "a" (addr) : "cc");
-        return rc;
-}
 #define ADDR2G (1ULL << 31)
 static void find_memory_chunks(struct mem_chunk chunk[])
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index cc8c484984e3..fd8e3111a4e8 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -1,7 +1,7 @@
 /*
 *  arch/s390/kernel/smp.c
 *
- *    Copyright IBM Corp. 1999,2007
+ *    Copyright IBM Corp. 1999, 2009
 *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *               Heiko Carstens (heiko.carstens@de.ibm.com)
@@ -1031,6 +1031,42 @@ out:
 static SYSDEV_CLASS_ATTR(dispatching, 0644, dispatching_show,
                         dispatching_store);
+/*
+ * If the resume kernel runs on another cpu than the suspended kernel,
+ * we have to switch the cpu IDs in the logical map.
+ */
+void smp_switch_boot_cpu_in_resume(u32 resume_phys_cpu_id,
+                                   struct _lowcore *suspend_lowcore)
+{
+        int cpu, suspend_cpu_id, resume_cpu_id;
+        u32 suspend_phys_cpu_id;
+        suspend_phys_cpu_id = __cpu_logical_map[suspend_lowcore->cpu_nr];
+        suspend_cpu_id = suspend_lowcore->cpu_nr;
+        for_each_present_cpu(cpu) {
+                if (__cpu_logical_map[cpu] == resume_phys_cpu_id) {
+                        resume_cpu_id = cpu;
+                        goto found;
+                }
+        }
+        panic("Could not find resume cpu in logical map.\n");
+found:
+        printk("Resume  cpu ID: %i/%i\n", resume_phys_cpu_id, resume_cpu_id);
+        printk("Suspend cpu ID: %i/%i\n", suspend_phys_cpu_id, suspend_cpu_id);
+        __cpu_logical_map[resume_cpu_id] = suspend_phys_cpu_id;
+        __cpu_logical_map[suspend_cpu_id] = resume_phys_cpu_id;
+        lowcore_ptr[suspend_cpu_id]->cpu_addr = resume_phys_cpu_id;
+}
+u32 smp_get_phys_cpu_id(void)
+{
+        return __cpu_logical_map[smp_processor_id()];
+}
 static int __init topology_init(void)
 {
        int cpu;
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 4ca8e826bf30..565667207985 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -313,3 +313,22 @@ int s390_enable_sie(void)
        return 0;
 }
 EXPORT_SYMBOL_GPL(s390_enable_sie);
+#ifdef CONFIG_DEBUG_PAGEALLOC
+#ifdef CONFIG_HIBERNATION
+bool kernel_page_present(struct page *page)
+{
+        unsigned long addr;
+        int cc;
+        addr = page_to_phys(page);
+        asm("lra %1,0(%1)\n"
+            "ipm %0\n"
+            "srl %0,28"
+            :"=d"(cc),"+a"(addr)::"cc");
+        return cc == 0;
+}
+#endif /* CONFIG_HIBERNATION */
+#endif /* CONFIG_DEBUG_PAGEALLOC */
diff --git a/arch/s390/power/Makefile b/arch/s390/power/Makefile
new file mode 100644
index 000000000000..973bb45a8fec
--- /dev/null
+++ b/arch/s390/power/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for s390 PM support
+#
+obj-$(CONFIG_HIBERNATION) += suspend.o
+obj-$(CONFIG_HIBERNATION) += swsusp.o
+obj-$(CONFIG_HIBERNATION) += swsusp_64.o
+obj-$(CONFIG_HIBERNATION) += swsusp_asm64.o
diff --git a/arch/s390/power/suspend.c b/arch/s390/power/suspend.c
new file mode 100644
index 000000000000..b3351eceebbe
--- /dev/null
+++ b/arch/s390/power/suspend.c
@@ -0,0 +1,40 @@
+/*
+ * Suspend support specific for s390.
+ *
+ * Copyright IBM Corp. 2009
+ *
+ * Author(s): Hans-Joachim Picht <hans@linux.vnet.ibm.com>
+ */
+#include <linux/mm.h>
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+#include <linux/pfn.h>
+#include <asm/sections.h>
+#include <asm/ipl.h>
+/*
+ * References to section boundaries
+ */
+extern const void __nosave_begin, __nosave_end;
+/*
+ *  check if given pfn is in the 'nosave' or in the read only NSS section
+ */
+int pfn_is_nosave(unsigned long pfn)
+{
+        unsigned long nosave_begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT;
+        unsigned long nosave_end_pfn = PAGE_ALIGN(__pa(&__nosave_end))
+                                        >> PAGE_SHIFT;
+        unsigned long eshared_pfn = PFN_DOWN(__pa(&_eshared)) - 1;
+        unsigned long stext_pfn = PFN_DOWN(__pa(&_stext));
+        if (pfn >= nosave_begin_pfn && pfn < nosave_end_pfn)
+                return 1;
+        if (pfn >= stext_pfn && pfn <= eshared_pfn) {
+                if (ipl_info.type == IPL_TYPE_NSS)
+                        return 1;
+        } else if ((tprot(pfn * PAGE_SIZE) && pfn > 0))
+                return 1;
+        return 0;
+}
diff --git a/arch/s390/power/swsusp.c b/arch/s390/power/swsusp.c
new file mode 100644
index 000000000000..e6a4fe9f5f24
--- /dev/null
+++ b/arch/s390/power/swsusp.c
@@ -0,0 +1,30 @@
+/*
+ * Support for suspend and resume on s390
+ *
+ * Copyright IBM Corp. 2009
+ *
+ * Author(s): Hans-Joachim Picht <hans@linux.vnet.ibm.com>
+ *
+ */
+/*
+ * save CPU registers before creating a hibernation image and before
+ * restoring the memory state from it
+ */
+void save_processor_state(void)
+{
+        /* implentation contained in the
+         * swsusp_arch_suspend function
+         */
+}
+/*
+ * restore the contents of CPU registers
+ */
+void restore_processor_state(void)
+{
+        /* implentation contained in the
+         * swsusp_arch_resume function
+         */
+}
diff --git a/arch/s390/power/swsusp_64.c b/arch/s390/power/swsusp_64.c
new file mode 100644
index 000000000000..9516a517d72f
--- /dev/null
+++ b/arch/s390/power/swsusp_64.c
@@ -0,0 +1,17 @@
+/*
+ * Support for suspend and resume on s390
+ *
+ * Copyright IBM Corp. 2009
+ *
+ * Author(s): Hans-Joachim Picht <hans@linux.vnet.ibm.com>
+ *
+ */
+#include <asm/system.h>
+#include <linux/interrupt.h>
+void do_after_copyback(void)
+{
+        mb();
+}
diff --git a/arch/s390/power/swsusp_asm64.S b/arch/s390/power/swsusp_asm64.S
new file mode 100644
index 000000000000..3c74e7d827c9
--- /dev/null
+++ b/arch/s390/power/swsusp_asm64.S
@@ -0,0 +1,199 @@
+/*
+ * S390 64-bit swsusp implementation
+ *
+ * Copyright IBM Corp. 2009
+ *
+ * Author(s): Hans-Joachim Picht <hans@linux.vnet.ibm.com>
+ *            Michael Holzheu <holzheu@linux.vnet.ibm.com>
+ */
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+/*
+ * Save register context in absolute 0 lowcore and call swsusp_save() to
+ * create in-memory kernel image. The context is saved in the designated
+ * "store status" memory locations (see POP).
+ * We return from this function twice. The first time during the suspend to
+ * disk process. The second time via the swsusp_arch_resume() function
+ * (see below) in the resume process.
+ * This function runs with disabled interrupts.
+ */
+        .section .text
+        .align  2
+        .globl swsusp_arch_suspend
+swsusp_arch_suspend:
+        stmg    %r6,%r15,__SF_GPRS(%r15)
+        lgr     %r1,%r15
+        aghi    %r15,-STACK_FRAME_OVERHEAD
+        stg     %r1,__SF_BACKCHAIN(%r15)
+        /* Deactivate DAT */
+        stnsm   __SF_EMPTY(%r15),0xfb
+        /* Switch off lowcore protection */
+        stctg   %c0,%c0,__SF_EMPTY(%r15)
+        ni      __SF_EMPTY+4(%r15),0xef
+        lctlg   %c0,%c0,__SF_EMPTY(%r15)
+        /* Store prefix register on stack */
+        stpx    __SF_EMPTY(%r15)
+        /* Setup base register for lowcore (absolute 0) */
+        llgf    %r1,__SF_EMPTY(%r15)
+        /* Get pointer to save area */
+        aghi    %r1,0x1000
+        /* Store registers */
+        mvc     0x318(4,%r1),__SF_EMPTY(%r15)   /* move prefix to lowcore */
+        stfpc   0x31c(%r1)                      /* store fpu control */
+        std     0,0x200(%r1)                    /* store f0 */
+        std     1,0x208(%r1)                    /* store f1 */
+        std     2,0x210(%r1)                    /* store f2 */
+        std     3,0x218(%r1)                    /* store f3 */
+        std     4,0x220(%r1)                    /* store f4 */
+        std     5,0x228(%r1)                    /* store f5 */
+        std     6,0x230(%r1)                    /* store f6 */
+        std     7,0x238(%r1)                    /* store f7 */
+        std     8,0x240(%r1)                    /* store f8 */
+        std     9,0x248(%r1)                    /* store f9 */
+        std     10,0x250(%r1)                   /* store f10 */
+        std     11,0x258(%r1)                   /* store f11 */
+        std     12,0x260(%r1)                   /* store f12 */
+        std     13,0x268(%r1)                   /* store f13 */
+        std     14,0x270(%r1)                   /* store f14 */
+        std     15,0x278(%r1)                   /* store f15 */
+        stam    %a0,%a15,0x340(%r1)             /* store access registers */
+        stctg   %c0,%c15,0x380(%r1)             /* store control registers */
+        stmg    %r0,%r15,0x280(%r1)             /* store general registers */
+        stpt    0x328(%r1)                      /* store timer */
+        stckc   0x330(%r1)                      /* store clock comparator */
+        /* Activate DAT */
+        stosm   __SF_EMPTY(%r15),0x04
+        /* Set prefix page to zero */
+        xc      __SF_EMPTY(4,%r15),__SF_EMPTY(%r15)
+        spx     __SF_EMPTY(%r15)
+        /* Setup lowcore */
+        brasl   %r14,setup_lowcore_early
+        /* Save image */
+        brasl   %r14,swsusp_save
+        /* Switch on lowcore protection */
+        stctg   %c0,%c0,__SF_EMPTY(%r15)
+        oi      __SF_EMPTY+4(%r15),0x10
+        lctlg   %c0,%c0,__SF_EMPTY(%r15)
+        /* Restore prefix register and return */
+        lghi    %r1,0x1000
+        spx     0x318(%r1)
+        lmg     %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15)
+        lghi    %r2,0
+        br      %r14
+/*
+ * Restore saved memory image to correct place and restore register context.
+ * Then we return to the function that called swsusp_arch_suspend().
+ * swsusp_arch_resume() runs with disabled interrupts.
+ */
+        .globl swsusp_arch_resume
+swsusp_arch_resume:
+        stmg    %r6,%r15,__SF_GPRS(%r15)
+        lgr     %r1,%r15
+        aghi    %r15,-STACK_FRAME_OVERHEAD
+        stg     %r1,__SF_BACKCHAIN(%r15)
+        /* Save boot cpu number */
+        brasl   %r14,smp_get_phys_cpu_id
+        lgr     %r10,%r2
+        /* Deactivate DAT */
+        stnsm   __SF_EMPTY(%r15),0xfb
+        /* Switch off lowcore protection */
+        stctg   %c0,%c0,__SF_EMPTY(%r15)
+        ni      __SF_EMPTY+4(%r15),0xef
+        lctlg   %c0,%c0,__SF_EMPTY(%r15)
+        /* Set prefix page to zero */
+        xc      __SF_EMPTY(4,%r15),__SF_EMPTY(%r15)
+        spx     __SF_EMPTY(%r15)
+        /* Restore saved image */
+        larl    %r1,restore_pblist
+        lg      %r1,0(%r1)
+        ltgr    %r1,%r1
+        jz      2f
+0:
+        lg      %r2,8(%r1)
+        lg      %r4,0(%r1)
+        lghi    %r3,PAGE_SIZE
+        lghi    %r5,PAGE_SIZE
+1:
+        mvcle   %r2,%r4,0
+        jo      1b
+        lg      %r1,16(%r1)
+        ltgr    %r1,%r1
+        jnz     0b
+2:
+        ptlb                            /* flush tlb */
+        /* Restore registers */
+        lghi    %r13,0x1000             /* %r1 = pointer to save arae */
+        spt     0x328(%r13)             /* reprogram timer */
+        //sckc  0x330(%r13)             /* set clock comparator */
+        lctlg   %c0,%c15,0x380(%r13)    /* load control registers */
+        lam     %a0,%a15,0x340(%r13)    /* load access registers */
+        lfpc    0x31c(%r13)             /* load fpu control */
+        ld      0,0x200(%r13)           /* load f0 */
+        ld      1,0x208(%r13)           /* load f1 */
+        ld      2,0x210(%r13)           /* load f2 */
+        ld      3,0x218(%r13)           /* load f3 */
+        ld      4,0x220(%r13)           /* load f4 */
+        ld      5,0x228(%r13)           /* load f5 */
+        ld      6,0x230(%r13)           /* load f6 */
+        ld      7,0x238(%r13)           /* load f7 */
+        ld      8,0x240(%r13)           /* load f8 */
+        ld      9,0x248(%r13)           /* load f9 */
+        ld      10,0x250(%r13)          /* load f10 */
+        ld      11,0x258(%r13)          /* load f11 */
+        ld      12,0x260(%r13)          /* load f12 */
+        ld      13,0x268(%r13)          /* load f13 */
+        ld      14,0x270(%r13)          /* load f14 */
+        ld      15,0x278(%r13)          /* load f15 */
+        /* Load old stack */
+        lg      %r15,0x2f8(%r13)
+        /* Pointer to save arae */
+        lghi    %r13,0x1000
+        /* Switch CPUs */
+        lgr     %r2,%r10                /* get cpu id */
+        llgf    %r3,0x318(%r13)
+        brasl   %r14,smp_switch_boot_cpu_in_resume
+        /* Restore prefix register */
+        spx     0x318(%r13)
+        /* Switch on lowcore protection */
+        stctg   %c0,%c0,__SF_EMPTY(%r15)
+        oi      __SF_EMPTY+4(%r15),0x10
+        lctlg   %c0,%c0,__SF_EMPTY(%r15)
+        /* Activate DAT */
+        stosm   __SF_EMPTY(%r15),0x04
+        /* Return 0 */
+        lmg     %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15)
+        lghi    %r2,0
+        br      %r14
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 739a12d2ffb9..ac1c620d1c7d 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -15,7 +15,9 @@ config SUPERH
        select HAVE_IOREMAP_PROT if MMU
        select HAVE_ARCH_TRACEHOOK
        select HAVE_DMA_API_DEBUG
+        select HAVE_PERF_COUNTER
        select RTC_LIB
+        select GENERIC_ATOMIC64
        help
          The SuperH is a RISC processor targeted for use in embedded systems
          and consumer electronics; it was also used in the Sega Dreamcast
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index 1c4d83ef2a47..7ffd1b4315bd 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -349,15 +349,6 @@ static int ov7725_power(struct device *dev, int mode)
        return 0;
 }
-static struct ov772x_camera_info ov7725_info = {
-        .buswidth  = SOCAM_DATAWIDTH_8,
-        .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
-        .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
-        .link = {
-                .power  = ov7725_power,
-        },
-};
 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
 };
@@ -402,25 +393,48 @@ static struct platform_device sdcard_cn3_device = {
        },
 };
-static struct platform_device *ap325rxa_devices[] __initdata = {
-        &smsc9118_device,
-        &ap325rxa_nor_flash_device,
-        &lcdc_device,
-        &ceu_device,
-        &nand_flash_device,
-        &sdcard_cn3_device,
-};
 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
        {
                I2C_BOARD_INFO("pcf8563", 0x51),
        },
+};
+static struct i2c_board_info ap325rxa_i2c_camera[] = {
        {
                I2C_BOARD_INFO("ov772x", 0x21),
-                .platform_data = &ov7725_info,
        },
 };
+static struct ov772x_camera_info ov7725_info = {
+        .buswidth       = SOCAM_DATAWIDTH_8,
+        .flags          = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
+        .edgectrl       = OV772X_AUTO_EDGECTRL(0xf, 0),
+        .link = {
+                .power          = ov7725_power,
+                .board_info     = &ap325rxa_i2c_camera[0],
+                .i2c_adapter_id = 0,
+                .module_name    = "ov772x",
+        },
+};
+static struct platform_device ap325rxa_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &ov7725_info.link,
+        },
+};
+static struct platform_device *ap325rxa_devices[] __initdata = {
+        &smsc9118_device,
+        &ap325rxa_nor_flash_device,
+        &lcdc_device,
+        &ceu_device,
+        &nand_flash_device,
+        &sdcard_cn3_device,
+        &ap325rxa_camera,
+};
 static struct spi_board_info ap325rxa_spi_devices[] = {
        {
                .modalias = "mmc_spi",
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index 7be56fb06c1f..42410a15d255 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -15,16 +15,18 @@
 #include <linux/fb.h>
 #include <linux/mtd/physmap.h>
 #include <linux/delay.h>
+#include <linux/interrupt.h>
 #include <linux/i2c.h>
 #include <linux/i2c-pca-platform.h>
 #include <linux/i2c-algo-pca.h>
+#include <linux/usb/r8a66597.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
 #include <linux/errno.h>
 #include <mach/sh7785lcr.h>
+#include <cpu/sh7785.h>
 #include <asm/heartbeat.h>
 #include <asm/clock.h>
-#include <cpu/sh7785.h>
 /*
 * NOTE: This board has 2 physical memory maps.
@@ -98,18 +100,21 @@ static struct platform_device nor_flash_device = {
        .resource       = nor_flash_resources,
 };
+static struct r8a66597_platdata r8a66597_data = {
+        .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
+        .vif = 1,
+};
 static struct resource r8a66597_usb_host_resources[] = {
        [0] = {
-                .name   = "r8a66597_hcd",
                .start  = R8A66597_ADDR,
                .end    = R8A66597_ADDR + R8A66597_SIZE - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .name   = "r8a66597_hcd",
                .start  = 2,
                .end    = 2,
-                .flags  = IORESOURCE_IRQ,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
        },
 };
@@ -119,6 +124,7 @@ static struct platform_device r8a66597_usb_host_device = {
        .dev = {
                .dma_mask               = NULL,
                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &r8a66597_data,
        },
        .num_resources  = ARRAY_SIZE(r8a66597_usb_host_resources),
        .resource       = r8a66597_usb_host_resources,
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index dd297d87f934..1639f8915000 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -20,6 +20,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/usb/r8a66597.h>
 #include <net/ax88796.h>
 #include <asm/machvec.h>
 #include <mach/highlander.h>
@@ -28,18 +30,21 @@
 #include <asm/io.h>
 #include <asm/io_trapped.h>
+static struct r8a66597_platdata r8a66597_data = {
+        .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
+        .vif = 1,
+};
 static struct resource r8a66597_usb_host_resources[] = {
        [0] = {
-                .name   = "r8a66597_hcd",
                .start  = 0xA4200000,
                .end    = 0xA42000FF,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .name   = "r8a66597_hcd",
                .start  = IRQ_EXT1,             /* irq number */
                .end    = IRQ_EXT1,
-                .flags  = IORESOURCE_IRQ,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
        },
 };
@@ -49,6 +54,7 @@ static struct platform_device r8a66597_usb_host_device = {
        .dev = {
                .dma_mask               = NULL,         /* don't use dma */
                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &r8a66597_data,
        },
        .num_resources  = ARRAY_SIZE(r8a66597_usb_host_resources),
        .resource       = r8a66597_usb_host_resources,
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 6ed401cd3156..f70f4644deb4 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -381,21 +381,6 @@ static struct platform_device migor_ceu_device = {
        },
 };
-static struct ov772x_camera_info ov7725_info = {
-        .buswidth  = SOCAM_DATAWIDTH_8,
-        .link = {
-                .power  = ov7725_power,
-        },
-};
-static struct tw9910_video_info tw9910_info = {
-        .buswidth = SOCAM_DATAWIDTH_8,
-        .mpout    = TW9910_MPO_FIELD,
-        .link = {
-                .power  = tw9910_power,
-        }
-};
 struct spi_gpio_platform_data sdcard_cn9_platform_data = {
        .sck = GPIO_PTD0,
        .mosi = GPIO_PTD1,
@@ -410,16 +395,6 @@ static struct platform_device sdcard_cn9_device = {
        },
 };
-static struct platform_device *migor_devices[] __initdata = {
-        &smc91x_eth_device,
-        &sh_keysc_device,
-        &migor_lcdc_device,
-        &migor_ceu_device,
-        &migor_nor_flash_device,
-        &migor_nand_flash_device,
-        &sdcard_cn9_device,
-};
 static struct i2c_board_info migor_i2c_devices[] = {
        {
                I2C_BOARD_INFO("rs5c372b", 0x32),
@@ -428,16 +403,66 @@ static struct i2c_board_info migor_i2c_devices[] = {
                I2C_BOARD_INFO("migor_ts", 0x51),
                .irq = 38, /* IRQ6 */
        },
+};
+static struct i2c_board_info migor_i2c_camera[] = {
        {
                I2C_BOARD_INFO("ov772x", 0x21),
-                .platform_data = &ov7725_info,
        },
        {
                I2C_BOARD_INFO("tw9910", 0x45),
-                .platform_data = &tw9910_info,
        },
 };
+static struct ov772x_camera_info ov7725_info = {
+        .buswidth       = SOCAM_DATAWIDTH_8,
+        .link = {
+                .power          = ov7725_power,
+                .board_info     = &migor_i2c_camera[0],
+                .i2c_adapter_id = 0,
+                .module_name    = "ov772x",
+        },
+};
+static struct tw9910_video_info tw9910_info = {
+        .buswidth       = SOCAM_DATAWIDTH_8,
+        .mpout          = TW9910_MPO_FIELD,
+        .link = {
+                .power          = tw9910_power,
+                .board_info     = &migor_i2c_camera[1],
+                .i2c_adapter_id = 0,
+                .module_name    = "tw9910",
+        }
+};
+static struct platform_device migor_camera[] = {
+        {
+                .name   = "soc-camera-pdrv",
+                .id     = 0,
+                .dev    = {
+                        .platform_data = &ov7725_info.link,
+                },
+        }, {
+                .name   = "soc-camera-pdrv",
+                .id     = 1,
+                .dev    = {
+                        .platform_data = &tw9910_info.link,
+                },
+        },
+};
+static struct platform_device *migor_devices[] __initdata = {
+        &smc91x_eth_device,
+        &sh_keysc_device,
+        &migor_lcdc_device,
+        &migor_ceu_device,
+        &migor_nor_flash_device,
+        &migor_nand_flash_device,
+        &sdcard_cn9_device,
+        &migor_camera[0],
+        &migor_camera[1],
+};
 static struct spi_board_info migor_spi_devices[] = {
        {
                .modalias = "mmc_spi",
diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c
index d8a65ea91665..4af3a771c058 100644
--- a/arch/sh/boards/mach-rsk/devices-rsk7203.c
+++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c
@@ -26,13 +26,13 @@ static struct smsc911x_platform_config smsc911x_config = {
        .phy_interface  = PHY_INTERFACE_MODE_MII,
        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_16BIT,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SWAP_FIFO,
 };
 static struct resource smsc911x_resources[] = {
        [0] = {
                .start          = 0x24000000,
-                .end            = 0x24000000 + 0x100,
+                .end            = 0x240000ff,
                .flags          = IORESOURCE_MEM,
        },
        [1] = {
@@ -99,6 +99,10 @@ static int __init rsk7203_devices_setup(void)
        gpio_request(GPIO_FN_TXD0, NULL);
        gpio_request(GPIO_FN_RXD0, NULL);
+        /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */
+        ctrl_outl(0x36db0400, 0xfffc0008); /* CS1BCR */
+        gpio_request(GPIO_FN_IRQ0_PB, NULL);
        return platform_add_devices(rsk7203_devices,
                                    ARRAY_SIZE(rsk7203_devices));
 }
diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c
index a340492087fa..8913ae39a802 100644
--- a/arch/sh/boards/mach-x3proto/setup.c
+++ b/arch/sh/boards/mach-x3proto/setup.c
@@ -15,6 +15,8 @@
 #include <linux/io.h>
 #include <linux/smc91x.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/usb/r8a66597.h>
 #include <asm/ilsel.h>
 static struct resource heartbeat_resources[] = {
@@ -58,17 +60,20 @@ static struct platform_device smc91x_device = {
        },
 };
+static struct r8a66597_platdata r8a66597_data = {
+        .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
+        .vif = 1,
+};
 static struct resource r8a66597_usb_host_resources[] = {
        [0] = {
-                .name   = "r8a66597_hcd",
                .start  = 0x18040000,
                .end    = 0x18080000 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .name   = "r8a66597_hcd",
                /* Filled in by ilsel */
-                .flags  = IORESOURCE_IRQ,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
        },
 };
@@ -78,6 +83,7 @@ static struct platform_device r8a66597_usb_host_device = {
        .dev = {
                .dma_mask               = NULL,         /* don't use dma */
                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &r8a66597_data,
        },
        .num_resources  = ARRAY_SIZE(r8a66597_usb_host_resources),
        .resource       = r8a66597_usb_host_resources,
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index d2ffc477549a..d6303d0e494e 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7751R)	+= pci-sh7751.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7763)        += pci-sh7780.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)        += pci-sh7780.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)        += pci-sh7780.o ops-sh4.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7786)        += ops-sh7786.o
 obj-$(CONFIG_CPU_SH5)                   += pci-sh5.o ops-sh5.o
 obj-$(CONFIG_SH_DREAMCAST)              += ops-dreamcast.o fixups-dreamcast.o \
diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c
new file mode 100644
index 000000000000..48f594b9582b
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-sh7786.c
@@ -0,0 +1,134 @@
+/*
+ * Generic SH7786 PCI-Express operations.
+ *
+ *  Copyright (C) 2009  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License v2. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include "pcie-sh7786.h"
+enum {
+        PCI_ACCESS_READ,
+        PCI_ACCESS_WRITE,
+};
+static DEFINE_SPINLOCK(sh7786_pcie_lock);
+static int sh7786_pcie_config_access(unsigned char access_type,
+                struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
+{
+        struct pci_channel *chan = bus->sysdata;
+        int dev, func;
+        dev = PCI_SLOT(devfn);
+        func = PCI_FUNC(devfn);
+        if (bus->number > 255 || dev > 31 || func > 7)
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
+        if (devfn)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        /* Set the PIO address */
+        pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
+                                (func << 16) | (where & ~3), SH4A_PCIEPAR);
+        /* Enable the configuration access */
+        pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
+        if (access_type == PCI_ACCESS_READ)
+                *data = pci_read_reg(chan, SH4A_PCIEPDR);
+        else
+                pci_write_reg(chan, *data, SH4A_PCIEPDR);
+        /* Check for master and target aborts */
+        if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        return PCIBIOS_SUCCESSFUL;
+}
+static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
+                            int where, int size, u32 *val)
+{
+        unsigned long flags;
+        int ret;
+        u32 data;
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        spin_lock_irqsave(&sh7786_pcie_lock, flags);
+        ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
+                                        devfn, where, &data);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                goto out;
+        if (size == 1)
+                *val = (data >> ((where & 3) << 3)) & 0xff;
+        else if (size == 2)
+                *val = (data >> ((where & 2) << 3)) & 0xffff;
+        else
+                *val = data;
+        dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
+                "where=0x%04x size=%d val=0x%08lx\n", bus->number,
+                devfn, where, size, (unsigned long)*val);
+out:
+        spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
+        return ret;
+}
+static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
+                             int where, int size, u32 val)
+{
+        unsigned long flags;
+        int shift, ret;
+        u32 data;
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        spin_lock_irqsave(&sh7786_pcie_lock, flags);
+        ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
+                                        devfn, where, &data);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                goto out;
+        dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
+                "where=0x%04x size=%d val=%08lx\n", bus->number,
+                devfn, where, size, (unsigned long)val);
+        if (size == 1) {
+                shift = (where & 3) << 3;
+                data &= ~(0xff << shift);
+                data |= ((val & 0xff) << shift);
+        } else if (size == 2) {
+                shift = (where & 2) << 3;
+                data &= ~(0xffff << shift);
+                data |= ((val & 0xffff) << shift);
+        } else
+                data = val;
+        ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
+                                        devfn, where, &data);
+out:
+        spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
+        return ret;
+}
+struct pci_ops sh7786_pci_ops = {
+        .read   = sh7786_pcie_read,
+        .write  = sh7786_pcie_write,
+};
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
new file mode 100644
index 000000000000..c655290a7750
--- /dev/null
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -0,0 +1,589 @@
+/*
+ * SH7786 PCI-Express controller definitions.
+ *
+ * Copyright (C) 2008, 2009 Renesas Technology Corp.
+ * All rights reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __PCI_SH7786_H
+#define __PCI_SH7786_H
+/* PCIe bus-0(x4) on SH7786 */                  // Rev1.171
+#define SH4A_PCIE_SPW_BASE      0xFE000000      /* spw config address for controller 0 */
+#define SH4A_PCIE_SPW_BASE1     0xFE200000      /* spw config address for controller 1 (Rev1.14)*/
+#define SH4A_PCIE_SPW_BASE2     0xFCC00000      /* spw config address for controller 2 (Rev1.171)*/
+#define SH4A_PCIE_SPW_BASE_LEN  0x00080000
+#define SH4A_PCI_CNFG_BASE      0xFE040000      /* pci config address for controller 0 */
+#define SH4A_PCI_CNFG_BASE1     0xFE240000      /* pci config address for controller 1 (Rev1.14)*/
+#define SH4A_PCI_CNFG_BASE2     0xFCC40000      /* pci config address for controller 2 (Rev1.171)*/
+#define SH4A_PCI_CNFG_BASE_LEN  0x00040000
+#define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0      /* offset to pci config_address */
+#define SH4A_PCIPIO_DATA_OFFSET 0x00000220      /* offset to pci config_data */
+/*
+ * for PEX8111(Max Payload Size=128B,PCIIO_SIZE=64K),
+ * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
+ */
+/* PCI0-0: PCI I/O space */
+#define SH4A_PCIIO_BASE         0xFD000000      /* PCI I/O for controller 0 */
+#define SH4A_PCIIO_BASE1        0xFD800000      /* PCI I/O for controller 1 (Rev1.14)*/
+#define SH4A_PCIIO_BASE2        0xFC800000      /* PCI I/O for controller 2 (Rev1.171)*/
+#define SH4A_PCIIO_SIZE64       0x00010000      /* PLX allows only 64K */
+#define SH4A_PCIIO_SIZE         0x00800000      /* 8M */
+#define SH4A_PCIIO_SIZE2        0x00400000      /* 4M (Rev1.171)*/
+/* PCI0-1: PCI memory space 29-bit address */
+#define SH4A_PCIMEM_BASE        0x10000000
+#define SH4A_PCIMEM_SIZE        0x04000000      /* 64M */
+/* PCI0-2: PCI memory space 32-bit address */
+#define SH4A_PCIMEM_BASEA       0xC0000000      /*  for controller 0 */
+#define SH4A_PCIMEM_BASEA1      0xA0000000      /*  for controller 1 (Rev1.14)*/
+#define SH4A_PCIMEM_BASEA2      0x80000000      /*  for controller 2 (Rev1.171)*/
+#define SH4A_PCIMEM_SIZEA       0x20000000      /* 512M */
+/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
+#define SH4A_PCIBMSTR_TRANSLATION       0x20000000
+#define SH4A_PCI_DEVICE_ID              0x0002
+#define SH4A_PCI_VENDOR_ID              0x1912
+// PCI compatible 000-03f
+#define PCI_CMD         0x004
+#define PCI_RID         0x008
+#define PCI_IBAR        0x010
+#define PCI_MBAR0       0x014
+#define PCI_MBAR1       0x018
+/* PCI power management/MSI/capablity 040-0ff */
+/* PCIE extended 100-fff */
+/* SH7786 device identification */      // Rev1.171
+#define SH4A_PVR                (0xFF000030)
+#define SH4A_PVR_SHX3           (0x10400000)
+#define SH4A_PRR                (0xFF000044)
+#define SH4A_PRR_SH7786         (0x00000400)    // Rev1.171
+/*      SPVCR0          */
+#define SH4A_PCIEVCR0           (0x000000)      /* R - 0x0000 0000 32 */
+#define         BITS_TOP_MB     (24)
+#define         MASK_TOP_MB     (0xff<<BITS_TOP_MB)
+#define         BITS_BOT_MB     (16)
+#define         MASK_BOT_MB     (0xff<<BITS_BOT_MB)
+#define         BITS_VC_ID      (0)
+#define         MASK_VC_ID      (0xffff<<BITS_VC_ID)
+/*      SPVCR1          */
+#define SH4A_PCIEVCR1           (0x000004)      /* R - 0x0000 0000 32*/
+#define         BITS_BADOPC     (5)             /* 5 BADOPC 0 R/W */
+#define         MASK_BADOPC     (1<<BITS_BADOPC)
+#define         BITS_BADDEST    (4)             /*4 BADDEST 0 R/W  */
+#define         MASK_BADDEST    (1<<BITS_BADDEST)
+#define         BITS_UNSOLRESP  (3)             /* 3 UNSOLRESP 0 R/W  */
+#define         MASK_UNSOLRESP  (1<<BITS_UNSOLRESP)
+#define         BITS_ERRSNT     (1)             /* 1 ERRSNT 0 */
+#define         MASK_ERRSNT     (1<<BITS_ERRSNT)
+#define         BITS_ERRRCV     (0)             /* 0 ERRRCV 0 */
+#define         MASK_ERRRCV     (1<<BITS_ERRRCV)
+/*      PCIEECR         */
+#define SH4A_PCIEECR            (0x000008)      /* R/W - 0x0000 0000 32 */
+#define         BITS_ENBL       (0)     /* 0 ENBL 0 R/W */
+#define         MASK_ENBL       (1<<BITS_ENBL)
+/*      PCIEPAR         */
+#define SH4A_PCIEPAR            (0x000010)      /* R/W - 0x0000 0000 32 */
+#define         BITS_BN         (24)
+#define         MASK_BN         (0xff<<BITS_BN)
+#define         BITS_DN         (19)
+#define         MASK_DN         (0x1f<<BITS_DN)
+#define         BITS_FN         (16)
+#define         MASK_FN         (0x7<<BITS_FN)
+#define         BITS_EREGNO     (8)
+#define         MASK_EREGNO     (0xff<<BITS_EREGNO)
+#define         BITS_REGNO      (2)
+#define         MASK_REGNO      (0x3f<<BITS_REGNO)
+/*      PCIEPCTLR       */
+#define SH4A_PCIEPCTLR          (0x000018)      /* R/W - 0x0000 0000 32 */
+#define         BITS_CCIE       (31)    /*  31 CCIE */
+#define         MASK_CCIE       (1<<BITS_CCIE)
+#define         BITS_TYPE       (8)
+#define         MASK_TYPE       (1<<BITS_TYPE)
+#define         BITS_C_VC       (0)
+#define         MASK_C_VC       (1<<BITS_C_VC)
+/*      PCIEPDR         */
+#define SH4A_PCIEPDR            (0x000020)      /* R/W - 0x0000 0000 32 */
+#define         BITS_PDR        (0)
+#define         MASK_PDR        (0xffffffff<<BITS_PDR)
+/*      PCIEMSGALR      */
+#define SH4A_PCIEMSGALR         (0x000030)      /* R/W - 0x0000 0000 32 */
+#define         BITS_MSGADRL    (0)
+#define         MASK_MSGADRL    (0xffffffff<<BITS_MSGADRL)
+/*      PCIEMSGAHR      */
+#define SH4A_PCIEMSGAHR         (0x000034)      /* R/W - 0x0000 0000 32 */
+#define         BITS_MSGADRH    (0)
+#define         MASK_MSGADRH    (0xffffffff<<BITS_MSGADRH)
+/*      PCIEMSGCTLR     */
+#define SH4A_PCIEMSGCTLR        (0x000038)      /* R/W - 0x0000 0000 32 */
+#define         BITS_MSGIE      (31)
+#define         MASK_MSGIE      (1<<BITS_MSGIE)
+#define         BITS_MROUTE     (16)
+#define         MASK_MROUTE     (0x7<<BITS_MROUTE)
+#define         BITS_MCODE      (8)
+#define         MASK_MCODE      (0xff<<BITS_MCODE)
+#define         BITS_M_VC       (0)
+#define         MASK_M_VC       (1<<BITS_M_VC)
+/*      PCIEMSG         */
+#define SH4A_PCIEMSG            (0x000040)      /* W - - 32     */
+#define         BITS_MDATA      (0)
+#define         MASK_MDATA      (0xffffffff<<BITS_MDATA)
+/*      PCIEPHYCTLR     */
+#define SH4A_PCIEPHYCTLR        (0x010000)      /* R/W - 0x0000 0000 32 */
+#define         BITS_CKE        (0)
+#define         MASK_CKE        (1<<BITS_CKE)
+/*      PCIERMSGIER     */
+#define SH4A_PCIERMSGIER        (0x004040)      /* R/W - 0x0000 0000 32 */
+/*      PCIEPHYADRR     */
+#define SH4A_PCIEPHYADRR        (0x010004)      /* R/W - 0x0000 0000 32 */
+#define         BITS_ACK        (24)                    // Rev1.171
+#define         MASK_ACK        (1<<BITS_ACK)           // Rev1.171
+#define         BITS_CMD        (16)                    // Rev1.171
+#define         MASK_CMD        (0x03<<BITS_CMD)        // Rev1.171
+#define         BITS_LANE       (8)
+#define         MASK_LANE       (0x0f<<BITS_LANE)
+#define         BITS_ADR        (0)
+#define         MASK_ADR        (0xff<<BITS_ADR)
+/*      PCIEPHYDINR     */                                                      // Rev1.171 start.
+#define SH4A_PCIEPHYDINR        (0x010008)      /* R/W - 0x0000 0000 32 */
+/*      PCIEPHYDOUTR    */
+#define SH4A_PCIEPHYDOUTR       (0x01000C)      /* R/W - 0x0000 0000 32 */
+/*      PCIEPHYSR       */
+#define SH4A_PCIEPHYSR          (0x010010)      /* R/W - 0x0000 0000 32 */      // Rev1.171 end.
+/*      PCIEPHYDATAR    */
+#define SH4A_PCIEPHYDATAR       (0x00008)       /* R/W - 0xxxxx xxxx 32 */
+#define         BITS_DATA       (0)
+#define         MASK_DATA       (0xffffffff<<BITS_DATA)
+/*      PCIETCTLR       */
+#define SH4A_PCIETCTLR          (0x020000)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_CFINT      (0)
+#define         MASK_CFINT      (1<<BITS_CFINT)
+/*      PCIETSTR        */
+#define SH4A_PCIETSTR           (0x020004)      /* R/W R/W 0x0000 0000 32  */
+/*      PCIEINTR        */
+#define SH4A_PCIEINTR           (0x020008)      /* R/W R/W 0x0000 0000 32  */
+#define         BITS_INT_RX_ERP                 (31)
+#define         MASK_INT_RX_ERP                 (1<<BITS_INT_RX_ERP)
+#define         BITS_INT_RX_VCX_Posted          (30)
+#define         MASK_INT_RX_VCX_Posted          (1<<BITS_INT_RX_VCX_Posted)
+#define         BITS_INT_RX_VCX_NonPosted       (29)
+#define         MASK_INT_RX_VCX_NonPosted       (1<<BITS_INT_RX_VCX_NonPosted)
+#define         BITS_INT_RX_VCX_CPL             (28)
+#define         MASK_INT_RX_VCX_CPL             (1<<BITS_INT_RX_VCX_CPL)
+#define         BITS_INT_TX_VCX_Posted          (26)
+#define         MASK_INT_TX_VCX_Posted          (1<<BITS_INT_TX_VCX_Posted)
+#define         BITS_INT_TX_VCX_NonPosted       (25)
+#define         MASK_INT_TX_VCX_NonPosted       (1<<BITS_INT_TX_VCX_NonPosted)
+#define         BITS_INT_TX_VCX_CPL             (24)
+#define         MASK_INT_TX_VCX_CPL             (1<<BITS_INT_TX_VCX_CPL)
+#define         BITS_INT_RX_VC0_Posted          (22)
+#define         MASK_INT_RX_VC0_Posted          (1<<BITS_INT_RX_VC0_Posted)
+#define         BITS_INT_RX_VC0_NonPosted       (21)
+#define         MASK_INT_RX_VC0_NonPosted       (1<<BITS_INT_RX_VC0_NonPosted)
+#define         BITS_INT_RX_VC0_CPL             (20)
+#define         MASK_INT_RX_VC0_CPL             (1<<BITS_INT_RX_VC0_CPL)
+#define         BITS_INT_TX_VC0_Posted          (18)
+#define         MASK_INT_TX_VC0_Posted          (1<<BITS_INT_TX_VC0_Posted)
+#define         BITS_INT_TX_VC0_NonPosted       (17)
+#define         MASK_INT_TX_VC0_NonPosted       (1<<BITS_INT_TX_VC0_NonPosted)
+#define         BITS_INT_TX_VC0_CPL             (16)
+#define         MASK_INT_TX_VC0_CPL             (1<<BITS_INT_TX_VC0_CPL)
+#define         BITS_INT_RX_CTRL                (15)
+#define         MASK_INT_RX_CTRL                (1<<BITS_INT_RX_CTRL)
+#define         BITS_INT_TX_CTRL                (14)
+#define         MASK_INT_TX_CTRL                (1<<BITS_INT_TX_CTRL)
+#define         BITS_INTTL                      (11)
+#define         MASK_INTTL                      (1<<BITS_INTTL)
+#define         BITS_INTDL                      (10)
+#define         MASK_INTDL                      (1<<BITS_INTDL)
+#define         BITS_INTMAC                     (9)
+#define         MASK_INTMAC                     (1<<BITS_INTMAC)
+#define         BITS_INTPM                      (8)
+#define         MASK_INTPM                      (1<<BITS_INTPM)
+/*      PCIEINTER       */
+#define SH4A_PCIEINTER          (0x02000C)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_INT_RX_ERP                 (31)
+#define         MASK_INT_RX_ERP                 (1<<BITS_INT_RX_ERP)
+#define         BITS_INT_RX_VCX_Posted          (30)
+#define         MASK_INT_RX_VCX_Posted          (1<<BITS_INT_RX_VCX_Posted)
+#define         BITS_INT_RX_VCX_NonPosted       (29)
+#define         MASK_INT_RX_VCX_NonPosted       (1<<BITS_INT_RX_VCX_NonPosted)
+#define         BITS_INT_RX_VCX_CPL             (28)
+#define         MASK_INT_RX_VCX_CPL             (1<<BITS_INT_RX_VCX_CPL)
+#define         BITS_INT_TX_VCX_Posted          (26)
+#define         MASK_INT_TX_VCX_Posted          (1<<BITS_INT_TX_VCX_Posted)
+#define         BITS_INT_TX_VCX_NonPosted       (25)
+#define         MASK_INT_TX_VCX_NonPosted       (1<<BITS_INT_TX_VCX_NonPosted)
+#define         BITS_INT_TX_VCX_CPL             (24)
+#define         MASK_INT_TX_VCX_CPL             (1<<BITS_INT_TX_VCX_CPL)
+#define         BITS_INT_RX_VC0_Posted          (22)
+#define         MASK_INT_RX_VC0_Posted          (1<<BITS_INT_RX_VC0_Posted)
+#define         BITS_INT_RX_VC0_NonPosted       (21)
+#define         MASK_INT_RX_VC0_NonPosted       (1<<BITS_INT_RX_VC0_NonPosted)
+#define         BITS_INT_RX_VC0_CPL             (20)
+#define         MASK_INT_RX_VC0_CPL             (1<<BITS_INT_RX_VC0_CPL)
+#define         BITS_INT_TX_VC0_Posted          (18)
+#define         MASK_INT_TX_VC0_Posted          (1<<BITS_INT_TX_VC0_Posted)
+#define         BITS_INT_TX_VC0_NonPosted       (17)
+#define         MASK_INT_TX_VC0_NonPosted       (1<<BITS_INT_TX_VC0_NonPosted)
+#define         BITS_INT_TX_VC0_CPL             (16)
+#define         MASK_INT_TX_VC0_CPL             (1<<BITS_INT_TX_VC0_CPL)
+#define         BITS_INT_RX_CTRL                (15)
+#define         MASK_INT_RX_CTRL                (1<<BITS_INT_RX_CTRL)
+#define         BITS_INT_TX_CTRL                (14)
+#define         MASK_INT_TX_CTRL                (1<<BITS_INT_TX_CTRL)
+#define         BITS_INTTL                      (11)
+#define         MASK_INTTL                      (1<<BITS_INTTL)
+#define         BITS_INTDL                      (10)
+#define         MASK_INTDL                      (1<<BITS_INTDL)
+#define         BITS_INTMAC                     (9)
+#define         MASK_INTMAC                     (1<<BITS_INTMAC)
+#define         BITS_INTPM                      (8)
+#define         MASK_INTPM                      (1<<BITS_INTPM)
+/*      PCIEAIR  */
+#define SH4A_PCIEAIR            (SH4A_PCIE_BASE + 0x020010)     /* R/W R/W 0xxxxx xxxx 32 */
+/*       PCIECIR         */
+#define SH4A_PCIECIR            (SH4A_PCIE_BASE)        /* R/W R/W 0xxxxx xxxx 32 */
+/*       PCIEERRFR       */                                                             // Rev1.18
+#define SH4A_PCIEERRFR          (0x020020)              /* R/W R/W 0xxxxx xxxx 32 */    // Rev1.18
+                                                                                        // Rev1.18
+/*      PCIELAR0        */
+#define SH4A_PCIELAR0           (0x020200)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_LARn       (20)
+#define         MASK_LARn       (0xfff<<BITS_LARn)
+#define SH4A_PCIE_020204        (0x020204)      /* R/W R/W 0x0000 0000 32 */
+/*      PCIELAMR0       */
+#define SH4A_PCIELAMR0          (0x020208)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_LAMRn      (20)
+#define         MASK_LAMRn      (0x1ff<<BITS_LAMRn)
+#define         BITS_LAREn      (0)
+#define         MASK_LAREn      (0x1<<BITS_LAREn)
+/*      PCIECSCR0       */
+#define SH4A_PCIECSCR0          (0x020210)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_RANGE      (2)
+#define         MASK_RANGE      (0x7<<BITS_RANGE)
+#define         BITS_SNPMD      (0)
+#define         MASK_SNPMD      (0x3<<BITS_SNPMD)
+/*      PCIECSAR0       */
+#define SH4A_PCIECSAR0          (0x020214)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_CSADR      (0)
+#define         MASK_CSADR      (0xffffffff<<BITS_CSADR)
+/*      PCIESTCTLR0     */
+#define SH4A_PCIESTCTLR0        (0x020218)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_SHPRI      (8)
+#define         MASK_SHPRI      (0x0f<<BITS_SHPRI)
+#define SH4A_PCIE_020224        (0x020224)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAR1           (0x020220)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAMR1          (0x020228)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSCR1          (0x020230)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSAR1          (0x020234)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIESTCTLR1        (0x020238)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAR2           (0x020240)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIE_020244        (0x020244)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAMR2          (0x020248)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSCR2          (0x020250)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSAR2          (0x020254)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIESTCTLR2        (0x020258)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAR3           (0x020260)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIE_020264        (0x020264)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAMR3          (0x020268)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSCR3          (0x020270)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSAR3          (0x020274)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIESTCTLR3        (0x020278)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAR4           (0x020280)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIE_020284        (0x020284)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAMR4          (0x020288)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSCR4          (0x020290)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSAR4          (0x020294)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIESTCTLR4        (0x020298)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAR5           (0x0202A0)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIE_0202A4        (0x0202A4)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIELAMR5          (0x0202A8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSCR5          (0x0202B0)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIECSAR5          (0x0202B4)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIESTCTLR5        (0x0202B8)      /* R/W R/W 0x0000 0000 32 */
+/*      PCIEPARL0       */
+#define SH4A_PCIEPARL0          (0x020400)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_PAL        (18)
+#define         MASK_PAL        (0x3fff<<BITS_PAL)
+/*      PCIEPARH0       */
+#define SH4A_PCIEPARH0          (0x020404)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_PAH        (0)
+#define         MASK_PAH        (0xffffffff<<BITS_PAH)
+/*      PCIEPAMR0        */
+#define SH4A_PCIEPAMR0          (0x020408)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_PAM        (18)
+#define         MASK_PAM        (0x3fff<<BITS_PAM)
+/*      PCIEPTCTLR0     */
+#define SH4A_PCIEPTCTLR0        (0x02040C)      /* R/W R/W 0x0000 0000 32 */
+#define         BITS_PARE       (31)
+#define         MASK_PARE       (0x1<<BITS_PARE)
+#define         BITS_TC         (20)
+#define         MASK_TC         (0x7<<BITS_TC)
+#define         BITS_T_VC       (16)
+#define         MASK_T_VC       (0x1<<BITS_T_VC)
+#define         BITS_LOCK       (12)
+#define         MASK_LOCK       (0x1<<BITS_LOCK)
+#define         BITS_SPC        (8)
+#define         MASK_SPC        (0x1<<BITS_SPC)
+#define SH4A_PCIEPARL1          (0x020420)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARH1          (0x020424)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPAMR1          (0x020428)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPTCTLR1        (0x02042C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARL2          (0x020440)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARH2          (0x020444)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPAMR2          (0x020448)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPTCTLR2        (0x02044C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARL3          (0x020460)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARH3          (0x020464)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPAMR3          (0x020468)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPTCTLR3        (0x02046C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARL4          (0x020480)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARH4          (0x020484)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPAMR4          (0x020488)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPTCTLR4        (0x02048C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARL5          (0x0204A0)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPARH5          (0x0204A4)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPAMR5          (0x0204A8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPTCTLR5        (0x0204AC)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMAOR          (0x021000)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAR0         (0x021100)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAHR0        (0x021104)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAR0         (0x021108)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAHR0        (0x02110C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMBCNTR0       (0x021110)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSBCNTR0      (0x021114)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSTRR0        (0x021118)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCAR0        (0x02111C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCR0         (0x021120)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCC2R0        (0x021124)      /* R/W R/W 0x0000 0000 - */
+#define SH4A_PCIEDMCCCR0        (0x021128)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAR1         (0x021140)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAHR1        (0x021144)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAR1         (0x021148)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAHR1        (0x02114C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMBCNTR1       (0x021150)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSBCNTR1      (0x021154)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSTRR1        (0x021158)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCAR1        (0x02115C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCR1         (0x021160)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCC2R1        (0x021164)      /* R/W R/W 0x0000 0000 - */
+#define SH4A_PCIEDMCCCR1        (0x021168)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAR2         (0x021180)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAHR2        (0x021184)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAR2         (0x021188)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAHR2        (0x02118C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMBCNTR2       (0x021190)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSBCNTR2      (0x021194)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSTRR2        (0x021198)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCAR2        (0x02119C)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCR2         (0x0211A0)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCC2R2        (0x0211A4)      /* R/W R/W 0x0000 0000 -  */
+#define SH4A_PCIEDMCCCR2        (0x0211A8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAR3         (0x0211C0)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSAHR3        (0x0211C4)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAR3         (0x0211C8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMDAHR3        (0x0211CC)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMBCNTR3       (0x0211D0)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSBCNTR3      (0x0211D4)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMSTRR3        (0x0211D8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCAR3        (0x0211DC)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCCR3         (0x0211E0)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCC2R3        (0x0211E4)      /* R/W R/W 0x0000 0000 -  */
+#define SH4A_PCIEDMCCCR3        (0x0211E8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEPCICONF0       (0x040000)      /* R R - 8/16/32 */
+#define SH4A_PCIEPCICONF1       (0x040004)      /* R/W R/W 0x0008 0000 8/16/32 */
+#define SH4A_PCIEPCICONF2       (0x040008)      /* R/W R/W 0xFF00 0000 8/16/32 */
+#define SH4A_PCIEPCICONF3       (0x04000C)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEPCICONF4       (0x040010)      /* - R/W - 8/16/32 */
+#define SH4A_PCIEPCICONF5       (0x040014)      /* - R/W - 8/16/32 */
+#define SH4A_PCIEPCICONF6       (0x040018)      /* - R/W - 8/16/32 */
+#define SH4A_PCIEPCICONF7       (0x04001C)      /* - R/W - 8/16/32 */
+#define SH4A_PCIEPCICONF8       (0x040020)      /* - R/W - 8/16/32 */
+#define SH4A_PCIEPCICONF9       (0x040024)      /* - R/W - 8/16/32 */
+#define SH4A_PCIEPCICONF10      (0x040028)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEPCICONF11      (0x04002C)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEPCICONF12      (0x040030)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEPCICONF13      (0x040034)      /* R/W R/W 0x0000 0040 8/16/32 */
+#define SH4A_PCIEPCICONF14      (0x040038)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEPCICONF15      (0x04003C)      /* R/W R/W 0x0000 00FF 8/16/32 */
+#define SH4A_PCIEPMCAP0         (0x040040)      /* R/W R 0x0003 5001 8/16/32 */
+#define SH4A_PCIEPMCAP1         (0x040044)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEMSICAP0        (0x040050)      /* R/W R/W 0x0180 7005 8/16/32 */
+#define SH4A_PCIEMSICAP1        (0x040054)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEMSICAP2        (0x040058)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEMSICAP3        (0x04005C)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEMSICAP4        (0x040060)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEMSICAP5        (0x040064)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEEXPCAP0        (0x040070)      /* R/W R/W 0x0001 0010 8/16/32 */
+#define SH4A_PCIEEXPCAP1        (0x040074)      /* R/W R 0x0000 0005 8/16/32 */
+#define SH4A_PCIEEXPCAP2        (0x040078)      /* R/W R/W 0x0000 0801 8/16/32 */
+#define SH4A_PCIEEXPCAP3        (0x04007C)      /* R/W R 0x0003 F421 8/16/32 */
+#define SH4A_PCIEEXPCAP4        (0x040080)      /* R/W R/W 0x0041 0000 8/16/32 */
+#define SH4A_PCIEEXPCAP5        (0x040084)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEEXPCAP6        (0x040088)      /* R/W R/W 0x0000 03C0 8/16/32 */
+#define SH4A_PCIEEXPCAP7        (0x04008C)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEEXPCAP8        (0x040090)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEVCCAP0         (0x040100)      /* R/W R 0x1B01 0002 8/16/32 */
+#define SH4A_PCIEVCCAP1         (0x040104)      /* R R 0x0000 0001 8/16/32 */
+#define SH4A_PCIEVCCAP2         (0x040108)      /* R R 0x0000 0000 8/16/32 */
+#define SH4A_PCIEVCCAP3         (0x04010C)      /* R R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEVCCAP4         (0x040110)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEVCCAP5         (0x040114)      /* R/W R/W 0x8000 00FF 8/16/32 */
+#define SH4A_PCIEVCCAP6         (0x040118)      /* R/W R 0x0002 0000 8/16/32 */
+#define SH4A_PCIEVCCAP7         (0x04011C)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEVCCAP8         (0x040120)      /* R/W R/W 0x0000 0000 8/16/32 */
+#define SH4A_PCIEVCCAP9         (0x040124)      /* R/W R 0x0002 0000 8/16/32 */
+#define SH4A_PCIENUMCAP0        (0x0001B0)      /* RW R 0x0001 0003 8/16/32 */
+#define SH4A_PCIENUMCAP1        (0x0001B4)      /* R R 0x0000 0000 8/16/32 */
+#define SH4A_PCIENUMCAP2        (0x0001B8)      /* R R 0x0000 0000 8/16/32 */
+#define SH4A_PCIEIDSETR0        (0x041000)      /* R/W R 0x0000 FFFF 16/32 */
+#define SH4A_PCIEIDSETR1        (0x041004)      /* R/W R 0xFF00 0000 16/32 */
+#define SH4A_PCIEBAR0SETR       (0x041008)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEBAR1SETR       (0x04100C)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEBAR2SETR       (0x041010)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEBAR3SETR       (0x041014)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEBAR4SETR       (0x041018)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEBAR5SETR       (0x04101C)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIECISSETR        (0x041020)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEIDSETR2        (0x041024)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEEROMSETR       (0x041028)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEDSERSETR0      (0x04102C)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEDSERSETR1      (0x041030)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIECTLR           (0x041040)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIETLSR           (0x041044)      /* R/W1C R 0x0000 0000 16/32 */
+#define SH4A_PCIETLCTLR         (0x041048)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEDLSR           (0x04104C)      /* R/W1C R 0x4003 0000 16/32 */
+#define SH4A_PCIEDLCTLR         (0x041050)      /* R R 0x0000 0000 16/32 */
+#define SH4A_PCIEMACSR          (0x041054)      /* R/W1C R 0x0041 0000 16/32 */
+#define SH4A_PCIEMACCTLR        (0x041058)      /* R/W R 0x0000 0000 16/32 */
+#define         PCIEMACCTLR_SCR_DIS     (1 << 27)       /* scramble disable */
+#define SH4A_PCIEPMSTR          (0x04105C)      /* R/W1C R 0x0000 0000 16/32 */
+#define SH4A_PCIEPMCTLR         (0x041060)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIETLINTENR       (0x041064)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEDLINTENR       (0x041068)      /* R/W R 0x0000 0000 16/32 */
+#define         PCIEDLINTENR_DLL_ACT_ENABLE     (1 << 31) /* DL active irq */
+#define SH4A_PCIEMACINTENR      (0x04106C)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIEPMINTENR       (0x041070)      /* R/W R 0x0000 0000 16/32 */
+#define SH4A_PCIETXDCTLR        (0x044000)      /* R/W - H'00000000_00000000 32/64 */
+#define SH4A_PCIETXCTLR         (0x044020)      /* R/W - H'00000000_00000000 32/64 */
+#define SH4A_PCIETXSR           (0x044028)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIETXVC0DCTLR     (0x044100)      /* R/W - H'00000000_00000000 32/64 */
+#define SH4A_PCIETXVC0SR        (0x044108)      /* R/W - H'00888000_00000000 32/64 */
+#define SH4A_PCIEVC0PDTXR       (0x044110)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0PHTXR       (0x044118)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0NPDTXR      (0x044120)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0NPHTXR      (0x044128)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0CDTXR       (0x044130)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0CHTXR       (0x044138)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIETXVCXDCTLR     (0x044200)      /* R/W - H'00000000_00000000 32/64 */
+#define SH4A_PCIETXVCXSR        (0x044208)      /* R/W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXPDTXR       (0x044210)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXPHTXR       (0x044218)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXNPDTXR      (0x044220)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXNPHTXR      (0x044228)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXCDTXR       (0x044230)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXCHTXR       (0x044238)      /* W - H'00000000_00000000 32/64 */
+#define SH4A_PCIERDCTLR         (0x046000)      /* RW - H'00000000_00000000 32/64 */
+#define SH4A_PCIEERPCTLR        (0x046008)      /* RW - H'00000000_00000000 32/64 */
+#define SH4A_PCIEERPHR          (0x046010)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEERPERR         (0x046018)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIERXVC0DCTLR     (0x046100)      /* RW - H'00000000_00000000 32/64 */
+#define SH4A_PCIERXVC0SR        (0x046108)      /* RW - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0PDRXR       (0x046140)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0PHRXR       (0x046148)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0PERR        (0x046150)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0NPDRXR      (0x046158)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0NPHRXR      (0x046160)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0NPERR       (0x046168)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0CDRXR       (0x046170)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0CHRXR       (0x046178)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVC0CERR        (0x046180)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIERXVCXDCTLR     (0x046200)      /* RW - H'00000000_00000000 32/64 */
+#define SH4A_PCIERXVCXSR        (0x046208)      /* RW - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXPDRXR       (0x046240)      /* R - H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXPHRXR       (0x046248)      /* R H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXPERR        (0x046250)      /* R H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXNPDRXR      (0x046258)      /* R H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXNPHRXR      (0x046260)      /* R H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXNPERR       (0x046268)      /* R H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXCDRXR       (0x046270)      /* R H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXCHRXR       (0x046278)      /* R H'00000000_00000000 32/64 */
+#define SH4A_PCIEVCXCERR        (0x046280)      /* R H'00000000_00000000 32/64 */
+/* SSI Register Definition for MSI WORK AROUND --hamada */
+#define SH4A_PCI_SSI_BASE       0xFFE00000      /* spw config address   */
+#define SH4A_PCI_SSI_BASE_LEN   0x00100000      /* 1MB                  */
+#define SH4A_SSICR0             (0x000000)
+#define SH4A_SSICR1             (0x010000)
+#define SH4A_SSICR2             (0x020000)
+#define SH4A_SSICR3             (0x030000)
+#define PCI_REG(x)              ((x) + 0x40000)
+static inline void
+pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg)
+{
+        __raw_writel(val, chan->reg_base + reg);
+}
+static inline unsigned long
+pci_read_reg(struct pci_channel *chan, unsigned long reg)
+{
+        return __raw_readl(chan->reg_base + reg);
+}
+#endif /* __PCI_SH7786_H */
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 157c320272cb..e8e78137c6f5 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -85,4 +85,6 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 #define smp_mb__after_atomic_inc()      barrier()
 #include <asm-generic/atomic-long.h>
+#include <asm-generic/atomic64.h>
 #endif /* __ASM_SH_ATOMIC_H */
diff --git a/arch/sh/include/asm/kmap_types.h b/arch/sh/include/asm/kmap_types.h
index 84d565c696be..5962b08b6dd8 100644
--- a/arch/sh/include/asm/kmap_types.h
+++ b/arch/sh/include/asm/kmap_types.h
@@ -3,30 +3,12 @@
 /* Dummy header just to define km_type. */
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
+#define  __WITH_KM_FENCE
-#else
-# define D(n)
 #endif
-enum km_type {
+#include <asm-generic/kmap_types.h>
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-#undef D
+#undef __WITH_KM_FENCE
 #endif
diff --git a/arch/sh/include/asm/perf_counter.h b/arch/sh/include/asm/perf_counter.h
new file mode 100644
index 000000000000..a8153c2aa6fa
--- /dev/null
+++ b/arch/sh/include/asm/perf_counter.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_SH_PERF_COUNTER_H
+#define __ASM_SH_PERF_COUNTER_H
+/* SH only supports software counters through this interface. */
+#define set_perf_counter_pending()      do { } while (0)
+#endif /* __ASM_SH_PERF_COUNTER_H */
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 318516f6bfad..c18f7d09281b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -15,6 +15,7 @@
 #include <linux/serial_sci.h>
 #include <linux/uio_driver.h>
 #include <linux/sh_timer.h>
+#include <linux/usb/r8a66597.h>
 #include <asm/clock.h>
 static struct resource iic_resources[] = {
@@ -38,18 +39,20 @@ static struct platform_device iic_device = {
        .resource       = iic_resources,
 };
+static struct r8a66597_platdata r8a66597_data = {
+        /* This set zero to all members */
+};
 static struct resource usb_host_resources[] = {
        [0] = {
-                .name   = "r8a66597_hcd",
                .start  = 0xa4d80000,
                .end    = 0xa4d800ff,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .name   = "r8a66597_hcd",
                .start  = 65,
                .end    = 65,
-                .flags  = IORESOURCE_IRQ,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
        },
 };
@@ -59,6 +62,7 @@ static struct platform_device usb_host_device = {
        .dev = {
                .dma_mask               = NULL,
                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &r8a66597_data,
        },
        .num_resources  = ARRAY_SIZE(usb_host_resources),
        .resource       = usb_host_resources,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index d8f4a13aeff9..e1bb80b2a27b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -13,6 +13,7 @@
 #include <linux/mm.h>
 #include <linux/serial_sci.h>
 #include <linux/uio_driver.h>
+#include <linux/usb/r8a66597.h>
 #include <linux/sh_timer.h>
 #include <linux/io.h>
 #include <asm/clock.h>
@@ -396,9 +397,12 @@ static struct platform_device rtc_device = {
        .resource       = rtc_resources,
 };
+static struct r8a66597_platdata r8a66597_data = {
+        /* This set zero to all members */
+};
 static struct resource sh7723_usb_host_resources[] = {
        [0] = {
-                .name   = "r8a66597_hcd",
                .start  = 0xa4d80000,
                .end    = 0xa4d800ff,
                .flags  = IORESOURCE_MEM,
@@ -406,7 +410,7 @@ static struct resource sh7723_usb_host_resources[] = {
        [1] = {
                .start  = 65,
                .end    = 65,
-                .flags  = IORESOURCE_IRQ,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
        },
 };
@@ -416,6 +420,7 @@ static struct platform_device sh7723_usb_host_device = {
        .dev = {
                .dma_mask               = NULL,         /*  not use dma */
                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &r8a66597_data,
        },
        .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
        .resource       = sh7723_usb_host_resources,
diff --git a/arch/sh/kernel/init_task.c b/arch/sh/kernel/init_task.c
index 80c35ff71d56..1719957c0a69 100644
--- a/arch/sh/kernel/init_task.c
+++ b/arch/sh/kernel/init_task.c
@@ -10,9 +10,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
 struct pt_regs fake_swapper_regs;
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial thread structure.
 *
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index cc12cd48bbc5..3f8b6a92eabd 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -37,6 +37,8 @@ config SPARC64
        select HAVE_KPROBES
        select HAVE_LMB
        select HAVE_SYSCALL_WRAPPERS
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE_MCOUNT_RECORD
        select USE_GENERIC_SMP_HELPERS if SMP
        select RTC_DRV_CMOS
        select RTC_DRV_BQ4802
@@ -93,6 +95,9 @@ config AUDIT_ARCH
 config HAVE_SETUP_PER_CPU_AREA
        def_bool y if SPARC64
+config HAVE_DYNAMIC_PER_CPU_AREA
+        def_bool y if SPARC64
 config GENERIC_HARDIRQS_NO__DO_IRQ
        bool
        def_bool y if SPARC64
diff --git a/arch/sparc/configs/sparc64_defconfig b/arch/sparc/configs/sparc64_defconfig
index b5d63bd8716e..0123a4c596ce 100644
--- a/arch/sparc/configs/sparc64_defconfig
+++ b/arch/sparc/configs/sparc64_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc2
+# Linux kernel version: 2.6.30
-# Fri Apr 17 02:03:07 2009
+# Tue Jun 16 04:59:36 2009
 #
 CONFIG_64BIT=y
 CONFIG_SPARC=y
@@ -19,6 +19,7 @@ CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 CONFIG_AUDIT_ARCH=y
 CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_HAVE_DYNAMIC_PER_CPU_AREA=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_MMU=y
 CONFIG_ARCH_NO_VIRT_TO_BUS=y
@@ -82,7 +83,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -95,16 +95,21 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
 CONFIG_TRACEPOINTS=y
-# CONFIG_MARKERS is not set
+CONFIG_MARKERS=y
 CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_KPROBES=y
@@ -202,6 +207,7 @@ CONFIG_NR_QUICK=1
 CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=8192
 CONFIG_SCHED_SMT=y
 CONFIG_SCHED_MC=y
 # CONFIG_PREEMPT_NONE is not set
@@ -321,6 +327,7 @@ CONFIG_VLAN_8021Q=m
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
@@ -340,7 +347,11 @@ CONFIG_WIRELESS=y
 CONFIG_WIRELESS_OLD_REGULATORY=y
 # CONFIG_WIRELESS_EXT is not set
 # CONFIG_LIB80211 is not set
-# CONFIG_MAC80211 is not set
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -364,6 +375,7 @@ CONFIG_EXTRA_FIRMWARE=""
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
 CONFIG_OF_DEVICE=y
+CONFIG_OF_MDIO=m
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_FD is not set
@@ -399,6 +411,7 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_AT24 is not set
 # CONFIG_EEPROM_LEGACY is not set
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
 CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
@@ -477,10 +490,6 @@ CONFIG_BLK_DEV_SR=m
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 # CONFIG_CHR_DEV_SCH is not set
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 # CONFIG_SCSI_LOGGING is not set
@@ -499,6 +508,7 @@ CONFIG_SCSI_FC_ATTRS=y
 CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 # CONFIG_SCSI_3W_9XXX is not set
 # CONFIG_SCSI_ACARD is not set
@@ -507,6 +517,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_AIC79XX is not set
 # CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_ARCMSR is not set
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
@@ -521,7 +532,6 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_STEX is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
@@ -569,7 +579,6 @@ CONFIG_DM_ZERO=m
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -635,6 +644,7 @@ CONFIG_NET_PCI=y
 # CONFIG_SMSC9420 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
+# CONFIG_KS8842 is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_SC92031 is not set
 # CONFIG_ATL2 is not set
@@ -1127,6 +1137,11 @@ CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
 CONFIG_SND_VMASTER=y
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_MPU401_UART=m
 CONFIG_SND_AC97_CODEC=m
 CONFIG_SND_DRIVERS=y
@@ -1153,6 +1168,7 @@ CONFIG_SND_ALI5451=m
 # CONFIG_SND_OXYGEN is not set
 # CONFIG_SND_CS4281 is not set
 # CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CTXFI is not set
 # CONFIG_SND_DARLA20 is not set
 # CONFIG_SND_GINA20 is not set
 # CONFIG_SND_LAYLA20 is not set
@@ -1183,6 +1199,7 @@ CONFIG_SND_ALI5451=m
 # CONFIG_SND_INTEL8X0 is not set
 # CONFIG_SND_INTEL8X0M is not set
 # CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LX6464ES is not set
 # CONFIG_SND_MAESTRO3 is not set
 # CONFIG_SND_MIXART is not set
 # CONFIG_SND_NM256 is not set
@@ -1229,6 +1246,7 @@ CONFIG_HID_BELKIN=y
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
 # CONFIG_DRAGONRISE_FF is not set
 CONFIG_HID_EZKEY=y
 CONFIG_HID_KYE=y
@@ -1246,9 +1264,14 @@ CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
 # CONFIG_GREENASIA_FF is not set
+CONFIG_HID_SMARTJOYPLUS=y
+# CONFIG_SMARTJOYPLUS_FF is not set
 CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
 # CONFIG_THRUSTMASTER_FF is not set
+CONFIG_HID_ZEROPLUS=y
 # CONFIG_ZEROPLUS_FF is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
@@ -1462,6 +1485,7 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1636,25 +1660,28 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_DEBUG_PAGEALLOC is not set
 CONFIG_NOP_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
 CONFIG_TRACING=y
+CONFIG_GENERIC_TRACER=y
 CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
-#
-# Tracers
-#
 # CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 CONFIG_BLK_DEV_IO_TRACE=y
 # CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
diff --git a/arch/sparc/include/asm/cpudata_64.h b/arch/sparc/include/asm/cpudata_64.h
index a11b89ee9ef8..926397d345ff 100644
--- a/arch/sparc/include/asm/cpudata_64.h
+++ b/arch/sparc/include/asm/cpudata_64.h
@@ -6,9 +6,6 @@
 #ifndef _SPARC64_CPUDATA_H
 #define _SPARC64_CPUDATA_H
-#include <asm/hypervisor.h>
-#include <asm/asi.h>
 #ifndef __ASSEMBLY__
 #include <linux/percpu.h>
@@ -38,202 +35,10 @@ DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
 #define cpu_data(__cpu)         per_cpu(__cpu_data, (__cpu))
 #define local_cpu_data()        __get_cpu_var(__cpu_data)
-/* Trap handling code needs to get at a few critical values upon
- * trap entry and to process TSB misses.  These cannot be in the
- * per_cpu() area as we really need to lock them into the TLB and
- * thus make them part of the main kernel image.  As a result we
- * try to make this as small as possible.
- *
- * This is padded out and aligned to 64-bytes to avoid false sharing
- * on SMP.
- */
-/* If you modify the size of this structure, please update
- * TRAP_BLOCK_SZ_SHIFT below.
- */
-struct thread_info;
-struct trap_per_cpu {
-/* D-cache line 1: Basic thread information, cpu and device mondo queues */
-        struct thread_info      *thread;
-        unsigned long           pgd_paddr;
-        unsigned long           cpu_mondo_pa;
-        unsigned long           dev_mondo_pa;
-/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
-        unsigned long           resum_mondo_pa;
-        unsigned long           resum_kernel_buf_pa;
-        unsigned long           nonresum_mondo_pa;
-        unsigned long           nonresum_kernel_buf_pa;
-/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
-        struct hv_fault_status  fault_info;
-/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
-        unsigned long           cpu_mondo_block_pa;
-        unsigned long           cpu_list_pa;
-        unsigned long           tsb_huge;
-        unsigned long           tsb_huge_temp;
-/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
-        unsigned long           irq_worklist_pa;
-        unsigned int            cpu_mondo_qmask;
-        unsigned int            dev_mondo_qmask;
-        unsigned int            resum_qmask;
-        unsigned int            nonresum_qmask;
-        void                    *hdesc;
-} __attribute__((aligned(64)));
-extern struct trap_per_cpu trap_block[NR_CPUS];
-extern void init_cur_cpu_trap(struct thread_info *);
-extern void setup_tba(void);
-extern int ncpus_probed;
 extern const struct seq_operations cpuinfo_op;
-extern unsigned long real_hard_smp_processor_id(void);
-struct cpuid_patch_entry {
-        unsigned int    addr;
-        unsigned int    cheetah_safari[4];
-        unsigned int    cheetah_jbus[4];
-        unsigned int    starfire[4];
-        unsigned int    sun4v[4];
-};
-extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
-struct sun4v_1insn_patch_entry {
-        unsigned int    addr;
-        unsigned int    insn;
-};
-extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
-        __sun4v_1insn_patch_end;
-struct sun4v_2insn_patch_entry {
-        unsigned int    addr;
-        unsigned int    insns[2];
-};
-extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
-        __sun4v_2insn_patch_end;
 #endif /* !(__ASSEMBLY__) */
-#define TRAP_PER_CPU_THREAD             0x00
+#include <asm/trap_block.h>
-#define TRAP_PER_CPU_PGD_PADDR          0x08
-#define TRAP_PER_CPU_CPU_MONDO_PA       0x10
-#define TRAP_PER_CPU_DEV_MONDO_PA       0x18
-#define TRAP_PER_CPU_RESUM_MONDO_PA     0x20
-#define TRAP_PER_CPU_RESUM_KBUF_PA      0x28
-#define TRAP_PER_CPU_NONRESUM_MONDO_PA  0x30
-#define TRAP_PER_CPU_NONRESUM_KBUF_PA   0x38
-#define TRAP_PER_CPU_FAULT_INFO         0x40
-#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
-#define TRAP_PER_CPU_CPU_LIST_PA        0xc8
-#define TRAP_PER_CPU_TSB_HUGE           0xd0
-#define TRAP_PER_CPU_TSB_HUGE_TEMP      0xd8
-#define TRAP_PER_CPU_IRQ_WORKLIST_PA    0xe0
-#define TRAP_PER_CPU_CPU_MONDO_QMASK    0xe8
-#define TRAP_PER_CPU_DEV_MONDO_QMASK    0xec
-#define TRAP_PER_CPU_RESUM_QMASK        0xf0
-#define TRAP_PER_CPU_NONRESUM_QMASK     0xf4
-#define TRAP_BLOCK_SZ_SHIFT             8
-#include <asm/scratchpad.h>
-#define __GET_CPUID(REG)                                \
-        /* Spitfire implementation (default). */        \
-661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
-        srlx            REG, 17, REG;                   \
-         and            REG, 0x1f, REG;                 \
-        nop;                                            \
-        .section        .cpuid_patch, "ax";             \
-        /* Instruction location. */                     \
-        .word           661b;                           \
-        /* Cheetah Safari implementation. */            \
-        ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
-        srlx            REG, 17, REG;                   \
-        and             REG, 0x3ff, REG;                \
-        nop;                                            \
-        /* Cheetah JBUS implementation. */              \
-        ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
-        srlx            REG, 17, REG;                   \
-        and             REG, 0x1f, REG;                 \
-        nop;                                            \
-        /* Starfire implementation. */                  \
-        sethi           %hi(0x1fff40000d0 >> 9), REG;   \
-        sllx            REG, 9, REG;                    \
-        or              REG, 0xd0, REG;                 \
-        lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
-        /* sun4v implementation. */                     \
-        mov             SCRATCHPAD_CPUID, REG;          \
-        ldxa            [REG] ASI_SCRATCHPAD, REG;      \
-        nop;                                            \
-        nop;                                            \
-        .previous;
-#ifdef CONFIG_SMP
-#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        __GET_CPUID(TMP)                        \
-        sethi   %hi(trap_block), DEST;          \
-        sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
-        or      DEST, %lo(trap_block), DEST;    \
-        add     DEST, TMP, DEST;                \
-/* Clobbers TMP, current address space PGD phys address into DEST.  */
-#define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
-        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
-/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
-#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
-        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
-/* Clobbers TMP, loads DEST with current thread info pointer.  */
-#define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
-        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
-/* Given the current thread info pointer in THR, load the per-cpu
- * area base of the current processor into DEST.  REG1, REG2, and REG3 are
- * clobbered.
- *
- * You absolutely cannot use DEST as a temporary in this code.  The
- * reason is that traps can happen during execution, and return from
- * trap will load the fully resolved DEST per-cpu base.  This can corrupt
- * the calculations done by the macro mid-stream.
- */
-#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
-        lduh    [THR + TI_CPU], REG1;                   \
-        sethi   %hi(__per_cpu_shift), REG3;             \
-        sethi   %hi(__per_cpu_base), REG2;              \
-        ldx     [REG3 + %lo(__per_cpu_shift)], REG3;    \
-        ldx     [REG2 + %lo(__per_cpu_base)], REG2;     \
-        sllx    REG1, REG3, REG3;                       \
-        add     REG3, REG2, DEST;
-#else
-#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        sethi   %hi(trap_block), DEST;          \
-        or      DEST, %lo(trap_block), DEST;    \
-/* Uniprocessor versions, we know the cpuid is zero.  */
-#define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
-        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
-/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
-#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
-        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
-#define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
-        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
-        ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
-/* No per-cpu areas on uniprocessor, so no need to load DEST.  */
-#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
-#endif /* !(CONFIG_SMP) */
 #endif /* _SPARC64_CPUDATA_H */
diff --git a/arch/sparc/include/asm/dma-mapping.h b/arch/sparc/include/asm/dma-mapping.h
index 0f4150e26619..204e4bf64438 100644
--- a/arch/sparc/include/asm/dma-mapping.h
+++ b/arch/sparc/include/asm/dma-mapping.h
@@ -1,8 +1,166 @@
 #ifndef ___ASM_SPARC_DMA_MAPPING_H
 #define ___ASM_SPARC_DMA_MAPPING_H
-#if defined(__sparc__) && defined(__arch64__)
-#include <asm/dma-mapping_64.h>
+#include <linux/scatterlist.h>
-#else
+#include <linux/mm.h>
-#include <asm/dma-mapping_32.h>
-#endif
+#define DMA_ERROR_CODE  (~(dma_addr_t)0x0)
+extern int dma_supported(struct device *dev, u64 mask);
+extern int dma_set_mask(struct device *dev, u64 dma_mask);
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_is_consistent(d, h) (1)
+struct dma_ops {
+        void *(*alloc_coherent)(struct device *dev, size_t size,
+                                dma_addr_t *dma_handle, gfp_t flag);
+        void (*free_coherent)(struct device *dev, size_t size,
+                              void *cpu_addr, dma_addr_t dma_handle);
+        dma_addr_t (*map_page)(struct device *dev, struct page *page,
+                               unsigned long offset, size_t size,
+                               enum dma_data_direction direction);
+        void (*unmap_page)(struct device *dev, dma_addr_t dma_addr,
+                           size_t size,
+                           enum dma_data_direction direction);
+        int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
+                      enum dma_data_direction direction);
+        void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
+                         int nhwentries,
+                         enum dma_data_direction direction);
+        void (*sync_single_for_cpu)(struct device *dev,
+                                    dma_addr_t dma_handle, size_t size,
+                                    enum dma_data_direction direction);
+        void (*sync_single_for_device)(struct device *dev,
+                                       dma_addr_t dma_handle, size_t size,
+                                       enum dma_data_direction direction);
+        void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
+                                int nelems,
+                                enum dma_data_direction direction);
+        void (*sync_sg_for_device)(struct device *dev,
+                                   struct scatterlist *sg, int nents,
+                                   enum dma_data_direction dir);
+};
+extern const struct dma_ops *dma_ops;
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t flag)
+{
+        return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
+}
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *cpu_addr, dma_addr_t dma_handle)
+{
+        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+}
+static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                                        size_t size,
+                                        enum dma_data_direction direction)
+{
+        return dma_ops->map_page(dev, virt_to_page(cpu_addr),
+                                 (unsigned long)cpu_addr & ~PAGE_MASK, size,
+                                 direction);
+}
+static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                                    size_t size,
+                                    enum dma_data_direction direction)
+{
+        dma_ops->unmap_page(dev, dma_addr, size, direction);
+}
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      unsigned long offset, size_t size,
+                                      enum dma_data_direction direction)
+{
+        return dma_ops->map_page(dev, page, offset, size, direction);
+}
+static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                  size_t size,
+                                  enum dma_data_direction direction)
+{
+        dma_ops->unmap_page(dev, dma_address, size, direction);
+}
+static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+                             int nents, enum dma_data_direction direction)
+{
+        return dma_ops->map_sg(dev, sg, nents, direction);
+}
+static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction direction)
+{
+        dma_ops->unmap_sg(dev, sg, nents, direction);
+}
+static inline void dma_sync_single_for_cpu(struct device *dev,
+                                           dma_addr_t dma_handle, size_t size,
+                                           enum dma_data_direction direction)
+{
+        dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
+}
+static inline void dma_sync_single_for_device(struct device *dev,
+                                              dma_addr_t dma_handle,
+                                              size_t size,
+                                              enum dma_data_direction direction)
+{
+        if (dma_ops->sync_single_for_device)
+                dma_ops->sync_single_for_device(dev, dma_handle, size,
+                                                direction);
+}
+static inline void dma_sync_sg_for_cpu(struct device *dev,
+                                       struct scatterlist *sg, int nelems,
+                                       enum dma_data_direction direction)
+{
+        dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
+}
+static inline void dma_sync_sg_for_device(struct device *dev,
+                                          struct scatterlist *sg, int nelems,
+                                          enum dma_data_direction direction)
+{
+        if (dma_ops->sync_sg_for_device)
+                dma_ops->sync_sg_for_device(dev, sg, nelems, direction);
+}
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+                                                 dma_addr_t dma_handle,
+                                                 unsigned long offset,
+                                                 size_t size,
+                                                 enum dma_data_direction dir)
+{
+        dma_sync_single_for_cpu(dev, dma_handle+offset, size, dir);
+}
+static inline void dma_sync_single_range_for_device(struct device *dev,
+                                                    dma_addr_t dma_handle,
+                                                    unsigned long offset,
+                                                    size_t size,
+                                                    enum dma_data_direction dir)
+{
+        dma_sync_single_for_device(dev, dma_handle+offset, size, dir);
+}
+static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return (dma_addr == DMA_ERROR_CODE);
+}
+static inline int dma_get_cache_alignment(void)
+{
+        /*
+         * no easy way to get cache size on all processors, so return
+         * the maximum possible, to be safe
+         */
+        return (1 << INTERNODE_CACHE_SHIFT);
+}
 #endif
diff --git a/arch/sparc/include/asm/dma-mapping_32.h b/arch/sparc/include/asm/dma-mapping_32.h
deleted file mode 100644
index 8a57ea0573e6..000000000000
--- a/arch/sparc/include/asm/dma-mapping_32.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef _ASM_SPARC_DMA_MAPPING_H
-#define _ASM_SPARC_DMA_MAPPING_H
-#include <linux/types.h>
-struct device;
-struct scatterlist;
-struct page;
-#define DMA_ERROR_CODE  (~(dma_addr_t)0x0)
-extern int dma_supported(struct device *dev, u64 mask);
-extern int dma_set_mask(struct device *dev, u64 dma_mask);
-extern void *dma_alloc_coherent(struct device *dev, size_t size,
-                                dma_addr_t *dma_handle, gfp_t flag);
-extern void dma_free_coherent(struct device *dev, size_t size,
-                              void *cpu_addr, dma_addr_t dma_handle);
-extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
-                                 size_t size,
-                                 enum dma_data_direction direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-                             size_t size,
-                             enum dma_data_direction direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                               unsigned long offset, size_t size,
-                               enum dma_data_direction direction);
-extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-                           size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg,
-                      int nents, enum dma_data_direction direction);
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                         int nents, enum dma_data_direction direction);
-extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-                                    size_t size,
-                                    enum dma_data_direction direction);
-extern void dma_sync_single_for_device(struct device *dev,
-                                       dma_addr_t dma_handle,
-                                       size_t size,
-                                       enum dma_data_direction direction);
-extern void dma_sync_single_range_for_cpu(struct device *dev,
-                                          dma_addr_t dma_handle,
-                                          unsigned long offset,
-                                          size_t size,
-                                          enum dma_data_direction direction);
-extern void dma_sync_single_range_for_device(struct device *dev,
-                                             dma_addr_t dma_handle,
-                                             unsigned long offset, size_t size,
-                                             enum dma_data_direction direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
-                                int nelems, enum dma_data_direction direction);
-extern void dma_sync_sg_for_device(struct device *dev,
-                                   struct scatterlist *sg, int nelems,
-                                   enum dma_data_direction direction);
-extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
-extern int dma_get_cache_alignment(void);
-#define dma_alloc_noncoherent   dma_alloc_coherent
-#define dma_free_noncoherent    dma_free_coherent
-#endif /* _ASM_SPARC_DMA_MAPPING_H */
diff --git a/arch/sparc/include/asm/dma-mapping_64.h b/arch/sparc/include/asm/dma-mapping_64.h
deleted file mode 100644
index bfa64f9702d5..000000000000
--- a/arch/sparc/include/asm/dma-mapping_64.h
+++ /dev/null
@@ -1,154 +0,0 @@
-#ifndef _ASM_SPARC64_DMA_MAPPING_H
-#define _ASM_SPARC64_DMA_MAPPING_H
-#include <linux/scatterlist.h>
-#include <linux/mm.h>
-#define DMA_ERROR_CODE  (~(dma_addr_t)0x0)
-struct dma_ops {
-        void *(*alloc_coherent)(struct device *dev, size_t size,
-                                dma_addr_t *dma_handle, gfp_t flag);
-        void (*free_coherent)(struct device *dev, size_t size,
-                              void *cpu_addr, dma_addr_t dma_handle);
-        dma_addr_t (*map_single)(struct device *dev, void *cpu_addr,
-                                 size_t size,
-                                 enum dma_data_direction direction);
-        void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
-                             size_t size,
-                             enum dma_data_direction direction);
-        int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
-                      enum dma_data_direction direction);
-        void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
-                         int nhwentries,
-                         enum dma_data_direction direction);
-        void (*sync_single_for_cpu)(struct device *dev,
-                                    dma_addr_t dma_handle, size_t size,
-                                    enum dma_data_direction direction);
-        void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
-                                int nelems,
-                                enum dma_data_direction direction);
-};
-extern const struct dma_ops *dma_ops;
-extern int dma_supported(struct device *dev, u64 mask);
-extern int dma_set_mask(struct device *dev, u64 dma_mask);
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                                       dma_addr_t *dma_handle, gfp_t flag)
-{
-        return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
-}
-static inline void dma_free_coherent(struct device *dev, size_t size,
-                                     void *cpu_addr, dma_addr_t dma_handle)
-{
-        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
-}
-static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
-                                        size_t size,
-                                        enum dma_data_direction direction)
-{
-        return dma_ops->map_single(dev, cpu_addr, size, direction);
-}
-static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-                                    size_t size,
-                                    enum dma_data_direction direction)
-{
-        dma_ops->unmap_single(dev, dma_addr, size, direction);
-}
-static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                                      unsigned long offset, size_t size,
-                                      enum dma_data_direction direction)
-{
-        return dma_ops->map_single(dev, page_address(page) + offset,
-                                   size, direction);
-}
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-                                  size_t size,
-                                  enum dma_data_direction direction)
-{
-        dma_ops->unmap_single(dev, dma_address, size, direction);
-}
-static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
-                             int nents, enum dma_data_direction direction)
-{
-        return dma_ops->map_sg(dev, sg, nents, direction);
-}
-static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction)
-{
-        dma_ops->unmap_sg(dev, sg, nents, direction);
-}
-static inline void dma_sync_single_for_cpu(struct device *dev,
-                                           dma_addr_t dma_handle, size_t size,
-                                           enum dma_data_direction direction)
-{
-        dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
-}
-static inline void dma_sync_single_for_device(struct device *dev,
-                                              dma_addr_t dma_handle,
-                                              size_t size,
-                                              enum dma_data_direction direction)
-{
-        /* No flushing needed to sync cpu writes to the device.  */
-}
-static inline void dma_sync_single_range_for_cpu(struct device *dev,
-                                                 dma_addr_t dma_handle,
-                                                 unsigned long offset,
-                                                 size_t size,
-                                                 enum dma_data_direction direction)
-{
-        dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
-}
-static inline void dma_sync_single_range_for_device(struct device *dev,
-                                                    dma_addr_t dma_handle,
-                                                    unsigned long offset,
-                                                    size_t size,
-                                                    enum dma_data_direction direction)
-{
-        /* No flushing needed to sync cpu writes to the device.  */
-}
-static inline void dma_sync_sg_for_cpu(struct device *dev,
-                                       struct scatterlist *sg, int nelems,
-                                       enum dma_data_direction direction)
-{
-        dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
-}
-static inline void dma_sync_sg_for_device(struct device *dev,
-                                          struct scatterlist *sg, int nelems,
-                                          enum dma_data_direction direction)
-{
-        /* No flushing needed to sync cpu writes to the device.  */
-}
-static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
-{
-        return (dma_addr == DMA_ERROR_CODE);
-}
-static inline int dma_get_cache_alignment(void)
-{
-        /* no easy way to get cache size on all processors, so return
-         * the maximum possible, to be safe */
-        return (1 << INTERNODE_CACHE_SHIFT);
-}
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d, h) (1)
-#endif /* _ASM_SPARC64_DMA_MAPPING_H */
diff --git a/arch/sparc/include/asm/errno.h b/arch/sparc/include/asm/errno.h
index a9ef172977de..4e2bc490d714 100644
--- a/arch/sparc/include/asm/errno.h
+++ b/arch/sparc/include/asm/errno.h
@@ -110,4 +110,6 @@
 #define EOWNERDEAD      132     /* Owner died */
 #define ENOTRECOVERABLE 133     /* State not recoverable */
+#define ERFKILL         134     /* Operation not possible due to RF-kill */
 #endif
diff --git a/arch/sparc/include/asm/ftrace.h b/arch/sparc/include/asm/ftrace.h
index d27716cd38c1..b0f18e9893db 100644
--- a/arch/sparc/include/asm/ftrace.h
+++ b/arch/sparc/include/asm/ftrace.h
@@ -11,4 +11,15 @@ extern void _mcount(void);
 #endif
+#ifdef CONFIG_DYNAMIC_FTRACE
+/* reloction of mcount call site is the same as the address */
+static inline unsigned long ftrace_call_adjust(unsigned long addr)
+{
+        return addr;
+}
+struct dyn_arch_ftrace {
+};
+#endif /*  CONFIG_DYNAMIC_FTRACE */
 #endif /* _ASM_SPARC64_FTRACE */
diff --git a/arch/sparc/include/asm/kmap_types.h b/arch/sparc/include/asm/kmap_types.h
index 602f5e034f7a..aad21745fbb9 100644
--- a/arch/sparc/include/asm/kmap_types.h
+++ b/arch/sparc/include/asm/kmap_types.h
@@ -5,21 +5,6 @@
 * is actually used on sparc.  -DaveM
 */
-enum km_type {
+#include <asm-generic/kmap_types.h>
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
 #endif
diff --git a/arch/sparc/include/asm/mdesc.h b/arch/sparc/include/asm/mdesc.h
index 1acc7272e537..9faa046713fb 100644
--- a/arch/sparc/include/asm/mdesc.h
+++ b/arch/sparc/include/asm/mdesc.h
@@ -71,7 +71,8 @@ struct mdesc_notifier_client {
 extern void mdesc_register_notifier(struct mdesc_notifier_client *client);
-extern void mdesc_fill_in_cpu_data(cpumask_t mask);
+extern void mdesc_fill_in_cpu_data(cpumask_t *mask);
+extern void mdesc_populate_present_mask(cpumask_t *mask);
 extern void sun4v_mdesc_init(void);
diff --git a/arch/sparc/include/asm/percpu_64.h b/arch/sparc/include/asm/percpu_64.h
index bee64593023e..007aafb4ae97 100644
--- a/arch/sparc/include/asm/percpu_64.h
+++ b/arch/sparc/include/asm/percpu_64.h
@@ -7,20 +7,16 @@ register unsigned long __local_per_cpu_offset asm("g5");
 #ifdef CONFIG_SMP
-extern void real_setup_per_cpu_areas(void);
+#include <asm/trap_block.h>
-extern unsigned long __per_cpu_base;
-extern unsigned long __per_cpu_shift;
 #define __per_cpu_offset(__cpu) \
-        (__per_cpu_base + ((unsigned long)(__cpu) << __per_cpu_shift))
+        (trap_block[(__cpu)].__per_cpu_base)
 #define per_cpu_offset(x) (__per_cpu_offset(x))
 #define __my_cpu_offset __local_per_cpu_offset
 #else /* ! SMP */
-#define real_setup_per_cpu_areas()              do { } while (0)
 #endif  /* SMP */
 #include <asm-generic/percpu.h>
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
index 900d44714f8d..be8d7aaeb60d 100644
--- a/arch/sparc/include/asm/prom.h
+++ b/arch/sparc/include/asm/prom.h
@@ -86,6 +86,8 @@ extern int of_node_to_nid(struct device_node *dp);
 #endif
 extern void prom_build_devicetree(void);
+extern void of_populate_present_mask(void);
+extern void of_fill_in_cpu_data(void);
 /* Dummy ref counting routines - to be implemented later */
 static inline struct device_node *of_node_get(struct device_node *node)
diff --git a/arch/sparc/include/asm/trap_block.h b/arch/sparc/include/asm/trap_block.h
new file mode 100644
index 000000000000..7e26b2db6211
--- /dev/null
+++ b/arch/sparc/include/asm/trap_block.h
@@ -0,0 +1,207 @@
+#ifndef _SPARC_TRAP_BLOCK_H
+#define _SPARC_TRAP_BLOCK_H
+#include <asm/hypervisor.h>
+#include <asm/asi.h>
+#ifndef __ASSEMBLY__
+/* Trap handling code needs to get at a few critical values upon
+ * trap entry and to process TSB misses.  These cannot be in the
+ * per_cpu() area as we really need to lock them into the TLB and
+ * thus make them part of the main kernel image.  As a result we
+ * try to make this as small as possible.
+ *
+ * This is padded out and aligned to 64-bytes to avoid false sharing
+ * on SMP.
+ */
+/* If you modify the size of this structure, please update
+ * TRAP_BLOCK_SZ_SHIFT below.
+ */
+struct thread_info;
+struct trap_per_cpu {
+/* D-cache line 1: Basic thread information, cpu and device mondo queues */
+        struct thread_info      *thread;
+        unsigned long           pgd_paddr;
+        unsigned long           cpu_mondo_pa;
+        unsigned long           dev_mondo_pa;
+/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
+        unsigned long           resum_mondo_pa;
+        unsigned long           resum_kernel_buf_pa;
+        unsigned long           nonresum_mondo_pa;
+        unsigned long           nonresum_kernel_buf_pa;
+/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
+        struct hv_fault_status  fault_info;
+/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
+        unsigned long           cpu_mondo_block_pa;
+        unsigned long           cpu_list_pa;
+        unsigned long           tsb_huge;
+        unsigned long           tsb_huge_temp;
+/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
+        unsigned long           irq_worklist_pa;
+        unsigned int            cpu_mondo_qmask;
+        unsigned int            dev_mondo_qmask;
+        unsigned int            resum_qmask;
+        unsigned int            nonresum_qmask;
+        unsigned long           __per_cpu_base;
+} __attribute__((aligned(64)));
+extern struct trap_per_cpu trap_block[NR_CPUS];
+extern void init_cur_cpu_trap(struct thread_info *);
+extern void setup_tba(void);
+extern int ncpus_probed;
+extern unsigned long real_hard_smp_processor_id(void);
+struct cpuid_patch_entry {
+        unsigned int    addr;
+        unsigned int    cheetah_safari[4];
+        unsigned int    cheetah_jbus[4];
+        unsigned int    starfire[4];
+        unsigned int    sun4v[4];
+};
+extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
+struct sun4v_1insn_patch_entry {
+        unsigned int    addr;
+        unsigned int    insn;
+};
+extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
+        __sun4v_1insn_patch_end;
+struct sun4v_2insn_patch_entry {
+        unsigned int    addr;
+        unsigned int    insns[2];
+};
+extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
+        __sun4v_2insn_patch_end;
+#endif /* !(__ASSEMBLY__) */
+#define TRAP_PER_CPU_THREAD             0x00
+#define TRAP_PER_CPU_PGD_PADDR          0x08
+#define TRAP_PER_CPU_CPU_MONDO_PA       0x10
+#define TRAP_PER_CPU_DEV_MONDO_PA       0x18
+#define TRAP_PER_CPU_RESUM_MONDO_PA     0x20
+#define TRAP_PER_CPU_RESUM_KBUF_PA      0x28
+#define TRAP_PER_CPU_NONRESUM_MONDO_PA  0x30
+#define TRAP_PER_CPU_NONRESUM_KBUF_PA   0x38
+#define TRAP_PER_CPU_FAULT_INFO         0x40
+#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
+#define TRAP_PER_CPU_CPU_LIST_PA        0xc8
+#define TRAP_PER_CPU_TSB_HUGE           0xd0
+#define TRAP_PER_CPU_TSB_HUGE_TEMP      0xd8
+#define TRAP_PER_CPU_IRQ_WORKLIST_PA    0xe0
+#define TRAP_PER_CPU_CPU_MONDO_QMASK    0xe8
+#define TRAP_PER_CPU_DEV_MONDO_QMASK    0xec
+#define TRAP_PER_CPU_RESUM_QMASK        0xf0
+#define TRAP_PER_CPU_NONRESUM_QMASK     0xf4
+#define TRAP_PER_CPU_PER_CPU_BASE       0xf8
+#define TRAP_BLOCK_SZ_SHIFT             8
+#include <asm/scratchpad.h>
+#define __GET_CPUID(REG)                                \
+        /* Spitfire implementation (default). */        \
+661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
+        srlx            REG, 17, REG;                   \
+         and            REG, 0x1f, REG;                 \
+        nop;                                            \
+        .section        .cpuid_patch, "ax";             \
+        /* Instruction location. */                     \
+        .word           661b;                           \
+        /* Cheetah Safari implementation. */            \
+        ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
+        srlx            REG, 17, REG;                   \
+        and             REG, 0x3ff, REG;                \
+        nop;                                            \
+        /* Cheetah JBUS implementation. */              \
+        ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
+        srlx            REG, 17, REG;                   \
+        and             REG, 0x1f, REG;                 \
+        nop;                                            \
+        /* Starfire implementation. */                  \
+        sethi           %hi(0x1fff40000d0 >> 9), REG;   \
+        sllx            REG, 9, REG;                    \
+        or              REG, 0xd0, REG;                 \
+        lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
+        /* sun4v implementation. */                     \
+        mov             SCRATCHPAD_CPUID, REG;          \
+        ldxa            [REG] ASI_SCRATCHPAD, REG;      \
+        nop;                                            \
+        nop;                                            \
+        .previous;
+#ifdef CONFIG_SMP
+#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        __GET_CPUID(TMP)                        \
+        sethi   %hi(trap_block), DEST;          \
+        sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
+        or      DEST, %lo(trap_block), DEST;    \
+        add     DEST, TMP, DEST;                \
+/* Clobbers TMP, current address space PGD phys address into DEST.  */
+#define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
+/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
+#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
+/* Clobbers TMP, loads DEST with current thread info pointer.  */
+#define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
+/* Given the current thread info pointer in THR, load the per-cpu
+ * area base of the current processor into DEST.  REG1, REG2, and REG3 are
+ * clobbered.
+ *
+ * You absolutely cannot use DEST as a temporary in this code.  The
+ * reason is that traps can happen during execution, and return from
+ * trap will load the fully resolved DEST per-cpu base.  This can corrupt
+ * the calculations done by the macro mid-stream.
+ */
+#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
+        lduh    [THR + TI_CPU], REG1;                   \
+        sethi   %hi(trap_block), REG2;                  \
+        sllx    REG1, TRAP_BLOCK_SZ_SHIFT, REG1;        \
+        or      REG2, %lo(trap_block), REG2;            \
+        add     REG2, REG1, REG2;                       \
+        ldx     [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
+#else
+#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        sethi   %hi(trap_block), DEST;          \
+        or      DEST, %lo(trap_block), DEST;    \
+/* Uniprocessor versions, we know the cpuid is zero.  */
+#define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
+/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
+#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)        \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        add     DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
+#define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
+        TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
+        ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
+/* No per-cpu areas on uniprocessor, so no need to load DEST.  */
+#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
+#endif /* !(CONFIG_SMP) */
+#endif /* _SPARC_TRAP_BLOCK_H */
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index b8eb71ef3163..b2c406de7d4f 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -394,8 +394,9 @@
 #define __NR_accept4            323
 #define __NR_preadv             324
 #define __NR_pwritev            325
+#define __NR_rt_tgsigqueueinfo  326
-#define NR_SYSCALLS             326
+#define NR_SYSCALLS             327
 #ifdef __32bit_syscall_numbers__
 /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 54742e58831c..475ce4696acd 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -37,6 +37,7 @@ obj-y                   += una_asm_$(BITS).o
 obj-$(CONFIG_SPARC32)   += muldiv.o
 obj-y                   += prom_common.o
 obj-y                   += prom_$(BITS).o
+obj-y                   += of_device_common.o
 obj-y                   += of_device_$(BITS).o
 obj-$(CONFIG_SPARC64)   += prom_irqtrans.o
@@ -54,6 +55,7 @@ obj-$(CONFIG_SPARC64)   += sstate.o
 obj-$(CONFIG_SPARC64)   += mdesc.o
 obj-$(CONFIG_SPARC64)   += pcr.o
 obj-$(CONFIG_SPARC64)   += nmi.o
+obj-$(CONFIG_SPARC64_SMP) += cpumap.o
 # sparc32 do not use GENERIC_HARDIRQS but uses the generic devres implementation
 obj-$(CONFIG_SPARC32)     += devres.o
diff --git a/arch/sparc/kernel/cpumap.c b/arch/sparc/kernel/cpumap.c
new file mode 100644
index 000000000000..7430ed080b23
--- /dev/null
+++ b/arch/sparc/kernel/cpumap.c
@@ -0,0 +1,431 @@
+/* cpumap.c: used for optimizing CPU assignment
+ *
+ * Copyright (C) 2009 Hong H. Pham <hong.pham@windriver.com>
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/spinlock.h>
+#include <asm/cpudata.h>
+#include "cpumap.h"
+enum {
+        CPUINFO_LVL_ROOT = 0,
+        CPUINFO_LVL_NODE,
+        CPUINFO_LVL_CORE,
+        CPUINFO_LVL_PROC,
+        CPUINFO_LVL_MAX,
+};
+enum {
+        ROVER_NO_OP              = 0,
+        /* Increment rover every time level is visited */
+        ROVER_INC_ON_VISIT       = 1 << 0,
+        /* Increment parent's rover every time rover wraps around */
+        ROVER_INC_PARENT_ON_LOOP = 1 << 1,
+};
+struct cpuinfo_node {
+        int id;
+        int level;
+        int num_cpus;    /* Number of CPUs in this hierarchy */
+        int parent_index;
+        int child_start; /* Array index of the first child node */
+        int child_end;   /* Array index of the last child node */
+        int rover;       /* Child node iterator */
+};
+struct cpuinfo_level {
+        int start_index; /* Index of first node of a level in a cpuinfo tree */
+        int end_index;   /* Index of last node of a level in a cpuinfo tree */
+        int num_nodes;   /* Number of nodes in a level in a cpuinfo tree */
+};
+struct cpuinfo_tree {
+        int total_nodes;
+        /* Offsets into nodes[] for each level of the tree */
+        struct cpuinfo_level level[CPUINFO_LVL_MAX];
+        struct cpuinfo_node  nodes[0];
+};
+static struct cpuinfo_tree *cpuinfo_tree;
+static u16 cpu_distribution_map[NR_CPUS];
+static DEFINE_SPINLOCK(cpu_map_lock);
+/* Niagara optimized cpuinfo tree traversal. */
+static const int niagara_iterate_method[] = {
+        [CPUINFO_LVL_ROOT] = ROVER_NO_OP,
+        /* Strands (or virtual CPUs) within a core may not run concurrently
+         * on the Niagara, as instruction pipeline(s) are shared.  Distribute
+         * work to strands in different cores first for better concurrency.
+         * Go to next NUMA node when all cores are used.
+         */
+        [CPUINFO_LVL_NODE] = ROVER_INC_ON_VISIT|ROVER_INC_PARENT_ON_LOOP,
+        /* Strands are grouped together by proc_id in cpuinfo_sparc, i.e.
+         * a proc_id represents an instruction pipeline.  Distribute work to
+         * strands in different proc_id groups if the core has multiple
+         * instruction pipelines (e.g. the Niagara 2/2+ has two).
+         */
+        [CPUINFO_LVL_CORE] = ROVER_INC_ON_VISIT,
+        /* Pick the next strand in the proc_id group. */
+        [CPUINFO_LVL_PROC] = ROVER_INC_ON_VISIT,
+};
+/* Generic cpuinfo tree traversal.  Distribute work round robin across NUMA
+ * nodes.
+ */
+static const int generic_iterate_method[] = {
+        [CPUINFO_LVL_ROOT] = ROVER_INC_ON_VISIT,
+        [CPUINFO_LVL_NODE] = ROVER_NO_OP,
+        [CPUINFO_LVL_CORE] = ROVER_INC_PARENT_ON_LOOP,
+        [CPUINFO_LVL_PROC] = ROVER_INC_ON_VISIT|ROVER_INC_PARENT_ON_LOOP,
+};
+static int cpuinfo_id(int cpu, int level)
+{
+        int id;
+        switch (level) {
+        case CPUINFO_LVL_ROOT:
+                id = 0;
+                break;
+        case CPUINFO_LVL_NODE:
+                id = cpu_to_node(cpu);
+                break;
+        case CPUINFO_LVL_CORE:
+                id = cpu_data(cpu).core_id;
+                break;
+        case CPUINFO_LVL_PROC:
+                id = cpu_data(cpu).proc_id;
+                break;
+        default:
+                id = -EINVAL;
+        }
+        return id;
+}
+/*
+ * Enumerate the CPU information in __cpu_data to determine the start index,
+ * end index, and number of nodes for each level in the cpuinfo tree.  The
+ * total number of cpuinfo nodes required to build the tree is returned.
+ */
+static int enumerate_cpuinfo_nodes(struct cpuinfo_level *tree_level)
+{
+        int prev_id[CPUINFO_LVL_MAX];
+        int i, n, num_nodes;
+        for (i = CPUINFO_LVL_ROOT; i < CPUINFO_LVL_MAX; i++) {
+                struct cpuinfo_level *lv = &tree_level[i];
+                prev_id[i] = -1;
+                lv->start_index = lv->end_index = lv->num_nodes = 0;
+        }
+        num_nodes = 1; /* Include the root node */
+        for (i = 0; i < num_possible_cpus(); i++) {
+                if (!cpu_online(i))
+                        continue;
+                n = cpuinfo_id(i, CPUINFO_LVL_NODE);
+                if (n > prev_id[CPUINFO_LVL_NODE]) {
+                        tree_level[CPUINFO_LVL_NODE].num_nodes++;
+                        prev_id[CPUINFO_LVL_NODE] = n;
+                        num_nodes++;
+                }
+                n = cpuinfo_id(i, CPUINFO_LVL_CORE);
+                if (n > prev_id[CPUINFO_LVL_CORE]) {
+                        tree_level[CPUINFO_LVL_CORE].num_nodes++;
+                        prev_id[CPUINFO_LVL_CORE] = n;
+                        num_nodes++;
+                }
+                n = cpuinfo_id(i, CPUINFO_LVL_PROC);
+                if (n > prev_id[CPUINFO_LVL_PROC]) {
+                        tree_level[CPUINFO_LVL_PROC].num_nodes++;
+                        prev_id[CPUINFO_LVL_PROC] = n;
+                        num_nodes++;
+                }
+        }
+        tree_level[CPUINFO_LVL_ROOT].num_nodes = 1;
+        n = tree_level[CPUINFO_LVL_NODE].num_nodes;
+        tree_level[CPUINFO_LVL_NODE].start_index = 1;
+        tree_level[CPUINFO_LVL_NODE].end_index   = n;
+        n++;
+        tree_level[CPUINFO_LVL_CORE].start_index = n;
+        n += tree_level[CPUINFO_LVL_CORE].num_nodes;
+        tree_level[CPUINFO_LVL_CORE].end_index   = n - 1;
+        tree_level[CPUINFO_LVL_PROC].start_index = n;
+        n += tree_level[CPUINFO_LVL_PROC].num_nodes;
+        tree_level[CPUINFO_LVL_PROC].end_index   = n - 1;
+        return num_nodes;
+}
+/* Build a tree representation of the CPU hierarchy using the per CPU
+ * information in __cpu_data.  Entries in __cpu_data[0..NR_CPUS] are
+ * assumed to be sorted in ascending order based on node, core_id, and
+ * proc_id (in order of significance).
+ */
+static struct cpuinfo_tree *build_cpuinfo_tree(void)
+{
+        struct cpuinfo_tree *new_tree;
+        struct cpuinfo_node *node;
+        struct cpuinfo_level tmp_level[CPUINFO_LVL_MAX];
+        int num_cpus[CPUINFO_LVL_MAX];
+        int level_rover[CPUINFO_LVL_MAX];
+        int prev_id[CPUINFO_LVL_MAX];
+        int n, id, cpu, prev_cpu, last_cpu, level;
+        n = enumerate_cpuinfo_nodes(tmp_level);
+        new_tree = kzalloc(sizeof(struct cpuinfo_tree) +
+                           (sizeof(struct cpuinfo_node) * n), GFP_ATOMIC);
+        if (!new_tree)
+                return NULL;
+        new_tree->total_nodes = n;
+        memcpy(&new_tree->level, tmp_level, sizeof(tmp_level));
+        prev_cpu = cpu = first_cpu(cpu_online_map);
+        /* Initialize all levels in the tree with the first CPU */
+        for (level = CPUINFO_LVL_PROC; level >= CPUINFO_LVL_ROOT; level--) {
+                n = new_tree->level[level].start_index;
+                level_rover[level] = n;
+                node = &new_tree->nodes[n];
+                id = cpuinfo_id(cpu, level);
+                if (unlikely(id < 0)) {
+                        kfree(new_tree);
+                        return NULL;
+                }
+                node->id = id;
+                node->level = level;
+                node->num_cpus = 1;
+                node->parent_index = (level > CPUINFO_LVL_ROOT)
+                    ? new_tree->level[level - 1].start_index : -1;
+                node->child_start = node->child_end = node->rover =
+                    (level == CPUINFO_LVL_PROC)
+                    ? cpu : new_tree->level[level + 1].start_index;
+                prev_id[level] = node->id;
+                num_cpus[level] = 1;
+        }
+        for (last_cpu = (num_possible_cpus() - 1); last_cpu >= 0; last_cpu--) {
+                if (cpu_online(last_cpu))
+                        break;
+        }
+        while (++cpu <= last_cpu) {
+                if (!cpu_online(cpu))
+                        continue;
+                for (level = CPUINFO_LVL_PROC; level >= CPUINFO_LVL_ROOT;
+                     level--) {
+                        id = cpuinfo_id(cpu, level);
+                        if (unlikely(id < 0)) {
+                                kfree(new_tree);
+                                return NULL;
+                        }
+                        if ((id != prev_id[level]) || (cpu == last_cpu)) {
+                                prev_id[level] = id;
+                                node = &new_tree->nodes[level_rover[level]];
+                                node->num_cpus = num_cpus[level];
+                                num_cpus[level] = 1;
+                                if (cpu == last_cpu)
+                                        node->num_cpus++;
+                                /* Connect tree node to parent */
+                                if (level == CPUINFO_LVL_ROOT)
+                                        node->parent_index = -1;
+                                else
+                                        node->parent_index =
+                                            level_rover[level - 1];
+                                if (level == CPUINFO_LVL_PROC) {
+                                        node->child_end =
+                                            (cpu == last_cpu) ? cpu : prev_cpu;
+                                } else {
+                                        node->child_end =
+                                            level_rover[level + 1] - 1;
+                                }
+                                /* Initialize the next node in the same level */
+                                n = ++level_rover[level];
+                                if (n <= new_tree->level[level].end_index) {
+                                        node = &new_tree->nodes[n];
+                                        node->id = id;
+                                        node->level = level;
+                                        /* Connect node to child */
+                                        node->child_start = node->child_end =
+                                        node->rover =
+                                            (level == CPUINFO_LVL_PROC)
+                                            ? cpu : level_rover[level + 1];
+                                }
+                        } else
+                                num_cpus[level]++;
+                }
+                prev_cpu = cpu;
+        }
+        return new_tree;
+}
+static void increment_rover(struct cpuinfo_tree *t, int node_index,
+                            int root_index, const int *rover_inc_table)
+{
+        struct cpuinfo_node *node = &t->nodes[node_index];
+        int top_level, level;
+        top_level = t->nodes[root_index].level;
+        for (level = node->level; level >= top_level; level--) {
+                node->rover++;
+                if (node->rover <= node->child_end)
+                        return;
+                node->rover = node->child_start;
+                /* If parent's rover does not need to be adjusted, stop here. */
+                if ((level == top_level) ||
+                    !(rover_inc_table[level] & ROVER_INC_PARENT_ON_LOOP))
+                        return;
+                node = &t->nodes[node->parent_index];
+        }
+}
+static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
+{
+        const int *rover_inc_table;
+        int level, new_index, index = root_index;
+        switch (sun4v_chip_type) {
+        case SUN4V_CHIP_NIAGARA1:
+        case SUN4V_CHIP_NIAGARA2:
+                rover_inc_table = niagara_iterate_method;
+                break;
+        default:
+                rover_inc_table = generic_iterate_method;
+        }
+        for (level = t->nodes[root_index].level; level < CPUINFO_LVL_MAX;
+             level++) {
+                new_index = t->nodes[index].rover;
+                if (rover_inc_table[level] & ROVER_INC_ON_VISIT)
+                        increment_rover(t, index, root_index, rover_inc_table);
+                index = new_index;
+        }
+        return index;
+}
+static void _cpu_map_rebuild(void)
+{
+        int i;
+        if (cpuinfo_tree) {
+                kfree(cpuinfo_tree);
+                cpuinfo_tree = NULL;
+        }
+        cpuinfo_tree = build_cpuinfo_tree();
+        if (!cpuinfo_tree)
+                return;
+        /* Build CPU distribution map that spans all online CPUs.  No need
+         * to check if the CPU is online, as that is done when the cpuinfo
+         * tree is being built.
+         */
+        for (i = 0; i < cpuinfo_tree->nodes[0].num_cpus; i++)
+                cpu_distribution_map[i] = iterate_cpu(cpuinfo_tree, 0);
+}
+/* Fallback if the cpuinfo tree could not be built.  CPU mapping is linear
+ * round robin.
+ */
+static int simple_map_to_cpu(unsigned int index)
+{
+        int i, end, cpu_rover;
+        cpu_rover = 0;
+        end = index % num_online_cpus();
+        for (i = 0; i < num_possible_cpus(); i++) {
+                if (cpu_online(cpu_rover)) {
+                        if (cpu_rover >= end)
+                                return cpu_rover;
+                        cpu_rover++;
+                }
+        }
+        /* Impossible, since num_online_cpus() <= num_possible_cpus() */
+        return first_cpu(cpu_online_map);
+}
+static int _map_to_cpu(unsigned int index)
+{
+        struct cpuinfo_node *root_node;
+        if (unlikely(!cpuinfo_tree)) {
+                _cpu_map_rebuild();
+                if (!cpuinfo_tree)
+                        return simple_map_to_cpu(index);
+        }
+        root_node = &cpuinfo_tree->nodes[0];
+#ifdef CONFIG_HOTPLUG_CPU
+        if (unlikely(root_node->num_cpus != num_online_cpus())) {
+                _cpu_map_rebuild();
+                if (!cpuinfo_tree)
+                        return simple_map_to_cpu(index);
+        }
+#endif
+        return cpu_distribution_map[index % root_node->num_cpus];
+}
+int map_to_cpu(unsigned int index)
+{
+        int mapped_cpu;
+        unsigned long flag;
+        spin_lock_irqsave(&cpu_map_lock, flag);
+        mapped_cpu = _map_to_cpu(index);
+#ifdef CONFIG_HOTPLUG_CPU
+        while (unlikely(!cpu_online(mapped_cpu)))
+                mapped_cpu = _map_to_cpu(index);
+#endif
+        spin_unlock_irqrestore(&cpu_map_lock, flag);
+        return mapped_cpu;
+}
+EXPORT_SYMBOL(map_to_cpu);
+void cpu_map_rebuild(void)
+{
+        unsigned long flag;
+        spin_lock_irqsave(&cpu_map_lock, flag);
+        _cpu_map_rebuild();
+        spin_unlock_irqrestore(&cpu_map_lock, flag);
+}
diff --git a/arch/sparc/kernel/cpumap.h b/arch/sparc/kernel/cpumap.h
new file mode 100644
index 000000000000..e639880ab864
--- /dev/null
+++ b/arch/sparc/kernel/cpumap.h
@@ -0,0 +1,16 @@
+#ifndef _CPUMAP_H
+#define _CPUMAP_H
+#ifdef CONFIG_SMP
+extern void cpu_map_rebuild(void);
+extern int  map_to_cpu(unsigned int index);
+#define cpu_map_init() cpu_map_rebuild()
+#else
+#define cpu_map_init() do {} while (0)
+static inline int map_to_cpu(unsigned int index)
+{
+        return raw_smp_processor_id();
+}
+#endif
+#endif
diff --git a/arch/sparc/kernel/dma.c b/arch/sparc/kernel/dma.c
index ebc8403b035e..524c32f97c55 100644
--- a/arch/sparc/kernel/dma.c
+++ b/arch/sparc/kernel/dma.c
@@ -35,8 +35,8 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
 }
 EXPORT_SYMBOL(dma_set_mask);
-void *dma_alloc_coherent(struct device *dev, size_t size,
+static void *dma32_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, gfp_t flag)
+                                  dma_addr_t *dma_handle, gfp_t flag)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type)
@@ -44,10 +44,9 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
 #endif
        return sbus_alloc_consistent(dev, size, dma_handle);
 }
-EXPORT_SYMBOL(dma_alloc_coherent);
-void dma_free_coherent(struct device *dev, size_t size,
+static void dma32_free_coherent(struct device *dev, size_t size,
-                       void *cpu_addr, dma_addr_t dma_handle)
+                                void *cpu_addr, dma_addr_t dma_handle)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type) {
@@ -58,38 +57,10 @@ void dma_free_coherent(struct device *dev, size_t size,
 #endif
        sbus_free_consistent(dev, size, cpu_addr, dma_handle);
 }
-EXPORT_SYMBOL(dma_free_coherent);
-dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+static dma_addr_t dma32_map_page(struct device *dev, struct page *page,
-                          size_t size, enum dma_data_direction direction)
+                                 unsigned long offset, size_t size,
-{
+                                 enum dma_data_direction direction)
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type)
-                return pci_map_single(to_pci_dev(dev), cpu_addr,
-                                      size, (int)direction);
-#endif
-        return sbus_map_single(dev, cpu_addr, size, (int)direction);
-}
-EXPORT_SYMBOL(dma_map_single);
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-                      size_t size,
-                      enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_unmap_single(to_pci_dev(dev), dma_addr,
-                                 size, (int)direction);
-                return;
-        }
-#endif
-        sbus_unmap_single(dev, dma_addr, size, (int)direction);
-}
-EXPORT_SYMBOL(dma_unmap_single);
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                        unsigned long offset, size_t size,
-                        enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type)
@@ -99,10 +70,9 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page,
        return sbus_map_single(dev, page_address(page) + offset,
                               size, (int)direction);
 }
-EXPORT_SYMBOL(dma_map_page);
-void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+static void dma32_unmap_page(struct device *dev, dma_addr_t dma_address,
-                    size_t size, enum dma_data_direction direction)
+                             size_t size, enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type) {
@@ -113,10 +83,9 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
 #endif
        sbus_unmap_single(dev, dma_address, size, (int)direction);
 }
-EXPORT_SYMBOL(dma_unmap_page);
-int dma_map_sg(struct device *dev, struct scatterlist *sg,
+static int dma32_map_sg(struct device *dev, struct scatterlist *sg,
-                             int nents, enum dma_data_direction direction)
+                        int nents, enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type)
@@ -124,10 +93,9 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg,
 #endif
        return sbus_map_sg(dev, sg, nents, direction);
 }
-EXPORT_SYMBOL(dma_map_sg);
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+void dma32_unmap_sg(struct device *dev, struct scatterlist *sg,
-                  int nents, enum dma_data_direction direction)
+                    int nents, enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type) {
@@ -137,10 +105,10 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
 #endif
        sbus_unmap_sg(dev, sg, nents, (int)direction);
 }
-EXPORT_SYMBOL(dma_unmap_sg);
-void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+static void dma32_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-                             size_t size, enum dma_data_direction direction)
+                                      size_t size,
+                                      enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type) {
@@ -151,10 +119,10 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 #endif
        sbus_dma_sync_single_for_cpu(dev, dma_handle, size, (int) direction);
 }
-EXPORT_SYMBOL(dma_sync_single_for_cpu);
-void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
+static void dma32_sync_single_for_device(struct device *dev,
-                                size_t size, enum dma_data_direction direction)
+                                         dma_addr_t dma_handle, size_t size,
+                                         enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type) {
@@ -165,28 +133,9 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
 #endif
        sbus_dma_sync_single_for_device(dev, dma_handle, size, (int) direction);
 }
-EXPORT_SYMBOL(dma_sync_single_for_device);
-void dma_sync_single_range_for_cpu(struct device *dev,
-                                   dma_addr_t dma_handle,
-                                   unsigned long offset,
-                                   size_t size,
-                                   enum dma_data_direction direction)
-{
-        dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
-}
-EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
-void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
-                                      unsigned long offset, size_t size,
-                                      enum dma_data_direction direction)
-{
-        dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
-}
-EXPORT_SYMBOL(dma_sync_single_range_for_device);
-void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+static void dma32_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
-                         int nelems, enum dma_data_direction direction)
+                                  int nelems, enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type) {
@@ -197,11 +146,10 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
 #endif
        BUG();
 }
-EXPORT_SYMBOL(dma_sync_sg_for_cpu);
-void dma_sync_sg_for_device(struct device *dev,
+static void dma32_sync_sg_for_device(struct device *dev,
-                            struct scatterlist *sg, int nelems,
+                                     struct scatterlist *sg, int nelems,
-                            enum dma_data_direction direction)
+                                     enum dma_data_direction direction)
 {
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type) {
@@ -212,16 +160,19 @@ void dma_sync_sg_for_device(struct device *dev,
 #endif
        BUG();
 }
-EXPORT_SYMBOL(dma_sync_sg_for_device);
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+static const struct dma_ops dma32_dma_ops = {
-{
+        .alloc_coherent         = dma32_alloc_coherent,
-        return (dma_addr == DMA_ERROR_CODE);
+        .free_coherent          = dma32_free_coherent,
-}
+        .map_page               = dma32_map_page,
-EXPORT_SYMBOL(dma_mapping_error);
+        .unmap_page             = dma32_unmap_page,
+        .map_sg                 = dma32_map_sg,
-int dma_get_cache_alignment(void)
+        .unmap_sg               = dma32_unmap_sg,
-{
+        .sync_single_for_cpu    = dma32_sync_single_for_cpu,
-        return 32;
+        .sync_single_for_device = dma32_sync_single_for_device,
-}
+        .sync_sg_for_cpu        = dma32_sync_sg_for_cpu,
-EXPORT_SYMBOL(dma_get_cache_alignment);
+        .sync_sg_for_device     = dma32_sync_sg_for_device,
+};
+const struct dma_ops *dma_ops = &dma32_dma_ops;
+EXPORT_SYMBOL(dma_ops);
diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c
index 90350f838f05..4a700f4b79ce 100644
--- a/arch/sparc/kernel/ds.c
+++ b/arch/sparc/kernel/ds.c
@@ -544,7 +544,8 @@ static int __cpuinit dr_cpu_configure(struct ds_info *dp,
                             resp_len, ncpus, mask,
                             DR_CPU_STAT_CONFIGURED);
-        mdesc_fill_in_cpu_data(*mask);
+        mdesc_populate_present_mask(mask);
+        mdesc_fill_in_cpu_data(mask);
        for_each_cpu_mask(cpu, *mask) {
                int err;
diff --git a/arch/sparc/kernel/ftrace.c b/arch/sparc/kernel/ftrace.c
index d0218e73f982..d3b1a3076569 100644
--- a/arch/sparc/kernel/ftrace.c
+++ b/arch/sparc/kernel/ftrace.c
@@ -7,14 +7,10 @@
 #include <asm/ftrace.h>
+#ifdef CONFIG_DYNAMIC_FTRACE
 static const u32 ftrace_nop = 0x01000000;
-unsigned char *ftrace_nop_replace(void)
+static u32 ftrace_call_replace(unsigned long ip, unsigned long addr)
-{
-        return (char *)&ftrace_nop;
-}
-unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
 {
        static u32 call;
        s32 off;
@@ -22,15 +18,11 @@ unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
        off = ((s32)addr - (s32)ip);
        call = 0x40000000 | ((u32)off >> 2);
-        return (unsigned char *) &call;
+        return call;
 }
-int
+static int ftrace_modify_code(unsigned long ip, u32 old, u32 new)
-ftrace_modify_code(unsigned long ip, unsigned char *old_code,
-                   unsigned char *new_code)
 {
-        u32 old = *(u32 *)old_code;
-        u32 new = *(u32 *)new_code;
        u32 replaced;
        int faulted;
@@ -59,18 +51,43 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code,
        return faulted;
 }
+int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned long ip = rec->ip;
+        u32 old, new;
+        old = ftrace_call_replace(ip, addr);
+        new = ftrace_nop;
+        return ftrace_modify_code(ip, old, new);
+}
+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned long ip = rec->ip;
+        u32 old, new;
+        old = ftrace_nop;
+        new = ftrace_call_replace(ip, addr);
+        return ftrace_modify_code(ip, old, new);
+}
 int ftrace_update_ftrace_func(ftrace_func_t func)
 {
        unsigned long ip = (unsigned long)(&ftrace_call);
-        unsigned char old[MCOUNT_INSN_SIZE], *new;
+        u32 old, new;
-        memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE);
+        old = *(u32 *) &ftrace_call;
        new = ftrace_call_replace(ip, (unsigned long)func);
        return ftrace_modify_code(ip, old, new);
 }
 int __init ftrace_dyn_arch_init(void *data)
 {
-        ftrace_mcount_set(data);
+        unsigned long *p = data;
+        *p = 0;
        return 0;
 }
+#endif
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 91bf4c7f79b9..f8f21050448b 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -641,28 +641,6 @@ tlb_fixup_done:
        /* Not reached... */
 1:
-        /* If we boot on a non-zero cpu, all of the per-cpu
-         * variable references we make before setting up the
-         * per-cpu areas will use a bogus offset.  Put a
-         * compensating factor into __per_cpu_base to handle
-         * this cleanly.
-         *
-         * What the per-cpu code calculates is:
-         *
-         *      __per_cpu_base + (cpu << __per_cpu_shift)
-         *
-         * These two variables are zero initially, so to
-         * make it all cancel out to zero we need to put
-         * "0 - (cpu << 0)" into __per_cpu_base so that the
-         * above formula evaluates to zero.
-         *
-         * We cannot even perform a printk() until this stuff
-         * is setup as that calls cpu_clock() which uses
-         * per-cpu variables.
-         */
-        sub     %g0, %o0, %o1
-        sethi   %hi(__per_cpu_base), %o2
-        stx     %o1, [%o2 + %lo(__per_cpu_base)]
 #else
        mov     0, %o0
 #endif
diff --git a/arch/sparc/kernel/init_task.c b/arch/sparc/kernel/init_task.c
index f28cb8278e98..28125c5b3d3c 100644
--- a/arch/sparc/kernel/init_task.c
+++ b/arch/sparc/kernel/init_task.c
@@ -10,10 +10,7 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
 struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_mm);
 EXPORT_SYMBOL(init_task);
 /* .text section in head.S is aligned at 8k boundary and this gets linked
diff --git a/arch/sparc/kernel/iommu.c b/arch/sparc/kernel/iommu.c
index d8900e1d5aad..0aeaefe696b9 100644
--- a/arch/sparc/kernel/iommu.c
+++ b/arch/sparc/kernel/iommu.c
@@ -351,8 +351,9 @@ static void dma_4u_free_coherent(struct device *dev, size_t size,
                free_pages((unsigned long)cpu, order);
 }
-static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz,
+static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page,
-                                    enum dma_data_direction direction)
+                                  unsigned long offset, size_t sz,
+                                  enum dma_data_direction direction)
 {
        struct iommu *iommu;
        struct strbuf *strbuf;
@@ -368,7 +369,7 @@ static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz,
        if (unlikely(direction == DMA_NONE))
                goto bad_no_ctx;
-        oaddr = (unsigned long)ptr;
+        oaddr = (unsigned long)(page_address(page) + offset);
        npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
        npages >>= IO_PAGE_SHIFT;
@@ -472,8 +473,8 @@ do_flush_sync:
                       vaddr, ctx, npages);
 }
-static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr,
+static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
-                                size_t sz, enum dma_data_direction direction)
+                              size_t sz, enum dma_data_direction direction)
 {
        struct iommu *iommu;
        struct strbuf *strbuf;
@@ -824,8 +825,8 @@ static void dma_4u_sync_sg_for_cpu(struct device *dev,
 static const struct dma_ops sun4u_dma_ops = {
        .alloc_coherent         = dma_4u_alloc_coherent,
        .free_coherent          = dma_4u_free_coherent,
-        .map_single             = dma_4u_map_single,
+        .map_page               = dma_4u_map_page,
-        .unmap_single           = dma_4u_unmap_single,
+        .unmap_page             = dma_4u_unmap_page,
        .map_sg                 = dma_4u_map_sg,
        .unmap_sg               = dma_4u_unmap_sg,
        .sync_single_for_cpu    = dma_4u_sync_single_for_cpu,
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c
index e5e78f9cfc95..bd075054942b 100644
--- a/arch/sparc/kernel/irq_64.c
+++ b/arch/sparc/kernel/irq_64.c
@@ -45,6 +45,7 @@
 #include <asm/cacheflush.h>
 #include "entry.h"
+#include "cpumap.h"
 #define NUM_IVECS       (IMAP_INR + 1)
@@ -256,35 +257,13 @@ static int irq_choose_cpu(unsigned int virt_irq)
        int cpuid;
        cpumask_copy(&mask, irq_desc[virt_irq].affinity);
-        if (cpus_equal(mask, CPU_MASK_ALL)) {
+        if (cpus_equal(mask, cpu_online_map)) {
-                static int irq_rover;
+                cpuid = map_to_cpu(virt_irq);
-                static DEFINE_SPINLOCK(irq_rover_lock);
-                unsigned long flags;
-                /* Round-robin distribution... */
-        do_round_robin:
-                spin_lock_irqsave(&irq_rover_lock, flags);
-                while (!cpu_online(irq_rover)) {
-                        if (++irq_rover >= nr_cpu_ids)
-                                irq_rover = 0;
-                }
-                cpuid = irq_rover;
-                do {
-                        if (++irq_rover >= nr_cpu_ids)
-                                irq_rover = 0;
-                } while (!cpu_online(irq_rover));
-                spin_unlock_irqrestore(&irq_rover_lock, flags);
        } else {
                cpumask_t tmp;
                cpus_and(tmp, cpu_online_map, mask);
+                cpuid = cpus_empty(tmp) ? map_to_cpu(virt_irq) : first_cpu(tmp);
-                if (cpus_empty(tmp))
-                        goto do_round_robin;
-                cpuid = first_cpu(tmp);
        }
        return cpuid;
diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c
index f0e6ed23a468..938da19dc065 100644
--- a/arch/sparc/kernel/mdesc.c
+++ b/arch/sparc/kernel/mdesc.c
@@ -574,7 +574,7 @@ static void __init report_platform_properties(void)
        mdesc_release(hp);
 }
-static void __devinit fill_in_one_cache(cpuinfo_sparc *c,
+static void __cpuinit fill_in_one_cache(cpuinfo_sparc *c,
                                        struct mdesc_handle *hp,
                                        u64 mp)
 {
@@ -619,8 +619,7 @@ static void __devinit fill_in_one_cache(cpuinfo_sparc *c,
        }
 }
-static void __devinit mark_core_ids(struct mdesc_handle *hp, u64 mp,
+static void __cpuinit mark_core_ids(struct mdesc_handle *hp, u64 mp, int core_id)
-                                    int core_id)
 {
        u64 a;
@@ -653,7 +652,7 @@ static void __devinit mark_core_ids(struct mdesc_handle *hp, u64 mp,
        }
 }
-static void __devinit set_core_ids(struct mdesc_handle *hp)
+static void __cpuinit set_core_ids(struct mdesc_handle *hp)
 {
        int idx;
        u64 mp;
@@ -678,8 +677,7 @@ static void __devinit set_core_ids(struct mdesc_handle *hp)
        }
 }
-static void __devinit mark_proc_ids(struct mdesc_handle *hp, u64 mp,
+static void __cpuinit mark_proc_ids(struct mdesc_handle *hp, u64 mp, int proc_id)
-                                    int proc_id)
 {
        u64 a;
@@ -698,8 +696,7 @@ static void __devinit mark_proc_ids(struct mdesc_handle *hp, u64 mp,
        }
 }
-static void __devinit __set_proc_ids(struct mdesc_handle *hp,
+static void __cpuinit __set_proc_ids(struct mdesc_handle *hp, const char *exec_unit_name)
-                                     const char *exec_unit_name)
 {
        int idx;
        u64 mp;
@@ -720,13 +717,13 @@ static void __devinit __set_proc_ids(struct mdesc_handle *hp,
        }
 }
-static void __devinit set_proc_ids(struct mdesc_handle *hp)
+static void __cpuinit set_proc_ids(struct mdesc_handle *hp)
 {
        __set_proc_ids(hp, "exec_unit");
        __set_proc_ids(hp, "exec-unit");
 }
-static void __devinit get_one_mondo_bits(const u64 *p, unsigned int *mask,
+static void __cpuinit get_one_mondo_bits(const u64 *p, unsigned int *mask,
                                         unsigned char def)
 {
        u64 val;
@@ -745,7 +742,7 @@ use_default:
        *mask = ((1U << def) * 64U) - 1U;
 }
-static void __devinit get_mondo_data(struct mdesc_handle *hp, u64 mp,
+static void __cpuinit get_mondo_data(struct mdesc_handle *hp, u64 mp,
                                     struct trap_per_cpu *tb)
 {
        const u64 *val;
@@ -763,23 +760,15 @@ static void __devinit get_mondo_data(struct mdesc_handle *hp, u64 mp,
        get_one_mondo_bits(val, &tb->nonresum_qmask, 2);
 }
-void __cpuinit mdesc_fill_in_cpu_data(cpumask_t mask)
+static void * __cpuinit mdesc_iterate_over_cpus(void *(*func)(struct mdesc_handle *, u64, int, void *), void *arg, cpumask_t *mask)
 {
        struct mdesc_handle *hp = mdesc_grab();
+        void *ret = NULL;
        u64 mp;
-        ncpus_probed = 0;
        mdesc_for_each_node_by_name(hp, mp, "cpu") {
                const u64 *id = mdesc_get_property(hp, mp, "id", NULL);
-                const u64 *cfreq = mdesc_get_property(hp, mp, "clock-frequency", NULL);
+                int cpuid = *id;
-                struct trap_per_cpu *tb;
-                cpuinfo_sparc *c;
-                int cpuid;
-                u64 a;
-                ncpus_probed++;
-                cpuid = *id;
 #ifdef CONFIG_SMP
                if (cpuid >= NR_CPUS) {
@@ -788,62 +777,104 @@ void __cpuinit mdesc_fill_in_cpu_data(cpumask_t mask)
                               cpuid, NR_CPUS);
                        continue;
                }
-                if (!cpu_isset(cpuid, mask))
+                if (!cpu_isset(cpuid, *mask))
                        continue;
-#else
-                /* On uniprocessor we only want the values for the
-                 * real physical cpu the kernel booted onto, however
-                 * cpu_data() only has one entry at index 0.
-                 */
-                if (cpuid != real_hard_smp_processor_id())
-                        continue;
-                cpuid = 0;
 #endif
-                c = &cpu_data(cpuid);
+                ret = func(hp, mp, cpuid, arg);
-                c->clock_tick = *cfreq;
+                if (ret)
+                        goto out;
+        }
+out:
+        mdesc_release(hp);
+        return ret;
+}
-                tb = &trap_block[cpuid];
+static void * __cpuinit record_one_cpu(struct mdesc_handle *hp, u64 mp, int cpuid, void *arg)
-                get_mondo_data(hp, mp, tb);
+{
+        ncpus_probed++;
+#ifdef CONFIG_SMP
+        set_cpu_present(cpuid, true);
+#endif
+        return NULL;
+}
-                mdesc_for_each_arc(a, hp, mp, MDESC_ARC_TYPE_FWD) {
+void __cpuinit mdesc_populate_present_mask(cpumask_t *mask)
-                        u64 j, t = mdesc_arc_target(hp, a);
+{
-                        const char *t_name;
+        if (tlb_type != hypervisor)
+                return;
-                        t_name = mdesc_node_name(hp, t);
+        ncpus_probed = 0;
-                        if (!strcmp(t_name, "cache")) {
+        mdesc_iterate_over_cpus(record_one_cpu, NULL, mask);
-                                fill_in_one_cache(c, hp, t);
+}
-                                continue;
-                        }
-                        mdesc_for_each_arc(j, hp, t, MDESC_ARC_TYPE_FWD) {
+static void * __cpuinit fill_in_one_cpu(struct mdesc_handle *hp, u64 mp, int cpuid, void *arg)
-                                u64 n = mdesc_arc_target(hp, j);
+{
-                                const char *n_name;
+        const u64 *cfreq = mdesc_get_property(hp, mp, "clock-frequency", NULL);
+        struct trap_per_cpu *tb;
+        cpuinfo_sparc *c;
+        u64 a;
-                                n_name = mdesc_node_name(hp, n);
+#ifndef CONFIG_SMP
-                                if (!strcmp(n_name, "cache"))
+        /* On uniprocessor we only want the values for the
-                                        fill_in_one_cache(c, hp, n);
+         * real physical cpu the kernel booted onto, however
-                        }
+         * cpu_data() only has one entry at index 0.
+         */
+        if (cpuid != real_hard_smp_processor_id())
+                return NULL;
+        cpuid = 0;
+#endif
+        c = &cpu_data(cpuid);
+        c->clock_tick = *cfreq;
+        tb = &trap_block[cpuid];
+        get_mondo_data(hp, mp, tb);
+        mdesc_for_each_arc(a, hp, mp, MDESC_ARC_TYPE_FWD) {
+                u64 j, t = mdesc_arc_target(hp, a);
+                const char *t_name;
+                t_name = mdesc_node_name(hp, t);
+                if (!strcmp(t_name, "cache")) {
+                        fill_in_one_cache(c, hp, t);
+                        continue;
                }
-#ifdef CONFIG_SMP
+                mdesc_for_each_arc(j, hp, t, MDESC_ARC_TYPE_FWD) {
-                cpu_set(cpuid, cpu_present_map);
+                        u64 n = mdesc_arc_target(hp, j);
-#endif
+                        const char *n_name;
-                c->core_id = 0;
+                        n_name = mdesc_node_name(hp, n);
-                c->proc_id = -1;
+                        if (!strcmp(n_name, "cache"))
+                                fill_in_one_cache(c, hp, n);
+                }
        }
+        c->core_id = 0;
+        c->proc_id = -1;
+        return NULL;
+}
+void __cpuinit mdesc_fill_in_cpu_data(cpumask_t *mask)
+{
+        struct mdesc_handle *hp;
+        mdesc_iterate_over_cpus(fill_in_one_cpu, NULL, mask);
 #ifdef CONFIG_SMP
        sparc64_multi_core = 1;
 #endif
+        hp = mdesc_grab();
        set_core_ids(hp);
        set_proc_ids(hp);
-        smp_fill_in_sib_core_maps();
        mdesc_release(hp);
+        smp_fill_in_sib_core_maps();
 }
 static ssize_t mdesc_read(struct file *file, char __user *buf,
@@ -887,7 +918,6 @@ void __init sun4v_mdesc_init(void)
 {
        struct mdesc_handle *hp;
        unsigned long len, real_len, status;
-        cpumask_t mask;
        (void) sun4v_mach_desc(0UL, 0UL, &len);
@@ -911,7 +941,4 @@ void __init sun4v_mdesc_init(void)
        cur_mdesc = hp;
        report_platform_properties();
-        cpus_setall(mask);
-        mdesc_fill_in_cpu_data(mask);
 }
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index c8f14c1dc521..90396702ea2c 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -6,159 +6,11 @@
 #include <linux/mod_devicetable.h>
 #include <linux/slab.h>
 #include <linux/errno.h>
+#include <linux/irq.h>
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
-static int node_match(struct device *dev, void *data)
+#include "of_device_common.h"
-{
-        struct of_device *op = to_of_device(dev);
-        struct device_node *dp = data;
-        return (op->node == dp);
-}
-struct of_device *of_find_device_by_node(struct device_node *dp)
-{
-        struct device *dev = bus_find_device(&of_platform_bus_type, NULL,
-                                             dp, node_match);
-        if (dev)
-                return to_of_device(dev);
-        return NULL;
-}
-EXPORT_SYMBOL(of_find_device_by_node);
-unsigned int irq_of_parse_and_map(struct device_node *node, int index)
-{
-        struct of_device *op = of_find_device_by_node(node);
-        if (!op || index >= op->num_irqs)
-                return 0;
-        return op->irqs[index];
-}
-EXPORT_SYMBOL(irq_of_parse_and_map);
-/* Take the archdata values for IOMMU, STC, and HOSTDATA found in
- * BUS and propagate to all child of_device objects.
- */
-void of_propagate_archdata(struct of_device *bus)
-{
-        struct dev_archdata *bus_sd = &bus->dev.archdata;
-        struct device_node *bus_dp = bus->node;
-        struct device_node *dp;
-        for (dp = bus_dp->child; dp; dp = dp->sibling) {
-                struct of_device *op = of_find_device_by_node(dp);
-                op->dev.archdata.iommu = bus_sd->iommu;
-                op->dev.archdata.stc = bus_sd->stc;
-                op->dev.archdata.host_controller = bus_sd->host_controller;
-                op->dev.archdata.numa_node = bus_sd->numa_node;
-                if (dp->child)
-                        of_propagate_archdata(op);
-        }
-}
-struct bus_type of_platform_bus_type;
-EXPORT_SYMBOL(of_platform_bus_type);
-static inline u64 of_read_addr(const u32 *cell, int size)
-{
-        u64 r = 0;
-        while (size--)
-                r = (r << 32) | *(cell++);
-        return r;
-}
-static void __init get_cells(struct device_node *dp,
-                             int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = of_n_addr_cells(dp);
-        if (sizec)
-                *sizec = of_n_size_cells(dp);
-}
-/* Max address size we deal with */
-#define OF_MAX_ADDR_CELLS       4
-struct of_bus {
-        const char      *name;
-        const char      *addr_prop_name;
-        int             (*match)(struct device_node *parent);
-        void            (*count_cells)(struct device_node *child,
-                                       int *addrc, int *sizec);
-        int             (*map)(u32 *addr, const u32 *range,
-                               int na, int ns, int pna);
-        unsigned long   (*get_flags)(const u32 *addr, unsigned long);
-};
-/*
- * Default translator (generic bus)
- */
-static void of_bus_default_count_cells(struct device_node *dev,
-                                       int *addrc, int *sizec)
-{
-        get_cells(dev, addrc, sizec);
-}
-/* Make sure the least significant 64-bits are in-range.  Even
- * for 3 or 4 cell values it is a good enough approximation.
- */
-static int of_out_of_range(const u32 *addr, const u32 *base,
-                           const u32 *size, int na, int ns)
-{
-        u64 a = of_read_addr(addr, na);
-        u64 b = of_read_addr(base, na);
-        if (a < b)
-                return 1;
-        b += of_read_addr(size, ns);
-        if (a >= b)
-                return 1;
-        return 0;
-}
-static int of_bus_default_map(u32 *addr, const u32 *range,
-                              int na, int ns, int pna)
-{
-        u32 result[OF_MAX_ADDR_CELLS];
-        int i;
-        if (ns > 2) {
-                printk("of_device: Cannot handle size cells (%d) > 2.", ns);
-                return -EINVAL;
-        }
-        if (of_out_of_range(addr, range, range + na + pna, na, ns))
-                return -EINVAL;
-        /* Start with the parent range base.  */
-        memcpy(result, range + na, pna * 4);
-        /* Add in the child address offset.  */
-        for (i = 0; i < na; i++)
-                result[pna - 1 - i] +=
-                        (addr[na - 1 - i] -
-                         range[na - 1 - i]);
-        memcpy(addr, result, pna * 4);
-        return 0;
-}
-static unsigned long of_bus_default_get_flags(const u32 *addr, unsigned long flags)
-{
-        if (flags)
-                return flags;
-        return IORESOURCE_MEM;
-}
 /*
 * PCI bus specific translator
@@ -240,47 +92,6 @@ static unsigned long of_bus_pci_get_flags(const u32 *addr, unsigned long flags)
        return flags;
 }
-/*
- * SBUS bus specific translator
- */
-static int of_bus_sbus_match(struct device_node *np)
-{
-        struct device_node *dp = np;
-        while (dp) {
-                if (!strcmp(dp->name, "sbus") ||
-                    !strcmp(dp->name, "sbi"))
-                        return 1;
-                /* Have a look at use_1to1_mapping().  We're trying
-                 * to match SBUS if that's the top-level bus and we
-                 * don't have some intervening real bus that provides
-                 * ranges based translations.
-                 */
-                if (of_find_property(dp, "ranges", NULL) != NULL)
-                        break;
-                dp = dp->parent;
-        }
-        return 0;
-}
-static void of_bus_sbus_count_cells(struct device_node *child,
-                                   int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = 2;
-        if (sizec)
-                *sizec = 1;
-}
-static int of_bus_sbus_map(u32 *addr, const u32 *range, int na, int ns, int pna)
-{
-        return of_bus_default_map(addr, range, na, ns, pna);
-}
 static unsigned long of_bus_sbus_get_flags(const u32 *addr, unsigned long flags)
 {
        return IORESOURCE_MEM;
@@ -307,7 +118,7 @@ static struct of_bus of_busses[] = {
                .addr_prop_name = "reg",
                .match = of_bus_sbus_match,
                .count_cells = of_bus_sbus_count_cells,
-                .map = of_bus_sbus_map,
+                .map = of_bus_default_map,
                .get_flags = of_bus_sbus_get_flags,
        },
        /* Default */
diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c
index 5ac287ac03de..881947e59e95 100644
--- a/arch/sparc/kernel/of_device_64.c
+++ b/arch/sparc/kernel/of_device_64.c
@@ -10,6 +10,8 @@
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
+#include "of_device_common.h"
 void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name)
 {
        unsigned long ret = res->start + offset;
@@ -35,156 +37,6 @@ void of_iounmap(struct resource *res, void __iomem *base, unsigned long size)
 }
 EXPORT_SYMBOL(of_iounmap);
-static int node_match(struct device *dev, void *data)
-{
-        struct of_device *op = to_of_device(dev);
-        struct device_node *dp = data;
-        return (op->node == dp);
-}
-struct of_device *of_find_device_by_node(struct device_node *dp)
-{
-        struct device *dev = bus_find_device(&of_platform_bus_type, NULL,
-                                             dp, node_match);
-        if (dev)
-                return to_of_device(dev);
-        return NULL;
-}
-EXPORT_SYMBOL(of_find_device_by_node);
-unsigned int irq_of_parse_and_map(struct device_node *node, int index)
-{
-        struct of_device *op = of_find_device_by_node(node);
-        if (!op || index >= op->num_irqs)
-                return 0;
-        return op->irqs[index];
-}
-EXPORT_SYMBOL(irq_of_parse_and_map);
-/* Take the archdata values for IOMMU, STC, and HOSTDATA found in
- * BUS and propagate to all child of_device objects.
- */
-void of_propagate_archdata(struct of_device *bus)
-{
-        struct dev_archdata *bus_sd = &bus->dev.archdata;
-        struct device_node *bus_dp = bus->node;
-        struct device_node *dp;
-        for (dp = bus_dp->child; dp; dp = dp->sibling) {
-                struct of_device *op = of_find_device_by_node(dp);
-                op->dev.archdata.iommu = bus_sd->iommu;
-                op->dev.archdata.stc = bus_sd->stc;
-                op->dev.archdata.host_controller = bus_sd->host_controller;
-                op->dev.archdata.numa_node = bus_sd->numa_node;
-                if (dp->child)
-                        of_propagate_archdata(op);
-        }
-}
-struct bus_type of_platform_bus_type;
-EXPORT_SYMBOL(of_platform_bus_type);
-static inline u64 of_read_addr(const u32 *cell, int size)
-{
-        u64 r = 0;
-        while (size--)
-                r = (r << 32) | *(cell++);
-        return r;
-}
-static void get_cells(struct device_node *dp, int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = of_n_addr_cells(dp);
-        if (sizec)
-                *sizec = of_n_size_cells(dp);
-}
-/* Max address size we deal with */
-#define OF_MAX_ADDR_CELLS       4
-struct of_bus {
-        const char      *name;
-        const char      *addr_prop_name;
-        int             (*match)(struct device_node *parent);
-        void            (*count_cells)(struct device_node *child,
-                                       int *addrc, int *sizec);
-        int             (*map)(u32 *addr, const u32 *range,
-                               int na, int ns, int pna);
-        unsigned long   (*get_flags)(const u32 *addr, unsigned long);
-};
-/*
- * Default translator (generic bus)
- */
-static void of_bus_default_count_cells(struct device_node *dev,
-                                       int *addrc, int *sizec)
-{
-        get_cells(dev, addrc, sizec);
-}
-/* Make sure the least significant 64-bits are in-range.  Even
- * for 3 or 4 cell values it is a good enough approximation.
- */
-static int of_out_of_range(const u32 *addr, const u32 *base,
-                           const u32 *size, int na, int ns)
-{
-        u64 a = of_read_addr(addr, na);
-        u64 b = of_read_addr(base, na);
-        if (a < b)
-                return 1;
-        b += of_read_addr(size, ns);
-        if (a >= b)
-                return 1;
-        return 0;
-}
-static int of_bus_default_map(u32 *addr, const u32 *range,
-                              int na, int ns, int pna)
-{
-        u32 result[OF_MAX_ADDR_CELLS];
-        int i;
-        if (ns > 2) {
-                printk("of_device: Cannot handle size cells (%d) > 2.", ns);
-                return -EINVAL;
-        }
-        if (of_out_of_range(addr, range, range + na + pna, na, ns))
-                return -EINVAL;
-        /* Start with the parent range base.  */
-        memcpy(result, range + na, pna * 4);
-        /* Add in the child address offset.  */
-        for (i = 0; i < na; i++)
-                result[pna - 1 - i] +=
-                        (addr[na - 1 - i] -
-                         range[na - 1 - i]);
-        memcpy(addr, result, pna * 4);
-        return 0;
-}
-static unsigned long of_bus_default_get_flags(const u32 *addr, unsigned long flags)
-{
-        if (flags)
-                return flags;
-        return IORESOURCE_MEM;
-}
 /*
 * PCI bus specific translator
 */
@@ -295,42 +147,6 @@ static unsigned long of_bus_pci_get_flags(const u32 *addr, unsigned long flags)
 }
 /*
- * SBUS bus specific translator
- */
-static int of_bus_sbus_match(struct device_node *np)
-{
-        struct device_node *dp = np;
-        while (dp) {
-                if (!strcmp(dp->name, "sbus") ||
-                    !strcmp(dp->name, "sbi"))
-                        return 1;
-                /* Have a look at use_1to1_mapping().  We're trying
-                 * to match SBUS if that's the top-level bus and we
-                 * don't have some intervening real bus that provides
-                 * ranges based translations.
-                 */
-                if (of_find_property(dp, "ranges", NULL) != NULL)
-                        break;
-                dp = dp->parent;
-        }
-        return 0;
-}
-static void of_bus_sbus_count_cells(struct device_node *child,
-                                   int *addrc, int *sizec)
-{
-        if (addrc)
-                *addrc = 2;
-        if (sizec)
-                *sizec = 1;
-}
-/*
 * FHC/Central bus specific translator.
 *
 * This is just needed to hard-code the address and size cell
diff --git a/arch/sparc/kernel/of_device_common.c b/arch/sparc/kernel/of_device_common.c
new file mode 100644
index 000000000000..cb8eb799bb6c
--- /dev/null
+++ b/arch/sparc/kernel/of_device_common.c
@@ -0,0 +1,174 @@
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/irq.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include "of_device_common.h"
+static int node_match(struct device *dev, void *data)
+{
+        struct of_device *op = to_of_device(dev);
+        struct device_node *dp = data;
+        return (op->node == dp);
+}
+struct of_device *of_find_device_by_node(struct device_node *dp)
+{
+        struct device *dev = bus_find_device(&of_platform_bus_type, NULL,
+                                             dp, node_match);
+        if (dev)
+                return to_of_device(dev);
+        return NULL;
+}
+EXPORT_SYMBOL(of_find_device_by_node);
+unsigned int irq_of_parse_and_map(struct device_node *node, int index)
+{
+        struct of_device *op = of_find_device_by_node(node);
+        if (!op || index >= op->num_irqs)
+                return 0;
+        return op->irqs[index];
+}
+EXPORT_SYMBOL(irq_of_parse_and_map);
+/* Take the archdata values for IOMMU, STC, and HOSTDATA found in
+ * BUS and propagate to all child of_device objects.
+ */
+void of_propagate_archdata(struct of_device *bus)
+{
+        struct dev_archdata *bus_sd = &bus->dev.archdata;
+        struct device_node *bus_dp = bus->node;
+        struct device_node *dp;
+        for (dp = bus_dp->child; dp; dp = dp->sibling) {
+                struct of_device *op = of_find_device_by_node(dp);
+                op->dev.archdata.iommu = bus_sd->iommu;
+                op->dev.archdata.stc = bus_sd->stc;
+                op->dev.archdata.host_controller = bus_sd->host_controller;
+                op->dev.archdata.numa_node = bus_sd->numa_node;
+                if (dp->child)
+                        of_propagate_archdata(op);
+        }
+}
+struct bus_type of_platform_bus_type;
+EXPORT_SYMBOL(of_platform_bus_type);
+static void get_cells(struct device_node *dp, int *addrc, int *sizec)
+{
+        if (addrc)
+                *addrc = of_n_addr_cells(dp);
+        if (sizec)
+                *sizec = of_n_size_cells(dp);
+}
+/*
+ * Default translator (generic bus)
+ */
+void of_bus_default_count_cells(struct device_node *dev, int *addrc, int *sizec)
+{
+        get_cells(dev, addrc, sizec);
+}
+/* Make sure the least significant 64-bits are in-range.  Even
+ * for 3 or 4 cell values it is a good enough approximation.
+ */
+int of_out_of_range(const u32 *addr, const u32 *base,
+                    const u32 *size, int na, int ns)
+{
+        u64 a = of_read_addr(addr, na);
+        u64 b = of_read_addr(base, na);
+        if (a < b)
+                return 1;
+        b += of_read_addr(size, ns);
+        if (a >= b)
+                return 1;
+        return 0;
+}
+int of_bus_default_map(u32 *addr, const u32 *range, int na, int ns, int pna)
+{
+        u32 result[OF_MAX_ADDR_CELLS];
+        int i;
+        if (ns > 2) {
+                printk("of_device: Cannot handle size cells (%d) > 2.", ns);
+                return -EINVAL;
+        }
+        if (of_out_of_range(addr, range, range + na + pna, na, ns))
+                return -EINVAL;
+        /* Start with the parent range base.  */
+        memcpy(result, range + na, pna * 4);
+        /* Add in the child address offset.  */
+        for (i = 0; i < na; i++)
+                result[pna - 1 - i] +=
+                        (addr[na - 1 - i] -
+                         range[na - 1 - i]);
+        memcpy(addr, result, pna * 4);
+        return 0;
+}
+unsigned long of_bus_default_get_flags(const u32 *addr, unsigned long flags)
+{
+        if (flags)
+                return flags;
+        return IORESOURCE_MEM;
+}
+/*
+ * SBUS bus specific translator
+ */
+int of_bus_sbus_match(struct device_node *np)
+{
+        struct device_node *dp = np;
+        while (dp) {
+                if (!strcmp(dp->name, "sbus") ||
+                    !strcmp(dp->name, "sbi"))
+                        return 1;
+                /* Have a look at use_1to1_mapping().  We're trying
+                 * to match SBUS if that's the top-level bus and we
+                 * don't have some intervening real bus that provides
+                 * ranges based translations.
+                 */
+                if (of_find_property(dp, "ranges", NULL) != NULL)
+                        break;
+                dp = dp->parent;
+        }
+        return 0;
+}
+void of_bus_sbus_count_cells(struct device_node *child, int *addrc, int *sizec)
+{
+        if (addrc)
+                *addrc = 2;
+        if (sizec)
+                *sizec = 1;
+}
diff --git a/arch/sparc/kernel/of_device_common.h b/arch/sparc/kernel/of_device_common.h
new file mode 100644
index 000000000000..cdfd23992841
--- /dev/null
+++ b/arch/sparc/kernel/of_device_common.h
@@ -0,0 +1,36 @@
+#ifndef _OF_DEVICE_COMMON_H
+#define _OF_DEVICE_COMMON_H
+static inline u64 of_read_addr(const u32 *cell, int size)
+{
+        u64 r = 0;
+        while (size--)
+                r = (r << 32) | *(cell++);
+        return r;
+}
+void of_bus_default_count_cells(struct device_node *dev, int *addrc,
+                                int *sizec);
+int of_out_of_range(const u32 *addr, const u32 *base,
+                    const u32 *size, int na, int ns);
+int of_bus_default_map(u32 *addr, const u32 *range, int na, int ns, int pna);
+unsigned long of_bus_default_get_flags(const u32 *addr, unsigned long flags);
+int of_bus_sbus_match(struct device_node *np);
+void of_bus_sbus_count_cells(struct device_node *child, int *addrc, int *sizec);
+/* Max address size we deal with */
+#define OF_MAX_ADDR_CELLS       4
+struct of_bus {
+        const char      *name;
+        const char      *addr_prop_name;
+        int             (*match)(struct device_node *parent);
+        void            (*count_cells)(struct device_node *child,
+                                       int *addrc, int *sizec);
+        int             (*map)(u32 *addr, const u32 *range,
+                               int na, int ns, int pna);
+        unsigned long   (*get_flags)(const u32 *addr, unsigned long);
+};
+#endif /* _OF_DEVICE_COMMON_H */
diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c
index 5db5ebed35da..2485eaa23101 100644
--- a/arch/sparc/kernel/pci_sun4v.c
+++ b/arch/sparc/kernel/pci_sun4v.c
@@ -230,8 +230,9 @@ static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
                free_pages((unsigned long)cpu, order);
 }
-static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz,
+static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
-                                    enum dma_data_direction direction)
+                                  unsigned long offset, size_t sz,
+                                  enum dma_data_direction direction)
 {
        struct iommu *iommu;
        unsigned long flags, npages, oaddr;
@@ -245,7 +246,7 @@ static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz,
        if (unlikely(direction == DMA_NONE))
                goto bad;
-        oaddr = (unsigned long)ptr;
+        oaddr = (unsigned long)(page_address(page) + offset);
        npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
        npages >>= IO_PAGE_SHIFT;
@@ -294,8 +295,8 @@ iommu_map_fail:
        return DMA_ERROR_CODE;
 }
-static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr,
+static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
-                                size_t sz, enum dma_data_direction direction)
+                              size_t sz, enum dma_data_direction direction)
 {
        struct pci_pbm_info *pbm;
        struct iommu *iommu;
@@ -537,8 +538,8 @@ static void dma_4v_sync_sg_for_cpu(struct device *dev,
 static const struct dma_ops sun4v_dma_ops = {
        .alloc_coherent                 = dma_4v_alloc_coherent,
        .free_coherent                  = dma_4v_free_coherent,
-        .map_single                     = dma_4v_map_single,
+        .map_page                       = dma_4v_map_page,
-        .unmap_single                   = dma_4v_unmap_single,
+        .unmap_page                     = dma_4v_unmap_page,
        .map_sg                         = dma_4v_map_sg,
        .unmap_sg                       = dma_4v_unmap_sg,
        .sync_single_for_cpu            = dma_4v_sync_single_for_cpu,
diff --git a/arch/sparc/kernel/prom.h b/arch/sparc/kernel/prom.h
index bb0f0fda6cab..453397fe5e14 100644
--- a/arch/sparc/kernel/prom.h
+++ b/arch/sparc/kernel/prom.h
@@ -22,7 +22,6 @@ static inline int is_root_node(const struct device_node *dp)
 extern char *build_path_component(struct device_node *dp);
 extern void of_console_init(void);
-extern void of_fill_in_cpu_data(void);
 extern unsigned int prom_early_allocated;
diff --git a/arch/sparc/kernel/prom_64.c b/arch/sparc/kernel/prom_64.c
index ca55c7012f77..fb06ac2bd38f 100644
--- a/arch/sparc/kernel/prom_64.c
+++ b/arch/sparc/kernel/prom_64.c
@@ -374,75 +374,26 @@ static const char *get_mid_prop(void)
        return (tlb_type == spitfire ? "upa-portid" : "portid");
 }
-struct device_node *of_find_node_by_cpuid(int cpuid)
+static void *of_iterate_over_cpus(void *(*func)(struct device_node *, int, int), int arg)
-{
-        struct device_node *dp;
-        const char *mid_prop = get_mid_prop();
-        for_each_node_by_type(dp, "cpu") {
-                int id = of_getintprop_default(dp, mid_prop, -1);
-                const char *this_mid_prop = mid_prop;
-                if (id < 0) {
-                        this_mid_prop = "cpuid";
-                        id = of_getintprop_default(dp, this_mid_prop, -1);
-                }
-                if (id < 0) {
-                        prom_printf("OF: Serious problem, cpu lacks "
-                                    "%s property", this_mid_prop);
-                        prom_halt();
-                }
-                if (cpuid == id)
-                        return dp;
-        }
-        return NULL;
-}
-void __init of_fill_in_cpu_data(void)
 {
        struct device_node *dp;
        const char *mid_prop;
-        if (tlb_type == hypervisor)
-                return;
        mid_prop = get_mid_prop();
-        ncpus_probed = 0;
        for_each_node_by_type(dp, "cpu") {
                int cpuid = of_getintprop_default(dp, mid_prop, -1);
                const char *this_mid_prop = mid_prop;
-                struct device_node *portid_parent;
+                void *ret;
-                int portid = -1;
-                portid_parent = NULL;
                if (cpuid < 0) {
                        this_mid_prop = "cpuid";
                        cpuid = of_getintprop_default(dp, this_mid_prop, -1);
-                        if (cpuid >= 0) {
-                                int limit = 2;
-                                portid_parent = dp;
-                                while (limit--) {
-                                        portid_parent = portid_parent->parent;
-                                        if (!portid_parent)
-                                                break;
-                                        portid = of_getintprop_default(portid_parent,
-                                                                       "portid", -1);
-                                        if (portid >= 0)
-                                                break;
-                                }
-                        }
                }
                if (cpuid < 0) {
                        prom_printf("OF: Serious problem, cpu lacks "
                                    "%s property", this_mid_prop);
                        prom_halt();
                }
-                ncpus_probed++;
 #ifdef CONFIG_SMP
                if (cpuid >= NR_CPUS) {
                        printk(KERN_WARNING "Ignoring CPU %d which is "
@@ -450,79 +401,142 @@ void __init of_fill_in_cpu_data(void)
                               cpuid, NR_CPUS);
                        continue;
                }
-#else
-                /* On uniprocessor we only want the values for the
-                 * real physical cpu the kernel booted onto, however
-                 * cpu_data() only has one entry at index 0.
-                 */
-                if (cpuid != real_hard_smp_processor_id())
-                        continue;
-                cpuid = 0;
 #endif
+                ret = func(dp, cpuid, arg);
+                if (ret)
+                        return ret;
+        }
+        return NULL;
+}
-                cpu_data(cpuid).clock_tick =
+static void *check_cpu_node(struct device_node *dp, int cpuid, int id)
-                        of_getintprop_default(dp, "clock-frequency", 0);
+{
+        if (id == cpuid)
-                if (portid_parent) {
+                return dp;
-                        cpu_data(cpuid).dcache_size =
+        return NULL;
-                                of_getintprop_default(dp, "l1-dcache-size",
+}
-                                                      16 * 1024);
-                        cpu_data(cpuid).dcache_line_size =
+struct device_node *of_find_node_by_cpuid(int cpuid)
-                                of_getintprop_default(dp, "l1-dcache-line-size",
+{
-                                                      32);
+        return of_iterate_over_cpus(check_cpu_node, cpuid);
-                        cpu_data(cpuid).icache_size =
+}
-                                of_getintprop_default(dp, "l1-icache-size",
-                                                      8 * 1024);
+static void *record_one_cpu(struct device_node *dp, int cpuid, int arg)
-                        cpu_data(cpuid).icache_line_size =
+{
-                                of_getintprop_default(dp, "l1-icache-line-size",
+        ncpus_probed++;
-                                                      32);
-                        cpu_data(cpuid).ecache_size =
-                                of_getintprop_default(dp, "l2-cache-size", 0);
-                        cpu_data(cpuid).ecache_line_size =
-                                of_getintprop_default(dp, "l2-cache-line-size", 0);
-                        if (!cpu_data(cpuid).ecache_size ||
-                            !cpu_data(cpuid).ecache_line_size) {
-                                cpu_data(cpuid).ecache_size =
-                                        of_getintprop_default(portid_parent,
-                                                              "l2-cache-size",
-                                                              (4 * 1024 * 1024));
-                                cpu_data(cpuid).ecache_line_size =
-                                        of_getintprop_default(portid_parent,
-                                                              "l2-cache-line-size", 64);
-                        }
-                        cpu_data(cpuid).core_id = portid + 1;
-                        cpu_data(cpuid).proc_id = portid;
 #ifdef CONFIG_SMP
-                        sparc64_multi_core = 1;
+        set_cpu_present(cpuid, true);
+        set_cpu_possible(cpuid, true);
 #endif
-                } else {
+        return NULL;
-                        cpu_data(cpuid).dcache_size =
+}
-                                of_getintprop_default(dp, "dcache-size", 16 * 1024);
-                        cpu_data(cpuid).dcache_line_size =
-                                of_getintprop_default(dp, "dcache-line-size", 32);
-                        cpu_data(cpuid).icache_size =
+void __init of_populate_present_mask(void)
-                                of_getintprop_default(dp, "icache-size", 16 * 1024);
+{
-                        cpu_data(cpuid).icache_line_size =
+        if (tlb_type == hypervisor)
-                                of_getintprop_default(dp, "icache-line-size", 32);
+                return;
+        ncpus_probed = 0;
+        of_iterate_over_cpus(record_one_cpu, 0);
+}
+static void *fill_in_one_cpu(struct device_node *dp, int cpuid, int arg)
+{
+        struct device_node *portid_parent = NULL;
+        int portid = -1;
+        if (of_find_property(dp, "cpuid", NULL)) {
+                int limit = 2;
+                portid_parent = dp;
+                while (limit--) {
+                        portid_parent = portid_parent->parent;
+                        if (!portid_parent)
+                                break;
+                        portid = of_getintprop_default(portid_parent,
+                                                       "portid", -1);
+                        if (portid >= 0)
+                                break;
+                }
+        }
+#ifndef CONFIG_SMP
+        /* On uniprocessor we only want the values for the
+         * real physical cpu the kernel booted onto, however
+         * cpu_data() only has one entry at index 0.
+         */
+        if (cpuid != real_hard_smp_processor_id())
+                return NULL;
+        cpuid = 0;
+#endif
+        cpu_data(cpuid).clock_tick =
+                of_getintprop_default(dp, "clock-frequency", 0);
+        if (portid_parent) {
+                cpu_data(cpuid).dcache_size =
+                        of_getintprop_default(dp, "l1-dcache-size",
+                                              16 * 1024);
+                cpu_data(cpuid).dcache_line_size =
+                        of_getintprop_default(dp, "l1-dcache-line-size",
+                                              32);
+                cpu_data(cpuid).icache_size =
+                        of_getintprop_default(dp, "l1-icache-size",
+                                              8 * 1024);
+                cpu_data(cpuid).icache_line_size =
+                        of_getintprop_default(dp, "l1-icache-line-size",
+                                              32);
+                cpu_data(cpuid).ecache_size =
+                        of_getintprop_default(dp, "l2-cache-size", 0);
+                cpu_data(cpuid).ecache_line_size =
+                        of_getintprop_default(dp, "l2-cache-line-size", 0);
+                if (!cpu_data(cpuid).ecache_size ||
+                    !cpu_data(cpuid).ecache_line_size) {
                        cpu_data(cpuid).ecache_size =
-                                of_getintprop_default(dp, "ecache-size",
+                                of_getintprop_default(portid_parent,
+                                                      "l2-cache-size",
                                                      (4 * 1024 * 1024));
                        cpu_data(cpuid).ecache_line_size =
-                                of_getintprop_default(dp, "ecache-line-size", 64);
+                                of_getintprop_default(portid_parent,
+                                                      "l2-cache-line-size", 64);
-                        cpu_data(cpuid).core_id = 0;
-                        cpu_data(cpuid).proc_id = -1;
                }
+                cpu_data(cpuid).core_id = portid + 1;
+                cpu_data(cpuid).proc_id = portid;
 #ifdef CONFIG_SMP
-                set_cpu_present(cpuid, true);
+                sparc64_multi_core = 1;
-                set_cpu_possible(cpuid, true);
 #endif
+        } else {
+                cpu_data(cpuid).dcache_size =
+                        of_getintprop_default(dp, "dcache-size", 16 * 1024);
+                cpu_data(cpuid).dcache_line_size =
+                        of_getintprop_default(dp, "dcache-line-size", 32);
+                cpu_data(cpuid).icache_size =
+                        of_getintprop_default(dp, "icache-size", 16 * 1024);
+                cpu_data(cpuid).icache_line_size =
+                        of_getintprop_default(dp, "icache-line-size", 32);
+                cpu_data(cpuid).ecache_size =
+                        of_getintprop_default(dp, "ecache-size",
+                                              (4 * 1024 * 1024));
+                cpu_data(cpuid).ecache_line_size =
+                        of_getintprop_default(dp, "ecache-line-size", 64);
+                cpu_data(cpuid).core_id = 0;
+                cpu_data(cpuid).proc_id = -1;
        }
+        return NULL;
+}
+void __init of_fill_in_cpu_data(void)
+{
+        if (tlb_type == hypervisor)
+                return;
+        of_iterate_over_cpus(fill_in_one_cpu, 0);
        smp_fill_in_sib_core_maps();
 }
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index ff7b591c8946..0fb5789d43c8 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -313,6 +313,4 @@ void __init prom_build_devicetree(void)
        printk("PROM: Built device tree with %u bytes of memory.\n",
               prom_early_allocated);
-        of_fill_in_cpu_data();
 }
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index f7642e5a94db..fa44eaf8d897 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -20,7 +20,8 @@
 #include <linux/cache.h>
 #include <linux/jiffies.h>
 #include <linux/profile.h>
-#include <linux/lmb.h>
+#include <linux/bootmem.h>
+#include <linux/vmalloc.h>
 #include <linux/cpu.h>
 #include <asm/head.h>
@@ -47,6 +48,8 @@
 #include <asm/ldc.h>
 #include <asm/hypervisor.h>
+#include "cpumap.h"
 int sparc64_multi_core __read_mostly;
 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
@@ -278,7 +281,7 @@ static unsigned long kimage_addr_to_ra(void *p)
        return kern_base + (val - KERNBASE);
 }
-static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
+static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, void **descrp)
 {
        extern unsigned long sparc64_ttable_tl0;
        extern unsigned long kern_locked_tte_data;
@@ -298,12 +301,12 @@ static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread
                       "hvtramp_descr.\n");
                return;
        }
+        *descrp = hdesc;
        hdesc->cpu = cpu;
        hdesc->num_mappings = num_kernel_image_mappings;
        tb = &trap_block[cpu];
-        tb->hdesc = hdesc;
        hdesc->fault_info_va = (unsigned long) &tb->fault_info;
        hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
@@ -341,12 +344,12 @@ static struct thread_info *cpu_new_thread = NULL;
 static int __cpuinit smp_boot_one_cpu(unsigned int cpu)
 {
-        struct trap_per_cpu *tb = &trap_block[cpu];
        unsigned long entry =
                (unsigned long)(&sparc64_cpu_startup);
        unsigned long cookie =
                (unsigned long)(&cpu_new_thread);
        struct task_struct *p;
+        void *descr = NULL;
        int timeout, ret;
        p = fork_idle(cpu);
@@ -359,7 +362,8 @@ static int __cpuinit smp_boot_one_cpu(unsigned int cpu)
 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
                if (ldom_domaining_enabled)
                        ldom_startcpu_cpuid(cpu,
-                                            (unsigned long) cpu_new_thread);
+                                            (unsigned long) cpu_new_thread,
+                                            &descr);
                else
 #endif
                        prom_startcpu_cpuid(cpu, entry, cookie);
@@ -383,10 +387,7 @@ static int __cpuinit smp_boot_one_cpu(unsigned int cpu)
        }
        cpu_new_thread = NULL;
-        if (tb->hdesc) {
+        kfree(descr);
-                kfree(tb->hdesc);
-                tb->hdesc = NULL;
-        }
        return ret;
 }
@@ -1315,6 +1316,8 @@ int __cpu_disable(void)
        cpu_clear(cpu, cpu_online_map);
        ipi_call_unlock();
+        cpu_map_rebuild();
        return 0;
 }
@@ -1373,36 +1376,171 @@ void smp_send_stop(void)
 {
 }
-unsigned long __per_cpu_base __read_mostly;
+/**
-unsigned long __per_cpu_shift __read_mostly;
+ * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
+ * @cpu: cpu to allocate for
+ * @size: size allocation in bytes
+ * @align: alignment
+ *
+ * Allocate @size bytes aligned at @align for cpu @cpu.  This wrapper
+ * does the right thing for NUMA regardless of the current
+ * configuration.
+ *
+ * RETURNS:
+ * Pointer to the allocated area on success, NULL on failure.
+ */
+static void * __init pcpu_alloc_bootmem(unsigned int cpu, unsigned long size,
+                                        unsigned long align)
+{
+        const unsigned long goal = __pa(MAX_DMA_ADDRESS);
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+        int node = cpu_to_node(cpu);
+        void *ptr;
+        if (!node_online(node) || !NODE_DATA(node)) {
+                ptr = __alloc_bootmem(size, align, goal);
+                pr_info("cpu %d has no node %d or node-local memory\n",
+                        cpu, node);
+                pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
+                         cpu, size, __pa(ptr));
+        } else {
+                ptr = __alloc_bootmem_node(NODE_DATA(node),
+                                           size, align, goal);
+                pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
+                         "%016lx\n", cpu, size, node, __pa(ptr));
+        }
+        return ptr;
+#else
+        return __alloc_bootmem(size, align, goal);
+#endif
+}
-EXPORT_SYMBOL(__per_cpu_base);
+static size_t pcpur_size __initdata;
-EXPORT_SYMBOL(__per_cpu_shift);
+static void **pcpur_ptrs __initdata;
-void __init real_setup_per_cpu_areas(void)
+static struct page * __init pcpur_get_page(unsigned int cpu, int pageno)
 {
-        unsigned long paddr, goal, size, i;
+        size_t off = (size_t)pageno << PAGE_SHIFT;
-        char *ptr;
-        /* Copy section for each CPU (we discard the original) */
+        if (off >= pcpur_size)
-        goal = PERCPU_ENOUGH_ROOM;
+                return NULL;
-        __per_cpu_shift = PAGE_SHIFT;
+        return virt_to_page(pcpur_ptrs[cpu] + off);
-        for (size = PAGE_SIZE; size < goal; size <<= 1UL)
+}
-                __per_cpu_shift++;
+#define PCPU_CHUNK_SIZE (4UL * 1024UL * 1024UL)
+static void __init pcpu_map_range(unsigned long start, unsigned long end,
+                                  struct page *page)
+{
+        unsigned long pfn = page_to_pfn(page);
+        unsigned long pte_base;
+        BUG_ON((pfn<<PAGE_SHIFT)&(PCPU_CHUNK_SIZE - 1UL));
+        pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
+                    _PAGE_CP_4U | _PAGE_CV_4U |
+                    _PAGE_P_4U | _PAGE_W_4U);
+        if (tlb_type == hypervisor)
+                pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
+                            _PAGE_CP_4V | _PAGE_CV_4V |
+                            _PAGE_P_4V | _PAGE_W_4V);
+        while (start < end) {
+                pgd_t *pgd = pgd_offset_k(start);
+                unsigned long this_end;
+                pud_t *pud;
+                pmd_t *pmd;
+                pte_t *pte;
+                pud = pud_offset(pgd, start);
+                if (pud_none(*pud)) {
+                        pmd_t *new;
+                        new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
+                        pud_populate(&init_mm, pud, new);
+                }
+                pmd = pmd_offset(pud, start);
+                if (!pmd_present(*pmd)) {
+                        pte_t *new;
+                        new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
+                        pmd_populate_kernel(&init_mm, pmd, new);
+                }
-        paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
+                pte = pte_offset_kernel(pmd, start);
-        if (!paddr) {
+                this_end = (start + PMD_SIZE) & PMD_MASK;
-                prom_printf("Cannot allocate per-cpu memory.\n");
+                if (this_end > end)
-                prom_halt();
+                        this_end = end;
+                while (start < this_end) {
+                        unsigned long paddr = pfn << PAGE_SHIFT;
+                        pte_val(*pte) = (paddr | pte_base);
+                        start += PAGE_SIZE;
+                        pte++;
+                        pfn++;
+                }
+        }
+}
+void __init setup_per_cpu_areas(void)
+{
+        size_t dyn_size, static_size = __per_cpu_end - __per_cpu_start;
+        static struct vm_struct vm;
+        unsigned long delta, cpu;
+        size_t pcpu_unit_size;
+        size_t ptrs_size;
+        pcpur_size = PFN_ALIGN(static_size + PERCPU_MODULE_RESERVE +
+                               PERCPU_DYNAMIC_RESERVE);
+        dyn_size = pcpur_size - static_size - PERCPU_MODULE_RESERVE;
+        ptrs_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpur_ptrs[0]));
+        pcpur_ptrs = alloc_bootmem(ptrs_size);
+        for_each_possible_cpu(cpu) {
+                pcpur_ptrs[cpu] = pcpu_alloc_bootmem(cpu, PCPU_CHUNK_SIZE,
+                                                     PCPU_CHUNK_SIZE);
+                free_bootmem(__pa(pcpur_ptrs[cpu] + pcpur_size),
+                             PCPU_CHUNK_SIZE - pcpur_size);
+                memcpy(pcpur_ptrs[cpu], __per_cpu_load, static_size);
        }
-        ptr = __va(paddr);
+        /* allocate address and map */
-        __per_cpu_base = ptr - __per_cpu_start;
+        vm.flags = VM_ALLOC;
+        vm.size = num_possible_cpus() * PCPU_CHUNK_SIZE;
+        vm_area_register_early(&vm, PCPU_CHUNK_SIZE);
+        for_each_possible_cpu(cpu) {
+                unsigned long start = (unsigned long) vm.addr;
+                unsigned long end;
+                start += cpu * PCPU_CHUNK_SIZE;
+                end = start + PCPU_CHUNK_SIZE;
+                pcpu_map_range(start, end, virt_to_page(pcpur_ptrs[cpu]));
+        }
-        for (i = 0; i < NR_CPUS; i++, ptr += size)
+        pcpu_unit_size = pcpu_setup_first_chunk(pcpur_get_page, static_size,
-                memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
+                                                PERCPU_MODULE_RESERVE, dyn_size,
+                                                PCPU_CHUNK_SIZE, vm.addr, NULL);
+        free_bootmem(__pa(pcpur_ptrs), ptrs_size);
+        delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
+        for_each_possible_cpu(cpu) {
+                __per_cpu_offset(cpu) = delta + cpu * pcpu_unit_size;
+        }
        /* Setup %g5 for the boot cpu.  */
        __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
+        of_fill_in_cpu_data();
+        if (tlb_type == hypervisor)
+                mdesc_fill_in_cpu_data(cpu_all_mask);
 }
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 00ec3b15f38c..690901657291 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -81,4 +81,6 @@ sys_call_table:
 /*305*/ .long sys_set_mempolicy, sys_kexec_load, sys_move_pages, sys_getcpu, sys_epoll_pwait
 /*310*/ .long sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
 /*315*/ .long sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1
-/*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv, sys_pwritev
+/*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
+/*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 82b5bf85b9d2..6b3ee88e253c 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -82,7 +82,8 @@ sys_call_table32:
        .word compat_sys_set_mempolicy, compat_sys_kexec_load, compat_sys_move_pages, sys_getcpu, compat_sys_epoll_pwait
 /*310*/ .word compat_sys_utimensat, compat_sys_signalfd, sys_timerfd_create, sys_eventfd, compat_sys_fallocate
        .word compat_sys_timerfd_settime, compat_sys_timerfd_gettime, compat_sys_signalfd4, sys_eventfd2, sys_epoll_create1
-/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv, compat_sys_pwritev
+/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv
+        .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo
 #endif /* CONFIG_COMPAT */
@@ -156,4 +157,5 @@ sys_call_table:
        .word sys_set_mempolicy, sys_kexec_load, sys_move_pages, sys_getcpu, sys_epoll_pwait
 /*310*/ .word sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
        .word sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1
-/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv, sys_pwritev
+/*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
+        .word sys_pwritev, sys_rt_tgsigqueueinfo
diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c
index d809c4ebb48f..10f7bb9fc140 100644
--- a/arch/sparc/kernel/traps_64.c
+++ b/arch/sparc/kernel/traps_64.c
@@ -2509,6 +2509,7 @@ void do_getpsr(struct pt_regs *regs)
 }
 struct trap_per_cpu trap_block[NR_CPUS];
+EXPORT_SYMBOL(trap_block);
 /* This can get invoked before sched_init() so play it super safe
 * and use hard_smp_processor_id().
@@ -2530,84 +2531,97 @@ extern void tsb_config_offsets_are_bolixed_dave(void);
 void __init trap_init(void)
 {
        /* Compile time sanity check. */
-        if (TI_TASK != offsetof(struct thread_info, task) ||
+        BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
-            TI_FLAGS != offsetof(struct thread_info, flags) ||
+                     TI_FLAGS != offsetof(struct thread_info, flags) ||
-            TI_CPU != offsetof(struct thread_info, cpu) ||
+                     TI_CPU != offsetof(struct thread_info, cpu) ||
-            TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
+                     TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
-            TI_KSP != offsetof(struct thread_info, ksp) ||
+                     TI_KSP != offsetof(struct thread_info, ksp) ||
-            TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
+                     TI_FAULT_ADDR != offsetof(struct thread_info,
-            TI_KREGS != offsetof(struct thread_info, kregs) ||
+                                               fault_address) ||
-            TI_UTRAPS != offsetof(struct thread_info, utraps) ||
+                     TI_KREGS != offsetof(struct thread_info, kregs) ||
-            TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
+                     TI_UTRAPS != offsetof(struct thread_info, utraps) ||
-            TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
+                     TI_EXEC_DOMAIN != offsetof(struct thread_info,
-            TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
+                                                exec_domain) ||
-            TI_GSR != offsetof(struct thread_info, gsr) ||
+                     TI_REG_WINDOW != offsetof(struct thread_info,
-            TI_XFSR != offsetof(struct thread_info, xfsr) ||
+                                               reg_window) ||
-            TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
+                     TI_RWIN_SPTRS != offsetof(struct thread_info,
-            TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
+                                               rwbuf_stkptrs) ||
-            TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
+                     TI_GSR != offsetof(struct thread_info, gsr) ||
-            TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
+                     TI_XFSR != offsetof(struct thread_info, xfsr) ||
-            TI_PCR != offsetof(struct thread_info, pcr_reg) ||
+                     TI_USER_CNTD0 != offsetof(struct thread_info,
-            TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
+                                               user_cntd0) ||
-            TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
+                     TI_USER_CNTD1 != offsetof(struct thread_info,
-            TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
+                                               user_cntd1) ||
-            TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
+                     TI_KERN_CNTD0 != offsetof(struct thread_info,
-            TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
+                                               kernel_cntd0) ||
-            TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
+                     TI_KERN_CNTD1 != offsetof(struct thread_info,
-            TI_FPREGS != offsetof(struct thread_info, fpregs) ||
+                                               kernel_cntd1) ||
-            (TI_FPREGS & (64 - 1)))
+                     TI_PCR != offsetof(struct thread_info, pcr_reg) ||
-                thread_info_offsets_are_bolixed_dave();
+                     TI_PRE_COUNT != offsetof(struct thread_info,
+                                              preempt_count) ||
-        if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
+                     TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
-            (TRAP_PER_CPU_PGD_PADDR !=
+                     TI_SYS_NOERROR != offsetof(struct thread_info,
-             offsetof(struct trap_per_cpu, pgd_paddr)) ||
+                                                syscall_noerror) ||
-            (TRAP_PER_CPU_CPU_MONDO_PA !=
+                     TI_RESTART_BLOCK != offsetof(struct thread_info,
-             offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
+                                                  restart_block) ||
-            (TRAP_PER_CPU_DEV_MONDO_PA !=
+                     TI_KUNA_REGS != offsetof(struct thread_info,
-             offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
+                                              kern_una_regs) ||
-            (TRAP_PER_CPU_RESUM_MONDO_PA !=
+                     TI_KUNA_INSN != offsetof(struct thread_info,
-             offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
+                                              kern_una_insn) ||
-            (TRAP_PER_CPU_RESUM_KBUF_PA !=
+                     TI_FPREGS != offsetof(struct thread_info, fpregs) ||
-             offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
+                     (TI_FPREGS & (64 - 1)));
-            (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
-             offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
+        BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
-            (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
+                                                     thread) ||
-             offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
+                     (TRAP_PER_CPU_PGD_PADDR !=
-            (TRAP_PER_CPU_FAULT_INFO !=
+                      offsetof(struct trap_per_cpu, pgd_paddr)) ||
-             offsetof(struct trap_per_cpu, fault_info)) ||
+                     (TRAP_PER_CPU_CPU_MONDO_PA !=
-            (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
+                      offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
-             offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
+                     (TRAP_PER_CPU_DEV_MONDO_PA !=
-            (TRAP_PER_CPU_CPU_LIST_PA !=
+                      offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
-             offsetof(struct trap_per_cpu, cpu_list_pa)) ||
+                     (TRAP_PER_CPU_RESUM_MONDO_PA !=
-            (TRAP_PER_CPU_TSB_HUGE !=
+                      offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
-             offsetof(struct trap_per_cpu, tsb_huge)) ||
+                     (TRAP_PER_CPU_RESUM_KBUF_PA !=
-            (TRAP_PER_CPU_TSB_HUGE_TEMP !=
+                      offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
-             offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
+                     (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
-            (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
+                      offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
-             offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
+                     (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
-            (TRAP_PER_CPU_CPU_MONDO_QMASK !=
+                      offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
-             offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
+                     (TRAP_PER_CPU_FAULT_INFO !=
-            (TRAP_PER_CPU_DEV_MONDO_QMASK !=
+                      offsetof(struct trap_per_cpu, fault_info)) ||
-             offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
+                     (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
-            (TRAP_PER_CPU_RESUM_QMASK !=
+                      offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
-             offsetof(struct trap_per_cpu, resum_qmask)) ||
+                     (TRAP_PER_CPU_CPU_LIST_PA !=
-            (TRAP_PER_CPU_NONRESUM_QMASK !=
+                      offsetof(struct trap_per_cpu, cpu_list_pa)) ||
-             offsetof(struct trap_per_cpu, nonresum_qmask)))
+                     (TRAP_PER_CPU_TSB_HUGE !=
-                trap_per_cpu_offsets_are_bolixed_dave();
+                      offsetof(struct trap_per_cpu, tsb_huge)) ||
+                     (TRAP_PER_CPU_TSB_HUGE_TEMP !=
-        if ((TSB_CONFIG_TSB !=
+                      offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
-             offsetof(struct tsb_config, tsb)) ||
+                     (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
-            (TSB_CONFIG_RSS_LIMIT !=
+                      offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
-             offsetof(struct tsb_config, tsb_rss_limit)) ||
+                     (TRAP_PER_CPU_CPU_MONDO_QMASK !=
-            (TSB_CONFIG_NENTRIES !=
+                      offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
-             offsetof(struct tsb_config, tsb_nentries)) ||
+                     (TRAP_PER_CPU_DEV_MONDO_QMASK !=
-            (TSB_CONFIG_REG_VAL !=
+                      offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
-             offsetof(struct tsb_config, tsb_reg_val)) ||
+                     (TRAP_PER_CPU_RESUM_QMASK !=
-            (TSB_CONFIG_MAP_VADDR !=
+                      offsetof(struct trap_per_cpu, resum_qmask)) ||
-             offsetof(struct tsb_config, tsb_map_vaddr)) ||
+                     (TRAP_PER_CPU_NONRESUM_QMASK !=
-            (TSB_CONFIG_MAP_PTE !=
+                      offsetof(struct trap_per_cpu, nonresum_qmask)) ||
-             offsetof(struct tsb_config, tsb_map_pte)))
+                     (TRAP_PER_CPU_PER_CPU_BASE !=
-                tsb_config_offsets_are_bolixed_dave();
+                      offsetof(struct trap_per_cpu, __per_cpu_base)));
+        BUILD_BUG_ON((TSB_CONFIG_TSB !=
+                      offsetof(struct tsb_config, tsb)) ||
+                     (TSB_CONFIG_RSS_LIMIT !=
+                      offsetof(struct tsb_config, tsb_rss_limit)) ||
+                     (TSB_CONFIG_NENTRIES !=
+                      offsetof(struct tsb_config, tsb_nentries)) ||
+                     (TSB_CONFIG_REG_VAL !=
+                      offsetof(struct tsb_config, tsb_reg_val)) ||
+                     (TSB_CONFIG_MAP_VADDR !=
+                      offsetof(struct tsb_config, tsb_map_vaddr)) ||
+                     (TSB_CONFIG_MAP_PTE !=
+                      offsetof(struct tsb_config, tsb_map_pte)));
        /* Attach to the address space of init_task.  On SMP we
         * do this in smp.c:smp_callin for other cpus.
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index cbb282dab5a7..26bb3919ff1f 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -358,6 +358,7 @@ void __init paging_init(void)
        protection_map[15] = PAGE_SHARED;
        btfixup();
        prom_build_devicetree();
+        of_fill_in_cpu_data();
        device_scan();
 }
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index f26a352c08a0..ca92e2f54e4d 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -1679,11 +1679,6 @@ pgd_t swapper_pg_dir[2048];
 static void sun4u_pgprot_init(void);
 static void sun4v_pgprot_init(void);
-/* Dummy function */
-void __init setup_per_cpu_areas(void)
-{
-}
 void __init paging_init(void)
 {
        unsigned long end_pfn, shift, phys_base;
@@ -1799,16 +1794,13 @@ void __init paging_init(void)
        if (tlb_type == hypervisor)
                sun4v_ktsb_register();
-        /* We must setup the per-cpu areas before we pull in the
-         * PROM and the MDESC.  The code there fills in cpu and
-         * other information into per-cpu data structures.
-         */
-        real_setup_per_cpu_areas();
        prom_build_devicetree();
+        of_populate_present_mask();
-        if (tlb_type == hypervisor)
+        if (tlb_type == hypervisor) {
                sun4v_mdesc_init();
+                mdesc_populate_present_mask(cpu_all_mask);
+        }
        /* Once the OF device tree and MDESC have been setup, we know
         * the list of possible cpus.  Therefore we can allocate the
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 06c9a7d98206..ade4eb373bdd 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -19,6 +19,7 @@
 #include <linux/fs.h>
 #include <linux/seq_file.h>
 #include <linux/kdebug.h>
+#include <linux/log2.h>
 #include <asm/bitext.h>
 #include <asm/page.h>
@@ -349,7 +350,7 @@ static void srmmu_free_nocache(unsigned long vaddr, int size)
                    vaddr, srmmu_nocache_end);
                BUG();
        }
-        if (size & (size-1)) {
+        if (!is_power_of_2(size)) {
                printk("Size 0x%x is not a power of 2\n", size);
                BUG();
        }
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 434ba121e3c5..3b44b47c7e1d 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -360,7 +360,7 @@ static struct platform_driver uml_net_driver = {
 static void net_device_release(struct device *dev)
 {
-        struct uml_net *device = dev->driver_data;
+        struct uml_net *device = dev_get_drvdata(dev);
        struct net_device *netdev = device->dev;
        struct uml_net_private *lp = netdev_priv(netdev);
@@ -440,7 +440,7 @@ static void eth_configure(int n, void *init, char *mac,
        device->pdev.id = n;
        device->pdev.name = DRIVER_NAME;
        device->pdev.dev.release = net_device_release;
-        device->pdev.dev.driver_data = device;
+        dev_set_drvdata(&device->pdev.dev, device);
        if (platform_device_register(&device->pdev))
                goto out_free_netdev;
        SET_NETDEV_DEV(dev,&device->pdev.dev);
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index aa9e926e13d7..8f05d4d9da12 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -778,7 +778,7 @@ static int ubd_open_dev(struct ubd *ubd_dev)
 static void ubd_device_release(struct device *dev)
 {
-        struct ubd *ubd_dev = dev->driver_data;
+        struct ubd *ubd_dev = dev_get_drvdata(dev);
        blk_cleanup_queue(ubd_dev->queue);
        *ubd_dev = ((struct ubd) DEFAULT_UBD);
@@ -807,7 +807,7 @@ static int ubd_disk_register(int major, u64 size, int unit,
                ubd_devs[unit].pdev.id   = unit;
                ubd_devs[unit].pdev.name = DRIVER_NAME;
                ubd_devs[unit].pdev.dev.release = ubd_device_release;
-                ubd_devs[unit].pdev.dev.driver_data = &ubd_devs[unit];
+                dev_set_drvdata(&ubd_devs[unit].pdev.dev, &ubd_devs[unit]);
                platform_device_register(&ubd_devs[unit].pdev);
                disk->driverfs_dev = &ubd_devs[unit].pdev.dev;
        }
diff --git a/arch/um/include/shared/init.h b/arch/um/include/shared/init.h
index 37dd097c16c0..b3906f860a87 100644
--- a/arch/um/include/shared/init.h
+++ b/arch/um/include/shared/init.h
@@ -27,7 +27,7 @@
 * sign followed by value, e.g.:
 *
 * static int init_variable __initdata = 0;
- * static char linux_logo[] __initdata = { 0x32, 0x36, ... };
+ * static const char linux_logo[] __initconst = { 0x32, 0x36, ... };
 *
 * Don't forget to initialize data not at file scope, i.e. within a function,
 * as gcc otherwise puts the data into the bss section and not into the init
diff --git a/arch/um/include/shared/net_user.h b/arch/um/include/shared/net_user.h
index 63bee158cd8e..3dabbe128e40 100644
--- a/arch/um/include/shared/net_user.h
+++ b/arch/um/include/shared/net_user.h
@@ -8,7 +8,7 @@
 #define ETH_ADDR_LEN (6)
 #define ETH_HEADER_ETHERTAP (16)
-#define ETH_HEADER_OTHER (14)
+#define ETH_HEADER_OTHER (26) /* 14 for ethernet + VLAN + MPLS for crazy people */
 #define ETH_MAX_PACKET (1500)
 #define UML_NET_VERSION (4)
diff --git a/arch/um/kernel/init_task.c b/arch/um/kernel/init_task.c
index 806d381947bf..b25121b537d8 100644
--- a/arch/um/kernel/init_task.c
+++ b/arch/um/kernel/init_task.c
@@ -10,11 +10,8 @@
 #include "linux/mqueue.h"
 #include "asm/uaccess.h"
-struct mm_struct init_mm = INIT_MM(init_mm);
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-EXPORT_SYMBOL(init_mm);
 /*
 * Initial task structure.
 *
diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c
index 336b61569072..454cdb43e351 100644
--- a/arch/um/kernel/irq.c
+++ b/arch/um/kernel/irq.c
@@ -358,7 +358,7 @@ EXPORT_SYMBOL(um_request_irq);
 EXPORT_SYMBOL(reactivate_fd);
 /*
- * hw_interrupt_type must define (startup || enable) &&
+ * irq_chip must define (startup || enable) &&
 * (shutdown || disable) && end
 */
 static void dummy(unsigned int irq)
@@ -366,7 +366,7 @@ static void dummy(unsigned int irq)
 }
 /* This is used for everything else than the timer. */
-static struct hw_interrupt_type normal_irq_type = {
+static struct irq_chip normal_irq_type = {
        .typename = "SIGIO",
        .release = free_irq_by_irq_and_dev,
        .disable = dummy,
@@ -375,7 +375,7 @@ static struct hw_interrupt_type normal_irq_type = {
        .end = dummy
 };
-static struct hw_interrupt_type SIGVTALRM_irq_type = {
+static struct irq_chip SIGVTALRM_irq_type = {
        .typename = "SIGVTALRM",
        .release = free_irq_by_irq_and_dev,
        .shutdown = dummy, /* never called */
diff --git a/arch/um/sys-i386/stub.S b/arch/um/sys-i386/stub.S
index c41b04bf5fa0..54a36ec20cb7 100644
--- a/arch/um/sys-i386/stub.S
+++ b/arch/um/sys-i386/stub.S
@@ -1,7 +1,7 @@
 #include "as-layout.h"
        .globl syscall_stub
-.section .__syscall_stub, "x"
+.section .__syscall_stub, "ax"
        .globl batch_syscall_stub
 batch_syscall_stub:
diff --git a/arch/um/sys-x86_64/asm/elf.h b/arch/um/sys-x86_64/asm/elf.h
index 6e8a9195e952..04b9e87c8dad 100644
--- a/arch/um/sys-x86_64/asm/elf.h
+++ b/arch/um/sys-x86_64/asm/elf.h
@@ -66,28 +66,28 @@ typedef struct user_i387_struct elf_fpregset_t;
        PT_REGS_R15(regs) = 0; \
 } while (0)
-#define ELF_CORE_COPY_REGS(pr_reg, regs)                \
+#define ELF_CORE_COPY_REGS(pr_reg, _regs)               \
-        (pr_reg)[0] = (regs)->regs.gp[0];                       \
+        (pr_reg)[0] = (_regs)->regs.gp[0];                      \
-        (pr_reg)[1] = (regs)->regs.gp[1];                       \
+        (pr_reg)[1] = (_regs)->regs.gp[1];                      \
-        (pr_reg)[2] = (regs)->regs.gp[2];                       \
+        (pr_reg)[2] = (_regs)->regs.gp[2];                      \
-        (pr_reg)[3] = (regs)->regs.gp[3];                       \
+        (pr_reg)[3] = (_regs)->regs.gp[3];                      \
-        (pr_reg)[4] = (regs)->regs.gp[4];                       \
+        (pr_reg)[4] = (_regs)->regs.gp[4];                      \
-        (pr_reg)[5] = (regs)->regs.gp[5];                       \
+        (pr_reg)[5] = (_regs)->regs.gp[5];                      \
-        (pr_reg)[6] = (regs)->regs.gp[6];                       \
+        (pr_reg)[6] = (_regs)->regs.gp[6];                      \
-        (pr_reg)[7] = (regs)->regs.gp[7];                       \
+        (pr_reg)[7] = (_regs)->regs.gp[7];                      \
-        (pr_reg)[8] = (regs)->regs.gp[8];                       \
+        (pr_reg)[8] = (_regs)->regs.gp[8];                      \
-        (pr_reg)[9] = (regs)->regs.gp[9];                       \
+        (pr_reg)[9] = (_regs)->regs.gp[9];                      \
-        (pr_reg)[10] = (regs)->regs.gp[10];                     \
+        (pr_reg)[10] = (_regs)->regs.gp[10];                    \
-        (pr_reg)[11] = (regs)->regs.gp[11];                     \
+        (pr_reg)[11] = (_regs)->regs.gp[11];                    \
-        (pr_reg)[12] = (regs)->regs.gp[12];                     \
+        (pr_reg)[12] = (_regs)->regs.gp[12];                    \
-        (pr_reg)[13] = (regs)->regs.gp[13];                     \
+        (pr_reg)[13] = (_regs)->regs.gp[13];                    \
-        (pr_reg)[14] = (regs)->regs.gp[14];                     \
+        (pr_reg)[14] = (_regs)->regs.gp[14];                    \
-        (pr_reg)[15] = (regs)->regs.gp[15];                     \
+        (pr_reg)[15] = (_regs)->regs.gp[15];                    \
-        (pr_reg)[16] = (regs)->regs.gp[16];                     \
+        (pr_reg)[16] = (_regs)->regs.gp[16];                    \
-        (pr_reg)[17] = (regs)->regs.gp[17];                     \
+        (pr_reg)[17] = (_regs)->regs.gp[17];                    \
-        (pr_reg)[18] = (regs)->regs.gp[18];                     \
+        (pr_reg)[18] = (_regs)->regs.gp[18];                    \
-        (pr_reg)[19] = (regs)->regs.gp[19];                     \
+        (pr_reg)[19] = (_regs)->regs.gp[19];                    \
-        (pr_reg)[20] = (regs)->regs.gp[20];                     \
+        (pr_reg)[20] = (_regs)->regs.gp[20];                    \
        (pr_reg)[21] = current->thread.arch.fs;                 \
        (pr_reg)[22] = 0;                                       \
        (pr_reg)[23] = 0;                                       \
diff --git a/arch/um/sys-x86_64/stub.S b/arch/um/sys-x86_64/stub.S
index 6d9edf9fabce..20e4a96a6dcb 100644
--- a/arch/um/sys-x86_64/stub.S
+++ b/arch/um/sys-x86_64/stub.S
@@ -1,7 +1,7 @@
 #include "as-layout.h"
        .globl syscall_stub
-.section .__syscall_stub, "x"
+.section .__syscall_stub, "ax"
 syscall_stub:
        syscall
        /* We don't have 64-bit constants, so this constructs the address
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 356d2ec8e2fb..cf42fc305419 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -46,6 +46,7 @@ config X86
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_BZIP2
        select HAVE_KERNEL_LZMA
+        select HAVE_ARCH_KMEMCHECK
 config OUTPUT_FORMAT
        string
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index edbd0ca62067..1b68659c41b4 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -81,6 +81,11 @@ ifdef CONFIG_CC_STACKPROTECTOR
        endif
 endif
+# Don't unroll struct assignments with kmemcheck enabled
+ifeq ($(CONFIG_KMEMCHECK),y)
+        KBUILD_CFLAGS += $(call cc-option,-fno-builtin-memcpy)
+endif
 # Stackpointer is addressed different for 32 bit and 64 bit x86
 sp-$(CONFIG_X86_32) := esp
 sp-$(CONFIG_X86_64) := rsp
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index f82fdc412c64..b93405b228b4 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -6,6 +6,7 @@
 * Documentation/DMA-API.txt for documentation.
 */
+#include <linux/kmemcheck.h>
 #include <linux/scatterlist.h>
 #include <linux/dma-debug.h>
 #include <linux/dma-attrs.h>
@@ -60,6 +61,7 @@ dma_map_single(struct device *hwdev, void *ptr, size_t size,
        dma_addr_t addr;
        BUG_ON(!valid_dma_direction(dir));
+        kmemcheck_mark_initialized(ptr, size);
        addr = ops->map_page(hwdev, virt_to_page(ptr),
                             (unsigned long)ptr & ~PAGE_MASK, size,
                             dir, NULL);
@@ -87,8 +89,12 @@ dma_map_sg(struct device *hwdev, struct scatterlist *sg,
 {
        struct dma_map_ops *ops = get_dma_ops(hwdev);
        int ents;
+        struct scatterlist *s;
+        int i;
        BUG_ON(!valid_dma_direction(dir));
+        for_each_sg(sg, s, nents, i)
+                kmemcheck_mark_initialized(sg_virt(s), s->length);
        ents = ops->map_sg(hwdev, sg, nents, dir, NULL);
        debug_dma_map_sg(hwdev, sg, nents, ents, dir);
@@ -200,6 +206,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
        dma_addr_t addr;
        BUG_ON(!valid_dma_direction(dir));
+        kmemcheck_mark_initialized(page_address(page) + offset, size);
        addr = ops->map_page(dev, page, offset, size, dir, NULL);
        debug_dma_map_page(dev, page, offset, size, dir, addr, false);
diff --git a/arch/x86/include/asm/kmap_types.h b/arch/x86/include/asm/kmap_types.h
index 5759c165a5cf..9e00a731a7fb 100644
--- a/arch/x86/include/asm/kmap_types.h
+++ b/arch/x86/include/asm/kmap_types.h
@@ -2,28 +2,11 @@
 #define _ASM_X86_KMAP_TYPES_H
 #if defined(CONFIG_X86_32) && defined(CONFIG_DEBUG_HIGHMEM)
-# define D(n) __KM_FENCE_##n ,
+#define  __WITH_KM_FENCE
-#else
-# define D(n)
 #endif
-enum km_type {
+#include <asm-generic/kmap_types.h>
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-#undef D
+#undef __WITH_KM_FENCE
 #endif /* _ASM_X86_KMAP_TYPES_H */
diff --git a/arch/x86/include/asm/kmemcheck.h b/arch/x86/include/asm/kmemcheck.h
new file mode 100644
index 000000000000..ed01518f297e
--- /dev/null
+++ b/arch/x86/include/asm/kmemcheck.h
@@ -0,0 +1,42 @@
+#ifndef ASM_X86_KMEMCHECK_H
+#define ASM_X86_KMEMCHECK_H
+#include <linux/types.h>
+#include <asm/ptrace.h>
+#ifdef CONFIG_KMEMCHECK
+bool kmemcheck_active(struct pt_regs *regs);
+void kmemcheck_show(struct pt_regs *regs);
+void kmemcheck_hide(struct pt_regs *regs);
+bool kmemcheck_fault(struct pt_regs *regs,
+        unsigned long address, unsigned long error_code);
+bool kmemcheck_trap(struct pt_regs *regs);
+#else
+static inline bool kmemcheck_active(struct pt_regs *regs)
+{
+        return false;
+}
+static inline void kmemcheck_show(struct pt_regs *regs)
+{
+}
+static inline void kmemcheck_hide(struct pt_regs *regs)
+{
+}
+static inline bool kmemcheck_fault(struct pt_regs *regs,
+        unsigned long address, unsigned long error_code)
+{
+        return false;
+}
+static inline bool kmemcheck_trap(struct pt_regs *regs)
+{
+        return false;
+}
+#endif /* CONFIG_KMEMCHECK */
+#endif
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 18ef7ebf2631..3cc06e3fceb8 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -317,6 +317,11 @@ static inline int pte_present(pte_t a)
        return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE);
 }
+static inline int pte_hidden(pte_t pte)
+{
+        return pte_flags(pte) & _PAGE_HIDDEN;
+}
 static inline int pmd_present(pmd_t pmd)
 {
        return pmd_flags(pmd) & _PAGE_PRESENT;
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 4d258ad76a0f..54cb697f4900 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -18,7 +18,7 @@
 #define _PAGE_BIT_GLOBAL        8       /* Global TLB entry PPro+ */
 #define _PAGE_BIT_UNUSED1       9       /* available for programmer */
 #define _PAGE_BIT_IOMAP         10      /* flag used to indicate IO mapping */
-#define _PAGE_BIT_UNUSED3       11
+#define _PAGE_BIT_HIDDEN        11      /* hidden by kmemcheck */
 #define _PAGE_BIT_PAT_LARGE     12      /* On 2MB or 1GB pages */
 #define _PAGE_BIT_SPECIAL       _PAGE_BIT_UNUSED1
 #define _PAGE_BIT_CPA_TEST      _PAGE_BIT_UNUSED1
@@ -41,13 +41,18 @@
 #define _PAGE_GLOBAL    (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
 #define _PAGE_UNUSED1   (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED1)
 #define _PAGE_IOMAP     (_AT(pteval_t, 1) << _PAGE_BIT_IOMAP)
-#define _PAGE_UNUSED3   (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED3)
 #define _PAGE_PAT       (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
 #define _PAGE_SPECIAL   (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
 #define _PAGE_CPA_TEST  (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
 #define __HAVE_ARCH_PTE_SPECIAL
+#ifdef CONFIG_KMEMCHECK
+#define _PAGE_HIDDEN    (_AT(pteval_t, 1) << _PAGE_BIT_HIDDEN)
+#else
+#define _PAGE_HIDDEN    (_AT(pteval_t, 0))
+#endif
 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 #define _PAGE_NX        (_AT(pteval_t, 1) << _PAGE_BIT_NX)
 #else
diff --git a/arch/x86/include/asm/string_32.h b/arch/x86/include/asm/string_32.h
index 0e0e3ba827f7..c86f452256de 100644
--- a/arch/x86/include/asm/string_32.h
+++ b/arch/x86/include/asm/string_32.h
@@ -177,10 +177,18 @@ static inline void *__memcpy3d(void *to, const void *from, size_t len)
 *      No 3D Now!
 */
+#ifndef CONFIG_KMEMCHECK
 #define memcpy(t, f, n)                         \
        (__builtin_constant_p((n))              \
         ? __constant_memcpy((t), (f), (n))     \
         : __memcpy((t), (f), (n)))
+#else
+/*
+ * kmemcheck becomes very happy if we use the REP instructions unconditionally,
+ * because it means that we know both memory operands in advance.
+ */
+#define memcpy(t, f, n) __memcpy((t), (f), (n))
+#endif
 #endif
diff --git a/arch/x86/include/asm/string_64.h b/arch/x86/include/asm/string_64.h
index 2afe164bf1e6..19e2c468fc2c 100644
--- a/arch/x86/include/asm/string_64.h
+++ b/arch/x86/include/asm/string_64.h
@@ -27,6 +27,7 @@ static __always_inline void *__inline_memcpy(void *to, const void *from, size_t
   function. */
 #define __HAVE_ARCH_MEMCPY 1
+#ifndef CONFIG_KMEMCHECK
 #if (__GNUC__ == 4 && __GNUC_MINOR__ >= 3) || __GNUC__ > 4
 extern void *memcpy(void *to, const void *from, size_t len);
 #else
@@ -42,6 +43,13 @@ extern void *__memcpy(void *to, const void *from, size_t len);
        __ret;                                                  \
 })
 #endif
+#else
+/*
+ * kmemcheck becomes very happy if we use the REP instructions unconditionally,
+ * because it means that we know both memory operands in advance.
+ */
+#define memcpy(dst, src, len) __inline_memcpy((dst), (src), (len))
+#endif
 #define __HAVE_ARCH_MEMSET
 void *memset(void *s, int c, size_t n);
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 602c769fc98c..b0783520988b 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -154,9 +154,9 @@ struct thread_info {
 /* thread information allocation */
 #ifdef CONFIG_DEBUG_STACK_USAGE
-#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO)
+#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO)
 #else
-#define THREAD_FLAGS GFP_KERNEL
+#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK)
 #endif
 #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
diff --git a/arch/x86/include/asm/timex.h b/arch/x86/include/asm/timex.h
index b5c9d45c981f..1375cfc93960 100644
--- a/arch/x86/include/asm/timex.h
+++ b/arch/x86/include/asm/timex.h
@@ -4,9 +4,7 @@
 #include <asm/processor.h>
 #include <asm/tsc.h>
-/* The PIT ticks at this frequency (in HZ): */
+/* Assume we use the PIT time source for the clock tick */
-#define PIT_TICK_RATE           1193182
 #define CLOCK_TICK_RATE         PIT_TICK_RATE
 #define ARCH_HAS_READ_CURRENT_TIMER
diff --git a/arch/x86/include/asm/xor.h b/arch/x86/include/asm/xor.h
index 11b3bb86e17b..7fcf6f3dbcc3 100644
--- a/arch/x86/include/asm/xor.h
+++ b/arch/x86/include/asm/xor.h
@@ -1,5 +1,10 @@
+#ifdef CONFIG_KMEMCHECK
+/* kmemcheck doesn't handle MMX/SSE/SSE2 instructions */
+# include <asm-generic/xor.h>
+#else
 #ifdef CONFIG_X86_32
 # include "xor_32.h"
 #else
 # include "xor_64.h"
 #endif
+#endif
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index ef0ae207a7c8..096d19aea2f7 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -463,7 +463,7 @@ static void uv_heartbeat(unsigned long ignored)
        uv_set_scir_bits(bits);
        /* enable next timer period */
-        mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
+        mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 }
 static void __cpuinit uv_heartbeat_enable(int cpu)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3ffdcfa9abdf..9fa33886c0d7 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -487,7 +487,6 @@ out:
 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 {
        char *v = c->x86_vendor_id;
-        static int printed;
        int i;
        for (i = 0; i < X86_VENDOR_NUM; i++) {
@@ -504,13 +503,9 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
                }
        }
-        if (!printed) {
+        printk_once(KERN_ERR
-                printed++;
+                        "CPU: vendor_id '%s' unknown, using generic init.\n" \
-                printk(KERN_ERR
+                        "CPU: Your system may be unstable.\n", v);
-                    "CPU: vendor_id '%s' unknown, using generic init.\n", v);
-                printk(KERN_ERR "CPU: Your system may be unstable.\n");
-        }
        c->x86_vendor = X86_VENDOR_UNKNOWN;
        this_cpu = &default_cpu;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index daed39ba2614..3260ab044996 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -86,6 +86,29 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
         */
        if (c->x86 == 6 && c->x86_model < 15)
                clear_cpu_cap(c, X86_FEATURE_PAT);
+#ifdef CONFIG_KMEMCHECK
+        /*
+         * P4s have a "fast strings" feature which causes single-
+         * stepping REP instructions to only generate a #DB on
+         * cache-line boundaries.
+         *
+         * Ingo Molnar reported a Pentium D (model 6) and a Xeon
+         * (model 2) with the same problem.
+         */
+        if (c->x86 == 15) {
+                u64 misc_enable;
+                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
+                        printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
+                        misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
+                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                }
+        }
+#endif
 }
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 2ac1f0c2beb3..b07af8861244 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -182,6 +182,11 @@ static struct notifier_block __refdata cpuid_class_cpu_notifier =
        .notifier_call = cpuid_class_cpu_callback,
 };
+static char *cpuid_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "cpu/%u/cpuid", MINOR(dev->devt));
+}
 static int __init cpuid_init(void)
 {
        int i, err = 0;
@@ -198,6 +203,7 @@ static int __init cpuid_init(void)
                err = PTR_ERR(cpuid_class);
                goto out_chrdev;
        }
+        cpuid_class->nodename = cpuid_nodename;
        for_each_online_cpu(i) {
                err = cpuid_device_create(i);
                if (err != 0)
diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index c2e0bb0890d4..5cf36c053ac4 100644
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -7,6 +7,7 @@
 #include <linux/spinlock.h>
 #include <linux/jiffies.h>
 #include <linux/module.h>
+#include <linux/timex.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
diff --git a/arch/x86/kernel/init_task.c b/arch/x86/kernel/init_task.c
index df3bf269beab..270ff83efc11 100644
--- a/arch/x86/kernel/init_task.c
+++ b/arch/x86/kernel/init_task.c
@@ -12,7 +12,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
 /*
 * Initial thread structure.
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 9c4461501fcb..9371448290ac 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -236,6 +236,7 @@ static const struct file_operations microcode_fops = {
 static struct miscdevice microcode_dev = {
        .minor                  = MICROCODE_MINOR,
        .name                   = "microcode",
+        .devnode                = "cpu/microcode",
        .fops                   = &microcode_fops,
 };
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index 3cf3413ec626..98fd6cd4e3a4 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -196,6 +196,11 @@ static struct notifier_block __refdata msr_class_cpu_notifier = {
        .notifier_call = msr_class_cpu_callback,
 };
+static char *msr_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "cpu/%u/msr", MINOR(dev->devt));
+}
 static int __init msr_init(void)
 {
        int i, err = 0;
@@ -212,6 +217,7 @@ static int __init msr_init(void)
                err = PTR_ERR(msr_class);
                goto out_chrdev;
        }
+        msr_class->nodename = msr_nodename;
        for_each_online_cpu(i) {
                err = msr_device_create(i);
                if (err != 0)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 3bb2be1649bd..994dd6a4a2a0 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -63,7 +63,7 @@ void arch_task_cache_init(void)
        task_xstate_cachep =
                kmem_cache_create("task_xstate", xstate_size,
                                  __alignof__(union thread_xstate),
-                                  SLAB_PANIC, NULL);
+                                  SLAB_PANIC | SLAB_NOTRACK, NULL);
 }
 /*
diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c
index 4aaf7e48394f..c3eb207181fe 100644
--- a/arch/x86/kernel/stacktrace.c
+++ b/arch/x86/kernel/stacktrace.c
@@ -77,6 +77,13 @@ void save_stack_trace(struct stack_trace *trace)
 }
 EXPORT_SYMBOL_GPL(save_stack_trace);
+void save_stack_trace_bp(struct stack_trace *trace, unsigned long bp)
+{
+        dump_trace(current, NULL, NULL, bp, &save_stack_ops, trace);
+        if (trace->nr_entries < trace->max_entries)
+                trace->entries[trace->nr_entries++] = ULONG_MAX;
+}
 void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 {
        dump_trace(tsk, NULL, NULL, 0, &save_stack_ops_nosched, trace);
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 1e1e27b7d438..5f935f0d5861 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -45,6 +45,7 @@
 #include <linux/edac.h>
 #endif
+#include <asm/kmemcheck.h>
 #include <asm/stacktrace.h>
 #include <asm/processor.h>
 #include <asm/debugreg.h>
@@ -534,6 +535,10 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
        get_debugreg(condition, 6);
+        /* Catch kmemcheck conditions first of all! */
+        if (condition & DR_STEP && kmemcheck_trap(regs))
+                return;
        /*
         * The processor cleared BTF, so don't mark that we need it set.
         */
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 3e1c057e98fe..ae3180c506a6 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -9,6 +9,7 @@
 #include <linux/delay.h>
 #include <linux/clocksource.h>
 #include <linux/percpu.h>
+#include <linux/timex.h>
 #include <asm/hpet.h>
 #include <asm/timer.h>
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 32d6ae8fb60e..e770bf349ec4 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -1277,7 +1277,7 @@ static struct vmcs *alloc_vmcs_cpu(int cpu)
        struct page *pages;
        struct vmcs *vmcs;
-        pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
+        pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
        if (!pages)
                return NULL;
        vmcs = page_address(pages);
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index fdd30d08ab52..eefdeee8a871 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_X86_PTDUMP)	+= dump_pagetables.o
 obj-$(CONFIG_HIGHMEM)           += highmem_32.o
+obj-$(CONFIG_KMEMCHECK)         += kmemcheck/
 obj-$(CONFIG_MMIOTRACE)         += mmiotrace.o
 mmiotrace-y                     := kmmio.o pf_in.o mmio-mod.o
 obj-$(CONFIG_MMIOTRACE_TEST)    += testmmiotrace.o
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index c6acc6326374..baa0e86adfbc 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -14,6 +14,7 @@
 #include <asm/traps.h>                  /* dotraplinkage, ...           */
 #include <asm/pgalloc.h>                /* pgd_*(), ...                 */
+#include <asm/kmemcheck.h>              /* kmemcheck_*(), ...           */
 /*
 * Page fault error code bits:
@@ -956,6 +957,13 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code)
        /* Get the faulting address: */
        address = read_cr2();
+        /*
+         * Detect and handle instructions that would cause a page fault for
+         * both a tracked kernel page and a userspace page.
+         */
+        if (kmemcheck_active(regs))
+                kmemcheck_hide(regs);
        if (unlikely(kmmio_fault(regs, address)))
                return;
@@ -973,9 +981,13 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code)
         * protection error (error_code & 9) == 0.
         */
        if (unlikely(fault_in_kernel_space(address))) {
-                if (!(error_code & (PF_RSVD|PF_USER|PF_PROT)) &&
+                if (!(error_code & (PF_RSVD | PF_USER | PF_PROT))) {
-                    vmalloc_fault(address) >= 0)
+                        if (vmalloc_fault(address) >= 0)
-                        return;
+                                return;
+                        if (kmemcheck_fault(regs, address, error_code))
+                                return;
+                }
                /* Can handle a stale RO->RW TLB: */
                if (spurious_fault(error_code, address))
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 34c1bfb64f1c..f53b57e4086f 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -213,7 +213,7 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
        if (!after_bootmem)
                init_gbpages();
-#ifdef CONFIG_DEBUG_PAGEALLOC
+#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KMEMCHECK)
        /*
         * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages.
         * This will simplify cpa(), which otherwise needs to support splitting
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 9ff3c0816d15..3cd7711bb949 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -111,7 +111,7 @@ static pte_t * __init one_page_table_init(pmd_t *pmd)
                pte_t *page_table = NULL;
                if (after_bootmem) {
-#ifdef CONFIG_DEBUG_PAGEALLOC
+#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KMEMCHECK)
                        page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE);
 #endif
                        if (!page_table)
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 52bb9519bb86..9c543290a813 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -104,7 +104,7 @@ static __ref void *spp_getpage(void)
        void *ptr;
        if (after_bootmem)
-                ptr = (void *) get_zeroed_page(GFP_ATOMIC);
+                ptr = (void *) get_zeroed_page(GFP_ATOMIC | __GFP_NOTRACK);
        else
                ptr = alloc_bootmem_pages(PAGE_SIZE);
@@ -281,7 +281,7 @@ static __ref void *alloc_low_page(unsigned long *phys)
        void *adr;
        if (after_bootmem) {
-                adr = (void *)get_zeroed_page(GFP_ATOMIC);
+                adr = (void *)get_zeroed_page(GFP_ATOMIC | __GFP_NOTRACK);
                *phys = __pa(adr);
                return adr;
diff --git a/arch/x86/mm/kmemcheck/Makefile b/arch/x86/mm/kmemcheck/Makefile
new file mode 100644
index 000000000000..520b3bce4095
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/Makefile
@@ -0,0 +1 @@
+obj-y := error.o kmemcheck.o opcode.o pte.o selftest.o shadow.o
diff --git a/arch/x86/mm/kmemcheck/error.c b/arch/x86/mm/kmemcheck/error.c
new file mode 100644
index 000000000000..4901d0dafda6
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/error.c
@@ -0,0 +1,228 @@
+#include <linux/interrupt.h>
+#include <linux/kdebug.h>
+#include <linux/kmemcheck.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/stacktrace.h>
+#include <linux/string.h>
+#include "error.h"
+#include "shadow.h"
+enum kmemcheck_error_type {
+        KMEMCHECK_ERROR_INVALID_ACCESS,
+        KMEMCHECK_ERROR_BUG,
+};
+#define SHADOW_COPY_SIZE (1 << CONFIG_KMEMCHECK_SHADOW_COPY_SHIFT)
+struct kmemcheck_error {
+        enum kmemcheck_error_type type;
+        union {
+                /* KMEMCHECK_ERROR_INVALID_ACCESS */
+                struct {
+                        /* Kind of access that caused the error */
+                        enum kmemcheck_shadow state;
+                        /* Address and size of the erroneous read */
+                        unsigned long   address;
+                        unsigned int    size;
+                };
+        };
+        struct pt_regs          regs;
+        struct stack_trace      trace;
+        unsigned long           trace_entries[32];
+        /* We compress it to a char. */
+        unsigned char           shadow_copy[SHADOW_COPY_SIZE];
+        unsigned char           memory_copy[SHADOW_COPY_SIZE];
+};
+/*
+ * Create a ring queue of errors to output. We can't call printk() directly
+ * from the kmemcheck traps, since this may call the console drivers and
+ * result in a recursive fault.
+ */
+static struct kmemcheck_error error_fifo[CONFIG_KMEMCHECK_QUEUE_SIZE];
+static unsigned int error_count;
+static unsigned int error_rd;
+static unsigned int error_wr;
+static unsigned int error_missed_count;
+static struct kmemcheck_error *error_next_wr(void)
+{
+        struct kmemcheck_error *e;
+        if (error_count == ARRAY_SIZE(error_fifo)) {
+                ++error_missed_count;
+                return NULL;
+        }
+        e = &error_fifo[error_wr];
+        if (++error_wr == ARRAY_SIZE(error_fifo))
+                error_wr = 0;
+        ++error_count;
+        return e;
+}
+static struct kmemcheck_error *error_next_rd(void)
+{
+        struct kmemcheck_error *e;
+        if (error_count == 0)
+                return NULL;
+        e = &error_fifo[error_rd];
+        if (++error_rd == ARRAY_SIZE(error_fifo))
+                error_rd = 0;
+        --error_count;
+        return e;
+}
+void kmemcheck_error_recall(void)
+{
+        static const char *desc[] = {
+                [KMEMCHECK_SHADOW_UNALLOCATED]          = "unallocated",
+                [KMEMCHECK_SHADOW_UNINITIALIZED]        = "uninitialized",
+                [KMEMCHECK_SHADOW_INITIALIZED]          = "initialized",
+                [KMEMCHECK_SHADOW_FREED]                = "freed",
+        };
+        static const char short_desc[] = {
+                [KMEMCHECK_SHADOW_UNALLOCATED]          = 'a',
+                [KMEMCHECK_SHADOW_UNINITIALIZED]        = 'u',
+                [KMEMCHECK_SHADOW_INITIALIZED]          = 'i',
+                [KMEMCHECK_SHADOW_FREED]                = 'f',
+        };
+        struct kmemcheck_error *e;
+        unsigned int i;
+        e = error_next_rd();
+        if (!e)
+                return;
+        switch (e->type) {
+        case KMEMCHECK_ERROR_INVALID_ACCESS:
+                printk(KERN_ERR  "WARNING: kmemcheck: Caught %d-bit read "
+                        "from %s memory (%p)\n",
+                        8 * e->size, e->state < ARRAY_SIZE(desc) ?
+                                desc[e->state] : "(invalid shadow state)",
+                        (void *) e->address);
+                printk(KERN_INFO);
+                for (i = 0; i < SHADOW_COPY_SIZE; ++i)
+                        printk("%02x", e->memory_copy[i]);
+                printk("\n");
+                printk(KERN_INFO);
+                for (i = 0; i < SHADOW_COPY_SIZE; ++i) {
+                        if (e->shadow_copy[i] < ARRAY_SIZE(short_desc))
+                                printk(" %c", short_desc[e->shadow_copy[i]]);
+                        else
+                                printk(" ?");
+                }
+                printk("\n");
+                printk(KERN_INFO "%*c\n", 2 + 2
+                        * (int) (e->address & (SHADOW_COPY_SIZE - 1)), '^');
+                break;
+        case KMEMCHECK_ERROR_BUG:
+                printk(KERN_EMERG "ERROR: kmemcheck: Fatal error\n");
+                break;
+        }
+        __show_regs(&e->regs, 1);
+        print_stack_trace(&e->trace, 0);
+}
+static void do_wakeup(unsigned long data)
+{
+        while (error_count > 0)
+                kmemcheck_error_recall();
+        if (error_missed_count > 0) {
+                printk(KERN_WARNING "kmemcheck: Lost %d error reports because "
+                        "the queue was too small\n", error_missed_count);
+                error_missed_count = 0;
+        }
+}
+static DECLARE_TASKLET(kmemcheck_tasklet, &do_wakeup, 0);
+/*
+ * Save the context of an error report.
+ */
+void kmemcheck_error_save(enum kmemcheck_shadow state,
+        unsigned long address, unsigned int size, struct pt_regs *regs)
+{
+        static unsigned long prev_ip;
+        struct kmemcheck_error *e;
+        void *shadow_copy;
+        void *memory_copy;
+        /* Don't report several adjacent errors from the same EIP. */
+        if (regs->ip == prev_ip)
+                return;
+        prev_ip = regs->ip;
+        e = error_next_wr();
+        if (!e)
+                return;
+        e->type = KMEMCHECK_ERROR_INVALID_ACCESS;
+        e->state = state;
+        e->address = address;
+        e->size = size;
+        /* Save regs */
+        memcpy(&e->regs, regs, sizeof(*regs));
+        /* Save stack trace */
+        e->trace.nr_entries = 0;
+        e->trace.entries = e->trace_entries;
+        e->trace.max_entries = ARRAY_SIZE(e->trace_entries);
+        e->trace.skip = 0;
+        save_stack_trace_bp(&e->trace, regs->bp);
+        /* Round address down to nearest 16 bytes */
+        shadow_copy = kmemcheck_shadow_lookup(address
+                & ~(SHADOW_COPY_SIZE - 1));
+        BUG_ON(!shadow_copy);
+        memcpy(e->shadow_copy, shadow_copy, SHADOW_COPY_SIZE);
+        kmemcheck_show_addr(address);
+        memory_copy = (void *) (address & ~(SHADOW_COPY_SIZE - 1));
+        memcpy(e->memory_copy, memory_copy, SHADOW_COPY_SIZE);
+        kmemcheck_hide_addr(address);
+        tasklet_hi_schedule_first(&kmemcheck_tasklet);
+}
+/*
+ * Save the context of a kmemcheck bug.
+ */
+void kmemcheck_error_save_bug(struct pt_regs *regs)
+{
+        struct kmemcheck_error *e;
+        e = error_next_wr();
+        if (!e)
+                return;
+        e->type = KMEMCHECK_ERROR_BUG;
+        memcpy(&e->regs, regs, sizeof(*regs));
+        e->trace.nr_entries = 0;
+        e->trace.entries = e->trace_entries;
+        e->trace.max_entries = ARRAY_SIZE(e->trace_entries);
+        e->trace.skip = 1;
+        save_stack_trace(&e->trace);
+        tasklet_hi_schedule_first(&kmemcheck_tasklet);
+}
diff --git a/arch/x86/mm/kmemcheck/error.h b/arch/x86/mm/kmemcheck/error.h
new file mode 100644
index 000000000000..0efc2e8d0a20
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/error.h
@@ -0,0 +1,15 @@
+#ifndef ARCH__X86__MM__KMEMCHECK__ERROR_H
+#define ARCH__X86__MM__KMEMCHECK__ERROR_H
+#include <linux/ptrace.h>
+#include "shadow.h"
+void kmemcheck_error_save(enum kmemcheck_shadow state,
+        unsigned long address, unsigned int size, struct pt_regs *regs);
+void kmemcheck_error_save_bug(struct pt_regs *regs);
+void kmemcheck_error_recall(void);
+#endif
diff --git a/arch/x86/mm/kmemcheck/kmemcheck.c b/arch/x86/mm/kmemcheck/kmemcheck.c
new file mode 100644
index 000000000000..2c55ed098654
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/kmemcheck.c
@@ -0,0 +1,640 @@
+/**
+ * kmemcheck - a heavyweight memory checker for the linux kernel
+ * Copyright (C) 2007, 2008  Vegard Nossum <vegardno@ifi.uio.no>
+ * (With a lot of help from Ingo Molnar and Pekka Enberg.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2) as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kallsyms.h>
+#include <linux/kernel.h>
+#include <linux/kmemcheck.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/page-flags.h>
+#include <linux/percpu.h>
+#include <linux/ptrace.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/cacheflush.h>
+#include <asm/kmemcheck.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+#include "error.h"
+#include "opcode.h"
+#include "pte.h"
+#include "selftest.h"
+#include "shadow.h"
+#ifdef CONFIG_KMEMCHECK_DISABLED_BY_DEFAULT
+#  define KMEMCHECK_ENABLED 0
+#endif
+#ifdef CONFIG_KMEMCHECK_ENABLED_BY_DEFAULT
+#  define KMEMCHECK_ENABLED 1
+#endif
+#ifdef CONFIG_KMEMCHECK_ONESHOT_BY_DEFAULT
+#  define KMEMCHECK_ENABLED 2
+#endif
+int kmemcheck_enabled = KMEMCHECK_ENABLED;
+int __init kmemcheck_init(void)
+{
+#ifdef CONFIG_SMP
+        /*
+         * Limit SMP to use a single CPU. We rely on the fact that this code
+         * runs before SMP is set up.
+         */
+        if (setup_max_cpus > 1) {
+                printk(KERN_INFO
+                        "kmemcheck: Limiting number of CPUs to 1.\n");
+                setup_max_cpus = 1;
+        }
+#endif
+        if (!kmemcheck_selftest()) {
+                printk(KERN_INFO "kmemcheck: self-tests failed; disabling\n");
+                kmemcheck_enabled = 0;
+                return -EINVAL;
+        }
+        printk(KERN_INFO "kmemcheck: Initialized\n");
+        return 0;
+}
+early_initcall(kmemcheck_init);
+/*
+ * We need to parse the kmemcheck= option before any memory is allocated.
+ */
+static int __init param_kmemcheck(char *str)
+{
+        if (!str)
+                return -EINVAL;
+        sscanf(str, "%d", &kmemcheck_enabled);
+        return 0;
+}
+early_param("kmemcheck", param_kmemcheck);
+int kmemcheck_show_addr(unsigned long address)
+{
+        pte_t *pte;
+        pte = kmemcheck_pte_lookup(address);
+        if (!pte)
+                return 0;
+        set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT));
+        __flush_tlb_one(address);
+        return 1;
+}
+int kmemcheck_hide_addr(unsigned long address)
+{
+        pte_t *pte;
+        pte = kmemcheck_pte_lookup(address);
+        if (!pte)
+                return 0;
+        set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT));
+        __flush_tlb_one(address);
+        return 1;
+}
+struct kmemcheck_context {
+        bool busy;
+        int balance;
+        /*
+         * There can be at most two memory operands to an instruction, but
+         * each address can cross a page boundary -- so we may need up to
+         * four addresses that must be hidden/revealed for each fault.
+         */
+        unsigned long addr[4];
+        unsigned long n_addrs;
+        unsigned long flags;
+        /* Data size of the instruction that caused a fault. */
+        unsigned int size;
+};
+static DEFINE_PER_CPU(struct kmemcheck_context, kmemcheck_context);
+bool kmemcheck_active(struct pt_regs *regs)
+{
+        struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
+        return data->balance > 0;
+}
+/* Save an address that needs to be shown/hidden */
+static void kmemcheck_save_addr(unsigned long addr)
+{
+        struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
+        BUG_ON(data->n_addrs >= ARRAY_SIZE(data->addr));
+        data->addr[data->n_addrs++] = addr;
+}
+static unsigned int kmemcheck_show_all(void)
+{
+        struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
+        unsigned int i;
+        unsigned int n;
+        n = 0;
+        for (i = 0; i < data->n_addrs; ++i)
+                n += kmemcheck_show_addr(data->addr[i]);
+        return n;
+}
+static unsigned int kmemcheck_hide_all(void)
+{
+        struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
+        unsigned int i;
+        unsigned int n;
+        n = 0;
+        for (i = 0; i < data->n_addrs; ++i)
+                n += kmemcheck_hide_addr(data->addr[i]);
+        return n;
+}
+/*
+ * Called from the #PF handler.
+ */
+void kmemcheck_show(struct pt_regs *regs)
+{
+        struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
+        BUG_ON(!irqs_disabled());
+        if (unlikely(data->balance != 0)) {
+                kmemcheck_show_all();
+                kmemcheck_error_save_bug(regs);
+                data->balance = 0;
+                return;
+        }
+        /*
+         * None of the addresses actually belonged to kmemcheck. Note that
+         * this is not an error.
+         */
+        if (kmemcheck_show_all() == 0)
+                return;
+        ++data->balance;
+        /*
+         * The IF needs to be cleared as well, so that the faulting
+         * instruction can run "uninterrupted". Otherwise, we might take
+         * an interrupt and start executing that before we've had a chance
+         * to hide the page again.
+         *
+         * NOTE: In the rare case of multiple faults, we must not override
+         * the original flags:
+         */
+        if (!(regs->flags & X86_EFLAGS_TF))
+                data->flags = regs->flags;
+        regs->flags |= X86_EFLAGS_TF;
+        regs->flags &= ~X86_EFLAGS_IF;
+}
+/*
+ * Called from the #DB handler.
+ */
+void kmemcheck_hide(struct pt_regs *regs)
+{
+        struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
+        int n;
+        BUG_ON(!irqs_disabled());
+        if (data->balance == 0)
+                return;
+        if (unlikely(data->balance != 1)) {
+                kmemcheck_show_all();
+                kmemcheck_error_save_bug(regs);
+                data->n_addrs = 0;
+                data->balance = 0;
+                if (!(data->flags & X86_EFLAGS_TF))
+                        regs->flags &= ~X86_EFLAGS_TF;
+                if (data->flags & X86_EFLAGS_IF)
+                        regs->flags |= X86_EFLAGS_IF;
+                return;
+        }
+        if (kmemcheck_enabled)
+                n = kmemcheck_hide_all();
+        else
+                n = kmemcheck_show_all();
+        if (n == 0)
+                return;
+        --data->balance;
+        data->n_addrs = 0;
+        if (!(data->flags & X86_EFLAGS_TF))
+                regs->flags &= ~X86_EFLAGS_TF;
+        if (data->flags & X86_EFLAGS_IF)
+                regs->flags |= X86_EFLAGS_IF;
+}
+void kmemcheck_show_pages(struct page *p, unsigned int n)
+{
+        unsigned int i;
+        for (i = 0; i < n; ++i) {
+                unsigned long address;
+                pte_t *pte;
+                unsigned int level;
+                address = (unsigned long) page_address(&p[i]);
+                pte = lookup_address(address, &level);
+                BUG_ON(!pte);
+                BUG_ON(level != PG_LEVEL_4K);
+                set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT));
+                set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_HIDDEN));
+                __flush_tlb_one(address);
+        }
+}
+bool kmemcheck_page_is_tracked(struct page *p)
+{
+        /* This will also check the "hidden" flag of the PTE. */
+        return kmemcheck_pte_lookup((unsigned long) page_address(p));
+}
+void kmemcheck_hide_pages(struct page *p, unsigned int n)
+{
+        unsigned int i;
+        for (i = 0; i < n; ++i) {
+                unsigned long address;
+                pte_t *pte;
+                unsigned int level;
+                address = (unsigned long) page_address(&p[i]);
+                pte = lookup_address(address, &level);
+                BUG_ON(!pte);
+                BUG_ON(level != PG_LEVEL_4K);
+                set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT));
+                set_pte(pte, __pte(pte_val(*pte) | _PAGE_HIDDEN));
+                __flush_tlb_one(address);
+        }
+}
+/* Access may NOT cross page boundary */
+static void kmemcheck_read_strict(struct pt_regs *regs,
+        unsigned long addr, unsigned int size)
+{
+        void *shadow;
+        enum kmemcheck_shadow status;
+        shadow = kmemcheck_shadow_lookup(addr);
+        if (!shadow)
+                return;
+        kmemcheck_save_addr(addr);
+        status = kmemcheck_shadow_test(shadow, size);
+        if (status == KMEMCHECK_SHADOW_INITIALIZED)
+                return;
+        if (kmemcheck_enabled)
+                kmemcheck_error_save(status, addr, size, regs);
+        if (kmemcheck_enabled == 2)
+                kmemcheck_enabled = 0;
+        /* Don't warn about it again. */
+        kmemcheck_shadow_set(shadow, size);
+}
+/* Access may cross page boundary */
+static void kmemcheck_read(struct pt_regs *regs,
+        unsigned long addr, unsigned int size)
+{
+        unsigned long page = addr & PAGE_MASK;
+        unsigned long next_addr = addr + size - 1;
+        unsigned long next_page = next_addr & PAGE_MASK;
+        if (likely(page == next_page)) {
+                kmemcheck_read_strict(regs, addr, size);
+                return;
+        }
+        /*
+         * What we do is basically to split the access across the
+         * two pages and handle each part separately. Yes, this means
+         * that we may now see reads that are 3 + 5 bytes, for
+         * example (and if both are uninitialized, there will be two
+         * reports), but it makes the code a lot simpler.
+         */
+        kmemcheck_read_strict(regs, addr, next_page - addr);
+        kmemcheck_read_strict(regs, next_page, next_addr - next_page);
+}
+static void kmemcheck_write_strict(struct pt_regs *regs,
+        unsigned long addr, unsigned int size)
+{
+        void *shadow;
+        shadow = kmemcheck_shadow_lookup(addr);
+        if (!shadow)
+                return;
+        kmemcheck_save_addr(addr);
+        kmemcheck_shadow_set(shadow, size);
+}
+static void kmemcheck_write(struct pt_regs *regs,
+        unsigned long addr, unsigned int size)
+{
+        unsigned long page = addr & PAGE_MASK;
+        unsigned long next_addr = addr + size - 1;
+        unsigned long next_page = next_addr & PAGE_MASK;
+        if (likely(page == next_page)) {
+                kmemcheck_write_strict(regs, addr, size);
+                return;
+        }
+        /* See comment in kmemcheck_read(). */
+        kmemcheck_write_strict(regs, addr, next_page - addr);
+        kmemcheck_write_strict(regs, next_page, next_addr - next_page);
+}
+/*
+ * Copying is hard. We have two addresses, each of which may be split across
+ * a page (and each page will have different shadow addresses).
+ */
+static void kmemcheck_copy(struct pt_regs *regs,
+        unsigned long src_addr, unsigned long dst_addr, unsigned int size)
+{
+        uint8_t shadow[8];
+        enum kmemcheck_shadow status;
+        unsigned long page;
+        unsigned long next_addr;
+        unsigned long next_page;
+        uint8_t *x;
+        unsigned int i;
+        unsigned int n;
+        BUG_ON(size > sizeof(shadow));
+        page = src_addr & PAGE_MASK;
+        next_addr = src_addr + size - 1;
+        next_page = next_addr & PAGE_MASK;
+        if (likely(page == next_page)) {
+                /* Same page */
+                x = kmemcheck_shadow_lookup(src_addr);
+                if (x) {
+                        kmemcheck_save_addr(src_addr);
+                        for (i = 0; i < size; ++i)
+                                shadow[i] = x[i];
+                } else {
+                        for (i = 0; i < size; ++i)
+                                shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
+                }
+        } else {
+                n = next_page - src_addr;
+                BUG_ON(n > sizeof(shadow));
+                /* First page */
+                x = kmemcheck_shadow_lookup(src_addr);
+                if (x) {
+                        kmemcheck_save_addr(src_addr);
+                        for (i = 0; i < n; ++i)
+                                shadow[i] = x[i];
+                } else {
+                        /* Not tracked */
+                        for (i = 0; i < n; ++i)
+                                shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
+                }
+                /* Second page */
+                x = kmemcheck_shadow_lookup(next_page);
+                if (x) {
+                        kmemcheck_save_addr(next_page);
+                        for (i = n; i < size; ++i)
+                                shadow[i] = x[i - n];
+                } else {
+                        /* Not tracked */
+                        for (i = n; i < size; ++i)
+                                shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
+                }
+        }
+        page = dst_addr & PAGE_MASK;
+        next_addr = dst_addr + size - 1;
+        next_page = next_addr & PAGE_MASK;
+        if (likely(page == next_page)) {
+                /* Same page */
+                x = kmemcheck_shadow_lookup(dst_addr);
+                if (x) {
+                        kmemcheck_save_addr(dst_addr);
+                        for (i = 0; i < size; ++i) {
+                                x[i] = shadow[i];
+                                shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
+                        }
+                }
+        } else {
+                n = next_page - dst_addr;
+                BUG_ON(n > sizeof(shadow));
+                /* First page */
+                x = kmemcheck_shadow_lookup(dst_addr);
+                if (x) {
+                        kmemcheck_save_addr(dst_addr);
+                        for (i = 0; i < n; ++i) {
+                                x[i] = shadow[i];
+                                shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
+                        }
+                }
+                /* Second page */
+                x = kmemcheck_shadow_lookup(next_page);
+                if (x) {
+                        kmemcheck_save_addr(next_page);
+                        for (i = n; i < size; ++i) {
+                                x[i - n] = shadow[i];
+                                shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
+                        }
+                }
+        }
+        status = kmemcheck_shadow_test(shadow, size);
+        if (status == KMEMCHECK_SHADOW_INITIALIZED)
+                return;
+        if (kmemcheck_enabled)
+                kmemcheck_error_save(status, src_addr, size, regs);
+        if (kmemcheck_enabled == 2)
+                kmemcheck_enabled = 0;
+}
+enum kmemcheck_method {
+        KMEMCHECK_READ,
+        KMEMCHECK_WRITE,
+};
+static void kmemcheck_access(struct pt_regs *regs,
+        unsigned long fallback_address, enum kmemcheck_method fallback_method)
+{
+        const uint8_t *insn;
+        const uint8_t *insn_primary;
+        unsigned int size;
+        struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
+        /* Recursive fault -- ouch. */
+        if (data->busy) {
+                kmemcheck_show_addr(fallback_address);
+                kmemcheck_error_save_bug(regs);
+                return;
+        }
+        data->busy = true;
+        insn = (const uint8_t *) regs->ip;
+        insn_primary = kmemcheck_opcode_get_primary(insn);
+        kmemcheck_opcode_decode(insn, &size);
+        switch (insn_primary[0]) {
+#ifdef CONFIG_KMEMCHECK_BITOPS_OK
+                /* AND, OR, XOR */
+                /*
+                 * Unfortunately, these instructions have to be excluded from
+                 * our regular checking since they access only some (and not
+                 * all) bits. This clears out "bogus" bitfield-access warnings.
+                 */
+        case 0x80:
+        case 0x81:
+        case 0x82:
+        case 0x83:
+                switch ((insn_primary[1] >> 3) & 7) {
+                        /* OR */
+                case 1:
+                        /* AND */
+                case 4:
+                        /* XOR */
+                case 6:
+                        kmemcheck_write(regs, fallback_address, size);
+                        goto out;
+                        /* ADD */
+                case 0:
+                        /* ADC */
+                case 2:
+                        /* SBB */
+                case 3:
+                        /* SUB */
+                case 5:
+                        /* CMP */
+                case 7:
+                        break;
+                }
+                break;
+#endif
+                /* MOVS, MOVSB, MOVSW, MOVSD */
+        case 0xa4:
+        case 0xa5:
+                /*
+                 * These instructions are special because they take two
+                 * addresses, but we only get one page fault.
+                 */
+                kmemcheck_copy(regs, regs->si, regs->di, size);
+                goto out;
+                /* CMPS, CMPSB, CMPSW, CMPSD */
+        case 0xa6:
+        case 0xa7:
+                kmemcheck_read(regs, regs->si, size);
+                kmemcheck_read(regs, regs->di, size);
+                goto out;
+        }
+        /*
+         * If the opcode isn't special in any way, we use the data from the
+         * page fault handler to determine the address and type of memory
+         * access.
+         */
+        switch (fallback_method) {
+        case KMEMCHECK_READ:
+                kmemcheck_read(regs, fallback_address, size);
+                goto out;
+        case KMEMCHECK_WRITE:
+                kmemcheck_write(regs, fallback_address, size);
+                goto out;
+        }
+out:
+        data->busy = false;
+}
+bool kmemcheck_fault(struct pt_regs *regs, unsigned long address,
+        unsigned long error_code)
+{
+        pte_t *pte;
+        /*
+         * XXX: Is it safe to assume that memory accesses from virtual 86
+         * mode or non-kernel code segments will _never_ access kernel
+         * memory (e.g. tracked pages)? For now, we need this to avoid
+         * invoking kmemcheck for PnP BIOS calls.
+         */
+        if (regs->flags & X86_VM_MASK)
+                return false;
+        if (regs->cs != __KERNEL_CS)
+                return false;
+        pte = kmemcheck_pte_lookup(address);
+        if (!pte)
+                return false;
+        if (error_code & 2)
+                kmemcheck_access(regs, address, KMEMCHECK_WRITE);
+        else
+                kmemcheck_access(regs, address, KMEMCHECK_READ);
+        kmemcheck_show(regs);
+        return true;
+}
+bool kmemcheck_trap(struct pt_regs *regs)
+{
+        if (!kmemcheck_active(regs))
+                return false;
+        /* We're done. */
+        kmemcheck_hide(regs);
+        return true;
+}
diff --git a/arch/x86/mm/kmemcheck/opcode.c b/arch/x86/mm/kmemcheck/opcode.c
new file mode 100644
index 000000000000..63c19e27aa6f
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/opcode.c
@@ -0,0 +1,106 @@
+#include <linux/types.h>
+#include "opcode.h"
+static bool opcode_is_prefix(uint8_t b)
+{
+        return
+                /* Group 1 */
+                b == 0xf0 || b == 0xf2 || b == 0xf3
+                /* Group 2 */
+                || b == 0x2e || b == 0x36 || b == 0x3e || b == 0x26
+                || b == 0x64 || b == 0x65 || b == 0x2e || b == 0x3e
+                /* Group 3 */
+                || b == 0x66
+                /* Group 4 */
+                || b == 0x67;
+}
+#ifdef CONFIG_X86_64
+static bool opcode_is_rex_prefix(uint8_t b)
+{
+        return (b & 0xf0) == 0x40;
+}
+#else
+static bool opcode_is_rex_prefix(uint8_t b)
+{
+        return false;
+}
+#endif
+#define REX_W (1 << 3)
+/*
+ * This is a VERY crude opcode decoder. We only need to find the size of the
+ * load/store that caused our #PF and this should work for all the opcodes
+ * that we care about. Moreover, the ones who invented this instruction set
+ * should be shot.
+ */
+void kmemcheck_opcode_decode(const uint8_t *op, unsigned int *size)
+{
+        /* Default operand size */
+        int operand_size_override = 4;
+        /* prefixes */
+        for (; opcode_is_prefix(*op); ++op) {
+                if (*op == 0x66)
+                        operand_size_override = 2;
+        }
+        /* REX prefix */
+        if (opcode_is_rex_prefix(*op)) {
+                uint8_t rex = *op;
+                ++op;
+                if (rex & REX_W) {
+                        switch (*op) {
+                        case 0x63:
+                                *size = 4;
+                                return;
+                        case 0x0f:
+                                ++op;
+                                switch (*op) {
+                                case 0xb6:
+                                case 0xbe:
+                                        *size = 1;
+                                        return;
+                                case 0xb7:
+                                case 0xbf:
+                                        *size = 2;
+                                        return;
+                                }
+                                break;
+                        }
+                        *size = 8;
+                        return;
+                }
+        }
+        /* escape opcode */
+        if (*op == 0x0f) {
+                ++op;
+                /*
+                 * This is move with zero-extend and sign-extend, respectively;
+                 * we don't have to think about 0xb6/0xbe, because this is
+                 * already handled in the conditional below.
+                 */
+                if (*op == 0xb7 || *op == 0xbf)
+                        operand_size_override = 2;
+        }
+        *size = (*op & 1) ? operand_size_override : 1;
+}
+const uint8_t *kmemcheck_opcode_get_primary(const uint8_t *op)
+{
+        /* skip prefixes */
+        while (opcode_is_prefix(*op))
+                ++op;
+        if (opcode_is_rex_prefix(*op))
+                ++op;
+        return op;
+}
diff --git a/arch/x86/mm/kmemcheck/opcode.h b/arch/x86/mm/kmemcheck/opcode.h
new file mode 100644
index 000000000000..6956aad66b5b
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/opcode.h
@@ -0,0 +1,9 @@
+#ifndef ARCH__X86__MM__KMEMCHECK__OPCODE_H
+#define ARCH__X86__MM__KMEMCHECK__OPCODE_H
+#include <linux/types.h>
+void kmemcheck_opcode_decode(const uint8_t *op, unsigned int *size);
+const uint8_t *kmemcheck_opcode_get_primary(const uint8_t *op);
+#endif
diff --git a/arch/x86/mm/kmemcheck/pte.c b/arch/x86/mm/kmemcheck/pte.c
new file mode 100644
index 000000000000..4ead26eeaf96
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/pte.c
@@ -0,0 +1,22 @@
+#include <linux/mm.h>
+#include <asm/pgtable.h>
+#include "pte.h"
+pte_t *kmemcheck_pte_lookup(unsigned long address)
+{
+        pte_t *pte;
+        unsigned int level;
+        pte = lookup_address(address, &level);
+        if (!pte)
+                return NULL;
+        if (level != PG_LEVEL_4K)
+                return NULL;
+        if (!pte_hidden(*pte))
+                return NULL;
+        return pte;
+}
diff --git a/arch/x86/mm/kmemcheck/pte.h b/arch/x86/mm/kmemcheck/pte.h
new file mode 100644
index 000000000000..9f5966456492
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/pte.h
@@ -0,0 +1,10 @@
+#ifndef ARCH__X86__MM__KMEMCHECK__PTE_H
+#define ARCH__X86__MM__KMEMCHECK__PTE_H
+#include <linux/mm.h>
+#include <asm/pgtable.h>
+pte_t *kmemcheck_pte_lookup(unsigned long address);
+#endif
diff --git a/arch/x86/mm/kmemcheck/selftest.c b/arch/x86/mm/kmemcheck/selftest.c
new file mode 100644
index 000000000000..036efbea8b28
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/selftest.c
@@ -0,0 +1,69 @@
+#include <linux/kernel.h>
+#include "opcode.h"
+#include "selftest.h"
+struct selftest_opcode {
+        unsigned int expected_size;
+        const uint8_t *insn;
+        const char *desc;
+};
+static const struct selftest_opcode selftest_opcodes[] = {
+        /* REP MOVS */
+        {1, "\xf3\xa4",                 "rep movsb <mem8>, <mem8>"},
+        {4, "\xf3\xa5",                 "rep movsl <mem32>, <mem32>"},
+        /* MOVZX / MOVZXD */
+        {1, "\x66\x0f\xb6\x51\xf8",     "movzwq <mem8>, <reg16>"},
+        {1, "\x0f\xb6\x51\xf8",         "movzwq <mem8>, <reg32>"},
+        /* MOVSX / MOVSXD */
+        {1, "\x66\x0f\xbe\x51\xf8",     "movswq <mem8>, <reg16>"},
+        {1, "\x0f\xbe\x51\xf8",         "movswq <mem8>, <reg32>"},
+#ifdef CONFIG_X86_64
+        /* MOVZX / MOVZXD */
+        {1, "\x49\x0f\xb6\x51\xf8",     "movzbq <mem8>, <reg64>"},
+        {2, "\x49\x0f\xb7\x51\xf8",     "movzbq <mem16>, <reg64>"},
+        /* MOVSX / MOVSXD */
+        {1, "\x49\x0f\xbe\x51\xf8",     "movsbq <mem8>, <reg64>"},
+        {2, "\x49\x0f\xbf\x51\xf8",     "movsbq <mem16>, <reg64>"},
+        {4, "\x49\x63\x51\xf8",         "movslq <mem32>, <reg64>"},
+#endif
+};
+static bool selftest_opcode_one(const struct selftest_opcode *op)
+{
+        unsigned size;
+        kmemcheck_opcode_decode(op->insn, &size);
+        if (size == op->expected_size)
+                return true;
+        printk(KERN_WARNING "kmemcheck: opcode %s: expected size %d, got %d\n",
+                op->desc, op->expected_size, size);
+        return false;
+}
+static bool selftest_opcodes_all(void)
+{
+        bool pass = true;
+        unsigned int i;
+        for (i = 0; i < ARRAY_SIZE(selftest_opcodes); ++i)
+                pass = pass && selftest_opcode_one(&selftest_opcodes[i]);
+        return pass;
+}
+bool kmemcheck_selftest(void)
+{
+        bool pass = true;
+        pass = pass && selftest_opcodes_all();
+        return pass;
+}
diff --git a/arch/x86/mm/kmemcheck/selftest.h b/arch/x86/mm/kmemcheck/selftest.h
new file mode 100644
index 000000000000..8fed4fe11f95
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/selftest.h
@@ -0,0 +1,6 @@
+#ifndef ARCH_X86_MM_KMEMCHECK_SELFTEST_H
+#define ARCH_X86_MM_KMEMCHECK_SELFTEST_H
+bool kmemcheck_selftest(void);
+#endif
diff --git a/arch/x86/mm/kmemcheck/shadow.c b/arch/x86/mm/kmemcheck/shadow.c
new file mode 100644
index 000000000000..e773b6bd0079
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/shadow.c
@@ -0,0 +1,162 @@
+#include <linux/kmemcheck.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include "pte.h"
+#include "shadow.h"
+/*
+ * Return the shadow address for the given address. Returns NULL if the
+ * address is not tracked.
+ *
+ * We need to be extremely careful not to follow any invalid pointers,
+ * because this function can be called for *any* possible address.
+ */
+void *kmemcheck_shadow_lookup(unsigned long address)
+{
+        pte_t *pte;
+        struct page *page;
+        if (!virt_addr_valid(address))
+                return NULL;
+        pte = kmemcheck_pte_lookup(address);
+        if (!pte)
+                return NULL;
+        page = virt_to_page(address);
+        if (!page->shadow)
+                return NULL;
+        return page->shadow + (address & (PAGE_SIZE - 1));
+}
+static void mark_shadow(void *address, unsigned int n,
+        enum kmemcheck_shadow status)
+{
+        unsigned long addr = (unsigned long) address;
+        unsigned long last_addr = addr + n - 1;
+        unsigned long page = addr & PAGE_MASK;
+        unsigned long last_page = last_addr & PAGE_MASK;
+        unsigned int first_n;
+        void *shadow;
+        /* If the memory range crosses a page boundary, stop there. */
+        if (page == last_page)
+                first_n = n;
+        else
+                first_n = page + PAGE_SIZE - addr;
+        shadow = kmemcheck_shadow_lookup(addr);
+        if (shadow)
+                memset(shadow, status, first_n);
+        addr += first_n;
+        n -= first_n;
+        /* Do full-page memset()s. */
+        while (n >= PAGE_SIZE) {
+                shadow = kmemcheck_shadow_lookup(addr);
+                if (shadow)
+                        memset(shadow, status, PAGE_SIZE);
+                addr += PAGE_SIZE;
+                n -= PAGE_SIZE;
+        }
+        /* Do the remaining page, if any. */
+        if (n > 0) {
+                shadow = kmemcheck_shadow_lookup(addr);
+                if (shadow)
+                        memset(shadow, status, n);
+        }
+}
+void kmemcheck_mark_unallocated(void *address, unsigned int n)
+{
+        mark_shadow(address, n, KMEMCHECK_SHADOW_UNALLOCATED);
+}
+void kmemcheck_mark_uninitialized(void *address, unsigned int n)
+{
+        mark_shadow(address, n, KMEMCHECK_SHADOW_UNINITIALIZED);
+}
+/*
+ * Fill the shadow memory of the given address such that the memory at that
+ * address is marked as being initialized.
+ */
+void kmemcheck_mark_initialized(void *address, unsigned int n)
+{
+        mark_shadow(address, n, KMEMCHECK_SHADOW_INITIALIZED);
+}
+EXPORT_SYMBOL_GPL(kmemcheck_mark_initialized);
+void kmemcheck_mark_freed(void *address, unsigned int n)
+{
+        mark_shadow(address, n, KMEMCHECK_SHADOW_FREED);
+}
+void kmemcheck_mark_unallocated_pages(struct page *p, unsigned int n)
+{
+        unsigned int i;
+        for (i = 0; i < n; ++i)
+                kmemcheck_mark_unallocated(page_address(&p[i]), PAGE_SIZE);
+}
+void kmemcheck_mark_uninitialized_pages(struct page *p, unsigned int n)
+{
+        unsigned int i;
+        for (i = 0; i < n; ++i)
+                kmemcheck_mark_uninitialized(page_address(&p[i]), PAGE_SIZE);
+}
+void kmemcheck_mark_initialized_pages(struct page *p, unsigned int n)
+{
+        unsigned int i;
+        for (i = 0; i < n; ++i)
+                kmemcheck_mark_initialized(page_address(&p[i]), PAGE_SIZE);
+}
+enum kmemcheck_shadow kmemcheck_shadow_test(void *shadow, unsigned int size)
+{
+        uint8_t *x;
+        unsigned int i;
+        x = shadow;
+#ifdef CONFIG_KMEMCHECK_PARTIAL_OK
+        /*
+         * Make sure _some_ bytes are initialized. Gcc frequently generates
+         * code to access neighboring bytes.
+         */
+        for (i = 0; i < size; ++i) {
+                if (x[i] == KMEMCHECK_SHADOW_INITIALIZED)
+                        return x[i];
+        }
+#else
+        /* All bytes must be initialized. */
+        for (i = 0; i < size; ++i) {
+                if (x[i] != KMEMCHECK_SHADOW_INITIALIZED)
+                        return x[i];
+        }
+#endif
+        return x[0];
+}
+void kmemcheck_shadow_set(void *shadow, unsigned int size)
+{
+        uint8_t *x;
+        unsigned int i;
+        x = shadow;
+        for (i = 0; i < size; ++i)
+                x[i] = KMEMCHECK_SHADOW_INITIALIZED;
+}
diff --git a/arch/x86/mm/kmemcheck/shadow.h b/arch/x86/mm/kmemcheck/shadow.h
new file mode 100644
index 000000000000..af46d9ab9d86
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/shadow.h
@@ -0,0 +1,16 @@
+#ifndef ARCH__X86__MM__KMEMCHECK__SHADOW_H
+#define ARCH__X86__MM__KMEMCHECK__SHADOW_H
+enum kmemcheck_shadow {
+        KMEMCHECK_SHADOW_UNALLOCATED,
+        KMEMCHECK_SHADOW_UNINITIALIZED,
+        KMEMCHECK_SHADOW_INITIALIZED,
+        KMEMCHECK_SHADOW_FREED,
+};
+void *kmemcheck_shadow_lookup(unsigned long address);
+enum kmemcheck_shadow kmemcheck_shadow_test(void *shadow, unsigned int size);
+void kmemcheck_shadow_set(void *shadow, unsigned int size);
+#endif
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 6ce9518fe2ac..3cfe9ced8a4c 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -470,7 +470,7 @@ static int split_large_page(pte_t *kpte, unsigned long address)
        if (!debug_pagealloc)
                spin_unlock(&cpa_lock);
-        base = alloc_pages(GFP_KERNEL, 0);
+        base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
        if (!debug_pagealloc)
                spin_lock(&cpa_lock);
        if (!base)
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 7aa03a5389f5..8e43bdd45456 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -4,9 +4,11 @@
 #include <asm/tlb.h>
 #include <asm/fixmap.h>
+#define PGALLOC_GFP GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO
 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 {
-        return (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
+        return (pte_t *)__get_free_page(PGALLOC_GFP);
 }
 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
@@ -14,9 +16,9 @@ pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
        struct page *pte;
 #ifdef CONFIG_HIGHPTE
-        pte = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM|__GFP_REPEAT|__GFP_ZERO, 0);
+        pte = alloc_pages(PGALLOC_GFP | __GFP_HIGHMEM, 0);
 #else
-        pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
+        pte = alloc_pages(PGALLOC_GFP, 0);
 #endif
        if (pte)
                pgtable_page_ctor(pte);
@@ -161,7 +163,7 @@ static int preallocate_pmds(pmd_t *pmds[])
        bool failed = false;
        for(i = 0; i < PREALLOCATED_PMDS; i++) {
-                pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
+                pmd_t *pmd = (pmd_t *)__get_free_page(PGALLOC_GFP);
                if (pmd == NULL)
                        failed = true;
                pmds[i] = pmd;
@@ -228,7 +230,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
        pmd_t *pmds[PREALLOCATED_PMDS];
        unsigned long flags;
-        pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
+        pgd = (pgd_t *)__get_free_page(PGALLOC_GFP);
        if (pgd == NULL)
                goto out;
diff --git a/arch/xtensa/include/asm/kmap_types.h b/arch/xtensa/include/asm/kmap_types.h
index 9e822d2e3bce..11c687e527f1 100644
--- a/arch/xtensa/include/asm/kmap_types.h
+++ b/arch/xtensa/include/asm/kmap_types.h
@@ -1,31 +1,6 @@
-/*
- * include/asm-xtensa/kmap_types.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
- */
 #ifndef _XTENSA_KMAP_TYPES_H
 #define _XTENSA_KMAP_TYPES_H
-enum km_type {
+#include <asm-generic/kmap_types.h>
-  KM_BOUNCE_READ,
-  KM_SKB_SUNRPC_DATA,
-  KM_SKB_DATA_SOFTIRQ,
-  KM_USER0,
-  KM_USER1,
-  KM_BIO_SRC_IRQ,
-  KM_BIO_DST_IRQ,
-  KM_PTE0,
-  KM_PTE1,
-  KM_IRQ0,
-  KM_IRQ1,
-  KM_SOFTIRQ0,
-  KM_SOFTIRQ1,
-  KM_TYPE_NR
-};
 #endif  /* _XTENSA_KMAP_TYPES_H */
diff --git a/arch/xtensa/kernel/init_task.c b/arch/xtensa/kernel/init_task.c
index e07f5c9fcd35..c4302f0e4ba0 100644
--- a/arch/xtensa/kernel/init_task.c
+++ b/arch/xtensa/kernel/init_task.c
@@ -23,10 +23,6 @@
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-EXPORT_SYMBOL(init_mm);
 union thread_union init_thread_union
        __attribute__((__section__(".data.init_task"))) =
 { INIT_THREAD_INFO(init_task) };