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-rw-r--r--arch/arm/mach-tegra/board-harmony-pinmux.c249
-rw-r--r--arch/arm/mach-tegra/board-paz00-pinmux.c249
-rw-r--r--arch/arm/mach-tegra/board-pinmux.c76
-rw-r--r--arch/arm/mach-tegra/board-pinmux.h35
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c314
-rw-r--r--arch/arm/mach-tegra/board-trimslice-pinmux.c252
-rw-r--r--arch/arm/mach-tegra/pinmux.c6
7 files changed, 606 insertions, 575 deletions
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 3ebe2c859a3b..83d420fbc58c 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-harmony-pinmux.c 2 * arch/arm/mach-tegra/board-harmony-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,136 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/of.h>
19
20#include <mach/pinmux.h>
21#include <mach/pinmux-tegra20.h>
22 19
23#include "board-harmony.h" 20#include "board-harmony.h"
24#include "board-pinmux.h" 21#include "board-pinmux.h"
25 22
26static struct tegra_pingroup_config harmony_pinmux[] = { 23static struct pinctrl_map harmony_map[] = {
27 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
28 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
29 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
30 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
31 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
32 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
33 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
34 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
35 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
36 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
37 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
38 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
39 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
40 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
41 {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 38 TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
42 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
43 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
44 {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 41 TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
45 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
47 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
48 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
49 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
50 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
51 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
52 {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 49 TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
53 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
54 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
55 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
56 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
57 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
58 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
59 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
60 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
61 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
63 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
65 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
66 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
67 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
68 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
84 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
85 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
86 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
87 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
90 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
91 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
92 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
93 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
94 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
95 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
96 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
97 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
98 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
99 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
102 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
105 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
106 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
107 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
108 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
109 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
110 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
111 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
112 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
113 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
114 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
115 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
116 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
117 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
118 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
119 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
120 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
121 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
122 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
123 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
124 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
126 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
127 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
128 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
129 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
130 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
131 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
132 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
133 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
134 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
135 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
136 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
137 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
138 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
139 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
140 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
141 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
142 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
140 TEGRA_MAP_CONF("ls", up, na),
141 TEGRA_MAP_CONF("lc", up, na),
142 TEGRA_MAP_CONF("ld17_0", down, na),
143 TEGRA_MAP_CONF("ld19_18", down, na),
144 TEGRA_MAP_CONF("ld21_20", down, na),
145 TEGRA_MAP_CONF("ld23_22", down, na),
143}; 146};
144 147
145static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
146 .pgs = harmony_pinmux, 149 .maps = harmony_map,
147 .pg_count = ARRAY_SIZE(harmony_pinmux), 150 .map_count = ARRAY_SIZE(harmony_map),
148}; 151};
149 152
150void harmony_pinmux_init(void) 153void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index f0ec46612f52..6f1111b48e7c 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-paz00-pinmux.c 2 * arch/arm/mach-tegra/board-paz00-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> 4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,136 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/of.h>
19
20#include <mach/pinmux.h>
21#include <mach/pinmux-tegra20.h>
22 19
23#include "board-paz00.h" 20#include "board-paz00.h"
24#include "board-pinmux.h" 21#include "board-pinmux.h"
25 22
26static struct tegra_pingroup_config paz00_pinmux[] = { 23static struct pinctrl_map paz00_map[] = {
27 {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
28 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
29 {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
30 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
31 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
32 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
33 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
34 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
35 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
36 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
37 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 34 TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
38 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
39 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
40 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
41 {TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
42 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
43 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
44 {TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
45 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
47 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
48 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
49 {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
50 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
51 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
52 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
53 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
54 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
55 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
56 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
57 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
58 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
59 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
60 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
61 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
63 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
65 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
66 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
67 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
68 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
84 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
85 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
86 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
87 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
88 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
89 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
90 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
91 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
92 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
93 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
95 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
96 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
97 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
98 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
99 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
102 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
104 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
105 {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
106 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
107 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
108 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
109 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
110 {TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 107 TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
111 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
112 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
113 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
114 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
115 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
116 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
117 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
118 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
119 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
120 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
121 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
122 {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
123 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
124 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
125 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
126 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
127 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
128 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
129 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
130 {TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
131 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
132 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
133 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
134 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
135 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
136 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
137 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
138 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
139 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
140 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
141 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
142 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
140 TEGRA_MAP_CONF("ls", up, na),
141 TEGRA_MAP_CONF("lc", up, na),
142 TEGRA_MAP_CONF("ld17_0", down, na),
143 TEGRA_MAP_CONF("ld19_18", down, na),
144 TEGRA_MAP_CONF("ld21_20", down, na),
145 TEGRA_MAP_CONF("ld23_22", down, na),
143}; 146};
144 147
145static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
146 .pgs = paz00_pinmux, 149 .maps = paz00_map,
147 .pg_count = ARRAY_SIZE(paz00_pinmux), 150 .map_count = ARRAY_SIZE(paz00_map),
148}; 151};
149 152
150void paz00_pinmux_init(void) 153void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index 3015b5a38936..3b7ad07fcbcb 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -18,47 +18,57 @@
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/string.h> 19#include <linux/string.h>
20 20
21#include <mach/pinmux.h>
22
23#include "board-pinmux.h" 21#include "board-pinmux.h"
24#include "devices.h" 22#include "devices.h"
25 23
26struct tegra_board_pinmux_conf *confs[2]; 24unsigned long tegra_pincfg_pullnone_driven[2] = {
25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
26 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
27};
27 28
28static void tegra_board_pinmux_setup_pinmux(void) 29unsigned long tegra_pincfg_pullnone_tristate[2] = {
29{ 30 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
30 int i; 31 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
32};
31 33
32 for (i = 0; i < ARRAY_SIZE(confs); i++) { 34unsigned long tegra_pincfg_pullnone_na[1] = {
33 if (!confs[i]) 35 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
34 continue; 36};
35 37
36 tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count); 38unsigned long tegra_pincfg_pullup_driven[2] = {
39 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
40 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
41};
37 42
38 if (confs[i]->drives) 43unsigned long tegra_pincfg_pullup_tristate[2] = {
39 tegra_drive_pinmux_config_table(confs[i]->drives, 44 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
40 confs[i]->drive_count); 45 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
41 } 46};
42}
43 47
44static int tegra_board_pinmux_bus_notify(struct notifier_block *nb, 48unsigned long tegra_pincfg_pullup_na[1] = {
45 unsigned long event, void *vdev) 49 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
46{ 50};
47 struct device *dev = vdev;
48 51
49 if (event != BUS_NOTIFY_BOUND_DRIVER) 52unsigned long tegra_pincfg_pulldown_driven[2] = {
50 return NOTIFY_DONE; 53 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
54 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
55};
51 56
52 if (strcmp(dev_name(dev), PINMUX_DEV)) 57unsigned long tegra_pincfg_pulldown_tristate[2] = {
53 return NOTIFY_DONE; 58 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
59 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
60};
54 61
55 tegra_board_pinmux_setup_pinmux(); 62unsigned long tegra_pincfg_pulldown_na[1] = {
63 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
64};
56 65
57 return NOTIFY_STOP_MASK; 66unsigned long tegra_pincfg_pullna_driven[1] = {
58} 67 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
68};
59 69
60static struct notifier_block nb = { 70unsigned long tegra_pincfg_pullna_tristate[1] = {
61 .notifier_call = tegra_board_pinmux_bus_notify, 71 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
62}; 72};
63 73
64static struct platform_device *devices[] = { 74static struct platform_device *devices[] = {
@@ -69,10 +79,10 @@ static struct platform_device *devices[] = {
69void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 79void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
70 struct tegra_board_pinmux_conf *conf_b) 80 struct tegra_board_pinmux_conf *conf_b)
71{ 81{
72 confs[0] = conf_a; 82 if (conf_a)
73 confs[1] = conf_b; 83 pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
74 84 if (conf_b)
75 bus_register_notifier(&platform_bus_type, &nb); 85 pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
76 86
77 if (!of_machine_is_compatible("nvidia,tegra20")) 87 if (!of_machine_is_compatible("nvidia,tegra20"))
78 platform_add_devices(devices, ARRAY_SIZE(devices)); 88 platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index e08214d84bd9..45b5ad8dc6de 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -15,16 +15,37 @@
15#ifndef __MACH_TEGRA_BOARD_PINMUX_H 15#ifndef __MACH_TEGRA_BOARD_PINMUX_H
16#define __MACH_TEGRA_BOARD_PINMUX_H 16#define __MACH_TEGRA_BOARD_PINMUX_H
17 17
18#include <linux/pinctrl/machine.h>
19
20#include <mach/pinconf-tegra.h>
21
18#define PINMUX_DEV "tegra-pinmux" 22#define PINMUX_DEV "tegra-pinmux"
19 23
20struct tegra_pingroup_config; 24#define TEGRA_MAP_MUX(_group_, _function_) \
25 PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
21 26
22struct tegra_board_pinmux_conf { 27#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
23 struct tegra_pingroup_config *pgs; 28 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
24 int pg_count;
25 29
26 struct tegra_drive_pingroup_config *drives; 30#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
27 int drive_count; 31 TEGRA_MAP_MUX(_group_, _function_), \
32 TEGRA_MAP_CONF(_group_, _pull_, _drive_)
33
34extern unsigned long tegra_pincfg_pullnone_driven[2];
35extern unsigned long tegra_pincfg_pullnone_tristate[2];
36extern unsigned long tegra_pincfg_pullnone_na[1];
37extern unsigned long tegra_pincfg_pullup_driven[2];
38extern unsigned long tegra_pincfg_pullup_tristate[2];
39extern unsigned long tegra_pincfg_pullup_na[1];
40extern unsigned long tegra_pincfg_pulldown_driven[2];
41extern unsigned long tegra_pincfg_pulldown_tristate[2];
42extern unsigned long tegra_pincfg_pulldown_na[1];
43extern unsigned long tegra_pincfg_pullna_driven[1];
44extern unsigned long tegra_pincfg_pullna_tristate[1];
45
46struct tegra_board_pinmux_conf {
47 struct pinctrl_map *maps;
48 int map_count;
28}; 49};
29 50
30void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 51void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 3bf7e9705b6a..11fc8a568c64 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010,2011 NVIDIA Corporation 2 * Copyright (C) 2010-2012 NVIDIA Corporation
3 * Copyright (C) 2011 Google, Inc. 3 * Copyright (C) 2011 Google, Inc.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
@@ -14,184 +14,176 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/of.h>
19 17
20#include <mach/pinmux.h>
21#include <mach/pinmux-tegra20.h>
22
23#include "board-pinmux.h"
24#include "board-seaboard.h" 18#include "board-seaboard.h"
19#include "board-pinmux.h"
25 20
26#define DEFAULT_DRIVE(_name) \ 21static unsigned long seaboard_pincfg_drive_sdio1[] = {
27 { \ 22 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
28 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ 23 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
29 .hsm = TEGRA_HSM_DISABLE, \ 24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
30 .schmitt = TEGRA_SCHMITT_ENABLE, \ 25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
31 .drive = TEGRA_DRIVE_DIV_1, \ 26 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
32 .pull_down = TEGRA_PULL_31, \ 27 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
33 .pull_up = TEGRA_PULL_31, \ 28 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
34 .slew_rising = TEGRA_SLEW_SLOWEST, \
35 .slew_falling = TEGRA_SLEW_SLOWEST, \
36 }
37
38static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
39 DEFAULT_DRIVE(SDIO1),
40}; 29};
41 30
42static struct tegra_pingroup_config common_pinmux[] = { 31static struct pinctrl_map common_map[] = {
43 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 32 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
44 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
45 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 34 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
46 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 35 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
47 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
48 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
49 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 38 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven),
50 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate),
51 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate),
52 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 41 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
53 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 42 TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven),
54 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 43 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
55 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven),
56 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("dta", "vi", down, driven),
57 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("dtb", "vi", down, driven),
58 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("dtc", "vi", down, driven),
59 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("dtd", "vi", down, driven),
60 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 49 TEGRA_MAP_MUXCONF("dte", "vi", down, tristate),
61 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
62 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
63 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate),
64 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
65 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 54 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
66 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 55 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
67 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
68 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 57 TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate),
69 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 58 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
70 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
71 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven),
72 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven),
73 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 62 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
74 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
75 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
76 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
77 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
78 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
79 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 68 TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate),
80 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
86 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
87 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
88 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
89 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
90 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
91 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
92 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
93 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
94 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
95 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
96 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
97 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
98 {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate),
99 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 88 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
100 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
101 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 90 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
102 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 91 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
103 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
104 {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven),
105 {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate),
106 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 95 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
107 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate),
108 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 97 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
109 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 98 TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate),
110 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 99 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
111 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 100 TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate),
112 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
113 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 102 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
114 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 103 TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate),
115 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
116 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
117 {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 106 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
118 {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven),
119 {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 108 TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven),
120 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven),
121 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven),
122 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 111 TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate),
123 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven),
124 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
125 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven),
126 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
127 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate),
128 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate),
129 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate),
130 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 119 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
131 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 120 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
132 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 121 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
133 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 122 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
134 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 123 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
135 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 124 TEGRA_MAP_MUXCONF("uad", "irda", none, driven),
136 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uca", "uartc", none, driven),
137 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 126 TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven),
138 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 127 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
139 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 128 TEGRA_MAP_CONF("ck32", none, na),
140 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 129 TEGRA_MAP_CONF("ddrc", none, na),
141 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_CONF("pmca", none, na),
142 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("pmcb", none, na),
143 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("pmcc", none, na),
144 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmcd", none, na),
145 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmce", none, na),
135 TEGRA_MAP_CONF("xm2c", none, na),
136 TEGRA_MAP_CONF("xm2d", none, na),
137 TEGRA_MAP_CONF("ls", up, na),
138 TEGRA_MAP_CONF("lc", up, na),
139 TEGRA_MAP_CONF("ld17_0", down, na),
140 TEGRA_MAP_CONF("ld19_18", down, na),
141 TEGRA_MAP_CONF("ld21_20", down, na),
142 TEGRA_MAP_CONF("ld23_22", down, na),
146}; 143};
147 144
148static struct tegra_pingroup_config seaboard_pinmux[] = { 145static struct pinctrl_map seaboard_map[] = {
149 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 146 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate),
150 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 147 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
151 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 148 TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven),
152 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 149 TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven),
153 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 150 TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate),
154 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 151 TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate),
155 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 152 TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate),
156 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 153 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
157 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 154 TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate),
158 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 155 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
159 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 156 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
160 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 157 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
161 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
162}; 158};
163 159
164static struct tegra_pingroup_config ventana_pinmux[] = { 160static struct pinctrl_map ventana_map[] = {
165 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 161 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven),
166 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 162 TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate),
167 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 163 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
168 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 164 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
169 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 165 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven),
170 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 166 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
171 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 167 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
172 {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 168 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven),
173 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 169 TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate),
174 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 170 TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate),
175 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 171 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
176 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
177 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
178}; 172};
179 173
180static struct tegra_board_pinmux_conf common_conf = { 174static struct tegra_board_pinmux_conf common_conf = {
181 .pgs = common_pinmux, 175 .maps = common_map,
182 .pg_count = ARRAY_SIZE(common_pinmux), 176 .map_count = ARRAY_SIZE(common_map),
183}; 177};
184 178
185static struct tegra_board_pinmux_conf seaboard_conf = { 179static struct tegra_board_pinmux_conf seaboard_conf = {
186 .pgs = seaboard_pinmux, 180 .maps = seaboard_map,
187 .pg_count = ARRAY_SIZE(seaboard_pinmux), 181 .map_count = ARRAY_SIZE(seaboard_map),
188 .drives = seaboard_drive_pinmux,
189 .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
190}; 182};
191 183
192static struct tegra_board_pinmux_conf ventana_conf = { 184static struct tegra_board_pinmux_conf ventana_conf = {
193 .pgs = ventana_pinmux, 185 .maps = ventana_map,
194 .pg_count = ARRAY_SIZE(ventana_pinmux), 186 .map_count = ARRAY_SIZE(ventana_map),
195}; 187};
196 188
197void seaboard_pinmux_init(void) 189void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a1902d4e8e5d..7b39511c0d4d 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-trimslice-pinmux.c 2 * arch/arm/mach-tegra/board-trimslice-pinmux.c
3 * 3 *
4 * Copyright (C) 2011 CompuLab, Ltd. 4 * Copyright (C) 2011 CompuLab, Ltd.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -14,137 +15,138 @@
14 * 15 *
15 */ 16 */
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/of.h>
19 18
20#include <mach/pinmux.h>
21#include <mach/pinmux-tegra20.h>
22
23#include "board-pinmux.h"
24#include "board-trimslice.h" 19#include "board-trimslice.h"
20#include "board-pinmux.h"
25 21
26static struct tegra_pingroup_config trimslice_pinmux[] = { 22static struct pinctrl_map trimslice_map[] = {
27 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 23 TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
28 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
29 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 25 TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
30 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 26 TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
31 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 27 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
32 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
33 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 29 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
34 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
35 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
36 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 32 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
37 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 33 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
38 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
39 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
40 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 36 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
41 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 37 TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
42 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
43 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
44 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
45 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
46 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 42 TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
47 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
48 {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 44 TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
49 {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
50 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
51 {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 47 TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
52 {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
53 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
54 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
55 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 51 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
56 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
57 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 53 TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
58 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
59 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
60 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 56 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
61 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 57 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
62 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 58 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
63 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 59 TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
64 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 60 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
65 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 61 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
66 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 62 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
67 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
68 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
84 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 80 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
85 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
86 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
87 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
90 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
91 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
92 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 88 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
93 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
94 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
95 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 91 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
96 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
97 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 93 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
98 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
99 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 97 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
102 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 98 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 99 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
105 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 101 TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
106 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
107 {TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 103 TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
108 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
109 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
110 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 106 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
111 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
112 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 108 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
113 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
114 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
115 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
116 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 112 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
117 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 113 TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
118 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
119 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
120 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
121 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
122 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
123 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
124 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
126 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
127 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
128 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
129 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
130 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
131 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
132 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
133 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
134 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_CONF("ck32", none, na),
135 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ddrc", none, na),
136 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("pmca", none, na),
137 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmcb", none, na),
138 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcc", none, na),
139 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcd", none, na),
140 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmce", none, na),
141 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("xm2c", none, na),
142 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2d", none, na),
139 TEGRA_MAP_CONF("ls", up, na),
140 TEGRA_MAP_CONF("lc", up, na),
141 TEGRA_MAP_CONF("ld17_0", down, na),
142 TEGRA_MAP_CONF("ld19_18", down, na),
143 TEGRA_MAP_CONF("ld21_20", down, na),
144 TEGRA_MAP_CONF("ld23_22", down, na),
143}; 145};
144 146
145static struct tegra_board_pinmux_conf conf = { 147static struct tegra_board_pinmux_conf conf = {
146 .pgs = trimslice_pinmux, 148 .maps = trimslice_map,
147 .pg_count = ARRAY_SIZE(trimslice_pinmux), 149 .map_count = ARRAY_SIZE(trimslice_map),
148}; 150};
149 151
150void trimslice_pinmux_init(void) 152void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index ac35d2b76850..7867a12748dd 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -711,10 +711,10 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
711 711
712static struct of_device_id tegra_pinmux_of_match[] __devinitdata = { 712static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
713#ifdef CONFIG_ARCH_TEGRA_2x_SOC 713#ifdef CONFIG_ARCH_TEGRA_2x_SOC
714 { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init }, 714 { .compatible = "nvidia,tegra20-pinmux-disabled", tegra20_pinmux_init },
715#endif 715#endif
716#ifdef CONFIG_ARCH_TEGRA_3x_SOC 716#ifdef CONFIG_ARCH_TEGRA_3x_SOC
717 { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init }, 717 { .compatible = "nvidia,tegra30-pinmux-disabled", tegra30_pinmux_init },
718#endif 718#endif
719 { }, 719 { },
720}; 720};
@@ -809,7 +809,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
809 809
810static struct platform_driver tegra_pinmux_driver = { 810static struct platform_driver tegra_pinmux_driver = {
811 .driver = { 811 .driver = {
812 .name = "tegra-pinmux", 812 .name = "tegra-pinmux-disabled",
813 .owner = THIS_MODULE, 813 .owner = THIS_MODULE,
814 .of_match_table = tegra_pinmux_of_match, 814 .of_match_table = tegra_pinmux_of_match,
815 }, 815 },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 17:54:33 -0500