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-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c3
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c108
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c4
-rw-r--r--arch/arm/mach-omap2/board-flash.c32
-rw-r--r--arch/arm/mach-omap2/board-flash.h4
-rw-r--r--arch/arm/mach-omap2/board-ldp.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom.c5
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c2
-rw-r--r--arch/arm/mach-omap2/devices.c41
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c7
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c113
-rw-r--r--arch/arm/mach-omap2/gpmc.c56
-rw-r--r--arch/arm/mach-omap2/id.c31
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c101
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c165
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c27
-rw-r--r--arch/arm/mach-omap2/omap_phy_internal.c93
-rw-r--r--arch/arm/mach-omap2/usb-musb.c219
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h16
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h18
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h2
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h9
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h11
-rw-r--r--arch/arm/plat-omap/include/plat/onenand.h10
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h4
-rw-r--r--arch/arm/plat-omap/sram.c16
30 files changed, 850 insertions, 257 deletions
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index ae890caa17a7..019fb7c67dc3 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
58CONFIG_NO_HZ=y 58CONFIG_NO_HZ=y
59CONFIG_HIGH_RES_TIMERS=y 59CONFIG_HIGH_RES_TIMERS=y
60CONFIG_SMP=y 60CONFIG_SMP=y
61CONFIG_NR_CPUS=2
61# CONFIG_LOCAL_TIMERS is not set 62# CONFIG_LOCAL_TIMERS is not set
62CONFIG_AEABI=y 63CONFIG_AEABI=y
63CONFIG_LEDS=y 64CONFIG_LEDS=y
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ec24999eefea..ee72a9787bf1 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -218,7 +218,8 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \
218 hsmmc.o \ 218 hsmmc.o \
219 omap_phy_internal.o 219 omap_phy_internal.o
220 220
221obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o 221obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \
222 omap_phy_internal.o \
222 223
223obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o 224obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
224 225
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index a15f115f1ba5..76a260f7c00e 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -810,7 +810,7 @@ static void __init omap_3430sdp_init(void)
810 omap_serial_init(); 810 omap_serial_init();
811 usb_musb_init(&musb_board_data); 811 usb_musb_init(&musb_board_data);
812 board_smc91x_init(); 812 board_smc91x_init();
813 board_flash_init(sdp_flash_partitions, chip_sel_3430); 813 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
814 sdp3430_display_init(); 814 sdp3430_display_init();
815 enable_board_wakeup_source(); 815 enable_board_wakeup_source();
816 usb_ehci_init(&ehci_pdata); 816 usb_ehci_init(&ehci_pdata);
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 16538757291a..8d1c4358ecf9 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -11,6 +11,7 @@
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/input.h> 12#include <linux/input.h>
13#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <linux/mtd/nand.h>
14 15
15#include <asm/mach-types.h> 16#include <asm/mach-types.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
@@ -208,7 +209,7 @@ static void __init omap_sdp_init(void)
208 zoom_peripherals_init(); 209 zoom_peripherals_init();
209 zoom_display_init(); 210 zoom_display_init();
210 board_smc91x_init(); 211 board_smc91x_init();
211 board_flash_init(sdp_flash_partitions, chip_sel_sdp); 212 board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
212 enable_board_wakeup_source(); 213 enable_board_wakeup_source();
213 usb_ehci_init(&ehci_pdata); 214 usb_ehci_init(&ehci_pdata);
214} 215}
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 27d9583811c2..1a943be822c3 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -35,6 +35,7 @@
35#include <plat/common.h> 35#include <plat/common.h>
36#include <plat/usb.h> 36#include <plat/usb.h>
37#include <plat/mmc.h> 37#include <plat/mmc.h>
38#include <plat/omap4-keypad.h>
38 39
39#include "mux.h" 40#include "mux.h"
40#include "hsmmc.h" 41#include "hsmmc.h"
@@ -44,10 +45,93 @@
44#define ETH_KS8851_IRQ 34 45#define ETH_KS8851_IRQ 34
45#define ETH_KS8851_POWER_ON 48 46#define ETH_KS8851_POWER_ON 48
46#define ETH_KS8851_QUART 138 47#define ETH_KS8851_QUART 138
47#define OMAP4SDP_MDM_PWR_EN_GPIO 157
48#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 48#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
49#define OMAP4_SFH7741_ENABLE_GPIO 188 49#define OMAP4_SFH7741_ENABLE_GPIO 188
50 50
51static const int sdp4430_keymap[] = {
52 KEY(0, 0, KEY_E),
53 KEY(0, 1, KEY_R),
54 KEY(0, 2, KEY_T),
55 KEY(0, 3, KEY_HOME),
56 KEY(0, 4, KEY_F5),
57 KEY(0, 5, KEY_UNKNOWN),
58 KEY(0, 6, KEY_I),
59 KEY(0, 7, KEY_LEFTSHIFT),
60
61 KEY(1, 0, KEY_D),
62 KEY(1, 1, KEY_F),
63 KEY(1, 2, KEY_G),
64 KEY(1, 3, KEY_SEND),
65 KEY(1, 4, KEY_F6),
66 KEY(1, 5, KEY_UNKNOWN),
67 KEY(1, 6, KEY_K),
68 KEY(1, 7, KEY_ENTER),
69
70 KEY(2, 0, KEY_X),
71 KEY(2, 1, KEY_C),
72 KEY(2, 2, KEY_V),
73 KEY(2, 3, KEY_END),
74 KEY(2, 4, KEY_F7),
75 KEY(2, 5, KEY_UNKNOWN),
76 KEY(2, 6, KEY_DOT),
77 KEY(2, 7, KEY_CAPSLOCK),
78
79 KEY(3, 0, KEY_Z),
80 KEY(3, 1, KEY_KPPLUS),
81 KEY(3, 2, KEY_B),
82 KEY(3, 3, KEY_F1),
83 KEY(3, 4, KEY_F8),
84 KEY(3, 5, KEY_UNKNOWN),
85 KEY(3, 6, KEY_O),
86 KEY(3, 7, KEY_SPACE),
87
88 KEY(4, 0, KEY_W),
89 KEY(4, 1, KEY_Y),
90 KEY(4, 2, KEY_U),
91 KEY(4, 3, KEY_F2),
92 KEY(4, 4, KEY_VOLUMEUP),
93 KEY(4, 5, KEY_UNKNOWN),
94 KEY(4, 6, KEY_L),
95 KEY(4, 7, KEY_LEFT),
96
97 KEY(5, 0, KEY_S),
98 KEY(5, 1, KEY_H),
99 KEY(5, 2, KEY_J),
100 KEY(5, 3, KEY_F3),
101 KEY(5, 4, KEY_F9),
102 KEY(5, 5, KEY_VOLUMEDOWN),
103 KEY(5, 6, KEY_M),
104 KEY(5, 7, KEY_RIGHT),
105
106 KEY(6, 0, KEY_Q),
107 KEY(6, 1, KEY_A),
108 KEY(6, 2, KEY_N),
109 KEY(6, 3, KEY_BACK),
110 KEY(6, 4, KEY_BACKSPACE),
111 KEY(6, 5, KEY_UNKNOWN),
112 KEY(6, 6, KEY_P),
113 KEY(6, 7, KEY_UP),
114
115 KEY(7, 0, KEY_PROG1),
116 KEY(7, 1, KEY_PROG2),
117 KEY(7, 2, KEY_PROG3),
118 KEY(7, 3, KEY_PROG4),
119 KEY(7, 4, KEY_F4),
120 KEY(7, 5, KEY_UNKNOWN),
121 KEY(7, 6, KEY_OK),
122 KEY(7, 7, KEY_DOWN),
123};
124
125static struct matrix_keymap_data sdp4430_keymap_data = {
126 .keymap = sdp4430_keymap,
127 .keymap_size = ARRAY_SIZE(sdp4430_keymap),
128};
129
130static struct omap4_keypad_platform_data sdp4430_keypad_data = {
131 .keymap_data = &sdp4430_keymap_data,
132 .rows = 8,
133 .cols = 8,
134};
51static struct gpio_led sdp4430_gpio_leds[] = { 135static struct gpio_led sdp4430_gpio_leds[] = {
52 { 136 {
53 .name = "omap4:green:debug0", 137 .name = "omap4:green:debug0",
@@ -250,16 +334,6 @@ static void __init omap_4430sdp_init_early(void)
250#endif 334#endif
251} 335}
252 336
253static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
254 .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
255 .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
256 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
257 .phy_reset = false,
258 .reset_gpio_port[0] = -EINVAL,
259 .reset_gpio_port[1] = -EINVAL,
260 .reset_gpio_port[2] = -EINVAL,
261};
262
263static struct omap_musb_board_data musb_board_data = { 337static struct omap_musb_board_data musb_board_data = {
264 .interface_type = MUSB_INTERFACE_UTMI, 338 .interface_type = MUSB_INTERFACE_UTMI,
265 .mode = MUSB_OTG, 339 .mode = MUSB_OTG,
@@ -572,14 +646,6 @@ static void __init omap_4430sdp_init(void)
572 omap_serial_init(); 646 omap_serial_init();
573 omap4_twl6030_hsmmc_init(mmc); 647 omap4_twl6030_hsmmc_init(mmc);
574 648
575 /* Power on the ULPI PHY */
576 status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3");
577 if (status)
578 pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__);
579 else
580 gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1);
581
582 usb_ehci_init(&ehci_pdata);
583 usb_musb_init(&musb_board_data); 649 usb_musb_init(&musb_board_data);
584 650
585 status = omap_ethernet_init(); 651 status = omap_ethernet_init();
@@ -590,6 +656,10 @@ static void __init omap_4430sdp_init(void)
590 spi_register_board_info(sdp4430_spi_board_info, 656 spi_register_board_info(sdp4430_spi_board_info,
591 ARRAY_SIZE(sdp4430_spi_board_info)); 657 ARRAY_SIZE(sdp4430_spi_board_info));
592 } 658 }
659
660 status = omap4_keyboard_init(&sdp4430_keypad_data);
661 if (status)
662 pr_err("Keypad initialization failed: %d\n", status);
593} 663}
594 664
595static void __init omap_4430sdp_map_io(void) 665static void __init omap_4430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index d0d0f5528132..8532d6e0d53a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -408,6 +408,10 @@ static struct omap_musb_board_data musb_board_data = {
408 .interface_type = MUSB_INTERFACE_ULPI, 408 .interface_type = MUSB_INTERFACE_ULPI,
409 .mode = MUSB_OTG, 409 .mode = MUSB_OTG,
410 .power = 500, 410 .power = 500,
411 .set_phy_power = am35x_musb_phy_power,
412 .clear_irq = am35x_musb_clear_irq,
413 .set_mode = am35x_musb_set_mode,
414 .reset = am35x_musb_reset,
411}; 415};
412 416
413static __init void am3517_evm_musb_init(void) 417static __init void am3517_evm_musb_init(void)
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index fd38c05bb47f..c32c06828f08 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * board-sdp-flash.c 2 * board-flash.c
3 * Modified from mach-omap2/board-3430sdp-flash.c 3 * Modified from mach-omap2/board-3430sdp-flash.c
4 * 4 *
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009 Nokia Corporation
@@ -16,6 +16,7 @@
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h> 17#include <linux/mtd/physmap.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <plat/irqs.h>
19 20
20#include <plat/gpmc.h> 21#include <plat/gpmc.h>
21#include <plat/nand.h> 22#include <plat/nand.h>
@@ -73,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
73 + FLASH_SIZE_SDPV1 - 1; 74 + FLASH_SIZE_SDPV1 - 1;
74 } 75 }
75 if (err < 0) { 76 if (err < 0) {
76 printk(KERN_ERR "NOR: Can't request GPMC CS\n"); 77 pr_err("NOR: Can't request GPMC CS\n");
77 return; 78 return;
78 } 79 }
79 if (platform_device_register(&board_nor_device) < 0) 80 if (platform_device_register(&board_nor_device) < 0)
80 printk(KERN_ERR "Unable to register NOR device\n"); 81 pr_err("Unable to register NOR device\n");
81} 82}
82 83
83#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ 84#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
@@ -139,12 +140,16 @@ static struct omap_nand_platform_data board_nand_data = {
139}; 140};
140 141
141void 142void
142__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) 143__init board_nand_init(struct mtd_partition *nand_parts,
144 u8 nr_parts, u8 cs, int nand_type)
143{ 145{
144 board_nand_data.cs = cs; 146 board_nand_data.cs = cs;
145 board_nand_data.parts = nand_parts; 147 board_nand_data.parts = nand_parts;
146 board_nand_data.nr_parts = nr_parts; 148 board_nand_data.nr_parts = nr_parts;
149 board_nand_data.devsize = nand_type;
147 150
151 board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
152 board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
148 gpmc_nand_init(&board_nand_data); 153 gpmc_nand_init(&board_nand_data);
149} 154}
150#else 155#else
@@ -189,12 +194,12 @@ unmap:
189} 194}
190 195
191/** 196/**
192 * sdp3430_flash_init - Identify devices connected to GPMC and register. 197 * board_flash_init - Identify devices connected to GPMC and register.
193 * 198 *
194 * @return - void. 199 * @return - void.
195 */ 200 */
196void board_flash_init(struct flash_partitions partition_info[], 201void board_flash_init(struct flash_partitions partition_info[],
197 char chip_sel_board[][GPMC_CS_NUM]) 202 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
198{ 203{
199 u8 cs = 0; 204 u8 cs = 0;
200 u8 norcs = GPMC_CS_NUM + 1; 205 u8 norcs = GPMC_CS_NUM + 1;
@@ -208,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
208 */ 213 */
209 idx = get_gpmc0_type(); 214 idx = get_gpmc0_type();
210 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { 215 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
211 printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); 216 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
212 return; 217 return;
213 } 218 }
214 config_sel = (unsigned char *)(chip_sel_board[idx]); 219 config_sel = (unsigned char *)(chip_sel_board[idx]);
@@ -232,23 +237,20 @@ void board_flash_init(struct flash_partitions partition_info[],
232 } 237 }
233 238
234 if (norcs > GPMC_CS_NUM) 239 if (norcs > GPMC_CS_NUM)
235 printk(KERN_INFO "NOR: Unable to find configuration " 240 pr_err("NOR: Unable to find configuration in GPMC\n");
236 "in GPMC\n");
237 else 241 else
238 board_nor_init(partition_info[0].parts, 242 board_nor_init(partition_info[0].parts,
239 partition_info[0].nr_parts, norcs); 243 partition_info[0].nr_parts, norcs);
240 244
241 if (onenandcs > GPMC_CS_NUM) 245 if (onenandcs > GPMC_CS_NUM)
242 printk(KERN_INFO "OneNAND: Unable to find configuration " 246 pr_err("OneNAND: Unable to find configuration in GPMC\n");
243 "in GPMC\n");
244 else 247 else
245 board_onenand_init(partition_info[1].parts, 248 board_onenand_init(partition_info[1].parts,
246 partition_info[1].nr_parts, onenandcs); 249 partition_info[1].nr_parts, onenandcs);
247 250
248 if (nandcs > GPMC_CS_NUM) 251 if (nandcs > GPMC_CS_NUM)
249 printk(KERN_INFO "NAND: Unable to find configuration " 252 pr_err("NAND: Unable to find configuration in GPMC\n");
250 "in GPMC\n");
251 else 253 else
252 board_nand_init(partition_info[2].parts, 254 board_nand_init(partition_info[2].parts,
253 partition_info[2].nr_parts, nandcs); 255 partition_info[2].nr_parts, nandcs, nand_type);
254} 256}
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 69befe00dd2f..c240a3f8d163 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -25,6 +25,6 @@ struct flash_partitions {
25}; 25};
26 26
27extern void board_flash_init(struct flash_partitions [], 27extern void board_flash_init(struct flash_partitions [],
28 char chip_sel[][GPMC_CS_NUM]); 28 char chip_sel[][GPMC_CS_NUM], int nand_type);
29extern void board_nand_init(struct mtd_partition *nand_parts, 29extern void board_nand_init(struct mtd_partition *nand_parts,
30 u8 nr_parts, u8 cs); 30 u8 nr_parts, u8 cs, int nand_type);
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8eb2cb7cbc7..a3fae5697a72 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -433,7 +433,7 @@ static void __init omap_ldp_init(void)
433 omap_serial_init(); 433 omap_serial_init();
434 usb_musb_init(&musb_board_data); 434 usb_musb_init(&musb_board_data);
435 board_nand_init(ldp_nand_partitions, 435 board_nand_init(ldp_nand_partitions,
436 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); 436 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
437 437
438 omap2_hsmmc_init(mmc); 438 omap2_hsmmc_init(mmc);
439 /* link regulators to MMC adapters */ 439 /* link regulators to MMC adapters */
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 85d4170f30ab..7e3f1595d77b 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -16,6 +16,7 @@
16#include <linux/input.h> 16#include <linux/input.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/i2c/twl.h> 18#include <linux/i2c/twl.h>
19#include <linux/mtd/nand.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -124,8 +125,8 @@ static void __init omap_zoom_init(void)
124 usb_ehci_init(&ehci_pdata); 125 usb_ehci_init(&ehci_pdata);
125 } 126 }
126 127
127 board_nand_init(zoom_nand_partitions, 128 board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
128 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); 129 ZOOM_NAND_CS, NAND_BUSWIDTH_16);
129 zoom_debugboard_init(); 130 zoom_debugboard_init();
130 zoom_peripherals_init(); 131 zoom_peripherals_init();
131 zoom_display_init(); 132 zoom_display_init();
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index a781cd6795a4..e25364de028a 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
97 u32 *field_val) 97 u32 *field_val)
98{ 98{
99 const struct clksel *clks; 99 const struct clksel *clks;
100 const struct clksel_rate *clkr, *max_clkr; 100 const struct clksel_rate *clkr, *max_clkr = NULL;
101 u8 max_div = 0; 101 u8 max_div = 0;
102 102
103 clks = _get_clksel_by_parent(clk, src_clk); 103 clks = _get_clksel_by_parent(clk, src_clk);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 71f099b85e7c..9ee876fd367a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -31,6 +31,7 @@
31#include <plat/dma.h> 31#include <plat/dma.h>
32#include <plat/omap_hwmod.h> 32#include <plat/omap_hwmod.h>
33#include <plat/omap_device.h> 33#include <plat/omap_device.h>
34#include <plat/omap4-keypad.h>
34 35
35#include "mux.h" 36#include "mux.h"
36#include "control.h" 37#include "control.h"
@@ -142,6 +143,46 @@ static inline void omap_init_camera(void)
142} 143}
143#endif 144#endif
144 145
146struct omap_device_pm_latency omap_keyboard_latency[] = {
147 {
148 .deactivate_func = omap_device_idle_hwmods,
149 .activate_func = omap_device_enable_hwmods,
150 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
151 },
152};
153
154int __init omap4_keyboard_init(struct omap4_keypad_platform_data
155 *sdp4430_keypad_data)
156{
157 struct omap_device *od;
158 struct omap_hwmod *oh;
159 struct omap4_keypad_platform_data *keypad_data;
160 unsigned int id = -1;
161 char *oh_name = "kbd";
162 char *name = "omap4-keypad";
163
164 oh = omap_hwmod_lookup(oh_name);
165 if (!oh) {
166 pr_err("Could not look up %s\n", oh_name);
167 return -ENODEV;
168 }
169
170 keypad_data = sdp4430_keypad_data;
171
172 od = omap_device_build(name, id, oh, keypad_data,
173 sizeof(struct omap4_keypad_platform_data),
174 omap_keyboard_latency,
175 ARRAY_SIZE(omap_keyboard_latency), 0);
176
177 if (IS_ERR(od)) {
178 WARN(1, "Cant build omap_device for %s:%s.\n",
179 name, oh->name);
180 return PTR_ERR(od);
181 }
182
183 return 0;
184}
185
145#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 186#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
146 187
147#define MBOX_REG_SIZE 0x120 188#define MBOX_REG_SIZE 0x120
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 2bb29c160702..c1791d08ae56 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,6 +12,7 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/mtd/nand.h>
15 16
16#include <asm/mach/flash.h> 17#include <asm/mach/flash.h>
17 18
@@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
69 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); 70 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
70 71
71 /* Configure GPMC */ 72 /* Configure GPMC */
72 gpmc_cs_configure(gpmc_nand_data->cs, 73 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
73 GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); 74 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
75 else
76 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
74 gpmc_cs_configure(gpmc_nand_data->cs, 77 gpmc_cs_configure(gpmc_nand_data->cs,
75 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); 78 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
76 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); 79 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 3a7d25fb00ef..d776ded9830d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
94} 94}
95 95
96static void set_onenand_cfg(void __iomem *onenand_base, int latency, 96static void set_onenand_cfg(void __iomem *onenand_base, int latency,
97 int sync_read, int sync_write, int hf) 97 int sync_read, int sync_write, int hf, int vhf)
98{ 98{
99 u32 reg; 99 u32 reg;
100 100
@@ -114,12 +114,57 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
114 reg |= ONENAND_SYS_CFG1_HF; 114 reg |= ONENAND_SYS_CFG1_HF;
115 else 115 else
116 reg &= ~ONENAND_SYS_CFG1_HF; 116 reg &= ~ONENAND_SYS_CFG1_HF;
117 if (vhf)
118 reg |= ONENAND_SYS_CFG1_VHF;
119 else
120 reg &= ~ONENAND_SYS_CFG1_VHF;
117 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); 121 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
118} 122}
119 123
124static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
125 void __iomem *onenand_base, bool *clk_dep)
126{
127 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
128 int freq = 0;
129
130 if (cfg->get_freq) {
131 struct onenand_freq_info fi;
132
133 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
134 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
135 fi.ver_id = ver;
136 freq = cfg->get_freq(&fi, clk_dep);
137 if (freq)
138 return freq;
139 }
140
141 switch ((ver >> 4) & 0xf) {
142 case 0:
143 freq = 40;
144 break;
145 case 1:
146 freq = 54;
147 break;
148 case 2:
149 freq = 66;
150 break;
151 case 3:
152 freq = 83;
153 break;
154 case 4:
155 freq = 104;
156 break;
157 default:
158 freq = 54;
159 break;
160 }
161
162 return freq;
163}
164
120static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, 165static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
121 void __iomem *onenand_base, 166 void __iomem *onenand_base,
122 int freq) 167 int *freq_ptr)
123{ 168{
124 struct gpmc_timings t; 169 struct gpmc_timings t;
125 const int t_cer = 15; 170 const int t_cer = 15;
@@ -130,10 +175,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
130 const int t_wph = 30; 175 const int t_wph = 30;
131 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 176 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
132 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; 177 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
133 int first_time = 0, hf = 0, sync_read = 0, sync_write = 0; 178 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
134 int err, ticks_cez; 179 int err, ticks_cez;
135 int cs = cfg->cs; 180 int cs = cfg->cs, freq = *freq_ptr;
136 u32 reg; 181 u32 reg;
182 bool clk_dep = false;
137 183
138 if (cfg->flags & ONENAND_SYNC_READ) { 184 if (cfg->flags & ONENAND_SYNC_READ) {
139 sync_read = 1; 185 sync_read = 1;
@@ -148,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
148 err = omap2_onenand_set_async_mode(cs, onenand_base); 194 err = omap2_onenand_set_async_mode(cs, onenand_base);
149 if (err) 195 if (err)
150 return err; 196 return err;
151 reg = readw(onenand_base + ONENAND_REG_VERSION_ID); 197 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
152 switch ((reg >> 4) & 0xf) {
153 case 0:
154 freq = 40;
155 break;
156 case 1:
157 freq = 54;
158 break;
159 case 2:
160 freq = 66;
161 break;
162 case 3:
163 freq = 83;
164 break;
165 case 4:
166 freq = 104;
167 break;
168 default:
169 freq = 54;
170 break;
171 }
172 first_time = 1; 198 first_time = 1;
173 } 199 }
174 200
@@ -180,7 +206,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
180 t_avdh = 2; 206 t_avdh = 2;
181 t_ach = 3; 207 t_ach = 3;
182 t_aavdh = 6; 208 t_aavdh = 6;
183 t_rdyo = 9; 209 t_rdyo = 6;
184 break; 210 break;
185 case 83: 211 case 83:
186 min_gpmc_clk_period = 12000; /* 83 MHz */ 212 min_gpmc_clk_period = 12000; /* 83 MHz */
@@ -217,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
217 gpmc_clk_ns = gpmc_ticks_to_ns(div); 243 gpmc_clk_ns = gpmc_ticks_to_ns(div);
218 if (gpmc_clk_ns < 15) /* >66Mhz */ 244 if (gpmc_clk_ns < 15) /* >66Mhz */
219 hf = 1; 245 hf = 1;
220 if (hf) 246 if (gpmc_clk_ns < 12) /* >83Mhz */
247 vhf = 1;
248 if (vhf)
249 latency = 8;
250 else if (hf)
221 latency = 6; 251 latency = 6;
222 else if (gpmc_clk_ns >= 25) /* 40 MHz*/ 252 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
223 latency = 3; 253 latency = 3;
224 else 254 else
225 latency = 4; 255 latency = 4;
226 256
257 if (clk_dep) {
258 if (gpmc_clk_ns < 12) { /* >83Mhz */
259 t_ces = 3;
260 t_avds = 4;
261 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
262 t_ces = 5;
263 t_avds = 4;
264 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
265 t_ces = 6;
266 t_avds = 5;
267 } else {
268 t_ces = 7;
269 t_avds = 7;
270 }
271 }
272
227 if (first_time) 273 if (first_time)
228 set_onenand_cfg(onenand_base, latency, 274 set_onenand_cfg(onenand_base, latency,
229 sync_read, sync_write, hf); 275 sync_read, sync_write, hf, vhf);
230 276
231 if (div == 1) { 277 if (div == 1) {
232 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); 278 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -264,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
264 /* Read */ 310 /* Read */
265 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); 311 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
266 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); 312 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
313 /* Force at least 1 clk between AVD High to OE Low */
314 if (t.oe_on <= t.adv_rd_off)
315 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
267 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); 316 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
268 t.oe_off = t.access + gpmc_round_ns_to_ticks(1); 317 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
269 t.cs_rd_off = t.oe_off; 318 t.cs_rd_off = t.oe_off;
@@ -317,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
317 if (err) 366 if (err)
318 return err; 367 return err;
319 368
320 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf); 369 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
370
371 *freq_ptr = freq;
321 372
322 return 0; 373 return 0;
323} 374}
324 375
325static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) 376static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
326{ 377{
327 struct device *dev = &gpmc_onenand_device.dev; 378 struct device *dev = &gpmc_onenand_device.dev;
328 379
329 /* Set sync timings in GPMC */ 380 /* Set sync timings in GPMC */
330 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, 381 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
331 freq) < 0) { 382 freq_ptr) < 0) {
332 dev_err(dev, "Unable to set synchronous mode\n"); 383 dev_err(dev, "Unable to set synchronous mode\n");
333 return -EINVAL; 384 return -EINVAL;
334 } 385 }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1b7b3e7d02f7..674174365f78 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,6 +14,7 @@
14 */ 14 */
15#undef DEBUG 15#undef DEBUG
16 16
17#include <linux/irq.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/init.h> 19#include <linux/init.h>
19#include <linux/err.h> 20#include <linux/err.h>
@@ -22,6 +23,7 @@
22#include <linux/spinlock.h> 23#include <linux/spinlock.h>
23#include <linux/io.h> 24#include <linux/io.h>
24#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/interrupt.h>
25 27
26#include <asm/mach-types.h> 28#include <asm/mach-types.h>
27#include <plat/gpmc.h> 29#include <plat/gpmc.h>
@@ -58,7 +60,6 @@
58#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 60#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
59#define GPMC_SECTION_SHIFT 28 /* 128 MB */ 61#define GPMC_SECTION_SHIFT 28 /* 128 MB */
60 62
61#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
62#define CS_NUM_SHIFT 24 63#define CS_NUM_SHIFT 24
63#define ENABLE_PREFETCH (0x1 << 7) 64#define ENABLE_PREFETCH (0x1 << 7)
64#define DMA_MPU_MODE 2 65#define DMA_MPU_MODE 2
@@ -100,6 +101,8 @@ static void __iomem *gpmc_base;
100 101
101static struct clk *gpmc_l3_clk; 102static struct clk *gpmc_l3_clk;
102 103
104static irqreturn_t gpmc_handle_irq(int irq, void *dev);
105
103static void gpmc_write_reg(int idx, u32 val) 106static void gpmc_write_reg(int idx, u32 val)
104{ 107{
105 __raw_writel(val, gpmc_base + idx); 108 __raw_writel(val, gpmc_base + idx);
@@ -497,6 +500,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
497 u32 regval = 0; 500 u32 regval = 0;
498 501
499 switch (cmd) { 502 switch (cmd) {
503 case GPMC_ENABLE_IRQ:
504 gpmc_write_reg(GPMC_IRQENABLE, wval);
505 break;
506
500 case GPMC_SET_IRQ_STATUS: 507 case GPMC_SET_IRQ_STATUS:
501 gpmc_write_reg(GPMC_IRQSTATUS, wval); 508 gpmc_write_reg(GPMC_IRQSTATUS, wval);
502 break; 509 break;
@@ -598,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
598/** 605/**
599 * gpmc_prefetch_enable - configures and starts prefetch transfer 606 * gpmc_prefetch_enable - configures and starts prefetch transfer
600 * @cs: cs (chip select) number 607 * @cs: cs (chip select) number
608 * @fifo_th: fifo threshold to be used for read/ write
601 * @dma_mode: dma mode enable (1) or disable (0) 609 * @dma_mode: dma mode enable (1) or disable (0)
602 * @u32_count: number of bytes to be transferred 610 * @u32_count: number of bytes to be transferred
603 * @is_write: prefetch read(0) or write post(1) mode 611 * @is_write: prefetch read(0) or write post(1) mode
604 */ 612 */
605int gpmc_prefetch_enable(int cs, int dma_mode, 613int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
606 unsigned int u32_count, int is_write) 614 unsigned int u32_count, int is_write)
607{ 615{
608 616
609 if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { 617 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
618 pr_err("gpmc: fifo threshold is not supported\n");
619 return -1;
620 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
610 /* Set the amount of bytes to be prefetched */ 621 /* Set the amount of bytes to be prefetched */
611 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); 622 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
612 623
@@ -614,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
614 * enable the engine. Set which cs is has requested for. 625 * enable the engine. Set which cs is has requested for.
615 */ 626 */
616 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | 627 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
617 PREFETCH_FIFOTHRESHOLD | 628 PREFETCH_FIFOTHRESHOLD(fifo_th) |
618 ENABLE_PREFETCH | 629 ENABLE_PREFETCH |
619 (dma_mode << DMA_MPU_MODE) | 630 (dma_mode << DMA_MPU_MODE) |
620 (0x1 & is_write))); 631 (0x1 & is_write)));
@@ -678,9 +689,10 @@ static void __init gpmc_mem_init(void)
678 } 689 }
679} 690}
680 691
681void __init gpmc_init(void) 692static int __init gpmc_init(void)
682{ 693{
683 u32 l; 694 u32 l, irq;
695 int cs, ret = -EINVAL;
684 char *ck = NULL; 696 char *ck = NULL;
685 697
686 if (cpu_is_omap24xx()) { 698 if (cpu_is_omap24xx()) {
@@ -698,7 +710,7 @@ void __init gpmc_init(void)
698 } 710 }
699 711
700 if (WARN_ON(!ck)) 712 if (WARN_ON(!ck))
701 return; 713 return ret;
702 714
703 gpmc_l3_clk = clk_get(NULL, ck); 715 gpmc_l3_clk = clk_get(NULL, ck);
704 if (IS_ERR(gpmc_l3_clk)) { 716 if (IS_ERR(gpmc_l3_clk)) {
@@ -723,6 +735,36 @@ void __init gpmc_init(void)
723 l |= (0x02 << 3) | (1 << 0); 735 l |= (0x02 << 3) | (1 << 0);
724 gpmc_write_reg(GPMC_SYSCONFIG, l); 736 gpmc_write_reg(GPMC_SYSCONFIG, l);
725 gpmc_mem_init(); 737 gpmc_mem_init();
738
739 /* initalize the irq_chained */
740 irq = OMAP_GPMC_IRQ_BASE;
741 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
742 set_irq_handler(irq, handle_simple_irq);
743 set_irq_flags(irq, IRQF_VALID);
744 irq++;
745 }
746
747 ret = request_irq(INT_34XX_GPMC_IRQ,
748 gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
749 if (ret)
750 pr_err("gpmc: irq-%d could not claim: err %d\n",
751 INT_34XX_GPMC_IRQ, ret);
752 return ret;
753}
754postcore_initcall(gpmc_init);
755
756static irqreturn_t gpmc_handle_irq(int irq, void *dev)
757{
758 u8 cs;
759
760 if (irq != INT_34XX_GPMC_IRQ)
761 return IRQ_HANDLED;
762 /* check cs to invoke the irq */
763 cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
764 if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
765 generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
766
767 return IRQ_HANDLED;
726} 768}
727 769
728#ifdef CONFIG_ARCH_OMAP3 770#ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 5c25f1b55235..3168b17bc264 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,7 +6,7 @@
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com> 7 * Written by Tony Lindgren <tony@atomide.com>
8 * 8 *
9 * Copyright (C) 2009 Texas Instruments 9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
@@ -328,7 +328,7 @@ static void __init omap4_check_revision(void)
328 */ 328 */
329 idcode = read_tap_reg(OMAP_TAP_IDCODE); 329 idcode = read_tap_reg(OMAP_TAP_IDCODE);
330 hawkeye = (idcode >> 12) & 0xffff; 330 hawkeye = (idcode >> 12) & 0xffff;
331 rev = (idcode >> 28) & 0xff; 331 rev = (idcode >> 28) & 0xf;
332 332
333 /* 333 /*
334 * Few initial ES2.0 samples IDCODE is same as ES1.0 334 * Few initial ES2.0 samples IDCODE is same as ES1.0
@@ -347,22 +347,31 @@ static void __init omap4_check_revision(void)
347 omap_chip.oc |= CHIP_IS_OMAP4430ES1; 347 omap_chip.oc |= CHIP_IS_OMAP4430ES1;
348 break; 348 break;
349 case 1: 349 case 1:
350 default:
350 omap_revision = OMAP4430_REV_ES2_0; 351 omap_revision = OMAP4430_REV_ES2_0;
351 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 352 omap_chip.oc |= CHIP_IS_OMAP4430ES2;
353 }
354 break;
355 case 0xb95c:
356 switch (rev) {
357 case 3:
358 omap_revision = OMAP4430_REV_ES2_1;
359 omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
352 break; 360 break;
361 case 4:
353 default: 362 default:
354 omap_revision = OMAP4430_REV_ES2_0; 363 omap_revision = OMAP4430_REV_ES2_2;
355 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 364 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
356 } 365 }
357 break; 366 break;
358 default: 367 default:
359 /* Unknown default to latest silicon rev as default*/ 368 /* Unknown default to latest silicon rev as default */
360 omap_revision = OMAP4430_REV_ES2_0; 369 omap_revision = OMAP4430_REV_ES2_2;
361 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 370 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
362 } 371 }
363 372
364 pr_info("OMAP%04x ES%d.0\n", 373 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
365 omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); 374 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
366} 375}
367 376
368#define OMAP3_SHOW_FEATURE(feat) \ 377#define OMAP3_SHOW_FEATURE(feat) \
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b8b49e4ae928..657f3c84687c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -30,7 +30,6 @@
30 30
31#include <plat/sram.h> 31#include <plat/sram.h>
32#include <plat/sdrc.h> 32#include <plat/sdrc.h>
33#include <plat/gpmc.h>
34#include <plat/serial.h> 33#include <plat/serial.h>
35 34
36#include "clock2xxx.h" 35#include "clock2xxx.h"
@@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
422 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 421 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
423 _omap2_init_reprogram_sdrc(); 422 _omap2_init_reprogram_sdrc();
424 } 423 }
425 gpmc_init();
426 424
427 omap_irq_base_init(); 425 omap_irq_base_init();
428} 426}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 60fe4aac1f50..7ba688a1c840 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -93,6 +93,16 @@ static struct omap_hwmod omap2430_uart3_hwmod;
93static struct omap_hwmod omap2430_i2c1_hwmod; 93static struct omap_hwmod omap2430_i2c1_hwmod;
94static struct omap_hwmod omap2430_i2c2_hwmod; 94static struct omap_hwmod omap2430_i2c2_hwmod;
95 95
96static struct omap_hwmod omap2430_usbhsotg_hwmod;
97
98/* l3_core -> usbhsotg interface */
99static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
100 .master = &omap2430_usbhsotg_hwmod,
101 .slave = &omap2430_l3_main_hwmod,
102 .clk = "core_l3_ck",
103 .user = OCP_USER_MPU,
104};
105
96/* I2C IP block address space length (in bytes) */ 106/* I2C IP block address space length (in bytes) */
97#define OMAP2_I2C_AS_LEN 128 107#define OMAP2_I2C_AS_LEN 128
98 108
@@ -193,6 +203,35 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
193 .user = OCP_USER_MPU | OCP_USER_SDMA, 203 .user = OCP_USER_MPU | OCP_USER_SDMA,
194}; 204};
195 205
206/*
207* usbhsotg interface data
208*/
209static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
210 {
211 .pa_start = OMAP243X_HS_BASE,
212 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
213 .flags = ADDR_TYPE_RT
214 },
215};
216
217/* l4_core ->usbhsotg interface */
218static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
219 .master = &omap2430_l4_core_hwmod,
220 .slave = &omap2430_usbhsotg_hwmod,
221 .clk = "usb_l4_ick",
222 .addr = omap2430_usbhsotg_addrs,
223 .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
224 .user = OCP_USER_MPU,
225};
226
227static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
228 &omap2430_usbhsotg__l3,
229};
230
231static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
232 &omap2430_l4_core__usbhsotg,
233};
234
196/* Slave interfaces on the L4_CORE interconnect */ 235/* Slave interfaces on the L4_CORE interconnect */
197static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { 236static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
198 &omap2430_l3_main__l4_core, 237 &omap2430_l3_main__l4_core,
@@ -1133,6 +1172,64 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
1133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1172 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1134}; 1173};
1135 1174
1175/*
1176 * usbhsotg
1177 */
1178static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1179 .rev_offs = 0x0400,
1180 .sysc_offs = 0x0404,
1181 .syss_offs = 0x0408,
1182 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1183 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1184 SYSC_HAS_AUTOIDLE),
1185 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1186 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1187 .sysc_fields = &omap_hwmod_sysc_type1,
1188};
1189
1190static struct omap_hwmod_class usbotg_class = {
1191 .name = "usbotg",
1192 .sysc = &omap2430_usbhsotg_sysc,
1193};
1194
1195/* usb_otg_hs */
1196static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1197
1198 { .name = "mc", .irq = 92 },
1199 { .name = "dma", .irq = 93 },
1200};
1201
1202static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1203 .name = "usb_otg_hs",
1204 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
1205 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
1206 .main_clk = "usbhs_ick",
1207 .prcm = {
1208 .omap2 = {
1209 .prcm_reg_id = 1,
1210 .module_bit = OMAP2430_EN_USBHS_MASK,
1211 .module_offs = CORE_MOD,
1212 .idlest_reg_id = 1,
1213 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1214 },
1215 },
1216 .masters = omap2430_usbhsotg_masters,
1217 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
1218 .slaves = omap2430_usbhsotg_slaves,
1219 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1220 .class = &usbotg_class,
1221 /*
1222 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1223 * broken when autoidle is enabled
1224 * workaround is to disable the autoidle bit at module level.
1225 */
1226 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1227 | HWMOD_SWSUP_MSTANDBY,
1228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1229};
1230
1231
1232
1136static __initdata struct omap_hwmod *omap2430_hwmods[] = { 1233static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1137 &omap2430_l3_main_hwmod, 1234 &omap2430_l3_main_hwmod,
1138 &omap2430_l4_core_hwmod, 1235 &omap2430_l4_core_hwmod,
@@ -1160,6 +1257,10 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1160 &omap2430_mcspi1_hwmod, 1257 &omap2430_mcspi1_hwmod,
1161 &omap2430_mcspi2_hwmod, 1258 &omap2430_mcspi2_hwmod,
1162 &omap2430_mcspi3_hwmod, 1259 &omap2430_mcspi3_hwmod,
1260
1261 /* usbotg class*/
1262 &omap2430_usbhsotg_hwmod,
1263
1163 NULL, 1264 NULL,
1164}; 1265};
1165 1266
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 800eda4adb54..879f55f272e2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,6 +29,7 @@
29#include "prm-regbits-34xx.h" 29#include "prm-regbits-34xx.h"
30#include "cm-regbits-34xx.h" 30#include "cm-regbits-34xx.h"
31#include "wd_timer.h" 31#include "wd_timer.h"
32#include <mach/am35xx.h>
32 33
33/* 34/*
34 * OMAP3xxx hardware module integration data 35 * OMAP3xxx hardware module integration data
@@ -60,6 +61,7 @@ static struct omap_hwmod omap34xx_mcspi1;
60static struct omap_hwmod omap34xx_mcspi2; 61static struct omap_hwmod omap34xx_mcspi2;
61static struct omap_hwmod omap34xx_mcspi3; 62static struct omap_hwmod omap34xx_mcspi3;
62static struct omap_hwmod omap34xx_mcspi4; 63static struct omap_hwmod omap34xx_mcspi4;
64static struct omap_hwmod am35xx_usbhsotg_hwmod;
63 65
64static struct omap_hwmod omap3xxx_dma_system_hwmod; 66static struct omap_hwmod omap3xxx_dma_system_hwmod;
65 67
@@ -112,7 +114,23 @@ static struct omap_hwmod omap3xxx_uart1_hwmod;
112static struct omap_hwmod omap3xxx_uart2_hwmod; 114static struct omap_hwmod omap3xxx_uart2_hwmod;
113static struct omap_hwmod omap3xxx_uart3_hwmod; 115static struct omap_hwmod omap3xxx_uart3_hwmod;
114static struct omap_hwmod omap3xxx_uart4_hwmod; 116static struct omap_hwmod omap3xxx_uart4_hwmod;
117static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
115 118
119/* l3_core -> usbhsotg interface */
120static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
121 .master = &omap3xxx_usbhsotg_hwmod,
122 .slave = &omap3xxx_l3_main_hwmod,
123 .clk = "core_l3_ick",
124 .user = OCP_USER_MPU,
125};
126
127/* l3_core -> am35xx_usbhsotg interface */
128static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
129 .master = &am35xx_usbhsotg_hwmod,
130 .slave = &omap3xxx_l3_main_hwmod,
131 .clk = "core_l3_ick",
132 .user = OCP_USER_MPU,
133};
116/* L4_CORE -> L4_WKUP interface */ 134/* L4_CORE -> L4_WKUP interface */
117static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 135static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
118 .master = &omap3xxx_l4_core_hwmod, 136 .master = &omap3xxx_l4_core_hwmod,
@@ -306,6 +324,61 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
306 .user = OCP_USER_MPU, 324 .user = OCP_USER_MPU,
307}; 325};
308 326
327/*
328* usbhsotg interface data
329*/
330
331static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
332 {
333 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
334 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
335 .flags = ADDR_TYPE_RT
336 },
337};
338
339/* l4_core -> usbhsotg */
340static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
341 .master = &omap3xxx_l4_core_hwmod,
342 .slave = &omap3xxx_usbhsotg_hwmod,
343 .clk = "l4_ick",
344 .addr = omap3xxx_usbhsotg_addrs,
345 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
346 .user = OCP_USER_MPU,
347};
348
349static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
350 &omap3xxx_usbhsotg__l3,
351};
352
353static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
354 &omap3xxx_l4_core__usbhsotg,
355};
356
357static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
358 {
359 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
360 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
361 .flags = ADDR_TYPE_RT
362 },
363};
364
365/* l4_core -> usbhsotg */
366static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
367 .master = &omap3xxx_l4_core_hwmod,
368 .slave = &am35xx_usbhsotg_hwmod,
369 .clk = "l4_ick",
370 .addr = am35xx_usbhsotg_addrs,
371 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
372 .user = OCP_USER_MPU,
373};
374
375static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
376 &am35xx_usbhsotg__l3,
377};
378
379static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
380 &am35xx_l4_core__usbhsotg,
381};
309/* Slave interfaces on the L4_CORE interconnect */ 382/* Slave interfaces on the L4_CORE interconnect */
310static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { 383static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
311 &omap3xxx_l3_main__l4_core, 384 &omap3xxx_l3_main__l4_core,
@@ -1630,6 +1703,91 @@ static struct omap_hwmod omap34xx_mcspi4 = {
1630 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1703 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1631}; 1704};
1632 1705
1706/*
1707 * usbhsotg
1708 */
1709static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1710 .rev_offs = 0x0400,
1711 .sysc_offs = 0x0404,
1712 .syss_offs = 0x0408,
1713 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1714 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1715 SYSC_HAS_AUTOIDLE),
1716 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1717 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1718 .sysc_fields = &omap_hwmod_sysc_type1,
1719};
1720
1721static struct omap_hwmod_class usbotg_class = {
1722 .name = "usbotg",
1723 .sysc = &omap3xxx_usbhsotg_sysc,
1724};
1725/* usb_otg_hs */
1726static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1727
1728 { .name = "mc", .irq = 92 },
1729 { .name = "dma", .irq = 93 },
1730};
1731
1732static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1733 .name = "usb_otg_hs",
1734 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1735 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
1736 .main_clk = "hsotgusb_ick",
1737 .prcm = {
1738 .omap2 = {
1739 .prcm_reg_id = 1,
1740 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1741 .module_offs = CORE_MOD,
1742 .idlest_reg_id = 1,
1743 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1744 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1745 },
1746 },
1747 .masters = omap3xxx_usbhsotg_masters,
1748 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
1749 .slaves = omap3xxx_usbhsotg_slaves,
1750 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
1751 .class = &usbotg_class,
1752
1753 /*
1754 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1755 * broken when autoidle is enabled
1756 * workaround is to disable the autoidle bit at module level.
1757 */
1758 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1759 | HWMOD_SWSUP_MSTANDBY,
1760 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1761};
1762
1763/* usb_otg_hs */
1764static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1765
1766 { .name = "mc", .irq = 71 },
1767};
1768
1769static struct omap_hwmod_class am35xx_usbotg_class = {
1770 .name = "am35xx_usbotg",
1771 .sysc = NULL,
1772};
1773
1774static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1775 .name = "am35x_otg_hs",
1776 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1777 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
1778 .main_clk = NULL,
1779 .prcm = {
1780 .omap2 = {
1781 },
1782 },
1783 .masters = am35xx_usbhsotg_masters,
1784 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
1785 .slaves = am35xx_usbhsotg_slaves,
1786 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
1787 .class = &am35xx_usbotg_class,
1788 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
1789};
1790
1633static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 1791static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1634 &omap3xxx_l3_main_hwmod, 1792 &omap3xxx_l3_main_hwmod,
1635 &omap3xxx_l4_core_hwmod, 1793 &omap3xxx_l4_core_hwmod,
@@ -1667,6 +1825,13 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1667 &omap34xx_mcspi2, 1825 &omap34xx_mcspi2,
1668 &omap34xx_mcspi3, 1826 &omap34xx_mcspi3,
1669 &omap34xx_mcspi4, 1827 &omap34xx_mcspi4,
1828
1829 /* usbotg class */
1830 &omap3xxx_usbhsotg_hwmod,
1831
1832 /* usbotg for am35x */
1833 &am35xx_usbhsotg_hwmod,
1834
1670 NULL, 1835 NULL,
1671}; 1836};
1672 1837
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 84e795cf0648..79a860178913 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -24,6 +24,7 @@
24#include <plat/cpu.h> 24#include <plat/cpu.h>
25#include <plat/gpio.h> 25#include <plat/gpio.h>
26#include <plat/dma.h> 26#include <plat/dma.h>
27#include <plat/mcspi.h>
27 28
28#include "omap_hwmod_common_data.h" 29#include "omap_hwmod_common_data.h"
29 30
@@ -3114,6 +3115,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3114static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { 3115static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3115 .name = "mcspi", 3116 .name = "mcspi",
3116 .sysc = &omap44xx_mcspi_sysc, 3117 .sysc = &omap44xx_mcspi_sysc,
3118 .rev = OMAP4_MCSPI_REV,
3117}; 3119};
3118 3120
3119/* mcspi1 */ 3121/* mcspi1 */
@@ -3156,6 +3158,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3156 &omap44xx_l4_per__mcspi1, 3158 &omap44xx_l4_per__mcspi1,
3157}; 3159};
3158 3160
3161/* mcspi1 dev_attr */
3162static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3163 .num_chipselect = 4,
3164};
3165
3159static struct omap_hwmod omap44xx_mcspi1_hwmod = { 3166static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3160 .name = "mcspi1", 3167 .name = "mcspi1",
3161 .class = &omap44xx_mcspi_hwmod_class, 3168 .class = &omap44xx_mcspi_hwmod_class,
@@ -3169,6 +3176,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3169 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, 3176 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3170 }, 3177 },
3171 }, 3178 },
3179 .dev_attr = &mcspi1_dev_attr,
3172 .slaves = omap44xx_mcspi1_slaves, 3180 .slaves = omap44xx_mcspi1_slaves,
3173 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), 3181 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 3182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -3210,6 +3218,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3210 &omap44xx_l4_per__mcspi2, 3218 &omap44xx_l4_per__mcspi2,
3211}; 3219};
3212 3220
3221/* mcspi2 dev_attr */
3222static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3223 .num_chipselect = 2,
3224};
3225
3213static struct omap_hwmod omap44xx_mcspi2_hwmod = { 3226static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3214 .name = "mcspi2", 3227 .name = "mcspi2",
3215 .class = &omap44xx_mcspi_hwmod_class, 3228 .class = &omap44xx_mcspi_hwmod_class,
@@ -3223,6 +3236,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3223 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, 3236 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3224 }, 3237 },
3225 }, 3238 },
3239 .dev_attr = &mcspi2_dev_attr,
3226 .slaves = omap44xx_mcspi2_slaves, 3240 .slaves = omap44xx_mcspi2_slaves,
3227 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), 3241 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 3242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -3264,6 +3278,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3264 &omap44xx_l4_per__mcspi3, 3278 &omap44xx_l4_per__mcspi3,
3265}; 3279};
3266 3280
3281/* mcspi3 dev_attr */
3282static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3283 .num_chipselect = 2,
3284};
3285
3267static struct omap_hwmod omap44xx_mcspi3_hwmod = { 3286static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3268 .name = "mcspi3", 3287 .name = "mcspi3",
3269 .class = &omap44xx_mcspi_hwmod_class, 3288 .class = &omap44xx_mcspi_hwmod_class,
@@ -3277,6 +3296,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3277 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, 3296 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3278 }, 3297 },
3279 }, 3298 },
3299 .dev_attr = &mcspi3_dev_attr,
3280 .slaves = omap44xx_mcspi3_slaves, 3300 .slaves = omap44xx_mcspi3_slaves,
3281 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), 3301 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3282 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 3302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -3316,6 +3336,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3316 &omap44xx_l4_per__mcspi4, 3336 &omap44xx_l4_per__mcspi4,
3317}; 3337};
3318 3338
3339/* mcspi4 dev_attr */
3340static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3341 .num_chipselect = 1,
3342};
3343
3319static struct omap_hwmod omap44xx_mcspi4_hwmod = { 3344static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3320 .name = "mcspi4", 3345 .name = "mcspi4",
3321 .class = &omap44xx_mcspi_hwmod_class, 3346 .class = &omap44xx_mcspi_hwmod_class,
@@ -3329,6 +3354,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3329 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, 3354 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3330 }, 3355 },
3331 }, 3356 },
3357 .dev_attr = &mcspi4_dev_attr,
3332 .slaves = omap44xx_mcspi4_slaves, 3358 .slaves = omap44xx_mcspi4_slaves,
3333 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), 3359 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 3360 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -3963,6 +3989,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3963static struct omap_hwmod omap44xx_timer1_hwmod = { 3989static struct omap_hwmod omap44xx_timer1_hwmod = {
3964 .name = "timer1", 3990 .name = "timer1",
3965 .class = &omap44xx_timer_1ms_hwmod_class, 3991 .class = &omap44xx_timer_1ms_hwmod_class,
3992 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3966 .mpu_irqs = omap44xx_timer1_irqs, 3993 .mpu_irqs = omap44xx_timer1_irqs,
3967 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), 3994 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
3968 .main_clk = "timer1_fck", 3995 .main_clk = "timer1_fck",
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 745252c60e32..f172ec06c06a 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -29,6 +29,7 @@
29#include <linux/usb.h> 29#include <linux/usb.h>
30 30
31#include <plat/usb.h> 31#include <plat/usb.h>
32#include "control.h"
32 33
33/* OMAP control module register for UTMI PHY */ 34/* OMAP control module register for UTMI PHY */
34#define CONTROL_DEV_CONF 0x300 35#define CONTROL_DEV_CONF 0x300
@@ -147,3 +148,95 @@ int omap4430_phy_exit(struct device *dev)
147 148
148 return 0; 149 return 0;
149} 150}
151
152void am35x_musb_reset(void)
153{
154 u32 regval;
155
156 /* Reset the musb interface */
157 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
158
159 regval |= AM35XX_USBOTGSS_SW_RST;
160 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
161
162 regval &= ~AM35XX_USBOTGSS_SW_RST;
163 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
164
165 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
166}
167
168void am35x_musb_phy_power(u8 on)
169{
170 unsigned long timeout = jiffies + msecs_to_jiffies(100);
171 u32 devconf2;
172
173 if (on) {
174 /*
175 * Start the on-chip PHY and its PLL.
176 */
177 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
178
179 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
180 devconf2 |= CONF2_PHY_PLLON;
181
182 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
183
184 pr_info(KERN_INFO "Waiting for PHY clock good...\n");
185 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
186 & CONF2_PHYCLKGD)) {
187 cpu_relax();
188
189 if (time_after(jiffies, timeout)) {
190 pr_err(KERN_ERR "musb PHY clock good timed out\n");
191 break;
192 }
193 }
194 } else {
195 /*
196 * Power down the on-chip PHY.
197 */
198 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
199
200 devconf2 &= ~CONF2_PHY_PLLON;
201 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
202 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
203 }
204}
205
206void am35x_musb_clear_irq(void)
207{
208 u32 regval;
209
210 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
211 regval |= AM35XX_USBOTGSS_INT_CLR;
212 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
213 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
214}
215
216void am35x_musb_set_mode(u8 musb_mode)
217{
218 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
219
220 devconf2 &= ~CONF2_OTGMODE;
221 switch (musb_mode) {
222#ifdef CONFIG_USB_MUSB_HDRC_HCD
223 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
224 devconf2 |= CONF2_FORCE_HOST;
225 break;
226#endif
227#ifdef CONFIG_USB_GADGET_MUSB_HDRC
228 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
229 devconf2 |= CONF2_FORCE_DEVICE;
230 break;
231#endif
232#ifdef CONFIG_USB_MUSB_OTG
233 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
234 devconf2 |= CONF2_NO_OVERRIDE;
235 break;
236#endif
237 default:
238 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
239 }
240
241 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
242}
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 5298949d4b11..a9d4d143086d 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -30,118 +30,11 @@
30#include <mach/irqs.h> 30#include <mach/irqs.h>
31#include <mach/am35xx.h> 31#include <mach/am35xx.h>
32#include <plat/usb.h> 32#include <plat/usb.h>
33#include "control.h" 33#include <plat/omap_device.h>
34#include "mux.h"
34 35
35#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) 36#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
36 37
37static void am35x_musb_reset(void)
38{
39 u32 regval;
40
41 /* Reset the musb interface */
42 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
43
44 regval |= AM35XX_USBOTGSS_SW_RST;
45 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
46
47 regval &= ~AM35XX_USBOTGSS_SW_RST;
48 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
49
50 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
51}
52
53static void am35x_musb_phy_power(u8 on)
54{
55 unsigned long timeout = jiffies + msecs_to_jiffies(100);
56 u32 devconf2;
57
58 if (on) {
59 /*
60 * Start the on-chip PHY and its PLL.
61 */
62 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
63
64 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
65 devconf2 |= CONF2_PHY_PLLON;
66
67 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
68
69 pr_info(KERN_INFO "Waiting for PHY clock good...\n");
70 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
71 & CONF2_PHYCLKGD)) {
72 cpu_relax();
73
74 if (time_after(jiffies, timeout)) {
75 pr_err(KERN_ERR "musb PHY clock good timed out\n");
76 break;
77 }
78 }
79 } else {
80 /*
81 * Power down the on-chip PHY.
82 */
83 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
84
85 devconf2 &= ~CONF2_PHY_PLLON;
86 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
87 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
88 }
89}
90
91static void am35x_musb_clear_irq(void)
92{
93 u32 regval;
94
95 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
96 regval |= AM35XX_USBOTGSS_INT_CLR;
97 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
98 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
99}
100
101static void am35x_musb_set_mode(u8 musb_mode)
102{
103 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
104
105 devconf2 &= ~CONF2_OTGMODE;
106 switch (musb_mode) {
107#ifdef CONFIG_USB_MUSB_HDRC_HCD
108 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
109 devconf2 |= CONF2_FORCE_HOST;
110 break;
111#endif
112#ifdef CONFIG_USB_GADGET_MUSB_HDRC
113 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
114 devconf2 |= CONF2_FORCE_DEVICE;
115 break;
116#endif
117#ifdef CONFIG_USB_MUSB_OTG
118 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
119 devconf2 |= CONF2_NO_OVERRIDE;
120 break;
121#endif
122 default:
123 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
124 }
125
126 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
127}
128
129static struct resource musb_resources[] = {
130 [0] = { /* start and end set dynamically */
131 .flags = IORESOURCE_MEM,
132 },
133 [1] = { /* general IRQ */
134 .start = INT_243X_HS_USB_MC,
135 .flags = IORESOURCE_IRQ,
136 .name = "mc",
137 },
138 [2] = { /* DMA IRQ */
139 .start = INT_243X_HS_USB_DMA,
140 .flags = IORESOURCE_IRQ,
141 .name = "dma",
142 },
143};
144
145static struct musb_hdrc_config musb_config = { 38static struct musb_hdrc_config musb_config = {
146 .multipoint = 1, 39 .multipoint = 1,
147 .dyn_fifo = 1, 40 .dyn_fifo = 1,
@@ -169,38 +62,65 @@ static struct musb_hdrc_platform_data musb_plat = {
169 62
170static u64 musb_dmamask = DMA_BIT_MASK(32); 63static u64 musb_dmamask = DMA_BIT_MASK(32);
171 64
172static struct platform_device musb_device = { 65static struct omap_device_pm_latency omap_musb_latency[] = {
173 .name = "musb-omap2430", 66 {
174 .id = -1, 67 .deactivate_func = omap_device_idle_hwmods,
175 .dev = { 68 .activate_func = omap_device_enable_hwmods,
176 .dma_mask = &musb_dmamask, 69 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
177 .coherent_dma_mask = DMA_BIT_MASK(32),
178 .platform_data = &musb_plat,
179 }, 70 },
180 .num_resources = ARRAY_SIZE(musb_resources),
181 .resource = musb_resources,
182}; 71};
183 72
73static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
74{
75 switch (board_data->interface_type) {
76 case MUSB_INTERFACE_UTMI:
77 omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT);
78 omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT);
79 break;
80 case MUSB_INTERFACE_ULPI:
81 omap_mux_init_signal("usba0_ulpiphy_clk",
82 OMAP_PIN_INPUT_PULLDOWN);
83 omap_mux_init_signal("usba0_ulpiphy_stp",
84 OMAP_PIN_INPUT_PULLDOWN);
85 omap_mux_init_signal("usba0_ulpiphy_dir",
86 OMAP_PIN_INPUT_PULLDOWN);
87 omap_mux_init_signal("usba0_ulpiphy_nxt",
88 OMAP_PIN_INPUT_PULLDOWN);
89 omap_mux_init_signal("usba0_ulpiphy_dat0",
90 OMAP_PIN_INPUT_PULLDOWN);
91 omap_mux_init_signal("usba0_ulpiphy_dat1",
92 OMAP_PIN_INPUT_PULLDOWN);
93 omap_mux_init_signal("usba0_ulpiphy_dat2",
94 OMAP_PIN_INPUT_PULLDOWN);
95 omap_mux_init_signal("usba0_ulpiphy_dat3",
96 OMAP_PIN_INPUT_PULLDOWN);
97 omap_mux_init_signal("usba0_ulpiphy_dat4",
98 OMAP_PIN_INPUT_PULLDOWN);
99 omap_mux_init_signal("usba0_ulpiphy_dat5",
100 OMAP_PIN_INPUT_PULLDOWN);
101 omap_mux_init_signal("usba0_ulpiphy_dat6",
102 OMAP_PIN_INPUT_PULLDOWN);
103 omap_mux_init_signal("usba0_ulpiphy_dat7",
104 OMAP_PIN_INPUT_PULLDOWN);
105 break;
106 default:
107 break;
108 }
109}
110
184void __init usb_musb_init(struct omap_musb_board_data *board_data) 111void __init usb_musb_init(struct omap_musb_board_data *board_data)
185{ 112{
186 if (cpu_is_omap243x()) { 113 struct omap_hwmod *oh;
187 musb_resources[0].start = OMAP243X_HS_BASE; 114 struct omap_device *od;
188 } else if (cpu_is_omap3517() || cpu_is_omap3505()) { 115 struct platform_device *pdev;
189 musb_device.name = "musb-am35x"; 116 struct device *dev;
190 musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; 117 int bus_id = -1;
191 musb_resources[1].start = INT_35XX_USBOTG_IRQ; 118 const char *oh_name, *name;
192 board_data->set_phy_power = am35x_musb_phy_power; 119
193 board_data->clear_irq = am35x_musb_clear_irq; 120 if (cpu_is_omap3517() || cpu_is_omap3505()) {
194 board_data->set_mode = am35x_musb_set_mode;
195 board_data->reset = am35x_musb_reset;
196 } else if (cpu_is_omap34xx()) {
197 musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
198 } else if (cpu_is_omap44xx()) { 121 } else if (cpu_is_omap44xx()) {
199 musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; 122 usb_musb_mux_init(board_data);
200 musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
201 musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
202 } 123 }
203 musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
204 124
205 /* 125 /*
206 * REVISIT: This line can be removed once all the platforms using 126 * REVISIT: This line can be removed once all the platforms using
@@ -212,8 +132,35 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
212 musb_plat.mode = board_data->mode; 132 musb_plat.mode = board_data->mode;
213 musb_plat.extvbus = board_data->extvbus; 133 musb_plat.extvbus = board_data->extvbus;
214 134
215 if (platform_device_register(&musb_device) < 0) 135 if (cpu_is_omap3517() || cpu_is_omap3505()) {
216 printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); 136 oh_name = "am35x_otg_hs";
137 name = "musb-am35x";
138 } else {
139 oh_name = "usb_otg_hs";
140 name = "musb-omap2430";
141 }
142
143 oh = omap_hwmod_lookup(oh_name);
144 if (!oh) {
145 pr_err("Could not look up %s\n", oh_name);
146 return;
147 }
148
149 od = omap_device_build(name, bus_id, oh, &musb_plat,
150 sizeof(musb_plat), omap_musb_latency,
151 ARRAY_SIZE(omap_musb_latency), false);
152 if (IS_ERR(od)) {
153 pr_err("Could not build omap_device for %s %s\n",
154 name, oh_name);
155 return;
156 }
157
158 pdev = &od->pdev;
159 dev = &pdev->dev;
160 get_device(dev);
161 dev->dma_mask = &musb_dmamask;
162 dev->coherent_dma_mask = musb_dmamask;
163 put_device(dev);
217} 164}
218 165
219#else 166#else
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index be99438d385e..8198bb6cdb5e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (C) 2004, 2008 Nokia Corporation 6 * Copyright (C) 2004, 2008 Nokia Corporation
7 * 7 *
8 * Copyright (C) 2009 Texas Instruments. 8 * Copyright (C) 2009-11 Texas Instruments.
9 * 9 *
10 * Written by Tony Lindgren <tony.lindgren@nokia.com> 10 * Written by Tony Lindgren <tony.lindgren@nokia.com>
11 * 11 *
@@ -405,8 +405,10 @@ IS_OMAP_TYPE(3517, 0x3517)
405#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) 405#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
406 406
407#define OMAP443X_CLASS 0x44300044 407#define OMAP443X_CLASS 0x44300044
408#define OMAP4430_REV_ES1_0 OMAP443X_CLASS 408#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
409#define OMAP4430_REV_ES2_0 0x44301044 409#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
410#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
411#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
410 412
411/* 413/*
412 * omap_chip bits 414 * omap_chip bits
@@ -434,12 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
434#define CHIP_IS_OMAP3630ES1_1 (1 << 9) 436#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
435#define CHIP_IS_OMAP3630ES1_2 (1 << 10) 437#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
436#define CHIP_IS_OMAP4430ES2 (1 << 11) 438#define CHIP_IS_OMAP4430ES2 (1 << 11)
439#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
440#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
437#define CHIP_IS_TI816X (1 << 14) 441#define CHIP_IS_TI816X (1 << 14)
438 442
439#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 443#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
440 444
441#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ 445#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
442 CHIP_IS_OMAP4430ES2) 446 CHIP_IS_OMAP4430ES2 | \
447 CHIP_IS_OMAP4430ES2_1 | \
448 CHIP_IS_OMAP4430ES2_2)
443 449
444/* 450/*
445 * "GE" here represents "greater than or equal to" in terms of ES 451 * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 85ded598853e..12b316165037 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
41#define GPMC_NAND_ADDRESS 0x0000000b 41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c 42#define GPMC_NAND_DATA 0x0000000c
43 43
44#define GPMC_ENABLE_IRQ 0x0000000d
45
44/* ECC commands */ 46/* ECC commands */
45#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 47#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
46#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 48#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
@@ -78,6 +80,19 @@
78#define WR_RD_PIN_MONITORING 0x00600000 80#define WR_RD_PIN_MONITORING 0x00600000
79#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) 81#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
80#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) 82#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
83#define GPMC_IRQ_FIFOEVENTENABLE 0x01
84#define GPMC_IRQ_COUNT_EVENT 0x02
85
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88
89enum omap_ecc {
90 /* 1-bit ecc: stored at end of spare area */
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
92 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
93 /* 1-bit ecc: stored at begining of spare area as romcode */
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
95};
81 96
82/* 97/*
83 * Note that all values in this struct are in nanoseconds except sync_clk 98 * Note that all values in this struct are in nanoseconds except sync_clk
@@ -130,12 +145,11 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
130extern void gpmc_cs_free(int cs); 145extern void gpmc_cs_free(int cs);
131extern int gpmc_cs_set_reserved(int cs, int reserved); 146extern int gpmc_cs_set_reserved(int cs, int reserved);
132extern int gpmc_cs_reserved(int cs); 147extern int gpmc_cs_reserved(int cs);
133extern int gpmc_prefetch_enable(int cs, int dma_mode, 148extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
134 unsigned int u32_count, int is_write); 149 unsigned int u32_count, int is_write);
135extern int gpmc_prefetch_reset(int cs); 150extern int gpmc_prefetch_reset(int cs);
136extern void omap3_gpmc_save_context(void); 151extern void omap3_gpmc_save_context(void);
137extern void omap3_gpmc_restore_context(void); 152extern void omap3_gpmc_restore_context(void);
138extern void gpmc_init(void);
139extern int gpmc_read_status(int cmd); 153extern int gpmc_read_status(int cmd);
140extern int gpmc_cs_configure(int cs, int cmd, int wval); 154extern int gpmc_cs_configure(int cs, int cmd, int wval);
141extern int gpmc_nand_read(int cs, int cmd); 155extern int gpmc_nand_read(int cs, int cmd);
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 69230d685538..19cbb5e9ece2 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -154,6 +154,8 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
154extern void flush_iotlb_all(struct iommu *obj); 154extern void flush_iotlb_all(struct iommu *obj);
155 155
156extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); 156extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
157extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
158 u32 **ppte);
157extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); 159extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
158 160
159extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); 161extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2910de921c52..1b911681e911 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -318,6 +318,7 @@
318#define INT_34XX_PRCM_MPU_IRQ 11 318#define INT_34XX_PRCM_MPU_IRQ 11
319#define INT_34XX_MCBSP1_IRQ 16 319#define INT_34XX_MCBSP1_IRQ 16
320#define INT_34XX_MCBSP2_IRQ 17 320#define INT_34XX_MCBSP2_IRQ 17
321#define INT_34XX_GPMC_IRQ 20
321#define INT_34XX_MCBSP3_IRQ 22 322#define INT_34XX_MCBSP3_IRQ 22
322#define INT_34XX_MCBSP4_IRQ 23 323#define INT_34XX_MCBSP4_IRQ 23
323#define INT_34XX_CAM_IRQ 24 324#define INT_34XX_CAM_IRQ 24
@@ -411,7 +412,13 @@
411#define TWL_IRQ_END TWL6030_IRQ_END 412#define TWL_IRQ_END TWL6030_IRQ_END
412#endif 413#endif
413 414
414#define NR_IRQS TWL_IRQ_END 415/* GPMC related */
416#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
417#define OMAP_GPMC_NR_IRQS 7
418#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
419
420
421#define NR_IRQS OMAP_GPMC_IRQ_END
415 422
416#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 423#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
417 424
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd082bb1..d86d1ecf0068 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -8,8 +8,16 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <plat/gpmc.h>
11#include <linux/mtd/partitions.h> 12#include <linux/mtd/partitions.h>
12 13
14enum nand_io {
15 NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
16 NAND_OMAP_POLLED, /* polled mode, without prefetch */
17 NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
18 NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
19};
20
13struct omap_nand_platform_data { 21struct omap_nand_platform_data {
14 unsigned int options; 22 unsigned int options;
15 int cs; 23 int cs;
@@ -20,8 +28,11 @@ struct omap_nand_platform_data {
20 int (*nand_setup)(void); 28 int (*nand_setup)(void);
21 int (*dev_ready)(struct omap_nand_platform_data *); 29 int (*dev_ready)(struct omap_nand_platform_data *);
22 int dma_channel; 30 int dma_channel;
31 int gpmc_irq;
32 enum nand_io xfer_type;
23 unsigned long phys_base; 33 unsigned long phys_base;
24 int devsize; 34 int devsize;
35 enum omap_ecc ecc_opt;
25}; 36};
26 37
27/* minimum size for IO mapping */ 38/* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index affe87e9ece7..cbe897ca7f9e 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,12 +15,20 @@
15#define ONENAND_SYNC_READ (1 << 0) 15#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1) 16#define ONENAND_SYNC_READWRITE (1 << 1)
17 17
18struct onenand_freq_info {
19 u16 maf_id;
20 u16 dev_id;
21 u16 ver_id;
22};
23
18struct omap_onenand_platform_data { 24struct omap_onenand_platform_data {
19 int cs; 25 int cs;
20 int gpio_irq; 26 int gpio_irq;
21 struct mtd_partition *parts; 27 struct mtd_partition *parts;
22 int nr_parts; 28 int nr_parts;
23 int (*onenand_setup)(void __iomem *, int freq); 29 int (*onenand_setup)(void __iomem *, int *freq_ptr);
30 int (*get_freq)(const struct onenand_freq_info *freq_info,
31 bool *clk_dep);
24 int dma_channel; 32 int dma_channel;
25 u8 flags; 33 u8 flags;
26 u8 regulator_can_sleep; 34 u8 regulator_can_sleep;
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 450a332f1009..077192759afc 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -91,6 +91,10 @@ extern int omap4430_phy_exit(struct device *dev);
91 91
92#endif 92#endif
93 93
94extern void am35x_musb_reset(void);
95extern void am35x_musb_phy_power(u8 on);
96extern void am35x_musb_clear_irq(void);
97extern void am35x_musb_set_mode(u8 musb_mode);
94 98
95/* 99/*
96 * FIXME correct answer depends on hmc_mode, 100 * FIXME correct answer depends on hmc_mode,
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index aedcb3be4e66..9d80064e979b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
405} 405}
406#endif 406#endif
407 407
408#ifdef CONFIG_ARCH_OMAP4
409static int __init omap44xx_sram_init(void)
410{
411 printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
412
413 return -ENODEV;
414}
415#else
416static inline int omap44xx_sram_init(void)
417{
418 return 0;
419}
420#endif
421
422int __init omap_sram_init(void) 408int __init omap_sram_init(void)
423{ 409{
424 omap_detect_sram(); 410 omap_detect_sram();
@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
432 omap243x_sram_init(); 418 omap243x_sram_init();
433 else if (cpu_is_omap34xx()) 419 else if (cpu_is_omap34xx())
434 omap34xx_sram_init(); 420 omap34xx_sram_init();
435 else if (cpu_is_omap44xx())
436 omap44xx_sram_init();
437 421
438 return 0; 422 return 0;
439} 423}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 17:40:08 -0500