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-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi40
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi40
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts10
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi10
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi40
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts10
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi40
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts10
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi40
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi10
-rw-r--r--arch/arm/mach-at91/at91sam9260.c2
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c2
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c2
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c2
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c27
-rw-r--r--arch/arm/mach-imx/clk-busy.c2
-rw-r--r--arch/arm/mach-ux500/board-mop500-regulators.c774
-rw-r--r--arch/arm/mach-ux500/board-mop500-regulators.h7
-rw-r--r--arch/arm/mach-ux500/board-mop500.c5
-rw-r--r--arch/arm/mach-vexpress/v2m.c8
-rw-r--r--arch/arm/plat-samsung/devs.c10
-rw-r--r--arch/mips/bcm63xx/dev-spi.c11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h1
-rw-r--r--arch/powerpc/mm/numa.c1
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.c2
25 files changed, 1011 insertions, 95 deletions
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index cb7bcc51608d..39253b9aedd1 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -322,6 +322,24 @@
322 }; 322 };
323 }; 323 };
324 324
325 spi0 {
326 pinctrl_spi0: spi0-0 {
327 atmel,pins =
328 <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */
329 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */
330 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */
331 };
332 };
333
334 spi1 {
335 pinctrl_spi1: spi1-0 {
336 atmel,pins =
337 <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */
338 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */
339 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */
340 };
341 };
342
325 pioA: gpio@fffff400 { 343 pioA: gpio@fffff400 {
326 compatible = "atmel,at91rm9200-gpio"; 344 compatible = "atmel,at91rm9200-gpio";
327 reg = <0xfffff400 0x200>; 345 reg = <0xfffff400 0x200>;
@@ -471,6 +489,28 @@
471 status = "disabled"; 489 status = "disabled";
472 }; 490 };
473 491
492 spi0: spi@fffc8000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "atmel,at91rm9200-spi";
496 reg = <0xfffc8000 0x200>;
497 interrupts = <12 4 3>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_spi0>;
500 status = "disabled";
501 };
502
503 spi1: spi@fffcc000 {
504 #address-cells = <1>;
505 #size-cells = <0>;
506 compatible = "atmel,at91rm9200-spi";
507 reg = <0xfffcc000 0x200>;
508 interrupts = <13 4 3>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&pinctrl_spi1>;
511 status = "disabled";
512 };
513
474 adc0: adc@fffe0000 { 514 adc0: adc@fffe0000 {
475 compatible = "atmel,at91sam9260-adc"; 515 compatible = "atmel,at91sam9260-adc";
476 reg = <0xfffe0000 0x100>; 516 reg = <0xfffe0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 271d4de026e9..94b58ab2cc08 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -303,6 +303,24 @@
303 }; 303 };
304 }; 304 };
305 305
306 spi0 {
307 pinctrl_spi0: spi0-0 {
308 atmel,pins =
309 <0 0 0x2 0x0 /* PA0 periph B SPI0_MISO pin */
310 0 1 0x2 0x0 /* PA1 periph B SPI0_MOSI pin */
311 0 2 0x2 0x0>; /* PA2 periph B SPI0_SPCK pin */
312 };
313 };
314
315 spi1 {
316 pinctrl_spi1: spi1-0 {
317 atmel,pins =
318 <1 12 0x1 0x0 /* PB12 periph A SPI1_MISO pin */
319 1 13 0x1 0x0 /* PB13 periph A SPI1_MOSI pin */
320 1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */
321 };
322 };
323
306 pioA: gpio@fffff200 { 324 pioA: gpio@fffff200 {
307 compatible = "atmel,at91rm9200-gpio"; 325 compatible = "atmel,at91rm9200-gpio";
308 reg = <0xfffff200 0x200>; 326 reg = <0xfffff200 0x200>;
@@ -462,6 +480,28 @@
462 reg = <0xfffffd40 0x10>; 480 reg = <0xfffffd40 0x10>;
463 status = "disabled"; 481 status = "disabled";
464 }; 482 };
483
484 spi0: spi@fffa4000 {
485 #address-cells = <1>;
486 #size-cells = <0>;
487 compatible = "atmel,at91rm9200-spi";
488 reg = <0xfffa4000 0x200>;
489 interrupts = <14 4 3>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pinctrl_spi0>;
492 status = "disabled";
493 };
494
495 spi1: spi@fffa8000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "atmel,at91rm9200-spi";
499 reg = <0xfffa8000 0x200>;
500 interrupts = <15 4 3>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_spi1>;
503 status = "disabled";
504 };
465 }; 505 };
466 506
467 nand0: nand@40000000 { 507 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 1eb08728f527..a14e424b2e81 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -79,6 +79,16 @@
79 }; 79 };
80 }; 80 };
81 }; 81 };
82
83 spi0: spi@fffa4000 {
84 status = "okay";
85 cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
86 mtd_dataflash@0 {
87 compatible = "atmel,at45", "atmel,dataflash";
88 spi-max-frequency = <50000000>;
89 reg = <0>;
90 };
91 };
82 }; 92 };
83 93
84 nand0: nand@40000000 { 94 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index da15e83e7f17..23d1f468f27f 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -96,6 +96,16 @@
96 status = "okay"; 96 status = "okay";
97 pinctrl-0 = <&pinctrl_ssc0_tx>; 97 pinctrl-0 = <&pinctrl_ssc0_tx>;
98 }; 98 };
99
100 spi0: spi@fffc8000 {
101 status = "okay";
102 cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
103 mtd_dataflash@0 {
104 compatible = "atmel,at45", "atmel,dataflash";
105 spi-max-frequency = <50000000>;
106 reg = <1>;
107 };
108 };
99 }; 109 };
100 110
101 nand0: nand@40000000 { 111 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6b1d4cab24c2..cfdf429578b5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -322,6 +322,24 @@
322 }; 322 };
323 }; 323 };
324 324
325 spi0 {
326 pinctrl_spi0: spi0-0 {
327 atmel,pins =
328 <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */
329 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */
330 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */
331 };
332 };
333
334 spi1 {
335 pinctrl_spi1: spi1-0 {
336 atmel,pins =
337 <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */
338 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */
339 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
340 };
341 };
342
325 pioA: gpio@fffff200 { 343 pioA: gpio@fffff200 {
326 compatible = "atmel,at91rm9200-gpio"; 344 compatible = "atmel,at91rm9200-gpio";
327 reg = <0xfffff200 0x200>; 345 reg = <0xfffff200 0x200>;
@@ -531,6 +549,28 @@
531 reg = <0xfffffd40 0x10>; 549 reg = <0xfffffd40 0x10>;
532 status = "disabled"; 550 status = "disabled";
533 }; 551 };
552
553 spi0: spi@fffa4000 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "atmel,at91rm9200-spi";
557 reg = <0xfffa4000 0x200>;
558 interrupts = <14 4 3>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_spi0>;
561 status = "disabled";
562 };
563
564 spi1: spi@fffa8000 {
565 #address-cells = <1>;
566 #size-cells = <0>;
567 compatible = "atmel,at91rm9200-spi";
568 reg = <0xfffa8000 0x200>;
569 interrupts = <15 4 3>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_spi1>;
572 status = "disabled";
573 };
534 }; 574 };
535 575
536 nand0: nand@40000000 { 576 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 20c31913c270..92c52a7d70bc 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -102,6 +102,16 @@
102 }; 102 };
103 }; 103 };
104 }; 104 };
105
106 spi0: spi@fffa4000{
107 status = "okay";
108 cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
109 mtd_dataflash@0 {
110 compatible = "atmel,at45", "atmel,dataflash";
111 spi-max-frequency = <13000000>;
112 reg = <0>;
113 };
114 };
105 }; 115 };
106 116
107 nand0: nand@40000000 { 117 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 7750f98dd764..b2961f1ea51b 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -261,6 +261,24 @@
261 }; 261 };
262 }; 262 };
263 263
264 spi0 {
265 pinctrl_spi0: spi0-0 {
266 atmel,pins =
267 <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
268 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
269 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
270 };
271 };
272
273 spi1 {
274 pinctrl_spi1: spi1-0 {
275 atmel,pins =
276 <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
277 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
278 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
279 };
280 };
281
264 pioA: gpio@fffff400 { 282 pioA: gpio@fffff400 {
265 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 283 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
266 reg = <0xfffff400 0x200>; 284 reg = <0xfffff400 0x200>;
@@ -373,6 +391,28 @@
373 #size-cells = <0>; 391 #size-cells = <0>;
374 status = "disabled"; 392 status = "disabled";
375 }; 393 };
394
395 spi0: spi@f0000000 {
396 #address-cells = <1>;
397 #size-cells = <0>;
398 compatible = "atmel,at91rm9200-spi";
399 reg = <0xf0000000 0x100>;
400 interrupts = <13 4 3>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_spi0>;
403 status = "disabled";
404 };
405
406 spi1: spi@f0004000 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "atmel,at91rm9200-spi";
410 reg = <0xf0004000 0x100>;
411 interrupts = <14 4 3>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_spi1>;
414 status = "disabled";
415 };
376 }; 416 };
377 417
378 nand0: nand@40000000 { 418 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d400f8de4387..34c842b1efb2 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -67,6 +67,16 @@
67 }; 67 };
68 }; 68 };
69 }; 69 };
70
71 spi0: spi@f0000000 {
72 status = "okay";
73 cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
74 m25p80@0 {
75 compatible = "atmel,at25df321a";
76 spi-max-frequency = <50000000>;
77 reg = <0>;
78 };
79 };
70 }; 80 };
71 81
72 nand0: nand@40000000 { 82 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index a98c0d50fbbe..347b438d47fa 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -343,6 +343,24 @@
343 }; 343 };
344 }; 344 };
345 345
346 spi0 {
347 pinctrl_spi0: spi0-0 {
348 atmel,pins =
349 <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
350 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
351 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
352 };
353 };
354
355 spi1 {
356 pinctrl_spi1: spi1-0 {
357 atmel,pins =
358 <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
359 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
360 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
361 };
362 };
363
346 pioA: gpio@fffff400 { 364 pioA: gpio@fffff400 {
347 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 365 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
348 reg = <0xfffff400 0x200>; 366 reg = <0xfffff400 0x200>;
@@ -529,6 +547,28 @@
529 trigger-value = <0x6>; 547 trigger-value = <0x6>;
530 }; 548 };
531 }; 549 };
550
551 spi0: spi@f0000000 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "atmel,at91rm9200-spi";
555 reg = <0xf0000000 0x100>;
556 interrupts = <13 4 3>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_spi0>;
559 status = "disabled";
560 };
561
562 spi1: spi@f0004000 {
563 #address-cells = <1>;
564 #size-cells = <0>;
565 compatible = "atmel,at91rm9200-spi";
566 reg = <0xf0004000 0x100>;
567 interrupts = <14 4 3>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_spi1>;
570 status = "disabled";
571 };
532 }; 572 };
533 573
534 nand0: nand@40000000 { 574 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 8a7cf1d9cf5d..09f5e667ca7a 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -84,6 +84,16 @@
84 }; 84 };
85 }; 85 };
86 }; 86 };
87
88 spi0: spi@f0000000 {
89 status = "okay";
90 cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
91 m25p80@0 {
92 compatible = "atmel,at25df321a";
93 spi-max-frequency = <50000000>;
94 reg = <0>;
95 };
96 };
87 }; 97 };
88 98
89 usb0: ohci@00600000 { 99 usb0: ohci@00600000 {
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index b67cd5374117..44199bc2c665 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -232,6 +232,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
232 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk), 232 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
233 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk), 233 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
234 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk), 234 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
235 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
236 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
235 /* fake hclk clock */ 237 /* fake hclk clock */
236 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 238 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
237 CLKDEV_CON_ID("pioA", &pioA_clk), 239 CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index d3addee43d8d..2ec5efea3f03 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -262,6 +262,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
262 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk), 262 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
263 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk), 263 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
264 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk), 264 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
265 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
266 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
265 /* fake hclk clock */ 267 /* fake hclk clock */
266 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), 268 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
267 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), 269 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 5dfc8fd87103..ccd078355eed 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -172,6 +172,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
172 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), 172 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), 173 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
174 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), 174 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
175 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
176 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
175 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk), 177 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
176 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk), 178 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
177 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk), 179 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 44a9a62dcc13..a200d8a17123 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -237,6 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
237 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), 237 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
238 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), 238 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
239 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk), 239 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
240 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
241 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
240 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk), 242 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
241 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk), 243 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
242 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk), 244 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 497fcb793dc1..d28c7fbaba2d 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -97,6 +97,19 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
97static struct regulator_consumer_supply max8952_consumer = 97static struct regulator_consumer_supply max8952_consumer =
98 REGULATOR_SUPPLY("vdd_arm", NULL); 98 REGULATOR_SUPPLY("vdd_arm", NULL);
99 99
100static struct regulator_init_data universal_max8952_reg_data = {
101 .constraints = {
102 .name = "VARM_1.2V",
103 .min_uV = 770000,
104 .max_uV = 1400000,
105 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
106 .always_on = 1,
107 .boot_on = 1,
108 },
109 .num_consumer_supplies = 1,
110 .consumer_supplies = &max8952_consumer,
111};
112
100static struct max8952_platform_data universal_max8952_pdata __initdata = { 113static struct max8952_platform_data universal_max8952_pdata __initdata = {
101 .gpio_vid0 = EXYNOS4_GPX0(3), 114 .gpio_vid0 = EXYNOS4_GPX0(3),
102 .gpio_vid1 = EXYNOS4_GPX0(4), 115 .gpio_vid1 = EXYNOS4_GPX0(4),
@@ -105,19 +118,7 @@ static struct max8952_platform_data universal_max8952_pdata __initdata = {
105 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */ 118 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
106 .sync_freq = 0, /* default: fastest */ 119 .sync_freq = 0, /* default: fastest */
107 .ramp_speed = 0, /* default: fastest */ 120 .ramp_speed = 0, /* default: fastest */
108 121 .reg_data = &universal_max8952_reg_data,
109 .reg_data = {
110 .constraints = {
111 .name = "VARM_1.2V",
112 .min_uV = 770000,
113 .max_uV = 1400000,
114 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
115 .always_on = 1,
116 .boot_on = 1,
117 },
118 .num_consumer_supplies = 1,
119 .consumer_supplies = &max8952_consumer,
120 },
121}; 122};
122 123
123static struct regulator_consumer_supply lp3974_buck1_consumer = 124static struct regulator_consumer_supply lp3974_buck1_consumer =
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
index 1ab91b5209e6..85b728cc27ab 100644
--- a/arch/arm/mach-imx/clk-busy.c
+++ b/arch/arm/mach-imx/clk-busy.c
@@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
169 169
170 busy->mux.reg = reg; 170 busy->mux.reg = reg;
171 busy->mux.shift = shift; 171 busy->mux.shift = shift;
172 busy->mux.width = width; 172 busy->mux.mask = BIT(width) - 1;
173 busy->mux.lock = &imx_ccm_lock; 173 busy->mux.lock = &imx_ccm_lock;
174 busy->mux_ops = &clk_mux_ops; 174 busy->mux_ops = &clk_mux_ops;
175 175
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 2a17bc506cff..ff3c9f016591 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -5,6 +5,7 @@
5 * 5 *
6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com>
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> 7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com>
8 * Daniel Willerud <daniel.willerud@stericsson.com>
8 * 9 *
9 * MOP500 board specific initialization for regulators 10 * MOP500 board specific initialization for regulators
10 */ 11 */
@@ -12,6 +13,7 @@
12#include <linux/regulator/machine.h> 13#include <linux/regulator/machine.h>
13#include <linux/regulator/ab8500.h> 14#include <linux/regulator/ab8500.h>
14#include "board-mop500-regulators.h" 15#include "board-mop500-regulators.h"
16#include "id.h"
15 17
16static struct regulator_consumer_supply gpio_en_3v3_consumers[] = { 18static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
17 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), 19 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
@@ -53,21 +55,37 @@ struct regulator_init_data tps61052_regulator = {
53}; 55};
54 56
55static struct regulator_consumer_supply ab8500_vaux1_consumers[] = { 57static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
56 /* External displays, connector on board 2v5 power supply */ 58 /* Main display, u8500 R3 uib */
57 REGULATOR_SUPPLY("vaux12v5", "mcde.0"), 59 REGULATOR_SUPPLY("vddi", "mcde_disp_sony_acx424akp.0"),
60 /* Main display, u8500 uib and ST uib */
61 REGULATOR_SUPPLY("vdd1", "samsung_s6d16d0.0"),
62 /* Secondary display, ST uib */
63 REGULATOR_SUPPLY("vdd1", "samsung_s6d16d0.1"),
58 /* SFH7741 proximity sensor */ 64 /* SFH7741 proximity sensor */
59 REGULATOR_SUPPLY("vcc", "gpio-keys.0"), 65 REGULATOR_SUPPLY("vcc", "gpio-keys.0"),
60 /* BH1780GLS ambient light sensor */ 66 /* BH1780GLS ambient light sensor */
61 REGULATOR_SUPPLY("vcc", "2-0029"), 67 REGULATOR_SUPPLY("vcc", "2-0029"),
62 /* lsm303dlh accelerometer */ 68 /* lsm303dlh accelerometer */
63 REGULATOR_SUPPLY("vdd", "3-0018"), 69 REGULATOR_SUPPLY("vdd", "2-0018"),
70 /* lsm303dlhc accelerometer */
71 REGULATOR_SUPPLY("vdd", "2-0019"),
64 /* lsm303dlh magnetometer */ 72 /* lsm303dlh magnetometer */
65 REGULATOR_SUPPLY("vdd", "3-001e"), 73 REGULATOR_SUPPLY("vdd", "2-001e"),
66 /* Rohm BU21013 Touchscreen devices */ 74 /* Rohm BU21013 Touchscreen devices */
67 REGULATOR_SUPPLY("avdd", "3-005c"), 75 REGULATOR_SUPPLY("avdd", "3-005c"),
68 REGULATOR_SUPPLY("avdd", "3-005d"), 76 REGULATOR_SUPPLY("avdd", "3-005d"),
69 /* Synaptics RMI4 Touchscreen device */ 77 /* Synaptics RMI4 Touchscreen device */
70 REGULATOR_SUPPLY("vdd", "3-004b"), 78 REGULATOR_SUPPLY("vdd", "3-004b"),
79 /* L3G4200D Gyroscope device */
80 REGULATOR_SUPPLY("vdd", "2-0068"),
81 /* Ambient light sensor device */
82 REGULATOR_SUPPLY("vdd", "3-0029"),
83 /* Pressure sensor device */
84 REGULATOR_SUPPLY("vdd", "2-005c"),
85 /* Cypress TrueTouch Touchscreen device */
86 REGULATOR_SUPPLY("vcpin", "spi8.0"),
87 /* Camera device */
88 REGULATOR_SUPPLY("vaux12v5", "mmio_camera"),
71}; 89};
72 90
73static struct regulator_consumer_supply ab8500_vaux2_consumers[] = { 91static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
@@ -75,18 +93,50 @@ static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
75 REGULATOR_SUPPLY("vmmc", "sdi4"), 93 REGULATOR_SUPPLY("vmmc", "sdi4"),
76 /* AB8500 audio codec */ 94 /* AB8500 audio codec */
77 REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"), 95 REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"),
96 /* AB8500 accessory detect 1 */
97 REGULATOR_SUPPLY("vcc-N2158", "ab8500-acc-det.0"),
98 /* AB8500 Tv-out device */
99 REGULATOR_SUPPLY("vcc-N2158", "mcde_tv_ab8500.4"),
100 /* AV8100 HDMI device */
101 REGULATOR_SUPPLY("vcc-N2158", "av8100_hdmi.3"),
78}; 102};
79 103
80static struct regulator_consumer_supply ab8500_vaux3_consumers[] = { 104static struct regulator_consumer_supply ab8500_vaux3_consumers[] = {
105 REGULATOR_SUPPLY("v-SD-STM", "stm"),
81 /* External MMC slot power */ 106 /* External MMC slot power */
82 REGULATOR_SUPPLY("vmmc", "sdi0"), 107 REGULATOR_SUPPLY("vmmc", "sdi0"),
83}; 108};
84 109
110static struct regulator_consumer_supply ab8505_vaux4_consumers[] = {
111};
112
113static struct regulator_consumer_supply ab8505_vaux5_consumers[] = {
114};
115
116static struct regulator_consumer_supply ab8505_vaux6_consumers[] = {
117};
118
119static struct regulator_consumer_supply ab8505_vaux8_consumers[] = {
120 /* AB8500 audio codec device */
121 REGULATOR_SUPPLY("v-aux8", NULL),
122};
123
124static struct regulator_consumer_supply ab8505_vadc_consumers[] = {
125 /* Internal general-purpose ADC */
126 REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
127 /* ADC for charger */
128 REGULATOR_SUPPLY("vddadc", "ab8500-charger.0"),
129};
130
85static struct regulator_consumer_supply ab8500_vtvout_consumers[] = { 131static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
86 /* TV-out DENC supply */ 132 /* TV-out DENC supply */
87 REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"), 133 REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"),
88 /* Internal general-purpose ADC */ 134 /* Internal general-purpose ADC */
89 REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"), 135 REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
136 /* ADC for charger */
137 REGULATOR_SUPPLY("vddadc", "ab8500-charger.0"),
138 /* AB8500 Tv-out device */
139 REGULATOR_SUPPLY("vtvout", "mcde_tv_ab8500.4"),
90}; 140};
91 141
92static struct regulator_consumer_supply ab8500_vaud_consumers[] = { 142static struct regulator_consumer_supply ab8500_vaud_consumers[] = {
@@ -114,77 +164,90 @@ static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
114 REGULATOR_SUPPLY("v-intcore", NULL), 164 REGULATOR_SUPPLY("v-intcore", NULL),
115 /* USB Transceiver */ 165 /* USB Transceiver */
116 REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"), 166 REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"),
167 /* Handled by abx500 clk driver */
168 REGULATOR_SUPPLY("v-intcore", "abx500-clk.0"),
169};
170
171static struct regulator_consumer_supply ab8505_usb_consumers[] = {
172 /* HS USB OTG physical interface */
173 REGULATOR_SUPPLY("v-ape", NULL),
117}; 174};
118 175
119static struct regulator_consumer_supply ab8500_vana_consumers[] = { 176static struct regulator_consumer_supply ab8500_vana_consumers[] = {
120 /* External displays, connector on board, 1v8 power supply */ 177 /* DB8500 DSI */
121 REGULATOR_SUPPLY("vsmps2", "mcde.0"), 178 REGULATOR_SUPPLY("vdddsi1v2", "mcde"),
179 REGULATOR_SUPPLY("vdddsi1v2", "b2r2_core"),
180 REGULATOR_SUPPLY("vdddsi1v2", "b2r2_1_core"),
181 REGULATOR_SUPPLY("vdddsi1v2", "dsilink.0"),
182 REGULATOR_SUPPLY("vdddsi1v2", "dsilink.1"),
183 REGULATOR_SUPPLY("vdddsi1v2", "dsilink.2"),
184 /* DB8500 CSI */
185 REGULATOR_SUPPLY("vddcsi1v2", "mmio_camera"),
122}; 186};
123 187
124/* ab8500 regulator register initialization */ 188/* ab8500 regulator register initialization */
125struct ab8500_regulator_reg_init 189static struct ab8500_regulator_reg_init ab8500_reg_init[] = {
126ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
127 /* 190 /*
128 * VanaRequestCtrl = HP/LP depending on VxRequest 191 * VanaRequestCtrl = HP/LP depending on VxRequest
129 * VextSupply1RequestCtrl = HP/LP depending on VxRequest 192 * VextSupply1RequestCtrl = HP/LP depending on VxRequest
130 */ 193 */
131 INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0x00), 194 INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0xf0, 0x00),
132 /* 195 /*
133 * VextSupply2RequestCtrl = HP/LP depending on VxRequest 196 * VextSupply2RequestCtrl = HP/LP depending on VxRequest
134 * VextSupply3RequestCtrl = HP/LP depending on VxRequest 197 * VextSupply3RequestCtrl = HP/LP depending on VxRequest
135 * Vaux1RequestCtrl = HP/LP depending on VxRequest 198 * Vaux1RequestCtrl = HP/LP depending on VxRequest
136 * Vaux2RequestCtrl = HP/LP depending on VxRequest 199 * Vaux2RequestCtrl = HP/LP depending on VxRequest
137 */ 200 */
138 INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0x00), 201 INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0xff, 0x00),
139 /* 202 /*
140 * Vaux3RequestCtrl = HP/LP depending on VxRequest 203 * Vaux3RequestCtrl = HP/LP depending on VxRequest
141 * SwHPReq = Control through SWValid disabled 204 * SwHPReq = Control through SWValid disabled
142 */ 205 */
143 INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x00), 206 INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x07, 0x00),
144 /* 207 /*
145 * VanaSysClkReq1HPValid = disabled 208 * VanaSysClkReq1HPValid = disabled
146 * Vaux1SysClkReq1HPValid = disabled 209 * Vaux1SysClkReq1HPValid = disabled
147 * Vaux2SysClkReq1HPValid = disabled 210 * Vaux2SysClkReq1HPValid = disabled
148 * Vaux3SysClkReq1HPValid = disabled 211 * Vaux3SysClkReq1HPValid = disabled
149 */ 212 */
150 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0x00), 213 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0xe8, 0x00),
151 /* 214 /*
152 * VextSupply1SysClkReq1HPValid = disabled 215 * VextSupply1SysClkReq1HPValid = disabled
153 * VextSupply2SysClkReq1HPValid = disabled 216 * VextSupply2SysClkReq1HPValid = disabled
154 * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled 217 * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled
155 */ 218 */
156 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x40), 219 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x70, 0x40),
157 /* 220 /*
158 * VanaHwHPReq1Valid = disabled 221 * VanaHwHPReq1Valid = disabled
159 * Vaux1HwHPreq1Valid = disabled 222 * Vaux1HwHPreq1Valid = disabled
160 * Vaux2HwHPReq1Valid = disabled 223 * Vaux2HwHPReq1Valid = disabled
161 * Vaux3HwHPReqValid = disabled 224 * Vaux3HwHPReqValid = disabled
162 */ 225 */
163 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0x00), 226 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0xe8, 0x00),
164 /* 227 /*
165 * VextSupply1HwHPReq1Valid = disabled 228 * VextSupply1HwHPReq1Valid = disabled
166 * VextSupply2HwHPReq1Valid = disabled 229 * VextSupply2HwHPReq1Valid = disabled
167 * VextSupply3HwHPReq1Valid = disabled 230 * VextSupply3HwHPReq1Valid = disabled
168 */ 231 */
169 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x00), 232 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x07, 0x00),
170 /* 233 /*
171 * VanaHwHPReq2Valid = disabled 234 * VanaHwHPReq2Valid = disabled
172 * Vaux1HwHPReq2Valid = disabled 235 * Vaux1HwHPReq2Valid = disabled
173 * Vaux2HwHPReq2Valid = disabled 236 * Vaux2HwHPReq2Valid = disabled
174 * Vaux3HwHPReq2Valid = disabled 237 * Vaux3HwHPReq2Valid = disabled
175 */ 238 */
176 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0x00), 239 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0xe8, 0x00),
177 /* 240 /*
178 * VextSupply1HwHPReq2Valid = disabled 241 * VextSupply1HwHPReq2Valid = disabled
179 * VextSupply2HwHPReq2Valid = disabled 242 * VextSupply2HwHPReq2Valid = disabled
180 * VextSupply3HwHPReq2Valid = HWReq2 controlled 243 * VextSupply3HwHPReq2Valid = HWReq2 controlled
181 */ 244 */
182 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x04), 245 INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x07, 0x04),
183 /* 246 /*
184 * VanaSwHPReqValid = disabled 247 * VanaSwHPReqValid = disabled
185 * Vaux1SwHPReqValid = disabled 248 * Vaux1SwHPReqValid = disabled
186 */ 249 */
187 INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0x00), 250 INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0xa0, 0x00),
188 /* 251 /*
189 * Vaux2SwHPReqValid = disabled 252 * Vaux2SwHPReqValid = disabled
190 * Vaux3SwHPReqValid = disabled 253 * Vaux3SwHPReqValid = disabled
@@ -192,7 +255,7 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
192 * VextSupply2SwHPReqValid = disabled 255 * VextSupply2SwHPReqValid = disabled
193 * VextSupply3SwHPReqValid = disabled 256 * VextSupply3SwHPReqValid = disabled
194 */ 257 */
195 INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x00), 258 INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x1f, 0x00),
196 /* 259 /*
197 * SysClkReq2Valid1 = SysClkReq2 controlled 260 * SysClkReq2Valid1 = SysClkReq2 controlled
198 * SysClkReq3Valid1 = disabled 261 * SysClkReq3Valid1 = disabled
@@ -202,7 +265,7 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
202 * SysClkReq7Valid1 = disabled 265 * SysClkReq7Valid1 = disabled
203 * SysClkReq8Valid1 = disabled 266 * SysClkReq8Valid1 = disabled
204 */ 267 */
205 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0x2a), 268 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0xfe, 0x2a),
206 /* 269 /*
207 * SysClkReq2Valid2 = disabled 270 * SysClkReq2Valid2 = disabled
208 * SysClkReq3Valid2 = disabled 271 * SysClkReq3Valid2 = disabled
@@ -212,7 +275,7 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
212 * SysClkReq7Valid2 = disabled 275 * SysClkReq7Valid2 = disabled
213 * SysClkReq8Valid2 = disabled 276 * SysClkReq8Valid2 = disabled
214 */ 277 */
215 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0x20), 278 INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0xfe, 0x20),
216 /* 279 /*
217 * VTVoutEna = disabled 280 * VTVoutEna = disabled
218 * Vintcore12Ena = disabled 281 * Vintcore12Ena = disabled
@@ -220,66 +283,62 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
220 * Vintcore12LP = inactive (HP) 283 * Vintcore12LP = inactive (HP)
221 * VTVoutLP = inactive (HP) 284 * VTVoutLP = inactive (HP)
222 */ 285 */
223 INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0x10), 286 INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0xfe, 0x10),
224 /* 287 /*
225 * VaudioEna = disabled 288 * VaudioEna = disabled
226 * VdmicEna = disabled 289 * VdmicEna = disabled
227 * Vamic1Ena = disabled 290 * Vamic1Ena = disabled
228 * Vamic2Ena = disabled 291 * Vamic2Ena = disabled
229 */ 292 */
230 INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x00), 293 INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x1e, 0x00),
231 /* 294 /*
232 * Vamic1_dzout = high-Z when Vamic1 is disabled 295 * Vamic1_dzout = high-Z when Vamic1 is disabled
233 * Vamic2_dzout = high-Z when Vamic2 is disabled 296 * Vamic2_dzout = high-Z when Vamic2 is disabled
234 */ 297 */
235 INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x00), 298 INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x03, 0x00),
236 /* 299 /*
237 * VPll = Hw controlled 300 * VPll = Hw controlled (NOTE! PRCMU bits)
238 * VanaRegu = force off 301 * VanaRegu = force off
239 */ 302 */
240 INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x02), 303 INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x0f, 0x02),
241 /* 304 /*
242 * VrefDDREna = disabled 305 * VrefDDREna = disabled
243 * VrefDDRSleepMode = inactive (no pulldown) 306 * VrefDDRSleepMode = inactive (no pulldown)
244 */ 307 */
245 INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x00), 308 INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x03, 0x00),
246 /* 309 /*
247 * VextSupply1Regu = HW control 310 * VextSupply1Regu = force LP
248 * VextSupply2Regu = HW control 311 * VextSupply2Regu = force OFF
249 * VextSupply3Regu = HW control 312 * VextSupply3Regu = force HP (-> STBB2=LP and TPS=LP)
250 * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0 313 * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0
251 * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0 314 * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0
252 */ 315 */
253 INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0x2a), 316 INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0xff, 0x13),
254 /* 317 /*
255 * Vaux1Regu = force HP 318 * Vaux1Regu = force HP
256 * Vaux2Regu = force off 319 * Vaux2Regu = force off
257 */ 320 */
258 INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x01), 321 INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x0f, 0x01),
259 /* 322 /*
260 * Vaux3regu = force off 323 * Vaux3Regu = force off
261 */ 324 */
262 INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x00), 325 INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x03, 0x00),
263 /* 326 /*
264 * Vsmps1 = 1.15V 327 * Vaux1Sel = 2.8 V
265 */ 328 */
266 INIT_REGULATOR_REGISTER(AB8500_VSMPS1SEL1, 0x24), 329 INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x0f, 0x0C),
267 /*
268 * Vaux1Sel = 2.5 V
269 */
270 INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x08),
271 /* 330 /*
272 * Vaux2Sel = 2.9 V 331 * Vaux2Sel = 2.9 V
273 */ 332 */
274 INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0d), 333 INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0f, 0x0d),
275 /* 334 /*
276 * Vaux3Sel = 2.91 V 335 * Vaux3Sel = 2.91 V
277 */ 336 */
278 INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07), 337 INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07, 0x07),
279 /* 338 /*
280 * VextSupply12LP = disabled (no LP) 339 * VextSupply12LP = disabled (no LP)
281 */ 340 */
282 INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x00), 341 INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x01, 0x00),
283 /* 342 /*
284 * Vaux1Disch = short discharge time 343 * Vaux1Disch = short discharge time
285 * Vaux2Disch = short discharge time 344 * Vaux2Disch = short discharge time
@@ -288,33 +347,26 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
288 * VTVoutDisch = short discharge time 347 * VTVoutDisch = short discharge time
289 * VaudioDisch = short discharge time 348 * VaudioDisch = short discharge time
290 */ 349 */
291 INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0x00), 350 INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0xfc, 0x00),
292 /* 351 /*
293 * VanaDisch = short discharge time 352 * VanaDisch = short discharge time
294 * VdmicPullDownEna = pulldown disabled when Vdmic is disabled 353 * VdmicPullDownEna = pulldown disabled when Vdmic is disabled
295 * VdmicDisch = short discharge time 354 * VdmicDisch = short discharge time
296 */ 355 */
297 INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x00), 356 INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x16, 0x00),
298}; 357};
299 358
300/* AB8500 regulators */ 359/* AB8500 regulators */
301struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { 360static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
302 /* supplies to the display/camera */ 361 /* supplies to the display/camera */
303 [AB8500_LDO_AUX1] = { 362 [AB8500_LDO_AUX1] = {
304 .constraints = { 363 .constraints = {
305 .name = "V-DISPLAY", 364 .name = "V-DISPLAY",
306 .min_uV = 2500000, 365 .min_uV = 2800000,
307 .max_uV = 2900000, 366 .max_uV = 3300000,
308 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 367 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
309 REGULATOR_CHANGE_STATUS, 368 REGULATOR_CHANGE_STATUS,
310 .boot_on = 1, /* display is on at boot */ 369 .boot_on = 1, /* display is on at boot */
311 /*
312 * This voltage cannot be disabled right now because
313 * it is somehow affecting the external MMC
314 * functionality, though that typically will use
315 * AUX3.
316 */
317 .always_on = 1,
318 }, 370 },
319 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), 371 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
320 .consumer_supplies = ab8500_vaux1_consumers, 372 .consumer_supplies = ab8500_vaux1_consumers,
@@ -326,7 +378,10 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
326 .min_uV = 1100000, 378 .min_uV = 1100000,
327 .max_uV = 3300000, 379 .max_uV = 3300000,
328 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 380 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
329 REGULATOR_CHANGE_STATUS, 381 REGULATOR_CHANGE_STATUS |
382 REGULATOR_CHANGE_MODE,
383 .valid_modes_mask = REGULATOR_MODE_NORMAL |
384 REGULATOR_MODE_IDLE,
330 }, 385 },
331 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers), 386 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
332 .consumer_supplies = ab8500_vaux2_consumers, 387 .consumer_supplies = ab8500_vaux2_consumers,
@@ -338,7 +393,10 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
338 .min_uV = 1100000, 393 .min_uV = 1100000,
339 .max_uV = 3300000, 394 .max_uV = 3300000,
340 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 395 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
341 REGULATOR_CHANGE_STATUS, 396 REGULATOR_CHANGE_STATUS |
397 REGULATOR_CHANGE_MODE,
398 .valid_modes_mask = REGULATOR_MODE_NORMAL |
399 REGULATOR_MODE_IDLE,
342 }, 400 },
343 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers), 401 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
344 .consumer_supplies = ab8500_vaux3_consumers, 402 .consumer_supplies = ab8500_vaux3_consumers,
@@ -392,18 +450,614 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
392 [AB8500_LDO_INTCORE] = { 450 [AB8500_LDO_INTCORE] = {
393 .constraints = { 451 .constraints = {
394 .name = "V-INTCORE", 452 .name = "V-INTCORE",
395 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 453 .min_uV = 1250000,
454 .max_uV = 1350000,
455 .input_uV = 1800000,
456 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
457 REGULATOR_CHANGE_STATUS |
458 REGULATOR_CHANGE_MODE |
459 REGULATOR_CHANGE_DRMS,
460 .valid_modes_mask = REGULATOR_MODE_NORMAL |
461 REGULATOR_MODE_IDLE,
396 }, 462 },
397 .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers), 463 .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
398 .consumer_supplies = ab8500_vintcore_consumers, 464 .consumer_supplies = ab8500_vintcore_consumers,
399 }, 465 },
400 /* supply for U8500 CSI/DSI, VANA LDO */ 466 /* supply for U8500 CSI-DSI, VANA LDO */
401 [AB8500_LDO_ANA] = { 467 [AB8500_LDO_ANA] = {
402 .constraints = { 468 .constraints = {
403 .name = "V-CSI/DSI", 469 .name = "V-CSI-DSI",
404 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 470 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
405 }, 471 },
406 .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers), 472 .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
407 .consumer_supplies = ab8500_vana_consumers, 473 .consumer_supplies = ab8500_vana_consumers,
408 }, 474 },
409}; 475};
476
477/* supply for VextSupply3 */
478static struct regulator_consumer_supply ab8500_ext_supply3_consumers[] = {
479 /* SIM supply for 3 V SIM cards */
480 REGULATOR_SUPPLY("vinvsim", "sim-detect.0"),
481};
482
483/* extended configuration for VextSupply2, only used for HREFP_V20 boards */
484static struct ab8500_ext_regulator_cfg ab8500_ext_supply2 = {
485 .hwreq = true,
486};
487
488/*
489 * AB8500 external regulators
490 */
491static struct regulator_init_data ab8500_ext_regulators[] = {
492 /* fixed Vbat supplies VSMPS1_EXT_1V8 */
493 [AB8500_EXT_SUPPLY1] = {
494 .constraints = {
495 .name = "ab8500-ext-supply1",
496 .min_uV = 1800000,
497 .max_uV = 1800000,
498 .initial_mode = REGULATOR_MODE_IDLE,
499 .boot_on = 1,
500 .always_on = 1,
501 },
502 },
503 /* fixed Vbat supplies VSMPS2_EXT_1V36 and VSMPS5_EXT_1V15 */
504 [AB8500_EXT_SUPPLY2] = {
505 .constraints = {
506 .name = "ab8500-ext-supply2",
507 .min_uV = 1360000,
508 .max_uV = 1360000,
509 },
510 },
511 /* fixed Vbat supplies VSMPS3_EXT_3V4 and VSMPS4_EXT_3V4 */
512 [AB8500_EXT_SUPPLY3] = {
513 .constraints = {
514 .name = "ab8500-ext-supply3",
515 .min_uV = 3400000,
516 .max_uV = 3400000,
517 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
518 .boot_on = 1,
519 },
520 .num_consumer_supplies =
521 ARRAY_SIZE(ab8500_ext_supply3_consumers),
522 .consumer_supplies = ab8500_ext_supply3_consumers,
523 },
524};
525
526/* ab8505 regulator register initialization */
527static struct ab8500_regulator_reg_init ab8505_reg_init[] = {
528 /*
529 * VarmRequestCtrl
530 * VsmpsCRequestCtrl
531 * VsmpsARequestCtrl
532 * VsmpsBRequestCtrl
533 */
534 INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL1, 0x00, 0x00),
535 /*
536 * VsafeRequestCtrl
537 * VpllRequestCtrl
538 * VanaRequestCtrl = HP/LP depending on VxRequest
539 */
540 INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL2, 0x30, 0x00),
541 /*
542 * Vaux1RequestCtrl = HP/LP depending on VxRequest
543 * Vaux2RequestCtrl = HP/LP depending on VxRequest
544 */
545 INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL3, 0xf0, 0x00),
546 /*
547 * Vaux3RequestCtrl = HP/LP depending on VxRequest
548 * SwHPReq = Control through SWValid disabled
549 */
550 INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL4, 0x07, 0x00),
551 /*
552 * VsmpsASysClkReq1HPValid
553 * VsmpsBSysClkReq1HPValid
554 * VsafeSysClkReq1HPValid
555 * VanaSysClkReq1HPValid = disabled
556 * VpllSysClkReq1HPValid
557 * Vaux1SysClkReq1HPValid = disabled
558 * Vaux2SysClkReq1HPValid = disabled
559 * Vaux3SysClkReq1HPValid = disabled
560 */
561 INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQ1HPVALID1, 0xe8, 0x00),
562 /*
563 * VsmpsCSysClkReq1HPValid
564 * VarmSysClkReq1HPValid
565 * VbbSysClkReq1HPValid
566 * VsmpsMSysClkReq1HPValid
567 */
568 INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQ1HPVALID2, 0x00, 0x00),
569 /*
570 * VsmpsAHwHPReq1Valid
571 * VsmpsBHwHPReq1Valid
572 * VsafeHwHPReq1Valid
573 * VanaHwHPReq1Valid = disabled
574 * VpllHwHPReq1Valid
575 * Vaux1HwHPreq1Valid = disabled
576 * Vaux2HwHPReq1Valid = disabled
577 * Vaux3HwHPReqValid = disabled
578 */
579 INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ1VALID1, 0xe8, 0x00),
580 /*
581 * VsmpsMHwHPReq1Valid
582 */
583 INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ1VALID2, 0x00, 0x00),
584 /*
585 * VsmpsAHwHPReq2Valid
586 * VsmpsBHwHPReq2Valid
587 * VsafeHwHPReq2Valid
588 * VanaHwHPReq2Valid = disabled
589 * VpllHwHPReq2Valid
590 * Vaux1HwHPReq2Valid = disabled
591 * Vaux2HwHPReq2Valid = disabled
592 * Vaux3HwHPReq2Valid = disabled
593 */
594 INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ2VALID1, 0xe8, 0x00),
595 /*
596 * VsmpsMHwHPReq2Valid
597 */
598 INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ2VALID2, 0x00, 0x00),
599 /**
600 * VsmpsCSwHPReqValid
601 * VarmSwHPReqValid
602 * VsmpsASwHPReqValid
603 * VsmpsBSwHPReqValid
604 * VsafeSwHPReqValid
605 * VanaSwHPReqValid
606 * VanaSwHPReqValid = disabled
607 * VpllSwHPReqValid
608 * Vaux1SwHPReqValid = disabled
609 */
610 INIT_REGULATOR_REGISTER(AB8505_REGUSWHPREQVALID1, 0xa0, 0x00),
611 /*
612 * Vaux2SwHPReqValid = disabled
613 * Vaux3SwHPReqValid = disabled
614 * VsmpsMSwHPReqValid
615 */
616 INIT_REGULATOR_REGISTER(AB8505_REGUSWHPREQVALID2, 0x03, 0x00),
617 /*
618 * SysClkReq2Valid1 = SysClkReq2 controlled
619 * SysClkReq3Valid1 = disabled
620 * SysClkReq4Valid1 = SysClkReq4 controlled
621 */
622 INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQVALID1, 0x0e, 0x0a),
623 /*
624 * SysClkReq2Valid2 = disabled
625 * SysClkReq3Valid2 = disabled
626 * SysClkReq4Valid2 = disabled
627 */
628 INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQVALID2, 0x0e, 0x00),
629 /*
630 * Vaux4SwHPReqValid
631 * Vaux4HwHPReq2Valid
632 * Vaux4HwHPReq1Valid
633 * Vaux4SysClkReq1HPValid
634 */
635 INIT_REGULATOR_REGISTER(AB8505_REGUVAUX4REQVALID, 0x00, 0x00),
636 /*
637 * VadcEna = disabled
638 * VintCore12Ena = disabled
639 * VintCore12Sel = 1.25 V
640 * VintCore12LP = inactive (HP)
641 * VadcLP = inactive (HP)
642 */
643 INIT_REGULATOR_REGISTER(AB8505_REGUMISC1, 0xfe, 0x10),
644 /*
645 * VaudioEna = disabled
646 * Vaux8Ena = disabled
647 * Vamic1Ena = disabled
648 * Vamic2Ena = disabled
649 */
650 INIT_REGULATOR_REGISTER(AB8505_VAUDIOSUPPLY, 0x1e, 0x00),
651 /*
652 * Vamic1_dzout = high-Z when Vamic1 is disabled
653 * Vamic2_dzout = high-Z when Vamic2 is disabled
654 */
655 INIT_REGULATOR_REGISTER(AB8505_REGUCTRL1VAMIC, 0x03, 0x00),
656 /*
657 * VsmpsARegu
658 * VsmpsASelCtrl
659 * VsmpsAAutoMode
660 * VsmpsAPWMMode
661 */
662 INIT_REGULATOR_REGISTER(AB8505_VSMPSAREGU, 0x00, 0x00),
663 /*
664 * VsmpsBRegu
665 * VsmpsBSelCtrl
666 * VsmpsBAutoMode
667 * VsmpsBPWMMode
668 */
669 INIT_REGULATOR_REGISTER(AB8505_VSMPSBREGU, 0x00, 0x00),
670 /*
671 * VsafeRegu
672 * VsafeSelCtrl
673 * VsafeAutoMode
674 * VsafePWMMode
675 */
676 INIT_REGULATOR_REGISTER(AB8505_VSAFEREGU, 0x00, 0x00),
677 /*
678 * VPll = Hw controlled (NOTE! PRCMU bits)
679 * VanaRegu = force off
680 */
681 INIT_REGULATOR_REGISTER(AB8505_VPLLVANAREGU, 0x0f, 0x02),
682 /*
683 * VextSupply1Regu = force OFF (OTP_ExtSupply12LPnPolarity 1)
684 * VextSupply2Regu = force OFF (OTP_ExtSupply12LPnPolarity 1)
685 * VextSupply3Regu = force OFF (OTP_ExtSupply3LPnPolarity 0)
686 * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0
687 * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0
688 */
689 INIT_REGULATOR_REGISTER(AB8505_EXTSUPPLYREGU, 0xff, 0x30),
690 /*
691 * Vaux1Regu = force HP
692 * Vaux2Regu = force off
693 */
694 INIT_REGULATOR_REGISTER(AB8505_VAUX12REGU, 0x0f, 0x01),
695 /*
696 * Vaux3Regu = force off
697 */
698 INIT_REGULATOR_REGISTER(AB8505_VRF1VAUX3REGU, 0x03, 0x00),
699 /*
700 * VsmpsASel1
701 */
702 INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL1, 0x00, 0x00),
703 /*
704 * VsmpsASel2
705 */
706 INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL2, 0x00, 0x00),
707 /*
708 * VsmpsASel3
709 */
710 INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL3, 0x00, 0x00),
711 /*
712 * VsmpsBSel1
713 */
714 INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL1, 0x00, 0x00),
715 /*
716 * VsmpsBSel2
717 */
718 INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL2, 0x00, 0x00),
719 /*
720 * VsmpsBSel3
721 */
722 INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL3, 0x00, 0x00),
723 /*
724 * VsafeSel1
725 */
726 INIT_REGULATOR_REGISTER(AB8505_VSAFESEL1, 0x00, 0x00),
727 /*
728 * VsafeSel2
729 */
730 INIT_REGULATOR_REGISTER(AB8505_VSAFESEL2, 0x00, 0x00),
731 /*
732 * VsafeSel3
733 */
734 INIT_REGULATOR_REGISTER(AB8505_VSAFESEL3, 0x00, 0x00),
735 /*
736 * Vaux1Sel = 2.8 V
737 */
738 INIT_REGULATOR_REGISTER(AB8505_VAUX1SEL, 0x0f, 0x0C),
739 /*
740 * Vaux2Sel = 2.9 V
741 */
742 INIT_REGULATOR_REGISTER(AB8505_VAUX2SEL, 0x0f, 0x0d),
743 /*
744 * Vaux3Sel = 2.91 V
745 */
746 INIT_REGULATOR_REGISTER(AB8505_VRF1VAUX3SEL, 0x07, 0x07),
747 /*
748 * Vaux4RequestCtrl
749 */
750 INIT_REGULATOR_REGISTER(AB8505_VAUX4REQCTRL, 0x00, 0x00),
751 /*
752 * Vaux4Regu
753 */
754 INIT_REGULATOR_REGISTER(AB8505_VAUX4REGU, 0x00, 0x00),
755 /*
756 * Vaux4Sel
757 */
758 INIT_REGULATOR_REGISTER(AB8505_VAUX4SEL, 0x00, 0x00),
759 /*
760 * Vaux1Disch = short discharge time
761 * Vaux2Disch = short discharge time
762 * Vaux3Disch = short discharge time
763 * Vintcore12Disch = short discharge time
764 * VTVoutDisch = short discharge time
765 * VaudioDisch = short discharge time
766 */
767 INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH, 0xfc, 0x00),
768 /*
769 * VanaDisch = short discharge time
770 * Vaux8PullDownEna = pulldown disabled when Vaux8 is disabled
771 * Vaux8Disch = short discharge time
772 */
773 INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH2, 0x16, 0x00),
774 /*
775 * Vaux4Disch = short discharge time
776 */
777 INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH3, 0x01, 0x00),
778 /*
779 * Vaux5Sel
780 * Vaux5LP
781 * Vaux5Ena
782 * Vaux5Disch
783 * Vaux5DisSfst
784 * Vaux5DisPulld
785 */
786 INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX5, 0x00, 0x00),
787 /*
788 * Vaux6Sel
789 * Vaux6LP
790 * Vaux6Ena
791 * Vaux6DisPulld
792 */
793 INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX6, 0x00, 0x00),
794};
795
796struct regulator_init_data ab8505_regulators[AB8505_NUM_REGULATORS] = {
797 /* supplies to the display/camera */
798 [AB8505_LDO_AUX1] = {
799 .constraints = {
800 .name = "V-DISPLAY",
801 .min_uV = 2800000,
802 .max_uV = 3300000,
803 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
804 REGULATOR_CHANGE_STATUS,
805 .boot_on = 1, /* display is on at boot */
806 },
807 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
808 .consumer_supplies = ab8500_vaux1_consumers,
809 },
810 /* supplies to the on-board eMMC */
811 [AB8505_LDO_AUX2] = {
812 .constraints = {
813 .name = "V-eMMC1",
814 .min_uV = 1100000,
815 .max_uV = 3300000,
816 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
817 REGULATOR_CHANGE_STATUS |
818 REGULATOR_CHANGE_MODE,
819 .valid_modes_mask = REGULATOR_MODE_NORMAL |
820 REGULATOR_MODE_IDLE,
821 },
822 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
823 .consumer_supplies = ab8500_vaux2_consumers,
824 },
825 /* supply for VAUX3, supplies to SDcard slots */
826 [AB8505_LDO_AUX3] = {
827 .constraints = {
828 .name = "V-MMC-SD",
829 .min_uV = 1100000,
830 .max_uV = 3300000,
831 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
832 REGULATOR_CHANGE_STATUS |
833 REGULATOR_CHANGE_MODE,
834 .valid_modes_mask = REGULATOR_MODE_NORMAL |
835 REGULATOR_MODE_IDLE,
836 },
837 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
838 .consumer_supplies = ab8500_vaux3_consumers,
839 },
840 /* supply for VAUX4, supplies to NFC and standalone secure element */
841 [AB8505_LDO_AUX4] = {
842 .constraints = {
843 .name = "V-NFC-SE",
844 .min_uV = 1100000,
845 .max_uV = 3300000,
846 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
847 REGULATOR_CHANGE_STATUS |
848 REGULATOR_CHANGE_MODE,
849 .valid_modes_mask = REGULATOR_MODE_NORMAL |
850 REGULATOR_MODE_IDLE,
851 },
852 .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux4_consumers),
853 .consumer_supplies = ab8505_vaux4_consumers,
854 },
855 /* supply for VAUX5, supplies to TBD */
856 [AB8505_LDO_AUX5] = {
857 .constraints = {
858 .name = "V-AUX5",
859 .min_uV = 1050000,
860 .max_uV = 2790000,
861 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
862 REGULATOR_CHANGE_STATUS |
863 REGULATOR_CHANGE_MODE,
864 .valid_modes_mask = REGULATOR_MODE_NORMAL |
865 REGULATOR_MODE_IDLE,
866 },
867 .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux5_consumers),
868 .consumer_supplies = ab8505_vaux5_consumers,
869 },
870 /* supply for VAUX6, supplies to TBD */
871 [AB8505_LDO_AUX6] = {
872 .constraints = {
873 .name = "V-AUX6",
874 .min_uV = 1050000,
875 .max_uV = 2790000,
876 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
877 REGULATOR_CHANGE_STATUS |
878 REGULATOR_CHANGE_MODE,
879 .valid_modes_mask = REGULATOR_MODE_NORMAL |
880 REGULATOR_MODE_IDLE,
881 },
882 .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux6_consumers),
883 .consumer_supplies = ab8505_vaux6_consumers,
884 },
885 /* supply for gpadc, ADC LDO */
886 [AB8505_LDO_ADC] = {
887 .constraints = {
888 .name = "V-ADC",
889 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
890 },
891 .num_consumer_supplies = ARRAY_SIZE(ab8505_vadc_consumers),
892 .consumer_supplies = ab8505_vadc_consumers,
893 },
894 /* supply for ab8500-vaudio, VAUDIO LDO */
895 [AB8505_LDO_AUDIO] = {
896 .constraints = {
897 .name = "V-AUD",
898 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
899 },
900 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers),
901 .consumer_supplies = ab8500_vaud_consumers,
902 },
903 /* supply for v-anamic1 VAMic1-LDO */
904 [AB8505_LDO_ANAMIC1] = {
905 .constraints = {
906 .name = "V-AMIC1",
907 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
908 REGULATOR_CHANGE_MODE,
909 .valid_modes_mask = REGULATOR_MODE_NORMAL |
910 REGULATOR_MODE_IDLE,
911 },
912 .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers),
913 .consumer_supplies = ab8500_vamic1_consumers,
914 },
915 /* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
916 [AB8505_LDO_ANAMIC2] = {
917 .constraints = {
918 .name = "V-AMIC2",
919 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
920 REGULATOR_CHANGE_MODE,
921 .valid_modes_mask = REGULATOR_MODE_NORMAL |
922 REGULATOR_MODE_IDLE,
923 },
924 .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers),
925 .consumer_supplies = ab8500_vamic2_consumers,
926 },
927 /* supply for v-aux8, VAUX8 LDO */
928 [AB8505_LDO_AUX8] = {
929 .constraints = {
930 .name = "V-AUX8",
931 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
932 },
933 .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux8_consumers),
934 .consumer_supplies = ab8505_vaux8_consumers,
935 },
936 /* supply for v-intcore12, VINTCORE12 LDO */
937 [AB8505_LDO_INTCORE] = {
938 .constraints = {
939 .name = "V-INTCORE",
940 .min_uV = 1250000,
941 .max_uV = 1350000,
942 .input_uV = 1800000,
943 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
944 REGULATOR_CHANGE_STATUS |
945 REGULATOR_CHANGE_MODE |
946 REGULATOR_CHANGE_DRMS,
947 .valid_modes_mask = REGULATOR_MODE_NORMAL |
948 REGULATOR_MODE_IDLE,
949 },
950 .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
951 .consumer_supplies = ab8500_vintcore_consumers,
952 },
953 /* supply for LDO USB */
954 [AB8505_LDO_USB] = {
955 .constraints = {
956 .name = "V-USB",
957 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
958 REGULATOR_CHANGE_MODE,
959 .valid_modes_mask = REGULATOR_MODE_NORMAL |
960 REGULATOR_MODE_IDLE,
961 },
962 .num_consumer_supplies = ARRAY_SIZE(ab8505_usb_consumers),
963 .consumer_supplies = ab8505_usb_consumers,
964 },
965 /* supply for U8500 CSI-DSI, VANA LDO */
966 [AB8505_LDO_ANA] = {
967 .constraints = {
968 .name = "V-CSI-DSI",
969 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
970 },
971 .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
972 .consumer_supplies = ab8500_vana_consumers,
973 },
974};
975
976struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
977 .reg_init = ab8500_reg_init,
978 .num_reg_init = ARRAY_SIZE(ab8500_reg_init),
979 .regulator = ab8500_regulators,
980 .num_regulator = ARRAY_SIZE(ab8500_regulators),
981 .ext_regulator = ab8500_ext_regulators,
982 .num_ext_regulator = ARRAY_SIZE(ab8500_ext_regulators),
983};
984
985/* Use the AB8500 init settings for AB8505 as they are the same right now */
986struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
987 .reg_init = ab8505_reg_init,
988 .num_reg_init = ARRAY_SIZE(ab8505_reg_init),
989 .regulator = ab8505_regulators,
990 .num_regulator = ARRAY_SIZE(ab8505_regulators),
991};
992
993static void ab8500_modify_reg_init(int id, u8 mask, u8 value)
994{
995 int i;
996
997 if (cpu_is_u8520()) {
998 for (i = ARRAY_SIZE(ab8505_reg_init) - 1; i >= 0; i--) {
999 if (ab8505_reg_init[i].id == id) {
1000 u8 initval = ab8505_reg_init[i].value;
1001 initval = (initval & ~mask) | (value & mask);
1002 ab8505_reg_init[i].value = initval;
1003
1004 BUG_ON(mask & ~ab8505_reg_init[i].mask);
1005 return;
1006 }
1007 }
1008 } else {
1009 for (i = ARRAY_SIZE(ab8500_reg_init) - 1; i >= 0; i--) {
1010 if (ab8500_reg_init[i].id == id) {
1011 u8 initval = ab8500_reg_init[i].value;
1012 initval = (initval & ~mask) | (value & mask);
1013 ab8500_reg_init[i].value = initval;
1014
1015 BUG_ON(mask & ~ab8500_reg_init[i].mask);
1016 return;
1017 }
1018 }
1019 }
1020
1021 BUG_ON(1);
1022}
1023
1024void mop500_regulator_init(void)
1025{
1026 struct regulator_init_data *regulator;
1027
1028 /*
1029 * Temporarily turn on Vaux2 on 8520 machine
1030 */
1031 if (cpu_is_u8520()) {
1032 /* Vaux2 initialized to be on */
1033 ab8500_modify_reg_init(AB8505_VAUX12REGU, 0x0f, 0x05);
1034 }
1035
1036 /*
1037 * Handle AB8500_EXT_SUPPLY2 on HREFP_V20_V50 boards (do it for
1038 * all HREFP_V20 boards)
1039 */
1040 if (cpu_is_u8500v20()) {
1041 /* VextSupply2RequestCtrl = HP/OFF depending on VxRequest */
1042 ab8500_modify_reg_init(AB8500_REGUREQUESTCTRL3, 0x01, 0x01);
1043
1044 /* VextSupply2SysClkReq1HPValid = SysClkReq1 controlled */
1045 ab8500_modify_reg_init(AB8500_REGUSYSCLKREQ1HPVALID2,
1046 0x20, 0x20);
1047
1048 /* VextSupply2 = force HP at initialization */
1049 ab8500_modify_reg_init(AB8500_EXTSUPPLYREGU, 0x0c, 0x04);
1050
1051 /* enable VextSupply2 during platform active */
1052 regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2];
1053 regulator->constraints.always_on = 1;
1054
1055 /* disable VextSupply2 in suspend */
1056 regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2];
1057 regulator->constraints.state_mem.disabled = 1;
1058 regulator->constraints.state_standby.disabled = 1;
1059
1060 /* enable VextSupply2 HW control (used in suspend) */
1061 regulator->driver_data = (void *)&ab8500_ext_supply2;
1062 }
1063}
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 78a0642a2206..9bece38fe933 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -14,10 +14,11 @@
14#include <linux/regulator/machine.h> 14#include <linux/regulator/machine.h>
15#include <linux/regulator/ab8500.h> 15#include <linux/regulator/ab8500.h>
16 16
17extern struct ab8500_regulator_reg_init 17extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
18ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS]; 18extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
19extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
20extern struct regulator_init_data tps61052_regulator; 19extern struct regulator_init_data tps61052_regulator;
21extern struct regulator_init_data gpio_en_3v3_regulator; 20extern struct regulator_init_data gpio_en_3v3_regulator;
22 21
22void mop500_regulator_init(void);
23
23#endif 24#endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 87d2d7b38ce9..ce672378a830 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -199,10 +199,7 @@ static struct platform_device snowball_sbnet_dev = {
199 199
200struct ab8500_platform_data ab8500_platdata = { 200struct ab8500_platform_data ab8500_platdata = {
201 .irq_base = MOP500_AB8500_IRQ_BASE, 201 .irq_base = MOP500_AB8500_IRQ_BASE,
202 .regulator_reg_init = ab8500_regulator_reg_init, 202 .regulator = &ab8500_regulator_plat_data,
203 .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init),
204 .regulator = ab8500_regulators,
205 .num_regulator = ARRAY_SIZE(ab8500_regulators),
206 .gpio = &ab8500_gpio_pdata, 203 .gpio = &ab8500_gpio_pdata,
207 .codec = &ab8500_codec_pdata, 204 .codec = &ab8500_codec_pdata,
208}; 205};
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 915683cb67d6..c5e20b52e3b7 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -21,6 +21,8 @@
21#include <linux/regulator/fixed.h> 21#include <linux/regulator/fixed.h>
22#include <linux/regulator/machine.h> 22#include <linux/regulator/machine.h>
23#include <linux/vexpress.h> 23#include <linux/vexpress.h>
24#include <linux/clk-provider.h>
25#include <linux/clkdev.h>
24 26
25#include <asm/arch_timer.h> 27#include <asm/arch_timer.h>
26#include <asm/mach-types.h> 28#include <asm/mach-types.h>
@@ -433,7 +435,7 @@ static void __init v2m_dt_timer_init(void)
433{ 435{
434 struct device_node *node = NULL; 436 struct device_node *node = NULL;
435 437
436 vexpress_clk_of_init(); 438 of_clk_init(NULL);
437 439
438 do { 440 do {
439 node = of_find_compatible_node(node, NULL, "arm,sp804"); 441 node = of_find_compatible_node(node, NULL, "arm,sp804");
@@ -441,6 +443,10 @@ static void __init v2m_dt_timer_init(void)
441 if (node) { 443 if (node) {
442 pr_info("Using SP804 '%s' as a clock & events source\n", 444 pr_info("Using SP804 '%s' as a clock & events source\n",
443 node->full_name); 445 node->full_name);
446 WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
447 "timclken1"), "v2m-timer0", "sp804"));
448 WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
449 "timclken2"), "v2m-timer1", "sp804"));
444 v2m_sp804_init(of_iomap(node, 0), 450 v2m_sp804_init(of_iomap(node, 0),
445 irq_of_parse_and_map(node, 0)); 451 irq_of_parse_and_map(node, 0));
446 } 452 }
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 51afedda9ab6..03db14d8ace9 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -10,6 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <linux/amba/pl330.h>
13#include <linux/kernel.h> 14#include <linux/kernel.h>
14#include <linux/types.h> 15#include <linux/types.h>
15#include <linux/interrupt.h> 16#include <linux/interrupt.h>
@@ -1552,6 +1553,9 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1552 pd.num_cs = num_cs; 1553 pd.num_cs = num_cs;
1553 pd.src_clk_nr = src_clk_nr; 1554 pd.src_clk_nr = src_clk_nr;
1554 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; 1555 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
1556#ifdef CONFIG_PL330_DMA
1557 pd.filter = pl330_filter;
1558#endif
1555 1559
1556 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0); 1560 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
1557} 1561}
@@ -1590,6 +1594,9 @@ void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1590 pd.num_cs = num_cs; 1594 pd.num_cs = num_cs;
1591 pd.src_clk_nr = src_clk_nr; 1595 pd.src_clk_nr = src_clk_nr;
1592 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; 1596 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
1597#ifdef CONFIG_PL330_DMA
1598 pd.filter = pl330_filter;
1599#endif
1593 1600
1594 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); 1601 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
1595} 1602}
@@ -1628,6 +1635,9 @@ void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1628 pd.num_cs = num_cs; 1635 pd.num_cs = num_cs;
1629 pd.src_clk_nr = src_clk_nr; 1636 pd.src_clk_nr = src_clk_nr;
1630 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; 1637 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
1638#ifdef CONFIG_PL330_DMA
1639 pd.filter = pl330_filter;
1640#endif
1631 1641
1632 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); 1642 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
1633} 1643}
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
index f1c9c3e2f678..e97fd60e92ef 100644
--- a/arch/mips/bcm63xx/dev-spi.c
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -85,20 +85,9 @@ static struct platform_device bcm63xx_spi_device = {
85 85
86int __init bcm63xx_spi_register(void) 86int __init bcm63xx_spi_register(void)
87{ 87{
88 struct clk *periph_clk;
89
90 if (BCMCPU_IS_6328() || BCMCPU_IS_6345()) 88 if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
91 return -ENODEV; 89 return -ENODEV;
92 90
93 periph_clk = clk_get(NULL, "periph");
94 if (IS_ERR(periph_clk)) {
95 pr_err("unable to get periph clock\n");
96 return -ENODEV;
97 }
98
99 /* Set bus frequency */
100 spi_pdata.speed_hz = clk_get_rate(periph_clk);
101
102 spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); 91 spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
103 spi_resources[0].end = spi_resources[0].start; 92 spi_resources[0].end = spi_resources[0].start;
104 spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI); 93 spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
index c9bae1362606..b0184cf02575 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -13,7 +13,6 @@ struct bcm63xx_spi_pdata {
13 unsigned int msg_ctl_width; 13 unsigned int msg_ctl_width;
14 int bus_num; 14 int bus_num;
15 int num_chipselect; 15 int num_chipselect;
16 u32 speed_hz;
17}; 16};
18 17
19enum bcm63xx_regs_spi { 18enum bcm63xx_regs_spi {
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index b8020dc7b71e..fa33c546e778 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -22,6 +22,7 @@
22#include <linux/pfn.h> 22#include <linux/pfn.h>
23#include <linux/cpuset.h> 23#include <linux/cpuset.h>
24#include <linux/node.h> 24#include <linux/node.h>
25#include <linux/slab.h>
25#include <asm/sparsemem.h> 26#include <asm/sparsemem.h>
26#include <asm/prom.h> 27#include <asm/prom.h>
27#include <asm/smp.h> 28#include <asm/smp.h>
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index c2c85f6cd738..a162a7f86b2e 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -35,7 +35,7 @@ static unsigned int nr_ports;
35 35
36static struct sh7786_pcie_hwops { 36static struct sh7786_pcie_hwops {
37 int (*core_init)(void); 37 int (*core_init)(void);
38 async_func_ptr *port_init_hw; 38 async_func_t port_init_hw;
39} *sh7786_pcie_hwops; 39} *sh7786_pcie_hwops;
40 40
41static struct resource sh7786_pci0_resources[] = { 41static struct resource sh7786_pci0_resources[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 09:31:11 -0500