105 files changed, 6798 insertions, 1682 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index db524e75c4a2..0f3417065d13 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -9,7 +9,7 @@ config ARM
        select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
        select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
        select HAVE_ARCH_KGDB
-        select HAVE_KPROBES if (!XIP_KERNEL)
+        select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
        select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
@@ -351,6 +351,14 @@ config ARCH_MXC
        help
          Support for Freescale MXC/iMX-based family of processors
+config ARCH_MXS
+        bool "Freescale MXS-based"
+        select GENERIC_CLOCKEVENTS
+        select ARCH_REQUIRE_GPIOLIB
+        select COMMON_CLKDEV
+        help
+          Support for Freescale MXS-based family of processors
 config ARCH_STMP3XXX
        bool "Freescale STMP3xxx"
        select CPU_ARM926T
@@ -902,6 +910,8 @@ source "arch/arm/mach-mv78xx0/Kconfig"
 source "arch/arm/plat-mxc/Kconfig"
+source "arch/arm/mach-mxs/Kconfig"
 source "arch/arm/mach-netx/Kconfig"
 source "arch/arm/mach-nomadik/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 057beb8ee203..c22c1adfedd6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -158,6 +158,7 @@ machine-$(CONFIG_ARCH_MX25)		:= imx
 machine-$(CONFIG_ARCH_MX3)              := mx3
 machine-$(CONFIG_ARCH_MX5)              := mx5
 machine-$(CONFIG_ARCH_MXC91231)         := mxc91231
+machine-$(CONFIG_ARCH_MXS)              := mxs
 machine-$(CONFIG_ARCH_NETX)             := netx
 machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
 machine-$(CONFIG_ARCH_NS9XXX)           := ns9xxx
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4113e2..4d26f2c52a75 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -70,12 +70,7 @@ else
 $(obj)/uImage: LOADADDR=$(ZRELADDR)
 endif
-ifeq ($(CONFIG_THUMB2_KERNEL),y)
-# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
-$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")
-else
 $(obj)/uImage: STARTADDR=$(LOADADDR)
-endif
 $(obj)/uImage:  $(obj)/zImage FORCE
        $(call if_changed,uimage)
diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S
index 8b0de41c3dcb..78b508075161 100644
--- a/arch/arm/boot/bootp/init.S
+++ b/arch/arm/boot/bootp/init.S
@@ -73,6 +73,8 @@ move:		ldmia	r4!, {r7 - r10}		@ move 32-bytes at a time
                .size   _start, . - _start
+                .align
                .type   data,#object
 data:           .word   initrd_start            @ source initrd address
                .word   initrd_phys             @ destination initrd address
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 9be21ba648cd..7193884ed8b0 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -125,9 +125,13 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 * sort out different calling conventions
 */
                .align
+                .arm                            @ Always enter in ARM state
 start:
                .type   start,#function
-                .rept   8
+ THUMB(         adr     r12, BSYM(1f)   )
+ THUMB(         bx      r12             )
+ THUMB(         .rept   6               )
+ ARM(           .rept   8               )
                mov     r0, r0
                .endr
@@ -135,6 +139,7 @@ start:
                .word   0x016f2818              @ Magic numbers to help the loader
                .word   start                   @ absolute load/run zImage address
                .word   _edata                  @ zImage end address
+ THUMB(         .thumb                  )
 1:              mov     r7, r1                  @ save architecture ID
                mov     r8, r2                  @ save atags pointer
@@ -174,7 +179,8 @@ not_angel:
                ldr     sp, [r0, #28]
 #ifdef CONFIG_AUTO_ZRELADDR
                @ determine final kernel image address
-                and     r4, pc, #0xf8000000
+                mov     r4, pc
+                and     r4, r4, #0xf8000000
                add     r4, r4, #TEXT_OFFSET
 #else
                ldr     r4, =zreladdr
@@ -445,7 +451,8 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
 */
                mov     r1, #0x1e
                orr     r1, r1, #3 << 10
-                mov     r2, pc, lsr #20
+                mov     r2, pc
+                mov     r2, r2, lsr #20
                orr     r1, r1, r2, lsl #20
                add     r0, r3, r2, lsl #2
                str     r1, [r0], #4
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 772f95f1aecd..e6388dcd8cfa 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -146,9 +146,15 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
        unsigned int shift = (irq % 4) * 8;
        unsigned int cpu = cpumask_first(mask_val);
        u32 val;
+        struct irq_desc *desc;
        spin_lock(&irq_controller_lock);
-        irq_desc[irq].node = cpu;
+        desc = irq_to_desc(irq);
+        if (desc == NULL) {
+                spin_unlock(&irq_controller_lock);
+                return -EINVAL;
+        }
+        desc->node = cpu;
        val = readl(reg) & ~(0xff << shift);
        val |= 1 << (cpu + shift);
        writel(val, reg);
@@ -210,7 +216,7 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
                          unsigned int irq_start)
 {
-        unsigned int max_irq, i;
+        unsigned int gic_irqs, irq_limit, i;
        u32 cpumask = 1 << smp_processor_id();
        if (gic_nr >= MAX_GIC_NR)
@@ -226,47 +232,49 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
        /*
         * Find out how many interrupts are supported.
-         */
-        max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
-        max_irq = (max_irq + 1) * 32;
-        /*
         * The GIC only supports up to 1020 interrupt sources.
-         * Limit this to either the architected maximum, or the
-         * platform maximum.
         */
-        if (max_irq > max(1020, NR_IRQS))
+        gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
-                max_irq = max(1020, NR_IRQS);
+        gic_irqs = (gic_irqs + 1) * 32;
+        if (gic_irqs > 1020)
+                gic_irqs = 1020;
        /*
         * Set all global interrupts to be level triggered, active low.
         */
-        for (i = 32; i < max_irq; i += 16)
+        for (i = 32; i < gic_irqs; i += 16)
                writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
        /*
         * Set all global interrupts to this CPU only.
         */
-        for (i = 32; i < max_irq; i += 4)
+        for (i = 32; i < gic_irqs; i += 4)
                writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
        /*
         * Set priority on all global interrupts.
         */
-        for (i = 32; i < max_irq; i += 4)
+        for (i = 32; i < gic_irqs; i += 4)
                writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
        /*
         * Disable all interrupts.  Leave the PPI and SGIs alone
         * as these enables are banked registers.
         */
-        for (i = 32; i < max_irq; i += 32)
+        for (i = 32; i < gic_irqs; i += 32)
                writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
        /*
+         * Limit number of interrupts registered to the platform maximum
+         */
+        irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;
+        if (WARN_ON(irq_limit > NR_IRQS))
+                irq_limit = NR_IRQS;
+        /*
         * Setup the Linux IRQ subsystem.
         */
-        for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
+        for (i = irq_start; i < irq_limit; i++) {
                set_irq_chip(i, &gic_chip);
                set_irq_chip_data(i, &gic_data[gic_nr]);
                set_irq_handler(i, handle_level_irq);
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
new file mode 100644
index 000000000000..38cb7c985426
--- /dev/null
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -0,0 +1,341 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_AT91=y
+CONFIG_MACH_ONEARM=y
+CONFIG_ARCH_AT91RM9200DK=y
+CONFIG_MACH_AT91RM9200EK=y
+CONFIG_MACH_CSB337=y
+CONFIG_MACH_CSB637=y
+CONFIG_MACH_CARMEVA=y
+CONFIG_MACH_ATEB9200=y
+CONFIG_MACH_KB9200=y
+CONFIG_MACH_PICOTUX2XX=y
+CONFIG_MACH_KAFA=y
+CONFIG_MACH_ECBAT91=y
+CONFIG_MACH_YL9200=y
+CONFIG_MACH_CPUAT91=y
+CONFIG_MACH_ECO920=y
+CONFIG_MTD_AT91_DATAFLASH_CARD=y
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=100
+# CONFIG_ARM_THUMB is not set
+CONFIG_PCCARD=y
+CONFIG_AT91_CF=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_ZBOOT_ROM_TEXT=0x10000000
+CONFIG_ZBOOT_ROM_BSS=0x20040000
+CONFIG_KEXEC=y
+CONFIG_FPE_NWFPE=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_ATMEL_TCLIB=y
+CONFIG_EEPROM_LEGACY=m
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_TUN=m
+CONFIG_PHYLIB=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_EPSON2888=y
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_LEGACY_PTY_COUNT=32
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_BITBANG=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HWMON=m
+CONFIG_SENSORS_ADM1021=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+CONFIG_SENSORS_ADM9240=m
+CONFIG_SENSORS_DS1621=m
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_IT87=m
+CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM73=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_MAX1619=m
+CONFIG_SENSORS_PCF8591=m
+CONFIG_SENSORS_SMSC47B397=m
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83L785TS=m
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_AT91RM9200_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_S1D13XXX=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_DISPLAY_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_MINI_4x6=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_MCT_U232=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_MMC=y
+CONFIG_MMC_AT91=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_REISERFS_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_CRAMFS=y
+CONFIG_MINIX_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_SMB_FS=m
+CONFIG_CIFS=m
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_SHA1=y
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
deleted file mode 100644
index 4438e64f3bfb..000000000000
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200DK=y
-CONFIG_MACH_ECO920=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_AT91_CF=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
deleted file mode 100644
index ccd517c64bc7..000000000000
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_AT91RM9200EK=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_S1D13XXX=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig
deleted file mode 100644
index 1b0e9a1689bb..000000000000
--- a/arch/arm/configs/ateb9200_defconfig
+++ /dev/null
@@ -1,131 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_ATEB9200=y
-CONFIG_PCCARD=m
-CONFIG_AT91_CF=m
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK_RO=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_TUN=m
-CONFIG_PHYLIB=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_NET_GL620A=y
-CONFIG_USB_NET_PLUSB=y
-CONFIG_USB_NET_RNDIS_HOST=y
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPPOE=m
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=m
-CONFIG_MMC_DEBUG=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-CONFIG_REISERFS_FS=m
-CONFIG_INOTIFY=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRC16=m
-CONFIG_LIBCRC32C=m
diff --git a/arch/arm/configs/carmeva_defconfig b/arch/arm/configs/carmeva_defconfig
deleted file mode 100644
index ac64dbd8a49c..000000000000
--- a/arch/arm/configs/carmeva_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_HOTPLUG is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_CARMEVA=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIO=m
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_MMC=m
-CONFIG_MMC_DEBUG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
diff --git a/arch/arm/configs/cpuat91_defconfig b/arch/arm/configs/cpuat91_defconfig
deleted file mode 100644
index 022aeb55b676..000000000000
--- a/arch/arm/configs/cpuat91_defconfig
+++ /dev/null
@@ -1,112 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_CPUAT91=y
-CONFIG_AT91_TIMER_HZ=100
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_PPP=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=32
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_AT91=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig
deleted file mode 100644
index a24c448840c4..000000000000
--- a/arch/arm/configs/csb337_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_CSB337=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_AT91_CF=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_SSC=y
-CONFIG_SCSI=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_KEYSPAN=y
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_MCT_U232=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
-# CONFIG_RTC_INTF_SYSFS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
deleted file mode 100644
index 98552adac5fb..000000000000
--- a/arch/arm/configs/csb637_defconfig
+++ /dev/null
@@ -1,98 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_CSB637=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_AT91_CF=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_KEYSPAN=y
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_MCT_U232=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/ecbat91_defconfig b/arch/arm/configs/ecbat91_defconfig
deleted file mode 100644
index 6bb6abdcea8c..000000000000
--- a/arch/arm/configs/ecbat91_defconfig
+++ /dev/null
@@ -1,99 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_ECBAT91=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_PCCARD=y
-CONFIG_AT91_CF=y
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="rootfstype=reiserfs root=/dev/mmcblk0p1 console=ttyS0,115200n8 rootdelay=1"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_PRINTER=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_AT91=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_REISERFS_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_PCBC=y
-CONFIG_CRYPTO_SHA1=y
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig
deleted file mode 100644
index 896dbe00dc6e..000000000000
--- a/arch/arm/configs/kafa_defconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_KAFA=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20800000,10M root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK_RO=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=32
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_DES=y
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
deleted file mode 100644
index 9f906a85f5c2..000000000000
--- a/arch/arm/configs/kb9202_defconfig
+++ /dev/null
@@ -1,127 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_KB9200=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x10000000
-CONFIG_ZBOOT_ROM_BSS=0x20040000
-CONFIG_CMDLINE="noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
-CONFIG_KEXEC=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_ATMEL_TCLIB=y
-CONFIG_ATMEL_SSC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_AT91RM9200_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_LIBUSUAL=y
-CONFIG_MMC=y
-CONFIG_MMC_AT91=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
deleted file mode 100644
index 1579857aeeaa..000000000000
--- a/arch/arm/configs/onearm_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_ONEARM=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_AT91_CF=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp mem=64M"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IPV6=y
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-# CONFIG_IPV6_SIT is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig
deleted file mode 100644
index 4c9afa478d57..000000000000
--- a/arch/arm/configs/picotux200_defconfig
+++ /dev/null
@@ -1,242 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=m
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EMBEDDED=y
-# CONFIG_KALLSYMS is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_MACH_PICOTUX2XX=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_KEXEC=y
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=m
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_NETDEVICES=y
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_HWMON=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91RM9200_WATCHDOG=m
-CONFIG_HID=m
-CONFIG_USB=m
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_MMC=m
-CONFIG_MMC_AT91=m
-CONFIG_RTC_CLASS=m
-CONFIG_RTC_DRV_AT91RM9200=m
-CONFIG_EXT2_FS=m
-CONFIG_EXT3_FS=m
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=m
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_NLS_DEFAULT="utf-8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_LIBCRC32C=m
diff --git a/arch/arm/configs/yl9200_defconfig b/arch/arm/configs/yl9200_defconfig
deleted file mode 100644
index 30c537f61089..000000000000
--- a/arch/arm/configs/yl9200_defconfig
+++ /dev/null
@@ -1,137 +0,0 @@
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200DK=y
-CONFIG_MACH_YL9200=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=3
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_ATA=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_ARM_AT91_ETHER=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_SPI=y
-CONFIG_SPI_DEBUG=y
-CONFIG_SPI_ATMEL=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_M66592=y
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_AT91=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-CONFIG_REISERFS_FS=y
-CONFIG_INOTIFY=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=1
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SLUB_DEBUG_ON=y
-CONFIG_DEBUG_KOBJECT=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LIST=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index c09e3573c5de..bb96a7d4bbf5 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -911,7 +911,7 @@ __kuser_cmpxchg:				@ 0xffff0fc0
         * A special ghost syscall is used for that (see traps.c).
         */
        stmfd   sp!, {r7, lr}
-        ldr     r7, =1f                 @ it's 20 bits
+        ldr     r7, 1f                  @ it's 20 bits
        swi     __ARM_NR_cmpxchg
        ldmfd   sp!, {r7, pc}
 1:      .word   __ARM_NR_cmpxchg
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index dd6b369ac69c..6bd82d25683c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -85,9 +85,11 @@ ENTRY(stext)
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
        movs    r10, r5                         @ invalid processor (r5=0)?
+ THUMB( it      eq )            @ force fixup-able long branch encoding
        beq     __error_p                       @ yes, error 'p'
        bl      __lookup_machine_type           @ r5=machinfo
        movs    r8, r5                          @ invalid machine (r5=0)?
+ THUMB( it      eq )            @ force fixup-able long branch encoding
        beq     __error_a                       @ yes, error 'a'
        bl      __vet_atags
 #ifdef CONFIG_SMP_ON_UP
@@ -262,6 +264,7 @@ __create_page_tables:
        mov     pc, lr
 ENDPROC(__create_page_tables)
        .ltorg
+        .align
 __enable_mmu_loc:
        .long   .
        .long   __enable_mmu
@@ -282,6 +285,7 @@ ENTRY(secondary_startup)
        bl      __lookup_processor_type
        movs    r10, r5                         @ invalid processor?
        moveq   r0, #'p'                        @ yes, error 'p'
+ THUMB( it      eq )            @ force fixup-able long branch encoding
        beq     __error_p
        /*
@@ -308,6 +312,8 @@ ENTRY(__secondary_switched)
        b       secondary_start_kernel
 ENDPROC(__secondary_switched)
+        .align
        .type   __secondary_data, %object
 __secondary_data:
        .long   .
@@ -413,6 +419,7 @@ __fixup_smp_on_up:
        mov     pc, lr
 ENDPROC(__fixup_smp)
+        .align
 1:      .word   .
        .word   __smpalt_begin
        .word   __smpalt_end
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index fd26f8d65151..9cf4cbf8f95b 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -59,6 +59,8 @@ relocate_new_kernel:
        ldr r2,kexec_boot_atags
        mov pc,lr
+        .align
        .globl kexec_start_address
 kexec_start_address:
        .long   0x0
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 821eb842795f..62d686f0b426 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -24,8 +24,8 @@ obj-$(CONFIG_ARCH_AT91X40)	+= at91x40.o at91x40_time.o
 # AT91RM9200 board-specific support
 obj-$(CONFIG_MACH_ONEARM)       += board-1arm.o
-obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
+obj-$(CONFIG_ARCH_AT91RM9200DK) += board-rm9200dk.o
-obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
+obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
 obj-$(CONFIG_MACH_CSB337)       += board-csb337.o
 obj-$(CONFIG_MACH_CSB637)       += board-csb637.o
 obj-$(CONFIG_MACH_CARMEVA)      += board-carmeva.o
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 9338825cfcd7..7b539228e0ef 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -1106,51 +1106,6 @@ static inline void configure_usart3_pins(unsigned pins)
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91rm9200_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
-                                at91_uarts[i] = &at91rm9200_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(0);
-                                at91_uarts[i] = &at91rm9200_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_usart3_pins(0);
-                                at91_uarts[i] = &at91rm9200_uart3_device;
-                                at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
-                                break;
-                        case 4:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91rm9200_dbgu_device;
-                                at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
        struct platform_device *pdev;
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 46bdc82d3fbf..8a3fc84847c1 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -39,24 +39,24 @@
 #include "generic.h"
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata onearm_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 3,
-        .tty_map        = { 4, 0, 1, -1, -1 },          /* ttyS0, ..., ttyS4 */
-};
 static void __init onearm_map_io(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
-        /* Setup the serial ports and console */
+        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_init_serial(&onearm_uart_config);
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 static void __init onearm_init_irq(void)
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index c0ce79d431a0..d2e1f4ec1fcc 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -39,17 +39,6 @@
 #include "generic.h"
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata kafa_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 0, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
 static void __init kafa_map_io(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
@@ -58,8 +47,14 @@ static void __init kafa_map_io(void)
        /* Set up the LEDs */
        at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
-        /* Setup the serial ports and console */
+        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_init_serial(&kafa_uart_config);
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 static void __init kafa_init_irq(void)
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 9d833bbc592d..55dad3a46547 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -43,24 +43,21 @@
 #include "generic.h"
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata picotux200_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
 static void __init picotux200_map_io(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91rm9200_initialize(18432000, AT91RM9200_BGA);
-        /* Setup the serial ports and console */
+        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_init_serial(&picotux200_uart_config);
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                          | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                          | ATMEL_UART_RI);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 static void __init picotux200_init_irq(void)
@@ -77,11 +74,6 @@ static struct at91_usbh_data __initdata picotux200_usbh_data = {
        .ports          = 1,
 };
-// static struct at91_udc_data __initdata picotux200_udc_data = {
-//      .vbus_pin       = AT91_PIN_PD4,
-//      .pullup_pin     = AT91_PIN_PD5,
-// };
 static struct at91_mmc_data __initdata picotux200_mmc_data = {
        .det_pin        = AT91_PIN_PB27,
        .slot_b         = 0,
@@ -89,21 +81,6 @@ static struct at91_mmc_data __initdata picotux200_mmc_data = {
        .wp_pin         = AT91_PIN_PA17,
 };
-// static struct spi_board_info picotux200_spi_devices[] = {
-//      {       /* DataFlash chip */
-//              .modalias       = "mtd_dataflash",
-//              .chip_select    = 0,
-//              .max_speed_hz   = 15 * 1000 * 1000,
-//      },
-// #ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-//      {       /* DataFlash card */
-//              .modalias       = "mtd_dataflash",
-//              .chip_select    = 3,
-//              .max_speed_hz   = 15 * 1000 * 1000,
-//      },
-// #endif
-// };
 #define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
 #define PICOTUX200_FLASH_SIZE   SZ_4M
@@ -135,21 +112,11 @@ static void __init picotux200_board_init(void)
        at91_add_device_eth(&picotux200_eth_data);
        /* USB Host */
        at91_add_device_usbh(&picotux200_usbh_data);
-        /* USB Device */
-        // at91_add_device_udc(&picotux200_udc_data);
-        // at91_set_multi_drive(picotux200_udc_data.pullup_pin, 1);     /* pullup_pin is connected to reset */
        /* I2C */
        at91_add_device_i2c(NULL, 0);
-        /* SPI */
-        // at91_add_device_spi(picotux200_spi_devices, ARRAY_SIZE(picotux200_spi_devices));
-#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-        /* DataFlash card */
-        at91_set_gpio_output(AT91_PIN_PB22, 0);
-#else
        /* MMC */
        at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
        at91_add_device_mmc(0, &picotux200_mmc_data);
-#endif
        /* NOR Flash */
        platform_device_register(&picotux200_flash);
 }
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index e14f0e165680..4c1047c8200d 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-at91/board-dk.c
+ * linux/arch/arm/mach-at91/board-rm9200dk.c
 *
 *  Copyright (C) 2005 SAN People
 *
@@ -91,10 +91,12 @@ static struct at91_cf_data __initdata dk_cf_data = {
        // .vcc_pin     = ... always powered
 };
+#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
 static struct at91_mmc_data __initdata dk_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
 };
+#endif
 static struct spi_board_info dk_spi_devices[] = {
        {       /* DataFlash chip */
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 56e92c4bbc2a..9df1be8818c0 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-at91/board-ek.c
+ * linux/arch/arm/mach-at91/board-rm9200ek.c
 *
 *  Copyright (C) 2005 SAN People
 *
@@ -84,12 +84,14 @@ static struct at91_udc_data __initdata ek_udc_data = {
        .pullup_pin     = AT91_PIN_PD5,
 };
+#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
 static struct at91_mmc_data __initdata ek_mmc_data = {
        .det_pin        = AT91_PIN_PB27,
        .slot_b         = 0,
        .wire4          = 1,
        .wp_pin         = AT91_PIN_PA17,
 };
+#endif
 static struct spi_board_info ek_spi_devices[] = {
        {       /* DataFlash chip */
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 89df00a9d2f7..e0f0080eb639 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -387,7 +387,7 @@ static struct spi_board_info yl9200_spi_devices[] = {
 * EPSON S1D13806 FB (discontinued chip)
 * EPSON S1D13506 FB
 */
-#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
+#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
 #include <video/s1d13xxxfb.h>
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 58528aa9c8a8..2b499eb343a1 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -137,13 +137,7 @@ extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_de
 extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
 extern void __init at91_set_serial_console(unsigned portnr);
-struct at91_uart_config {
-        unsigned short  console_tty;    /* tty number of serial console */
-        unsigned short  nr_tty;         /* number of serial tty's */
-        short           tty_map[];      /* map UART to tty number */
-};
 extern struct platform_device *atmel_default_console_device;
-extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
 struct atmel_uart_data {
        short                   use_dma_tx;     /* use transmit DMA? */
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 38088c36936c..78defd71a829 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -369,7 +369,7 @@ static int __init cns3xxx_pcie_init(void)
 {
        int i;
-        hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+        hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
                        "imprecise external abort");
        for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
new file mode 100644
index 000000000000..c4ac7b415195
--- /dev/null
+++ b/arch/arm/mach-mxs/Kconfig
@@ -0,0 +1,34 @@
+if ARCH_MXS
+source "arch/arm/mach-mxs/devices/Kconfig"
+config SOC_IMX23
+        bool
+        select CPU_ARM926T
+config SOC_IMX28
+        bool
+        select CPU_ARM926T
+comment "MXS platforms:"
+config MACH_MX23EVK
+        bool "Support MX23EVK Platform"
+        select SOC_IMX23
+        select MXS_HAVE_PLATFORM_DUART
+        default y
+        help
+          Include support for MX23EVK platform. This includes specific
+          configurations for the board and its peripherals.
+config MACH_MX28EVK
+        bool "Support MX28EVK Platform"
+        select SOC_IMX28
+        select MXS_HAVE_PLATFORM_DUART
+        select MXS_HAVE_PLATFORM_FEC
+        default y
+        help
+          Include support for MX28EVK platform. This includes specific
+          configurations for the board and its peripherals.
+endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
new file mode 100644
index 000000000000..39d3f9c2a841
--- /dev/null
+++ b/arch/arm/mach-mxs/Makefile
@@ -0,0 +1,10 @@
+# Common support
+obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
+obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
+obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
+obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
+obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
+obj-y += devices/
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
new file mode 100644
index 000000000000..eb541e0291da
--- /dev/null
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y := 0x40008000
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
new file mode 100644
index 000000000000..8f5a19ab558c
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+#include <mach/mx23.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+#include "regs-clkctrl-mx23.h"
+#define CLKCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
+#define DIGCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
+#define PARENT_RATE_SHIFT       8
+static int _raw_clk_enable(struct clk *clk)
+{
+        u32 reg;
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg &= ~(1 << clk->enable_shift);
+                __raw_writel(reg, clk->enable_reg);
+        }
+        return 0;
+}
+static void _raw_clk_disable(struct clk *clk)
+{
+        u32 reg;
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg |= 1 << clk->enable_shift;
+                __raw_writel(reg, clk->enable_reg);
+        }
+}
+/*
+ * ref_xtal_clk
+ */
+static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
+{
+        return 24000000;
+}
+static struct clk ref_xtal_clk = {
+        .get_rate = ref_xtal_clk_get_rate,
+};
+/*
+ * pll_clk
+ */
+static unsigned long pll_clk_get_rate(struct clk *clk)
+{
+        return 480000000;
+}
+static int pll_clk_enable(struct clk *clk)
+{
+        __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
+                        BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
+        /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
+         * and is incorrect (excessive). Per definition of the PLLCTRL0
+         * POWER field, waiting at least 10us.
+         */
+        udelay(10);
+        return 0;
+}
+static void pll_clk_disable(struct clk *clk)
+{
+        __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
+                        BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
+}
+static struct clk pll_clk = {
+         .get_rate = pll_clk_get_rate,
+         .enable = pll_clk_enable,
+         .disable = pll_clk_disable,
+         .parent = &ref_xtal_clk,
+};
+/*
+ * ref_clk
+ */
+#define _CLK_GET_RATE_REF(name, sr, ss)                                 \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        unsigned long parent_rate;                                      \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
+        div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
+        parent_rate = clk_get_rate(clk->parent);                        \
+                                                                        \
+        return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
+                        div, PARENT_RATE_SHIFT);                        \
+}
+_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
+_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
+_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
+_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
+#define _DEFINE_CLOCK_REF(name, er, es)                                 \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
+                .get_rate       = name##_get_rate,                      \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = &pll_clk,                             \
+        }
+_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
+_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
+_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
+_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
+/*
+ * General clocks
+ *
+ * clk_get_rate
+ */
+static unsigned long rtc_clk_get_rate(struct clk *clk)
+{
+        /* ref_xtal_clk is implemented as the only parent */
+        return clk_get_rate(clk->parent) / 768;
+}
+static unsigned long clk32k_clk_get_rate(struct clk *clk)
+{
+        return clk->parent->get_rate(clk->parent) / 750;
+}
+#define _CLK_GET_RATE(name, rs)                                         \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+                                                                        \
+        if (clk->parent == &ref_xtal_clk)                               \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
+                        BP_CLKCTRL_##rs##_DIV_XTAL;                     \
+        else                                                            \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
+                        BP_CLKCTRL_##rs##_DIV_##rs;                     \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        return clk_get_rate(clk->parent) / div;                         \
+}
+_CLK_GET_RATE(cpu_clk, CPU)
+_CLK_GET_RATE(emi_clk, EMI)
+#define _CLK_GET_RATE1(name, rs)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+        div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        return clk_get_rate(clk->parent) / div;                         \
+}
+_CLK_GET_RATE1(hbus_clk, HBUS)
+_CLK_GET_RATE1(xbus_clk, XBUS)
+_CLK_GET_RATE1(ssp_clk, SSP)
+_CLK_GET_RATE1(gpmi_clk, GPMI)
+_CLK_GET_RATE1(lcdif_clk, PIX)
+#define _CLK_GET_RATE_STUB(name)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        return clk_get_rate(clk->parent);                               \
+}
+_CLK_GET_RATE_STUB(uart_clk)
+_CLK_GET_RATE_STUB(audio_clk)
+_CLK_GET_RATE_STUB(pwm_clk)
+/*
+ * clk_set_rate
+ */
+static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, bm_busy, div_max, d, f, div, frac;
+        unsigned long diff, parent_rate, calc_rate;
+        int i;
+        parent_rate = clk_get_rate(clk->parent);
+        if (clk->parent == &ref_xtal_clk) {
+                div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
+                bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
+                div = DIV_ROUND_UP(parent_rate, rate);
+                if (div == 0 || div > div_max)
+                        return -EINVAL;
+        } else {
+                div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
+                bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
+                rate >>= PARENT_RATE_SHIFT;
+                parent_rate >>= PARENT_RATE_SHIFT;
+                diff = parent_rate;
+                div = frac = 1;
+                for (d = 1; d <= div_max; d++) {
+                        f = parent_rate * 18 / d / rate;
+                        if ((parent_rate * 18 / d) % rate)
+                                f++;
+                        if (f < 18 || f > 35)
+                                continue;
+                        calc_rate = parent_rate * 18 / f / d;
+                        if (calc_rate > rate)
+                                continue;
+                        if (rate - calc_rate < diff) {
+                                frac = f;
+                                div = d;
+                                diff = rate - calc_rate;
+                        }
+                        if (diff == 0)
+                                break;
+                }
+                if (diff == parent_rate)
+                        return -EINVAL;
+                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+                reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
+                reg |= frac;
+                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+        }
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
+        reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
+        reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
+        for (i = 10000; i; i--)
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
+                                        HW_CLKCTRL_CPU) & bm_busy))
+                        break;
+        if (!i) {
+                pr_err("%s: divider writing timeout\n", __func__);
+                return -ETIMEDOUT;
+        }
+        return 0;
+}
+#define _CLK_SET_RATE(name, dr)                                         \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u32 reg, div_max, div;                                          \
+        unsigned long parent_rate;                                      \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
+                                                                        \
+        div = DIV_ROUND_UP(parent_rate, rate);                          \
+        if (div == 0 || div > div_max)                                  \
+                return -EINVAL;                                         \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+        reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
+        reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
+        if (reg | (1 << clk->enable_shift)) {                           \
+                pr_err("%s: clock is gated\n", __func__);               \
+                return -EINVAL;                                         \
+        }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+_CLK_SET_RATE(xbus_clk, XBUS)
+_CLK_SET_RATE(ssp_clk, SSP)
+_CLK_SET_RATE(gpmi_clk, GPMI)
+_CLK_SET_RATE(lcdif_clk, PIX)
+#define _CLK_SET_RATE_STUB(name)                                        \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        return -EINVAL;                                                 \
+}
+_CLK_SET_RATE_STUB(emi_clk)
+_CLK_SET_RATE_STUB(uart_clk)
+_CLK_SET_RATE_STUB(audio_clk)
+_CLK_SET_RATE_STUB(pwm_clk)
+_CLK_SET_RATE_STUB(clk32k_clk)
+/*
+ * clk_set_parent
+ */
+#define _CLK_SET_PARENT(name, bit)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent) {                                    \
+                __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
+                         HW_CLKCTRL_CLKSEQ_TOG);                        \
+                clk->parent = parent;                                   \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+_CLK_SET_PARENT(cpu_clk, CPU)
+_CLK_SET_PARENT(emi_clk, EMI)
+_CLK_SET_PARENT(ssp_clk, SSP)
+_CLK_SET_PARENT(gpmi_clk, GPMI)
+_CLK_SET_PARENT(lcdif_clk, PIX)
+#define _CLK_SET_PARENT_STUB(name)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent)                                      \
+                return -EINVAL;                                         \
+        else                                                            \
+                return 0;                                               \
+}
+_CLK_SET_PARENT_STUB(uart_clk)
+_CLK_SET_PARENT_STUB(audio_clk)
+_CLK_SET_PARENT_STUB(pwm_clk)
+_CLK_SET_PARENT_STUB(clk32k_clk)
+/*
+ * clk definition
+ */
+static struct clk cpu_clk = {
+        .get_rate = cpu_clk_get_rate,
+        .set_rate = cpu_clk_set_rate,
+        .set_parent = cpu_clk_set_parent,
+        .parent = &ref_cpu_clk,
+};
+static struct clk hbus_clk = {
+        .get_rate = hbus_clk_get_rate,
+        .parent = &cpu_clk,
+};
+static struct clk xbus_clk = {
+        .get_rate = xbus_clk_get_rate,
+        .set_rate = xbus_clk_set_rate,
+        .parent = &ref_xtal_clk,
+};
+static struct clk rtc_clk = {
+        .get_rate = rtc_clk_get_rate,
+        .parent = &ref_xtal_clk,
+};
+/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
+static struct clk usb_clk = {
+        .enable_reg = DIGCTRL_BASE_ADDR,
+        .enable_shift = 2,
+        .enable = _raw_clk_enable,
+        .disable = _raw_clk_disable,
+        .parent = &pll_clk,
+};
+#define _DEFINE_CLOCK(name, er, es, p)                                  \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_##es,               \
+                .get_rate       = name##_get_rate,                      \
+                .set_rate       = name##_set_rate,                      \
+                .set_parent     = name##_set_parent,                    \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = p,                                    \
+        }
+_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
+        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
+        _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
+        _REGISTER_CLOCK(NULL, "usb", usb_clk)
+        _REGISTER_CLOCK(NULL, "audio", audio_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+};
+static int clk_misc_init(void)
+{
+        u32 reg;
+        int i;
+        /* Fix up parent per register setting */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
+        cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
+                        &ref_xtal_clk : &ref_cpu_clk;
+        emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
+                        &ref_xtal_clk : &ref_emi_clk;
+        ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
+                        &ref_xtal_clk : &ref_io_clk;
+        gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
+                        &ref_xtal_clk : &ref_io_clk;
+        lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
+                        &ref_xtal_clk : &ref_pix_clk;
+        /* Use int div over frac when both are available */
+        __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+        reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
+        reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+        reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
+        reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
+        /*
+         * Set safe hbus clock divider. A divider of 3 ensure that
+         * the Vddd voltage required for the cpu clock is sufficiently
+         * high for the hbus clock.
+         */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+        reg &= BM_CLKCTRL_HBUS_DIV;
+        reg |= 3 << BP_CLKCTRL_HBUS_DIV;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+        for (i = 10000; i; i--)
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
+                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
+                        break;
+        if (!i) {
+                pr_err("%s: divider writing timeout\n", __func__);
+                return -ETIMEDOUT;
+        }
+        /* Gate off cpu clock in WFI for power saving */
+        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
+        return 0;
+}
+int __init mx23_clocks_init(void)
+{
+        clk_misc_init();
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+        mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
+        return 0;
+}
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
new file mode 100644
index 000000000000..74e2103c6011
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -0,0 +1,734 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+#include <mach/mx28.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+#include "regs-clkctrl-mx28.h"
+#define CLKCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
+#define DIGCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
+#define PARENT_RATE_SHIFT       8
+static struct clk pll2_clk;
+static struct clk cpu_clk;
+static struct clk emi_clk;
+static struct clk saif0_clk;
+static struct clk saif1_clk;
+static struct clk clk32k_clk;
+static int _raw_clk_enable(struct clk *clk)
+{
+        u32 reg;
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg &= ~(1 << clk->enable_shift);
+                __raw_writel(reg, clk->enable_reg);
+        }
+        return 0;
+}
+static void _raw_clk_disable(struct clk *clk)
+{
+        u32 reg;
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg |= 1 << clk->enable_shift;
+                __raw_writel(reg, clk->enable_reg);
+        }
+}
+/*
+ * ref_xtal_clk
+ */
+static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
+{
+        return 24000000;
+}
+static struct clk ref_xtal_clk = {
+        .get_rate = ref_xtal_clk_get_rate,
+};
+/*
+ * pll_clk
+ */
+static unsigned long pll0_clk_get_rate(struct clk *clk)
+{
+        return 480000000;
+}
+static unsigned long pll1_clk_get_rate(struct clk *clk)
+{
+        return 480000000;
+}
+static unsigned long pll2_clk_get_rate(struct clk *clk)
+{
+        return 50000000;
+}
+#define _CLK_ENABLE_PLL(name, r, g)                                     \
+static int name##_enable(struct clk *clk)                               \
+{                                                                       \
+        __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
+                     CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET);    \
+        udelay(10);                                                     \
+                                                                        \
+        if (clk == &pll2_clk)                                           \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
+        else                                                            \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
+                                                                        \
+        return 0;                                                       \
+}
+_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
+_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
+_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
+#define _CLK_DISABLE_PLL(name, r, g)                                    \
+static void name##_disable(struct clk *clk)                             \
+{                                                                       \
+        __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
+                     CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR);    \
+                                                                        \
+        if (clk == &pll2_clk)                                           \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
+        else                                                            \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
+                                                                        \
+}
+_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
+_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
+_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
+#define _DEFINE_CLOCK_PLL(name)                                         \
+        static struct clk name = {                                      \
+                .get_rate       = name##_get_rate,                      \
+                .enable         = name##_enable,                        \
+                .disable        = name##_disable,                       \
+                .parent         = &ref_xtal_clk,                        \
+        }
+_DEFINE_CLOCK_PLL(pll0_clk);
+_DEFINE_CLOCK_PLL(pll1_clk);
+_DEFINE_CLOCK_PLL(pll2_clk);
+/*
+ * ref_clk
+ */
+#define _CLK_GET_RATE_REF(name, sr, ss)                                 \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        unsigned long parent_rate;                                      \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
+        div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
+        parent_rate = clk_get_rate(clk->parent);                        \
+                                                                        \
+        return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
+                        div, PARENT_RATE_SHIFT);                        \
+}
+_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
+_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
+_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
+_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
+_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
+_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
+#define _DEFINE_CLOCK_REF(name, er, es)                                 \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
+                .get_rate       = name##_get_rate,                      \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = &pll0_clk,                            \
+        }
+_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
+_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
+_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
+_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
+_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
+_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
+/*
+ * General clocks
+ *
+ * clk_get_rate
+ */
+static unsigned long lradc_clk_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 16;
+}
+static unsigned long rtc_clk_get_rate(struct clk *clk)
+{
+        /* ref_xtal_clk is implemented as the only parent */
+        return clk_get_rate(clk->parent) / 768;
+}
+static unsigned long clk32k_clk_get_rate(struct clk *clk)
+{
+        return clk->parent->get_rate(clk->parent) / 750;
+}
+static unsigned long spdif_clk_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 4;
+}
+#define _CLK_GET_RATE(name, rs)                                         \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+                                                                        \
+        if (clk->parent == &ref_xtal_clk)                               \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
+                        BP_CLKCTRL_##rs##_DIV_XTAL;                     \
+        else                                                            \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
+                        BP_CLKCTRL_##rs##_DIV_##rs;                     \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        return clk_get_rate(clk->parent) / div;                         \
+}
+_CLK_GET_RATE(cpu_clk, CPU)
+_CLK_GET_RATE(emi_clk, EMI)
+#define _CLK_GET_RATE1(name, rs)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+        div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        if (clk == &saif0_clk || clk == &saif1_clk)                     \
+                return clk_get_rate(clk->parent) >> 16 * div;           \
+        else                                                            \
+                return clk_get_rate(clk->parent) / div;                 \
+}
+_CLK_GET_RATE1(hbus_clk, HBUS)
+_CLK_GET_RATE1(xbus_clk, XBUS)
+_CLK_GET_RATE1(ssp0_clk, SSP0)
+_CLK_GET_RATE1(ssp1_clk, SSP1)
+_CLK_GET_RATE1(ssp2_clk, SSP2)
+_CLK_GET_RATE1(ssp3_clk, SSP3)
+_CLK_GET_RATE1(gpmi_clk, GPMI)
+_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
+_CLK_GET_RATE1(saif0_clk, SAIF0)
+_CLK_GET_RATE1(saif1_clk, SAIF1)
+#define _CLK_GET_RATE_STUB(name)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        return clk_get_rate(clk->parent);                               \
+}
+_CLK_GET_RATE_STUB(uart_clk)
+_CLK_GET_RATE_STUB(pwm_clk)
+_CLK_GET_RATE_STUB(can0_clk)
+_CLK_GET_RATE_STUB(can1_clk)
+_CLK_GET_RATE_STUB(fec_clk)
+/*
+ * clk_set_rate
+ */
+/* fool compiler */
+#define BM_CLKCTRL_CPU_DIV      0
+#define BP_CLKCTRL_CPU_DIV      0
+#define BM_CLKCTRL_CPU_BUSY     0
+#define _CLK_SET_RATE(name, dr, fr, fs)                                 \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u32 reg, bm_busy, div_max, d, f, div, frac;                     \
+        unsigned long diff, parent_rate, calc_rate;                     \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
+        bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
+                                                                        \
+        if (clk->parent == &ref_xtal_clk) {                             \
+                div = DIV_ROUND_UP(parent_rate, rate);                  \
+                if (clk == &cpu_clk) {                                  \
+                        div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
+                                BP_CLKCTRL_CPU_DIV_XTAL;                \
+                        bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;         \
+                }                                                       \
+                if (div == 0 || div > div_max)                          \
+                        return -EINVAL;                                 \
+        } else {                                                        \
+                rate >>= PARENT_RATE_SHIFT;                             \
+                parent_rate >>= PARENT_RATE_SHIFT;                      \
+                diff = parent_rate;                                     \
+                div = frac = 1;                                         \
+                if (clk == &cpu_clk) {                                  \
+                        div_max = BM_CLKCTRL_CPU_DIV_CPU >>             \
+                                BP_CLKCTRL_CPU_DIV_CPU;                 \
+                        bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;          \
+                }                                                       \
+                for (d = 1; d <= div_max; d++) {                        \
+                        f = parent_rate * 18 / d / rate;                \
+                        if ((parent_rate * 18 / d) % rate)              \
+                                f++;                                    \
+                        if (f < 18 || f > 35)                           \
+                                continue;                               \
+                                                                        \
+                        calc_rate = parent_rate * 18 / f / d;           \
+                        if (calc_rate > rate)                           \
+                                continue;                               \
+                                                                        \
+                        if (rate - calc_rate < diff) {                  \
+                                frac = f;                               \
+                                div = d;                                \
+                                diff = rate - calc_rate;                \
+                        }                                               \
+                                                                        \
+                        if (diff == 0)                                  \
+                                break;                                  \
+                }                                                       \
+                                                                        \
+                if (diff == parent_rate)                                \
+                        return -EINVAL;                                 \
+                                                                        \
+                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
+                reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
+                reg |= frac;                                            \
+                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
+        }                                                               \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+        if (clk == &cpu_clk) {                                          \
+                reg &= ~BM_CLKCTRL_CPU_DIV_CPU;                         \
+                reg |= div << BP_CLKCTRL_CPU_DIV_CPU;                   \
+        } else {                                                        \
+                reg &= ~BM_CLKCTRL_##dr##_DIV;                          \
+                reg |= div << BP_CLKCTRL_##dr##_DIV;                    \
+                if (reg | (1 << clk->enable_shift)) {                   \
+                        pr_err("%s: clock is gated\n", __func__);       \
+                        return -EINVAL;                                 \
+                }                                                       \
+        }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);          \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##dr) & bm_busy))                    \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
+_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
+_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
+_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
+_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
+_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
+_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
+#define _CLK_SET_RATE1(name, dr)                                        \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u32 reg, div_max, div;                                          \
+        unsigned long parent_rate;                                      \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
+                                                                        \
+        div = DIV_ROUND_UP(parent_rate, rate);                          \
+        if (div == 0 || div > div_max)                                  \
+                return -EINVAL;                                         \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+        reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
+        reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
+        if (reg | (1 << clk->enable_shift)) {                           \
+                pr_err("%s: clock is gated\n", __func__);               \
+                return -EINVAL;                                         \
+        }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+_CLK_SET_RATE1(xbus_clk, XBUS)
+/* saif clock uses 16 bits frac div */
+#define _CLK_SET_RATE_SAIF(name, rs)                                    \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u16 div;                                                        \
+        u32 reg;                                                        \
+        u64 lrate;                                                      \
+        unsigned long parent_rate;                                      \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        if (rate > parent_rate)                                         \
+                return -EINVAL;                                         \
+                                                                        \
+        lrate = (u64)rate << 16;                                        \
+        do_div(lrate, parent_rate);                                     \
+        div = (u16)lrate;                                               \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+        reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
+        reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY))     \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
+_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
+#define _CLK_SET_RATE_STUB(name)                                        \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        return -EINVAL;                                                 \
+}
+_CLK_SET_RATE_STUB(emi_clk)
+_CLK_SET_RATE_STUB(uart_clk)
+_CLK_SET_RATE_STUB(pwm_clk)
+_CLK_SET_RATE_STUB(spdif_clk)
+_CLK_SET_RATE_STUB(clk32k_clk)
+_CLK_SET_RATE_STUB(can0_clk)
+_CLK_SET_RATE_STUB(can1_clk)
+_CLK_SET_RATE_STUB(fec_clk)
+/*
+ * clk_set_parent
+ */
+#define _CLK_SET_PARENT(name, bit)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent) {                                    \
+                __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
+                         HW_CLKCTRL_CLKSEQ_TOG);                        \
+                clk->parent = parent;                                   \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+_CLK_SET_PARENT(cpu_clk, CPU)
+_CLK_SET_PARENT(emi_clk, EMI)
+_CLK_SET_PARENT(ssp0_clk, SSP0)
+_CLK_SET_PARENT(ssp1_clk, SSP1)
+_CLK_SET_PARENT(ssp2_clk, SSP2)
+_CLK_SET_PARENT(ssp3_clk, SSP3)
+_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
+_CLK_SET_PARENT(gpmi_clk, GPMI)
+_CLK_SET_PARENT(saif0_clk, SAIF0)
+_CLK_SET_PARENT(saif1_clk, SAIF1)
+#define _CLK_SET_PARENT_STUB(name)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent)                                      \
+                return -EINVAL;                                         \
+        else                                                            \
+                return 0;                                               \
+}
+_CLK_SET_PARENT_STUB(pwm_clk)
+_CLK_SET_PARENT_STUB(uart_clk)
+_CLK_SET_PARENT_STUB(clk32k_clk)
+_CLK_SET_PARENT_STUB(spdif_clk)
+_CLK_SET_PARENT_STUB(fec_clk)
+_CLK_SET_PARENT_STUB(can0_clk)
+_CLK_SET_PARENT_STUB(can1_clk)
+/*
+ * clk definition
+ */
+static struct clk cpu_clk = {
+        .get_rate = cpu_clk_get_rate,
+        .set_rate = cpu_clk_set_rate,
+        .set_parent = cpu_clk_set_parent,
+        .parent = &ref_cpu_clk,
+};
+static struct clk hbus_clk = {
+        .get_rate = hbus_clk_get_rate,
+        .parent = &cpu_clk,
+};
+static struct clk xbus_clk = {
+        .get_rate = xbus_clk_get_rate,
+        .set_rate = xbus_clk_set_rate,
+        .parent = &ref_xtal_clk,
+};
+static struct clk lradc_clk = {
+        .get_rate = lradc_clk_get_rate,
+        .parent = &clk32k_clk,
+};
+static struct clk rtc_clk = {
+        .get_rate = rtc_clk_get_rate,
+        .parent = &ref_xtal_clk,
+};
+/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
+static struct clk usb0_clk = {
+        .enable_reg = DIGCTRL_BASE_ADDR,
+        .enable_shift = 2,
+        .enable = _raw_clk_enable,
+        .disable = _raw_clk_disable,
+        .parent = &pll0_clk,
+};
+static struct clk usb1_clk = {
+        .enable_reg = DIGCTRL_BASE_ADDR,
+        .enable_shift = 16,
+        .enable = _raw_clk_enable,
+        .disable = _raw_clk_disable,
+        .parent = &pll1_clk,
+};
+#define _DEFINE_CLOCK(name, er, es, p)                                  \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_##es,               \
+                .get_rate       = name##_get_rate,                      \
+                .set_rate       = name##_set_rate,                      \
+                .set_parent     = name##_set_parent,                    \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = p,                                    \
+        }
+_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
+_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
+_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
+_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
+        _REGISTER_CLOCK("pll2", NULL, pll2_clk)
+        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
+        _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
+        _REGISTER_CLOCK(NULL, "can0", can0_clk)
+        _REGISTER_CLOCK(NULL, "can1", can1_clk)
+        _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
+        _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
+        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
+};
+static int clk_misc_init(void)
+{
+        u32 reg;
+        int i;
+        /* Fix up parent per register setting */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
+        cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
+                        &ref_xtal_clk : &ref_cpu_clk;
+        emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
+                        &ref_xtal_clk : &ref_emi_clk;
+        ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
+                        &ref_xtal_clk : &ref_io0_clk;
+        ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
+                        &ref_xtal_clk : &ref_io0_clk;
+        ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
+                        &ref_xtal_clk : &ref_io1_clk;
+        ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
+                        &ref_xtal_clk : &ref_io1_clk;
+        lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
+                        &ref_xtal_clk : &ref_pix_clk;
+        gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
+                        &ref_xtal_clk : &ref_gpmi_clk;
+        saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
+                        &ref_xtal_clk : &pll0_clk;
+        saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
+                        &ref_xtal_clk : &pll0_clk;
+        /* Use int div over frac when both are available */
+        __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+        reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
+        reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
+        reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
+        reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
+        reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+        reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
+        reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
+        /* SAIF has to use frac div for functional operation */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
+        reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
+        reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
+        /*
+         * Set safe hbus clock divider. A divider of 3 ensure that
+         * the Vddd voltage required for the cpu clock is sufficiently
+         * high for the hbus clock.
+         */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+        reg &= BM_CLKCTRL_HBUS_DIV;
+        reg |= 3 << BP_CLKCTRL_HBUS_DIV;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+        for (i = 10000; i; i--)
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
+                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
+                        break;
+        if (!i) {
+                pr_err("%s: divider writing timeout\n", __func__);
+                return -ETIMEDOUT;
+        }
+        /* Gate off cpu clock in WFI for power saving */
+        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
+        /* Extra fec clock setting */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        reg &= ~BM_CLKCTRL_ENET_SLEEP;
+        reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        return 0;
+}
+int __init mx28_clocks_init(void)
+{
+        clk_misc_init();
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+        mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
+        return 0;
+}
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
new file mode 100644
index 000000000000..e7d2269cf70e
--- /dev/null
+++ b/arch/arm/mach-mxs/clock.c
@@ -0,0 +1,200 @@
+/*
+ * Based on arch/arm/plat-omap/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+/* #define DEBUG */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/proc_fs.h>
+#include <linux/semaphore.h>
+#include <linux/string.h>
+#include <mach/clock.h>
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+static void __clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+        WARN_ON(!clk->usecount);
+        if (!(--clk->usecount)) {
+                if (clk->disable)
+                        clk->disable(clk);
+                __clk_disable(clk->parent);
+                __clk_disable(clk->secondary);
+        }
+}
+static int __clk_enable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+        if (clk->usecount++ == 0) {
+                __clk_enable(clk->parent);
+                __clk_enable(clk->secondary);
+                if (clk->enable)
+                        clk->enable(clk);
+        }
+        return 0;
+}
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+        mutex_lock(&clocks_mutex);
+        ret = __clk_enable(clk);
+        mutex_unlock(&clocks_mutex);
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+        mutex_lock(&clocks_mutex);
+        __clk_disable(clk);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_disable);
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return 0UL;
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL(clk_get_rate);
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
+                return 0;
+        return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL(clk_round_rate);
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+        if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
+                return ret;
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_rate(clk, rate);
+        mutex_unlock(&clocks_mutex);
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = -EINVAL;
+        struct clk *old;
+        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
+            IS_ERR(parent) || clk->set_parent == NULL)
+                return ret;
+        if (clk->usecount)
+                clk_enable(parent);
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_parent(clk, parent);
+        if (ret == 0) {
+                old = clk->parent;
+                clk->parent = parent;
+        } else {
+                old = parent;
+        }
+        mutex_unlock(&clocks_mutex);
+        if (clk->usecount)
+                clk_disable(old);
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        struct clk *ret = NULL;
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
new file mode 100644
index 000000000000..d0f49fc0abb5
--- /dev/null
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx23.h>
+#include <mach/devices-common.h>
+extern const struct mxs_duart_data mx23_duart_data __initconst;
+#define mx23_add_duart() \
+        mxs_add_duart(&mx23_duart_data)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
new file mode 100644
index 000000000000..00b736c434ba
--- /dev/null
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+extern const struct mxs_duart_data mx28_duart_data __initconst;
+#define mx28_add_duart() \
+        mxs_add_duart(&mx28_duart_data)
+extern const struct mxs_fec_data mx28_fec_data[] __initconst;
+#define mx28_add_fec(id, pdata) \
+        mxs_add_fec(&mx28_fec_data[id], pdata)
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
new file mode 100644
index 000000000000..6b60f02ca2e3
--- /dev/null
+++ b/arch/arm/mach-mxs/devices.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <mach/common.h>
+struct platform_device *__init mxs_add_platform_device_dmamask(
+                const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data, u64 dmamask)
+{
+        int ret = -ENOMEM;
+        struct platform_device *pdev;
+        pdev = platform_device_alloc(name, id);
+        if (!pdev)
+                goto err;
+        if (dmamask) {
+                /*
+                 * This memory isn't freed when the device is put,
+                 * I don't have a nice idea for that though.  Conceptually
+                 * dma_mask in struct device should not be a pointer.
+                 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
+                 */
+                pdev->dev.dma_mask =
+                        kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
+                if (!pdev->dev.dma_mask)
+                        /* ret is still -ENOMEM; */
+                        goto err;
+                *pdev->dev.dma_mask = dmamask;
+                pdev->dev.coherent_dma_mask = dmamask;
+        }
+        if (res) {
+                ret = platform_device_add_resources(pdev, res, num_resources);
+                if (ret)
+                        goto err;
+        }
+        if (data) {
+                ret = platform_device_add_data(pdev, data, size_data);
+                if (ret)
+                        goto err;
+        }
+        ret = platform_device_add(pdev);
+        if (ret) {
+err:
+                platform_device_put(pdev);
+                return ERR_PTR(ret);
+        }
+        return pdev;
+}
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
new file mode 100644
index 000000000000..a35a2dc55395
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -0,0 +1,5 @@
+config MXS_HAVE_PLATFORM_DUART
+        bool
+config MXS_HAVE_PLATFORM_FEC
+        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
new file mode 100644
index 000000000000..4b5266a3e6d9
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
diff --git a/arch/arm/mach-mxs/devices/platform-duart.c b/arch/arm/mach-mxs/devices/platform-duart.c
new file mode 100644
index 000000000000..2fe0df5b0aad
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-duart.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#define mxs_duart_data_entry(soc)                                       \
+        {                                                               \
+                .iobase = soc ## _DUART_BASE_ADDR,                      \
+                .irq = soc ## _INT_DUART,                               \
+        }
+#ifdef CONFIG_SOC_IMX23
+const struct mxs_duart_data mx23_duart_data __initconst =
+        mxs_duart_data_entry(MX23);
+#endif
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_duart_data mx28_duart_data __initconst =
+        mxs_duart_data_entry(MX28);
+#endif
+struct platform_device *__init mxs_add_duart(
+                const struct mxs_duart_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res),
+                                        NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
new file mode 100644
index 000000000000..c08168cf3dec
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#define mxs_fec_data_entry_single(soc, _id)                             \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR,        \
+                .irq = soc ## _INT_ENET_MAC ## _id,                     \
+        }
+#define mxs_fec_data_entry(soc, _id)                                    \
+        [_id] = mxs_fec_data_entry_single(soc, _id)
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_fec_data mx28_fec_data[] __initconst = {
+#define mx28_fec_data_entry(_id)                                        \
+        mxs_fec_data_entry(MX28, _id)
+        mx28_fec_data_entry(0),
+        mx28_fec_data_entry(1),
+};
+#endif
+struct platform_device *__init mxs_add_fec(
+                const struct mxs_fec_data *data,
+                const struct fec_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_16K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return mxs_add_platform_device("fec", data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
new file mode 100644
index 000000000000..d7ad7a61366d
--- /dev/null
+++ b/arch/arm/mach-mxs/gpio.c
@@ -0,0 +1,325 @@
+/*
+ * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * Based on code from Freescale,
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <asm-generic/bug.h>
+#include "gpio.h"
+static struct mxs_gpio_port *mxs_gpio_ports;
+static int gpio_table_size;
+#define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
+#define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
+#define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
+#define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
+#define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
+#define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
+#define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
+#define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
+#define GPIO_INT_FALL_EDGE      0x0
+#define GPIO_INT_LOW_LEV        0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_HIGH_LEV       0x3
+#define GPIO_INT_LEV_MASK       (1 << 0)
+#define GPIO_INT_POL_MASK       (1 << 1)
+/* Note: This driver assumes 32 GPIOs are handled in one register */
+static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
+{
+        __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
+}
+static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
+                                int enable)
+{
+        if (enable) {
+                __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
+                __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
+        } else {
+                __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
+        }
+}
+static void mxs_gpio_ack_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
+}
+static void mxs_gpio_mask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
+}
+static void mxs_gpio_unmask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
+}
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
+static int mxs_gpio_set_irq_type(u32 irq, u32 type)
+{
+        u32 gpio = irq_to_gpio(irq);
+        u32 pin_mask = 1 << (gpio & 31);
+        struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+        void __iomem *pin_addr;
+        int edge;
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                edge = GPIO_INT_RISE_EDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                edge = GPIO_INT_FALL_EDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                edge = GPIO_INT_LOW_LEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                edge = GPIO_INT_HIGH_LEV;
+                break;
+        default:
+                return -EINVAL;
+        }
+        /* set level or edge */
+        pin_addr = port->base + PINCTRL_IRQLEV(port->id);
+        if (edge & GPIO_INT_LEV_MASK)
+                __mxs_setl(pin_mask, pin_addr);
+        else
+                __mxs_clrl(pin_mask, pin_addr);
+        /* set polarity */
+        pin_addr = port->base + PINCTRL_IRQPOL(port->id);
+        if (edge & GPIO_INT_POL_MASK)
+                __mxs_setl(pin_mask, pin_addr);
+        else
+                __mxs_clrl(pin_mask, pin_addr);
+        clear_gpio_irqstatus(port, gpio & 0x1f);
+        return 0;
+}
+/* MXS has one interrupt *per* gpio port */
+static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 irq_stat;
+        struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
+        u32 gpio_irq_no_base = port->virtual_irq_start;
+        irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
+                        __raw_readl(port->base + PINCTRL_IRQEN(port->id));
+        while (irq_stat != 0) {
+                int irqoffset = fls(irq_stat) - 1;
+                generic_handle_irq(gpio_irq_no_base + irqoffset);
+                irq_stat &= ~(1 << irqoffset);
+        }
+}
+/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param  irq          interrupt source number
+ * @param  enable       enable as wake-up if equal to non-zero
+ * @return       This function returns 0 on success.
+ */
+static int mxs_gpio_set_wake_irq(u32 irq, u32 enable)
+{
+        u32 gpio = irq_to_gpio(irq);
+        u32 gpio_idx = gpio & 0x1f;
+        struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+        if (enable) {
+                if (port->irq_high && (gpio_idx >= 16))
+                        enable_irq_wake(port->irq_high);
+                else
+                        enable_irq_wake(port->irq);
+        } else {
+                if (port->irq_high && (gpio_idx >= 16))
+                        disable_irq_wake(port->irq_high);
+                else
+                        disable_irq_wake(port->irq);
+        }
+        return 0;
+}
+static struct irq_chip gpio_irq_chip = {
+        .ack = mxs_gpio_ack_irq,
+        .mask = mxs_gpio_mask_irq,
+        .unmask = mxs_gpio_unmask_irq,
+        .set_type = mxs_gpio_set_irq_type,
+        .set_wake = mxs_gpio_set_wake_irq,
+};
+static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
+                                int dir)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
+        if (dir)
+                __mxs_setl(1 << offset, pin_addr);
+        else
+                __mxs_clrl(1 << offset, pin_addr);
+}
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
+}
+static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
+        if (value)
+                __mxs_setl(1 << offset, pin_addr);
+        else
+                __mxs_clrl(1 << offset, pin_addr);
+}
+static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        return port->virtual_irq_start + offset;
+}
+static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        mxs_set_gpio_direction(chip, offset, 0);
+        return 0;
+}
+static int mxs_gpio_direction_output(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        mxs_gpio_set(chip, offset, value);
+        mxs_set_gpio_direction(chip, offset, 1);
+        return 0;
+}
+int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
+{
+        int i, j;
+        /* save for local usage */
+        mxs_gpio_ports = port;
+        gpio_table_size = cnt;
+        pr_info("MXS GPIO hardware\n");
+        for (i = 0; i < cnt; i++) {
+                /* disable the interrupt and clear the status */
+                __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
+                __raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
+                /* clear address has to be used to clear IRQSTAT bits */
+                __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
+                for (j = port[i].virtual_irq_start;
+                        j < port[i].virtual_irq_start + 32; j++) {
+                        set_irq_chip(j, &gpio_irq_chip);
+                        set_irq_handler(j, handle_level_irq);
+                        set_irq_flags(j, IRQF_VALID);
+                }
+                /* setup one handler for each entry */
+                set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler);
+                set_irq_data(port[i].irq, &port[i]);
+                /* register gpio chip */
+                port[i].chip.direction_input = mxs_gpio_direction_input;
+                port[i].chip.direction_output = mxs_gpio_direction_output;
+                port[i].chip.get = mxs_gpio_get;
+                port[i].chip.set = mxs_gpio_set;
+                port[i].chip.to_irq = mxs_gpio_to_irq;
+                port[i].chip.base = i * 32;
+                port[i].chip.ngpio = 32;
+                /* its a serious configuration bug when it fails */
+                BUG_ON(gpiochip_add(&port[i].chip) < 0);
+        }
+        return 0;
+}
+#define DEFINE_MXS_GPIO_PORT(soc, _id)                                  \
+        {                                                               \
+                .chip.label = "gpio-" #_id,                             \
+                .id = _id,                                              \
+                .irq = soc ## _INT_GPIO ## _id,                         \
+                .base = soc ## _IO_ADDRESS(                             \
+                                soc ## _PINCTRL ## _BASE_ADDR),         \
+                .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32,   \
+        }
+#define DEFINE_REGISTER_FUNCTION(prefix)                                \
+int __init prefix ## _register_gpios(void)                              \
+{                                                                       \
+        return mxs_gpio_init(prefix ## _gpio_ports,                     \
+                        ARRAY_SIZE(prefix ## _gpio_ports));             \
+}
+#ifdef CONFIG_SOC_IMX23
+static struct mxs_gpio_port mx23_gpio_ports[] = {
+        DEFINE_MXS_GPIO_PORT(MX23, 0),
+        DEFINE_MXS_GPIO_PORT(MX23, 1),
+        DEFINE_MXS_GPIO_PORT(MX23, 2),
+};
+DEFINE_REGISTER_FUNCTION(mx23)
+#endif
+#ifdef CONFIG_SOC_IMX28
+static struct mxs_gpio_port mx28_gpio_ports[] = {
+        DEFINE_MXS_GPIO_PORT(MX28, 0),
+        DEFINE_MXS_GPIO_PORT(MX28, 1),
+        DEFINE_MXS_GPIO_PORT(MX28, 2),
+        DEFINE_MXS_GPIO_PORT(MX28, 3),
+        DEFINE_MXS_GPIO_PORT(MX28, 4),
+};
+DEFINE_REGISTER_FUNCTION(mx28)
+#endif
diff --git a/arch/arm/mach-mxs/gpio.h b/arch/arm/mach-mxs/gpio.h
new file mode 100644
index 000000000000..005bb06630b1
--- /dev/null
+++ b/arch/arm/mach-mxs/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#ifndef __MXS_GPIO_H__
+#define __MXS_GPIO_H__
+struct mxs_gpio_port {
+        void __iomem *base;
+        int id;
+        int irq;
+        int irq_high;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+int mxs_gpio_init(struct mxs_gpio_port*, int);
+#endif /* __MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
new file mode 100644
index 000000000000..5dd43ba70058
--- /dev/null
+++ b/arch/arm/mach-mxs/icoll.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach/mxs.h>
+#include <mach/common.h>
+#define HW_ICOLL_VECTOR                         0x0000
+#define HW_ICOLL_LEVELACK                       0x0010
+#define HW_ICOLL_CTRL                           0x0020
+#define HW_ICOLL_INTERRUPTn_SET(n)              (0x0124 + (n) * 0x10)
+#define HW_ICOLL_INTERRUPTn_CLR(n)              (0x0128 + (n) * 0x10)
+#define BM_ICOLL_INTERRUPTn_ENABLE              0x00000004
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
+static void icoll_ack_irq(unsigned int irq)
+{
+        /*
+         * The Interrupt Collector is able to prioritize irqs.
+         * Currently only level 0 is used. So acking can use
+         * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
+         */
+        __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
+                        icoll_base + HW_ICOLL_LEVELACK);
+}
+static void icoll_mask_irq(unsigned int irq)
+{
+        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+                        icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq));
+}
+static void icoll_unmask_irq(unsigned int irq)
+{
+        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+                        icoll_base + HW_ICOLL_INTERRUPTn_SET(irq));
+}
+static struct irq_chip mxs_icoll_chip = {
+        .ack = icoll_ack_irq,
+        .mask = icoll_mask_irq,
+        .unmask = icoll_unmask_irq,
+};
+void __init icoll_init_irq(void)
+{
+        int i;
+        /*
+         * Interrupt Collector reset, which initializes the priority
+         * for each irq to level 0.
+         */
+        mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
+        for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
+                set_irq_chip(i, &mxs_icoll_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-mxs/include/mach/clkdev.h b/arch/arm/mach-mxs/include/mach/clkdev.h
new file mode 100644
index 000000000000..3a8f2e3a6309
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_MXS_CLKDEV_H__
+#define __MACH_MXS_CLKDEV_H__
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
new file mode 100644
index 000000000000..041e276d8a32
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#ifndef __MACH_MXS_CLOCK_H__
+#define __MACH_MXS_CLOCK_H__
+#ifndef __ASSEMBLY__
+#include <linux/list.h>
+struct module;
+struct clk {
+        int id;
+        /* Source clock this clk depends on */
+        struct clk *parent;
+        /* Secondary clock to enable/disable with this clock */
+        struct clk *secondary;
+        /* Reference count of clock enable/disable */
+        __s8 usecount;
+        /* Register bit position for clock's enable/disable control. */
+        u8 enable_shift;
+        /* Register address for clock's enable/disable control. */
+        void __iomem *enable_reg;
+        u32 flags;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+#endif /* __ASSEMBLY__ */
+#endif /* __MACH_MXS_CLOCK_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
new file mode 100644
index 000000000000..59133eb3cc96
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_MXS_COMMON_H__
+#define __MACH_MXS_COMMON_H__
+struct clk;
+extern int mxs_reset_block(void __iomem *);
+extern void mxs_timer_init(struct clk *, int);
+extern int mx23_register_gpios(void);
+extern int mx23_clocks_init(void);
+extern void mx23_map_io(void);
+extern void mx23_init_irq(void);
+extern int mx28_register_gpios(void);
+extern int mx28_clocks_init(void);
+extern void mx28_map_io(void);
+extern void mx28_init_irq(void);
+extern void icoll_init_irq(void);
+#endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S
new file mode 100644
index 000000000000..79650a1ad78d
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
+/* arch/arm/mach-mxs/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#ifdef CONFIG_SOC_IMX23
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
+#endif
+#define UART_PADDR      MX23_DUART_BASE_ADDR
+#endif
+#ifdef CONFIG_SOC_IMX28
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
+#endif
+#define UART_PADDR      MX28_DUART_BASE_ADDR
+#endif
+#define UART_VADDR      MXS_IO_ADDRESS(UART_PADDR)
+                .macro  addruart, rp, rv
+                ldr     \rp, =UART_PADDR        @ physical
+                ldr     \rv, =UART_VADDR        @ virtual
+                .endm
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
new file mode 100644
index 000000000000..3da48d4d3273
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+struct platform_device *mxs_add_platform_device_dmamask(
+                const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data, u64 dmamask);
+static inline struct platform_device *mxs_add_platform_device(
+                const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data)
+{
+        return mxs_add_platform_device_dmamask(
+                        name, id, res, num_resources, data, size_data, 0);
+}
+/* duart */
+struct mxs_duart_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_duart(
+                const struct mxs_duart_data *data);
+/* fec */
+#include <linux/fec.h>
+struct mxs_fec_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_fec(
+                const struct mxs_fec_data *data,
+                const struct fec_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S
new file mode 100644
index 000000000000..9f0da12e657a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/entry-macro.S
@@ -0,0 +1,41 @@
+/*
+ * Low-level IRQ helper macros for Freescale MXS-based
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <mach/mxs.h>
+#define MXS_ICOLL_VBASE         MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
+#define HW_ICOLL_STAT_OFFSET    0x70
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
+        cmp     \irqnr, #0x7F
+        strne   \irqnr, [\base]
+        moveqs  \irqnr, #0
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =MXS_ICOLL_VBASE
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
new file mode 100644
index 000000000000..828ccccb6aad
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#ifndef __MACH_MXS_GPIO_H__
+#define __MACH_MXS_GPIO_H__
+#include <asm-generic/gpio.h>
+#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+#define gpio_to_irq             __gpio_to_irq
+#define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
+#endif /* __MACH_MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h
new file mode 100644
index 000000000000..53e89a09bf0d
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/hardware.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#ifndef __MACH_MXS_HARDWARE_H__
+#define __MACH_MXS_HARDWARE_H__
+#ifdef __ASSEMBLER__
+#define IOMEM(addr)     (addr)
+#else
+#define IOMEM(addr)     ((void __force __iomem *)(addr))
+#endif
+#endif /* __MACH_MXS_HARDWARE_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/io.h b/arch/arm/mach-mxs/include/mach/io.h
new file mode 100644
index 000000000000..289b7227e072
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_MXS_IO_H__
+#define __MACH_MXS_IO_H__
+/* Allow IO space to be anywhere in the memory */
+#define IO_SPACE_LIMIT 0xffffffff
+/* io address mapping macro */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+#endif /* __MACH_MXS_IO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
new file mode 100644
index 000000000000..94e5dd83cdb8
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_IOMUX_MX23_H__
+#define __MACH_IOMUX_MX23_H__
+#include <mach/iomux.h>
+/*
+ * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *                                                                      BANK    PIN     MUX
+ */
+/* MUXSEL_0 */
+#define MX23_PAD_GPMI_D00__GPMI_D00             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D01__GPMI_D01             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D02__GPMI_D02             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D03__GPMI_D03             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D04__GPMI_D04             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D05__GPMI_D05             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D06__GPMI_D06             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D07__GPMI_D07             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D08__GPMI_D08             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D09__GPMI_D09             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D10__GPMI_D10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D11__GPMI_D11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D12__GPMI_D12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D13__GPMI_D13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D14__GPMI_D14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D15__GPMI_D15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CLE__GPMI_CLE             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_ALE__GPMI_ALE             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE2N__GPMI_CE2N           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY0__GPMI_RDY0           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY1__GPMI_RDY1           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY2__GPMI_RDY2           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY3__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WPN__GPMI_WPN             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WRN__GPMI_WRN             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDN__GPMI_RDN             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_CTS__AUART1_CTS         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RTS__AUART1_RTS         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RX__AUART1_RX           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_TX__AUART1_TX           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SCL__I2C_SCL               MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SDA__I2C_SDA               MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D00__LCD_D00               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D01__LCD_D01               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D02__LCD_D02               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D03__LCD_D03               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D04__LCD_D04               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D05__LCD_D05               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D06__LCD_D06               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D07__LCD_D07               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D08__LCD_D08               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D09__LCD_D09               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D10__LCD_D10               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D11__LCD_D11               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D12__LCD_D12               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D13__LCD_D13               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D14__LCD_D14               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D15__LCD_D15               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D16__LCD_D16               MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D17__LCD_D17               MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RESET__LCD_RESET           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RS__LCD_RS                 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_WR__LCD_WR                 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_CS__LCD_CS                 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_DOTCK__LCD_DOTCK           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_ENABLE__LCD_ENABLE         MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_HSYNC__LCD_HSYNC           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_VSYNC__LCD_VSYNC           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX23_PAD_PWM0__PWM0                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX23_PAD_PWM1__PWM1                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX23_PAD_PWM2__PWM2                     MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX23_PAD_PWM3__PWM3                     MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX23_PAD_PWM4__PWM4                     MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_CMD__SSP1_CMD             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DETECT__SSP1_DETECT       MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA0__SSP1_DATA0         MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA1__SSP1_DATA1         MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA2__SSP1_DATA2         MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA3__SSP1_DATA3         MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_SCK__SSP1_SCK             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYA__ROTARYA               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYB__ROTARYB               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A00__EMI_A00               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A01__EMI_A01               MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A02__EMI_A02               MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A03__EMI_A03               MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A04__EMI_A04               MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A05__EMI_A05               MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A06__EMI_A06               MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A07__EMI_A07               MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A08__EMI_A08               MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A09__EMI_A09               MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A10__EMI_A10               MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A11__EMI_A11               MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A12__EMI_A12               MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA0__EMI_BA0               MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA1__EMI_BA1               MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CASN__EMI_CASN             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE0N__EMI_CE0N             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE1N__EMI_CE1N             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE1N__GPMI_CE1N           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE0N__GPMI_CE0N           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CKE__EMI_CKE               MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_RASN__EMI_RASN             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_WEN__EMI_WEN               MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D00__EMI_D00               MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D01__EMI_D01               MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D02__EMI_D02               MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D03__EMI_D03               MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D04__EMI_D04               MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D05__EMI_D05               MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D06__EMI_D06               MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D07__EMI_D07               MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D08__EMI_D08               MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D09__EMI_D09               MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D10__EMI_D10               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D11__EMI_D11               MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D12__EMI_D12               MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D13__EMI_D13               MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D14__EMI_D14               MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D15__EMI_D15               MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM0__EMI_DQM0             MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM1__EMI_DQM1             MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS0__EMI_DQS0             MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS1__EMI_DQS1             MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLK__EMI_CLK               MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLKN__EMI_CLKN             MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+/* MUXSEL_1 */
+#define MX23_PAD_GPMI_D00__LCD_D8               MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D01__LCD_D9               MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D02__LCD_D10              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D03__LCD_D11              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D04__LCD_D12              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D05__LCD_D13              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D06__LCD_D14              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D07__LCD_D15              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D08__LCD_D18              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D09__LCD_D19              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D10__LCD_D20              MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D11__LCD_D21              MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D12__LCD_D22              MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D13__LCD_D23              MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D14__AUART2_RX            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D15__AUART2_TX            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CLE__LCD_D16              MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_ALE__LCD_D17              MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CE2N__ATA_A2              MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RTS__IR_CLK             MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RX__IR_RX               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_TX__IR_TX               MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SCL__GPMI_RDY2             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SDA__GPMI_CE2N             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D00__ETM_DA8               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D01__ETM_DA9               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D02__ETM_DA10              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D03__ETM_DA11              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D04__ETM_DA12              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D05__ETM_DA13              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D06__ETM_DA14              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D07__ETM_DA15              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D08__ETM_DA0               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D09__ETM_DA1               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D10__ETM_DA2               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D11__ETM_DA3               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D12__ETM_DA4               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D13__ETM_DA5               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D14__ETM_DA6               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D15__ETM_DA7               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RESET__ETM_TCTL            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RS__ETM_TCLK               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_DOTCK__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_ENABLE__I2C_SCL            MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_HSYNC__I2C_SDA             MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_VSYNC__LCD_BUSY            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX23_PAD_PWM0__ROTARYA                  MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX23_PAD_PWM1__ROTARYB                  MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX23_PAD_PWM2__GPMI_RDY3                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX23_PAD_PWM3__ETM_TCTL                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX23_PAD_PWM4__ETM_TCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DETECT__GPMI_CE3N         MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA1__I2C_SCL            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA2__I2C_SDA            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYA__AUART2_RTS            MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYB__AUART2_CTS            MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
+/* MUXSEL_2 */
+#define MX23_PAD_GPMI_D00__SSP2_DATA0           MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D01__SSP2_DATA1           MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D02__SSP2_DATA2           MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D03__SSP2_DATA3           MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D04__SSP2_DATA4           MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D05__SSP2_DATA5           MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D06__SSP2_DATA6           MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D07__SSP2_DATA7           MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D08__SSP1_DATA4           MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D09__SSP1_DATA5           MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D10__SSP1_DATA6           MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D11__SSP1_DATA7           MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D15__GPMI_CE3N            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY0__SSP2_DETECT         MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY1__SSP2_CMD            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_WRN__SSP2_SCK             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_CTS__SSP1_DATA4         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RTS__SSP1_DATA5         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RX__SSP1_DATA6          MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_TX__SSP1_DATA7          MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SCL__AUART1_TX             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SDA__AUART1_RX             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D08__SAIF2_SDATA0          MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D09__SAIF1_SDATA0          MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D11__SAIF_LRCLK            MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D12__SAIF2_SDATA1          MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D13__SAIF2_SDATA2          MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D14__SAIF1_SDATA2          MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D15__SAIF1_SDATA1          MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_RESET__GPMI_CE3N           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX23_PAD_PWM0__DUART_RX                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
+#define MX23_PAD_PWM1__DUART_TX                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
+#define MX23_PAD_PWM3__AUART1_CTS               MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX23_PAD_PWM4__AUART1_RTS               MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_CMD__JTAG_TDO             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DETECT__USB_OTG_ID        MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA0__JTAG_TDI           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA1__JTAG_TCLK          MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA2__JTAG_RTCK          MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA3__JTAG_TMS           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_SCK__JTAG_TRST            MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYA__SPDIF                 MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYB__GPMI_CE3N             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
+/* MUXSEL_GPIO */
+#define MX23_PAD_GPMI_D00__GPO_0_0              MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D01__GPO_0_1              MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D02__GPO_0_2              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D03__GPO_0_3              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D04__GPO_0_4              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D05__GPO_0_5              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D06__GPO_0_6              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D07__GPO_0_7              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D08__GPO_0_8              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D09__GPO_0_9              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D10__GPO_0_10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D11__GPO_0_11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D12__GPO_0_12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D13__GPO_0_13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D14__GPO_0_14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D15__GPO_0_15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CLE__GPO_0_16             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_ALE__GPO_0_17             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE2N__GPO_0_18            MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY0__GPO_0_19            MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY1__GPO_0_20            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY2__GPO_0_21            MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY3__GPO_0_22            MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WPN__GPO_0_23             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WRN__GPO_0_24             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDN__GPO_0_25             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_CTS__GPO_0_26           MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RTS__GPO_0_27           MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RX__GPO_0_28            MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_TX__GPO_0_29            MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SCL__GPO_0_30              MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SDA__GPO_0_31              MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D00__GPO_1_0               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D01__GPO_1_1               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D02__GPO_1_2               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D03__GPO_1_3               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D04__GPO_1_4               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D05__GPO_1_5               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D06__GPO_1_6               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D07__GPO_1_7               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D08__GPO_1_8               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D09__GPO_1_9               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D10__GPO_1_10              MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D11__GPO_1_11              MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D12__GPO_1_12              MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D13__GPO_1_13              MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D14__GPO_1_14              MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D15__GPO_1_15              MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D16__GPO_1_16              MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D17__GPO_1_17              MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RESET__GPO_1_18            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RS__GPO_1_19               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_WR__GPO_1_20               MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_CS__GPO_1_21               MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_DOTCK__GPO_1_22            MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_ENABLE__GPO_1_23           MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_HSYNC__GPO_1_24            MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_VSYNC__GPO_1_25            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM0__GPO_1_26                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM1__GPO_1_27                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM2__GPO_1_28                 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM3__GPO_1_29                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM4__GPO_1_30                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_CMD__GPO_2_0              MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DETECT__GPO_2_1           MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA0__GPO_2_2            MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA1__GPO_2_3            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA2__GPO_2_4            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA3__GPO_2_5            MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_SCK__GPO_2_6              MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYA__GPO_2_7               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYB__GPO_2_8               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A00__GPO_2_9               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A01__GPO_2_10              MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A02__GPO_2_11              MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A03__GPO_2_12              MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A04__GPO_2_13              MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A05__GPO_2_14              MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A06__GPO_2_15              MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A07__GPO_2_16              MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A08__GPO_2_17              MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A09__GPO_2_18              MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A10__GPO_2_19              MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A11__GPO_2_20              MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A12__GPO_2_21              MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA0__GPO_2_22              MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA1__GPO_2_23              MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CASN__GPO_2_24             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE0N__GPO_2_25             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE1N__GPO_2_26             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE1N__GPO_2_27            MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE0N__GPO_2_28            MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CKE__GPO_2_29              MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_RASN__GPO_2_30             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_WEN__GPO_2_31              MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
+#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
new file mode 100644
index 000000000000..f50fefd10520
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_IOMUX_MX28_H__
+#define __MACH_IOMUX_MX28_H__
+#include <mach/iomux.h>
+/*
+ * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *                                                                      BANK    PIN     MUX
+ */
+/* MUXSEL_0 */
+#define MX28_PAD_GPMI_D00__GPMI_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D01__GPMI_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D02__GPMI_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D03__GPMI_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D04__GPMI_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D05__GPMI_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D06__GPMI_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D07__GPMI_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE0N__GPMI_CE0N                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE1N__GPMI_CE1N                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE2N__GPMI_CE2N                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE3N__GPMI_CE3N                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY0__GPMI_READY0                 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY1__GPMI_READY1                 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY2__GPMI_READY2                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY3__GPMI_READY3                 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDN__GPMI_RDN                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_WRN__GPMI_WRN                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_ALE__GPMI_ALE                     MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CLE__GPMI_CLE                     MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RESETN__GPMI_RESETN               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D00__LCD_D0                        MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D01__LCD_D1                        MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D02__LCD_D2                        MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D03__LCD_D3                        MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D04__LCD_D4                        MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D05__LCD_D5                        MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D06__LCD_D6                        MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D07__LCD_D7                        MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D08__LCD_D8                        MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D09__LCD_D9                        MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D10__LCD_D10                       MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D11__LCD_D11                       MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D12__LCD_D12                       MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D13__LCD_D13                       MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D14__LCD_D14                       MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D15__LCD_D15                       MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D16__LCD_D16                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D17__LCD_D17                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D18__LCD_D18                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D19__LCD_D19                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D20__LCD_D20                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D21__LCD_D21                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D22__LCD_D22                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D23__LCD_D23                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RD_E__LCD_RD_E                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RS__LCD_RS                         MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_CS__LCD_CS                         MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_VSYNC__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_HSYNC__LCD_HSYNC                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_ENABLE__LCD_ENABLE                 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA0__SSP0_D0                    MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA1__SSP0_D1                    MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA2__SSP0_D2                    MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA3__SSP0_D3                    MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA4__SSP0_D4                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA5__SSP0_D5                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA6__SSP0_D6                    MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA7__SSP0_D7                    MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_CMD__SSP0_CMD                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT          MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_SCK__SSP0_SCK                     MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_SCK__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_CMD__SSP1_CMD                     MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA0__SSP1_D0                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA3__SSP1_D3                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SCK__SSP2_SCK                     MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MOSI__SSP2_CMD                    MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MISO__SSP2_D0                     MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS0__SSP2_D3                      MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS1__SSP2_D4                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS2__SSP2_D5                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SCK__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MOSI__SSP3_CMD                    MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MISO__SSP3_D0                     MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SS0__SSP3_D3                      MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_RX__AUART0_RX                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_TX__AUART0_TX                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_CTS__AUART0_CTS                 MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_RTS__AUART0_RTS                 MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RX__AUART1_RX                   MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_TX__AUART1_TX                   MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_CTS__AUART1_CTS                 MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RTS__AUART1_RTS                 MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RX__AUART2_RX                   MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_TX__AUART2_TX                   MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_CTS__AUART2_CTS                 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RTS__AUART2_RTS                 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RX__AUART3_RX                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_TX__AUART3_TX                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_CTS__AUART3_CTS                 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RTS__AUART3_RTS                 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX28_PAD_PWM0__PWM_0                            MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX28_PAD_PWM1__PWM_1                            MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX28_PAD_PWM2__PWM_2                            MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK               MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK             MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0             MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SCL__I2C0_SCL                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SDA__I2C0_SDA                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SPDIF__SPDIF_TX                        MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
+#define MX28_PAD_PWM3__PWM_3                            MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
+#define MX28_PAD_PWM4__PWM_4                            MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RESET__LCD_RESET                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_MDC__ENET0_MDC                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_MDIO__ENET0_MDIO                 MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN               MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD0__ENET0_RXD0                 MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD1__ENET0_RXD1                 MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK             MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD0__ENET0_TXD0                 MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD1__ENET0_TXD1                 MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD2__ENET0_RXD2                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD3__ENET0_RXD3                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD2__ENET0_TXD2                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD3__ENET0_TXD3                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK             MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_COL__ENET0_COL                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_CRS__ENET0_CRS                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
+#define MX28_PAD_ENET_CLK__CLKCTRL_ENET                 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
+#define MX28_PAD_JTAG_RTCK__JTAG_RTCK                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D00__EMI_DATA0                     MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D01__EMI_DATA1                     MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D02__EMI_DATA2                     MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D03__EMI_DATA3                     MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D04__EMI_DATA4                     MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D05__EMI_DATA5                     MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D06__EMI_DATA6                     MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D07__EMI_DATA7                     MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D08__EMI_DATA8                     MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D09__EMI_DATA9                     MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D10__EMI_DATA10                    MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D11__EMI_DATA11                    MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D12__EMI_DATA12                    MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D13__EMI_DATA13                    MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D14__EMI_DATA14                    MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D15__EMI_DATA15                    MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT0__EMI_ODT0                     MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM0__EMI_DQM0                     MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT1__EMI_ODT1                     MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM1__EMI_DQM1                     MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CLK__EMI_CLK                       MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS0__EMI_DQS0                     MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS1__EMI_DQS1                     MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN             MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A00__EMI_ADDR0                     MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A01__EMI_ADDR1                     MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A02__EMI_ADDR2                     MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A03__EMI_ADDR3                     MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A04__EMI_ADDR4                     MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A05__EMI_ADDR5                     MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A06__EMI_ADDR6                     MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A07__EMI_ADDR7                     MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A08__EMI_ADDR8                     MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A09__EMI_ADDR9                     MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A10__EMI_ADDR10                    MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A11__EMI_ADDR11                    MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A12__EMI_ADDR12                    MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A13__EMI_ADDR13                    MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A14__EMI_ADDR14                    MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA0__EMI_BA0                       MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA1__EMI_BA1                       MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA2__EMI_BA2                       MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CASN__EMI_CASN                     MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_RASN__EMI_RASN                     MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_WEN__EMI_WEN                       MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE0N__EMI_CE0N                     MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE1N__EMI_CE1N                     MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CKE__EMI_CKE                       MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
+/* MUXSEL_1 */
+#define MX28_PAD_GPMI_D00__SSP1_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D01__SSP1_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D02__SSP1_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D03__SSP1_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D04__SSP1_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D05__SSP1_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D06__SSP1_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D07__SSP1_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE0N__SSP3_D0                     MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE1N__SSP3_D3                     MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE2N__CAN1_TX                     MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE3N__CAN1_RX                     MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY1__SSP1_CMD                    MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY2__CAN0_TX                     MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY3__CAN0_RX                     MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDN__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_WRN__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_ALE__SSP3_D1                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CLE__SSP3_D2                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RESETN__SSP3_CMD                  MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D03__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D04__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D08__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D09__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT         MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN          MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT         MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RD_E__LCD_VSYNC                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RS__LCD_DOTCLK                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_CS__LCD_ENABLE                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA4__SSP2_D0                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA5__SSP2_D3                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA6__SSP2_CMD                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA7__SSP2_SCK                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_SCK__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_CMD__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA0__SSP2_D6                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA3__SSP2_D7                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SCK__AUART2_RX                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MOSI__AUART2_TX                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MISO__AUART3_RX                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS0__AUART3_TX                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS1__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS2__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SCK__AUART4_TX                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MOSI__AUART4_RX                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MISO__AUART4_RTS                  MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SS0__AUART4_CTS                   MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_RX__I2C0_SCL                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_TX__I2C0_SDA                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_CTS__AUART4_RX                  MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_RTS__AUART4_TX                  MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT           MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RTS__USB0_ID                    MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RX__SSP3_D1                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_TX__SSP3_D2                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_CTS__I2C1_SCL                   MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RTS__I2C1_SDA                   MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RX__CAN0_TX                     MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_TX__CAN0_RX                     MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_CTS__CAN1_TX                    MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RTS__CAN1_RX                    MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
+#define MX28_PAD_PWM0__I2C1_SCL                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
+#define MX28_PAD_PWM1__I2C1_SDA                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
+#define MX28_PAD_PWM2__USB0_ID                          MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_MCLK__PWM_3                      MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_LRCLK__PWM_4                     MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_BITCLK__PWM_5                    MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_SDATA0__PWM_6                    MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA               MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB               MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF1_SDATA0__PWM_7                    MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RESET__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_MDC__GPMI_CE4N                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_MDIO__GPMI_CE5N                  MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N                 MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD0__GPMI_CE7N                  MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD1__GPMI_READY4                MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER            MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_EN__GPMI_READY5               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD0__GPMI_READY6                MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD1__GPMI_READY7                MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD2__ENET1_RXD0                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD3__ENET1_RXD1                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD2__ENET1_TXD0                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD3__ENET1_TXD1                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER              MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_COL__ENET1_TX_EN                 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_CRS__ENET1_RX_EN                 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
+/* MUXSEL_2 */
+#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER                 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK                  MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY0__USB0_ID                     MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER               MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_ALE__SSP3_D4                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CLE__SSP3_D5                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D00__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D01__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D02__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D03__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D04__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D05__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D06__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D07__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D08__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D09__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D10__ETM_DA10                      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D11__ETM_DA11                      MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D12__ETM_DA12                      MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D13__ETM_DA13                      MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D14__ETM_DA14                      MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D15__ETM_DA15                      MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D16__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D17__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D18__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D19__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D20__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D21__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D22__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D23__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_RD_E__ETM_TCTL                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_WR_RWN__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_HSYNC__ETM_TCTL                    MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_DOTCLK__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT        MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN         MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT      MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN       MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1                 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2                MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2                 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT        MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT       MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN         MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_RX__DUART_CTS                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_TX__DUART_RTS                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_CTS__DUART_RX                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_RTS__DUART_TX                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RX__PWM_0                       MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_TX__PWM_1                       MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA             MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB             MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RX__SSP3_D4                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_TX__SSP3_D5                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK                MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT       MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
+#define MX28_PAD_PWM0__DUART_RX                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
+#define MX28_PAD_PWM1__DUART_TX                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
+#define MX28_PAD_PWM2__USB1_OVERCURRENT                 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_MCLK__AUART4_CTS                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS                MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_BITCLK__AUART4_RX                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_SDATA0__AUART4_TX                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SCL__DUART_RX                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SDA__DUART_TX                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SPDIF__ENET1_RX_ER                     MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1                MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2               MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1              MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2               MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT    MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT      MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN       MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN     MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT       MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN        MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
+/* MUXSEL_GPIO */
+#define MX28_PAD_GPMI_D00__GPIO_0_0                     MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D01__GPIO_0_1                     MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D02__GPIO_0_2                     MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D03__GPIO_0_3                     MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D04__GPIO_0_4                     MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D05__GPIO_0_5                     MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D06__GPIO_0_6                     MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D07__GPIO_0_7                     MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE0N__GPIO_0_16                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE1N__GPIO_0_17                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE2N__GPIO_0_18                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE3N__GPIO_0_19                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY0__GPIO_0_20                   MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY1__GPIO_0_21                   MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY2__GPIO_0_22                   MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY3__GPIO_0_23                   MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDN__GPIO_0_24                    MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_WRN__GPIO_0_25                    MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_ALE__GPIO_0_26                    MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CLE__GPIO_0_27                    MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RESETN__GPIO_0_28                 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D00__GPIO_1_0                      MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D01__GPIO_1_1                      MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D02__GPIO_1_2                      MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D03__GPIO_1_3                      MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D04__GPIO_1_4                      MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D05__GPIO_1_5                      MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D06__GPIO_1_6                      MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D07__GPIO_1_7                      MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D08__GPIO_1_8                      MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D09__GPIO_1_9                      MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D10__GPIO_1_10                     MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D11__GPIO_1_11                     MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D12__GPIO_1_12                     MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D13__GPIO_1_13                     MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D14__GPIO_1_14                     MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D15__GPIO_1_15                     MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D16__GPIO_1_16                     MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D17__GPIO_1_17                     MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D18__GPIO_1_18                     MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D19__GPIO_1_19                     MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D20__GPIO_1_20                     MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D21__GPIO_1_21                     MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D22__GPIO_1_22                     MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D23__GPIO_1_23                     MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RD_E__GPIO_1_24                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_WR_RWN__GPIO_1_25                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RS__GPIO_1_26                      MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_CS__GPIO_1_27                      MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_VSYNC__GPIO_1_28                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_HSYNC__GPIO_1_29                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_DOTCLK__GPIO_1_30                  MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_ENABLE__GPIO_1_31                  MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA0__GPIO_2_0                   MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA1__GPIO_2_1                   MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA2__GPIO_2_2                   MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA3__GPIO_2_3                   MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA4__GPIO_2_4                   MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA5__GPIO_2_5                   MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA6__GPIO_2_6                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA7__GPIO_2_7                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_CMD__GPIO_2_8                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DETECT__GPIO_2_9                  MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_SCK__GPIO_2_10                    MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_SCK__GPIO_2_12                    MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_CMD__GPIO_2_13                    MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA0__GPIO_2_14                  MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA3__GPIO_2_15                  MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SCK__GPIO_2_16                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MOSI__GPIO_2_17                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MISO__GPIO_2_18                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS0__GPIO_2_19                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS1__GPIO_2_20                    MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS2__GPIO_2_21                    MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SCK__GPIO_2_24                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MOSI__GPIO_2_25                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MISO__GPIO_2_26                   MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SS0__GPIO_2_27                    MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_RX__GPIO_3_0                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_TX__GPIO_3_1                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_CTS__GPIO_3_2                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_RTS__GPIO_3_3                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RX__GPIO_3_4                    MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_TX__GPIO_3_5                    MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_CTS__GPIO_3_6                   MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RTS__GPIO_3_7                   MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RX__GPIO_3_8                    MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_TX__GPIO_3_9                    MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_CTS__GPIO_3_10                  MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RTS__GPIO_3_11                  MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RX__GPIO_3_12                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_TX__GPIO_3_13                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_CTS__GPIO_3_14                  MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RTS__GPIO_3_15                  MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM0__GPIO_3_16                        MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM1__GPIO_3_17                        MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM2__GPIO_3_18                        MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_MCLK__GPIO_3_20                  MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21                 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SCL__GPIO_3_24                    MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SDA__GPIO_3_25                    MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26                MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SPDIF__GPIO_3_27                       MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM3__GPIO_3_28                        MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM4__GPIO_3_29                        MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RESET__GPIO_3_30                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_MDC__GPIO_4_0                    MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_MDIO__GPIO_4_1                   MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_EN__GPIO_4_2                  MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD0__GPIO_4_3                   MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD1__GPIO_4_4                   MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5                 MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_EN__GPIO_4_6                  MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD0__GPIO_4_7                   MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD1__GPIO_4_8                   MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD2__GPIO_4_9                   MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD3__GPIO_4_10                  MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD2__GPIO_4_11                  MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD3__GPIO_4_12                  MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13                MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_COL__GPIO_4_14                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_CRS__GPIO_4_15                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET_CLK__GPIO_4_16                    MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_JTAG_RTCK__GPIO_4_20                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
+#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
new file mode 100644
index 000000000000..fe558e3c5a9a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                      <armlinux@phytec.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __MACH_MXS_IOMUX_H__
+#define __MACH_MXS_IOMUX_H__
+/*
+ * IOMUX/PAD Bit field definitions
+ *
+ * PAD_BANK:             0..2   (3)
+ * PAD_PIN:              3..7   (5)
+ * PAD_MUXSEL:           8..9   (2)
+ * PAD_MA:              10..11  (2)
+ * PAD_MA_VALID:        12      (1)
+ * PAD_VOL:             13      (1)
+ * PAD_VOL_VALID:       14      (1)
+ * PAD_PULL:            15      (1)
+ * PAD_PULL_VALID:      16      (1)
+ * RESERVED:            17..31  (15)
+ */
+typedef u32 iomux_cfg_t;
+#define MXS_PAD_BANK_SHIFT      0
+#define MXS_PAD_BANK_MASK       ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
+#define MXS_PAD_PIN_SHIFT       3
+#define MXS_PAD_PIN_MASK        ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
+#define MXS_PAD_MUXSEL_SHIFT    8
+#define MXS_PAD_MUXSEL_MASK     ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
+#define MXS_PAD_MA_SHIFT        10
+#define MXS_PAD_MA_MASK         ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
+#define MXS_PAD_MA_VALID_SHIFT  12
+#define MXS_PAD_MA_VALID_MASK   ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
+#define MXS_PAD_VOL_SHIFT       13
+#define MXS_PAD_VOL_MASK        ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
+#define MXS_PAD_VOL_VALID_SHIFT 14
+#define MXS_PAD_VOL_VALID_MASK  ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
+#define MXS_PAD_PULL_SHIFT      15
+#define MXS_PAD_PULL_MASK       ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
+#define MXS_PAD_PULL_VALID_SHIFT 16
+#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
+#define PAD_MUXSEL_0            0
+#define PAD_MUXSEL_1            1
+#define PAD_MUXSEL_2            2
+#define PAD_MUXSEL_GPIO         3
+#define PAD_4MA                 0
+#define PAD_8MA                 1
+#define PAD_12MA                2
+#define PAD_16MA                3
+#define PAD_1V8                 0
+#define PAD_3V3                 1
+#define PAD_NOPULL              0
+#define PAD_PULLUP              1
+#define MXS_PAD_4MA     ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_8MA     ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_12MA    ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_16MA    ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_1V8     ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
+                                        MXS_PAD_VOL_VALID_MASK)
+#define MXS_PAD_3V3     ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
+                                        MXS_PAD_VOL_VALID_MASK)
+#define MXS_PAD_NOPULL  ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
+                                        MXS_PAD_PULL_VALID_MASK)
+#define MXS_PAD_PULLUP  ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
+                                        MXS_PAD_PULL_VALID_MASK)
+#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)           \
+                (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |         \
+                ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |            \
+                ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |      \
+                ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |              \
+                ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |            \
+                ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
+/*
+ * A pad becomes naked, when none of mA, vol or pull
+ * validity bits is set.
+ */
+#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
+                MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
+static inline unsigned int PAD_BANK(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
+}
+static inline unsigned int PAD_PIN(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
+}
+static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
+}
+static inline unsigned int PAD_MA(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
+}
+static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
+}
+static inline unsigned int PAD_VOL(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
+}
+static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
+}
+static inline unsigned int PAD_PULL(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
+}
+static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
+}
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad);
+/*
+ * configures multiple pads
+ * convenient way to call the above function with tables
+ */
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
+#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h
new file mode 100644
index 000000000000..f771039b814a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/irqs.h
@@ -0,0 +1,32 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_MXS_IRQS_H__
+#define __MACH_MXS_IRQS_H__
+#define MXS_INTERNAL_IRQS       128
+#define MXS_GPIO_IRQ_START      MXS_INTERNAL_IRQS
+/* the maximum for MXS-based */
+#define MXS_GPIO_IRQS           (32 * 5)
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase MXS_BOARD_IRQS, but keep it
+ * within sensible limits.
+ */
+#define MXS_BOARD_IRQ_START     (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS)
+#define MXS_BOARD_IRQS          16
+#define NR_IRQS                 (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS)
+#endif /* __MACH_MXS_IRQS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/memory.h b/arch/arm/mach-mxs/include/mach/memory.h
new file mode 100644
index 000000000000..b5420a5c2d4b
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/memory.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __MACH_MXS_MEMORY_H__
+#define __MACH_MXS_MEMORY_H__
+#define PHYS_OFFSET             UL(0x40000000)
+#endif /* __MACH_MXS_MEMORY_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
new file mode 100644
index 000000000000..9edd02ec8e30
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __MACH_MX23_H__
+#define __MACH_MX23_H__
+#include <mach/mxs.h>
+/*
+ * OCRAM
+ */
+#define MX23_OCRAM_BASE_ADDR            0x00000000
+#define MX23_OCRAM_SIZE                 SZ_32K
+/*
+ * IO
+ */
+#define MX23_IO_BASE_ADDR               0x80000000
+#define MX23_IO_SIZE                    SZ_1M
+#define MX23_ICOLL_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x000000)
+#define MX23_APBH_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x004000)
+#define MX23_BCH_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x00a000)
+#define MX23_GPMI_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x00c000)
+#define MX23_SSP1_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x010000)
+#define MX23_PINCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x018000)
+#define MX23_DIGCTL_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x01c000)
+#define MX23_ETM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x020000)
+#define MX23_APBX_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x024000)
+#define MX23_DCP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x028000)
+#define MX23_PXP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x02a000)
+#define MX23_OCOTP_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x02c000)
+#define MX23_AXI_AHB0_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x02e000)
+#define MX23_LCDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x030000)
+#define MX23_SSP2_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x034000)
+#define MX23_TVENC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x038000)
+#define MX23_CLKCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x040000)
+#define MX23_SAIF0_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x042000)
+#define MX23_POWER_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x044000)
+#define MX23_SAIF1_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x046000)
+#define MX23_AUDIOOUT_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x048000)
+#define MX23_AUDIOIN_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x04c000)
+#define MX23_LRADC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x050000)
+#define MX23_SPDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x054000)
+#define MX23_I2C0_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x058000)
+#define MX23_RTC_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x05c000)
+#define MX23_PWM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x064000)
+#define MX23_TIMROT_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x068000)
+#define MX23_AUART1_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06c000)
+#define MX23_AUART2_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06e000)
+#define MX23_DUART_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x070000)
+#define MX23_USBPHY_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x07c000)
+#define MX23_USBCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x080000)
+#define MX23_DRAM_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x0e0000)
+#define MX23_IO_P2V(x)                  MXS_IO_P2V(x)
+#define MX23_IO_ADDRESS(x)              IOMEM(MX23_IO_P2V(x))
+/*
+ * IRQ
+ */
+#define MX23_INT_DUART                  0
+#define MX23_INT_COMMS_RX               1
+#define MX23_INT_COMMS_TX               1
+#define MX23_INT_SSP2_ERROR             2
+#define MX23_INT_VDD5V                  3
+#define MX23_INT_HEADPHONE_SHORT        4
+#define MX23_INT_DAC_DMA                5
+#define MX23_INT_DAC_ERROR              6
+#define MX23_INT_ADC_DMA                7
+#define MX23_INT_ADC_ERROR              8
+#define MX23_INT_SPDIF_DMA              9
+#define MX23_INT_SAIF2_DMA              9
+#define MX23_INT_SPDIF_ERROR            10
+#define MX23_INT_SAIF1_IRQ              10
+#define MX23_INT_SAIF2_IRQ              10
+#define MX23_INT_USB_CTRL               11
+#define MX23_INT_USB_WAKEUP             12
+#define MX23_INT_GPMI_DMA               13
+#define MX23_INT_SSP1_DMA               14
+#define MX23_INT_SSP_ERROR              15
+#define MX23_INT_GPIO0                  16
+#define MX23_INT_GPIO1                  17
+#define MX23_INT_GPIO2                  18
+#define MX23_INT_SAIF1_DMA              19
+#define MX23_INT_SSP2_DMA               20
+#define MX23_INT_ECC8_IRQ               21
+#define MX23_INT_RTC_ALARM              22
+#define MX23_INT_UARTAPP_TX_DMA         23
+#define MX23_INT_UARTAPP_INTERNAL       24
+#define MX23_INT_UARTAPP_RX_DMA         25
+#define MX23_INT_I2C_DMA                26
+#define MX23_INT_I2C_ERROR              27
+#define MX23_INT_TIMER0                 28
+#define MX23_INT_TIMER1                 29
+#define MX23_INT_TIMER2                 30
+#define MX23_INT_TIMER3                 31
+#define MX23_INT_BATT_BRNOUT            32
+#define MX23_INT_VDDD_BRNOUT            33
+#define MX23_INT_VDDIO_BRNOUT           34
+#define MX23_INT_VDD18_BRNOUT           35
+#define MX23_INT_TOUCH_DETECT           36
+#define MX23_INT_LRADC_CH0              37
+#define MX23_INT_LRADC_CH1              38
+#define MX23_INT_LRADC_CH2              39
+#define MX23_INT_LRADC_CH3              40
+#define MX23_INT_LRADC_CH4              41
+#define MX23_INT_LRADC_CH5              42
+#define MX23_INT_LRADC_CH6              43
+#define MX23_INT_LRADC_CH7              44
+#define MX23_INT_LCDIF_DMA              45
+#define MX23_INT_LCDIF_ERROR            46
+#define MX23_INT_DIGCTL_DEBUG_TRAP      47
+#define MX23_INT_RTC_1MSEC              48
+#define MX23_INT_DRI_DMA                49
+#define MX23_INT_DRI_ATTENTION          50
+#define MX23_INT_GPMI_ATTENTION         51
+#define MX23_INT_IR                     52
+#define MX23_INT_DCP_VMI                53
+#define MX23_INT_DCP                    54
+#define MX23_INT_BCH                    56
+#define MX23_INT_PXP                    57
+#define MX23_INT_UARTAPP2_TX_DMA        58
+#define MX23_INT_UARTAPP2_INTERNAL      59
+#define MX23_INT_UARTAPP2_RX_DMA        60
+#define MX23_INT_VDAC_DETECT            61
+#define MX23_INT_VDD5V_DROOP            64
+#define MX23_INT_DCDC4P2_BO             65
+#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
new file mode 100644
index 000000000000..0716745267ad
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __MACH_MX28_H__
+#define __MACH_MX28_H__
+#include <mach/mxs.h>
+/*
+ * OCRAM
+ */
+#define MX28_OCRAM_BASE_ADDR            0x00000000
+#define MX28_OCRAM_SIZE                 SZ_128K
+/*
+ * IO
+ */
+#define MX28_IO_BASE_ADDR               0x80000000
+#define MX28_IO_SIZE                    SZ_1M
+#define MX28_ICOLL_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x000000)
+#define MX28_HSADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x002000)
+#define MX28_APBH_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x004000)
+#define MX28_PERFMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x006000)
+#define MX28_BCH_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x00a000)
+#define MX28_GPMI_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x00c000)
+#define MX28_SSP0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x010000)
+#define MX28_SSP1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x012000)
+#define MX28_SSP2_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x014000)
+#define MX28_SSP3_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x016000)
+#define MX28_PINCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x018000)
+#define MX28_DIGCTL_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x01c000)
+#define MX28_ETM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x022000)
+#define MX28_APBX_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x024000)
+#define MX28_DCP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x028000)
+#define MX28_PXP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x02a000)
+#define MX28_OCOTP_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x02c000)
+#define MX28_AXI_AHB0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x02e000)
+#define MX28_LCDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x030000)
+#define MX28_CAN0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x032000)
+#define MX28_CAN1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x034000)
+#define MX28_SIMDBG_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x03c000)
+#define MX28_SIMGPMISEL_BASE_ADDR       (MX28_IO_BASE_ADDR + 0x03c200)
+#define MX28_SIMSSPSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c300)
+#define MX28_SIMMEMSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c400)
+#define MX28_GPIOMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c500)
+#define MX28_SIMENET_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c700)
+#define MX28_ARMJTAG_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c800)
+#define MX28_CLKCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x040000)
+#define MX28_SAIF0_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x042000)
+#define MX28_POWER_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x044000)
+#define MX28_SAIF1_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x046000)
+#define MX28_LRADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x050000)
+#define MX28_SPDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x054000)
+#define MX28_RTC_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x056000)
+#define MX28_I2C0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x058000)
+#define MX28_I2C1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x05a000)
+#define MX28_PWM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x064000)
+#define MX28_TIMROT_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x068000)
+#define MX28_AUART0_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06a000)
+#define MX28_AUART1_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06c000)
+#define MX28_AUART2_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06e000)
+#define MX28_AUART3_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x070000)
+#define MX28_AUART4_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x072000)
+#define MX28_DUART_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x074000)
+#define MX28_USBPHY0_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07C000)
+#define MX28_USBPHY1_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07e000)
+#define MX28_USBCTRL0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x080000)
+#define MX28_USBCTRL1_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x090000)
+#define MX28_DFLPT_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x0c0000)
+#define MX28_DRAM_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x0e0000)
+#define MX28_ENET_MAC0_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f0000)
+#define MX28_ENET_MAC1_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f4000)
+#define MX28_IO_P2V(x)                  MXS_IO_P2V(x)
+#define MX28_IO_ADDRESS(x)              IOMEM(MX28_IO_P2V(x))
+/*
+ * IRQ
+ */
+#define MX28_INT_BATT_BRNOUT            0
+#define MX28_INT_VDDD_BRNOUT            1
+#define MX28_INT_VDDIO_BRNOUT           2
+#define MX28_INT_VDDA_BRNOUT            3
+#define MX28_INT_VDD5V_DROOP            4
+#define MX28_INT_DCDC4P2_BRNOUT         5
+#define MX28_INT_VDD5V                  6
+#define MX28_INT_CAN0                   8
+#define MX28_INT_CAN1                   9
+#define MX28_INT_LRADC_TOUCH            10
+#define MX28_INT_HSADC                  13
+#define MX28_INT_IRADC_THRESH0          14
+#define MX28_INT_IRADC_THRESH1          15
+#define MX28_INT_LRADC_CH0              16
+#define MX28_INT_LRADC_CH1              17
+#define MX28_INT_LRADC_CH2              18
+#define MX28_INT_LRADC_CH3              19
+#define MX28_INT_LRADC_CH4              20
+#define MX28_INT_LRADC_CH5              21
+#define MX28_INT_LRADC_CH6              22
+#define MX28_INT_LRADC_CH7              23
+#define MX28_INT_LRADC_BUTTON0          24
+#define MX28_INT_LRADC_BUTTON1          25
+#define MX28_INT_PERFMON                27
+#define MX28_INT_RTC_1MSEC              28
+#define MX28_INT_RTC_ALARM              29
+#define MX28_INT_COMMS                  31
+#define MX28_INT_EMI_ERR                32
+#define MX28_INT_LCDIF                  38
+#define MX28_INT_PXP                    39
+#define MX28_INT_BCH                    41
+#define MX28_INT_GPMI                   42
+#define MX28_INT_SPDIF_ERROR            45
+#define MX28_INT_DUART                  47
+#define MX28_INT_TIMER0                 48
+#define MX28_INT_TIMER1                 49
+#define MX28_INT_TIMER2                 50
+#define MX28_INT_TIMER3                 51
+#define MX28_INT_DCP_VMI                52
+#define MX28_INT_DCP                    53
+#define MX28_INT_DCP_SECURE             54
+#define MX28_INT_SAIF1                  58
+#define MX28_INT_SAIF0                  59
+#define MX28_INT_SPDIF_DMA              66
+#define MX28_INT_I2C0_DMA               68
+#define MX28_INT_I2C1_DMA               69
+#define MX28_INT_AUART0_RX_DMA          70
+#define MX28_INT_AUART0_TX_DMA          71
+#define MX28_INT_AUART1_RX_DMA          72
+#define MX28_INT_AUART1_TX_DMA          73
+#define MX28_INT_AUART2_RX_DMA          74
+#define MX28_INT_AUART2_TX_DMA          75
+#define MX28_INT_AUART3_RX_DMA          76
+#define MX28_INT_AUART3_TX_DMA          77
+#define MX28_INT_AUART4_RX_DMA          78
+#define MX28_INT_AUART4_TX_DMA          79
+#define MX28_INT_SAIF0_DMA              80
+#define MX28_INT_SAIF1_DMA              81
+#define MX28_INT_SSP0_DMA               82
+#define MX28_INT_SSP1_DMA               83
+#define MX28_INT_SSP2_DMA               84
+#define MX28_INT_SSP3_DMA               85
+#define MX28_INT_LCDIF_DMA              86
+#define MX28_INT_HSADC_DMA              87
+#define MX28_INT_GPMI_DMA               88
+#define MX28_INT_DIGCTL_DEBUG_TRAP      89
+#define MX28_INT_USB1                   92
+#define MX28_INT_USB0                   93
+#define MX28_INT_USB1_WAKEUP            94
+#define MX28_INT_USB0_WAKEUP            95
+#define MX28_INT_SSP0                   96
+#define MX28_INT_SSP1                   97
+#define MX28_INT_SSP2                   98
+#define MX28_INT_SSP3                   99
+#define MX28_INT_ENET_SWI               100
+#define MX28_INT_ENET_MAC0              101
+#define MX28_INT_ENET_MAC1              102
+#define MX28_INT_ENET_MAC0_1588         103
+#define MX28_INT_ENET_MAC1_1588         104
+#define MX28_INT_I2C1_ERROR             110
+#define MX28_INT_I2C0_ERROR             111
+#define MX28_INT_AUART0                 112
+#define MX28_INT_AUART1                 113
+#define MX28_INT_AUART2                 114
+#define MX28_INT_AUART3                 115
+#define MX28_INT_AUART4                 116
+#define MX28_INT_GPIO4                  123
+#define MX28_INT_GPIO3                  124
+#define MX28_INT_GPIO2                  125
+#define MX28_INT_GPIO1                  126
+#define MX28_INT_GPIO0                  127
+#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
new file mode 100644
index 000000000000..f186c08c2911
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __MACH_MXS_H__
+#define __MACH_MXS_H__
+#ifndef __ASSEMBLER__
+#include <linux/io.h>
+#endif
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+/*
+ * MXS CPU types
+ */
+#define cpu_is_mx23()           (machine_is_mx23evk())
+#define cpu_is_mx28()           (machine_is_mx28evk())
+/*
+ * IO addresses common to MXS-based
+ */
+#define MXS_IO_BASE_ADDR                0x80000000
+#define MXS_IO_SIZE                     SZ_1M
+#define MXS_ICOLL_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x000000)
+#define MXS_APBH_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x004000)
+#define MXS_BCH_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x00a000)
+#define MXS_GPMI_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x00c000)
+#define MXS_PINCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x018000)
+#define MXS_DIGCTL_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x01c000)
+#define MXS_APBX_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x024000)
+#define MXS_DCP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x028000)
+#define MXS_PXP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x02a000)
+#define MXS_OCOTP_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x02c000)
+#define MXS_AXI_AHB0_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x02e000)
+#define MXS_LCDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x030000)
+#define MXS_CLKCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x040000)
+#define MXS_SAIF0_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x042000)
+#define MXS_POWER_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x044000)
+#define MXS_SAIF1_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x046000)
+#define MXS_LRADC_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x050000)
+#define MXS_SPDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x054000)
+#define MXS_I2C0_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x058000)
+#define MXS_PWM_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x064000)
+#define MXS_TIMROT_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x068000)
+#define MXS_AUART1_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06c000)
+#define MXS_AUART2_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06e000)
+#define MXS_DRAM_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x0e0000)
+/*
+ * It maps the whole address space to [0xf4000000, 0xf50fffff].
+ *
+ *      OCRAM   0x00000000+0x020000     ->      0xf4000000+0x020000
+ *      IO      0x80000000+0x100000     ->      0xf5000000+0x100000
+ */
+#define MXS_IO_P2V(x)   (0xf4000000 +                                   \
+                        (((x) & 0x80000000) >> 7) +                     \
+                        (((x) & 0x000fffff)))
+#define MXS_IO_ADDRESS(x)       IOMEM(MXS_IO_P2V(x))
+#define mxs_map_entry(soc, name, _type) {                               \
+        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
+        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
+        .length = soc ## _ ## name ## _SIZE,                            \
+        .type = _type,                                                  \
+}
+#define MXS_SET_ADDR            0x4
+#define MXS_CLR_ADDR            0x8
+#define MXS_TOG_ADDR            0xc
+#ifndef __ASSEMBLER__
+static inline void __mxs_setl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_SET_ADDR);
+}
+static inline void __mxs_clrl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_CLR_ADDR);
+}
+static inline void __mxs_togl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_TOG_ADDR);
+}
+#endif
+#endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h
new file mode 100644
index 000000000000..0e428239b433
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/system.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_MXS_SYSTEM_H__
+#define __MACH_MXS_SYSTEM_H__
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+void arch_reset(char mode, const char *cmd);
+#endif /* __MACH_MXS_SYSTEM_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h
new file mode 100644
index 000000000000..734ce8984a64
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/timex.h
@@ -0,0 +1,21 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_MXS_TIMEX_H__
+#define __MACH_MXS_TIMEX_H__
+#define CLOCK_TICK_RATE         32000   /* 32K */
+#endif /* __MACH_MXS_TIMEX_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
new file mode 100644
index 000000000000..a005e76f34f9
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -0,0 +1,76 @@
+/*
+ *  arch/arm/mach-mxs/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *  Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_MXS_UNCOMPRESS_H__
+#define __MACH_MXS_UNCOMPRESS_H__
+#include <asm/mach-types.h>
+static unsigned long mxs_duart_base;
+#define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
+#define MXS_DUART_DR            0x00
+#define MXS_DUART_FR            0x18
+#define MXS_DUART_FR_TXFE       (1 << 7)
+#define MXS_DUART_CR            0x30
+#define MXS_DUART_CR_UARTEN     (1 << 0)
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader. If it's not, the output is
+ * simply discarded.
+ */
+static void putc(int ch)
+{
+        if (!mxs_duart_base)
+                return;
+        if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN))
+                return;
+        while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE))
+                barrier();
+        MXS_DUART(MXS_DUART_DR) = ch;
+}
+static inline void flush(void)
+{
+}
+#define MX23_DUART_BASE_ADDR    0x80070000
+#define MX28_DUART_BASE_ADDR    0x80074000
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+        switch (arch_id) {
+        case MACH_TYPE_MX23EVK:
+                mxs_duart_base = MX23_DUART_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX28EVK:
+                mxs_duart_base = MX28_DUART_BASE_ADDR;
+                break;
+        default:
+                break;
+        }
+}
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
+#endif /* __MACH_MXS_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h
new file mode 100644
index 000000000000..103b0165ed0b
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2000 Russell King.
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_MXS_VMALLOC_H__
+#define __MACH_MXS_VMALLOC_H__
+/* vmalloc ending address */
+#define VMALLOC_END       0xf4000000UL
+#endif /* __MACH_MXS_VMALLOC_H__ */
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c
new file mode 100644
index 000000000000..0e804e2f11f4
--- /dev/null
+++ b/arch/arm/mach-mxs/iomux.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
+#include <mach/mxs.h>
+#include <mach/iomux.h>
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad)
+{
+        u32 reg, ofs, bp, bm;
+        void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR);
+        /* muxsel */
+        ofs = 0x100;
+        ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
+        bp = PAD_PIN(pad) % 16 * 2;
+        bm = 0x3 << bp;
+        reg = __raw_readl(iomux_base + ofs);
+        reg &= ~bm;
+        reg |= PAD_MUXSEL(pad) << bp;
+        __raw_writel(reg, iomux_base + ofs);
+        /* drive */
+        ofs = cpu_is_mx23() ? 0x200 : 0x300;
+        ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
+        /* mA */
+        if (PAD_MA_VALID(pad)) {
+                bp = PAD_PIN(pad) % 8 * 4;
+                bm = 0x3 << bp;
+                reg = __raw_readl(iomux_base + ofs);
+                reg &= ~bm;
+                reg |= PAD_MA(pad) << bp;
+                __raw_writel(reg, iomux_base + ofs);
+        }
+        /* vol */
+        if (PAD_VOL_VALID(pad)) {
+                bp = PAD_PIN(pad) % 8 * 4 + 2;
+                if (PAD_VOL(pad))
+                        __mxs_setl(1 << bp, iomux_base + ofs);
+                else
+                        __mxs_clrl(1 << bp, iomux_base + ofs);
+        }
+        /* pull */
+        if (PAD_PULL_VALID(pad)) {
+                ofs = cpu_is_mx23() ? 0x400 : 0x600;
+                ofs += PAD_BANK(pad) * 0x10;
+                bp = PAD_PIN(pad);
+                if (PAD_PULL(pad))
+                        __mxs_setl(1 << bp, iomux_base + ofs);
+                else
+                        __mxs_clrl(1 << bp, iomux_base + ofs);
+        }
+        return 0;
+}
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
+{
+        const iomux_cfg_t *p = pad_list;
+        int i;
+        int ret;
+        for (i = 0; i < count; i++) {
+                ret = mxs_iomux_setup_pad(*p);
+                if (ret)
+                        return ret;
+                p++;
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
new file mode 100644
index 000000000000..aa0640052f58
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/iomux-mx23.h>
+#include "devices-mx23.h"
+static const iomux_cfg_t mx23evk_pads[] __initconst = {
+        /* duart */
+        MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA,
+        MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA,
+};
+static void __init mx23evk_init(void)
+{
+        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
+        mx23_add_duart();
+}
+static void __init mx23evk_timer_init(void)
+{
+        mx23_clocks_init();
+}
+static struct sys_timer mx23evk_timer = {
+        .init   = mx23evk_timer_init,
+};
+MACHINE_START(MX23EVK, "Freescale MX23 EVK")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .map_io         = mx23_map_io,
+        .init_irq       = mx23_init_irq,
+        .init_machine   = mx23evk_init,
+        .timer          = &mx23evk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
new file mode 100644
index 000000000000..d162e95910f3
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/iomux-mx28.h>
+#include "devices-mx28.h"
+#include "gpio.h"
+#define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
+#define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
+static const iomux_cfg_t mx28evk_pads[] __initconst = {
+        /* duart */
+        MX28_PAD_PWM0__DUART_RX |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_PWM1__DUART_TX |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* fec0 */
+        MX28_PAD_ENET0_MDC__ENET0_MDC |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        /* phy power line */
+        MX28_PAD_SSP1_DATA3__GPIO_2_15 |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* phy reset line */
+        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+};
+/* fec */
+static void __init mx28evk_fec_reset(void)
+{
+        int ret;
+        struct clk *clk;
+        /* Enable fec phy clock */
+        clk = clk_get_sys("pll2", NULL);
+        if (!IS_ERR(clk))
+                clk_enable(clk);
+        /* Power up fec phy */
+        ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
+        if (ret) {
+                pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret);
+                return;
+        }
+        ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0);
+        if (ret) {
+                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret);
+                return;
+        }
+        /* Reset fec phy */
+        ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset");
+        if (ret) {
+                pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret);
+                return;
+        }
+        gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0);
+        if (ret) {
+                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret);
+                return;
+        }
+        mdelay(1);
+        gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
+}
+static const struct fec_platform_data mx28_fec_pdata __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+static void __init mx28evk_init(void)
+{
+        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
+        mx28_add_duart();
+        mx28evk_fec_reset();
+        mx28_add_fec(0, &mx28_fec_pdata);
+}
+static void __init mx28evk_timer_init(void)
+{
+        mx28_clocks_init();
+}
+static struct sys_timer mx28evk_timer = {
+        .init   = mx28evk_timer_init,
+};
+MACHINE_START(MX28EVK, "Freescale MX28 EVK")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .map_io         = mx28_map_io,
+        .init_irq       = mx28_init_irq,
+        .init_machine   = mx28evk_init,
+        .timer          = &mx28evk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c
new file mode 100644
index 000000000000..5148cd64a6b7
--- /dev/null
+++ b/arch/arm/mach-mxs/mm-mx23.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License.  You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * Create static mapping between physical to virtual memory.
+ */
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/mach/map.h>
+#include <mach/mx23.h>
+#include <mach/common.h>
+#include <mach/iomux.h>
+/*
+ * Define the MX23 memory map.
+ */
+static struct map_desc mx23_io_desc[] __initdata = {
+        mxs_map_entry(MX23, OCRAM, MT_DEVICE),
+        mxs_map_entry(MX23, IO, MT_DEVICE),
+};
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx23_map_io(void)
+{
+        iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
+}
+void __init mx23_init_irq(void)
+{
+        icoll_init_irq();
+        mx23_register_gpios();
+}
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c
new file mode 100644
index 000000000000..7e4cea32ebc6
--- /dev/null
+++ b/arch/arm/mach-mxs/mm-mx28.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License.  You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * Create static mapping between physical to virtual memory.
+ */
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/mach/map.h>
+#include <mach/mx28.h>
+#include <mach/common.h>
+#include <mach/iomux.h>
+/*
+ * Define the MX28 memory map.
+ */
+static struct map_desc mx28_io_desc[] __initdata = {
+        mxs_map_entry(MX28, OCRAM, MT_DEVICE),
+        mxs_map_entry(MX28, IO, MT_DEVICE),
+};
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx28_map_io(void)
+{
+        iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
+}
+void __init mx28_init_irq(void)
+{
+        icoll_init_irq();
+        mx28_register_gpios();
+}
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 000000000000..dbc04747b691
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,455 @@
+/*
+ * Freescale CLKCTRL Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.48
+ * Template revision: 26195
+ */
+#ifndef __REGS_CLKCTRL_MX23_H__
+#define __REGS_CLKCTRL_MX23_H__
+#define HW_CLKCTRL_PLLCTRL0     (0x00000000)
+#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
+#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
+#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
+#define BP_CLKCTRL_PLLCTRL0_RSRVD6      30
+#define BM_CLKCTRL_PLLCTRL0_RSRVD6      0xC0000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
+                (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL     28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL     0x30000000
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD5      26
+#define BM_CLKCTRL_PLLCTRL0_RSRVD5      0x0C000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)  \
+                (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL      24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL      0x03000000
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD4      22
+#define BM_CLKCTRL_PLLCTRL0_RSRVD4      0x00C00000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)  \
+                (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL     20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL     0x00300000
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
+                (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLLCTRL0_RSRVD3      0x00080000
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
+#define BM_CLKCTRL_PLLCTRL0_RSRVD2      0x00020000
+#define BM_CLKCTRL_PLLCTRL0_POWER       0x00010000
+#define BP_CLKCTRL_PLLCTRL0_RSRVD1      0
+#define BM_CLKCTRL_PLLCTRL0_RSRVD1      0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
+#define HW_CLKCTRL_PLLCTRL1     (0x00000010)
+#define BM_CLKCTRL_PLLCTRL1_LOCK        0x80000000
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK  0x40000000
+#define BP_CLKCTRL_PLLCTRL1_RSRVD1      16
+#define BM_CLKCTRL_PLLCTRL1_RSRVD1      0x3FFF0000
+#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)  \
+                (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT  0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT  0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
+#define HW_CLKCTRL_CPU  (0x00000020)
+#define HW_CLKCTRL_CPU_SET      (0x00000024)
+#define HW_CLKCTRL_CPU_CLR      (0x00000028)
+#define HW_CLKCTRL_CPU_TOG      (0x0000002c)
+#define BP_CLKCTRL_CPU_RSRVD5   30
+#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v) \
+                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
+#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
+#define BP_CLKCTRL_CPU_DIV_XTAL 16
+#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
+                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
+#define BP_CLKCTRL_CPU_RSRVD3   13
+#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
+#define BF_CLKCTRL_CPU_RSRVD3(v)  \
+                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
+#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
+#define BP_CLKCTRL_CPU_RSRVD1   6
+#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
+#define BF_CLKCTRL_CPU_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
+#define BP_CLKCTRL_CPU_DIV_CPU  0
+#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
+#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
+                (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
+#define HW_CLKCTRL_HBUS (0x00000030)
+#define HW_CLKCTRL_HBUS_SET     (0x00000034)
+#define HW_CLKCTRL_HBUS_CLR     (0x00000038)
+#define HW_CLKCTRL_HBUS_TOG     (0x0000003c)
+#define BP_CLKCTRL_HBUS_RSRVD4  30
+#define BM_CLKCTRL_HBUS_RSRVD4  0xC0000000
+#define BF_CLKCTRL_HBUS_RSRVD4(v) \
+                (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
+#define BM_CLKCTRL_HBUS_BUSY    0x20000000
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x10000000
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x08000000
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE   0x01000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE       0x00800000
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE  0x00100000
+#define BM_CLKCTRL_HBUS_RSRVD2  0x00080000
+#define BP_CLKCTRL_HBUS_SLOW_DIV        16
+#define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
+                (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
+#define BP_CLKCTRL_HBUS_RSRVD1  6
+#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
+#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
+#define BP_CLKCTRL_HBUS_DIV     0
+#define BM_CLKCTRL_HBUS_DIV     0x0000001F
+#define BF_CLKCTRL_HBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
+#define HW_CLKCTRL_XBUS (0x00000040)
+#define BM_CLKCTRL_XBUS_BUSY    0x80000000
+#define BP_CLKCTRL_XBUS_RSRVD1  11
+#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF800
+#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
+                (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_XBUS_DIV     0
+#define BM_CLKCTRL_XBUS_DIV     0x000003FF
+#define BF_CLKCTRL_XBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
+#define HW_CLKCTRL_XTAL (0x00000050)
+#define HW_CLKCTRL_XTAL_SET     (0x00000054)
+#define HW_CLKCTRL_XTAL_CLR     (0x00000058)
+#define HW_CLKCTRL_XTAL_TOG     (0x0000005c)
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x08000000
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
+#define BP_CLKCTRL_XTAL_RSRVD1  2
+#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
+#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
+                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
+#define BP_CLKCTRL_XTAL_DIV_UART        0
+#define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
+#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
+                (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
+#define HW_CLKCTRL_PIX  (0x00000060)
+#define BP_CLKCTRL_PIX_CLKGATE  31
+#define BM_CLKCTRL_PIX_CLKGATE  0x80000000
+#define BM_CLKCTRL_PIX_RSRVD2   0x40000000
+#define BM_CLKCTRL_PIX_BUSY     0x20000000
+#define BP_CLKCTRL_PIX_RSRVD1   13
+#define BM_CLKCTRL_PIX_RSRVD1   0x1FFFE000
+#define BF_CLKCTRL_PIX_RSRVD1(v)  \
+                (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x00001000
+#define BP_CLKCTRL_PIX_DIV      0
+#define BM_CLKCTRL_PIX_DIV      0x00000FFF
+#define BF_CLKCTRL_PIX_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_PIX_DIV)
+#define HW_CLKCTRL_SSP  (0x00000070)
+#define BP_CLKCTRL_SSP_CLKGATE  31
+#define BM_CLKCTRL_SSP_CLKGATE  0x80000000
+#define BM_CLKCTRL_SSP_RSRVD2   0x40000000
+#define BM_CLKCTRL_SSP_BUSY     0x20000000
+#define BP_CLKCTRL_SSP_RSRVD1   10
+#define BM_CLKCTRL_SSP_RSRVD1   0x1FFFFC00
+#define BF_CLKCTRL_SSP_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x00000200
+#define BP_CLKCTRL_SSP_DIV      0
+#define BM_CLKCTRL_SSP_DIV      0x000001FF
+#define BF_CLKCTRL_SSP_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP_DIV)
+#define HW_CLKCTRL_GPMI (0x00000080)
+#define BP_CLKCTRL_GPMI_CLKGATE 31
+#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
+#define BM_CLKCTRL_GPMI_BUSY    0x20000000
+#define BP_CLKCTRL_GPMI_RSRVD1  11
+#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
+#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
+                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_GPMI_DIV     0
+#define BM_CLKCTRL_GPMI_DIV     0x000003FF
+#define BF_CLKCTRL_GPMI_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
+#define HW_CLKCTRL_SPDIF        (0x00000090)
+#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
+#define BP_CLKCTRL_SPDIF_RSRVD  0
+#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
+#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
+#define HW_CLKCTRL_EMI  (0x000000a0)
+#define BP_CLKCTRL_EMI_CLKGATE  31
+#define BM_CLKCTRL_EMI_CLKGATE  0x80000000
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN     0x40000000
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
+#define BP_CLKCTRL_EMI_RSRVD3   18
+#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
+#define BF_CLKCTRL_EMI_RSRVD3(v)  \
+                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
+#define BP_CLKCTRL_EMI_RSRVD2   12
+#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
+#define BF_CLKCTRL_EMI_RSRVD2(v)  \
+                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
+#define BP_CLKCTRL_EMI_DIV_XTAL 8
+#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
+                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
+#define BP_CLKCTRL_EMI_RSRVD1   6
+#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
+#define BF_CLKCTRL_EMI_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
+#define BP_CLKCTRL_EMI_DIV_EMI  0
+#define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
+#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
+                (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
+#define HW_CLKCTRL_IR   (0x000000b0)
+#define BM_CLKCTRL_IR_CLKGATE   0x80000000
+#define BM_CLKCTRL_IR_RSRVD3    0x40000000
+#define BM_CLKCTRL_IR_AUTO_DIV  0x20000000
+#define BM_CLKCTRL_IR_IR_BUSY   0x10000000
+#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
+#define BP_CLKCTRL_IR_RSRVD2    25
+#define BM_CLKCTRL_IR_RSRVD2    0x06000000
+#define BF_CLKCTRL_IR_RSRVD2(v)  \
+                (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
+#define BP_CLKCTRL_IR_IROV_DIV  16
+#define BM_CLKCTRL_IR_IROV_DIV  0x01FF0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)  \
+                (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
+#define BP_CLKCTRL_IR_RSRVD1    10
+#define BM_CLKCTRL_IR_RSRVD1    0x0000FC00
+#define BF_CLKCTRL_IR_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
+#define BP_CLKCTRL_IR_IR_DIV    0
+#define BM_CLKCTRL_IR_IR_DIV    0x000003FF
+#define BF_CLKCTRL_IR_IR_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
+#define HW_CLKCTRL_SAIF (0x000000c0)
+#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
+#define BM_CLKCTRL_SAIF_RSRVD2  0x40000000
+#define BM_CLKCTRL_SAIF_BUSY    0x20000000
+#define BP_CLKCTRL_SAIF_RSRVD1  17
+#define BM_CLKCTRL_SAIF_RSRVD1  0x1FFE0000
+#define BF_CLKCTRL_SAIF_RSRVD1(v)  \
+                (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x00010000
+#define BP_CLKCTRL_SAIF_DIV     0
+#define BM_CLKCTRL_SAIF_DIV     0x0000FFFF
+#define BF_CLKCTRL_SAIF_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
+#define HW_CLKCTRL_TV   (0x000000d0)
+#define BM_CLKCTRL_TV_CLK_TV108M_GATE   0x80000000
+#define BM_CLKCTRL_TV_CLK_TV_GATE       0x40000000
+#define BP_CLKCTRL_TV_RSRVD     0
+#define BM_CLKCTRL_TV_RSRVD     0x3FFFFFFF
+#define BF_CLKCTRL_TV_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
+#define HW_CLKCTRL_ETM  (0x000000e0)
+#define BM_CLKCTRL_ETM_CLKGATE  0x80000000
+#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
+#define BM_CLKCTRL_ETM_BUSY     0x20000000
+#define BP_CLKCTRL_ETM_RSRVD1   7
+#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF80
+#define BF_CLKCTRL_ETM_RSRVD1(v)  \
+                (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000040
+#define BP_CLKCTRL_ETM_DIV      0
+#define BM_CLKCTRL_ETM_DIV      0x0000003F
+#define BF_CLKCTRL_ETM_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_ETM_DIV)
+#define HW_CLKCTRL_FRAC (0x000000f0)
+#define HW_CLKCTRL_FRAC_SET     (0x000000f4)
+#define HW_CLKCTRL_FRAC_CLR     (0x000000f8)
+#define HW_CLKCTRL_FRAC_TOG     (0x000000fc)
+#define BP_CLKCTRL_FRAC_CLKGATEIO       31
+#define BM_CLKCTRL_FRAC_CLKGATEIO       0x80000000
+#define BM_CLKCTRL_FRAC_IO_STABLE       0x40000000
+#define BP_CLKCTRL_FRAC_IOFRAC  24
+#define BM_CLKCTRL_FRAC_IOFRAC  0x3F000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v)  \
+                (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
+#define BP_CLKCTRL_FRAC_CLKGATEPIX      23
+#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x00800000
+#define BM_CLKCTRL_FRAC_PIX_STABLE      0x00400000
+#define BP_CLKCTRL_FRAC_PIXFRAC 16
+#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v)  \
+                (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
+#define BP_CLKCTRL_FRAC_CLKGATEEMI      15
+#define BM_CLKCTRL_FRAC_CLKGATEEMI      0x00008000
+#define BM_CLKCTRL_FRAC_EMI_STABLE      0x00004000
+#define BP_CLKCTRL_FRAC_EMIFRAC 8
+#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v)  \
+                (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
+#define BP_CLKCTRL_FRAC_CLKGATECPU      7
+#define BM_CLKCTRL_FRAC_CLKGATECPU      0x00000080
+#define BM_CLKCTRL_FRAC_CPU_STABLE      0x00000040
+#define BP_CLKCTRL_FRAC_CPUFRAC 0
+#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
+#define BF_CLKCTRL_FRAC_CPUFRAC(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
+#define HW_CLKCTRL_FRAC1        (0x00000100)
+#define HW_CLKCTRL_FRAC1_SET    (0x00000104)
+#define HW_CLKCTRL_FRAC1_CLR    (0x00000108)
+#define HW_CLKCTRL_FRAC1_TOG    (0x0000010c)
+#define BM_CLKCTRL_FRAC1_CLKGATEVID     0x80000000
+#define BM_CLKCTRL_FRAC1_VID_STABLE     0x40000000
+#define BP_CLKCTRL_FRAC1_RSRVD1 0
+#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
+#define BF_CLKCTRL_FRAC1_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
+#define HW_CLKCTRL_CLKSEQ       (0x00000110)
+#define HW_CLKCTRL_CLKSEQ_SET   (0x00000114)
+#define HW_CLKCTRL_CLKSEQ_CLR   (0x00000118)
+#define HW_CLKCTRL_CLKSEQ_TOG   (0x0000011c)
+#define BP_CLKCTRL_CLKSEQ_RSRVD1        9
+#define BM_CLKCTRL_CLKSEQ_RSRVD1        0xFFFFFE00
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
+                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00000080
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000040
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP    0x00000020
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000010
+#define BM_CLKCTRL_CLKSEQ_BYPASS_IR     0x00000008
+#define BM_CLKCTRL_CLKSEQ_RSRVD0        0x00000004
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX    0x00000002
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF   0x00000001
+#define HW_CLKCTRL_RESET        (0x00000120)
+#define BP_CLKCTRL_RESET_RSRVD  2
+#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFFC
+#define BF_CLKCTRL_RESET_RSRVD(v) \
+                (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
+#define BM_CLKCTRL_RESET_CHIP   0x00000002
+#define BM_CLKCTRL_RESET_DIG    0x00000001
+#define HW_CLKCTRL_STATUS       (0x00000130)
+#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
+                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
+#define BP_CLKCTRL_STATUS_RSRVD 0
+#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
+#define BF_CLKCTRL_STATUS_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
+#define HW_CLKCTRL_VERSION      (0x00000140)
+#define BP_CLKCTRL_VERSION_MAJOR        24
+#define BM_CLKCTRL_VERSION_MAJOR        0xFF000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) \
+                (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
+#define BP_CLKCTRL_VERSION_MINOR        16
+#define BM_CLKCTRL_VERSION_MINOR        0x00FF0000
+#define BF_CLKCTRL_VERSION_MINOR(v)  \
+                (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
+#define BP_CLKCTRL_VERSION_STEP 0
+#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
+#define BF_CLKCTRL_VERSION_STEP(v)  \
+                (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
+#endif /* __REGS_CLKCTRL_MX23_H__ */
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
new file mode 100644
index 000000000000..661df18755f7
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -0,0 +1,663 @@
+/*
+ * Freescale CLKCTRL Register Definitions
+ *
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.48
+ * Template revision: 26195
+ */
+#ifndef __REGS_CLKCTRL_MX28_H__
+#define __REGS_CLKCTRL_MX28_H__
+#define HW_CLKCTRL_PLL0CTRL0    (0x00000000)
+#define HW_CLKCTRL_PLL0CTRL0_SET        (0x00000004)
+#define HW_CLKCTRL_PLL0CTRL0_CLR        (0x00000008)
+#define HW_CLKCTRL_PLL0CTRL0_TOG        (0x0000000c)
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD6     30
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD6     0xC0000000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
+                (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
+#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL    28
+#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL    0x30000000
+#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD5     26
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD5     0x0C000000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v)  \
+                (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
+#define BP_CLKCTRL_PLL0CTRL0_CP_SEL     24
+#define BM_CLKCTRL_PLL0CTRL0_CP_SEL     0x03000000
+#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD4     22
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD4     0x00C00000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v)  \
+                (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
+#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL    20
+#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL    0x00300000
+#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v)  \
+                (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER     0x1
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST    0x2
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD3     0x00080000
+#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS        0x00040000
+#define BM_CLKCTRL_PLL0CTRL0_POWER      0x00020000
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD1     0
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD1     0x0001FFFF
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
+#define HW_CLKCTRL_PLL0CTRL1    (0x00000010)
+#define BM_CLKCTRL_PLL0CTRL1_LOCK       0x80000000
+#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
+#define BP_CLKCTRL_PLL0CTRL1_RSRVD1     16
+#define BM_CLKCTRL_PLL0CTRL1_RSRVD1     0x3FFF0000
+#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v)  \
+                (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
+#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
+#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
+#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
+#define HW_CLKCTRL_PLL1CTRL0    (0x00000020)
+#define HW_CLKCTRL_PLL1CTRL0_SET        (0x00000024)
+#define HW_CLKCTRL_PLL1CTRL0_CLR        (0x00000028)
+#define HW_CLKCTRL_PLL1CTRL0_TOG        (0x0000002c)
+#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD6     0x40000000
+#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL    28
+#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL    0x30000000
+#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD5     26
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD5     0x0C000000
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v)  \
+                (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
+#define BP_CLKCTRL_PLL1CTRL0_CP_SEL     24
+#define BM_CLKCTRL_PLL1CTRL0_CP_SEL     0x03000000
+#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD4     22
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD4     0x00C00000
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v)  \
+                (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
+#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL    20
+#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL    0x00300000
+#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v)  \
+                (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER     0x1
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST    0x2
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD3     0x00080000
+#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS        0x00040000
+#define BM_CLKCTRL_PLL1CTRL0_POWER      0x00020000
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD1     0
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD1     0x0001FFFF
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
+#define HW_CLKCTRL_PLL1CTRL1    (0x00000030)
+#define BM_CLKCTRL_PLL1CTRL1_LOCK       0x80000000
+#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
+#define BP_CLKCTRL_PLL1CTRL1_RSRVD1     16
+#define BM_CLKCTRL_PLL1CTRL1_RSRVD1     0x3FFF0000
+#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v)  \
+                (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
+#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
+#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
+#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
+#define HW_CLKCTRL_PLL2CTRL0    (0x00000040)
+#define HW_CLKCTRL_PLL2CTRL0_SET        (0x00000044)
+#define HW_CLKCTRL_PLL2CTRL0_CLR        (0x00000048)
+#define HW_CLKCTRL_PLL2CTRL0_TOG        (0x0000004c)
+#define BM_CLKCTRL_PLL2CTRL0_CLKGATE    0x80000000
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD3     0x40000000
+#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL    28
+#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL    0x30000000
+#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD2     0x08000000
+#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B    0x04000000
+#define BP_CLKCTRL_PLL2CTRL0_CP_SEL     24
+#define BM_CLKCTRL_PLL2CTRL0_CP_SEL     0x03000000
+#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
+#define BM_CLKCTRL_PLL2CTRL0_POWER      0x00800000
+#define BP_CLKCTRL_PLL2CTRL0_RSRVD1     0
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD1     0x007FFFFF
+#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
+#define HW_CLKCTRL_CPU  (0x00000050)
+#define HW_CLKCTRL_CPU_SET      (0x00000054)
+#define HW_CLKCTRL_CPU_CLR      (0x00000058)
+#define HW_CLKCTRL_CPU_TOG      (0x0000005c)
+#define BP_CLKCTRL_CPU_RSRVD5   30
+#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v) \
+                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
+#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
+#define BP_CLKCTRL_CPU_DIV_XTAL 16
+#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
+                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
+#define BP_CLKCTRL_CPU_RSRVD3   13
+#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
+#define BF_CLKCTRL_CPU_RSRVD3(v)  \
+                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
+#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
+#define BP_CLKCTRL_CPU_RSRVD1   6
+#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
+#define BF_CLKCTRL_CPU_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
+#define BP_CLKCTRL_CPU_DIV_CPU  0
+#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
+#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
+                (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
+#define HW_CLKCTRL_HBUS (0x00000060)
+#define HW_CLKCTRL_HBUS_SET     (0x00000064)
+#define HW_CLKCTRL_HBUS_CLR     (0x00000068)
+#define HW_CLKCTRL_HBUS_TOG     (0x0000006c)
+#define BM_CLKCTRL_HBUS_ASM_BUSY        0x80000000
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x40000000
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x20000000
+#define BM_CLKCTRL_HBUS_RSRVD2  0x10000000
+#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE   0x08000000
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE   0x01000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE       0x00800000
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
+#define BM_CLKCTRL_HBUS_ASM_ENABLE      0x00100000
+#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE   0x00080000
+#define BP_CLKCTRL_HBUS_SLOW_DIV        16
+#define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
+                (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
+#define BP_CLKCTRL_HBUS_RSRVD1  6
+#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
+#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
+#define BP_CLKCTRL_HBUS_DIV     0
+#define BM_CLKCTRL_HBUS_DIV     0x0000001F
+#define BF_CLKCTRL_HBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
+#define HW_CLKCTRL_XBUS (0x00000070)
+#define BM_CLKCTRL_XBUS_BUSY    0x80000000
+#define BP_CLKCTRL_XBUS_RSRVD1  12
+#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF000
+#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
+                (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
+#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE   0x00000800
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_XBUS_DIV     0
+#define BM_CLKCTRL_XBUS_DIV     0x000003FF
+#define BF_CLKCTRL_XBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
+#define HW_CLKCTRL_XTAL (0x00000080)
+#define HW_CLKCTRL_XTAL_SET     (0x00000084)
+#define HW_CLKCTRL_XTAL_CLR     (0x00000088)
+#define HW_CLKCTRL_XTAL_TOG     (0x0000008c)
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
+#define BM_CLKCTRL_XTAL_RSRVD3  0x40000000
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
+#define BP_CLKCTRL_XTAL_RSRVD2  27
+#define BM_CLKCTRL_XTAL_RSRVD2  0x18000000
+#define BF_CLKCTRL_XTAL_RSRVD2(v)  \
+                (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
+#define BP_CLKCTRL_XTAL_RSRVD1  2
+#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
+#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
+                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
+#define BP_CLKCTRL_XTAL_DIV_UART        0
+#define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
+#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
+                (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
+#define HW_CLKCTRL_SSP0 (0x00000090)
+#define BP_CLKCTRL_SSP0_CLKGATE 31
+#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP0_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP0_BUSY    0x20000000
+#define BP_CLKCTRL_SSP0_RSRVD1  10
+#define BM_CLKCTRL_SSP0_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP0_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
+#define BM_CLKCTRL_SSP0_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP0_DIV     0
+#define BM_CLKCTRL_SSP0_DIV     0x000001FF
+#define BF_CLKCTRL_SSP0_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
+#define HW_CLKCTRL_SSP1 (0x000000a0)
+#define BP_CLKCTRL_SSP1_CLKGATE 31
+#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP1_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP1_BUSY    0x20000000
+#define BP_CLKCTRL_SSP1_RSRVD1  10
+#define BM_CLKCTRL_SSP1_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP1_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
+#define BM_CLKCTRL_SSP1_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP1_DIV     0
+#define BM_CLKCTRL_SSP1_DIV     0x000001FF
+#define BF_CLKCTRL_SSP1_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
+#define HW_CLKCTRL_SSP2 (0x000000b0)
+#define BP_CLKCTRL_SSP2_CLKGATE 31
+#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP2_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP2_BUSY    0x20000000
+#define BP_CLKCTRL_SSP2_RSRVD1  10
+#define BM_CLKCTRL_SSP2_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP2_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
+#define BM_CLKCTRL_SSP2_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP2_DIV     0
+#define BM_CLKCTRL_SSP2_DIV     0x000001FF
+#define BF_CLKCTRL_SSP2_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
+#define HW_CLKCTRL_SSP3 (0x000000c0)
+#define BP_CLKCTRL_SSP3_CLKGATE 31
+#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP3_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP3_BUSY    0x20000000
+#define BP_CLKCTRL_SSP3_RSRVD1  10
+#define BM_CLKCTRL_SSP3_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP3_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
+#define BM_CLKCTRL_SSP3_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP3_DIV     0
+#define BM_CLKCTRL_SSP3_DIV     0x000001FF
+#define BF_CLKCTRL_SSP3_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
+#define HW_CLKCTRL_GPMI (0x000000d0)
+#define BP_CLKCTRL_GPMI_CLKGATE 31
+#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
+#define BM_CLKCTRL_GPMI_BUSY    0x20000000
+#define BP_CLKCTRL_GPMI_RSRVD1  11
+#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
+#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
+                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_GPMI_DIV     0
+#define BM_CLKCTRL_GPMI_DIV     0x000003FF
+#define BF_CLKCTRL_GPMI_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
+#define HW_CLKCTRL_SPDIF        (0x000000e0)
+#define BP_CLKCTRL_SPDIF_CLKGATE        31
+#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
+#define BP_CLKCTRL_SPDIF_RSRVD  0
+#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
+#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
+#define HW_CLKCTRL_EMI  (0x000000f0)
+#define BP_CLKCTRL_EMI_CLKGATE  31
+#define BM_CLKCTRL_EMI_CLKGATE  0x80000000
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN     0x40000000
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
+#define BP_CLKCTRL_EMI_RSRVD3   18
+#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
+#define BF_CLKCTRL_EMI_RSRVD3(v)  \
+                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
+#define BP_CLKCTRL_EMI_RSRVD2   12
+#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
+#define BF_CLKCTRL_EMI_RSRVD2(v)  \
+                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
+#define BP_CLKCTRL_EMI_DIV_XTAL 8
+#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
+                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
+#define BP_CLKCTRL_EMI_RSRVD1   6
+#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
+#define BF_CLKCTRL_EMI_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
+#define BP_CLKCTRL_EMI_DIV_EMI  0
+#define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
+#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
+                (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
+#define HW_CLKCTRL_SAIF0        (0x00000100)
+#define BP_CLKCTRL_SAIF0_CLKGATE        31
+#define BM_CLKCTRL_SAIF0_CLKGATE        0x80000000
+#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
+#define BM_CLKCTRL_SAIF0_BUSY   0x20000000
+#define BP_CLKCTRL_SAIF0_RSRVD1 17
+#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
+#define BF_CLKCTRL_SAIF0_RSRVD1(v)  \
+                (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
+#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN    0x00010000
+#define BP_CLKCTRL_SAIF0_DIV    0
+#define BM_CLKCTRL_SAIF0_DIV    0x0000FFFF
+#define BF_CLKCTRL_SAIF0_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
+#define HW_CLKCTRL_SAIF1        (0x00000110)
+#define BP_CLKCTRL_SAIF1_CLKGATE        31
+#define BM_CLKCTRL_SAIF1_CLKGATE        0x80000000
+#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
+#define BM_CLKCTRL_SAIF1_BUSY   0x20000000
+#define BP_CLKCTRL_SAIF1_RSRVD1 17
+#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
+#define BF_CLKCTRL_SAIF1_RSRVD1(v)  \
+                (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
+#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN    0x00010000
+#define BP_CLKCTRL_SAIF1_DIV    0
+#define BM_CLKCTRL_SAIF1_DIV    0x0000FFFF
+#define BF_CLKCTRL_SAIF1_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
+#define HW_CLKCTRL_DIS_LCDIF    (0x00000120)
+#define BP_CLKCTRL_DIS_LCDIF_CLKGATE    31
+#define BM_CLKCTRL_DIS_LCDIF_CLKGATE    0x80000000
+#define BM_CLKCTRL_DIS_LCDIF_RSRVD2     0x40000000
+#define BM_CLKCTRL_DIS_LCDIF_BUSY       0x20000000
+#define BP_CLKCTRL_DIS_LCDIF_RSRVD1     14
+#define BM_CLKCTRL_DIS_LCDIF_RSRVD1     0x1FFFC000
+#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v)  \
+                (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
+#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN        0x00002000
+#define BP_CLKCTRL_DIS_LCDIF_DIV        0
+#define BM_CLKCTRL_DIS_LCDIF_DIV        0x00001FFF
+#define BF_CLKCTRL_DIS_LCDIF_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
+#define HW_CLKCTRL_ETM  (0x00000130)
+#define BM_CLKCTRL_ETM_CLKGATE  0x80000000
+#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
+#define BM_CLKCTRL_ETM_BUSY     0x20000000
+#define BP_CLKCTRL_ETM_RSRVD1   8
+#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF00
+#define BF_CLKCTRL_ETM_RSRVD1(v)  \
+                (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000080
+#define BP_CLKCTRL_ETM_DIV      0
+#define BM_CLKCTRL_ETM_DIV      0x0000007F
+#define BF_CLKCTRL_ETM_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_ETM_DIV)
+#define HW_CLKCTRL_ENET (0x00000140)
+#define BM_CLKCTRL_ENET_SLEEP   0x80000000
+#define BP_CLKCTRL_ENET_DISABLE 30
+#define BM_CLKCTRL_ENET_DISABLE 0x40000000
+#define BM_CLKCTRL_ENET_STATUS  0x20000000
+#define BM_CLKCTRL_ENET_RSRVD1  0x10000000
+#define BM_CLKCTRL_ENET_BUSY_TIME       0x08000000
+#define BP_CLKCTRL_ENET_DIV_TIME        21
+#define BM_CLKCTRL_ENET_DIV_TIME        0x07E00000
+#define BF_CLKCTRL_ENET_DIV_TIME(v)  \
+                (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
+#define BM_CLKCTRL_ENET_BUSY    0x08000000
+#define BP_CLKCTRL_ENET_DIV     21
+#define BM_CLKCTRL_ENET_DIV     0x07E00000
+#define BF_CLKCTRL_ENET_DIV(v)  \
+                (((v) << 21) & BM_CLKCTRL_ENET_DIV)
+#define BP_CLKCTRL_ENET_TIME_SEL        19
+#define BM_CLKCTRL_ENET_TIME_SEL        0x00180000
+#define BF_CLKCTRL_ENET_TIME_SEL(v)  \
+                (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
+#define BV_CLKCTRL_ENET_TIME_SEL__XTAL      0x0
+#define BV_CLKCTRL_ENET_TIME_SEL__PLL       0x1
+#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK  0x2
+#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_ENET_CLK_OUT_EN      0x00040000
+#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP        0x00020000
+#define BM_CLKCTRL_ENET_RESET_BY_SW     0x00010000
+#define BP_CLKCTRL_ENET_RSRVD0  0
+#define BM_CLKCTRL_ENET_RSRVD0  0x0000FFFF
+#define BF_CLKCTRL_ENET_RSRVD0(v)  \
+                (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
+#define HW_CLKCTRL_HSADC        (0x00000150)
+#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
+#define BM_CLKCTRL_HSADC_RESETB 0x40000000
+#define BP_CLKCTRL_HSADC_FREQDIV        28
+#define BM_CLKCTRL_HSADC_FREQDIV        0x30000000
+#define BF_CLKCTRL_HSADC_FREQDIV(v)  \
+                (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
+#define BP_CLKCTRL_HSADC_RSRVD1 0
+#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
+#define BF_CLKCTRL_HSADC_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
+#define HW_CLKCTRL_FLEXCAN      (0x00000160)
+#define BM_CLKCTRL_FLEXCAN_RSRVD2       0x80000000
+#define BP_CLKCTRL_FLEXCAN_STOP_CAN0    30
+#define BM_CLKCTRL_FLEXCAN_STOP_CAN0    0x40000000
+#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS  0x20000000
+#define BP_CLKCTRL_FLEXCAN_STOP_CAN1    28
+#define BM_CLKCTRL_FLEXCAN_STOP_CAN1    0x10000000
+#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS  0x08000000
+#define BP_CLKCTRL_FLEXCAN_RSRVD1       0
+#define BM_CLKCTRL_FLEXCAN_RSRVD1       0x07FFFFFF
+#define BF_CLKCTRL_FLEXCAN_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
+#define HW_CLKCTRL_FRAC0        (0x000001b0)
+#define HW_CLKCTRL_FRAC0_SET    (0x000001b4)
+#define HW_CLKCTRL_FRAC0_CLR    (0x000001b8)
+#define HW_CLKCTRL_FRAC0_TOG    (0x000001bc)
+#define BP_CLKCTRL_FRAC0_CLKGATEIO0     31
+#define BM_CLKCTRL_FRAC0_CLKGATEIO0     0x80000000
+#define BM_CLKCTRL_FRAC0_IO0_STABLE     0x40000000
+#define BP_CLKCTRL_FRAC0_IO0FRAC        24
+#define BM_CLKCTRL_FRAC0_IO0FRAC        0x3F000000
+#define BF_CLKCTRL_FRAC0_IO0FRAC(v)  \
+                (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
+#define BP_CLKCTRL_FRAC0_CLKGATEIO1     23
+#define BM_CLKCTRL_FRAC0_CLKGATEIO1     0x00800000
+#define BM_CLKCTRL_FRAC0_IO1_STABLE     0x00400000
+#define BP_CLKCTRL_FRAC0_IO1FRAC        16
+#define BM_CLKCTRL_FRAC0_IO1FRAC        0x003F0000
+#define BF_CLKCTRL_FRAC0_IO1FRAC(v)  \
+                (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
+#define BP_CLKCTRL_FRAC0_CLKGATEEMI     15
+#define BM_CLKCTRL_FRAC0_CLKGATEEMI     0x00008000
+#define BM_CLKCTRL_FRAC0_EMI_STABLE     0x00004000
+#define BP_CLKCTRL_FRAC0_EMIFRAC        8
+#define BM_CLKCTRL_FRAC0_EMIFRAC        0x00003F00
+#define BF_CLKCTRL_FRAC0_EMIFRAC(v)  \
+                (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
+#define BP_CLKCTRL_FRAC0_CLKGATECPU     7
+#define BM_CLKCTRL_FRAC0_CLKGATECPU     0x00000080
+#define BM_CLKCTRL_FRAC0_CPU_STABLE     0x00000040
+#define BP_CLKCTRL_FRAC0_CPUFRAC        0
+#define BM_CLKCTRL_FRAC0_CPUFRAC        0x0000003F
+#define BF_CLKCTRL_FRAC0_CPUFRAC(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
+#define HW_CLKCTRL_FRAC1        (0x000001c0)
+#define HW_CLKCTRL_FRAC1_SET    (0x000001c4)
+#define HW_CLKCTRL_FRAC1_CLR    (0x000001c8)
+#define HW_CLKCTRL_FRAC1_TOG    (0x000001cc)
+#define BP_CLKCTRL_FRAC1_RSRVD2 24
+#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
+#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
+                (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
+#define BP_CLKCTRL_FRAC1_CLKGATEGPMI    23
+#define BM_CLKCTRL_FRAC1_CLKGATEGPMI    0x00800000
+#define BM_CLKCTRL_FRAC1_GPMI_STABLE    0x00400000
+#define BP_CLKCTRL_FRAC1_GPMIFRAC       16
+#define BM_CLKCTRL_FRAC1_GPMIFRAC       0x003F0000
+#define BF_CLKCTRL_FRAC1_GPMIFRAC(v)  \
+                (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
+#define BP_CLKCTRL_FRAC1_CLKGATEHSADC   15
+#define BM_CLKCTRL_FRAC1_CLKGATEHSADC   0x00008000
+#define BM_CLKCTRL_FRAC1_HSADC_STABLE   0x00004000
+#define BP_CLKCTRL_FRAC1_HSADCFRAC      8
+#define BM_CLKCTRL_FRAC1_HSADCFRAC      0x00003F00
+#define BF_CLKCTRL_FRAC1_HSADCFRAC(v)  \
+                (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
+#define BP_CLKCTRL_FRAC1_CLKGATEPIX     7
+#define BM_CLKCTRL_FRAC1_CLKGATEPIX     0x00000080
+#define BM_CLKCTRL_FRAC1_PIX_STABLE     0x00000040
+#define BP_CLKCTRL_FRAC1_PIXFRAC        0
+#define BM_CLKCTRL_FRAC1_PIXFRAC        0x0000003F
+#define BF_CLKCTRL_FRAC1_PIXFRAC(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
+#define HW_CLKCTRL_CLKSEQ       (0x000001d0)
+#define HW_CLKCTRL_CLKSEQ_SET   (0x000001d4)
+#define HW_CLKCTRL_CLKSEQ_CLR   (0x000001d8)
+#define HW_CLKCTRL_CLKSEQ_TOG   (0x000001dc)
+#define BP_CLKCTRL_CLKSEQ_RSRVD0        19
+#define BM_CLKCTRL_CLKSEQ_RSRVD0        0xFFF80000
+#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
+                (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00040000
+#define BP_CLKCTRL_CLKSEQ_RSRVD1        15
+#define BM_CLKCTRL_CLKSEQ_RSRVD1        0x00038000
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v)  \
+                (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF      0x00004000
+#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
+#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD    0x0
+#define BP_CLKCTRL_CLKSEQ_RSRVD2        9
+#define BM_CLKCTRL_CLKSEQ_RSRVD2        0x00003E00
+#define BF_CLKCTRL_CLKSEQ_RSRVD2(v)  \
+                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000080
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3   0x00000040
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2   0x00000020
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1   0x00000010
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0   0x00000008
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000004
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1  0x00000002
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0  0x00000001
+#define HW_CLKCTRL_RESET        (0x000001e0)
+#define BP_CLKCTRL_RESET_RSRVD  6
+#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFC0
+#define BF_CLKCTRL_RESET_RSRVD(v) \
+                (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
+#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE       0x00000020
+#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE  0x00000010
+#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE   0x00000008
+#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT  0x00000004
+#define BM_CLKCTRL_RESET_CHIP   0x00000002
+#define BM_CLKCTRL_RESET_DIG    0x00000001
+#define HW_CLKCTRL_STATUS       (0x000001f0)
+#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
+                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
+#define BP_CLKCTRL_STATUS_RSRVD 0
+#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
+#define BF_CLKCTRL_STATUS_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
+#define HW_CLKCTRL_VERSION      (0x00000200)
+#define BP_CLKCTRL_VERSION_MAJOR        24
+#define BM_CLKCTRL_VERSION_MAJOR        0xFF000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) \
+                (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
+#define BP_CLKCTRL_VERSION_MINOR        16
+#define BM_CLKCTRL_VERSION_MINOR        0x00FF0000
+#define BF_CLKCTRL_VERSION_MINOR(v)  \
+                (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
+#define BP_CLKCTRL_VERSION_STEP 0
+#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
+#define BF_CLKCTRL_VERSION_STEP(v)  \
+                (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
+#endif /* __REGS_CLKCTRL_MX28_H__ */
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
new file mode 100644
index 000000000000..9343d7edd4f6
--- /dev/null
+++ b/arch/arm/mach-mxs/system.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <asm/proc-fns.h>
+#include <asm/system.h>
+#include <mach/mxs.h>
+#include <mach/common.h>
+#define MX23_CLKCTRL_RESET_OFFSET       0x120
+#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
+#define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
+#define MXS_MODULE_CLKGATE              (1 << 30)
+#define MXS_MODULE_SFTRST               (1 << 31)
+static void __iomem *mxs_clkctrl_reset_addr;
+/*
+ * Reset the system. It is called by machine_restart().
+ */
+void arch_reset(char mode, const char *cmd)
+{
+        /* reset the chip */
+        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
+        pr_err("Failed to assert the chip reset\n");
+        /* Delay to allow the serial port to show the message */
+        mdelay(50);
+        /* We'll take a jump through zero as a poor second */
+        cpu_reset(0);
+}
+static int __init mxs_arch_reset_init(void)
+{
+        struct clk *clk;
+        mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
+                                (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
+                                                 MX28_CLKCTRL_RESET_OFFSET);
+        clk = clk_get_sys("rtc", NULL);
+        if (!IS_ERR(clk))
+                clk_enable(clk);
+        return 0;
+}
+core_initcall(mxs_arch_reset_init);
+/*
+ * Clear the bit and poll it cleared.  This is usually called with
+ * a reset address and mask being either SFTRST(bit 31) or CLKGATE
+ * (bit 30).
+ */
+static int clear_poll_bit(void __iomem *addr, u32 mask)
+{
+        int timeout = 0x400;
+        /* clear the bit */
+        __mxs_clrl(mask, addr);
+        /*
+         * SFTRST needs 3 GPMI clocks to settle, the reference manual
+         * recommends to wait 1us.
+         */
+        udelay(1);
+        /* poll the bit becoming clear */
+        while ((__raw_readl(addr) & mask) && --timeout)
+                /* nothing */;
+        return !timeout;
+}
+int mxs_reset_block(void __iomem *reset_addr)
+{
+        int ret;
+        int timeout = 0x400;
+        /* clear and poll SFTRST */
+        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
+        if (unlikely(ret))
+                goto error;
+        /* clear CLKGATE */
+        __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
+        /* set SFTRST to reset the block */
+        __mxs_setl(MXS_MODULE_SFTRST, reset_addr);
+        udelay(1);
+        /* poll CLKGATE becoming set */
+        while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
+                /* nothing */;
+        if (unlikely(!timeout))
+                goto error;
+        /* clear and poll SFTRST */
+        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
+        if (unlikely(ret))
+                goto error;
+        /* clear and poll CLKGATE */
+        ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
+        if (unlikely(ret))
+                goto error;
+        return 0;
+error:
+        pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
+        return -ETIMEDOUT;
+}
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
new file mode 100644
index 000000000000..13647f301860
--- /dev/null
+++ b/arch/arm/mach-mxs/timer.c
@@ -0,0 +1,296 @@
+/*
+ *  Copyright (C) 2000-2001 Deep Blue Solutions
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
+ *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <asm/mach/time.h>
+#include <mach/mxs.h>
+#include <mach/common.h>
+/*
+ * There are 2 versions of the timrot on Freescale MXS-based SoCs.
+ * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
+ * extends the counter to 32 bits.
+ *
+ * The implementation uses two timers, one for clock_event and
+ * another for clocksource. MX28 uses timrot 0 and 1, while MX23
+ * uses 0 and 2.
+ */
+#define MX23_TIMROT_VERSION_OFFSET      0x0a0
+#define MX28_TIMROT_VERSION_OFFSET      0x120
+#define BP_TIMROT_MAJOR_VERSION         24
+#define BV_TIMROT_VERSION_1             0x01
+#define BV_TIMROT_VERSION_2             0x02
+#define timrot_is_v1()  (timrot_major_version == BV_TIMROT_VERSION_1)
+/*
+ * There are 4 registers for each timrotv2 instance, and 2 registers
+ * for each timrotv1. So address step 0x40 in macros below strides
+ * one instance of timrotv2 while two instances of timrotv1.
+ *
+ * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
+ * on MX28 while timrot2 on MX23.
+ */
+/* common between v1 and v2 */
+#define HW_TIMROT_ROTCTRL               0x00
+#define HW_TIMROT_TIMCTRLn(n)           (0x20 + (n) * 0x40)
+/* v1 only */
+#define HW_TIMROT_TIMCOUNTn(n)          (0x30 + (n) * 0x40)
+/* v2 only */
+#define HW_TIMROT_RUNNING_COUNTn(n)     (0x30 + (n) * 0x40)
+#define HW_TIMROT_FIXED_COUNTn(n)       (0x40 + (n) * 0x40)
+#define BM_TIMROT_TIMCTRLn_RELOAD       (1 << 6)
+#define BM_TIMROT_TIMCTRLn_UPDATE       (1 << 7)
+#define BM_TIMROT_TIMCTRLn_IRQ_EN       (1 << 14)
+#define BM_TIMROT_TIMCTRLn_IRQ          (1 << 15)
+#define BP_TIMROT_TIMCTRLn_SELECT       0
+#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
+#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
+static struct clock_event_device mxs_clockevent_device;
+static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
+static u32 timrot_major_version;
+static inline void timrot_irq_disable(void)
+{
+        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+}
+static inline void timrot_irq_enable(void)
+{
+        __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+}
+static void timrot_irq_acknowledge(void)
+{
+        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+}
+static cycle_t timrotv1_get_cycles(struct clocksource *cs)
+{
+        return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
+                        & 0xffff0000) >> 16);
+}
+static cycle_t timrotv2_get_cycles(struct clocksource *cs)
+{
+        return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
+}
+static int timrotv1_set_next_event(unsigned long evt,
+                                        struct clock_event_device *dev)
+{
+        /* timrot decrements the count */
+        __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
+        return 0;
+}
+static int timrotv2_set_next_event(unsigned long evt,
+                                        struct clock_event_device *dev)
+{
+        /* timrot decrements the count */
+        __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
+        return 0;
+}
+static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+        timrot_irq_acknowledge();
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+static struct irqaction mxs_timer_irq = {
+        .name           = "MXS Timer Tick",
+        .dev_id         = &mxs_clockevent_device,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = mxs_timer_interrupt,
+};
+#ifdef DEBUG
+static const char *clock_event_mode_label[] const = {
+        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
+        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
+        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
+        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
+};
+#endif /* DEBUG */
+static void mxs_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        /* Disable interrupt in timer module */
+        timrot_irq_disable();
+        if (mode != mxs_clockevent_mode) {
+                /* Set event time into the furthest future */
+                if (timrot_is_v1())
+                        __raw_writel(0xffff,
+                                mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
+                else
+                        __raw_writel(0xffffffff,
+                                mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
+                /* Clear pending interrupt */
+                timrot_irq_acknowledge();
+        }
+#ifdef DEBUG
+        pr_info("%s: changing mode from %s to %s\n", __func__,
+                clock_event_mode_label[mxs_clockevent_mode],
+                clock_event_mode_label[mode]);
+#endif /* DEBUG */
+        /* Remember timer mode */
+        mxs_clockevent_mode = mode;
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                pr_err("%s: Periodic mode is not implemented\n", __func__);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                timrot_irq_enable();
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
+}
+static struct clock_event_device mxs_clockevent_device = {
+        .name           = "mxs_timrot",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = mxs_set_mode,
+        .set_next_event = timrotv2_set_next_event,
+        .rating         = 200,
+};
+static int __init mxs_clockevent_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+        mxs_clockevent_device.mult =
+                div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
+        mxs_clockevent_device.cpumask = cpumask_of(0);
+        if (timrot_is_v1()) {
+                mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
+                mxs_clockevent_device.max_delta_ns =
+                        clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
+                mxs_clockevent_device.min_delta_ns =
+                        clockevent_delta2ns(0xf, &mxs_clockevent_device);
+        } else {
+                mxs_clockevent_device.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
+                mxs_clockevent_device.min_delta_ns =
+                        clockevent_delta2ns(0xf, &mxs_clockevent_device);
+        }
+        clockevents_register_device(&mxs_clockevent_device);
+        return 0;
+}
+static struct clocksource clocksource_mxs = {
+        .name           = "mxs_timer",
+        .rating         = 200,
+        .read           = timrotv2_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static int __init mxs_clocksource_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+        if (timrot_is_v1()) {
+                clocksource_mxs.read = timrotv1_get_cycles;
+                clocksource_mxs.mask = CLOCKSOURCE_MASK(16);
+        }
+        clocksource_register_hz(&clocksource_mxs, c);
+        return 0;
+}
+void __init mxs_timer_init(struct clk *timer_clk, int irq)
+{
+        clk_enable(timer_clk);
+        /*
+         * Initialize timers to a known state
+         */
+        mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
+        /* get timrot version */
+        timrot_major_version = __raw_readl(mxs_timrot_base +
+                                (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
+                                                MX28_TIMROT_VERSION_OFFSET));
+        timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
+        /* one for clock_event */
+        __raw_writel((timrot_is_v1() ?
+                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
+                        BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
+                        BM_TIMROT_TIMCTRLn_UPDATE |
+                        BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+        /* another for clocksource */
+        __raw_writel((timrot_is_v1() ?
+                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
+                        BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
+                        BM_TIMROT_TIMCTRLn_RELOAD,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
+        /* set clocksource timer fixed count to the maximum */
+        if (timrot_is_v1())
+                __raw_writel(0xffff,
+                        mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
+        else
+                __raw_writel(0xffffffff,
+                        mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
+        /* init and register the timer to the framework */
+        mxs_clocksource_init(timer_clk);
+        mxs_clockevent_init(timer_clk);
+        /* Make irqs happen */
+        setup_irq(irq, &mxs_timer_irq);
+}
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
index 4075473cf68a..b34be4554d40 100644
--- a/arch/arm/mach-realview/headsmp.S
+++ b/arch/arm/mach-realview/headsmp.S
@@ -35,5 +35,6 @@ pen:	ldr	r7, [r6]
         */
        b       secondary_startup
+        .align
 1:      .long   .
        .long   pen_release
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 8ea3bffb4e00..a0e7c12868bd 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -21,8 +21,8 @@
 #include <mach/io.h>
        .macro  addruart, rp, rv
-        ldreq   \rp, =IO_APB_PHYS       @ physical
+        ldr     \rp, =IO_APB_PHYS       @ physical
-        ldrne   \rv, =IO_APB_VIRT        @ virtual
+        ldr     \rv, =IO_APB_VIRT        @ virtual
 #if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
 #error "A debug UART must be selected in the kernel config to use DEBUG_LL"
 #elif defined(CONFIG_TEGRA_DEBUG_UARTA)
diff --git a/arch/arm/mach-vexpress/headsmp.S b/arch/arm/mach-vexpress/headsmp.S
index 8a78ff68e1ee..7a3f0632947c 100644
--- a/arch/arm/mach-vexpress/headsmp.S
+++ b/arch/arm/mach-vexpress/headsmp.S
@@ -35,5 +35,6 @@ pen:	ldr	r7, [r6]
         */
        b       secondary_startup
+        .align
 1:      .long   .
        .long   pen_release
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 53cbe2225153..9b9ff5d949fd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -381,7 +381,7 @@ __v7_ca9mp_proc_info:
                PMD_SECT_XN | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
-        b       __v7_ca9mp_setup
+        W(b)    __v7_ca9mp_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
@@ -413,7 +413,7 @@ __v7_proc_info:
                PMD_SECT_XN | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
-        b       __v7_setup
+        W(b)    __v7_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 85d3e55ca4a9..558cdfaf76b6 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -18,6 +18,7 @@
 #include <linux/time.h>
 #include <linux/init.h>
 #include <linux/timex.h>
+#include <linux/sched.h>
 #include <linux/io.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
@@ -36,7 +37,7 @@
 /*
 * IOP clocksource (free-running timer 1).
 */
-static cycle_t iop_clocksource_read(struct clocksource *unused)
+static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
 {
        return 0xffffffffu - read_tcr1();
 }
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index d66cead97d28..9897dcfc16d6 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -206,6 +206,7 @@ ENTRY(vfp_save_state)
        mov     pc, lr
 ENDPROC(vfp_save_state)
+        .align
 last_VFP_context_address:
        .word   last_VFP_context
diff --git a/arch/mn10300/include/asm/syscall.h b/arch/mn10300/include/asm/syscall.h
new file mode 100644
index 000000000000..b44b0bb75a01
--- /dev/null
+++ b/arch/mn10300/include/asm/syscall.h
@@ -0,0 +1,117 @@
+/* Access to user system call parameters and results
+ *
+ * See asm-generic/syscall.h for function descriptions.
+ *
+ * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SYSCALL_H
+#define _ASM_SYSCALL_H
+#include <linux/sched.h>
+#include <linux/err.h>
+extern const unsigned long sys_call_table[];
+static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+        return regs->orig_d0;
+}
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        regs->d0 = regs->orig_d0;
+}
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        unsigned long error = regs->d0;
+        return IS_ERR_VALUE(error) ? error : 0;
+}
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->d0;
+}
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        regs->d0 = (long) error ?: val;
+}
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+        switch (i) {
+        case 0:
+                if (!n--) break;
+                *args++ = regs->a0;
+        case 1:
+                if (!n--) break;
+                *args++ = regs->d1;
+        case 2:
+                if (!n--) break;
+                *args++ = regs->a3;
+        case 3:
+                if (!n--) break;
+                *args++ = regs->a2;
+        case 4:
+                if (!n--) break;
+                *args++ = regs->d3;
+        case 5:
+                if (!n--) break;
+                *args++ = regs->d2;
+        case 6:
+                if (!n--) break;
+        default:
+                BUG();
+                break;
+        }
+}
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        switch (i) {
+        case 0:
+                if (!n--) break;
+                regs->a0 = *args++;
+        case 1:
+                if (!n--) break;
+                regs->d1 = *args++;
+        case 2:
+                if (!n--) break;
+                regs->a3 = *args++;
+        case 3:
+                if (!n--) break;
+                regs->a2 = *args++;
+        case 4:
+                if (!n--) break;
+                regs->d3 = *args++;
+        case 5:
+                if (!n--) break;
+                regs->d2 = *args++;
+        case 6:
+                if (!n--) break;
+        default:
+                BUG();
+                break;
+        }
+}
+#endif /* _ASM_SYSCALL_H */
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index 5024f643b3b1..d7d94b845dc2 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -75,9 +75,6 @@ static void cpu_unmask_irq(unsigned int irq)
        smp_send_all_nop();
 }
-void no_ack_irq(unsigned int irq) { }
-void no_end_irq(unsigned int irq) { }
 void cpu_ack_irq(unsigned int irq)
 {
        unsigned long mask = EIEM_MASK(irq);
@@ -241,7 +238,7 @@ int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
        /* for iosapic interrupts */
        if (type) {
-                set_irq_chip_and_handler(irq, type, handle_level_irq);
+                set_irq_chip_and_handler(irq, type, handle_percpu_irq);
                set_irq_chip_data(irq, data);
                cpu_unmask_irq(irq);
        }
@@ -392,7 +389,7 @@ static void claim_cpu_irqs(void)
        int i;
        for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
                set_irq_chip_and_handler(i, &cpu_interrupt_type,
-                        handle_level_irq);
+                                         handle_percpu_irq);
        }
        set_irq_handler(TIMER_IRQ, handle_percpu_irq);
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index 35c827e94e31..609a331878e7 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -98,7 +98,6 @@ void
 sys_rt_sigreturn(struct pt_regs *regs, int in_syscall)
 {
        struct rt_sigframe __user *frame;
-        struct siginfo si;
        sigset_t set;
        unsigned long usp = (regs->gr[30] & ~(0x01UL));
        unsigned long sigframe_size = PARISC_RT_SIGFRAME_SIZE;
@@ -178,13 +177,7 @@ sys_rt_sigreturn(struct pt_regs *regs, int in_syscall)
 give_sigsegv:
        DBG(1,"sys_rt_sigreturn: Sending SIGSEGV\n");
-        si.si_signo = SIGSEGV;
+        force_sig(SIGSEGV, current);
-        si.si_errno = 0;
-        si.si_code = SI_KERNEL;
-        si.si_pid = task_pid_vnr(current);
-        si.si_uid = current_uid();
-        si.si_addr = &frame->uc;
-        force_sig_info(SIGSEGV, &si, current);
        return;
 }
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index 56c8687b29b3..7eff9b7347c0 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -19,6 +19,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/rcupdate.h>
 #include <linux/posix-timers.h>
+#include <linux/cpu.h>
 #include <asm/s390_ext.h>
 #include <asm/timer.h>
@@ -566,6 +567,23 @@ void init_cpu_vtimer(void)
        __ctl_set_bit(0,10);
 }
+static int __cpuinit s390_nohz_notify(struct notifier_block *self,
+                                      unsigned long action, void *hcpu)
+{
+        struct s390_idle_data *idle;
+        long cpu = (long) hcpu;
+        idle = &per_cpu(s390_idle, cpu);
+        switch (action) {
+        case CPU_DYING:
+        case CPU_DYING_FROZEN:
+                idle->nohz_delay = 0;
+        default:
+                break;
+        }
+        return NOTIFY_OK;
+}
 void __init vtime_init(void)
 {
        /* request the cpu timer external interrupt */
@@ -574,5 +592,6 @@ void __init vtime_init(void)
        /* Enable cpu timer interrupts on the boot cpu. */
        init_cpu_vtimer();
+        cpu_notifier(s390_nohz_notify, 0);
 }
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 2eaeb9e59585..f48c492a68d3 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -720,32 +720,6 @@ static struct platform_device camera_devices[] = {
 };
 /* FSI */
-/*
- * FSI-B use external clock which came from da7210.
- * So, we should change parent of fsi
- */
-#define FCLKBCR         0xa415000c
-static void fsimck_init(struct clk *clk)
-{
-        u32 status = __raw_readl(clk->enable_reg);
-        /* use external clock */
-        status &= ~0x000000ff;
-        status |= 0x00000080;
-        __raw_writel(status, clk->enable_reg);
-}
-static struct clk_ops fsimck_clk_ops = {
-        .init = fsimck_init,
-};
-static struct clk fsimckb_clk = {
-        .ops            = &fsimck_clk_ops,
-        .enable_reg     = (void __iomem *)FCLKBCR,
-        .rate           = 0, /* unknown */
-};
 static struct sh_fsi_platform_info fsi_info = {
        .portb_flags = SH_FSI_BRS_INV |
                       SH_FSI_OUT_SLAVE_MODE |
@@ -1264,10 +1238,10 @@ static int __init arch_setup(void)
        /* change parent of FSI B */
        clk = clk_get(NULL, "fsib_clk");
        if (!IS_ERR(clk)) {
-                clk_register(&fsimckb_clk);
+                /* 48kHz dummy clock was used to make sure 1/1 divide */
-                clk_set_parent(clk, &fsimckb_clk);
+                clk_set_rate(&sh7724_fsimckb_clk, 48000);
-                clk_set_rate(clk, 11000);
+                clk_set_parent(clk, &sh7724_fsimckb_clk);
-                clk_set_rate(&fsimckb_clk, 11000);
+                clk_set_rate(clk, 48000);
                clk_put(clk);
        }
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index c31d228fdfc6..527a0cd956b5 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -283,31 +283,6 @@ static struct platform_device ceu1_device = {
 };
 /* FSI */
-/*
- * FSI-A use external clock which came from ak464x.
- * So, we should change parent of fsi
- */
-#define FCLKACR         0xa4150008
-static void fsimck_init(struct clk *clk)
-{
-        u32 status = __raw_readl(clk->enable_reg);
-        /* use external clock */
-        status &= ~0x000000ff;
-        status |= 0x00000080;
-        __raw_writel(status, clk->enable_reg);
-}
-static struct clk_ops fsimck_clk_ops = {
-        .init = fsimck_init,
-};
-static struct clk fsimcka_clk = {
-        .ops            = &fsimck_clk_ops,
-        .enable_reg     = (void __iomem *)FCLKACR,
-        .rate           = 0, /* unknown */
-};
 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
 static struct sh_fsi_platform_info fsi_info = {
        .porta_flags = SH_FSI_BRS_INV |
@@ -852,37 +827,29 @@ static int __init devices_setup(void)
        gpio_request(GPIO_FN_KEYOUT0,     NULL);
        /* enable FSI */
-        gpio_request(GPIO_FN_FSIMCKB,    NULL);
        gpio_request(GPIO_FN_FSIMCKA,    NULL);
+        gpio_request(GPIO_FN_FSIIASD,    NULL);
        gpio_request(GPIO_FN_FSIOASD,    NULL);
        gpio_request(GPIO_FN_FSIIABCK,   NULL);
        gpio_request(GPIO_FN_FSIIALRCK,  NULL);
        gpio_request(GPIO_FN_FSIOABCK,   NULL);
        gpio_request(GPIO_FN_FSIOALRCK,  NULL);
        gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
-        gpio_request(GPIO_FN_FSIIBSD,    NULL);
-        gpio_request(GPIO_FN_FSIOBSD,    NULL);
-        gpio_request(GPIO_FN_FSIIBBCK,   NULL);
-        gpio_request(GPIO_FN_FSIIBLRCK,  NULL);
-        gpio_request(GPIO_FN_FSIOBBCK,   NULL);
-        gpio_request(GPIO_FN_FSIOBLRCK,  NULL);
-        gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
-        gpio_request(GPIO_FN_FSIIASD,    NULL);
        /* set SPU2 clock to 83.4 MHz */
        clk = clk_get(NULL, "spu_clk");
-        if (clk) {
+        if (!IS_ERR(clk)) {
                clk_set_rate(clk, clk_round_rate(clk, 83333333));
                clk_put(clk);
        }
        /* change parent of FSI A */
        clk = clk_get(NULL, "fsia_clk");
-        if (clk) {
+        if (!IS_ERR(clk)) {
-                clk_register(&fsimcka_clk);
+                /* 48kHz dummy clock was used to make sure 1/1 divide */
-                clk_set_parent(clk, &fsimcka_clk);
+                clk_set_rate(&sh7724_fsimcka_clk, 48000);
-                clk_set_rate(clk, 11000);
+                clk_set_parent(clk, &sh7724_fsimcka_clk);
-                clk_set_rate(&fsimcka_clk, 11000);
+                clk_set_rate(clk, 48000);
                clk_put(clk);
        }
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 1f4e562c5e8c..82e1eabeac98 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -96,7 +96,7 @@ void kmap_coherent_init(void);
 void *kmap_coherent(struct page *page, unsigned long addr);
 void kunmap_coherent(void *kvaddr);
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 void cpu_cache_init(void);
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
index 4c27b68789b3..7eb435999426 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7724.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -303,4 +303,7 @@ enum {
        SHDMA_SLAVE_SDHI1_RX,
 };
+extern struct clk sh7724_fsimcka_clk;
+extern struct clk sh7724_fsimckb_clk;
 #endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 0fe2e9329cb2..271c0b325a9a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -111,12 +111,21 @@ static struct clk div3_clk = {
        .parent         = &pll_clk,
 };
+/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
+struct clk sh7724_fsimcka_clk = {
+};
+struct clk sh7724_fsimckb_clk = {
+};
 static struct clk *main_clks[] = {
        &r_clk,
        &extal_clk,
        &fll_clk,
        &pll_clk,
        &div3_clk,
+        &sh7724_fsimcka_clk,
+        &sh7724_fsimckb_clk,
 };
 static void div4_kick(struct clk *clk)
@@ -154,16 +163,38 @@ struct clk div4_clks[DIV4_NR] = {
        [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 };
-enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
+enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
 static struct clk div6_clks[DIV6_NR] = {
        [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
-        [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
-        [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
        [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
        [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
 };
+enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
+/* Indices are important - they are the actual src selecting values */
+static struct clk *fclkacr_parent[] = {
+        [0] = &div3_clk,
+        [1] = NULL,
+        [2] = &sh7724_fsimcka_clk,
+        [3] = NULL,
+};
+static struct clk *fclkbcr_parent[] = {
+        [0] = &div3_clk,
+        [1] = NULL,
+        [2] = &sh7724_fsimckb_clk,
+        [3] = NULL,
+};
+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
+        [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
+                                      fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
+        [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
+                                      fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
+};
 static struct clk mstp_clks[HWBLK_NR] = {
        SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
        SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
@@ -240,8 +271,8 @@ static struct clk_lookup lookups[] = {
        /* DIV6 clocks */
        CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
-        CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
+        CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
-        CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
+        CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
        CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
@@ -376,6 +407,9 @@ int __init arch_clk_init(void)
                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
+        if (!ret)
                ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
        return ret;
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 2cfae81914aa..92eb98633ab0 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -114,7 +114,7 @@ static void sh4_flush_dcache_page(void *arg)
        struct address_space *mapping = page_mapping(page);
        if (mapping && !mapping_mapped(mapping))
-                set_bit(PG_dcache_dirty, &page->flags);
+                clear_bit(PG_dcache_clean, &page->flags);
        else
 #endif
                flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
@@ -239,7 +239,7 @@ static void sh4_flush_cache_page(void *args)
                 * another ASID than the current one.
                 */
                map_coherent = (current_cpu_data.dcache.n_aliases &&
-                        !test_bit(PG_dcache_dirty, &page->flags) &&
+                        test_bit(PG_dcache_clean, &page->flags) &&
                        page_mapped(page));
                if (map_coherent)
                        vaddr = kmap_coherent(page, address);
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index f498da1cce7a..7729cca727eb 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -139,7 +139,7 @@ static void sh7705_flush_dcache_page(void *arg)
        struct address_space *mapping = page_mapping(page);
        if (mapping && !mapping_mapped(mapping))
-                set_bit(PG_dcache_dirty, &page->flags);
+                clear_bit(PG_dcache_clean, &page->flags);
        else
                __flush_dcache_page(__pa(page_address(page)));
 }
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index ba401d137bb9..88d3dc3d30d5 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -60,14 +60,14 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
                       unsigned long len)
 {
        if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
-            !test_bit(PG_dcache_dirty, &page->flags)) {
+            test_bit(PG_dcache_clean, &page->flags)) {
                void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
                memcpy(vto, src, len);
                kunmap_coherent(vto);
        } else {
                memcpy(dst, src, len);
                if (boot_cpu_data.dcache.n_aliases)
-                        set_bit(PG_dcache_dirty, &page->flags);
+                        clear_bit(PG_dcache_clean, &page->flags);
        }
        if (vma->vm_flags & VM_EXEC)
@@ -79,14 +79,14 @@ void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
                         unsigned long len)
 {
        if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
-            !test_bit(PG_dcache_dirty, &page->flags)) {
+            test_bit(PG_dcache_clean, &page->flags)) {
                void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
                memcpy(dst, vfrom, len);
                kunmap_coherent(vfrom);
        } else {
                memcpy(dst, src, len);
                if (boot_cpu_data.dcache.n_aliases)
-                        set_bit(PG_dcache_dirty, &page->flags);
+                        clear_bit(PG_dcache_clean, &page->flags);
        }
 }
@@ -98,7 +98,7 @@ void copy_user_highpage(struct page *to, struct page *from,
        vto = kmap_atomic(to, KM_USER1);
        if (boot_cpu_data.dcache.n_aliases && page_mapped(from) &&
-            !test_bit(PG_dcache_dirty, &from->flags)) {
+            test_bit(PG_dcache_clean, &from->flags)) {
                vfrom = kmap_coherent(from, vaddr);
                copy_page(vto, vfrom);
                kunmap_coherent(vfrom);
@@ -141,7 +141,7 @@ void __update_cache(struct vm_area_struct *vma,
        page = pfn_to_page(pfn);
        if (pfn_valid(pfn)) {
-                int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
+                int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
                if (dirty)
                        __flush_purge_region(page_address(page), PAGE_SIZE);
        }
@@ -153,7 +153,7 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
        if (pages_do_alias(addr, vmaddr)) {
                if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
-                    !test_bit(PG_dcache_dirty, &page->flags)) {
+                    test_bit(PG_dcache_clean, &page->flags)) {
                        void *kaddr;
                        kaddr = kmap_coherent(page, vmaddr);
diff --git a/arch/sh/mm/kmap.c b/arch/sh/mm/kmap.c
index 15d74ea42094..ec29e14ec5a8 100644
--- a/arch/sh/mm/kmap.c
+++ b/arch/sh/mm/kmap.c
@@ -34,7 +34,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
        enum fixed_addresses idx;
        unsigned long vaddr;
-        BUG_ON(test_bit(PG_dcache_dirty, &page->flags));
+        BUG_ON(!test_bit(PG_dcache_clean, &page->flags));
        pagefault_disable();
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index d7b5109f7a9c..25cd4a07d09f 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -70,6 +70,9 @@ static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
 struct xen_pci_frontend_ops *xen_pci_frontend;
 EXPORT_SYMBOL_GPL(xen_pci_frontend);
+#define XEN_PIRQ_MSI_DATA  (MSI_DATA_TRIGGER_EDGE | \
+                MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0))
 static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
                struct msi_msg *msg)
 {
@@ -83,12 +86,7 @@ static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
                MSI_ADDR_REDIRECTION_CPU |
                MSI_ADDR_DEST_ID(pirq);
-        msg->data =
+        msg->data = XEN_PIRQ_MSI_DATA;
-                MSI_DATA_TRIGGER_EDGE |
-                MSI_DATA_LEVEL_ASSERT |
-                /* delivery mode reserved */
-                (3 << 8) |
-                MSI_DATA_VECTOR(0);
 }
 static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
@@ -98,8 +96,23 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
        struct msi_msg msg;
        list_for_each_entry(msidesc, &dev->msi_list, list) {
+                __read_msi_msg(msidesc, &msg);
+                pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) |
+                        ((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff);
+                if (xen_irq_from_pirq(pirq) >= 0 && msg.data == XEN_PIRQ_MSI_DATA) {
+                        xen_allocate_pirq_msi((type == PCI_CAP_ID_MSIX) ?
+                                        "msi-x" : "msi", &irq, &pirq, XEN_ALLOC_IRQ);
+                        if (irq < 0)
+                                goto error;
+                        ret = set_irq_msi(irq, msidesc);
+                        if (ret < 0)
+                                goto error_while;
+                        printk(KERN_DEBUG "xen: msi already setup: msi --> irq=%d"
+                                        " pirq=%d\n", irq, pirq);
+                        return 0;
+                }
                xen_allocate_pirq_msi((type == PCI_CAP_ID_MSIX) ?
-                                "msi-x" : "msi", &irq, &pirq);
+                                "msi-x" : "msi", &irq, &pirq, (XEN_ALLOC_IRQ | XEN_ALLOC_PIRQ));
                if (irq < 0 || pirq < 0)
                        goto error;
                printk(KERN_DEBUG "xen: msi --> irq=%d, pirq=%d\n", irq, pirq);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 02c710bebf7a..44dcad43989d 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1021,10 +1021,6 @@ static void xen_reboot(int reason)
 {
        struct sched_shutdown r = { .reason = reason };
-#ifdef CONFIG_SMP
-        stop_other_cpus();
-#endif
        if (HYPERVISOR_sched_op(SCHEDOP_shutdown, &r))
                BUG();
 }
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index a1feff9e59b6..44924e551fde 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -2415,8 +2415,6 @@ void __init xen_init_mmu_ops(void)
        x86_init.paging.pagetable_setup_done = xen_pagetable_setup_done;
        pv_mmu_ops = xen_mmu_ops;
-        vmap_lazy_unmap = false;
        memset(dummy_mapping, 0xff, PAGE_SIZE);
 }
diff --git a/arch/x86/xen/platform-pci-unplug.c b/arch/x86/xen/platform-pci-unplug.c
index 0f456386cce5..25c52f94a27c 100644
--- a/arch/x86/xen/platform-pci-unplug.c
+++ b/arch/x86/xen/platform-pci-unplug.c
@@ -68,7 +68,7 @@ static int __init check_platform_magic(void)
        return 0;
 }
-void __init xen_unplug_emulated_devices(void)
+void xen_unplug_emulated_devices(void)
 {
        int r;
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index 01afd8a94607..b5a7f928234b 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -181,24 +181,21 @@ char * __init xen_memory_setup(void)
        for (i = 0; i < memmap.nr_entries; i++) {
                unsigned long long end = map[i].addr + map[i].size;
-                if (map[i].type == E820_RAM) {
+                if (map[i].type == E820_RAM && end > mem_end) {
-                        if (map[i].addr < mem_end && end > mem_end) {
+                        /* RAM off the end - may be partially included */
-                                /* Truncate region to max_mem. */
+                        u64 delta = min(map[i].size, end - mem_end);
-                                u64 delta = end - mem_end;
-                                map[i].size -= delta;
+                        map[i].size -= delta;
-                                extra_pages += PFN_DOWN(delta);
+                        end -= delta;
-                                end = mem_end;
+                        extra_pages += PFN_DOWN(delta);
-                        }
                }
-                if (end > xen_extra_mem_start)
+                if (map[i].size > 0 && end > xen_extra_mem_start)
                        xen_extra_mem_start = end;
-                /* If region is non-RAM or below mem_end, add what remains */
+                /* Add region if any remains */
-                if ((map[i].type != E820_RAM || map[i].addr < mem_end) &&
+                if (map[i].size > 0)
-                    map[i].size > 0)
                        e820_add_region(map[i].addr, map[i].size, map[i].type);
        }
@@ -252,20 +249,6 @@ char * __init xen_memory_setup(void)
        return "Xen";
 }
-static void xen_idle(void)
-{
-        local_irq_disable();
-        if (need_resched())
-                local_irq_enable();
-        else {
-                current_thread_info()->status &= ~TS_POLLING;
-                smp_mb__after_clear_bit();
-                safe_halt();
-                current_thread_info()->status |= TS_POLLING;
-        }
-}
 /*
 * Set the bit indicating "nosegneg" library variants should be used.
 * We only need to bother in pure 32-bit mode; compat 32-bit processes
@@ -362,7 +345,11 @@ void __init xen_arch_setup(void)
               MAX_GUEST_CMDLINE > COMMAND_LINE_SIZE ?
               COMMAND_LINE_SIZE : MAX_GUEST_CMDLINE);
-        pm_idle = xen_idle;
+        /* Set up idle, making sure it calls safe_halt() pvop */
+#ifdef CONFIG_X86_32
+        boot_cpu_data.hlt_works_ok = 1;
+#endif
+        pm_idle = default_idle;
        fiddle_vdso();
 }
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
index 1d789d56877c..9bbd63a129b5 100644
--- a/arch/x86/xen/suspend.c
+++ b/arch/x86/xen/suspend.c
@@ -31,6 +31,7 @@ void xen_hvm_post_suspend(int suspend_cancelled)
        int cpu;
        xen_hvm_init_shared_info();
        xen_callback_vector();
+        xen_unplug_emulated_devices();
        if (xen_feature(XENFEAT_hvm_safe_pvclock)) {
                for_each_online_cpu(cpu) {
                        xen_setup_runstate_info(cpu);
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 64044747348e..9d41bf985757 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -43,7 +43,7 @@ void xen_vcpu_restore(void);
 void xen_callback_vector(void);
 void xen_hvm_init_shared_info(void);
-void __init xen_unplug_emulated_devices(void);
+void xen_unplug_emulated_devices(void);
 void __init xen_build_dynamic_phys_to_machine(void);