2 files changed, 44 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 771a776d6101..6ed608322ddc 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -84,6 +84,10 @@
                           6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
                           7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
 
+                fpga@4,0 {
+                        compatible = "gef,fpga-regs";
+                        reg = <0x4 0x0 0x40>;
+                };
                 gef_pic: pic@4,4000 {
                         #interrupt-cells = <1>;
                         interrupt-controller;
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 3873c2018cc3..821c45fac18b 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -73,6 +73,7 @@ static void __init gef_sbc610_init_irq(void)
 
 static void __init gef_sbc610_setup_arch(void)
 {
+        struct device_node *regs;
 #ifdef CONFIG_PCI
         struct device_node *np;
 
@@ -86,8 +87,43 @@ static void __init gef_sbc610_setup_arch(void)
 #ifdef CONFIG_SMP
         mpc86xx_smp_init();
 #endif
+
+        /* Remap basic board registers */
+        regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
+        if (regs) {
+                sbc610_regs = of_iomap(regs, 0);
+                if (sbc610_regs == NULL)
+                        printk(KERN_WARNING "Unable to map board registers\n");
+                of_node_put(regs);
+        }
+}
+
+/* Return the PCB revision */
+static unsigned int gef_sbc610_get_pcb_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread32(sbc610_regs);
+        return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int gef_sbc610_get_board_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread32(sbc610_regs);
+        return (reg >> 16) & 0xff;
 }
 
+/* Return the FPGA revision */
+static unsigned int gef_sbc610_get_fpga_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread32(sbc610_regs);
+        return (reg >> 24) & 0xf;
+}
 
 static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 {
@@ -96,6 +132,10 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 
         seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 
+        seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
+                ('A' + gef_sbc610_get_board_rev() - 1));
+        seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
+
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 }