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-rw-r--r--arch/arm/configs/clps7500_defconfig801
-rw-r--r--arch/arm/include/asm/mmu.h1
-rw-r--r--arch/arm/kernel/isa.c1
-rw-r--r--arch/arm/mach-at91/at91cap9.c1
-rw-r--r--arch/arm/mach-at91/at91rm9200.c1
-rw-r--r--arch/arm/mach-at91/at91sam9260.c1
-rw-r--r--arch/arm/mach-at91/at91sam9261.c1
-rw-r--r--arch/arm/mach-at91/at91sam9263.c1
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c1
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c1
-rw-r--r--arch/arm/mach-clps711x/edb7211-mm.c1
-rw-r--r--arch/arm/mach-clps711x/fortunet.c1
-rw-r--r--arch/arm/mach-davinci/devices.c1
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-footbridge/common.c9
-rw-r--r--arch/arm/mach-footbridge/common.h1
-rw-r--r--arch/arm/mach-footbridge/dc21285.c23
-rw-r--r--arch/arm/mach-footbridge/isa-irq.c2
-rw-r--r--arch/arm/mach-h720x/h7202-eval.c1
-rw-r--r--arch/arm/mach-kirkwood/common.c1
-rw-r--r--arch/arm/mach-kirkwood/pcie.c1
-rw-r--r--arch/arm/mach-ks8695/devices.c1
-rw-r--r--arch/arm/mach-msm/devices.c1
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c1
-rw-r--r--arch/arm/mach-mx2/devices.c1
-rw-r--r--arch/arm/mach-mx3/devices.c1
-rw-r--r--arch/arm/mach-netx/fb.c2
-rw-r--r--arch/arm/mach-netx/time.c2
-rw-r--r--arch/arm/mach-netx/xc.c1
-rw-r--r--arch/arm/mach-omap1/mcbsp.c1
-rw-r--r--arch/arm/mach-omap2/mcbsp.c1
-rw-r--r--arch/arm/mach-orion5x/pci.c1
-rw-r--r--arch/arm/mach-pnx4008/gpio.c1
-rw-r--r--arch/arm/mach-pnx4008/i2c.c1
-rw-r--r--arch/arm/mach-pxa/corgi.c54
-rw-r--r--arch/arm/mach-pxa/e350.c1
-rw-r--r--arch/arm/mach-pxa/e400.c1
-rw-r--r--arch/arm/mach-pxa/e740.c1
-rw-r--r--arch/arm/mach-pxa/e750.c53
-rw-r--r--arch/arm/mach-pxa/e800.c1
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h2
-rw-r--r--arch/arm/mach-pxa/poodle.c51
-rw-r--r--arch/arm/mach-pxa/spitz.c77
-rw-r--r--arch/arm/mach-realview/platsmp.c1
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-s3c2410/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c2
-rw-r--r--arch/arm/mach-s3c6400/include/mach/irqs.h4
-rw-r--r--arch/arm/mm/dma-mapping.c28
-rw-r--r--arch/arm/plat-omap/i2c.c1
-rw-r--r--arch/arm/plat-s3c/dev-fb.c1
-rw-r--r--arch/arm/plat-s3c/dev-i2c0.c1
-rw-r--r--arch/arm/plat-s3c/dev-i2c1.c1
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c18
-rw-r--r--arch/arm/plat-s3c24xx/pwm.c2
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/irqs.h2
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c15
-rw-r--r--arch/blackfin/include/asm/mmu.h1
-rw-r--r--arch/blackfin/kernel/ptrace.c6
-rw-r--r--arch/blackfin/kernel/traps.c11
-rw-r--r--arch/frv/kernel/ptrace.c11
-rw-r--r--arch/h8300/include/asm/mmu.h1
-rw-r--r--arch/ia64/include/asm/acpi-ext.h1
-rw-r--r--arch/ia64/include/asm/irq.h2
-rw-r--r--arch/ia64/include/asm/sn/acpi.h2
-rw-r--r--arch/ia64/include/asm/topology.h2
-rw-r--r--arch/ia64/kernel/acpi.c1
-rw-r--r--arch/ia64/kernel/irq.c15
-rw-r--r--arch/ia64/sn/kernel/io_acpi_init.c103
-rw-r--r--arch/ia64/sn/kernel/io_common.c5
-rw-r--r--arch/m68k/amiga/amiints.c12
-rw-r--r--arch/m68k/amiga/cia.c4
-rw-r--r--arch/m68k/amiga/config.c3
-rw-r--r--arch/m68k/apollo/config.c7
-rw-r--r--arch/m68k/atari/atakeyb.c10
-rw-r--r--arch/m68k/atari/stdma.c5
-rw-r--r--arch/m68k/atari/time.c5
-rw-r--r--arch/m68k/bvme6000/config.c1
-rw-r--r--arch/m68k/hp300/time.c3
-rw-r--r--arch/m68k/kernel/.gitignore1
-rw-r--r--arch/m68k/kernel/entry.S2
-rw-r--r--arch/m68k/kernel/setup.c11
-rw-r--r--arch/m68k/kernel/signal.c15
-rw-r--r--arch/m68k/kernel/vmlinux-sun3.lds1
-rw-r--r--arch/m68k/mac/baboon.c3
-rw-r--r--arch/m68k/mac/config.c12
-rw-r--r--arch/m68k/mac/debug.c1
-rw-r--r--arch/m68k/mac/iop.c10
-rw-r--r--arch/m68k/mac/macints.c15
-rw-r--r--arch/m68k/mac/misc.c1
-rw-r--r--arch/m68k/mac/oss.c25
-rw-r--r--arch/m68k/mac/psc.c12
-rw-r--r--arch/m68k/mac/via.c35
-rw-r--r--arch/m68k/math-emu/fp_log.c1
-rw-r--r--arch/m68k/mm/init.c4
-rw-r--r--arch/m68k/mm/motorola.c7
-rw-r--r--arch/m68k/mvme147/config.c6
-rw-r--r--arch/m68k/mvme16x/config.c1
-rw-r--r--arch/m68k/q40/config.c3
-rw-r--r--arch/m68k/sun3/config.c8
-rw-r--r--arch/m68k/sun3/mmu_emu.c1
-rw-r--r--arch/m68k/sun3/sun3ints.c9
-rw-r--r--arch/m68k/sun3x/config.c1
-rw-r--r--arch/m68knommu/include/asm/mmu.h1
-rw-r--r--arch/mips/Kconfig71
-rw-r--r--arch/mips/Makefile40
-rw-r--r--arch/mips/alchemy/Kconfig5
-rw-r--r--arch/mips/alchemy/common/Makefile4
-rw-r--r--arch/mips/alchemy/common/au1xxx_irqmap.c205
-rw-r--r--arch/mips/alchemy/common/clocks.c65
-rw-r--r--arch/mips/alchemy/common/cputable.c52
-rw-r--r--arch/mips/alchemy/common/dbdma.c65
-rw-r--r--arch/mips/alchemy/common/irq.c745
-rw-r--r--arch/mips/alchemy/common/power.c406
-rw-r--r--arch/mips/alchemy/common/reset.c2
-rw-r--r--arch/mips/alchemy/common/setup.c71
-rw-r--r--arch/mips/alchemy/common/sleeper.S118
-rw-r--r--arch/mips/alchemy/common/time.c311
-rw-r--r--arch/mips/alchemy/db1x00/init.c62
-rw-r--r--arch/mips/alchemy/devboards/Makefile18
-rw-r--r--arch/mips/alchemy/devboards/db1x00/Makefile (renamed from arch/mips/alchemy/db1x00/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c (renamed from arch/mips/alchemy/db1x00/board_setup.c)37
-rw-r--r--arch/mips/alchemy/devboards/db1x00/irqmap.c (renamed from arch/mips/alchemy/db1x00/irqmap.c)24
-rw-r--r--arch/mips/alchemy/devboards/pb1000/Makefile (renamed from arch/mips/alchemy/pb1000/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c (renamed from arch/mips/alchemy/pb1000/board_setup.c)30
-rw-r--r--arch/mips/alchemy/devboards/pb1100/Makefile (renamed from arch/mips/alchemy/pb1100/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1100/board_setup.c (renamed from arch/mips/alchemy/pb1100/board_setup.c)47
-rw-r--r--arch/mips/alchemy/devboards/pb1200/Makefile (renamed from arch/mips/alchemy/pb1200/Makefile)3
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c (renamed from arch/mips/alchemy/pb1200/board_setup.c)34
-rw-r--r--arch/mips/alchemy/devboards/pb1200/irqmap.c (renamed from arch/mips/alchemy/pb1200/irqmap.c)94
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c (renamed from arch/mips/alchemy/pb1200/platform.c)0
-rw-r--r--arch/mips/alchemy/devboards/pb1500/Makefile (renamed from arch/mips/alchemy/pb1500/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c (renamed from arch/mips/alchemy/pb1500/board_setup.c)44
-rw-r--r--arch/mips/alchemy/devboards/pb1550/Makefile (renamed from arch/mips/alchemy/pb1550/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c (renamed from arch/mips/alchemy/pb1550/board_setup.c)34
-rw-r--r--arch/mips/alchemy/devboards/pm.c229
-rw-r--r--arch/mips/alchemy/devboards/prom.c (renamed from arch/mips/alchemy/pb1200/init.c)26
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c12
-rw-r--r--arch/mips/alchemy/mtx-1/init.c2
-rw-r--r--arch/mips/alchemy/mtx-1/irqmap.c18
-rw-r--r--arch/mips/alchemy/pb1000/init.c57
-rw-r--r--arch/mips/alchemy/pb1000/irqmap.c38
-rw-r--r--arch/mips/alchemy/pb1100/init.c60
-rw-r--r--arch/mips/alchemy/pb1100/irqmap.c40
-rw-r--r--arch/mips/alchemy/pb1500/init.c58
-rw-r--r--arch/mips/alchemy/pb1500/irqmap.c46
-rw-r--r--arch/mips/alchemy/pb1550/init.c58
-rw-r--r--arch/mips/alchemy/pb1550/irqmap.c43
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c12
-rw-r--r--arch/mips/alchemy/xxs1500/init.c2
-rw-r--r--arch/mips/alchemy/xxs1500/irqmap.c31
-rw-r--r--arch/mips/cavium-octeon/Kconfig85
-rw-r--r--arch/mips/cavium-octeon/Makefile16
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c58
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c32
-rw-r--r--arch/mips/cavium-octeon/executive/Makefile13
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-bootmem.c586
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c734
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-sysinfo.c116
-rw-r--r--arch/mips/cavium-octeon/executive/octeon-model.c358
-rw-r--r--arch/mips/cavium-octeon/flash_setup.c84
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c497
-rw-r--r--arch/mips/cavium-octeon/octeon-memcpy.S521
-rw-r--r--arch/mips/cavium-octeon/serial.c136
-rw-r--r--arch/mips/cavium-octeon/setup.c929
-rw-r--r--arch/mips/cavium-octeon/smp.c211
-rw-r--r--arch/mips/configs/cavium-octeon_defconfig943
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/cpu.h14
-rw-r--r--arch/mips/include/asm/hazards.h4
-rw-r--r--arch/mips/include/asm/io.h14
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h89
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h5
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h78
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h64
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h244
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h131
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/war.h26
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-lemote/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mipsregs.h22
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-asm.h128
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h262
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h288
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ciu-defs.h1616
-rw-r--r--arch/mips/include/asm/octeon/cvmx-gpio-defs.h219
-rw-r--r--arch/mips/include/asm/octeon/cvmx-iob-defs.h530
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ipd-defs.h877
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c-defs.h963
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h325
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2d-defs.h369
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2t-defs.h141
-rw-r--r--arch/mips/include/asm/octeon/cvmx-led-defs.h240
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mio-defs.h2004
-rw-r--r--arch/mips/include/asm/octeon/cvmx-packet.h61
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow-defs.h698
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spinlock.h232
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sysinfo.h152
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h505
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h119
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h321
-rw-r--r--arch/mips/include/asm/octeon/octeon.h248
-rw-r--r--arch/mips/include/asm/processor.h69
-rw-r--r--arch/mips/include/asm/ptrace.h4
-rw-r--r--arch/mips/include/asm/smp.h3
-rw-r--r--arch/mips/include/asm/stackframe.h17
-rw-r--r--arch/mips/include/asm/time.h24
-rw-r--r--arch/mips/kernel/Makefile5
-rw-r--r--arch/mips/kernel/asm-offsets.c31
-rw-r--r--arch/mips/kernel/branch.c33
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c31
-rw-r--r--arch/mips/kernel/csrc-r4k.c2
-rw-r--r--arch/mips/kernel/genex.S4
-rw-r--r--arch/mips/kernel/irq.c1
-rw-r--r--arch/mips/kernel/octeon_switch.S506
-rw-r--r--arch/mips/kernel/ptrace32.c64
-rw-r--r--arch/mips/kernel/traps.c21
-rw-r--r--arch/mips/lib/Makefile1
-rw-r--r--arch/mips/mm/Makefile1
-rw-r--r--arch/mips/mm/c-octeon.c307
-rw-r--r--arch/mips/mm/cache.c6
-rw-r--r--arch/mips/mm/cex-oct.S70
-rw-r--r--arch/mips/mm/dma-default.c25
-rw-r--r--arch/mips/mm/tlb-r4k.c5
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--arch/parisc/Makefile2
-rw-r--r--arch/parisc/include/asm/Kbuild1
-rw-r--r--arch/parisc/include/asm/byteorder.h77
-rw-r--r--arch/parisc/include/asm/checksum.h2
-rw-r--r--arch/parisc/include/asm/io.h12
-rw-r--r--arch/parisc/include/asm/mmu_context.h13
-rw-r--r--arch/parisc/include/asm/processor.h4
-rw-r--r--arch/parisc/include/asm/swab.h66
-rw-r--r--arch/parisc/include/asm/uaccess.h2
-rw-r--r--arch/parisc/kernel/drivers.c40
-rw-r--r--arch/parisc/kernel/hpmc.S8
-rw-r--r--arch/parisc/kernel/irq.c11
-rw-r--r--arch/parisc/kernel/pdc_cons.c2
-rw-r--r--arch/parisc/kernel/perf.c4
-rw-r--r--arch/parisc/kernel/processor.c68
-rw-r--r--arch/parisc/kernel/setup.c11
-rw-r--r--arch/parisc/kernel/smp.c32
-rw-r--r--arch/parisc/kernel/time.c4
-rw-r--r--arch/parisc/kernel/topology.c4
-rw-r--r--arch/parisc/kernel/traps.c9
-rw-r--r--arch/parisc/kernel/unwind.c2
-rw-r--r--arch/parisc/lib/iomap.c2
-rw-r--r--arch/parisc/lib/memcpy.c2
-rw-r--r--arch/parisc/mm/fault.c58
-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts15
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts2
-rw-r--r--arch/powerpc/configs/86xx/gef_sbc610_defconfig1
-rw-r--r--arch/powerpc/include/asm/cell-pmu.h2
-rw-r--r--arch/powerpc/include/asm/oprofile_impl.h6
-rw-r--r--arch/powerpc/include/asm/qe.h19
-rw-r--r--arch/powerpc/kernel/asm-offsets.c7
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S6
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c9
-rw-r--r--arch/powerpc/mm/mmu_decl.h11
-rw-r--r--arch/powerpc/oprofile/cell/pr_util.h11
-rw-r--r--arch/powerpc/oprofile/cell/spu_profiler.c56
-rw-r--r--arch/powerpc/oprofile/common.c22
-rw-r--r--arch/powerpc/oprofile/op_model_cell.c748
-rw-r--r--arch/powerpc/platforms/cell/cbe_cpufreq.c2
-rw-r--r--arch/powerpc/platforms/cell/cpufreq_spudemand.c4
-rw-r--r--arch/powerpc/platforms/cell/spufs/spufs.h2
-rw-r--r--arch/powerpc/platforms/fsl_uli1575.c1
-rw-r--r--arch/powerpc/platforms/pasemi/cpufreq.c2
-rw-r--r--arch/powerpc/platforms/powermac/cpufreq_64.c2
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c107
-rw-r--r--arch/s390/include/asm/chpid.h2
-rw-r--r--arch/s390/include/asm/chsc.h1
-rw-r--r--arch/s390/include/asm/cmb.h3
-rw-r--r--arch/s390/include/asm/dasd.h2
-rw-r--r--arch/s390/include/asm/kvm.h2
-rw-r--r--arch/s390/include/asm/posix_types.h4
-rw-r--r--arch/s390/include/asm/ptrace.h7
-rw-r--r--arch/s390/include/asm/qeth.h1
-rw-r--r--arch/s390/include/asm/schid.h2
-rw-r--r--arch/s390/include/asm/swab.h2
-rw-r--r--arch/s390/include/asm/types.h6
-rw-r--r--arch/s390/kernel/entry.h2
-rw-r--r--arch/s390/kernel/smp.c3
-rw-r--r--arch/s390/kernel/sys_s390.c19
-rw-r--r--arch/s390/kernel/vdso.c3
-rw-r--r--arch/s390/kernel/vdso32/gettimeofday.S4
-rw-r--r--arch/s390/kvm/diag.c2
-rw-r--r--arch/s390/kvm/interrupt.c6
-rw-r--r--arch/s390/kvm/priv.c2
-rw-r--r--arch/sh/include/asm/mmu.h1
-rw-r--r--arch/sparc/configs/sparc32_defconfig290
-rw-r--r--arch/sparc/include/asm/oplib_32.h11
-rw-r--r--arch/sparc/include/asm/oplib_64.h10
-rw-r--r--arch/sparc/include/asm/signal.h4
-rw-r--r--arch/sparc/include/asm/topology_64.h4
-rw-r--r--arch/sparc/kernel/auxio_32.c3
-rw-r--r--arch/sparc/kernel/auxio_64.c2
-rw-r--r--arch/sparc/kernel/cpu.c2
-rw-r--r--arch/sparc/kernel/idprom.c3
-rw-r--r--arch/sparc/kernel/ioport.c15
-rw-r--r--arch/sparc/kernel/irq_32.c1
-rw-r--r--arch/sparc/kernel/pci.c1
-rw-r--r--arch/sparc/kernel/pcic.c6
-rw-r--r--arch/sparc/kernel/process_32.c2
-rw-r--r--arch/sparc/kernel/process_64.c2
-rw-r--r--arch/sparc/kernel/psycho_common.c60
-rw-r--r--arch/sparc/kernel/sbus.c1
-rw-r--r--arch/sparc/kernel/setup_32.c3
-rw-r--r--arch/sparc/kernel/setup_64.c3
-rw-r--r--arch/sparc/kernel/sparc_ksyms_32.c225
-rw-r--r--arch/sparc/kernel/sparc_ksyms_64.c243
-rw-r--r--arch/sparc/kernel/sun4d_smp.c4
-rw-r--r--arch/sparc/kernel/sun4m_smp.c5
-rw-r--r--arch/sparc/kernel/sys_sparc_64.c2
-rw-r--r--arch/sparc/kernel/time_32.c2
-rw-r--r--arch/sparc/kernel/time_64.c2
-rw-r--r--arch/sparc/kernel/traps_32.c1
-rw-r--r--arch/sparc/kernel/traps_64.c2
-rw-r--r--arch/sparc/kernel/unaligned_64.c8
-rw-r--r--arch/sparc/lib/Makefile1
-rw-r--r--arch/sparc/lib/PeeCeeI.c8
-rw-r--r--arch/sparc/lib/ksyms.c196
-rw-r--r--arch/sparc/lib/user_fixup.c5
-rw-r--r--arch/sparc/mm/generic_32.c1
-rw-r--r--arch/sparc/mm/generic_64.c1
-rw-r--r--arch/sparc/mm/highmem.c2
-rw-r--r--arch/sparc/mm/init_32.c6
-rw-r--r--arch/sparc/mm/init_64.c4
-rw-r--r--arch/sparc/prom/init_32.c4
-rw-r--r--arch/sparc/prom/misc_32.c3
-rw-r--r--arch/sparc/prom/misc_64.c3
-rw-r--r--arch/sparc/prom/ranges.c3
-rw-r--r--arch/sparc/prom/tree_32.c17
-rw-r--r--arch/sparc/prom/tree_64.c18
-rw-r--r--arch/x86/Kconfig1
-rw-r--r--arch/x86/include/asm/bitops.h2
-rw-r--r--arch/x86/include/asm/es7000/apic.h2
-rw-r--r--arch/x86/include/asm/es7000/mpparse.h3
-rw-r--r--arch/x86/include/asm/genapic_32.h8
-rw-r--r--arch/x86/include/asm/mach-default/mach_mpparse.h4
-rw-r--r--arch/x86/include/asm/mach-default/mach_wakecpu.h6
-rw-r--r--arch/x86/include/asm/mach-generic/mach_mpparse.h5
-rw-r--r--arch/x86/include/asm/mach-generic/mach_mpspec.h4
-rw-r--r--arch/x86/include/asm/mpspec_def.h102
-rw-r--r--arch/x86/include/asm/mtrr.h10
-rw-r--r--arch/x86/include/asm/numaq/mpparse.h3
-rw-r--r--arch/x86/include/asm/setup.h14
-rw-r--r--arch/x86/include/asm/smp.h32
-rw-r--r--arch/x86/include/asm/summit/apic.h1
-rw-r--r--arch/x86/include/asm/summit/mpparse.h2
-rw-r--r--arch/x86/kernel/acpi/boot.c17
-rw-r--r--arch/x86/kernel/acpi/cstate.c74
-rw-r--r--arch/x86/kernel/acpi/sleep.c2
-rw-r--r--arch/x86/kernel/apic.c15
-rw-r--r--arch/x86/kernel/apm_32.c4
-rw-r--r--arch/x86/kernel/cpu/common.c26
-rw-r--r--arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c149
-rw-r--r--arch/x86/kernel/cpu/cpufreq/longhaul.c2
-rw-r--r--arch/x86/kernel/cpu/cpufreq/p4-clockmod.c8
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.c6
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.h2
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c35
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-ich.c18
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_32.c2
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd_64.c2
-rw-r--r--arch/x86/kernel/cpu/mcheck/p5.c2
-rw-r--r--arch/x86/kernel/cpu/mcheck/p6.c2
-rw-r--r--arch/x86/kernel/cpu/mcheck/winchip.c2
-rw-r--r--arch/x86/kernel/e820.c21
-rw-r--r--arch/x86/kernel/early-quirks.c22
-rw-r--r--arch/x86/kernel/head_64.S2
-rw-r--r--arch/x86/kernel/i8259.c8
-rw-r--r--arch/x86/kernel/io_apic.c2
-rw-r--r--arch/x86/kernel/ioport.c4
-rw-r--r--arch/x86/kernel/irq.c2
-rw-r--r--arch/x86/kernel/irq_32.c10
-rw-r--r--arch/x86/kernel/irq_64.c22
-rw-r--r--arch/x86/kernel/irqinit_32.c12
-rw-r--r--arch/x86/kernel/irqinit_64.c8
-rw-r--r--arch/x86/kernel/mpparse.c351
-rw-r--r--arch/x86/kernel/nmi.c1
-rw-r--r--arch/x86/kernel/numaq_32.c38
-rw-r--r--arch/x86/kernel/process_32.c19
-rw-r--r--arch/x86/kernel/setup_percpu.c36
-rw-r--r--arch/x86/kernel/smp.c19
-rw-r--r--arch/x86/kernel/smpboot.c130
-rw-r--r--arch/x86/kernel/time_32.c4
-rw-r--r--arch/x86/kernel/time_64.c2
-rw-r--r--arch/x86/kernel/traps.c3
-rw-r--r--arch/x86/kernel/visws_quirks.c32
-rw-r--r--arch/x86/mach-generic/es7000.c10
-rw-r--r--arch/x86/mach-generic/numaq.c3
-rw-r--r--arch/x86/mach-generic/probe.c3
-rw-r--r--arch/x86/mm/fault.c2
-rw-r--r--arch/x86/mm/k8topology_64.c20
-rw-r--r--arch/x86/oprofile/op_model_amd.c149
404 files changed, 22000 insertions, 4837 deletions
diff --git a/arch/arm/configs/clps7500_defconfig b/arch/arm/configs/clps7500_defconfig
deleted file mode 100644
index 49e9f9d8b3d1..000000000000
--- a/arch/arm/configs/clps7500_defconfig
+++ /dev/null
@@ -1,801 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2
4# Sun Mar 27 17:20:48 2005
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y
19
20#
21# General setup
22#
23CONFIG_LOCALVERSION=""
24CONFIG_SWAP=y
25CONFIG_SYSVIPC=y
26# CONFIG_POSIX_MQUEUE is not set
27# CONFIG_BSD_PROCESS_ACCT is not set
28# CONFIG_SYSCTL is not set
29# CONFIG_AUDIT is not set
30# CONFIG_HOTPLUG is not set
31CONFIG_KOBJECT_UEVENT=y
32# CONFIG_IKCONFIG is not set
33CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_BASE_FULL=y
37CONFIG_FUTEX=y
38CONFIG_EPOLL=y
39CONFIG_CC_OPTIMIZE_FOR_SIZE=y
40CONFIG_SHMEM=y
41CONFIG_CC_ALIGN_FUNCTIONS=0
42CONFIG_CC_ALIGN_LABELS=0
43CONFIG_CC_ALIGN_LOOPS=0
44CONFIG_CC_ALIGN_JUMPS=0
45# CONFIG_TINY_SHMEM is not set
46CONFIG_BASE_SMALL=0
47
48#
49# Loadable module support
50#
51# CONFIG_MODULES is not set
52
53#
54# System Type
55#
56CONFIG_ARCH_CLPS7500=y
57# CONFIG_ARCH_CLPS711X is not set
58# CONFIG_ARCH_CO285 is not set
59# CONFIG_ARCH_EBSA110 is not set
60# CONFIG_ARCH_FOOTBRIDGE is not set
61# CONFIG_ARCH_INTEGRATOR is not set
62# CONFIG_ARCH_IOP3XX is not set
63# CONFIG_ARCH_IXP4XX is not set
64# CONFIG_ARCH_IXP2000 is not set
65# CONFIG_ARCH_L7200 is not set
66# CONFIG_ARCH_PXA is not set
67# CONFIG_ARCH_RPC is not set
68# CONFIG_ARCH_SA1100 is not set
69# CONFIG_ARCH_S3C2410 is not set
70# CONFIG_ARCH_SHARK is not set
71# CONFIG_ARCH_LH7A40X is not set
72# CONFIG_ARCH_OMAP is not set
73# CONFIG_ARCH_VERSATILE is not set
74# CONFIG_ARCH_IMX is not set
75# CONFIG_ARCH_H720X is not set
76
77#
78# Processor Type
79#
80CONFIG_CPU_32=y
81CONFIG_CPU_ARM710=y
82CONFIG_CPU_32v3=y
83CONFIG_CPU_CACHE_V3=y
84CONFIG_CPU_CACHE_VIVT=y
85CONFIG_CPU_COPY_V3=y
86CONFIG_CPU_TLB_V3=y
87
88#
89# Processor Features
90#
91CONFIG_TIMER_ACORN=y
92
93#
94# Bus support
95#
96CONFIG_ISA=y
97
98#
99# PCCARD (PCMCIA/CardBus) support
100#
101# CONFIG_PCCARD is not set
102
103#
104# Kernel Features
105#
106# CONFIG_PREEMPT is not set
107CONFIG_ALIGNMENT_TRAP=y
108
109#
110# Boot options
111#
112CONFIG_ZBOOT_ROM_TEXT=0x0
113CONFIG_ZBOOT_ROM_BSS=0x0
114CONFIG_CMDLINE="mem=16M root=nfs"
115# CONFIG_XIP_KERNEL is not set
116
117#
118# Floating point emulation
119#
120
121#
122# At least one emulation must be selected
123#
124# CONFIG_FPE_NWFPE is not set
125
126#
127# Userspace binary formats
128#
129CONFIG_BINFMT_ELF=y
130# CONFIG_BINFMT_AOUT is not set
131# CONFIG_BINFMT_MISC is not set
132# CONFIG_ARTHUR is not set
133
134#
135# Power management options
136#
137# CONFIG_PM is not set
138
139#
140# Device Drivers
141#
142
143#
144# Generic Driver Options
145#
146CONFIG_STANDALONE=y
147CONFIG_PREVENT_FIRMWARE_BUILD=y
148# CONFIG_FW_LOADER is not set
149
150#
151# Memory Technology Devices (MTD)
152#
153CONFIG_MTD=y
154# CONFIG_MTD_DEBUG is not set
155# CONFIG_MTD_CONCAT is not set
156# CONFIG_MTD_PARTITIONS is not set
157
158#
159# User Modules And Translation Layers
160#
161# CONFIG_MTD_CHAR is not set
162# CONFIG_MTD_BLOCK is not set
163# CONFIG_MTD_BLOCK_RO is not set
164# CONFIG_FTL is not set
165# CONFIG_NFTL is not set
166# CONFIG_INFTL is not set
167
168#
169# RAM/ROM/Flash chip drivers
170#
171# CONFIG_MTD_CFI is not set
172# CONFIG_MTD_JEDECPROBE is not set
173CONFIG_MTD_MAP_BANK_WIDTH_1=y
174CONFIG_MTD_MAP_BANK_WIDTH_2=y
175CONFIG_MTD_MAP_BANK_WIDTH_4=y
176# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
177# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
178# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
179CONFIG_MTD_CFI_I1=y
180CONFIG_MTD_CFI_I2=y
181# CONFIG_MTD_CFI_I4 is not set
182# CONFIG_MTD_CFI_I8 is not set
183# CONFIG_MTD_RAM is not set
184# CONFIG_MTD_ROM is not set
185# CONFIG_MTD_ABSENT is not set
186
187#
188# Mapping drivers for chip access
189#
190# CONFIG_MTD_COMPLEX_MAPPINGS is not set
191
192#
193# Self-contained MTD device drivers
194#
195# CONFIG_MTD_SLRAM is not set
196# CONFIG_MTD_PHRAM is not set
197# CONFIG_MTD_MTDRAM is not set
198# CONFIG_MTD_BLKMTD is not set
199# CONFIG_MTD_BLOCK2MTD is not set
200
201#
202# Disk-On-Chip Device Drivers
203#
204# CONFIG_MTD_DOC2000 is not set
205# CONFIG_MTD_DOC2001 is not set
206# CONFIG_MTD_DOC2001PLUS is not set
207
208#
209# NAND Flash Device Drivers
210#
211# CONFIG_MTD_NAND is not set
212
213#
214# Parallel port support
215#
216CONFIG_PARPORT=y
217CONFIG_PARPORT_PC=y
218CONFIG_PARPORT_PC_FIFO=y
219# CONFIG_PARPORT_PC_SUPERIO is not set
220# CONFIG_PARPORT_ARC is not set
221# CONFIG_PARPORT_GSC is not set
222CONFIG_PARPORT_1284=y
223
224#
225# Plug and Play support
226#
227# CONFIG_PNP is not set
228
229#
230# Block devices
231#
232# CONFIG_BLK_DEV_FD is not set
233# CONFIG_BLK_DEV_XD is not set
234# CONFIG_PARIDE is not set
235# CONFIG_BLK_DEV_COW_COMMON is not set
236# CONFIG_BLK_DEV_LOOP is not set
237CONFIG_BLK_DEV_NBD=y
238CONFIG_BLK_DEV_RAM=y
239CONFIG_BLK_DEV_RAM_COUNT=16
240CONFIG_BLK_DEV_RAM_SIZE=4096
241# CONFIG_BLK_DEV_INITRD is not set
242CONFIG_INITRAMFS_SOURCE=""
243# CONFIG_CDROM_PKTCDVD is not set
244
245#
246# IO Schedulers
247#
248CONFIG_IOSCHED_NOOP=y
249CONFIG_IOSCHED_AS=y
250CONFIG_IOSCHED_DEADLINE=y
251CONFIG_IOSCHED_CFQ=y
252# CONFIG_ATA_OVER_ETH is not set
253
254#
255# ATA/ATAPI/MFM/RLL support
256#
257# CONFIG_IDE is not set
258
259#
260# SCSI device support
261#
262# CONFIG_SCSI is not set
263
264#
265# Multi-device support (RAID and LVM)
266#
267# CONFIG_MD is not set
268
269#
270# Fusion MPT device support
271#
272
273#
274# IEEE 1394 (FireWire) support
275#
276
277#
278# I2O device support
279#
280
281#
282# Networking support
283#
284CONFIG_NET=y
285
286#
287# Networking options
288#
289# CONFIG_PACKET is not set
290# CONFIG_NETLINK_DEV is not set
291CONFIG_UNIX=y
292# CONFIG_NET_KEY is not set
293CONFIG_INET=y
294# CONFIG_IP_MULTICAST is not set
295# CONFIG_IP_ADVANCED_ROUTER is not set
296CONFIG_IP_PNP=y
297# CONFIG_IP_PNP_DHCP is not set
298CONFIG_IP_PNP_BOOTP=y
299# CONFIG_IP_PNP_RARP is not set
300# CONFIG_NET_IPIP is not set
301# CONFIG_NET_IPGRE is not set
302# CONFIG_ARPD is not set
303# CONFIG_SYN_COOKIES is not set
304# CONFIG_INET_AH is not set
305# CONFIG_INET_ESP is not set
306# CONFIG_INET_IPCOMP is not set
307# CONFIG_INET_TUNNEL is not set
308CONFIG_IP_TCPDIAG=y
309# CONFIG_IP_TCPDIAG_IPV6 is not set
310# CONFIG_IPV6 is not set
311# CONFIG_NETFILTER is not set
312
313#
314# SCTP Configuration (EXPERIMENTAL)
315#
316# CONFIG_IP_SCTP is not set
317# CONFIG_ATM is not set
318# CONFIG_BRIDGE is not set
319# CONFIG_VLAN_8021Q is not set
320# CONFIG_DECNET is not set
321# CONFIG_LLC2 is not set
322# CONFIG_IPX is not set
323# CONFIG_ATALK is not set
324# CONFIG_X25 is not set
325# CONFIG_LAPB is not set
326# CONFIG_NET_DIVERT is not set
327# CONFIG_ECONET is not set
328# CONFIG_WAN_ROUTER is not set
329
330#
331# QoS and/or fair queueing
332#
333# CONFIG_NET_SCHED is not set
334# CONFIG_NET_CLS_ROUTE is not set
335
336#
337# Network testing
338#
339# CONFIG_NET_PKTGEN is not set
340# CONFIG_NETPOLL is not set
341# CONFIG_NET_POLL_CONTROLLER is not set
342# CONFIG_HAMRADIO is not set
343# CONFIG_IRDA is not set
344# CONFIG_BT is not set
345CONFIG_NETDEVICES=y
346CONFIG_DUMMY=y
347# CONFIG_BONDING is not set
348# CONFIG_EQUALIZER is not set
349# CONFIG_TUN is not set
350
351#
352# ARCnet devices
353#
354# CONFIG_ARCNET is not set
355
356#
357# Ethernet (10 or 100Mbit)
358#
359CONFIG_NET_ETHERNET=y
360# CONFIG_MII is not set
361# CONFIG_NET_VENDOR_3COM is not set
362# CONFIG_LANCE is not set
363# CONFIG_NET_VENDOR_SMC is not set
364# CONFIG_SMC91X is not set
365# CONFIG_NET_VENDOR_RACAL is not set
366# CONFIG_AT1700 is not set
367# CONFIG_DEPCA is not set
368# CONFIG_HP100 is not set
369# CONFIG_NET_ISA is not set
370CONFIG_NET_PCI=y
371# CONFIG_AC3200 is not set
372# CONFIG_APRICOT is not set
373CONFIG_CS89x0=y
374# CONFIG_NET_POCKET is not set
375
376#
377# Ethernet (1000 Mbit)
378#
379
380#
381# Ethernet (10000 Mbit)
382#
383
384#
385# Token Ring devices
386#
387# CONFIG_TR is not set
388
389#
390# Wireless LAN (non-hamradio)
391#
392# CONFIG_NET_RADIO is not set
393
394#
395# Wan interfaces
396#
397# CONFIG_WAN is not set
398# CONFIG_PLIP is not set
399CONFIG_PPP=y
400# CONFIG_PPP_MULTILINK is not set
401# CONFIG_PPP_FILTER is not set
402# CONFIG_PPP_ASYNC is not set
403# CONFIG_PPP_SYNC_TTY is not set
404# CONFIG_PPP_DEFLATE is not set
405# CONFIG_PPP_BSDCOMP is not set
406# CONFIG_PPPOE is not set
407CONFIG_SLIP=y
408CONFIG_SLIP_COMPRESSED=y
409# CONFIG_SLIP_SMART is not set
410# CONFIG_SLIP_MODE_SLIP6 is not set
411# CONFIG_SHAPER is not set
412# CONFIG_NETCONSOLE is not set
413
414#
415# ISDN subsystem
416#
417# CONFIG_ISDN is not set
418
419#
420# Input device support
421#
422CONFIG_INPUT=y
423
424#
425# Userland interfaces
426#
427CONFIG_INPUT_MOUSEDEV=y
428CONFIG_INPUT_MOUSEDEV_PSAUX=y
429CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
430CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
431# CONFIG_INPUT_JOYDEV is not set
432# CONFIG_INPUT_TSDEV is not set
433# CONFIG_INPUT_EVDEV is not set
434# CONFIG_INPUT_EVBUG is not set
435
436#
437# Input Device Drivers
438#
439CONFIG_INPUT_KEYBOARD=y
440CONFIG_KEYBOARD_ATKBD=y
441# CONFIG_KEYBOARD_SUNKBD is not set
442# CONFIG_KEYBOARD_LKKBD is not set
443# CONFIG_KEYBOARD_XTKBD is not set
444# CONFIG_KEYBOARD_NEWTON is not set
445CONFIG_INPUT_MOUSE=y
446CONFIG_MOUSE_PS2=y
447# CONFIG_MOUSE_SERIAL is not set
448# CONFIG_MOUSE_INPORT is not set
449# CONFIG_MOUSE_LOGIBM is not set
450# CONFIG_MOUSE_PC110PAD is not set
451# CONFIG_MOUSE_VSXXXAA is not set
452# CONFIG_INPUT_JOYSTICK is not set
453# CONFIG_INPUT_TOUCHSCREEN is not set
454# CONFIG_INPUT_MISC is not set
455
456#
457# Hardware I/O ports
458#
459CONFIG_SERIO=y
460# CONFIG_SERIO_SERPORT is not set
461# CONFIG_SERIO_PARKBD is not set
462CONFIG_SERIO_RPCKBD=y
463CONFIG_SERIO_LIBPS2=y
464# CONFIG_SERIO_RAW is not set
465# CONFIG_GAMEPORT is not set
466CONFIG_SOUND_GAMEPORT=y
467
468#
469# Character devices
470#
471CONFIG_VT=y
472CONFIG_VT_CONSOLE=y
473CONFIG_HW_CONSOLE=y
474# CONFIG_SERIAL_NONSTANDARD is not set
475
476#
477# Serial drivers
478#
479CONFIG_SERIAL_8250=y
480CONFIG_SERIAL_8250_CONSOLE=y
481CONFIG_SERIAL_8250_NR_UARTS=4
482# CONFIG_SERIAL_8250_EXTENDED is not set
483
484#
485# Non-8250 serial port support
486#
487CONFIG_SERIAL_CORE=y
488CONFIG_SERIAL_CORE_CONSOLE=y
489CONFIG_UNIX98_PTYS=y
490CONFIG_LEGACY_PTYS=y
491CONFIG_LEGACY_PTY_COUNT=256
492CONFIG_PRINTER=y
493# CONFIG_LP_CONSOLE is not set
494# CONFIG_PPDEV is not set
495# CONFIG_TIPAR is not set
496
497#
498# IPMI
499#
500# CONFIG_IPMI_HANDLER is not set
501
502#
503# Watchdog Cards
504#
505# CONFIG_WATCHDOG is not set
506# CONFIG_NVRAM is not set
507# CONFIG_RTC is not set
508# CONFIG_DTLK is not set
509# CONFIG_R3964 is not set
510
511#
512# Ftape, the floppy tape device driver
513#
514# CONFIG_DRM is not set
515# CONFIG_RAW_DRIVER is not set
516
517#
518# TPM devices
519#
520# CONFIG_TCG_TPM is not set
521
522#
523# I2C support
524#
525CONFIG_I2C=y
526# CONFIG_I2C_CHARDEV is not set
527
528#
529# I2C Algorithms
530#
531CONFIG_I2C_ALGOBIT=y
532# CONFIG_I2C_ALGOPCF is not set
533# CONFIG_I2C_ALGOPCA is not set
534
535#
536# I2C Hardware Bus support
537#
538# CONFIG_I2C_ELEKTOR is not set
539# CONFIG_I2C_PARPORT is not set
540# CONFIG_I2C_PARPORT_LIGHT is not set
541# CONFIG_I2C_PCA_ISA is not set
542
543#
544# Hardware Sensors Chip support
545#
546# CONFIG_I2C_SENSOR is not set
547# CONFIG_SENSORS_ADM1021 is not set
548# CONFIG_SENSORS_ADM1025 is not set
549# CONFIG_SENSORS_ADM1026 is not set
550# CONFIG_SENSORS_ADM1031 is not set
551# CONFIG_SENSORS_ASB100 is not set
552# CONFIG_SENSORS_DS1621 is not set
553# CONFIG_SENSORS_FSCHER is not set
554# CONFIG_SENSORS_FSCPOS is not set
555# CONFIG_SENSORS_GL518SM is not set
556# CONFIG_SENSORS_GL520SM is not set
557# CONFIG_SENSORS_IT87 is not set
558# CONFIG_SENSORS_LM63 is not set
559# CONFIG_SENSORS_LM75 is not set
560# CONFIG_SENSORS_LM77 is not set
561# CONFIG_SENSORS_LM78 is not set
562# CONFIG_SENSORS_LM80 is not set
563# CONFIG_SENSORS_LM83 is not set
564# CONFIG_SENSORS_LM85 is not set
565# CONFIG_SENSORS_LM87 is not set
566# CONFIG_SENSORS_LM90 is not set
567# CONFIG_SENSORS_MAX1619 is not set
568# CONFIG_SENSORS_PC87360 is not set
569# CONFIG_SENSORS_SMSC47B397 is not set
570# CONFIG_SENSORS_SMSC47M1 is not set
571# CONFIG_SENSORS_W83781D is not set
572# CONFIG_SENSORS_W83L785TS is not set
573# CONFIG_SENSORS_W83627HF is not set
574
575#
576# Other I2C Chip support
577#
578# CONFIG_SENSORS_EEPROM is not set
579# CONFIG_SENSORS_PCF8574 is not set
580# CONFIG_SENSORS_PCF8591 is not set
581# CONFIG_SENSORS_RTC8564 is not set
582# CONFIG_I2C_DEBUG_CORE is not set
583# CONFIG_I2C_DEBUG_ALGO is not set
584# CONFIG_I2C_DEBUG_BUS is not set
585# CONFIG_I2C_DEBUG_CHIP is not set
586
587#
588# Misc devices
589#
590
591#
592# Multimedia devices
593#
594# CONFIG_VIDEO_DEV is not set
595
596#
597# Digital Video Broadcasting Devices
598#
599# CONFIG_DVB is not set
600
601#
602# Graphics support
603#
604CONFIG_FB=y
605CONFIG_FB_CFB_FILLRECT=y
606CONFIG_FB_CFB_COPYAREA=y
607CONFIG_FB_CFB_IMAGEBLIT=y
608CONFIG_FB_SOFT_CURSOR=y
609# CONFIG_FB_MODE_HELPERS is not set
610# CONFIG_FB_TILEBLITTING is not set
611CONFIG_FB_ACORN=y
612# CONFIG_FB_VIRTUAL is not set
613
614#
615# Console display driver support
616#
617# CONFIG_VGA_CONSOLE is not set
618# CONFIG_MDA_CONSOLE is not set
619CONFIG_DUMMY_CONSOLE=y
620CONFIG_FRAMEBUFFER_CONSOLE=y
621CONFIG_FONTS=y
622CONFIG_FONT_8x8=y
623CONFIG_FONT_8x16=y
624# CONFIG_FONT_6x11 is not set
625# CONFIG_FONT_PEARL_8x8 is not set
626# CONFIG_FONT_ACORN_8x8 is not set
627# CONFIG_FONT_MINI_4x6 is not set
628# CONFIG_FONT_SUN8x16 is not set
629# CONFIG_FONT_SUN12x22 is not set
630
631#
632# Logo configuration
633#
634CONFIG_LOGO=y
635CONFIG_LOGO_LINUX_MONO=y
636CONFIG_LOGO_LINUX_VGA16=y
637CONFIG_LOGO_LINUX_CLUT224=y
638# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
639
640#
641# Sound
642#
643# CONFIG_SOUND is not set
644
645#
646# USB support
647#
648CONFIG_USB_ARCH_HAS_HCD=y
649# CONFIG_USB_ARCH_HAS_OHCI is not set
650# CONFIG_USB is not set
651
652#
653# USB Gadget Support
654#
655# CONFIG_USB_GADGET is not set
656
657#
658# MMC/SD Card support
659#
660# CONFIG_MMC is not set
661
662#
663# File systems
664#
665CONFIG_EXT2_FS=y
666# CONFIG_EXT2_FS_XATTR is not set
667# CONFIG_EXT3_FS is not set
668# CONFIG_JBD is not set
669# CONFIG_REISERFS_FS is not set
670# CONFIG_JFS_FS is not set
671
672#
673# XFS support
674#
675# CONFIG_XFS_FS is not set
676CONFIG_MINIX_FS=y
677# CONFIG_ROMFS_FS is not set
678# CONFIG_QUOTA is not set
679CONFIG_DNOTIFY=y
680# CONFIG_AUTOFS_FS is not set
681# CONFIG_AUTOFS4_FS is not set
682
683#
684# CD-ROM/DVD Filesystems
685#
686# CONFIG_ISO9660_FS is not set
687# CONFIG_UDF_FS is not set
688
689#
690# DOS/FAT/NT Filesystems
691#
692# CONFIG_MSDOS_FS is not set
693# CONFIG_VFAT_FS is not set
694# CONFIG_NTFS_FS is not set
695
696#
697# Pseudo filesystems
698#
699CONFIG_PROC_FS=y
700CONFIG_SYSFS=y
701# CONFIG_DEVFS_FS is not set
702# CONFIG_DEVPTS_FS_XATTR is not set
703# CONFIG_TMPFS is not set
704# CONFIG_HUGETLB_PAGE is not set
705CONFIG_RAMFS=y
706
707#
708# Miscellaneous filesystems
709#
710# CONFIG_ADFS_FS is not set
711# CONFIG_AFFS_FS is not set
712# CONFIG_HFS_FS is not set
713# CONFIG_HFSPLUS_FS is not set
714# CONFIG_BEFS_FS is not set
715# CONFIG_BFS_FS is not set
716# CONFIG_EFS_FS is not set
717# CONFIG_JFFS_FS is not set
718# CONFIG_JFFS2_FS is not set
719# CONFIG_CRAMFS is not set
720# CONFIG_VXFS_FS is not set
721# CONFIG_HPFS_FS is not set
722# CONFIG_QNX4FS_FS is not set
723# CONFIG_SYSV_FS is not set
724# CONFIG_UFS_FS is not set
725
726#
727# Network File Systems
728#
729CONFIG_NFS_FS=y
730# CONFIG_NFS_V3 is not set
731# CONFIG_NFS_V4 is not set
732# CONFIG_NFS_DIRECTIO is not set
733# CONFIG_NFSD is not set
734CONFIG_ROOT_NFS=y
735CONFIG_LOCKD=y
736CONFIG_SUNRPC=y
737# CONFIG_RPCSEC_GSS_KRB5 is not set
738# CONFIG_RPCSEC_GSS_SPKM3 is not set
739# CONFIG_SMB_FS is not set
740# CONFIG_CIFS is not set
741# CONFIG_NCP_FS is not set
742# CONFIG_CODA_FS is not set
743# CONFIG_AFS_FS is not set
744
745#
746# Partition Types
747#
748CONFIG_PARTITION_ADVANCED=y
749# CONFIG_ACORN_PARTITION is not set
750# CONFIG_OSF_PARTITION is not set
751# CONFIG_AMIGA_PARTITION is not set
752# CONFIG_ATARI_PARTITION is not set
753# CONFIG_MAC_PARTITION is not set
754# CONFIG_MSDOS_PARTITION is not set
755# CONFIG_LDM_PARTITION is not set
756# CONFIG_SGI_PARTITION is not set
757# CONFIG_ULTRIX_PARTITION is not set
758# CONFIG_SUN_PARTITION is not set
759# CONFIG_EFI_PARTITION is not set
760
761#
762# Native Language Support
763#
764# CONFIG_NLS is not set
765
766#
767# Profiling support
768#
769# CONFIG_PROFILING is not set
770
771#
772# Kernel hacking
773#
774# CONFIG_PRINTK_TIME is not set
775# CONFIG_DEBUG_KERNEL is not set
776CONFIG_LOG_BUF_SHIFT=14
777# CONFIG_DEBUG_BUGVERBOSE is not set
778CONFIG_FRAME_POINTER=y
779# CONFIG_DEBUG_USER is not set
780
781#
782# Security options
783#
784# CONFIG_KEYS is not set
785# CONFIG_SECURITY is not set
786
787#
788# Cryptographic options
789#
790# CONFIG_CRYPTO is not set
791
792#
793# Hardware crypto devices
794#
795
796#
797# Library routines
798#
799# CONFIG_CRC_CCITT is not set
800CONFIG_CRC32=y
801# CONFIG_LIBCRC32C is not set
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 53099d4ee421..b561584d04a1 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -24,7 +24,6 @@ typedef struct {
24 * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com> 24 * modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
25 */ 25 */
26typedef struct { 26typedef struct {
27 struct vm_list_struct *vmlist;
28 unsigned long end_brk; 27 unsigned long end_brk;
29} mm_context_t; 28} mm_context_t;
30 29
diff --git a/arch/arm/kernel/isa.c b/arch/arm/kernel/isa.c
index 50a30bc91872..8ac9b8424007 100644
--- a/arch/arm/kernel/isa.c
+++ b/arch/arm/kernel/isa.c
@@ -16,6 +16,7 @@
16#include <linux/fs.h> 16#include <linux/fs.h>
17#include <linux/sysctl.h> 17#include <linux/sysctl.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/io.h>
19 20
20static unsigned int isa_membase, isa_portbase, isa_portshift; 21static unsigned int isa_membase, isa_portbase, isa_portshift;
21 22
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 0a38c69fdbc4..73376170fb91 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -15,6 +15,7 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/pm.h> 16#include <linux/pm.h>
17 17
18#include <asm/irq.h>
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
19#include <asm/mach/map.h> 20#include <asm/mach/map.h>
20 21
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 28594fcc88e3..2e9ecad97f3d 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14 14
15#include <asm/irq.h>
15#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
17#include <mach/at91rm9200.h> 18#include <mach/at91rm9200.h>
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index accb69ec478e..0894f1077be7 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -13,6 +13,7 @@
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/pm.h> 14#include <linux/pm.h>
15 15
16#include <asm/irq.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
18#include <mach/cpu.h> 19#include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 7b51a59ae8b3..3acd7d7e6a42 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -13,6 +13,7 @@
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/pm.h> 14#include <linux/pm.h>
15 15
16#include <asm/irq.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
18#include <mach/at91sam9261.h> 19#include <mach/at91sam9261.h>
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index ada4b6769107..942792d630d8 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -13,6 +13,7 @@
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/pm.h> 14#include <linux/pm.h>
15 15
16#include <asm/irq.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
18#include <mach/at91sam9263.h> 19#include <mach/at91sam9263.h>
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 252e954b49fd..211c5c14a1e6 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -12,6 +12,7 @@
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/pm.h> 13#include <linux/pm.h>
14 14
15#include <asm/irq.h>
15#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
17#include <mach/cpu.h> 18#include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 9b937ee4815a..35e12a49d1a6 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -29,6 +29,7 @@
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/board.h> 30#include <mach/board.h>
31#include <mach/gpio.h> 31#include <mach/gpio.h>
32#include <mach/at91sam9_smc.h>
32#include <mach/at91_shdwc.h> 33#include <mach/at91_shdwc.h>
33 34
34#include "sam9_smc.h" 35#include "sam9_smc.h"
diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
index c58e32ec4c5d..0bea1454ae03 100644
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ b/arch/arm/mach-clps711x/edb7211-mm.c
@@ -24,7 +24,6 @@
24 24
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <asm/page.h> 26#include <asm/page.h>
27#include <asm/pgtable.h>
28#include <asm/sizes.h> 27#include <asm/sizes.h>
29 28
30#include <asm/mach/map.h> 29#include <asm/mach/map.h>
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 7122b3d21043..7430e4049d87 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -24,7 +24,6 @@
24#include <linux/initrd.h> 24#include <linux/initrd.h>
25 25
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <asm/irq.h>
28#include <asm/setup.h> 27#include <asm/setup.h>
29#include <asm/mach-types.h> 28#include <asm/mach-types.h>
30 29
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3d4b1de8f898..808633f9f03c 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -20,6 +20,7 @@
20 20
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/i2c.h> 22#include <mach/i2c.h>
23#include <mach/irqs.h>
23 24
24static struct resource i2c_resources[] = { 25static struct resource i2c_resources[] = {
25 { 26 {
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index b3a2961f0f46..b456f079f43f 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <asm-generic/gpio.h> 17#include <asm-generic/gpio.h>
18#include <mach/hardware.h> 18#include <mach/hardware.h>
19#include <mach/irqs.h>
19 20
20/* 21/*
21 * basic gpio routines 22 * basic gpio routines
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 36ff06d4df15..b97f529e58e8 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -28,12 +28,17 @@
28 28
29#include "common.h" 29#include "common.h"
30 30
31extern void __init isa_init_irq(unsigned int irq);
32
33unsigned int mem_fclk_21285 = 50000000; 31unsigned int mem_fclk_21285 = 50000000;
34 32
35EXPORT_SYMBOL(mem_fclk_21285); 33EXPORT_SYMBOL(mem_fclk_21285);
36 34
35static void __init early_fclk(char **arg)
36{
37 mem_fclk_21285 = simple_strtoul(*arg, arg, 0);
38}
39
40__early_param("mem_fclk_21285=", early_fclk);
41
37static int __init parse_tag_memclk(const struct tag *tag) 42static int __init parse_tag_memclk(const struct tag *tag)
38{ 43{
39 mem_fclk_21285 = tag->u.memclk.fmemclk; 44 mem_fclk_21285 = tag->u.memclk.fmemclk;
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index 580e31bbc711..b05e662d21ad 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -7,3 +7,4 @@ extern void isa_rtc_init(void);
7extern void footbridge_map_io(void); 7extern void footbridge_map_io(void);
8extern void footbridge_init_irq(void); 8extern void footbridge_init_irq(void);
9 9
10extern void isa_init_irq(unsigned int irq);
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 133086019e3e..3ffa54841ec5 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -287,6 +287,9 @@ struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
287 return pci_scan_bus(0, &dc21285_ops, sys); 287 return pci_scan_bus(0, &dc21285_ops, sys);
288} 288}
289 289
290#define dc21285_request_irq(_a, _b, _c, _d, _e) \
291 WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
292
290void __init dc21285_preinit(void) 293void __init dc21285_preinit(void)
291{ 294{
292 unsigned int mem_size, mem_mask; 295 unsigned int mem_size, mem_mask;
@@ -335,16 +338,16 @@ void __init dc21285_preinit(void)
335 /* 338 /*
336 * We don't care if these fail. 339 * We don't care if these fail.
337 */ 340 */
338 request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED, 341 dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED,
339 "PCI system error", &serr_timer); 342 "PCI system error", &serr_timer);
340 request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED, 343 dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED,
341 "PCI parity error", &perr_timer); 344 "PCI parity error", &perr_timer);
342 request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED, 345 dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED,
343 "PCI abort", NULL); 346 "PCI abort", NULL);
344 request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED, 347 dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED,
345 "Discard timer", NULL); 348 "Discard timer", NULL);
346 request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED, 349 dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED,
347 "PCI data parity", NULL); 350 "PCI data parity", NULL);
348 351
349 if (cfn_mode) { 352 if (cfn_mode) {
350 static struct resource csrio; 353 static struct resource csrio;
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 9ee80a211d3c..8bfd06aeb64d 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -28,6 +28,8 @@
28#include <asm/irq.h> 28#include <asm/irq.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30 30
31#include "common.h"
32
31static void isa_mask_pic_lo_irq(unsigned int irq) 33static void isa_mask_pic_lo_irq(unsigned int irq)
32{ 34{
33 unsigned int mask = 1 << (irq & 7); 35 unsigned int mask = 1 << (irq & 7);
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 56161d55cf47..8c0ba99d683f 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -25,6 +25,7 @@
25#include <asm/page.h> 25#include <asm/page.h>
26#include <asm/pgtable.h> 26#include <asm/pgtable.h>
27#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
28#include <mach/irqs.h>
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include "common.h" 30#include "common.h"
30 31
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 7b8ef97fb501..b3404b7775b3 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -698,6 +698,7 @@ void __init kirkwood_init(void)
698 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", 698 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
699 kirkwood_id(), kirkwood_tclk); 699 kirkwood_id(), kirkwood_tclk);
700 kirkwood_ge00_shared_data.t_clk = kirkwood_tclk; 700 kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
701 kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
701 kirkwood_spi_plat_data.tclk = kirkwood_tclk; 702 kirkwood_spi_plat_data.tclk = kirkwood_tclk;
702 kirkwood_uart0_data[0].uartclk = kirkwood_tclk; 703 kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
703 kirkwood_uart1_data[0].uartclk = kirkwood_tclk; 704 kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index f6b08f207c89..73fccacd1a73 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,6 +11,7 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <asm/irq.h>
14#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
15#include <plat/pcie.h> 16#include <plat/pcie.h>
16#include "common.h" 17#include "common.h"
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 36ab0fd3d9b6..b89fb6d46ccc 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -22,6 +22,7 @@
22 22
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
25#include <mach/irqs.h>
25#include <mach/regs-wan.h> 26#include <mach/regs-wan.h>
26#include <mach/regs-lan.h> 27#include <mach/regs-lan.h>
27#include <mach/regs-hpna.h> 28#include <mach/regs-hpna.h>
diff --git a/arch/arm/mach-msm/devices.c b/arch/arm/mach-msm/devices.c
index f2a74b92a97f..31b6b30e98bf 100644
--- a/arch/arm/mach-msm/devices.c
+++ b/arch/arm/mach-msm/devices.c
@@ -16,6 +16,7 @@
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18 18
19#include <mach/irqs.h>
19#include <mach/msm_iomap.h> 20#include <mach/msm_iomap.h>
20#include "devices.h" 21#include "devices.h"
21 22
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 430ea84d587d..aad3a7a2f830 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -11,6 +11,7 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <asm/irq.h>
14#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
15#include <plat/pcie.h> 16#include <plat/pcie.h>
16#include "common.h" 17#include "common.h"
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index af121f5ab710..2f9240be1c76 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -32,6 +32,7 @@
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/gpio.h> 33#include <linux/gpio.h>
34 34
35#include <mach/irqs.h>
35#include <mach/hardware.h> 36#include <mach/hardware.h>
36 37
37/* 38/*
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 1d46cb4adf96..f8428800f286 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -22,6 +22,7 @@
22#include <linux/serial.h> 22#include <linux/serial.h>
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25#include <mach/irqs.h>
25#include <mach/imx-uart.h> 26#include <mach/imx-uart.h>
26 27
27static struct resource uart0[] = { 28static struct resource uart0[] = {
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index ea8fa8898fe8..1d844e228ea9 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -24,6 +24,8 @@
24#include <linux/amba/clcd.h> 24#include <linux/amba/clcd.h>
25#include <linux/err.h> 25#include <linux/err.h>
26 26
27#include <asm/irq.h>
28
27#include <mach/netx-regs.h> 29#include <mach/netx-regs.h>
28#include <mach/hardware.h> 30#include <mach/hardware.h>
29 31
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index d51d627ce7cf..f201fddb594f 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -163,7 +163,7 @@ static void __init netx_timer_init(void)
163 * Adding some safety ... */ 163 * Adding some safety ... */
164 netx_clockevent.min_delta_ns = 164 netx_clockevent.min_delta_ns =
165 clockevent_delta2ns(0xa00, &netx_clockevent); 165 clockevent_delta2ns(0xa00, &netx_clockevent);
166 netx_clockevent.cpumask = cpumask_of_cpu(0); 166 netx_clockevent.cpumask = cpumask_of(0);
167 clockevents_register_device(&netx_clockevent); 167 clockevents_register_device(&netx_clockevent);
168} 168}
169 169
diff --git a/arch/arm/mach-netx/xc.c b/arch/arm/mach-netx/xc.c
index 8fc6205dc3a5..181a78ba8165 100644
--- a/arch/arm/mach-netx/xc.c
+++ b/arch/arm/mach-netx/xc.c
@@ -24,6 +24,7 @@
24#include <linux/io.h> 24#include <linux/io.h>
25 25
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/irqs.h>
27#include <mach/netx-regs.h> 28#include <mach/netx-regs.h>
28 29
29#include <mach/xc.h> 30#include <mach/xc.h>
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 7de7c6915584..4474da7bc88a 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -18,6 +18,7 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19 19
20#include <mach/dma.h> 20#include <mach/dma.h>
21#include <mach/irqs.h>
21#include <mach/mux.h> 22#include <mach/mux.h>
22#include <mach/cpu.h> 23#include <mach/cpu.h>
23#include <mach/mcbsp.h> 24#include <mach/mcbsp.h>
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index cae3ebe249b3..acdc709901cd 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -18,6 +18,7 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19 19
20#include <mach/dma.h> 20#include <mach/dma.h>
21#include <mach/irqs.h>
21#include <mach/mux.h> 22#include <mach/mux.h>
22#include <mach/cpu.h> 23#include <mach/cpu.h>
23#include <mach/mcbsp.h> 24#include <mach/mcbsp.h>
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index a7b7d77b1b09..d0a785a3b880 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -13,6 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <asm/irq.h>
16#include <asm/mach/pci.h> 17#include <asm/mach/pci.h>
17#include <plat/pcie.h> 18#include <plat/pcie.h>
18#include "common.h" 19#include "common.h"
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
index 015cc21d5f55..f219914f5b29 100644
--- a/arch/arm/mach-pnx4008/gpio.c
+++ b/arch/arm/mach-pnx4008/gpio.c
@@ -18,6 +18,7 @@
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <mach/hardware.h>
21#include <mach/platform.h> 22#include <mach/platform.h>
22#include <mach/gpio.h> 23#include <mach/gpio.h>
23 24
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
index 87c093286ff9..f3fea29c00d3 100644
--- a/arch/arm/mach-pnx4008/i2c.c
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -15,6 +15,7 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <mach/platform.h> 17#include <mach/platform.h>
18#include <mach/irqs.h>
18#include <mach/i2c.h> 19#include <mach/i2c.h>
19 20
20static int set_clock_run(struct platform_device *pdev) 21static int set_clock_run(struct platform_device *pdev)
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index c5e28a46b292..a8d91b6c136b 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -27,6 +27,7 @@
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28#include <linux/spi/ads7846.h> 28#include <linux/spi/ads7846.h>
29#include <linux/spi/corgi_lcd.h> 29#include <linux/spi/corgi_lcd.h>
30#include <linux/mtd/sharpsl.h>
30#include <video/w100fb.h> 31#include <video/w100fb.h>
31 32
32#include <asm/setup.h> 33#include <asm/setup.h>
@@ -542,6 +543,55 @@ err_free_1:
542static inline void corgi_init_spi(void) {} 543static inline void corgi_init_spi(void) {}
543#endif 544#endif
544 545
546static struct mtd_partition sharpsl_nand_partitions[] = {
547 {
548 .name = "System Area",
549 .offset = 0,
550 .size = 7 * 1024 * 1024,
551 },
552 {
553 .name = "Root Filesystem",
554 .offset = 7 * 1024 * 1024,
555 .size = 25 * 1024 * 1024,
556 },
557 {
558 .name = "Home Filesystem",
559 .offset = MTDPART_OFS_APPEND,
560 .size = MTDPART_SIZ_FULL,
561 },
562};
563
564static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
565
566static struct nand_bbt_descr sharpsl_bbt = {
567 .options = 0,
568 .offs = 4,
569 .len = 2,
570 .pattern = scan_ff_pattern
571};
572
573static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
574 .badblock_pattern = &sharpsl_bbt,
575 .partitions = sharpsl_nand_partitions,
576 .nr_partitions = ARRAY_SIZE(sharpsl_nand_partitions),
577};
578
579static struct resource sharpsl_nand_resources[] = {
580 {
581 .start = 0x0C000000,
582 .end = 0x0C000FFF,
583 .flags = IORESOURCE_MEM,
584 },
585};
586
587static struct platform_device sharpsl_nand_device = {
588 .name = "sharpsl-nand",
589 .id = -1,
590 .resource = sharpsl_nand_resources,
591 .num_resources = ARRAY_SIZE(sharpsl_nand_resources),
592 .dev.platform_data = &sharpsl_nand_platform_data,
593};
594
545static struct mtd_partition sharpsl_rom_parts[] = { 595static struct mtd_partition sharpsl_rom_parts[] = {
546 { 596 {
547 .name ="Boot PROM Filesystem", 597 .name ="Boot PROM Filesystem",
@@ -577,6 +627,7 @@ static struct platform_device *devices[] __initdata = {
577 &corgifb_device, 627 &corgifb_device,
578 &corgikbd_device, 628 &corgikbd_device,
579 &corgiled_device, 629 &corgiled_device,
630 &sharpsl_nand_device,
580 &sharpsl_rom_device, 631 &sharpsl_rom_device,
581}; 632};
582 633
@@ -617,6 +668,9 @@ static void __init corgi_init(void)
617 668
618 platform_scoop_config = &corgi_pcmcia_config; 669 platform_scoop_config = &corgi_pcmcia_config;
619 670
671 if (machine_is_husky())
672 sharpsl_nand_partitions[1].size = 53 * 1024 * 1024;
673
620 platform_add_devices(devices, ARRAY_SIZE(devices)); 674 platform_add_devices(devices, ARRAY_SIZE(devices));
621} 675}
622 676
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c
index 251129391d7d..edcd9d5ce545 100644
--- a/arch/arm/mach-pxa/e350.c
+++ b/arch/arm/mach-pxa/e350.c
@@ -20,6 +20,7 @@
20#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
21#include <asm/mach-types.h> 21#include <asm/mach-types.h>
22 22
23#include <mach/irqs.h>
23#include <mach/mfp-pxa25x.h> 24#include <mach/mfp-pxa25x.h>
24#include <mach/pxa-regs.h> 25#include <mach/pxa-regs.h>
25#include <mach/hardware.h> 26#include <mach/hardware.h>
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c
index bed0336aca3d..77bb8e2c48c0 100644
--- a/arch/arm/mach-pxa/e400.c
+++ b/arch/arm/mach-pxa/e400.c
@@ -28,6 +28,7 @@
28#include <mach/eseries-gpio.h> 28#include <mach/eseries-gpio.h>
29#include <mach/pxafb.h> 29#include <mach/pxafb.h>
30#include <mach/udc.h> 30#include <mach/udc.h>
31#include <mach/irqs.h>
31 32
32#include "generic.h" 33#include "generic.h"
33#include "eseries.h" 34#include "eseries.h"
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
index b00d670b2ea6..6d48e00f4f0b 100644
--- a/arch/arm/mach-pxa/e740.c
+++ b/arch/arm/mach-pxa/e740.c
@@ -30,6 +30,7 @@
30#include <mach/eseries-gpio.h> 30#include <mach/eseries-gpio.h>
31#include <mach/udc.h> 31#include <mach/udc.h>
32#include <mach/irda.h> 32#include <mach/irda.h>
33#include <mach/irqs.h>
33 34
34#include "generic.h" 35#include "generic.h"
35#include "eseries.h" 36#include "eseries.h"
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c
index 84d7c1aac58d..be1ab8edb973 100644
--- a/arch/arm/mach-pxa/e750.c
+++ b/arch/arm/mach-pxa/e750.c
@@ -29,6 +29,7 @@
29#include <mach/eseries-gpio.h> 29#include <mach/eseries-gpio.h>
30#include <mach/udc.h> 30#include <mach/udc.h>
31#include <mach/irda.h> 31#include <mach/irda.h>
32#include <mach/irqs.h>
32 33
33#include "generic.h" 34#include "generic.h"
34#include "eseries.h" 35#include "eseries.h"
@@ -105,6 +106,57 @@ static struct platform_device e750_fb_device = {
105 .resource = e750_fb_resources, 106 .resource = e750_fb_resources,
106}; 107};
107 108
109/* -------------------- e750 MFP parameters -------------------- */
110
111static unsigned long e750_pin_config[] __initdata = {
112 /* Chip selects */
113 GPIO15_nCS_1, /* CS1 - Flash */
114 GPIO79_nCS_3, /* CS3 - IMAGEON */
115 GPIO80_nCS_4, /* CS4 - TMIO */
116
117 /* Clocks */
118 GPIO11_3_6MHz,
119
120 /* BTUART */
121 GPIO42_BTUART_RXD,
122 GPIO43_BTUART_TXD,
123 GPIO44_BTUART_CTS,
124
125 /* TMIO controller */
126 GPIO19_GPIO, /* t7l66xb #PCLR */
127 GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
128
129 /* UDC */
130 GPIO13_GPIO,
131 GPIO3_GPIO,
132
133 /* IrDA */
134 GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
135
136 /* PC Card */
137 GPIO8_GPIO, /* CD0 */
138 GPIO44_GPIO, /* CD1 */
139 GPIO11_GPIO, /* IRQ0 */
140 GPIO6_GPIO, /* IRQ1 */
141 GPIO27_GPIO, /* RST0 */
142 GPIO24_GPIO, /* RST1 */
143 GPIO20_GPIO, /* PWR0 */
144 GPIO23_GPIO, /* PWR1 */
145 GPIO48_nPOE,
146 GPIO49_nPWE,
147 GPIO50_nPIOR,
148 GPIO51_nPIOW,
149 GPIO52_nPCE_1,
150 GPIO53_nPCE_2,
151 GPIO54_nPSKTSEL,
152 GPIO55_nPREG,
153 GPIO56_nPWAIT,
154 GPIO57_nIOIS16,
155
156 /* wakeup */
157 GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
158};
159
108/* ----------------- e750 tc6393xb parameters ------------------ */ 160/* ----------------- e750 tc6393xb parameters ------------------ */
109 161
110static struct tc6393xb_platform_data e750_tc6393xb_info = { 162static struct tc6393xb_platform_data e750_tc6393xb_info = {
@@ -137,6 +189,7 @@ static struct platform_device *devices[] __initdata = {
137 189
138static void __init e750_init(void) 190static void __init e750_init(void)
139{ 191{
192 pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config));
140 clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev, 193 clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev,
141 "GPIO11_CLK", NULL), 194 "GPIO11_CLK", NULL),
142 eseries_get_tmio_gpios(); 195 eseries_get_tmio_gpios();
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c
index 9a86a426f924..cc9b1293e866 100644
--- a/arch/arm/mach-pxa/e800.c
+++ b/arch/arm/mach-pxa/e800.c
@@ -28,6 +28,7 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/eseries-gpio.h> 29#include <mach/eseries-gpio.h>
30#include <mach/udc.h> 30#include <mach/udc.h>
31#include <mach/irqs.h>
31 32
32#include "generic.h" 33#include "generic.h"
33#include "eseries.h" 34#include "eseries.h"
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index b1fcd10ab6c6..bcf3fb2c4b3a 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -193,10 +193,8 @@
193#define CKEN_MINI_IM 48 /* < Mini-IM */ 193#define CKEN_MINI_IM 48 /* < Mini-IM */
194#define CKEN_MINI_LCD 49 /* < Mini LCD */ 194#define CKEN_MINI_LCD 49 /* < Mini LCD */
195 195
196#if defined(CONFIG_CPU_PXA310)
197#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ 196#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
198#define CKEN_MVED 43 /* < MVED clock enable */ 197#define CKEN_MVED 43 /* < MVED clock enable */
199#endif
200 198
201/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ 199/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
202#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ 200#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index ae88855bf974..f9093beba752 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -24,6 +24,7 @@
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h> 26#include <linux/spi/ads7846.h>
27#include <linux/mtd/sharpsl.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <asm/mach-types.h> 30#include <asm/mach-types.h>
@@ -414,6 +415,55 @@ static struct pxafb_mach_info poodle_fb_info = {
414 .lcd_conn = LCD_COLOR_TFT_16BPP, 415 .lcd_conn = LCD_COLOR_TFT_16BPP,
415}; 416};
416 417
418static struct mtd_partition sharpsl_nand_partitions[] = {
419 {
420 .name = "System Area",
421 .offset = 0,
422 .size = 7 * 1024 * 1024,
423 },
424 {
425 .name = "Root Filesystem",
426 .offset = 7 * 1024 * 1024,
427 .size = 22 * 1024 * 1024,
428 },
429 {
430 .name = "Home Filesystem",
431 .offset = MTDPART_OFS_APPEND,
432 .size = MTDPART_SIZ_FULL,
433 },
434};
435
436static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
437
438static struct nand_bbt_descr sharpsl_bbt = {
439 .options = 0,
440 .offs = 4,
441 .len = 2,
442 .pattern = scan_ff_pattern
443};
444
445static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
446 .badblock_pattern = &sharpsl_bbt,
447 .partitions = sharpsl_nand_partitions,
448 .nr_partitions = ARRAY_SIZE(sharpsl_nand_partitions),
449};
450
451static struct resource sharpsl_nand_resources[] = {
452 {
453 .start = 0x0C000000,
454 .end = 0x0C000FFF,
455 .flags = IORESOURCE_MEM,
456 },
457};
458
459static struct platform_device sharpsl_nand_device = {
460 .name = "sharpsl-nand",
461 .id = -1,
462 .resource = sharpsl_nand_resources,
463 .num_resources = ARRAY_SIZE(sharpsl_nand_resources),
464 .dev.platform_data = &sharpsl_nand_platform_data,
465};
466
417static struct mtd_partition sharpsl_rom_parts[] = { 467static struct mtd_partition sharpsl_rom_parts[] = {
418 { 468 {
419 .name ="Boot PROM Filesystem", 469 .name ="Boot PROM Filesystem",
@@ -447,6 +497,7 @@ static struct platform_device sharpsl_rom_device = {
447static struct platform_device *devices[] __initdata = { 497static struct platform_device *devices[] __initdata = {
448 &poodle_locomo_device, 498 &poodle_locomo_device,
449 &poodle_scoop_device, 499 &poodle_scoop_device,
500 &sharpsl_nand_device,
450 &sharpsl_rom_device, 501 &sharpsl_rom_device,
451}; 502};
452 503
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 7299d87a1cb3..6d447c9ce8ab 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,6 +31,7 @@
31#include <linux/spi/spi.h> 31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h> 32#include <linux/spi/ads7846.h>
33#include <linux/spi/corgi_lcd.h> 33#include <linux/spi/corgi_lcd.h>
34#include <linux/mtd/sharpsl.h>
34 35
35#include <asm/setup.h> 36#include <asm/setup.h>
36#include <asm/memory.h> 37#include <asm/memory.h>
@@ -613,6 +614,54 @@ static struct pxafb_mach_info spitz_pxafb_info = {
613 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING, 614 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
614}; 615};
615 616
617static struct mtd_partition sharpsl_nand_partitions[] = {
618 {
619 .name = "System Area",
620 .offset = 0,
621 .size = 7 * 1024 * 1024,
622 },
623 {
624 .name = "Root Filesystem",
625 .offset = 7 * 1024 * 1024,
626 },
627 {
628 .name = "Home Filesystem",
629 .offset = MTDPART_OFS_APPEND,
630 .size = MTDPART_SIZ_FULL,
631 },
632};
633
634static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
635
636static struct nand_bbt_descr sharpsl_bbt = {
637 .options = 0,
638 .offs = 4,
639 .len = 2,
640 .pattern = scan_ff_pattern
641};
642
643static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
644 .badblock_pattern = &sharpsl_bbt,
645 .partitions = sharpsl_nand_partitions,
646 .nr_partitions = ARRAY_SIZE(sharpsl_nand_partitions),
647};
648
649static struct resource sharpsl_nand_resources[] = {
650 {
651 .start = 0x0C000000,
652 .end = 0x0C000FFF,
653 .flags = IORESOURCE_MEM,
654 },
655};
656
657static struct platform_device sharpsl_nand_device = {
658 .name = "sharpsl-nand",
659 .id = -1,
660 .resource = sharpsl_nand_resources,
661 .num_resources = ARRAY_SIZE(sharpsl_nand_resources),
662 .dev.platform_data = &sharpsl_nand_platform_data,
663};
664
616 665
617static struct mtd_partition sharpsl_rom_parts[] = { 666static struct mtd_partition sharpsl_rom_parts[] = {
618 { 667 {
@@ -648,6 +697,7 @@ static struct platform_device *devices[] __initdata = {
648 &spitzscoop_device, 697 &spitzscoop_device,
649 &spitzkbd_device, 698 &spitzkbd_device,
650 &spitzled_device, 699 &spitzled_device,
700 &sharpsl_nand_device,
651 &sharpsl_rom_device, 701 &sharpsl_rom_device,
652}; 702};
653 703
@@ -671,6 +721,14 @@ static void __init common_init(void)
671 pm_power_off = spitz_poweroff; 721 pm_power_off = spitz_poweroff;
672 arm_pm_restart = spitz_restart; 722 arm_pm_restart = spitz_restart;
673 723
724 if (machine_is_spitz()) {
725 sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
726 } else if (machine_is_akita()) {
727 sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
728 } else if (machine_is_borzoi()) {
729 sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
730 }
731
674 PMCR = 0x00; 732 PMCR = 0x00;
675 733
676 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */ 734 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
@@ -715,10 +773,29 @@ static struct i2c_board_info akita_i2c_board_info[] = {
715 }, 773 },
716}; 774};
717 775
776static struct nand_bbt_descr sharpsl_akita_bbt = {
777 .options = 0,
778 .offs = 4,
779 .len = 1,
780 .pattern = scan_ff_pattern
781};
782
783static struct nand_ecclayout akita_oobinfo = {
784 .eccbytes = 24,
785 .eccpos = {
786 0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
787 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
788 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
789 .oobfree = {{0x08, 0x09}}
790};
791
718static void __init akita_init(void) 792static void __init akita_init(void)
719{ 793{
720 spitz_ficp_platform_data.transceiver_mode = akita_irda_transceiver_mode; 794 spitz_ficp_platform_data.transceiver_mode = akita_irda_transceiver_mode;
721 795
796 sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
797 sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
798
722 /* We just pretend the second element of the array doesn't exist */ 799 /* We just pretend the second element of the array doesn't exist */
723 spitz_pcmcia_config.num_devs = 1; 800 spitz_pcmcia_config.num_devs = 1;
724 platform_scoop_config = &spitz_pcmcia_config; 801 platform_scoop_config = &spitz_pcmcia_config;
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 8fce85f33033..ea3c75595fa9 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -12,6 +12,7 @@
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/device.h> 14#include <linux/device.h>
15#include <linux/jiffies.h>
15#include <linux/smp.h> 16#include <linux/smp.h>
16#include <linux/io.h> 17#include <linux/io.h>
17 18
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index e0349af8a483..00476a573bbe 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -14,6 +14,7 @@
14#define gpio_get_value __gpio_get_value 14#define gpio_get_value __gpio_get_value
15#define gpio_set_value __gpio_set_value 15#define gpio_set_value __gpio_set_value
16#define gpio_cansleep __gpio_cansleep 16#define gpio_cansleep __gpio_cansleep
17#define gpio_to_irq __gpio_to_irq
17 18
18/* some boards require extra gpio capacity to support external 19/* some boards require extra gpio capacity to support external
19 * devices that need GPIO. 20 * devices that need GPIO.
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 9565903d490b..49efce8cd4a7 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -12,10 +12,6 @@
12#ifndef __ASM_ARCH_IRQS_H 12#ifndef __ASM_ARCH_IRQS_H
13#define __ASM_ARCH_IRQS_H __FILE__ 13#define __ASM_ARCH_IRQS_H __FILE__
14 14
15#ifndef __ASM_ARM_IRQ_H
16#error "Do not include this directly, instead #include <asm/irq.h>"
17#endif
18
19/* we keep the first set of CPU IRQs out of the range of 15/* we keep the first set of CPU IRQs out of the range of
20 * the ISA space, so that the PC104 has them to itself 16 * the ISA space, so that the PC104 has them to itself
21 * and we don't end up having to do horrible things to the 17 * and we don't end up having to do horrible things to the
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 0a6d0a5d961b..315c42e31278 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -47,7 +47,7 @@
47#include <plat/clock.h> 47#include <plat/clock.h>
48#include <plat/devs.h> 48#include <plat/devs.h>
49#include <plat/cpu.h> 49#include <plat/cpu.h>
50#include <asm/plat-s3c24xx/mci.h> 50#include <plat/mci.h>
51 51
52static struct map_desc at2440evb_iodesc[] __initdata = { 52static struct map_desc at2440evb_iodesc[] __initdata = {
53 /* Nothing here */ 53 /* Nothing here */
diff --git a/arch/arm/mach-s3c6400/include/mach/irqs.h b/arch/arm/mach-s3c6400/include/mach/irqs.h
index b38c47cffc28..4c97f9a4370b 100644
--- a/arch/arm/mach-s3c6400/include/mach/irqs.h
+++ b/arch/arm/mach-s3c6400/include/mach/irqs.h
@@ -11,10 +11,6 @@
11#ifndef __ASM_ARCH_IRQS_H 11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H __FILE__ 12#define __ASM_ARCH_IRQS_H __FILE__
13 13
14#ifndef __ASM_ARM_IRQ_H
15#error "Do not include this directly, instead #include <asm/irq.h>"
16#endif
17
18#include <plat/irqs.h> 14#include <plat/irqs.h>
19 15
20#endif /* __ASM_ARCH_IRQ_H */ 16#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 67960017dc8f..310e479309ef 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -71,7 +71,7 @@ static DEFINE_SPINLOCK(consistent_lock);
71 * the amount of RAM found at boot time.) I would imagine that get_vm_area() 71 * the amount of RAM found at boot time.) I would imagine that get_vm_area()
72 * would have to initialise this each time prior to calling vm_region_alloc(). 72 * would have to initialise this each time prior to calling vm_region_alloc().
73 */ 73 */
74struct vm_region { 74struct arm_vm_region {
75 struct list_head vm_list; 75 struct list_head vm_list;
76 unsigned long vm_start; 76 unsigned long vm_start;
77 unsigned long vm_end; 77 unsigned long vm_end;
@@ -79,20 +79,20 @@ struct vm_region {
79 int vm_active; 79 int vm_active;
80}; 80};
81 81
82static struct vm_region consistent_head = { 82static struct arm_vm_region consistent_head = {
83 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), 83 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
84 .vm_start = CONSISTENT_BASE, 84 .vm_start = CONSISTENT_BASE,
85 .vm_end = CONSISTENT_END, 85 .vm_end = CONSISTENT_END,
86}; 86};
87 87
88static struct vm_region * 88static struct arm_vm_region *
89vm_region_alloc(struct vm_region *head, size_t size, gfp_t gfp) 89arm_vm_region_alloc(struct arm_vm_region *head, size_t size, gfp_t gfp)
90{ 90{
91 unsigned long addr = head->vm_start, end = head->vm_end - size; 91 unsigned long addr = head->vm_start, end = head->vm_end - size;
92 unsigned long flags; 92 unsigned long flags;
93 struct vm_region *c, *new; 93 struct arm_vm_region *c, *new;
94 94
95 new = kmalloc(sizeof(struct vm_region), gfp); 95 new = kmalloc(sizeof(struct arm_vm_region), gfp);
96 if (!new) 96 if (!new)
97 goto out; 97 goto out;
98 98
@@ -127,9 +127,9 @@ vm_region_alloc(struct vm_region *head, size_t size, gfp_t gfp)
127 return NULL; 127 return NULL;
128} 128}
129 129
130static struct vm_region *vm_region_find(struct vm_region *head, unsigned long addr) 130static struct arm_vm_region *arm_vm_region_find(struct arm_vm_region *head, unsigned long addr)
131{ 131{
132 struct vm_region *c; 132 struct arm_vm_region *c;
133 133
134 list_for_each_entry(c, &head->vm_list, vm_list) { 134 list_for_each_entry(c, &head->vm_list, vm_list) {
135 if (c->vm_active && c->vm_start == addr) 135 if (c->vm_active && c->vm_start == addr)
@@ -149,7 +149,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
149 pgprot_t prot) 149 pgprot_t prot)
150{ 150{
151 struct page *page; 151 struct page *page;
152 struct vm_region *c; 152 struct arm_vm_region *c;
153 unsigned long order; 153 unsigned long order;
154 u64 mask = ISA_DMA_THRESHOLD, limit; 154 u64 mask = ISA_DMA_THRESHOLD, limit;
155 155
@@ -214,7 +214,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
214 /* 214 /*
215 * Allocate a virtual address in the consistent mapping region. 215 * Allocate a virtual address in the consistent mapping region.
216 */ 216 */
217 c = vm_region_alloc(&consistent_head, size, 217 c = arm_vm_region_alloc(&consistent_head, size,
218 gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); 218 gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
219 if (c) { 219 if (c) {
220 pte_t *pte; 220 pte_t *pte;
@@ -311,13 +311,13 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
311 void *cpu_addr, dma_addr_t dma_addr, size_t size) 311 void *cpu_addr, dma_addr_t dma_addr, size_t size)
312{ 312{
313 unsigned long flags, user_size, kern_size; 313 unsigned long flags, user_size, kern_size;
314 struct vm_region *c; 314 struct arm_vm_region *c;
315 int ret = -ENXIO; 315 int ret = -ENXIO;
316 316
317 user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; 317 user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
318 318
319 spin_lock_irqsave(&consistent_lock, flags); 319 spin_lock_irqsave(&consistent_lock, flags);
320 c = vm_region_find(&consistent_head, (unsigned long)cpu_addr); 320 c = arm_vm_region_find(&consistent_head, (unsigned long)cpu_addr);
321 spin_unlock_irqrestore(&consistent_lock, flags); 321 spin_unlock_irqrestore(&consistent_lock, flags);
322 322
323 if (c) { 323 if (c) {
@@ -359,7 +359,7 @@ EXPORT_SYMBOL(dma_mmap_writecombine);
359 */ 359 */
360void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) 360void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
361{ 361{
362 struct vm_region *c; 362 struct arm_vm_region *c;
363 unsigned long flags, addr; 363 unsigned long flags, addr;
364 pte_t *ptep; 364 pte_t *ptep;
365 int idx; 365 int idx;
@@ -378,7 +378,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
378 size = PAGE_ALIGN(size); 378 size = PAGE_ALIGN(size);
379 379
380 spin_lock_irqsave(&consistent_lock, flags); 380 spin_lock_irqsave(&consistent_lock, flags);
381 c = vm_region_find(&consistent_head, (unsigned long)cpu_addr); 381 c = arm_vm_region_find(&consistent_head, (unsigned long)cpu_addr);
382 if (!c) 382 if (!c)
383 goto no_area; 383 goto no_area;
384 384
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 89a6ab0b7db8..467531edefd3 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,6 +26,7 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <mach/irqs.h>
29#include <mach/mux.h> 30#include <mach/mux.h>
30 31
31#define OMAP_I2C_SIZE 0x3f 32#define OMAP_I2C_SIZE 0x3f
diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-s3c/dev-fb.c
index 0454b8ec02e2..a90198fc4b0f 100644
--- a/arch/arm/plat-s3c/dev-fb.c
+++ b/arch/arm/plat-s3c/dev-fb.c
@@ -16,6 +16,7 @@
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/fb.h> 17#include <linux/fb.h>
18 18
19#include <mach/irqs.h>
19#include <mach/map.h> 20#include <mach/map.h>
20#include <mach/regs-fb.h> 21#include <mach/regs-fb.h>
21 22
diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c
index 2c0128c77c6e..fe327074037e 100644
--- a/arch/arm/plat-s3c/dev-i2c0.c
+++ b/arch/arm/plat-s3c/dev-i2c0.c
@@ -15,6 +15,7 @@
15#include <linux/string.h> 15#include <linux/string.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17 17
18#include <mach/irqs.h>
18#include <mach/map.h> 19#include <mach/map.h>
19 20
20#include <plat/regs-iic.h> 21#include <plat/regs-iic.h>
diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c
index 9658fb0aec95..2387fbf57af6 100644
--- a/arch/arm/plat-s3c/dev-i2c1.c
+++ b/arch/arm/plat-s3c/dev-i2c1.c
@@ -15,6 +15,7 @@
15#include <linux/string.h> 15#include <linux/string.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17 17
18#include <mach/irqs.h>
18#include <mach/map.h> 19#include <mach/map.h>
19 20
20#include <plat/regs-iic.h> 21#include <plat/regs-iic.h>
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index f95c6c9d9f1a..94a341aaa4e4 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -59,6 +59,22 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
59 return 0; 59 return 0;
60} 60}
61 61
62static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
63{
64 if (offset < 4)
65 return IRQ_EINT0 + offset;
66
67 if (offset < 8)
68 return IRQ_EINT4 + offset - 4;
69
70 return -EINVAL;
71}
72
73static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
74{
75 return IRQ_EINT8 + offset;
76}
77
62struct s3c_gpio_chip s3c24xx_gpios[] = { 78struct s3c_gpio_chip s3c24xx_gpios[] = {
63 [0] = { 79 [0] = {
64 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), 80 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
@@ -114,6 +130,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
114 .owner = THIS_MODULE, 130 .owner = THIS_MODULE,
115 .label = "GPIOF", 131 .label = "GPIOF",
116 .ngpio = 8, 132 .ngpio = 8,
133 .to_irq = s3c24xx_gpiolib_bankf_toirq,
117 }, 134 },
118 }, 135 },
119 [6] = { 136 [6] = {
@@ -123,6 +140,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
123 .owner = THIS_MODULE, 140 .owner = THIS_MODULE,
124 .label = "GPIOG", 141 .label = "GPIOG",
125 .ngpio = 10, 142 .ngpio = 10,
143 .to_irq = s3c24xx_gpiolib_bankg_toirq,
126 }, 144 },
127 }, 145 },
128}; 146};
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
index ec56b88866c4..0120b760315b 100644
--- a/arch/arm/plat-s3c24xx/pwm.c
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -19,6 +19,8 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/pwm.h> 20#include <linux/pwm.h>
21 21
22#include <mach/irqs.h>
23
22#include <plat/devs.h> 24#include <plat/devs.h>
23#include <plat/regs-timer.h> 25#include <plat/regs-timer.h>
24 26
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
index 02e8dd4c97d5..2846f550b727 100644
--- a/arch/arm/plat-s3c64xx/include/plat/irqs.h
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -191,7 +191,7 @@
191#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) 191#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
192#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) 192#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
193 193
194#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x)) 194#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no))
195 195
196/* Set the default NR_IRQS */ 196/* Set the default NR_IRQS */
197 197
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index ea7bc1e8562b..3fbfd1e32a9e 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1305,7 +1305,7 @@ struct platform_device *__init
1305at32_add_device_mci(unsigned int id, struct mci_platform_data *data) 1305at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1306{ 1306{
1307 struct platform_device *pdev; 1307 struct platform_device *pdev;
1308 struct dw_dma_slave *dws; 1308 struct dw_dma_slave *dws = &data->dma_slave;
1309 u32 pioa_mask; 1309 u32 pioa_mask;
1310 u32 piob_mask; 1310 u32 piob_mask;
1311 1311
@@ -1324,22 +1324,13 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1324 ARRAY_SIZE(atmel_mci0_resource))) 1324 ARRAY_SIZE(atmel_mci0_resource)))
1325 goto fail; 1325 goto fail;
1326 1326
1327 if (data->dma_slave) 1327 dws->dma_dev = &dw_dmac0_device.dev;
1328 dws = kmemdup(to_dw_dma_slave(data->dma_slave), 1328 dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1329 sizeof(struct dw_dma_slave), GFP_KERNEL);
1330 else
1331 dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
1332
1333 dws->slave.dev = &pdev->dev;
1334 dws->slave.dma_dev = &dw_dmac0_device.dev;
1335 dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
1336 dws->cfg_hi = (DWC_CFGH_SRC_PER(0) 1329 dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1337 | DWC_CFGH_DST_PER(1)); 1330 | DWC_CFGH_DST_PER(1));
1338 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL 1331 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1339 | DWC_CFGL_HS_SRC_POL); 1332 | DWC_CFGL_HS_SRC_POL);
1340 1333
1341 data->dma_slave = &dws->slave;
1342
1343 if (platform_device_add_data(pdev, data, 1334 if (platform_device_add_data(pdev, data,
1344 sizeof(struct mci_platform_data))) 1335 sizeof(struct mci_platform_data)))
1345 goto fail; 1336 goto fail;
diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h
index 757e43906ed4..dbfd686360e6 100644
--- a/arch/blackfin/include/asm/mmu.h
+++ b/arch/blackfin/include/asm/mmu.h
@@ -10,7 +10,6 @@ struct sram_list_struct {
10}; 10};
11 11
12typedef struct { 12typedef struct {
13 struct vm_list_struct *vmlist;
14 unsigned long end_brk; 13 unsigned long end_brk;
15 unsigned long stack_start; 14 unsigned long stack_start;
16 15
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index d2d388536630..594e325b40e4 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -160,15 +160,15 @@ put_reg(struct task_struct *task, int regno, unsigned long data)
160static inline int is_user_addr_valid(struct task_struct *child, 160static inline int is_user_addr_valid(struct task_struct *child,
161 unsigned long start, unsigned long len) 161 unsigned long start, unsigned long len)
162{ 162{
163 struct vm_list_struct *vml; 163 struct vm_area_struct *vma;
164 struct sram_list_struct *sraml; 164 struct sram_list_struct *sraml;
165 165
166 /* overflow */ 166 /* overflow */
167 if (start + len < start) 167 if (start + len < start)
168 return -EIO; 168 return -EIO;
169 169
170 for (vml = child->mm->context.vmlist; vml; vml = vml->next) 170 vma = find_vma(child->mm, start);
171 if (start >= vml->vma->vm_start && start + len < vml->vma->vm_end) 171 if (vma && start >= vma->vm_start && start + len <= vma->vm_end)
172 return 0; 172 return 0;
173 173
174 for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next) 174 for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next)
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 17d8e4172896..5b0667da8d05 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -32,6 +32,7 @@
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/kallsyms.h> 33#include <linux/kallsyms.h>
34#include <linux/fs.h> 34#include <linux/fs.h>
35#include <linux/rbtree.h>
35#include <asm/traps.h> 36#include <asm/traps.h>
36#include <asm/cacheflush.h> 37#include <asm/cacheflush.h>
37#include <asm/cplb.h> 38#include <asm/cplb.h>
@@ -83,6 +84,7 @@ static void decode_address(char *buf, unsigned long address)
83 struct mm_struct *mm; 84 struct mm_struct *mm;
84 unsigned long flags, offset; 85 unsigned long flags, offset;
85 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic(); 86 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
87 struct rb_node *n;
86 88
87#ifdef CONFIG_KALLSYMS 89#ifdef CONFIG_KALLSYMS
88 unsigned long symsize; 90 unsigned long symsize;
@@ -128,9 +130,10 @@ static void decode_address(char *buf, unsigned long address)
128 if (!mm) 130 if (!mm)
129 continue; 131 continue;
130 132
131 vml = mm->context.vmlist; 133 for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
132 while (vml) { 134 struct vm_area_struct *vma;
133 struct vm_area_struct *vma = vml->vma; 135
136 vma = rb_entry(n, struct vm_area_struct, vm_rb);
134 137
135 if (address >= vma->vm_start && address < vma->vm_end) { 138 if (address >= vma->vm_start && address < vma->vm_end) {
136 char _tmpbuf[256]; 139 char _tmpbuf[256];
@@ -176,8 +179,6 @@ static void decode_address(char *buf, unsigned long address)
176 179
177 goto done; 180 goto done;
178 } 181 }
179
180 vml = vml->next;
181 } 182 }
182 if (!in_atomic) 183 if (!in_atomic)
183 mmput(mm); 184 mmput(mm);
diff --git a/arch/frv/kernel/ptrace.c b/arch/frv/kernel/ptrace.c
index 709e9bdc6126..5e7d401d21e7 100644
--- a/arch/frv/kernel/ptrace.c
+++ b/arch/frv/kernel/ptrace.c
@@ -69,7 +69,8 @@ static inline int put_reg(struct task_struct *task, int regno,
69} 69}
70 70
71/* 71/*
72 * check that an address falls within the bounds of the target process's memory mappings 72 * check that an address falls within the bounds of the target process's memory
73 * mappings
73 */ 74 */
74static inline int is_user_addr_valid(struct task_struct *child, 75static inline int is_user_addr_valid(struct task_struct *child,
75 unsigned long start, unsigned long len) 76 unsigned long start, unsigned long len)
@@ -79,11 +80,11 @@ static inline int is_user_addr_valid(struct task_struct *child,
79 return -EIO; 80 return -EIO;
80 return 0; 81 return 0;
81#else 82#else
82 struct vm_list_struct *vml; 83 struct vm_area_struct *vma;
83 84
84 for (vml = child->mm->context.vmlist; vml; vml = vml->next) 85 vma = find_vma(child->mm, start);
85 if (start >= vml->vma->vm_start && start + len <= vml->vma->vm_end) 86 if (vma && start >= vma->vm_start && start + len <= vma->vm_end)
86 return 0; 87 return 0;
87 88
88 return -EIO; 89 return -EIO;
89#endif 90#endif
diff --git a/arch/h8300/include/asm/mmu.h b/arch/h8300/include/asm/mmu.h
index 2ce06ea46104..31309969df70 100644
--- a/arch/h8300/include/asm/mmu.h
+++ b/arch/h8300/include/asm/mmu.h
@@ -4,7 +4,6 @@
4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */ 4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
5 5
6typedef struct { 6typedef struct {
7 struct vm_list_struct *vmlist;
8 unsigned long end_brk; 7 unsigned long end_brk;
9} mm_context_t; 8} mm_context_t;
10 9
diff --git a/arch/ia64/include/asm/acpi-ext.h b/arch/ia64/include/asm/acpi-ext.h
index 734d137dda6e..7f8362b379eb 100644
--- a/arch/ia64/include/asm/acpi-ext.h
+++ b/arch/ia64/include/asm/acpi-ext.h
@@ -14,7 +14,6 @@
14#define _ASM_IA64_ACPI_EXT_H 14#define _ASM_IA64_ACPI_EXT_H
15 15
16#include <linux/types.h> 16#include <linux/types.h>
17#include <acpi/actypes.h>
18 17
19extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length); 18extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length);
20 19
diff --git a/arch/ia64/include/asm/irq.h b/arch/ia64/include/asm/irq.h
index 36429a532630..5282546cdf82 100644
--- a/arch/ia64/include/asm/irq.h
+++ b/arch/ia64/include/asm/irq.h
@@ -27,7 +27,7 @@ irq_canonicalize (int irq)
27} 27}
28 28
29extern void set_irq_affinity_info (unsigned int irq, int dest, int redir); 29extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
30bool is_affinity_mask_valid(cpumask_var_t cpumask); 30bool is_affinity_mask_valid(const struct cpumask *cpumask);
31 31
32#define is_affinity_mask_valid is_affinity_mask_valid 32#define is_affinity_mask_valid is_affinity_mask_valid
33 33
diff --git a/arch/ia64/include/asm/sn/acpi.h b/arch/ia64/include/asm/sn/acpi.h
index 9ce2801cbd57..fd480db25565 100644
--- a/arch/ia64/include/asm/sn/acpi.h
+++ b/arch/ia64/include/asm/sn/acpi.h
@@ -9,8 +9,6 @@
9#ifndef _ASM_IA64_SN_ACPI_H 9#ifndef _ASM_IA64_SN_ACPI_H
10#define _ASM_IA64_SN_ACPI_H 10#define _ASM_IA64_SN_ACPI_H
11 11
12#include "acpi/acglobal.h"
13
14extern int sn_acpi_rev; 12extern int sn_acpi_rev;
15#define SN_ACPI_BASE_SUPPORT() (sn_acpi_rev >= 0x20101) 13#define SN_ACPI_BASE_SUPPORT() (sn_acpi_rev >= 0x20101)
16 14
diff --git a/arch/ia64/include/asm/topology.h b/arch/ia64/include/asm/topology.h
index 76a33a91ca69..32f3af1641c5 100644
--- a/arch/ia64/include/asm/topology.h
+++ b/arch/ia64/include/asm/topology.h
@@ -124,7 +124,7 @@ extern void arch_fix_phys_package_id(int num, u32 slot);
124 124
125#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \ 125#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \
126 cpu_all_mask : \ 126 cpu_all_mask : \
127 cpumask_from_node(pcibus_to_node(bus))) 127 cpumask_of_node(pcibus_to_node(bus)))
128 128
129#include <asm-generic/topology.h> 129#include <asm-generic/topology.h>
130 130
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 0553648b7595..d541671caf4a 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -65,6 +65,7 @@ EXPORT_SYMBOL(pm_idle);
65void (*pm_power_off) (void); 65void (*pm_power_off) (void);
66EXPORT_SYMBOL(pm_power_off); 66EXPORT_SYMBOL(pm_power_off);
67 67
68u32 acpi_rsdt_forced;
68unsigned int acpi_cpei_override; 69unsigned int acpi_cpei_override;
69unsigned int acpi_cpei_phys_cpuid; 70unsigned int acpi_cpei_phys_cpuid;
70 71
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c
index 95ff16cb05d8..a58f64ca9f0e 100644
--- a/arch/ia64/kernel/irq.c
+++ b/arch/ia64/kernel/irq.c
@@ -102,17 +102,14 @@ static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
102 102
103void set_irq_affinity_info (unsigned int irq, int hwid, int redir) 103void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
104{ 104{
105 cpumask_t mask = CPU_MASK_NONE;
106
107 cpu_set(cpu_logical_id(hwid), mask);
108
109 if (irq < NR_IRQS) { 105 if (irq < NR_IRQS) {
110 irq_desc[irq].affinity = mask; 106 cpumask_copy(&irq_desc[irq].affinity,
107 cpumask_of(cpu_logical_id(hwid)));
111 irq_redir[irq] = (char) (redir & 0xff); 108 irq_redir[irq] = (char) (redir & 0xff);
112 } 109 }
113} 110}
114 111
115bool is_affinity_mask_valid(cpumask_var_t cpumask) 112bool is_affinity_mask_valid(const struct cpumask *cpumask)
116{ 113{
117 if (ia64_platform_is("sn2")) { 114 if (ia64_platform_is("sn2")) {
118 /* Only allow one CPU to be specified in the smp_affinity mask */ 115 /* Only allow one CPU to be specified in the smp_affinity mask */
@@ -128,7 +125,7 @@ bool is_affinity_mask_valid(cpumask_var_t cpumask)
128unsigned int vectors_in_migration[NR_IRQS]; 125unsigned int vectors_in_migration[NR_IRQS];
129 126
130/* 127/*
131 * Since cpu_online_map is already updated, we just need to check for 128 * Since cpu_online_mask is already updated, we just need to check for
132 * affinity that has zeros 129 * affinity that has zeros
133 */ 130 */
134static void migrate_irqs(void) 131static void migrate_irqs(void)
@@ -158,7 +155,7 @@ static void migrate_irqs(void)
158 */ 155 */
159 vectors_in_migration[irq] = irq; 156 vectors_in_migration[irq] = irq;
160 157
161 new_cpu = any_online_cpu(cpu_online_map); 158 new_cpu = cpumask_any(cpu_online_mask);
162 159
163 /* 160 /*
164 * Al three are essential, currently WARN_ON.. maybe panic? 161 * Al three are essential, currently WARN_ON.. maybe panic?
@@ -191,7 +188,7 @@ void fixup_irqs(void)
191 * Find a new timesync master 188 * Find a new timesync master
192 */ 189 */
193 if (smp_processor_id() == time_keeper_id) { 190 if (smp_processor_id() == time_keeper_id) {
194 time_keeper_id = first_cpu(cpu_online_map); 191 time_keeper_id = cpumask_first(cpu_online_mask);
195 printk ("CPU %d is now promoted to time-keeper master\n", time_keeper_id); 192 printk ("CPU %d is now promoted to time-keeper master\n", time_keeper_id);
196 } 193 }
197 194
diff --git a/arch/ia64/sn/kernel/io_acpi_init.c b/arch/ia64/sn/kernel/io_acpi_init.c
index bc610a6c7851..c5a214026a77 100644
--- a/arch/ia64/sn/kernel/io_acpi_init.c
+++ b/arch/ia64/sn/kernel/io_acpi_init.c
@@ -13,7 +13,6 @@
13#include <asm/sn/sn_sal.h> 13#include <asm/sn/sn_sal.h>
14#include "xtalk/hubdev.h" 14#include "xtalk/hubdev.h"
15#include <linux/acpi.h> 15#include <linux/acpi.h>
16#include <acpi/acnamesp.h>
17 16
18 17
19/* 18/*
@@ -64,6 +63,7 @@ static acpi_status __init
64sn_acpi_hubdev_init(acpi_handle handle, u32 depth, void *context, void **ret) 63sn_acpi_hubdev_init(acpi_handle handle, u32 depth, void *context, void **ret)
65{ 64{
66 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 65 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
66 struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
67 u64 addr; 67 u64 addr;
68 struct hubdev_info *hubdev; 68 struct hubdev_info *hubdev;
69 struct hubdev_info *hubdev_ptr; 69 struct hubdev_info *hubdev_ptr;
@@ -77,11 +77,12 @@ sn_acpi_hubdev_init(acpi_handle handle, u32 depth, void *context, void **ret)
77 status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS, 77 status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS,
78 &sn_uuid, &buffer); 78 &sn_uuid, &buffer);
79 if (ACPI_FAILURE(status)) { 79 if (ACPI_FAILURE(status)) {
80 acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
80 printk(KERN_ERR 81 printk(KERN_ERR
81 "sn_acpi_hubdev_init: acpi_get_vendor_resource() " 82 "sn_acpi_hubdev_init: acpi_get_vendor_resource() "
82 "(0x%x) failed for: ", status); 83 "(0x%x) failed for: %s\n", status,
83 acpi_ns_print_node_pathname(handle, NULL); 84 (char *)name_buffer.pointer);
84 printk("\n"); 85 kfree(name_buffer.pointer);
85 return AE_OK; /* Continue walking namespace */ 86 return AE_OK; /* Continue walking namespace */
86 } 87 }
87 88
@@ -89,11 +90,12 @@ sn_acpi_hubdev_init(acpi_handle handle, u32 depth, void *context, void **ret)
89 vendor = &resource->data.vendor_typed; 90 vendor = &resource->data.vendor_typed;
90 if ((vendor->byte_length - sizeof(struct acpi_vendor_uuid)) != 91 if ((vendor->byte_length - sizeof(struct acpi_vendor_uuid)) !=
91 sizeof(struct hubdev_info *)) { 92 sizeof(struct hubdev_info *)) {
93 acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
92 printk(KERN_ERR 94 printk(KERN_ERR
93 "sn_acpi_hubdev_init: Invalid vendor data length: %d for: ", 95 "sn_acpi_hubdev_init: Invalid vendor data length: "
94 vendor->byte_length); 96 "%d for: %s\n",
95 acpi_ns_print_node_pathname(handle, NULL); 97 vendor->byte_length, (char *)name_buffer.pointer);
96 printk("\n"); 98 kfree(name_buffer.pointer);
97 goto exit; 99 goto exit;
98 } 100 }
99 101
@@ -120,6 +122,7 @@ sn_get_bussoft_ptr(struct pci_bus *bus)
120{ 122{
121 u64 addr; 123 u64 addr;
122 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 124 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
125 struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
123 acpi_handle handle; 126 acpi_handle handle;
124 struct pcibus_bussoft *prom_bussoft_ptr; 127 struct pcibus_bussoft *prom_bussoft_ptr;
125 struct acpi_resource *resource; 128 struct acpi_resource *resource;
@@ -131,11 +134,11 @@ sn_get_bussoft_ptr(struct pci_bus *bus)
131 status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS, 134 status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS,
132 &sn_uuid, &buffer); 135 &sn_uuid, &buffer);
133 if (ACPI_FAILURE(status)) { 136 if (ACPI_FAILURE(status)) {
137 acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
134 printk(KERN_ERR "%s: " 138 printk(KERN_ERR "%s: "
135 "acpi_get_vendor_resource() failed (0x%x) for: ", 139 "acpi_get_vendor_resource() failed (0x%x) for: %s\n",
136 __func__, status); 140 __func__, status, (char *)name_buffer.pointer);
137 acpi_ns_print_node_pathname(handle, NULL); 141 kfree(name_buffer.pointer);
138 printk("\n");
139 return NULL; 142 return NULL;
140 } 143 }
141 resource = buffer.pointer; 144 resource = buffer.pointer;
@@ -168,6 +171,7 @@ sn_extract_device_info(acpi_handle handle, struct pcidev_info **pcidev_info,
168{ 171{
169 u64 addr; 172 u64 addr;
170 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 173 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
174 struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
171 struct sn_irq_info *irq_info, *irq_info_prom; 175 struct sn_irq_info *irq_info, *irq_info_prom;
172 struct pcidev_info *pcidev_ptr, *pcidev_prom_ptr; 176 struct pcidev_info *pcidev_ptr, *pcidev_prom_ptr;
173 struct acpi_resource *resource; 177 struct acpi_resource *resource;
@@ -182,11 +186,11 @@ sn_extract_device_info(acpi_handle handle, struct pcidev_info **pcidev_info,
182 status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS, 186 status = acpi_get_vendor_resource(handle, METHOD_NAME__CRS,
183 &sn_uuid, &buffer); 187 &sn_uuid, &buffer);
184 if (ACPI_FAILURE(status)) { 188 if (ACPI_FAILURE(status)) {
189 acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
185 printk(KERN_ERR 190 printk(KERN_ERR
186 "%s: acpi_get_vendor_resource() failed (0x%x) for: ", 191 "%s: acpi_get_vendor_resource() failed (0x%x) for: %s\n",
187 __func__, status); 192 __func__, status, (char *)name_buffer.pointer);
188 acpi_ns_print_node_pathname(handle, NULL); 193 kfree(name_buffer.pointer);
189 printk("\n");
190 return 1; 194 return 1;
191 } 195 }
192 196
@@ -194,11 +198,12 @@ sn_extract_device_info(acpi_handle handle, struct pcidev_info **pcidev_info,
194 vendor = &resource->data.vendor_typed; 198 vendor = &resource->data.vendor_typed;
195 if ((vendor->byte_length - sizeof(struct acpi_vendor_uuid)) != 199 if ((vendor->byte_length - sizeof(struct acpi_vendor_uuid)) !=
196 sizeof(struct pci_devdev_info *)) { 200 sizeof(struct pci_devdev_info *)) {
201 acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
197 printk(KERN_ERR 202 printk(KERN_ERR
198 "%s: Invalid vendor data length: %d for: ", 203 "%s: Invalid vendor data length: %d for: %s\n",
199 __func__, vendor->byte_length); 204 __func__, vendor->byte_length,
200 acpi_ns_print_node_pathname(handle, NULL); 205 (char *)name_buffer.pointer);
201 printk("\n"); 206 kfree(name_buffer.pointer);
202 ret = 1; 207 ret = 1;
203 goto exit; 208 goto exit;
204 } 209 }
@@ -239,6 +244,9 @@ get_host_devfn(acpi_handle device_handle, acpi_handle rootbus_handle)
239 acpi_handle parent; 244 acpi_handle parent;
240 int slot; 245 int slot;
241 acpi_status status; 246 acpi_status status;
247 struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
248
249 acpi_get_name(device_handle, ACPI_FULL_PATHNAME, &name_buffer);
242 250
243 /* 251 /*
244 * Do an upward search to find the root bus device, and 252 * Do an upward search to find the root bus device, and
@@ -249,9 +257,8 @@ get_host_devfn(acpi_handle device_handle, acpi_handle rootbus_handle)
249 status = acpi_get_parent(child, &parent); 257 status = acpi_get_parent(child, &parent);
250 if (ACPI_FAILURE(status)) { 258 if (ACPI_FAILURE(status)) {
251 printk(KERN_ERR "%s: acpi_get_parent() failed " 259 printk(KERN_ERR "%s: acpi_get_parent() failed "
252 "(0x%x) for: ", __func__, status); 260 "(0x%x) for: %s\n", __func__, status,
253 acpi_ns_print_node_pathname(child, NULL); 261 (char *)name_buffer.pointer);
254 printk("\n");
255 panic("%s: Unable to find host devfn\n", __func__); 262 panic("%s: Unable to find host devfn\n", __func__);
256 } 263 }
257 if (parent == rootbus_handle) 264 if (parent == rootbus_handle)
@@ -259,22 +266,20 @@ get_host_devfn(acpi_handle device_handle, acpi_handle rootbus_handle)
259 child = parent; 266 child = parent;
260 } 267 }
261 if (!child) { 268 if (!child) {
262 printk(KERN_ERR "%s: Unable to find root bus for: ", 269 printk(KERN_ERR "%s: Unable to find root bus for: %s\n",
263 __func__); 270 __func__, (char *)name_buffer.pointer);
264 acpi_ns_print_node_pathname(device_handle, NULL);
265 printk("\n");
266 BUG(); 271 BUG();
267 } 272 }
268 273
269 status = acpi_evaluate_integer(child, METHOD_NAME__ADR, NULL, &adr); 274 status = acpi_evaluate_integer(child, METHOD_NAME__ADR, NULL, &adr);
270 if (ACPI_FAILURE(status)) { 275 if (ACPI_FAILURE(status)) {
271 printk(KERN_ERR "%s: Unable to get _ADR (0x%x) for: ", 276 printk(KERN_ERR "%s: Unable to get _ADR (0x%x) for: %s\n",
272 __func__, status); 277 __func__, status, (char *)name_buffer.pointer);
273 acpi_ns_print_node_pathname(child, NULL);
274 printk("\n");
275 panic("%s: Unable to find host devfn\n", __func__); 278 panic("%s: Unable to find host devfn\n", __func__);
276 } 279 }
277 280
281 kfree(name_buffer.pointer);
282
278 slot = (adr >> 16) & 0xffff; 283 slot = (adr >> 16) & 0xffff;
279 function = adr & 0xffff; 284 function = adr & 0xffff;
280 devfn = PCI_DEVFN(slot, function); 285 devfn = PCI_DEVFN(slot, function);
@@ -300,27 +305,28 @@ find_matching_device(acpi_handle handle, u32 lvl, void *context, void **rv)
300 int function; 305 int function;
301 int slot; 306 int slot;
302 struct sn_pcidev_match *info = context; 307 struct sn_pcidev_match *info = context;
308 struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
303 309
304 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL, 310 status = acpi_evaluate_integer(handle, METHOD_NAME__ADR, NULL,
305 &adr); 311 &adr);
306 if (ACPI_SUCCESS(status)) { 312 if (ACPI_SUCCESS(status)) {
307 status = acpi_get_parent(handle, &parent); 313 status = acpi_get_parent(handle, &parent);
308 if (ACPI_FAILURE(status)) { 314 if (ACPI_FAILURE(status)) {
315 acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
309 printk(KERN_ERR 316 printk(KERN_ERR
310 "%s: acpi_get_parent() failed (0x%x) for: ", 317 "%s: acpi_get_parent() failed (0x%x) for: %s\n",
311 __func__, status); 318 __func__, status, (char *)name_buffer.pointer);
312 acpi_ns_print_node_pathname(handle, NULL); 319 kfree(name_buffer.pointer);
313 printk("\n");
314 return AE_OK; 320 return AE_OK;
315 } 321 }
316 status = acpi_evaluate_integer(parent, METHOD_NAME__BBN, 322 status = acpi_evaluate_integer(parent, METHOD_NAME__BBN,
317 NULL, &bbn); 323 NULL, &bbn);
318 if (ACPI_FAILURE(status)) { 324 if (ACPI_FAILURE(status)) {
325 acpi_get_name(handle, ACPI_FULL_PATHNAME, &name_buffer);
319 printk(KERN_ERR 326 printk(KERN_ERR
320 "%s: Failed to find _BBN in parent of: ", 327 "%s: Failed to find _BBN in parent of: %s\n",
321 __func__); 328 __func__, (char *)name_buffer.pointer);
322 acpi_ns_print_node_pathname(handle, NULL); 329 kfree(name_buffer.pointer);
323 printk("\n");
324 return AE_OK; 330 return AE_OK;
325 } 331 }
326 332
@@ -350,24 +356,27 @@ sn_acpi_get_pcidev_info(struct pci_dev *dev, struct pcidev_info **pcidev_info,
350 acpi_handle rootbus_handle; 356 acpi_handle rootbus_handle;
351 unsigned long long segment; 357 unsigned long long segment;
352 acpi_status status; 358 acpi_status status;
359 struct acpi_buffer name_buffer = { ACPI_ALLOCATE_BUFFER, NULL };
353 360
354 rootbus_handle = PCI_CONTROLLER(dev)->acpi_handle; 361 rootbus_handle = PCI_CONTROLLER(dev)->acpi_handle;
355 status = acpi_evaluate_integer(rootbus_handle, METHOD_NAME__SEG, NULL, 362 status = acpi_evaluate_integer(rootbus_handle, METHOD_NAME__SEG, NULL,
356 &segment); 363 &segment);
357 if (ACPI_SUCCESS(status)) { 364 if (ACPI_SUCCESS(status)) {
358 if (segment != pci_domain_nr(dev)) { 365 if (segment != pci_domain_nr(dev)) {
366 acpi_get_name(rootbus_handle, ACPI_FULL_PATHNAME,
367 &name_buffer);
359 printk(KERN_ERR 368 printk(KERN_ERR
360 "%s: Segment number mismatch, 0x%llx vs 0x%x for: ", 369 "%s: Segment number mismatch, 0x%llx vs 0x%x for: %s\n",
361 __func__, segment, pci_domain_nr(dev)); 370 __func__, segment, pci_domain_nr(dev),
362 acpi_ns_print_node_pathname(rootbus_handle, NULL); 371 (char *)name_buffer.pointer);
363 printk("\n"); 372 kfree(name_buffer.pointer);
364 return 1; 373 return 1;
365 } 374 }
366 } else { 375 } else {
367 printk(KERN_ERR "%s: Unable to get __SEG from: ", 376 acpi_get_name(rootbus_handle, ACPI_FULL_PATHNAME, &name_buffer);
368 __func__); 377 printk(KERN_ERR "%s: Unable to get __SEG from: %s\n",
369 acpi_ns_print_node_pathname(rootbus_handle, NULL); 378 __func__, (char *)name_buffer.pointer);
370 printk("\n"); 379 kfree(name_buffer.pointer);
371 return 1; 380 return 1;
372 } 381 }
373 382
diff --git a/arch/ia64/sn/kernel/io_common.c b/arch/ia64/sn/kernel/io_common.c
index 8a924a5661dd..0d4ffa4da1da 100644
--- a/arch/ia64/sn/kernel/io_common.c
+++ b/arch/ia64/sn/kernel/io_common.c
@@ -26,7 +26,6 @@
26#include <linux/acpi.h> 26#include <linux/acpi.h>
27#include <asm/sn/sn2/sn_hwperf.h> 27#include <asm/sn/sn2/sn_hwperf.h>
28#include <asm/sn/acpi.h> 28#include <asm/sn/acpi.h>
29#include "acpi/acglobal.h"
30 29
31extern void sn_init_cpei_timer(void); 30extern void sn_init_cpei_timer(void);
32extern void register_sn_procfs(void); 31extern void register_sn_procfs(void);
@@ -473,7 +472,7 @@ sn_io_early_init(void)
473 { 472 {
474 struct acpi_table_header *header = NULL; 473 struct acpi_table_header *header = NULL;
475 474
476 acpi_get_table_by_index(ACPI_TABLE_INDEX_DSDT, &header); 475 acpi_get_table(ACPI_SIG_DSDT, 1, &header);
477 BUG_ON(header == NULL); 476 BUG_ON(header == NULL);
478 sn_acpi_rev = header->oem_revision; 477 sn_acpi_rev = header->oem_revision;
479 } 478 }
@@ -505,7 +504,7 @@ sn_io_early_init(void)
505 504
506 { 505 {
507 struct acpi_table_header *header; 506 struct acpi_table_header *header;
508 (void)acpi_get_table_by_index(ACPI_TABLE_INDEX_DSDT, &header); 507 (void)acpi_get_table(ACPI_SIG_DSDT, 1, &header);
509 printk(KERN_INFO "ACPI DSDT OEM Rev 0x%x\n", 508 printk(KERN_INFO "ACPI DSDT OEM Rev 0x%x\n",
510 header->oem_revision); 509 header->oem_revision);
511 } 510 }
diff --git a/arch/m68k/amiga/amiints.c b/arch/m68k/amiga/amiints.c
index 907a5533c845..c5b5212cc3f9 100644
--- a/arch/m68k/amiga/amiints.c
+++ b/arch/m68k/amiga/amiints.c
@@ -72,10 +72,14 @@ static struct irq_controller amiga_irq_controller = {
72 72
73void __init amiga_init_IRQ(void) 73void __init amiga_init_IRQ(void)
74{ 74{
75 request_irq(IRQ_AUTO_1, ami_int1, 0, "int1", NULL); 75 if (request_irq(IRQ_AUTO_1, ami_int1, 0, "int1", NULL))
76 request_irq(IRQ_AUTO_3, ami_int3, 0, "int3", NULL); 76 pr_err("Couldn't register int%d\n", 1);
77 request_irq(IRQ_AUTO_4, ami_int4, 0, "int4", NULL); 77 if (request_irq(IRQ_AUTO_3, ami_int3, 0, "int3", NULL))
78 request_irq(IRQ_AUTO_5, ami_int5, 0, "int5", NULL); 78 pr_err("Couldn't register int%d\n", 3);
79 if (request_irq(IRQ_AUTO_4, ami_int4, 0, "int4", NULL))
80 pr_err("Couldn't register int%d\n", 4);
81 if (request_irq(IRQ_AUTO_5, ami_int5, 0, "int5", NULL))
82 pr_err("Couldn't register int%d\n", 5);
79 83
80 m68k_setup_irq_controller(&amiga_irq_controller, IRQ_USER, AMI_STD_IRQS); 84 m68k_setup_irq_controller(&amiga_irq_controller, IRQ_USER, AMI_STD_IRQS);
81 85
diff --git a/arch/m68k/amiga/cia.c b/arch/m68k/amiga/cia.c
index 343fab49bd9a..ecd0f7ca6f0e 100644
--- a/arch/m68k/amiga/cia.c
+++ b/arch/m68k/amiga/cia.c
@@ -176,5 +176,7 @@ void __init cia_init_IRQ(struct ciabase *base)
176 /* override auto int and install CIA handler */ 176 /* override auto int and install CIA handler */
177 m68k_setup_irq_controller(&auto_irq_controller, base->handler_irq, 1); 177 m68k_setup_irq_controller(&auto_irq_controller, base->handler_irq, 1);
178 m68k_irq_startup(base->handler_irq); 178 m68k_irq_startup(base->handler_irq);
179 request_irq(base->handler_irq, cia_handler, IRQF_SHARED, base->name, base); 179 if (request_irq(base->handler_irq, cia_handler, IRQF_SHARED,
180 base->name, base))
181 pr_err("Couldn't register %s interrupt\n", base->name);
180} 182}
diff --git a/arch/m68k/amiga/config.c b/arch/m68k/amiga/config.c
index ab9862c3a136..6e562751ad51 100644
--- a/arch/m68k/amiga/config.c
+++ b/arch/m68k/amiga/config.c
@@ -493,7 +493,8 @@ static void __init amiga_sched_init(irq_handler_t timer_routine)
493 * Please don't change this to use ciaa, as it interferes with the 493 * Please don't change this to use ciaa, as it interferes with the
494 * SCSI code. We'll have to take a look at this later 494 * SCSI code. We'll have to take a look at this later
495 */ 495 */
496 request_irq(IRQ_AMIGA_CIAB_TA, timer_routine, 0, "timer", NULL); 496 if (request_irq(IRQ_AMIGA_CIAB_TA, timer_routine, 0, "timer", NULL))
497 pr_err("Couldn't register timer interrupt\n");
497 /* start timer */ 498 /* start timer */
498 ciab.cra |= 0x11; 499 ciab.cra |= 0x11;
499} 500}
diff --git a/arch/m68k/apollo/config.c b/arch/m68k/apollo/config.c
index 78df98f2029a..8d3eafab1ffe 100644
--- a/arch/m68k/apollo/config.c
+++ b/arch/m68k/apollo/config.c
@@ -31,10 +31,6 @@ extern unsigned long dn_gettimeoffset(void);
31extern int dn_dummy_hwclk(int, struct rtc_time *); 31extern int dn_dummy_hwclk(int, struct rtc_time *);
32extern int dn_dummy_set_clock_mmss(unsigned long); 32extern int dn_dummy_set_clock_mmss(unsigned long);
33extern void dn_dummy_reset(void); 33extern void dn_dummy_reset(void);
34extern void dn_dummy_waitbut(void);
35extern struct fb_info *dn_fb_init(long *);
36extern void dn_dummy_debug_init(void);
37extern irqreturn_t dn_process_int(int irq, struct pt_regs *fp);
38#ifdef CONFIG_HEARTBEAT 34#ifdef CONFIG_HEARTBEAT
39static void dn_heartbeat(int on); 35static void dn_heartbeat(int on);
40#endif 36#endif
@@ -204,7 +200,8 @@ void dn_sched_init(irq_handler_t timer_routine)
204 printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3)); 200 printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3));
205#endif 201#endif
206 202
207 request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine); 203 if (request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine))
204 pr_err("Couldn't register timer interrupt\n");
208} 205}
209 206
210unsigned long dn_gettimeoffset(void) { 207unsigned long dn_gettimeoffset(void) {
diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c
index c038b7c7eff0..a5f33c059979 100644
--- a/arch/m68k/atari/atakeyb.c
+++ b/arch/m68k/atari/atakeyb.c
@@ -33,7 +33,6 @@
33#include <asm/atari_joystick.h> 33#include <asm/atari_joystick.h>
34#include <asm/irq.h> 34#include <asm/irq.h>
35 35
36extern unsigned int keymap_count;
37 36
38/* Hook for MIDI serial driver */ 37/* Hook for MIDI serial driver */
39void (*atari_MIDI_interrupt_hook) (void); 38void (*atari_MIDI_interrupt_hook) (void);
@@ -567,14 +566,19 @@ static int atari_keyb_done = 0;
567 566
568int atari_keyb_init(void) 567int atari_keyb_init(void)
569{ 568{
569 int error;
570
570 if (atari_keyb_done) 571 if (atari_keyb_done)
571 return 0; 572 return 0;
572 573
573 kb_state.state = KEYBOARD; 574 kb_state.state = KEYBOARD;
574 kb_state.len = 0; 575 kb_state.len = 0;
575 576
576 request_irq(IRQ_MFP_ACIA, atari_keyboard_interrupt, IRQ_TYPE_SLOW, 577 error = request_irq(IRQ_MFP_ACIA, atari_keyboard_interrupt,
577 "keyboard/mouse/MIDI", atari_keyboard_interrupt); 578 IRQ_TYPE_SLOW, "keyboard/mouse/MIDI",
579 atari_keyboard_interrupt);
580 if (error)
581 return error;
578 582
579 atari_turnoff_irq(IRQ_MFP_ACIA); 583 atari_turnoff_irq(IRQ_MFP_ACIA);
580 do { 584 do {
diff --git a/arch/m68k/atari/stdma.c b/arch/m68k/atari/stdma.c
index d1bd029a34ac..604329fafbb8 100644
--- a/arch/m68k/atari/stdma.c
+++ b/arch/m68k/atari/stdma.c
@@ -179,8 +179,9 @@ EXPORT_SYMBOL(stdma_islocked);
179void __init stdma_init(void) 179void __init stdma_init(void)
180{ 180{
181 stdma_isr = NULL; 181 stdma_isr = NULL;
182 request_irq(IRQ_MFP_FDC, stdma_int, IRQ_TYPE_SLOW | IRQF_SHARED, 182 if (request_irq(IRQ_MFP_FDC, stdma_int, IRQ_TYPE_SLOW | IRQF_SHARED,
183 "ST-DMA: floppy/ACSI/IDE/Falcon-SCSI", stdma_int); 183 "ST-DMA: floppy/ACSI/IDE/Falcon-SCSI", stdma_int))
184 pr_err("Couldn't register ST-DMA interrupt\n");
184} 185}
185 186
186 187
diff --git a/arch/m68k/atari/time.c b/arch/m68k/atari/time.c
index 1edde27fa32d..d076ff8d1b39 100644
--- a/arch/m68k/atari/time.c
+++ b/arch/m68k/atari/time.c
@@ -31,8 +31,9 @@ atari_sched_init(irq_handler_t timer_routine)
31 /* start timer C, div = 1:100 */ 31 /* start timer C, div = 1:100 */
32 mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60; 32 mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60;
33 /* install interrupt service routine for MFP Timer C */ 33 /* install interrupt service routine for MFP Timer C */
34 request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW, 34 if (request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW,
35 "timer", timer_routine); 35 "timer", timer_routine))
36 pr_err("Couldn't register timer interrupt\n");
36} 37}
37 38
38/* ++andreas: gettimeoffset fixed to check for pending interrupt */ 39/* ++andreas: gettimeoffset fixed to check for pending interrupt */
diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c
index c072595928c0..9fe6fefb5e14 100644
--- a/arch/m68k/bvme6000/config.c
+++ b/arch/m68k/bvme6000/config.c
@@ -43,7 +43,6 @@ extern unsigned long bvme6000_gettimeoffset (void);
43extern int bvme6000_hwclk (int, struct rtc_time *); 43extern int bvme6000_hwclk (int, struct rtc_time *);
44extern int bvme6000_set_clock_mmss (unsigned long); 44extern int bvme6000_set_clock_mmss (unsigned long);
45extern void bvme6000_reset (void); 45extern void bvme6000_reset (void);
46extern void bvme6000_waitbut(void);
47void bvme6000_set_vectors (void); 46void bvme6000_set_vectors (void);
48 47
49/* Save tick handler routine pointer, will point to do_timer() in 48/* Save tick handler routine pointer, will point to do_timer() in
diff --git a/arch/m68k/hp300/time.c b/arch/m68k/hp300/time.c
index dd7c8a2583d3..f6312c7d8727 100644
--- a/arch/m68k/hp300/time.c
+++ b/arch/m68k/hp300/time.c
@@ -70,7 +70,8 @@ void __init hp300_sched_init(irq_handler_t vector)
70 70
71 asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE)); 71 asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE));
72 72
73 request_irq(IRQ_AUTO_6, hp300_tick, IRQ_FLG_STD, "timer tick", vector); 73 if (request_irq(IRQ_AUTO_6, hp300_tick, IRQ_FLG_STD, "timer tick", vector))
74 pr_err("Couldn't register timer interrupt\n");
74 75
75 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ 76 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */
76 out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ 77 out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */
diff --git a/arch/m68k/kernel/.gitignore b/arch/m68k/kernel/.gitignore
new file mode 100644
index 000000000000..c5f676c3c224
--- /dev/null
+++ b/arch/m68k/kernel/.gitignore
@@ -0,0 +1 @@
vmlinux.lds
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index f28404d9a2bc..5b780826647c 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -424,7 +424,7 @@ resume:
424.data 424.data
425ALIGN 425ALIGN
426sys_call_table: 426sys_call_table:
427 .long sys_ni_syscall /* 0 - old "setup()" system call*/ 427 .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */
428 .long sys_exit 428 .long sys_exit
429 .long sys_fork 429 .long sys_fork
430 .long sys_read 430 .long sys_read
diff --git a/arch/m68k/kernel/setup.c b/arch/m68k/kernel/setup.c
index 4d97bd2bd573..303730afb1c9 100644
--- a/arch/m68k/kernel/setup.c
+++ b/arch/m68k/kernel/setup.c
@@ -26,6 +26,7 @@
26#include <linux/initrd.h> 26#include <linux/initrd.h>
27 27
28#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
29#include <asm/sections.h>
29#include <asm/setup.h> 30#include <asm/setup.h>
30#include <asm/fpu.h> 31#include <asm/fpu.h>
31#include <asm/irq.h> 32#include <asm/irq.h>
@@ -62,7 +63,6 @@ EXPORT_SYMBOL(vme_brdtype);
62int m68k_is040or060; 63int m68k_is040or060;
63EXPORT_SYMBOL(m68k_is040or060); 64EXPORT_SYMBOL(m68k_is040or060);
64 65
65extern int end;
66extern unsigned long availmem; 66extern unsigned long availmem;
67 67
68int m68k_num_memory; 68int m68k_num_memory;
@@ -215,11 +215,10 @@ static void __init m68k_parse_bootinfo(const struct bi_record *record)
215 215
216void __init setup_arch(char **cmdline_p) 216void __init setup_arch(char **cmdline_p)
217{ 217{
218 extern int _etext, _edata, _end;
219 int i; 218 int i;
220 219
221 /* The bootinfo is located right after the kernel bss */ 220 /* The bootinfo is located right after the kernel bss */
222 m68k_parse_bootinfo((const struct bi_record *)&_end); 221 m68k_parse_bootinfo((const struct bi_record *)_end);
223 222
224 if (CPU_IS_040) 223 if (CPU_IS_040)
225 m68k_is040or060 = 4; 224 m68k_is040or060 = 4;
@@ -252,9 +251,9 @@ void __init setup_arch(char **cmdline_p)
252 } 251 }
253 252
254 init_mm.start_code = PAGE_OFFSET; 253 init_mm.start_code = PAGE_OFFSET;
255 init_mm.end_code = (unsigned long) &_etext; 254 init_mm.end_code = (unsigned long)_etext;
256 init_mm.end_data = (unsigned long) &_edata; 255 init_mm.end_data = (unsigned long)_edata;
257 init_mm.brk = (unsigned long) &_end; 256 init_mm.brk = (unsigned long)_end;
258 257
259 *cmdline_p = m68k_command_line; 258 *cmdline_p = m68k_command_line;
260 memcpy(boot_command_line, *cmdline_p, CL_SIZE); 259 memcpy(boot_command_line, *cmdline_p, CL_SIZE);
diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c
index f9af893cd289..de2d05ddd86d 100644
--- a/arch/m68k/kernel/signal.c
+++ b/arch/m68k/kernel/signal.c
@@ -326,6 +326,9 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __u
326 struct sigcontext context; 326 struct sigcontext context;
327 int err; 327 int err;
328 328
329 /* Always make any pending restarted system calls return -EINTR */
330 current_thread_info()->restart_block.fn = do_no_restart_syscall;
331
329 /* get previous context */ 332 /* get previous context */
330 if (copy_from_user(&context, usc, sizeof(context))) 333 if (copy_from_user(&context, usc, sizeof(context)))
331 goto badframe; 334 goto badframe;
@@ -411,6 +414,9 @@ rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
411 unsigned long usp; 414 unsigned long usp;
412 int err; 415 int err;
413 416
417 /* Always make any pending restarted system calls return -EINTR */
418 current_thread_info()->restart_block.fn = do_no_restart_syscall;
419
414 err = __get_user(temp, &uc->uc_mcontext.version); 420 err = __get_user(temp, &uc->uc_mcontext.version);
415 if (temp != MCONTEXT_VERSION) 421 if (temp != MCONTEXT_VERSION)
416 goto badframe; 422 goto badframe;
@@ -937,6 +943,15 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
937 regs->d0 = -EINTR; 943 regs->d0 = -EINTR;
938 break; 944 break;
939 945
946 case -ERESTART_RESTARTBLOCK:
947 if (!has_handler) {
948 regs->d0 = __NR_restart_syscall;
949 regs->pc -= 2;
950 break;
951 }
952 regs->d0 = -EINTR;
953 break;
954
940 case -ERESTARTSYS: 955 case -ERESTARTSYS:
941 if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) { 956 if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
942 regs->d0 = -EINTR; 957 regs->d0 = -EINTR;
diff --git a/arch/m68k/kernel/vmlinux-sun3.lds b/arch/m68k/kernel/vmlinux-sun3.lds
index 8a4919e4d36a..d9368c0709ba 100644
--- a/arch/m68k/kernel/vmlinux-sun3.lds
+++ b/arch/m68k/kernel/vmlinux-sun3.lds
@@ -33,6 +33,7 @@ SECTIONS
33 } :data 33 } :data
34 /* End of data goes *here* so that freeing init code works properly. */ 34 /* End of data goes *here* so that freeing init code works properly. */
35 _edata = .; 35 _edata = .;
36 NOTES
36 37
37 /* will be freed after init */ 38 /* will be freed after init */
38 . = ALIGN(PAGE_SIZE); /* Init code and data */ 39 . = ALIGN(PAGE_SIZE); /* Init code and data */
diff --git a/arch/m68k/mac/baboon.c b/arch/m68k/mac/baboon.c
index 245d16d078ad..2a96bebd8969 100644
--- a/arch/m68k/mac/baboon.c
+++ b/arch/m68k/mac/baboon.c
@@ -92,7 +92,8 @@ static irqreturn_t baboon_irq(int irq, void *dev_id)
92void __init baboon_register_interrupts(void) 92void __init baboon_register_interrupts(void)
93{ 93{
94 baboon_disabled = 0; 94 baboon_disabled = 0;
95 request_irq(IRQ_NUBUS_C, baboon_irq, 0, "baboon", (void *)baboon); 95 if (request_irq(IRQ_NUBUS_C, baboon_irq, 0, "baboon", (void *)baboon))
96 pr_err("Couldn't register baboon interrupt\n");
96} 97}
97 98
98/* 99/*
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
index 8819b97be324..98b6bcfb37bf 100644
--- a/arch/m68k/mac/config.c
+++ b/arch/m68k/mac/config.c
@@ -47,13 +47,6 @@
47 47
48struct mac_booter_data mac_bi_data; 48struct mac_booter_data mac_bi_data;
49 49
50/* New m68k bootinfo stuff and videobase */
51
52extern int m68k_num_memory;
53extern struct mem_info m68k_memory[NUM_MEMINFO];
54
55extern struct mem_info m68k_ramdisk;
56
57/* The phys. video addr. - might be bogus on some machines */ 50/* The phys. video addr. - might be bogus on some machines */
58static unsigned long mac_orig_videoaddr; 51static unsigned long mac_orig_videoaddr;
59 52
@@ -61,7 +54,6 @@ static unsigned long mac_orig_videoaddr;
61extern unsigned long mac_gettimeoffset(void); 54extern unsigned long mac_gettimeoffset(void);
62extern int mac_hwclk(int, struct rtc_time *); 55extern int mac_hwclk(int, struct rtc_time *);
63extern int mac_set_clock_mmss(unsigned long); 56extern int mac_set_clock_mmss(unsigned long);
64extern int show_mac_interrupts(struct seq_file *, void *);
65extern void iop_preinit(void); 57extern void iop_preinit(void);
66extern void iop_init(void); 58extern void iop_init(void);
67extern void via_init(void); 59extern void via_init(void);
@@ -805,10 +797,6 @@ static void __init mac_identify(void)
805 mac_bi_data.boottime, mac_bi_data.gmtbias); 797 mac_bi_data.boottime, mac_bi_data.gmtbias);
806 printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n", 798 printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n",
807 mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize); 799 mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize);
808#if 0
809 printk("Ramdisk: addr 0x%lx size 0x%lx\n",
810 m68k_ramdisk.addr, m68k_ramdisk.size);
811#endif
812 800
813 iop_init(); 801 iop_init();
814 via_init(); 802 via_init();
diff --git a/arch/m68k/mac/debug.c b/arch/m68k/mac/debug.c
index 65dd77a742a3..bce074ceb768 100644
--- a/arch/m68k/mac/debug.c
+++ b/arch/m68k/mac/debug.c
@@ -27,7 +27,6 @@
27#include <asm/macints.h> 27#include <asm/macints.h>
28 28
29extern unsigned long mac_videobase; 29extern unsigned long mac_videobase;
30extern unsigned long mac_videodepth;
31extern unsigned long mac_rowbytes; 30extern unsigned long mac_rowbytes;
32 31
33extern void mac_serial_print(const char *); 32extern void mac_serial_print(const char *);
diff --git a/arch/m68k/mac/iop.c b/arch/m68k/mac/iop.c
index 326fb9978094..1ad4e9d80eba 100644
--- a/arch/m68k/mac/iop.c
+++ b/arch/m68k/mac/iop.c
@@ -305,14 +305,16 @@ void __init iop_register_interrupts(void)
305{ 305{
306 if (iop_ism_present) { 306 if (iop_ism_present) {
307 if (oss_present) { 307 if (oss_present) {
308 request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, 308 if (request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq,
309 IRQ_FLG_LOCK, "ISM IOP", 309 IRQ_FLG_LOCK, "ISM IOP",
310 (void *) IOP_NUM_ISM); 310 (void *) IOP_NUM_ISM))
311 pr_err("Couldn't register ISM IOP interrupt\n");
311 oss_irq_enable(IRQ_MAC_ADB); 312 oss_irq_enable(IRQ_MAC_ADB);
312 } else { 313 } else {
313 request_irq(IRQ_VIA2_0, iop_ism_irq, 314 if (request_irq(IRQ_VIA2_0, iop_ism_irq,
314 IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP", 315 IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP",
315 (void *) IOP_NUM_ISM); 316 (void *) IOP_NUM_ISM))
317 pr_err("Couldn't register ISM IOP interrupt\n");
316 } 318 }
317 if (!iop_alive(iop_base[IOP_NUM_ISM])) { 319 if (!iop_alive(iop_base[IOP_NUM_ISM])) {
318 printk("IOP: oh my god, they killed the ISM IOP!\n"); 320 printk("IOP: oh my god, they killed the ISM IOP!\n");
diff --git a/arch/m68k/mac/macints.c b/arch/m68k/mac/macints.c
index 82e560c076ce..23711074e0e2 100644
--- a/arch/m68k/mac/macints.c
+++ b/arch/m68k/mac/macints.c
@@ -134,6 +134,7 @@
134#include <asm/errno.h> 134#include <asm/errno.h>
135#include <asm/macints.h> 135#include <asm/macints.h>
136#include <asm/irq_regs.h> 136#include <asm/irq_regs.h>
137#include <asm/mac_oss.h>
137 138
138#define DEBUG_SPURIOUS 139#define DEBUG_SPURIOUS
139#define SHUTUP_SONIC 140#define SHUTUP_SONIC
@@ -146,7 +147,6 @@ static int scc_mask;
146 * VIA/RBV hooks 147 * VIA/RBV hooks
147 */ 148 */
148 149
149extern void via_init(void);
150extern void via_register_interrupts(void); 150extern void via_register_interrupts(void);
151extern void via_irq_enable(int); 151extern void via_irq_enable(int);
152extern void via_irq_disable(int); 152extern void via_irq_disable(int);
@@ -157,9 +157,6 @@ extern int via_irq_pending(int);
157 * OSS hooks 157 * OSS hooks
158 */ 158 */
159 159
160extern int oss_present;
161
162extern void oss_init(void);
163extern void oss_register_interrupts(void); 160extern void oss_register_interrupts(void);
164extern void oss_irq_enable(int); 161extern void oss_irq_enable(int);
165extern void oss_irq_disable(int); 162extern void oss_irq_disable(int);
@@ -170,9 +167,6 @@ extern int oss_irq_pending(int);
170 * PSC hooks 167 * PSC hooks
171 */ 168 */
172 169
173extern int psc_present;
174
175extern void psc_init(void);
176extern void psc_register_interrupts(void); 170extern void psc_register_interrupts(void);
177extern void psc_irq_enable(int); 171extern void psc_irq_enable(int);
178extern void psc_irq_disable(int); 172extern void psc_irq_disable(int);
@@ -191,12 +185,10 @@ extern void iop_register_interrupts(void);
191 185
192extern int baboon_present; 186extern int baboon_present;
193 187
194extern void baboon_init(void);
195extern void baboon_register_interrupts(void); 188extern void baboon_register_interrupts(void);
196extern void baboon_irq_enable(int); 189extern void baboon_irq_enable(int);
197extern void baboon_irq_disable(int); 190extern void baboon_irq_disable(int);
198extern void baboon_irq_clear(int); 191extern void baboon_irq_clear(int);
199extern int baboon_irq_pending(int);
200 192
201/* 193/*
202 * SCC interrupt routines 194 * SCC interrupt routines
@@ -258,8 +250,9 @@ void __init mac_init_IRQ(void)
258 if (baboon_present) 250 if (baboon_present)
259 baboon_register_interrupts(); 251 baboon_register_interrupts();
260 iop_register_interrupts(); 252 iop_register_interrupts();
261 request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI", 253 if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI",
262 mac_nmi_handler); 254 mac_nmi_handler))
255 pr_err("Couldn't register NMI\n");
263#ifdef DEBUG_MACINTS 256#ifdef DEBUG_MACINTS
264 printk("mac_init_IRQ(): Done!\n"); 257 printk("mac_init_IRQ(): Done!\n");
265#endif 258#endif
diff --git a/arch/m68k/mac/misc.c b/arch/m68k/mac/misc.c
index a44c7086ab39..5d818568b343 100644
--- a/arch/m68k/mac/misc.c
+++ b/arch/m68k/mac/misc.c
@@ -35,7 +35,6 @@
35 35
36#define RTC_OFFSET 2082844800 36#define RTC_OFFSET 2082844800
37 37
38extern struct mac_booter_data mac_bi_data;
39static void (*rom_reset)(void); 38static void (*rom_reset)(void);
40 39
41#ifdef CONFIG_ADB_CUDA 40#ifdef CONFIG_ADB_CUDA
diff --git a/arch/m68k/mac/oss.c b/arch/m68k/mac/oss.c
index 8426501119ca..f3d23d6ebcf8 100644
--- a/arch/m68k/mac/oss.c
+++ b/arch/m68k/mac/oss.c
@@ -66,16 +66,21 @@ void __init oss_init(void)
66 66
67void __init oss_register_interrupts(void) 67void __init oss_register_interrupts(void)
68{ 68{
69 request_irq(OSS_IRQLEV_SCSI, oss_irq, IRQ_FLG_LOCK, 69 if (request_irq(OSS_IRQLEV_SCSI, oss_irq, IRQ_FLG_LOCK,
70 "scsi", (void *) oss); 70 "scsi", (void *) oss))
71 request_irq(OSS_IRQLEV_IOPSCC, mac_scc_dispatch, IRQ_FLG_LOCK, 71 pr_err("Couldn't register %s interrupt\n", "scsi");
72 "scc", mac_scc_dispatch); 72 if (request_irq(OSS_IRQLEV_IOPSCC, mac_scc_dispatch, IRQ_FLG_LOCK,
73 request_irq(OSS_IRQLEV_NUBUS, oss_nubus_irq, IRQ_FLG_LOCK, 73 "scc", mac_scc_dispatch))
74 "nubus", (void *) oss); 74 pr_err("Couldn't register %s interrupt\n", "scc");
75 request_irq(OSS_IRQLEV_SOUND, oss_irq, IRQ_FLG_LOCK, 75 if (request_irq(OSS_IRQLEV_NUBUS, oss_nubus_irq, IRQ_FLG_LOCK,
76 "sound", (void *) oss); 76 "nubus", (void *) oss))
77 request_irq(OSS_IRQLEV_VIA1, via1_irq, IRQ_FLG_LOCK, 77 pr_err("Couldn't register %s interrupt\n", "nubus");
78 "via1", (void *) via1); 78 if (request_irq(OSS_IRQLEV_SOUND, oss_irq, IRQ_FLG_LOCK,
79 "sound", (void *) oss))
80 pr_err("Couldn't register %s interrupt\n", "sound");
81 if (request_irq(OSS_IRQLEV_VIA1, via1_irq, IRQ_FLG_LOCK,
82 "via1", (void *) via1))
83 pr_err("Couldn't register %s interrupt\n", "via1");
79} 84}
80 85
81/* 86/*
diff --git a/arch/m68k/mac/psc.c b/arch/m68k/mac/psc.c
index f84a4dd64f94..ba6ccab64018 100644
--- a/arch/m68k/mac/psc.c
+++ b/arch/m68k/mac/psc.c
@@ -117,10 +117,14 @@ void __init psc_init(void)
117 117
118void __init psc_register_interrupts(void) 118void __init psc_register_interrupts(void)
119{ 119{
120 request_irq(IRQ_AUTO_3, psc_irq, 0, "psc3", (void *) 0x30); 120 if (request_irq(IRQ_AUTO_3, psc_irq, 0, "psc3", (void *) 0x30))
121 request_irq(IRQ_AUTO_4, psc_irq, 0, "psc4", (void *) 0x40); 121 pr_err("Couldn't register psc%d interrupt\n", 3);
122 request_irq(IRQ_AUTO_5, psc_irq, 0, "psc5", (void *) 0x50); 122 if (request_irq(IRQ_AUTO_4, psc_irq, 0, "psc4", (void *) 0x40))
123 request_irq(IRQ_AUTO_6, psc_irq, 0, "psc6", (void *) 0x60); 123 pr_err("Couldn't register psc%d interrupt\n", 4);
124 if (request_irq(IRQ_AUTO_5, psc_irq, 0, "psc5", (void *) 0x50))
125 pr_err("Couldn't register psc%d interrupt\n", 5);
126 if (request_irq(IRQ_AUTO_6, psc_irq, 0, "psc6", (void *) 0x60))
127 pr_err("Couldn't register psc%d interrupt\n", 6);
124} 128}
125 129
126/* 130/*
diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c
index f01d418e64fe..7d97ba54536e 100644
--- a/arch/m68k/mac/via.c
+++ b/arch/m68k/mac/via.c
@@ -34,6 +34,7 @@
34#include <asm/macints.h> 34#include <asm/macints.h>
35#include <asm/mac_via.h> 35#include <asm/mac_via.h>
36#include <asm/mac_psc.h> 36#include <asm/mac_psc.h>
37#include <asm/mac_oss.h>
37 38
38volatile __u8 *via1, *via2; 39volatile __u8 *via1, *via2;
39int rbv_present; 40int rbv_present;
@@ -84,7 +85,6 @@ void via_irq_disable(int irq);
84void via_irq_clear(int irq); 85void via_irq_clear(int irq);
85 86
86extern irqreturn_t mac_scc_dispatch(int, void *); 87extern irqreturn_t mac_scc_dispatch(int, void *);
87extern int oss_present;
88 88
89/* 89/*
90 * Initialize the VIAs 90 * Initialize the VIAs
@@ -283,7 +283,8 @@ void __init via_init_clock(irq_handler_t func)
283 via1[vT1CL] = MAC_CLOCK_LOW; 283 via1[vT1CL] = MAC_CLOCK_LOW;
284 via1[vT1CH] = MAC_CLOCK_HIGH; 284 via1[vT1CH] = MAC_CLOCK_HIGH;
285 285
286 request_irq(IRQ_MAC_TIMER_1, func, IRQ_FLG_LOCK, "timer", func); 286 if (request_irq(IRQ_MAC_TIMER_1, func, IRQ_FLG_LOCK, "timer", func))
287 pr_err("Couldn't register %s interrupt\n", "timer");
287} 288}
288 289
289/* 290/*
@@ -293,25 +294,31 @@ void __init via_init_clock(irq_handler_t func)
293void __init via_register_interrupts(void) 294void __init via_register_interrupts(void)
294{ 295{
295 if (via_alt_mapping) { 296 if (via_alt_mapping) {
296 request_irq(IRQ_AUTO_1, via1_irq, 297 if (request_irq(IRQ_AUTO_1, via1_irq,
297 IRQ_FLG_LOCK|IRQ_FLG_FAST, "software", 298 IRQ_FLG_LOCK|IRQ_FLG_FAST, "software",
298 (void *) via1); 299 (void *) via1))
299 request_irq(IRQ_AUTO_6, via1_irq, 300 pr_err("Couldn't register %s interrupt\n", "software");
301 if (request_irq(IRQ_AUTO_6, via1_irq,
300 IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", 302 IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1",
301 (void *) via1); 303 (void *) via1))
304 pr_err("Couldn't register %s interrupt\n", "via1");
302 } else { 305 } else {
303 request_irq(IRQ_AUTO_1, via1_irq, 306 if (request_irq(IRQ_AUTO_1, via1_irq,
304 IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1", 307 IRQ_FLG_LOCK|IRQ_FLG_FAST, "via1",
305 (void *) via1); 308 (void *) via1))
309 pr_err("Couldn't register %s interrupt\n", "via1");
306 } 310 }
307 request_irq(IRQ_AUTO_2, via2_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, 311 if (request_irq(IRQ_AUTO_2, via2_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST,
308 "via2", (void *) via2); 312 "via2", (void *) via2))
313 pr_err("Couldn't register %s interrupt\n", "via2");
309 if (!psc_present) { 314 if (!psc_present) {
310 request_irq(IRQ_AUTO_4, mac_scc_dispatch, IRQ_FLG_LOCK, 315 if (request_irq(IRQ_AUTO_4, mac_scc_dispatch, IRQ_FLG_LOCK,
311 "scc", mac_scc_dispatch); 316 "scc", mac_scc_dispatch))
317 pr_err("Couldn't register %s interrupt\n", "scc");
312 } 318 }
313 request_irq(IRQ_MAC_NUBUS, via_nubus_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST, 319 if (request_irq(IRQ_MAC_NUBUS, via_nubus_irq,
314 "nubus", (void *) via2); 320 IRQ_FLG_LOCK|IRQ_FLG_FAST, "nubus", (void *) via2))
321 pr_err("Couldn't register %s interrupt\n", "nubus");
315} 322}
316 323
317/* 324/*
diff --git a/arch/m68k/math-emu/fp_log.c b/arch/m68k/math-emu/fp_log.c
index b1033ae0d6f0..367ecee2f981 100644
--- a/arch/m68k/math-emu/fp_log.c
+++ b/arch/m68k/math-emu/fp_log.c
@@ -24,7 +24,6 @@ static const struct fp_ext fp_one =
24 24
25extern struct fp_ext *fp_fadd(struct fp_ext *dest, const struct fp_ext *src); 25extern struct fp_ext *fp_fadd(struct fp_ext *dest, const struct fp_ext *src);
26extern struct fp_ext *fp_fdiv(struct fp_ext *dest, const struct fp_ext *src); 26extern struct fp_ext *fp_fdiv(struct fp_ext *dest, const struct fp_ext *src);
27extern struct fp_ext *fp_fmul(struct fp_ext *dest, const struct fp_ext *src);
28 27
29struct fp_ext * 28struct fp_ext *
30fp_fsqrt(struct fp_ext *dest, struct fp_ext *src) 29fp_fsqrt(struct fp_ext *dest, struct fp_ext *src)
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 81bb08ceec18..0007b2adf3a3 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -28,6 +28,7 @@
28#ifdef CONFIG_ATARI 28#ifdef CONFIG_ATARI
29#include <asm/atari_stram.h> 29#include <asm/atari_stram.h>
30#endif 30#endif
31#include <asm/sections.h>
31#include <asm/tlb.h> 32#include <asm/tlb.h>
32 33
33DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 34DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -73,9 +74,6 @@ extern void init_pointer_table(unsigned long ptable);
73 74
74/* References to section boundaries */ 75/* References to section boundaries */
75 76
76extern char _text[], _etext[];
77extern char __init_begin[], __init_end[];
78
79extern pmd_t *zero_pgtable; 77extern pmd_t *zero_pgtable;
80 78
81void __init mem_init(void) 79void __init mem_init(void)
diff --git a/arch/m68k/mm/motorola.c b/arch/m68k/mm/motorola.c
index c5dbb9bdb322..4665fc84b7dc 100644
--- a/arch/m68k/mm/motorola.c
+++ b/arch/m68k/mm/motorola.c
@@ -30,6 +30,7 @@
30#ifdef CONFIG_ATARI 30#ifdef CONFIG_ATARI
31#include <asm/atari_stram.h> 31#include <asm/atari_stram.h>
32#endif 32#endif
33#include <asm/sections.h>
33 34
34#undef DEBUG 35#undef DEBUG
35 36
@@ -301,14 +302,12 @@ void __init paging_init(void)
301 } 302 }
302} 303}
303 304
304extern char __init_begin, __init_end;
305
306void free_initmem(void) 305void free_initmem(void)
307{ 306{
308 unsigned long addr; 307 unsigned long addr;
309 308
310 addr = (unsigned long)&__init_begin; 309 addr = (unsigned long)__init_begin;
311 for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) { 310 for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) {
312 virt_to_page(addr)->flags &= ~(1 << PG_reserved); 311 virt_to_page(addr)->flags &= ~(1 << PG_reserved);
313 init_page_count(virt_to_page(addr)); 312 init_page_count(virt_to_page(addr));
314 free_page(addr); 313 free_page(addr);
diff --git a/arch/m68k/mvme147/config.c b/arch/m68k/mvme147/config.c
index 43cdf476ffab..100baaa692a1 100644
--- a/arch/m68k/mvme147/config.c
+++ b/arch/m68k/mvme147/config.c
@@ -42,7 +42,6 @@ extern unsigned long mvme147_gettimeoffset (void);
42extern int mvme147_hwclk (int, struct rtc_time *); 42extern int mvme147_hwclk (int, struct rtc_time *);
43extern int mvme147_set_clock_mmss (unsigned long); 43extern int mvme147_set_clock_mmss (unsigned long);
44extern void mvme147_reset (void); 44extern void mvme147_reset (void);
45extern void mvme147_waitbut(void);
46 45
47 46
48static int bcd2int (unsigned char b); 47static int bcd2int (unsigned char b);
@@ -115,8 +114,9 @@ static irqreturn_t mvme147_timer_int (int irq, void *dev_id)
115void mvme147_sched_init (irq_handler_t timer_routine) 114void mvme147_sched_init (irq_handler_t timer_routine)
116{ 115{
117 tick_handler = timer_routine; 116 tick_handler = timer_routine;
118 request_irq (PCC_IRQ_TIMER1, mvme147_timer_int, 117 if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, IRQ_FLG_REPLACE,
119 IRQ_FLG_REPLACE, "timer 1", NULL); 118 "timer 1", NULL))
119 pr_err("Couldn't register timer interrupt\n");
120 120
121 /* Init the clock with a value */ 121 /* Init the clock with a value */
122 /* our clock goes off every 6.25us */ 122 /* our clock goes off every 6.25us */
diff --git a/arch/m68k/mvme16x/config.c b/arch/m68k/mvme16x/config.c
index 1521826fc3c7..11edf61cc2c4 100644
--- a/arch/m68k/mvme16x/config.c
+++ b/arch/m68k/mvme16x/config.c
@@ -48,7 +48,6 @@ extern unsigned long mvme16x_gettimeoffset (void);
48extern int mvme16x_hwclk (int, struct rtc_time *); 48extern int mvme16x_hwclk (int, struct rtc_time *);
49extern int mvme16x_set_clock_mmss (unsigned long); 49extern int mvme16x_set_clock_mmss (unsigned long);
50extern void mvme16x_reset (void); 50extern void mvme16x_reset (void);
51extern void mvme16x_waitbut(void);
52 51
53int bcd2int (unsigned char b); 52int bcd2int (unsigned char b);
54 53
diff --git a/arch/m68k/q40/config.c b/arch/m68k/q40/config.c
index 7110546e3c00..31ab3f08bbda 100644
--- a/arch/m68k/q40/config.c
+++ b/arch/m68k/q40/config.c
@@ -36,7 +36,6 @@
36#include <asm/machdep.h> 36#include <asm/machdep.h>
37#include <asm/q40_master.h> 37#include <asm/q40_master.h>
38 38
39extern irqreturn_t q40_process_int(int level, struct pt_regs *regs);
40extern void q40_init_IRQ(void); 39extern void q40_init_IRQ(void);
41static void q40_get_model(char *model); 40static void q40_get_model(char *model);
42extern void q40_sched_init(irq_handler_t handler); 41extern void q40_sched_init(irq_handler_t handler);
@@ -47,8 +46,6 @@ static unsigned int q40_get_ss(void);
47static int q40_set_clock_mmss(unsigned long); 46static int q40_set_clock_mmss(unsigned long);
48static int q40_get_rtc_pll(struct rtc_pll_info *pll); 47static int q40_get_rtc_pll(struct rtc_pll_info *pll);
49static int q40_set_rtc_pll(struct rtc_pll_info *pll); 48static int q40_set_rtc_pll(struct rtc_pll_info *pll);
50extern void q40_waitbut(void);
51void q40_set_vectors(void);
52 49
53extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); 50extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
54 51
diff --git a/arch/m68k/sun3/config.c b/arch/m68k/sun3/config.c
index 8dfaa201342e..2ca25bd01a96 100644
--- a/arch/m68k/sun3/config.c
+++ b/arch/m68k/sun3/config.c
@@ -27,23 +27,21 @@
27#include <asm/sun3mmu.h> 27#include <asm/sun3mmu.h>
28#include <asm/rtc.h> 28#include <asm/rtc.h>
29#include <asm/machdep.h> 29#include <asm/machdep.h>
30#include <asm/idprom.h>
30#include <asm/intersil.h> 31#include <asm/intersil.h>
31#include <asm/irq.h> 32#include <asm/irq.h>
33#include <asm/sections.h>
32#include <asm/segment.h> 34#include <asm/segment.h>
33#include <asm/sun3ints.h> 35#include <asm/sun3ints.h>
34 36
35extern char _text, _end;
36
37char sun3_reserved_pmeg[SUN3_PMEGS_NUM]; 37char sun3_reserved_pmeg[SUN3_PMEGS_NUM];
38 38
39extern unsigned long sun3_gettimeoffset(void); 39extern unsigned long sun3_gettimeoffset(void);
40static void sun3_sched_init(irq_handler_t handler); 40static void sun3_sched_init(irq_handler_t handler);
41extern void sun3_get_model (char* model); 41extern void sun3_get_model (char* model);
42extern void idprom_init (void);
43extern int sun3_hwclk(int set, struct rtc_time *t); 42extern int sun3_hwclk(int set, struct rtc_time *t);
44 43
45volatile char* clock_va; 44volatile char* clock_va;
46extern volatile unsigned char* sun3_intreg;
47extern unsigned long availmem; 45extern unsigned long availmem;
48unsigned long num_pages; 46unsigned long num_pages;
49 47
@@ -149,7 +147,7 @@ void __init config_sun3(void)
149 mach_halt = sun3_halt; 147 mach_halt = sun3_halt;
150 mach_get_hardware_list = sun3_get_hardware_list; 148 mach_get_hardware_list = sun3_get_hardware_list;
151 149
152 memory_start = ((((int)&_end) + 0x2000) & ~0x1fff); 150 memory_start = ((((unsigned long)_end) + 0x2000) & ~0x1fff);
153// PROM seems to want the last couple of physical pages. --m 151// PROM seems to want the last couple of physical pages. --m
154 memory_end = *(romvec->pv_sun3mem) + PAGE_OFFSET - 2*PAGE_SIZE; 152 memory_end = *(romvec->pv_sun3mem) + PAGE_OFFSET - 2*PAGE_SIZE;
155 153
diff --git a/arch/m68k/sun3/mmu_emu.c b/arch/m68k/sun3/mmu_emu.c
index 60f9d4500d72..3cd19390aae5 100644
--- a/arch/m68k/sun3/mmu_emu.c
+++ b/arch/m68k/sun3/mmu_emu.c
@@ -27,7 +27,6 @@
27#include <asm/mmu_context.h> 27#include <asm/mmu_context.h>
28#include <asm/dvma.h> 28#include <asm/dvma.h>
29 29
30extern void prom_reboot (char *) __attribute__ ((__noreturn__));
31 30
32#undef DEBUG_MMU_EMU 31#undef DEBUG_MMU_EMU
33#define DEBUG_PROM_MAPS 32#define DEBUG_PROM_MAPS
diff --git a/arch/m68k/sun3/sun3ints.c b/arch/m68k/sun3/sun3ints.c
index 7364cd67455e..ad90393a3361 100644
--- a/arch/m68k/sun3/sun3ints.c
+++ b/arch/m68k/sun3/sun3ints.c
@@ -105,7 +105,10 @@ void __init sun3_init_IRQ(void)
105 m68k_setup_irq_controller(&sun3_irq_controller, IRQ_AUTO_1, 7); 105 m68k_setup_irq_controller(&sun3_irq_controller, IRQ_AUTO_1, 7);
106 m68k_setup_user_interrupt(VEC_USER, 128, NULL); 106 m68k_setup_user_interrupt(VEC_USER, 128, NULL);
107 107
108 request_irq(IRQ_AUTO_5, sun3_int5, 0, "int5", NULL); 108 if (request_irq(IRQ_AUTO_5, sun3_int5, 0, "int5", NULL))
109 request_irq(IRQ_AUTO_7, sun3_int7, 0, "int7", NULL); 109 pr_err("Couldn't register %s interrupt\n", "int5");
110 request_irq(IRQ_USER+127, sun3_vec255, 0, "vec255", NULL); 110 if (request_irq(IRQ_AUTO_7, sun3_int7, 0, "int7", NULL))
111 pr_err("Couldn't register %s interrupt\n", "int7");
112 if (request_irq(IRQ_USER+127, sun3_vec255, 0, "vec255", NULL))
113 pr_err("Couldn't register %s interrupt\n", "vec255");
111} 114}
diff --git a/arch/m68k/sun3x/config.c b/arch/m68k/sun3x/config.c
index 2b1ca2db070f..fc599fad4a54 100644
--- a/arch/m68k/sun3x/config.c
+++ b/arch/m68k/sun3x/config.c
@@ -23,7 +23,6 @@
23#include "time.h" 23#include "time.h"
24 24
25volatile char *clock_va; 25volatile char *clock_va;
26extern volatile unsigned char *sun3_intreg;
27 26
28extern void sun3_get_model(char *model); 27extern void sun3_get_model(char *model);
29 28
diff --git a/arch/m68knommu/include/asm/mmu.h b/arch/m68knommu/include/asm/mmu.h
index 5fa6b68353ba..e2da1e6f09fe 100644
--- a/arch/m68knommu/include/asm/mmu.h
+++ b/arch/m68knommu/include/asm/mmu.h
@@ -4,7 +4,6 @@
4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */ 4/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
5 5
6typedef struct { 6typedef struct {
7 struct vm_list_struct *vmlist;
8 unsigned long end_brk; 7 unsigned long end_brk;
9} mm_context_t; 8} mm_context_t;
10 9
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a5255e7c79e0..52c80c2a57f2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -595,6 +595,44 @@ config WR_PPMC
595 This enables support for the Wind River MIPS32 4KC PPMC evaluation 595 This enables support for the Wind River MIPS32 4KC PPMC evaluation
596 board, which is based on GT64120 bridge chip. 596 board, which is based on GT64120 bridge chip.
597 597
598config CAVIUM_OCTEON_SIMULATOR
599 bool "Support for the Cavium Networks Octeon Simulator"
600 select CEVT_R4K
601 select 64BIT_PHYS_ADDR
602 select DMA_COHERENT
603 select SYS_SUPPORTS_64BIT_KERNEL
604 select SYS_SUPPORTS_BIG_ENDIAN
605 select SYS_SUPPORTS_HIGHMEM
606 select CPU_CAVIUM_OCTEON
607 help
608 The Octeon simulator is software performance model of the Cavium
609 Octeon Processor. It supports simulating Octeon processors on x86
610 hardware.
611
612config CAVIUM_OCTEON_REFERENCE_BOARD
613 bool "Support for the Cavium Networks Octeon reference board"
614 select CEVT_R4K
615 select 64BIT_PHYS_ADDR
616 select DMA_COHERENT
617 select SYS_SUPPORTS_64BIT_KERNEL
618 select SYS_SUPPORTS_BIG_ENDIAN
619 select SYS_SUPPORTS_HIGHMEM
620 select SYS_HAS_EARLY_PRINTK
621 select CPU_CAVIUM_OCTEON
622 select SWAP_IO_SPACE
623 help
624 This option supports all of the Octeon reference boards from Cavium
625 Networks. It builds a kernel that dynamically determines the Octeon
626 CPU type and supports all known board reference implementations.
627 Some of the supported boards are:
628 EBT3000
629 EBH3000
630 EBH3100
631 Thunder
632 Kodama
633 Hikari
634 Say Y here for most Octeon reference boards.
635
598endchoice 636endchoice
599 637
600source "arch/mips/alchemy/Kconfig" 638source "arch/mips/alchemy/Kconfig"
@@ -607,6 +645,7 @@ source "arch/mips/sgi-ip27/Kconfig"
607source "arch/mips/sibyte/Kconfig" 645source "arch/mips/sibyte/Kconfig"
608source "arch/mips/txx9/Kconfig" 646source "arch/mips/txx9/Kconfig"
609source "arch/mips/vr41xx/Kconfig" 647source "arch/mips/vr41xx/Kconfig"
648source "arch/mips/cavium-octeon/Kconfig"
610 649
611endmenu 650endmenu
612 651
@@ -682,7 +721,11 @@ config CEVT_DS1287
682config CEVT_GT641XX 721config CEVT_GT641XX
683 bool 722 bool
684 723
724config CEVT_R4K_LIB
725 bool
726
685config CEVT_R4K 727config CEVT_R4K
728 select CEVT_R4K_LIB
686 bool 729 bool
687 730
688config CEVT_SB1250 731config CEVT_SB1250
@@ -697,7 +740,11 @@ config CSRC_BCM1480
697config CSRC_IOASIC 740config CSRC_IOASIC
698 bool 741 bool
699 742
743config CSRC_R4K_LIB
744 bool
745
700config CSRC_R4K 746config CSRC_R4K
747 select CSRC_R4K_LIB
701 bool 748 bool
702 749
703config CSRC_SB1250 750config CSRC_SB1250
@@ -835,6 +882,9 @@ config IRQ_GT641XX
835config IRQ_GIC 882config IRQ_GIC
836 bool 883 bool
837 884
885config IRQ_CPU_OCTEON
886 bool
887
838config MIPS_BOARDS_GEN 888config MIPS_BOARDS_GEN
839 bool 889 bool
840 890
@@ -924,7 +974,7 @@ config BOOT_ELF32
924config MIPS_L1_CACHE_SHIFT 974config MIPS_L1_CACHE_SHIFT
925 int 975 int
926 default "4" if MACH_DECSTATION || MIKROTIK_RB532 976 default "4" if MACH_DECSTATION || MIKROTIK_RB532
927 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM 977 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
928 default "4" if PMC_MSP4200_EVAL 978 default "4" if PMC_MSP4200_EVAL
929 default "5" 979 default "5"
930 980
@@ -1185,6 +1235,23 @@ config CPU_SB1
1185 select CPU_SUPPORTS_HIGHMEM 1235 select CPU_SUPPORTS_HIGHMEM
1186 select WEAK_ORDERING 1236 select WEAK_ORDERING
1187 1237
1238config CPU_CAVIUM_OCTEON
1239 bool "Cavium Octeon processor"
1240 select IRQ_CPU
1241 select IRQ_CPU_OCTEON
1242 select CPU_HAS_PREFETCH
1243 select CPU_SUPPORTS_64BIT_KERNEL
1244 select SYS_SUPPORTS_SMP
1245 select NR_CPUS_DEFAULT_16
1246 select WEAK_ORDERING
1247 select WEAK_REORDERING_BEYOND_LLSC
1248 select CPU_SUPPORTS_HIGHMEM
1249 help
1250 The Cavium Octeon processor is a highly integrated chip containing
1251 many ethernet hardware widgets for networking tasks. The processor
1252 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1253 Full details can be found at http://www.caviumnetworks.com.
1254
1188endchoice 1255endchoice
1189 1256
1190config SYS_HAS_CPU_LOONGSON2 1257config SYS_HAS_CPU_LOONGSON2
@@ -1285,7 +1352,7 @@ config CPU_MIPSR1
1285 1352
1286config CPU_MIPSR2 1353config CPU_MIPSR2
1287 bool 1354 bool
1288 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 1355 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1289 1356
1290config SYS_SUPPORTS_32BIT_KERNEL 1357config SYS_SUPPORTS_32BIT_KERNEL
1291 bool 1358 bool
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 28c55f608913..21b00e95daef 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -144,6 +144,10 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
144cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap 144cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
145cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ 145cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
146 -Wa,--trap 146 -Wa,--trap
147cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
148ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
149cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
150endif
147 151
148cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) 152cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
149cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) 153cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
@@ -184,84 +188,84 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
184# 188#
185# AMD Alchemy Pb1000 eval board 189# AMD Alchemy Pb1000 eval board
186# 190#
187libs-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/pb1000/ 191core-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/devboards/
188cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 192cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
189load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 193load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
190 194
191# 195#
192# AMD Alchemy Pb1100 eval board 196# AMD Alchemy Pb1100 eval board
193# 197#
194libs-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/pb1100/ 198core-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/devboards/
195cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 199cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
196load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 200load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
197 201
198# 202#
199# AMD Alchemy Pb1500 eval board 203# AMD Alchemy Pb1500 eval board
200# 204#
201libs-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/pb1500/ 205core-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/devboards/
202cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 206cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
203load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 207load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
204 208
205# 209#
206# AMD Alchemy Pb1550 eval board 210# AMD Alchemy Pb1550 eval board
207# 211#
208libs-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/pb1550/ 212core-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/devboards/
209cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 213cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
210load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 214load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
211 215
212# 216#
213# AMD Alchemy Pb1200 eval board 217# AMD Alchemy Pb1200 eval board
214# 218#
215libs-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/pb1200/ 219core-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/devboards/
216cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 220cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
217load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 221load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
218 222
219# 223#
220# AMD Alchemy Db1000 eval board 224# AMD Alchemy Db1000 eval board
221# 225#
222libs-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/db1x00/ 226core-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/devboards/
223cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 227cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
224load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 228load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
225 229
226# 230#
227# AMD Alchemy Db1100 eval board 231# AMD Alchemy Db1100 eval board
228# 232#
229libs-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/db1x00/ 233core-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/devboards/
230cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 234cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
231load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 235load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
232 236
233# 237#
234# AMD Alchemy Db1500 eval board 238# AMD Alchemy Db1500 eval board
235# 239#
236libs-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/db1x00/ 240core-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/devboards/
237cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 241cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
238load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 242load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
239 243
240# 244#
241# AMD Alchemy Db1550 eval board 245# AMD Alchemy Db1550 eval board
242# 246#
243libs-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/db1x00/ 247core-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/devboards/
244cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 248cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
245load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 249load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
246 250
247# 251#
248# AMD Alchemy Db1200 eval board 252# AMD Alchemy Db1200 eval board
249# 253#
250libs-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/pb1200/ 254core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/
251cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 255cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
252load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 256load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
253 257
254# 258#
255# AMD Alchemy Bosporus eval board 259# AMD Alchemy Bosporus eval board
256# 260#
257libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/db1x00/ 261core-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/devboards/
258cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 262cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
259load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 263load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
260 264
261# 265#
262# AMD Alchemy Mirage eval board 266# AMD Alchemy Mirage eval board
263# 267#
264libs-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/db1x00/ 268core-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/devboards/
265cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 269cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
266load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 270load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000
267 271
@@ -586,6 +590,18 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
586core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ 590core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
587core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/ 591core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
588 592
593#
594# Cavium Octeon
595#
596core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/
597cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
598core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/executive/
599ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
600load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
601else
602load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
603endif
604
589cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 605cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
590drivers-$(CONFIG_PCI) += arch/mips/pci/ 606drivers-$(CONFIG_PCI) += arch/mips/pci/
591 607
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index e4a057d80ab6..7f8ef13d0014 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -128,9 +128,10 @@ config SOC_AU1200
128config SOC_AU1X00 128config SOC_AU1X00
129 bool 129 bool
130 select 64BIT_PHYS_ADDR 130 select 64BIT_PHYS_ADDR
131 select CEVT_R4K 131 select CEVT_R4K_LIB
132 select CSRC_R4K 132 select CSRC_R4K_LIB
133 select IRQ_CPU 133 select IRQ_CPU
134 select SYS_HAS_CPU_MIPS32_R1 134 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 135 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 136 select SYS_SUPPORTS_APM_EMULATION
137 select GENERIC_HARDIRQS_NO__DO_IRQ
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index df48fd65bbf3..d50d4764eafe 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,8 +6,8 @@
6# 6#
7 7
8obj-y += prom.o irq.o puts.o time.o reset.o \ 8obj-y += prom.o irq.o puts.o time.o reset.o \
9 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ 9 clocks.o platform.o power.o setup.o \
10 sleeper.o cputable.o dma.o dbdma.o gpio.o 10 sleeper.o dma.o dbdma.o gpio.o
11 11
12obj-$(CONFIG_PCI) += pci.o 12obj-$(CONFIG_PCI) += pci.o
13 13
diff --git a/arch/mips/alchemy/common/au1xxx_irqmap.c b/arch/mips/alchemy/common/au1xxx_irqmap.c
deleted file mode 100644
index c7ca1596394c..000000000000
--- a/arch/mips/alchemy/common/au1xxx_irqmap.c
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx processor specific IRQ tables
4 *
5 * Copyright 2004 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#include <linux/init.h>
29#include <linux/kernel.h>
30
31#include <au1000.h>
32
33/* The IC0 interrupt table. This is processor, rather than
34 * board dependent, so no reason to keep this info in the board
35 * dependent files.
36 *
37 * Careful if you change match 2 request!
38 * The interrupt handler is called directly from the low level dispatch code.
39 */
40struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
41
42#if defined(CONFIG_SOC_AU1000)
43 { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
44 { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
45 { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 },
46 { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
47 { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
48 { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
49 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
50 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
51 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
52 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
53 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
54 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
55 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
56 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
57 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
58 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
59 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
60 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
61 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
62 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
63 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
64 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
65 { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
66 { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
67 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
68 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
69 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
70 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
71 { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
72 { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
73 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
74
75#elif defined(CONFIG_SOC_AU1500)
76
77 { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
78 { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
79 { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
80 { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
81 { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
82 { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
83 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
84 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
85 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
86 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
87 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
88 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
89 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
90 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
91 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
92 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
93 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
94 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
95 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
96 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
97 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
98 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
99 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
100 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
101 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
102 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
103 { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
104 { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
105 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
106
107#elif defined(CONFIG_SOC_AU1100)
108
109 { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
110 { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
111 { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
112 { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
113 { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
114 { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
115 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
116 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
117 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
118 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
119 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
120 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
121 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
122 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
123 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
124 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
125 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
126 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
127 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
128 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
129 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
130 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
131 { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
132 { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
133 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
134 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
135 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
136 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
137 { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
138 /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */
139 { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
140 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
141
142#elif defined(CONFIG_SOC_AU1550)
143
144 { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
145 { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
146 { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
147 { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
148 { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 },
149 { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
150 { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
151 { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },
152 { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
153 { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
154 { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
155 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
156 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 },
157 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 },
158 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
159 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
160 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
161 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
162 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
163 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
164 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
165 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
166 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 },
167 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
168 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
169 { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
170 { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
171 { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
172
173#elif defined(CONFIG_SOC_AU1200)
174
175 { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
176 { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },
177 { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
178 { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
179 { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },
180 { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
181 { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },
182 { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
183 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
184 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 },
185 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 },
186 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
187 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
188 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
189 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
190 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
191 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
192 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
193 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
194 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 },
195 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
196 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
197 { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 },
198
199#else
200#error "Error: Unknown Alchemy SOC"
201#endif
202
203};
204
205int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 043429d17c5f..d8991854530e 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -27,12 +27,21 @@
27 */ 27 */
28 28
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <asm/time.h>
30#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
31 33
34/*
35 * I haven't found anyone that doesn't use a 12 MHz source clock,
36 * but just in case.....
37 */
38#define AU1000_SRC_CLK 12000000
39
32static unsigned int au1x00_clock; /* Hz */ 40static unsigned int au1x00_clock; /* Hz */
33static unsigned int lcd_clock; /* KHz */
34static unsigned long uart_baud_base; 41static unsigned long uart_baud_base;
35 42
43static DEFINE_SPINLOCK(time_lock);
44
36/* 45/*
37 * Set the au1000_clock 46 * Set the au1000_clock
38 */ 47 */
@@ -63,31 +72,45 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base)
63} 72}
64 73
65/* 74/*
66 * Calculate the Au1x00's LCD clock based on the current 75 * We read the real processor speed from the PLL. This is important
67 * cpu clock and the system bus clock, and try to keep it 76 * because it is more accurate than computing it from the 32 KHz
68 * below 40 MHz (the Pb1000 board can lock-up if the LCD 77 * counter, if it exists. If we don't have an accurate processor
69 * clock is over 40 MHz). 78 * speed, all of the peripherals that derive their clocks based on
79 * this advertised speed will introduce error and sometimes not work
80 * properly. This function is futher convoluted to still allow configurations
81 * to do that in case they have really, really old silicon with a
82 * write-only PLL register. -- Dan
70 */ 83 */
71void set_au1x00_lcd_clock(void) 84unsigned long au1xxx_calc_clock(void)
72{ 85{
73 unsigned int static_cfg0; 86 unsigned long cpu_speed;
74 unsigned int sys_busclk = (get_au1x00_speed() / 1000) / 87 unsigned long flags;
75 ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2);
76 88
77 static_cfg0 = au_readl(MEM_STCFG0); 89 spin_lock_irqsave(&time_lock, flags);
78 90
79 if (static_cfg0 & (1 << 11)) 91 /*
80 lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ 92 * On early Au1000, sys_cpupll was write-only. Since these
93 * silicon versions of Au1000 are not sold by AMD, we don't bend
94 * over backwards trying to determine the frequency.
95 */
96 if (au1xxx_cpu_has_pll_wo())
97#ifdef CONFIG_SOC_AU1000_FREQUENCY
98 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
99#else
100 cpu_speed = 396000000;
101#endif
81 else 102 else
82 lcd_clock = sys_busclk / 4; 103 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
83 104
84 if (lcd_clock > 50000) /* Epson MAX */ 105 /* On Alchemy CPU:counter ratio is 1:1 */
85 printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n", 106 mips_hpt_frequency = cpu_speed;
86 lcd_clock); 107 /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
87} 108 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
109 & 0x03) + 2) * 16));
88 110
89unsigned int get_au1x00_lcd_clock(void) 111 spin_unlock_irqrestore(&time_lock, flags);
90{ 112
91 return lcd_clock; 113 set_au1x00_speed(cpu_speed);
114
115 return cpu_speed;
92} 116}
93EXPORT_SYMBOL(get_au1x00_lcd_clock);
diff --git a/arch/mips/alchemy/common/cputable.c b/arch/mips/alchemy/common/cputable.c
deleted file mode 100644
index ba6430bc2d03..000000000000
--- a/arch/mips/alchemy/common/cputable.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * arch/mips/au1000/common/cputable.c
3 *
4 * Copyright (C) 2004 Dan Malek (dan@embeddededge.com)
5 * Copied from PowerPC and updated for Alchemy Au1xxx processors.
6 *
7 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/mach-au1x00/au1000.h>
16
17struct cpu_spec *cur_cpu_spec[NR_CPUS];
18
19/* With some thought, we can probably use the mask to reduce the
20 * size of the table.
21 */
22struct cpu_spec cpu_specs[] = {
23 { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
24 { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
25 { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
26 { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
27 { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
28 { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
29 { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
30 { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
31 { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
32 { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
33 { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
34 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
35 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
36 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
37 { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
38 { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
39 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
40};
41
42void set_cpuspec(void)
43{
44 struct cpu_spec *sp;
45 u32 prid;
46
47 prid = read_c0_prid();
48 sp = cpu_specs;
49 while ((prid & sp->prid_mask) != sp->prid_value)
50 sp++;
51 cur_cpu_spec[0] = sp;
52}
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 601ee9180ee4..3ab6d80d150d 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -174,6 +174,11 @@ static dbdev_tab_t dbdev_tab[] = {
174 174
175#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) 175#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
176 176
177#ifdef CONFIG_PM
178static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8];
179#endif
180
181
177static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 182static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
178 183
179static dbdev_tab_t *find_dbdev_id(u32 id) 184static dbdev_tab_t *find_dbdev_id(u32 id)
@@ -975,4 +980,64 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
975 return nbytes; 980 return nbytes;
976} 981}
977 982
983#ifdef CONFIG_PM
984void au1xxx_dbdma_suspend(void)
985{
986 int i;
987 u32 addr;
988
989 addr = DDMA_GLOBAL_BASE;
990 au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00);
991 au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04);
992 au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08);
993 au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c);
994
995 /* save channel configurations */
996 for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) {
997 au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00);
998 au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04);
999 au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08);
1000 au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c);
1001 au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10);
1002 au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14);
1003 au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18);
1004
1005 /* halt channel */
1006 au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00);
1007 au_sync();
1008 while (!(au_readl(addr + 0x14) & 1))
1009 au_sync();
1010
1011 addr += 0x100; /* next channel base */
1012 }
1013 /* disable channel interrupts */
1014 au_writel(0, DDMA_GLOBAL_BASE + 0x0c);
1015 au_sync();
1016}
1017
1018void au1xxx_dbdma_resume(void)
1019{
1020 int i;
1021 u32 addr;
1022
1023 addr = DDMA_GLOBAL_BASE;
1024 au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00);
1025 au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04);
1026 au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08);
1027 au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c);
1028
1029 /* restore channel configurations */
1030 for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) {
1031 au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00);
1032 au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04);
1033 au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08);
1034 au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c);
1035 au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10);
1036 au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14);
1037 au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18);
1038 au_sync();
1039 addr += 0x100; /* next channel base */
1040 }
1041}
1042#endif /* CONFIG_PM */
978#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 1043#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 40c6ceceb5f9..c88c821b4c36 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -24,6 +24,7 @@
24 * with this program; if not, write to the Free Software Foundation, Inc., 24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 26 */
27
27#include <linux/bitops.h> 28#include <linux/bitops.h>
28#include <linux/init.h> 29#include <linux/init.h>
29#include <linux/interrupt.h> 30#include <linux/interrupt.h>
@@ -36,15 +37,172 @@
36#include <asm/mach-pb1x00/pb1000.h> 37#include <asm/mach-pb1x00/pb1000.h>
37#endif 38#endif
38 39
39#define EXT_INTC0_REQ0 2 /* IP 2 */ 40static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
40#define EXT_INTC0_REQ1 3 /* IP 3 */ 41
41#define EXT_INTC1_REQ0 4 /* IP 4 */ 42/* per-processor fixed function irqs */
42#define EXT_INTC1_REQ1 5 /* IP 5 */ 43struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = {
43#define MIPS_TIMER_IP 7 /* IP 7 */ 44
44 45#if defined(CONFIG_SOC_AU1000)
45void (*board_init_irq)(void) __initdata = NULL; 46 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
47 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
48 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
49 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
50 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
51 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
52 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
53 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
54 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
55 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
56 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
57 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
58 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
59 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
60 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
61 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
62 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
63 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
64 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
65 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
66 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
67 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
68 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
69 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
70 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
71 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
72 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
73 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
74 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
75 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
76 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
77
78#elif defined(CONFIG_SOC_AU1500)
79
80 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
81 { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
82 { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
83 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
84 { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
85 { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
86 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
87 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
88 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
89 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
90 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
91 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
92 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
93 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
94 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
95 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
96 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
97 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
98 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
99 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
100 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
101 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
102 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
103 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
104 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
105 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
106 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
107 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
108 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
109
110#elif defined(CONFIG_SOC_AU1100)
111
112 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
113 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
114 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
115 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
116 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
120 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
121 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
122 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
123 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
124 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
125 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
127 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
128 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
129 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
130 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
131 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
132 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
133 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
134 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
137 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
138 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
139 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
141 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
142 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
143
144#elif defined(CONFIG_SOC_AU1550)
145
146 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
147 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
148 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
149 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
150 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
152 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
153 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
154 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
155 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
156 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
158 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
159 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
160 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
161 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
162 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
163 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
164 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
165 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
166 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
167 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
168 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
169 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
171 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
172 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
173 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
174
175#elif defined(CONFIG_SOC_AU1200)
176
177 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
178 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
179 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
180 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
181 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
182 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
185 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
189 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
190 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
191 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
192 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
193 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
194 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
195 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
196 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
197 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
198 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
199 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
200
201#else
202#error "Error: Unknown Alchemy SOC"
203#endif
204};
46 205
47static DEFINE_SPINLOCK(irq_lock);
48 206
49#ifdef CONFIG_PM 207#ifdef CONFIG_PM
50 208
@@ -130,67 +288,47 @@ void restore_au1xxx_intctl(void)
130#endif /* CONFIG_PM */ 288#endif /* CONFIG_PM */
131 289
132 290
133inline void local_enable_irq(unsigned int irq_nr) 291static void au1x_ic0_unmask(unsigned int irq_nr)
134{ 292{
135 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 293 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
136 294 au_writel(1 << bit, IC0_MASKSET);
137 if (bit >= 32) { 295 au_writel(1 << bit, IC0_WAKESET);
138 au_writel(1 << (bit - 32), IC1_MASKSET);
139 au_writel(1 << (bit - 32), IC1_WAKESET);
140 } else {
141 au_writel(1 << bit, IC0_MASKSET);
142 au_writel(1 << bit, IC0_WAKESET);
143 }
144 au_sync(); 296 au_sync();
145} 297}
146 298
147 299static void au1x_ic1_unmask(unsigned int irq_nr)
148inline void local_disable_irq(unsigned int irq_nr)
149{ 300{
150 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 301 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
302 au_writel(1 << bit, IC1_MASKSET);
303 au_writel(1 << bit, IC1_WAKESET);
151 304
152 if (bit >= 32) { 305/* very hacky. does the pb1000 cpld auto-disable this int?
153 au_writel(1 << (bit - 32), IC1_MASKCLR); 306 * nowhere in the current kernel sources is it disabled. --mlau
154 au_writel(1 << (bit - 32), IC1_WAKECLR); 307 */
155 } else { 308#if defined(CONFIG_MIPS_PB1000)
156 au_writel(1 << bit, IC0_MASKCLR); 309 if (irq_nr == AU1000_GPIO_15)
157 au_writel(1 << bit, IC0_WAKECLR); 310 au_writel(0x4000, PB1000_MDR); /* enable int */
158 } 311#endif
159 au_sync(); 312 au_sync();
160} 313}
161 314
162 315static void au1x_ic0_mask(unsigned int irq_nr)
163static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
164{ 316{
165 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 317 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
166 318 au_writel(1 << bit, IC0_MASKCLR);
167 if (bit >= 32) { 319 au_writel(1 << bit, IC0_WAKECLR);
168 au_writel(1 << (bit - 32), IC1_RISINGCLR);
169 au_writel(1 << (bit - 32), IC1_MASKCLR);
170 } else {
171 au_writel(1 << bit, IC0_RISINGCLR);
172 au_writel(1 << bit, IC0_MASKCLR);
173 }
174 au_sync(); 320 au_sync();
175} 321}
176 322
177 323static void au1x_ic1_mask(unsigned int irq_nr)
178static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
179{ 324{
180 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 325 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
181 326 au_writel(1 << bit, IC1_MASKCLR);
182 if (bit >= 32) { 327 au_writel(1 << bit, IC1_WAKECLR);
183 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
184 au_writel(1 << (bit - 32), IC1_MASKCLR);
185 } else {
186 au_writel(1 << bit, IC0_FALLINGCLR);
187 au_writel(1 << bit, IC0_MASKCLR);
188 }
189 au_sync(); 328 au_sync();
190} 329}
191 330
192 331static void au1x_ic0_ack(unsigned int irq_nr)
193static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
194{ 332{
195 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 333 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
196 334
@@ -198,349 +336,229 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
198 * This may assume that we don't get interrupts from 336 * This may assume that we don't get interrupts from
199 * both edges at once, or if we do, that we don't care. 337 * both edges at once, or if we do, that we don't care.
200 */ 338 */
201 if (bit >= 32) { 339 au_writel(1 << bit, IC0_FALLINGCLR);
202 au_writel(1 << (bit - 32), IC1_FALLINGCLR); 340 au_writel(1 << bit, IC0_RISINGCLR);
203 au_writel(1 << (bit - 32), IC1_RISINGCLR);
204 au_writel(1 << (bit - 32), IC1_MASKCLR);
205 } else {
206 au_writel(1 << bit, IC0_FALLINGCLR);
207 au_writel(1 << bit, IC0_RISINGCLR);
208 au_writel(1 << bit, IC0_MASKCLR);
209 }
210 au_sync(); 341 au_sync();
211} 342}
212 343
213static inline void mask_and_ack_level_irq(unsigned int irq_nr) 344static void au1x_ic1_ack(unsigned int irq_nr)
214{ 345{
215 local_disable_irq(irq_nr); 346 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
216 au_sync();
217#if defined(CONFIG_MIPS_PB1000)
218 if (irq_nr == AU1000_GPIO_15) {
219 au_writel(0x8000, PB1000_MDR); /* ack int */
220 au_sync();
221 }
222#endif
223}
224
225static void end_irq(unsigned int irq_nr)
226{
227 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
228 local_enable_irq(irq_nr);
229 347
230#if defined(CONFIG_MIPS_PB1000) 348 /*
231 if (irq_nr == AU1000_GPIO_15) { 349 * This may assume that we don't get interrupts from
232 au_writel(0x4000, PB1000_MDR); /* enable int */ 350 * both edges at once, or if we do, that we don't care.
233 au_sync(); 351 */
234 } 352 au_writel(1 << bit, IC1_FALLINGCLR);
235#endif 353 au_writel(1 << bit, IC1_RISINGCLR);
354 au_sync();
236} 355}
237 356
238unsigned long save_local_and_disable(int controller) 357static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
239{ 358{
240 int i; 359 unsigned int bit = irq - AU1000_INTC1_INT_BASE;
241 unsigned long flags, mask; 360 unsigned long wakemsk, flags;
242
243 spin_lock_irqsave(&irq_lock, flags);
244 if (controller) {
245 mask = au_readl(IC1_MASKSET);
246 for (i = 32; i < 64; i++)
247 local_disable_irq(i);
248 } else {
249 mask = au_readl(IC0_MASKSET);
250 for (i = 0; i < 32; i++)
251 local_disable_irq(i);
252 }
253 spin_unlock_irqrestore(&irq_lock, flags);
254
255 return mask;
256}
257 361
258void restore_local_and_enable(int controller, unsigned long mask) 362 /* only GPIO 0-7 can act as wakeup source: */
259{ 363 if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7))
260 int i; 364 return -EINVAL;
261 unsigned long flags, new_mask;
262
263 spin_lock_irqsave(&irq_lock, flags);
264 for (i = 0; i < 32; i++)
265 if (mask & (1 << i)) {
266 if (controller)
267 local_enable_irq(i + 32);
268 else
269 local_enable_irq(i);
270 }
271 365
272 if (controller) 366 local_irq_save(flags);
273 new_mask = au_readl(IC1_MASKSET); 367 wakemsk = au_readl(SYS_WAKEMSK);
368 if (on)
369 wakemsk |= 1 << bit;
274 else 370 else
275 new_mask = au_readl(IC0_MASKSET); 371 wakemsk &= ~(1 << bit);
372 au_writel(wakemsk, SYS_WAKEMSK);
373 au_sync();
374 local_irq_restore(flags);
276 375
277 spin_unlock_irqrestore(&irq_lock, flags); 376 return 0;
278} 377}
279 378
280 379/*
281static struct irq_chip rise_edge_irq_type = { 380 * irq_chips for both ICs; this way the mask handlers can be
282 .name = "Au1000 Rise Edge", 381 * as short as possible.
283 .ack = mask_and_ack_rise_edge_irq, 382 *
284 .mask = local_disable_irq, 383 * NOTE: the ->ack() callback is used by the handle_edge_irq
285 .mask_ack = mask_and_ack_rise_edge_irq, 384 * flowhandler only, the ->mask_ack() one by handle_level_irq,
286 .unmask = local_enable_irq, 385 * so no need for an irq_chip for each type of irq (level/edge).
287 .end = end_irq, 386 */
288}; 387static struct irq_chip au1x_ic0_chip = {
289 388 .name = "Alchemy-IC0",
290static struct irq_chip fall_edge_irq_type = { 389 .ack = au1x_ic0_ack, /* edge */
291 .name = "Au1000 Fall Edge", 390 .mask = au1x_ic0_mask,
292 .ack = mask_and_ack_fall_edge_irq, 391 .mask_ack = au1x_ic0_mask, /* level */
293 .mask = local_disable_irq, 392 .unmask = au1x_ic0_unmask,
294 .mask_ack = mask_and_ack_fall_edge_irq, 393 .set_type = au1x_ic_settype,
295 .unmask = local_enable_irq,
296 .end = end_irq,
297};
298
299static struct irq_chip either_edge_irq_type = {
300 .name = "Au1000 Rise or Fall Edge",
301 .ack = mask_and_ack_either_edge_irq,
302 .mask = local_disable_irq,
303 .mask_ack = mask_and_ack_either_edge_irq,
304 .unmask = local_enable_irq,
305 .end = end_irq,
306}; 394};
307 395
308static struct irq_chip level_irq_type = { 396static struct irq_chip au1x_ic1_chip = {
309 .name = "Au1000 Level", 397 .name = "Alchemy-IC1",
310 .ack = mask_and_ack_level_irq, 398 .ack = au1x_ic1_ack, /* edge */
311 .mask = local_disable_irq, 399 .mask = au1x_ic1_mask,
312 .mask_ack = mask_and_ack_level_irq, 400 .mask_ack = au1x_ic1_mask, /* level */
313 .unmask = local_enable_irq, 401 .unmask = au1x_ic1_unmask,
314 .end = end_irq, 402 .set_type = au1x_ic_settype,
403 .set_wake = au1x_ic1_setwake,
315}; 404};
316 405
317static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req) 406static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
318{ 407{
319 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 408 struct irq_chip *chip;
320 409 unsigned long icr[6];
321 if (irq_nr > AU1000_MAX_INTR) 410 unsigned int bit, ic;
322 return; 411 int ret;
323 412
324 /* Config2[n], Config1[n], Config0[n] */ 413 if (irq >= AU1000_INTC1_INT_BASE) {
325 if (bit >= 32) { 414 bit = irq - AU1000_INTC1_INT_BASE;
326 switch (type) { 415 chip = &au1x_ic1_chip;
327 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 416 ic = 1;
328 au_writel(1 << (bit - 32), IC1_CFG2CLR);
329 au_writel(1 << (bit - 32), IC1_CFG1CLR);
330 au_writel(1 << (bit - 32), IC1_CFG0SET);
331 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1 << (bit - 32), IC1_CFG2CLR);
335 au_writel(1 << (bit - 32), IC1_CFG1SET);
336 au_writel(1 << (bit - 32), IC1_CFG0CLR);
337 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1 << (bit - 32), IC1_CFG2CLR);
341 au_writel(1 << (bit - 32), IC1_CFG1SET);
342 au_writel(1 << (bit - 32), IC1_CFG0SET);
343 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1 << (bit - 32), IC1_CFG2SET);
347 au_writel(1 << (bit - 32), IC1_CFG1CLR);
348 au_writel(1 << (bit - 32), IC1_CFG0SET);
349 set_irq_chip(irq_nr, &level_irq_type);
350 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1 << (bit - 32), IC1_CFG2SET);
353 au_writel(1 << (bit - 32), IC1_CFG1SET);
354 au_writel(1 << (bit - 32), IC1_CFG0CLR);
355 set_irq_chip(irq_nr, &level_irq_type);
356 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1 << (bit - 32), IC1_CFG0CLR);
359 au_writel(1 << (bit - 32), IC1_CFG1CLR);
360 au_writel(1 << (bit - 32), IC1_CFG2CLR);
361 break;
362 default: /* disable the interrupt */
363 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
364 type, irq_nr);
365 au_writel(1 << (bit - 32), IC1_CFG0CLR);
366 au_writel(1 << (bit - 32), IC1_CFG1CLR);
367 au_writel(1 << (bit - 32), IC1_CFG2CLR);
368 return;
369 }
370 if (int_req) /* assign to interrupt request 1 */
371 au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
372 else /* assign to interrupt request 0 */
373 au_writel(1 << (bit - 32), IC1_ASSIGNSET);
374 au_writel(1 << (bit - 32), IC1_SRCSET);
375 au_writel(1 << (bit - 32), IC1_MASKCLR);
376 au_writel(1 << (bit - 32), IC1_WAKECLR);
377 } else { 417 } else {
378 switch (type) { 418 bit = irq - AU1000_INTC0_INT_BASE;
379 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 419 chip = &au1x_ic0_chip;
380 au_writel(1 << bit, IC0_CFG2CLR); 420 ic = 0;
381 au_writel(1 << bit, IC0_CFG1CLR); 421 }
382 au_writel(1 << bit, IC0_CFG0SET); 422
383 set_irq_chip(irq_nr, &rise_edge_irq_type); 423 if (bit > 31)
384 break; 424 return -EINVAL;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 425
386 au_writel(1 << bit, IC0_CFG2CLR); 426 icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
387 au_writel(1 << bit, IC0_CFG1SET); 427 icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
388 au_writel(1 << bit, IC0_CFG0CLR); 428 icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
389 set_irq_chip(irq_nr, &fall_edge_irq_type); 429 icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
390 break; 430 icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 431 icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
392 au_writel(1 << bit, IC0_CFG2CLR); 432
393 au_writel(1 << bit, IC0_CFG1SET); 433 ret = 0;
394 au_writel(1 << bit, IC0_CFG0SET); 434
395 set_irq_chip(irq_nr, &either_edge_irq_type); 435 switch (flow_type) { /* cfgregs 2:1:0 */
396 break; 436 case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 437 au_writel(1 << bit, icr[5]);
398 au_writel(1 << bit, IC0_CFG2SET); 438 au_writel(1 << bit, icr[4]);
399 au_writel(1 << bit, IC0_CFG1CLR); 439 au_writel(1 << bit, icr[0]);
400 au_writel(1 << bit, IC0_CFG0SET); 440 set_irq_chip_and_handler_name(irq, chip,
401 set_irq_chip(irq_nr, &level_irq_type); 441 handle_edge_irq, "riseedge");
402 break; 442 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 443 case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */
404 au_writel(1 << bit, IC0_CFG2SET); 444 au_writel(1 << bit, icr[5]);
405 au_writel(1 << bit, IC0_CFG1SET); 445 au_writel(1 << bit, icr[1]);
406 au_writel(1 << bit, IC0_CFG0CLR); 446 au_writel(1 << bit, icr[3]);
407 set_irq_chip(irq_nr, &level_irq_type); 447 set_irq_chip_and_handler_name(irq, chip,
408 break; 448 handle_edge_irq, "falledge");
409 case INTC_INT_DISABLED: /* 0:0:0 */ 449 break;
410 au_writel(1 << bit, IC0_CFG0CLR); 450 case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */
411 au_writel(1 << bit, IC0_CFG1CLR); 451 au_writel(1 << bit, icr[5]);
412 au_writel(1 << bit, IC0_CFG2CLR); 452 au_writel(1 << bit, icr[1]);
413 break; 453 au_writel(1 << bit, icr[0]);
414 default: /* disable the interrupt */ 454 set_irq_chip_and_handler_name(irq, chip,
415 printk(KERN_WARNING "unexpected int type %d (irq %d)\n", 455 handle_edge_irq, "bothedge");
416 type, irq_nr); 456 break;
417 au_writel(1 << bit, IC0_CFG0CLR); 457 case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */
418 au_writel(1 << bit, IC0_CFG1CLR); 458 au_writel(1 << bit, icr[2]);
419 au_writel(1 << bit, IC0_CFG2CLR); 459 au_writel(1 << bit, icr[4]);
420 return; 460 au_writel(1 << bit, icr[0]);
421 } 461 set_irq_chip_and_handler_name(irq, chip,
422 if (int_req) /* assign to interrupt request 1 */ 462 handle_level_irq, "hilevel");
423 au_writel(1 << bit, IC0_ASSIGNCLR); 463 break;
424 else /* assign to interrupt request 0 */ 464 case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */
425 au_writel(1 << bit, IC0_ASSIGNSET); 465 au_writel(1 << bit, icr[2]);
426 au_writel(1 << bit, IC0_SRCSET); 466 au_writel(1 << bit, icr[1]);
427 au_writel(1 << bit, IC0_MASKCLR); 467 au_writel(1 << bit, icr[3]);
428 au_writel(1 << bit, IC0_WAKECLR); 468 set_irq_chip_and_handler_name(irq, chip,
469 handle_level_irq, "lowlevel");
470 break;
471 case IRQ_TYPE_NONE: /* 0:0:0 */
472 au_writel(1 << bit, icr[5]);
473 au_writel(1 << bit, icr[4]);
474 au_writel(1 << bit, icr[3]);
475 /* set at least chip so we can call set_irq_type() on it */
476 set_irq_chip(irq, chip);
477 break;
478 default:
479 ret = -EINVAL;
429 } 480 }
430 au_sync(); 481 au_sync();
431}
432 482
433/* 483 return ret;
434 * Interrupts are nested. Even if an interrupt handler is registered 484}
435 * as "fast", we might get another interrupt before we return from
436 * intcX_reqX_irqdispatch().
437 */
438 485
439static void intc0_req0_irqdispatch(void) 486asmlinkage void plat_irq_dispatch(void)
440{ 487{
441 static unsigned long intc0_req0; 488 unsigned int pending = read_c0_status() & read_c0_cause();
442 unsigned int bit; 489 unsigned long s, off, bit;
443
444 intc0_req0 |= au_readl(IC0_REQ0INT);
445 490
446 if (!intc0_req0) 491 if (pending & CAUSEF_IP7) {
492 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
447 return; 493 return;
448 494 } else if (pending & CAUSEF_IP2) {
495 s = IC0_REQ0INT;
496 off = AU1000_INTC0_INT_BASE;
497 } else if (pending & CAUSEF_IP3) {
498 s = IC0_REQ1INT;
499 off = AU1000_INTC0_INT_BASE;
500 } else if (pending & CAUSEF_IP4) {
501 s = IC1_REQ0INT;
502 off = AU1000_INTC1_INT_BASE;
503 } else if (pending & CAUSEF_IP5) {
504 s = IC1_REQ1INT;
505 off = AU1000_INTC1_INT_BASE;
506 } else
507 goto spurious;
508
509 bit = 0;
510 s = au_readl(s);
511 if (unlikely(!s)) {
512spurious:
513 spurious_interrupt();
514 return;
515 }
449#ifdef AU1000_USB_DEV_REQ_INT 516#ifdef AU1000_USB_DEV_REQ_INT
450 /* 517 /*
451 * Because of the tight timing of SETUP token to reply 518 * Because of the tight timing of SETUP token to reply
452 * transactions, the USB devices-side packet complete 519 * transactions, the USB devices-side packet complete
453 * interrupt needs the highest priority. 520 * interrupt needs the highest priority.
454 */ 521 */
455 if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) { 522 bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE);
456 intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT); 523 if ((pending & CAUSEF_IP2) && (s & bit)) {
457 do_IRQ(AU1000_USB_DEV_REQ_INT); 524 do_IRQ(AU1000_USB_DEV_REQ_INT);
458 return; 525 return;
459 } 526 }
460#endif 527#endif
461 bit = __ffs(intc0_req0); 528 do_IRQ(__ffs(s) + off);
462 intc0_req0 &= ~(1 << bit);
463 do_IRQ(AU1000_INTC0_INT_BASE + bit);
464} 529}
465 530
466 531/* setup edge/level and assign request 0/1 */
467static void intc0_req1_irqdispatch(void) 532void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count)
468{
469 static unsigned long intc0_req1;
470 unsigned int bit;
471
472 intc0_req1 |= au_readl(IC0_REQ1INT);
473
474 if (!intc0_req1)
475 return;
476
477 bit = __ffs(intc0_req1);
478 intc0_req1 &= ~(1 << bit);
479 do_IRQ(AU1000_INTC0_INT_BASE + bit);
480}
481
482
483/*
484 * Interrupt Controller 1:
485 * interrupts 32 - 63
486 */
487static void intc1_req0_irqdispatch(void)
488{ 533{
489 static unsigned long intc1_req0; 534 unsigned int bit, irq_nr;
490 unsigned int bit; 535
491 536 while (count--) {
492 intc1_req0 |= au_readl(IC1_REQ0INT); 537 irq_nr = map[count].im_irq;
493 538
494 if (!intc1_req0) 539 if (((irq_nr < AU1000_INTC0_INT_BASE) ||
495 return; 540 (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
496 541 ((irq_nr < AU1000_INTC1_INT_BASE) ||
497 bit = __ffs(intc1_req0); 542 (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
498 intc1_req0 &= ~(1 << bit); 543 continue;
499 do_IRQ(AU1000_INTC1_INT_BASE + bit); 544
500} 545 if (irq_nr >= AU1000_INTC1_INT_BASE) {
501 546 bit = irq_nr - AU1000_INTC1_INT_BASE;
502 547 if (map[count].im_request)
503static void intc1_req1_irqdispatch(void) 548 au_writel(1 << bit, IC1_ASSIGNCLR);
504{ 549 } else {
505 static unsigned long intc1_req1; 550 bit = irq_nr - AU1000_INTC0_INT_BASE;
506 unsigned int bit; 551 if (map[count].im_request)
507 552 au_writel(1 << bit, IC0_ASSIGNCLR);
508 intc1_req1 |= au_readl(IC1_REQ1INT); 553 }
509
510 if (!intc1_req1)
511 return;
512
513 bit = __ffs(intc1_req1);
514 intc1_req1 &= ~(1 << bit);
515 do_IRQ(AU1000_INTC1_INT_BASE + bit);
516}
517
518asmlinkage void plat_irq_dispatch(void)
519{
520 unsigned int pending = read_c0_status() & read_c0_cause();
521 554
522 if (pending & CAUSEF_IP7) 555 au1x_ic_settype(irq_nr, map[count].im_type);
523 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 556 }
524 else if (pending & CAUSEF_IP2)
525 intc0_req0_irqdispatch();
526 else if (pending & CAUSEF_IP3)
527 intc0_req1_irqdispatch();
528 else if (pending & CAUSEF_IP4)
529 intc1_req0_irqdispatch();
530 else if (pending & CAUSEF_IP5)
531 intc1_req1_irqdispatch();
532 else
533 spurious_interrupt();
534} 557}
535 558
536void __init arch_init_irq(void) 559void __init arch_init_irq(void)
537{ 560{
538 int i; 561 int i;
539 struct au1xxx_irqmap *imp;
540 extern struct au1xxx_irqmap au1xxx_irq_map[];
541 extern struct au1xxx_irqmap au1xxx_ic0_map[];
542 extern int au1xxx_nr_irqs;
543 extern int au1xxx_ic0_nr_irqs;
544 562
545 /* 563 /*
546 * Initialize interrupt controllers to a safe state. 564 * Initialize interrupt controllers to a safe state.
@@ -569,28 +587,25 @@ void __init arch_init_irq(void)
569 587
570 mips_cpu_irq_init(); 588 mips_cpu_irq_init();
571 589
572 /* 590 /* register all 64 possible IC0+IC1 irq sources as type "none".
573 * Initialize IC0, which is fixed per processor. 591 * Use set_irq_type() to set edge/level behaviour at runtime.
574 */ 592 */
575 imp = au1xxx_ic0_map; 593 for (i = AU1000_INTC0_INT_BASE;
576 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) { 594 (i < AU1000_INTC0_INT_BASE + 32); i++)
577 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); 595 au1x_ic_settype(i, IRQ_TYPE_NONE);
578 imp++; 596
579 } 597 for (i = AU1000_INTC1_INT_BASE;
598 (i < AU1000_INTC1_INT_BASE + 32); i++)
599 au1x_ic_settype(i, IRQ_TYPE_NONE);
580 600
581 /* 601 /*
582 * Now set up the irq mapping for the board. 602 * Initialize IC0, which is fixed per processor.
583 */ 603 */
584 imp = au1xxx_irq_map; 604 au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
585 for (i = 0; i < au1xxx_nr_irqs; i++) {
586 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
587 imp++;
588 }
589
590 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
591 605
592 /* Board specific IRQ initialization. 606 /* Boards can register additional (GPIO-based) IRQs.
593 */ 607 */
594 if (board_init_irq) 608 board_init_irq();
595 board_init_irq(); 609
610 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
596} 611}
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bd854a6d1d89..6ab7b42aa1be 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -35,25 +35,12 @@
35#include <linux/jiffies.h> 35#include <linux/jiffies.h>
36 36
37#include <asm/uaccess.h> 37#include <asm/uaccess.h>
38#include <asm/cacheflush.h>
39#include <asm/mach-au1x00/au1000.h> 38#include <asm/mach-au1x00/au1000.h>
40 39#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
41#ifdef CONFIG_PM 40#include <asm/mach-au1x00/au1xxx_dbdma.h>
42
43#define DEBUG 1
44#ifdef DEBUG
45#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args)
46#else
47#define DPRINTK(fmt, args...)
48#endif 41#endif
49 42
50static void au1000_calibrate_delay(void); 43#ifdef CONFIG_PM
51
52extern unsigned long save_local_and_disable(int controller);
53extern void restore_local_and_enable(int controller, unsigned long mask);
54extern void local_enable_irq(unsigned int irq_nr);
55
56static DEFINE_SPINLOCK(pm_lock);
57 44
58/* 45/*
59 * We need to save/restore a bunch of core registers that are 46 * We need to save/restore a bunch of core registers that are
@@ -65,29 +52,16 @@ static DEFINE_SPINLOCK(pm_lock);
65 * We only have to save/restore registers that aren't otherwise 52 * We only have to save/restore registers that aren't otherwise
66 * done as part of a driver pm_* function. 53 * done as part of a driver pm_* function.
67 */ 54 */
68static unsigned int sleep_aux_pll_cntrl; 55static unsigned int sleep_uart0_inten;
69static unsigned int sleep_cpu_pll_cntrl; 56static unsigned int sleep_uart0_fifoctl;
70static unsigned int sleep_pin_function; 57static unsigned int sleep_uart0_linectl;
71static unsigned int sleep_uart0_inten; 58static unsigned int sleep_uart0_clkdiv;
72static unsigned int sleep_uart0_fifoctl; 59static unsigned int sleep_uart0_enable;
73static unsigned int sleep_uart0_linectl; 60static unsigned int sleep_usb[2];
74static unsigned int sleep_uart0_clkdiv; 61static unsigned int sleep_sys_clocks[5];
75static unsigned int sleep_uart0_enable; 62static unsigned int sleep_sys_pinfunc;
76static unsigned int sleep_usbhost_enable; 63static unsigned int sleep_static_memctlr[4][3];
77static unsigned int sleep_usbdev_enable;
78static unsigned int sleep_static_memctlr[4][3];
79 64
80/*
81 * Define this to cause the value you write to /proc/sys/pm/sleep to
82 * set the TOY timer for the amount of time you want to sleep.
83 * This is done mainly for testing, but may be useful in other cases.
84 * The value is number of 32KHz ticks to sleep.
85 */
86#define SLEEP_TEST_TIMEOUT 1
87#ifdef SLEEP_TEST_TIMEOUT
88static int sleep_ticks;
89void wakeup_counter0_set(int ticks);
90#endif
91 65
92static void save_core_regs(void) 66static void save_core_regs(void)
93{ 67{
@@ -105,31 +79,45 @@ static void save_core_regs(void)
105 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); 79 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
106 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); 80 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
107 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); 81 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
82 au_sync();
108 83
84#ifndef CONFIG_SOC_AU1200
109 /* Shutdown USB host/device. */ 85 /* Shutdown USB host/device. */
110 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); 86 sleep_usb[0] = au_readl(USB_HOST_CONFIG);
111 87
112 /* There appears to be some undocumented reset register.... */ 88 /* There appears to be some undocumented reset register.... */
113 au_writel(0, 0xb0100004); au_sync(); 89 au_writel(0, 0xb0100004);
114 au_writel(0, USB_HOST_CONFIG); au_sync(); 90 au_sync();
91 au_writel(0, USB_HOST_CONFIG);
92 au_sync();
115 93
116 sleep_usbdev_enable = au_readl(USBD_ENABLE); 94 sleep_usb[1] = au_readl(USBD_ENABLE);
117 au_writel(0, USBD_ENABLE); au_sync(); 95 au_writel(0, USBD_ENABLE);
96 au_sync();
97
98#else /* AU1200 */
99
100 /* enable access to OTG mmio so we can save OTG CAP/MUX.
101 * FIXME: write an OTG driver and move this stuff there!
102 */
103 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
104 au_sync();
105 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
106 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
107#endif
118 108
119 /* Save interrupt controller state. */ 109 /* Save interrupt controller state. */
120 save_au1xxx_intctl(); 110 save_au1xxx_intctl();
121 111
122 /* Clocks and PLLs. */ 112 /* Clocks and PLLs. */
123 sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); 113 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
114 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
115 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
116 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
117 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
124 118
125 /* 119 /* pin mux config */
126 * We don't really need to do this one, but unless we 120 sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
127 * write it again it won't have a valid value if we
128 * happen to read it.
129 */
130 sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL);
131
132 sleep_pin_function = au_readl(SYS_PINFUNC);
133 121
134 /* Save the static memory controller configuration. */ 122 /* Save the static memory controller configuration. */
135 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); 123 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
@@ -144,16 +132,45 @@ static void save_core_regs(void)
144 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); 132 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
145 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); 133 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
146 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); 134 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
135
136#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
137 au1xxx_dbdma_suspend();
138#endif
147} 139}
148 140
149static void restore_core_regs(void) 141static void restore_core_regs(void)
150{ 142{
151 extern void restore_au1xxx_intctl(void); 143 /* restore clock configuration. Writing CPUPLL last will
152 extern void wakeup_counter0_adjust(void); 144 * stall a bit and stabilize other clocks (unless this is
145 * one of those Au1000 with a write-only PLL, where we dont
146 * have a valid value)
147 */
148 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
149 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
150 au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
151 au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
152 if (!au1xxx_cpu_has_pll_wo())
153 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
154 au_sync();
153 155
154 au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync(); 156 au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
155 au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); 157 au_sync();
156 au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); 158
159#ifndef CONFIG_SOC_AU1200
160 au_writel(sleep_usb[0], USB_HOST_CONFIG);
161 au_writel(sleep_usb[1], USBD_ENABLE);
162 au_sync();
163#else
164 /* enable accces to OTG memory */
165 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
166 au_sync();
167
168 /* restore OTG caps and port mux. */
169 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
170 au_sync();
171 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
172 au_sync();
173#endif
157 174
158 /* Restore the static memory controller configuration. */ 175 /* Restore the static memory controller configuration. */
159 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 176 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
@@ -184,282 +201,17 @@ static void restore_core_regs(void)
184 } 201 }
185 202
186 restore_au1xxx_intctl(); 203 restore_au1xxx_intctl();
187 wakeup_counter0_adjust();
188}
189
190unsigned long suspend_mode;
191 204
192void wakeup_from_suspend(void) 205#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
193{ 206 au1xxx_dbdma_resume();
194 suspend_mode = 0; 207#endif
195} 208}
196 209
197int au_sleep(void) 210void au_sleep(void)
198{ 211{
199 unsigned long wakeup, flags;
200 extern void save_and_sleep(void);
201
202 spin_lock_irqsave(&pm_lock, flags);
203
204 save_core_regs(); 212 save_core_regs();
205 213 au1xxx_save_and_sleep();
206 flush_cache_all();
207
208 /**
209 ** The code below is all system dependent and we should probably
210 ** have a function call out of here to set this up. You need
211 ** to configure the GPIO or timer interrupts that will bring
212 ** you out of sleep.
213 ** For testing, the TOY counter wakeup is useful.
214 **/
215#if 0
216 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
217
218 /* GPIO 6 can cause a wake up event */
219 wakeup = au_readl(SYS_WAKEMSK);
220 wakeup &= ~(1 << 8); /* turn off match20 wakeup */
221 wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */
222#else
223 /* For testing, allow match20 to wake us up. */
224#ifdef SLEEP_TEST_TIMEOUT
225 wakeup_counter0_set(sleep_ticks);
226#endif
227 wakeup = 1 << 8; /* turn on match20 wakeup */
228 wakeup = 0;
229#endif
230 au_writel(1, SYS_WAKESRC); /* clear cause */
231 au_sync();
232 au_writel(wakeup, SYS_WAKEMSK);
233 au_sync();
234
235 save_and_sleep();
236
237 /*
238 * After a wakeup, the cpu vectors back to 0x1fc00000, so
239 * it's up to the boot code to get us back here.
240 */
241 restore_core_regs(); 214 restore_core_regs();
242 spin_unlock_irqrestore(&pm_lock, flags);
243 return 0;
244}
245
246static int pm_do_sleep(ctl_table *ctl, int write, struct file *file,
247 void __user *buffer, size_t *len, loff_t *ppos)
248{
249#ifdef SLEEP_TEST_TIMEOUT
250#define TMPBUFLEN2 16
251 char buf[TMPBUFLEN2], *p;
252#endif
253
254 if (!write)
255 *len = 0;
256 else {
257#ifdef SLEEP_TEST_TIMEOUT
258 if (*len > TMPBUFLEN2 - 1)
259 return -EFAULT;
260 if (copy_from_user(buf, buffer, *len))
261 return -EFAULT;
262 buf[*len] = 0;
263 p = buf;
264 sleep_ticks = simple_strtoul(p, &p, 0);
265#endif
266
267 au_sleep();
268 }
269 return 0;
270}
271
272static int pm_do_freq(ctl_table *ctl, int write, struct file *file,
273 void __user *buffer, size_t *len, loff_t *ppos)
274{
275 int retval = 0, i;
276 unsigned long val, pll;
277#define TMPBUFLEN 64
278#define MAX_CPU_FREQ 396
279 char buf[TMPBUFLEN], *p;
280 unsigned long flags, intc0_mask, intc1_mask;
281 unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh;
282 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
283 unsigned long baud_rate;
284
285 spin_lock_irqsave(&pm_lock, flags);
286 if (!write)
287 *len = 0;
288 else {
289 /* Parse the new frequency */
290 if (*len > TMPBUFLEN - 1) {
291 spin_unlock_irqrestore(&pm_lock, flags);
292 return -EFAULT;
293 }
294 if (copy_from_user(buf, buffer, *len)) {
295 spin_unlock_irqrestore(&pm_lock, flags);
296 return -EFAULT;
297 }
298 buf[*len] = 0;
299 p = buf;
300 val = simple_strtoul(p, &p, 0);
301 if (val > MAX_CPU_FREQ) {
302 spin_unlock_irqrestore(&pm_lock, flags);
303 return -EFAULT;
304 }
305
306 pll = val / 12;
307 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
308 /* Revisit this for higher speed CPUs */
309 spin_unlock_irqrestore(&pm_lock, flags);
310 return -EFAULT;
311 }
312
313 old_baud_base = get_au1x00_uart_baud_base();
314 old_cpu_freq = get_au1x00_speed();
315
316 new_cpu_freq = pll * 12 * 1000000;
317 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)
318 & 0x03) + 2) * 16));
319 set_au1x00_speed(new_cpu_freq);
320 set_au1x00_uart_baud_base(new_baud_base);
321
322 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
323 new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) |
324 (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
325
326 au_writel(pll, SYS_CPUPLL);
327 au_sync_delay(1);
328 au_writel(new_refresh, MEM_SDREFCFG);
329 au_sync_delay(1);
330
331 for (i = 0; i < 4; i++)
332 if (au_readl(UART_BASE + UART_MOD_CNTRL +
333 i * 0x00100000) == 3) {
334 old_clk = au_readl(UART_BASE + UART_CLK +
335 i * 0x00100000);
336 baud_rate = old_baud_base / old_clk;
337 /*
338 * We won't get an exact baud rate and the error
339 * could be significant enough that our new
340 * calculation will result in a clock that will
341 * give us a baud rate that's too far off from
342 * what we really want.
343 */
344 if (baud_rate > 100000)
345 baud_rate = 115200;
346 else if (baud_rate > 50000)
347 baud_rate = 57600;
348 else if (baud_rate > 30000)
349 baud_rate = 38400;
350 else if (baud_rate > 17000)
351 baud_rate = 19200;
352 else
353 baud_rate = 9600;
354 new_clk = new_baud_base / baud_rate;
355 au_writel(new_clk, UART_BASE + UART_CLK +
356 i * 0x00100000);
357 au_sync_delay(10);
358 }
359 }
360
361 /*
362 * We don't want _any_ interrupts other than match20. Otherwise our
363 * au1000_calibrate_delay() calculation will be off, potentially a lot.
364 */
365 intc0_mask = save_local_and_disable(0);
366 intc1_mask = save_local_and_disable(1);
367 local_enable_irq(AU1000_TOY_MATCH2_INT);
368 spin_unlock_irqrestore(&pm_lock, flags);
369 au1000_calibrate_delay();
370 restore_local_and_enable(0, intc0_mask);
371 restore_local_and_enable(1, intc1_mask);
372
373 return retval;
374} 215}
375 216
376
377static struct ctl_table pm_table[] = {
378 {
379 .ctl_name = CTL_UNNUMBERED,
380 .procname = "sleep",
381 .data = NULL,
382 .maxlen = 0,
383 .mode = 0600,
384 .proc_handler = &pm_do_sleep
385 },
386 {
387 .ctl_name = CTL_UNNUMBERED,
388 .procname = "freq",
389 .data = NULL,
390 .maxlen = 0,
391 .mode = 0600,
392 .proc_handler = &pm_do_freq
393 },
394 {}
395};
396
397static struct ctl_table pm_dir_table[] = {
398 {
399 .ctl_name = CTL_UNNUMBERED,
400 .procname = "pm",
401 .mode = 0555,
402 .child = pm_table
403 },
404 {}
405};
406
407/*
408 * Initialize power interface
409 */
410static int __init pm_init(void)
411{
412 register_sysctl_table(pm_dir_table);
413 return 0;
414}
415
416__initcall(pm_init);
417
418/*
419 * This is right out of init/main.c
420 */
421
422/*
423 * This is the number of bits of precision for the loops_per_jiffy.
424 * Each bit takes on average 1.5/HZ seconds. This (like the original)
425 * is a little better than 1%.
426 */
427#define LPS_PREC 8
428
429static void au1000_calibrate_delay(void)
430{
431 unsigned long ticks, loopbit;
432 int lps_precision = LPS_PREC;
433
434 loops_per_jiffy = 1 << 12;
435
436 while (loops_per_jiffy <<= 1) {
437 /* Wait for "start of" clock tick */
438 ticks = jiffies;
439 while (ticks == jiffies)
440 /* nothing */ ;
441 /* Go ... */
442 ticks = jiffies;
443 __delay(loops_per_jiffy);
444 ticks = jiffies - ticks;
445 if (ticks)
446 break;
447 }
448
449 /*
450 * Do a binary approximation to get loops_per_jiffy set to be equal
451 * one clock (up to lps_precision bits)
452 */
453 loops_per_jiffy >>= 1;
454 loopbit = loops_per_jiffy;
455 while (lps_precision-- && (loopbit >>= 1)) {
456 loops_per_jiffy |= loopbit;
457 ticks = jiffies;
458 while (ticks == jiffies);
459 ticks = jiffies;
460 __delay(loops_per_jiffy);
461 if (jiffies != ticks) /* longer than 1 tick */
462 loops_per_jiffy &= ~loopbit;
463 }
464}
465#endif /* CONFIG_PM */ 217#endif /* CONFIG_PM */
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
index d555429c8d6f..0191c936cb5e 100644
--- a/arch/mips/alchemy/common/reset.c
+++ b/arch/mips/alchemy/common/reset.c
@@ -31,8 +31,6 @@
31 31
32#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
33 33
34extern int au_sleep(void);
35
36void au1000_restart(char *command) 34void au1000_restart(char *command)
37{ 35{
38 /* Set all integrated peripherals to disabled states */ 36 /* Set all integrated peripherals to disabled states */
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1ac6b06f42a3..3f036b3d400e 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -35,7 +35,6 @@
35#include <asm/time.h> 35#include <asm/time.h>
36 36
37#include <au1000.h> 37#include <au1000.h>
38#include <prom.h>
39 38
40extern void __init board_setup(void); 39extern void __init board_setup(void);
41extern void au1000_restart(char *); 40extern void au1000_restart(char *);
@@ -45,80 +44,34 @@ extern void set_cpuspec(void);
45 44
46void __init plat_mem_setup(void) 45void __init plat_mem_setup(void)
47{ 46{
48 struct cpu_spec *sp; 47 unsigned long est_freq;
49 char *argptr;
50 unsigned long prid, cpufreq, bclk;
51 48
52 set_cpuspec(); 49 /* determine core clock */
53 sp = cur_cpu_spec[0]; 50 est_freq = au1xxx_calc_clock();
51 est_freq += 5000; /* round */
52 est_freq -= est_freq % 10000;
53 printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(),
54 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
54 55
55 board_setup(); /* board specific setup */ 56 _machine_restart = au1000_restart;
56 57 _machine_halt = au1000_halt;
57 prid = read_c0_prid(); 58 pm_power_off = au1000_power_off;
58 if (sp->cpu_pll_wo)
59#ifdef CONFIG_SOC_AU1000_FREQUENCY
60 cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
61#else
62 cpufreq = 396;
63#endif
64 else
65 cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
66 printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
67 59
68 if (sp->cpu_bclk) { 60 board_setup(); /* board specific setup */
69 /* Enable BCLK switching */
70 bclk = au_readl(SYS_POWERCTRL);
71 au_writel(bclk | 0x60, SYS_POWERCTRL);
72 printk(KERN_INFO "BCLK switching enabled!\n");
73 }
74 61
75 if (sp->cpu_od) 62 if (au1xxx_cpu_needs_config_od())
76 /* Various early Au1xx0 errata corrected by this */ 63 /* Various early Au1xx0 errata corrected by this */
77 set_c0_config(1 << 19); /* Set Config[OD] */ 64 set_c0_config(1 << 19); /* Set Config[OD] */
78 else 65 else
79 /* Clear to obtain best system bus performance */ 66 /* Clear to obtain best system bus performance */
80 clear_c0_config(1 << 19); /* Clear Config[OD] */ 67 clear_c0_config(1 << 19); /* Clear Config[OD] */
81 68
82 argptr = prom_getcmdline();
83
84#ifdef CONFIG_SERIAL_8250_CONSOLE
85 argptr = strstr(argptr, "console=");
86 if (argptr == NULL) {
87 argptr = prom_getcmdline();
88 strcat(argptr, " console=ttyS0,115200");
89 }
90#endif
91
92#ifdef CONFIG_FB_AU1100
93 argptr = strstr(argptr, "video=");
94 if (argptr == NULL) {
95 argptr = prom_getcmdline();
96 /* default panel */
97 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
98 }
99#endif
100
101#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
102 /* au1000 does not support vra, au1500 and au1100 do */
103 strcat(argptr, " au1000_audio=vra");
104 argptr = prom_getcmdline();
105#endif
106 _machine_restart = au1000_restart;
107 _machine_halt = au1000_halt;
108 pm_power_off = au1000_power_off;
109
110 /* IO/MEM resources. */ 69 /* IO/MEM resources. */
111 set_io_port_base(0); 70 set_io_port_base(0);
112 ioport_resource.start = IOPORT_RESOURCE_START; 71 ioport_resource.start = IOPORT_RESOURCE_START;
113 ioport_resource.end = IOPORT_RESOURCE_END; 72 ioport_resource.end = IOPORT_RESOURCE_END;
114 iomem_resource.start = IOMEM_RESOURCE_START; 73 iomem_resource.start = IOMEM_RESOURCE_START;
115 iomem_resource.end = IOMEM_RESOURCE_END; 74 iomem_resource.end = IOMEM_RESOURCE_END;
116
117 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
118 au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
119 au_sync();
120 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
121 au_writel(0, SYS_TOYTRIM);
122} 75}
123 76
124#if defined(CONFIG_64BIT_PHYS_ADDR) 77#if defined(CONFIG_64BIT_PHYS_ADDR)
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 3006e270c8bc..4f4b16741d12 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -15,16 +15,17 @@
15#include <asm/regdef.h> 15#include <asm/regdef.h>
16#include <asm/stackframe.h> 16#include <asm/stackframe.h>
17 17
18 .extern __flush_cache_all
19
18 .text 20 .text
19 .set macro 21 .set noreorder
20 .set noat 22 .set noat
21 .align 5 23 .align 5
22 24
23/* Save all of the processor general registers and go to sleep. 25/* Save all of the processor general registers and go to sleep.
24 * A wakeup condition will get us back here to restore the registers. 26 * A wakeup condition will get us back here to restore the registers.
25 */ 27 */
26LEAF(save_and_sleep) 28LEAF(au1xxx_save_and_sleep)
27
28 subu sp, PT_SIZE 29 subu sp, PT_SIZE
29 sw $1, PT_R1(sp) 30 sw $1, PT_R1(sp)
30 sw $2, PT_R2(sp) 31 sw $2, PT_R2(sp)
@@ -33,14 +34,6 @@ LEAF(save_and_sleep)
33 sw $5, PT_R5(sp) 34 sw $5, PT_R5(sp)
34 sw $6, PT_R6(sp) 35 sw $6, PT_R6(sp)
35 sw $7, PT_R7(sp) 36 sw $7, PT_R7(sp)
36 sw $8, PT_R8(sp)
37 sw $9, PT_R9(sp)
38 sw $10, PT_R10(sp)
39 sw $11, PT_R11(sp)
40 sw $12, PT_R12(sp)
41 sw $13, PT_R13(sp)
42 sw $14, PT_R14(sp)
43 sw $15, PT_R15(sp)
44 sw $16, PT_R16(sp) 37 sw $16, PT_R16(sp)
45 sw $17, PT_R17(sp) 38 sw $17, PT_R17(sp)
46 sw $18, PT_R18(sp) 39 sw $18, PT_R18(sp)
@@ -49,12 +42,9 @@ LEAF(save_and_sleep)
49 sw $21, PT_R21(sp) 42 sw $21, PT_R21(sp)
50 sw $22, PT_R22(sp) 43 sw $22, PT_R22(sp)
51 sw $23, PT_R23(sp) 44 sw $23, PT_R23(sp)
52 sw $24, PT_R24(sp)
53 sw $25, PT_R25(sp)
54 sw $26, PT_R26(sp) 45 sw $26, PT_R26(sp)
55 sw $27, PT_R27(sp) 46 sw $27, PT_R27(sp)
56 sw $28, PT_R28(sp) 47 sw $28, PT_R28(sp)
57 sw $29, PT_R29(sp)
58 sw $30, PT_R30(sp) 48 sw $30, PT_R30(sp)
59 sw $31, PT_R31(sp) 49 sw $31, PT_R31(sp)
60 mfc0 k0, CP0_STATUS 50 mfc0 k0, CP0_STATUS
@@ -66,20 +56,26 @@ LEAF(save_and_sleep)
66 mfc0 k0, CP0_CONFIG 56 mfc0 k0, CP0_CONFIG
67 sw k0, 0x14(sp) 57 sw k0, 0x14(sp)
68 58
59 /* flush caches to make sure context is in memory */
60 la t1, __flush_cache_all
61 lw t0, 0(t1)
62 jalr t0
63 nop
64
69 /* Now set up the scratch registers so the boot rom will 65 /* Now set up the scratch registers so the boot rom will
70 * return to this point upon wakeup. 66 * return to this point upon wakeup.
67 * sys_scratch0 : SP
68 * sys_scratch1 : RA
71 */ 69 */
72 la k0, 1f 70 lui t3, 0xb190 /* sys_xxx */
73 lui k1, 0xb190 71 sw sp, 0x0018(t3)
74 ori k1, 0x18 72 la k0, 3f /* resume path */
75 sw sp, 0(k1) 73 sw k0, 0x001c(t3)
76 ori k1, 0x1c
77 sw k0, 0(k1)
78 74
79/* Put SDRAM into self refresh. Preload instructions into cache, 75 /* Put SDRAM into self refresh: Preload instructions into cache,
80 * issue a precharge, then auto refresh, then sleep commands to it. 76 * issue a precharge, auto/self refresh, then sleep commands to it.
81 */ 77 */
82 la t0, sdsleep 78 la t0, 1f
83 .set mips3 79 .set mips3
84 cache 0x14, 0(t0) 80 cache 0x14, 0(t0)
85 cache 0x14, 32(t0) 81 cache 0x14, 32(t0)
@@ -87,24 +83,57 @@ LEAF(save_and_sleep)
87 cache 0x14, 96(t0) 83 cache 0x14, 96(t0)
88 .set mips0 84 .set mips0
89 85
90sdsleep: 861: lui a0, 0xb400 /* mem_xxx */
91 lui k0, 0xb400 87#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \
92 sw zero, 0x001c(k0) /* Precharge */ 88 defined(CONFIG_SOC_AU1500)
93 sw zero, 0x0020(k0) /* Auto refresh */ 89 sw zero, 0x001c(a0) /* Precharge */
94 sw zero, 0x0030(k0) /* SDRAM sleep */ 90 sync
91 sw zero, 0x0020(a0) /* Auto Refresh */
92 sync
93 sw zero, 0x0030(a0) /* Sleep */
94 sync
95#endif
96
97#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
98 sw zero, 0x08c0(a0) /* Precharge */
95 sync 99 sync
100 sw zero, 0x08d0(a0) /* Self Refresh */
101 sync
102
103 /* wait for sdram to enter self-refresh mode */
104 lui t0, 0x0100
1052: lw t1, 0x0850(a0) /* mem_sdstat */
106 and t2, t1, t0
107 beq t2, zero, 2b
108 nop
96 109
97 lui k1, 0xb190 110 /* disable SDRAM clocks */
98 sw zero, 0x0078(k1) /* get ready to sleep */ 111 lui t0, 0xcfff
112 ori t0, t0, 0xffff
113 lw t1, 0x0840(a0) /* mem_sdconfiga */
114 and t1, t0, t1 /* clear CE[1:0] */
115 sw t1, 0x0840(a0) /* mem_sdconfiga */
99 sync 116 sync
100 sw zero, 0x007c(k1) /* Put processor to sleep */ 117#endif
118
119 /* put power supply and processor to sleep */
120 sw zero, 0x0078(t3) /* sys_slppwr */
121 sync
122 sw zero, 0x007c(t3) /* sys_sleep */
101 sync 123 sync
124 nop
125 nop
126 nop
127 nop
128 nop
129 nop
130 nop
131 nop
102 132
103 /* This is where we return upon wakeup. 133 /* This is where we return upon wakeup.
104 * Reload all of the registers and return. 134 * Reload all of the registers and return.
105 */ 135 */
1061: nop 1363: lw k0, 0x20(sp)
107 lw k0, 0x20(sp)
108 mtc0 k0, CP0_STATUS 137 mtc0 k0, CP0_STATUS
109 lw k0, 0x1c(sp) 138 lw k0, 0x1c(sp)
110 mtc0 k0, CP0_CONTEXT 139 mtc0 k0, CP0_CONTEXT
@@ -113,10 +142,11 @@ sdsleep:
113 lw k0, 0x14(sp) 142 lw k0, 0x14(sp)
114 mtc0 k0, CP0_CONFIG 143 mtc0 k0, CP0_CONFIG
115 144
116 /* We need to catch the ealry Alchemy SOCs with 145 /* We need to catch the early Alchemy SOCs with
117 * the write-only Config[OD] bit and set it back to one... 146 * the write-only Config[OD] bit and set it back to one...
118 */ 147 */
119 jal au1x00_fixup_config_od 148 jal au1x00_fixup_config_od
149 nop
120 lw $1, PT_R1(sp) 150 lw $1, PT_R1(sp)
121 lw $2, PT_R2(sp) 151 lw $2, PT_R2(sp)
122 lw $3, PT_R3(sp) 152 lw $3, PT_R3(sp)
@@ -124,14 +154,6 @@ sdsleep:
124 lw $5, PT_R5(sp) 154 lw $5, PT_R5(sp)
125 lw $6, PT_R6(sp) 155 lw $6, PT_R6(sp)
126 lw $7, PT_R7(sp) 156 lw $7, PT_R7(sp)
127 lw $8, PT_R8(sp)
128 lw $9, PT_R9(sp)
129 lw $10, PT_R10(sp)
130 lw $11, PT_R11(sp)
131 lw $12, PT_R12(sp)
132 lw $13, PT_R13(sp)
133 lw $14, PT_R14(sp)
134 lw $15, PT_R15(sp)
135 lw $16, PT_R16(sp) 157 lw $16, PT_R16(sp)
136 lw $17, PT_R17(sp) 158 lw $17, PT_R17(sp)
137 lw $18, PT_R18(sp) 159 lw $18, PT_R18(sp)
@@ -140,15 +162,11 @@ sdsleep:
140 lw $21, PT_R21(sp) 162 lw $21, PT_R21(sp)
141 lw $22, PT_R22(sp) 163 lw $22, PT_R22(sp)
142 lw $23, PT_R23(sp) 164 lw $23, PT_R23(sp)
143 lw $24, PT_R24(sp)
144 lw $25, PT_R25(sp)
145 lw $26, PT_R26(sp) 165 lw $26, PT_R26(sp)
146 lw $27, PT_R27(sp) 166 lw $27, PT_R27(sp)
147 lw $28, PT_R28(sp) 167 lw $28, PT_R28(sp)
148 lw $29, PT_R29(sp)
149 lw $30, PT_R30(sp) 168 lw $30, PT_R30(sp)
150 lw $31, PT_R31(sp) 169 lw $31, PT_R31(sp)
151 addiu sp, PT_SIZE
152
153 jr ra 170 jr ra
154END(save_and_sleep) 171 addiu sp, PT_SIZE
172END(au1xxx_save_and_sleep)
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 563d9390a872..32880146cbc1 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -1,5 +1,7 @@
1/* 1/*
2 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
2 * 3 *
4 * Previous incarnations were:
3 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> 5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
4 * Copied and modified Carsten Langgaard's time.c 6 * Copied and modified Carsten Langgaard's time.c
5 * 7 *
@@ -23,244 +25,141 @@
23 * 25 *
24 * ######################################################################## 26 * ########################################################################
25 * 27 *
26 * Setting up the clock on the MIPS boards. 28 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
27 * 29 * databooks). Firmware/Board init code must enable the counters in the
28 * We provide the clock interrupt processing and the timer offset compute 30 * counter control register, otherwise the CP0 counter clocksource/event
29 * functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is 31 * will be installed instead (and use of 'wait' instruction is prohibited).
30 * available. -- Dan
31 */ 32 */
32 33
33#include <linux/types.h> 34#include <linux/clockchips.h>
34#include <linux/init.h> 35#include <linux/clocksource.h>
36#include <linux/interrupt.h>
35#include <linux/spinlock.h> 37#include <linux/spinlock.h>
36 38
37#include <asm/mipsregs.h>
38#include <asm/time.h> 39#include <asm/time.h>
39#include <asm/mach-au1x00/au1000.h> 40#include <asm/mach-au1x00/au1000.h>
40 41
41static int no_au1xxx_32khz; 42/* 32kHz clock enabled and detected */
42extern int allow_au1k_wait; /* default off for CP0 Counter */ 43#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
43
44#ifdef CONFIG_PM
45#if HZ < 100 || HZ > 1000
46#error "unsupported HZ value! Must be in [100,1000]"
47#endif
48#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */
49static unsigned long last_pc0, last_match20;
50#endif
51 44
52static DEFINE_SPINLOCK(time_lock); 45extern int allow_au1k_wait; /* default off for CP0 Counter */
53
54unsigned long wtimer;
55 46
56#ifdef CONFIG_PM 47static cycle_t au1x_counter1_read(void)
57static irqreturn_t counter0_irq(int irq, void *dev_id)
58{ 48{
59 unsigned long pc0; 49 return au_readl(SYS_RTCREAD);
60 int time_elapsed;
61 static int jiffie_drift;
62
63 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
64 /* should never happen! */
65 printk(KERN_WARNING "counter 0 w status error\n");
66 return IRQ_NONE;
67 }
68
69 pc0 = au_readl(SYS_TOYREAD);
70 if (pc0 < last_match20)
71 /* counter overflowed */
72 time_elapsed = (0xffffffff - last_match20) + pc0;
73 else
74 time_elapsed = pc0 - last_match20;
75
76 while (time_elapsed > 0) {
77 do_timer(1);
78#ifndef CONFIG_SMP
79 update_process_times(user_mode(get_irq_regs()));
80#endif
81 time_elapsed -= MATCH20_INC;
82 last_match20 += MATCH20_INC;
83 jiffie_drift++;
84 }
85
86 last_pc0 = pc0;
87 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
88 au_sync();
89
90 /*
91 * Our counter ticks at 10.009765625 ms/tick, we we're running
92 * almost 10 uS too slow per tick.
93 */
94
95 if (jiffie_drift >= 999) {
96 jiffie_drift -= 999;
97 do_timer(1); /* increment jiffies by one */
98#ifndef CONFIG_SMP
99 update_process_times(user_mode(get_irq_regs()));
100#endif
101 }
102
103 return IRQ_HANDLED;
104} 50}
105 51
106struct irqaction counter0_action = { 52static struct clocksource au1x_counter1_clocksource = {
107 .handler = counter0_irq, 53 .name = "alchemy-counter1",
108 .flags = IRQF_DISABLED, 54 .read = au1x_counter1_read,
109 .name = "alchemy-toy", 55 .mask = CLOCKSOURCE_MASK(32),
110 .dev_id = NULL, 56 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
57 .rating = 100,
111}; 58};
112 59
113/* When we wakeup from sleep, we have to "catch up" on all of the 60static int au1x_rtcmatch2_set_next_event(unsigned long delta,
114 * timer ticks we have missed. 61 struct clock_event_device *cd)
115 */
116void wakeup_counter0_adjust(void)
117{ 62{
118 unsigned long pc0; 63 delta += au_readl(SYS_RTCREAD);
119 int time_elapsed; 64 /* wait for register access */
120 65 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
121 pc0 = au_readl(SYS_TOYREAD); 66 ;
122 if (pc0 < last_match20) 67 au_writel(delta, SYS_RTCMATCH2);
123 /* counter overflowed */
124 time_elapsed = (0xffffffff - last_match20) + pc0;
125 else
126 time_elapsed = pc0 - last_match20;
127
128 while (time_elapsed > 0) {
129 time_elapsed -= MATCH20_INC;
130 last_match20 += MATCH20_INC;
131 }
132
133 last_pc0 = pc0;
134 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
135 au_sync(); 68 au_sync();
136 69
70 return 0;
137} 71}
138 72
139/* This is just for debugging to set the timer for a sleep delay. */ 73static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
140void wakeup_counter0_set(int ticks) 74 struct clock_event_device *cd)
141{ 75{
142 unsigned long pc0;
143
144 pc0 = au_readl(SYS_TOYREAD);
145 last_pc0 = pc0;
146 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
147 au_sync();
148} 76}
149#endif
150 77
151/* 78static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
152 * I haven't found anyone that doesn't use a 12 MHz source clock,
153 * but just in case.....
154 */
155#define AU1000_SRC_CLK 12000000
156
157/*
158 * We read the real processor speed from the PLL. This is important
159 * because it is more accurate than computing it from the 32 KHz
160 * counter, if it exists. If we don't have an accurate processor
161 * speed, all of the peripherals that derive their clocks based on
162 * this advertised speed will introduce error and sometimes not work
163 * properly. This function is futher convoluted to still allow configurations
164 * to do that in case they have really, really old silicon with a
165 * write-only PLL register, that we need the 32 KHz when power management
166 * "wait" is enabled, and we need to detect if the 32 KHz isn't present
167 * but requested......got it? :-) -- Dan
168 */
169unsigned long calc_clock(void)
170{ 79{
171 unsigned long cpu_speed; 80 struct clock_event_device *cd = dev_id;
172 unsigned long flags; 81 cd->event_handler(cd);
173 unsigned long counter; 82 return IRQ_HANDLED;
174 83}
175 spin_lock_irqsave(&time_lock, flags);
176
177 /* Power management cares if we don't have a 32 KHz counter. */
178 no_au1xxx_32khz = 0;
179 counter = au_readl(SYS_COUNTER_CNTRL);
180 if (counter & SYS_CNTRL_E0) {
181 int trim_divide = 16;
182
183 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
184
185 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
186 /* RTC now ticks at 32.768/16 kHz */
187 au_writel(trim_divide - 1, SYS_RTCTRIM);
188 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
189 84
190 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 85static struct clock_event_device au1x_rtcmatch2_clockdev = {
191 au_writel(0, SYS_TOYWRITE); 86 .name = "rtcmatch2",
192 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 87 .features = CLOCK_EVT_FEAT_ONESHOT,
193 } else 88 .rating = 100,
194 no_au1xxx_32khz = 1; 89 .irq = AU1000_RTC_MATCH2_INT,
90 .set_next_event = au1x_rtcmatch2_set_next_event,
91 .set_mode = au1x_rtcmatch2_set_mode,
92 .cpumask = CPU_MASK_ALL,
93};
195 94
196 /* 95static struct irqaction au1x_rtcmatch2_irqaction = {
197 * On early Au1000, sys_cpupll was write-only. Since these 96 .handler = au1x_rtcmatch2_irq,
198 * silicon versions of Au1000 are not sold by AMD, we don't bend 97 .flags = IRQF_DISABLED | IRQF_TIMER,
199 * over backwards trying to determine the frequency. 98 .name = "timer",
200 */ 99 .dev_id = &au1x_rtcmatch2_clockdev,
201 if (cur_cpu_spec[0]->cpu_pll_wo) 100};
202#ifdef CONFIG_SOC_AU1000_FREQUENCY
203 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
204#else
205 cpu_speed = 396000000;
206#endif
207 else
208 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
209 /* On Alchemy CPU:counter ratio is 1:1 */
210 mips_hpt_frequency = cpu_speed;
211 /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
212 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
213 & 0x03) + 2) * 16));
214 spin_unlock_irqrestore(&time_lock, flags);
215 return cpu_speed;
216}
217 101
218void __init plat_time_init(void) 102void __init plat_time_init(void)
219{ 103{
220 unsigned int est_freq = calc_clock(); 104 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
221 105 unsigned long t;
222 est_freq += 5000; /* round */ 106
223 est_freq -= est_freq%10000; 107 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
224 printk(KERN_INFO "CPU frequency %u.%02u MHz\n", 108 * has been detected. If so install the rtcmatch2 clocksource,
225 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); 109 * otherwise don't bother. Note that both bits being set is by
226 set_au1x00_speed(est_freq); 110 * no means a definite guarantee that the counters actually work
227 set_au1x00_lcd_clock(); /* program the LCD clock */ 111 * (the 32S bit seems to be stuck set to 1 once a single clock-
112 * edge is detected, hence the timeouts).
113 */
114 if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
115 goto cntr_err;
228 116
229#ifdef CONFIG_PM
230 /* 117 /*
231 * setup counter 0, since it keeps ticking after a 118 * setup counter 1 (RTC) to tick at full speed
232 * 'wait' instruction has been executed. The CP0 timer and
233 * counter 1 do NOT continue running after 'wait'
234 *
235 * It's too early to call request_irq() here, so we handle
236 * counter 0 interrupt as a special irq and it doesn't show
237 * up under /proc/interrupts.
238 *
239 * Check to ensure we really have a 32 KHz oscillator before
240 * we do this.
241 */ 119 */
242 if (no_au1xxx_32khz) 120 t = 0xffffff;
243 printk(KERN_WARNING "WARNING: no 32KHz clock found.\n"); 121 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--)
244 else { 122 asm volatile ("nop");
245 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); 123 if (!t)
246 au_writel(0, SYS_TOYWRITE); 124 goto cntr_err;
247 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
248
249 au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK);
250 au_writel(~0, SYS_WAKESRC);
251 au_sync();
252 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
253 125
254 /* Setup match20 to interrupt once every HZ */ 126 au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */
255 last_pc0 = last_match20 = au_readl(SYS_TOYREAD); 127 au_sync();
256 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
257 au_sync();
258 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
259 setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
260 128
261 /* We can use the real 'wait' instruction. */ 129 t = 0xffffff;
262 allow_au1k_wait = 1; 130 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--)
263 } 131 asm volatile ("nop");
132 if (!t)
133 goto cntr_err;
134 au_writel(0, SYS_RTCWRITE);
135 au_sync();
264 136
265#endif 137 t = 0xffffff;
138 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--)
139 asm volatile ("nop");
140 if (!t)
141 goto cntr_err;
142
143 /* register counter1 clocksource and event device */
144 clocksource_set_clock(&au1x_counter1_clocksource, 32768);
145 clocksource_register(&au1x_counter1_clocksource);
146
147 cd->shift = 32;
148 cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
149 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
150 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
151 clockevents_register_device(cd);
152 setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);
153
154 printk(KERN_INFO "Alchemy clocksource installed\n");
155
156 /* can now use 'wait' */
157 allow_au1k_wait = 1;
158 return;
159
160cntr_err:
161 /* counters unusable, use C0 counter */
162 r4k_clockevent_init();
163 init_r4k_clocksource();
164 allow_au1k_wait = 0;
266} 165}
diff --git a/arch/mips/alchemy/db1x00/init.c b/arch/mips/alchemy/db1x00/init.c
deleted file mode 100644
index 847413514964..000000000000
--- a/arch/mips/alchemy/db1x00/init.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PB1000 board setup
4 *
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/kernel.h>
31
32#include <asm/bootinfo.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38#ifdef CONFIG_MIPS_BOSPORUS
39 return "Alchemy Bosporus Gateway Reference";
40#else
41 return "Alchemy Db1x00";
42#endif
43}
44
45void __init prom_init(void)
46{
47 unsigned char *memsize_str;
48 unsigned long memsize;
49
50 prom_argc = fw_arg0;
51 prom_argv = (char **)fw_arg1;
52 prom_envp = (char **)fw_arg2;
53
54 prom_init_cmdline();
55
56 memsize_str = prom_getenv("memsize");
57 if (!memsize_str)
58 memsize = 0x04000000;
59 else
60 strict_strtol(memsize_str, 0, &memsize);
61 add_memory_region(0, memsize, BOOT_MEM_RAM);
62}
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
new file mode 100644
index 000000000000..730f9f2b30e8
--- /dev/null
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -0,0 +1,18 @@
1#
2# Alchemy Develboards
3#
4
5obj-y += prom.o
6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1000) += pb1000/
8obj-$(CONFIG_MIPS_PB1100) += pb1100/
9obj-$(CONFIG_MIPS_PB1200) += pb1200/
10obj-$(CONFIG_MIPS_PB1500) += pb1500/
11obj-$(CONFIG_MIPS_PB1550) += pb1550/
12obj-$(CONFIG_MIPS_DB1000) += db1x00/
13obj-$(CONFIG_MIPS_DB1100) += db1x00/
14obj-$(CONFIG_MIPS_DB1200) += pb1200/
15obj-$(CONFIG_MIPS_DB1500) += db1x00/
16obj-$(CONFIG_MIPS_DB1550) += db1x00/
17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/
diff --git a/arch/mips/alchemy/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
index 274db3b55d82..432241ab8677 100644
--- a/arch/mips/alchemy/db1x00/Makefile
+++ b/arch/mips/alchemy/devboards/db1x00/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards. 5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o irqmap.o
diff --git a/arch/mips/alchemy/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 9e5ccbbfcedd..a75ffbf99f25 100644
--- a/arch/mips/alchemy/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -32,8 +32,20 @@
32#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
33#include <asm/mach-db1x00/db1x00.h> 33#include <asm/mach-db1x00/db1x00.h>
34 34
35#include <prom.h>
36
37
35static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; 38static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
36 39
40const char *get_system_type(void)
41{
42#ifdef CONFIG_MIPS_BOSPORUS
43 return "Alchemy Bosporus Gateway Reference";
44#else
45 return "Alchemy Db1x00";
46#endif
47}
48
37void board_reset(void) 49void board_reset(void)
38{ 50{
39 /* Hit BCSR.SW_RESET[RESET] */ 51 /* Hit BCSR.SW_RESET[RESET] */
@@ -43,6 +55,31 @@ void board_reset(void)
43void __init board_setup(void) 55void __init board_setup(void)
44{ 56{
45 u32 pin_func = 0; 57 u32 pin_func = 0;
58 char *argptr;
59
60 argptr = prom_getcmdline();
61#ifdef CONFIG_SERIAL_8250_CONSOLE
62 argptr = strstr(argptr, "console=");
63 if (argptr == NULL) {
64 argptr = prom_getcmdline();
65 strcat(argptr, " console=ttyS0,115200");
66 }
67#endif
68
69#ifdef CONFIG_FB_AU1100
70 argptr = strstr(argptr, "video=");
71 if (argptr == NULL) {
72 argptr = prom_getcmdline();
73 /* default panel */
74 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
75 }
76#endif
77
78#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
79 /* au1000 does not support vra, au1500 and au1100 do */
80 strcat(argptr, " au1000_audio=vra");
81 argptr = prom_getcmdline();
82#endif
46 83
47 /* Not valid for Au1550 */ 84 /* Not valid for Au1550 */
48#if defined(CONFIG_IRDA) && \ 85#if defined(CONFIG_IRDA) && \
diff --git a/arch/mips/alchemy/db1x00/irqmap.c b/arch/mips/alchemy/devboards/db1x00/irqmap.c
index 94c090e8bf7a..0b09025087c6 100644
--- a/arch/mips/alchemy/db1x00/irqmap.c
+++ b/arch/mips/alchemy/devboards/db1x00/irqmap.c
@@ -27,6 +27,7 @@
27 */ 27 */
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/interrupt.h>
30 31
31#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
32 33
@@ -66,21 +67,24 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
66 67
67#ifndef CONFIG_MIPS_MIRAGE 68#ifndef CONFIG_MIPS_MIRAGE
68#ifdef CONFIG_MIPS_DB1550 69#ifdef CONFIG_MIPS_DB1550
69 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ 70 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
70 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ 71 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
71#else 72#else
72 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 Fully_Interted# */ 73 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 Fully_Interted# */
73 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 STSCHG# */ 74 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 STSCHG# */
74 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ 75 { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
75 76
76 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 Fully_Interted# */ 77 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 Fully_Interted# */
77 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 STSCHG# */ 78 { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 STSCHG# */
78 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ 79 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
79#endif 80#endif
80#else 81#else
81 { AU1000_GPIO_7, INTC_INT_RISE_EDGE, 0 }, /* touchscreen pen down */ 82 { AU1000_GPIO_7, IRQF_TRIGGER_RISING, 0 }, /* touchscreen pen down */
82#endif 83#endif
83 84
84}; 85};
85 86
86int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 87void __init board_init_irq(void)
88{
89 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
90}
diff --git a/arch/mips/alchemy/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
index 99bbec0ca41b..97c6615ba2bb 100644
--- a/arch/mips/alchemy/pb1000/Makefile
+++ b/arch/mips/alchemy/devboards/pb1000/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1000 board. 5# Makefile for the Alchemy Semiconductor Pb1000 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index 25df167a95b3..aed2fdecc709 100644
--- a/arch/mips/alchemy/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -23,22 +23,48 @@
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26#include <linux/init.h>
27#include <linux/delay.h> 26#include <linux/delay.h>
28 27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <asm/mach-au1x00/au1000.h> 29#include <asm/mach-au1x00/au1000.h>
30#include <asm/mach-pb1x00/pb1000.h> 30#include <asm/mach-pb1x00/pb1000.h>
31#include <prom.h>
32
33
34struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
35 { AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 },
36};
37
38
39const char *get_system_type(void)
40{
41 return "Alchemy Pb1000";
42}
31 43
32void board_reset(void) 44void board_reset(void)
33{ 45{
34} 46}
35 47
48void __init board_init_irq(void)
49{
50 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
51}
52
36void __init board_setup(void) 53void __init board_setup(void)
37{ 54{
38 u32 pin_func, static_cfg0; 55 u32 pin_func, static_cfg0;
39 u32 sys_freqctrl, sys_clksrc; 56 u32 sys_freqctrl, sys_clksrc;
40 u32 prid = read_c0_prid(); 57 u32 prid = read_c0_prid();
41 58
59#ifdef CONFIG_SERIAL_8250_CONSOLE
60 char *argptr = prom_getcmdline();
61 argptr = strstr(argptr, "console=");
62 if (argptr == NULL) {
63 argptr = prom_getcmdline();
64 strcat(argptr, " console=ttyS0,115200");
65 }
66#endif
67
42 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 68 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
43 au_writel(8, SYS_AUXPLL); 69 au_writel(8, SYS_AUXPLL);
44 au_writel(0, SYS_PINSTATERD); 70 au_writel(0, SYS_PINSTATERD);
diff --git a/arch/mips/alchemy/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
index 793e97c49e46..c586dd7e91dc 100644
--- a/arch/mips/alchemy/pb1100/Makefile
+++ b/arch/mips/alchemy/devboards/pb1100/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1100 board. 5# Makefile for the Alchemy Semiconductor Pb1100 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index c0bfd59a7a36..4df57fae15d4 100644
--- a/arch/mips/alchemy/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -25,19 +25,66 @@
25 25
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/interrupt.h>
28 29
29#include <asm/mach-au1x00/au1000.h> 30#include <asm/mach-au1x00/au1000.h>
30#include <asm/mach-pb1x00/pb1100.h> 31#include <asm/mach-pb1x00/pb1100.h>
31 32
33#include <prom.h>
34
35
36struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
37 { AU1000_GPIO_9, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card Fully_Inserted# */
38 { AU1000_GPIO_10, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card STSCHG# */
39 { AU1000_GPIO_11, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card IRQ# */
40 { AU1000_GPIO_13, IRQF_TRIGGER_LOW, 0 }, /* DC_IRQ# */
41};
42
43
44const char *get_system_type(void)
45{
46 return "Alchemy Pb1100";
47}
48
32void board_reset(void) 49void board_reset(void)
33{ 50{
34 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 51 /* Hit BCSR.RST_VDDI[SOFT_RESET] */
35 au_writel(0x00000000, PB1100_RST_VDDI); 52 au_writel(0x00000000, PB1100_RST_VDDI);
36} 53}
37 54
55void __init board_init_irq(void)
56{
57 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
58}
59
38void __init board_setup(void) 60void __init board_setup(void)
39{ 61{
40 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; 62 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
63 char *argptr;
64
65 argptr = prom_getcmdline();
66#ifdef CONFIG_SERIAL_8250_CONSOLE
67 argptr = strstr(argptr, "console=");
68 if (argptr == NULL) {
69 argptr = prom_getcmdline();
70 strcat(argptr, " console=ttyS0,115200");
71 }
72#endif
73
74#ifdef CONFIG_FB_AU1100
75 argptr = strstr(argptr, "video=");
76 if (argptr == NULL) {
77 argptr = prom_getcmdline();
78 /* default panel */
79 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
80 }
81#endif
82
83#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
84 /* au1000 does not support vra, au1500 and au1100 do */
85 strcat(argptr, " au1000_audio=vra");
86 argptr = prom_getcmdline();
87#endif
41 88
42 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 89 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
43 au_writel(8, SYS_AUXPLL); 90 au_writel(8, SYS_AUXPLL);
diff --git a/arch/mips/alchemy/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
index d678adf7ce85..c8c3a99fb68a 100644
--- a/arch/mips/alchemy/pb1200/Makefile
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -2,7 +2,6 @@
2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. 2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3# 3#
4 4
5lib-y := init.o board_setup.o irqmap.o 5obj-y := board_setup.o irqmap.o platform.o
6obj-y += platform.o
7 6
8EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 6cb2115059ad..94e6b7e7753d 100644
--- a/arch/mips/alchemy/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -30,8 +30,11 @@
30#include <prom.h> 30#include <prom.h>
31#include <au1xxx.h> 31#include <au1xxx.h>
32 32
33extern void _board_init_irq(void); 33
34extern void (*board_init_irq)(void); 34const char *get_system_type(void)
35{
36 return "Alchemy Pb1200";
37}
35 38
36void board_reset(void) 39void board_reset(void)
37{ 40{
@@ -41,7 +44,19 @@ void board_reset(void)
41 44
42void __init board_setup(void) 45void __init board_setup(void)
43{ 46{
44 char *argptr = NULL; 47 char *argptr;
48
49 argptr = prom_getcmdline();
50#ifdef CONFIG_SERIAL_8250_CONSOLE
51 argptr = strstr(argptr, "console=");
52 if (argptr == NULL) {
53 argptr = prom_getcmdline();
54 strcat(argptr, " console=ttyS0,115200");
55 }
56#endif
57#ifdef CONFIG_FB_AU1200
58 strcat(argptr, " video=au1200fb:panel:bs");
59#endif
45 60
46#if 0 61#if 0
47 { 62 {
@@ -99,16 +114,6 @@ void __init board_setup(void)
99 } 114 }
100#endif 115#endif
101 116
102#ifdef CONFIG_FB_AU1200
103 argptr = prom_getcmdline();
104#ifdef CONFIG_MIPS_PB1200
105 strcat(argptr, " video=au1200fb:panel:bs");
106#endif
107#ifdef CONFIG_MIPS_DB1200
108 strcat(argptr, " video=au1200fb:panel:bs");
109#endif
110#endif
111
112 /* 117 /*
113 * The Pb1200 development board uses external MUX for PSC0 to 118 * The Pb1200 development board uses external MUX for PSC0 to
114 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI 119 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
@@ -124,9 +129,6 @@ void __init board_setup(void)
124#ifdef CONFIG_MIPS_DB1200 129#ifdef CONFIG_MIPS_DB1200
125 printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); 130 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
126#endif 131#endif
127
128 /* Setup Pb1200 External Interrupt Controller */
129 board_init_irq = _board_init_irq;
130} 132}
131 133
132int board_au1200fb_panel(void) 134int board_au1200fb_panel(void)
diff --git a/arch/mips/alchemy/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c
index 2a505ad8715b..fe47498da280 100644
--- a/arch/mips/alchemy/pb1200/irqmap.c
+++ b/arch/mips/alchemy/devboards/pb1200/irqmap.c
@@ -40,91 +40,65 @@
40 40
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 /* This is external interrupt cascade */ 42 /* This is external interrupt cascade */
43 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, 43 { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 },
44}; 44};
45 45
46int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
47 46
48/* 47/*
49 * Support for External interrupts on the Pb1200 Development platform. 48 * Support for External interrupts on the Pb1200 Development platform.
50 */ 49 */
51static volatile int pb1200_cascade_en;
52 50
53irqreturn_t pb1200_cascade_handler(int irq, void *dev_id) 51static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
54{ 52{
55 unsigned short bisr = bcsr->int_status; 53 unsigned short bisr = bcsr->int_status;
56 int extirq_nr = 0;
57
58 /* Clear all the edge interrupts. This has no effect on level. */
59 bcsr->int_status = bisr;
60 for ( ; bisr; bisr &= bisr - 1) {
61 extirq_nr = PB1200_INT_BEGIN + __ffs(bisr);
62 /* Ack and dispatch IRQ */
63 do_IRQ(extirq_nr);
64 }
65
66 return IRQ_RETVAL(1);
67}
68 54
69inline void pb1200_enable_irq(unsigned int irq_nr) 55 for ( ; bisr; bisr &= bisr - 1)
70{ 56 generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr));
71 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
72 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
73} 57}
74 58
75inline void pb1200_disable_irq(unsigned int irq_nr) 59/* NOTE: both the enable and mask bits must be cleared, otherwise the
60 * CPLD generates tons of spurious interrupts (at least on the DB1200).
61 */
62static void pb1200_mask_irq(unsigned int irq_nr)
76{ 63{
77 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); 64 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
78 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); 65 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
66 au_sync();
79} 67}
80 68
81static unsigned int pb1200_setup_cascade(void) 69static void pb1200_maskack_irq(unsigned int irq_nr)
82{
83 return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
84 0, "Pb1200 Cascade", &pb1200_cascade_handler);
85}
86
87static unsigned int pb1200_startup_irq(unsigned int irq)
88{ 70{
89 if (++pb1200_cascade_en == 1) { 71 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
90 int res; 72 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
91 73 bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */
92 res = pb1200_setup_cascade(); 74 au_sync();
93 if (res)
94 return res;
95 }
96
97 pb1200_enable_irq(irq);
98
99 return 0;
100} 75}
101 76
102static void pb1200_shutdown_irq(unsigned int irq) 77static void pb1200_unmask_irq(unsigned int irq_nr)
103{ 78{
104 pb1200_disable_irq(irq); 79 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
105 if (--pb1200_cascade_en == 0) 80 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
106 free_irq(AU1000_GPIO_7, &pb1200_cascade_handler); 81 au_sync();
107} 82}
108 83
109static struct irq_chip external_irq_type = { 84static struct irq_chip pb1200_cpld_irq_type = {
110#ifdef CONFIG_MIPS_PB1200 85#ifdef CONFIG_MIPS_PB1200
111 .name = "Pb1200 Ext", 86 .name = "Pb1200 Ext",
112#endif 87#endif
113#ifdef CONFIG_MIPS_DB1200 88#ifdef CONFIG_MIPS_DB1200
114 .name = "Db1200 Ext", 89 .name = "Db1200 Ext",
115#endif 90#endif
116 .startup = pb1200_startup_irq, 91 .mask = pb1200_mask_irq,
117 .shutdown = pb1200_shutdown_irq, 92 .mask_ack = pb1200_maskack_irq,
118 .ack = pb1200_disable_irq, 93 .unmask = pb1200_unmask_irq,
119 .mask = pb1200_disable_irq,
120 .mask_ack = pb1200_disable_irq,
121 .unmask = pb1200_enable_irq,
122}; 94};
123 95
124void _board_init_irq(void) 96void __init board_init_irq(void)
125{ 97{
126 unsigned int irq; 98 unsigned int irq;
127 99
100 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
101
128#ifdef CONFIG_MIPS_PB1200 102#ifdef CONFIG_MIPS_PB1200
129 /* We have a problem with CPLD rev 3. */ 103 /* We have a problem with CPLD rev 3. */
130 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { 104 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
@@ -146,15 +120,15 @@ void _board_init_irq(void)
146 panic("Game over. Your score is 0."); 120 panic("Game over. Your score is 0.");
147 } 121 }
148#endif 122#endif
123 /* mask & disable & ack all */
124 bcsr->intclr_mask = 0xffff;
125 bcsr->intclr = 0xffff;
126 bcsr->int_status = 0xffff;
127 au_sync();
149 128
150 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) { 129 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++)
151 set_irq_chip_and_handler(irq, &external_irq_type, 130 set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type,
152 handle_level_irq); 131 handle_level_irq, "level");
153 pb1200_disable_irq(irq);
154 }
155 132
156 /* 133 set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler);
157 * GPIO_7 can not be hooked here, so it is hooked upon first
158 * request of any source attached to the cascade.
159 */
160} 134}
diff --git a/arch/mips/alchemy/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 95303297c534..95303297c534 100644
--- a/arch/mips/alchemy/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
diff --git a/arch/mips/alchemy/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
index 602f38df20bb..173b419a7479 100644
--- a/arch/mips/alchemy/pb1500/Makefile
+++ b/arch/mips/alchemy/devboards/pb1500/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1500 board. 5# Makefile for the Alchemy Semiconductor Pb1500 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 035771c6e5b8..fed3b093156a 100644
--- a/arch/mips/alchemy/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -25,20 +25,64 @@
25 25
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/interrupt.h>
28 29
29#include <asm/mach-au1x00/au1000.h> 30#include <asm/mach-au1x00/au1000.h>
30#include <asm/mach-pb1x00/pb1500.h> 31#include <asm/mach-pb1x00/pb1500.h>
31 32
33#include <prom.h>
34
35
36char irq_tab_alchemy[][5] __initdata = {
37 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
38 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
39};
40
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
43 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
44 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
45 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
46 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
47};
48
49
50const char *get_system_type(void)
51{
52 return "Alchemy Pb1500";
53}
54
32void board_reset(void) 55void board_reset(void)
33{ 56{
34 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 57 /* Hit BCSR.RST_VDDI[SOFT_RESET] */
35 au_writel(0x00000000, PB1500_RST_VDDI); 58 au_writel(0x00000000, PB1500_RST_VDDI);
36} 59}
37 60
61void __init board_init_irq(void)
62{
63 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
64}
65
38void __init board_setup(void) 66void __init board_setup(void)
39{ 67{
40 u32 pin_func; 68 u32 pin_func;
41 u32 sys_freqctrl, sys_clksrc; 69 u32 sys_freqctrl, sys_clksrc;
70 char *argptr;
71
72 argptr = prom_getcmdline();
73#ifdef CONFIG_SERIAL_8250_CONSOLE
74 argptr = strstr(argptr, "console=");
75 if (argptr == NULL) {
76 argptr = prom_getcmdline();
77 strcat(argptr, " console=ttyS0,115200");
78 }
79#endif
80
81#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
82 /* au1000 does not support vra, au1500 and au1100 do */
83 strcat(argptr, " au1000_audio=vra");
84 argptr = prom_getcmdline();
85#endif
42 86
43 sys_clksrc = sys_freqctrl = pin_func = 0; 87 sys_clksrc = sys_freqctrl = pin_func = 0;
44 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 88 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
diff --git a/arch/mips/alchemy/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
index 7d8beca87fa5..cff95bcdb2ca 100644
--- a/arch/mips/alchemy/pb1550/Makefile
+++ b/arch/mips/alchemy/devboards/pb1550/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1550 board. 5# Makefile for the Alchemy Semiconductor Pb1550 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index 0ed76b64b6ab..b6e9e7d247a3 100644
--- a/arch/mips/alchemy/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -28,20 +28,54 @@
28 */ 28 */
29 29
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/interrupt.h>
31 32
32#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
33#include <asm/mach-pb1x00/pb1550.h> 34#include <asm/mach-pb1x00/pb1550.h>
34 35
36#include <prom.h>
37
38
39char irq_tab_alchemy[][5] __initdata = {
40 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
41 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
42};
43
44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
45 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
46 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
47};
48
49const char *get_system_type(void)
50{
51 return "Alchemy Pb1550";
52}
53
35void board_reset(void) 54void board_reset(void)
36{ 55{
37 /* Hit BCSR.SYSTEM[RESET] */ 56 /* Hit BCSR.SYSTEM[RESET] */
38 au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C); 57 au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
39} 58}
40 59
60void __init board_init_irq(void)
61{
62 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
63}
64
41void __init board_setup(void) 65void __init board_setup(void)
42{ 66{
43 u32 pin_func; 67 u32 pin_func;
44 68
69#ifdef CONFIG_SERIAL_8250_CONSOLE
70 char *argptr;
71 argptr = prom_getcmdline();
72 argptr = strstr(argptr, "console=");
73 if (argptr == NULL) {
74 argptr = prom_getcmdline();
75 strcat(argptr, " console=ttyS0,115200");
76 }
77#endif
78
45 /* 79 /*
46 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, 80 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
47 * but it is board specific code, so put it here. 81 * but it is board specific code, so put it here.
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
new file mode 100644
index 000000000000..d5eb9c325ed0
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -0,0 +1,229 @@
1/*
2 * Alchemy Development Board example suspend userspace interface.
3 *
4 * (c) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
5 */
6
7#include <linux/init.h>
8#include <linux/kobject.h>
9#include <linux/suspend.h>
10#include <linux/sysfs.h>
11#include <asm/mach-au1x00/au1000.h>
12
13/*
14 * Generic suspend userspace interface for Alchemy development boards.
15 * This code exports a few sysfs nodes under /sys/power/db1x/ which
16 * can be used by userspace to en/disable all au1x-provided wakeup
17 * sources and configure the timeout after which the the TOYMATCH2 irq
18 * is to trigger a wakeup.
19 */
20
21
22static unsigned long db1x_pm_sleep_secs;
23static unsigned long db1x_pm_wakemsk;
24static unsigned long db1x_pm_last_wakesrc;
25
26static int db1x_pm_enter(suspend_state_t state)
27{
28 /* enable GPIO based wakeup */
29 au_writel(1, SYS_PININPUTEN);
30
31 /* clear and setup wake cause and source */
32 au_writel(0, SYS_WAKEMSK);
33 au_sync();
34 au_writel(0, SYS_WAKESRC);
35 au_sync();
36
37 au_writel(db1x_pm_wakemsk, SYS_WAKEMSK);
38 au_sync();
39
40 /* setup 1Hz-timer-based wakeup: wait for reg access */
41 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
42 asm volatile ("nop");
43
44 au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2);
45 au_sync();
46
47 /* wait for value to really hit the register */
48 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
49 asm volatile ("nop");
50
51 /* ...and now the sandman can come! */
52 au_sleep();
53
54 return 0;
55}
56
57static int db1x_pm_begin(suspend_state_t state)
58{
59 if (!db1x_pm_wakemsk) {
60 printk(KERN_ERR "db1x: no wakeup source activated!\n");
61 return -EINVAL;
62 }
63
64 return 0;
65}
66
67static void db1x_pm_end(void)
68{
69 /* read and store wakeup source, the clear the register. To
70 * be able to clear it, WAKEMSK must be cleared first.
71 */
72 db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
73
74 au_writel(0, SYS_WAKEMSK);
75 au_writel(0, SYS_WAKESRC);
76 au_sync();
77
78}
79
80static struct platform_suspend_ops db1x_pm_ops = {
81 .valid = suspend_valid_only_mem,
82 .begin = db1x_pm_begin,
83 .enter = db1x_pm_enter,
84 .end = db1x_pm_end,
85};
86
87#define ATTRCMP(x) (0 == strcmp(attr->attr.name, #x))
88
89static ssize_t db1x_pmattr_show(struct kobject *kobj,
90 struct kobj_attribute *attr,
91 char *buf)
92{
93 int idx;
94
95 if (ATTRCMP(timer_timeout))
96 return sprintf(buf, "%lu\n", db1x_pm_sleep_secs);
97
98 else if (ATTRCMP(timer))
99 return sprintf(buf, "%u\n",
100 !!(db1x_pm_wakemsk & SYS_WAKEMSK_M2));
101
102 else if (ATTRCMP(wakesrc))
103 return sprintf(buf, "%lu\n", db1x_pm_last_wakesrc);
104
105 else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) ||
106 ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) ||
107 ATTRCMP(gpio6) || ATTRCMP(gpio7)) {
108 idx = (attr->attr.name)[4] - '0';
109 return sprintf(buf, "%d\n",
110 !!(db1x_pm_wakemsk & SYS_WAKEMSK_GPIO(idx)));
111
112 } else if (ATTRCMP(wakemsk)) {
113 return sprintf(buf, "%08lx\n", db1x_pm_wakemsk);
114 }
115
116 return -ENOENT;
117}
118
119static ssize_t db1x_pmattr_store(struct kobject *kobj,
120 struct kobj_attribute *attr,
121 const char *instr,
122 size_t bytes)
123{
124 unsigned long l;
125 int tmp;
126
127 if (ATTRCMP(timer_timeout)) {
128 tmp = strict_strtoul(instr, 0, &l);
129 if (tmp)
130 return tmp;
131
132 db1x_pm_sleep_secs = l;
133
134 } else if (ATTRCMP(timer)) {
135 if (instr[0] != '0')
136 db1x_pm_wakemsk |= SYS_WAKEMSK_M2;
137 else
138 db1x_pm_wakemsk &= ~SYS_WAKEMSK_M2;
139
140 } else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) ||
141 ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) ||
142 ATTRCMP(gpio6) || ATTRCMP(gpio7)) {
143 tmp = (attr->attr.name)[4] - '0';
144 if (instr[0] != '0') {
145 db1x_pm_wakemsk |= SYS_WAKEMSK_GPIO(tmp);
146 } else {
147 db1x_pm_wakemsk &= ~SYS_WAKEMSK_GPIO(tmp);
148 }
149
150 } else if (ATTRCMP(wakemsk)) {
151 tmp = strict_strtoul(instr, 0, &l);
152 if (tmp)
153 return tmp;
154
155 db1x_pm_wakemsk = l & 0x0000003f;
156
157 } else
158 bytes = -ENOENT;
159
160 return bytes;
161}
162
163#define ATTR(x) \
164 static struct kobj_attribute x##_attribute = \
165 __ATTR(x, 0664, db1x_pmattr_show, \
166 db1x_pmattr_store);
167
168ATTR(gpio0) /* GPIO-based wakeup enable */
169ATTR(gpio1)
170ATTR(gpio2)
171ATTR(gpio3)
172ATTR(gpio4)
173ATTR(gpio5)
174ATTR(gpio6)
175ATTR(gpio7)
176ATTR(timer) /* TOYMATCH2-based wakeup enable */
177ATTR(timer_timeout) /* timer-based wakeup timeout value, in seconds */
178ATTR(wakesrc) /* contents of SYS_WAKESRC after last wakeup */
179ATTR(wakemsk) /* direct access to SYS_WAKEMSK */
180
181#define ATTR_LIST(x) & x ## _attribute.attr
182static struct attribute *db1x_pmattrs[] = {
183 ATTR_LIST(gpio0),
184 ATTR_LIST(gpio1),
185 ATTR_LIST(gpio2),
186 ATTR_LIST(gpio3),
187 ATTR_LIST(gpio4),
188 ATTR_LIST(gpio5),
189 ATTR_LIST(gpio6),
190 ATTR_LIST(gpio7),
191 ATTR_LIST(timer),
192 ATTR_LIST(timer_timeout),
193 ATTR_LIST(wakesrc),
194 ATTR_LIST(wakemsk),
195 NULL, /* terminator */
196};
197
198static struct attribute_group db1x_pmattr_group = {
199 .name = "db1x",
200 .attrs = db1x_pmattrs,
201};
202
203/*
204 * Initialize suspend interface
205 */
206static int __init pm_init(void)
207{
208 /* init TOY to tick at 1Hz if not already done. No need to wait
209 * for confirmation since there's plenty of time from here to
210 * the next suspend cycle.
211 */
212 if (au_readl(SYS_TOYTRIM) != 32767) {
213 au_writel(32767, SYS_TOYTRIM);
214 au_sync();
215 }
216
217 db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
218
219 au_writel(0, SYS_WAKESRC);
220 au_sync();
221 au_writel(0, SYS_WAKEMSK);
222 au_sync();
223
224 suspend_set_ops(&db1x_pm_ops);
225
226 return sysfs_create_group(power_kobj, &db1x_pmattr_group);
227}
228
229late_initcall(pm_init);
diff --git a/arch/mips/alchemy/pb1200/init.c b/arch/mips/alchemy/devboards/prom.c
index e9b2a0fd48ae..0042bd6b1d7d 100644
--- a/arch/mips/alchemy/pb1200/init.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common code used by all Alchemy develboards.
2 * 3 *
3 * BRIEF MODULE DESCRIPTION 4 * Extracted from files which had this to say:
4 * PB1200 board setup
5 * 5 *
6 * Copyright 2001, 2008 MontaVista Software Inc. 6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com> 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
@@ -29,15 +29,19 @@
29 29
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h> 32#include <asm/bootinfo.h>
34 33#include <asm/mach-au1x00/au1000.h>
35#include <prom.h> 34#include <prom.h>
36 35
37const char *get_system_type(void) 36#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \
38{ 37 defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \
39 return "Alchemy Pb1200"; 38 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \
40} 39 defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
40#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000
41
42#else /* Au1550/Au1200-based develboards */
43#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000
44#endif
41 45
42void __init prom_init(void) 46void __init prom_init(void)
43{ 47{
@@ -51,8 +55,8 @@ void __init prom_init(void)
51 prom_init_cmdline(); 55 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize"); 56 memsize_str = prom_getenv("memsize");
53 if (!memsize_str) 57 if (!memsize_str)
54 memsize = 0x08000000; 58 memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
55 else 59 else
56 strict_strtol(memsize_str, 0, &memsize); 60 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 61 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 62}
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3f8079186cf2..8ed1ae12bc55 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -32,6 +32,8 @@
32 32
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34 34
35#include <prom.h>
36
35extern int (*board_pci_idsel)(unsigned int devsel, int assert); 37extern int (*board_pci_idsel)(unsigned int devsel, int assert);
36int mtx1_pci_idsel(unsigned int devsel, int assert); 38int mtx1_pci_idsel(unsigned int devsel, int assert);
37 39
@@ -43,6 +45,16 @@ void board_reset(void)
43 45
44void __init board_setup(void) 46void __init board_setup(void)
45{ 47{
48#ifdef CONFIG_SERIAL_8250_CONSOLE
49 char *argptr;
50 argptr = prom_getcmdline();
51 argptr = strstr(argptr, "console=");
52 if (argptr == NULL) {
53 argptr = prom_getcmdline();
54 strcat(argptr, " console=ttyS0,115200");
55 }
56#endif
57
46#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 58#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
47 /* Enable USB power switch */ 59 /* Enable USB power switch */
48 au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); 60 au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
index 3bae13c28954..5e871c8d9e96 100644
--- a/arch/mips/alchemy/mtx-1/init.c
+++ b/arch/mips/alchemy/mtx-1/init.c
@@ -55,6 +55,6 @@ void __init prom_init(void)
55 if (!memsize_str) 55 if (!memsize_str)
56 memsize = 0x04000000; 56 memsize = 0x04000000;
57 else 57 else
58 strict_strtol(memsize_str, 0, &memsize); 58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 60}
diff --git a/arch/mips/alchemy/mtx-1/irqmap.c b/arch/mips/alchemy/mtx-1/irqmap.c
index f2bf02951e9c..f1ab12ab3433 100644
--- a/arch/mips/alchemy/mtx-1/irqmap.c
+++ b/arch/mips/alchemy/mtx-1/irqmap.c
@@ -27,7 +27,7 @@
27 */ 27 */
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30 30#include <linux/interrupt.h>
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32 32
33char irq_tab_alchemy[][5] __initdata = { 33char irq_tab_alchemy[][5] __initdata = {
@@ -42,11 +42,15 @@ char irq_tab_alchemy[][5] __initdata = {
42}; 42};
43 43
44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
45 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, 45 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
46 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 46 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
47 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, 47 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
48 { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, 48 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
49 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, 49 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
50}; 50};
51 51
52int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 52
53void __init board_init_irq(void)
54{
55 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
56}
diff --git a/arch/mips/alchemy/pb1000/init.c b/arch/mips/alchemy/pb1000/init.c
deleted file mode 100644
index 8a9c7d57208d..000000000000
--- a/arch/mips/alchemy/pb1000/init.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Pb1000 board setup
4 *
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/kernel.h>
31
32#include <asm/bootinfo.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38 return "Alchemy Pb1000";
39}
40
41void __init prom_init(void)
42{
43 unsigned char *memsize_str;
44 unsigned long memsize;
45
46 prom_argc = (int)fw_arg0;
47 prom_argv = (char **)fw_arg1;
48 prom_envp = (char **)fw_arg2;
49
50 prom_init_cmdline();
51 memsize_str = prom_getenv("memsize");
52 if (!memsize_str)
53 memsize = 0x04000000;
54 else
55 strict_strtol(memsize_str, 0, &memsize);
56 add_memory_region(0, memsize, BOOT_MEM_RAM);
57}
diff --git a/arch/mips/alchemy/pb1000/irqmap.c b/arch/mips/alchemy/pb1000/irqmap.c
deleted file mode 100644
index b3d56b0af321..000000000000
--- a/arch/mips/alchemy/pb1000/irqmap.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/interrupt.h>
31
32#include <asm/mach-au1x00/au1000.h>
33
34struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
35 { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
36};
37
38int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/pb1100/init.c b/arch/mips/alchemy/pb1100/init.c
deleted file mode 100644
index 7c6792308bc5..000000000000
--- a/arch/mips/alchemy/pb1100/init.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Pb1100 board setup
5 *
6 * Copyright 2002, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1100";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg3;
50
51 prom_init_cmdline();
52
53 memsize_str = prom_getenv("memsize");
54 if (!memsize_str)
55 memsize = 0x04000000;
56 else
57 strict_strtol(memsize_str, 0, &memsize);
58
59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60}
diff --git a/arch/mips/alchemy/pb1100/irqmap.c b/arch/mips/alchemy/pb1100/irqmap.c
deleted file mode 100644
index 9b7dd8b41283..000000000000
--- a/arch/mips/alchemy/pb1100/irqmap.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 IRQ map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30
31#include <asm/mach-au1x00/au1000.h>
32
33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
34 { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card Fully_Inserted# */
35 { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card STSCHG# */
36 { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card IRQ# */
37 { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, /* DC_IRQ# */
38};
39
40int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/pb1500/init.c b/arch/mips/alchemy/pb1500/init.c
deleted file mode 100644
index 3b6e395cf952..000000000000
--- a/arch/mips/alchemy/pb1500/init.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Pb1500 board setup
5 *
6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1500";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = (int)fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x04000000;
55 else
56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
diff --git a/arch/mips/alchemy/pb1500/irqmap.c b/arch/mips/alchemy/pb1500/irqmap.c
deleted file mode 100644
index 39c4682766a8..000000000000
--- a/arch/mips/alchemy/pb1500/irqmap.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30
31#include <asm/mach-au1x00/au1000.h>
32
33char irq_tab_alchemy[][5] __initdata = {
34 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
35 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
36};
37
38struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
39 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 },
40 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
41 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
42 { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 },
43 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
44};
45
46int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/pb1550/init.c b/arch/mips/alchemy/pb1550/init.c
deleted file mode 100644
index e1055a13a1a0..000000000000
--- a/arch/mips/alchemy/pb1550/init.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Pb1550 board setup
5 *
6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1550";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = (int)fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x08000000;
55 else
56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
diff --git a/arch/mips/alchemy/pb1550/irqmap.c b/arch/mips/alchemy/pb1550/irqmap.c
deleted file mode 100644
index a02a4d1fa899..000000000000
--- a/arch/mips/alchemy/pb1550/irqmap.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 IRQ map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30
31#include <asm/mach-au1x00/au1000.h>
32
33char irq_tab_alchemy[][5] __initdata = {
34 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
35 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
36};
37
38struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
39 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
40 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
41};
42
43int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 4c587acac5c3..a2634fabc50d 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -28,6 +28,8 @@
28 28
29#include <asm/mach-au1x00/au1000.h> 29#include <asm/mach-au1x00/au1000.h>
30 30
31#include <prom.h>
32
31void board_reset(void) 33void board_reset(void)
32{ 34{
33 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 35 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
@@ -38,6 +40,16 @@ void __init board_setup(void)
38{ 40{
39 u32 pin_func; 41 u32 pin_func;
40 42
43#ifdef CONFIG_SERIAL_8250_CONSOLE
44 char *argptr;
45 argptr = prom_getcmdline();
46 argptr = strstr(argptr, "console=");
47 if (argptr == NULL) {
48 argptr = prom_getcmdline();
49 strcat(argptr, " console=ttyS0,115200");
50 }
51#endif
52
41 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ 53 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
42 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; 54 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
43 pin_func |= SYS_PF_UR3; 55 pin_func |= SYS_PF_UR3;
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 7516434760a1..456fa142c093 100644
--- a/arch/mips/alchemy/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
53 if (!memsize_str) 53 if (!memsize_str)
54 memsize = 0x04000000; 54 memsize = 0x04000000;
55 else 55 else
56 strict_strtol(memsize_str, 0, &memsize); 56 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 58}
diff --git a/arch/mips/alchemy/xxs1500/irqmap.c b/arch/mips/alchemy/xxs1500/irqmap.c
index edf06ed11870..0f0f3012e5fd 100644
--- a/arch/mips/alchemy/xxs1500/irqmap.c
+++ b/arch/mips/alchemy/xxs1500/irqmap.c
@@ -27,23 +27,26 @@
27 */ 27 */
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30 30#include <linux/interrupt.h>
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32 32
33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
34 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, 34 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
35 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 35 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
36 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, 36 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
37 { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, 37 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
38 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, 38 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
39 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, 39 { AU1500_GPIO_207, IRQF_TRIGGER_LOW, 0 },
40 40
41 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, 41 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
42 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, 42 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
43 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, 43 { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 },
44 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, 44 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 },
45 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ 45 { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* CF interrupt */
46 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, 46 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 },
47}; 47};
48 48
49int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 49void __init board_init_irq(void)
50{
51 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
52}
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
new file mode 100644
index 000000000000..094c17e38e16
--- /dev/null
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -0,0 +1,85 @@
1config CAVIUM_OCTEON_SPECIFIC_OPTIONS
2 bool "Enable Octeon specific options"
3 depends on CPU_CAVIUM_OCTEON
4 default "y"
5
6config CAVIUM_OCTEON_2ND_KERNEL
7 bool "Build the kernel to be used as a 2nd kernel on the same chip"
8 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
9 default "n"
10 help
11 This option configures this kernel to be linked at a different
12 address and use the 2nd uart for output. This allows a kernel built
13 with this option to be run at the same time as one built without this
14 option.
15
16config CAVIUM_OCTEON_HW_FIX_UNALIGNED
17 bool "Enable hardware fixups of unaligned loads and stores"
18 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
19 default "y"
20 help
21 Configure the Octeon hardware to automatically fix unaligned loads
22 and stores. Normally unaligned accesses are fixed using a kernel
23 exception handler. This option enables the hardware automatic fixups,
24 which requires only an extra 3 cycles. Disable this option if you
25 are running code that relies on address exceptions on unaligned
26 accesses.
27
28config CAVIUM_OCTEON_CVMSEG_SIZE
29 int "Number of L1 cache lines reserved for CVMSEG memory"
30 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
31 range 0 54
32 default 1
33 help
34 CVMSEG LM is a segment that accesses portions of the dcache as a
35 local memory; the larger CVMSEG is, the smaller the cache is.
36 This selects the size of CVMSEG LM, which is in cache blocks. The
37 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
38 between zero and 6192 bytes).
39
40config CAVIUM_OCTEON_LOCK_L2
41 bool "Lock often used kernel code in the L2"
42 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
43 default "y"
44 help
45 Enable locking parts of the kernel into the L2 cache.
46
47config CAVIUM_OCTEON_LOCK_L2_TLB
48 bool "Lock the TLB handler in L2"
49 depends on CAVIUM_OCTEON_LOCK_L2
50 default "y"
51 help
52 Lock the low level TLB fast path into L2.
53
54config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
55 bool "Lock the exception handler in L2"
56 depends on CAVIUM_OCTEON_LOCK_L2
57 default "y"
58 help
59 Lock the low level exception handler into L2.
60
61config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
62 bool "Lock the interrupt handler in L2"
63 depends on CAVIUM_OCTEON_LOCK_L2
64 default "y"
65 help
66 Lock the low level interrupt handler into L2.
67
68config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
69 bool "Lock the 2nd level interrupt handler in L2"
70 depends on CAVIUM_OCTEON_LOCK_L2
71 default "y"
72 help
73 Lock the 2nd level interrupt handler in L2.
74
75config CAVIUM_OCTEON_LOCK_L2_MEMCPY
76 bool "Lock memcpy() in L2"
77 depends on CAVIUM_OCTEON_LOCK_L2
78 default "y"
79 help
80 Lock the kernel's implementation of memcpy() into L2.
81
82config ARCH_SPARSEMEM_ENABLE
83 def_bool y
84 select SPARSEMEM_STATIC
85 depends on CPU_CAVIUM_OCTEON
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
new file mode 100644
index 000000000000..1c2a7faf5881
--- /dev/null
+++ b/arch/mips/cavium-octeon/Makefile
@@ -0,0 +1,16 @@
1#
2# Makefile for the Cavium Octeon specific kernel interface routines
3# under Linux.
4#
5# This file is subject to the terms and conditions of the GNU General Public
6# License. See the file "COPYING" in the main directory of this archive
7# for more details.
8#
9# Copyright (C) 2005-2008 Cavium Networks
10#
11
12obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o
15
16obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
new file mode 100644
index 000000000000..70fd92c31657
--- /dev/null
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -0,0 +1,58 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8#include <linux/clocksource.h>
9#include <linux/init.h>
10
11#include <asm/time.h>
12
13#include <asm/octeon/octeon.h>
14#include <asm/octeon/cvmx-ipd-defs.h>
15
16/*
17 * Set the current core's cvmcount counter to the value of the
18 * IPD_CLK_COUNT. We do this on all cores as they are brought
19 * on-line. This allows for a read from a local cpu register to
20 * access a synchronized counter.
21 *
22 */
23void octeon_init_cvmcount(void)
24{
25 unsigned long flags;
26 unsigned loops = 2;
27
28 /* Clobber loops so GCC will not unroll the following while loop. */
29 asm("" : "+r" (loops));
30
31 local_irq_save(flags);
32 /*
33 * Loop several times so we are executing from the cache,
34 * which should give more deterministic timing.
35 */
36 while (loops--)
37 write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
38 local_irq_restore(flags);
39}
40
41static cycle_t octeon_cvmcount_read(void)
42{
43 return read_c0_cvmcount();
44}
45
46static struct clocksource clocksource_mips = {
47 .name = "OCTEON_CVMCOUNT",
48 .read = octeon_cvmcount_read,
49 .mask = CLOCKSOURCE_MASK(64),
50 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
51};
52
53void __init plat_time_init(void)
54{
55 clocksource_mips.rating = 300;
56 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
57 clocksource_register(&clocksource_mips);
58}
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
new file mode 100644
index 000000000000..01b1ef94b361
--- /dev/null
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -0,0 +1,32 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
7 * Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
8 * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
9 * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
10 * IP32 changes by Ilya.
11 * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
12 * the kernels original.
13 */
14#include <linux/types.h>
15#include <linux/mm.h>
16
17#include <dma-coherence.h>
18
19dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
20{
21 /* Without PCI/PCIe this function can be called for Octeon internal
22 devices such as USB. These devices all support 64bit addressing */
23 mb();
24 return virt_to_phys(ptr);
25}
26
27void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
28{
29 /* Without PCI/PCIe this function can be called for Octeon internal
30 * devices such as USB. These devices all support 64bit addressing */
31 return;
32}
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
new file mode 100644
index 000000000000..80d6cb26766b
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for the Cavium Octeon specific kernel interface routines
3# under Linux.
4#
5# This file is subject to the terms and conditions of the GNU General Public
6# License. See the file "COPYING" in the main directory of this archive
7# for more details.
8#
9# Copyright (C) 2005-2008 Cavium Networks
10#
11
12obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
13
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
new file mode 100644
index 000000000000..4f5a08b37ccd
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -0,0 +1,586 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Simple allocate only memory allocator. Used to allocate memory at
30 * application start time.
31 */
32
33#include <linux/kernel.h>
34
35#include <asm/octeon/cvmx.h>
36#include <asm/octeon/cvmx-spinlock.h>
37#include <asm/octeon/cvmx-bootmem.h>
38
39/*#define DEBUG */
40
41
42static struct cvmx_bootmem_desc *cvmx_bootmem_desc;
43
44/* See header file for descriptions of functions */
45
46/*
47 * Wrapper functions are provided for reading/writing the size and
48 * next block values as these may not be directly addressible (in 32
49 * bit applications, for instance.) Offsets of data elements in
50 * bootmem list, must match cvmx_bootmem_block_header_t.
51 */
52#define NEXT_OFFSET 0
53#define SIZE_OFFSET 8
54
55static void cvmx_bootmem_phy_set_size(uint64_t addr, uint64_t size)
56{
57 cvmx_write64_uint64((addr + SIZE_OFFSET) | (1ull << 63), size);
58}
59
60static void cvmx_bootmem_phy_set_next(uint64_t addr, uint64_t next)
61{
62 cvmx_write64_uint64((addr + NEXT_OFFSET) | (1ull << 63), next);
63}
64
65static uint64_t cvmx_bootmem_phy_get_size(uint64_t addr)
66{
67 return cvmx_read64_uint64((addr + SIZE_OFFSET) | (1ull << 63));
68}
69
70static uint64_t cvmx_bootmem_phy_get_next(uint64_t addr)
71{
72 return cvmx_read64_uint64((addr + NEXT_OFFSET) | (1ull << 63));
73}
74
75void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
76 uint64_t min_addr, uint64_t max_addr)
77{
78 int64_t address;
79 address =
80 cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, 0);
81
82 if (address > 0)
83 return cvmx_phys_to_ptr(address);
84 else
85 return NULL;
86}
87
88void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
89 uint64_t alignment)
90{
91 return cvmx_bootmem_alloc_range(size, alignment, address,
92 address + size);
93}
94
95void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
96{
97 return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
98}
99
100int cvmx_bootmem_free_named(char *name)
101{
102 return cvmx_bootmem_phy_named_block_free(name, 0);
103}
104
105struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name)
106{
107 return cvmx_bootmem_phy_named_block_find(name, 0);
108}
109
110void cvmx_bootmem_lock(void)
111{
112 cvmx_spinlock_lock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
113}
114
115void cvmx_bootmem_unlock(void)
116{
117 cvmx_spinlock_unlock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
118}
119
120int cvmx_bootmem_init(void *mem_desc_ptr)
121{
122 /* Here we set the global pointer to the bootmem descriptor
123 * block. This pointer will be used directly, so we will set
124 * it up to be directly usable by the application. It is set
125 * up as follows for the various runtime/ABI combinations:
126 *
127 * Linux 64 bit: Set XKPHYS bit
128 * Linux 32 bit: use mmap to create mapping, use virtual address
129 * CVMX 64 bit: use physical address directly
130 * CVMX 32 bit: use physical address directly
131 *
132 * Note that the CVMX environment assumes the use of 1-1 TLB
133 * mappings so that the physical addresses can be used
134 * directly
135 */
136 if (!cvmx_bootmem_desc) {
137#if defined(CVMX_ABI_64)
138 /* Set XKPHYS bit */
139 cvmx_bootmem_desc = cvmx_phys_to_ptr(CAST64(mem_desc_ptr));
140#else
141 cvmx_bootmem_desc = (struct cvmx_bootmem_desc *) mem_desc_ptr;
142#endif
143 }
144
145 return 0;
146}
147
148/*
149 * The cvmx_bootmem_phy* functions below return 64 bit physical
150 * addresses, and expose more features that the cvmx_bootmem_functions
151 * above. These are required for full memory space access in 32 bit
152 * applications, as well as for using some advance features. Most
153 * applications should not need to use these.
154 */
155
156int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
157 uint64_t address_max, uint64_t alignment,
158 uint32_t flags)
159{
160
161 uint64_t head_addr;
162 uint64_t ent_addr;
163 /* points to previous list entry, NULL current entry is head of list */
164 uint64_t prev_addr = 0;
165 uint64_t new_ent_addr = 0;
166 uint64_t desired_min_addr;
167
168#ifdef DEBUG
169 cvmx_dprintf("cvmx_bootmem_phy_alloc: req_size: 0x%llx, "
170 "min_addr: 0x%llx, max_addr: 0x%llx, align: 0x%llx\n",
171 (unsigned long long)req_size,
172 (unsigned long long)address_min,
173 (unsigned long long)address_max,
174 (unsigned long long)alignment);
175#endif
176
177 if (cvmx_bootmem_desc->major_version > 3) {
178 cvmx_dprintf("ERROR: Incompatible bootmem descriptor "
179 "version: %d.%d at addr: %p\n",
180 (int)cvmx_bootmem_desc->major_version,
181 (int)cvmx_bootmem_desc->minor_version,
182 cvmx_bootmem_desc);
183 goto error_out;
184 }
185
186 /*
187 * Do a variety of checks to validate the arguments. The
188 * allocator code will later assume that these checks have
189 * been made. We validate that the requested constraints are
190 * not self-contradictory before we look through the list of
191 * available memory.
192 */
193
194 /* 0 is not a valid req_size for this allocator */
195 if (!req_size)
196 goto error_out;
197
198 /* Round req_size up to mult of minimum alignment bytes */
199 req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) &
200 ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
201
202 /*
203 * Convert !0 address_min and 0 address_max to special case of
204 * range that specifies an exact memory block to allocate. Do
205 * this before other checks and adjustments so that this
206 * tranformation will be validated.
207 */
208 if (address_min && !address_max)
209 address_max = address_min + req_size;
210 else if (!address_min && !address_max)
211 address_max = ~0ull; /* If no limits given, use max limits */
212
213
214 /*
215 * Enforce minimum alignment (this also keeps the minimum free block
216 * req_size the same as the alignment req_size.
217 */
218 if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE)
219 alignment = CVMX_BOOTMEM_ALIGNMENT_SIZE;
220
221 /*
222 * Adjust address minimum based on requested alignment (round
223 * up to meet alignment). Do this here so we can reject
224 * impossible requests up front. (NOP for address_min == 0)
225 */
226 if (alignment)
227 address_min = __ALIGN_MASK(address_min, (alignment - 1));
228
229 /*
230 * Reject inconsistent args. We have adjusted these, so this
231 * may fail due to our internal changes even if this check
232 * would pass for the values the user supplied.
233 */
234 if (req_size > address_max - address_min)
235 goto error_out;
236
237 /* Walk through the list entries - first fit found is returned */
238
239 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
240 cvmx_bootmem_lock();
241 head_addr = cvmx_bootmem_desc->head_addr;
242 ent_addr = head_addr;
243 for (; ent_addr;
244 prev_addr = ent_addr,
245 ent_addr = cvmx_bootmem_phy_get_next(ent_addr)) {
246 uint64_t usable_base, usable_max;
247 uint64_t ent_size = cvmx_bootmem_phy_get_size(ent_addr);
248
249 if (cvmx_bootmem_phy_get_next(ent_addr)
250 && ent_addr > cvmx_bootmem_phy_get_next(ent_addr)) {
251 cvmx_dprintf("Internal bootmem_alloc() error: ent: "
252 "0x%llx, next: 0x%llx\n",
253 (unsigned long long)ent_addr,
254 (unsigned long long)
255 cvmx_bootmem_phy_get_next(ent_addr));
256 goto error_out;
257 }
258
259 /*
260 * Determine if this is an entry that can satisify the
261 * request Check to make sure entry is large enough to
262 * satisfy request.
263 */
264 usable_base =
265 __ALIGN_MASK(max(address_min, ent_addr), alignment - 1);
266 usable_max = min(address_max, ent_addr + ent_size);
267 /*
268 * We should be able to allocate block at address
269 * usable_base.
270 */
271
272 desired_min_addr = usable_base;
273 /*
274 * Determine if request can be satisfied from the
275 * current entry.
276 */
277 if (!((ent_addr + ent_size) > usable_base
278 && ent_addr < address_max
279 && req_size <= usable_max - usable_base))
280 continue;
281 /*
282 * We have found an entry that has room to satisfy the
283 * request, so allocate it from this entry. If end
284 * CVMX_BOOTMEM_FLAG_END_ALLOC set, then allocate from
285 * the end of this block rather than the beginning.
286 */
287 if (flags & CVMX_BOOTMEM_FLAG_END_ALLOC) {
288 desired_min_addr = usable_max - req_size;
289 /*
290 * Align desired address down to required
291 * alignment.
292 */
293 desired_min_addr &= ~(alignment - 1);
294 }
295
296 /* Match at start of entry */
297 if (desired_min_addr == ent_addr) {
298 if (req_size < ent_size) {
299 /*
300 * big enough to create a new block
301 * from top portion of block.
302 */
303 new_ent_addr = ent_addr + req_size;
304 cvmx_bootmem_phy_set_next(new_ent_addr,
305 cvmx_bootmem_phy_get_next(ent_addr));
306 cvmx_bootmem_phy_set_size(new_ent_addr,
307 ent_size -
308 req_size);
309
310 /*
311 * Adjust next pointer as following
312 * code uses this.
313 */
314 cvmx_bootmem_phy_set_next(ent_addr,
315 new_ent_addr);
316 }
317
318 /*
319 * adjust prev ptr or head to remove this
320 * entry from list.
321 */
322 if (prev_addr)
323 cvmx_bootmem_phy_set_next(prev_addr,
324 cvmx_bootmem_phy_get_next(ent_addr));
325 else
326 /*
327 * head of list being returned, so
328 * update head ptr.
329 */
330 cvmx_bootmem_desc->head_addr =
331 cvmx_bootmem_phy_get_next(ent_addr);
332
333 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
334 cvmx_bootmem_unlock();
335 return desired_min_addr;
336 }
337 /*
338 * block returned doesn't start at beginning of entry,
339 * so we know that we will be splitting a block off
340 * the front of this one. Create a new block from the
341 * beginning, add to list, and go to top of loop
342 * again.
343 *
344 * create new block from high portion of
345 * block, so that top block starts at desired
346 * addr.
347 */
348 new_ent_addr = desired_min_addr;
349 cvmx_bootmem_phy_set_next(new_ent_addr,
350 cvmx_bootmem_phy_get_next
351 (ent_addr));
352 cvmx_bootmem_phy_set_size(new_ent_addr,
353 cvmx_bootmem_phy_get_size
354 (ent_addr) -
355 (desired_min_addr -
356 ent_addr));
357 cvmx_bootmem_phy_set_size(ent_addr,
358 desired_min_addr - ent_addr);
359 cvmx_bootmem_phy_set_next(ent_addr, new_ent_addr);
360 /* Loop again to handle actual alloc from new block */
361 }
362error_out:
363 /* We didn't find anything, so return error */
364 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
365 cvmx_bootmem_unlock();
366 return -1;
367}
368
369int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
370{
371 uint64_t cur_addr;
372 uint64_t prev_addr = 0; /* zero is invalid */
373 int retval = 0;
374
375#ifdef DEBUG
376 cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n",
377 (unsigned long long)phy_addr, (unsigned long long)size);
378#endif
379 if (cvmx_bootmem_desc->major_version > 3) {
380 cvmx_dprintf("ERROR: Incompatible bootmem descriptor "
381 "version: %d.%d at addr: %p\n",
382 (int)cvmx_bootmem_desc->major_version,
383 (int)cvmx_bootmem_desc->minor_version,
384 cvmx_bootmem_desc);
385 return 0;
386 }
387
388 /* 0 is not a valid size for this allocator */
389 if (!size)
390 return 0;
391
392 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
393 cvmx_bootmem_lock();
394 cur_addr = cvmx_bootmem_desc->head_addr;
395 if (cur_addr == 0 || phy_addr < cur_addr) {
396 /* add at front of list - special case with changing head ptr */
397 if (cur_addr && phy_addr + size > cur_addr)
398 goto bootmem_free_done; /* error, overlapping section */
399 else if (phy_addr + size == cur_addr) {
400 /* Add to front of existing first block */
401 cvmx_bootmem_phy_set_next(phy_addr,
402 cvmx_bootmem_phy_get_next
403 (cur_addr));
404 cvmx_bootmem_phy_set_size(phy_addr,
405 cvmx_bootmem_phy_get_size
406 (cur_addr) + size);
407 cvmx_bootmem_desc->head_addr = phy_addr;
408
409 } else {
410 /* New block before first block. OK if cur_addr is 0 */
411 cvmx_bootmem_phy_set_next(phy_addr, cur_addr);
412 cvmx_bootmem_phy_set_size(phy_addr, size);
413 cvmx_bootmem_desc->head_addr = phy_addr;
414 }
415 retval = 1;
416 goto bootmem_free_done;
417 }
418
419 /* Find place in list to add block */
420 while (cur_addr && phy_addr > cur_addr) {
421 prev_addr = cur_addr;
422 cur_addr = cvmx_bootmem_phy_get_next(cur_addr);
423 }
424
425 if (!cur_addr) {
426 /*
427 * We have reached the end of the list, add on to end,
428 * checking to see if we need to combine with last
429 * block
430 */
431 if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) ==
432 phy_addr) {
433 cvmx_bootmem_phy_set_size(prev_addr,
434 cvmx_bootmem_phy_get_size
435 (prev_addr) + size);
436 } else {
437 cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
438 cvmx_bootmem_phy_set_size(phy_addr, size);
439 cvmx_bootmem_phy_set_next(phy_addr, 0);
440 }
441 retval = 1;
442 goto bootmem_free_done;
443 } else {
444 /*
445 * insert between prev and cur nodes, checking for
446 * merge with either/both.
447 */
448 if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) ==
449 phy_addr) {
450 /* Merge with previous */
451 cvmx_bootmem_phy_set_size(prev_addr,
452 cvmx_bootmem_phy_get_size
453 (prev_addr) + size);
454 if (phy_addr + size == cur_addr) {
455 /* Also merge with current */
456 cvmx_bootmem_phy_set_size(prev_addr,
457 cvmx_bootmem_phy_get_size(cur_addr) +
458 cvmx_bootmem_phy_get_size(prev_addr));
459 cvmx_bootmem_phy_set_next(prev_addr,
460 cvmx_bootmem_phy_get_next(cur_addr));
461 }
462 retval = 1;
463 goto bootmem_free_done;
464 } else if (phy_addr + size == cur_addr) {
465 /* Merge with current */
466 cvmx_bootmem_phy_set_size(phy_addr,
467 cvmx_bootmem_phy_get_size
468 (cur_addr) + size);
469 cvmx_bootmem_phy_set_next(phy_addr,
470 cvmx_bootmem_phy_get_next
471 (cur_addr));
472 cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
473 retval = 1;
474 goto bootmem_free_done;
475 }
476
477 /* It is a standalone block, add in between prev and cur */
478 cvmx_bootmem_phy_set_size(phy_addr, size);
479 cvmx_bootmem_phy_set_next(phy_addr, cur_addr);
480 cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
481
482 }
483 retval = 1;
484
485bootmem_free_done:
486 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
487 cvmx_bootmem_unlock();
488 return retval;
489
490}
491
492struct cvmx_bootmem_named_block_desc *
493 cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags)
494{
495 unsigned int i;
496 struct cvmx_bootmem_named_block_desc *named_block_array_ptr;
497
498#ifdef DEBUG
499 cvmx_dprintf("cvmx_bootmem_phy_named_block_find: %s\n", name);
500#endif
501 /*
502 * Lock the structure to make sure that it is not being
503 * changed while we are examining it.
504 */
505 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
506 cvmx_bootmem_lock();
507
508 /* Use XKPHYS for 64 bit linux */
509 named_block_array_ptr = (struct cvmx_bootmem_named_block_desc *)
510 cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
511
512#ifdef DEBUG
513 cvmx_dprintf
514 ("cvmx_bootmem_phy_named_block_find: named_block_array_ptr: %p\n",
515 named_block_array_ptr);
516#endif
517 if (cvmx_bootmem_desc->major_version == 3) {
518 for (i = 0;
519 i < cvmx_bootmem_desc->named_block_num_blocks; i++) {
520 if ((name && named_block_array_ptr[i].size
521 && !strncmp(name, named_block_array_ptr[i].name,
522 cvmx_bootmem_desc->named_block_name_len
523 - 1))
524 || (!name && !named_block_array_ptr[i].size)) {
525 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
526 cvmx_bootmem_unlock();
527
528 return &(named_block_array_ptr[i]);
529 }
530 }
531 } else {
532 cvmx_dprintf("ERROR: Incompatible bootmem descriptor "
533 "version: %d.%d at addr: %p\n",
534 (int)cvmx_bootmem_desc->major_version,
535 (int)cvmx_bootmem_desc->minor_version,
536 cvmx_bootmem_desc);
537 }
538 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
539 cvmx_bootmem_unlock();
540
541 return NULL;
542}
543
544int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
545{
546 struct cvmx_bootmem_named_block_desc *named_block_ptr;
547
548 if (cvmx_bootmem_desc->major_version != 3) {
549 cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: "
550 "%d.%d at addr: %p\n",
551 (int)cvmx_bootmem_desc->major_version,
552 (int)cvmx_bootmem_desc->minor_version,
553 cvmx_bootmem_desc);
554 return 0;
555 }
556#ifdef DEBUG
557 cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s\n", name);
558#endif
559
560 /*
561 * Take lock here, as name lookup/block free/name free need to
562 * be atomic.
563 */
564 cvmx_bootmem_lock();
565
566 named_block_ptr =
567 cvmx_bootmem_phy_named_block_find(name,
568 CVMX_BOOTMEM_FLAG_NO_LOCKING);
569 if (named_block_ptr) {
570#ifdef DEBUG
571 cvmx_dprintf("cvmx_bootmem_phy_named_block_free: "
572 "%s, base: 0x%llx, size: 0x%llx\n",
573 name,
574 (unsigned long long)named_block_ptr->base_addr,
575 (unsigned long long)named_block_ptr->size);
576#endif
577 __cvmx_bootmem_phy_free(named_block_ptr->base_addr,
578 named_block_ptr->size,
579 CVMX_BOOTMEM_FLAG_NO_LOCKING);
580 named_block_ptr->size = 0;
581 /* Set size to zero to indicate block not used. */
582 }
583
584 cvmx_bootmem_unlock();
585 return named_block_ptr != NULL; /* 0 on failure, 1 on success */
586}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
new file mode 100644
index 000000000000..6abe56f1e097
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -0,0 +1,734 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Implementation of the Level 2 Cache (L2C) control, measurement, and
30 * debugging facilities.
31 */
32
33#include <asm/octeon/cvmx.h>
34#include <asm/octeon/cvmx-l2c.h>
35#include <asm/octeon/cvmx-spinlock.h>
36
37/*
38 * This spinlock is used internally to ensure that only one core is
39 * performing certain L2 operations at a time.
40 *
41 * NOTE: This only protects calls from within a single application -
42 * if multiple applications or operating systems are running, then it
43 * is up to the user program to coordinate between them.
44 */
45static cvmx_spinlock_t cvmx_l2c_spinlock;
46
47static inline int l2_size_half(void)
48{
49 uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
50 return !!(val & (1ull << 34));
51}
52
53int cvmx_l2c_get_core_way_partition(uint32_t core)
54{
55 uint32_t field;
56
57 /* Validate the core number */
58 if (core >= cvmx_octeon_num_cores())
59 return -1;
60
61 /*
62 * Use the lower two bits of the coreNumber to determine the
63 * bit offset of the UMSK[] field in the L2C_SPAR register.
64 */
65 field = (core & 0x3) * 8;
66
67 /*
68 * Return the UMSK[] field from the appropriate L2C_SPAR
69 * register based on the coreNumber.
70 */
71
72 switch (core & 0xC) {
73 case 0x0:
74 return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >>
75 field;
76 case 0x4:
77 return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >>
78 field;
79 case 0x8:
80 return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >>
81 field;
82 case 0xC:
83 return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >>
84 field;
85 }
86 return 0;
87}
88
89int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
90{
91 uint32_t field;
92 uint32_t valid_mask;
93
94 valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
95
96 mask &= valid_mask;
97
98 /* A UMSK setting which blocks all L2C Ways is an error. */
99 if (mask == valid_mask)
100 return -1;
101
102 /* Validate the core number */
103 if (core >= cvmx_octeon_num_cores())
104 return -1;
105
106 /* Check to make sure current mask & new mask don't block all ways */
107 if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) ==
108 valid_mask)
109 return -1;
110
111 /* Use the lower two bits of core to determine the bit offset of the
112 * UMSK[] field in the L2C_SPAR register.
113 */
114 field = (core & 0x3) * 8;
115
116 /* Assign the new mask setting to the UMSK[] field in the appropriate
117 * L2C_SPAR register based on the core_num.
118 *
119 */
120 switch (core & 0xC) {
121 case 0x0:
122 cvmx_write_csr(CVMX_L2C_SPAR0,
123 (cvmx_read_csr(CVMX_L2C_SPAR0) &
124 ~(0xFF << field)) | mask << field);
125 break;
126 case 0x4:
127 cvmx_write_csr(CVMX_L2C_SPAR1,
128 (cvmx_read_csr(CVMX_L2C_SPAR1) &
129 ~(0xFF << field)) | mask << field);
130 break;
131 case 0x8:
132 cvmx_write_csr(CVMX_L2C_SPAR2,
133 (cvmx_read_csr(CVMX_L2C_SPAR2) &
134 ~(0xFF << field)) | mask << field);
135 break;
136 case 0xC:
137 cvmx_write_csr(CVMX_L2C_SPAR3,
138 (cvmx_read_csr(CVMX_L2C_SPAR3) &
139 ~(0xFF << field)) | mask << field);
140 break;
141 }
142 return 0;
143}
144
145int cvmx_l2c_set_hw_way_partition(uint32_t mask)
146{
147 uint32_t valid_mask;
148
149 valid_mask = 0xff;
150
151 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) {
152 if (l2_size_half())
153 valid_mask = 0xf;
154 } else if (l2_size_half())
155 valid_mask = 0x3;
156
157 mask &= valid_mask;
158
159 /* A UMSK setting which blocks all L2C Ways is an error. */
160 if (mask == valid_mask)
161 return -1;
162 /* Check to make sure current mask & new mask don't block all ways */
163 if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) ==
164 valid_mask)
165 return -1;
166
167 cvmx_write_csr(CVMX_L2C_SPAR4,
168 (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
169 return 0;
170}
171
172int cvmx_l2c_get_hw_way_partition(void)
173{
174 return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
175}
176
177void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
178 uint32_t clear_on_read)
179{
180 union cvmx_l2c_pfctl pfctl;
181
182 pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
183
184 switch (counter) {
185 case 0:
186 pfctl.s.cnt0sel = event;
187 pfctl.s.cnt0ena = 1;
188 if (!cvmx_octeon_is_pass1())
189 pfctl.s.cnt0rdclr = clear_on_read;
190 break;
191 case 1:
192 pfctl.s.cnt1sel = event;
193 pfctl.s.cnt1ena = 1;
194 if (!cvmx_octeon_is_pass1())
195 pfctl.s.cnt1rdclr = clear_on_read;
196 break;
197 case 2:
198 pfctl.s.cnt2sel = event;
199 pfctl.s.cnt2ena = 1;
200 if (!cvmx_octeon_is_pass1())
201 pfctl.s.cnt2rdclr = clear_on_read;
202 break;
203 case 3:
204 default:
205 pfctl.s.cnt3sel = event;
206 pfctl.s.cnt3ena = 1;
207 if (!cvmx_octeon_is_pass1())
208 pfctl.s.cnt3rdclr = clear_on_read;
209 break;
210 }
211
212 cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
213}
214
215uint64_t cvmx_l2c_read_perf(uint32_t counter)
216{
217 switch (counter) {
218 case 0:
219 return cvmx_read_csr(CVMX_L2C_PFC0);
220 case 1:
221 return cvmx_read_csr(CVMX_L2C_PFC1);
222 case 2:
223 return cvmx_read_csr(CVMX_L2C_PFC2);
224 case 3:
225 default:
226 return cvmx_read_csr(CVMX_L2C_PFC3);
227 }
228}
229
230/**
231 * @INTERNAL
232 * Helper function use to fault in cache lines for L2 cache locking
233 *
234 * @addr: Address of base of memory region to read into L2 cache
235 * @len: Length (in bytes) of region to fault in
236 */
237static void fault_in(uint64_t addr, int len)
238{
239 volatile char *ptr;
240 volatile char dummy;
241 /*
242 * Adjust addr and length so we get all cache lines even for
243 * small ranges spanning two cache lines
244 */
245 len += addr & CVMX_CACHE_LINE_MASK;
246 addr &= ~CVMX_CACHE_LINE_MASK;
247 ptr = (volatile char *)cvmx_phys_to_ptr(addr);
248 /*
249 * Invalidate L1 cache to make sure all loads result in data
250 * being in L2.
251 */
252 CVMX_DCACHE_INVALIDATE;
253 while (len > 0) {
254 dummy += *ptr;
255 len -= CVMX_CACHE_LINE_SIZE;
256 ptr += CVMX_CACHE_LINE_SIZE;
257 }
258}
259
260int cvmx_l2c_lock_line(uint64_t addr)
261{
262 int retval = 0;
263 union cvmx_l2c_dbg l2cdbg;
264 union cvmx_l2c_lckbase lckbase;
265 union cvmx_l2c_lckoff lckoff;
266 union cvmx_l2t_err l2t_err;
267 l2cdbg.u64 = 0;
268 lckbase.u64 = 0;
269 lckoff.u64 = 0;
270
271 cvmx_spinlock_lock(&cvmx_l2c_spinlock);
272
273 /* Clear l2t error bits if set */
274 l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
275 l2t_err.s.lckerr = 1;
276 l2t_err.s.lckerr2 = 1;
277 cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
278
279 addr &= ~CVMX_CACHE_LINE_MASK;
280
281 /* Set this core as debug core */
282 l2cdbg.s.ppnum = cvmx_get_core_num();
283 CVMX_SYNC;
284 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
285 cvmx_read_csr(CVMX_L2C_DBG);
286
287 lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
288 cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
289 cvmx_read_csr(CVMX_L2C_LCKOFF);
290
291 if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
292 int alias_shift =
293 CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
294 uint64_t addr_tmp =
295 addr ^ (addr & ((1 << alias_shift) - 1)) >>
296 CVMX_L2_SET_BITS;
297 lckbase.s.lck_base = addr_tmp >> 7;
298 } else {
299 lckbase.s.lck_base = addr >> 7;
300 }
301
302 lckbase.s.lck_ena = 1;
303 cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
304 cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
305
306 fault_in(addr, CVMX_CACHE_LINE_SIZE);
307
308 lckbase.s.lck_ena = 0;
309 cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
310 cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
311
312 /* Stop being debug core */
313 cvmx_write_csr(CVMX_L2C_DBG, 0);
314 cvmx_read_csr(CVMX_L2C_DBG);
315
316 l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
317 if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
318 retval = 1; /* We were unable to lock the line */
319
320 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
321
322 return retval;
323}
324
325int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
326{
327 int retval = 0;
328
329 /* Round start/end to cache line boundaries */
330 len += start & CVMX_CACHE_LINE_MASK;
331 start &= ~CVMX_CACHE_LINE_MASK;
332 len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
333
334 while (len) {
335 retval += cvmx_l2c_lock_line(start);
336 start += CVMX_CACHE_LINE_SIZE;
337 len -= CVMX_CACHE_LINE_SIZE;
338 }
339
340 return retval;
341}
342
343void cvmx_l2c_flush(void)
344{
345 uint64_t assoc, set;
346 uint64_t n_assoc, n_set;
347 union cvmx_l2c_dbg l2cdbg;
348
349 cvmx_spinlock_lock(&cvmx_l2c_spinlock);
350
351 l2cdbg.u64 = 0;
352 if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
353 l2cdbg.s.ppnum = cvmx_get_core_num();
354 l2cdbg.s.finv = 1;
355 n_set = CVMX_L2_SETS;
356 n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC;
357 for (set = 0; set < n_set; set++) {
358 for (assoc = 0; assoc < n_assoc; assoc++) {
359 l2cdbg.s.set = assoc;
360 /* Enter debug mode, and make sure all other
361 ** writes complete before we enter debug
362 ** mode */
363 CVMX_SYNCW;
364 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
365 cvmx_read_csr(CVMX_L2C_DBG);
366
367 CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
368 (CVMX_MIPS_SPACE_XKPHYS,
369 set * CVMX_CACHE_LINE_SIZE), 0);
370 CVMX_SYNCW; /* Push STF out to L2 */
371 /* Exit debug mode */
372 CVMX_SYNC;
373 cvmx_write_csr(CVMX_L2C_DBG, 0);
374 cvmx_read_csr(CVMX_L2C_DBG);
375 }
376 }
377
378 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
379}
380
381int cvmx_l2c_unlock_line(uint64_t address)
382{
383 int assoc;
384 union cvmx_l2c_tag tag;
385 union cvmx_l2c_dbg l2cdbg;
386 uint32_t tag_addr;
387
388 uint32_t index = cvmx_l2c_address_to_index(address);
389
390 cvmx_spinlock_lock(&cvmx_l2c_spinlock);
391 /* Compute portion of address that is stored in tag */
392 tag_addr =
393 ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) &
394 ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
395 for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
396 tag = cvmx_get_l2c_tag(assoc, index);
397
398 if (tag.s.V && (tag.s.addr == tag_addr)) {
399 l2cdbg.u64 = 0;
400 l2cdbg.s.ppnum = cvmx_get_core_num();
401 l2cdbg.s.set = assoc;
402 l2cdbg.s.finv = 1;
403
404 CVMX_SYNC;
405 /* Enter debug mode */
406 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
407 cvmx_read_csr(CVMX_L2C_DBG);
408
409 CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
410 (CVMX_MIPS_SPACE_XKPHYS,
411 address), 0);
412 CVMX_SYNC;
413 /* Exit debug mode */
414 cvmx_write_csr(CVMX_L2C_DBG, 0);
415 cvmx_read_csr(CVMX_L2C_DBG);
416 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
417 return tag.s.L;
418 }
419 }
420 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
421 return 0;
422}
423
424int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
425{
426 int num_unlocked = 0;
427 /* Round start/end to cache line boundaries */
428 len += start & CVMX_CACHE_LINE_MASK;
429 start &= ~CVMX_CACHE_LINE_MASK;
430 len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
431 while (len > 0) {
432 num_unlocked += cvmx_l2c_unlock_line(start);
433 start += CVMX_CACHE_LINE_SIZE;
434 len -= CVMX_CACHE_LINE_SIZE;
435 }
436
437 return num_unlocked;
438}
439
440/*
441 * Internal l2c tag types. These are converted to a generic structure
442 * that can be used on all chips.
443 */
444union __cvmx_l2c_tag {
445 uint64_t u64;
446 struct cvmx_l2c_tag_cn50xx {
447 uint64_t reserved:40;
448 uint64_t V:1; /* Line valid */
449 uint64_t D:1; /* Line dirty */
450 uint64_t L:1; /* Line locked */
451 uint64_t U:1; /* Use, LRU eviction */
452 uint64_t addr:20; /* Phys mem addr (33..14) */
453 } cn50xx;
454 struct cvmx_l2c_tag_cn30xx {
455 uint64_t reserved:41;
456 uint64_t V:1; /* Line valid */
457 uint64_t D:1; /* Line dirty */
458 uint64_t L:1; /* Line locked */
459 uint64_t U:1; /* Use, LRU eviction */
460 uint64_t addr:19; /* Phys mem addr (33..15) */
461 } cn30xx;
462 struct cvmx_l2c_tag_cn31xx {
463 uint64_t reserved:42;
464 uint64_t V:1; /* Line valid */
465 uint64_t D:1; /* Line dirty */
466 uint64_t L:1; /* Line locked */
467 uint64_t U:1; /* Use, LRU eviction */
468 uint64_t addr:18; /* Phys mem addr (33..16) */
469 } cn31xx;
470 struct cvmx_l2c_tag_cn38xx {
471 uint64_t reserved:43;
472 uint64_t V:1; /* Line valid */
473 uint64_t D:1; /* Line dirty */
474 uint64_t L:1; /* Line locked */
475 uint64_t U:1; /* Use, LRU eviction */
476 uint64_t addr:17; /* Phys mem addr (33..17) */
477 } cn38xx;
478 struct cvmx_l2c_tag_cn58xx {
479 uint64_t reserved:44;
480 uint64_t V:1; /* Line valid */
481 uint64_t D:1; /* Line dirty */
482 uint64_t L:1; /* Line locked */
483 uint64_t U:1; /* Use, LRU eviction */
484 uint64_t addr:16; /* Phys mem addr (33..18) */
485 } cn58xx;
486 struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
487 struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
488};
489
490/**
491 * @INTERNAL
492 * Function to read a L2C tag. This code make the current core
493 * the 'debug core' for the L2. This code must only be executed by
494 * 1 core at a time.
495 *
496 * @assoc: Association (way) of the tag to dump
497 * @index: Index of the cacheline
498 *
499 * Returns The Octeon model specific tag structure. This is
500 * translated by a wrapper function to a generic form that is
501 * easier for applications to use.
502 */
503static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
504{
505
506 uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
507 uint64_t core = cvmx_get_core_num();
508 union __cvmx_l2c_tag tag_val;
509 uint64_t dbg_addr = CVMX_L2C_DBG;
510 unsigned long flags;
511
512 union cvmx_l2c_dbg debug_val;
513 debug_val.u64 = 0;
514 /*
515 * For low core count parts, the core number is always small enough
516 * to stay in the correct field and not set any reserved bits.
517 */
518 debug_val.s.ppnum = core;
519 debug_val.s.l2t = 1;
520 debug_val.s.set = assoc;
521 /*
522 * Make sure core is quiet (no prefetches, etc.) before
523 * entering debug mode.
524 */
525 CVMX_SYNC;
526 /* Flush L1 to make sure debug load misses L1 */
527 CVMX_DCACHE_INVALIDATE;
528
529 local_irq_save(flags);
530
531 /*
532 * The following must be done in assembly as when in debug
533 * mode all data loads from L2 return special debug data, not
534 * normal memory contents. Also, interrupts must be
535 * disabled, since if an interrupt occurs while in debug mode
536 * the ISR will get debug data from all its memory reads
537 * instead of the contents of memory
538 */
539
540 asm volatile (".set push \n"
541 " .set mips64 \n"
542 " .set noreorder \n"
543 /* Enter debug mode, wait for store */
544 " sd %[dbg_val], 0(%[dbg_addr]) \n"
545 " ld $0, 0(%[dbg_addr]) \n"
546 /* Read L2C tag data */
547 " ld %[tag_val], 0(%[tag_addr]) \n"
548 /* Exit debug mode, wait for store */
549 " sd $0, 0(%[dbg_addr]) \n"
550 " ld $0, 0(%[dbg_addr]) \n"
551 /* Invalidate dcache to discard debug data */
552 " cache 9, 0($0) \n"
553 " .set pop" :
554 [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr),
555 [dbg_val] "r"(debug_val.u64),
556 [tag_addr] "r"(debug_tag_addr) : "memory");
557
558 local_irq_restore(flags);
559 return tag_val;
560
561}
562
563union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
564{
565 union __cvmx_l2c_tag tmp_tag;
566 union cvmx_l2c_tag tag;
567 tag.u64 = 0;
568
569 if ((int)association >= cvmx_l2c_get_num_assoc()) {
570 cvmx_dprintf
571 ("ERROR: cvmx_get_l2c_tag association out of range\n");
572 return tag;
573 }
574 if ((int)index >= cvmx_l2c_get_num_sets()) {
575 cvmx_dprintf("ERROR: cvmx_get_l2c_tag "
576 "index out of range (arg: %d, max: %d\n",
577 index, cvmx_l2c_get_num_sets());
578 return tag;
579 }
580 /* __read_l2_tag is intended for internal use only */
581 tmp_tag = __read_l2_tag(association, index);
582
583 /*
584 * Convert all tag structure types to generic version, as it
585 * can represent all models.
586 */
587 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
588 tag.s.V = tmp_tag.cn58xx.V;
589 tag.s.D = tmp_tag.cn58xx.D;
590 tag.s.L = tmp_tag.cn58xx.L;
591 tag.s.U = tmp_tag.cn58xx.U;
592 tag.s.addr = tmp_tag.cn58xx.addr;
593 } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
594 tag.s.V = tmp_tag.cn38xx.V;
595 tag.s.D = tmp_tag.cn38xx.D;
596 tag.s.L = tmp_tag.cn38xx.L;
597 tag.s.U = tmp_tag.cn38xx.U;
598 tag.s.addr = tmp_tag.cn38xx.addr;
599 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
600 || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
601 tag.s.V = tmp_tag.cn31xx.V;
602 tag.s.D = tmp_tag.cn31xx.D;
603 tag.s.L = tmp_tag.cn31xx.L;
604 tag.s.U = tmp_tag.cn31xx.U;
605 tag.s.addr = tmp_tag.cn31xx.addr;
606 } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
607 tag.s.V = tmp_tag.cn30xx.V;
608 tag.s.D = tmp_tag.cn30xx.D;
609 tag.s.L = tmp_tag.cn30xx.L;
610 tag.s.U = tmp_tag.cn30xx.U;
611 tag.s.addr = tmp_tag.cn30xx.addr;
612 } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
613 tag.s.V = tmp_tag.cn50xx.V;
614 tag.s.D = tmp_tag.cn50xx.D;
615 tag.s.L = tmp_tag.cn50xx.L;
616 tag.s.U = tmp_tag.cn50xx.U;
617 tag.s.addr = tmp_tag.cn50xx.addr;
618 } else {
619 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
620 }
621
622 return tag;
623}
624
625uint32_t cvmx_l2c_address_to_index(uint64_t addr)
626{
627 uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
628 union cvmx_l2c_cfg l2c_cfg;
629 l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
630
631 if (l2c_cfg.s.idxalias) {
632 idx ^=
633 ((addr & CVMX_L2C_ALIAS_MASK) >>
634 CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
635 }
636 idx &= CVMX_L2C_IDX_MASK;
637 return idx;
638}
639
640int cvmx_l2c_get_cache_size_bytes(void)
641{
642 return cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() *
643 CVMX_CACHE_LINE_SIZE;
644}
645
646/**
647 * Return log base 2 of the number of sets in the L2 cache
648 * Returns
649 */
650int cvmx_l2c_get_set_bits(void)
651{
652 int l2_set_bits;
653 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
654 l2_set_bits = 11; /* 2048 sets */
655 else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
656 l2_set_bits = 10; /* 1024 sets */
657 else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
658 || OCTEON_IS_MODEL(OCTEON_CN52XX))
659 l2_set_bits = 9; /* 512 sets */
660 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
661 l2_set_bits = 8; /* 256 sets */
662 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
663 l2_set_bits = 7; /* 128 sets */
664 else {
665 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
666 l2_set_bits = 11; /* 2048 sets */
667 }
668 return l2_set_bits;
669
670}
671
672/* Return the number of sets in the L2 Cache */
673int cvmx_l2c_get_num_sets(void)
674{
675 return 1 << cvmx_l2c_get_set_bits();
676}
677
678/* Return the number of associations in the L2 Cache */
679int cvmx_l2c_get_num_assoc(void)
680{
681 int l2_assoc;
682 if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
683 OCTEON_IS_MODEL(OCTEON_CN52XX) ||
684 OCTEON_IS_MODEL(OCTEON_CN58XX) ||
685 OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX))
686 l2_assoc = 8;
687 else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
688 OCTEON_IS_MODEL(OCTEON_CN30XX))
689 l2_assoc = 4;
690 else {
691 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
692 l2_assoc = 8;
693 }
694
695 /* Check to see if part of the cache is disabled */
696 if (cvmx_fuse_read(265))
697 l2_assoc = l2_assoc >> 2;
698 else if (cvmx_fuse_read(264))
699 l2_assoc = l2_assoc >> 1;
700
701 return l2_assoc;
702}
703
704/**
705 * Flush a line from the L2 cache
706 * This should only be called from one core at a time, as this routine
707 * sets the core to the 'debug' core in order to flush the line.
708 *
709 * @assoc: Association (or way) to flush
710 * @index: Index to flush
711 */
712void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
713{
714 union cvmx_l2c_dbg l2cdbg;
715
716 l2cdbg.u64 = 0;
717 l2cdbg.s.ppnum = cvmx_get_core_num();
718 l2cdbg.s.finv = 1;
719
720 l2cdbg.s.set = assoc;
721 /*
722 * Enter debug mode, and make sure all other writes complete
723 * before we enter debug mode.
724 */
725 asm volatile ("sync" : : : "memory");
726 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
727 cvmx_read_csr(CVMX_L2C_DBG);
728
729 CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0);
730 /* Exit debug mode */
731 asm volatile ("sync" : : : "memory");
732 cvmx_write_csr(CVMX_L2C_DBG, 0);
733 cvmx_read_csr(CVMX_L2C_DBG);
734}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
new file mode 100644
index 000000000000..4812370706a1
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -0,0 +1,116 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * This module provides system/board/application information obtained
30 * by the bootloader.
31 */
32
33#include <asm/octeon/cvmx.h>
34#include <asm/octeon/cvmx-spinlock.h>
35#include <asm/octeon/cvmx-sysinfo.h>
36
37/**
38 * This structure defines the private state maintained by sysinfo module.
39 *
40 */
41static struct {
42 struct cvmx_sysinfo sysinfo; /* system information */
43 cvmx_spinlock_t lock; /* mutex spinlock */
44
45} state = {
46 .lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER
47};
48
49
50/*
51 * Global variables that define the min/max of the memory region set
52 * up for 32 bit userspace access.
53 */
54uint64_t linux_mem32_min;
55uint64_t linux_mem32_max;
56uint64_t linux_mem32_wired;
57uint64_t linux_mem32_offset;
58
59/**
60 * This function returns the application information as obtained
61 * by the bootloader. This provides the core mask of the cores
62 * running the same application image, as well as the physical
63 * memory regions available to the core.
64 *
65 * Returns Pointer to the boot information structure
66 *
67 */
68struct cvmx_sysinfo *cvmx_sysinfo_get(void)
69{
70 return &(state.sysinfo);
71}
72
73/**
74 * This function is used in non-simple executive environments (such as
75 * Linux kernel, u-boot, etc.) to configure the minimal fields that
76 * are required to use simple executive files directly.
77 *
78 * Locking (if required) must be handled outside of this
79 * function
80 *
81 * @phy_mem_desc_ptr:
82 * Pointer to global physical memory descriptor
83 * (bootmem descriptor) @board_type: Octeon board
84 * type enumeration
85 *
86 * @board_rev_major:
87 * Board major revision
88 * @board_rev_minor:
89 * Board minor revision
90 * @cpu_clock_hz:
91 * CPU clock freqency in hertz
92 *
93 * Returns 0: Failure
94 * 1: success
95 */
96int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
97 uint16_t board_type,
98 uint8_t board_rev_major,
99 uint8_t board_rev_minor,
100 uint32_t cpu_clock_hz)
101{
102
103 /* The sysinfo structure was already initialized */
104 if (state.sysinfo.board_type)
105 return 0;
106
107 memset(&(state.sysinfo), 0x0, sizeof(state.sysinfo));
108 state.sysinfo.phy_mem_desc_ptr = phy_mem_desc_ptr;
109 state.sysinfo.board_type = board_type;
110 state.sysinfo.board_rev_major = board_rev_major;
111 state.sysinfo.board_rev_minor = board_rev_minor;
112 state.sysinfo.cpu_clock_hz = cpu_clock_hz;
113
114 return 1;
115}
116
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
new file mode 100644
index 000000000000..9afc3794ed1b
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -0,0 +1,358 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * File defining functions for working with different Octeon
30 * models.
31 */
32#include <asm/octeon/octeon.h>
33
34/**
35 * Given the chip processor ID from COP0, this function returns a
36 * string representing the chip model number. The string is of the
37 * form CNXXXXpX.X-FREQ-SUFFIX.
38 * - XXXX = The chip model number
39 * - X.X = Chip pass number
40 * - FREQ = Current frequency in Mhz
41 * - SUFFIX = NSP, EXP, SCP, SSP, or CP
42 *
43 * @chip_id: Chip ID
44 *
45 * Returns Model string
46 */
47const char *octeon_model_get_string(uint32_t chip_id)
48{
49 static char buffer[32];
50 return octeon_model_get_string_buffer(chip_id, buffer);
51}
52
53/*
54 * Version of octeon_model_get_string() that takes buffer as argument,
55 * as running early in u-boot static/global variables don't work when
56 * running from flash.
57 */
58const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
59{
60 const char *family;
61 const char *core_model;
62 char pass[4];
63 int clock_mhz;
64 const char *suffix;
65 union cvmx_l2d_fus3 fus3;
66 int num_cores;
67 union cvmx_mio_fus_dat2 fus_dat2;
68 union cvmx_mio_fus_dat3 fus_dat3;
69 char fuse_model[10];
70 uint32_t fuse_data = 0;
71
72 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
73 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
74 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
75
76 num_cores = cvmx_octeon_num_cores();
77
78 /* Make sure the non existant devices look disabled */
79 switch ((chip_id >> 8) & 0xff) {
80 case 6: /* CN50XX */
81 case 2: /* CN30XX */
82 fus_dat3.s.nodfa_dte = 1;
83 fus_dat3.s.nozip = 1;
84 break;
85 case 4: /* CN57XX or CN56XX */
86 fus_dat3.s.nodfa_dte = 1;
87 break;
88 default:
89 break;
90 }
91
92 /* Make a guess at the suffix */
93 /* NSP = everything */
94 /* EXP = No crypto */
95 /* SCP = No DFA, No zip */
96 /* CP = No DFA, No crypto, No zip */
97 if (fus_dat3.s.nodfa_dte) {
98 if (fus_dat2.s.nocrypto)
99 suffix = "CP";
100 else
101 suffix = "SCP";
102 } else if (fus_dat2.s.nocrypto)
103 suffix = "EXP";
104 else
105 suffix = "NSP";
106
107 /*
108 * Assume pass number is encoded using <5:3><2:0>. Exceptions
109 * will be fixed later.
110 */
111 sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7);
112
113 /*
114 * Use the number of cores to determine the last 2 digits of
115 * the model number. There are some exceptions that are fixed
116 * later.
117 */
118 switch (num_cores) {
119 case 16:
120 core_model = "60";
121 break;
122 case 15:
123 core_model = "58";
124 break;
125 case 14:
126 core_model = "55";
127 break;
128 case 13:
129 core_model = "52";
130 break;
131 case 12:
132 core_model = "50";
133 break;
134 case 11:
135 core_model = "48";
136 break;
137 case 10:
138 core_model = "45";
139 break;
140 case 9:
141 core_model = "42";
142 break;
143 case 8:
144 core_model = "40";
145 break;
146 case 7:
147 core_model = "38";
148 break;
149 case 6:
150 core_model = "34";
151 break;
152 case 5:
153 core_model = "32";
154 break;
155 case 4:
156 core_model = "30";
157 break;
158 case 3:
159 core_model = "25";
160 break;
161 case 2:
162 core_model = "20";
163 break;
164 case 1:
165 core_model = "10";
166 break;
167 default:
168 core_model = "XX";
169 break;
170 }
171
172 /* Now figure out the family, the first two digits */
173 switch ((chip_id >> 8) & 0xff) {
174 case 0: /* CN38XX, CN37XX or CN36XX */
175 if (fus3.cn38xx.crip_512k) {
176 /*
177 * For some unknown reason, the 16 core one is
178 * called 37 instead of 36.
179 */
180 if (num_cores >= 16)
181 family = "37";
182 else
183 family = "36";
184 } else
185 family = "38";
186 /*
187 * This series of chips didn't follow the standard
188 * pass numbering.
189 */
190 switch (chip_id & 0xf) {
191 case 0:
192 strcpy(pass, "1.X");
193 break;
194 case 1:
195 strcpy(pass, "2.X");
196 break;
197 case 3:
198 strcpy(pass, "3.X");
199 break;
200 default:
201 strcpy(pass, "X.X");
202 break;
203 }
204 break;
205 case 1: /* CN31XX or CN3020 */
206 if ((chip_id & 0x10) || fus3.cn31xx.crip_128k)
207 family = "30";
208 else
209 family = "31";
210 /*
211 * This series of chips didn't follow the standard
212 * pass numbering.
213 */
214 switch (chip_id & 0xf) {
215 case 0:
216 strcpy(pass, "1.0");
217 break;
218 case 2:
219 strcpy(pass, "1.1");
220 break;
221 default:
222 strcpy(pass, "X.X");
223 break;
224 }
225 break;
226 case 2: /* CN3010 or CN3005 */
227 family = "30";
228 /* A chip with half cache is an 05 */
229 if (fus3.cn30xx.crip_64k)
230 core_model = "05";
231 /*
232 * This series of chips didn't follow the standard
233 * pass numbering.
234 */
235 switch (chip_id & 0xf) {
236 case 0:
237 strcpy(pass, "1.0");
238 break;
239 case 2:
240 strcpy(pass, "1.1");
241 break;
242 default:
243 strcpy(pass, "X.X");
244 break;
245 }
246 break;
247 case 3: /* CN58XX */
248 family = "58";
249 /* Special case. 4 core, no crypto */
250 if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
251 core_model = "29";
252
253 /* Pass 1 uses different encodings for pass numbers */
254 if ((chip_id & 0xFF) < 0x8) {
255 switch (chip_id & 0x3) {
256 case 0:
257 strcpy(pass, "1.0");
258 break;
259 case 1:
260 strcpy(pass, "1.1");
261 break;
262 case 3:
263 strcpy(pass, "1.2");
264 break;
265 default:
266 strcpy(pass, "1.X");
267 break;
268 }
269 }
270 break;
271 case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
272 if (fus_dat2.cn56xx.raid_en) {
273 if (fus3.cn56xx.crip_1024k)
274 family = "55";
275 else
276 family = "57";
277 if (fus_dat2.cn56xx.nocrypto)
278 suffix = "SP";
279 else
280 suffix = "SSP";
281 } else {
282 if (fus_dat2.cn56xx.nocrypto)
283 suffix = "CP";
284 else {
285 suffix = "NSP";
286 if (fus_dat3.s.nozip)
287 suffix = "SCP";
288 }
289 if (fus3.cn56xx.crip_1024k)
290 family = "54";
291 else
292 family = "56";
293 }
294 break;
295 case 6: /* CN50XX */
296 family = "50";
297 break;
298 case 7: /* CN52XX */
299 if (fus3.cn52xx.crip_256k)
300 family = "51";
301 else
302 family = "52";
303 break;
304 default:
305 family = "XX";
306 core_model = "XX";
307 strcpy(pass, "X.X");
308 suffix = "XXX";
309 break;
310 }
311
312 clock_mhz = octeon_get_clock_rate() / 1000000;
313
314 if (family[0] != '3') {
315 /* Check for model in fuses, overrides normal decode */
316 /* This is _not_ valid for Octeon CN3XXX models */
317 fuse_data |= cvmx_fuse_read_byte(51);
318 fuse_data = fuse_data << 8;
319 fuse_data |= cvmx_fuse_read_byte(50);
320 fuse_data = fuse_data << 8;
321 fuse_data |= cvmx_fuse_read_byte(49);
322 fuse_data = fuse_data << 8;
323 fuse_data |= cvmx_fuse_read_byte(48);
324 if (fuse_data & 0x7ffff) {
325 int model = fuse_data & 0x3fff;
326 int suffix = (fuse_data >> 14) & 0x1f;
327 if (suffix && model) {
328 /*
329 * Have both number and suffix in
330 * fuses, so both
331 */
332 sprintf(fuse_model, "%d%c",
333 model, 'A' + suffix - 1);
334 core_model = "";
335 family = fuse_model;
336 } else if (suffix && !model) {
337 /*
338 * Only have suffix, so add suffix to
339 * 'normal' model number.
340 */
341 sprintf(fuse_model, "%s%c", core_model,
342 'A' + suffix - 1);
343 core_model = fuse_model;
344 } else {
345 /*
346 * Don't have suffix, so just use
347 * model from fuses.
348 */
349 sprintf(fuse_model, "%d", model);
350 core_model = "";
351 family = fuse_model;
352 }
353 }
354 }
355 sprintf(buffer, "CN%s%sp%s-%d-%s",
356 family, core_model, pass, clock_mhz, suffix);
357 return buffer;
358}
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
new file mode 100644
index 000000000000..553d36cbcc42
--- /dev/null
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -0,0 +1,84 @@
1/*
2 * Octeon Bootbus flash setup
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2007, 2008 Cavium Networks
9 */
10#include <linux/kernel.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/map.h>
13#include <linux/mtd/partitions.h>
14
15#include <asm/octeon/octeon.h>
16
17static struct map_info flash_map;
18static struct mtd_info *mymtd;
19#ifdef CONFIG_MTD_PARTITIONS
20static int nr_parts;
21static struct mtd_partition *parts;
22static const char *part_probe_types[] = {
23 "cmdlinepart",
24#ifdef CONFIG_MTD_REDBOOT_PARTS
25 "RedBoot",
26#endif
27 NULL
28};
29#endif
30
31/**
32 * Module/ driver initialization.
33 *
34 * Returns Zero on success
35 */
36static int __init flash_init(void)
37{
38 /*
39 * Read the bootbus region 0 setup to determine the base
40 * address of the flash.
41 */
42 union cvmx_mio_boot_reg_cfgx region_cfg;
43 region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0));
44 if (region_cfg.s.en) {
45 /*
46 * The bootloader always takes the flash and sets its
47 * address so the entire flash fits below
48 * 0x1fc00000. This way the flash aliases to
49 * 0x1fc00000 for booting. Software can access the
50 * full flash at the true address, while core boot can
51 * access 4MB.
52 */
53 /* Use this name so old part lines work */
54 flash_map.name = "phys_mapped_flash";
55 flash_map.phys = region_cfg.s.base << 16;
56 flash_map.size = 0x1fc00000 - flash_map.phys;
57 flash_map.bankwidth = 1;
58 flash_map.virt = ioremap(flash_map.phys, flash_map.size);
59 pr_notice("Bootbus flash: Setting flash for %luMB flash at "
60 "0x%08lx\n", flash_map.size >> 20, flash_map.phys);
61 simple_map_init(&flash_map);
62 mymtd = do_map_probe("cfi_probe", &flash_map);
63 if (mymtd) {
64 mymtd->owner = THIS_MODULE;
65
66#ifdef CONFIG_MTD_PARTITIONS
67 nr_parts = parse_mtd_partitions(mymtd,
68 part_probe_types,
69 &parts, 0);
70 if (nr_parts > 0)
71 add_mtd_partitions(mymtd, parts, nr_parts);
72 else
73 add_mtd_device(mymtd);
74#else
75 add_mtd_device(mymtd);
76#endif
77 } else {
78 pr_err("Failed to register MTD device for flash\n");
79 }
80 }
81 return 0;
82}
83
84late_initcall(flash_init);
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
new file mode 100644
index 000000000000..fc72984a5dae
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -0,0 +1,497 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#include <linux/irq.h>
9#include <linux/interrupt.h>
10#include <linux/hardirq.h>
11
12#include <asm/octeon/octeon.h>
13
14DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
15DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
16DEFINE_SPINLOCK(octeon_irq_msi_lock);
17
18static void octeon_irq_core_ack(unsigned int irq)
19{
20 unsigned int bit = irq - OCTEON_IRQ_SW0;
21 /*
22 * We don't need to disable IRQs to make these atomic since
23 * they are already disabled earlier in the low level
24 * interrupt code.
25 */
26 clear_c0_status(0x100 << bit);
27 /* The two user interrupts must be cleared manually. */
28 if (bit < 2)
29 clear_c0_cause(0x100 << bit);
30}
31
32static void octeon_irq_core_eoi(unsigned int irq)
33{
34 irq_desc_t *desc = irq_desc + irq;
35 unsigned int bit = irq - OCTEON_IRQ_SW0;
36 /*
37 * If an IRQ is being processed while we are disabling it the
38 * handler will attempt to unmask the interrupt after it has
39 * been disabled.
40 */
41 if (desc->status & IRQ_DISABLED)
42 return;
43
44 /* There is a race here. We should fix it. */
45
46 /*
47 * We don't need to disable IRQs to make these atomic since
48 * they are already disabled earlier in the low level
49 * interrupt code.
50 */
51 set_c0_status(0x100 << bit);
52}
53
54static void octeon_irq_core_enable(unsigned int irq)
55{
56 unsigned long flags;
57 unsigned int bit = irq - OCTEON_IRQ_SW0;
58
59 /*
60 * We need to disable interrupts to make sure our updates are
61 * atomic.
62 */
63 local_irq_save(flags);
64 set_c0_status(0x100 << bit);
65 local_irq_restore(flags);
66}
67
68static void octeon_irq_core_disable_local(unsigned int irq)
69{
70 unsigned long flags;
71 unsigned int bit = irq - OCTEON_IRQ_SW0;
72 /*
73 * We need to disable interrupts to make sure our updates are
74 * atomic.
75 */
76 local_irq_save(flags);
77 clear_c0_status(0x100 << bit);
78 local_irq_restore(flags);
79}
80
81static void octeon_irq_core_disable(unsigned int irq)
82{
83#ifdef CONFIG_SMP
84 on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local,
85 (void *) (long) irq, 1);
86#else
87 octeon_irq_core_disable_local(irq);
88#endif
89}
90
91static struct irq_chip octeon_irq_chip_core = {
92 .name = "Core",
93 .enable = octeon_irq_core_enable,
94 .disable = octeon_irq_core_disable,
95 .ack = octeon_irq_core_ack,
96 .eoi = octeon_irq_core_eoi,
97};
98
99
100static void octeon_irq_ciu0_ack(unsigned int irq)
101{
102 /*
103 * In order to avoid any locking accessing the CIU, we
104 * acknowledge CIU interrupts by disabling all of them. This
105 * way we can use a per core register and avoid any out of
106 * core locking requirements. This has the side affect that
107 * CIU interrupts can't be processed recursively.
108 *
109 * We don't need to disable IRQs to make these atomic since
110 * they are already disabled earlier in the low level
111 * interrupt code.
112 */
113 clear_c0_status(0x100 << 2);
114}
115
116static void octeon_irq_ciu0_eoi(unsigned int irq)
117{
118 /*
119 * Enable all CIU interrupts again. We don't need to disable
120 * IRQs to make these atomic since they are already disabled
121 * earlier in the low level interrupt code.
122 */
123 set_c0_status(0x100 << 2);
124}
125
126static void octeon_irq_ciu0_enable(unsigned int irq)
127{
128 int coreid = cvmx_get_core_num();
129 unsigned long flags;
130 uint64_t en0;
131 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
132
133 /*
134 * A read lock is used here to make sure only one core is ever
135 * updating the CIU enable bits at a time. During an enable
136 * the cores don't interfere with each other. During a disable
137 * the write lock stops any enables that might cause a
138 * problem.
139 */
140 read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
141 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
142 en0 |= 1ull << bit;
143 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
144 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
145 read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
146}
147
148static void octeon_irq_ciu0_disable(unsigned int irq)
149{
150 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
151 unsigned long flags;
152 uint64_t en0;
153#ifdef CONFIG_SMP
154 int cpu;
155 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
156 for_each_online_cpu(cpu) {
157 int coreid = cpu_logical_map(cpu);
158 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
159 en0 &= ~(1ull << bit);
160 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
161 }
162 /*
163 * We need to do a read after the last update to make sure all
164 * of them are done.
165 */
166 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
167 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
168#else
169 int coreid = cvmx_get_core_num();
170 local_irq_save(flags);
171 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
172 en0 &= ~(1ull << bit);
173 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
174 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
175 local_irq_restore(flags);
176#endif
177}
178
179#ifdef CONFIG_SMP
180static void octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
181{
182 int cpu;
183 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
184
185 write_lock(&octeon_irq_ciu0_rwlock);
186 for_each_online_cpu(cpu) {
187 int coreid = cpu_logical_map(cpu);
188 uint64_t en0 =
189 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
190 if (cpumask_test_cpu(cpu, dest))
191 en0 |= 1ull << bit;
192 else
193 en0 &= ~(1ull << bit);
194 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
195 }
196 /*
197 * We need to do a read after the last update to make sure all
198 * of them are done.
199 */
200 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
201 write_unlock(&octeon_irq_ciu0_rwlock);
202}
203#endif
204
205static struct irq_chip octeon_irq_chip_ciu0 = {
206 .name = "CIU0",
207 .enable = octeon_irq_ciu0_enable,
208 .disable = octeon_irq_ciu0_disable,
209 .ack = octeon_irq_ciu0_ack,
210 .eoi = octeon_irq_ciu0_eoi,
211#ifdef CONFIG_SMP
212 .set_affinity = octeon_irq_ciu0_set_affinity,
213#endif
214};
215
216
217static void octeon_irq_ciu1_ack(unsigned int irq)
218{
219 /*
220 * In order to avoid any locking accessing the CIU, we
221 * acknowledge CIU interrupts by disabling all of them. This
222 * way we can use a per core register and avoid any out of
223 * core locking requirements. This has the side affect that
224 * CIU interrupts can't be processed recursively. We don't
225 * need to disable IRQs to make these atomic since they are
226 * already disabled earlier in the low level interrupt code.
227 */
228 clear_c0_status(0x100 << 3);
229}
230
231static void octeon_irq_ciu1_eoi(unsigned int irq)
232{
233 /*
234 * Enable all CIU interrupts again. We don't need to disable
235 * IRQs to make these atomic since they are already disabled
236 * earlier in the low level interrupt code.
237 */
238 set_c0_status(0x100 << 3);
239}
240
241static void octeon_irq_ciu1_enable(unsigned int irq)
242{
243 int coreid = cvmx_get_core_num();
244 unsigned long flags;
245 uint64_t en1;
246 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
247
248 /*
249 * A read lock is used here to make sure only one core is ever
250 * updating the CIU enable bits at a time. During an enable
251 * the cores don't interfere with each other. During a disable
252 * the write lock stops any enables that might cause a
253 * problem.
254 */
255 read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
256 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
257 en1 |= 1ull << bit;
258 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
259 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
260 read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
261}
262
263static void octeon_irq_ciu1_disable(unsigned int irq)
264{
265 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
266 unsigned long flags;
267 uint64_t en1;
268#ifdef CONFIG_SMP
269 int cpu;
270 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
271 for_each_online_cpu(cpu) {
272 int coreid = cpu_logical_map(cpu);
273 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
274 en1 &= ~(1ull << bit);
275 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
276 }
277 /*
278 * We need to do a read after the last update to make sure all
279 * of them are done.
280 */
281 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
282 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
283#else
284 int coreid = cvmx_get_core_num();
285 local_irq_save(flags);
286 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
287 en1 &= ~(1ull << bit);
288 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
289 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
290 local_irq_restore(flags);
291#endif
292}
293
294#ifdef CONFIG_SMP
295static void octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest)
296{
297 int cpu;
298 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
299
300 write_lock(&octeon_irq_ciu1_rwlock);
301 for_each_online_cpu(cpu) {
302 int coreid = cpu_logical_map(cpu);
303 uint64_t en1 =
304 cvmx_read_csr(CVMX_CIU_INTX_EN1
305 (coreid * 2 + 1));
306 if (cpumask_test_cpu(cpu, dest))
307 en1 |= 1ull << bit;
308 else
309 en1 &= ~(1ull << bit);
310 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
311 }
312 /*
313 * We need to do a read after the last update to make sure all
314 * of them are done.
315 */
316 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
317 write_unlock(&octeon_irq_ciu1_rwlock);
318}
319#endif
320
321static struct irq_chip octeon_irq_chip_ciu1 = {
322 .name = "CIU1",
323 .enable = octeon_irq_ciu1_enable,
324 .disable = octeon_irq_ciu1_disable,
325 .ack = octeon_irq_ciu1_ack,
326 .eoi = octeon_irq_ciu1_eoi,
327#ifdef CONFIG_SMP
328 .set_affinity = octeon_irq_ciu1_set_affinity,
329#endif
330};
331
332#ifdef CONFIG_PCI_MSI
333
334static void octeon_irq_msi_ack(unsigned int irq)
335{
336 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
337 /* These chips have PCI */
338 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
339 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
340 } else {
341 /*
342 * These chips have PCIe. Thankfully the ACK doesn't
343 * need any locking.
344 */
345 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
346 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
347 }
348}
349
350static void octeon_irq_msi_eoi(unsigned int irq)
351{
352 /* Nothing needed */
353}
354
355static void octeon_irq_msi_enable(unsigned int irq)
356{
357 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
358 /*
359 * Octeon PCI doesn't have the ability to mask/unmask
360 * MSI interrupts individually. Instead of
361 * masking/unmasking them in groups of 16, we simple
362 * assume MSI devices are well behaved. MSI
363 * interrupts are always enable and the ACK is assumed
364 * to be enough.
365 */
366 } else {
367 /* These chips have PCIe. Note that we only support
368 * the first 64 MSI interrupts. Unfortunately all the
369 * MSI enables are in the same register. We use
370 * MSI0's lock to control access to them all.
371 */
372 uint64_t en;
373 unsigned long flags;
374 spin_lock_irqsave(&octeon_irq_msi_lock, flags);
375 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
376 en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
377 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
378 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
379 spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
380 }
381}
382
383static void octeon_irq_msi_disable(unsigned int irq)
384{
385 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
386 /* See comment in enable */
387 } else {
388 /*
389 * These chips have PCIe. Note that we only support
390 * the first 64 MSI interrupts. Unfortunately all the
391 * MSI enables are in the same register. We use
392 * MSI0's lock to control access to them all.
393 */
394 uint64_t en;
395 unsigned long flags;
396 spin_lock_irqsave(&octeon_irq_msi_lock, flags);
397 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
398 en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
399 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
400 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
401 spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
402 }
403}
404
405static struct irq_chip octeon_irq_chip_msi = {
406 .name = "MSI",
407 .enable = octeon_irq_msi_enable,
408 .disable = octeon_irq_msi_disable,
409 .ack = octeon_irq_msi_ack,
410 .eoi = octeon_irq_msi_eoi,
411};
412#endif
413
414void __init arch_init_irq(void)
415{
416 int irq;
417
418#ifdef CONFIG_SMP
419 /* Set the default affinity to the boot cpu. */
420 cpumask_clear(irq_default_affinity);
421 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
422#endif
423
424 if (NR_IRQS < OCTEON_IRQ_LAST)
425 pr_err("octeon_irq_init: NR_IRQS is set too low\n");
426
427 /* 0 - 15 reserved for i8259 master and slave controller. */
428
429 /* 17 - 23 Mips internal */
430 for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
431 set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
432 handle_percpu_irq);
433 }
434
435 /* 24 - 87 CIU_INT_SUM0 */
436 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
437 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0,
438 handle_percpu_irq);
439 }
440
441 /* 88 - 151 CIU_INT_SUM1 */
442 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
443 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1,
444 handle_percpu_irq);
445 }
446
447#ifdef CONFIG_PCI_MSI
448 /* 152 - 215 PCI/PCIe MSI interrupts */
449 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
450 set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
451 handle_percpu_irq);
452 }
453#endif
454 set_c0_status(0x300 << 2);
455}
456
457asmlinkage void plat_irq_dispatch(void)
458{
459 const unsigned long core_id = cvmx_get_core_num();
460 const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
461 const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
462 const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
463 const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
464 unsigned long cop0_cause;
465 unsigned long cop0_status;
466 uint64_t ciu_en;
467 uint64_t ciu_sum;
468
469 while (1) {
470 cop0_cause = read_c0_cause();
471 cop0_status = read_c0_status();
472 cop0_cause &= cop0_status;
473 cop0_cause &= ST0_IM;
474
475 if (unlikely(cop0_cause & STATUSF_IP2)) {
476 ciu_sum = cvmx_read_csr(ciu_sum0_address);
477 ciu_en = cvmx_read_csr(ciu_en0_address);
478 ciu_sum &= ciu_en;
479 if (likely(ciu_sum))
480 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
481 else
482 spurious_interrupt();
483 } else if (unlikely(cop0_cause & STATUSF_IP3)) {
484 ciu_sum = cvmx_read_csr(ciu_sum1_address);
485 ciu_en = cvmx_read_csr(ciu_en1_address);
486 ciu_sum &= ciu_en;
487 if (likely(ciu_sum))
488 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
489 else
490 spurious_interrupt();
491 } else if (likely(cop0_cause)) {
492 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
493 } else {
494 break;
495 }
496 }
497}
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
new file mode 100644
index 000000000000..88e0cddca205
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -0,0 +1,521 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Unified implementation of memcpy, memmove and the __copy_user backend.
7 *
8 * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
9 * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
10 * Copyright (C) 2002 Broadcom, Inc.
11 * memcpy/copy_user author: Mark Vandevoorde
12 *
13 * Mnemonic names for arguments to memcpy/__copy_user
14 */
15
16#include <asm/asm.h>
17#include <asm/asm-offsets.h>
18#include <asm/regdef.h>
19
20#define dst a0
21#define src a1
22#define len a2
23
24/*
25 * Spec
26 *
27 * memcpy copies len bytes from src to dst and sets v0 to dst.
28 * It assumes that
29 * - src and dst don't overlap
30 * - src is readable
31 * - dst is writable
32 * memcpy uses the standard calling convention
33 *
34 * __copy_user copies up to len bytes from src to dst and sets a2 (len) to
35 * the number of uncopied bytes due to an exception caused by a read or write.
36 * __copy_user assumes that src and dst don't overlap, and that the call is
37 * implementing one of the following:
38 * copy_to_user
39 * - src is readable (no exceptions when reading src)
40 * copy_from_user
41 * - dst is writable (no exceptions when writing dst)
42 * __copy_user uses a non-standard calling convention; see
43 * arch/mips/include/asm/uaccess.h
44 *
45 * When an exception happens on a load, the handler must
46 # ensure that all of the destination buffer is overwritten to prevent
47 * leaking information to user mode programs.
48 */
49
50/*
51 * Implementation
52 */
53
54/*
55 * The exception handler for loads requires that:
56 * 1- AT contain the address of the byte just past the end of the source
57 * of the copy,
58 * 2- src_entry <= src < AT, and
59 * 3- (dst - src) == (dst_entry - src_entry),
60 * The _entry suffix denotes values when __copy_user was called.
61 *
62 * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
63 * (2) is met by incrementing src by the number of bytes copied
64 * (3) is met by not doing loads between a pair of increments of dst and src
65 *
66 * The exception handlers for stores adjust len (if necessary) and return.
67 * These handlers do not need to overwrite any data.
68 *
69 * For __rmemcpy and memmove an exception is always a kernel bug, therefore
70 * they're not protected.
71 */
72
73#define EXC(inst_reg,addr,handler) \
749: inst_reg, addr; \
75 .section __ex_table,"a"; \
76 PTR 9b, handler; \
77 .previous
78
79/*
80 * Only on the 64-bit kernel we can made use of 64-bit registers.
81 */
82#ifdef CONFIG_64BIT
83#define USE_DOUBLE
84#endif
85
86#ifdef USE_DOUBLE
87
88#define LOAD ld
89#define LOADL ldl
90#define LOADR ldr
91#define STOREL sdl
92#define STORER sdr
93#define STORE sd
94#define ADD daddu
95#define SUB dsubu
96#define SRL dsrl
97#define SRA dsra
98#define SLL dsll
99#define SLLV dsllv
100#define SRLV dsrlv
101#define NBYTES 8
102#define LOG_NBYTES 3
103
104/*
105 * As we are sharing code base with the mips32 tree (which use the o32 ABI
106 * register definitions). We need to redefine the register definitions from
107 * the n64 ABI register naming to the o32 ABI register naming.
108 */
109#undef t0
110#undef t1
111#undef t2
112#undef t3
113#define t0 $8
114#define t1 $9
115#define t2 $10
116#define t3 $11
117#define t4 $12
118#define t5 $13
119#define t6 $14
120#define t7 $15
121
122#else
123
124#define LOAD lw
125#define LOADL lwl
126#define LOADR lwr
127#define STOREL swl
128#define STORER swr
129#define STORE sw
130#define ADD addu
131#define SUB subu
132#define SRL srl
133#define SLL sll
134#define SRA sra
135#define SLLV sllv
136#define SRLV srlv
137#define NBYTES 4
138#define LOG_NBYTES 2
139
140#endif /* USE_DOUBLE */
141
142#ifdef CONFIG_CPU_LITTLE_ENDIAN
143#define LDFIRST LOADR
144#define LDREST LOADL
145#define STFIRST STORER
146#define STREST STOREL
147#define SHIFT_DISCARD SLLV
148#else
149#define LDFIRST LOADL
150#define LDREST LOADR
151#define STFIRST STOREL
152#define STREST STORER
153#define SHIFT_DISCARD SRLV
154#endif
155
156#define FIRST(unit) ((unit)*NBYTES)
157#define REST(unit) (FIRST(unit)+NBYTES-1)
158#define UNIT(unit) FIRST(unit)
159
160#define ADDRMASK (NBYTES-1)
161
162 .text
163 .set noreorder
164 .set noat
165
166/*
167 * A combined memcpy/__copy_user
168 * __copy_user sets len to 0 for success; else to an upper bound of
169 * the number of uncopied bytes.
170 * memcpy sets v0 to dst.
171 */
172 .align 5
173LEAF(memcpy) /* a0=dst a1=src a2=len */
174 move v0, dst /* return value */
175__memcpy:
176FEXPORT(__copy_user)
177 /*
178 * Note: dst & src may be unaligned, len may be 0
179 * Temps
180 */
181 #
182 # Octeon doesn't care if the destination is unaligned. The hardware
183 # can fix it faster than we can special case the assembly.
184 #
185 pref 0, 0(src)
186 sltu t0, len, NBYTES # Check if < 1 word
187 bnez t0, copy_bytes_checklen
188 and t0, src, ADDRMASK # Check if src unaligned
189 bnez t0, src_unaligned
190 sltu t0, len, 4*NBYTES # Check if < 4 words
191 bnez t0, less_than_4units
192 sltu t0, len, 8*NBYTES # Check if < 8 words
193 bnez t0, less_than_8units
194 sltu t0, len, 16*NBYTES # Check if < 16 words
195 bnez t0, cleanup_both_aligned
196 sltu t0, len, 128+1 # Check if len < 129
197 bnez t0, 1f # Skip prefetch if len is too short
198 sltu t0, len, 256+1 # Check if len < 257
199 bnez t0, 1f # Skip prefetch if len is too short
200 pref 0, 128(src) # We must not prefetch invalid addresses
201 #
202 # This is where we loop if there is more than 128 bytes left
2032: pref 0, 256(src) # We must not prefetch invalid addresses
204 #
205 # This is where we loop if we can't prefetch anymore
2061:
207EXC( LOAD t0, UNIT(0)(src), l_exc)
208EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
209EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
210EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
211 SUB len, len, 16*NBYTES
212EXC( STORE t0, UNIT(0)(dst), s_exc_p16u)
213EXC( STORE t1, UNIT(1)(dst), s_exc_p15u)
214EXC( STORE t2, UNIT(2)(dst), s_exc_p14u)
215EXC( STORE t3, UNIT(3)(dst), s_exc_p13u)
216EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
217EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
218EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
219EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
220EXC( STORE t0, UNIT(4)(dst), s_exc_p12u)
221EXC( STORE t1, UNIT(5)(dst), s_exc_p11u)
222EXC( STORE t2, UNIT(6)(dst), s_exc_p10u)
223 ADD src, src, 16*NBYTES
224EXC( STORE t3, UNIT(7)(dst), s_exc_p9u)
225 ADD dst, dst, 16*NBYTES
226EXC( LOAD t0, UNIT(-8)(src), l_exc_copy)
227EXC( LOAD t1, UNIT(-7)(src), l_exc_copy)
228EXC( LOAD t2, UNIT(-6)(src), l_exc_copy)
229EXC( LOAD t3, UNIT(-5)(src), l_exc_copy)
230EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u)
231EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u)
232EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u)
233EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
234EXC( LOAD t0, UNIT(-4)(src), l_exc_copy)
235EXC( LOAD t1, UNIT(-3)(src), l_exc_copy)
236EXC( LOAD t2, UNIT(-2)(src), l_exc_copy)
237EXC( LOAD t3, UNIT(-1)(src), l_exc_copy)
238EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u)
239EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u)
240EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u)
241EXC( STORE t3, UNIT(-1)(dst), s_exc_p1u)
242 sltu t0, len, 256+1 # See if we can prefetch more
243 beqz t0, 2b
244 sltu t0, len, 128 # See if we can loop more time
245 beqz t0, 1b
246 nop
247 #
248 # Jump here if there are less than 16*NBYTES left.
249 #
250cleanup_both_aligned:
251 beqz len, done
252 sltu t0, len, 8*NBYTES
253 bnez t0, less_than_8units
254 nop
255EXC( LOAD t0, UNIT(0)(src), l_exc)
256EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
257EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
258EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
259 SUB len, len, 8*NBYTES
260EXC( STORE t0, UNIT(0)(dst), s_exc_p8u)
261EXC( STORE t1, UNIT(1)(dst), s_exc_p7u)
262EXC( STORE t2, UNIT(2)(dst), s_exc_p6u)
263EXC( STORE t3, UNIT(3)(dst), s_exc_p5u)
264EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
265EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
266EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
267EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
268EXC( STORE t0, UNIT(4)(dst), s_exc_p4u)
269EXC( STORE t1, UNIT(5)(dst), s_exc_p3u)
270EXC( STORE t2, UNIT(6)(dst), s_exc_p2u)
271EXC( STORE t3, UNIT(7)(dst), s_exc_p1u)
272 ADD src, src, 8*NBYTES
273 beqz len, done
274 ADD dst, dst, 8*NBYTES
275 #
276 # Jump here if there are less than 8*NBYTES left.
277 #
278less_than_8units:
279 sltu t0, len, 4*NBYTES
280 bnez t0, less_than_4units
281 nop
282EXC( LOAD t0, UNIT(0)(src), l_exc)
283EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
284EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
285EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
286 SUB len, len, 4*NBYTES
287EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
288EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
289EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
290EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
291 ADD src, src, 4*NBYTES
292 beqz len, done
293 ADD dst, dst, 4*NBYTES
294 #
295 # Jump here if there are less than 4*NBYTES left. This means
296 # we may need to copy up to 3 NBYTES words.
297 #
298less_than_4units:
299 sltu t0, len, 1*NBYTES
300 bnez t0, copy_bytes_checklen
301 nop
302 #
303 # 1) Copy NBYTES, then check length again
304 #
305EXC( LOAD t0, 0(src), l_exc)
306 SUB len, len, NBYTES
307 sltu t1, len, 8
308EXC( STORE t0, 0(dst), s_exc_p1u)
309 ADD src, src, NBYTES
310 bnez t1, copy_bytes_checklen
311 ADD dst, dst, NBYTES
312 #
313 # 2) Copy NBYTES, then check length again
314 #
315EXC( LOAD t0, 0(src), l_exc)
316 SUB len, len, NBYTES
317 sltu t1, len, 8
318EXC( STORE t0, 0(dst), s_exc_p1u)
319 ADD src, src, NBYTES
320 bnez t1, copy_bytes_checklen
321 ADD dst, dst, NBYTES
322 #
323 # 3) Copy NBYTES, then check length again
324 #
325EXC( LOAD t0, 0(src), l_exc)
326 SUB len, len, NBYTES
327 ADD src, src, NBYTES
328 ADD dst, dst, NBYTES
329 b copy_bytes_checklen
330EXC( STORE t0, -8(dst), s_exc_p1u)
331
332src_unaligned:
333#define rem t8
334 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
335 beqz t0, cleanup_src_unaligned
336 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
3371:
338/*
339 * Avoid consecutive LD*'s to the same register since some mips
340 * implementations can't issue them in the same cycle.
341 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
342 * are to the same unit (unless src is aligned, but it's not).
343 */
344EXC( LDFIRST t0, FIRST(0)(src), l_exc)
345EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
346 SUB len, len, 4*NBYTES
347EXC( LDREST t0, REST(0)(src), l_exc_copy)
348EXC( LDREST t1, REST(1)(src), l_exc_copy)
349EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
350EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
351EXC( LDREST t2, REST(2)(src), l_exc_copy)
352EXC( LDREST t3, REST(3)(src), l_exc_copy)
353 ADD src, src, 4*NBYTES
354EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
355EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
356EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
357EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
358 bne len, rem, 1b
359 ADD dst, dst, 4*NBYTES
360
361cleanup_src_unaligned:
362 beqz len, done
363 and rem, len, NBYTES-1 # rem = len % NBYTES
364 beq rem, len, copy_bytes
365 nop
3661:
367EXC( LDFIRST t0, FIRST(0)(src), l_exc)
368EXC( LDREST t0, REST(0)(src), l_exc_copy)
369 SUB len, len, NBYTES
370EXC( STORE t0, 0(dst), s_exc_p1u)
371 ADD src, src, NBYTES
372 bne len, rem, 1b
373 ADD dst, dst, NBYTES
374
375copy_bytes_checklen:
376 beqz len, done
377 nop
378copy_bytes:
379 /* 0 < len < NBYTES */
380#define COPY_BYTE(N) \
381EXC( lb t0, N(src), l_exc); \
382 SUB len, len, 1; \
383 beqz len, done; \
384EXC( sb t0, N(dst), s_exc_p1)
385
386 COPY_BYTE(0)
387 COPY_BYTE(1)
388#ifdef USE_DOUBLE
389 COPY_BYTE(2)
390 COPY_BYTE(3)
391 COPY_BYTE(4)
392 COPY_BYTE(5)
393#endif
394EXC( lb t0, NBYTES-2(src), l_exc)
395 SUB len, len, 1
396 jr ra
397EXC( sb t0, NBYTES-2(dst), s_exc_p1)
398done:
399 jr ra
400 nop
401 END(memcpy)
402
403l_exc_copy:
404 /*
405 * Copy bytes from src until faulting load address (or until a
406 * lb faults)
407 *
408 * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
409 * may be more than a byte beyond the last address.
410 * Hence, the lb below may get an exception.
411 *
412 * Assumes src < THREAD_BUADDR($28)
413 */
414 LOAD t0, TI_TASK($28)
415 nop
416 LOAD t0, THREAD_BUADDR(t0)
4171:
418EXC( lb t1, 0(src), l_exc)
419 ADD src, src, 1
420 sb t1, 0(dst) # can't fault -- we're copy_from_user
421 bne src, t0, 1b
422 ADD dst, dst, 1
423l_exc:
424 LOAD t0, TI_TASK($28)
425 nop
426 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
427 nop
428 SUB len, AT, t0 # len number of uncopied bytes
429 /*
430 * Here's where we rely on src and dst being incremented in tandem,
431 * See (3) above.
432 * dst += (fault addr - src) to put dst at first byte to clear
433 */
434 ADD dst, t0 # compute start address in a1
435 SUB dst, src
436 /*
437 * Clear len bytes starting at dst. Can't call __bzero because it
438 * might modify len. An inefficient loop for these rare times...
439 */
440 beqz len, done
441 SUB src, len, 1
4421: sb zero, 0(dst)
443 ADD dst, dst, 1
444 bnez src, 1b
445 SUB src, src, 1
446 jr ra
447 nop
448
449
450#define SEXC(n) \
451s_exc_p ## n ## u: \
452 jr ra; \
453 ADD len, len, n*NBYTES
454
455SEXC(16)
456SEXC(15)
457SEXC(14)
458SEXC(13)
459SEXC(12)
460SEXC(11)
461SEXC(10)
462SEXC(9)
463SEXC(8)
464SEXC(7)
465SEXC(6)
466SEXC(5)
467SEXC(4)
468SEXC(3)
469SEXC(2)
470SEXC(1)
471
472s_exc_p1:
473 jr ra
474 ADD len, len, 1
475s_exc:
476 jr ra
477 nop
478
479 .align 5
480LEAF(memmove)
481 ADD t0, a0, a2
482 ADD t1, a1, a2
483 sltu t0, a1, t0 # dst + len <= src -> memcpy
484 sltu t1, a0, t1 # dst >= src + len -> memcpy
485 and t0, t1
486 beqz t0, __memcpy
487 move v0, a0 /* return value */
488 beqz a2, r_out
489 END(memmove)
490
491 /* fall through to __rmemcpy */
492LEAF(__rmemcpy) /* a0=dst a1=src a2=len */
493 sltu t0, a1, a0
494 beqz t0, r_end_bytes_up # src >= dst
495 nop
496 ADD a0, a2 # dst = dst + len
497 ADD a1, a2 # src = src + len
498
499r_end_bytes:
500 lb t0, -1(a1)
501 SUB a2, a2, 0x1
502 sb t0, -1(a0)
503 SUB a1, a1, 0x1
504 bnez a2, r_end_bytes
505 SUB a0, a0, 0x1
506
507r_out:
508 jr ra
509 move a2, zero
510
511r_end_bytes_up:
512 lb t0, (a1)
513 SUB a2, a2, 0x1
514 sb t0, (a0)
515 ADD a1, a1, 0x1
516 bnez a2, r_end_bytes_up
517 ADD a0, a0, 0x1
518
519 jr ra
520 move a2, zero
521 END(__rmemcpy)
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
new file mode 100644
index 000000000000..8240728d485a
--- /dev/null
+++ b/arch/mips/cavium-octeon/serial.c
@@ -0,0 +1,136 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
7 */
8#include <linux/console.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/serial.h>
13#include <linux/serial_8250.h>
14#include <linux/serial_reg.h>
15#include <linux/tty.h>
16
17#include <asm/time.h>
18
19#include <asm/octeon/octeon.h>
20
21#ifdef CONFIG_GDB_CONSOLE
22#define DEBUG_UART 0
23#else
24#define DEBUG_UART 1
25#endif
26
27unsigned int octeon_serial_in(struct uart_port *up, int offset)
28{
29 int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
30 if (offset == UART_IIR && (rv & 0xf) == 7) {
31 /* Busy interrupt, read the USR (39) and try again. */
32 cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
33 rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
34 }
35 return rv;
36}
37
38void octeon_serial_out(struct uart_port *up, int offset, int value)
39{
40 /*
41 * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
42 * working.
43 */
44 if (offset == UART_LCR)
45 value &= 0x9f;
46 cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
47}
48
49/*
50 * Allocated in .bss, so it is all zeroed.
51 */
52#define OCTEON_MAX_UARTS 3
53static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1];
54static struct platform_device octeon_uart8250_device = {
55 .name = "serial8250",
56 .id = PLAT8250_DEV_PLATFORM,
57 .dev = {
58 .platform_data = octeon_uart8250_data,
59 },
60};
61
62static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
63{
64 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
65 p->type = PORT_OCTEON;
66 p->iotype = UPIO_MEM;
67 p->regshift = 3; /* I/O addresses are every 8 bytes */
68 p->uartclk = mips_hpt_frequency;
69 p->serial_in = octeon_serial_in;
70 p->serial_out = octeon_serial_out;
71}
72
73static int __init octeon_serial_init(void)
74{
75 int enable_uart0;
76 int enable_uart1;
77 int enable_uart2;
78 struct plat_serial8250_port *p;
79
80#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
81 /*
82 * If we are configured to run as the second of two kernels,
83 * disable uart0 and enable uart1. Uart0 is owned by the first
84 * kernel
85 */
86 enable_uart0 = 0;
87 enable_uart1 = 1;
88#else
89 /*
90 * We are configured for the first kernel. We'll enable uart0
91 * if the bootloader told us to use 0, otherwise will enable
92 * uart 1.
93 */
94 enable_uart0 = (octeon_get_boot_uart() == 0);
95 enable_uart1 = (octeon_get_boot_uart() == 1);
96#ifdef CONFIG_KGDB
97 enable_uart1 = 1;
98#endif
99#endif
100
101 /* Right now CN52XX is the only chip with a third uart */
102 enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX);
103
104 p = octeon_uart8250_data;
105 if (enable_uart0) {
106 /* Add a ttyS device for hardware uart 0 */
107 octeon_uart_set_common(p);
108 p->membase = (void *) CVMX_MIO_UARTX_RBR(0);
109 p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1);
110 p->irq = OCTEON_IRQ_UART0;
111 p++;
112 }
113
114 if (enable_uart1) {
115 /* Add a ttyS device for hardware uart 1 */
116 octeon_uart_set_common(p);
117 p->membase = (void *) CVMX_MIO_UARTX_RBR(1);
118 p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1);
119 p->irq = OCTEON_IRQ_UART1;
120 p++;
121 }
122 if (enable_uart2) {
123 /* Add a ttyS device for hardware uart 2 */
124 octeon_uart_set_common(p);
125 p->membase = (void *) CVMX_MIO_UART2_RBR;
126 p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1);
127 p->irq = OCTEON_IRQ_UART2;
128 p++;
129 }
130
131 BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]);
132
133 return platform_device_register(&octeon_uart8250_device);
134}
135
136device_initcall(octeon_serial_init);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
new file mode 100644
index 000000000000..e085feddb4a4
--- /dev/null
+++ b/arch/mips/cavium-octeon/setup.c
@@ -0,0 +1,929 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9#include <linux/init.h>
10#include <linux/console.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/serial.h>
16#include <linux/types.h>
17#include <linux/string.h> /* for memset */
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/time.h>
21#include <linux/platform_device.h>
22#include <linux/serial_core.h>
23#include <linux/serial_8250.h>
24#include <linux/string.h>
25
26#include <asm/processor.h>
27#include <asm/reboot.h>
28#include <asm/smp-ops.h>
29#include <asm/system.h>
30#include <asm/irq_cpu.h>
31#include <asm/mipsregs.h>
32#include <asm/bootinfo.h>
33#include <asm/sections.h>
34#include <asm/time.h>
35
36#include <asm/octeon/octeon.h>
37
38#ifdef CONFIG_CAVIUM_DECODE_RSL
39extern void cvmx_interrupt_rsl_decode(void);
40extern int __cvmx_interrupt_ecc_report_single_bit_errors;
41extern void cvmx_interrupt_rsl_enable(void);
42#endif
43
44extern struct plat_smp_ops octeon_smp_ops;
45
46#ifdef CONFIG_PCI
47extern void pci_console_init(const char *arg);
48#endif
49
50#ifdef CONFIG_CAVIUM_RESERVE32
51extern uint64_t octeon_reserve32_memory;
52#endif
53static unsigned long long MAX_MEMORY = 512ull << 20;
54
55struct octeon_boot_descriptor *octeon_boot_desc_ptr;
56
57struct cvmx_bootinfo *octeon_bootinfo;
58EXPORT_SYMBOL(octeon_bootinfo);
59
60#ifdef CONFIG_CAVIUM_RESERVE32
61uint64_t octeon_reserve32_memory;
62EXPORT_SYMBOL(octeon_reserve32_memory);
63#endif
64
65static int octeon_uart;
66
67extern asmlinkage void handle_int(void);
68extern asmlinkage void plat_irq_dispatch(void);
69
70/**
71 * Return non zero if we are currently running in the Octeon simulator
72 *
73 * Returns
74 */
75int octeon_is_simulation(void)
76{
77 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
78}
79EXPORT_SYMBOL(octeon_is_simulation);
80
81/**
82 * Return true if Octeon is in PCI Host mode. This means
83 * Linux can control the PCI bus.
84 *
85 * Returns Non zero if Octeon in host mode.
86 */
87int octeon_is_pci_host(void)
88{
89#ifdef CONFIG_PCI
90 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
91#else
92 return 0;
93#endif
94}
95
96/**
97 * Get the clock rate of Octeon
98 *
99 * Returns Clock rate in HZ
100 */
101uint64_t octeon_get_clock_rate(void)
102{
103 if (octeon_is_simulation())
104 octeon_bootinfo->eclock_hz = 6000000;
105 return octeon_bootinfo->eclock_hz;
106}
107EXPORT_SYMBOL(octeon_get_clock_rate);
108
109/**
110 * Write to the LCD display connected to the bootbus. This display
111 * exists on most Cavium evaluation boards. If it doesn't exist, then
112 * this function doesn't do anything.
113 *
114 * @s: String to write
115 */
116void octeon_write_lcd(const char *s)
117{
118 if (octeon_bootinfo->led_display_base_addr) {
119 void __iomem *lcd_address =
120 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
121 8);
122 int i;
123 for (i = 0; i < 8; i++, s++) {
124 if (*s)
125 iowrite8(*s, lcd_address + i);
126 else
127 iowrite8(' ', lcd_address + i);
128 }
129 iounmap(lcd_address);
130 }
131}
132
133/**
134 * Return the console uart passed by the bootloader
135 *
136 * Returns uart (0 or 1)
137 */
138int octeon_get_boot_uart(void)
139{
140 int uart;
141#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
142 uart = 1;
143#else
144 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
145 1 : 0;
146#endif
147 return uart;
148}
149
150/**
151 * Get the coremask Linux was booted on.
152 *
153 * Returns Core mask
154 */
155int octeon_get_boot_coremask(void)
156{
157 return octeon_boot_desc_ptr->core_mask;
158}
159
160/**
161 * Check the hardware BIST results for a CPU
162 */
163void octeon_check_cpu_bist(void)
164{
165 const int coreid = cvmx_get_core_num();
166 unsigned long long mask;
167 unsigned long long bist_val;
168
169 /* Check BIST results for COP0 registers */
170 mask = 0x1f00000000ull;
171 bist_val = read_octeon_c0_icacheerr();
172 if (bist_val & mask)
173 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
174 coreid, bist_val);
175
176 bist_val = read_octeon_c0_dcacheerr();
177 if (bist_val & 1)
178 pr_err("Core%d L1 Dcache parity error: "
179 "CacheErr(dcache) = 0x%llx\n",
180 coreid, bist_val);
181
182 mask = 0xfc00000000000000ull;
183 bist_val = read_c0_cvmmemctl();
184 if (bist_val & mask)
185 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
186 coreid, bist_val);
187
188 write_octeon_c0_dcacheerr(0);
189}
190
191#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
192/**
193 * Called on every core to setup the wired tlb entry needed
194 * if CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB is set.
195 *
196 */
197static void octeon_hal_setup_per_cpu_reserved32(void *unused)
198{
199 /*
200 * The config has selected to wire the reserve32 memory for all
201 * userspace applications. We need to put a wired TLB entry in for each
202 * 512MB of reserve32 memory. We only handle double 256MB pages here,
203 * so reserve32 must be multiple of 512MB.
204 */
205 uint32_t size = CONFIG_CAVIUM_RESERVE32;
206 uint32_t entrylo0 =
207 0x7 | ((octeon_reserve32_memory & ((1ul << 40) - 1)) >> 6);
208 uint32_t entrylo1 = entrylo0 + (256 << 14);
209 uint32_t entryhi = (0x80000000UL - (CONFIG_CAVIUM_RESERVE32 << 20));
210 while (size >= 512) {
211#if 0
212 pr_info("CPU%d: Adding double wired TLB entry for 0x%lx\n",
213 smp_processor_id(), entryhi);
214#endif
215 add_wired_entry(entrylo0, entrylo1, entryhi, PM_256M);
216 entrylo0 += 512 << 14;
217 entrylo1 += 512 << 14;
218 entryhi += 512 << 20;
219 size -= 512;
220 }
221}
222#endif /* CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB */
223
224/**
225 * Called to release the named block which was used to made sure
226 * that nobody used the memory for something else during
227 * init. Now we'll free it so userspace apps can use this
228 * memory region with bootmem_alloc.
229 *
230 * This function is called only once from prom_free_prom_memory().
231 */
232void octeon_hal_setup_reserved32(void)
233{
234#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
235 on_each_cpu(octeon_hal_setup_per_cpu_reserved32, NULL, 0, 1);
236#endif
237}
238
239/**
240 * Reboot Octeon
241 *
242 * @command: Command to pass to the bootloader. Currently ignored.
243 */
244static void octeon_restart(char *command)
245{
246 /* Disable all watchdogs before soft reset. They don't get cleared */
247#ifdef CONFIG_SMP
248 int cpu;
249 for_each_online_cpu(cpu)
250 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
251#else
252 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
253#endif
254
255 mb();
256 while (1)
257 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
258}
259
260
261/**
262 * Permanently stop a core.
263 *
264 * @arg: Ignored.
265 */
266static void octeon_kill_core(void *arg)
267{
268 mb();
269 if (octeon_is_simulation()) {
270 /* The simulator needs the watchdog to stop for dead cores */
271 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
272 /* A break instruction causes the simulator stop a core */
273 asm volatile ("sync\nbreak");
274 }
275}
276
277
278/**
279 * Halt the system
280 */
281static void octeon_halt(void)
282{
283 smp_call_function(octeon_kill_core, NULL, 0);
284
285 switch (octeon_bootinfo->board_type) {
286 case CVMX_BOARD_TYPE_NAO38:
287 /* Driving a 1 to GPIO 12 shuts off this board */
288 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
289 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
290 break;
291 default:
292 octeon_write_lcd("PowerOff");
293 break;
294 }
295
296 octeon_kill_core(NULL);
297}
298
299#if 0
300/**
301 * Platform time init specifics.
302 * Returns
303 */
304void __init plat_time_init(void)
305{
306 /* Nothing special here, but we are required to have one */
307}
308
309#endif
310
311/**
312 * Handle all the error condition interrupts that might occur.
313 *
314 */
315#ifdef CONFIG_CAVIUM_DECODE_RSL
316static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
317{
318 cvmx_interrupt_rsl_decode();
319 return IRQ_HANDLED;
320}
321#endif
322
323/**
324 * Return a string representing the system type
325 *
326 * Returns
327 */
328const char *octeon_board_type_string(void)
329{
330 static char name[80];
331 sprintf(name, "%s (%s)",
332 cvmx_board_type_to_string(octeon_bootinfo->board_type),
333 octeon_model_get_string(read_c0_prid()));
334 return name;
335}
336
337const char *get_system_type(void)
338 __attribute__ ((alias("octeon_board_type_string")));
339
340void octeon_user_io_init(void)
341{
342 union octeon_cvmemctl cvmmemctl;
343 union cvmx_iob_fau_timeout fau_timeout;
344 union cvmx_pow_nw_tim nm_tim;
345 uint64_t cvmctl;
346
347 /* Get the current settings for CP0_CVMMEMCTL_REG */
348 cvmmemctl.u64 = read_c0_cvmmemctl();
349 /* R/W If set, marked write-buffer entries time out the same
350 * as as other entries; if clear, marked write-buffer entries
351 * use the maximum timeout. */
352 cvmmemctl.s.dismarkwblongto = 1;
353 /* R/W If set, a merged store does not clear the write-buffer
354 * entry timeout state. */
355 cvmmemctl.s.dismrgclrwbto = 0;
356 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
357 * word location for an IOBDMA. The other 8 bits come from the
358 * SCRADDR field of the IOBDMA. */
359 cvmmemctl.s.iobdmascrmsb = 0;
360 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
361 * clear, SYNCWS and SYNCS only order unmarked
362 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
363 * set. */
364 cvmmemctl.s.syncwsmarked = 0;
365 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
366 cvmmemctl.s.dissyncws = 0;
367 /* R/W If set, no stall happens on write buffer full. */
368 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
369 cvmmemctl.s.diswbfst = 1;
370 else
371 cvmmemctl.s.diswbfst = 0;
372 /* R/W If set (and SX set), supervisor-level loads/stores can
373 * use XKPHYS addresses with <48>==0 */
374 cvmmemctl.s.xkmemenas = 0;
375
376 /* R/W If set (and UX set), user-level loads/stores can use
377 * XKPHYS addresses with VA<48>==0 */
378 cvmmemctl.s.xkmemenau = 0;
379
380 /* R/W If set (and SX set), supervisor-level loads/stores can
381 * use XKPHYS addresses with VA<48>==1 */
382 cvmmemctl.s.xkioenas = 0;
383
384 /* R/W If set (and UX set), user-level loads/stores can use
385 * XKPHYS addresses with VA<48>==1 */
386 cvmmemctl.s.xkioenau = 0;
387
388 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
389 * when this is set) RW, reset to 0. */
390 cvmmemctl.s.allsyncw = 0;
391
392 /* R/W If set, no stores merge, and all stores reach the
393 * coherent bus in order. */
394 cvmmemctl.s.nomerge = 0;
395 /* R/W Selects the bit in the counter used for DID time-outs 0
396 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
397 * between 1x and 2x this interval. For example, with
398 * DIDTTO=3, expiration interval is between 16K and 32K. */
399 cvmmemctl.s.didtto = 0;
400 /* R/W If set, the (mem) CSR clock never turns off. */
401 cvmmemctl.s.csrckalwys = 0;
402 /* R/W If set, mclk never turns off. */
403 cvmmemctl.s.mclkalwys = 0;
404 /* R/W Selects the bit in the counter used for write buffer
405 * flush time-outs (WBFLT+11) is the bit position in an
406 * internal counter used to determine expiration. The write
407 * buffer expires between 1x and 2x this interval. For
408 * example, with WBFLT = 0, a write buffer expires between 2K
409 * and 4K cycles after the write buffer entry is allocated. */
410 cvmmemctl.s.wbfltime = 0;
411 /* R/W If set, do not put Istream in the L2 cache. */
412 cvmmemctl.s.istrnol2 = 0;
413 /* R/W The write buffer threshold. */
414 cvmmemctl.s.wbthresh = 10;
415 /* R/W If set, CVMSEG is available for loads/stores in
416 * kernel/debug mode. */
417#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
418 cvmmemctl.s.cvmsegenak = 1;
419#else
420 cvmmemctl.s.cvmsegenak = 0;
421#endif
422 /* R/W If set, CVMSEG is available for loads/stores in
423 * supervisor mode. */
424 cvmmemctl.s.cvmsegenas = 0;
425 /* R/W If set, CVMSEG is available for loads/stores in user
426 * mode. */
427 cvmmemctl.s.cvmsegenau = 0;
428 /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
429 * is max legal value. */
430 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
431
432
433 if (smp_processor_id() == 0)
434 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
435 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
436 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
437
438 write_c0_cvmmemctl(cvmmemctl.u64);
439
440 /* Move the performance counter interrupts to IRQ 6 */
441 cvmctl = read_c0_cvmctl();
442 cvmctl &= ~(7 << 7);
443 cvmctl |= 6 << 7;
444 write_c0_cvmctl(cvmctl);
445
446 /* Set a default for the hardware timeouts */
447 fau_timeout.u64 = 0;
448 fau_timeout.s.tout_val = 0xfff;
449 /* Disable tagwait FAU timeout */
450 fau_timeout.s.tout_enb = 0;
451 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
452
453 nm_tim.u64 = 0;
454 /* 4096 cycles */
455 nm_tim.s.nw_tim = 3;
456 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
457
458 write_octeon_c0_icacheerr(0);
459 write_c0_derraddr1(0);
460}
461
462/**
463 * Early entry point for arch setup
464 */
465void __init prom_init(void)
466{
467 struct cvmx_sysinfo *sysinfo;
468 const int coreid = cvmx_get_core_num();
469 int i;
470 int argc;
471 struct uart_port octeon_port;
472#ifdef CONFIG_CAVIUM_RESERVE32
473 int64_t addr = -1;
474#endif
475 /*
476 * The bootloader passes a pointer to the boot descriptor in
477 * $a3, this is available as fw_arg3.
478 */
479 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
480 octeon_bootinfo =
481 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
482 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
483
484 /*
485 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
486 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
487 */
488 if (!octeon_is_simulation() &&
489 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
490 cvmx_write_csr(CVMX_LED_EN, 0);
491 cvmx_write_csr(CVMX_LED_PRT, 0);
492 cvmx_write_csr(CVMX_LED_DBG, 0);
493 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
494 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
495 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
496 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
497 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
498 cvmx_write_csr(CVMX_LED_EN, 1);
499 }
500#ifdef CONFIG_CAVIUM_RESERVE32
501 /*
502 * We need to temporarily allocate all memory in the reserve32
503 * region. This makes sure the kernel doesn't allocate this
504 * memory when it is getting memory from the
505 * bootloader. Later, after the memory allocations are
506 * complete, the reserve32 will be freed.
507 */
508#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
509 if (CONFIG_CAVIUM_RESERVE32 & 0x1ff)
510 pr_err("CAVIUM_RESERVE32 isn't a multiple of 512MB. "
511 "This is required if CAVIUM_RESERVE32_USE_WIRED_TLB "
512 "is set\n");
513 else
514 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
515 0, 0, 512 << 20,
516 "CAVIUM_RESERVE32", 0);
517#else
518 /*
519 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
520 * is in case we later use hugetlb entries with it.
521 */
522 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
523 0, 0, 2 << 20,
524 "CAVIUM_RESERVE32", 0);
525#endif
526 if (addr < 0)
527 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
528 else
529 octeon_reserve32_memory = addr;
530#endif
531
532#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
533 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
534 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
535 } else {
536 uint32_t ebase = read_c0_ebase() & 0x3ffff000;
537#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
538 /* TLB refill */
539 cvmx_l2c_lock_mem_region(ebase, 0x100);
540#endif
541#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
542 /* General exception */
543 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
544#endif
545#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
546 /* Interrupt handler */
547 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
548#endif
549#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
550 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
551 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
552#endif
553#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
554 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
555#endif
556 }
557#endif
558
559 sysinfo = cvmx_sysinfo_get();
560 memset(sysinfo, 0, sizeof(*sysinfo));
561 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
562 sysinfo->phy_mem_desc_ptr =
563 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
564 sysinfo->core_mask = octeon_bootinfo->core_mask;
565 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
566 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
567 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
568 sysinfo->board_type = octeon_bootinfo->board_type;
569 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
570 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
571 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
572 sizeof(sysinfo->mac_addr_base));
573 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
574 memcpy(sysinfo->board_serial_number,
575 octeon_bootinfo->board_serial_number,
576 sizeof(sysinfo->board_serial_number));
577 sysinfo->compact_flash_common_base_addr =
578 octeon_bootinfo->compact_flash_common_base_addr;
579 sysinfo->compact_flash_attribute_base_addr =
580 octeon_bootinfo->compact_flash_attribute_base_addr;
581 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
582 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
583 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
584
585
586 octeon_check_cpu_bist();
587
588 octeon_uart = octeon_get_boot_uart();
589
590 /*
591 * Disable All CIU Interrupts. The ones we need will be
592 * enabled later. Read the SUM register so we know the write
593 * completed.
594 */
595 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
596 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
597 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
598 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
599 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
600
601#ifdef CONFIG_SMP
602 octeon_write_lcd("LinuxSMP");
603#else
604 octeon_write_lcd("Linux");
605#endif
606
607#ifdef CONFIG_CAVIUM_GDB
608 /*
609 * When debugging the linux kernel, force the cores to enter
610 * the debug exception handler to break in.
611 */
612 if (octeon_get_boot_debug_flag()) {
613 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
614 cvmx_read_csr(CVMX_CIU_DINT);
615 }
616#endif
617
618 /*
619 * BIST should always be enabled when doing a soft reset. L2
620 * Cache locking for instance is not cleared unless BIST is
621 * enabled. Unfortunately due to a chip errata G-200 for
622 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
623 */
624 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
625 OCTEON_IS_MODEL(OCTEON_CN31XX))
626 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
627 else
628 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
629
630 /* Default to 64MB in the simulator to speed things up */
631 if (octeon_is_simulation())
632 MAX_MEMORY = 64ull << 20;
633
634 arcs_cmdline[0] = 0;
635 argc = octeon_boot_desc_ptr->argc;
636 for (i = 0; i < argc; i++) {
637 const char *arg =
638 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
639 if ((strncmp(arg, "MEM=", 4) == 0) ||
640 (strncmp(arg, "mem=", 4) == 0)) {
641 sscanf(arg + 4, "%llu", &MAX_MEMORY);
642 MAX_MEMORY <<= 20;
643 if (MAX_MEMORY == 0)
644 MAX_MEMORY = 32ull << 30;
645 } else if (strcmp(arg, "ecc_verbose") == 0) {
646#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
647 __cvmx_interrupt_ecc_report_single_bit_errors = 1;
648 pr_notice("Reporting of single bit ECC errors is "
649 "turned on\n");
650#endif
651 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
652 sizeof(arcs_cmdline) - 1) {
653 strcat(arcs_cmdline, " ");
654 strcat(arcs_cmdline, arg);
655 }
656 }
657
658 if (strstr(arcs_cmdline, "console=") == NULL) {
659#ifdef CONFIG_GDB_CONSOLE
660 strcat(arcs_cmdline, " console=gdb");
661#else
662#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
663 strcat(arcs_cmdline, " console=ttyS0,115200");
664#else
665 if (octeon_uart == 1)
666 strcat(arcs_cmdline, " console=ttyS1,115200");
667 else
668 strcat(arcs_cmdline, " console=ttyS0,115200");
669#endif
670#endif
671 }
672
673 if (octeon_is_simulation()) {
674 /*
675 * The simulator uses a mtdram device pre filled with
676 * the filesystem. Also specify the calibration delay
677 * to avoid calculating it every time.
678 */
679 strcat(arcs_cmdline, " rw root=1f00"
680 " lpj=60176 slram=root,0x40000000,+1073741824");
681 }
682
683 mips_hpt_frequency = octeon_get_clock_rate();
684
685 octeon_init_cvmcount();
686
687 _machine_restart = octeon_restart;
688 _machine_halt = octeon_halt;
689
690 memset(&octeon_port, 0, sizeof(octeon_port));
691 /*
692 * For early_serial_setup we don't set the port type or
693 * UPF_FIXED_TYPE.
694 */
695 octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ;
696 octeon_port.iotype = UPIO_MEM;
697 /* I/O addresses are every 8 bytes */
698 octeon_port.regshift = 3;
699 /* Clock rate of the chip */
700 octeon_port.uartclk = mips_hpt_frequency;
701 octeon_port.fifosize = 64;
702 octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart);
703 octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase);
704 octeon_port.serial_in = octeon_serial_in;
705 octeon_port.serial_out = octeon_serial_out;
706#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
707 octeon_port.line = 0;
708#else
709 octeon_port.line = octeon_uart;
710#endif
711 octeon_port.irq = 42 + octeon_uart;
712 early_serial_setup(&octeon_port);
713
714 octeon_user_io_init();
715 register_smp_ops(&octeon_smp_ops);
716}
717
718void __init plat_mem_setup(void)
719{
720 uint64_t mem_alloc_size;
721 uint64_t total;
722 int64_t memory;
723
724 total = 0;
725
726 /* First add the init memory we will be returning. */
727 memory = __pa_symbol(&__init_begin) & PAGE_MASK;
728 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
729 if (mem_alloc_size > 0) {
730 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
731 total += mem_alloc_size;
732 }
733
734 /*
735 * The Mips memory init uses the first memory location for
736 * some memory vectors. When SPARSEMEM is in use, it doesn't
737 * verify that the size is big enough for the final
738 * vectors. Making the smallest chuck 4MB seems to be enough
739 * to consistantly work.
740 */
741 mem_alloc_size = 4 << 20;
742 if (mem_alloc_size > MAX_MEMORY)
743 mem_alloc_size = MAX_MEMORY;
744
745 /*
746 * When allocating memory, we want incrementing addresses from
747 * bootmem_alloc so the code in add_memory_region can merge
748 * regions next to each other.
749 */
750 cvmx_bootmem_lock();
751 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
752 && (total < MAX_MEMORY)) {
753#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
754 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
755 __pa_symbol(&__init_end), -1,
756 0x100000,
757 CVMX_BOOTMEM_FLAG_NO_LOCKING);
758#elif defined(CONFIG_HIGHMEM)
759 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
760 0x100000,
761 CVMX_BOOTMEM_FLAG_NO_LOCKING);
762#else
763 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
764 0x100000,
765 CVMX_BOOTMEM_FLAG_NO_LOCKING);
766#endif
767 if (memory >= 0) {
768 /*
769 * This function automatically merges address
770 * regions next to each other if they are
771 * received in incrementing order.
772 */
773 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
774 total += mem_alloc_size;
775 } else {
776 break;
777 }
778 }
779 cvmx_bootmem_unlock();
780
781#ifdef CONFIG_CAVIUM_RESERVE32
782 /*
783 * Now that we've allocated the kernel memory it is safe to
784 * free the reserved region. We free it here so that builtin
785 * drivers can use the memory.
786 */
787 if (octeon_reserve32_memory)
788 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
789#endif /* CONFIG_CAVIUM_RESERVE32 */
790
791 if (total == 0)
792 panic("Unable to allocate memory from "
793 "cvmx_bootmem_phy_alloc\n");
794}
795
796
797int prom_putchar(char c)
798{
799 uint64_t lsrval;
800
801 /* Spin until there is room */
802 do {
803 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
804 } while ((lsrval & 0x20) == 0);
805
806 /* Write the byte */
807 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c);
808 return 1;
809}
810
811void prom_free_prom_memory(void)
812{
813#ifdef CONFIG_CAVIUM_DECODE_RSL
814 cvmx_interrupt_rsl_enable();
815
816 /* Add an interrupt handler for general failures. */
817 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
818 "RML/RSL", octeon_rlm_interrupt)) {
819 panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
820 }
821#endif
822
823 /* This call is here so that it is performed after any TLB
824 initializations. It needs to be after these in case the
825 CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
826 octeon_hal_setup_reserved32();
827}
828
829static struct octeon_cf_data octeon_cf_data;
830
831static int __init octeon_cf_device_init(void)
832{
833 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
834 unsigned long base_ptr, region_base, region_size;
835 struct platform_device *pd;
836 struct resource cf_resources[3];
837 unsigned int num_resources;
838 int i;
839 int ret = 0;
840
841 /* Setup octeon-cf platform device if present. */
842 base_ptr = 0;
843 if (octeon_bootinfo->major_version == 1
844 && octeon_bootinfo->minor_version >= 1) {
845 if (octeon_bootinfo->compact_flash_common_base_addr)
846 base_ptr =
847 octeon_bootinfo->compact_flash_common_base_addr;
848 } else {
849 base_ptr = 0x1d000800;
850 }
851
852 if (!base_ptr)
853 return ret;
854
855 /* Find CS0 region. */
856 for (i = 0; i < 8; i++) {
857 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
858 region_base = mio_boot_reg_cfg.s.base << 16;
859 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
860 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
861 && base_ptr < region_base + region_size)
862 break;
863 }
864 if (i >= 7) {
865 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
866 goto out;
867 }
868 octeon_cf_data.base_region = i;
869 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
870 octeon_cf_data.base_region_bias = base_ptr - region_base;
871 memset(cf_resources, 0, sizeof(cf_resources));
872 num_resources = 0;
873 cf_resources[num_resources].flags = IORESOURCE_MEM;
874 cf_resources[num_resources].start = region_base;
875 cf_resources[num_resources].end = region_base + region_size - 1;
876 num_resources++;
877
878
879 if (!(base_ptr & 0xfffful)) {
880 /*
881 * Boot loader signals availability of DMA (true_ide
882 * mode) by setting low order bits of base_ptr to
883 * zero.
884 */
885
886 /* Asume that CS1 immediately follows. */
887 mio_boot_reg_cfg.u64 =
888 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
889 region_base = mio_boot_reg_cfg.s.base << 16;
890 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
891 if (!mio_boot_reg_cfg.s.en)
892 goto out;
893
894 cf_resources[num_resources].flags = IORESOURCE_MEM;
895 cf_resources[num_resources].start = region_base;
896 cf_resources[num_resources].end = region_base + region_size - 1;
897 num_resources++;
898
899 octeon_cf_data.dma_engine = 0;
900 cf_resources[num_resources].flags = IORESOURCE_IRQ;
901 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
902 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
903 num_resources++;
904 } else {
905 octeon_cf_data.dma_engine = -1;
906 }
907
908 pd = platform_device_alloc("pata_octeon_cf", -1);
909 if (!pd) {
910 ret = -ENOMEM;
911 goto out;
912 }
913 pd->dev.platform_data = &octeon_cf_data;
914
915 ret = platform_device_add_resources(pd, cf_resources, num_resources);
916 if (ret)
917 goto fail;
918
919 ret = platform_device_add(pd);
920 if (ret)
921 goto fail;
922
923 return ret;
924fail:
925 platform_device_put(pd);
926out:
927 return ret;
928}
929device_initcall(octeon_cf_device_init);
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
new file mode 100644
index 000000000000..24e0ad63980a
--- /dev/null
+++ b/arch/mips/cavium-octeon/smp.c
@@ -0,0 +1,211 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#include <linux/init.h>
9#include <linux/delay.h>
10#include <linux/smp.h>
11#include <linux/interrupt.h>
12#include <linux/kernel_stat.h>
13#include <linux/sched.h>
14#include <linux/module.h>
15
16#include <asm/mmu_context.h>
17#include <asm/system.h>
18#include <asm/time.h>
19
20#include <asm/octeon/octeon.h>
21
22volatile unsigned long octeon_processor_boot = 0xff;
23volatile unsigned long octeon_processor_sp;
24volatile unsigned long octeon_processor_gp;
25
26static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
27{
28 const int coreid = cvmx_get_core_num();
29 uint64_t action;
30
31 /* Load the mailbox register to figure out what we're supposed to do */
32 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid));
33
34 /* Clear the mailbox to clear the interrupt */
35 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
36
37 if (action & SMP_CALL_FUNCTION)
38 smp_call_function_interrupt();
39
40 /* Check if we've been told to flush the icache */
41 if (action & SMP_ICACHE_FLUSH)
42 asm volatile ("synci 0($0)\n");
43 return IRQ_HANDLED;
44}
45
46/**
47 * Cause the function described by call_data to be executed on the passed
48 * cpu. When the function has finished, increment the finished field of
49 * call_data.
50 */
51void octeon_send_ipi_single(int cpu, unsigned int action)
52{
53 int coreid = cpu_logical_map(cpu);
54 /*
55 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
56 coreid, action);
57 */
58 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
59}
60
61static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
62{
63 unsigned int i;
64
65 for_each_cpu_mask(i, mask)
66 octeon_send_ipi_single(i, action);
67}
68
69/**
70 * Detect available CPUs, populate phys_cpu_present_map
71 */
72static void octeon_smp_setup(void)
73{
74 const int coreid = cvmx_get_core_num();
75 int cpus;
76 int id;
77
78 int core_mask = octeon_get_boot_coremask();
79
80 cpus_clear(cpu_possible_map);
81 __cpu_number_map[coreid] = 0;
82 __cpu_logical_map[0] = coreid;
83 cpu_set(0, cpu_possible_map);
84
85 cpus = 1;
86 for (id = 0; id < 16; id++) {
87 if ((id != coreid) && (core_mask & (1 << id))) {
88 cpu_set(cpus, cpu_possible_map);
89 __cpu_number_map[id] = cpus;
90 __cpu_logical_map[cpus] = id;
91 cpus++;
92 }
93 }
94}
95
96/**
97 * Firmware CPU startup hook
98 *
99 */
100static void octeon_boot_secondary(int cpu, struct task_struct *idle)
101{
102 int count;
103
104 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
105 cpu_logical_map(cpu));
106
107 octeon_processor_sp = __KSTK_TOS(idle);
108 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
109 octeon_processor_boot = cpu_logical_map(cpu);
110 mb();
111
112 count = 10000;
113 while (octeon_processor_sp && count) {
114 /* Waiting for processor to get the SP and GP */
115 udelay(1);
116 count--;
117 }
118 if (count == 0)
119 pr_err("Secondary boot timeout\n");
120}
121
122/**
123 * After we've done initial boot, this function is called to allow the
124 * board code to clean up state, if needed
125 */
126static void octeon_init_secondary(void)
127{
128 const int coreid = cvmx_get_core_num();
129 union cvmx_ciu_intx_sum0 interrupt_enable;
130
131 octeon_check_cpu_bist();
132 octeon_init_cvmcount();
133 /*
134 pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
135 */
136 /* Enable Mailbox interrupts to this core. These are the only
137 interrupts allowed on line 3 */
138 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
139 interrupt_enable.u64 = 0;
140 interrupt_enable.s.mbox = 0x3;
141 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
142 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
143 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
144 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
145 /* Enable core interrupt processing for 2,3 and 7 */
146 set_c0_status(0x8c01);
147}
148
149/**
150 * Callout to firmware before smp_init
151 *
152 */
153void octeon_prepare_cpus(unsigned int max_cpus)
154{
155 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
156 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED,
157 "mailbox0", mailbox_interrupt)) {
158 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
159 }
160 if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED,
161 "mailbox1", mailbox_interrupt)) {
162 panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
163 }
164}
165
166/**
167 * Last chance for the board code to finish SMP initialization before
168 * the CPU is "online".
169 */
170static void octeon_smp_finish(void)
171{
172#ifdef CONFIG_CAVIUM_GDB
173 unsigned long tmp;
174 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
175 to be not masked by this core so we know the signal is received by
176 someone */
177 asm volatile ("dmfc0 %0, $22\n"
178 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
179#endif
180
181 octeon_user_io_init();
182
183 /* to generate the first CPU timer interrupt */
184 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
185}
186
187/**
188 * Hook for after all CPUs are online
189 */
190static void octeon_cpus_done(void)
191{
192#ifdef CONFIG_CAVIUM_GDB
193 unsigned long tmp;
194 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
195 to be not masked by this core so we know the signal is received by
196 someone */
197 asm volatile ("dmfc0 %0, $22\n"
198 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
199#endif
200}
201
202struct plat_smp_ops octeon_smp_ops = {
203 .send_ipi_single = octeon_send_ipi_single,
204 .send_ipi_mask = octeon_send_ipi_mask,
205 .init_secondary = octeon_init_secondary,
206 .smp_finish = octeon_smp_finish,
207 .cpus_done = octeon_cpus_done,
208 .boot_secondary = octeon_boot_secondary,
209 .smp_setup = octeon_smp_setup,
210 .prepare_cpus = octeon_prepare_cpus,
211};
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
new file mode 100644
index 000000000000..7afaa28a3768
--- /dev/null
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -0,0 +1,943 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc6
4# Wed Dec 3 11:00:58 2008
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
19# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set
21# CONFIG_MACH_EMMA is not set
22# CONFIG_MACH_VR41XX is not set
23# CONFIG_NXP_STB220 is not set
24# CONFIG_NXP_STB225 is not set
25# CONFIG_PNX8550_JBS is not set
26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set
29# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP28 is not set
32# CONFIG_SGI_IP32 is not set
33# CONFIG_SIBYTE_CRHINE is not set
34# CONFIG_SIBYTE_CARMEL is not set
35# CONFIG_SIBYTE_CRHONE is not set
36# CONFIG_SIBYTE_RHONE is not set
37# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set
39# CONFIG_SIBYTE_SENTOSA is not set
40# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set
42# CONFIG_MACH_TX39XX is not set
43# CONFIG_MACH_TX49XX is not set
44# CONFIG_MIKROTIK_RB532 is not set
45# CONFIG_WR_PPMC is not set
46# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
47CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
48CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y
49# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set
50CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y
51CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
52CONFIG_CAVIUM_OCTEON_LOCK_L2=y
53CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
54CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
55CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
56CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
57CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
58CONFIG_ARCH_SPARSEMEM_ENABLE=y
59CONFIG_RWSEM_GENERIC_SPINLOCK=y
60# CONFIG_ARCH_HAS_ILOG2_U32 is not set
61# CONFIG_ARCH_HAS_ILOG2_U64 is not set
62CONFIG_ARCH_SUPPORTS_OPROFILE=y
63CONFIG_GENERIC_FIND_NEXT_BIT=y
64CONFIG_GENERIC_HWEIGHT=y
65CONFIG_GENERIC_CALIBRATE_DELAY=y
66CONFIG_GENERIC_CLOCKEVENTS=y
67CONFIG_GENERIC_TIME=y
68CONFIG_GENERIC_CMOS_UPDATE=y
69CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
70# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
71CONFIG_CEVT_R4K=y
72CONFIG_CSRC_R4K=y
73CONFIG_DMA_COHERENT=y
74# CONFIG_EARLY_PRINTK is not set
75CONFIG_SYS_HAS_EARLY_PRINTK=y
76# CONFIG_HOTPLUG_CPU is not set
77# CONFIG_NO_IOPORT is not set
78CONFIG_CPU_BIG_ENDIAN=y
79# CONFIG_CPU_LITTLE_ENDIAN is not set
80CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
81CONFIG_IRQ_CPU=y
82CONFIG_IRQ_CPU_OCTEON=y
83CONFIG_SWAP_IO_SPACE=y
84CONFIG_MIPS_L1_CACHE_SHIFT=7
85
86#
87# CPU selection
88#
89# CONFIG_CPU_LOONGSON2 is not set
90# CONFIG_CPU_MIPS32_R1 is not set
91# CONFIG_CPU_MIPS32_R2 is not set
92# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set
97# CONFIG_CPU_R4300 is not set
98# CONFIG_CPU_R4X00 is not set
99# CONFIG_CPU_TX49XX is not set
100# CONFIG_CPU_R5000 is not set
101# CONFIG_CPU_R5432 is not set
102# CONFIG_CPU_R5500 is not set
103# CONFIG_CPU_R6000 is not set
104# CONFIG_CPU_NEVADA is not set
105# CONFIG_CPU_R8000 is not set
106# CONFIG_CPU_R10000 is not set
107# CONFIG_CPU_RM7000 is not set
108# CONFIG_CPU_RM9000 is not set
109# CONFIG_CPU_SB1 is not set
110CONFIG_CPU_CAVIUM_OCTEON=y
111CONFIG_WEAK_ORDERING=y
112CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
113CONFIG_CPU_MIPSR2=y
114CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
115CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
116
117#
118# Kernel type
119#
120# CONFIG_32BIT is not set
121CONFIG_64BIT=y
122CONFIG_PAGE_SIZE_4KB=y
123# CONFIG_PAGE_SIZE_8KB is not set
124# CONFIG_PAGE_SIZE_16KB is not set
125# CONFIG_PAGE_SIZE_64KB is not set
126CONFIG_CPU_HAS_PREFETCH=y
127CONFIG_MIPS_MT_DISABLED=y
128# CONFIG_MIPS_MT_SMP is not set
129# CONFIG_MIPS_MT_SMTC is not set
130CONFIG_64BIT_PHYS_ADDR=y
131CONFIG_CPU_HAS_SYNC=y
132CONFIG_GENERIC_HARDIRQS=y
133CONFIG_GENERIC_IRQ_PROBE=y
134CONFIG_IRQ_PER_CPU=y
135CONFIG_CPU_SUPPORTS_HIGHMEM=y
136CONFIG_SYS_SUPPORTS_HIGHMEM=y
137CONFIG_ARCH_FLATMEM_ENABLE=y
138CONFIG_ARCH_POPULATES_NODE_MAP=y
139CONFIG_SELECT_MEMORY_MODEL=y
140# CONFIG_FLATMEM_MANUAL is not set
141# CONFIG_DISCONTIGMEM_MANUAL is not set
142CONFIG_SPARSEMEM_MANUAL=y
143CONFIG_SPARSEMEM=y
144CONFIG_HAVE_MEMORY_PRESENT=y
145CONFIG_SPARSEMEM_STATIC=y
146CONFIG_PAGEFLAGS_EXTENDED=y
147CONFIG_SPLIT_PTLOCK_CPUS=4
148CONFIG_RESOURCES_64BIT=y
149CONFIG_PHYS_ADDR_T_64BIT=y
150CONFIG_ZONE_DMA_FLAG=0
151CONFIG_VIRT_TO_BUS=y
152CONFIG_UNEVICTABLE_LRU=y
153CONFIG_SMP=y
154CONFIG_SYS_SUPPORTS_SMP=y
155CONFIG_NR_CPUS_DEFAULT_16=y
156CONFIG_NR_CPUS=16
157# CONFIG_NO_HZ is not set
158# CONFIG_HIGH_RES_TIMERS is not set
159CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
160# CONFIG_HZ_48 is not set
161# CONFIG_HZ_100 is not set
162# CONFIG_HZ_128 is not set
163CONFIG_HZ_250=y
164# CONFIG_HZ_256 is not set
165# CONFIG_HZ_1000 is not set
166# CONFIG_HZ_1024 is not set
167CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
168CONFIG_HZ=250
169# CONFIG_PREEMPT_NONE is not set
170# CONFIG_PREEMPT_VOLUNTARY is not set
171CONFIG_PREEMPT=y
172# CONFIG_PREEMPT_RCU is not set
173# CONFIG_KEXEC is not set
174CONFIG_SECCOMP=y
175CONFIG_LOCKDEP_SUPPORT=y
176CONFIG_STACKTRACE_SUPPORT=y
177CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
178
179#
180# General setup
181#
182CONFIG_EXPERIMENTAL=y
183CONFIG_LOCK_KERNEL=y
184CONFIG_INIT_ENV_ARG_LIMIT=32
185CONFIG_LOCALVERSION=""
186CONFIG_LOCALVERSION_AUTO=y
187CONFIG_SWAP=y
188CONFIG_SYSVIPC=y
189CONFIG_SYSVIPC_SYSCTL=y
190CONFIG_POSIX_MQUEUE=y
191CONFIG_BSD_PROCESS_ACCT=y
192CONFIG_BSD_PROCESS_ACCT_V3=y
193# CONFIG_TASKSTATS is not set
194# CONFIG_AUDIT is not set
195CONFIG_IKCONFIG=y
196CONFIG_IKCONFIG_PROC=y
197CONFIG_LOG_BUF_SHIFT=14
198# CONFIG_CGROUPS is not set
199CONFIG_GROUP_SCHED=y
200CONFIG_FAIR_GROUP_SCHED=y
201# CONFIG_RT_GROUP_SCHED is not set
202CONFIG_USER_SCHED=y
203# CONFIG_CGROUP_SCHED is not set
204CONFIG_SYSFS_DEPRECATED=y
205CONFIG_SYSFS_DEPRECATED_V2=y
206CONFIG_RELAY=y
207# CONFIG_NAMESPACES is not set
208CONFIG_BLK_DEV_INITRD=y
209CONFIG_INITRAMFS_SOURCE=""
210# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
211CONFIG_SYSCTL=y
212CONFIG_EMBEDDED=y
213CONFIG_SYSCTL_SYSCALL=y
214CONFIG_KALLSYMS=y
215# CONFIG_KALLSYMS_ALL is not set
216# CONFIG_KALLSYMS_EXTRA_PASS is not set
217CONFIG_HOTPLUG=y
218CONFIG_PRINTK=y
219CONFIG_BUG=y
220CONFIG_ELF_CORE=y
221# CONFIG_PCSPKR_PLATFORM is not set
222CONFIG_COMPAT_BRK=y
223CONFIG_BASE_FULL=y
224CONFIG_FUTEX=y
225CONFIG_ANON_INODES=y
226CONFIG_EPOLL=y
227CONFIG_SIGNALFD=y
228CONFIG_TIMERFD=y
229CONFIG_EVENTFD=y
230CONFIG_SHMEM=y
231CONFIG_AIO=y
232CONFIG_VM_EVENT_COUNTERS=y
233CONFIG_SLAB=y
234# CONFIG_SLUB is not set
235# CONFIG_SLOB is not set
236# CONFIG_PROFILING is not set
237# CONFIG_MARKERS is not set
238CONFIG_HAVE_OPROFILE=y
239CONFIG_USE_GENERIC_SMP_HELPERS=y
240# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
241CONFIG_SLABINFO=y
242CONFIG_RT_MUTEXES=y
243# CONFIG_TINY_SHMEM is not set
244CONFIG_BASE_SMALL=0
245CONFIG_MODULES=y
246# CONFIG_MODULE_FORCE_LOAD is not set
247CONFIG_MODULE_UNLOAD=y
248# CONFIG_MODULE_FORCE_UNLOAD is not set
249# CONFIG_MODVERSIONS is not set
250# CONFIG_MODULE_SRCVERSION_ALL is not set
251CONFIG_KMOD=y
252CONFIG_STOP_MACHINE=y
253CONFIG_BLOCK=y
254# CONFIG_BLK_DEV_IO_TRACE is not set
255# CONFIG_BLK_DEV_BSG is not set
256# CONFIG_BLK_DEV_INTEGRITY is not set
257CONFIG_BLOCK_COMPAT=y
258
259#
260# IO Schedulers
261#
262CONFIG_IOSCHED_NOOP=y
263CONFIG_IOSCHED_AS=y
264CONFIG_IOSCHED_DEADLINE=y
265CONFIG_IOSCHED_CFQ=y
266# CONFIG_DEFAULT_AS is not set
267# CONFIG_DEFAULT_DEADLINE is not set
268CONFIG_DEFAULT_CFQ=y
269# CONFIG_DEFAULT_NOOP is not set
270CONFIG_DEFAULT_IOSCHED="cfq"
271CONFIG_CLASSIC_RCU=y
272# CONFIG_PROBE_INITRD_HEADER is not set
273# CONFIG_FREEZER is not set
274
275#
276# Bus options (PCI, PCMCIA, EISA, ISA, TC)
277#
278# CONFIG_ARCH_SUPPORTS_MSI is not set
279CONFIG_MMU=y
280# CONFIG_PCCARD is not set
281
282#
283# Executable file formats
284#
285CONFIG_BINFMT_ELF=y
286# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
287# CONFIG_HAVE_AOUT is not set
288# CONFIG_BINFMT_MISC is not set
289CONFIG_MIPS32_COMPAT=y
290CONFIG_COMPAT=y
291CONFIG_SYSVIPC_COMPAT=y
292CONFIG_MIPS32_O32=y
293CONFIG_MIPS32_N32=y
294CONFIG_BINFMT_ELF32=y
295
296#
297# Power management options
298#
299# CONFIG_PM is not set
300CONFIG_NET=y
301
302#
303# Networking options
304#
305CONFIG_PACKET=y
306CONFIG_PACKET_MMAP=y
307CONFIG_UNIX=y
308CONFIG_XFRM=y
309# CONFIG_XFRM_USER is not set
310# CONFIG_XFRM_SUB_POLICY is not set
311# CONFIG_XFRM_MIGRATE is not set
312# CONFIG_XFRM_STATISTICS is not set
313# CONFIG_NET_KEY is not set
314CONFIG_INET=y
315CONFIG_IP_MULTICAST=y
316CONFIG_IP_ADVANCED_ROUTER=y
317CONFIG_ASK_IP_FIB_HASH=y
318# CONFIG_IP_FIB_TRIE is not set
319CONFIG_IP_FIB_HASH=y
320CONFIG_IP_MULTIPLE_TABLES=y
321CONFIG_IP_ROUTE_MULTIPATH=y
322CONFIG_IP_ROUTE_VERBOSE=y
323CONFIG_IP_PNP=y
324CONFIG_IP_PNP_DHCP=y
325CONFIG_IP_PNP_BOOTP=y
326CONFIG_IP_PNP_RARP=y
327# CONFIG_NET_IPIP is not set
328# CONFIG_NET_IPGRE is not set
329CONFIG_IP_MROUTE=y
330CONFIG_IP_PIMSM_V1=y
331CONFIG_IP_PIMSM_V2=y
332# CONFIG_ARPD is not set
333CONFIG_SYN_COOKIES=y
334# CONFIG_INET_AH is not set
335# CONFIG_INET_ESP is not set
336# CONFIG_INET_IPCOMP is not set
337# CONFIG_INET_XFRM_TUNNEL is not set
338# CONFIG_INET_TUNNEL is not set
339CONFIG_INET_XFRM_MODE_TRANSPORT=y
340CONFIG_INET_XFRM_MODE_TUNNEL=y
341CONFIG_INET_XFRM_MODE_BEET=y
342# CONFIG_INET_LRO is not set
343CONFIG_INET_DIAG=y
344CONFIG_INET_TCP_DIAG=y
345# CONFIG_TCP_CONG_ADVANCED is not set
346CONFIG_TCP_CONG_CUBIC=y
347CONFIG_DEFAULT_TCP_CONG="cubic"
348# CONFIG_TCP_MD5SIG is not set
349# CONFIG_IPV6 is not set
350# CONFIG_NETLABEL is not set
351# CONFIG_NETWORK_SECMARK is not set
352# CONFIG_NETFILTER is not set
353# CONFIG_IP_DCCP is not set
354# CONFIG_IP_SCTP is not set
355# CONFIG_TIPC is not set
356# CONFIG_ATM is not set
357# CONFIG_BRIDGE is not set
358# CONFIG_NET_DSA is not set
359# CONFIG_VLAN_8021Q is not set
360# CONFIG_DECNET is not set
361# CONFIG_LLC2 is not set
362# CONFIG_IPX is not set
363# CONFIG_ATALK is not set
364# CONFIG_X25 is not set
365# CONFIG_LAPB is not set
366# CONFIG_ECONET is not set
367# CONFIG_WAN_ROUTER is not set
368# CONFIG_NET_SCHED is not set
369
370#
371# Network testing
372#
373# CONFIG_NET_PKTGEN is not set
374# CONFIG_HAMRADIO is not set
375# CONFIG_CAN is not set
376# CONFIG_IRDA is not set
377# CONFIG_BT is not set
378# CONFIG_AF_RXRPC is not set
379# CONFIG_PHONET is not set
380CONFIG_FIB_RULES=y
381# CONFIG_WIRELESS is not set
382# CONFIG_RFKILL is not set
383# CONFIG_NET_9P is not set
384
385#
386# Device Drivers
387#
388
389#
390# Generic Driver Options
391#
392CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
393CONFIG_STANDALONE=y
394CONFIG_PREVENT_FIRMWARE_BUILD=y
395# CONFIG_FW_LOADER is not set
396# CONFIG_DEBUG_DRIVER is not set
397# CONFIG_DEBUG_DEVRES is not set
398# CONFIG_SYS_HYPERVISOR is not set
399# CONFIG_CONNECTOR is not set
400CONFIG_MTD=y
401# CONFIG_MTD_DEBUG is not set
402# CONFIG_MTD_CONCAT is not set
403CONFIG_MTD_PARTITIONS=y
404# CONFIG_MTD_REDBOOT_PARTS is not set
405# CONFIG_MTD_CMDLINE_PARTS is not set
406# CONFIG_MTD_AR7_PARTS is not set
407
408#
409# User Modules And Translation Layers
410#
411CONFIG_MTD_CHAR=y
412CONFIG_MTD_BLKDEVS=y
413CONFIG_MTD_BLOCK=y
414# CONFIG_FTL is not set
415# CONFIG_NFTL is not set
416# CONFIG_INFTL is not set
417# CONFIG_RFD_FTL is not set
418# CONFIG_SSFDC is not set
419# CONFIG_MTD_OOPS is not set
420
421#
422# RAM/ROM/Flash chip drivers
423#
424CONFIG_MTD_CFI=y
425# CONFIG_MTD_JEDECPROBE is not set
426CONFIG_MTD_GEN_PROBE=y
427# CONFIG_MTD_CFI_ADV_OPTIONS is not set
428CONFIG_MTD_MAP_BANK_WIDTH_1=y
429CONFIG_MTD_MAP_BANK_WIDTH_2=y
430CONFIG_MTD_MAP_BANK_WIDTH_4=y
431# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
432# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
433# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
434CONFIG_MTD_CFI_I1=y
435CONFIG_MTD_CFI_I2=y
436# CONFIG_MTD_CFI_I4 is not set
437# CONFIG_MTD_CFI_I8 is not set
438# CONFIG_MTD_CFI_INTELEXT is not set
439CONFIG_MTD_CFI_AMDSTD=y
440# CONFIG_MTD_CFI_STAA is not set
441CONFIG_MTD_CFI_UTIL=y
442# CONFIG_MTD_RAM is not set
443# CONFIG_MTD_ROM is not set
444# CONFIG_MTD_ABSENT is not set
445
446#
447# Mapping drivers for chip access
448#
449# CONFIG_MTD_COMPLEX_MAPPINGS is not set
450CONFIG_MTD_PHYSMAP=y
451CONFIG_MTD_PHYSMAP_START=0x8000000
452CONFIG_MTD_PHYSMAP_LEN=0x0
453CONFIG_MTD_PHYSMAP_BANKWIDTH=2
454# CONFIG_MTD_PLATRAM is not set
455
456#
457# Self-contained MTD device drivers
458#
459# CONFIG_MTD_SLRAM is not set
460# CONFIG_MTD_PHRAM is not set
461# CONFIG_MTD_MTDRAM is not set
462# CONFIG_MTD_BLOCK2MTD is not set
463
464#
465# Disk-On-Chip Device Drivers
466#
467# CONFIG_MTD_DOC2000 is not set
468# CONFIG_MTD_DOC2001 is not set
469# CONFIG_MTD_DOC2001PLUS is not set
470# CONFIG_MTD_NAND is not set
471# CONFIG_MTD_ONENAND is not set
472
473#
474# UBI - Unsorted block images
475#
476# CONFIG_MTD_UBI is not set
477# CONFIG_PARPORT is not set
478CONFIG_BLK_DEV=y
479# CONFIG_BLK_DEV_COW_COMMON is not set
480CONFIG_BLK_DEV_LOOP=y
481# CONFIG_BLK_DEV_CRYPTOLOOP is not set
482# CONFIG_BLK_DEV_NBD is not set
483# CONFIG_BLK_DEV_RAM is not set
484# CONFIG_CDROM_PKTCDVD is not set
485# CONFIG_ATA_OVER_ETH is not set
486# CONFIG_BLK_DEV_HD is not set
487# CONFIG_MISC_DEVICES is not set
488CONFIG_HAVE_IDE=y
489# CONFIG_IDE is not set
490
491#
492# SCSI device support
493#
494# CONFIG_RAID_ATTRS is not set
495# CONFIG_SCSI is not set
496# CONFIG_SCSI_DMA is not set
497# CONFIG_SCSI_NETLINK is not set
498# CONFIG_ATA is not set
499# CONFIG_MD is not set
500CONFIG_NETDEVICES=y
501# CONFIG_DUMMY is not set
502# CONFIG_BONDING is not set
503# CONFIG_MACVLAN is not set
504# CONFIG_EQUALIZER is not set
505# CONFIG_TUN is not set
506# CONFIG_VETH is not set
507# CONFIG_PHYLIB is not set
508CONFIG_NET_ETHERNET=y
509CONFIG_MII=y
510# CONFIG_AX88796 is not set
511# CONFIG_SMC91X is not set
512# CONFIG_DM9000 is not set
513# CONFIG_IBM_NEW_EMAC_ZMII is not set
514# CONFIG_IBM_NEW_EMAC_RGMII is not set
515# CONFIG_IBM_NEW_EMAC_TAH is not set
516# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
517# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
518# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
519# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
520# CONFIG_B44 is not set
521CONFIG_NETDEV_1000=y
522# CONFIG_NETDEV_10000 is not set
523
524#
525# Wireless LAN
526#
527# CONFIG_WLAN_PRE80211 is not set
528# CONFIG_WLAN_80211 is not set
529# CONFIG_IWLWIFI_LEDS is not set
530# CONFIG_WAN is not set
531# CONFIG_PPP is not set
532# CONFIG_SLIP is not set
533# CONFIG_NETCONSOLE is not set
534# CONFIG_NETPOLL is not set
535# CONFIG_NET_POLL_CONTROLLER is not set
536# CONFIG_ISDN is not set
537# CONFIG_PHONE is not set
538
539#
540# Input device support
541#
542# CONFIG_INPUT is not set
543
544#
545# Hardware I/O ports
546#
547# CONFIG_SERIO is not set
548# CONFIG_GAMEPORT is not set
549
550#
551# Character devices
552#
553# CONFIG_VT is not set
554CONFIG_DEVKMEM=y
555# CONFIG_SERIAL_NONSTANDARD is not set
556
557#
558# Serial drivers
559#
560CONFIG_SERIAL_8250=y
561CONFIG_SERIAL_8250_CONSOLE=y
562CONFIG_SERIAL_8250_NR_UARTS=2
563CONFIG_SERIAL_8250_RUNTIME_UARTS=2
564# CONFIG_SERIAL_8250_EXTENDED is not set
565
566#
567# Non-8250 serial port support
568#
569CONFIG_SERIAL_CORE=y
570CONFIG_SERIAL_CORE_CONSOLE=y
571CONFIG_UNIX98_PTYS=y
572CONFIG_LEGACY_PTYS=y
573CONFIG_LEGACY_PTY_COUNT=256
574# CONFIG_IPMI_HANDLER is not set
575# CONFIG_HW_RANDOM is not set
576# CONFIG_R3964 is not set
577# CONFIG_RAW_DRIVER is not set
578# CONFIG_TCG_TPM is not set
579# CONFIG_I2C is not set
580# CONFIG_SPI is not set
581# CONFIG_W1 is not set
582# CONFIG_POWER_SUPPLY is not set
583# CONFIG_HWMON is not set
584# CONFIG_THERMAL is not set
585# CONFIG_THERMAL_HWMON is not set
586CONFIG_WATCHDOG=y
587# CONFIG_WATCHDOG_NOWAYOUT is not set
588
589#
590# Watchdog Device Drivers
591#
592# CONFIG_SOFT_WATCHDOG is not set
593CONFIG_SSB_POSSIBLE=y
594
595#
596# Sonics Silicon Backplane
597#
598# CONFIG_SSB is not set
599
600#
601# Multifunction device drivers
602#
603# CONFIG_MFD_CORE is not set
604# CONFIG_MFD_SM501 is not set
605# CONFIG_HTC_PASIC3 is not set
606# CONFIG_MFD_TMIO is not set
607# CONFIG_REGULATOR is not set
608
609#
610# Multimedia devices
611#
612
613#
614# Multimedia core support
615#
616# CONFIG_VIDEO_DEV is not set
617# CONFIG_DVB_CORE is not set
618# CONFIG_VIDEO_MEDIA is not set
619
620#
621# Multimedia drivers
622#
623# CONFIG_DAB is not set
624
625#
626# Graphics support
627#
628# CONFIG_VGASTATE is not set
629# CONFIG_VIDEO_OUTPUT_CONTROL is not set
630# CONFIG_FB is not set
631# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
632
633#
634# Display device support
635#
636# CONFIG_DISPLAY_SUPPORT is not set
637# CONFIG_SOUND is not set
638# CONFIG_USB_SUPPORT is not set
639# CONFIG_MMC is not set
640# CONFIG_MEMSTICK is not set
641# CONFIG_NEW_LEDS is not set
642# CONFIG_ACCESSIBILITY is not set
643CONFIG_RTC_LIB=y
644# CONFIG_RTC_CLASS is not set
645# CONFIG_DMADEVICES is not set
646# CONFIG_UIO is not set
647# CONFIG_STAGING is not set
648CONFIG_STAGING_EXCLUDE_BUILD=y
649
650#
651# File systems
652#
653# CONFIG_EXT2_FS is not set
654# CONFIG_EXT3_FS is not set
655# CONFIG_EXT4_FS is not set
656# CONFIG_REISERFS_FS is not set
657# CONFIG_JFS_FS is not set
658# CONFIG_FS_POSIX_ACL is not set
659CONFIG_FILE_LOCKING=y
660# CONFIG_XFS_FS is not set
661# CONFIG_GFS2_FS is not set
662# CONFIG_OCFS2_FS is not set
663CONFIG_DNOTIFY=y
664CONFIG_INOTIFY=y
665CONFIG_INOTIFY_USER=y
666# CONFIG_QUOTA is not set
667# CONFIG_AUTOFS_FS is not set
668# CONFIG_AUTOFS4_FS is not set
669# CONFIG_FUSE_FS is not set
670
671#
672# CD-ROM/DVD Filesystems
673#
674# CONFIG_ISO9660_FS is not set
675# CONFIG_UDF_FS is not set
676
677#
678# DOS/FAT/NT Filesystems
679#
680# CONFIG_MSDOS_FS is not set
681# CONFIG_VFAT_FS is not set
682# CONFIG_NTFS_FS is not set
683
684#
685# Pseudo filesystems
686#
687CONFIG_PROC_FS=y
688CONFIG_PROC_KCORE=y
689CONFIG_PROC_SYSCTL=y
690CONFIG_PROC_PAGE_MONITOR=y
691CONFIG_SYSFS=y
692CONFIG_TMPFS=y
693# CONFIG_TMPFS_POSIX_ACL is not set
694# CONFIG_HUGETLB_PAGE is not set
695# CONFIG_CONFIGFS_FS is not set
696
697#
698# Miscellaneous filesystems
699#
700# CONFIG_ADFS_FS is not set
701# CONFIG_AFFS_FS is not set
702# CONFIG_HFS_FS is not set
703# CONFIG_HFSPLUS_FS is not set
704# CONFIG_BEFS_FS is not set
705# CONFIG_BFS_FS is not set
706# CONFIG_EFS_FS is not set
707# CONFIG_JFFS2_FS is not set
708# CONFIG_CRAMFS is not set
709# CONFIG_VXFS_FS is not set
710# CONFIG_MINIX_FS is not set
711# CONFIG_OMFS_FS is not set
712# CONFIG_HPFS_FS is not set
713# CONFIG_QNX4FS_FS is not set
714# CONFIG_ROMFS_FS is not set
715# CONFIG_SYSV_FS is not set
716# CONFIG_UFS_FS is not set
717# CONFIG_NETWORK_FILESYSTEMS is not set
718
719#
720# Partition Types
721#
722# CONFIG_PARTITION_ADVANCED is not set
723CONFIG_MSDOS_PARTITION=y
724CONFIG_NLS=y
725CONFIG_NLS_DEFAULT="iso8859-1"
726CONFIG_NLS_CODEPAGE_437=y
727# CONFIG_NLS_CODEPAGE_737 is not set
728# CONFIG_NLS_CODEPAGE_775 is not set
729# CONFIG_NLS_CODEPAGE_850 is not set
730# CONFIG_NLS_CODEPAGE_852 is not set
731# CONFIG_NLS_CODEPAGE_855 is not set
732# CONFIG_NLS_CODEPAGE_857 is not set
733# CONFIG_NLS_CODEPAGE_860 is not set
734# CONFIG_NLS_CODEPAGE_861 is not set
735# CONFIG_NLS_CODEPAGE_862 is not set
736# CONFIG_NLS_CODEPAGE_863 is not set
737# CONFIG_NLS_CODEPAGE_864 is not set
738# CONFIG_NLS_CODEPAGE_865 is not set
739# CONFIG_NLS_CODEPAGE_866 is not set
740# CONFIG_NLS_CODEPAGE_869 is not set
741# CONFIG_NLS_CODEPAGE_936 is not set
742# CONFIG_NLS_CODEPAGE_950 is not set
743# CONFIG_NLS_CODEPAGE_932 is not set
744# CONFIG_NLS_CODEPAGE_949 is not set
745# CONFIG_NLS_CODEPAGE_874 is not set
746# CONFIG_NLS_ISO8859_8 is not set
747# CONFIG_NLS_CODEPAGE_1250 is not set
748# CONFIG_NLS_CODEPAGE_1251 is not set
749# CONFIG_NLS_ASCII is not set
750CONFIG_NLS_ISO8859_1=y
751# CONFIG_NLS_ISO8859_2 is not set
752# CONFIG_NLS_ISO8859_3 is not set
753# CONFIG_NLS_ISO8859_4 is not set
754# CONFIG_NLS_ISO8859_5 is not set
755# CONFIG_NLS_ISO8859_6 is not set
756# CONFIG_NLS_ISO8859_7 is not set
757# CONFIG_NLS_ISO8859_9 is not set
758# CONFIG_NLS_ISO8859_13 is not set
759# CONFIG_NLS_ISO8859_14 is not set
760# CONFIG_NLS_ISO8859_15 is not set
761# CONFIG_NLS_KOI8_R is not set
762# CONFIG_NLS_KOI8_U is not set
763# CONFIG_NLS_UTF8 is not set
764# CONFIG_DLM is not set
765
766#
767# Kernel hacking
768#
769CONFIG_TRACE_IRQFLAGS_SUPPORT=y
770# CONFIG_PRINTK_TIME is not set
771CONFIG_ENABLE_WARN_DEPRECATED=y
772CONFIG_ENABLE_MUST_CHECK=y
773CONFIG_FRAME_WARN=2048
774CONFIG_MAGIC_SYSRQ=y
775# CONFIG_UNUSED_SYMBOLS is not set
776CONFIG_DEBUG_FS=y
777# CONFIG_HEADERS_CHECK is not set
778CONFIG_DEBUG_KERNEL=y
779# CONFIG_DEBUG_SHIRQ is not set
780CONFIG_DETECT_SOFTLOCKUP=y
781# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
782CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
783CONFIG_SCHED_DEBUG=y
784# CONFIG_SCHEDSTATS is not set
785# CONFIG_TIMER_STATS is not set
786# CONFIG_DEBUG_OBJECTS is not set
787# CONFIG_DEBUG_SLAB is not set
788CONFIG_DEBUG_PREEMPT=y
789# CONFIG_DEBUG_RT_MUTEXES is not set
790# CONFIG_RT_MUTEX_TESTER is not set
791CONFIG_DEBUG_SPINLOCK=y
792# CONFIG_DEBUG_MUTEXES is not set
793# CONFIG_DEBUG_LOCK_ALLOC is not set
794# CONFIG_PROVE_LOCKING is not set
795# CONFIG_LOCK_STAT is not set
796CONFIG_DEBUG_SPINLOCK_SLEEP=y
797# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
798# CONFIG_DEBUG_KOBJECT is not set
799CONFIG_DEBUG_INFO=y
800# CONFIG_DEBUG_VM is not set
801# CONFIG_DEBUG_WRITECOUNT is not set
802# CONFIG_DEBUG_MEMORY_INIT is not set
803# CONFIG_DEBUG_LIST is not set
804# CONFIG_DEBUG_SG is not set
805# CONFIG_BOOT_PRINTK_DELAY is not set
806# CONFIG_RCU_TORTURE_TEST is not set
807# CONFIG_RCU_CPU_STALL_DETECTOR is not set
808# CONFIG_BACKTRACE_SELF_TEST is not set
809# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
810# CONFIG_FAULT_INJECTION is not set
811CONFIG_SYSCTL_SYSCALL_CHECK=y
812
813#
814# Tracers
815#
816# CONFIG_IRQSOFF_TRACER is not set
817# CONFIG_PREEMPT_TRACER is not set
818# CONFIG_SCHED_TRACER is not set
819# CONFIG_CONTEXT_SWITCH_TRACER is not set
820# CONFIG_BOOT_TRACER is not set
821# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
822# CONFIG_SAMPLES is not set
823CONFIG_HAVE_ARCH_KGDB=y
824# CONFIG_KGDB is not set
825CONFIG_CMDLINE=""
826# CONFIG_DEBUG_STACK_USAGE is not set
827# CONFIG_RUNTIME_DEBUG is not set
828
829#
830# Security options
831#
832# CONFIG_KEYS is not set
833CONFIG_SECURITY=y
834# CONFIG_SECURITYFS is not set
835CONFIG_SECURITY_NETWORK=y
836# CONFIG_SECURITY_NETWORK_XFRM is not set
837# CONFIG_SECURITY_FILE_CAPABILITIES is not set
838CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
839CONFIG_CRYPTO=y
840
841#
842# Crypto core or helper
843#
844# CONFIG_CRYPTO_FIPS is not set
845CONFIG_CRYPTO_ALGAPI=y
846CONFIG_CRYPTO_AEAD=y
847CONFIG_CRYPTO_BLKCIPHER=y
848CONFIG_CRYPTO_HASH=y
849CONFIG_CRYPTO_RNG=y
850CONFIG_CRYPTO_MANAGER=y
851# CONFIG_CRYPTO_GF128MUL is not set
852# CONFIG_CRYPTO_NULL is not set
853# CONFIG_CRYPTO_CRYPTD is not set
854# CONFIG_CRYPTO_AUTHENC is not set
855# CONFIG_CRYPTO_TEST is not set
856
857#
858# Authenticated Encryption with Associated Data
859#
860# CONFIG_CRYPTO_CCM is not set
861# CONFIG_CRYPTO_GCM is not set
862# CONFIG_CRYPTO_SEQIV is not set
863
864#
865# Block modes
866#
867CONFIG_CRYPTO_CBC=y
868# CONFIG_CRYPTO_CTR is not set
869# CONFIG_CRYPTO_CTS is not set
870# CONFIG_CRYPTO_ECB is not set
871# CONFIG_CRYPTO_LRW is not set
872# CONFIG_CRYPTO_PCBC is not set
873# CONFIG_CRYPTO_XTS is not set
874
875#
876# Hash modes
877#
878CONFIG_CRYPTO_HMAC=y
879# CONFIG_CRYPTO_XCBC is not set
880
881#
882# Digest
883#
884# CONFIG_CRYPTO_CRC32C is not set
885# CONFIG_CRYPTO_MD4 is not set
886CONFIG_CRYPTO_MD5=y
887# CONFIG_CRYPTO_MICHAEL_MIC is not set
888# CONFIG_CRYPTO_RMD128 is not set
889# CONFIG_CRYPTO_RMD160 is not set
890# CONFIG_CRYPTO_RMD256 is not set
891# CONFIG_CRYPTO_RMD320 is not set
892# CONFIG_CRYPTO_SHA1 is not set
893# CONFIG_CRYPTO_SHA256 is not set
894# CONFIG_CRYPTO_SHA512 is not set
895# CONFIG_CRYPTO_TGR192 is not set
896# CONFIG_CRYPTO_WP512 is not set
897
898#
899# Ciphers
900#
901# CONFIG_CRYPTO_AES is not set
902# CONFIG_CRYPTO_ANUBIS is not set
903# CONFIG_CRYPTO_ARC4 is not set
904# CONFIG_CRYPTO_BLOWFISH is not set
905# CONFIG_CRYPTO_CAMELLIA is not set
906# CONFIG_CRYPTO_CAST5 is not set
907# CONFIG_CRYPTO_CAST6 is not set
908CONFIG_CRYPTO_DES=y
909# CONFIG_CRYPTO_FCRYPT is not set
910# CONFIG_CRYPTO_KHAZAD is not set
911# CONFIG_CRYPTO_SALSA20 is not set
912# CONFIG_CRYPTO_SEED is not set
913# CONFIG_CRYPTO_SERPENT is not set
914# CONFIG_CRYPTO_TEA is not set
915# CONFIG_CRYPTO_TWOFISH is not set
916
917#
918# Compression
919#
920# CONFIG_CRYPTO_DEFLATE is not set
921# CONFIG_CRYPTO_LZO is not set
922
923#
924# Random Number Generation
925#
926# CONFIG_CRYPTO_ANSI_CPRNG is not set
927CONFIG_CRYPTO_HW=y
928
929#
930# Library routines
931#
932CONFIG_BITREVERSE=y
933# CONFIG_CRC_CCITT is not set
934# CONFIG_CRC16 is not set
935# CONFIG_CRC_T10DIF is not set
936# CONFIG_CRC_ITU_T is not set
937CONFIG_CRC32=y
938# CONFIG_CRC7 is not set
939# CONFIG_LIBCRC32C is not set
940CONFIG_PLIST=y
941CONFIG_HAS_IOMEM=y
942CONFIG_HAS_IOPORT=y
943CONFIG_HAS_DMA=y
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 12d12dfe73c0..a0d14f85b781 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -38,6 +38,9 @@
38#ifndef cpu_has_tx39_cache 38#ifndef cpu_has_tx39_cache
39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40#endif 40#endif
41#ifndef cpu_has_octeon_cache
42#define cpu_has_octeon_cache 0
43#endif
41#ifndef cpu_has_fpu 44#ifndef cpu_has_fpu
42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 45#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 46#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 229a786101d9..c018727c7ddc 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -33,6 +33,7 @@
33#define PRID_COMP_TOSHIBA 0x070000 33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000 34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000 35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_CAVIUM 0x0d0000
36 37
37 38
38/* 39/*
@@ -114,6 +115,18 @@
114#define PRID_IMP_BCM3302 0x9000 115#define PRID_IMP_BCM3302 0x9000
115 116
116/* 117/*
118 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
119 */
120
121#define PRID_IMP_CAVIUM_CN38XX 0x0000
122#define PRID_IMP_CAVIUM_CN31XX 0x0100
123#define PRID_IMP_CAVIUM_CN30XX 0x0200
124#define PRID_IMP_CAVIUM_CN58XX 0x0300
125#define PRID_IMP_CAVIUM_CN56XX 0x0400
126#define PRID_IMP_CAVIUM_CN50XX 0x0600
127#define PRID_IMP_CAVIUM_CN52XX 0x0700
128
129/*
117 * Definitions for 7:0 on legacy processors 130 * Definitions for 7:0 on legacy processors
118 */ 131 */
119 132
@@ -203,6 +216,7 @@ enum cpu_type_enum {
203 * MIPS64 class processors 216 * MIPS64 class processors
204 */ 217 */
205 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 218 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
219 CPU_CAVIUM_OCTEON,
206 220
207 CPU_LAST 221 CPU_LAST
208}; 222};
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 2de638f84c86..43baed16a109 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -42,7 +42,7 @@ ASMMACRO(_ehb,
42/* 42/*
43 * TLB hazards 43 * TLB hazards
44 */ 44 */
45#if defined(CONFIG_CPU_MIPSR2) 45#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
46 46
47/* 47/*
48 * MIPSR2 defines ehb for hazard avoidance 48 * MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do { \
138 __instruction_hazard(); \ 138 __instruction_hazard(); \
139} while (0) 139} while (0)
140 140
141#elif defined(CONFIG_CPU_R10000) 141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
142 142
143/* 143/*
144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 501a40b9f18d..436878e4e063 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr)
295#undef __IS_KSEG1 295#undef __IS_KSEG1
296} 296}
297 297
298#ifdef CONFIG_CPU_CAVIUM_OCTEON
299#define war_octeon_io_reorder_wmb() wmb()
300#else
301#define war_octeon_io_reorder_wmb() do { } while (0)
302#endif
303
298#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 304#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
299 \ 305 \
300static inline void pfx##write##bwlq(type val, \ 306static inline void pfx##write##bwlq(type val, \
@@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \
303 volatile type *__mem; \ 309 volatile type *__mem; \
304 type __val; \ 310 type __val; \
305 \ 311 \
312 war_octeon_io_reorder_wmb(); \
313 \
306 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 314 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
307 \ 315 \
308 __val = pfx##ioswab##bwlq(__mem, val); \ 316 __val = pfx##ioswab##bwlq(__mem, val); \
@@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
370 volatile type *__addr; \ 378 volatile type *__addr; \
371 type __val; \ 379 type __val; \
372 \ 380 \
381 war_octeon_io_reorder_wmb(); \
382 \
373 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 383 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
374 \ 384 \
375 __val = pfx##ioswab##bwlq(__addr, val); \ 385 __val = pfx##ioswab##bwlq(__addr, val); \
@@ -504,8 +514,12 @@ BUILDSTRING(q, u64)
504#endif 514#endif
505 515
506 516
517#ifdef CONFIG_CPU_CAVIUM_OCTEON
518#define mmiowb() wmb()
519#else
507/* Depends on MIPS II instruction set */ 520/* Depends on MIPS II instruction set */
508#define mmiowb() asm volatile ("sync" ::: "memory") 521#define mmiowb() asm volatile ("sync" ::: "memory")
522#endif
509 523
510static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 524static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
511{ 525{
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 0d302bad4492..62f91f50b5b5 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -91,14 +91,57 @@ static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg; 91 return *(volatile u32 *)reg;
92} 92}
93 93
94/* Early Au1000 have a write-only SYS_CPUPLL register. */
95static inline int au1xxx_cpu_has_pll_wo(void)
96{
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
101 return 1;
102 }
103 return 0;
104}
105
106/* does CPU need CONFIG[OD] set to fix tons of errata? */
107static inline int au1xxx_cpu_needs_config_od(void)
108{
109 /*
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
113 */
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
119 /*
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
123 */
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
128 return 1;
129 }
130 return 0;
131}
94 132
95/* arch/mips/au1000/common/clocks.c */ 133/* arch/mips/au1000/common/clocks.c */
96extern void set_au1x00_speed(unsigned int new_freq); 134extern void set_au1x00_speed(unsigned int new_freq);
97extern unsigned int get_au1x00_speed(void); 135extern unsigned int get_au1x00_speed(void);
98extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 136extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
99extern unsigned long get_au1x00_uart_baud_base(void); 137extern unsigned long get_au1x00_uart_baud_base(void);
100extern void set_au1x00_lcd_clock(void); 138extern unsigned long au1xxx_calc_clock(void);
101extern unsigned int get_au1x00_lcd_clock(void); 139
140/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
141void au1xxx_save_and_sleep(void);
142void au_sleep(void);
143void save_au1xxx_intctl(void);
144void restore_au1xxx_intctl(void);
102 145
103/* 146/*
104 * Every board describes its IRQ mapping with this table. 147 * Every board describes its IRQ mapping with this table.
@@ -109,10 +152,11 @@ struct au1xxx_irqmap {
109 int im_request; 152 int im_request;
110}; 153};
111 154
112/* 155/* core calls this function to let boards initialize other IRQ sources */
113 * init_IRQ looks for a table with this name. 156void board_init_irq(void);
114 */ 157
115extern struct au1xxx_irqmap au1xxx_irq_map[]; 158/* boards call this to register additional (GPIO) interrupts */
159void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
116 160
117#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 161#endif /* !defined (_LANGUAGE_ASSEMBLY) */
118 162
@@ -505,15 +549,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
505 549
506#define IC1_TESTBIT 0xB1800080 550#define IC1_TESTBIT 0xB1800080
507 551
508/* Interrupt Configuration Modes */
509#define INTC_INT_DISABLED 0x0
510#define INTC_INT_RISE_EDGE 0x1
511#define INTC_INT_FALL_EDGE 0x2
512#define INTC_INT_RISE_AND_FALL_EDGE 0x3
513#define INTC_INT_HIGH_LEVEL 0x5
514#define INTC_INT_LOW_LEVEL 0x6
515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
516
517/* Interrupt Numbers */ 552/* Interrupt Numbers */
518/* Au1000 */ 553/* Au1000 */
519#ifdef CONFIG_SOC_AU1000 554#ifdef CONFIG_SOC_AU1000
@@ -1525,6 +1560,10 @@ enum soc_au1200_ints {
1525#define SYS_SLPPWR 0xB1900078 1560#define SYS_SLPPWR 0xB1900078
1526#define SYS_SLEEP 0xB190007C 1561#define SYS_SLEEP 0xB190007C
1527 1562
1563#define SYS_WAKEMSK_D2 (1 << 9)
1564#define SYS_WAKEMSK_M2 (1 << 8)
1565#define SYS_WAKEMSK_GPIO(x) (1 << (x))
1566
1528/* Clock Controller */ 1567/* Clock Controller */
1529#define SYS_FREQCTRL0 0xB1900020 1568#define SYS_FREQCTRL0 0xB1900020
1530# define SYS_FC_FRDIV2_BIT 22 1569# define SYS_FC_FRDIV2_BIT 22
@@ -1749,24 +1788,4 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1749 1788
1750#endif 1789#endif
1751 1790
1752/*
1753 * Processor information based on PRID.
1754 * Copied from PowerPC.
1755 */
1756#ifndef _LANGUAGE_ASSEMBLY
1757struct cpu_spec {
1758 /* CPU is matched via (PRID & prid_mask) == prid_value */
1759 unsigned int prid_mask;
1760 unsigned int prid_value;
1761
1762 char *cpu_name;
1763 unsigned char cpu_od; /* Set Config[OD] */
1764 unsigned char cpu_bclk; /* Enable BCLK switching */
1765 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
1766};
1767
1768extern struct cpu_spec cpu_specs[];
1769extern struct cpu_spec *cur_cpu_spec[];
1770#endif
1771
1772#endif 1791#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 44a67bf05dc1..06f68f43800a 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -357,6 +357,11 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); 357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
358extern void au1xxx_ddma_del_device(u32 devid); 358extern void au1xxx_ddma_del_device(u32 devid);
359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); 359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
360#ifdef CONFIG_PM
361void au1xxx_dbdma_suspend(void);
362void au1xxx_dbdma_resume(void);
363#endif
364
360 365
361/* 366/*
362 * Some compatibilty macros -- needed to make changes to API 367 * Some compatibilty macros -- needed to make changes to API
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
new file mode 100644
index 000000000000..04ce6e6569da
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -0,0 +1,78 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Cavium Networks
7 */
8#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
10
11#include <linux/types.h>
12#include <asm/mipsregs.h>
13
14/*
15 * Cavium Octeons are MIPS64v2 processors
16 */
17#define cpu_dcache_line_size() 128
18#define cpu_icache_line_size() 128
19
20
21#define cpu_has_4kex 1
22#define cpu_has_3k_cache 0
23#define cpu_has_4k_cache 0
24#define cpu_has_tx39_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_counter 1
27#define cpu_has_watch 1
28#define cpu_has_divec 1
29#define cpu_has_vce 0
30#define cpu_has_cache_cdex_p 0
31#define cpu_has_cache_cdex_s 0
32#define cpu_has_prefetch 1
33
34/*
35 * We should disable LL/SC on non SMP systems as it is faster to
36 * disable interrupts for atomic access than a LL/SC. Unfortunatly we
37 * cannot as this breaks asm/futex.h
38 */
39#define cpu_has_llsc 1
40#define cpu_has_vtag_icache 1
41#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0
43#define cpu_has_64bits 1
44#define cpu_has_octeon_cache 1
45#define cpu_has_saa octeon_has_saa()
46#define cpu_has_mips32r1 0
47#define cpu_has_mips32r2 0
48#define cpu_has_mips64r1 0
49#define cpu_has_mips64r2 1
50#define cpu_has_dsp 0
51#define cpu_has_mipsmt 0
52#define cpu_has_userlocal 0
53#define cpu_has_vint 0
54#define cpu_has_veic 0
55#define ARCH_HAS_READ_CURRENT_TIMER 1
56#define ARCH_HAS_IRQ_PER_CPU 1
57#define ARCH_HAS_SPINLOCK_PREFETCH 1
58#define spin_lock_prefetch(x) prefetch(x)
59#define PREFETCH_STRIDE 128
60
61static inline int read_current_timer(unsigned long *result)
62{
63 asm volatile ("rdhwr %0,$31\n"
64#ifndef CONFIG_64BIT
65 "\tsll %0, 0"
66#endif
67 : "=r" (*result));
68 return 0;
69}
70
71static inline int octeon_has_saa(void)
72{
73 int id;
74 asm volatile ("mfc0 %0, $15,0" : "=r" (id));
75 return id >= 0x000d0300;
76}
77
78#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
new file mode 100644
index 000000000000..f30fce92aabb
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -0,0 +1,64 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 *
8 *
9 * Similar to mach-generic/dma-coherence.h except
10 * plat_device_is_coherent hard coded to return 1.
11 *
12 */
13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
15
16struct device;
17
18dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
19void octeon_unmap_dma_mem(struct device *, dma_addr_t);
20
21static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
22 size_t size)
23{
24 return octeon_map_dma_mem(dev, addr, size);
25}
26
27static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
28 struct page *page)
29{
30 return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
31}
32
33static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
34{
35 return dma_addr;
36}
37
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
39{
40 octeon_unmap_dma_mem(dev, dma_addr);
41}
42
43static inline int plat_dma_supported(struct device *dev, u64 mask)
44{
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 mb();
51}
52
53static inline int plat_device_is_coherent(struct device *dev)
54{
55 return 1;
56}
57
58static inline int plat_dma_mapping_error(struct device *dev,
59 dma_addr_t dma_addr)
60{
61 return dma_addr == -1;
62}
63
64#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
new file mode 100644
index 000000000000..d32220fbf4f1
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -0,0 +1,244 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __OCTEON_IRQ_H__
9#define __OCTEON_IRQ_H__
10
11#define NR_IRQS OCTEON_IRQ_LAST
12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13
14/* 0 - 7 represent the i8259 master */
15#define OCTEON_IRQ_I8259M0 0
16#define OCTEON_IRQ_I8259M1 1
17#define OCTEON_IRQ_I8259M2 2
18#define OCTEON_IRQ_I8259M3 3
19#define OCTEON_IRQ_I8259M4 4
20#define OCTEON_IRQ_I8259M5 5
21#define OCTEON_IRQ_I8259M6 6
22#define OCTEON_IRQ_I8259M7 7
23/* 8 - 15 represent the i8259 slave */
24#define OCTEON_IRQ_I8259S0 8
25#define OCTEON_IRQ_I8259S1 9
26#define OCTEON_IRQ_I8259S2 10
27#define OCTEON_IRQ_I8259S3 11
28#define OCTEON_IRQ_I8259S4 12
29#define OCTEON_IRQ_I8259S5 13
30#define OCTEON_IRQ_I8259S6 14
31#define OCTEON_IRQ_I8259S7 15
32/* 16 - 23 represent the 8 MIPS standard interrupt sources */
33#define OCTEON_IRQ_SW0 16
34#define OCTEON_IRQ_SW1 17
35#define OCTEON_IRQ_CIU0 18
36#define OCTEON_IRQ_CIU1 19
37#define OCTEON_IRQ_CIU4 20
38#define OCTEON_IRQ_5 21
39#define OCTEON_IRQ_PERF 22
40#define OCTEON_IRQ_TIMER 23
41/* 24 - 87 represent the sources in CIU_INTX_EN0 */
42#define OCTEON_IRQ_WORKQ0 24
43#define OCTEON_IRQ_WORKQ1 25
44#define OCTEON_IRQ_WORKQ2 26
45#define OCTEON_IRQ_WORKQ3 27
46#define OCTEON_IRQ_WORKQ4 28
47#define OCTEON_IRQ_WORKQ5 29
48#define OCTEON_IRQ_WORKQ6 30
49#define OCTEON_IRQ_WORKQ7 31
50#define OCTEON_IRQ_WORKQ8 32
51#define OCTEON_IRQ_WORKQ9 33
52#define OCTEON_IRQ_WORKQ10 34
53#define OCTEON_IRQ_WORKQ11 35
54#define OCTEON_IRQ_WORKQ12 36
55#define OCTEON_IRQ_WORKQ13 37
56#define OCTEON_IRQ_WORKQ14 38
57#define OCTEON_IRQ_WORKQ15 39
58#define OCTEON_IRQ_GPIO0 40
59#define OCTEON_IRQ_GPIO1 41
60#define OCTEON_IRQ_GPIO2 42
61#define OCTEON_IRQ_GPIO3 43
62#define OCTEON_IRQ_GPIO4 44
63#define OCTEON_IRQ_GPIO5 45
64#define OCTEON_IRQ_GPIO6 46
65#define OCTEON_IRQ_GPIO7 47
66#define OCTEON_IRQ_GPIO8 48
67#define OCTEON_IRQ_GPIO9 49
68#define OCTEON_IRQ_GPIO10 50
69#define OCTEON_IRQ_GPIO11 51
70#define OCTEON_IRQ_GPIO12 52
71#define OCTEON_IRQ_GPIO13 53
72#define OCTEON_IRQ_GPIO14 54
73#define OCTEON_IRQ_GPIO15 55
74#define OCTEON_IRQ_MBOX0 56
75#define OCTEON_IRQ_MBOX1 57
76#define OCTEON_IRQ_UART0 58
77#define OCTEON_IRQ_UART1 59
78#define OCTEON_IRQ_PCI_INT0 60
79#define OCTEON_IRQ_PCI_INT1 61
80#define OCTEON_IRQ_PCI_INT2 62
81#define OCTEON_IRQ_PCI_INT3 63
82#define OCTEON_IRQ_PCI_MSI0 64
83#define OCTEON_IRQ_PCI_MSI1 65
84#define OCTEON_IRQ_PCI_MSI2 66
85#define OCTEON_IRQ_PCI_MSI3 67
86#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */
87#define OCTEON_IRQ_TWSI 69
88#define OCTEON_IRQ_RML 70
89#define OCTEON_IRQ_TRACE 71
90#define OCTEON_IRQ_GMX_DRP0 72
91#define OCTEON_IRQ_GMX_DRP1 73
92#define OCTEON_IRQ_IPD_DRP 74
93#define OCTEON_IRQ_KEY_ZERO 75
94#define OCTEON_IRQ_TIMER0 76
95#define OCTEON_IRQ_TIMER1 77
96#define OCTEON_IRQ_TIMER2 78
97#define OCTEON_IRQ_TIMER3 79
98#define OCTEON_IRQ_USB0 80
99#define OCTEON_IRQ_PCM 81
100#define OCTEON_IRQ_MPI 82
101#define OCTEON_IRQ_TWSI2 83
102#define OCTEON_IRQ_POWIQ 84
103#define OCTEON_IRQ_IPDPPTHR 85
104#define OCTEON_IRQ_MII0 86
105#define OCTEON_IRQ_BOOTDMA 87
106/* 88 - 151 represent the sources in CIU_INTX_EN1 */
107#define OCTEON_IRQ_WDOG0 88
108#define OCTEON_IRQ_WDOG1 89
109#define OCTEON_IRQ_WDOG2 90
110#define OCTEON_IRQ_WDOG3 91
111#define OCTEON_IRQ_WDOG4 92
112#define OCTEON_IRQ_WDOG5 93
113#define OCTEON_IRQ_WDOG6 94
114#define OCTEON_IRQ_WDOG7 95
115#define OCTEON_IRQ_WDOG8 96
116#define OCTEON_IRQ_WDOG9 97
117#define OCTEON_IRQ_WDOG10 98
118#define OCTEON_IRQ_WDOG11 99
119#define OCTEON_IRQ_WDOG12 100
120#define OCTEON_IRQ_WDOG13 101
121#define OCTEON_IRQ_WDOG14 102
122#define OCTEON_IRQ_WDOG15 103
123#define OCTEON_IRQ_UART2 104
124#define OCTEON_IRQ_USB1 105
125#define OCTEON_IRQ_MII1 106
126#define OCTEON_IRQ_RESERVED107 107
127#define OCTEON_IRQ_RESERVED108 108
128#define OCTEON_IRQ_RESERVED109 109
129#define OCTEON_IRQ_RESERVED110 110
130#define OCTEON_IRQ_RESERVED111 111
131#define OCTEON_IRQ_RESERVED112 112
132#define OCTEON_IRQ_RESERVED113 113
133#define OCTEON_IRQ_RESERVED114 114
134#define OCTEON_IRQ_RESERVED115 115
135#define OCTEON_IRQ_RESERVED116 116
136#define OCTEON_IRQ_RESERVED117 117
137#define OCTEON_IRQ_RESERVED118 118
138#define OCTEON_IRQ_RESERVED119 119
139#define OCTEON_IRQ_RESERVED120 120
140#define OCTEON_IRQ_RESERVED121 121
141#define OCTEON_IRQ_RESERVED122 122
142#define OCTEON_IRQ_RESERVED123 123
143#define OCTEON_IRQ_RESERVED124 124
144#define OCTEON_IRQ_RESERVED125 125
145#define OCTEON_IRQ_RESERVED126 126
146#define OCTEON_IRQ_RESERVED127 127
147#define OCTEON_IRQ_RESERVED128 128
148#define OCTEON_IRQ_RESERVED129 129
149#define OCTEON_IRQ_RESERVED130 130
150#define OCTEON_IRQ_RESERVED131 131
151#define OCTEON_IRQ_RESERVED132 132
152#define OCTEON_IRQ_RESERVED133 133
153#define OCTEON_IRQ_RESERVED134 134
154#define OCTEON_IRQ_RESERVED135 135
155#define OCTEON_IRQ_RESERVED136 136
156#define OCTEON_IRQ_RESERVED137 137
157#define OCTEON_IRQ_RESERVED138 138
158#define OCTEON_IRQ_RESERVED139 139
159#define OCTEON_IRQ_RESERVED140 140
160#define OCTEON_IRQ_RESERVED141 141
161#define OCTEON_IRQ_RESERVED142 142
162#define OCTEON_IRQ_RESERVED143 143
163#define OCTEON_IRQ_RESERVED144 144
164#define OCTEON_IRQ_RESERVED145 145
165#define OCTEON_IRQ_RESERVED146 146
166#define OCTEON_IRQ_RESERVED147 147
167#define OCTEON_IRQ_RESERVED148 148
168#define OCTEON_IRQ_RESERVED149 149
169#define OCTEON_IRQ_RESERVED150 150
170#define OCTEON_IRQ_RESERVED151 151
171
172#ifdef CONFIG_PCI_MSI
173/* 152 - 215 represent the MSI interrupts 0-63 */
174#define OCTEON_IRQ_MSI_BIT0 152
175#define OCTEON_IRQ_MSI_BIT1 153
176#define OCTEON_IRQ_MSI_BIT2 154
177#define OCTEON_IRQ_MSI_BIT3 155
178#define OCTEON_IRQ_MSI_BIT4 156
179#define OCTEON_IRQ_MSI_BIT5 157
180#define OCTEON_IRQ_MSI_BIT6 158
181#define OCTEON_IRQ_MSI_BIT7 159
182#define OCTEON_IRQ_MSI_BIT8 160
183#define OCTEON_IRQ_MSI_BIT9 161
184#define OCTEON_IRQ_MSI_BIT10 162
185#define OCTEON_IRQ_MSI_BIT11 163
186#define OCTEON_IRQ_MSI_BIT12 164
187#define OCTEON_IRQ_MSI_BIT13 165
188#define OCTEON_IRQ_MSI_BIT14 166
189#define OCTEON_IRQ_MSI_BIT15 167
190#define OCTEON_IRQ_MSI_BIT16 168
191#define OCTEON_IRQ_MSI_BIT17 169
192#define OCTEON_IRQ_MSI_BIT18 170
193#define OCTEON_IRQ_MSI_BIT19 171
194#define OCTEON_IRQ_MSI_BIT20 172
195#define OCTEON_IRQ_MSI_BIT21 173
196#define OCTEON_IRQ_MSI_BIT22 174
197#define OCTEON_IRQ_MSI_BIT23 175
198#define OCTEON_IRQ_MSI_BIT24 176
199#define OCTEON_IRQ_MSI_BIT25 177
200#define OCTEON_IRQ_MSI_BIT26 178
201#define OCTEON_IRQ_MSI_BIT27 179
202#define OCTEON_IRQ_MSI_BIT28 180
203#define OCTEON_IRQ_MSI_BIT29 181
204#define OCTEON_IRQ_MSI_BIT30 182
205#define OCTEON_IRQ_MSI_BIT31 183
206#define OCTEON_IRQ_MSI_BIT32 184
207#define OCTEON_IRQ_MSI_BIT33 185
208#define OCTEON_IRQ_MSI_BIT34 186
209#define OCTEON_IRQ_MSI_BIT35 187
210#define OCTEON_IRQ_MSI_BIT36 188
211#define OCTEON_IRQ_MSI_BIT37 189
212#define OCTEON_IRQ_MSI_BIT38 190
213#define OCTEON_IRQ_MSI_BIT39 191
214#define OCTEON_IRQ_MSI_BIT40 192
215#define OCTEON_IRQ_MSI_BIT41 193
216#define OCTEON_IRQ_MSI_BIT42 194
217#define OCTEON_IRQ_MSI_BIT43 195
218#define OCTEON_IRQ_MSI_BIT44 196
219#define OCTEON_IRQ_MSI_BIT45 197
220#define OCTEON_IRQ_MSI_BIT46 198
221#define OCTEON_IRQ_MSI_BIT47 199
222#define OCTEON_IRQ_MSI_BIT48 200
223#define OCTEON_IRQ_MSI_BIT49 201
224#define OCTEON_IRQ_MSI_BIT50 202
225#define OCTEON_IRQ_MSI_BIT51 203
226#define OCTEON_IRQ_MSI_BIT52 204
227#define OCTEON_IRQ_MSI_BIT53 205
228#define OCTEON_IRQ_MSI_BIT54 206
229#define OCTEON_IRQ_MSI_BIT55 207
230#define OCTEON_IRQ_MSI_BIT56 208
231#define OCTEON_IRQ_MSI_BIT57 209
232#define OCTEON_IRQ_MSI_BIT58 210
233#define OCTEON_IRQ_MSI_BIT59 211
234#define OCTEON_IRQ_MSI_BIT60 212
235#define OCTEON_IRQ_MSI_BIT61 213
236#define OCTEON_IRQ_MSI_BIT62 214
237#define OCTEON_IRQ_MSI_BIT63 215
238
239#define OCTEON_IRQ_LAST 216
240#else
241#define OCTEON_IRQ_LAST 152
242#endif
243
244#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
new file mode 100644
index 000000000000..0b2b5eb22e9b
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -0,0 +1,131 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2008 Cavium Networks, Inc
7 */
8#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
9#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
10
11
12#define CP0_CYCLE_COUNTER $9, 6
13#define CP0_CVMCTL_REG $9, 7
14#define CP0_CVMMEMCTL_REG $11,7
15#define CP0_PRID_REG $15, 0
16#define CP0_PRID_OCTEON_PASS1 0x000d0000
17#define CP0_PRID_OCTEON_CN30XX 0x000d0200
18
19.macro kernel_entry_setup
20 # Registers set by bootloader:
21 # (only 32 bits set by bootloader, all addresses are physical
22 # addresses, and need to have the appropriate memory region set
23 # by the kernel
24 # a0 = argc
25 # a1 = argv (kseg0 compat addr)
26 # a2 = 1 if init core, zero otherwise
27 # a3 = address of boot descriptor block
28 .set push
29 .set arch=octeon
30 # Read the cavium mem control register
31 dmfc0 v0, CP0_CVMMEMCTL_REG
32 # Clear the lower 6 bits, the CVMSEG size
33 dins v0, $0, 0, 6
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
37#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
38 # Disable unaligned load/store support but leave HW fixup enabled
39 or v0, v0, 0x5001
40 xor v0, v0, 0x1001
41#else
42 # Disable unaligned load/store and HW fixup support
43 or v0, v0, 0x5001
44 xor v0, v0, 0x5001
45#endif
46 # Read the processor ID register
47 mfc0 v1, CP0_PRID_REG
48 # Disable instruction prefetching (Octeon Pass1 errata)
49 or v0, v0, 0x2000
50 # Skip reenable of prefetching for Octeon Pass1
51 beq v1, CP0_PRID_OCTEON_PASS1, skip
52 nop
53 # Reenable instruction prefetching, not on Pass1
54 xor v0, v0, 0x2000
55 # Strip off pass number off of processor id
56 srl v1, 8
57 sll v1, 8
58 # CN30XX needs some extra stuff turned off for better performance
59 bne v1, CP0_PRID_OCTEON_CN30XX, skip
60 nop
61 # CN30XX Use random Icache replacement
62 or v0, v0, 0x400
63 # CN30XX Disable instruction prefetching
64 or v0, v0, 0x2000
65skip:
66 # Write the cavium control register
67 dmtc0 v0, CP0_CVMCTL_REG
68 sync
69 # Flush dcache after config change
70 cache 9, 0($0)
71 # Get my core id
72 rdhwr v0, $0
73 # Jump the master to kernel_entry
74 bne a2, zero, octeon_main_processor
75 nop
76
77#ifdef CONFIG_SMP
78
79 #
80 # All cores other than the master need to wait here for SMP bootstrap
81 # to begin
82 #
83
84 # This is the variable where the next core to boot os stored
85 PTR_LA t0, octeon_processor_boot
86octeon_spin_wait_boot:
87 # Get the core id of the next to be booted
88 LONG_L t1, (t0)
89 # Keep looping if it isn't me
90 bne t1, v0, octeon_spin_wait_boot
91 nop
92 # Get my GP from the global variable
93 PTR_LA t0, octeon_processor_gp
94 LONG_L gp, (t0)
95 # Get my SP from the global variable
96 PTR_LA t0, octeon_processor_sp
97 LONG_L sp, (t0)
98 # Set the SP global variable to zero so the master knows we've started
99 LONG_S zero, (t0)
100#ifdef __OCTEON__
101 syncw
102 syncw
103#else
104 sync
105#endif
106 # Jump to the normal Linux SMP entry point
107 j smp_bootstrap
108 nop
109#else /* CONFIG_SMP */
110
111 #
112 # Someone tried to boot SMP with a non SMP kernel. All extra cores
113 # will halt here.
114 #
115octeon_wait_forever:
116 wait
117 b octeon_wait_forever
118 nop
119
120#endif /* CONFIG_SMP */
121octeon_main_processor:
122 .set pop
123.endm
124
125/*
126 * Do SMP slave processor setup necessary before we can savely execute C code.
127 */
128 .macro smp_slave_setup
129 .endm
130
131#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
new file mode 100644
index 000000000000..c4712d7cc81d
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
8 */
9#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
10#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
11
12#define R4600_V1_INDEX_ICACHEOP_WAR 0
13#define R4600_V1_HIT_CACHEOP_WAR 0
14#define R4600_V2_HIT_CACHEOP_WAR 0
15#define R5432_CP0_INTERRUPT_WAR 0
16#define BCM1250_M3_WAR 0
17#define SIBYTE_1956_WAR 0
18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0
25
26#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 76e04e7feb84..36c611b6c597 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -28,10 +28,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
28 return dma_addr; 28 return dma_addr;
29} 29}
30 30
31static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 31static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
32{ 32{
33} 33}
34 34
35static inline int plat_dma_supported(struct device *dev, u64 mask)
36{
37 /*
38 * we fall back to GFP_DMA when the mask isn't all 1s,
39 * so we can't guarantee allocations that must be
40 * within a tighter range than GFP_DMA..
41 */
42 if (mask < DMA_BIT_MASK(24))
43 return 0;
44
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 return;
51}
52
53static inline int plat_dma_mapping_error(struct device *dev,
54 dma_addr_t dma_addr)
55{
56 return 0;
57}
58
35static inline int plat_device_is_coherent(struct device *dev) 59static inline int plat_device_is_coherent(struct device *dev)
36{ 60{
37#ifdef CONFIG_DMA_COHERENT 61#ifdef CONFIG_DMA_COHERENT
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index ed7e6222dc15..4c21bfca10c3 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -38,10 +38,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
38 return dma_addr & ~(0xffUL << 56); 38 return dma_addr & ~(0xffUL << 56);
39} 39}
40 40
41static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 41static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
42{ 42{
43} 43}
44 44
45static inline int plat_dma_supported(struct device *dev, u64 mask)
46{
47 /*
48 * we fall back to GFP_DMA when the mask isn't all 1s,
49 * so we can't guarantee allocations that must be
50 * within a tighter range than GFP_DMA..
51 */
52 if (mask < DMA_BIT_MASK(24))
53 return 0;
54
55 return 1;
56}
57
58static inline void plat_extra_sync_for_device(struct device *dev)
59{
60 return;
61}
62
63static inline int plat_dma_mapping_error(struct device *dev,
64 dma_addr_t dma_addr)
65{
66 return 0;
67}
68
45static inline int plat_device_is_coherent(struct device *dev) 69static inline int plat_device_is_coherent(struct device *dev)
46{ 70{
47 return 1; /* IP27 non-cohernet mode is unsupported */ 71 return 1; /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index a5511ebb2d53..7ae40f4b1c80 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -60,10 +60,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
60 return addr; 60 return addr;
61} 61}
62 62
63static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 63static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
64{ 64{
65} 65}
66 66
67static inline int plat_dma_supported(struct device *dev, u64 mask)
68{
69 /*
70 * we fall back to GFP_DMA when the mask isn't all 1s,
71 * so we can't guarantee allocations that must be
72 * within a tighter range than GFP_DMA..
73 */
74 if (mask < DMA_BIT_MASK(24))
75 return 0;
76
77 return 1;
78}
79
80static inline void plat_extra_sync_for_device(struct device *dev)
81{
82 return;
83}
84
85static inline int plat_dma_mapping_error(struct device *dev,
86 dma_addr_t dma_addr)
87{
88 return 0;
89}
90
67static inline int plat_device_is_coherent(struct device *dev) 91static inline int plat_device_is_coherent(struct device *dev)
68{ 92{
69 return 0; /* IP32 is non-cohernet */ 93 return 0; /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index d66979a124a8..1c7cd27efa7b 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -27,11 +27,35 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
27 return vdma_log2phys(dma_addr); 27 return vdma_log2phys(dma_addr);
28} 28}
29 29
30static void plat_unmap_dma_mem(dma_addr_t dma_addr) 30static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
31{ 31{
32 vdma_free(dma_addr); 32 vdma_free(dma_addr);
33} 33}
34 34
35static inline int plat_dma_supported(struct device *dev, u64 mask)
36{
37 /*
38 * we fall back to GFP_DMA when the mask isn't all 1s,
39 * so we can't guarantee allocations that must be
40 * within a tighter range than GFP_DMA..
41 */
42 if (mask < DMA_BIT_MASK(24))
43 return 0;
44
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 return;
51}
52
53static inline int plat_dma_mapping_error(struct device *dev,
54 dma_addr_t dma_addr)
55{
56 return 0;
57}
58
35static inline int plat_device_is_coherent(struct device *dev) 59static inline int plat_device_is_coherent(struct device *dev)
36{ 60{
37 return 0; 61 return 0;
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 7e914777ebc4..38fad7dfe7da 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -30,10 +30,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
30 return dma_addr & 0x7fffffff; 30 return dma_addr & 0x7fffffff;
31} 31}
32 32
33static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 33static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
34{ 34{
35} 35}
36 36
37static inline int plat_dma_supported(struct device *dev, u64 mask)
38{
39 /*
40 * we fall back to GFP_DMA when the mask isn't all 1s,
41 * so we can't guarantee allocations that must be
42 * within a tighter range than GFP_DMA..
43 */
44 if (mask < DMA_BIT_MASK(24))
45 return 0;
46
47 return 1;
48}
49
50static inline void plat_extra_sync_for_device(struct device *dev)
51{
52 return;
53}
54
55static inline int plat_dma_mapping_error(struct device *dev,
56 dma_addr_t dma_addr)
57{
58 return 0;
59}
60
37static inline int plat_device_is_coherent(struct device *dev) 61static inline int plat_device_is_coherent(struct device *dev)
38{ 62{
39 return 0; 63 return 0;
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9316324d070d..0417516503f6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1000,6 +1000,26 @@ do { \
1000#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1000#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1001#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1001#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1002 1002
1003
1004/* Cavium OCTEON (cnMIPS) */
1005#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1006#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1007
1008#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1009#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1010
1011#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1012#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1013/*
1014 * The cacheerr registers are not standardized. On OCTEON, they are
1015 * 64 bits wide.
1016 */
1017#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1018#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1019
1020#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1021#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1022
1003/* 1023/*
1004 * Macros to access the floating point coprocessor control registers 1024 * Macros to access the floating point coprocessor control registers
1005 */ 1025 */
@@ -1008,6 +1028,8 @@ do { \
1008 __asm__ __volatile__( \ 1028 __asm__ __volatile__( \
1009 ".set\tpush\n\t" \ 1029 ".set\tpush\n\t" \
1010 ".set\treorder\n\t" \ 1030 ".set\treorder\n\t" \
1031 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1032 ".set\tmips1\n\t" \
1011 "cfc1\t%0,"STR(source)"\n\t" \ 1033 "cfc1\t%0,"STR(source)"\n\t" \
1012 ".set\tpop" \ 1034 ".set\tpop" \
1013 : "=r" (__res)); \ 1035 : "=r" (__res)); \
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index e2e09b2cd265..d94085a3eafb 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -116,6 +116,8 @@ search_module_dbetables(unsigned long addr)
116#define MODULE_PROC_FAMILY "SB1 " 116#define MODULE_PROC_FAMILY "SB1 "
117#elif defined CONFIG_CPU_LOONGSON2 117#elif defined CONFIG_CPU_LOONGSON2
118#define MODULE_PROC_FAMILY "LOONGSON2 " 118#define MODULE_PROC_FAMILY "LOONGSON2 "
119#elif defined CONFIG_CPU_CAVIUM_OCTEON
120#define MODULE_PROC_FAMILY "OCTEON "
119#else 121#else
120#error MODULE_PROC_FAMILY undefined for your processor configuration 122#error MODULE_PROC_FAMILY undefined for your processor configuration
121#endif 123#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
new file mode 100644
index 000000000000..b21d3fc1ef91
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -0,0 +1,128 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * This is file defines ASM primitives for the executive.
31 */
32#ifndef __CVMX_ASM_H__
33#define __CVMX_ASM_H__
34
35#include "octeon-model.h"
36
37/* other useful stuff */
38#define CVMX_SYNC asm volatile ("sync" : : : "memory")
39/* String version of SYNCW macro for using in inline asm constructs */
40#define CVMX_SYNCW_STR "syncw\nsyncw\n"
41#ifdef __OCTEON__
42
43/* Deprecated, will be removed in future release */
44#define CVMX_SYNCIO asm volatile ("nop")
45
46#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory")
47
48/* Deprecated, will be removed in future release */
49#define CVMX_SYNCIOALL asm volatile ("nop")
50
51/*
52 * We actually use two syncw instructions in a row when we need a write
53 * memory barrier. This is because the CN3XXX series of Octeons have
54 * errata Core-401. This can cause a single syncw to not enforce
55 * ordering under very rare conditions. Even if it is rare, better safe
56 * than sorry.
57 */
58#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory")
59
60/*
61 * Define new sync instructions to be normal SYNC instructions for
62 * operating systems that use threads.
63 */
64#define CVMX_SYNCWS CVMX_SYNCW
65#define CVMX_SYNCS CVMX_SYNC
66#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
67#else
68/*
69 * Not using a Cavium compiler, always use the slower sync so the
70 * assembler stays happy.
71 */
72/* Deprecated, will be removed in future release */
73#define CVMX_SYNCIO asm volatile ("nop")
74
75#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory")
76
77/* Deprecated, will be removed in future release */
78#define CVMX_SYNCIOALL asm volatile ("nop")
79
80#define CVMX_SYNCW asm volatile ("sync" : : : "memory")
81#define CVMX_SYNCWS CVMX_SYNCW
82#define CVMX_SYNCS CVMX_SYNC
83#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
84#endif
85
86/*
87 * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
88 * (actually old value or zero) until that byte is stored to (by this or
89 * another processor. Note that the value of each byte is not only
90 * unpredictable, but may also change again - up until the point when one
91 * of the cores stores to the byte.
92 */
93#define CVMX_PREPARE_FOR_STORE(address, offset) \
94 asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
95 [rbase] "d" (address))
96/*
97 * This is a command headed to the L2 controller to tell it to clear
98 * its dirty bit for a block. Basically, SW is telling HW that the
99 * current version of the block will not be used.
100 */
101#define CVMX_DONT_WRITE_BACK(address, offset) \
102 asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
103 [rbase] "d" (address))
104
105/* flush stores, invalidate entire icache */
106#define CVMX_ICACHE_INVALIDATE \
107 { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }
108
109/* flush stores, invalidate entire icache */
110#define CVMX_ICACHE_INVALIDATE2 \
111 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); }
112
113/* complete prefetches, invalidate entire dcache */
114#define CVMX_DCACHE_INVALIDATE \
115 { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
116
117
118#define CVMX_POP(result, input) \
119 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
120#define CVMX_DPOP(result, input) \
121 asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
122
123/* some new cop0-like stuff */
124#define CVMX_RDHWR(result, regstr) \
125 asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
126#define CVMX_RDHWRNV(result, regstr) \
127 asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
128#endif /* __CVMX_ASM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
new file mode 100644
index 000000000000..692989acd8a9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -0,0 +1,262 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Header file containing the ABI with the bootloader.
30 */
31
32#ifndef __CVMX_BOOTINFO_H__
33#define __CVMX_BOOTINFO_H__
34
35/*
36 * Current major and minor versions of the CVMX bootinfo block that is
37 * passed from the bootloader to the application. This is versioned
38 * so that applications can properly handle multiple bootloader
39 * versions.
40 */
41#define CVMX_BOOTINFO_MAJ_VER 1
42#define CVMX_BOOTINFO_MIN_VER 2
43
44#if (CVMX_BOOTINFO_MAJ_VER == 1)
45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
46/*
47 * This structure is populated by the bootloader. For binary
48 * compatibility the only changes that should be made are
49 * adding members to the end of the structure, and the minor
50 * version should be incremented at that time.
51 * If an incompatible change is made, the major version
52 * must be incremented, and the minor version should be reset
53 * to 0.
54 */
55struct cvmx_bootinfo {
56 uint32_t major_version;
57 uint32_t minor_version;
58
59 uint64_t stack_top;
60 uint64_t heap_base;
61 uint64_t heap_end;
62 uint64_t desc_vaddr;
63
64 uint32_t exception_base_addr;
65 uint32_t stack_size;
66 uint32_t flags;
67 uint32_t core_mask;
68 /* DRAM size in megabytes */
69 uint32_t dram_size;
70 /* physical address of free memory descriptor block*/
71 uint32_t phy_mem_desc_addr;
72 /* used to pass flags from app to debugger */
73 uint32_t debugger_flags_base_addr;
74
75 /* CPU clock speed, in hz */
76 uint32_t eclock_hz;
77
78 /* DRAM clock speed, in hz */
79 uint32_t dclock_hz;
80
81 uint32_t reserved0;
82 uint16_t board_type;
83 uint8_t board_rev_major;
84 uint8_t board_rev_minor;
85 uint16_t reserved1;
86 uint8_t reserved2;
87 uint8_t reserved3;
88 char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
89 uint8_t mac_addr_base[6];
90 uint8_t mac_addr_count;
91#if (CVMX_BOOTINFO_MIN_VER >= 1)
92 /*
93 * Several boards support compact flash on the Octeon boot
94 * bus. The CF memory spaces may be mapped to different
95 * addresses on different boards. These are the physical
96 * addresses, so care must be taken to use the correct
97 * XKPHYS/KSEG0 addressing depending on the application's
98 * ABI. These values will be 0 if CF is not present.
99 */
100 uint64_t compact_flash_common_base_addr;
101 uint64_t compact_flash_attribute_base_addr;
102 /*
103 * Base address of the LED display (as on EBT3000 board)
104 * This will be 0 if LED display not present.
105 */
106 uint64_t led_display_base_addr;
107#endif
108#if (CVMX_BOOTINFO_MIN_VER >= 2)
109 /* DFA reference clock in hz (if applicable)*/
110 uint32_t dfa_ref_clock_hz;
111
112 /*
113 * flags indicating various configuration options. These
114 * flags supercede the 'flags' variable and should be used
115 * instead if available.
116 */
117 uint32_t config_flags;
118#endif
119
120};
121
122#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
123#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1)
124#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2)
125#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3)
126/* This flag is set if the TLB mappings are not contained in the
127 * 0x10000000 - 0x20000000 boot bus region. */
128#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4)
129#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5)
130
131#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
132
133/* Type defines for board and chip types */
134enum cvmx_board_types_enum {
135 CVMX_BOARD_TYPE_NULL = 0,
136 CVMX_BOARD_TYPE_SIM = 1,
137 CVMX_BOARD_TYPE_EBT3000 = 2,
138 CVMX_BOARD_TYPE_KODAMA = 3,
139 CVMX_BOARD_TYPE_NIAGARA = 4,
140 CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
141 CVMX_BOARD_TYPE_THUNDER = 6,
142 CVMX_BOARD_TYPE_TRANTOR = 7,
143 CVMX_BOARD_TYPE_EBH3000 = 8,
144 CVMX_BOARD_TYPE_EBH3100 = 9,
145 CVMX_BOARD_TYPE_HIKARI = 10,
146 CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
147 CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
148 CVMX_BOARD_TYPE_KBP = 13,
149 /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
150 CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
151 CVMX_BOARD_TYPE_EBT5800 = 15,
152 CVMX_BOARD_TYPE_NICPRO2 = 16,
153 CVMX_BOARD_TYPE_EBH5600 = 17,
154 CVMX_BOARD_TYPE_EBH5601 = 18,
155 CVMX_BOARD_TYPE_EBH5200 = 19,
156 CVMX_BOARD_TYPE_BBGW_REF = 20,
157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
158 CVMX_BOARD_TYPE_EBT5600 = 22,
159 CVMX_BOARD_TYPE_EBH5201 = 23,
160 CVMX_BOARD_TYPE_MAX,
161
162 /*
163 * The range from CVMX_BOARD_TYPE_MAX to
164 * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
165 * SDK use.
166 */
167
168 /*
169 * Set aside a range for customer boards. These numbers are managed
170 * by Cavium.
171 */
172 CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
173 CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
174 CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
175 CVMX_BOARD_TYPE_CUST_NB5 = 10003,
176 CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
177 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
178
179 /*
180 * Set aside a range for customer private use. The SDK won't
181 * use any numbers in this range.
182 */
183 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
184 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
185
186 /* The remaining range is reserved for future use. */
187};
188
189enum cvmx_chip_types_enum {
190 CVMX_CHIP_TYPE_NULL = 0,
191 CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
192 CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
193 CVMX_CHIP_TYPE_MAX,
194};
195
196/* Compatability alias for NAC38 name change, planned to be removed
197 * from SDK 1.7 */
198#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38
199
200/* Functions to return string based on type */
201#define ENUM_BRD_TYPE_CASE(x) \
202 case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */
203static inline const char *cvmx_board_type_to_string(enum
204 cvmx_board_types_enum type)
205{
206 switch (type) {
207 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL)
208 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM)
209 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000)
210 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA)
211 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA)
212 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38)
213 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER)
214 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR)
215 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000)
216 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100)
217 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI)
218 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5)
219 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5)
220 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP)
221 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5)
222 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800)
223 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2)
224 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600)
225 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601)
226 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200)
227 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF)
228 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
229 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
230 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
231 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
232
233 /* Customer boards listed here */
234 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN)
235 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16)
236 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
237 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
238 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
239 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
240
241 /* Customer private range */
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
244 }
245 return "Unsupported Board";
246}
247
248#define ENUM_CHIP_TYPE_CASE(x) \
249 case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */
250static inline const char *cvmx_chip_type_to_string(enum
251 cvmx_chip_types_enum type)
252{
253 switch (type) {
254 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
255 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
256 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
257 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
258 }
259 return "Unsupported Chip";
260}
261
262#endif /* __CVMX_BOOTINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
new file mode 100644
index 000000000000..1cbe4b55889d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -0,0 +1,288 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Simple allocate only memory allocator. Used to allocate memory at
30 * application start time.
31 */
32
33#ifndef __CVMX_BOOTMEM_H__
34#define __CVMX_BOOTMEM_H__
35/* Must be multiple of 8, changing breaks ABI */
36#define CVMX_BOOTMEM_NAME_LEN 128
37
38/* Can change without breaking ABI */
39#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
40
41/* minimum alignment of bootmem alloced blocks */
42#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull)
43
44/* Flags for cvmx_bootmem_phy_mem* functions */
45/* Allocate from end of block instead of beginning */
46#define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0)
47
48/* Don't do any locking. */
49#define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1)
50
51/* First bytes of each free physical block of memory contain this structure,
52 * which is used to maintain the free memory list. Since the bootloader is
53 * only 32 bits, there is a union providing 64 and 32 bit versions. The
54 * application init code converts addresses to 64 bit addresses before the
55 * application starts.
56 */
57struct cvmx_bootmem_block_header {
58 /*
59 * Note: these are referenced from assembly routines in the
60 * bootloader, so this structure should not be changed
61 * without changing those routines as well.
62 */
63 uint64_t next_block_addr;
64 uint64_t size;
65
66};
67
68/*
69 * Structure for named memory blocks. Number of descriptors available
70 * can be changed without affecting compatiblity, but name length
71 * changes require a bump in the bootmem descriptor version Note: This
72 * structure must be naturally 64 bit aligned, as a single memory
73 * image will be used by both 32 and 64 bit programs.
74 */
75struct cvmx_bootmem_named_block_desc {
76 /* Base address of named block */
77 uint64_t base_addr;
78 /*
79 * Size actually allocated for named block (may differ from
80 * requested).
81 */
82 uint64_t size;
83 /* name of named block */
84 char name[CVMX_BOOTMEM_NAME_LEN];
85};
86
87/* Current descriptor versions */
88/* CVMX bootmem descriptor major version */
89#define CVMX_BOOTMEM_DESC_MAJ_VER 3
90
91/* CVMX bootmem descriptor minor version */
92#define CVMX_BOOTMEM_DESC_MIN_VER 0
93
94/* First three members of cvmx_bootmem_desc_t are left in original
95 * positions for backwards compatibility.
96 */
97struct cvmx_bootmem_desc {
98 /* spinlock to control access to list */
99 uint32_t lock;
100 /* flags for indicating various conditions */
101 uint32_t flags;
102 uint64_t head_addr;
103
104 /* Incremented when incompatible changes made */
105 uint32_t major_version;
106
107 /*
108 * Incremented changed when compatible changes made, reset to
109 * zero when major incremented.
110 */
111 uint32_t minor_version;
112
113 uint64_t app_data_addr;
114 uint64_t app_data_size;
115
116 /* number of elements in named blocks array */
117 uint32_t named_block_num_blocks;
118
119 /* length of name array in bootmem blocks */
120 uint32_t named_block_name_len;
121 /* address of named memory block descriptors */
122 uint64_t named_block_array_addr;
123
124};
125
126/**
127 * Initialize the boot alloc memory structures. This is
128 * normally called inside of cvmx_user_app_init()
129 *
130 * @mem_desc_ptr: Address of the free memory list
131 */
132extern int cvmx_bootmem_init(void *mem_desc_ptr);
133
134/**
135 * Allocate a block of memory from the free list that was passed
136 * to the application by the bootloader.
137 * This is an allocate-only algorithm, so freeing memory is not possible.
138 *
139 * @size: Size in bytes of block to allocate
140 * @alignment: Alignment required - must be power of 2
141 *
142 * Returns pointer to block of memory, NULL on error
143 */
144extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
145
146/**
147 * Allocate a block of memory from the free list that was
148 * passed to the application by the bootloader at a specific
149 * address. This is an allocate-only algorithm, so
150 * freeing memory is not possible. Allocation will fail if
151 * memory cannot be allocated at the specified address.
152 *
153 * @size: Size in bytes of block to allocate
154 * @address: Physical address to allocate memory at. If this memory is not
155 * available, the allocation fails.
156 * @alignment: Alignment required - must be power of 2
157 * Returns pointer to block of memory, NULL on error
158 */
159extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
160 uint64_t alignment);
161
162/**
163 * Allocate a block of memory from the free list that was
164 * passed to the application by the bootloader within a specified
165 * address range. This is an allocate-only algorithm, so
166 * freeing memory is not possible. Allocation will fail if
167 * memory cannot be allocated in the requested range.
168 *
169 * @size: Size in bytes of block to allocate
170 * @min_addr: defines the minimum address of the range
171 * @max_addr: defines the maximum address of the range
172 * @alignment: Alignment required - must be power of 2
173 * Returns pointer to block of memory, NULL on error
174 */
175extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
176 uint64_t min_addr, uint64_t max_addr);
177
178/**
179 * Frees a previously allocated named bootmem block.
180 *
181 * @name: name of block to free
182 *
183 * Returns 0 on failure,
184 * !0 on success
185 */
186extern int cvmx_bootmem_free_named(char *name);
187
188/**
189 * Finds a named bootmem block by name.
190 *
191 * @name: name of block to free
192 *
193 * Returns pointer to named block descriptor on success
194 * 0 on failure
195 */
196struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
197
198/**
199 * Allocates a block of physical memory from the free list, at
200 * (optional) requested address and alignment.
201 *
202 * @req_size: size of region to allocate. All requests are rounded up
203 * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
204 *
205 * @address_min: Minimum address that block can occupy.
206 *
207 * @address_max: Specifies the maximum address_min (inclusive) that
208 * the allocation can use.
209 *
210 * @alignment: Requested alignment of the block. If this alignment
211 * cannot be met, the allocation fails. This must be a
212 * power of 2. (Note: Alignment of
213 * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
214 * internally enforced. Requested alignments of less than
215 * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
216 * CVMX_BOOTMEM_ALIGNMENT_SIZE.)
217 *
218 * @flags: Flags to control options for the allocation.
219 *
220 * Returns physical address of block allocated, or -1 on failure
221 */
222int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
223 uint64_t address_max, uint64_t alignment,
224 uint32_t flags);
225
226/**
227 * Finds a named memory block by name.
228 * Also used for finding an unused entry in the named block table.
229 *
230 * @name: Name of memory block to find. If NULL pointer given, then
231 * finds unused descriptor, if available.
232 *
233 * @flags: Flags to control options for the allocation.
234 *
235 * Returns Pointer to memory block descriptor, NULL if not found.
236 * If NULL returned when name parameter is NULL, then no memory
237 * block descriptors are available.
238 */
239struct cvmx_bootmem_named_block_desc *
240cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
241
242/**
243 * Frees a named block.
244 *
245 * @name: name of block to free
246 * @flags: flags for passing options
247 *
248 * Returns 0 on failure
249 * 1 on success
250 */
251int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
252
253/**
254 * Frees a block to the bootmem allocator list. This must
255 * be used with care, as the size provided must match the size
256 * of the block that was allocated, or the list will become
257 * corrupted.
258 *
259 * IMPORTANT: This is only intended to be used as part of named block
260 * frees and initial population of the free memory list.
261 * *
262 *
263 * @phy_addr: physical address of block
264 * @size: size of block in bytes.
265 * @flags: flags for passing options
266 *
267 * Returns 1 on success,
268 * 0 on failure
269 */
270int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
271
272/**
273 * Locks the bootmem allocator. This is useful in certain situations
274 * where multiple allocations must be made without being interrupted.
275 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
276 *
277 */
278void cvmx_bootmem_lock(void);
279
280/**
281 * Unlocks the bootmem allocator. This is useful in certain situations
282 * where multiple allocations must be made without being interrupted.
283 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
284 *
285 */
286void cvmx_bootmem_unlock(void);
287
288#endif /* __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
new file mode 100644
index 000000000000..f8f05b7764b7
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -0,0 +1,1616 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_CIU_DEFS_H__
29#define __CVMX_CIU_DEFS_H__
30
31#define CVMX_CIU_BIST \
32 CVMX_ADD_IO_SEG(0x0001070000000730ull)
33#define CVMX_CIU_DINT \
34 CVMX_ADD_IO_SEG(0x0001070000000720ull)
35#define CVMX_CIU_FUSE \
36 CVMX_ADD_IO_SEG(0x0001070000000728ull)
37#define CVMX_CIU_GSTOP \
38 CVMX_ADD_IO_SEG(0x0001070000000710ull)
39#define CVMX_CIU_INTX_EN0(offset) \
40 CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
41#define CVMX_CIU_INTX_EN0_W1C(offset) \
42 CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
43#define CVMX_CIU_INTX_EN0_W1S(offset) \
44 CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
45#define CVMX_CIU_INTX_EN1(offset) \
46 CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
47#define CVMX_CIU_INTX_EN1_W1C(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
49#define CVMX_CIU_INTX_EN1_W1S(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
51#define CVMX_CIU_INTX_EN4_0(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
53#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
55#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
57#define CVMX_CIU_INTX_EN4_1(offset) \
58 CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
59#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
60 CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
61#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
62 CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
63#define CVMX_CIU_INTX_SUM0(offset) \
64 CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
65#define CVMX_CIU_INTX_SUM4(offset) \
66 CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
67#define CVMX_CIU_INT_SUM1 \
68 CVMX_ADD_IO_SEG(0x0001070000000108ull)
69#define CVMX_CIU_MBOX_CLRX(offset) \
70 CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
71#define CVMX_CIU_MBOX_SETX(offset) \
72 CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
73#define CVMX_CIU_NMI \
74 CVMX_ADD_IO_SEG(0x0001070000000718ull)
75#define CVMX_CIU_PCI_INTA \
76 CVMX_ADD_IO_SEG(0x0001070000000750ull)
77#define CVMX_CIU_PP_DBG \
78 CVMX_ADD_IO_SEG(0x0001070000000708ull)
79#define CVMX_CIU_PP_POKEX(offset) \
80 CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
81#define CVMX_CIU_PP_RST \
82 CVMX_ADD_IO_SEG(0x0001070000000700ull)
83#define CVMX_CIU_QLM_DCOK \
84 CVMX_ADD_IO_SEG(0x0001070000000760ull)
85#define CVMX_CIU_QLM_JTGC \
86 CVMX_ADD_IO_SEG(0x0001070000000768ull)
87#define CVMX_CIU_QLM_JTGD \
88 CVMX_ADD_IO_SEG(0x0001070000000770ull)
89#define CVMX_CIU_SOFT_BIST \
90 CVMX_ADD_IO_SEG(0x0001070000000738ull)
91#define CVMX_CIU_SOFT_PRST \
92 CVMX_ADD_IO_SEG(0x0001070000000748ull)
93#define CVMX_CIU_SOFT_PRST1 \
94 CVMX_ADD_IO_SEG(0x0001070000000758ull)
95#define CVMX_CIU_SOFT_RST \
96 CVMX_ADD_IO_SEG(0x0001070000000740ull)
97#define CVMX_CIU_TIMX(offset) \
98 CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
99#define CVMX_CIU_WDOGX(offset) \
100 CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
101
102union cvmx_ciu_bist {
103 uint64_t u64;
104 struct cvmx_ciu_bist_s {
105 uint64_t reserved_4_63:60;
106 uint64_t bist:4;
107 } s;
108 struct cvmx_ciu_bist_s cn30xx;
109 struct cvmx_ciu_bist_s cn31xx;
110 struct cvmx_ciu_bist_s cn38xx;
111 struct cvmx_ciu_bist_s cn38xxp2;
112 struct cvmx_ciu_bist_cn50xx {
113 uint64_t reserved_2_63:62;
114 uint64_t bist:2;
115 } cn50xx;
116 struct cvmx_ciu_bist_cn52xx {
117 uint64_t reserved_3_63:61;
118 uint64_t bist:3;
119 } cn52xx;
120 struct cvmx_ciu_bist_cn52xx cn52xxp1;
121 struct cvmx_ciu_bist_s cn56xx;
122 struct cvmx_ciu_bist_s cn56xxp1;
123 struct cvmx_ciu_bist_s cn58xx;
124 struct cvmx_ciu_bist_s cn58xxp1;
125};
126
127union cvmx_ciu_dint {
128 uint64_t u64;
129 struct cvmx_ciu_dint_s {
130 uint64_t reserved_16_63:48;
131 uint64_t dint:16;
132 } s;
133 struct cvmx_ciu_dint_cn30xx {
134 uint64_t reserved_1_63:63;
135 uint64_t dint:1;
136 } cn30xx;
137 struct cvmx_ciu_dint_cn31xx {
138 uint64_t reserved_2_63:62;
139 uint64_t dint:2;
140 } cn31xx;
141 struct cvmx_ciu_dint_s cn38xx;
142 struct cvmx_ciu_dint_s cn38xxp2;
143 struct cvmx_ciu_dint_cn31xx cn50xx;
144 struct cvmx_ciu_dint_cn52xx {
145 uint64_t reserved_4_63:60;
146 uint64_t dint:4;
147 } cn52xx;
148 struct cvmx_ciu_dint_cn52xx cn52xxp1;
149 struct cvmx_ciu_dint_cn56xx {
150 uint64_t reserved_12_63:52;
151 uint64_t dint:12;
152 } cn56xx;
153 struct cvmx_ciu_dint_cn56xx cn56xxp1;
154 struct cvmx_ciu_dint_s cn58xx;
155 struct cvmx_ciu_dint_s cn58xxp1;
156};
157
158union cvmx_ciu_fuse {
159 uint64_t u64;
160 struct cvmx_ciu_fuse_s {
161 uint64_t reserved_16_63:48;
162 uint64_t fuse:16;
163 } s;
164 struct cvmx_ciu_fuse_cn30xx {
165 uint64_t reserved_1_63:63;
166 uint64_t fuse:1;
167 } cn30xx;
168 struct cvmx_ciu_fuse_cn31xx {
169 uint64_t reserved_2_63:62;
170 uint64_t fuse:2;
171 } cn31xx;
172 struct cvmx_ciu_fuse_s cn38xx;
173 struct cvmx_ciu_fuse_s cn38xxp2;
174 struct cvmx_ciu_fuse_cn31xx cn50xx;
175 struct cvmx_ciu_fuse_cn52xx {
176 uint64_t reserved_4_63:60;
177 uint64_t fuse:4;
178 } cn52xx;
179 struct cvmx_ciu_fuse_cn52xx cn52xxp1;
180 struct cvmx_ciu_fuse_cn56xx {
181 uint64_t reserved_12_63:52;
182 uint64_t fuse:12;
183 } cn56xx;
184 struct cvmx_ciu_fuse_cn56xx cn56xxp1;
185 struct cvmx_ciu_fuse_s cn58xx;
186 struct cvmx_ciu_fuse_s cn58xxp1;
187};
188
189union cvmx_ciu_gstop {
190 uint64_t u64;
191 struct cvmx_ciu_gstop_s {
192 uint64_t reserved_1_63:63;
193 uint64_t gstop:1;
194 } s;
195 struct cvmx_ciu_gstop_s cn30xx;
196 struct cvmx_ciu_gstop_s cn31xx;
197 struct cvmx_ciu_gstop_s cn38xx;
198 struct cvmx_ciu_gstop_s cn38xxp2;
199 struct cvmx_ciu_gstop_s cn50xx;
200 struct cvmx_ciu_gstop_s cn52xx;
201 struct cvmx_ciu_gstop_s cn52xxp1;
202 struct cvmx_ciu_gstop_s cn56xx;
203 struct cvmx_ciu_gstop_s cn56xxp1;
204 struct cvmx_ciu_gstop_s cn58xx;
205 struct cvmx_ciu_gstop_s cn58xxp1;
206};
207
208union cvmx_ciu_intx_en0 {
209 uint64_t u64;
210 struct cvmx_ciu_intx_en0_s {
211 uint64_t bootdma:1;
212 uint64_t mii:1;
213 uint64_t ipdppthr:1;
214 uint64_t powiq:1;
215 uint64_t twsi2:1;
216 uint64_t mpi:1;
217 uint64_t pcm:1;
218 uint64_t usb:1;
219 uint64_t timer:4;
220 uint64_t key_zero:1;
221 uint64_t ipd_drp:1;
222 uint64_t gmx_drp:2;
223 uint64_t trace:1;
224 uint64_t rml:1;
225 uint64_t twsi:1;
226 uint64_t reserved_44_44:1;
227 uint64_t pci_msi:4;
228 uint64_t pci_int:4;
229 uint64_t uart:2;
230 uint64_t mbox:2;
231 uint64_t gpio:16;
232 uint64_t workq:16;
233 } s;
234 struct cvmx_ciu_intx_en0_cn30xx {
235 uint64_t reserved_59_63:5;
236 uint64_t mpi:1;
237 uint64_t pcm:1;
238 uint64_t usb:1;
239 uint64_t timer:4;
240 uint64_t reserved_51_51:1;
241 uint64_t ipd_drp:1;
242 uint64_t reserved_49_49:1;
243 uint64_t gmx_drp:1;
244 uint64_t reserved_47_47:1;
245 uint64_t rml:1;
246 uint64_t twsi:1;
247 uint64_t reserved_44_44:1;
248 uint64_t pci_msi:4;
249 uint64_t pci_int:4;
250 uint64_t uart:2;
251 uint64_t mbox:2;
252 uint64_t gpio:16;
253 uint64_t workq:16;
254 } cn30xx;
255 struct cvmx_ciu_intx_en0_cn31xx {
256 uint64_t reserved_59_63:5;
257 uint64_t mpi:1;
258 uint64_t pcm:1;
259 uint64_t usb:1;
260 uint64_t timer:4;
261 uint64_t reserved_51_51:1;
262 uint64_t ipd_drp:1;
263 uint64_t reserved_49_49:1;
264 uint64_t gmx_drp:1;
265 uint64_t trace:1;
266 uint64_t rml:1;
267 uint64_t twsi:1;
268 uint64_t reserved_44_44:1;
269 uint64_t pci_msi:4;
270 uint64_t pci_int:4;
271 uint64_t uart:2;
272 uint64_t mbox:2;
273 uint64_t gpio:16;
274 uint64_t workq:16;
275 } cn31xx;
276 struct cvmx_ciu_intx_en0_cn38xx {
277 uint64_t reserved_56_63:8;
278 uint64_t timer:4;
279 uint64_t key_zero:1;
280 uint64_t ipd_drp:1;
281 uint64_t gmx_drp:2;
282 uint64_t trace:1;
283 uint64_t rml:1;
284 uint64_t twsi:1;
285 uint64_t reserved_44_44:1;
286 uint64_t pci_msi:4;
287 uint64_t pci_int:4;
288 uint64_t uart:2;
289 uint64_t mbox:2;
290 uint64_t gpio:16;
291 uint64_t workq:16;
292 } cn38xx;
293 struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
294 struct cvmx_ciu_intx_en0_cn30xx cn50xx;
295 struct cvmx_ciu_intx_en0_cn52xx {
296 uint64_t bootdma:1;
297 uint64_t mii:1;
298 uint64_t ipdppthr:1;
299 uint64_t powiq:1;
300 uint64_t twsi2:1;
301 uint64_t reserved_57_58:2;
302 uint64_t usb:1;
303 uint64_t timer:4;
304 uint64_t reserved_51_51:1;
305 uint64_t ipd_drp:1;
306 uint64_t reserved_49_49:1;
307 uint64_t gmx_drp:1;
308 uint64_t trace:1;
309 uint64_t rml:1;
310 uint64_t twsi:1;
311 uint64_t reserved_44_44:1;
312 uint64_t pci_msi:4;
313 uint64_t pci_int:4;
314 uint64_t uart:2;
315 uint64_t mbox:2;
316 uint64_t gpio:16;
317 uint64_t workq:16;
318 } cn52xx;
319 struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
320 struct cvmx_ciu_intx_en0_cn56xx {
321 uint64_t bootdma:1;
322 uint64_t mii:1;
323 uint64_t ipdppthr:1;
324 uint64_t powiq:1;
325 uint64_t twsi2:1;
326 uint64_t reserved_57_58:2;
327 uint64_t usb:1;
328 uint64_t timer:4;
329 uint64_t key_zero:1;
330 uint64_t ipd_drp:1;
331 uint64_t gmx_drp:2;
332 uint64_t trace:1;
333 uint64_t rml:1;
334 uint64_t twsi:1;
335 uint64_t reserved_44_44:1;
336 uint64_t pci_msi:4;
337 uint64_t pci_int:4;
338 uint64_t uart:2;
339 uint64_t mbox:2;
340 uint64_t gpio:16;
341 uint64_t workq:16;
342 } cn56xx;
343 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
344 struct cvmx_ciu_intx_en0_cn38xx cn58xx;
345 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
346};
347
348union cvmx_ciu_intx_en0_w1c {
349 uint64_t u64;
350 struct cvmx_ciu_intx_en0_w1c_s {
351 uint64_t bootdma:1;
352 uint64_t mii:1;
353 uint64_t ipdppthr:1;
354 uint64_t powiq:1;
355 uint64_t twsi2:1;
356 uint64_t reserved_57_58:2;
357 uint64_t usb:1;
358 uint64_t timer:4;
359 uint64_t key_zero:1;
360 uint64_t ipd_drp:1;
361 uint64_t gmx_drp:2;
362 uint64_t trace:1;
363 uint64_t rml:1;
364 uint64_t twsi:1;
365 uint64_t reserved_44_44:1;
366 uint64_t pci_msi:4;
367 uint64_t pci_int:4;
368 uint64_t uart:2;
369 uint64_t mbox:2;
370 uint64_t gpio:16;
371 uint64_t workq:16;
372 } s;
373 struct cvmx_ciu_intx_en0_w1c_cn52xx {
374 uint64_t bootdma:1;
375 uint64_t mii:1;
376 uint64_t ipdppthr:1;
377 uint64_t powiq:1;
378 uint64_t twsi2:1;
379 uint64_t reserved_57_58:2;
380 uint64_t usb:1;
381 uint64_t timer:4;
382 uint64_t reserved_51_51:1;
383 uint64_t ipd_drp:1;
384 uint64_t reserved_49_49:1;
385 uint64_t gmx_drp:1;
386 uint64_t trace:1;
387 uint64_t rml:1;
388 uint64_t twsi:1;
389 uint64_t reserved_44_44:1;
390 uint64_t pci_msi:4;
391 uint64_t pci_int:4;
392 uint64_t uart:2;
393 uint64_t mbox:2;
394 uint64_t gpio:16;
395 uint64_t workq:16;
396 } cn52xx;
397 struct cvmx_ciu_intx_en0_w1c_s cn56xx;
398 struct cvmx_ciu_intx_en0_w1c_cn58xx {
399 uint64_t reserved_56_63:8;
400 uint64_t timer:4;
401 uint64_t key_zero:1;
402 uint64_t ipd_drp:1;
403 uint64_t gmx_drp:2;
404 uint64_t trace:1;
405 uint64_t rml:1;
406 uint64_t twsi:1;
407 uint64_t reserved_44_44:1;
408 uint64_t pci_msi:4;
409 uint64_t pci_int:4;
410 uint64_t uart:2;
411 uint64_t mbox:2;
412 uint64_t gpio:16;
413 uint64_t workq:16;
414 } cn58xx;
415};
416
417union cvmx_ciu_intx_en0_w1s {
418 uint64_t u64;
419 struct cvmx_ciu_intx_en0_w1s_s {
420 uint64_t bootdma:1;
421 uint64_t mii:1;
422 uint64_t ipdppthr:1;
423 uint64_t powiq:1;
424 uint64_t twsi2:1;
425 uint64_t reserved_57_58:2;
426 uint64_t usb:1;
427 uint64_t timer:4;
428 uint64_t key_zero:1;
429 uint64_t ipd_drp:1;
430 uint64_t gmx_drp:2;
431 uint64_t trace:1;
432 uint64_t rml:1;
433 uint64_t twsi:1;
434 uint64_t reserved_44_44:1;
435 uint64_t pci_msi:4;
436 uint64_t pci_int:4;
437 uint64_t uart:2;
438 uint64_t mbox:2;
439 uint64_t gpio:16;
440 uint64_t workq:16;
441 } s;
442 struct cvmx_ciu_intx_en0_w1s_cn52xx {
443 uint64_t bootdma:1;
444 uint64_t mii:1;
445 uint64_t ipdppthr:1;
446 uint64_t powiq:1;
447 uint64_t twsi2:1;
448 uint64_t reserved_57_58:2;
449 uint64_t usb:1;
450 uint64_t timer:4;
451 uint64_t reserved_51_51:1;
452 uint64_t ipd_drp:1;
453 uint64_t reserved_49_49:1;
454 uint64_t gmx_drp:1;
455 uint64_t trace:1;
456 uint64_t rml:1;
457 uint64_t twsi:1;
458 uint64_t reserved_44_44:1;
459 uint64_t pci_msi:4;
460 uint64_t pci_int:4;
461 uint64_t uart:2;
462 uint64_t mbox:2;
463 uint64_t gpio:16;
464 uint64_t workq:16;
465 } cn52xx;
466 struct cvmx_ciu_intx_en0_w1s_s cn56xx;
467 struct cvmx_ciu_intx_en0_w1s_cn58xx {
468 uint64_t reserved_56_63:8;
469 uint64_t timer:4;
470 uint64_t key_zero:1;
471 uint64_t ipd_drp:1;
472 uint64_t gmx_drp:2;
473 uint64_t trace:1;
474 uint64_t rml:1;
475 uint64_t twsi:1;
476 uint64_t reserved_44_44:1;
477 uint64_t pci_msi:4;
478 uint64_t pci_int:4;
479 uint64_t uart:2;
480 uint64_t mbox:2;
481 uint64_t gpio:16;
482 uint64_t workq:16;
483 } cn58xx;
484};
485
486union cvmx_ciu_intx_en1 {
487 uint64_t u64;
488 struct cvmx_ciu_intx_en1_s {
489 uint64_t reserved_20_63:44;
490 uint64_t nand:1;
491 uint64_t mii1:1;
492 uint64_t usb1:1;
493 uint64_t uart2:1;
494 uint64_t wdog:16;
495 } s;
496 struct cvmx_ciu_intx_en1_cn30xx {
497 uint64_t reserved_1_63:63;
498 uint64_t wdog:1;
499 } cn30xx;
500 struct cvmx_ciu_intx_en1_cn31xx {
501 uint64_t reserved_2_63:62;
502 uint64_t wdog:2;
503 } cn31xx;
504 struct cvmx_ciu_intx_en1_cn38xx {
505 uint64_t reserved_16_63:48;
506 uint64_t wdog:16;
507 } cn38xx;
508 struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
509 struct cvmx_ciu_intx_en1_cn31xx cn50xx;
510 struct cvmx_ciu_intx_en1_cn52xx {
511 uint64_t reserved_20_63:44;
512 uint64_t nand:1;
513 uint64_t mii1:1;
514 uint64_t usb1:1;
515 uint64_t uart2:1;
516 uint64_t reserved_4_15:12;
517 uint64_t wdog:4;
518 } cn52xx;
519 struct cvmx_ciu_intx_en1_cn52xxp1 {
520 uint64_t reserved_19_63:45;
521 uint64_t mii1:1;
522 uint64_t usb1:1;
523 uint64_t uart2:1;
524 uint64_t reserved_4_15:12;
525 uint64_t wdog:4;
526 } cn52xxp1;
527 struct cvmx_ciu_intx_en1_cn56xx {
528 uint64_t reserved_12_63:52;
529 uint64_t wdog:12;
530 } cn56xx;
531 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
532 struct cvmx_ciu_intx_en1_cn38xx cn58xx;
533 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
534};
535
536union cvmx_ciu_intx_en1_w1c {
537 uint64_t u64;
538 struct cvmx_ciu_intx_en1_w1c_s {
539 uint64_t reserved_20_63:44;
540 uint64_t nand:1;
541 uint64_t mii1:1;
542 uint64_t usb1:1;
543 uint64_t uart2:1;
544 uint64_t wdog:16;
545 } s;
546 struct cvmx_ciu_intx_en1_w1c_cn52xx {
547 uint64_t reserved_20_63:44;
548 uint64_t nand:1;
549 uint64_t mii1:1;
550 uint64_t usb1:1;
551 uint64_t uart2:1;
552 uint64_t reserved_4_15:12;
553 uint64_t wdog:4;
554 } cn52xx;
555 struct cvmx_ciu_intx_en1_w1c_cn56xx {
556 uint64_t reserved_12_63:52;
557 uint64_t wdog:12;
558 } cn56xx;
559 struct cvmx_ciu_intx_en1_w1c_cn58xx {
560 uint64_t reserved_16_63:48;
561 uint64_t wdog:16;
562 } cn58xx;
563};
564
565union cvmx_ciu_intx_en1_w1s {
566 uint64_t u64;
567 struct cvmx_ciu_intx_en1_w1s_s {
568 uint64_t reserved_20_63:44;
569 uint64_t nand:1;
570 uint64_t mii1:1;
571 uint64_t usb1:1;
572 uint64_t uart2:1;
573 uint64_t wdog:16;
574 } s;
575 struct cvmx_ciu_intx_en1_w1s_cn52xx {
576 uint64_t reserved_20_63:44;
577 uint64_t nand:1;
578 uint64_t mii1:1;
579 uint64_t usb1:1;
580 uint64_t uart2:1;
581 uint64_t reserved_4_15:12;
582 uint64_t wdog:4;
583 } cn52xx;
584 struct cvmx_ciu_intx_en1_w1s_cn56xx {
585 uint64_t reserved_12_63:52;
586 uint64_t wdog:12;
587 } cn56xx;
588 struct cvmx_ciu_intx_en1_w1s_cn58xx {
589 uint64_t reserved_16_63:48;
590 uint64_t wdog:16;
591 } cn58xx;
592};
593
594union cvmx_ciu_intx_en4_0 {
595 uint64_t u64;
596 struct cvmx_ciu_intx_en4_0_s {
597 uint64_t bootdma:1;
598 uint64_t mii:1;
599 uint64_t ipdppthr:1;
600 uint64_t powiq:1;
601 uint64_t twsi2:1;
602 uint64_t mpi:1;
603 uint64_t pcm:1;
604 uint64_t usb:1;
605 uint64_t timer:4;
606 uint64_t key_zero:1;
607 uint64_t ipd_drp:1;
608 uint64_t gmx_drp:2;
609 uint64_t trace:1;
610 uint64_t rml:1;
611 uint64_t twsi:1;
612 uint64_t reserved_44_44:1;
613 uint64_t pci_msi:4;
614 uint64_t pci_int:4;
615 uint64_t uart:2;
616 uint64_t mbox:2;
617 uint64_t gpio:16;
618 uint64_t workq:16;
619 } s;
620 struct cvmx_ciu_intx_en4_0_cn50xx {
621 uint64_t reserved_59_63:5;
622 uint64_t mpi:1;
623 uint64_t pcm:1;
624 uint64_t usb:1;
625 uint64_t timer:4;
626 uint64_t reserved_51_51:1;
627 uint64_t ipd_drp:1;
628 uint64_t reserved_49_49:1;
629 uint64_t gmx_drp:1;
630 uint64_t reserved_47_47:1;
631 uint64_t rml:1;
632 uint64_t twsi:1;
633 uint64_t reserved_44_44:1;
634 uint64_t pci_msi:4;
635 uint64_t pci_int:4;
636 uint64_t uart:2;
637 uint64_t mbox:2;
638 uint64_t gpio:16;
639 uint64_t workq:16;
640 } cn50xx;
641 struct cvmx_ciu_intx_en4_0_cn52xx {
642 uint64_t bootdma:1;
643 uint64_t mii:1;
644 uint64_t ipdppthr:1;
645 uint64_t powiq:1;
646 uint64_t twsi2:1;
647 uint64_t reserved_57_58:2;
648 uint64_t usb:1;
649 uint64_t timer:4;
650 uint64_t reserved_51_51:1;
651 uint64_t ipd_drp:1;
652 uint64_t reserved_49_49:1;
653 uint64_t gmx_drp:1;
654 uint64_t trace:1;
655 uint64_t rml:1;
656 uint64_t twsi:1;
657 uint64_t reserved_44_44:1;
658 uint64_t pci_msi:4;
659 uint64_t pci_int:4;
660 uint64_t uart:2;
661 uint64_t mbox:2;
662 uint64_t gpio:16;
663 uint64_t workq:16;
664 } cn52xx;
665 struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
666 struct cvmx_ciu_intx_en4_0_cn56xx {
667 uint64_t bootdma:1;
668 uint64_t mii:1;
669 uint64_t ipdppthr:1;
670 uint64_t powiq:1;
671 uint64_t twsi2:1;
672 uint64_t reserved_57_58:2;
673 uint64_t usb:1;
674 uint64_t timer:4;
675 uint64_t key_zero:1;
676 uint64_t ipd_drp:1;
677 uint64_t gmx_drp:2;
678 uint64_t trace:1;
679 uint64_t rml:1;
680 uint64_t twsi:1;
681 uint64_t reserved_44_44:1;
682 uint64_t pci_msi:4;
683 uint64_t pci_int:4;
684 uint64_t uart:2;
685 uint64_t mbox:2;
686 uint64_t gpio:16;
687 uint64_t workq:16;
688 } cn56xx;
689 struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
690 struct cvmx_ciu_intx_en4_0_cn58xx {
691 uint64_t reserved_56_63:8;
692 uint64_t timer:4;
693 uint64_t key_zero:1;
694 uint64_t ipd_drp:1;
695 uint64_t gmx_drp:2;
696 uint64_t trace:1;
697 uint64_t rml:1;
698 uint64_t twsi:1;
699 uint64_t reserved_44_44:1;
700 uint64_t pci_msi:4;
701 uint64_t pci_int:4;
702 uint64_t uart:2;
703 uint64_t mbox:2;
704 uint64_t gpio:16;
705 uint64_t workq:16;
706 } cn58xx;
707 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
708};
709
710union cvmx_ciu_intx_en4_0_w1c {
711 uint64_t u64;
712 struct cvmx_ciu_intx_en4_0_w1c_s {
713 uint64_t bootdma:1;
714 uint64_t mii:1;
715 uint64_t ipdppthr:1;
716 uint64_t powiq:1;
717 uint64_t twsi2:1;
718 uint64_t reserved_57_58:2;
719 uint64_t usb:1;
720 uint64_t timer:4;
721 uint64_t key_zero:1;
722 uint64_t ipd_drp:1;
723 uint64_t gmx_drp:2;
724 uint64_t trace:1;
725 uint64_t rml:1;
726 uint64_t twsi:1;
727 uint64_t reserved_44_44:1;
728 uint64_t pci_msi:4;
729 uint64_t pci_int:4;
730 uint64_t uart:2;
731 uint64_t mbox:2;
732 uint64_t gpio:16;
733 uint64_t workq:16;
734 } s;
735 struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
736 uint64_t bootdma:1;
737 uint64_t mii:1;
738 uint64_t ipdppthr:1;
739 uint64_t powiq:1;
740 uint64_t twsi2:1;
741 uint64_t reserved_57_58:2;
742 uint64_t usb:1;
743 uint64_t timer:4;
744 uint64_t reserved_51_51:1;
745 uint64_t ipd_drp:1;
746 uint64_t reserved_49_49:1;
747 uint64_t gmx_drp:1;
748 uint64_t trace:1;
749 uint64_t rml:1;
750 uint64_t twsi:1;
751 uint64_t reserved_44_44:1;
752 uint64_t pci_msi:4;
753 uint64_t pci_int:4;
754 uint64_t uart:2;
755 uint64_t mbox:2;
756 uint64_t gpio:16;
757 uint64_t workq:16;
758 } cn52xx;
759 struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
760 struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
761 uint64_t reserved_56_63:8;
762 uint64_t timer:4;
763 uint64_t key_zero:1;
764 uint64_t ipd_drp:1;
765 uint64_t gmx_drp:2;
766 uint64_t trace:1;
767 uint64_t rml:1;
768 uint64_t twsi:1;
769 uint64_t reserved_44_44:1;
770 uint64_t pci_msi:4;
771 uint64_t pci_int:4;
772 uint64_t uart:2;
773 uint64_t mbox:2;
774 uint64_t gpio:16;
775 uint64_t workq:16;
776 } cn58xx;
777};
778
779union cvmx_ciu_intx_en4_0_w1s {
780 uint64_t u64;
781 struct cvmx_ciu_intx_en4_0_w1s_s {
782 uint64_t bootdma:1;
783 uint64_t mii:1;
784 uint64_t ipdppthr:1;
785 uint64_t powiq:1;
786 uint64_t twsi2:1;
787 uint64_t reserved_57_58:2;
788 uint64_t usb:1;
789 uint64_t timer:4;
790 uint64_t key_zero:1;
791 uint64_t ipd_drp:1;
792 uint64_t gmx_drp:2;
793 uint64_t trace:1;
794 uint64_t rml:1;
795 uint64_t twsi:1;
796 uint64_t reserved_44_44:1;
797 uint64_t pci_msi:4;
798 uint64_t pci_int:4;
799 uint64_t uart:2;
800 uint64_t mbox:2;
801 uint64_t gpio:16;
802 uint64_t workq:16;
803 } s;
804 struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
805 uint64_t bootdma:1;
806 uint64_t mii:1;
807 uint64_t ipdppthr:1;
808 uint64_t powiq:1;
809 uint64_t twsi2:1;
810 uint64_t reserved_57_58:2;
811 uint64_t usb:1;
812 uint64_t timer:4;
813 uint64_t reserved_51_51:1;
814 uint64_t ipd_drp:1;
815 uint64_t reserved_49_49:1;
816 uint64_t gmx_drp:1;
817 uint64_t trace:1;
818 uint64_t rml:1;
819 uint64_t twsi:1;
820 uint64_t reserved_44_44:1;
821 uint64_t pci_msi:4;
822 uint64_t pci_int:4;
823 uint64_t uart:2;
824 uint64_t mbox:2;
825 uint64_t gpio:16;
826 uint64_t workq:16;
827 } cn52xx;
828 struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
829 struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
830 uint64_t reserved_56_63:8;
831 uint64_t timer:4;
832 uint64_t key_zero:1;
833 uint64_t ipd_drp:1;
834 uint64_t gmx_drp:2;
835 uint64_t trace:1;
836 uint64_t rml:1;
837 uint64_t twsi:1;
838 uint64_t reserved_44_44:1;
839 uint64_t pci_msi:4;
840 uint64_t pci_int:4;
841 uint64_t uart:2;
842 uint64_t mbox:2;
843 uint64_t gpio:16;
844 uint64_t workq:16;
845 } cn58xx;
846};
847
848union cvmx_ciu_intx_en4_1 {
849 uint64_t u64;
850 struct cvmx_ciu_intx_en4_1_s {
851 uint64_t reserved_20_63:44;
852 uint64_t nand:1;
853 uint64_t mii1:1;
854 uint64_t usb1:1;
855 uint64_t uart2:1;
856 uint64_t wdog:16;
857 } s;
858 struct cvmx_ciu_intx_en4_1_cn50xx {
859 uint64_t reserved_2_63:62;
860 uint64_t wdog:2;
861 } cn50xx;
862 struct cvmx_ciu_intx_en4_1_cn52xx {
863 uint64_t reserved_20_63:44;
864 uint64_t nand:1;
865 uint64_t mii1:1;
866 uint64_t usb1:1;
867 uint64_t uart2:1;
868 uint64_t reserved_4_15:12;
869 uint64_t wdog:4;
870 } cn52xx;
871 struct cvmx_ciu_intx_en4_1_cn52xxp1 {
872 uint64_t reserved_19_63:45;
873 uint64_t mii1:1;
874 uint64_t usb1:1;
875 uint64_t uart2:1;
876 uint64_t reserved_4_15:12;
877 uint64_t wdog:4;
878 } cn52xxp1;
879 struct cvmx_ciu_intx_en4_1_cn56xx {
880 uint64_t reserved_12_63:52;
881 uint64_t wdog:12;
882 } cn56xx;
883 struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
884 struct cvmx_ciu_intx_en4_1_cn58xx {
885 uint64_t reserved_16_63:48;
886 uint64_t wdog:16;
887 } cn58xx;
888 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
889};
890
891union cvmx_ciu_intx_en4_1_w1c {
892 uint64_t u64;
893 struct cvmx_ciu_intx_en4_1_w1c_s {
894 uint64_t reserved_20_63:44;
895 uint64_t nand:1;
896 uint64_t mii1:1;
897 uint64_t usb1:1;
898 uint64_t uart2:1;
899 uint64_t wdog:16;
900 } s;
901 struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
902 uint64_t reserved_20_63:44;
903 uint64_t nand:1;
904 uint64_t mii1:1;
905 uint64_t usb1:1;
906 uint64_t uart2:1;
907 uint64_t reserved_4_15:12;
908 uint64_t wdog:4;
909 } cn52xx;
910 struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
911 uint64_t reserved_12_63:52;
912 uint64_t wdog:12;
913 } cn56xx;
914 struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
915 uint64_t reserved_16_63:48;
916 uint64_t wdog:16;
917 } cn58xx;
918};
919
920union cvmx_ciu_intx_en4_1_w1s {
921 uint64_t u64;
922 struct cvmx_ciu_intx_en4_1_w1s_s {
923 uint64_t reserved_20_63:44;
924 uint64_t nand:1;
925 uint64_t mii1:1;
926 uint64_t usb1:1;
927 uint64_t uart2:1;
928 uint64_t wdog:16;
929 } s;
930 struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
931 uint64_t reserved_20_63:44;
932 uint64_t nand:1;
933 uint64_t mii1:1;
934 uint64_t usb1:1;
935 uint64_t uart2:1;
936 uint64_t reserved_4_15:12;
937 uint64_t wdog:4;
938 } cn52xx;
939 struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
940 uint64_t reserved_12_63:52;
941 uint64_t wdog:12;
942 } cn56xx;
943 struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
944 uint64_t reserved_16_63:48;
945 uint64_t wdog:16;
946 } cn58xx;
947};
948
949union cvmx_ciu_intx_sum0 {
950 uint64_t u64;
951 struct cvmx_ciu_intx_sum0_s {
952 uint64_t bootdma:1;
953 uint64_t mii:1;
954 uint64_t ipdppthr:1;
955 uint64_t powiq:1;
956 uint64_t twsi2:1;
957 uint64_t mpi:1;
958 uint64_t pcm:1;
959 uint64_t usb:1;
960 uint64_t timer:4;
961 uint64_t key_zero:1;
962 uint64_t ipd_drp:1;
963 uint64_t gmx_drp:2;
964 uint64_t trace:1;
965 uint64_t rml:1;
966 uint64_t twsi:1;
967 uint64_t wdog_sum:1;
968 uint64_t pci_msi:4;
969 uint64_t pci_int:4;
970 uint64_t uart:2;
971 uint64_t mbox:2;
972 uint64_t gpio:16;
973 uint64_t workq:16;
974 } s;
975 struct cvmx_ciu_intx_sum0_cn30xx {
976 uint64_t reserved_59_63:5;
977 uint64_t mpi:1;
978 uint64_t pcm:1;
979 uint64_t usb:1;
980 uint64_t timer:4;
981 uint64_t reserved_51_51:1;
982 uint64_t ipd_drp:1;
983 uint64_t reserved_49_49:1;
984 uint64_t gmx_drp:1;
985 uint64_t reserved_47_47:1;
986 uint64_t rml:1;
987 uint64_t twsi:1;
988 uint64_t wdog_sum:1;
989 uint64_t pci_msi:4;
990 uint64_t pci_int:4;
991 uint64_t uart:2;
992 uint64_t mbox:2;
993 uint64_t gpio:16;
994 uint64_t workq:16;
995 } cn30xx;
996 struct cvmx_ciu_intx_sum0_cn31xx {
997 uint64_t reserved_59_63:5;
998 uint64_t mpi:1;
999 uint64_t pcm:1;
1000 uint64_t usb:1;
1001 uint64_t timer:4;
1002 uint64_t reserved_51_51:1;
1003 uint64_t ipd_drp:1;
1004 uint64_t reserved_49_49:1;
1005 uint64_t gmx_drp:1;
1006 uint64_t trace:1;
1007 uint64_t rml:1;
1008 uint64_t twsi:1;
1009 uint64_t wdog_sum:1;
1010 uint64_t pci_msi:4;
1011 uint64_t pci_int:4;
1012 uint64_t uart:2;
1013 uint64_t mbox:2;
1014 uint64_t gpio:16;
1015 uint64_t workq:16;
1016 } cn31xx;
1017 struct cvmx_ciu_intx_sum0_cn38xx {
1018 uint64_t reserved_56_63:8;
1019 uint64_t timer:4;
1020 uint64_t key_zero:1;
1021 uint64_t ipd_drp:1;
1022 uint64_t gmx_drp:2;
1023 uint64_t trace:1;
1024 uint64_t rml:1;
1025 uint64_t twsi:1;
1026 uint64_t wdog_sum:1;
1027 uint64_t pci_msi:4;
1028 uint64_t pci_int:4;
1029 uint64_t uart:2;
1030 uint64_t mbox:2;
1031 uint64_t gpio:16;
1032 uint64_t workq:16;
1033 } cn38xx;
1034 struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
1035 struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
1036 struct cvmx_ciu_intx_sum0_cn52xx {
1037 uint64_t bootdma:1;
1038 uint64_t mii:1;
1039 uint64_t ipdppthr:1;
1040 uint64_t powiq:1;
1041 uint64_t twsi2:1;
1042 uint64_t reserved_57_58:2;
1043 uint64_t usb:1;
1044 uint64_t timer:4;
1045 uint64_t reserved_51_51:1;
1046 uint64_t ipd_drp:1;
1047 uint64_t reserved_49_49:1;
1048 uint64_t gmx_drp:1;
1049 uint64_t trace:1;
1050 uint64_t rml:1;
1051 uint64_t twsi:1;
1052 uint64_t wdog_sum:1;
1053 uint64_t pci_msi:4;
1054 uint64_t pci_int:4;
1055 uint64_t uart:2;
1056 uint64_t mbox:2;
1057 uint64_t gpio:16;
1058 uint64_t workq:16;
1059 } cn52xx;
1060 struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
1061 struct cvmx_ciu_intx_sum0_cn56xx {
1062 uint64_t bootdma:1;
1063 uint64_t mii:1;
1064 uint64_t ipdppthr:1;
1065 uint64_t powiq:1;
1066 uint64_t twsi2:1;
1067 uint64_t reserved_57_58:2;
1068 uint64_t usb:1;
1069 uint64_t timer:4;
1070 uint64_t key_zero:1;
1071 uint64_t ipd_drp:1;
1072 uint64_t gmx_drp:2;
1073 uint64_t trace:1;
1074 uint64_t rml:1;
1075 uint64_t twsi:1;
1076 uint64_t wdog_sum:1;
1077 uint64_t pci_msi:4;
1078 uint64_t pci_int:4;
1079 uint64_t uart:2;
1080 uint64_t mbox:2;
1081 uint64_t gpio:16;
1082 uint64_t workq:16;
1083 } cn56xx;
1084 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
1085 struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
1086 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
1087};
1088
1089union cvmx_ciu_intx_sum4 {
1090 uint64_t u64;
1091 struct cvmx_ciu_intx_sum4_s {
1092 uint64_t bootdma:1;
1093 uint64_t mii:1;
1094 uint64_t ipdppthr:1;
1095 uint64_t powiq:1;
1096 uint64_t twsi2:1;
1097 uint64_t mpi:1;
1098 uint64_t pcm:1;
1099 uint64_t usb:1;
1100 uint64_t timer:4;
1101 uint64_t key_zero:1;
1102 uint64_t ipd_drp:1;
1103 uint64_t gmx_drp:2;
1104 uint64_t trace:1;
1105 uint64_t rml:1;
1106 uint64_t twsi:1;
1107 uint64_t wdog_sum:1;
1108 uint64_t pci_msi:4;
1109 uint64_t pci_int:4;
1110 uint64_t uart:2;
1111 uint64_t mbox:2;
1112 uint64_t gpio:16;
1113 uint64_t workq:16;
1114 } s;
1115 struct cvmx_ciu_intx_sum4_cn50xx {
1116 uint64_t reserved_59_63:5;
1117 uint64_t mpi:1;
1118 uint64_t pcm:1;
1119 uint64_t usb:1;
1120 uint64_t timer:4;
1121 uint64_t reserved_51_51:1;
1122 uint64_t ipd_drp:1;
1123 uint64_t reserved_49_49:1;
1124 uint64_t gmx_drp:1;
1125 uint64_t reserved_47_47:1;
1126 uint64_t rml:1;
1127 uint64_t twsi:1;
1128 uint64_t wdog_sum:1;
1129 uint64_t pci_msi:4;
1130 uint64_t pci_int:4;
1131 uint64_t uart:2;
1132 uint64_t mbox:2;
1133 uint64_t gpio:16;
1134 uint64_t workq:16;
1135 } cn50xx;
1136 struct cvmx_ciu_intx_sum4_cn52xx {
1137 uint64_t bootdma:1;
1138 uint64_t mii:1;
1139 uint64_t ipdppthr:1;
1140 uint64_t powiq:1;
1141 uint64_t twsi2:1;
1142 uint64_t reserved_57_58:2;
1143 uint64_t usb:1;
1144 uint64_t timer:4;
1145 uint64_t reserved_51_51:1;
1146 uint64_t ipd_drp:1;
1147 uint64_t reserved_49_49:1;
1148 uint64_t gmx_drp:1;
1149 uint64_t trace:1;
1150 uint64_t rml:1;
1151 uint64_t twsi:1;
1152 uint64_t wdog_sum:1;
1153 uint64_t pci_msi:4;
1154 uint64_t pci_int:4;
1155 uint64_t uart:2;
1156 uint64_t mbox:2;
1157 uint64_t gpio:16;
1158 uint64_t workq:16;
1159 } cn52xx;
1160 struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
1161 struct cvmx_ciu_intx_sum4_cn56xx {
1162 uint64_t bootdma:1;
1163 uint64_t mii:1;
1164 uint64_t ipdppthr:1;
1165 uint64_t powiq:1;
1166 uint64_t twsi2:1;
1167 uint64_t reserved_57_58:2;
1168 uint64_t usb:1;
1169 uint64_t timer:4;
1170 uint64_t key_zero:1;
1171 uint64_t ipd_drp:1;
1172 uint64_t gmx_drp:2;
1173 uint64_t trace:1;
1174 uint64_t rml:1;
1175 uint64_t twsi:1;
1176 uint64_t wdog_sum:1;
1177 uint64_t pci_msi:4;
1178 uint64_t pci_int:4;
1179 uint64_t uart:2;
1180 uint64_t mbox:2;
1181 uint64_t gpio:16;
1182 uint64_t workq:16;
1183 } cn56xx;
1184 struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
1185 struct cvmx_ciu_intx_sum4_cn58xx {
1186 uint64_t reserved_56_63:8;
1187 uint64_t timer:4;
1188 uint64_t key_zero:1;
1189 uint64_t ipd_drp:1;
1190 uint64_t gmx_drp:2;
1191 uint64_t trace:1;
1192 uint64_t rml:1;
1193 uint64_t twsi:1;
1194 uint64_t wdog_sum:1;
1195 uint64_t pci_msi:4;
1196 uint64_t pci_int:4;
1197 uint64_t uart:2;
1198 uint64_t mbox:2;
1199 uint64_t gpio:16;
1200 uint64_t workq:16;
1201 } cn58xx;
1202 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
1203};
1204
1205union cvmx_ciu_int_sum1 {
1206 uint64_t u64;
1207 struct cvmx_ciu_int_sum1_s {
1208 uint64_t reserved_20_63:44;
1209 uint64_t nand:1;
1210 uint64_t mii1:1;
1211 uint64_t usb1:1;
1212 uint64_t uart2:1;
1213 uint64_t wdog:16;
1214 } s;
1215 struct cvmx_ciu_int_sum1_cn30xx {
1216 uint64_t reserved_1_63:63;
1217 uint64_t wdog:1;
1218 } cn30xx;
1219 struct cvmx_ciu_int_sum1_cn31xx {
1220 uint64_t reserved_2_63:62;
1221 uint64_t wdog:2;
1222 } cn31xx;
1223 struct cvmx_ciu_int_sum1_cn38xx {
1224 uint64_t reserved_16_63:48;
1225 uint64_t wdog:16;
1226 } cn38xx;
1227 struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
1228 struct cvmx_ciu_int_sum1_cn31xx cn50xx;
1229 struct cvmx_ciu_int_sum1_cn52xx {
1230 uint64_t reserved_20_63:44;
1231 uint64_t nand:1;
1232 uint64_t mii1:1;
1233 uint64_t usb1:1;
1234 uint64_t uart2:1;
1235 uint64_t reserved_4_15:12;
1236 uint64_t wdog:4;
1237 } cn52xx;
1238 struct cvmx_ciu_int_sum1_cn52xxp1 {
1239 uint64_t reserved_19_63:45;
1240 uint64_t mii1:1;
1241 uint64_t usb1:1;
1242 uint64_t uart2:1;
1243 uint64_t reserved_4_15:12;
1244 uint64_t wdog:4;
1245 } cn52xxp1;
1246 struct cvmx_ciu_int_sum1_cn56xx {
1247 uint64_t reserved_12_63:52;
1248 uint64_t wdog:12;
1249 } cn56xx;
1250 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
1251 struct cvmx_ciu_int_sum1_cn38xx cn58xx;
1252 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
1253};
1254
1255union cvmx_ciu_mbox_clrx {
1256 uint64_t u64;
1257 struct cvmx_ciu_mbox_clrx_s {
1258 uint64_t reserved_32_63:32;
1259 uint64_t bits:32;
1260 } s;
1261 struct cvmx_ciu_mbox_clrx_s cn30xx;
1262 struct cvmx_ciu_mbox_clrx_s cn31xx;
1263 struct cvmx_ciu_mbox_clrx_s cn38xx;
1264 struct cvmx_ciu_mbox_clrx_s cn38xxp2;
1265 struct cvmx_ciu_mbox_clrx_s cn50xx;
1266 struct cvmx_ciu_mbox_clrx_s cn52xx;
1267 struct cvmx_ciu_mbox_clrx_s cn52xxp1;
1268 struct cvmx_ciu_mbox_clrx_s cn56xx;
1269 struct cvmx_ciu_mbox_clrx_s cn56xxp1;
1270 struct cvmx_ciu_mbox_clrx_s cn58xx;
1271 struct cvmx_ciu_mbox_clrx_s cn58xxp1;
1272};
1273
1274union cvmx_ciu_mbox_setx {
1275 uint64_t u64;
1276 struct cvmx_ciu_mbox_setx_s {
1277 uint64_t reserved_32_63:32;
1278 uint64_t bits:32;
1279 } s;
1280 struct cvmx_ciu_mbox_setx_s cn30xx;
1281 struct cvmx_ciu_mbox_setx_s cn31xx;
1282 struct cvmx_ciu_mbox_setx_s cn38xx;
1283 struct cvmx_ciu_mbox_setx_s cn38xxp2;
1284 struct cvmx_ciu_mbox_setx_s cn50xx;
1285 struct cvmx_ciu_mbox_setx_s cn52xx;
1286 struct cvmx_ciu_mbox_setx_s cn52xxp1;
1287 struct cvmx_ciu_mbox_setx_s cn56xx;
1288 struct cvmx_ciu_mbox_setx_s cn56xxp1;
1289 struct cvmx_ciu_mbox_setx_s cn58xx;
1290 struct cvmx_ciu_mbox_setx_s cn58xxp1;
1291};
1292
1293union cvmx_ciu_nmi {
1294 uint64_t u64;
1295 struct cvmx_ciu_nmi_s {
1296 uint64_t reserved_16_63:48;
1297 uint64_t nmi:16;
1298 } s;
1299 struct cvmx_ciu_nmi_cn30xx {
1300 uint64_t reserved_1_63:63;
1301 uint64_t nmi:1;
1302 } cn30xx;
1303 struct cvmx_ciu_nmi_cn31xx {
1304 uint64_t reserved_2_63:62;
1305 uint64_t nmi:2;
1306 } cn31xx;
1307 struct cvmx_ciu_nmi_s cn38xx;
1308 struct cvmx_ciu_nmi_s cn38xxp2;
1309 struct cvmx_ciu_nmi_cn31xx cn50xx;
1310 struct cvmx_ciu_nmi_cn52xx {
1311 uint64_t reserved_4_63:60;
1312 uint64_t nmi:4;
1313 } cn52xx;
1314 struct cvmx_ciu_nmi_cn52xx cn52xxp1;
1315 struct cvmx_ciu_nmi_cn56xx {
1316 uint64_t reserved_12_63:52;
1317 uint64_t nmi:12;
1318 } cn56xx;
1319 struct cvmx_ciu_nmi_cn56xx cn56xxp1;
1320 struct cvmx_ciu_nmi_s cn58xx;
1321 struct cvmx_ciu_nmi_s cn58xxp1;
1322};
1323
1324union cvmx_ciu_pci_inta {
1325 uint64_t u64;
1326 struct cvmx_ciu_pci_inta_s {
1327 uint64_t reserved_2_63:62;
1328 uint64_t intr:2;
1329 } s;
1330 struct cvmx_ciu_pci_inta_s cn30xx;
1331 struct cvmx_ciu_pci_inta_s cn31xx;
1332 struct cvmx_ciu_pci_inta_s cn38xx;
1333 struct cvmx_ciu_pci_inta_s cn38xxp2;
1334 struct cvmx_ciu_pci_inta_s cn50xx;
1335 struct cvmx_ciu_pci_inta_s cn52xx;
1336 struct cvmx_ciu_pci_inta_s cn52xxp1;
1337 struct cvmx_ciu_pci_inta_s cn56xx;
1338 struct cvmx_ciu_pci_inta_s cn56xxp1;
1339 struct cvmx_ciu_pci_inta_s cn58xx;
1340 struct cvmx_ciu_pci_inta_s cn58xxp1;
1341};
1342
1343union cvmx_ciu_pp_dbg {
1344 uint64_t u64;
1345 struct cvmx_ciu_pp_dbg_s {
1346 uint64_t reserved_16_63:48;
1347 uint64_t ppdbg:16;
1348 } s;
1349 struct cvmx_ciu_pp_dbg_cn30xx {
1350 uint64_t reserved_1_63:63;
1351 uint64_t ppdbg:1;
1352 } cn30xx;
1353 struct cvmx_ciu_pp_dbg_cn31xx {
1354 uint64_t reserved_2_63:62;
1355 uint64_t ppdbg:2;
1356 } cn31xx;
1357 struct cvmx_ciu_pp_dbg_s cn38xx;
1358 struct cvmx_ciu_pp_dbg_s cn38xxp2;
1359 struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
1360 struct cvmx_ciu_pp_dbg_cn52xx {
1361 uint64_t reserved_4_63:60;
1362 uint64_t ppdbg:4;
1363 } cn52xx;
1364 struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
1365 struct cvmx_ciu_pp_dbg_cn56xx {
1366 uint64_t reserved_12_63:52;
1367 uint64_t ppdbg:12;
1368 } cn56xx;
1369 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
1370 struct cvmx_ciu_pp_dbg_s cn58xx;
1371 struct cvmx_ciu_pp_dbg_s cn58xxp1;
1372};
1373
1374union cvmx_ciu_pp_pokex {
1375 uint64_t u64;
1376 struct cvmx_ciu_pp_pokex_s {
1377 uint64_t reserved_0_63:64;
1378 } s;
1379 struct cvmx_ciu_pp_pokex_s cn30xx;
1380 struct cvmx_ciu_pp_pokex_s cn31xx;
1381 struct cvmx_ciu_pp_pokex_s cn38xx;
1382 struct cvmx_ciu_pp_pokex_s cn38xxp2;
1383 struct cvmx_ciu_pp_pokex_s cn50xx;
1384 struct cvmx_ciu_pp_pokex_s cn52xx;
1385 struct cvmx_ciu_pp_pokex_s cn52xxp1;
1386 struct cvmx_ciu_pp_pokex_s cn56xx;
1387 struct cvmx_ciu_pp_pokex_s cn56xxp1;
1388 struct cvmx_ciu_pp_pokex_s cn58xx;
1389 struct cvmx_ciu_pp_pokex_s cn58xxp1;
1390};
1391
1392union cvmx_ciu_pp_rst {
1393 uint64_t u64;
1394 struct cvmx_ciu_pp_rst_s {
1395 uint64_t reserved_16_63:48;
1396 uint64_t rst:15;
1397 uint64_t rst0:1;
1398 } s;
1399 struct cvmx_ciu_pp_rst_cn30xx {
1400 uint64_t reserved_1_63:63;
1401 uint64_t rst0:1;
1402 } cn30xx;
1403 struct cvmx_ciu_pp_rst_cn31xx {
1404 uint64_t reserved_2_63:62;
1405 uint64_t rst:1;
1406 uint64_t rst0:1;
1407 } cn31xx;
1408 struct cvmx_ciu_pp_rst_s cn38xx;
1409 struct cvmx_ciu_pp_rst_s cn38xxp2;
1410 struct cvmx_ciu_pp_rst_cn31xx cn50xx;
1411 struct cvmx_ciu_pp_rst_cn52xx {
1412 uint64_t reserved_4_63:60;
1413 uint64_t rst:3;
1414 uint64_t rst0:1;
1415 } cn52xx;
1416 struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
1417 struct cvmx_ciu_pp_rst_cn56xx {
1418 uint64_t reserved_12_63:52;
1419 uint64_t rst:11;
1420 uint64_t rst0:1;
1421 } cn56xx;
1422 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
1423 struct cvmx_ciu_pp_rst_s cn58xx;
1424 struct cvmx_ciu_pp_rst_s cn58xxp1;
1425};
1426
1427union cvmx_ciu_qlm_dcok {
1428 uint64_t u64;
1429 struct cvmx_ciu_qlm_dcok_s {
1430 uint64_t reserved_4_63:60;
1431 uint64_t qlm_dcok:4;
1432 } s;
1433 struct cvmx_ciu_qlm_dcok_cn52xx {
1434 uint64_t reserved_2_63:62;
1435 uint64_t qlm_dcok:2;
1436 } cn52xx;
1437 struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
1438 struct cvmx_ciu_qlm_dcok_s cn56xx;
1439 struct cvmx_ciu_qlm_dcok_s cn56xxp1;
1440};
1441
1442union cvmx_ciu_qlm_jtgc {
1443 uint64_t u64;
1444 struct cvmx_ciu_qlm_jtgc_s {
1445 uint64_t reserved_11_63:53;
1446 uint64_t clk_div:3;
1447 uint64_t reserved_6_7:2;
1448 uint64_t mux_sel:2;
1449 uint64_t bypass:4;
1450 } s;
1451 struct cvmx_ciu_qlm_jtgc_cn52xx {
1452 uint64_t reserved_11_63:53;
1453 uint64_t clk_div:3;
1454 uint64_t reserved_5_7:3;
1455 uint64_t mux_sel:1;
1456 uint64_t reserved_2_3:2;
1457 uint64_t bypass:2;
1458 } cn52xx;
1459 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
1460 struct cvmx_ciu_qlm_jtgc_s cn56xx;
1461 struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
1462};
1463
1464union cvmx_ciu_qlm_jtgd {
1465 uint64_t u64;
1466 struct cvmx_ciu_qlm_jtgd_s {
1467 uint64_t capture:1;
1468 uint64_t shift:1;
1469 uint64_t update:1;
1470 uint64_t reserved_44_60:17;
1471 uint64_t select:4;
1472 uint64_t reserved_37_39:3;
1473 uint64_t shft_cnt:5;
1474 uint64_t shft_reg:32;
1475 } s;
1476 struct cvmx_ciu_qlm_jtgd_cn52xx {
1477 uint64_t capture:1;
1478 uint64_t shift:1;
1479 uint64_t update:1;
1480 uint64_t reserved_42_60:19;
1481 uint64_t select:2;
1482 uint64_t reserved_37_39:3;
1483 uint64_t shft_cnt:5;
1484 uint64_t shft_reg:32;
1485 } cn52xx;
1486 struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
1487 struct cvmx_ciu_qlm_jtgd_s cn56xx;
1488 struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
1489 uint64_t capture:1;
1490 uint64_t shift:1;
1491 uint64_t update:1;
1492 uint64_t reserved_37_60:24;
1493 uint64_t shft_cnt:5;
1494 uint64_t shft_reg:32;
1495 } cn56xxp1;
1496};
1497
1498union cvmx_ciu_soft_bist {
1499 uint64_t u64;
1500 struct cvmx_ciu_soft_bist_s {
1501 uint64_t reserved_1_63:63;
1502 uint64_t soft_bist:1;
1503 } s;
1504 struct cvmx_ciu_soft_bist_s cn30xx;
1505 struct cvmx_ciu_soft_bist_s cn31xx;
1506 struct cvmx_ciu_soft_bist_s cn38xx;
1507 struct cvmx_ciu_soft_bist_s cn38xxp2;
1508 struct cvmx_ciu_soft_bist_s cn50xx;
1509 struct cvmx_ciu_soft_bist_s cn52xx;
1510 struct cvmx_ciu_soft_bist_s cn52xxp1;
1511 struct cvmx_ciu_soft_bist_s cn56xx;
1512 struct cvmx_ciu_soft_bist_s cn56xxp1;
1513 struct cvmx_ciu_soft_bist_s cn58xx;
1514 struct cvmx_ciu_soft_bist_s cn58xxp1;
1515};
1516
1517union cvmx_ciu_soft_prst {
1518 uint64_t u64;
1519 struct cvmx_ciu_soft_prst_s {
1520 uint64_t reserved_3_63:61;
1521 uint64_t host64:1;
1522 uint64_t npi:1;
1523 uint64_t soft_prst:1;
1524 } s;
1525 struct cvmx_ciu_soft_prst_s cn30xx;
1526 struct cvmx_ciu_soft_prst_s cn31xx;
1527 struct cvmx_ciu_soft_prst_s cn38xx;
1528 struct cvmx_ciu_soft_prst_s cn38xxp2;
1529 struct cvmx_ciu_soft_prst_s cn50xx;
1530 struct cvmx_ciu_soft_prst_cn52xx {
1531 uint64_t reserved_1_63:63;
1532 uint64_t soft_prst:1;
1533 } cn52xx;
1534 struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
1535 struct cvmx_ciu_soft_prst_cn52xx cn56xx;
1536 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
1537 struct cvmx_ciu_soft_prst_s cn58xx;
1538 struct cvmx_ciu_soft_prst_s cn58xxp1;
1539};
1540
1541union cvmx_ciu_soft_prst1 {
1542 uint64_t u64;
1543 struct cvmx_ciu_soft_prst1_s {
1544 uint64_t reserved_1_63:63;
1545 uint64_t soft_prst:1;
1546 } s;
1547 struct cvmx_ciu_soft_prst1_s cn52xx;
1548 struct cvmx_ciu_soft_prst1_s cn52xxp1;
1549 struct cvmx_ciu_soft_prst1_s cn56xx;
1550 struct cvmx_ciu_soft_prst1_s cn56xxp1;
1551};
1552
1553union cvmx_ciu_soft_rst {
1554 uint64_t u64;
1555 struct cvmx_ciu_soft_rst_s {
1556 uint64_t reserved_1_63:63;
1557 uint64_t soft_rst:1;
1558 } s;
1559 struct cvmx_ciu_soft_rst_s cn30xx;
1560 struct cvmx_ciu_soft_rst_s cn31xx;
1561 struct cvmx_ciu_soft_rst_s cn38xx;
1562 struct cvmx_ciu_soft_rst_s cn38xxp2;
1563 struct cvmx_ciu_soft_rst_s cn50xx;
1564 struct cvmx_ciu_soft_rst_s cn52xx;
1565 struct cvmx_ciu_soft_rst_s cn52xxp1;
1566 struct cvmx_ciu_soft_rst_s cn56xx;
1567 struct cvmx_ciu_soft_rst_s cn56xxp1;
1568 struct cvmx_ciu_soft_rst_s cn58xx;
1569 struct cvmx_ciu_soft_rst_s cn58xxp1;
1570};
1571
1572union cvmx_ciu_timx {
1573 uint64_t u64;
1574 struct cvmx_ciu_timx_s {
1575 uint64_t reserved_37_63:27;
1576 uint64_t one_shot:1;
1577 uint64_t len:36;
1578 } s;
1579 struct cvmx_ciu_timx_s cn30xx;
1580 struct cvmx_ciu_timx_s cn31xx;
1581 struct cvmx_ciu_timx_s cn38xx;
1582 struct cvmx_ciu_timx_s cn38xxp2;
1583 struct cvmx_ciu_timx_s cn50xx;
1584 struct cvmx_ciu_timx_s cn52xx;
1585 struct cvmx_ciu_timx_s cn52xxp1;
1586 struct cvmx_ciu_timx_s cn56xx;
1587 struct cvmx_ciu_timx_s cn56xxp1;
1588 struct cvmx_ciu_timx_s cn58xx;
1589 struct cvmx_ciu_timx_s cn58xxp1;
1590};
1591
1592union cvmx_ciu_wdogx {
1593 uint64_t u64;
1594 struct cvmx_ciu_wdogx_s {
1595 uint64_t reserved_46_63:18;
1596 uint64_t gstopen:1;
1597 uint64_t dstop:1;
1598 uint64_t cnt:24;
1599 uint64_t len:16;
1600 uint64_t state:2;
1601 uint64_t mode:2;
1602 } s;
1603 struct cvmx_ciu_wdogx_s cn30xx;
1604 struct cvmx_ciu_wdogx_s cn31xx;
1605 struct cvmx_ciu_wdogx_s cn38xx;
1606 struct cvmx_ciu_wdogx_s cn38xxp2;
1607 struct cvmx_ciu_wdogx_s cn50xx;
1608 struct cvmx_ciu_wdogx_s cn52xx;
1609 struct cvmx_ciu_wdogx_s cn52xxp1;
1610 struct cvmx_ciu_wdogx_s cn56xx;
1611 struct cvmx_ciu_wdogx_s cn56xxp1;
1612 struct cvmx_ciu_wdogx_s cn58xx;
1613 struct cvmx_ciu_wdogx_s cn58xxp1;
1614};
1615
1616#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
new file mode 100644
index 000000000000..5fdd6ba48a05
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -0,0 +1,219 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GPIO_DEFS_H__
29#define __CVMX_GPIO_DEFS_H__
30
31#define CVMX_GPIO_BIT_CFGX(offset) \
32 CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
33#define CVMX_GPIO_BOOT_ENA \
34 CVMX_ADD_IO_SEG(0x00010700000008A8ull)
35#define CVMX_GPIO_CLK_GENX(offset) \
36 CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
37#define CVMX_GPIO_DBG_ENA \
38 CVMX_ADD_IO_SEG(0x00010700000008A0ull)
39#define CVMX_GPIO_INT_CLR \
40 CVMX_ADD_IO_SEG(0x0001070000000898ull)
41#define CVMX_GPIO_RX_DAT \
42 CVMX_ADD_IO_SEG(0x0001070000000880ull)
43#define CVMX_GPIO_TX_CLR \
44 CVMX_ADD_IO_SEG(0x0001070000000890ull)
45#define CVMX_GPIO_TX_SET \
46 CVMX_ADD_IO_SEG(0x0001070000000888ull)
47#define CVMX_GPIO_XBIT_CFGX(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
49
50union cvmx_gpio_bit_cfgx {
51 uint64_t u64;
52 struct cvmx_gpio_bit_cfgx_s {
53 uint64_t reserved_15_63:49;
54 uint64_t clk_gen:1;
55 uint64_t clk_sel:2;
56 uint64_t fil_sel:4;
57 uint64_t fil_cnt:4;
58 uint64_t int_type:1;
59 uint64_t int_en:1;
60 uint64_t rx_xor:1;
61 uint64_t tx_oe:1;
62 } s;
63 struct cvmx_gpio_bit_cfgx_cn30xx {
64 uint64_t reserved_12_63:52;
65 uint64_t fil_sel:4;
66 uint64_t fil_cnt:4;
67 uint64_t int_type:1;
68 uint64_t int_en:1;
69 uint64_t rx_xor:1;
70 uint64_t tx_oe:1;
71 } cn30xx;
72 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
73 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
74 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
75 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
76 struct cvmx_gpio_bit_cfgx_s cn52xx;
77 struct cvmx_gpio_bit_cfgx_s cn52xxp1;
78 struct cvmx_gpio_bit_cfgx_s cn56xx;
79 struct cvmx_gpio_bit_cfgx_s cn56xxp1;
80 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
81 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
82};
83
84union cvmx_gpio_boot_ena {
85 uint64_t u64;
86 struct cvmx_gpio_boot_ena_s {
87 uint64_t reserved_12_63:52;
88 uint64_t boot_ena:4;
89 uint64_t reserved_0_7:8;
90 } s;
91 struct cvmx_gpio_boot_ena_s cn30xx;
92 struct cvmx_gpio_boot_ena_s cn31xx;
93 struct cvmx_gpio_boot_ena_s cn50xx;
94};
95
96union cvmx_gpio_clk_genx {
97 uint64_t u64;
98 struct cvmx_gpio_clk_genx_s {
99 uint64_t reserved_32_63:32;
100 uint64_t n:32;
101 } s;
102 struct cvmx_gpio_clk_genx_s cn52xx;
103 struct cvmx_gpio_clk_genx_s cn52xxp1;
104 struct cvmx_gpio_clk_genx_s cn56xx;
105 struct cvmx_gpio_clk_genx_s cn56xxp1;
106};
107
108union cvmx_gpio_dbg_ena {
109 uint64_t u64;
110 struct cvmx_gpio_dbg_ena_s {
111 uint64_t reserved_21_63:43;
112 uint64_t dbg_ena:21;
113 } s;
114 struct cvmx_gpio_dbg_ena_s cn30xx;
115 struct cvmx_gpio_dbg_ena_s cn31xx;
116 struct cvmx_gpio_dbg_ena_s cn50xx;
117};
118
119union cvmx_gpio_int_clr {
120 uint64_t u64;
121 struct cvmx_gpio_int_clr_s {
122 uint64_t reserved_16_63:48;
123 uint64_t type:16;
124 } s;
125 struct cvmx_gpio_int_clr_s cn30xx;
126 struct cvmx_gpio_int_clr_s cn31xx;
127 struct cvmx_gpio_int_clr_s cn38xx;
128 struct cvmx_gpio_int_clr_s cn38xxp2;
129 struct cvmx_gpio_int_clr_s cn50xx;
130 struct cvmx_gpio_int_clr_s cn52xx;
131 struct cvmx_gpio_int_clr_s cn52xxp1;
132 struct cvmx_gpio_int_clr_s cn56xx;
133 struct cvmx_gpio_int_clr_s cn56xxp1;
134 struct cvmx_gpio_int_clr_s cn58xx;
135 struct cvmx_gpio_int_clr_s cn58xxp1;
136};
137
138union cvmx_gpio_rx_dat {
139 uint64_t u64;
140 struct cvmx_gpio_rx_dat_s {
141 uint64_t reserved_24_63:40;
142 uint64_t dat:24;
143 } s;
144 struct cvmx_gpio_rx_dat_s cn30xx;
145 struct cvmx_gpio_rx_dat_s cn31xx;
146 struct cvmx_gpio_rx_dat_cn38xx {
147 uint64_t reserved_16_63:48;
148 uint64_t dat:16;
149 } cn38xx;
150 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
151 struct cvmx_gpio_rx_dat_s cn50xx;
152 struct cvmx_gpio_rx_dat_cn38xx cn52xx;
153 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
154 struct cvmx_gpio_rx_dat_cn38xx cn56xx;
155 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
156 struct cvmx_gpio_rx_dat_cn38xx cn58xx;
157 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
158};
159
160union cvmx_gpio_tx_clr {
161 uint64_t u64;
162 struct cvmx_gpio_tx_clr_s {
163 uint64_t reserved_24_63:40;
164 uint64_t clr:24;
165 } s;
166 struct cvmx_gpio_tx_clr_s cn30xx;
167 struct cvmx_gpio_tx_clr_s cn31xx;
168 struct cvmx_gpio_tx_clr_cn38xx {
169 uint64_t reserved_16_63:48;
170 uint64_t clr:16;
171 } cn38xx;
172 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
173 struct cvmx_gpio_tx_clr_s cn50xx;
174 struct cvmx_gpio_tx_clr_cn38xx cn52xx;
175 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
176 struct cvmx_gpio_tx_clr_cn38xx cn56xx;
177 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
178 struct cvmx_gpio_tx_clr_cn38xx cn58xx;
179 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
180};
181
182union cvmx_gpio_tx_set {
183 uint64_t u64;
184 struct cvmx_gpio_tx_set_s {
185 uint64_t reserved_24_63:40;
186 uint64_t set:24;
187 } s;
188 struct cvmx_gpio_tx_set_s cn30xx;
189 struct cvmx_gpio_tx_set_s cn31xx;
190 struct cvmx_gpio_tx_set_cn38xx {
191 uint64_t reserved_16_63:48;
192 uint64_t set:16;
193 } cn38xx;
194 struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
195 struct cvmx_gpio_tx_set_s cn50xx;
196 struct cvmx_gpio_tx_set_cn38xx cn52xx;
197 struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
198 struct cvmx_gpio_tx_set_cn38xx cn56xx;
199 struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
200 struct cvmx_gpio_tx_set_cn38xx cn58xx;
201 struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
202};
203
204union cvmx_gpio_xbit_cfgx {
205 uint64_t u64;
206 struct cvmx_gpio_xbit_cfgx_s {
207 uint64_t reserved_12_63:52;
208 uint64_t fil_sel:4;
209 uint64_t fil_cnt:4;
210 uint64_t reserved_2_3:2;
211 uint64_t rx_xor:1;
212 uint64_t tx_oe:1;
213 } s;
214 struct cvmx_gpio_xbit_cfgx_s cn30xx;
215 struct cvmx_gpio_xbit_cfgx_s cn31xx;
216 struct cvmx_gpio_xbit_cfgx_s cn50xx;
217};
218
219#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
new file mode 100644
index 000000000000..0ee36baec500
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -0,0 +1,530 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_IOB_DEFS_H__
29#define __CVMX_IOB_DEFS_H__
30
31#define CVMX_IOB_BIST_STATUS \
32 CVMX_ADD_IO_SEG(0x00011800F00007F8ull)
33#define CVMX_IOB_CTL_STATUS \
34 CVMX_ADD_IO_SEG(0x00011800F0000050ull)
35#define CVMX_IOB_DWB_PRI_CNT \
36 CVMX_ADD_IO_SEG(0x00011800F0000028ull)
37#define CVMX_IOB_FAU_TIMEOUT \
38 CVMX_ADD_IO_SEG(0x00011800F0000000ull)
39#define CVMX_IOB_I2C_PRI_CNT \
40 CVMX_ADD_IO_SEG(0x00011800F0000010ull)
41#define CVMX_IOB_INB_CONTROL_MATCH \
42 CVMX_ADD_IO_SEG(0x00011800F0000078ull)
43#define CVMX_IOB_INB_CONTROL_MATCH_ENB \
44 CVMX_ADD_IO_SEG(0x00011800F0000088ull)
45#define CVMX_IOB_INB_DATA_MATCH \
46 CVMX_ADD_IO_SEG(0x00011800F0000070ull)
47#define CVMX_IOB_INB_DATA_MATCH_ENB \
48 CVMX_ADD_IO_SEG(0x00011800F0000080ull)
49#define CVMX_IOB_INT_ENB \
50 CVMX_ADD_IO_SEG(0x00011800F0000060ull)
51#define CVMX_IOB_INT_SUM \
52 CVMX_ADD_IO_SEG(0x00011800F0000058ull)
53#define CVMX_IOB_N2C_L2C_PRI_CNT \
54 CVMX_ADD_IO_SEG(0x00011800F0000020ull)
55#define CVMX_IOB_N2C_RSP_PRI_CNT \
56 CVMX_ADD_IO_SEG(0x00011800F0000008ull)
57#define CVMX_IOB_OUTB_COM_PRI_CNT \
58 CVMX_ADD_IO_SEG(0x00011800F0000040ull)
59#define CVMX_IOB_OUTB_CONTROL_MATCH \
60 CVMX_ADD_IO_SEG(0x00011800F0000098ull)
61#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
62 CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
63#define CVMX_IOB_OUTB_DATA_MATCH \
64 CVMX_ADD_IO_SEG(0x00011800F0000090ull)
65#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
66 CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
67#define CVMX_IOB_OUTB_FPA_PRI_CNT \
68 CVMX_ADD_IO_SEG(0x00011800F0000048ull)
69#define CVMX_IOB_OUTB_REQ_PRI_CNT \
70 CVMX_ADD_IO_SEG(0x00011800F0000038ull)
71#define CVMX_IOB_P2C_REQ_PRI_CNT \
72 CVMX_ADD_IO_SEG(0x00011800F0000018ull)
73#define CVMX_IOB_PKT_ERR \
74 CVMX_ADD_IO_SEG(0x00011800F0000068ull)
75
76union cvmx_iob_bist_status {
77 uint64_t u64;
78 struct cvmx_iob_bist_status_s {
79 uint64_t reserved_18_63:46;
80 uint64_t icnrcb:1;
81 uint64_t icr0:1;
82 uint64_t icr1:1;
83 uint64_t icnr1:1;
84 uint64_t icnr0:1;
85 uint64_t ibdr0:1;
86 uint64_t ibdr1:1;
87 uint64_t ibr0:1;
88 uint64_t ibr1:1;
89 uint64_t icnrt:1;
90 uint64_t ibrq0:1;
91 uint64_t ibrq1:1;
92 uint64_t icrn0:1;
93 uint64_t icrn1:1;
94 uint64_t icrp0:1;
95 uint64_t icrp1:1;
96 uint64_t ibd:1;
97 uint64_t icd:1;
98 } s;
99 struct cvmx_iob_bist_status_s cn30xx;
100 struct cvmx_iob_bist_status_s cn31xx;
101 struct cvmx_iob_bist_status_s cn38xx;
102 struct cvmx_iob_bist_status_s cn38xxp2;
103 struct cvmx_iob_bist_status_s cn50xx;
104 struct cvmx_iob_bist_status_s cn52xx;
105 struct cvmx_iob_bist_status_s cn52xxp1;
106 struct cvmx_iob_bist_status_s cn56xx;
107 struct cvmx_iob_bist_status_s cn56xxp1;
108 struct cvmx_iob_bist_status_s cn58xx;
109 struct cvmx_iob_bist_status_s cn58xxp1;
110};
111
112union cvmx_iob_ctl_status {
113 uint64_t u64;
114 struct cvmx_iob_ctl_status_s {
115 uint64_t reserved_5_63:59;
116 uint64_t outb_mat:1;
117 uint64_t inb_mat:1;
118 uint64_t pko_enb:1;
119 uint64_t dwb_enb:1;
120 uint64_t fau_end:1;
121 } s;
122 struct cvmx_iob_ctl_status_s cn30xx;
123 struct cvmx_iob_ctl_status_s cn31xx;
124 struct cvmx_iob_ctl_status_s cn38xx;
125 struct cvmx_iob_ctl_status_s cn38xxp2;
126 struct cvmx_iob_ctl_status_s cn50xx;
127 struct cvmx_iob_ctl_status_s cn52xx;
128 struct cvmx_iob_ctl_status_s cn52xxp1;
129 struct cvmx_iob_ctl_status_s cn56xx;
130 struct cvmx_iob_ctl_status_s cn56xxp1;
131 struct cvmx_iob_ctl_status_s cn58xx;
132 struct cvmx_iob_ctl_status_s cn58xxp1;
133};
134
135union cvmx_iob_dwb_pri_cnt {
136 uint64_t u64;
137 struct cvmx_iob_dwb_pri_cnt_s {
138 uint64_t reserved_16_63:48;
139 uint64_t cnt_enb:1;
140 uint64_t cnt_val:15;
141 } s;
142 struct cvmx_iob_dwb_pri_cnt_s cn38xx;
143 struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
144 struct cvmx_iob_dwb_pri_cnt_s cn52xx;
145 struct cvmx_iob_dwb_pri_cnt_s cn52xxp1;
146 struct cvmx_iob_dwb_pri_cnt_s cn56xx;
147 struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
148 struct cvmx_iob_dwb_pri_cnt_s cn58xx;
149 struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
150};
151
152union cvmx_iob_fau_timeout {
153 uint64_t u64;
154 struct cvmx_iob_fau_timeout_s {
155 uint64_t reserved_13_63:51;
156 uint64_t tout_enb:1;
157 uint64_t tout_val:12;
158 } s;
159 struct cvmx_iob_fau_timeout_s cn30xx;
160 struct cvmx_iob_fau_timeout_s cn31xx;
161 struct cvmx_iob_fau_timeout_s cn38xx;
162 struct cvmx_iob_fau_timeout_s cn38xxp2;
163 struct cvmx_iob_fau_timeout_s cn50xx;
164 struct cvmx_iob_fau_timeout_s cn52xx;
165 struct cvmx_iob_fau_timeout_s cn52xxp1;
166 struct cvmx_iob_fau_timeout_s cn56xx;
167 struct cvmx_iob_fau_timeout_s cn56xxp1;
168 struct cvmx_iob_fau_timeout_s cn58xx;
169 struct cvmx_iob_fau_timeout_s cn58xxp1;
170};
171
172union cvmx_iob_i2c_pri_cnt {
173 uint64_t u64;
174 struct cvmx_iob_i2c_pri_cnt_s {
175 uint64_t reserved_16_63:48;
176 uint64_t cnt_enb:1;
177 uint64_t cnt_val:15;
178 } s;
179 struct cvmx_iob_i2c_pri_cnt_s cn38xx;
180 struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
181 struct cvmx_iob_i2c_pri_cnt_s cn52xx;
182 struct cvmx_iob_i2c_pri_cnt_s cn52xxp1;
183 struct cvmx_iob_i2c_pri_cnt_s cn56xx;
184 struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
185 struct cvmx_iob_i2c_pri_cnt_s cn58xx;
186 struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
187};
188
189union cvmx_iob_inb_control_match {
190 uint64_t u64;
191 struct cvmx_iob_inb_control_match_s {
192 uint64_t reserved_29_63:35;
193 uint64_t mask:8;
194 uint64_t opc:4;
195 uint64_t dst:9;
196 uint64_t src:8;
197 } s;
198 struct cvmx_iob_inb_control_match_s cn30xx;
199 struct cvmx_iob_inb_control_match_s cn31xx;
200 struct cvmx_iob_inb_control_match_s cn38xx;
201 struct cvmx_iob_inb_control_match_s cn38xxp2;
202 struct cvmx_iob_inb_control_match_s cn50xx;
203 struct cvmx_iob_inb_control_match_s cn52xx;
204 struct cvmx_iob_inb_control_match_s cn52xxp1;
205 struct cvmx_iob_inb_control_match_s cn56xx;
206 struct cvmx_iob_inb_control_match_s cn56xxp1;
207 struct cvmx_iob_inb_control_match_s cn58xx;
208 struct cvmx_iob_inb_control_match_s cn58xxp1;
209};
210
211union cvmx_iob_inb_control_match_enb {
212 uint64_t u64;
213 struct cvmx_iob_inb_control_match_enb_s {
214 uint64_t reserved_29_63:35;
215 uint64_t mask:8;
216 uint64_t opc:4;
217 uint64_t dst:9;
218 uint64_t src:8;
219 } s;
220 struct cvmx_iob_inb_control_match_enb_s cn30xx;
221 struct cvmx_iob_inb_control_match_enb_s cn31xx;
222 struct cvmx_iob_inb_control_match_enb_s cn38xx;
223 struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
224 struct cvmx_iob_inb_control_match_enb_s cn50xx;
225 struct cvmx_iob_inb_control_match_enb_s cn52xx;
226 struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
227 struct cvmx_iob_inb_control_match_enb_s cn56xx;
228 struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
229 struct cvmx_iob_inb_control_match_enb_s cn58xx;
230 struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
231};
232
233union cvmx_iob_inb_data_match {
234 uint64_t u64;
235 struct cvmx_iob_inb_data_match_s {
236 uint64_t data:64;
237 } s;
238 struct cvmx_iob_inb_data_match_s cn30xx;
239 struct cvmx_iob_inb_data_match_s cn31xx;
240 struct cvmx_iob_inb_data_match_s cn38xx;
241 struct cvmx_iob_inb_data_match_s cn38xxp2;
242 struct cvmx_iob_inb_data_match_s cn50xx;
243 struct cvmx_iob_inb_data_match_s cn52xx;
244 struct cvmx_iob_inb_data_match_s cn52xxp1;
245 struct cvmx_iob_inb_data_match_s cn56xx;
246 struct cvmx_iob_inb_data_match_s cn56xxp1;
247 struct cvmx_iob_inb_data_match_s cn58xx;
248 struct cvmx_iob_inb_data_match_s cn58xxp1;
249};
250
251union cvmx_iob_inb_data_match_enb {
252 uint64_t u64;
253 struct cvmx_iob_inb_data_match_enb_s {
254 uint64_t data:64;
255 } s;
256 struct cvmx_iob_inb_data_match_enb_s cn30xx;
257 struct cvmx_iob_inb_data_match_enb_s cn31xx;
258 struct cvmx_iob_inb_data_match_enb_s cn38xx;
259 struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
260 struct cvmx_iob_inb_data_match_enb_s cn50xx;
261 struct cvmx_iob_inb_data_match_enb_s cn52xx;
262 struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
263 struct cvmx_iob_inb_data_match_enb_s cn56xx;
264 struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
265 struct cvmx_iob_inb_data_match_enb_s cn58xx;
266 struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
267};
268
269union cvmx_iob_int_enb {
270 uint64_t u64;
271 struct cvmx_iob_int_enb_s {
272 uint64_t reserved_6_63:58;
273 uint64_t p_dat:1;
274 uint64_t np_dat:1;
275 uint64_t p_eop:1;
276 uint64_t p_sop:1;
277 uint64_t np_eop:1;
278 uint64_t np_sop:1;
279 } s;
280 struct cvmx_iob_int_enb_cn30xx {
281 uint64_t reserved_4_63:60;
282 uint64_t p_eop:1;
283 uint64_t p_sop:1;
284 uint64_t np_eop:1;
285 uint64_t np_sop:1;
286 } cn30xx;
287 struct cvmx_iob_int_enb_cn30xx cn31xx;
288 struct cvmx_iob_int_enb_cn30xx cn38xx;
289 struct cvmx_iob_int_enb_cn30xx cn38xxp2;
290 struct cvmx_iob_int_enb_s cn50xx;
291 struct cvmx_iob_int_enb_s cn52xx;
292 struct cvmx_iob_int_enb_s cn52xxp1;
293 struct cvmx_iob_int_enb_s cn56xx;
294 struct cvmx_iob_int_enb_s cn56xxp1;
295 struct cvmx_iob_int_enb_s cn58xx;
296 struct cvmx_iob_int_enb_s cn58xxp1;
297};
298
299union cvmx_iob_int_sum {
300 uint64_t u64;
301 struct cvmx_iob_int_sum_s {
302 uint64_t reserved_6_63:58;
303 uint64_t p_dat:1;
304 uint64_t np_dat:1;
305 uint64_t p_eop:1;
306 uint64_t p_sop:1;
307 uint64_t np_eop:1;
308 uint64_t np_sop:1;
309 } s;
310 struct cvmx_iob_int_sum_cn30xx {
311 uint64_t reserved_4_63:60;
312 uint64_t p_eop:1;
313 uint64_t p_sop:1;
314 uint64_t np_eop:1;
315 uint64_t np_sop:1;
316 } cn30xx;
317 struct cvmx_iob_int_sum_cn30xx cn31xx;
318 struct cvmx_iob_int_sum_cn30xx cn38xx;
319 struct cvmx_iob_int_sum_cn30xx cn38xxp2;
320 struct cvmx_iob_int_sum_s cn50xx;
321 struct cvmx_iob_int_sum_s cn52xx;
322 struct cvmx_iob_int_sum_s cn52xxp1;
323 struct cvmx_iob_int_sum_s cn56xx;
324 struct cvmx_iob_int_sum_s cn56xxp1;
325 struct cvmx_iob_int_sum_s cn58xx;
326 struct cvmx_iob_int_sum_s cn58xxp1;
327};
328
329union cvmx_iob_n2c_l2c_pri_cnt {
330 uint64_t u64;
331 struct cvmx_iob_n2c_l2c_pri_cnt_s {
332 uint64_t reserved_16_63:48;
333 uint64_t cnt_enb:1;
334 uint64_t cnt_val:15;
335 } s;
336 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
337 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
338 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx;
339 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1;
340 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx;
341 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
342 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
343 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
344};
345
346union cvmx_iob_n2c_rsp_pri_cnt {
347 uint64_t u64;
348 struct cvmx_iob_n2c_rsp_pri_cnt_s {
349 uint64_t reserved_16_63:48;
350 uint64_t cnt_enb:1;
351 uint64_t cnt_val:15;
352 } s;
353 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
354 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
355 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx;
356 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1;
357 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx;
358 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
359 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
360 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
361};
362
363union cvmx_iob_outb_com_pri_cnt {
364 uint64_t u64;
365 struct cvmx_iob_outb_com_pri_cnt_s {
366 uint64_t reserved_16_63:48;
367 uint64_t cnt_enb:1;
368 uint64_t cnt_val:15;
369 } s;
370 struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
371 struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
372 struct cvmx_iob_outb_com_pri_cnt_s cn52xx;
373 struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1;
374 struct cvmx_iob_outb_com_pri_cnt_s cn56xx;
375 struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
376 struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
377 struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
378};
379
380union cvmx_iob_outb_control_match {
381 uint64_t u64;
382 struct cvmx_iob_outb_control_match_s {
383 uint64_t reserved_26_63:38;
384 uint64_t mask:8;
385 uint64_t eot:1;
386 uint64_t dst:8;
387 uint64_t src:9;
388 } s;
389 struct cvmx_iob_outb_control_match_s cn30xx;
390 struct cvmx_iob_outb_control_match_s cn31xx;
391 struct cvmx_iob_outb_control_match_s cn38xx;
392 struct cvmx_iob_outb_control_match_s cn38xxp2;
393 struct cvmx_iob_outb_control_match_s cn50xx;
394 struct cvmx_iob_outb_control_match_s cn52xx;
395 struct cvmx_iob_outb_control_match_s cn52xxp1;
396 struct cvmx_iob_outb_control_match_s cn56xx;
397 struct cvmx_iob_outb_control_match_s cn56xxp1;
398 struct cvmx_iob_outb_control_match_s cn58xx;
399 struct cvmx_iob_outb_control_match_s cn58xxp1;
400};
401
402union cvmx_iob_outb_control_match_enb {
403 uint64_t u64;
404 struct cvmx_iob_outb_control_match_enb_s {
405 uint64_t reserved_26_63:38;
406 uint64_t mask:8;
407 uint64_t eot:1;
408 uint64_t dst:8;
409 uint64_t src:9;
410 } s;
411 struct cvmx_iob_outb_control_match_enb_s cn30xx;
412 struct cvmx_iob_outb_control_match_enb_s cn31xx;
413 struct cvmx_iob_outb_control_match_enb_s cn38xx;
414 struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
415 struct cvmx_iob_outb_control_match_enb_s cn50xx;
416 struct cvmx_iob_outb_control_match_enb_s cn52xx;
417 struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
418 struct cvmx_iob_outb_control_match_enb_s cn56xx;
419 struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
420 struct cvmx_iob_outb_control_match_enb_s cn58xx;
421 struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
422};
423
424union cvmx_iob_outb_data_match {
425 uint64_t u64;
426 struct cvmx_iob_outb_data_match_s {
427 uint64_t data:64;
428 } s;
429 struct cvmx_iob_outb_data_match_s cn30xx;
430 struct cvmx_iob_outb_data_match_s cn31xx;
431 struct cvmx_iob_outb_data_match_s cn38xx;
432 struct cvmx_iob_outb_data_match_s cn38xxp2;
433 struct cvmx_iob_outb_data_match_s cn50xx;
434 struct cvmx_iob_outb_data_match_s cn52xx;
435 struct cvmx_iob_outb_data_match_s cn52xxp1;
436 struct cvmx_iob_outb_data_match_s cn56xx;
437 struct cvmx_iob_outb_data_match_s cn56xxp1;
438 struct cvmx_iob_outb_data_match_s cn58xx;
439 struct cvmx_iob_outb_data_match_s cn58xxp1;
440};
441
442union cvmx_iob_outb_data_match_enb {
443 uint64_t u64;
444 struct cvmx_iob_outb_data_match_enb_s {
445 uint64_t data:64;
446 } s;
447 struct cvmx_iob_outb_data_match_enb_s cn30xx;
448 struct cvmx_iob_outb_data_match_enb_s cn31xx;
449 struct cvmx_iob_outb_data_match_enb_s cn38xx;
450 struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
451 struct cvmx_iob_outb_data_match_enb_s cn50xx;
452 struct cvmx_iob_outb_data_match_enb_s cn52xx;
453 struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
454 struct cvmx_iob_outb_data_match_enb_s cn56xx;
455 struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
456 struct cvmx_iob_outb_data_match_enb_s cn58xx;
457 struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
458};
459
460union cvmx_iob_outb_fpa_pri_cnt {
461 uint64_t u64;
462 struct cvmx_iob_outb_fpa_pri_cnt_s {
463 uint64_t reserved_16_63:48;
464 uint64_t cnt_enb:1;
465 uint64_t cnt_val:15;
466 } s;
467 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
468 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
469 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx;
470 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1;
471 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx;
472 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
473 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
474 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
475};
476
477union cvmx_iob_outb_req_pri_cnt {
478 uint64_t u64;
479 struct cvmx_iob_outb_req_pri_cnt_s {
480 uint64_t reserved_16_63:48;
481 uint64_t cnt_enb:1;
482 uint64_t cnt_val:15;
483 } s;
484 struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
485 struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
486 struct cvmx_iob_outb_req_pri_cnt_s cn52xx;
487 struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1;
488 struct cvmx_iob_outb_req_pri_cnt_s cn56xx;
489 struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
490 struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
491 struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
492};
493
494union cvmx_iob_p2c_req_pri_cnt {
495 uint64_t u64;
496 struct cvmx_iob_p2c_req_pri_cnt_s {
497 uint64_t reserved_16_63:48;
498 uint64_t cnt_enb:1;
499 uint64_t cnt_val:15;
500 } s;
501 struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
502 struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
503 struct cvmx_iob_p2c_req_pri_cnt_s cn52xx;
504 struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1;
505 struct cvmx_iob_p2c_req_pri_cnt_s cn56xx;
506 struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
507 struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
508 struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
509};
510
511union cvmx_iob_pkt_err {
512 uint64_t u64;
513 struct cvmx_iob_pkt_err_s {
514 uint64_t reserved_6_63:58;
515 uint64_t port:6;
516 } s;
517 struct cvmx_iob_pkt_err_s cn30xx;
518 struct cvmx_iob_pkt_err_s cn31xx;
519 struct cvmx_iob_pkt_err_s cn38xx;
520 struct cvmx_iob_pkt_err_s cn38xxp2;
521 struct cvmx_iob_pkt_err_s cn50xx;
522 struct cvmx_iob_pkt_err_s cn52xx;
523 struct cvmx_iob_pkt_err_s cn52xxp1;
524 struct cvmx_iob_pkt_err_s cn56xx;
525 struct cvmx_iob_pkt_err_s cn56xxp1;
526 struct cvmx_iob_pkt_err_s cn58xx;
527 struct cvmx_iob_pkt_err_s cn58xxp1;
528};
529
530#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
new file mode 100644
index 000000000000..f8b8fc657d2c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -0,0 +1,877 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_IPD_DEFS_H__
29#define __CVMX_IPD_DEFS_H__
30
31#define CVMX_IPD_1ST_MBUFF_SKIP \
32 CVMX_ADD_IO_SEG(0x00014F0000000000ull)
33#define CVMX_IPD_1st_NEXT_PTR_BACK \
34 CVMX_ADD_IO_SEG(0x00014F0000000150ull)
35#define CVMX_IPD_2nd_NEXT_PTR_BACK \
36 CVMX_ADD_IO_SEG(0x00014F0000000158ull)
37#define CVMX_IPD_BIST_STATUS \
38 CVMX_ADD_IO_SEG(0x00014F00000007F8ull)
39#define CVMX_IPD_BP_PRT_RED_END \
40 CVMX_ADD_IO_SEG(0x00014F0000000328ull)
41#define CVMX_IPD_CLK_COUNT \
42 CVMX_ADD_IO_SEG(0x00014F0000000338ull)
43#define CVMX_IPD_CTL_STATUS \
44 CVMX_ADD_IO_SEG(0x00014F0000000018ull)
45#define CVMX_IPD_INT_ENB \
46 CVMX_ADD_IO_SEG(0x00014F0000000160ull)
47#define CVMX_IPD_INT_SUM \
48 CVMX_ADD_IO_SEG(0x00014F0000000168ull)
49#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \
50 CVMX_ADD_IO_SEG(0x00014F0000000008ull)
51#define CVMX_IPD_PACKET_MBUFF_SIZE \
52 CVMX_ADD_IO_SEG(0x00014F0000000010ull)
53#define CVMX_IPD_PKT_PTR_VALID \
54 CVMX_ADD_IO_SEG(0x00014F0000000358ull)
55#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \
56 CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8))
57#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \
58 CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36)
59#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \
60 CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36)
61#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \
62 CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8))
63#define CVMX_IPD_PORT_QOS_INTX(offset) \
64 CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8))
65#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \
66 CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8))
67#define CVMX_IPD_PORT_QOS_X_CNT(offset) \
68 CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8))
69#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \
70 CVMX_ADD_IO_SEG(0x00014F0000000348ull)
71#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \
72 CVMX_ADD_IO_SEG(0x00014F0000000350ull)
73#define CVMX_IPD_PTR_COUNT \
74 CVMX_ADD_IO_SEG(0x00014F0000000320ull)
75#define CVMX_IPD_PWP_PTR_FIFO_CTL \
76 CVMX_ADD_IO_SEG(0x00014F0000000340ull)
77#define CVMX_IPD_QOS0_RED_MARKS \
78 CVMX_ADD_IO_SEG(0x00014F0000000178ull)
79#define CVMX_IPD_QOS1_RED_MARKS \
80 CVMX_ADD_IO_SEG(0x00014F0000000180ull)
81#define CVMX_IPD_QOS2_RED_MARKS \
82 CVMX_ADD_IO_SEG(0x00014F0000000188ull)
83#define CVMX_IPD_QOS3_RED_MARKS \
84 CVMX_ADD_IO_SEG(0x00014F0000000190ull)
85#define CVMX_IPD_QOS4_RED_MARKS \
86 CVMX_ADD_IO_SEG(0x00014F0000000198ull)
87#define CVMX_IPD_QOS5_RED_MARKS \
88 CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
89#define CVMX_IPD_QOS6_RED_MARKS \
90 CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
91#define CVMX_IPD_QOS7_RED_MARKS \
92 CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
93#define CVMX_IPD_QOSX_RED_MARKS(offset) \
94 CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
95#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
96 CVMX_ADD_IO_SEG(0x00014F0000000330ull)
97#define CVMX_IPD_RED_PORT_ENABLE \
98 CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
99#define CVMX_IPD_RED_PORT_ENABLE2 \
100 CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
101#define CVMX_IPD_RED_QUE0_PARAM \
102 CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
103#define CVMX_IPD_RED_QUE1_PARAM \
104 CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
105#define CVMX_IPD_RED_QUE2_PARAM \
106 CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
107#define CVMX_IPD_RED_QUE3_PARAM \
108 CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
109#define CVMX_IPD_RED_QUE4_PARAM \
110 CVMX_ADD_IO_SEG(0x00014F0000000300ull)
111#define CVMX_IPD_RED_QUE5_PARAM \
112 CVMX_ADD_IO_SEG(0x00014F0000000308ull)
113#define CVMX_IPD_RED_QUE6_PARAM \
114 CVMX_ADD_IO_SEG(0x00014F0000000310ull)
115#define CVMX_IPD_RED_QUE7_PARAM \
116 CVMX_ADD_IO_SEG(0x00014F0000000318ull)
117#define CVMX_IPD_RED_QUEX_PARAM(offset) \
118 CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
119#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
120 CVMX_ADD_IO_SEG(0x00014F0000000148ull)
121#define CVMX_IPD_SUB_PORT_FCS \
122 CVMX_ADD_IO_SEG(0x00014F0000000170ull)
123#define CVMX_IPD_SUB_PORT_QOS_CNT \
124 CVMX_ADD_IO_SEG(0x00014F0000000800ull)
125#define CVMX_IPD_WQE_FPA_QUEUE \
126 CVMX_ADD_IO_SEG(0x00014F0000000020ull)
127#define CVMX_IPD_WQE_PTR_VALID \
128 CVMX_ADD_IO_SEG(0x00014F0000000360ull)
129
130union cvmx_ipd_1st_mbuff_skip {
131 uint64_t u64;
132 struct cvmx_ipd_1st_mbuff_skip_s {
133 uint64_t reserved_6_63:58;
134 uint64_t skip_sz:6;
135 } s;
136 struct cvmx_ipd_1st_mbuff_skip_s cn30xx;
137 struct cvmx_ipd_1st_mbuff_skip_s cn31xx;
138 struct cvmx_ipd_1st_mbuff_skip_s cn38xx;
139 struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2;
140 struct cvmx_ipd_1st_mbuff_skip_s cn50xx;
141 struct cvmx_ipd_1st_mbuff_skip_s cn52xx;
142 struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1;
143 struct cvmx_ipd_1st_mbuff_skip_s cn56xx;
144 struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
145 struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
146 struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
147};
148
149union cvmx_ipd_1st_next_ptr_back {
150 uint64_t u64;
151 struct cvmx_ipd_1st_next_ptr_back_s {
152 uint64_t reserved_4_63:60;
153 uint64_t back:4;
154 } s;
155 struct cvmx_ipd_1st_next_ptr_back_s cn30xx;
156 struct cvmx_ipd_1st_next_ptr_back_s cn31xx;
157 struct cvmx_ipd_1st_next_ptr_back_s cn38xx;
158 struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2;
159 struct cvmx_ipd_1st_next_ptr_back_s cn50xx;
160 struct cvmx_ipd_1st_next_ptr_back_s cn52xx;
161 struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1;
162 struct cvmx_ipd_1st_next_ptr_back_s cn56xx;
163 struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
164 struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
165 struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
166};
167
168union cvmx_ipd_2nd_next_ptr_back {
169 uint64_t u64;
170 struct cvmx_ipd_2nd_next_ptr_back_s {
171 uint64_t reserved_4_63:60;
172 uint64_t back:4;
173 } s;
174 struct cvmx_ipd_2nd_next_ptr_back_s cn30xx;
175 struct cvmx_ipd_2nd_next_ptr_back_s cn31xx;
176 struct cvmx_ipd_2nd_next_ptr_back_s cn38xx;
177 struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2;
178 struct cvmx_ipd_2nd_next_ptr_back_s cn50xx;
179 struct cvmx_ipd_2nd_next_ptr_back_s cn52xx;
180 struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1;
181 struct cvmx_ipd_2nd_next_ptr_back_s cn56xx;
182 struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
183 struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
184 struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
185};
186
187union cvmx_ipd_bist_status {
188 uint64_t u64;
189 struct cvmx_ipd_bist_status_s {
190 uint64_t reserved_18_63:46;
191 uint64_t csr_mem:1;
192 uint64_t csr_ncmd:1;
193 uint64_t pwq_wqed:1;
194 uint64_t pwq_wp1:1;
195 uint64_t pwq_pow:1;
196 uint64_t ipq_pbe1:1;
197 uint64_t ipq_pbe0:1;
198 uint64_t pbm3:1;
199 uint64_t pbm2:1;
200 uint64_t pbm1:1;
201 uint64_t pbm0:1;
202 uint64_t pbm_word:1;
203 uint64_t pwq1:1;
204 uint64_t pwq0:1;
205 uint64_t prc_off:1;
206 uint64_t ipd_old:1;
207 uint64_t ipd_new:1;
208 uint64_t pwp:1;
209 } s;
210 struct cvmx_ipd_bist_status_cn30xx {
211 uint64_t reserved_16_63:48;
212 uint64_t pwq_wqed:1;
213 uint64_t pwq_wp1:1;
214 uint64_t pwq_pow:1;
215 uint64_t ipq_pbe1:1;
216 uint64_t ipq_pbe0:1;
217 uint64_t pbm3:1;
218 uint64_t pbm2:1;
219 uint64_t pbm1:1;
220 uint64_t pbm0:1;
221 uint64_t pbm_word:1;
222 uint64_t pwq1:1;
223 uint64_t pwq0:1;
224 uint64_t prc_off:1;
225 uint64_t ipd_old:1;
226 uint64_t ipd_new:1;
227 uint64_t pwp:1;
228 } cn30xx;
229 struct cvmx_ipd_bist_status_cn30xx cn31xx;
230 struct cvmx_ipd_bist_status_cn30xx cn38xx;
231 struct cvmx_ipd_bist_status_cn30xx cn38xxp2;
232 struct cvmx_ipd_bist_status_cn30xx cn50xx;
233 struct cvmx_ipd_bist_status_s cn52xx;
234 struct cvmx_ipd_bist_status_s cn52xxp1;
235 struct cvmx_ipd_bist_status_s cn56xx;
236 struct cvmx_ipd_bist_status_s cn56xxp1;
237 struct cvmx_ipd_bist_status_cn30xx cn58xx;
238 struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
239};
240
241union cvmx_ipd_bp_prt_red_end {
242 uint64_t u64;
243 struct cvmx_ipd_bp_prt_red_end_s {
244 uint64_t reserved_40_63:24;
245 uint64_t prt_enb:40;
246 } s;
247 struct cvmx_ipd_bp_prt_red_end_cn30xx {
248 uint64_t reserved_36_63:28;
249 uint64_t prt_enb:36;
250 } cn30xx;
251 struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
252 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
253 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
254 struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
255 struct cvmx_ipd_bp_prt_red_end_s cn52xx;
256 struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
257 struct cvmx_ipd_bp_prt_red_end_s cn56xx;
258 struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
259 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
260 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
261};
262
263union cvmx_ipd_clk_count {
264 uint64_t u64;
265 struct cvmx_ipd_clk_count_s {
266 uint64_t clk_cnt:64;
267 } s;
268 struct cvmx_ipd_clk_count_s cn30xx;
269 struct cvmx_ipd_clk_count_s cn31xx;
270 struct cvmx_ipd_clk_count_s cn38xx;
271 struct cvmx_ipd_clk_count_s cn38xxp2;
272 struct cvmx_ipd_clk_count_s cn50xx;
273 struct cvmx_ipd_clk_count_s cn52xx;
274 struct cvmx_ipd_clk_count_s cn52xxp1;
275 struct cvmx_ipd_clk_count_s cn56xx;
276 struct cvmx_ipd_clk_count_s cn56xxp1;
277 struct cvmx_ipd_clk_count_s cn58xx;
278 struct cvmx_ipd_clk_count_s cn58xxp1;
279};
280
281union cvmx_ipd_ctl_status {
282 uint64_t u64;
283 struct cvmx_ipd_ctl_status_s {
284 uint64_t reserved_15_63:49;
285 uint64_t no_wptr:1;
286 uint64_t pq_apkt:1;
287 uint64_t pq_nabuf:1;
288 uint64_t ipd_full:1;
289 uint64_t pkt_off:1;
290 uint64_t len_m8:1;
291 uint64_t reset:1;
292 uint64_t addpkt:1;
293 uint64_t naddbuf:1;
294 uint64_t pkt_lend:1;
295 uint64_t wqe_lend:1;
296 uint64_t pbp_en:1;
297 uint64_t opc_mode:2;
298 uint64_t ipd_en:1;
299 } s;
300 struct cvmx_ipd_ctl_status_cn30xx {
301 uint64_t reserved_10_63:54;
302 uint64_t len_m8:1;
303 uint64_t reset:1;
304 uint64_t addpkt:1;
305 uint64_t naddbuf:1;
306 uint64_t pkt_lend:1;
307 uint64_t wqe_lend:1;
308 uint64_t pbp_en:1;
309 uint64_t opc_mode:2;
310 uint64_t ipd_en:1;
311 } cn30xx;
312 struct cvmx_ipd_ctl_status_cn30xx cn31xx;
313 struct cvmx_ipd_ctl_status_cn30xx cn38xx;
314 struct cvmx_ipd_ctl_status_cn38xxp2 {
315 uint64_t reserved_9_63:55;
316 uint64_t reset:1;
317 uint64_t addpkt:1;
318 uint64_t naddbuf:1;
319 uint64_t pkt_lend:1;
320 uint64_t wqe_lend:1;
321 uint64_t pbp_en:1;
322 uint64_t opc_mode:2;
323 uint64_t ipd_en:1;
324 } cn38xxp2;
325 struct cvmx_ipd_ctl_status_s cn50xx;
326 struct cvmx_ipd_ctl_status_s cn52xx;
327 struct cvmx_ipd_ctl_status_s cn52xxp1;
328 struct cvmx_ipd_ctl_status_s cn56xx;
329 struct cvmx_ipd_ctl_status_s cn56xxp1;
330 struct cvmx_ipd_ctl_status_cn58xx {
331 uint64_t reserved_12_63:52;
332 uint64_t ipd_full:1;
333 uint64_t pkt_off:1;
334 uint64_t len_m8:1;
335 uint64_t reset:1;
336 uint64_t addpkt:1;
337 uint64_t naddbuf:1;
338 uint64_t pkt_lend:1;
339 uint64_t wqe_lend:1;
340 uint64_t pbp_en:1;
341 uint64_t opc_mode:2;
342 uint64_t ipd_en:1;
343 } cn58xx;
344 struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
345};
346
347union cvmx_ipd_int_enb {
348 uint64_t u64;
349 struct cvmx_ipd_int_enb_s {
350 uint64_t reserved_12_63:52;
351 uint64_t pq_sub:1;
352 uint64_t pq_add:1;
353 uint64_t bc_ovr:1;
354 uint64_t d_coll:1;
355 uint64_t c_coll:1;
356 uint64_t cc_ovr:1;
357 uint64_t dc_ovr:1;
358 uint64_t bp_sub:1;
359 uint64_t prc_par3:1;
360 uint64_t prc_par2:1;
361 uint64_t prc_par1:1;
362 uint64_t prc_par0:1;
363 } s;
364 struct cvmx_ipd_int_enb_cn30xx {
365 uint64_t reserved_5_63:59;
366 uint64_t bp_sub:1;
367 uint64_t prc_par3:1;
368 uint64_t prc_par2:1;
369 uint64_t prc_par1:1;
370 uint64_t prc_par0:1;
371 } cn30xx;
372 struct cvmx_ipd_int_enb_cn30xx cn31xx;
373 struct cvmx_ipd_int_enb_cn38xx {
374 uint64_t reserved_10_63:54;
375 uint64_t bc_ovr:1;
376 uint64_t d_coll:1;
377 uint64_t c_coll:1;
378 uint64_t cc_ovr:1;
379 uint64_t dc_ovr:1;
380 uint64_t bp_sub:1;
381 uint64_t prc_par3:1;
382 uint64_t prc_par2:1;
383 uint64_t prc_par1:1;
384 uint64_t prc_par0:1;
385 } cn38xx;
386 struct cvmx_ipd_int_enb_cn30xx cn38xxp2;
387 struct cvmx_ipd_int_enb_cn38xx cn50xx;
388 struct cvmx_ipd_int_enb_s cn52xx;
389 struct cvmx_ipd_int_enb_s cn52xxp1;
390 struct cvmx_ipd_int_enb_s cn56xx;
391 struct cvmx_ipd_int_enb_s cn56xxp1;
392 struct cvmx_ipd_int_enb_cn38xx cn58xx;
393 struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
394};
395
396union cvmx_ipd_int_sum {
397 uint64_t u64;
398 struct cvmx_ipd_int_sum_s {
399 uint64_t reserved_12_63:52;
400 uint64_t pq_sub:1;
401 uint64_t pq_add:1;
402 uint64_t bc_ovr:1;
403 uint64_t d_coll:1;
404 uint64_t c_coll:1;
405 uint64_t cc_ovr:1;
406 uint64_t dc_ovr:1;
407 uint64_t bp_sub:1;
408 uint64_t prc_par3:1;
409 uint64_t prc_par2:1;
410 uint64_t prc_par1:1;
411 uint64_t prc_par0:1;
412 } s;
413 struct cvmx_ipd_int_sum_cn30xx {
414 uint64_t reserved_5_63:59;
415 uint64_t bp_sub:1;
416 uint64_t prc_par3:1;
417 uint64_t prc_par2:1;
418 uint64_t prc_par1:1;
419 uint64_t prc_par0:1;
420 } cn30xx;
421 struct cvmx_ipd_int_sum_cn30xx cn31xx;
422 struct cvmx_ipd_int_sum_cn38xx {
423 uint64_t reserved_10_63:54;
424 uint64_t bc_ovr:1;
425 uint64_t d_coll:1;
426 uint64_t c_coll:1;
427 uint64_t cc_ovr:1;
428 uint64_t dc_ovr:1;
429 uint64_t bp_sub:1;
430 uint64_t prc_par3:1;
431 uint64_t prc_par2:1;
432 uint64_t prc_par1:1;
433 uint64_t prc_par0:1;
434 } cn38xx;
435 struct cvmx_ipd_int_sum_cn30xx cn38xxp2;
436 struct cvmx_ipd_int_sum_cn38xx cn50xx;
437 struct cvmx_ipd_int_sum_s cn52xx;
438 struct cvmx_ipd_int_sum_s cn52xxp1;
439 struct cvmx_ipd_int_sum_s cn56xx;
440 struct cvmx_ipd_int_sum_s cn56xxp1;
441 struct cvmx_ipd_int_sum_cn38xx cn58xx;
442 struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
443};
444
445union cvmx_ipd_not_1st_mbuff_skip {
446 uint64_t u64;
447 struct cvmx_ipd_not_1st_mbuff_skip_s {
448 uint64_t reserved_6_63:58;
449 uint64_t skip_sz:6;
450 } s;
451 struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
452 struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
453 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;
454 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;
455 struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;
456 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;
457 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;
458 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;
459 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
460 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
461 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
462};
463
464union cvmx_ipd_packet_mbuff_size {
465 uint64_t u64;
466 struct cvmx_ipd_packet_mbuff_size_s {
467 uint64_t reserved_12_63:52;
468 uint64_t mb_size:12;
469 } s;
470 struct cvmx_ipd_packet_mbuff_size_s cn30xx;
471 struct cvmx_ipd_packet_mbuff_size_s cn31xx;
472 struct cvmx_ipd_packet_mbuff_size_s cn38xx;
473 struct cvmx_ipd_packet_mbuff_size_s cn38xxp2;
474 struct cvmx_ipd_packet_mbuff_size_s cn50xx;
475 struct cvmx_ipd_packet_mbuff_size_s cn52xx;
476 struct cvmx_ipd_packet_mbuff_size_s cn52xxp1;
477 struct cvmx_ipd_packet_mbuff_size_s cn56xx;
478 struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
479 struct cvmx_ipd_packet_mbuff_size_s cn58xx;
480 struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
481};
482
483union cvmx_ipd_pkt_ptr_valid {
484 uint64_t u64;
485 struct cvmx_ipd_pkt_ptr_valid_s {
486 uint64_t reserved_29_63:35;
487 uint64_t ptr:29;
488 } s;
489 struct cvmx_ipd_pkt_ptr_valid_s cn30xx;
490 struct cvmx_ipd_pkt_ptr_valid_s cn31xx;
491 struct cvmx_ipd_pkt_ptr_valid_s cn38xx;
492 struct cvmx_ipd_pkt_ptr_valid_s cn50xx;
493 struct cvmx_ipd_pkt_ptr_valid_s cn52xx;
494 struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1;
495 struct cvmx_ipd_pkt_ptr_valid_s cn56xx;
496 struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
497 struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
498 struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
499};
500
501union cvmx_ipd_portx_bp_page_cnt {
502 uint64_t u64;
503 struct cvmx_ipd_portx_bp_page_cnt_s {
504 uint64_t reserved_18_63:46;
505 uint64_t bp_enb:1;
506 uint64_t page_cnt:17;
507 } s;
508 struct cvmx_ipd_portx_bp_page_cnt_s cn30xx;
509 struct cvmx_ipd_portx_bp_page_cnt_s cn31xx;
510 struct cvmx_ipd_portx_bp_page_cnt_s cn38xx;
511 struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2;
512 struct cvmx_ipd_portx_bp_page_cnt_s cn50xx;
513 struct cvmx_ipd_portx_bp_page_cnt_s cn52xx;
514 struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1;
515 struct cvmx_ipd_portx_bp_page_cnt_s cn56xx;
516 struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
517 struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
518 struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
519};
520
521union cvmx_ipd_portx_bp_page_cnt2 {
522 uint64_t u64;
523 struct cvmx_ipd_portx_bp_page_cnt2_s {
524 uint64_t reserved_18_63:46;
525 uint64_t bp_enb:1;
526 uint64_t page_cnt:17;
527 } s;
528 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
529 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
530 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
531 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
532};
533
534union cvmx_ipd_port_bp_counters2_pairx {
535 uint64_t u64;
536 struct cvmx_ipd_port_bp_counters2_pairx_s {
537 uint64_t reserved_25_63:39;
538 uint64_t cnt_val:25;
539 } s;
540 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
541 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
542 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
543 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
544};
545
546union cvmx_ipd_port_bp_counters_pairx {
547 uint64_t u64;
548 struct cvmx_ipd_port_bp_counters_pairx_s {
549 uint64_t reserved_25_63:39;
550 uint64_t cnt_val:25;
551 } s;
552 struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
553 struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
554 struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
555 struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
556 struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
557 struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
558 struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
559 struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
560 struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
561 struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
562 struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
563};
564
565union cvmx_ipd_port_qos_x_cnt {
566 uint64_t u64;
567 struct cvmx_ipd_port_qos_x_cnt_s {
568 uint64_t wmark:32;
569 uint64_t cnt:32;
570 } s;
571 struct cvmx_ipd_port_qos_x_cnt_s cn52xx;
572 struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
573 struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
574 struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
575};
576
577union cvmx_ipd_port_qos_intx {
578 uint64_t u64;
579 struct cvmx_ipd_port_qos_intx_s {
580 uint64_t intr:64;
581 } s;
582 struct cvmx_ipd_port_qos_intx_s cn52xx;
583 struct cvmx_ipd_port_qos_intx_s cn52xxp1;
584 struct cvmx_ipd_port_qos_intx_s cn56xx;
585 struct cvmx_ipd_port_qos_intx_s cn56xxp1;
586};
587
588union cvmx_ipd_port_qos_int_enbx {
589 uint64_t u64;
590 struct cvmx_ipd_port_qos_int_enbx_s {
591 uint64_t enb:64;
592 } s;
593 struct cvmx_ipd_port_qos_int_enbx_s cn52xx;
594 struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
595 struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
596 struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
597};
598
599union cvmx_ipd_prc_hold_ptr_fifo_ctl {
600 uint64_t u64;
601 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
602 uint64_t reserved_39_63:25;
603 uint64_t max_pkt:3;
604 uint64_t praddr:3;
605 uint64_t ptr:29;
606 uint64_t cena:1;
607 uint64_t raddr:3;
608 } s;
609 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
610 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
611 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
612 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
613 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
614 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
615 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
616 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
617 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
618 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
619};
620
621union cvmx_ipd_prc_port_ptr_fifo_ctl {
622 uint64_t u64;
623 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
624 uint64_t reserved_44_63:20;
625 uint64_t max_pkt:7;
626 uint64_t ptr:29;
627 uint64_t cena:1;
628 uint64_t raddr:7;
629 } s;
630 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
631 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
632 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
633 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
634 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
635 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
636 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
637 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
638 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
639 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
640};
641
642union cvmx_ipd_ptr_count {
643 uint64_t u64;
644 struct cvmx_ipd_ptr_count_s {
645 uint64_t reserved_19_63:45;
646 uint64_t pktv_cnt:1;
647 uint64_t wqev_cnt:1;
648 uint64_t pfif_cnt:3;
649 uint64_t pkt_pcnt:7;
650 uint64_t wqe_pcnt:7;
651 } s;
652 struct cvmx_ipd_ptr_count_s cn30xx;
653 struct cvmx_ipd_ptr_count_s cn31xx;
654 struct cvmx_ipd_ptr_count_s cn38xx;
655 struct cvmx_ipd_ptr_count_s cn38xxp2;
656 struct cvmx_ipd_ptr_count_s cn50xx;
657 struct cvmx_ipd_ptr_count_s cn52xx;
658 struct cvmx_ipd_ptr_count_s cn52xxp1;
659 struct cvmx_ipd_ptr_count_s cn56xx;
660 struct cvmx_ipd_ptr_count_s cn56xxp1;
661 struct cvmx_ipd_ptr_count_s cn58xx;
662 struct cvmx_ipd_ptr_count_s cn58xxp1;
663};
664
665union cvmx_ipd_pwp_ptr_fifo_ctl {
666 uint64_t u64;
667 struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
668 uint64_t reserved_61_63:3;
669 uint64_t max_cnts:7;
670 uint64_t wraddr:8;
671 uint64_t praddr:8;
672 uint64_t ptr:29;
673 uint64_t cena:1;
674 uint64_t raddr:8;
675 } s;
676 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx;
677 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx;
678 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx;
679 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx;
680 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx;
681 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1;
682 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx;
683 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
684 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
685 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
686};
687
688union cvmx_ipd_qosx_red_marks {
689 uint64_t u64;
690 struct cvmx_ipd_qosx_red_marks_s {
691 uint64_t drop:32;
692 uint64_t pass:32;
693 } s;
694 struct cvmx_ipd_qosx_red_marks_s cn30xx;
695 struct cvmx_ipd_qosx_red_marks_s cn31xx;
696 struct cvmx_ipd_qosx_red_marks_s cn38xx;
697 struct cvmx_ipd_qosx_red_marks_s cn38xxp2;
698 struct cvmx_ipd_qosx_red_marks_s cn50xx;
699 struct cvmx_ipd_qosx_red_marks_s cn52xx;
700 struct cvmx_ipd_qosx_red_marks_s cn52xxp1;
701 struct cvmx_ipd_qosx_red_marks_s cn56xx;
702 struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
703 struct cvmx_ipd_qosx_red_marks_s cn58xx;
704 struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
705};
706
707union cvmx_ipd_que0_free_page_cnt {
708 uint64_t u64;
709 struct cvmx_ipd_que0_free_page_cnt_s {
710 uint64_t reserved_32_63:32;
711 uint64_t q0_pcnt:32;
712 } s;
713 struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
714 struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
715 struct cvmx_ipd_que0_free_page_cnt_s cn38xx;
716 struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;
717 struct cvmx_ipd_que0_free_page_cnt_s cn50xx;
718 struct cvmx_ipd_que0_free_page_cnt_s cn52xx;
719 struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;
720 struct cvmx_ipd_que0_free_page_cnt_s cn56xx;
721 struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
722 struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
723 struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
724};
725
726union cvmx_ipd_red_port_enable {
727 uint64_t u64;
728 struct cvmx_ipd_red_port_enable_s {
729 uint64_t prb_dly:14;
730 uint64_t avg_dly:14;
731 uint64_t prt_enb:36;
732 } s;
733 struct cvmx_ipd_red_port_enable_s cn30xx;
734 struct cvmx_ipd_red_port_enable_s cn31xx;
735 struct cvmx_ipd_red_port_enable_s cn38xx;
736 struct cvmx_ipd_red_port_enable_s cn38xxp2;
737 struct cvmx_ipd_red_port_enable_s cn50xx;
738 struct cvmx_ipd_red_port_enable_s cn52xx;
739 struct cvmx_ipd_red_port_enable_s cn52xxp1;
740 struct cvmx_ipd_red_port_enable_s cn56xx;
741 struct cvmx_ipd_red_port_enable_s cn56xxp1;
742 struct cvmx_ipd_red_port_enable_s cn58xx;
743 struct cvmx_ipd_red_port_enable_s cn58xxp1;
744};
745
746union cvmx_ipd_red_port_enable2 {
747 uint64_t u64;
748 struct cvmx_ipd_red_port_enable2_s {
749 uint64_t reserved_4_63:60;
750 uint64_t prt_enb:4;
751 } s;
752 struct cvmx_ipd_red_port_enable2_s cn52xx;
753 struct cvmx_ipd_red_port_enable2_s cn52xxp1;
754 struct cvmx_ipd_red_port_enable2_s cn56xx;
755 struct cvmx_ipd_red_port_enable2_s cn56xxp1;
756};
757
758union cvmx_ipd_red_quex_param {
759 uint64_t u64;
760 struct cvmx_ipd_red_quex_param_s {
761 uint64_t reserved_49_63:15;
762 uint64_t use_pcnt:1;
763 uint64_t new_con:8;
764 uint64_t avg_con:8;
765 uint64_t prb_con:32;
766 } s;
767 struct cvmx_ipd_red_quex_param_s cn30xx;
768 struct cvmx_ipd_red_quex_param_s cn31xx;
769 struct cvmx_ipd_red_quex_param_s cn38xx;
770 struct cvmx_ipd_red_quex_param_s cn38xxp2;
771 struct cvmx_ipd_red_quex_param_s cn50xx;
772 struct cvmx_ipd_red_quex_param_s cn52xx;
773 struct cvmx_ipd_red_quex_param_s cn52xxp1;
774 struct cvmx_ipd_red_quex_param_s cn56xx;
775 struct cvmx_ipd_red_quex_param_s cn56xxp1;
776 struct cvmx_ipd_red_quex_param_s cn58xx;
777 struct cvmx_ipd_red_quex_param_s cn58xxp1;
778};
779
780union cvmx_ipd_sub_port_bp_page_cnt {
781 uint64_t u64;
782 struct cvmx_ipd_sub_port_bp_page_cnt_s {
783 uint64_t reserved_31_63:33;
784 uint64_t port:6;
785 uint64_t page_cnt:25;
786 } s;
787 struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
788 struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
789 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
790 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
791 struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
792 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
793 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
794 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
795 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
796 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
797 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
798};
799
800union cvmx_ipd_sub_port_fcs {
801 uint64_t u64;
802 struct cvmx_ipd_sub_port_fcs_s {
803 uint64_t reserved_40_63:24;
804 uint64_t port_bit2:4;
805 uint64_t reserved_32_35:4;
806 uint64_t port_bit:32;
807 } s;
808 struct cvmx_ipd_sub_port_fcs_cn30xx {
809 uint64_t reserved_3_63:61;
810 uint64_t port_bit:3;
811 } cn30xx;
812 struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx;
813 struct cvmx_ipd_sub_port_fcs_cn38xx {
814 uint64_t reserved_32_63:32;
815 uint64_t port_bit:32;
816 } cn38xx;
817 struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2;
818 struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx;
819 struct cvmx_ipd_sub_port_fcs_s cn52xx;
820 struct cvmx_ipd_sub_port_fcs_s cn52xxp1;
821 struct cvmx_ipd_sub_port_fcs_s cn56xx;
822 struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
823 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
824 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
825};
826
827union cvmx_ipd_sub_port_qos_cnt {
828 uint64_t u64;
829 struct cvmx_ipd_sub_port_qos_cnt_s {
830 uint64_t reserved_41_63:23;
831 uint64_t port_qos:9;
832 uint64_t cnt:32;
833 } s;
834 struct cvmx_ipd_sub_port_qos_cnt_s cn52xx;
835 struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
836 struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
837 struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
838};
839
840union cvmx_ipd_wqe_fpa_queue {
841 uint64_t u64;
842 struct cvmx_ipd_wqe_fpa_queue_s {
843 uint64_t reserved_3_63:61;
844 uint64_t wqe_pool:3;
845 } s;
846 struct cvmx_ipd_wqe_fpa_queue_s cn30xx;
847 struct cvmx_ipd_wqe_fpa_queue_s cn31xx;
848 struct cvmx_ipd_wqe_fpa_queue_s cn38xx;
849 struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2;
850 struct cvmx_ipd_wqe_fpa_queue_s cn50xx;
851 struct cvmx_ipd_wqe_fpa_queue_s cn52xx;
852 struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1;
853 struct cvmx_ipd_wqe_fpa_queue_s cn56xx;
854 struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
855 struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
856 struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
857};
858
859union cvmx_ipd_wqe_ptr_valid {
860 uint64_t u64;
861 struct cvmx_ipd_wqe_ptr_valid_s {
862 uint64_t reserved_29_63:35;
863 uint64_t ptr:29;
864 } s;
865 struct cvmx_ipd_wqe_ptr_valid_s cn30xx;
866 struct cvmx_ipd_wqe_ptr_valid_s cn31xx;
867 struct cvmx_ipd_wqe_ptr_valid_s cn38xx;
868 struct cvmx_ipd_wqe_ptr_valid_s cn50xx;
869 struct cvmx_ipd_wqe_ptr_valid_s cn52xx;
870 struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1;
871 struct cvmx_ipd_wqe_ptr_valid_s cn56xx;
872 struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
873 struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
874 struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
875};
876
877#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
new file mode 100644
index 000000000000..337583842b51
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -0,0 +1,963 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2C_DEFS_H__
29#define __CVMX_L2C_DEFS_H__
30
31#define CVMX_L2C_BST0 \
32 CVMX_ADD_IO_SEG(0x00011800800007F8ull)
33#define CVMX_L2C_BST1 \
34 CVMX_ADD_IO_SEG(0x00011800800007F0ull)
35#define CVMX_L2C_BST2 \
36 CVMX_ADD_IO_SEG(0x00011800800007E8ull)
37#define CVMX_L2C_CFG \
38 CVMX_ADD_IO_SEG(0x0001180080000000ull)
39#define CVMX_L2C_DBG \
40 CVMX_ADD_IO_SEG(0x0001180080000030ull)
41#define CVMX_L2C_DUT \
42 CVMX_ADD_IO_SEG(0x0001180080000050ull)
43#define CVMX_L2C_GRPWRR0 \
44 CVMX_ADD_IO_SEG(0x00011800800000C8ull)
45#define CVMX_L2C_GRPWRR1 \
46 CVMX_ADD_IO_SEG(0x00011800800000D0ull)
47#define CVMX_L2C_INT_EN \
48 CVMX_ADD_IO_SEG(0x0001180080000100ull)
49#define CVMX_L2C_INT_STAT \
50 CVMX_ADD_IO_SEG(0x00011800800000F8ull)
51#define CVMX_L2C_LCKBASE \
52 CVMX_ADD_IO_SEG(0x0001180080000058ull)
53#define CVMX_L2C_LCKOFF \
54 CVMX_ADD_IO_SEG(0x0001180080000060ull)
55#define CVMX_L2C_LFB0 \
56 CVMX_ADD_IO_SEG(0x0001180080000038ull)
57#define CVMX_L2C_LFB1 \
58 CVMX_ADD_IO_SEG(0x0001180080000040ull)
59#define CVMX_L2C_LFB2 \
60 CVMX_ADD_IO_SEG(0x0001180080000048ull)
61#define CVMX_L2C_LFB3 \
62 CVMX_ADD_IO_SEG(0x00011800800000B8ull)
63#define CVMX_L2C_OOB \
64 CVMX_ADD_IO_SEG(0x00011800800000D8ull)
65#define CVMX_L2C_OOB1 \
66 CVMX_ADD_IO_SEG(0x00011800800000E0ull)
67#define CVMX_L2C_OOB2 \
68 CVMX_ADD_IO_SEG(0x00011800800000E8ull)
69#define CVMX_L2C_OOB3 \
70 CVMX_ADD_IO_SEG(0x00011800800000F0ull)
71#define CVMX_L2C_PFC0 \
72 CVMX_ADD_IO_SEG(0x0001180080000098ull)
73#define CVMX_L2C_PFC1 \
74 CVMX_ADD_IO_SEG(0x00011800800000A0ull)
75#define CVMX_L2C_PFC2 \
76 CVMX_ADD_IO_SEG(0x00011800800000A8ull)
77#define CVMX_L2C_PFC3 \
78 CVMX_ADD_IO_SEG(0x00011800800000B0ull)
79#define CVMX_L2C_PFCTL \
80 CVMX_ADD_IO_SEG(0x0001180080000090ull)
81#define CVMX_L2C_PFCX(offset) \
82 CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8))
83#define CVMX_L2C_PPGRP \
84 CVMX_ADD_IO_SEG(0x00011800800000C0ull)
85#define CVMX_L2C_SPAR0 \
86 CVMX_ADD_IO_SEG(0x0001180080000068ull)
87#define CVMX_L2C_SPAR1 \
88 CVMX_ADD_IO_SEG(0x0001180080000070ull)
89#define CVMX_L2C_SPAR2 \
90 CVMX_ADD_IO_SEG(0x0001180080000078ull)
91#define CVMX_L2C_SPAR3 \
92 CVMX_ADD_IO_SEG(0x0001180080000080ull)
93#define CVMX_L2C_SPAR4 \
94 CVMX_ADD_IO_SEG(0x0001180080000088ull)
95
96union cvmx_l2c_bst0 {
97 uint64_t u64;
98 struct cvmx_l2c_bst0_s {
99 uint64_t reserved_24_63:40;
100 uint64_t dtbnk:1;
101 uint64_t wlb_msk:4;
102 uint64_t dtcnt:13;
103 uint64_t dt:1;
104 uint64_t stin_msk:1;
105 uint64_t wlb_dat:4;
106 } s;
107 struct cvmx_l2c_bst0_cn30xx {
108 uint64_t reserved_23_63:41;
109 uint64_t wlb_msk:4;
110 uint64_t reserved_15_18:4;
111 uint64_t dtcnt:9;
112 uint64_t dt:1;
113 uint64_t reserved_4_4:1;
114 uint64_t wlb_dat:4;
115 } cn30xx;
116 struct cvmx_l2c_bst0_cn31xx {
117 uint64_t reserved_23_63:41;
118 uint64_t wlb_msk:4;
119 uint64_t reserved_16_18:3;
120 uint64_t dtcnt:10;
121 uint64_t dt:1;
122 uint64_t stin_msk:1;
123 uint64_t wlb_dat:4;
124 } cn31xx;
125 struct cvmx_l2c_bst0_cn38xx {
126 uint64_t reserved_19_63:45;
127 uint64_t dtcnt:13;
128 uint64_t dt:1;
129 uint64_t stin_msk:1;
130 uint64_t wlb_dat:4;
131 } cn38xx;
132 struct cvmx_l2c_bst0_cn38xx cn38xxp2;
133 struct cvmx_l2c_bst0_cn50xx {
134 uint64_t reserved_24_63:40;
135 uint64_t dtbnk:1;
136 uint64_t wlb_msk:4;
137 uint64_t reserved_16_18:3;
138 uint64_t dtcnt:10;
139 uint64_t dt:1;
140 uint64_t stin_msk:1;
141 uint64_t wlb_dat:4;
142 } cn50xx;
143 struct cvmx_l2c_bst0_cn50xx cn52xx;
144 struct cvmx_l2c_bst0_cn50xx cn52xxp1;
145 struct cvmx_l2c_bst0_s cn56xx;
146 struct cvmx_l2c_bst0_s cn56xxp1;
147 struct cvmx_l2c_bst0_s cn58xx;
148 struct cvmx_l2c_bst0_s cn58xxp1;
149};
150
151union cvmx_l2c_bst1 {
152 uint64_t u64;
153 struct cvmx_l2c_bst1_s {
154 uint64_t reserved_9_63:55;
155 uint64_t l2t:9;
156 } s;
157 struct cvmx_l2c_bst1_cn30xx {
158 uint64_t reserved_16_63:48;
159 uint64_t vwdf:4;
160 uint64_t lrf:2;
161 uint64_t vab_vwcf:1;
162 uint64_t reserved_5_8:4;
163 uint64_t l2t:5;
164 } cn30xx;
165 struct cvmx_l2c_bst1_cn30xx cn31xx;
166 struct cvmx_l2c_bst1_cn38xx {
167 uint64_t reserved_16_63:48;
168 uint64_t vwdf:4;
169 uint64_t lrf:2;
170 uint64_t vab_vwcf:1;
171 uint64_t l2t:9;
172 } cn38xx;
173 struct cvmx_l2c_bst1_cn38xx cn38xxp2;
174 struct cvmx_l2c_bst1_cn38xx cn50xx;
175 struct cvmx_l2c_bst1_cn52xx {
176 uint64_t reserved_19_63:45;
177 uint64_t plc2:1;
178 uint64_t plc1:1;
179 uint64_t plc0:1;
180 uint64_t vwdf:4;
181 uint64_t reserved_11_11:1;
182 uint64_t ilc:1;
183 uint64_t vab_vwcf:1;
184 uint64_t l2t:9;
185 } cn52xx;
186 struct cvmx_l2c_bst1_cn52xx cn52xxp1;
187 struct cvmx_l2c_bst1_cn56xx {
188 uint64_t reserved_24_63:40;
189 uint64_t plc2:1;
190 uint64_t plc1:1;
191 uint64_t plc0:1;
192 uint64_t ilc:1;
193 uint64_t vwdf1:4;
194 uint64_t vwdf0:4;
195 uint64_t vab_vwcf1:1;
196 uint64_t reserved_10_10:1;
197 uint64_t vab_vwcf0:1;
198 uint64_t l2t:9;
199 } cn56xx;
200 struct cvmx_l2c_bst1_cn56xx cn56xxp1;
201 struct cvmx_l2c_bst1_cn38xx cn58xx;
202 struct cvmx_l2c_bst1_cn38xx cn58xxp1;
203};
204
205union cvmx_l2c_bst2 {
206 uint64_t u64;
207 struct cvmx_l2c_bst2_s {
208 uint64_t reserved_16_63:48;
209 uint64_t mrb:4;
210 uint64_t reserved_4_11:8;
211 uint64_t ipcbst:1;
212 uint64_t picbst:1;
213 uint64_t xrdmsk:1;
214 uint64_t xrddat:1;
215 } s;
216 struct cvmx_l2c_bst2_cn30xx {
217 uint64_t reserved_16_63:48;
218 uint64_t mrb:4;
219 uint64_t rmdf:4;
220 uint64_t reserved_4_7:4;
221 uint64_t ipcbst:1;
222 uint64_t reserved_2_2:1;
223 uint64_t xrdmsk:1;
224 uint64_t xrddat:1;
225 } cn30xx;
226 struct cvmx_l2c_bst2_cn30xx cn31xx;
227 struct cvmx_l2c_bst2_cn38xx {
228 uint64_t reserved_16_63:48;
229 uint64_t mrb:4;
230 uint64_t rmdf:4;
231 uint64_t rhdf:4;
232 uint64_t ipcbst:1;
233 uint64_t picbst:1;
234 uint64_t xrdmsk:1;
235 uint64_t xrddat:1;
236 } cn38xx;
237 struct cvmx_l2c_bst2_cn38xx cn38xxp2;
238 struct cvmx_l2c_bst2_cn30xx cn50xx;
239 struct cvmx_l2c_bst2_cn30xx cn52xx;
240 struct cvmx_l2c_bst2_cn30xx cn52xxp1;
241 struct cvmx_l2c_bst2_cn56xx {
242 uint64_t reserved_16_63:48;
243 uint64_t mrb:4;
244 uint64_t rmdb:4;
245 uint64_t rhdb:4;
246 uint64_t ipcbst:1;
247 uint64_t picbst:1;
248 uint64_t xrdmsk:1;
249 uint64_t xrddat:1;
250 } cn56xx;
251 struct cvmx_l2c_bst2_cn56xx cn56xxp1;
252 struct cvmx_l2c_bst2_cn56xx cn58xx;
253 struct cvmx_l2c_bst2_cn56xx cn58xxp1;
254};
255
256union cvmx_l2c_cfg {
257 uint64_t u64;
258 struct cvmx_l2c_cfg_s {
259 uint64_t reserved_20_63:44;
260 uint64_t bstrun:1;
261 uint64_t lbist:1;
262 uint64_t xor_bank:1;
263 uint64_t dpres1:1;
264 uint64_t dpres0:1;
265 uint64_t dfill_dis:1;
266 uint64_t fpexp:4;
267 uint64_t fpempty:1;
268 uint64_t fpen:1;
269 uint64_t idxalias:1;
270 uint64_t mwf_crd:4;
271 uint64_t rsp_arb_mode:1;
272 uint64_t rfb_arb_mode:1;
273 uint64_t lrf_arb_mode:1;
274 } s;
275 struct cvmx_l2c_cfg_cn30xx {
276 uint64_t reserved_14_63:50;
277 uint64_t fpexp:4;
278 uint64_t fpempty:1;
279 uint64_t fpen:1;
280 uint64_t idxalias:1;
281 uint64_t mwf_crd:4;
282 uint64_t rsp_arb_mode:1;
283 uint64_t rfb_arb_mode:1;
284 uint64_t lrf_arb_mode:1;
285 } cn30xx;
286 struct cvmx_l2c_cfg_cn30xx cn31xx;
287 struct cvmx_l2c_cfg_cn30xx cn38xx;
288 struct cvmx_l2c_cfg_cn30xx cn38xxp2;
289 struct cvmx_l2c_cfg_cn50xx {
290 uint64_t reserved_20_63:44;
291 uint64_t bstrun:1;
292 uint64_t lbist:1;
293 uint64_t reserved_14_17:4;
294 uint64_t fpexp:4;
295 uint64_t fpempty:1;
296 uint64_t fpen:1;
297 uint64_t idxalias:1;
298 uint64_t mwf_crd:4;
299 uint64_t rsp_arb_mode:1;
300 uint64_t rfb_arb_mode:1;
301 uint64_t lrf_arb_mode:1;
302 } cn50xx;
303 struct cvmx_l2c_cfg_cn50xx cn52xx;
304 struct cvmx_l2c_cfg_cn50xx cn52xxp1;
305 struct cvmx_l2c_cfg_s cn56xx;
306 struct cvmx_l2c_cfg_s cn56xxp1;
307 struct cvmx_l2c_cfg_cn58xx {
308 uint64_t reserved_20_63:44;
309 uint64_t bstrun:1;
310 uint64_t lbist:1;
311 uint64_t reserved_15_17:3;
312 uint64_t dfill_dis:1;
313 uint64_t fpexp:4;
314 uint64_t fpempty:1;
315 uint64_t fpen:1;
316 uint64_t idxalias:1;
317 uint64_t mwf_crd:4;
318 uint64_t rsp_arb_mode:1;
319 uint64_t rfb_arb_mode:1;
320 uint64_t lrf_arb_mode:1;
321 } cn58xx;
322 struct cvmx_l2c_cfg_cn58xxp1 {
323 uint64_t reserved_15_63:49;
324 uint64_t dfill_dis:1;
325 uint64_t fpexp:4;
326 uint64_t fpempty:1;
327 uint64_t fpen:1;
328 uint64_t idxalias:1;
329 uint64_t mwf_crd:4;
330 uint64_t rsp_arb_mode:1;
331 uint64_t rfb_arb_mode:1;
332 uint64_t lrf_arb_mode:1;
333 } cn58xxp1;
334};
335
336union cvmx_l2c_dbg {
337 uint64_t u64;
338 struct cvmx_l2c_dbg_s {
339 uint64_t reserved_15_63:49;
340 uint64_t lfb_enum:4;
341 uint64_t lfb_dmp:1;
342 uint64_t ppnum:4;
343 uint64_t set:3;
344 uint64_t finv:1;
345 uint64_t l2d:1;
346 uint64_t l2t:1;
347 } s;
348 struct cvmx_l2c_dbg_cn30xx {
349 uint64_t reserved_13_63:51;
350 uint64_t lfb_enum:2;
351 uint64_t lfb_dmp:1;
352 uint64_t reserved_5_9:5;
353 uint64_t set:2;
354 uint64_t finv:1;
355 uint64_t l2d:1;
356 uint64_t l2t:1;
357 } cn30xx;
358 struct cvmx_l2c_dbg_cn31xx {
359 uint64_t reserved_14_63:50;
360 uint64_t lfb_enum:3;
361 uint64_t lfb_dmp:1;
362 uint64_t reserved_7_9:3;
363 uint64_t ppnum:1;
364 uint64_t reserved_5_5:1;
365 uint64_t set:2;
366 uint64_t finv:1;
367 uint64_t l2d:1;
368 uint64_t l2t:1;
369 } cn31xx;
370 struct cvmx_l2c_dbg_s cn38xx;
371 struct cvmx_l2c_dbg_s cn38xxp2;
372 struct cvmx_l2c_dbg_cn50xx {
373 uint64_t reserved_14_63:50;
374 uint64_t lfb_enum:3;
375 uint64_t lfb_dmp:1;
376 uint64_t reserved_7_9:3;
377 uint64_t ppnum:1;
378 uint64_t set:3;
379 uint64_t finv:1;
380 uint64_t l2d:1;
381 uint64_t l2t:1;
382 } cn50xx;
383 struct cvmx_l2c_dbg_cn52xx {
384 uint64_t reserved_14_63:50;
385 uint64_t lfb_enum:3;
386 uint64_t lfb_dmp:1;
387 uint64_t reserved_8_9:2;
388 uint64_t ppnum:2;
389 uint64_t set:3;
390 uint64_t finv:1;
391 uint64_t l2d:1;
392 uint64_t l2t:1;
393 } cn52xx;
394 struct cvmx_l2c_dbg_cn52xx cn52xxp1;
395 struct cvmx_l2c_dbg_s cn56xx;
396 struct cvmx_l2c_dbg_s cn56xxp1;
397 struct cvmx_l2c_dbg_s cn58xx;
398 struct cvmx_l2c_dbg_s cn58xxp1;
399};
400
401union cvmx_l2c_dut {
402 uint64_t u64;
403 struct cvmx_l2c_dut_s {
404 uint64_t reserved_32_63:32;
405 uint64_t dtena:1;
406 uint64_t reserved_30_30:1;
407 uint64_t dt_vld:1;
408 uint64_t dt_tag:29;
409 } s;
410 struct cvmx_l2c_dut_s cn30xx;
411 struct cvmx_l2c_dut_s cn31xx;
412 struct cvmx_l2c_dut_s cn38xx;
413 struct cvmx_l2c_dut_s cn38xxp2;
414 struct cvmx_l2c_dut_s cn50xx;
415 struct cvmx_l2c_dut_s cn52xx;
416 struct cvmx_l2c_dut_s cn52xxp1;
417 struct cvmx_l2c_dut_s cn56xx;
418 struct cvmx_l2c_dut_s cn56xxp1;
419 struct cvmx_l2c_dut_s cn58xx;
420 struct cvmx_l2c_dut_s cn58xxp1;
421};
422
423union cvmx_l2c_grpwrr0 {
424 uint64_t u64;
425 struct cvmx_l2c_grpwrr0_s {
426 uint64_t plc1rmsk:32;
427 uint64_t plc0rmsk:32;
428 } s;
429 struct cvmx_l2c_grpwrr0_s cn52xx;
430 struct cvmx_l2c_grpwrr0_s cn52xxp1;
431 struct cvmx_l2c_grpwrr0_s cn56xx;
432 struct cvmx_l2c_grpwrr0_s cn56xxp1;
433};
434
435union cvmx_l2c_grpwrr1 {
436 uint64_t u64;
437 struct cvmx_l2c_grpwrr1_s {
438 uint64_t ilcrmsk:32;
439 uint64_t plc2rmsk:32;
440 } s;
441 struct cvmx_l2c_grpwrr1_s cn52xx;
442 struct cvmx_l2c_grpwrr1_s cn52xxp1;
443 struct cvmx_l2c_grpwrr1_s cn56xx;
444 struct cvmx_l2c_grpwrr1_s cn56xxp1;
445};
446
447union cvmx_l2c_int_en {
448 uint64_t u64;
449 struct cvmx_l2c_int_en_s {
450 uint64_t reserved_9_63:55;
451 uint64_t lck2ena:1;
452 uint64_t lckena:1;
453 uint64_t l2ddeden:1;
454 uint64_t l2dsecen:1;
455 uint64_t l2tdeden:1;
456 uint64_t l2tsecen:1;
457 uint64_t oob3en:1;
458 uint64_t oob2en:1;
459 uint64_t oob1en:1;
460 } s;
461 struct cvmx_l2c_int_en_s cn52xx;
462 struct cvmx_l2c_int_en_s cn52xxp1;
463 struct cvmx_l2c_int_en_s cn56xx;
464 struct cvmx_l2c_int_en_s cn56xxp1;
465};
466
467union cvmx_l2c_int_stat {
468 uint64_t u64;
469 struct cvmx_l2c_int_stat_s {
470 uint64_t reserved_9_63:55;
471 uint64_t lck2:1;
472 uint64_t lck:1;
473 uint64_t l2dded:1;
474 uint64_t l2dsec:1;
475 uint64_t l2tded:1;
476 uint64_t l2tsec:1;
477 uint64_t oob3:1;
478 uint64_t oob2:1;
479 uint64_t oob1:1;
480 } s;
481 struct cvmx_l2c_int_stat_s cn52xx;
482 struct cvmx_l2c_int_stat_s cn52xxp1;
483 struct cvmx_l2c_int_stat_s cn56xx;
484 struct cvmx_l2c_int_stat_s cn56xxp1;
485};
486
487union cvmx_l2c_lckbase {
488 uint64_t u64;
489 struct cvmx_l2c_lckbase_s {
490 uint64_t reserved_31_63:33;
491 uint64_t lck_base:27;
492 uint64_t reserved_1_3:3;
493 uint64_t lck_ena:1;
494 } s;
495 struct cvmx_l2c_lckbase_s cn30xx;
496 struct cvmx_l2c_lckbase_s cn31xx;
497 struct cvmx_l2c_lckbase_s cn38xx;
498 struct cvmx_l2c_lckbase_s cn38xxp2;
499 struct cvmx_l2c_lckbase_s cn50xx;
500 struct cvmx_l2c_lckbase_s cn52xx;
501 struct cvmx_l2c_lckbase_s cn52xxp1;
502 struct cvmx_l2c_lckbase_s cn56xx;
503 struct cvmx_l2c_lckbase_s cn56xxp1;
504 struct cvmx_l2c_lckbase_s cn58xx;
505 struct cvmx_l2c_lckbase_s cn58xxp1;
506};
507
508union cvmx_l2c_lckoff {
509 uint64_t u64;
510 struct cvmx_l2c_lckoff_s {
511 uint64_t reserved_10_63:54;
512 uint64_t lck_offset:10;
513 } s;
514 struct cvmx_l2c_lckoff_s cn30xx;
515 struct cvmx_l2c_lckoff_s cn31xx;
516 struct cvmx_l2c_lckoff_s cn38xx;
517 struct cvmx_l2c_lckoff_s cn38xxp2;
518 struct cvmx_l2c_lckoff_s cn50xx;
519 struct cvmx_l2c_lckoff_s cn52xx;
520 struct cvmx_l2c_lckoff_s cn52xxp1;
521 struct cvmx_l2c_lckoff_s cn56xx;
522 struct cvmx_l2c_lckoff_s cn56xxp1;
523 struct cvmx_l2c_lckoff_s cn58xx;
524 struct cvmx_l2c_lckoff_s cn58xxp1;
525};
526
527union cvmx_l2c_lfb0 {
528 uint64_t u64;
529 struct cvmx_l2c_lfb0_s {
530 uint64_t reserved_32_63:32;
531 uint64_t stcpnd:1;
532 uint64_t stpnd:1;
533 uint64_t stinv:1;
534 uint64_t stcfl:1;
535 uint64_t vam:1;
536 uint64_t inxt:4;
537 uint64_t itl:1;
538 uint64_t ihd:1;
539 uint64_t set:3;
540 uint64_t vabnum:4;
541 uint64_t sid:9;
542 uint64_t cmd:4;
543 uint64_t vld:1;
544 } s;
545 struct cvmx_l2c_lfb0_cn30xx {
546 uint64_t reserved_32_63:32;
547 uint64_t stcpnd:1;
548 uint64_t stpnd:1;
549 uint64_t stinv:1;
550 uint64_t stcfl:1;
551 uint64_t vam:1;
552 uint64_t reserved_25_26:2;
553 uint64_t inxt:2;
554 uint64_t itl:1;
555 uint64_t ihd:1;
556 uint64_t reserved_20_20:1;
557 uint64_t set:2;
558 uint64_t reserved_16_17:2;
559 uint64_t vabnum:2;
560 uint64_t sid:9;
561 uint64_t cmd:4;
562 uint64_t vld:1;
563 } cn30xx;
564 struct cvmx_l2c_lfb0_cn31xx {
565 uint64_t reserved_32_63:32;
566 uint64_t stcpnd:1;
567 uint64_t stpnd:1;
568 uint64_t stinv:1;
569 uint64_t stcfl:1;
570 uint64_t vam:1;
571 uint64_t reserved_26_26:1;
572 uint64_t inxt:3;
573 uint64_t itl:1;
574 uint64_t ihd:1;
575 uint64_t reserved_20_20:1;
576 uint64_t set:2;
577 uint64_t reserved_17_17:1;
578 uint64_t vabnum:3;
579 uint64_t sid:9;
580 uint64_t cmd:4;
581 uint64_t vld:1;
582 } cn31xx;
583 struct cvmx_l2c_lfb0_s cn38xx;
584 struct cvmx_l2c_lfb0_s cn38xxp2;
585 struct cvmx_l2c_lfb0_cn50xx {
586 uint64_t reserved_32_63:32;
587 uint64_t stcpnd:1;
588 uint64_t stpnd:1;
589 uint64_t stinv:1;
590 uint64_t stcfl:1;
591 uint64_t vam:1;
592 uint64_t reserved_26_26:1;
593 uint64_t inxt:3;
594 uint64_t itl:1;
595 uint64_t ihd:1;
596 uint64_t set:3;
597 uint64_t reserved_17_17:1;
598 uint64_t vabnum:3;
599 uint64_t sid:9;
600 uint64_t cmd:4;
601 uint64_t vld:1;
602 } cn50xx;
603 struct cvmx_l2c_lfb0_cn50xx cn52xx;
604 struct cvmx_l2c_lfb0_cn50xx cn52xxp1;
605 struct cvmx_l2c_lfb0_s cn56xx;
606 struct cvmx_l2c_lfb0_s cn56xxp1;
607 struct cvmx_l2c_lfb0_s cn58xx;
608 struct cvmx_l2c_lfb0_s cn58xxp1;
609};
610
611union cvmx_l2c_lfb1 {
612 uint64_t u64;
613 struct cvmx_l2c_lfb1_s {
614 uint64_t reserved_19_63:45;
615 uint64_t dsgoing:1;
616 uint64_t bid:2;
617 uint64_t wtrsp:1;
618 uint64_t wtdw:1;
619 uint64_t wtdq:1;
620 uint64_t wtwhp:1;
621 uint64_t wtwhf:1;
622 uint64_t wtwrm:1;
623 uint64_t wtstm:1;
624 uint64_t wtrda:1;
625 uint64_t wtstdt:1;
626 uint64_t wtstrsp:1;
627 uint64_t wtstrsc:1;
628 uint64_t wtvtm:1;
629 uint64_t wtmfl:1;
630 uint64_t prbrty:1;
631 uint64_t wtprb:1;
632 uint64_t vld:1;
633 } s;
634 struct cvmx_l2c_lfb1_s cn30xx;
635 struct cvmx_l2c_lfb1_s cn31xx;
636 struct cvmx_l2c_lfb1_s cn38xx;
637 struct cvmx_l2c_lfb1_s cn38xxp2;
638 struct cvmx_l2c_lfb1_s cn50xx;
639 struct cvmx_l2c_lfb1_s cn52xx;
640 struct cvmx_l2c_lfb1_s cn52xxp1;
641 struct cvmx_l2c_lfb1_s cn56xx;
642 struct cvmx_l2c_lfb1_s cn56xxp1;
643 struct cvmx_l2c_lfb1_s cn58xx;
644 struct cvmx_l2c_lfb1_s cn58xxp1;
645};
646
647union cvmx_l2c_lfb2 {
648 uint64_t u64;
649 struct cvmx_l2c_lfb2_s {
650 uint64_t reserved_0_63:64;
651 } s;
652 struct cvmx_l2c_lfb2_cn30xx {
653 uint64_t reserved_27_63:37;
654 uint64_t lfb_tag:19;
655 uint64_t lfb_idx:8;
656 } cn30xx;
657 struct cvmx_l2c_lfb2_cn31xx {
658 uint64_t reserved_27_63:37;
659 uint64_t lfb_tag:17;
660 uint64_t lfb_idx:10;
661 } cn31xx;
662 struct cvmx_l2c_lfb2_cn31xx cn38xx;
663 struct cvmx_l2c_lfb2_cn31xx cn38xxp2;
664 struct cvmx_l2c_lfb2_cn50xx {
665 uint64_t reserved_27_63:37;
666 uint64_t lfb_tag:20;
667 uint64_t lfb_idx:7;
668 } cn50xx;
669 struct cvmx_l2c_lfb2_cn52xx {
670 uint64_t reserved_27_63:37;
671 uint64_t lfb_tag:18;
672 uint64_t lfb_idx:9;
673 } cn52xx;
674 struct cvmx_l2c_lfb2_cn52xx cn52xxp1;
675 struct cvmx_l2c_lfb2_cn56xx {
676 uint64_t reserved_27_63:37;
677 uint64_t lfb_tag:16;
678 uint64_t lfb_idx:11;
679 } cn56xx;
680 struct cvmx_l2c_lfb2_cn56xx cn56xxp1;
681 struct cvmx_l2c_lfb2_cn56xx cn58xx;
682 struct cvmx_l2c_lfb2_cn56xx cn58xxp1;
683};
684
685union cvmx_l2c_lfb3 {
686 uint64_t u64;
687 struct cvmx_l2c_lfb3_s {
688 uint64_t reserved_5_63:59;
689 uint64_t stpartdis:1;
690 uint64_t lfb_hwm:4;
691 } s;
692 struct cvmx_l2c_lfb3_cn30xx {
693 uint64_t reserved_5_63:59;
694 uint64_t stpartdis:1;
695 uint64_t reserved_2_3:2;
696 uint64_t lfb_hwm:2;
697 } cn30xx;
698 struct cvmx_l2c_lfb3_cn31xx {
699 uint64_t reserved_5_63:59;
700 uint64_t stpartdis:1;
701 uint64_t reserved_3_3:1;
702 uint64_t lfb_hwm:3;
703 } cn31xx;
704 struct cvmx_l2c_lfb3_s cn38xx;
705 struct cvmx_l2c_lfb3_s cn38xxp2;
706 struct cvmx_l2c_lfb3_cn31xx cn50xx;
707 struct cvmx_l2c_lfb3_cn31xx cn52xx;
708 struct cvmx_l2c_lfb3_cn31xx cn52xxp1;
709 struct cvmx_l2c_lfb3_s cn56xx;
710 struct cvmx_l2c_lfb3_s cn56xxp1;
711 struct cvmx_l2c_lfb3_s cn58xx;
712 struct cvmx_l2c_lfb3_s cn58xxp1;
713};
714
715union cvmx_l2c_oob {
716 uint64_t u64;
717 struct cvmx_l2c_oob_s {
718 uint64_t reserved_2_63:62;
719 uint64_t dwbena:1;
720 uint64_t stena:1;
721 } s;
722 struct cvmx_l2c_oob_s cn52xx;
723 struct cvmx_l2c_oob_s cn52xxp1;
724 struct cvmx_l2c_oob_s cn56xx;
725 struct cvmx_l2c_oob_s cn56xxp1;
726};
727
728union cvmx_l2c_oob1 {
729 uint64_t u64;
730 struct cvmx_l2c_oob1_s {
731 uint64_t fadr:27;
732 uint64_t fsrc:1;
733 uint64_t reserved_34_35:2;
734 uint64_t sadr:14;
735 uint64_t reserved_14_19:6;
736 uint64_t size:14;
737 } s;
738 struct cvmx_l2c_oob1_s cn52xx;
739 struct cvmx_l2c_oob1_s cn52xxp1;
740 struct cvmx_l2c_oob1_s cn56xx;
741 struct cvmx_l2c_oob1_s cn56xxp1;
742};
743
744union cvmx_l2c_oob2 {
745 uint64_t u64;
746 struct cvmx_l2c_oob2_s {
747 uint64_t fadr:27;
748 uint64_t fsrc:1;
749 uint64_t reserved_34_35:2;
750 uint64_t sadr:14;
751 uint64_t reserved_14_19:6;
752 uint64_t size:14;
753 } s;
754 struct cvmx_l2c_oob2_s cn52xx;
755 struct cvmx_l2c_oob2_s cn52xxp1;
756 struct cvmx_l2c_oob2_s cn56xx;
757 struct cvmx_l2c_oob2_s cn56xxp1;
758};
759
760union cvmx_l2c_oob3 {
761 uint64_t u64;
762 struct cvmx_l2c_oob3_s {
763 uint64_t fadr:27;
764 uint64_t fsrc:1;
765 uint64_t reserved_34_35:2;
766 uint64_t sadr:14;
767 uint64_t reserved_14_19:6;
768 uint64_t size:14;
769 } s;
770 struct cvmx_l2c_oob3_s cn52xx;
771 struct cvmx_l2c_oob3_s cn52xxp1;
772 struct cvmx_l2c_oob3_s cn56xx;
773 struct cvmx_l2c_oob3_s cn56xxp1;
774};
775
776union cvmx_l2c_pfcx {
777 uint64_t u64;
778 struct cvmx_l2c_pfcx_s {
779 uint64_t reserved_36_63:28;
780 uint64_t pfcnt0:36;
781 } s;
782 struct cvmx_l2c_pfcx_s cn30xx;
783 struct cvmx_l2c_pfcx_s cn31xx;
784 struct cvmx_l2c_pfcx_s cn38xx;
785 struct cvmx_l2c_pfcx_s cn38xxp2;
786 struct cvmx_l2c_pfcx_s cn50xx;
787 struct cvmx_l2c_pfcx_s cn52xx;
788 struct cvmx_l2c_pfcx_s cn52xxp1;
789 struct cvmx_l2c_pfcx_s cn56xx;
790 struct cvmx_l2c_pfcx_s cn56xxp1;
791 struct cvmx_l2c_pfcx_s cn58xx;
792 struct cvmx_l2c_pfcx_s cn58xxp1;
793};
794
795union cvmx_l2c_pfctl {
796 uint64_t u64;
797 struct cvmx_l2c_pfctl_s {
798 uint64_t reserved_36_63:28;
799 uint64_t cnt3rdclr:1;
800 uint64_t cnt2rdclr:1;
801 uint64_t cnt1rdclr:1;
802 uint64_t cnt0rdclr:1;
803 uint64_t cnt3ena:1;
804 uint64_t cnt3clr:1;
805 uint64_t cnt3sel:6;
806 uint64_t cnt2ena:1;
807 uint64_t cnt2clr:1;
808 uint64_t cnt2sel:6;
809 uint64_t cnt1ena:1;
810 uint64_t cnt1clr:1;
811 uint64_t cnt1sel:6;
812 uint64_t cnt0ena:1;
813 uint64_t cnt0clr:1;
814 uint64_t cnt0sel:6;
815 } s;
816 struct cvmx_l2c_pfctl_s cn30xx;
817 struct cvmx_l2c_pfctl_s cn31xx;
818 struct cvmx_l2c_pfctl_s cn38xx;
819 struct cvmx_l2c_pfctl_s cn38xxp2;
820 struct cvmx_l2c_pfctl_s cn50xx;
821 struct cvmx_l2c_pfctl_s cn52xx;
822 struct cvmx_l2c_pfctl_s cn52xxp1;
823 struct cvmx_l2c_pfctl_s cn56xx;
824 struct cvmx_l2c_pfctl_s cn56xxp1;
825 struct cvmx_l2c_pfctl_s cn58xx;
826 struct cvmx_l2c_pfctl_s cn58xxp1;
827};
828
829union cvmx_l2c_ppgrp {
830 uint64_t u64;
831 struct cvmx_l2c_ppgrp_s {
832 uint64_t reserved_24_63:40;
833 uint64_t pp11grp:2;
834 uint64_t pp10grp:2;
835 uint64_t pp9grp:2;
836 uint64_t pp8grp:2;
837 uint64_t pp7grp:2;
838 uint64_t pp6grp:2;
839 uint64_t pp5grp:2;
840 uint64_t pp4grp:2;
841 uint64_t pp3grp:2;
842 uint64_t pp2grp:2;
843 uint64_t pp1grp:2;
844 uint64_t pp0grp:2;
845 } s;
846 struct cvmx_l2c_ppgrp_cn52xx {
847 uint64_t reserved_8_63:56;
848 uint64_t pp3grp:2;
849 uint64_t pp2grp:2;
850 uint64_t pp1grp:2;
851 uint64_t pp0grp:2;
852 } cn52xx;
853 struct cvmx_l2c_ppgrp_cn52xx cn52xxp1;
854 struct cvmx_l2c_ppgrp_s cn56xx;
855 struct cvmx_l2c_ppgrp_s cn56xxp1;
856};
857
858union cvmx_l2c_spar0 {
859 uint64_t u64;
860 struct cvmx_l2c_spar0_s {
861 uint64_t reserved_32_63:32;
862 uint64_t umsk3:8;
863 uint64_t umsk2:8;
864 uint64_t umsk1:8;
865 uint64_t umsk0:8;
866 } s;
867 struct cvmx_l2c_spar0_cn30xx {
868 uint64_t reserved_4_63:60;
869 uint64_t umsk0:4;
870 } cn30xx;
871 struct cvmx_l2c_spar0_cn31xx {
872 uint64_t reserved_12_63:52;
873 uint64_t umsk1:4;
874 uint64_t reserved_4_7:4;
875 uint64_t umsk0:4;
876 } cn31xx;
877 struct cvmx_l2c_spar0_s cn38xx;
878 struct cvmx_l2c_spar0_s cn38xxp2;
879 struct cvmx_l2c_spar0_cn50xx {
880 uint64_t reserved_16_63:48;
881 uint64_t umsk1:8;
882 uint64_t umsk0:8;
883 } cn50xx;
884 struct cvmx_l2c_spar0_s cn52xx;
885 struct cvmx_l2c_spar0_s cn52xxp1;
886 struct cvmx_l2c_spar0_s cn56xx;
887 struct cvmx_l2c_spar0_s cn56xxp1;
888 struct cvmx_l2c_spar0_s cn58xx;
889 struct cvmx_l2c_spar0_s cn58xxp1;
890};
891
892union cvmx_l2c_spar1 {
893 uint64_t u64;
894 struct cvmx_l2c_spar1_s {
895 uint64_t reserved_32_63:32;
896 uint64_t umsk7:8;
897 uint64_t umsk6:8;
898 uint64_t umsk5:8;
899 uint64_t umsk4:8;
900 } s;
901 struct cvmx_l2c_spar1_s cn38xx;
902 struct cvmx_l2c_spar1_s cn38xxp2;
903 struct cvmx_l2c_spar1_s cn56xx;
904 struct cvmx_l2c_spar1_s cn56xxp1;
905 struct cvmx_l2c_spar1_s cn58xx;
906 struct cvmx_l2c_spar1_s cn58xxp1;
907};
908
909union cvmx_l2c_spar2 {
910 uint64_t u64;
911 struct cvmx_l2c_spar2_s {
912 uint64_t reserved_32_63:32;
913 uint64_t umsk11:8;
914 uint64_t umsk10:8;
915 uint64_t umsk9:8;
916 uint64_t umsk8:8;
917 } s;
918 struct cvmx_l2c_spar2_s cn38xx;
919 struct cvmx_l2c_spar2_s cn38xxp2;
920 struct cvmx_l2c_spar2_s cn56xx;
921 struct cvmx_l2c_spar2_s cn56xxp1;
922 struct cvmx_l2c_spar2_s cn58xx;
923 struct cvmx_l2c_spar2_s cn58xxp1;
924};
925
926union cvmx_l2c_spar3 {
927 uint64_t u64;
928 struct cvmx_l2c_spar3_s {
929 uint64_t reserved_32_63:32;
930 uint64_t umsk15:8;
931 uint64_t umsk14:8;
932 uint64_t umsk13:8;
933 uint64_t umsk12:8;
934 } s;
935 struct cvmx_l2c_spar3_s cn38xx;
936 struct cvmx_l2c_spar3_s cn38xxp2;
937 struct cvmx_l2c_spar3_s cn58xx;
938 struct cvmx_l2c_spar3_s cn58xxp1;
939};
940
941union cvmx_l2c_spar4 {
942 uint64_t u64;
943 struct cvmx_l2c_spar4_s {
944 uint64_t reserved_8_63:56;
945 uint64_t umskiob:8;
946 } s;
947 struct cvmx_l2c_spar4_cn30xx {
948 uint64_t reserved_4_63:60;
949 uint64_t umskiob:4;
950 } cn30xx;
951 struct cvmx_l2c_spar4_cn30xx cn31xx;
952 struct cvmx_l2c_spar4_s cn38xx;
953 struct cvmx_l2c_spar4_s cn38xxp2;
954 struct cvmx_l2c_spar4_s cn50xx;
955 struct cvmx_l2c_spar4_s cn52xx;
956 struct cvmx_l2c_spar4_s cn52xxp1;
957 struct cvmx_l2c_spar4_s cn56xx;
958 struct cvmx_l2c_spar4_s cn56xxp1;
959 struct cvmx_l2c_spar4_s cn58xx;
960 struct cvmx_l2c_spar4_s cn58xxp1;
961};
962
963#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
new file mode 100644
index 000000000000..2a8c0902ea50
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -0,0 +1,325 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
31 * facilities.
32 */
33
34#ifndef __CVMX_L2C_H__
35#define __CVMX_L2C_H__
36
37/* Deprecated macro, use function */
38#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc()
39
40/* Deprecated macro, use function */
41#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()
42
43/* Deprecated macro, use function */
44#define CVMX_L2_SETS cvmx_l2c_get_num_sets()
45
46#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
47#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
48
49/* Defines for index aliasing computations */
50#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
51 (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
52
53#define CVMX_L2C_ALIAS_MASK \
54 (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
55
56union cvmx_l2c_tag {
57 uint64_t u64;
58 struct {
59 uint64_t reserved:28;
60 uint64_t V:1; /* Line valid */
61 uint64_t D:1; /* Line dirty */
62 uint64_t L:1; /* Line locked */
63 uint64_t U:1; /* Use, LRU eviction */
64 uint64_t addr:32; /* Phys mem (not all bits valid) */
65 } s;
66};
67
68 /* L2C Performance Counter events. */
69enum cvmx_l2c_event {
70 CVMX_L2C_EVENT_CYCLES = 0,
71 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
73 CVMX_L2C_EVENT_DATA_MISS = 3,
74 CVMX_L2C_EVENT_DATA_HIT = 4,
75 CVMX_L2C_EVENT_MISS = 5,
76 CVMX_L2C_EVENT_HIT = 6,
77 CVMX_L2C_EVENT_VICTIM_HIT = 7,
78 CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
79 CVMX_L2C_EVENT_TAG_PROBE = 9,
80 CVMX_L2C_EVENT_TAG_UPDATE = 10,
81 CVMX_L2C_EVENT_TAG_COMPLETE = 11,
82 CVMX_L2C_EVENT_TAG_DIRTY = 12,
83 CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
84 CVMX_L2C_EVENT_DATA_STORE_READ = 14,
85 CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
86 CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
87 CVMX_L2C_EVENT_WRITE_REQUEST = 17,
88 CVMX_L2C_EVENT_READ_REQUEST = 18,
89 CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
90 CVMX_L2C_EVENT_XMC_NOP = 20,
91 CVMX_L2C_EVENT_XMC_LDT = 21,
92 CVMX_L2C_EVENT_XMC_LDI = 22,
93 CVMX_L2C_EVENT_XMC_LDD = 23,
94 CVMX_L2C_EVENT_XMC_STF = 24,
95 CVMX_L2C_EVENT_XMC_STT = 25,
96 CVMX_L2C_EVENT_XMC_STP = 26,
97 CVMX_L2C_EVENT_XMC_STC = 27,
98 CVMX_L2C_EVENT_XMC_DWB = 28,
99 CVMX_L2C_EVENT_XMC_PL2 = 29,
100 CVMX_L2C_EVENT_XMC_PSL1 = 30,
101 CVMX_L2C_EVENT_XMC_IOBLD = 31,
102 CVMX_L2C_EVENT_XMC_IOBST = 32,
103 CVMX_L2C_EVENT_XMC_IOBDMA = 33,
104 CVMX_L2C_EVENT_XMC_IOBRSP = 34,
105 CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
106 CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
107 CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
108 CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
109 CVMX_L2C_EVENT_RSC_NOP = 39,
110 CVMX_L2C_EVENT_RSC_STDN = 40,
111 CVMX_L2C_EVENT_RSC_FILL = 41,
112 CVMX_L2C_EVENT_RSC_REFL = 42,
113 CVMX_L2C_EVENT_RSC_STIN = 43,
114 CVMX_L2C_EVENT_RSC_SCIN = 44,
115 CVMX_L2C_EVENT_RSC_SCFL = 45,
116 CVMX_L2C_EVENT_RSC_SCDN = 46,
117 CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
118 CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
119 CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
120 CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
121 CVMX_L2C_EVENT_LRF_REQ = 51,
122 CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
123 CVMX_L2C_EVENT_DT_WR_INVAL = 53
124};
125
126/**
127 * Configure one of the four L2 Cache performance counters to capture event
128 * occurences.
129 *
130 * @counter: The counter to configure. Range 0..3.
131 * @event: The type of L2 Cache event occurrence to count.
132 * @clear_on_read: When asserted, any read of the performance counter
133 * clears the counter.
134 *
135 * The routine does not clear the counter.
136 */
137void cvmx_l2c_config_perf(uint32_t counter,
138 enum cvmx_l2c_event event, uint32_t clear_on_read);
139/**
140 * Read the given L2 Cache performance counter. The counter must be configured
141 * before reading, but this routine does not enforce this requirement.
142 *
143 * @counter: The counter to configure. Range 0..3.
144 *
145 * Returns The current counter value.
146 */
147uint64_t cvmx_l2c_read_perf(uint32_t counter);
148
149/**
150 * Return the L2 Cache way partitioning for a given core.
151 *
152 * @core: The core processor of interest.
153 *
154 * Returns The mask specifying the partitioning. 0 bits in mask indicates
155 * the cache 'ways' that a core can evict from.
156 * -1 on error
157 */
158int cvmx_l2c_get_core_way_partition(uint32_t core);
159
160/**
161 * Partitions the L2 cache for a core
162 *
163 * @core: The core that the partitioning applies to.
164 *
165 * @mask: The partitioning of the ways expressed as a binary mask. A 0
166 * bit allows the core to evict cache lines from a way, while a
167 * 1 bit blocks the core from evicting any lines from that
168 * way. There must be at least one allowed way (0 bit) in the
169 * mask.
170 *
171 * If any ways are blocked for all cores and the HW blocks, then those
172 * ways will never have any cache lines evicted from them. All cores
173 * and the hardware blocks are free to read from all ways regardless
174 * of the partitioning.
175 */
176int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
177
178/**
179 * Return the L2 Cache way partitioning for the hw blocks.
180 *
181 * Returns The mask specifying the reserved way. 0 bits in mask indicates
182 * the cache 'ways' that a core can evict from.
183 * -1 on error
184 */
185int cvmx_l2c_get_hw_way_partition(void);
186
187/**
188 * Partitions the L2 cache for the hardware blocks.
189 *
190 * @mask: The partitioning of the ways expressed as a binary mask. A 0
191 * bit allows the core to evict cache lines from a way, while a
192 * 1 bit blocks the core from evicting any lines from that
193 * way. There must be at least one allowed way (0 bit) in the
194 * mask.
195 *
196 * If any ways are blocked for all cores and the HW blocks, then those
197 * ways will never have any cache lines evicted from them. All cores
198 * and the hardware blocks are free to read from all ways regardless
199 * of the partitioning.
200 */
201int cvmx_l2c_set_hw_way_partition(uint32_t mask);
202
203/**
204 * Locks a line in the L2 cache at the specified physical address
205 *
206 * @addr: physical address of line to lock
207 *
208 * Returns 0 on success,
209 * 1 if line not locked.
210 */
211int cvmx_l2c_lock_line(uint64_t addr);
212
213/**
214 * Locks a specified memory region in the L2 cache.
215 *
216 * Note that if not all lines can be locked, that means that all
217 * but one of the ways (associations) available to the locking
218 * core are locked. Having only 1 association available for
219 * normal caching may have a significant adverse affect on performance.
220 * Care should be taken to ensure that enough of the L2 cache is left
221 * unlocked to allow for normal caching of DRAM.
222 *
223 * @start: Physical address of the start of the region to lock
224 * @len: Length (in bytes) of region to lock
225 *
226 * Returns Number of requested lines that where not locked.
227 * 0 on success (all locked)
228 */
229int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
230
231/**
232 * Unlock and flush a cache line from the L2 cache.
233 * IMPORTANT: Must only be run by one core at a time due to use
234 * of L2C debug features.
235 * Note that this function will flush a matching but unlocked cache line.
236 * (If address is not in L2, no lines are flushed.)
237 *
238 * @address: Physical address to unlock
239 *
240 * Returns 0: line not unlocked
241 * 1: line unlocked
242 */
243int cvmx_l2c_unlock_line(uint64_t address);
244
245/**
246 * Unlocks a region of memory that is locked in the L2 cache
247 *
248 * @start: start physical address
249 * @len: length (in bytes) to unlock
250 *
251 * Returns Number of locked lines that the call unlocked
252 */
253int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
254
255/**
256 * Read the L2 controller tag for a given location in L2
257 *
258 * @association:
259 * Which association to read line from
260 * @index: Which way to read from.
261 *
262 * Returns l2c tag structure for line requested.
263 */
264union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
265
266/* Wrapper around deprecated old function name */
267static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
268 uint32_t index)
269{
270 return cvmx_l2c_get_tag(association, index);
271}
272
273/**
274 * Returns the cache index for a given physical address
275 *
276 * @addr: physical address
277 *
278 * Returns L2 cache index
279 */
280uint32_t cvmx_l2c_address_to_index(uint64_t addr);
281
282/**
283 * Flushes (and unlocks) the entire L2 cache.
284 * IMPORTANT: Must only be run by one core at a time due to use
285 * of L2C debug features.
286 */
287void cvmx_l2c_flush(void);
288
289/**
290 *
291 * Returns Returns the size of the L2 cache in bytes,
292 * -1 on error (unrecognized model)
293 */
294int cvmx_l2c_get_cache_size_bytes(void);
295
296/**
297 * Return the number of sets in the L2 Cache
298 *
299 * Returns
300 */
301int cvmx_l2c_get_num_sets(void);
302
303/**
304 * Return log base 2 of the number of sets in the L2 cache
305 * Returns
306 */
307int cvmx_l2c_get_set_bits(void);
308/**
309 * Return the number of associations in the L2 Cache
310 *
311 * Returns
312 */
313int cvmx_l2c_get_num_assoc(void);
314
315/**
316 * Flush a line from the L2 cache
317 * This should only be called from one core at a time, as this routine
318 * sets the core to the 'debug' core in order to flush the line.
319 *
320 * @assoc: Association (or way) to flush
321 * @index: Index to flush
322 */
323void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
324
325#endif /* __CVMX_L2C_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
new file mode 100644
index 000000000000..d7102d455e1b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -0,0 +1,369 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2D_DEFS_H__
29#define __CVMX_L2D_DEFS_H__
30
31#define CVMX_L2D_BST0 \
32 CVMX_ADD_IO_SEG(0x0001180080000780ull)
33#define CVMX_L2D_BST1 \
34 CVMX_ADD_IO_SEG(0x0001180080000788ull)
35#define CVMX_L2D_BST2 \
36 CVMX_ADD_IO_SEG(0x0001180080000790ull)
37#define CVMX_L2D_BST3 \
38 CVMX_ADD_IO_SEG(0x0001180080000798ull)
39#define CVMX_L2D_ERR \
40 CVMX_ADD_IO_SEG(0x0001180080000010ull)
41#define CVMX_L2D_FADR \
42 CVMX_ADD_IO_SEG(0x0001180080000018ull)
43#define CVMX_L2D_FSYN0 \
44 CVMX_ADD_IO_SEG(0x0001180080000020ull)
45#define CVMX_L2D_FSYN1 \
46 CVMX_ADD_IO_SEG(0x0001180080000028ull)
47#define CVMX_L2D_FUS0 \
48 CVMX_ADD_IO_SEG(0x00011800800007A0ull)
49#define CVMX_L2D_FUS1 \
50 CVMX_ADD_IO_SEG(0x00011800800007A8ull)
51#define CVMX_L2D_FUS2 \
52 CVMX_ADD_IO_SEG(0x00011800800007B0ull)
53#define CVMX_L2D_FUS3 \
54 CVMX_ADD_IO_SEG(0x00011800800007B8ull)
55
56union cvmx_l2d_bst0 {
57 uint64_t u64;
58 struct cvmx_l2d_bst0_s {
59 uint64_t reserved_35_63:29;
60 uint64_t ftl:1;
61 uint64_t q0stat:34;
62 } s;
63 struct cvmx_l2d_bst0_s cn30xx;
64 struct cvmx_l2d_bst0_s cn31xx;
65 struct cvmx_l2d_bst0_s cn38xx;
66 struct cvmx_l2d_bst0_s cn38xxp2;
67 struct cvmx_l2d_bst0_s cn50xx;
68 struct cvmx_l2d_bst0_s cn52xx;
69 struct cvmx_l2d_bst0_s cn52xxp1;
70 struct cvmx_l2d_bst0_s cn56xx;
71 struct cvmx_l2d_bst0_s cn56xxp1;
72 struct cvmx_l2d_bst0_s cn58xx;
73 struct cvmx_l2d_bst0_s cn58xxp1;
74};
75
76union cvmx_l2d_bst1 {
77 uint64_t u64;
78 struct cvmx_l2d_bst1_s {
79 uint64_t reserved_34_63:30;
80 uint64_t q1stat:34;
81 } s;
82 struct cvmx_l2d_bst1_s cn30xx;
83 struct cvmx_l2d_bst1_s cn31xx;
84 struct cvmx_l2d_bst1_s cn38xx;
85 struct cvmx_l2d_bst1_s cn38xxp2;
86 struct cvmx_l2d_bst1_s cn50xx;
87 struct cvmx_l2d_bst1_s cn52xx;
88 struct cvmx_l2d_bst1_s cn52xxp1;
89 struct cvmx_l2d_bst1_s cn56xx;
90 struct cvmx_l2d_bst1_s cn56xxp1;
91 struct cvmx_l2d_bst1_s cn58xx;
92 struct cvmx_l2d_bst1_s cn58xxp1;
93};
94
95union cvmx_l2d_bst2 {
96 uint64_t u64;
97 struct cvmx_l2d_bst2_s {
98 uint64_t reserved_34_63:30;
99 uint64_t q2stat:34;
100 } s;
101 struct cvmx_l2d_bst2_s cn30xx;
102 struct cvmx_l2d_bst2_s cn31xx;
103 struct cvmx_l2d_bst2_s cn38xx;
104 struct cvmx_l2d_bst2_s cn38xxp2;
105 struct cvmx_l2d_bst2_s cn50xx;
106 struct cvmx_l2d_bst2_s cn52xx;
107 struct cvmx_l2d_bst2_s cn52xxp1;
108 struct cvmx_l2d_bst2_s cn56xx;
109 struct cvmx_l2d_bst2_s cn56xxp1;
110 struct cvmx_l2d_bst2_s cn58xx;
111 struct cvmx_l2d_bst2_s cn58xxp1;
112};
113
114union cvmx_l2d_bst3 {
115 uint64_t u64;
116 struct cvmx_l2d_bst3_s {
117 uint64_t reserved_34_63:30;
118 uint64_t q3stat:34;
119 } s;
120 struct cvmx_l2d_bst3_s cn30xx;
121 struct cvmx_l2d_bst3_s cn31xx;
122 struct cvmx_l2d_bst3_s cn38xx;
123 struct cvmx_l2d_bst3_s cn38xxp2;
124 struct cvmx_l2d_bst3_s cn50xx;
125 struct cvmx_l2d_bst3_s cn52xx;
126 struct cvmx_l2d_bst3_s cn52xxp1;
127 struct cvmx_l2d_bst3_s cn56xx;
128 struct cvmx_l2d_bst3_s cn56xxp1;
129 struct cvmx_l2d_bst3_s cn58xx;
130 struct cvmx_l2d_bst3_s cn58xxp1;
131};
132
133union cvmx_l2d_err {
134 uint64_t u64;
135 struct cvmx_l2d_err_s {
136 uint64_t reserved_6_63:58;
137 uint64_t bmhclsel:1;
138 uint64_t ded_err:1;
139 uint64_t sec_err:1;
140 uint64_t ded_intena:1;
141 uint64_t sec_intena:1;
142 uint64_t ecc_ena:1;
143 } s;
144 struct cvmx_l2d_err_s cn30xx;
145 struct cvmx_l2d_err_s cn31xx;
146 struct cvmx_l2d_err_s cn38xx;
147 struct cvmx_l2d_err_s cn38xxp2;
148 struct cvmx_l2d_err_s cn50xx;
149 struct cvmx_l2d_err_s cn52xx;
150 struct cvmx_l2d_err_s cn52xxp1;
151 struct cvmx_l2d_err_s cn56xx;
152 struct cvmx_l2d_err_s cn56xxp1;
153 struct cvmx_l2d_err_s cn58xx;
154 struct cvmx_l2d_err_s cn58xxp1;
155};
156
157union cvmx_l2d_fadr {
158 uint64_t u64;
159 struct cvmx_l2d_fadr_s {
160 uint64_t reserved_19_63:45;
161 uint64_t fadru:1;
162 uint64_t fowmsk:4;
163 uint64_t fset:3;
164 uint64_t fadr:11;
165 } s;
166 struct cvmx_l2d_fadr_cn30xx {
167 uint64_t reserved_18_63:46;
168 uint64_t fowmsk:4;
169 uint64_t reserved_13_13:1;
170 uint64_t fset:2;
171 uint64_t reserved_9_10:2;
172 uint64_t fadr:9;
173 } cn30xx;
174 struct cvmx_l2d_fadr_cn31xx {
175 uint64_t reserved_18_63:46;
176 uint64_t fowmsk:4;
177 uint64_t reserved_13_13:1;
178 uint64_t fset:2;
179 uint64_t reserved_10_10:1;
180 uint64_t fadr:10;
181 } cn31xx;
182 struct cvmx_l2d_fadr_cn38xx {
183 uint64_t reserved_18_63:46;
184 uint64_t fowmsk:4;
185 uint64_t fset:3;
186 uint64_t fadr:11;
187 } cn38xx;
188 struct cvmx_l2d_fadr_cn38xx cn38xxp2;
189 struct cvmx_l2d_fadr_cn50xx {
190 uint64_t reserved_18_63:46;
191 uint64_t fowmsk:4;
192 uint64_t fset:3;
193 uint64_t reserved_8_10:3;
194 uint64_t fadr:8;
195 } cn50xx;
196 struct cvmx_l2d_fadr_cn52xx {
197 uint64_t reserved_18_63:46;
198 uint64_t fowmsk:4;
199 uint64_t fset:3;
200 uint64_t reserved_10_10:1;
201 uint64_t fadr:10;
202 } cn52xx;
203 struct cvmx_l2d_fadr_cn52xx cn52xxp1;
204 struct cvmx_l2d_fadr_s cn56xx;
205 struct cvmx_l2d_fadr_s cn56xxp1;
206 struct cvmx_l2d_fadr_s cn58xx;
207 struct cvmx_l2d_fadr_s cn58xxp1;
208};
209
210union cvmx_l2d_fsyn0 {
211 uint64_t u64;
212 struct cvmx_l2d_fsyn0_s {
213 uint64_t reserved_20_63:44;
214 uint64_t fsyn_ow1:10;
215 uint64_t fsyn_ow0:10;
216 } s;
217 struct cvmx_l2d_fsyn0_s cn30xx;
218 struct cvmx_l2d_fsyn0_s cn31xx;
219 struct cvmx_l2d_fsyn0_s cn38xx;
220 struct cvmx_l2d_fsyn0_s cn38xxp2;
221 struct cvmx_l2d_fsyn0_s cn50xx;
222 struct cvmx_l2d_fsyn0_s cn52xx;
223 struct cvmx_l2d_fsyn0_s cn52xxp1;
224 struct cvmx_l2d_fsyn0_s cn56xx;
225 struct cvmx_l2d_fsyn0_s cn56xxp1;
226 struct cvmx_l2d_fsyn0_s cn58xx;
227 struct cvmx_l2d_fsyn0_s cn58xxp1;
228};
229
230union cvmx_l2d_fsyn1 {
231 uint64_t u64;
232 struct cvmx_l2d_fsyn1_s {
233 uint64_t reserved_20_63:44;
234 uint64_t fsyn_ow3:10;
235 uint64_t fsyn_ow2:10;
236 } s;
237 struct cvmx_l2d_fsyn1_s cn30xx;
238 struct cvmx_l2d_fsyn1_s cn31xx;
239 struct cvmx_l2d_fsyn1_s cn38xx;
240 struct cvmx_l2d_fsyn1_s cn38xxp2;
241 struct cvmx_l2d_fsyn1_s cn50xx;
242 struct cvmx_l2d_fsyn1_s cn52xx;
243 struct cvmx_l2d_fsyn1_s cn52xxp1;
244 struct cvmx_l2d_fsyn1_s cn56xx;
245 struct cvmx_l2d_fsyn1_s cn56xxp1;
246 struct cvmx_l2d_fsyn1_s cn58xx;
247 struct cvmx_l2d_fsyn1_s cn58xxp1;
248};
249
250union cvmx_l2d_fus0 {
251 uint64_t u64;
252 struct cvmx_l2d_fus0_s {
253 uint64_t reserved_34_63:30;
254 uint64_t q0fus:34;
255 } s;
256 struct cvmx_l2d_fus0_s cn30xx;
257 struct cvmx_l2d_fus0_s cn31xx;
258 struct cvmx_l2d_fus0_s cn38xx;
259 struct cvmx_l2d_fus0_s cn38xxp2;
260 struct cvmx_l2d_fus0_s cn50xx;
261 struct cvmx_l2d_fus0_s cn52xx;
262 struct cvmx_l2d_fus0_s cn52xxp1;
263 struct cvmx_l2d_fus0_s cn56xx;
264 struct cvmx_l2d_fus0_s cn56xxp1;
265 struct cvmx_l2d_fus0_s cn58xx;
266 struct cvmx_l2d_fus0_s cn58xxp1;
267};
268
269union cvmx_l2d_fus1 {
270 uint64_t u64;
271 struct cvmx_l2d_fus1_s {
272 uint64_t reserved_34_63:30;
273 uint64_t q1fus:34;
274 } s;
275 struct cvmx_l2d_fus1_s cn30xx;
276 struct cvmx_l2d_fus1_s cn31xx;
277 struct cvmx_l2d_fus1_s cn38xx;
278 struct cvmx_l2d_fus1_s cn38xxp2;
279 struct cvmx_l2d_fus1_s cn50xx;
280 struct cvmx_l2d_fus1_s cn52xx;
281 struct cvmx_l2d_fus1_s cn52xxp1;
282 struct cvmx_l2d_fus1_s cn56xx;
283 struct cvmx_l2d_fus1_s cn56xxp1;
284 struct cvmx_l2d_fus1_s cn58xx;
285 struct cvmx_l2d_fus1_s cn58xxp1;
286};
287
288union cvmx_l2d_fus2 {
289 uint64_t u64;
290 struct cvmx_l2d_fus2_s {
291 uint64_t reserved_34_63:30;
292 uint64_t q2fus:34;
293 } s;
294 struct cvmx_l2d_fus2_s cn30xx;
295 struct cvmx_l2d_fus2_s cn31xx;
296 struct cvmx_l2d_fus2_s cn38xx;
297 struct cvmx_l2d_fus2_s cn38xxp2;
298 struct cvmx_l2d_fus2_s cn50xx;
299 struct cvmx_l2d_fus2_s cn52xx;
300 struct cvmx_l2d_fus2_s cn52xxp1;
301 struct cvmx_l2d_fus2_s cn56xx;
302 struct cvmx_l2d_fus2_s cn56xxp1;
303 struct cvmx_l2d_fus2_s cn58xx;
304 struct cvmx_l2d_fus2_s cn58xxp1;
305};
306
307union cvmx_l2d_fus3 {
308 uint64_t u64;
309 struct cvmx_l2d_fus3_s {
310 uint64_t reserved_40_63:24;
311 uint64_t ema_ctl:3;
312 uint64_t reserved_34_36:3;
313 uint64_t q3fus:34;
314 } s;
315 struct cvmx_l2d_fus3_cn30xx {
316 uint64_t reserved_35_63:29;
317 uint64_t crip_64k:1;
318 uint64_t q3fus:34;
319 } cn30xx;
320 struct cvmx_l2d_fus3_cn31xx {
321 uint64_t reserved_35_63:29;
322 uint64_t crip_128k:1;
323 uint64_t q3fus:34;
324 } cn31xx;
325 struct cvmx_l2d_fus3_cn38xx {
326 uint64_t reserved_36_63:28;
327 uint64_t crip_256k:1;
328 uint64_t crip_512k:1;
329 uint64_t q3fus:34;
330 } cn38xx;
331 struct cvmx_l2d_fus3_cn38xx cn38xxp2;
332 struct cvmx_l2d_fus3_cn50xx {
333 uint64_t reserved_40_63:24;
334 uint64_t ema_ctl:3;
335 uint64_t reserved_36_36:1;
336 uint64_t crip_32k:1;
337 uint64_t crip_64k:1;
338 uint64_t q3fus:34;
339 } cn50xx;
340 struct cvmx_l2d_fus3_cn52xx {
341 uint64_t reserved_40_63:24;
342 uint64_t ema_ctl:3;
343 uint64_t reserved_36_36:1;
344 uint64_t crip_128k:1;
345 uint64_t crip_256k:1;
346 uint64_t q3fus:34;
347 } cn52xx;
348 struct cvmx_l2d_fus3_cn52xx cn52xxp1;
349 struct cvmx_l2d_fus3_cn56xx {
350 uint64_t reserved_40_63:24;
351 uint64_t ema_ctl:3;
352 uint64_t reserved_36_36:1;
353 uint64_t crip_512k:1;
354 uint64_t crip_1024k:1;
355 uint64_t q3fus:34;
356 } cn56xx;
357 struct cvmx_l2d_fus3_cn56xx cn56xxp1;
358 struct cvmx_l2d_fus3_cn58xx {
359 uint64_t reserved_39_63:25;
360 uint64_t ema_ctl:2;
361 uint64_t reserved_36_36:1;
362 uint64_t crip_512k:1;
363 uint64_t crip_1024k:1;
364 uint64_t q3fus:34;
365 } cn58xx;
366 struct cvmx_l2d_fus3_cn58xx cn58xxp1;
367};
368
369#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
new file mode 100644
index 000000000000..2639a3f5ffc2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -0,0 +1,141 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2T_DEFS_H__
29#define __CVMX_L2T_DEFS_H__
30
31#define CVMX_L2T_ERR \
32 CVMX_ADD_IO_SEG(0x0001180080000008ull)
33
34union cvmx_l2t_err {
35 uint64_t u64;
36 struct cvmx_l2t_err_s {
37 uint64_t reserved_29_63:35;
38 uint64_t fadru:1;
39 uint64_t lck_intena2:1;
40 uint64_t lckerr2:1;
41 uint64_t lck_intena:1;
42 uint64_t lckerr:1;
43 uint64_t fset:3;
44 uint64_t fadr:10;
45 uint64_t fsyn:6;
46 uint64_t ded_err:1;
47 uint64_t sec_err:1;
48 uint64_t ded_intena:1;
49 uint64_t sec_intena:1;
50 uint64_t ecc_ena:1;
51 } s;
52 struct cvmx_l2t_err_cn30xx {
53 uint64_t reserved_28_63:36;
54 uint64_t lck_intena2:1;
55 uint64_t lckerr2:1;
56 uint64_t lck_intena:1;
57 uint64_t lckerr:1;
58 uint64_t reserved_23_23:1;
59 uint64_t fset:2;
60 uint64_t reserved_19_20:2;
61 uint64_t fadr:8;
62 uint64_t fsyn:6;
63 uint64_t ded_err:1;
64 uint64_t sec_err:1;
65 uint64_t ded_intena:1;
66 uint64_t sec_intena:1;
67 uint64_t ecc_ena:1;
68 } cn30xx;
69 struct cvmx_l2t_err_cn31xx {
70 uint64_t reserved_28_63:36;
71 uint64_t lck_intena2:1;
72 uint64_t lckerr2:1;
73 uint64_t lck_intena:1;
74 uint64_t lckerr:1;
75 uint64_t reserved_23_23:1;
76 uint64_t fset:2;
77 uint64_t reserved_20_20:1;
78 uint64_t fadr:9;
79 uint64_t fsyn:6;
80 uint64_t ded_err:1;
81 uint64_t sec_err:1;
82 uint64_t ded_intena:1;
83 uint64_t sec_intena:1;
84 uint64_t ecc_ena:1;
85 } cn31xx;
86 struct cvmx_l2t_err_cn38xx {
87 uint64_t reserved_28_63:36;
88 uint64_t lck_intena2:1;
89 uint64_t lckerr2:1;
90 uint64_t lck_intena:1;
91 uint64_t lckerr:1;
92 uint64_t fset:3;
93 uint64_t fadr:10;
94 uint64_t fsyn:6;
95 uint64_t ded_err:1;
96 uint64_t sec_err:1;
97 uint64_t ded_intena:1;
98 uint64_t sec_intena:1;
99 uint64_t ecc_ena:1;
100 } cn38xx;
101 struct cvmx_l2t_err_cn38xx cn38xxp2;
102 struct cvmx_l2t_err_cn50xx {
103 uint64_t reserved_28_63:36;
104 uint64_t lck_intena2:1;
105 uint64_t lckerr2:1;
106 uint64_t lck_intena:1;
107 uint64_t lckerr:1;
108 uint64_t fset:3;
109 uint64_t reserved_18_20:3;
110 uint64_t fadr:7;
111 uint64_t fsyn:6;
112 uint64_t ded_err:1;
113 uint64_t sec_err:1;
114 uint64_t ded_intena:1;
115 uint64_t sec_intena:1;
116 uint64_t ecc_ena:1;
117 } cn50xx;
118 struct cvmx_l2t_err_cn52xx {
119 uint64_t reserved_28_63:36;
120 uint64_t lck_intena2:1;
121 uint64_t lckerr2:1;
122 uint64_t lck_intena:1;
123 uint64_t lckerr:1;
124 uint64_t fset:3;
125 uint64_t reserved_20_20:1;
126 uint64_t fadr:9;
127 uint64_t fsyn:6;
128 uint64_t ded_err:1;
129 uint64_t sec_err:1;
130 uint64_t ded_intena:1;
131 uint64_t sec_intena:1;
132 uint64_t ecc_ena:1;
133 } cn52xx;
134 struct cvmx_l2t_err_cn52xx cn52xxp1;
135 struct cvmx_l2t_err_s cn56xx;
136 struct cvmx_l2t_err_s cn56xxp1;
137 struct cvmx_l2t_err_s cn58xx;
138 struct cvmx_l2t_err_s cn58xxp1;
139};
140
141#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
new file mode 100644
index 000000000000..16f174a4dadf
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -0,0 +1,240 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_LED_DEFS_H__
29#define __CVMX_LED_DEFS_H__
30
31#define CVMX_LED_BLINK \
32 CVMX_ADD_IO_SEG(0x0001180000001A48ull)
33#define CVMX_LED_CLK_PHASE \
34 CVMX_ADD_IO_SEG(0x0001180000001A08ull)
35#define CVMX_LED_CYLON \
36 CVMX_ADD_IO_SEG(0x0001180000001AF8ull)
37#define CVMX_LED_DBG \
38 CVMX_ADD_IO_SEG(0x0001180000001A18ull)
39#define CVMX_LED_EN \
40 CVMX_ADD_IO_SEG(0x0001180000001A00ull)
41#define CVMX_LED_POLARITY \
42 CVMX_ADD_IO_SEG(0x0001180000001A50ull)
43#define CVMX_LED_PRT \
44 CVMX_ADD_IO_SEG(0x0001180000001A10ull)
45#define CVMX_LED_PRT_FMT \
46 CVMX_ADD_IO_SEG(0x0001180000001A30ull)
47#define CVMX_LED_PRT_STATUSX(offset) \
48 CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
49#define CVMX_LED_UDD_CNTX(offset) \
50 CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
51#define CVMX_LED_UDD_DATX(offset) \
52 CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
53#define CVMX_LED_UDD_DAT_CLRX(offset) \
54 CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
55#define CVMX_LED_UDD_DAT_SETX(offset) \
56 CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
57
58union cvmx_led_blink {
59 uint64_t u64;
60 struct cvmx_led_blink_s {
61 uint64_t reserved_8_63:56;
62 uint64_t rate:8;
63 } s;
64 struct cvmx_led_blink_s cn38xx;
65 struct cvmx_led_blink_s cn38xxp2;
66 struct cvmx_led_blink_s cn56xx;
67 struct cvmx_led_blink_s cn56xxp1;
68 struct cvmx_led_blink_s cn58xx;
69 struct cvmx_led_blink_s cn58xxp1;
70};
71
72union cvmx_led_clk_phase {
73 uint64_t u64;
74 struct cvmx_led_clk_phase_s {
75 uint64_t reserved_7_63:57;
76 uint64_t phase:7;
77 } s;
78 struct cvmx_led_clk_phase_s cn38xx;
79 struct cvmx_led_clk_phase_s cn38xxp2;
80 struct cvmx_led_clk_phase_s cn56xx;
81 struct cvmx_led_clk_phase_s cn56xxp1;
82 struct cvmx_led_clk_phase_s cn58xx;
83 struct cvmx_led_clk_phase_s cn58xxp1;
84};
85
86union cvmx_led_cylon {
87 uint64_t u64;
88 struct cvmx_led_cylon_s {
89 uint64_t reserved_16_63:48;
90 uint64_t rate:16;
91 } s;
92 struct cvmx_led_cylon_s cn38xx;
93 struct cvmx_led_cylon_s cn38xxp2;
94 struct cvmx_led_cylon_s cn56xx;
95 struct cvmx_led_cylon_s cn56xxp1;
96 struct cvmx_led_cylon_s cn58xx;
97 struct cvmx_led_cylon_s cn58xxp1;
98};
99
100union cvmx_led_dbg {
101 uint64_t u64;
102 struct cvmx_led_dbg_s {
103 uint64_t reserved_1_63:63;
104 uint64_t dbg_en:1;
105 } s;
106 struct cvmx_led_dbg_s cn38xx;
107 struct cvmx_led_dbg_s cn38xxp2;
108 struct cvmx_led_dbg_s cn56xx;
109 struct cvmx_led_dbg_s cn56xxp1;
110 struct cvmx_led_dbg_s cn58xx;
111 struct cvmx_led_dbg_s cn58xxp1;
112};
113
114union cvmx_led_en {
115 uint64_t u64;
116 struct cvmx_led_en_s {
117 uint64_t reserved_1_63:63;
118 uint64_t en:1;
119 } s;
120 struct cvmx_led_en_s cn38xx;
121 struct cvmx_led_en_s cn38xxp2;
122 struct cvmx_led_en_s cn56xx;
123 struct cvmx_led_en_s cn56xxp1;
124 struct cvmx_led_en_s cn58xx;
125 struct cvmx_led_en_s cn58xxp1;
126};
127
128union cvmx_led_polarity {
129 uint64_t u64;
130 struct cvmx_led_polarity_s {
131 uint64_t reserved_1_63:63;
132 uint64_t polarity:1;
133 } s;
134 struct cvmx_led_polarity_s cn38xx;
135 struct cvmx_led_polarity_s cn38xxp2;
136 struct cvmx_led_polarity_s cn56xx;
137 struct cvmx_led_polarity_s cn56xxp1;
138 struct cvmx_led_polarity_s cn58xx;
139 struct cvmx_led_polarity_s cn58xxp1;
140};
141
142union cvmx_led_prt {
143 uint64_t u64;
144 struct cvmx_led_prt_s {
145 uint64_t reserved_8_63:56;
146 uint64_t prt_en:8;
147 } s;
148 struct cvmx_led_prt_s cn38xx;
149 struct cvmx_led_prt_s cn38xxp2;
150 struct cvmx_led_prt_s cn56xx;
151 struct cvmx_led_prt_s cn56xxp1;
152 struct cvmx_led_prt_s cn58xx;
153 struct cvmx_led_prt_s cn58xxp1;
154};
155
156union cvmx_led_prt_fmt {
157 uint64_t u64;
158 struct cvmx_led_prt_fmt_s {
159 uint64_t reserved_4_63:60;
160 uint64_t format:4;
161 } s;
162 struct cvmx_led_prt_fmt_s cn38xx;
163 struct cvmx_led_prt_fmt_s cn38xxp2;
164 struct cvmx_led_prt_fmt_s cn56xx;
165 struct cvmx_led_prt_fmt_s cn56xxp1;
166 struct cvmx_led_prt_fmt_s cn58xx;
167 struct cvmx_led_prt_fmt_s cn58xxp1;
168};
169
170union cvmx_led_prt_statusx {
171 uint64_t u64;
172 struct cvmx_led_prt_statusx_s {
173 uint64_t reserved_6_63:58;
174 uint64_t status:6;
175 } s;
176 struct cvmx_led_prt_statusx_s cn38xx;
177 struct cvmx_led_prt_statusx_s cn38xxp2;
178 struct cvmx_led_prt_statusx_s cn56xx;
179 struct cvmx_led_prt_statusx_s cn56xxp1;
180 struct cvmx_led_prt_statusx_s cn58xx;
181 struct cvmx_led_prt_statusx_s cn58xxp1;
182};
183
184union cvmx_led_udd_cntx {
185 uint64_t u64;
186 struct cvmx_led_udd_cntx_s {
187 uint64_t reserved_6_63:58;
188 uint64_t cnt:6;
189 } s;
190 struct cvmx_led_udd_cntx_s cn38xx;
191 struct cvmx_led_udd_cntx_s cn38xxp2;
192 struct cvmx_led_udd_cntx_s cn56xx;
193 struct cvmx_led_udd_cntx_s cn56xxp1;
194 struct cvmx_led_udd_cntx_s cn58xx;
195 struct cvmx_led_udd_cntx_s cn58xxp1;
196};
197
198union cvmx_led_udd_datx {
199 uint64_t u64;
200 struct cvmx_led_udd_datx_s {
201 uint64_t reserved_32_63:32;
202 uint64_t dat:32;
203 } s;
204 struct cvmx_led_udd_datx_s cn38xx;
205 struct cvmx_led_udd_datx_s cn38xxp2;
206 struct cvmx_led_udd_datx_s cn56xx;
207 struct cvmx_led_udd_datx_s cn56xxp1;
208 struct cvmx_led_udd_datx_s cn58xx;
209 struct cvmx_led_udd_datx_s cn58xxp1;
210};
211
212union cvmx_led_udd_dat_clrx {
213 uint64_t u64;
214 struct cvmx_led_udd_dat_clrx_s {
215 uint64_t reserved_32_63:32;
216 uint64_t clr:32;
217 } s;
218 struct cvmx_led_udd_dat_clrx_s cn38xx;
219 struct cvmx_led_udd_dat_clrx_s cn38xxp2;
220 struct cvmx_led_udd_dat_clrx_s cn56xx;
221 struct cvmx_led_udd_dat_clrx_s cn56xxp1;
222 struct cvmx_led_udd_dat_clrx_s cn58xx;
223 struct cvmx_led_udd_dat_clrx_s cn58xxp1;
224};
225
226union cvmx_led_udd_dat_setx {
227 uint64_t u64;
228 struct cvmx_led_udd_dat_setx_s {
229 uint64_t reserved_32_63:32;
230 uint64_t set:32;
231 } s;
232 struct cvmx_led_udd_dat_setx_s cn38xx;
233 struct cvmx_led_udd_dat_setx_s cn38xxp2;
234 struct cvmx_led_udd_dat_setx_s cn56xx;
235 struct cvmx_led_udd_dat_setx_s cn56xxp1;
236 struct cvmx_led_udd_dat_setx_s cn58xx;
237 struct cvmx_led_udd_dat_setx_s cn58xxp1;
238};
239
240#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
new file mode 100644
index 000000000000..6555f0530988
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -0,0 +1,2004 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIO_DEFS_H__
29#define __CVMX_MIO_DEFS_H__
30
31#define CVMX_MIO_BOOT_BIST_STAT \
32 CVMX_ADD_IO_SEG(0x00011800000000F8ull)
33#define CVMX_MIO_BOOT_COMP \
34 CVMX_ADD_IO_SEG(0x00011800000000B8ull)
35#define CVMX_MIO_BOOT_DMA_CFGX(offset) \
36 CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8))
37#define CVMX_MIO_BOOT_DMA_INTX(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8))
39#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8))
41#define CVMX_MIO_BOOT_DMA_TIMX(offset) \
42 CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8))
43#define CVMX_MIO_BOOT_ERR \
44 CVMX_ADD_IO_SEG(0x00011800000000A0ull)
45#define CVMX_MIO_BOOT_INT \
46 CVMX_ADD_IO_SEG(0x00011800000000A8ull)
47#define CVMX_MIO_BOOT_LOC_ADR \
48 CVMX_ADD_IO_SEG(0x0001180000000090ull)
49#define CVMX_MIO_BOOT_LOC_CFGX(offset) \
50 CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8))
51#define CVMX_MIO_BOOT_LOC_DAT \
52 CVMX_ADD_IO_SEG(0x0001180000000098ull)
53#define CVMX_MIO_BOOT_PIN_DEFS \
54 CVMX_ADD_IO_SEG(0x00011800000000C0ull)
55#define CVMX_MIO_BOOT_REG_CFGX(offset) \
56 CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8))
57#define CVMX_MIO_BOOT_REG_TIMX(offset) \
58 CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8))
59#define CVMX_MIO_BOOT_THR \
60 CVMX_ADD_IO_SEG(0x00011800000000B0ull)
61#define CVMX_MIO_FUS_BNK_DATX(offset) \
62 CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8))
63#define CVMX_MIO_FUS_DAT0 \
64 CVMX_ADD_IO_SEG(0x0001180000001400ull)
65#define CVMX_MIO_FUS_DAT1 \
66 CVMX_ADD_IO_SEG(0x0001180000001408ull)
67#define CVMX_MIO_FUS_DAT2 \
68 CVMX_ADD_IO_SEG(0x0001180000001410ull)
69#define CVMX_MIO_FUS_DAT3 \
70 CVMX_ADD_IO_SEG(0x0001180000001418ull)
71#define CVMX_MIO_FUS_EMA \
72 CVMX_ADD_IO_SEG(0x0001180000001550ull)
73#define CVMX_MIO_FUS_PDF \
74 CVMX_ADD_IO_SEG(0x0001180000001420ull)
75#define CVMX_MIO_FUS_PLL \
76 CVMX_ADD_IO_SEG(0x0001180000001580ull)
77#define CVMX_MIO_FUS_PROG \
78 CVMX_ADD_IO_SEG(0x0001180000001510ull)
79#define CVMX_MIO_FUS_PROG_TIMES \
80 CVMX_ADD_IO_SEG(0x0001180000001518ull)
81#define CVMX_MIO_FUS_RCMD \
82 CVMX_ADD_IO_SEG(0x0001180000001500ull)
83#define CVMX_MIO_FUS_SPR_REPAIR_RES \
84 CVMX_ADD_IO_SEG(0x0001180000001548ull)
85#define CVMX_MIO_FUS_SPR_REPAIR_SUM \
86 CVMX_ADD_IO_SEG(0x0001180000001540ull)
87#define CVMX_MIO_FUS_UNLOCK \
88 CVMX_ADD_IO_SEG(0x0001180000001578ull)
89#define CVMX_MIO_FUS_WADR \
90 CVMX_ADD_IO_SEG(0x0001180000001508ull)
91#define CVMX_MIO_NDF_DMA_CFG \
92 CVMX_ADD_IO_SEG(0x0001180000000168ull)
93#define CVMX_MIO_NDF_DMA_INT \
94 CVMX_ADD_IO_SEG(0x0001180000000170ull)
95#define CVMX_MIO_NDF_DMA_INT_EN \
96 CVMX_ADD_IO_SEG(0x0001180000000178ull)
97#define CVMX_MIO_PLL_CTL \
98 CVMX_ADD_IO_SEG(0x0001180000001448ull)
99#define CVMX_MIO_PLL_SETTING \
100 CVMX_ADD_IO_SEG(0x0001180000001440ull)
101#define CVMX_MIO_TWSX_INT(offset) \
102 CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512))
103#define CVMX_MIO_TWSX_SW_TWSI(offset) \
104 CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512))
105#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \
106 CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512))
107#define CVMX_MIO_TWSX_TWSI_SW(offset) \
108 CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512))
109#define CVMX_MIO_UART2_DLH \
110 CVMX_ADD_IO_SEG(0x0001180000000488ull)
111#define CVMX_MIO_UART2_DLL \
112 CVMX_ADD_IO_SEG(0x0001180000000480ull)
113#define CVMX_MIO_UART2_FAR \
114 CVMX_ADD_IO_SEG(0x0001180000000520ull)
115#define CVMX_MIO_UART2_FCR \
116 CVMX_ADD_IO_SEG(0x0001180000000450ull)
117#define CVMX_MIO_UART2_HTX \
118 CVMX_ADD_IO_SEG(0x0001180000000708ull)
119#define CVMX_MIO_UART2_IER \
120 CVMX_ADD_IO_SEG(0x0001180000000408ull)
121#define CVMX_MIO_UART2_IIR \
122 CVMX_ADD_IO_SEG(0x0001180000000410ull)
123#define CVMX_MIO_UART2_LCR \
124 CVMX_ADD_IO_SEG(0x0001180000000418ull)
125#define CVMX_MIO_UART2_LSR \
126 CVMX_ADD_IO_SEG(0x0001180000000428ull)
127#define CVMX_MIO_UART2_MCR \
128 CVMX_ADD_IO_SEG(0x0001180000000420ull)
129#define CVMX_MIO_UART2_MSR \
130 CVMX_ADD_IO_SEG(0x0001180000000430ull)
131#define CVMX_MIO_UART2_RBR \
132 CVMX_ADD_IO_SEG(0x0001180000000400ull)
133#define CVMX_MIO_UART2_RFL \
134 CVMX_ADD_IO_SEG(0x0001180000000608ull)
135#define CVMX_MIO_UART2_RFW \
136 CVMX_ADD_IO_SEG(0x0001180000000530ull)
137#define CVMX_MIO_UART2_SBCR \
138 CVMX_ADD_IO_SEG(0x0001180000000620ull)
139#define CVMX_MIO_UART2_SCR \
140 CVMX_ADD_IO_SEG(0x0001180000000438ull)
141#define CVMX_MIO_UART2_SFE \
142 CVMX_ADD_IO_SEG(0x0001180000000630ull)
143#define CVMX_MIO_UART2_SRR \
144 CVMX_ADD_IO_SEG(0x0001180000000610ull)
145#define CVMX_MIO_UART2_SRT \
146 CVMX_ADD_IO_SEG(0x0001180000000638ull)
147#define CVMX_MIO_UART2_SRTS \
148 CVMX_ADD_IO_SEG(0x0001180000000618ull)
149#define CVMX_MIO_UART2_STT \
150 CVMX_ADD_IO_SEG(0x0001180000000700ull)
151#define CVMX_MIO_UART2_TFL \
152 CVMX_ADD_IO_SEG(0x0001180000000600ull)
153#define CVMX_MIO_UART2_TFR \
154 CVMX_ADD_IO_SEG(0x0001180000000528ull)
155#define CVMX_MIO_UART2_THR \
156 CVMX_ADD_IO_SEG(0x0001180000000440ull)
157#define CVMX_MIO_UART2_USR \
158 CVMX_ADD_IO_SEG(0x0001180000000538ull)
159#define CVMX_MIO_UARTX_DLH(offset) \
160 CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
161#define CVMX_MIO_UARTX_DLL(offset) \
162 CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
163#define CVMX_MIO_UARTX_FAR(offset) \
164 CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
165#define CVMX_MIO_UARTX_FCR(offset) \
166 CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
167#define CVMX_MIO_UARTX_HTX(offset) \
168 CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
169#define CVMX_MIO_UARTX_IER(offset) \
170 CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
171#define CVMX_MIO_UARTX_IIR(offset) \
172 CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
173#define CVMX_MIO_UARTX_LCR(offset) \
174 CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
175#define CVMX_MIO_UARTX_LSR(offset) \
176 CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
177#define CVMX_MIO_UARTX_MCR(offset) \
178 CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
179#define CVMX_MIO_UARTX_MSR(offset) \
180 CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
181#define CVMX_MIO_UARTX_RBR(offset) \
182 CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
183#define CVMX_MIO_UARTX_RFL(offset) \
184 CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
185#define CVMX_MIO_UARTX_RFW(offset) \
186 CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
187#define CVMX_MIO_UARTX_SBCR(offset) \
188 CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
189#define CVMX_MIO_UARTX_SCR(offset) \
190 CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
191#define CVMX_MIO_UARTX_SFE(offset) \
192 CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
193#define CVMX_MIO_UARTX_SRR(offset) \
194 CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
195#define CVMX_MIO_UARTX_SRT(offset) \
196 CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
197#define CVMX_MIO_UARTX_SRTS(offset) \
198 CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
199#define CVMX_MIO_UARTX_STT(offset) \
200 CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
201#define CVMX_MIO_UARTX_TFL(offset) \
202 CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
203#define CVMX_MIO_UARTX_TFR(offset) \
204 CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
205#define CVMX_MIO_UARTX_THR(offset) \
206 CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
207#define CVMX_MIO_UARTX_USR(offset) \
208 CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
209
210union cvmx_mio_boot_bist_stat {
211 uint64_t u64;
212 struct cvmx_mio_boot_bist_stat_s {
213 uint64_t reserved_2_63:62;
214 uint64_t loc:1;
215 uint64_t ncbi:1;
216 } s;
217 struct cvmx_mio_boot_bist_stat_cn30xx {
218 uint64_t reserved_4_63:60;
219 uint64_t ncbo_1:1;
220 uint64_t ncbo_0:1;
221 uint64_t loc:1;
222 uint64_t ncbi:1;
223 } cn30xx;
224 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
225 struct cvmx_mio_boot_bist_stat_cn38xx {
226 uint64_t reserved_3_63:61;
227 uint64_t ncbo_0:1;
228 uint64_t loc:1;
229 uint64_t ncbi:1;
230 } cn38xx;
231 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
232 struct cvmx_mio_boot_bist_stat_cn50xx {
233 uint64_t reserved_6_63:58;
234 uint64_t pcm_1:1;
235 uint64_t pcm_0:1;
236 uint64_t ncbo_1:1;
237 uint64_t ncbo_0:1;
238 uint64_t loc:1;
239 uint64_t ncbi:1;
240 } cn50xx;
241 struct cvmx_mio_boot_bist_stat_cn52xx {
242 uint64_t reserved_6_63:58;
243 uint64_t ndf:2;
244 uint64_t ncbo_0:1;
245 uint64_t dma:1;
246 uint64_t loc:1;
247 uint64_t ncbi:1;
248 } cn52xx;
249 struct cvmx_mio_boot_bist_stat_cn52xxp1 {
250 uint64_t reserved_4_63:60;
251 uint64_t ncbo_0:1;
252 uint64_t dma:1;
253 uint64_t loc:1;
254 uint64_t ncbi:1;
255 } cn52xxp1;
256 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
257 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
258 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
259 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
260};
261
262union cvmx_mio_boot_comp {
263 uint64_t u64;
264 struct cvmx_mio_boot_comp_s {
265 uint64_t reserved_10_63:54;
266 uint64_t pctl:5;
267 uint64_t nctl:5;
268 } s;
269 struct cvmx_mio_boot_comp_s cn50xx;
270 struct cvmx_mio_boot_comp_s cn52xx;
271 struct cvmx_mio_boot_comp_s cn52xxp1;
272 struct cvmx_mio_boot_comp_s cn56xx;
273 struct cvmx_mio_boot_comp_s cn56xxp1;
274};
275
276union cvmx_mio_boot_dma_cfgx {
277 uint64_t u64;
278 struct cvmx_mio_boot_dma_cfgx_s {
279 uint64_t en:1;
280 uint64_t rw:1;
281 uint64_t clr:1;
282 uint64_t reserved_60_60:1;
283 uint64_t swap32:1;
284 uint64_t swap16:1;
285 uint64_t swap8:1;
286 uint64_t endian:1;
287 uint64_t size:20;
288 uint64_t adr:36;
289 } s;
290 struct cvmx_mio_boot_dma_cfgx_s cn52xx;
291 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
292 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
293 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
294};
295
296union cvmx_mio_boot_dma_intx {
297 uint64_t u64;
298 struct cvmx_mio_boot_dma_intx_s {
299 uint64_t reserved_2_63:62;
300 uint64_t dmarq:1;
301 uint64_t done:1;
302 } s;
303 struct cvmx_mio_boot_dma_intx_s cn52xx;
304 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
305 struct cvmx_mio_boot_dma_intx_s cn56xx;
306 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
307};
308
309union cvmx_mio_boot_dma_int_enx {
310 uint64_t u64;
311 struct cvmx_mio_boot_dma_int_enx_s {
312 uint64_t reserved_2_63:62;
313 uint64_t dmarq:1;
314 uint64_t done:1;
315 } s;
316 struct cvmx_mio_boot_dma_int_enx_s cn52xx;
317 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
318 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
319 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
320};
321
322union cvmx_mio_boot_dma_timx {
323 uint64_t u64;
324 struct cvmx_mio_boot_dma_timx_s {
325 uint64_t dmack_pi:1;
326 uint64_t dmarq_pi:1;
327 uint64_t tim_mult:2;
328 uint64_t rd_dly:3;
329 uint64_t ddr:1;
330 uint64_t width:1;
331 uint64_t reserved_48_54:7;
332 uint64_t pause:6;
333 uint64_t dmack_h:6;
334 uint64_t we_n:6;
335 uint64_t we_a:6;
336 uint64_t oe_n:6;
337 uint64_t oe_a:6;
338 uint64_t dmack_s:6;
339 uint64_t dmarq:6;
340 } s;
341 struct cvmx_mio_boot_dma_timx_s cn52xx;
342 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
343 struct cvmx_mio_boot_dma_timx_s cn56xx;
344 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
345};
346
347union cvmx_mio_boot_err {
348 uint64_t u64;
349 struct cvmx_mio_boot_err_s {
350 uint64_t reserved_2_63:62;
351 uint64_t wait_err:1;
352 uint64_t adr_err:1;
353 } s;
354 struct cvmx_mio_boot_err_s cn30xx;
355 struct cvmx_mio_boot_err_s cn31xx;
356 struct cvmx_mio_boot_err_s cn38xx;
357 struct cvmx_mio_boot_err_s cn38xxp2;
358 struct cvmx_mio_boot_err_s cn50xx;
359 struct cvmx_mio_boot_err_s cn52xx;
360 struct cvmx_mio_boot_err_s cn52xxp1;
361 struct cvmx_mio_boot_err_s cn56xx;
362 struct cvmx_mio_boot_err_s cn56xxp1;
363 struct cvmx_mio_boot_err_s cn58xx;
364 struct cvmx_mio_boot_err_s cn58xxp1;
365};
366
367union cvmx_mio_boot_int {
368 uint64_t u64;
369 struct cvmx_mio_boot_int_s {
370 uint64_t reserved_2_63:62;
371 uint64_t wait_int:1;
372 uint64_t adr_int:1;
373 } s;
374 struct cvmx_mio_boot_int_s cn30xx;
375 struct cvmx_mio_boot_int_s cn31xx;
376 struct cvmx_mio_boot_int_s cn38xx;
377 struct cvmx_mio_boot_int_s cn38xxp2;
378 struct cvmx_mio_boot_int_s cn50xx;
379 struct cvmx_mio_boot_int_s cn52xx;
380 struct cvmx_mio_boot_int_s cn52xxp1;
381 struct cvmx_mio_boot_int_s cn56xx;
382 struct cvmx_mio_boot_int_s cn56xxp1;
383 struct cvmx_mio_boot_int_s cn58xx;
384 struct cvmx_mio_boot_int_s cn58xxp1;
385};
386
387union cvmx_mio_boot_loc_adr {
388 uint64_t u64;
389 struct cvmx_mio_boot_loc_adr_s {
390 uint64_t reserved_8_63:56;
391 uint64_t adr:5;
392 uint64_t reserved_0_2:3;
393 } s;
394 struct cvmx_mio_boot_loc_adr_s cn30xx;
395 struct cvmx_mio_boot_loc_adr_s cn31xx;
396 struct cvmx_mio_boot_loc_adr_s cn38xx;
397 struct cvmx_mio_boot_loc_adr_s cn38xxp2;
398 struct cvmx_mio_boot_loc_adr_s cn50xx;
399 struct cvmx_mio_boot_loc_adr_s cn52xx;
400 struct cvmx_mio_boot_loc_adr_s cn52xxp1;
401 struct cvmx_mio_boot_loc_adr_s cn56xx;
402 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
403 struct cvmx_mio_boot_loc_adr_s cn58xx;
404 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
405};
406
407union cvmx_mio_boot_loc_cfgx {
408 uint64_t u64;
409 struct cvmx_mio_boot_loc_cfgx_s {
410 uint64_t reserved_32_63:32;
411 uint64_t en:1;
412 uint64_t reserved_28_30:3;
413 uint64_t base:25;
414 uint64_t reserved_0_2:3;
415 } s;
416 struct cvmx_mio_boot_loc_cfgx_s cn30xx;
417 struct cvmx_mio_boot_loc_cfgx_s cn31xx;
418 struct cvmx_mio_boot_loc_cfgx_s cn38xx;
419 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2;
420 struct cvmx_mio_boot_loc_cfgx_s cn50xx;
421 struct cvmx_mio_boot_loc_cfgx_s cn52xx;
422 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1;
423 struct cvmx_mio_boot_loc_cfgx_s cn56xx;
424 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
425 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
426 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
427};
428
429union cvmx_mio_boot_loc_dat {
430 uint64_t u64;
431 struct cvmx_mio_boot_loc_dat_s {
432 uint64_t data:64;
433 } s;
434 struct cvmx_mio_boot_loc_dat_s cn30xx;
435 struct cvmx_mio_boot_loc_dat_s cn31xx;
436 struct cvmx_mio_boot_loc_dat_s cn38xx;
437 struct cvmx_mio_boot_loc_dat_s cn38xxp2;
438 struct cvmx_mio_boot_loc_dat_s cn50xx;
439 struct cvmx_mio_boot_loc_dat_s cn52xx;
440 struct cvmx_mio_boot_loc_dat_s cn52xxp1;
441 struct cvmx_mio_boot_loc_dat_s cn56xx;
442 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
443 struct cvmx_mio_boot_loc_dat_s cn58xx;
444 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
445};
446
447union cvmx_mio_boot_pin_defs {
448 uint64_t u64;
449 struct cvmx_mio_boot_pin_defs_s {
450 uint64_t reserved_16_63:48;
451 uint64_t ale:1;
452 uint64_t width:1;
453 uint64_t dmack_p2:1;
454 uint64_t dmack_p1:1;
455 uint64_t dmack_p0:1;
456 uint64_t term:2;
457 uint64_t nand:1;
458 uint64_t reserved_0_7:8;
459 } s;
460 struct cvmx_mio_boot_pin_defs_cn52xx {
461 uint64_t reserved_16_63:48;
462 uint64_t ale:1;
463 uint64_t width:1;
464 uint64_t reserved_13_13:1;
465 uint64_t dmack_p1:1;
466 uint64_t dmack_p0:1;
467 uint64_t term:2;
468 uint64_t nand:1;
469 uint64_t reserved_0_7:8;
470 } cn52xx;
471 struct cvmx_mio_boot_pin_defs_cn56xx {
472 uint64_t reserved_16_63:48;
473 uint64_t ale:1;
474 uint64_t width:1;
475 uint64_t dmack_p2:1;
476 uint64_t dmack_p1:1;
477 uint64_t dmack_p0:1;
478 uint64_t term:2;
479 uint64_t reserved_0_8:9;
480 } cn56xx;
481};
482
483union cvmx_mio_boot_reg_cfgx {
484 uint64_t u64;
485 struct cvmx_mio_boot_reg_cfgx_s {
486 uint64_t reserved_44_63:20;
487 uint64_t dmack:2;
488 uint64_t tim_mult:2;
489 uint64_t rd_dly:3;
490 uint64_t sam:1;
491 uint64_t we_ext:2;
492 uint64_t oe_ext:2;
493 uint64_t en:1;
494 uint64_t orbit:1;
495 uint64_t ale:1;
496 uint64_t width:1;
497 uint64_t size:12;
498 uint64_t base:16;
499 } s;
500 struct cvmx_mio_boot_reg_cfgx_cn30xx {
501 uint64_t reserved_37_63:27;
502 uint64_t sam:1;
503 uint64_t we_ext:2;
504 uint64_t oe_ext:2;
505 uint64_t en:1;
506 uint64_t orbit:1;
507 uint64_t ale:1;
508 uint64_t width:1;
509 uint64_t size:12;
510 uint64_t base:16;
511 } cn30xx;
512 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
513 struct cvmx_mio_boot_reg_cfgx_cn38xx {
514 uint64_t reserved_32_63:32;
515 uint64_t en:1;
516 uint64_t orbit:1;
517 uint64_t reserved_28_29:2;
518 uint64_t size:12;
519 uint64_t base:16;
520 } cn38xx;
521 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
522 struct cvmx_mio_boot_reg_cfgx_cn50xx {
523 uint64_t reserved_42_63:22;
524 uint64_t tim_mult:2;
525 uint64_t rd_dly:3;
526 uint64_t sam:1;
527 uint64_t we_ext:2;
528 uint64_t oe_ext:2;
529 uint64_t en:1;
530 uint64_t orbit:1;
531 uint64_t ale:1;
532 uint64_t width:1;
533 uint64_t size:12;
534 uint64_t base:16;
535 } cn50xx;
536 struct cvmx_mio_boot_reg_cfgx_s cn52xx;
537 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
538 struct cvmx_mio_boot_reg_cfgx_s cn56xx;
539 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
540 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
541 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
542};
543
544union cvmx_mio_boot_reg_timx {
545 uint64_t u64;
546 struct cvmx_mio_boot_reg_timx_s {
547 uint64_t pagem:1;
548 uint64_t waitm:1;
549 uint64_t pages:2;
550 uint64_t ale:6;
551 uint64_t page:6;
552 uint64_t wait:6;
553 uint64_t pause:6;
554 uint64_t wr_hld:6;
555 uint64_t rd_hld:6;
556 uint64_t we:6;
557 uint64_t oe:6;
558 uint64_t ce:6;
559 uint64_t adr:6;
560 } s;
561 struct cvmx_mio_boot_reg_timx_s cn30xx;
562 struct cvmx_mio_boot_reg_timx_s cn31xx;
563 struct cvmx_mio_boot_reg_timx_cn38xx {
564 uint64_t pagem:1;
565 uint64_t waitm:1;
566 uint64_t pages:2;
567 uint64_t reserved_54_59:6;
568 uint64_t page:6;
569 uint64_t wait:6;
570 uint64_t pause:6;
571 uint64_t wr_hld:6;
572 uint64_t rd_hld:6;
573 uint64_t we:6;
574 uint64_t oe:6;
575 uint64_t ce:6;
576 uint64_t adr:6;
577 } cn38xx;
578 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
579 struct cvmx_mio_boot_reg_timx_s cn50xx;
580 struct cvmx_mio_boot_reg_timx_s cn52xx;
581 struct cvmx_mio_boot_reg_timx_s cn52xxp1;
582 struct cvmx_mio_boot_reg_timx_s cn56xx;
583 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
584 struct cvmx_mio_boot_reg_timx_s cn58xx;
585 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
586};
587
588union cvmx_mio_boot_thr {
589 uint64_t u64;
590 struct cvmx_mio_boot_thr_s {
591 uint64_t reserved_22_63:42;
592 uint64_t dma_thr:6;
593 uint64_t reserved_14_15:2;
594 uint64_t fif_cnt:6;
595 uint64_t reserved_6_7:2;
596 uint64_t fif_thr:6;
597 } s;
598 struct cvmx_mio_boot_thr_cn30xx {
599 uint64_t reserved_14_63:50;
600 uint64_t fif_cnt:6;
601 uint64_t reserved_6_7:2;
602 uint64_t fif_thr:6;
603 } cn30xx;
604 struct cvmx_mio_boot_thr_cn30xx cn31xx;
605 struct cvmx_mio_boot_thr_cn30xx cn38xx;
606 struct cvmx_mio_boot_thr_cn30xx cn38xxp2;
607 struct cvmx_mio_boot_thr_cn30xx cn50xx;
608 struct cvmx_mio_boot_thr_s cn52xx;
609 struct cvmx_mio_boot_thr_s cn52xxp1;
610 struct cvmx_mio_boot_thr_s cn56xx;
611 struct cvmx_mio_boot_thr_s cn56xxp1;
612 struct cvmx_mio_boot_thr_cn30xx cn58xx;
613 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
614};
615
616union cvmx_mio_fus_bnk_datx {
617 uint64_t u64;
618 struct cvmx_mio_fus_bnk_datx_s {
619 uint64_t dat:64;
620 } s;
621 struct cvmx_mio_fus_bnk_datx_s cn50xx;
622 struct cvmx_mio_fus_bnk_datx_s cn52xx;
623 struct cvmx_mio_fus_bnk_datx_s cn52xxp1;
624 struct cvmx_mio_fus_bnk_datx_s cn56xx;
625 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
626 struct cvmx_mio_fus_bnk_datx_s cn58xx;
627 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
628};
629
630union cvmx_mio_fus_dat0 {
631 uint64_t u64;
632 struct cvmx_mio_fus_dat0_s {
633 uint64_t reserved_32_63:32;
634 uint64_t man_info:32;
635 } s;
636 struct cvmx_mio_fus_dat0_s cn30xx;
637 struct cvmx_mio_fus_dat0_s cn31xx;
638 struct cvmx_mio_fus_dat0_s cn38xx;
639 struct cvmx_mio_fus_dat0_s cn38xxp2;
640 struct cvmx_mio_fus_dat0_s cn50xx;
641 struct cvmx_mio_fus_dat0_s cn52xx;
642 struct cvmx_mio_fus_dat0_s cn52xxp1;
643 struct cvmx_mio_fus_dat0_s cn56xx;
644 struct cvmx_mio_fus_dat0_s cn56xxp1;
645 struct cvmx_mio_fus_dat0_s cn58xx;
646 struct cvmx_mio_fus_dat0_s cn58xxp1;
647};
648
649union cvmx_mio_fus_dat1 {
650 uint64_t u64;
651 struct cvmx_mio_fus_dat1_s {
652 uint64_t reserved_32_63:32;
653 uint64_t man_info:32;
654 } s;
655 struct cvmx_mio_fus_dat1_s cn30xx;
656 struct cvmx_mio_fus_dat1_s cn31xx;
657 struct cvmx_mio_fus_dat1_s cn38xx;
658 struct cvmx_mio_fus_dat1_s cn38xxp2;
659 struct cvmx_mio_fus_dat1_s cn50xx;
660 struct cvmx_mio_fus_dat1_s cn52xx;
661 struct cvmx_mio_fus_dat1_s cn52xxp1;
662 struct cvmx_mio_fus_dat1_s cn56xx;
663 struct cvmx_mio_fus_dat1_s cn56xxp1;
664 struct cvmx_mio_fus_dat1_s cn58xx;
665 struct cvmx_mio_fus_dat1_s cn58xxp1;
666};
667
668union cvmx_mio_fus_dat2 {
669 uint64_t u64;
670 struct cvmx_mio_fus_dat2_s {
671 uint64_t reserved_34_63:30;
672 uint64_t fus318:1;
673 uint64_t raid_en:1;
674 uint64_t reserved_30_31:2;
675 uint64_t nokasu:1;
676 uint64_t nodfa_cp2:1;
677 uint64_t nomul:1;
678 uint64_t nocrypto:1;
679 uint64_t rst_sht:1;
680 uint64_t bist_dis:1;
681 uint64_t chip_id:8;
682 uint64_t reserved_0_15:16;
683 } s;
684 struct cvmx_mio_fus_dat2_cn30xx {
685 uint64_t reserved_29_63:35;
686 uint64_t nodfa_cp2:1;
687 uint64_t nomul:1;
688 uint64_t nocrypto:1;
689 uint64_t rst_sht:1;
690 uint64_t bist_dis:1;
691 uint64_t chip_id:8;
692 uint64_t pll_off:4;
693 uint64_t reserved_1_11:11;
694 uint64_t pp_dis:1;
695 } cn30xx;
696 struct cvmx_mio_fus_dat2_cn31xx {
697 uint64_t reserved_29_63:35;
698 uint64_t nodfa_cp2:1;
699 uint64_t nomul:1;
700 uint64_t nocrypto:1;
701 uint64_t rst_sht:1;
702 uint64_t bist_dis:1;
703 uint64_t chip_id:8;
704 uint64_t pll_off:4;
705 uint64_t reserved_2_11:10;
706 uint64_t pp_dis:2;
707 } cn31xx;
708 struct cvmx_mio_fus_dat2_cn38xx {
709 uint64_t reserved_29_63:35;
710 uint64_t nodfa_cp2:1;
711 uint64_t nomul:1;
712 uint64_t nocrypto:1;
713 uint64_t rst_sht:1;
714 uint64_t bist_dis:1;
715 uint64_t chip_id:8;
716 uint64_t pp_dis:16;
717 } cn38xx;
718 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
719 struct cvmx_mio_fus_dat2_cn50xx {
720 uint64_t reserved_34_63:30;
721 uint64_t fus318:1;
722 uint64_t raid_en:1;
723 uint64_t reserved_30_31:2;
724 uint64_t nokasu:1;
725 uint64_t nodfa_cp2:1;
726 uint64_t nomul:1;
727 uint64_t nocrypto:1;
728 uint64_t rst_sht:1;
729 uint64_t bist_dis:1;
730 uint64_t chip_id:8;
731 uint64_t reserved_2_15:14;
732 uint64_t pp_dis:2;
733 } cn50xx;
734 struct cvmx_mio_fus_dat2_cn52xx {
735 uint64_t reserved_34_63:30;
736 uint64_t fus318:1;
737 uint64_t raid_en:1;
738 uint64_t reserved_30_31:2;
739 uint64_t nokasu:1;
740 uint64_t nodfa_cp2:1;
741 uint64_t nomul:1;
742 uint64_t nocrypto:1;
743 uint64_t rst_sht:1;
744 uint64_t bist_dis:1;
745 uint64_t chip_id:8;
746 uint64_t reserved_4_15:12;
747 uint64_t pp_dis:4;
748 } cn52xx;
749 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
750 struct cvmx_mio_fus_dat2_cn56xx {
751 uint64_t reserved_34_63:30;
752 uint64_t fus318:1;
753 uint64_t raid_en:1;
754 uint64_t reserved_30_31:2;
755 uint64_t nokasu:1;
756 uint64_t nodfa_cp2:1;
757 uint64_t nomul:1;
758 uint64_t nocrypto:1;
759 uint64_t rst_sht:1;
760 uint64_t bist_dis:1;
761 uint64_t chip_id:8;
762 uint64_t reserved_12_15:4;
763 uint64_t pp_dis:12;
764 } cn56xx;
765 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
766 struct cvmx_mio_fus_dat2_cn58xx {
767 uint64_t reserved_30_63:34;
768 uint64_t nokasu:1;
769 uint64_t nodfa_cp2:1;
770 uint64_t nomul:1;
771 uint64_t nocrypto:1;
772 uint64_t rst_sht:1;
773 uint64_t bist_dis:1;
774 uint64_t chip_id:8;
775 uint64_t pp_dis:16;
776 } cn58xx;
777 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
778};
779
780union cvmx_mio_fus_dat3 {
781 uint64_t u64;
782 struct cvmx_mio_fus_dat3_s {
783 uint64_t reserved_32_63:32;
784 uint64_t pll_div4:1;
785 uint64_t zip_crip:2;
786 uint64_t bar2_en:1;
787 uint64_t efus_lck:1;
788 uint64_t efus_ign:1;
789 uint64_t nozip:1;
790 uint64_t nodfa_dte:1;
791 uint64_t icache:24;
792 } s;
793 struct cvmx_mio_fus_dat3_cn30xx {
794 uint64_t reserved_32_63:32;
795 uint64_t pll_div4:1;
796 uint64_t reserved_29_30:2;
797 uint64_t bar2_en:1;
798 uint64_t efus_lck:1;
799 uint64_t efus_ign:1;
800 uint64_t nozip:1;
801 uint64_t nodfa_dte:1;
802 uint64_t icache:24;
803 } cn30xx;
804 struct cvmx_mio_fus_dat3_s cn31xx;
805 struct cvmx_mio_fus_dat3_cn38xx {
806 uint64_t reserved_31_63:33;
807 uint64_t zip_crip:2;
808 uint64_t bar2_en:1;
809 uint64_t efus_lck:1;
810 uint64_t efus_ign:1;
811 uint64_t nozip:1;
812 uint64_t nodfa_dte:1;
813 uint64_t icache:24;
814 } cn38xx;
815 struct cvmx_mio_fus_dat3_cn38xxp2 {
816 uint64_t reserved_29_63:35;
817 uint64_t bar2_en:1;
818 uint64_t efus_lck:1;
819 uint64_t efus_ign:1;
820 uint64_t nozip:1;
821 uint64_t nodfa_dte:1;
822 uint64_t icache:24;
823 } cn38xxp2;
824 struct cvmx_mio_fus_dat3_cn38xx cn50xx;
825 struct cvmx_mio_fus_dat3_cn38xx cn52xx;
826 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1;
827 struct cvmx_mio_fus_dat3_cn38xx cn56xx;
828 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
829 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
830 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
831};
832
833union cvmx_mio_fus_ema {
834 uint64_t u64;
835 struct cvmx_mio_fus_ema_s {
836 uint64_t reserved_7_63:57;
837 uint64_t eff_ema:3;
838 uint64_t reserved_3_3:1;
839 uint64_t ema:3;
840 } s;
841 struct cvmx_mio_fus_ema_s cn50xx;
842 struct cvmx_mio_fus_ema_s cn52xx;
843 struct cvmx_mio_fus_ema_s cn52xxp1;
844 struct cvmx_mio_fus_ema_s cn56xx;
845 struct cvmx_mio_fus_ema_s cn56xxp1;
846 struct cvmx_mio_fus_ema_cn58xx {
847 uint64_t reserved_2_63:62;
848 uint64_t ema:2;
849 } cn58xx;
850 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
851};
852
853union cvmx_mio_fus_pdf {
854 uint64_t u64;
855 struct cvmx_mio_fus_pdf_s {
856 uint64_t pdf:64;
857 } s;
858 struct cvmx_mio_fus_pdf_s cn50xx;
859 struct cvmx_mio_fus_pdf_s cn52xx;
860 struct cvmx_mio_fus_pdf_s cn52xxp1;
861 struct cvmx_mio_fus_pdf_s cn56xx;
862 struct cvmx_mio_fus_pdf_s cn56xxp1;
863 struct cvmx_mio_fus_pdf_s cn58xx;
864};
865
866union cvmx_mio_fus_pll {
867 uint64_t u64;
868 struct cvmx_mio_fus_pll_s {
869 uint64_t reserved_2_63:62;
870 uint64_t rfslip:1;
871 uint64_t fbslip:1;
872 } s;
873 struct cvmx_mio_fus_pll_s cn50xx;
874 struct cvmx_mio_fus_pll_s cn52xx;
875 struct cvmx_mio_fus_pll_s cn52xxp1;
876 struct cvmx_mio_fus_pll_s cn56xx;
877 struct cvmx_mio_fus_pll_s cn56xxp1;
878 struct cvmx_mio_fus_pll_s cn58xx;
879 struct cvmx_mio_fus_pll_s cn58xxp1;
880};
881
882union cvmx_mio_fus_prog {
883 uint64_t u64;
884 struct cvmx_mio_fus_prog_s {
885 uint64_t reserved_1_63:63;
886 uint64_t prog:1;
887 } s;
888 struct cvmx_mio_fus_prog_s cn30xx;
889 struct cvmx_mio_fus_prog_s cn31xx;
890 struct cvmx_mio_fus_prog_s cn38xx;
891 struct cvmx_mio_fus_prog_s cn38xxp2;
892 struct cvmx_mio_fus_prog_s cn50xx;
893 struct cvmx_mio_fus_prog_s cn52xx;
894 struct cvmx_mio_fus_prog_s cn52xxp1;
895 struct cvmx_mio_fus_prog_s cn56xx;
896 struct cvmx_mio_fus_prog_s cn56xxp1;
897 struct cvmx_mio_fus_prog_s cn58xx;
898 struct cvmx_mio_fus_prog_s cn58xxp1;
899};
900
901union cvmx_mio_fus_prog_times {
902 uint64_t u64;
903 struct cvmx_mio_fus_prog_times_s {
904 uint64_t reserved_33_63:31;
905 uint64_t prog_pin:1;
906 uint64_t out:8;
907 uint64_t sclk_lo:4;
908 uint64_t sclk_hi:12;
909 uint64_t setup:8;
910 } s;
911 struct cvmx_mio_fus_prog_times_s cn50xx;
912 struct cvmx_mio_fus_prog_times_s cn52xx;
913 struct cvmx_mio_fus_prog_times_s cn52xxp1;
914 struct cvmx_mio_fus_prog_times_s cn56xx;
915 struct cvmx_mio_fus_prog_times_s cn56xxp1;
916 struct cvmx_mio_fus_prog_times_s cn58xx;
917 struct cvmx_mio_fus_prog_times_s cn58xxp1;
918};
919
920union cvmx_mio_fus_rcmd {
921 uint64_t u64;
922 struct cvmx_mio_fus_rcmd_s {
923 uint64_t reserved_24_63:40;
924 uint64_t dat:8;
925 uint64_t reserved_13_15:3;
926 uint64_t pend:1;
927 uint64_t reserved_9_11:3;
928 uint64_t efuse:1;
929 uint64_t addr:8;
930 } s;
931 struct cvmx_mio_fus_rcmd_cn30xx {
932 uint64_t reserved_24_63:40;
933 uint64_t dat:8;
934 uint64_t reserved_13_15:3;
935 uint64_t pend:1;
936 uint64_t reserved_9_11:3;
937 uint64_t efuse:1;
938 uint64_t reserved_7_7:1;
939 uint64_t addr:7;
940 } cn30xx;
941 struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
942 struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
943 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2;
944 struct cvmx_mio_fus_rcmd_cn30xx cn50xx;
945 struct cvmx_mio_fus_rcmd_s cn52xx;
946 struct cvmx_mio_fus_rcmd_s cn52xxp1;
947 struct cvmx_mio_fus_rcmd_s cn56xx;
948 struct cvmx_mio_fus_rcmd_s cn56xxp1;
949 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
950 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
951};
952
953union cvmx_mio_fus_spr_repair_res {
954 uint64_t u64;
955 struct cvmx_mio_fus_spr_repair_res_s {
956 uint64_t reserved_42_63:22;
957 uint64_t repair2:14;
958 uint64_t repair1:14;
959 uint64_t repair0:14;
960 } s;
961 struct cvmx_mio_fus_spr_repair_res_s cn30xx;
962 struct cvmx_mio_fus_spr_repair_res_s cn31xx;
963 struct cvmx_mio_fus_spr_repair_res_s cn38xx;
964 struct cvmx_mio_fus_spr_repair_res_s cn50xx;
965 struct cvmx_mio_fus_spr_repair_res_s cn52xx;
966 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
967 struct cvmx_mio_fus_spr_repair_res_s cn56xx;
968 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
969 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
970 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
971};
972
973union cvmx_mio_fus_spr_repair_sum {
974 uint64_t u64;
975 struct cvmx_mio_fus_spr_repair_sum_s {
976 uint64_t reserved_1_63:63;
977 uint64_t too_many:1;
978 } s;
979 struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
980 struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
981 struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
982 struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
983 struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
984 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
985 struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
986 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
987 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
988 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
989};
990
991union cvmx_mio_fus_unlock {
992 uint64_t u64;
993 struct cvmx_mio_fus_unlock_s {
994 uint64_t reserved_24_63:40;
995 uint64_t key:24;
996 } s;
997 struct cvmx_mio_fus_unlock_s cn30xx;
998 struct cvmx_mio_fus_unlock_s cn31xx;
999};
1000
1001union cvmx_mio_fus_wadr {
1002 uint64_t u64;
1003 struct cvmx_mio_fus_wadr_s {
1004 uint64_t reserved_10_63:54;
1005 uint64_t addr:10;
1006 } s;
1007 struct cvmx_mio_fus_wadr_s cn30xx;
1008 struct cvmx_mio_fus_wadr_s cn31xx;
1009 struct cvmx_mio_fus_wadr_s cn38xx;
1010 struct cvmx_mio_fus_wadr_s cn38xxp2;
1011 struct cvmx_mio_fus_wadr_cn50xx {
1012 uint64_t reserved_2_63:62;
1013 uint64_t addr:2;
1014 } cn50xx;
1015 struct cvmx_mio_fus_wadr_cn52xx {
1016 uint64_t reserved_3_63:61;
1017 uint64_t addr:3;
1018 } cn52xx;
1019 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
1020 struct cvmx_mio_fus_wadr_cn52xx cn56xx;
1021 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
1022 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
1023 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
1024};
1025
1026union cvmx_mio_ndf_dma_cfg {
1027 uint64_t u64;
1028 struct cvmx_mio_ndf_dma_cfg_s {
1029 uint64_t en:1;
1030 uint64_t rw:1;
1031 uint64_t clr:1;
1032 uint64_t reserved_60_60:1;
1033 uint64_t swap32:1;
1034 uint64_t swap16:1;
1035 uint64_t swap8:1;
1036 uint64_t endian:1;
1037 uint64_t size:20;
1038 uint64_t adr:36;
1039 } s;
1040 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
1041};
1042
1043union cvmx_mio_ndf_dma_int {
1044 uint64_t u64;
1045 struct cvmx_mio_ndf_dma_int_s {
1046 uint64_t reserved_1_63:63;
1047 uint64_t done:1;
1048 } s;
1049 struct cvmx_mio_ndf_dma_int_s cn52xx;
1050};
1051
1052union cvmx_mio_ndf_dma_int_en {
1053 uint64_t u64;
1054 struct cvmx_mio_ndf_dma_int_en_s {
1055 uint64_t reserved_1_63:63;
1056 uint64_t done:1;
1057 } s;
1058 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
1059};
1060
1061union cvmx_mio_pll_ctl {
1062 uint64_t u64;
1063 struct cvmx_mio_pll_ctl_s {
1064 uint64_t reserved_5_63:59;
1065 uint64_t bw_ctl:5;
1066 } s;
1067 struct cvmx_mio_pll_ctl_s cn30xx;
1068 struct cvmx_mio_pll_ctl_s cn31xx;
1069};
1070
1071union cvmx_mio_pll_setting {
1072 uint64_t u64;
1073 struct cvmx_mio_pll_setting_s {
1074 uint64_t reserved_17_63:47;
1075 uint64_t setting:17;
1076 } s;
1077 struct cvmx_mio_pll_setting_s cn30xx;
1078 struct cvmx_mio_pll_setting_s cn31xx;
1079};
1080
1081union cvmx_mio_twsx_int {
1082 uint64_t u64;
1083 struct cvmx_mio_twsx_int_s {
1084 uint64_t reserved_12_63:52;
1085 uint64_t scl:1;
1086 uint64_t sda:1;
1087 uint64_t scl_ovr:1;
1088 uint64_t sda_ovr:1;
1089 uint64_t reserved_7_7:1;
1090 uint64_t core_en:1;
1091 uint64_t ts_en:1;
1092 uint64_t st_en:1;
1093 uint64_t reserved_3_3:1;
1094 uint64_t core_int:1;
1095 uint64_t ts_int:1;
1096 uint64_t st_int:1;
1097 } s;
1098 struct cvmx_mio_twsx_int_s cn30xx;
1099 struct cvmx_mio_twsx_int_s cn31xx;
1100 struct cvmx_mio_twsx_int_s cn38xx;
1101 struct cvmx_mio_twsx_int_cn38xxp2 {
1102 uint64_t reserved_7_63:57;
1103 uint64_t core_en:1;
1104 uint64_t ts_en:1;
1105 uint64_t st_en:1;
1106 uint64_t reserved_3_3:1;
1107 uint64_t core_int:1;
1108 uint64_t ts_int:1;
1109 uint64_t st_int:1;
1110 } cn38xxp2;
1111 struct cvmx_mio_twsx_int_s cn50xx;
1112 struct cvmx_mio_twsx_int_s cn52xx;
1113 struct cvmx_mio_twsx_int_s cn52xxp1;
1114 struct cvmx_mio_twsx_int_s cn56xx;
1115 struct cvmx_mio_twsx_int_s cn56xxp1;
1116 struct cvmx_mio_twsx_int_s cn58xx;
1117 struct cvmx_mio_twsx_int_s cn58xxp1;
1118};
1119
1120union cvmx_mio_twsx_sw_twsi {
1121 uint64_t u64;
1122 struct cvmx_mio_twsx_sw_twsi_s {
1123 uint64_t v:1;
1124 uint64_t slonly:1;
1125 uint64_t eia:1;
1126 uint64_t op:4;
1127 uint64_t r:1;
1128 uint64_t sovr:1;
1129 uint64_t size:3;
1130 uint64_t scr:2;
1131 uint64_t a:10;
1132 uint64_t ia:5;
1133 uint64_t eop_ia:3;
1134 uint64_t d:32;
1135 } s;
1136 struct cvmx_mio_twsx_sw_twsi_s cn30xx;
1137 struct cvmx_mio_twsx_sw_twsi_s cn31xx;
1138 struct cvmx_mio_twsx_sw_twsi_s cn38xx;
1139 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2;
1140 struct cvmx_mio_twsx_sw_twsi_s cn50xx;
1141 struct cvmx_mio_twsx_sw_twsi_s cn52xx;
1142 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1;
1143 struct cvmx_mio_twsx_sw_twsi_s cn56xx;
1144 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
1145 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
1146 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
1147};
1148
1149union cvmx_mio_twsx_sw_twsi_ext {
1150 uint64_t u64;
1151 struct cvmx_mio_twsx_sw_twsi_ext_s {
1152 uint64_t reserved_40_63:24;
1153 uint64_t ia:8;
1154 uint64_t d:32;
1155 } s;
1156 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
1157 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
1158 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx;
1159 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2;
1160 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx;
1161 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx;
1162 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1;
1163 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx;
1164 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
1165 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
1166 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
1167};
1168
1169union cvmx_mio_twsx_twsi_sw {
1170 uint64_t u64;
1171 struct cvmx_mio_twsx_twsi_sw_s {
1172 uint64_t v:2;
1173 uint64_t reserved_32_61:30;
1174 uint64_t d:32;
1175 } s;
1176 struct cvmx_mio_twsx_twsi_sw_s cn30xx;
1177 struct cvmx_mio_twsx_twsi_sw_s cn31xx;
1178 struct cvmx_mio_twsx_twsi_sw_s cn38xx;
1179 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2;
1180 struct cvmx_mio_twsx_twsi_sw_s cn50xx;
1181 struct cvmx_mio_twsx_twsi_sw_s cn52xx;
1182 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1;
1183 struct cvmx_mio_twsx_twsi_sw_s cn56xx;
1184 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
1185 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
1186 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
1187};
1188
1189union cvmx_mio_uartx_dlh {
1190 uint64_t u64;
1191 struct cvmx_mio_uartx_dlh_s {
1192 uint64_t reserved_8_63:56;
1193 uint64_t dlh:8;
1194 } s;
1195 struct cvmx_mio_uartx_dlh_s cn30xx;
1196 struct cvmx_mio_uartx_dlh_s cn31xx;
1197 struct cvmx_mio_uartx_dlh_s cn38xx;
1198 struct cvmx_mio_uartx_dlh_s cn38xxp2;
1199 struct cvmx_mio_uartx_dlh_s cn50xx;
1200 struct cvmx_mio_uartx_dlh_s cn52xx;
1201 struct cvmx_mio_uartx_dlh_s cn52xxp1;
1202 struct cvmx_mio_uartx_dlh_s cn56xx;
1203 struct cvmx_mio_uartx_dlh_s cn56xxp1;
1204 struct cvmx_mio_uartx_dlh_s cn58xx;
1205 struct cvmx_mio_uartx_dlh_s cn58xxp1;
1206};
1207
1208union cvmx_mio_uartx_dll {
1209 uint64_t u64;
1210 struct cvmx_mio_uartx_dll_s {
1211 uint64_t reserved_8_63:56;
1212 uint64_t dll:8;
1213 } s;
1214 struct cvmx_mio_uartx_dll_s cn30xx;
1215 struct cvmx_mio_uartx_dll_s cn31xx;
1216 struct cvmx_mio_uartx_dll_s cn38xx;
1217 struct cvmx_mio_uartx_dll_s cn38xxp2;
1218 struct cvmx_mio_uartx_dll_s cn50xx;
1219 struct cvmx_mio_uartx_dll_s cn52xx;
1220 struct cvmx_mio_uartx_dll_s cn52xxp1;
1221 struct cvmx_mio_uartx_dll_s cn56xx;
1222 struct cvmx_mio_uartx_dll_s cn56xxp1;
1223 struct cvmx_mio_uartx_dll_s cn58xx;
1224 struct cvmx_mio_uartx_dll_s cn58xxp1;
1225};
1226
1227union cvmx_mio_uartx_far {
1228 uint64_t u64;
1229 struct cvmx_mio_uartx_far_s {
1230 uint64_t reserved_1_63:63;
1231 uint64_t far:1;
1232 } s;
1233 struct cvmx_mio_uartx_far_s cn30xx;
1234 struct cvmx_mio_uartx_far_s cn31xx;
1235 struct cvmx_mio_uartx_far_s cn38xx;
1236 struct cvmx_mio_uartx_far_s cn38xxp2;
1237 struct cvmx_mio_uartx_far_s cn50xx;
1238 struct cvmx_mio_uartx_far_s cn52xx;
1239 struct cvmx_mio_uartx_far_s cn52xxp1;
1240 struct cvmx_mio_uartx_far_s cn56xx;
1241 struct cvmx_mio_uartx_far_s cn56xxp1;
1242 struct cvmx_mio_uartx_far_s cn58xx;
1243 struct cvmx_mio_uartx_far_s cn58xxp1;
1244};
1245
1246union cvmx_mio_uartx_fcr {
1247 uint64_t u64;
1248 struct cvmx_mio_uartx_fcr_s {
1249 uint64_t reserved_8_63:56;
1250 uint64_t rxtrig:2;
1251 uint64_t txtrig:2;
1252 uint64_t reserved_3_3:1;
1253 uint64_t txfr:1;
1254 uint64_t rxfr:1;
1255 uint64_t en:1;
1256 } s;
1257 struct cvmx_mio_uartx_fcr_s cn30xx;
1258 struct cvmx_mio_uartx_fcr_s cn31xx;
1259 struct cvmx_mio_uartx_fcr_s cn38xx;
1260 struct cvmx_mio_uartx_fcr_s cn38xxp2;
1261 struct cvmx_mio_uartx_fcr_s cn50xx;
1262 struct cvmx_mio_uartx_fcr_s cn52xx;
1263 struct cvmx_mio_uartx_fcr_s cn52xxp1;
1264 struct cvmx_mio_uartx_fcr_s cn56xx;
1265 struct cvmx_mio_uartx_fcr_s cn56xxp1;
1266 struct cvmx_mio_uartx_fcr_s cn58xx;
1267 struct cvmx_mio_uartx_fcr_s cn58xxp1;
1268};
1269
1270union cvmx_mio_uartx_htx {
1271 uint64_t u64;
1272 struct cvmx_mio_uartx_htx_s {
1273 uint64_t reserved_1_63:63;
1274 uint64_t htx:1;
1275 } s;
1276 struct cvmx_mio_uartx_htx_s cn30xx;
1277 struct cvmx_mio_uartx_htx_s cn31xx;
1278 struct cvmx_mio_uartx_htx_s cn38xx;
1279 struct cvmx_mio_uartx_htx_s cn38xxp2;
1280 struct cvmx_mio_uartx_htx_s cn50xx;
1281 struct cvmx_mio_uartx_htx_s cn52xx;
1282 struct cvmx_mio_uartx_htx_s cn52xxp1;
1283 struct cvmx_mio_uartx_htx_s cn56xx;
1284 struct cvmx_mio_uartx_htx_s cn56xxp1;
1285 struct cvmx_mio_uartx_htx_s cn58xx;
1286 struct cvmx_mio_uartx_htx_s cn58xxp1;
1287};
1288
1289union cvmx_mio_uartx_ier {
1290 uint64_t u64;
1291 struct cvmx_mio_uartx_ier_s {
1292 uint64_t reserved_8_63:56;
1293 uint64_t ptime:1;
1294 uint64_t reserved_4_6:3;
1295 uint64_t edssi:1;
1296 uint64_t elsi:1;
1297 uint64_t etbei:1;
1298 uint64_t erbfi:1;
1299 } s;
1300 struct cvmx_mio_uartx_ier_s cn30xx;
1301 struct cvmx_mio_uartx_ier_s cn31xx;
1302 struct cvmx_mio_uartx_ier_s cn38xx;
1303 struct cvmx_mio_uartx_ier_s cn38xxp2;
1304 struct cvmx_mio_uartx_ier_s cn50xx;
1305 struct cvmx_mio_uartx_ier_s cn52xx;
1306 struct cvmx_mio_uartx_ier_s cn52xxp1;
1307 struct cvmx_mio_uartx_ier_s cn56xx;
1308 struct cvmx_mio_uartx_ier_s cn56xxp1;
1309 struct cvmx_mio_uartx_ier_s cn58xx;
1310 struct cvmx_mio_uartx_ier_s cn58xxp1;
1311};
1312
1313union cvmx_mio_uartx_iir {
1314 uint64_t u64;
1315 struct cvmx_mio_uartx_iir_s {
1316 uint64_t reserved_8_63:56;
1317 uint64_t fen:2;
1318 uint64_t reserved_4_5:2;
1319 uint64_t iid:4;
1320 } s;
1321 struct cvmx_mio_uartx_iir_s cn30xx;
1322 struct cvmx_mio_uartx_iir_s cn31xx;
1323 struct cvmx_mio_uartx_iir_s cn38xx;
1324 struct cvmx_mio_uartx_iir_s cn38xxp2;
1325 struct cvmx_mio_uartx_iir_s cn50xx;
1326 struct cvmx_mio_uartx_iir_s cn52xx;
1327 struct cvmx_mio_uartx_iir_s cn52xxp1;
1328 struct cvmx_mio_uartx_iir_s cn56xx;
1329 struct cvmx_mio_uartx_iir_s cn56xxp1;
1330 struct cvmx_mio_uartx_iir_s cn58xx;
1331 struct cvmx_mio_uartx_iir_s cn58xxp1;
1332};
1333
1334union cvmx_mio_uartx_lcr {
1335 uint64_t u64;
1336 struct cvmx_mio_uartx_lcr_s {
1337 uint64_t reserved_8_63:56;
1338 uint64_t dlab:1;
1339 uint64_t brk:1;
1340 uint64_t reserved_5_5:1;
1341 uint64_t eps:1;
1342 uint64_t pen:1;
1343 uint64_t stop:1;
1344 uint64_t cls:2;
1345 } s;
1346 struct cvmx_mio_uartx_lcr_s cn30xx;
1347 struct cvmx_mio_uartx_lcr_s cn31xx;
1348 struct cvmx_mio_uartx_lcr_s cn38xx;
1349 struct cvmx_mio_uartx_lcr_s cn38xxp2;
1350 struct cvmx_mio_uartx_lcr_s cn50xx;
1351 struct cvmx_mio_uartx_lcr_s cn52xx;
1352 struct cvmx_mio_uartx_lcr_s cn52xxp1;
1353 struct cvmx_mio_uartx_lcr_s cn56xx;
1354 struct cvmx_mio_uartx_lcr_s cn56xxp1;
1355 struct cvmx_mio_uartx_lcr_s cn58xx;
1356 struct cvmx_mio_uartx_lcr_s cn58xxp1;
1357};
1358
1359union cvmx_mio_uartx_lsr {
1360 uint64_t u64;
1361 struct cvmx_mio_uartx_lsr_s {
1362 uint64_t reserved_8_63:56;
1363 uint64_t ferr:1;
1364 uint64_t temt:1;
1365 uint64_t thre:1;
1366 uint64_t bi:1;
1367 uint64_t fe:1;
1368 uint64_t pe:1;
1369 uint64_t oe:1;
1370 uint64_t dr:1;
1371 } s;
1372 struct cvmx_mio_uartx_lsr_s cn30xx;
1373 struct cvmx_mio_uartx_lsr_s cn31xx;
1374 struct cvmx_mio_uartx_lsr_s cn38xx;
1375 struct cvmx_mio_uartx_lsr_s cn38xxp2;
1376 struct cvmx_mio_uartx_lsr_s cn50xx;
1377 struct cvmx_mio_uartx_lsr_s cn52xx;
1378 struct cvmx_mio_uartx_lsr_s cn52xxp1;
1379 struct cvmx_mio_uartx_lsr_s cn56xx;
1380 struct cvmx_mio_uartx_lsr_s cn56xxp1;
1381 struct cvmx_mio_uartx_lsr_s cn58xx;
1382 struct cvmx_mio_uartx_lsr_s cn58xxp1;
1383};
1384
1385union cvmx_mio_uartx_mcr {
1386 uint64_t u64;
1387 struct cvmx_mio_uartx_mcr_s {
1388 uint64_t reserved_6_63:58;
1389 uint64_t afce:1;
1390 uint64_t loop:1;
1391 uint64_t out2:1;
1392 uint64_t out1:1;
1393 uint64_t rts:1;
1394 uint64_t dtr:1;
1395 } s;
1396 struct cvmx_mio_uartx_mcr_s cn30xx;
1397 struct cvmx_mio_uartx_mcr_s cn31xx;
1398 struct cvmx_mio_uartx_mcr_s cn38xx;
1399 struct cvmx_mio_uartx_mcr_s cn38xxp2;
1400 struct cvmx_mio_uartx_mcr_s cn50xx;
1401 struct cvmx_mio_uartx_mcr_s cn52xx;
1402 struct cvmx_mio_uartx_mcr_s cn52xxp1;
1403 struct cvmx_mio_uartx_mcr_s cn56xx;
1404 struct cvmx_mio_uartx_mcr_s cn56xxp1;
1405 struct cvmx_mio_uartx_mcr_s cn58xx;
1406 struct cvmx_mio_uartx_mcr_s cn58xxp1;
1407};
1408
1409union cvmx_mio_uartx_msr {
1410 uint64_t u64;
1411 struct cvmx_mio_uartx_msr_s {
1412 uint64_t reserved_8_63:56;
1413 uint64_t dcd:1;
1414 uint64_t ri:1;
1415 uint64_t dsr:1;
1416 uint64_t cts:1;
1417 uint64_t ddcd:1;
1418 uint64_t teri:1;
1419 uint64_t ddsr:1;
1420 uint64_t dcts:1;
1421 } s;
1422 struct cvmx_mio_uartx_msr_s cn30xx;
1423 struct cvmx_mio_uartx_msr_s cn31xx;
1424 struct cvmx_mio_uartx_msr_s cn38xx;
1425 struct cvmx_mio_uartx_msr_s cn38xxp2;
1426 struct cvmx_mio_uartx_msr_s cn50xx;
1427 struct cvmx_mio_uartx_msr_s cn52xx;
1428 struct cvmx_mio_uartx_msr_s cn52xxp1;
1429 struct cvmx_mio_uartx_msr_s cn56xx;
1430 struct cvmx_mio_uartx_msr_s cn56xxp1;
1431 struct cvmx_mio_uartx_msr_s cn58xx;
1432 struct cvmx_mio_uartx_msr_s cn58xxp1;
1433};
1434
1435union cvmx_mio_uartx_rbr {
1436 uint64_t u64;
1437 struct cvmx_mio_uartx_rbr_s {
1438 uint64_t reserved_8_63:56;
1439 uint64_t rbr:8;
1440 } s;
1441 struct cvmx_mio_uartx_rbr_s cn30xx;
1442 struct cvmx_mio_uartx_rbr_s cn31xx;
1443 struct cvmx_mio_uartx_rbr_s cn38xx;
1444 struct cvmx_mio_uartx_rbr_s cn38xxp2;
1445 struct cvmx_mio_uartx_rbr_s cn50xx;
1446 struct cvmx_mio_uartx_rbr_s cn52xx;
1447 struct cvmx_mio_uartx_rbr_s cn52xxp1;
1448 struct cvmx_mio_uartx_rbr_s cn56xx;
1449 struct cvmx_mio_uartx_rbr_s cn56xxp1;
1450 struct cvmx_mio_uartx_rbr_s cn58xx;
1451 struct cvmx_mio_uartx_rbr_s cn58xxp1;
1452};
1453
1454union cvmx_mio_uartx_rfl {
1455 uint64_t u64;
1456 struct cvmx_mio_uartx_rfl_s {
1457 uint64_t reserved_7_63:57;
1458 uint64_t rfl:7;
1459 } s;
1460 struct cvmx_mio_uartx_rfl_s cn30xx;
1461 struct cvmx_mio_uartx_rfl_s cn31xx;
1462 struct cvmx_mio_uartx_rfl_s cn38xx;
1463 struct cvmx_mio_uartx_rfl_s cn38xxp2;
1464 struct cvmx_mio_uartx_rfl_s cn50xx;
1465 struct cvmx_mio_uartx_rfl_s cn52xx;
1466 struct cvmx_mio_uartx_rfl_s cn52xxp1;
1467 struct cvmx_mio_uartx_rfl_s cn56xx;
1468 struct cvmx_mio_uartx_rfl_s cn56xxp1;
1469 struct cvmx_mio_uartx_rfl_s cn58xx;
1470 struct cvmx_mio_uartx_rfl_s cn58xxp1;
1471};
1472
1473union cvmx_mio_uartx_rfw {
1474 uint64_t u64;
1475 struct cvmx_mio_uartx_rfw_s {
1476 uint64_t reserved_10_63:54;
1477 uint64_t rffe:1;
1478 uint64_t rfpe:1;
1479 uint64_t rfwd:8;
1480 } s;
1481 struct cvmx_mio_uartx_rfw_s cn30xx;
1482 struct cvmx_mio_uartx_rfw_s cn31xx;
1483 struct cvmx_mio_uartx_rfw_s cn38xx;
1484 struct cvmx_mio_uartx_rfw_s cn38xxp2;
1485 struct cvmx_mio_uartx_rfw_s cn50xx;
1486 struct cvmx_mio_uartx_rfw_s cn52xx;
1487 struct cvmx_mio_uartx_rfw_s cn52xxp1;
1488 struct cvmx_mio_uartx_rfw_s cn56xx;
1489 struct cvmx_mio_uartx_rfw_s cn56xxp1;
1490 struct cvmx_mio_uartx_rfw_s cn58xx;
1491 struct cvmx_mio_uartx_rfw_s cn58xxp1;
1492};
1493
1494union cvmx_mio_uartx_sbcr {
1495 uint64_t u64;
1496 struct cvmx_mio_uartx_sbcr_s {
1497 uint64_t reserved_1_63:63;
1498 uint64_t sbcr:1;
1499 } s;
1500 struct cvmx_mio_uartx_sbcr_s cn30xx;
1501 struct cvmx_mio_uartx_sbcr_s cn31xx;
1502 struct cvmx_mio_uartx_sbcr_s cn38xx;
1503 struct cvmx_mio_uartx_sbcr_s cn38xxp2;
1504 struct cvmx_mio_uartx_sbcr_s cn50xx;
1505 struct cvmx_mio_uartx_sbcr_s cn52xx;
1506 struct cvmx_mio_uartx_sbcr_s cn52xxp1;
1507 struct cvmx_mio_uartx_sbcr_s cn56xx;
1508 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
1509 struct cvmx_mio_uartx_sbcr_s cn58xx;
1510 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
1511};
1512
1513union cvmx_mio_uartx_scr {
1514 uint64_t u64;
1515 struct cvmx_mio_uartx_scr_s {
1516 uint64_t reserved_8_63:56;
1517 uint64_t scr:8;
1518 } s;
1519 struct cvmx_mio_uartx_scr_s cn30xx;
1520 struct cvmx_mio_uartx_scr_s cn31xx;
1521 struct cvmx_mio_uartx_scr_s cn38xx;
1522 struct cvmx_mio_uartx_scr_s cn38xxp2;
1523 struct cvmx_mio_uartx_scr_s cn50xx;
1524 struct cvmx_mio_uartx_scr_s cn52xx;
1525 struct cvmx_mio_uartx_scr_s cn52xxp1;
1526 struct cvmx_mio_uartx_scr_s cn56xx;
1527 struct cvmx_mio_uartx_scr_s cn56xxp1;
1528 struct cvmx_mio_uartx_scr_s cn58xx;
1529 struct cvmx_mio_uartx_scr_s cn58xxp1;
1530};
1531
1532union cvmx_mio_uartx_sfe {
1533 uint64_t u64;
1534 struct cvmx_mio_uartx_sfe_s {
1535 uint64_t reserved_1_63:63;
1536 uint64_t sfe:1;
1537 } s;
1538 struct cvmx_mio_uartx_sfe_s cn30xx;
1539 struct cvmx_mio_uartx_sfe_s cn31xx;
1540 struct cvmx_mio_uartx_sfe_s cn38xx;
1541 struct cvmx_mio_uartx_sfe_s cn38xxp2;
1542 struct cvmx_mio_uartx_sfe_s cn50xx;
1543 struct cvmx_mio_uartx_sfe_s cn52xx;
1544 struct cvmx_mio_uartx_sfe_s cn52xxp1;
1545 struct cvmx_mio_uartx_sfe_s cn56xx;
1546 struct cvmx_mio_uartx_sfe_s cn56xxp1;
1547 struct cvmx_mio_uartx_sfe_s cn58xx;
1548 struct cvmx_mio_uartx_sfe_s cn58xxp1;
1549};
1550
1551union cvmx_mio_uartx_srr {
1552 uint64_t u64;
1553 struct cvmx_mio_uartx_srr_s {
1554 uint64_t reserved_3_63:61;
1555 uint64_t stfr:1;
1556 uint64_t srfr:1;
1557 uint64_t usr:1;
1558 } s;
1559 struct cvmx_mio_uartx_srr_s cn30xx;
1560 struct cvmx_mio_uartx_srr_s cn31xx;
1561 struct cvmx_mio_uartx_srr_s cn38xx;
1562 struct cvmx_mio_uartx_srr_s cn38xxp2;
1563 struct cvmx_mio_uartx_srr_s cn50xx;
1564 struct cvmx_mio_uartx_srr_s cn52xx;
1565 struct cvmx_mio_uartx_srr_s cn52xxp1;
1566 struct cvmx_mio_uartx_srr_s cn56xx;
1567 struct cvmx_mio_uartx_srr_s cn56xxp1;
1568 struct cvmx_mio_uartx_srr_s cn58xx;
1569 struct cvmx_mio_uartx_srr_s cn58xxp1;
1570};
1571
1572union cvmx_mio_uartx_srt {
1573 uint64_t u64;
1574 struct cvmx_mio_uartx_srt_s {
1575 uint64_t reserved_2_63:62;
1576 uint64_t srt:2;
1577 } s;
1578 struct cvmx_mio_uartx_srt_s cn30xx;
1579 struct cvmx_mio_uartx_srt_s cn31xx;
1580 struct cvmx_mio_uartx_srt_s cn38xx;
1581 struct cvmx_mio_uartx_srt_s cn38xxp2;
1582 struct cvmx_mio_uartx_srt_s cn50xx;
1583 struct cvmx_mio_uartx_srt_s cn52xx;
1584 struct cvmx_mio_uartx_srt_s cn52xxp1;
1585 struct cvmx_mio_uartx_srt_s cn56xx;
1586 struct cvmx_mio_uartx_srt_s cn56xxp1;
1587 struct cvmx_mio_uartx_srt_s cn58xx;
1588 struct cvmx_mio_uartx_srt_s cn58xxp1;
1589};
1590
1591union cvmx_mio_uartx_srts {
1592 uint64_t u64;
1593 struct cvmx_mio_uartx_srts_s {
1594 uint64_t reserved_1_63:63;
1595 uint64_t srts:1;
1596 } s;
1597 struct cvmx_mio_uartx_srts_s cn30xx;
1598 struct cvmx_mio_uartx_srts_s cn31xx;
1599 struct cvmx_mio_uartx_srts_s cn38xx;
1600 struct cvmx_mio_uartx_srts_s cn38xxp2;
1601 struct cvmx_mio_uartx_srts_s cn50xx;
1602 struct cvmx_mio_uartx_srts_s cn52xx;
1603 struct cvmx_mio_uartx_srts_s cn52xxp1;
1604 struct cvmx_mio_uartx_srts_s cn56xx;
1605 struct cvmx_mio_uartx_srts_s cn56xxp1;
1606 struct cvmx_mio_uartx_srts_s cn58xx;
1607 struct cvmx_mio_uartx_srts_s cn58xxp1;
1608};
1609
1610union cvmx_mio_uartx_stt {
1611 uint64_t u64;
1612 struct cvmx_mio_uartx_stt_s {
1613 uint64_t reserved_2_63:62;
1614 uint64_t stt:2;
1615 } s;
1616 struct cvmx_mio_uartx_stt_s cn30xx;
1617 struct cvmx_mio_uartx_stt_s cn31xx;
1618 struct cvmx_mio_uartx_stt_s cn38xx;
1619 struct cvmx_mio_uartx_stt_s cn38xxp2;
1620 struct cvmx_mio_uartx_stt_s cn50xx;
1621 struct cvmx_mio_uartx_stt_s cn52xx;
1622 struct cvmx_mio_uartx_stt_s cn52xxp1;
1623 struct cvmx_mio_uartx_stt_s cn56xx;
1624 struct cvmx_mio_uartx_stt_s cn56xxp1;
1625 struct cvmx_mio_uartx_stt_s cn58xx;
1626 struct cvmx_mio_uartx_stt_s cn58xxp1;
1627};
1628
1629union cvmx_mio_uartx_tfl {
1630 uint64_t u64;
1631 struct cvmx_mio_uartx_tfl_s {
1632 uint64_t reserved_7_63:57;
1633 uint64_t tfl:7;
1634 } s;
1635 struct cvmx_mio_uartx_tfl_s cn30xx;
1636 struct cvmx_mio_uartx_tfl_s cn31xx;
1637 struct cvmx_mio_uartx_tfl_s cn38xx;
1638 struct cvmx_mio_uartx_tfl_s cn38xxp2;
1639 struct cvmx_mio_uartx_tfl_s cn50xx;
1640 struct cvmx_mio_uartx_tfl_s cn52xx;
1641 struct cvmx_mio_uartx_tfl_s cn52xxp1;
1642 struct cvmx_mio_uartx_tfl_s cn56xx;
1643 struct cvmx_mio_uartx_tfl_s cn56xxp1;
1644 struct cvmx_mio_uartx_tfl_s cn58xx;
1645 struct cvmx_mio_uartx_tfl_s cn58xxp1;
1646};
1647
1648union cvmx_mio_uartx_tfr {
1649 uint64_t u64;
1650 struct cvmx_mio_uartx_tfr_s {
1651 uint64_t reserved_8_63:56;
1652 uint64_t tfr:8;
1653 } s;
1654 struct cvmx_mio_uartx_tfr_s cn30xx;
1655 struct cvmx_mio_uartx_tfr_s cn31xx;
1656 struct cvmx_mio_uartx_tfr_s cn38xx;
1657 struct cvmx_mio_uartx_tfr_s cn38xxp2;
1658 struct cvmx_mio_uartx_tfr_s cn50xx;
1659 struct cvmx_mio_uartx_tfr_s cn52xx;
1660 struct cvmx_mio_uartx_tfr_s cn52xxp1;
1661 struct cvmx_mio_uartx_tfr_s cn56xx;
1662 struct cvmx_mio_uartx_tfr_s cn56xxp1;
1663 struct cvmx_mio_uartx_tfr_s cn58xx;
1664 struct cvmx_mio_uartx_tfr_s cn58xxp1;
1665};
1666
1667union cvmx_mio_uartx_thr {
1668 uint64_t u64;
1669 struct cvmx_mio_uartx_thr_s {
1670 uint64_t reserved_8_63:56;
1671 uint64_t thr:8;
1672 } s;
1673 struct cvmx_mio_uartx_thr_s cn30xx;
1674 struct cvmx_mio_uartx_thr_s cn31xx;
1675 struct cvmx_mio_uartx_thr_s cn38xx;
1676 struct cvmx_mio_uartx_thr_s cn38xxp2;
1677 struct cvmx_mio_uartx_thr_s cn50xx;
1678 struct cvmx_mio_uartx_thr_s cn52xx;
1679 struct cvmx_mio_uartx_thr_s cn52xxp1;
1680 struct cvmx_mio_uartx_thr_s cn56xx;
1681 struct cvmx_mio_uartx_thr_s cn56xxp1;
1682 struct cvmx_mio_uartx_thr_s cn58xx;
1683 struct cvmx_mio_uartx_thr_s cn58xxp1;
1684};
1685
1686union cvmx_mio_uartx_usr {
1687 uint64_t u64;
1688 struct cvmx_mio_uartx_usr_s {
1689 uint64_t reserved_5_63:59;
1690 uint64_t rff:1;
1691 uint64_t rfne:1;
1692 uint64_t tfe:1;
1693 uint64_t tfnf:1;
1694 uint64_t busy:1;
1695 } s;
1696 struct cvmx_mio_uartx_usr_s cn30xx;
1697 struct cvmx_mio_uartx_usr_s cn31xx;
1698 struct cvmx_mio_uartx_usr_s cn38xx;
1699 struct cvmx_mio_uartx_usr_s cn38xxp2;
1700 struct cvmx_mio_uartx_usr_s cn50xx;
1701 struct cvmx_mio_uartx_usr_s cn52xx;
1702 struct cvmx_mio_uartx_usr_s cn52xxp1;
1703 struct cvmx_mio_uartx_usr_s cn56xx;
1704 struct cvmx_mio_uartx_usr_s cn56xxp1;
1705 struct cvmx_mio_uartx_usr_s cn58xx;
1706 struct cvmx_mio_uartx_usr_s cn58xxp1;
1707};
1708
1709union cvmx_mio_uart2_dlh {
1710 uint64_t u64;
1711 struct cvmx_mio_uart2_dlh_s {
1712 uint64_t reserved_8_63:56;
1713 uint64_t dlh:8;
1714 } s;
1715 struct cvmx_mio_uart2_dlh_s cn52xx;
1716 struct cvmx_mio_uart2_dlh_s cn52xxp1;
1717};
1718
1719union cvmx_mio_uart2_dll {
1720 uint64_t u64;
1721 struct cvmx_mio_uart2_dll_s {
1722 uint64_t reserved_8_63:56;
1723 uint64_t dll:8;
1724 } s;
1725 struct cvmx_mio_uart2_dll_s cn52xx;
1726 struct cvmx_mio_uart2_dll_s cn52xxp1;
1727};
1728
1729union cvmx_mio_uart2_far {
1730 uint64_t u64;
1731 struct cvmx_mio_uart2_far_s {
1732 uint64_t reserved_1_63:63;
1733 uint64_t far:1;
1734 } s;
1735 struct cvmx_mio_uart2_far_s cn52xx;
1736 struct cvmx_mio_uart2_far_s cn52xxp1;
1737};
1738
1739union cvmx_mio_uart2_fcr {
1740 uint64_t u64;
1741 struct cvmx_mio_uart2_fcr_s {
1742 uint64_t reserved_8_63:56;
1743 uint64_t rxtrig:2;
1744 uint64_t txtrig:2;
1745 uint64_t reserved_3_3:1;
1746 uint64_t txfr:1;
1747 uint64_t rxfr:1;
1748 uint64_t en:1;
1749 } s;
1750 struct cvmx_mio_uart2_fcr_s cn52xx;
1751 struct cvmx_mio_uart2_fcr_s cn52xxp1;
1752};
1753
1754union cvmx_mio_uart2_htx {
1755 uint64_t u64;
1756 struct cvmx_mio_uart2_htx_s {
1757 uint64_t reserved_1_63:63;
1758 uint64_t htx:1;
1759 } s;
1760 struct cvmx_mio_uart2_htx_s cn52xx;
1761 struct cvmx_mio_uart2_htx_s cn52xxp1;
1762};
1763
1764union cvmx_mio_uart2_ier {
1765 uint64_t u64;
1766 struct cvmx_mio_uart2_ier_s {
1767 uint64_t reserved_8_63:56;
1768 uint64_t ptime:1;
1769 uint64_t reserved_4_6:3;
1770 uint64_t edssi:1;
1771 uint64_t elsi:1;
1772 uint64_t etbei:1;
1773 uint64_t erbfi:1;
1774 } s;
1775 struct cvmx_mio_uart2_ier_s cn52xx;
1776 struct cvmx_mio_uart2_ier_s cn52xxp1;
1777};
1778
1779union cvmx_mio_uart2_iir {
1780 uint64_t u64;
1781 struct cvmx_mio_uart2_iir_s {
1782 uint64_t reserved_8_63:56;
1783 uint64_t fen:2;
1784 uint64_t reserved_4_5:2;
1785 uint64_t iid:4;
1786 } s;
1787 struct cvmx_mio_uart2_iir_s cn52xx;
1788 struct cvmx_mio_uart2_iir_s cn52xxp1;
1789};
1790
1791union cvmx_mio_uart2_lcr {
1792 uint64_t u64;
1793 struct cvmx_mio_uart2_lcr_s {
1794 uint64_t reserved_8_63:56;
1795 uint64_t dlab:1;
1796 uint64_t brk:1;
1797 uint64_t reserved_5_5:1;
1798 uint64_t eps:1;
1799 uint64_t pen:1;
1800 uint64_t stop:1;
1801 uint64_t cls:2;
1802 } s;
1803 struct cvmx_mio_uart2_lcr_s cn52xx;
1804 struct cvmx_mio_uart2_lcr_s cn52xxp1;
1805};
1806
1807union cvmx_mio_uart2_lsr {
1808 uint64_t u64;
1809 struct cvmx_mio_uart2_lsr_s {
1810 uint64_t reserved_8_63:56;
1811 uint64_t ferr:1;
1812 uint64_t temt:1;
1813 uint64_t thre:1;
1814 uint64_t bi:1;
1815 uint64_t fe:1;
1816 uint64_t pe:1;
1817 uint64_t oe:1;
1818 uint64_t dr:1;
1819 } s;
1820 struct cvmx_mio_uart2_lsr_s cn52xx;
1821 struct cvmx_mio_uart2_lsr_s cn52xxp1;
1822};
1823
1824union cvmx_mio_uart2_mcr {
1825 uint64_t u64;
1826 struct cvmx_mio_uart2_mcr_s {
1827 uint64_t reserved_6_63:58;
1828 uint64_t afce:1;
1829 uint64_t loop:1;
1830 uint64_t out2:1;
1831 uint64_t out1:1;
1832 uint64_t rts:1;
1833 uint64_t dtr:1;
1834 } s;
1835 struct cvmx_mio_uart2_mcr_s cn52xx;
1836 struct cvmx_mio_uart2_mcr_s cn52xxp1;
1837};
1838
1839union cvmx_mio_uart2_msr {
1840 uint64_t u64;
1841 struct cvmx_mio_uart2_msr_s {
1842 uint64_t reserved_8_63:56;
1843 uint64_t dcd:1;
1844 uint64_t ri:1;
1845 uint64_t dsr:1;
1846 uint64_t cts:1;
1847 uint64_t ddcd:1;
1848 uint64_t teri:1;
1849 uint64_t ddsr:1;
1850 uint64_t dcts:1;
1851 } s;
1852 struct cvmx_mio_uart2_msr_s cn52xx;
1853 struct cvmx_mio_uart2_msr_s cn52xxp1;
1854};
1855
1856union cvmx_mio_uart2_rbr {
1857 uint64_t u64;
1858 struct cvmx_mio_uart2_rbr_s {
1859 uint64_t reserved_8_63:56;
1860 uint64_t rbr:8;
1861 } s;
1862 struct cvmx_mio_uart2_rbr_s cn52xx;
1863 struct cvmx_mio_uart2_rbr_s cn52xxp1;
1864};
1865
1866union cvmx_mio_uart2_rfl {
1867 uint64_t u64;
1868 struct cvmx_mio_uart2_rfl_s {
1869 uint64_t reserved_7_63:57;
1870 uint64_t rfl:7;
1871 } s;
1872 struct cvmx_mio_uart2_rfl_s cn52xx;
1873 struct cvmx_mio_uart2_rfl_s cn52xxp1;
1874};
1875
1876union cvmx_mio_uart2_rfw {
1877 uint64_t u64;
1878 struct cvmx_mio_uart2_rfw_s {
1879 uint64_t reserved_10_63:54;
1880 uint64_t rffe:1;
1881 uint64_t rfpe:1;
1882 uint64_t rfwd:8;
1883 } s;
1884 struct cvmx_mio_uart2_rfw_s cn52xx;
1885 struct cvmx_mio_uart2_rfw_s cn52xxp1;
1886};
1887
1888union cvmx_mio_uart2_sbcr {
1889 uint64_t u64;
1890 struct cvmx_mio_uart2_sbcr_s {
1891 uint64_t reserved_1_63:63;
1892 uint64_t sbcr:1;
1893 } s;
1894 struct cvmx_mio_uart2_sbcr_s cn52xx;
1895 struct cvmx_mio_uart2_sbcr_s cn52xxp1;
1896};
1897
1898union cvmx_mio_uart2_scr {
1899 uint64_t u64;
1900 struct cvmx_mio_uart2_scr_s {
1901 uint64_t reserved_8_63:56;
1902 uint64_t scr:8;
1903 } s;
1904 struct cvmx_mio_uart2_scr_s cn52xx;
1905 struct cvmx_mio_uart2_scr_s cn52xxp1;
1906};
1907
1908union cvmx_mio_uart2_sfe {
1909 uint64_t u64;
1910 struct cvmx_mio_uart2_sfe_s {
1911 uint64_t reserved_1_63:63;
1912 uint64_t sfe:1;
1913 } s;
1914 struct cvmx_mio_uart2_sfe_s cn52xx;
1915 struct cvmx_mio_uart2_sfe_s cn52xxp1;
1916};
1917
1918union cvmx_mio_uart2_srr {
1919 uint64_t u64;
1920 struct cvmx_mio_uart2_srr_s {
1921 uint64_t reserved_3_63:61;
1922 uint64_t stfr:1;
1923 uint64_t srfr:1;
1924 uint64_t usr:1;
1925 } s;
1926 struct cvmx_mio_uart2_srr_s cn52xx;
1927 struct cvmx_mio_uart2_srr_s cn52xxp1;
1928};
1929
1930union cvmx_mio_uart2_srt {
1931 uint64_t u64;
1932 struct cvmx_mio_uart2_srt_s {
1933 uint64_t reserved_2_63:62;
1934 uint64_t srt:2;
1935 } s;
1936 struct cvmx_mio_uart2_srt_s cn52xx;
1937 struct cvmx_mio_uart2_srt_s cn52xxp1;
1938};
1939
1940union cvmx_mio_uart2_srts {
1941 uint64_t u64;
1942 struct cvmx_mio_uart2_srts_s {
1943 uint64_t reserved_1_63:63;
1944 uint64_t srts:1;
1945 } s;
1946 struct cvmx_mio_uart2_srts_s cn52xx;
1947 struct cvmx_mio_uart2_srts_s cn52xxp1;
1948};
1949
1950union cvmx_mio_uart2_stt {
1951 uint64_t u64;
1952 struct cvmx_mio_uart2_stt_s {
1953 uint64_t reserved_2_63:62;
1954 uint64_t stt:2;
1955 } s;
1956 struct cvmx_mio_uart2_stt_s cn52xx;
1957 struct cvmx_mio_uart2_stt_s cn52xxp1;
1958};
1959
1960union cvmx_mio_uart2_tfl {
1961 uint64_t u64;
1962 struct cvmx_mio_uart2_tfl_s {
1963 uint64_t reserved_7_63:57;
1964 uint64_t tfl:7;
1965 } s;
1966 struct cvmx_mio_uart2_tfl_s cn52xx;
1967 struct cvmx_mio_uart2_tfl_s cn52xxp1;
1968};
1969
1970union cvmx_mio_uart2_tfr {
1971 uint64_t u64;
1972 struct cvmx_mio_uart2_tfr_s {
1973 uint64_t reserved_8_63:56;
1974 uint64_t tfr:8;
1975 } s;
1976 struct cvmx_mio_uart2_tfr_s cn52xx;
1977 struct cvmx_mio_uart2_tfr_s cn52xxp1;
1978};
1979
1980union cvmx_mio_uart2_thr {
1981 uint64_t u64;
1982 struct cvmx_mio_uart2_thr_s {
1983 uint64_t reserved_8_63:56;
1984 uint64_t thr:8;
1985 } s;
1986 struct cvmx_mio_uart2_thr_s cn52xx;
1987 struct cvmx_mio_uart2_thr_s cn52xxp1;
1988};
1989
1990union cvmx_mio_uart2_usr {
1991 uint64_t u64;
1992 struct cvmx_mio_uart2_usr_s {
1993 uint64_t reserved_5_63:59;
1994 uint64_t rff:1;
1995 uint64_t rfne:1;
1996 uint64_t tfe:1;
1997 uint64_t tfnf:1;
1998 uint64_t busy:1;
1999 } s;
2000 struct cvmx_mio_uart2_usr_s cn52xx;
2001 struct cvmx_mio_uart2_usr_s cn52xxp1;
2002};
2003
2004#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
new file mode 100644
index 000000000000..38aefa1bab9d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
@@ -0,0 +1,61 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Packet buffer defines.
30 */
31
32#ifndef __CVMX_PACKET_H__
33#define __CVMX_PACKET_H__
34
35/**
36 * This structure defines a buffer pointer on Octeon
37 */
38union cvmx_buf_ptr {
39 void *ptr;
40 uint64_t u64;
41 struct {
42 /* if set, invert the "free" pick of the overall
43 * packet. HW always sets this bit to 0 on inbound
44 * packet */
45 uint64_t i:1;
46
47 /* Indicates the amount to back up to get to the
48 * buffer start in cache lines. In most cases this is
49 * less than one complete cache line, so the value is
50 * zero */
51 uint64_t back:4;
52 /* The pool that the buffer came from / goes to */
53 uint64_t pool:3;
54 /* The size of the segment pointed to by addr (in bytes) */
55 uint64_t size:16;
56 /* Pointer to the first byte of the data, NOT buffer */
57 uint64_t addr:40;
58 } s;
59};
60
61#endif /* __CVMX_PACKET_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
new file mode 100644
index 000000000000..2d82e24be51c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -0,0 +1,698 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_POW_DEFS_H__
29#define __CVMX_POW_DEFS_H__
30
31#define CVMX_POW_BIST_STAT \
32 CVMX_ADD_IO_SEG(0x00016700000003F8ull)
33#define CVMX_POW_DS_PC \
34 CVMX_ADD_IO_SEG(0x0001670000000398ull)
35#define CVMX_POW_ECC_ERR \
36 CVMX_ADD_IO_SEG(0x0001670000000218ull)
37#define CVMX_POW_INT_CTL \
38 CVMX_ADD_IO_SEG(0x0001670000000220ull)
39#define CVMX_POW_IQ_CNTX(offset) \
40 CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8))
41#define CVMX_POW_IQ_COM_CNT \
42 CVMX_ADD_IO_SEG(0x0001670000000388ull)
43#define CVMX_POW_IQ_INT \
44 CVMX_ADD_IO_SEG(0x0001670000000238ull)
45#define CVMX_POW_IQ_INT_EN \
46 CVMX_ADD_IO_SEG(0x0001670000000240ull)
47#define CVMX_POW_IQ_THRX(offset) \
48 CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8))
49#define CVMX_POW_NOS_CNT \
50 CVMX_ADD_IO_SEG(0x0001670000000228ull)
51#define CVMX_POW_NW_TIM \
52 CVMX_ADD_IO_SEG(0x0001670000000210ull)
53#define CVMX_POW_PF_RST_MSK \
54 CVMX_ADD_IO_SEG(0x0001670000000230ull)
55#define CVMX_POW_PP_GRP_MSKX(offset) \
56 CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
57#define CVMX_POW_QOS_RNDX(offset) \
58 CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
59#define CVMX_POW_QOS_THRX(offset) \
60 CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
61#define CVMX_POW_TS_PC \
62 CVMX_ADD_IO_SEG(0x0001670000000390ull)
63#define CVMX_POW_WA_COM_PC \
64 CVMX_ADD_IO_SEG(0x0001670000000380ull)
65#define CVMX_POW_WA_PCX(offset) \
66 CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
67#define CVMX_POW_WQ_INT \
68 CVMX_ADD_IO_SEG(0x0001670000000200ull)
69#define CVMX_POW_WQ_INT_CNTX(offset) \
70 CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
71#define CVMX_POW_WQ_INT_PC \
72 CVMX_ADD_IO_SEG(0x0001670000000208ull)
73#define CVMX_POW_WQ_INT_THRX(offset) \
74 CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
75#define CVMX_POW_WS_PCX(offset) \
76 CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
77
78union cvmx_pow_bist_stat {
79 uint64_t u64;
80 struct cvmx_pow_bist_stat_s {
81 uint64_t reserved_32_63:32;
82 uint64_t pp:16;
83 uint64_t reserved_0_15:16;
84 } s;
85 struct cvmx_pow_bist_stat_cn30xx {
86 uint64_t reserved_17_63:47;
87 uint64_t pp:1;
88 uint64_t reserved_9_15:7;
89 uint64_t cam:1;
90 uint64_t nbt1:1;
91 uint64_t nbt0:1;
92 uint64_t index:1;
93 uint64_t fidx:1;
94 uint64_t nbr1:1;
95 uint64_t nbr0:1;
96 uint64_t pend:1;
97 uint64_t adr:1;
98 } cn30xx;
99 struct cvmx_pow_bist_stat_cn31xx {
100 uint64_t reserved_18_63:46;
101 uint64_t pp:2;
102 uint64_t reserved_9_15:7;
103 uint64_t cam:1;
104 uint64_t nbt1:1;
105 uint64_t nbt0:1;
106 uint64_t index:1;
107 uint64_t fidx:1;
108 uint64_t nbr1:1;
109 uint64_t nbr0:1;
110 uint64_t pend:1;
111 uint64_t adr:1;
112 } cn31xx;
113 struct cvmx_pow_bist_stat_cn38xx {
114 uint64_t reserved_32_63:32;
115 uint64_t pp:16;
116 uint64_t reserved_10_15:6;
117 uint64_t cam:1;
118 uint64_t nbt:1;
119 uint64_t index:1;
120 uint64_t fidx:1;
121 uint64_t nbr1:1;
122 uint64_t nbr0:1;
123 uint64_t pend1:1;
124 uint64_t pend0:1;
125 uint64_t adr1:1;
126 uint64_t adr0:1;
127 } cn38xx;
128 struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
129 struct cvmx_pow_bist_stat_cn31xx cn50xx;
130 struct cvmx_pow_bist_stat_cn52xx {
131 uint64_t reserved_20_63:44;
132 uint64_t pp:4;
133 uint64_t reserved_9_15:7;
134 uint64_t cam:1;
135 uint64_t nbt1:1;
136 uint64_t nbt0:1;
137 uint64_t index:1;
138 uint64_t fidx:1;
139 uint64_t nbr1:1;
140 uint64_t nbr0:1;
141 uint64_t pend:1;
142 uint64_t adr:1;
143 } cn52xx;
144 struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
145 struct cvmx_pow_bist_stat_cn56xx {
146 uint64_t reserved_28_63:36;
147 uint64_t pp:12;
148 uint64_t reserved_10_15:6;
149 uint64_t cam:1;
150 uint64_t nbt:1;
151 uint64_t index:1;
152 uint64_t fidx:1;
153 uint64_t nbr1:1;
154 uint64_t nbr0:1;
155 uint64_t pend1:1;
156 uint64_t pend0:1;
157 uint64_t adr1:1;
158 uint64_t adr0:1;
159 } cn56xx;
160 struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
161 struct cvmx_pow_bist_stat_cn38xx cn58xx;
162 struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
163};
164
165union cvmx_pow_ds_pc {
166 uint64_t u64;
167 struct cvmx_pow_ds_pc_s {
168 uint64_t reserved_32_63:32;
169 uint64_t ds_pc:32;
170 } s;
171 struct cvmx_pow_ds_pc_s cn30xx;
172 struct cvmx_pow_ds_pc_s cn31xx;
173 struct cvmx_pow_ds_pc_s cn38xx;
174 struct cvmx_pow_ds_pc_s cn38xxp2;
175 struct cvmx_pow_ds_pc_s cn50xx;
176 struct cvmx_pow_ds_pc_s cn52xx;
177 struct cvmx_pow_ds_pc_s cn52xxp1;
178 struct cvmx_pow_ds_pc_s cn56xx;
179 struct cvmx_pow_ds_pc_s cn56xxp1;
180 struct cvmx_pow_ds_pc_s cn58xx;
181 struct cvmx_pow_ds_pc_s cn58xxp1;
182};
183
184union cvmx_pow_ecc_err {
185 uint64_t u64;
186 struct cvmx_pow_ecc_err_s {
187 uint64_t reserved_45_63:19;
188 uint64_t iop_ie:13;
189 uint64_t reserved_29_31:3;
190 uint64_t iop:13;
191 uint64_t reserved_14_15:2;
192 uint64_t rpe_ie:1;
193 uint64_t rpe:1;
194 uint64_t reserved_9_11:3;
195 uint64_t syn:5;
196 uint64_t dbe_ie:1;
197 uint64_t sbe_ie:1;
198 uint64_t dbe:1;
199 uint64_t sbe:1;
200 } s;
201 struct cvmx_pow_ecc_err_s cn30xx;
202 struct cvmx_pow_ecc_err_cn31xx {
203 uint64_t reserved_14_63:50;
204 uint64_t rpe_ie:1;
205 uint64_t rpe:1;
206 uint64_t reserved_9_11:3;
207 uint64_t syn:5;
208 uint64_t dbe_ie:1;
209 uint64_t sbe_ie:1;
210 uint64_t dbe:1;
211 uint64_t sbe:1;
212 } cn31xx;
213 struct cvmx_pow_ecc_err_s cn38xx;
214 struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
215 struct cvmx_pow_ecc_err_s cn50xx;
216 struct cvmx_pow_ecc_err_s cn52xx;
217 struct cvmx_pow_ecc_err_s cn52xxp1;
218 struct cvmx_pow_ecc_err_s cn56xx;
219 struct cvmx_pow_ecc_err_s cn56xxp1;
220 struct cvmx_pow_ecc_err_s cn58xx;
221 struct cvmx_pow_ecc_err_s cn58xxp1;
222};
223
224union cvmx_pow_int_ctl {
225 uint64_t u64;
226 struct cvmx_pow_int_ctl_s {
227 uint64_t reserved_6_63:58;
228 uint64_t pfr_dis:1;
229 uint64_t nbr_thr:5;
230 } s;
231 struct cvmx_pow_int_ctl_s cn30xx;
232 struct cvmx_pow_int_ctl_s cn31xx;
233 struct cvmx_pow_int_ctl_s cn38xx;
234 struct cvmx_pow_int_ctl_s cn38xxp2;
235 struct cvmx_pow_int_ctl_s cn50xx;
236 struct cvmx_pow_int_ctl_s cn52xx;
237 struct cvmx_pow_int_ctl_s cn52xxp1;
238 struct cvmx_pow_int_ctl_s cn56xx;
239 struct cvmx_pow_int_ctl_s cn56xxp1;
240 struct cvmx_pow_int_ctl_s cn58xx;
241 struct cvmx_pow_int_ctl_s cn58xxp1;
242};
243
244union cvmx_pow_iq_cntx {
245 uint64_t u64;
246 struct cvmx_pow_iq_cntx_s {
247 uint64_t reserved_32_63:32;
248 uint64_t iq_cnt:32;
249 } s;
250 struct cvmx_pow_iq_cntx_s cn30xx;
251 struct cvmx_pow_iq_cntx_s cn31xx;
252 struct cvmx_pow_iq_cntx_s cn38xx;
253 struct cvmx_pow_iq_cntx_s cn38xxp2;
254 struct cvmx_pow_iq_cntx_s cn50xx;
255 struct cvmx_pow_iq_cntx_s cn52xx;
256 struct cvmx_pow_iq_cntx_s cn52xxp1;
257 struct cvmx_pow_iq_cntx_s cn56xx;
258 struct cvmx_pow_iq_cntx_s cn56xxp1;
259 struct cvmx_pow_iq_cntx_s cn58xx;
260 struct cvmx_pow_iq_cntx_s cn58xxp1;
261};
262
263union cvmx_pow_iq_com_cnt {
264 uint64_t u64;
265 struct cvmx_pow_iq_com_cnt_s {
266 uint64_t reserved_32_63:32;
267 uint64_t iq_cnt:32;
268 } s;
269 struct cvmx_pow_iq_com_cnt_s cn30xx;
270 struct cvmx_pow_iq_com_cnt_s cn31xx;
271 struct cvmx_pow_iq_com_cnt_s cn38xx;
272 struct cvmx_pow_iq_com_cnt_s cn38xxp2;
273 struct cvmx_pow_iq_com_cnt_s cn50xx;
274 struct cvmx_pow_iq_com_cnt_s cn52xx;
275 struct cvmx_pow_iq_com_cnt_s cn52xxp1;
276 struct cvmx_pow_iq_com_cnt_s cn56xx;
277 struct cvmx_pow_iq_com_cnt_s cn56xxp1;
278 struct cvmx_pow_iq_com_cnt_s cn58xx;
279 struct cvmx_pow_iq_com_cnt_s cn58xxp1;
280};
281
282union cvmx_pow_iq_int {
283 uint64_t u64;
284 struct cvmx_pow_iq_int_s {
285 uint64_t reserved_8_63:56;
286 uint64_t iq_int:8;
287 } s;
288 struct cvmx_pow_iq_int_s cn52xx;
289 struct cvmx_pow_iq_int_s cn52xxp1;
290 struct cvmx_pow_iq_int_s cn56xx;
291 struct cvmx_pow_iq_int_s cn56xxp1;
292};
293
294union cvmx_pow_iq_int_en {
295 uint64_t u64;
296 struct cvmx_pow_iq_int_en_s {
297 uint64_t reserved_8_63:56;
298 uint64_t int_en:8;
299 } s;
300 struct cvmx_pow_iq_int_en_s cn52xx;
301 struct cvmx_pow_iq_int_en_s cn52xxp1;
302 struct cvmx_pow_iq_int_en_s cn56xx;
303 struct cvmx_pow_iq_int_en_s cn56xxp1;
304};
305
306union cvmx_pow_iq_thrx {
307 uint64_t u64;
308 struct cvmx_pow_iq_thrx_s {
309 uint64_t reserved_32_63:32;
310 uint64_t iq_thr:32;
311 } s;
312 struct cvmx_pow_iq_thrx_s cn52xx;
313 struct cvmx_pow_iq_thrx_s cn52xxp1;
314 struct cvmx_pow_iq_thrx_s cn56xx;
315 struct cvmx_pow_iq_thrx_s cn56xxp1;
316};
317
318union cvmx_pow_nos_cnt {
319 uint64_t u64;
320 struct cvmx_pow_nos_cnt_s {
321 uint64_t reserved_12_63:52;
322 uint64_t nos_cnt:12;
323 } s;
324 struct cvmx_pow_nos_cnt_cn30xx {
325 uint64_t reserved_7_63:57;
326 uint64_t nos_cnt:7;
327 } cn30xx;
328 struct cvmx_pow_nos_cnt_cn31xx {
329 uint64_t reserved_9_63:55;
330 uint64_t nos_cnt:9;
331 } cn31xx;
332 struct cvmx_pow_nos_cnt_s cn38xx;
333 struct cvmx_pow_nos_cnt_s cn38xxp2;
334 struct cvmx_pow_nos_cnt_cn31xx cn50xx;
335 struct cvmx_pow_nos_cnt_cn52xx {
336 uint64_t reserved_10_63:54;
337 uint64_t nos_cnt:10;
338 } cn52xx;
339 struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
340 struct cvmx_pow_nos_cnt_s cn56xx;
341 struct cvmx_pow_nos_cnt_s cn56xxp1;
342 struct cvmx_pow_nos_cnt_s cn58xx;
343 struct cvmx_pow_nos_cnt_s cn58xxp1;
344};
345
346union cvmx_pow_nw_tim {
347 uint64_t u64;
348 struct cvmx_pow_nw_tim_s {
349 uint64_t reserved_10_63:54;
350 uint64_t nw_tim:10;
351 } s;
352 struct cvmx_pow_nw_tim_s cn30xx;
353 struct cvmx_pow_nw_tim_s cn31xx;
354 struct cvmx_pow_nw_tim_s cn38xx;
355 struct cvmx_pow_nw_tim_s cn38xxp2;
356 struct cvmx_pow_nw_tim_s cn50xx;
357 struct cvmx_pow_nw_tim_s cn52xx;
358 struct cvmx_pow_nw_tim_s cn52xxp1;
359 struct cvmx_pow_nw_tim_s cn56xx;
360 struct cvmx_pow_nw_tim_s cn56xxp1;
361 struct cvmx_pow_nw_tim_s cn58xx;
362 struct cvmx_pow_nw_tim_s cn58xxp1;
363};
364
365union cvmx_pow_pf_rst_msk {
366 uint64_t u64;
367 struct cvmx_pow_pf_rst_msk_s {
368 uint64_t reserved_8_63:56;
369 uint64_t rst_msk:8;
370 } s;
371 struct cvmx_pow_pf_rst_msk_s cn50xx;
372 struct cvmx_pow_pf_rst_msk_s cn52xx;
373 struct cvmx_pow_pf_rst_msk_s cn52xxp1;
374 struct cvmx_pow_pf_rst_msk_s cn56xx;
375 struct cvmx_pow_pf_rst_msk_s cn56xxp1;
376 struct cvmx_pow_pf_rst_msk_s cn58xx;
377 struct cvmx_pow_pf_rst_msk_s cn58xxp1;
378};
379
380union cvmx_pow_pp_grp_mskx {
381 uint64_t u64;
382 struct cvmx_pow_pp_grp_mskx_s {
383 uint64_t reserved_48_63:16;
384 uint64_t qos7_pri:4;
385 uint64_t qos6_pri:4;
386 uint64_t qos5_pri:4;
387 uint64_t qos4_pri:4;
388 uint64_t qos3_pri:4;
389 uint64_t qos2_pri:4;
390 uint64_t qos1_pri:4;
391 uint64_t qos0_pri:4;
392 uint64_t grp_msk:16;
393 } s;
394 struct cvmx_pow_pp_grp_mskx_cn30xx {
395 uint64_t reserved_16_63:48;
396 uint64_t grp_msk:16;
397 } cn30xx;
398 struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
399 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
400 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
401 struct cvmx_pow_pp_grp_mskx_s cn50xx;
402 struct cvmx_pow_pp_grp_mskx_s cn52xx;
403 struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
404 struct cvmx_pow_pp_grp_mskx_s cn56xx;
405 struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
406 struct cvmx_pow_pp_grp_mskx_s cn58xx;
407 struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
408};
409
410union cvmx_pow_qos_rndx {
411 uint64_t u64;
412 struct cvmx_pow_qos_rndx_s {
413 uint64_t reserved_32_63:32;
414 uint64_t rnd_p3:8;
415 uint64_t rnd_p2:8;
416 uint64_t rnd_p1:8;
417 uint64_t rnd:8;
418 } s;
419 struct cvmx_pow_qos_rndx_s cn30xx;
420 struct cvmx_pow_qos_rndx_s cn31xx;
421 struct cvmx_pow_qos_rndx_s cn38xx;
422 struct cvmx_pow_qos_rndx_s cn38xxp2;
423 struct cvmx_pow_qos_rndx_s cn50xx;
424 struct cvmx_pow_qos_rndx_s cn52xx;
425 struct cvmx_pow_qos_rndx_s cn52xxp1;
426 struct cvmx_pow_qos_rndx_s cn56xx;
427 struct cvmx_pow_qos_rndx_s cn56xxp1;
428 struct cvmx_pow_qos_rndx_s cn58xx;
429 struct cvmx_pow_qos_rndx_s cn58xxp1;
430};
431
432union cvmx_pow_qos_thrx {
433 uint64_t u64;
434 struct cvmx_pow_qos_thrx_s {
435 uint64_t reserved_60_63:4;
436 uint64_t des_cnt:12;
437 uint64_t buf_cnt:12;
438 uint64_t free_cnt:12;
439 uint64_t reserved_23_23:1;
440 uint64_t max_thr:11;
441 uint64_t reserved_11_11:1;
442 uint64_t min_thr:11;
443 } s;
444 struct cvmx_pow_qos_thrx_cn30xx {
445 uint64_t reserved_55_63:9;
446 uint64_t des_cnt:7;
447 uint64_t reserved_43_47:5;
448 uint64_t buf_cnt:7;
449 uint64_t reserved_31_35:5;
450 uint64_t free_cnt:7;
451 uint64_t reserved_18_23:6;
452 uint64_t max_thr:6;
453 uint64_t reserved_6_11:6;
454 uint64_t min_thr:6;
455 } cn30xx;
456 struct cvmx_pow_qos_thrx_cn31xx {
457 uint64_t reserved_57_63:7;
458 uint64_t des_cnt:9;
459 uint64_t reserved_45_47:3;
460 uint64_t buf_cnt:9;
461 uint64_t reserved_33_35:3;
462 uint64_t free_cnt:9;
463 uint64_t reserved_20_23:4;
464 uint64_t max_thr:8;
465 uint64_t reserved_8_11:4;
466 uint64_t min_thr:8;
467 } cn31xx;
468 struct cvmx_pow_qos_thrx_s cn38xx;
469 struct cvmx_pow_qos_thrx_s cn38xxp2;
470 struct cvmx_pow_qos_thrx_cn31xx cn50xx;
471 struct cvmx_pow_qos_thrx_cn52xx {
472 uint64_t reserved_58_63:6;
473 uint64_t des_cnt:10;
474 uint64_t reserved_46_47:2;
475 uint64_t buf_cnt:10;
476 uint64_t reserved_34_35:2;
477 uint64_t free_cnt:10;
478 uint64_t reserved_21_23:3;
479 uint64_t max_thr:9;
480 uint64_t reserved_9_11:3;
481 uint64_t min_thr:9;
482 } cn52xx;
483 struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
484 struct cvmx_pow_qos_thrx_s cn56xx;
485 struct cvmx_pow_qos_thrx_s cn56xxp1;
486 struct cvmx_pow_qos_thrx_s cn58xx;
487 struct cvmx_pow_qos_thrx_s cn58xxp1;
488};
489
490union cvmx_pow_ts_pc {
491 uint64_t u64;
492 struct cvmx_pow_ts_pc_s {
493 uint64_t reserved_32_63:32;
494 uint64_t ts_pc:32;
495 } s;
496 struct cvmx_pow_ts_pc_s cn30xx;
497 struct cvmx_pow_ts_pc_s cn31xx;
498 struct cvmx_pow_ts_pc_s cn38xx;
499 struct cvmx_pow_ts_pc_s cn38xxp2;
500 struct cvmx_pow_ts_pc_s cn50xx;
501 struct cvmx_pow_ts_pc_s cn52xx;
502 struct cvmx_pow_ts_pc_s cn52xxp1;
503 struct cvmx_pow_ts_pc_s cn56xx;
504 struct cvmx_pow_ts_pc_s cn56xxp1;
505 struct cvmx_pow_ts_pc_s cn58xx;
506 struct cvmx_pow_ts_pc_s cn58xxp1;
507};
508
509union cvmx_pow_wa_com_pc {
510 uint64_t u64;
511 struct cvmx_pow_wa_com_pc_s {
512 uint64_t reserved_32_63:32;
513 uint64_t wa_pc:32;
514 } s;
515 struct cvmx_pow_wa_com_pc_s cn30xx;
516 struct cvmx_pow_wa_com_pc_s cn31xx;
517 struct cvmx_pow_wa_com_pc_s cn38xx;
518 struct cvmx_pow_wa_com_pc_s cn38xxp2;
519 struct cvmx_pow_wa_com_pc_s cn50xx;
520 struct cvmx_pow_wa_com_pc_s cn52xx;
521 struct cvmx_pow_wa_com_pc_s cn52xxp1;
522 struct cvmx_pow_wa_com_pc_s cn56xx;
523 struct cvmx_pow_wa_com_pc_s cn56xxp1;
524 struct cvmx_pow_wa_com_pc_s cn58xx;
525 struct cvmx_pow_wa_com_pc_s cn58xxp1;
526};
527
528union cvmx_pow_wa_pcx {
529 uint64_t u64;
530 struct cvmx_pow_wa_pcx_s {
531 uint64_t reserved_32_63:32;
532 uint64_t wa_pc:32;
533 } s;
534 struct cvmx_pow_wa_pcx_s cn30xx;
535 struct cvmx_pow_wa_pcx_s cn31xx;
536 struct cvmx_pow_wa_pcx_s cn38xx;
537 struct cvmx_pow_wa_pcx_s cn38xxp2;
538 struct cvmx_pow_wa_pcx_s cn50xx;
539 struct cvmx_pow_wa_pcx_s cn52xx;
540 struct cvmx_pow_wa_pcx_s cn52xxp1;
541 struct cvmx_pow_wa_pcx_s cn56xx;
542 struct cvmx_pow_wa_pcx_s cn56xxp1;
543 struct cvmx_pow_wa_pcx_s cn58xx;
544 struct cvmx_pow_wa_pcx_s cn58xxp1;
545};
546
547union cvmx_pow_wq_int {
548 uint64_t u64;
549 struct cvmx_pow_wq_int_s {
550 uint64_t reserved_32_63:32;
551 uint64_t iq_dis:16;
552 uint64_t wq_int:16;
553 } s;
554 struct cvmx_pow_wq_int_s cn30xx;
555 struct cvmx_pow_wq_int_s cn31xx;
556 struct cvmx_pow_wq_int_s cn38xx;
557 struct cvmx_pow_wq_int_s cn38xxp2;
558 struct cvmx_pow_wq_int_s cn50xx;
559 struct cvmx_pow_wq_int_s cn52xx;
560 struct cvmx_pow_wq_int_s cn52xxp1;
561 struct cvmx_pow_wq_int_s cn56xx;
562 struct cvmx_pow_wq_int_s cn56xxp1;
563 struct cvmx_pow_wq_int_s cn58xx;
564 struct cvmx_pow_wq_int_s cn58xxp1;
565};
566
567union cvmx_pow_wq_int_cntx {
568 uint64_t u64;
569 struct cvmx_pow_wq_int_cntx_s {
570 uint64_t reserved_28_63:36;
571 uint64_t tc_cnt:4;
572 uint64_t ds_cnt:12;
573 uint64_t iq_cnt:12;
574 } s;
575 struct cvmx_pow_wq_int_cntx_cn30xx {
576 uint64_t reserved_28_63:36;
577 uint64_t tc_cnt:4;
578 uint64_t reserved_19_23:5;
579 uint64_t ds_cnt:7;
580 uint64_t reserved_7_11:5;
581 uint64_t iq_cnt:7;
582 } cn30xx;
583 struct cvmx_pow_wq_int_cntx_cn31xx {
584 uint64_t reserved_28_63:36;
585 uint64_t tc_cnt:4;
586 uint64_t reserved_21_23:3;
587 uint64_t ds_cnt:9;
588 uint64_t reserved_9_11:3;
589 uint64_t iq_cnt:9;
590 } cn31xx;
591 struct cvmx_pow_wq_int_cntx_s cn38xx;
592 struct cvmx_pow_wq_int_cntx_s cn38xxp2;
593 struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
594 struct cvmx_pow_wq_int_cntx_cn52xx {
595 uint64_t reserved_28_63:36;
596 uint64_t tc_cnt:4;
597 uint64_t reserved_22_23:2;
598 uint64_t ds_cnt:10;
599 uint64_t reserved_10_11:2;
600 uint64_t iq_cnt:10;
601 } cn52xx;
602 struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
603 struct cvmx_pow_wq_int_cntx_s cn56xx;
604 struct cvmx_pow_wq_int_cntx_s cn56xxp1;
605 struct cvmx_pow_wq_int_cntx_s cn58xx;
606 struct cvmx_pow_wq_int_cntx_s cn58xxp1;
607};
608
609union cvmx_pow_wq_int_pc {
610 uint64_t u64;
611 struct cvmx_pow_wq_int_pc_s {
612 uint64_t reserved_60_63:4;
613 uint64_t pc:28;
614 uint64_t reserved_28_31:4;
615 uint64_t pc_thr:20;
616 uint64_t reserved_0_7:8;
617 } s;
618 struct cvmx_pow_wq_int_pc_s cn30xx;
619 struct cvmx_pow_wq_int_pc_s cn31xx;
620 struct cvmx_pow_wq_int_pc_s cn38xx;
621 struct cvmx_pow_wq_int_pc_s cn38xxp2;
622 struct cvmx_pow_wq_int_pc_s cn50xx;
623 struct cvmx_pow_wq_int_pc_s cn52xx;
624 struct cvmx_pow_wq_int_pc_s cn52xxp1;
625 struct cvmx_pow_wq_int_pc_s cn56xx;
626 struct cvmx_pow_wq_int_pc_s cn56xxp1;
627 struct cvmx_pow_wq_int_pc_s cn58xx;
628 struct cvmx_pow_wq_int_pc_s cn58xxp1;
629};
630
631union cvmx_pow_wq_int_thrx {
632 uint64_t u64;
633 struct cvmx_pow_wq_int_thrx_s {
634 uint64_t reserved_29_63:35;
635 uint64_t tc_en:1;
636 uint64_t tc_thr:4;
637 uint64_t reserved_23_23:1;
638 uint64_t ds_thr:11;
639 uint64_t reserved_11_11:1;
640 uint64_t iq_thr:11;
641 } s;
642 struct cvmx_pow_wq_int_thrx_cn30xx {
643 uint64_t reserved_29_63:35;
644 uint64_t tc_en:1;
645 uint64_t tc_thr:4;
646 uint64_t reserved_18_23:6;
647 uint64_t ds_thr:6;
648 uint64_t reserved_6_11:6;
649 uint64_t iq_thr:6;
650 } cn30xx;
651 struct cvmx_pow_wq_int_thrx_cn31xx {
652 uint64_t reserved_29_63:35;
653 uint64_t tc_en:1;
654 uint64_t tc_thr:4;
655 uint64_t reserved_20_23:4;
656 uint64_t ds_thr:8;
657 uint64_t reserved_8_11:4;
658 uint64_t iq_thr:8;
659 } cn31xx;
660 struct cvmx_pow_wq_int_thrx_s cn38xx;
661 struct cvmx_pow_wq_int_thrx_s cn38xxp2;
662 struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
663 struct cvmx_pow_wq_int_thrx_cn52xx {
664 uint64_t reserved_29_63:35;
665 uint64_t tc_en:1;
666 uint64_t tc_thr:4;
667 uint64_t reserved_21_23:3;
668 uint64_t ds_thr:9;
669 uint64_t reserved_9_11:3;
670 uint64_t iq_thr:9;
671 } cn52xx;
672 struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
673 struct cvmx_pow_wq_int_thrx_s cn56xx;
674 struct cvmx_pow_wq_int_thrx_s cn56xxp1;
675 struct cvmx_pow_wq_int_thrx_s cn58xx;
676 struct cvmx_pow_wq_int_thrx_s cn58xxp1;
677};
678
679union cvmx_pow_ws_pcx {
680 uint64_t u64;
681 struct cvmx_pow_ws_pcx_s {
682 uint64_t reserved_32_63:32;
683 uint64_t ws_pc:32;
684 } s;
685 struct cvmx_pow_ws_pcx_s cn30xx;
686 struct cvmx_pow_ws_pcx_s cn31xx;
687 struct cvmx_pow_ws_pcx_s cn38xx;
688 struct cvmx_pow_ws_pcx_s cn38xxp2;
689 struct cvmx_pow_ws_pcx_s cn50xx;
690 struct cvmx_pow_ws_pcx_s cn52xx;
691 struct cvmx_pow_ws_pcx_s cn52xxp1;
692 struct cvmx_pow_ws_pcx_s cn56xx;
693 struct cvmx_pow_ws_pcx_s cn56xxp1;
694 struct cvmx_pow_ws_pcx_s cn58xx;
695 struct cvmx_pow_ws_pcx_s cn58xxp1;
696};
697
698#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h
new file mode 100644
index 000000000000..2fbf0871df11
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h
@@ -0,0 +1,232 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Implementation of spinlocks for Octeon CVMX. Although similar in
30 * function to Linux kernel spinlocks, they are not compatible.
31 * Octeon CVMX spinlocks are only used to synchronize with the boot
32 * monitor and other non-Linux programs running in the system.
33 */
34
35#ifndef __CVMX_SPINLOCK_H__
36#define __CVMX_SPINLOCK_H__
37
38#include "cvmx-asm.h"
39
40/* Spinlocks for Octeon */
41
42/* define these to enable recursive spinlock debugging */
43/*#define CVMX_SPINLOCK_DEBUG */
44
45/**
46 * Spinlocks for Octeon CVMX
47 */
48typedef struct {
49 volatile uint32_t value;
50} cvmx_spinlock_t;
51
52/* note - macros not expanded in inline ASM, so values hardcoded */
53#define CVMX_SPINLOCK_UNLOCKED_VAL 0
54#define CVMX_SPINLOCK_LOCKED_VAL 1
55
56#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL}
57
58/**
59 * Initialize a spinlock
60 *
61 * @lock: Lock to initialize
62 */
63static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock)
64{
65 lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
66}
67
68/**
69 * Return non-zero if the spinlock is currently locked
70 *
71 * @lock: Lock to check
72 * Returns Non-zero if locked
73 */
74static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock)
75{
76 return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL;
77}
78
79/**
80 * Releases lock
81 *
82 * @lock: pointer to lock structure
83 */
84static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
85{
86 CVMX_SYNCWS;
87 lock->value = 0;
88 CVMX_SYNCWS;
89}
90
91/**
92 * Attempts to take the lock, but does not spin if lock is not available.
93 * May take some time to acquire the lock even if it is available
94 * due to the ll/sc not succeeding.
95 *
96 * @lock: pointer to lock structure
97 *
98 * Returns 0: lock successfully taken
99 * 1: lock not taken, held by someone else
100 * These return values match the Linux semantics.
101 */
102
103static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
104{
105 unsigned int tmp;
106
107 __asm__ __volatile__(".set noreorder \n"
108 "1: ll %[tmp], %[val] \n"
109 /* if lock held, fail immediately */
110 " bnez %[tmp], 2f \n"
111 " li %[tmp], 1 \n"
112 " sc %[tmp], %[val] \n"
113 " beqz %[tmp], 1b \n"
114 " li %[tmp], 0 \n"
115 "2: \n"
116 ".set reorder \n" :
117 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
118 : : "memory");
119
120 return tmp != 0; /* normalize to 0 or 1 */
121}
122
123/**
124 * Gets lock, spins until lock is taken
125 *
126 * @lock: pointer to lock structure
127 */
128static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
129{
130 unsigned int tmp;
131
132 __asm__ __volatile__(".set noreorder \n"
133 "1: ll %[tmp], %[val] \n"
134 " bnez %[tmp], 1b \n"
135 " li %[tmp], 1 \n"
136 " sc %[tmp], %[val] \n"
137 " beqz %[tmp], 1b \n"
138 " nop \n"
139 ".set reorder \n" :
140 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
141 : : "memory");
142
143}
144
145/** ********************************************************************
146 * Bit spinlocks
147 * These spinlocks use a single bit (bit 31) of a 32 bit word for locking.
148 * The rest of the bits in the word are left undisturbed. This enables more
149 * compact data structures as only 1 bit is consumed for the lock.
150 *
151 */
152
153/**
154 * Gets lock, spins until lock is taken
155 * Preserves the low 31 bits of the 32 bit
156 * word used for the lock.
157 *
158 *
159 * @word: word to lock bit 31 of
160 */
161static inline void cvmx_spinlock_bit_lock(uint32_t *word)
162{
163 unsigned int tmp;
164 unsigned int sav;
165
166 __asm__ __volatile__(".set noreorder \n"
167 ".set noat \n"
168 "1: ll %[tmp], %[val] \n"
169 " bbit1 %[tmp], 31, 1b \n"
170 " li $at, 1 \n"
171 " ins %[tmp], $at, 31, 1 \n"
172 " sc %[tmp], %[val] \n"
173 " beqz %[tmp], 1b \n"
174 " nop \n"
175 ".set at \n"
176 ".set reorder \n" :
177 [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
178 : : "memory");
179
180}
181
182/**
183 * Attempts to get lock, returns immediately with success/failure
184 * Preserves the low 31 bits of the 32 bit
185 * word used for the lock.
186 *
187 *
188 * @word: word to lock bit 31 of
189 * Returns 0: lock successfully taken
190 * 1: lock not taken, held by someone else
191 * These return values match the Linux semantics.
192 */
193static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
194{
195 unsigned int tmp;
196
197 __asm__ __volatile__(".set noreorder\n\t"
198 ".set noat\n"
199 "1: ll %[tmp], %[val] \n"
200 /* if lock held, fail immediately */
201 " bbit1 %[tmp], 31, 2f \n"
202 " li $at, 1 \n"
203 " ins %[tmp], $at, 31, 1 \n"
204 " sc %[tmp], %[val] \n"
205 " beqz %[tmp], 1b \n"
206 " li %[tmp], 0 \n"
207 "2: \n"
208 ".set at \n"
209 ".set reorder \n" :
210 [val] "+m"(*word), [tmp] "=&r"(tmp)
211 : : "memory");
212
213 return tmp != 0; /* normalize to 0 or 1 */
214}
215
216/**
217 * Releases bit lock
218 *
219 * Unconditionally clears bit 31 of the lock word. Note that this is
220 * done non-atomically, as this implementation assumes that the rest
221 * of the bits in the word are protected by the lock.
222 *
223 * @word: word to unlock bit 31 in
224 */
225static inline void cvmx_spinlock_bit_unlock(uint32_t *word)
226{
227 CVMX_SYNCWS;
228 *word &= ~(1UL << 31);
229 CVMX_SYNCWS;
230}
231
232#endif /* __CVMX_SPINLOCK_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
new file mode 100644
index 000000000000..61dd5741afe4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
@@ -0,0 +1,152 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * This module provides system/board information obtained by the bootloader.
30 */
31
32#ifndef __CVMX_SYSINFO_H__
33#define __CVMX_SYSINFO_H__
34
35#define OCTEON_SERIAL_LEN 20
36/**
37 * Structure describing application specific information.
38 * __cvmx_app_init() populates this from the cvmx boot descriptor.
39 * This structure is private to simple executive applications, so
40 * no versioning is required.
41 *
42 * This structure must be provided with some fields set in order to
43 * use simple executive functions in other applications (Linux kernel,
44 * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is
45 * provided to set the required values in these cases.
46 */
47struct cvmx_sysinfo {
48 /* System wide variables */
49 /* installed DRAM in system, in bytes */
50 uint64_t system_dram_size;
51
52 /* ptr to memory descriptor block */
53 void *phy_mem_desc_ptr;
54
55
56 /* Application image specific variables */
57 /* stack top address (virtual) */
58 uint64_t stack_top;
59 /* heap base address (virtual) */
60 uint64_t heap_base;
61 /* stack size in bytes */
62 uint32_t stack_size;
63 /* heap size in bytes */
64 uint32_t heap_size;
65 /* coremask defining cores running application */
66 uint32_t core_mask;
67 /* Deprecated, use cvmx_coremask_first_core() to select init core */
68 uint32_t init_core;
69
70 /* exception base address, as set by bootloader */
71 uint64_t exception_base_addr;
72
73 /* cpu clock speed in hz */
74 uint32_t cpu_clock_hz;
75
76 /* dram data rate in hz (data rate = 2 * clock rate */
77 uint32_t dram_data_rate_hz;
78
79
80 uint16_t board_type;
81 uint8_t board_rev_major;
82 uint8_t board_rev_minor;
83 uint8_t mac_addr_base[6];
84 uint8_t mac_addr_count;
85 char board_serial_number[OCTEON_SERIAL_LEN];
86 /*
87 * Several boards support compact flash on the Octeon boot
88 * bus. The CF memory spaces may be mapped to different
89 * addresses on different boards. These values will be 0 if
90 * CF is not present. Note that these addresses are physical
91 * addresses, and it is up to the application to use the
92 * proper addressing mode (XKPHYS, KSEG0, etc.)
93 */
94 uint64_t compact_flash_common_base_addr;
95 uint64_t compact_flash_attribute_base_addr;
96 /*
97 * Base address of the LED display (as on EBT3000 board) This
98 * will be 0 if LED display not present. Note that this
99 * address is a physical address, and it is up to the
100 * application to use the proper addressing mode (XKPHYS,
101 * KSEG0, etc.)
102 */
103 uint64_t led_display_base_addr;
104 /* DFA reference clock in hz (if applicable)*/
105 uint32_t dfa_ref_clock_hz;
106 /* configuration flags from bootloader */
107 uint32_t bootloader_config_flags;
108
109 /* Uart number used for console */
110 uint8_t console_uart_num;
111};
112
113/**
114 * This function returns the system/board information as obtained
115 * by the bootloader.
116 *
117 *
118 * Returns Pointer to the boot information structure
119 *
120 */
121
122extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
123
124/**
125 * This function is used in non-simple executive environments (such as
126 * Linux kernel, u-boot, etc.) to configure the minimal fields that
127 * are required to use simple executive files directly.
128 *
129 * Locking (if required) must be handled outside of this
130 * function
131 *
132 * @phy_mem_desc_ptr: Pointer to global physical memory descriptor
133 * (bootmem descriptor) @board_type: Octeon board
134 * type enumeration
135 *
136 * @board_rev_major:
137 * Board major revision
138 * @board_rev_minor:
139 * Board minor revision
140 * @cpu_clock_hz:
141 * CPU clock freqency in hertz
142 *
143 * Returns 0: Failure
144 * 1: success
145 */
146extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
147 uint16_t board_type,
148 uint8_t board_rev_major,
149 uint8_t board_rev_minor,
150 uint32_t cpu_clock_hz);
151
152#endif /* __CVMX_SYSINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
new file mode 100644
index 000000000000..03fddfa3e928
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -0,0 +1,505 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_H__
29#define __CVMX_H__
30
31#include <linux/kernel.h>
32#include <linux/string.h>
33
34#include "cvmx-asm.h"
35#include "cvmx-packet.h"
36#include "cvmx-sysinfo.h"
37
38#include "cvmx-ciu-defs.h"
39#include "cvmx-gpio-defs.h"
40#include "cvmx-iob-defs.h"
41#include "cvmx-ipd-defs.h"
42#include "cvmx-l2c-defs.h"
43#include "cvmx-l2d-defs.h"
44#include "cvmx-l2t-defs.h"
45#include "cvmx-led-defs.h"
46#include "cvmx-mio-defs.h"
47#include "cvmx-pow-defs.h"
48
49#include "cvmx-bootinfo.h"
50#include "cvmx-bootmem.h"
51#include "cvmx-l2c.h"
52
53#ifndef CVMX_ENABLE_DEBUG_PRINTS
54#define CVMX_ENABLE_DEBUG_PRINTS 1
55#endif
56
57#if CVMX_ENABLE_DEBUG_PRINTS
58#define cvmx_dprintf printk
59#else
60#define cvmx_dprintf(...) {}
61#endif
62
63#define CVMX_MAX_CORES (16)
64#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
65#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
66#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
67#define CAST64(v) ((long long)(long)(v))
68#define CASTPTR(type, v) ((type *)(long)(v))
69
70/*
71 * Returns processor ID, different Linux and simple exec versions
72 * provided in the cvmx-app-init*.c files.
73 */
74static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
75static inline uint32_t cvmx_get_proc_id(void)
76{
77 uint32_t id;
78 asm("mfc0 %0, $15,0" : "=r"(id));
79 return id;
80}
81
82/* turn the variable name into a string */
83#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
84#define CVMX_TMP_STR2(x) #x
85
86/**
87 * Builds a bit mask given the required size in bits.
88 *
89 * @bits: Number of bits in the mask
90 * Returns The mask
91 */ static inline uint64_t cvmx_build_mask(uint64_t bits)
92{
93 return ~((~0x0ull) << bits);
94}
95
96/**
97 * Builds a memory address for I/O based on the Major and Sub DID.
98 *
99 * @major_did: 5 bit major did
100 * @sub_did: 3 bit sub did
101 * Returns I/O base address
102 */
103static inline uint64_t cvmx_build_io_address(uint64_t major_did,
104 uint64_t sub_did)
105{
106 return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
107}
108
109/**
110 * Perform mask and shift to place the supplied value into
111 * the supplied bit rage.
112 *
113 * Example: cvmx_build_bits(39,24,value)
114 * <pre>
115 * 6 5 4 3 3 2 1
116 * 3 5 7 9 1 3 5 7 0
117 * +-------+-------+-------+-------+-------+-------+-------+------+
118 * 000000000000000000000000___________value000000000000000000000000
119 * </pre>
120 *
121 * @high_bit: Highest bit value can occupy (inclusive) 0-63
122 * @low_bit: Lowest bit value can occupy inclusive 0-high_bit
123 * @value: Value to use
124 * Returns Value masked and shifted
125 */
126static inline uint64_t cvmx_build_bits(uint64_t high_bit,
127 uint64_t low_bit, uint64_t value)
128{
129 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
130}
131
132enum cvmx_mips_space {
133 CVMX_MIPS_SPACE_XKSEG = 3LL,
134 CVMX_MIPS_SPACE_XKPHYS = 2LL,
135 CVMX_MIPS_SPACE_XSSEG = 1LL,
136 CVMX_MIPS_SPACE_XUSEG = 0LL
137};
138
139/* These macros for use when using 32 bit pointers. */
140#define CVMX_MIPS32_SPACE_KSEG0 1l
141#define CVMX_ADD_SEG32(segment, add) \
142 (((int32_t)segment << 31) | (int32_t)(add))
143
144#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
145
146/* These macros simplify the process of creating common IO addresses */
147#define CVMX_ADD_SEG(segment, add) \
148 ((((uint64_t)segment) << 62) | (add))
149#ifndef CVMX_ADD_IO_SEG
150#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
151#endif
152
153/**
154 * Convert a memory pointer (void*) into a hardware compatable
155 * memory address (uint64_t). Octeon hardware widgets don't
156 * understand logical addresses.
157 *
158 * @ptr: C style memory pointer
159 * Returns Hardware physical address
160 */
161static inline uint64_t cvmx_ptr_to_phys(void *ptr)
162{
163 if (sizeof(void *) == 8) {
164 /*
165 * We're running in 64 bit mode. Normally this means
166 * that we can use 40 bits of address space (the
167 * hardware limit). Unfortunately there is one case
168 * were we need to limit this to 30 bits, sign
169 * extended 32 bit. Although these are 64 bits wide,
170 * only 30 bits can be used.
171 */
172 if ((CAST64(ptr) >> 62) == 3)
173 return CAST64(ptr) & cvmx_build_mask(30);
174 else
175 return CAST64(ptr) & cvmx_build_mask(40);
176 } else {
177 return (long)(ptr) & 0x1fffffff;
178 }
179}
180
181/**
182 * Convert a hardware physical address (uint64_t) into a
183 * memory pointer (void *).
184 *
185 * @physical_address:
186 * Hardware physical address to memory
187 * Returns Pointer to memory
188 */
189static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
190{
191 if (sizeof(void *) == 8) {
192 /* Just set the top bit, avoiding any TLB uglyness */
193 return CASTPTR(void,
194 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
195 physical_address));
196 } else {
197 return CASTPTR(void,
198 CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
199 physical_address));
200 }
201}
202
203/* The following #if controls the definition of the macro
204 CVMX_BUILD_WRITE64. This macro is used to build a store operation to
205 a full 64bit address. With a 64bit ABI, this can be done with a simple
206 pointer access. 32bit ABIs require more complicated assembly */
207
208/* We have a full 64bit ABI. Writing to a 64bit address can be done with
209 a simple volatile pointer */
210#define CVMX_BUILD_WRITE64(TYPE, ST) \
211static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
212{ \
213 *CASTPTR(volatile TYPE##_t, addr) = val; \
214}
215
216
217/* The following #if controls the definition of the macro
218 CVMX_BUILD_READ64. This macro is used to build a load operation from
219 a full 64bit address. With a 64bit ABI, this can be done with a simple
220 pointer access. 32bit ABIs require more complicated assembly */
221
222/* We have a full 64bit ABI. Writing to a 64bit address can be done with
223 a simple volatile pointer */
224#define CVMX_BUILD_READ64(TYPE, LT) \
225static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
226{ \
227 return *CASTPTR(volatile TYPE##_t, addr); \
228}
229
230
231/* The following defines 8 functions for writing to a 64bit address. Each
232 takes two arguments, the address and the value to write.
233 cvmx_write64_int64 cvmx_write64_uint64
234 cvmx_write64_int32 cvmx_write64_uint32
235 cvmx_write64_int16 cvmx_write64_uint16
236 cvmx_write64_int8 cvmx_write64_uint8 */
237CVMX_BUILD_WRITE64(int64, "sd");
238CVMX_BUILD_WRITE64(int32, "sw");
239CVMX_BUILD_WRITE64(int16, "sh");
240CVMX_BUILD_WRITE64(int8, "sb");
241CVMX_BUILD_WRITE64(uint64, "sd");
242CVMX_BUILD_WRITE64(uint32, "sw");
243CVMX_BUILD_WRITE64(uint16, "sh");
244CVMX_BUILD_WRITE64(uint8, "sb");
245#define cvmx_write64 cvmx_write64_uint64
246
247/* The following defines 8 functions for reading from a 64bit address. Each
248 takes the address as the only argument
249 cvmx_read64_int64 cvmx_read64_uint64
250 cvmx_read64_int32 cvmx_read64_uint32
251 cvmx_read64_int16 cvmx_read64_uint16
252 cvmx_read64_int8 cvmx_read64_uint8 */
253CVMX_BUILD_READ64(int64, "ld");
254CVMX_BUILD_READ64(int32, "lw");
255CVMX_BUILD_READ64(int16, "lh");
256CVMX_BUILD_READ64(int8, "lb");
257CVMX_BUILD_READ64(uint64, "ld");
258CVMX_BUILD_READ64(uint32, "lw");
259CVMX_BUILD_READ64(uint16, "lhu");
260CVMX_BUILD_READ64(uint8, "lbu");
261#define cvmx_read64 cvmx_read64_uint64
262
263
264static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
265{
266 cvmx_write64(csr_addr, val);
267
268 /*
269 * Perform an immediate read after every write to an RSL
270 * register to force the write to complete. It doesn't matter
271 * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
272 * because it is fast and harmless.
273 */
274 if ((csr_addr >> 40) == (0x800118))
275 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
276}
277
278static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
279{
280 cvmx_write64(io_addr, val);
281
282}
283
284static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
285{
286 uint64_t val = cvmx_read64(csr_addr);
287 return val;
288}
289
290
291static inline void cvmx_send_single(uint64_t data)
292{
293 const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
294 cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
295}
296
297static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
298{
299 union {
300 uint64_t u64;
301 struct {
302 uint64_t scraddr:8;
303 uint64_t len:8;
304 uint64_t addr:48;
305 } s;
306 } addr;
307 addr.u64 = csr_addr;
308 addr.s.scraddr = scraddr >> 3;
309 addr.s.len = 1;
310 cvmx_send_single(addr.u64);
311}
312
313/* Return true if Octeon is CN38XX pass 1 */
314static inline int cvmx_octeon_is_pass1(void)
315{
316#if OCTEON_IS_COMMON_BINARY()
317 return 0; /* Pass 1 isn't supported for common binaries */
318#else
319/* Now that we know we're built for a specific model, only check CN38XX */
320#if OCTEON_IS_MODEL(OCTEON_CN38XX)
321 return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
322#else
323 return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
324#endif
325#endif
326}
327
328static inline unsigned int cvmx_get_core_num(void)
329{
330 unsigned int core_num;
331 CVMX_RDHWRNV(core_num, 0);
332 return core_num;
333}
334
335/**
336 * Returns the number of bits set in the provided value.
337 * Simple wrapper for POP instruction.
338 *
339 * @val: 32 bit value to count set bits in
340 *
341 * Returns Number of bits set
342 */
343static inline uint32_t cvmx_pop(uint32_t val)
344{
345 uint32_t pop;
346 CVMX_POP(pop, val);
347 return pop;
348}
349
350/**
351 * Returns the number of bits set in the provided value.
352 * Simple wrapper for DPOP instruction.
353 *
354 * @val: 64 bit value to count set bits in
355 *
356 * Returns Number of bits set
357 */
358static inline int cvmx_dpop(uint64_t val)
359{
360 int pop;
361 CVMX_DPOP(pop, val);
362 return pop;
363}
364
365/**
366 * Provide current cycle counter as a return value
367 *
368 * Returns current cycle counter
369 */
370
371static inline uint64_t cvmx_get_cycle(void)
372{
373 uint64_t cycle;
374 CVMX_RDHWR(cycle, 31);
375 return cycle;
376}
377
378/**
379 * Reads a chip global cycle counter. This counts CPU cycles since
380 * chip reset. The counter is 64 bit.
381 * This register does not exist on CN38XX pass 1 silicion
382 *
383 * Returns Global chip cycle count since chip reset.
384 */
385static inline uint64_t cvmx_get_cycle_global(void)
386{
387 if (cvmx_octeon_is_pass1())
388 return 0;
389 else
390 return cvmx_read64(CVMX_IPD_CLK_COUNT);
391}
392
393/**
394 * This macro spins on a field waiting for it to reach a value. It
395 * is common in code to need to wait for a specific field in a CSR
396 * to match a specific value. Conceptually this macro expands to:
397 *
398 * 1) read csr at "address" with a csr typedef of "type"
399 * 2) Check if ("type".s."field" "op" "value")
400 * 3) If #2 isn't true loop to #1 unless too much time has passed.
401 */
402#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
403 ( \
404{ \
405 int result; \
406 do { \
407 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
408 cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
409 type c; \
410 while (1) { \
411 c.u64 = cvmx_read_csr(address); \
412 if ((c.s.field) op(value)) { \
413 result = 0; \
414 break; \
415 } else if (cvmx_get_cycle() > done) { \
416 result = -1; \
417 break; \
418 } else \
419 cvmx_wait(100); \
420 } \
421 } while (0); \
422 result; \
423})
424
425/***************************************************************************/
426
427static inline void cvmx_reset_octeon(void)
428{
429 union cvmx_ciu_soft_rst ciu_soft_rst;
430 ciu_soft_rst.u64 = 0;
431 ciu_soft_rst.s.soft_rst = 1;
432 cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
433}
434
435/* Return the number of cores available in the chip */
436static inline uint32_t cvmx_octeon_num_cores(void)
437{
438 uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
439 return cvmx_pop(ciu_fuse);
440}
441
442/**
443 * Read a byte of fuse data
444 * @byte_addr: address to read
445 *
446 * Returns fuse value: 0 or 1
447 */
448static uint8_t cvmx_fuse_read_byte(int byte_addr)
449{
450 union cvmx_mio_fus_rcmd read_cmd;
451
452 read_cmd.u64 = 0;
453 read_cmd.s.addr = byte_addr;
454 read_cmd.s.pend = 1;
455 cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
456 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
457 && read_cmd.s.pend)
458 ;
459 return read_cmd.s.dat;
460}
461
462/**
463 * Read a single fuse bit
464 *
465 * @fuse: Fuse number (0-1024)
466 *
467 * Returns fuse value: 0 or 1
468 */
469static inline int cvmx_fuse_read(int fuse)
470{
471 return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1;
472}
473
474static inline int cvmx_octeon_model_CN36XX(void)
475{
476 return OCTEON_IS_MODEL(OCTEON_CN38XX)
477 && !cvmx_octeon_is_pass1()
478 && cvmx_fuse_read(264);
479}
480
481static inline int cvmx_octeon_zip_present(void)
482{
483 return octeon_has_feature(OCTEON_FEATURE_ZIP);
484}
485
486static inline int cvmx_octeon_dfa_present(void)
487{
488 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
489 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
490 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
491 return 0;
492 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
493 return 0;
494 else if (cvmx_octeon_is_pass1())
495 return 1;
496 else
497 return !cvmx_fuse_read(120);
498}
499
500static inline int cvmx_octeon_crypto_present(void)
501{
502 return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
503}
504
505#endif /* __CVMX_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
new file mode 100644
index 000000000000..04fac684069c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -0,0 +1,119 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * File defining checks for different Octeon features.
30 */
31
32#ifndef __OCTEON_FEATURE_H__
33#define __OCTEON_FEATURE_H__
34
35enum octeon_feature {
36 /*
37 * Octeon models in the CN5XXX family and higher support
38 * atomic add instructions to memory (saa/saad).
39 */
40 OCTEON_FEATURE_SAAD,
41 /* Does this Octeon support the ZIP offload engine? */
42 OCTEON_FEATURE_ZIP,
43 /* Does this Octeon support crypto acceleration using COP2? */
44 OCTEON_FEATURE_CRYPTO,
45 /* Does this Octeon support PCI express? */
46 OCTEON_FEATURE_PCIE,
47 /* Some Octeon models support internal memory for storing
48 * cryptographic keys */
49 OCTEON_FEATURE_KEY_MEMORY,
50 /* Octeon has a LED controller for banks of external LEDs */
51 OCTEON_FEATURE_LED_CONTROLLER,
52 /* Octeon has a trace buffer */
53 OCTEON_FEATURE_TRA,
54 /* Octeon has a management port */
55 OCTEON_FEATURE_MGMT_PORT,
56 /* Octeon has a raid unit */
57 OCTEON_FEATURE_RAID,
58 /* Octeon has a builtin USB */
59 OCTEON_FEATURE_USB,
60};
61
62static inline int cvmx_fuse_read(int fuse);
63
64/**
65 * Determine if the current Octeon supports a specific feature. These
66 * checks have been optimized to be fairly quick, but they should still
67 * be kept out of fast path code.
68 *
69 * @feature: Feature to check for. This should always be a constant so the
70 * compiler can remove the switch statement through optimization.
71 *
72 * Returns Non zero if the feature exists. Zero if the feature does not
73 * exist.
74 */
75static inline int octeon_has_feature(enum octeon_feature feature)
76{
77 switch (feature) {
78 case OCTEON_FEATURE_SAAD:
79 return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
80
81 case OCTEON_FEATURE_ZIP:
82 if (OCTEON_IS_MODEL(OCTEON_CN30XX)
83 || OCTEON_IS_MODEL(OCTEON_CN50XX)
84 || OCTEON_IS_MODEL(OCTEON_CN52XX))
85 return 0;
86 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
87 return 1;
88 else
89 return !cvmx_fuse_read(121);
90
91 case OCTEON_FEATURE_CRYPTO:
92 return !cvmx_fuse_read(90);
93
94 case OCTEON_FEATURE_PCIE:
95 return OCTEON_IS_MODEL(OCTEON_CN56XX)
96 || OCTEON_IS_MODEL(OCTEON_CN52XX);
97
98 case OCTEON_FEATURE_KEY_MEMORY:
99 case OCTEON_FEATURE_LED_CONTROLLER:
100 return OCTEON_IS_MODEL(OCTEON_CN38XX)
101 || OCTEON_IS_MODEL(OCTEON_CN58XX)
102 || OCTEON_IS_MODEL(OCTEON_CN56XX);
103 case OCTEON_FEATURE_TRA:
104 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
105 || OCTEON_IS_MODEL(OCTEON_CN50XX));
106 case OCTEON_FEATURE_MGMT_PORT:
107 return OCTEON_IS_MODEL(OCTEON_CN56XX)
108 || OCTEON_IS_MODEL(OCTEON_CN52XX);
109 case OCTEON_FEATURE_RAID:
110 return OCTEON_IS_MODEL(OCTEON_CN56XX)
111 || OCTEON_IS_MODEL(OCTEON_CN52XX);
112 case OCTEON_FEATURE_USB:
113 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
114 || OCTEON_IS_MODEL(OCTEON_CN58XX));
115 }
116 return 0;
117}
118
119#endif /* __OCTEON_FEATURE_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
new file mode 100644
index 000000000000..cf50336eca2e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -0,0 +1,321 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * File defining different Octeon model IDs and macros to
31 * compare them.
32 *
33 */
34
35#ifndef __OCTEON_MODEL_H__
36#define __OCTEON_MODEL_H__
37
38/* NOTE: These must match what is checked in common-config.mk */
39/* Defines to represent the different versions of Octeon. */
40
41/*
42 * IMPORTANT: When the default pass is updated for an Octeon Model,
43 * the corresponding change must also be made in the oct-sim script.
44 */
45
46/*
47 * The defines below should be used with the OCTEON_IS_MODEL() macro
48 * to determine what model of chip the software is running on. Models
49 * ending in 'XX' match multiple models (families), while specific
50 * models match only that model. If a pass (revision) is specified,
51 * then only that revision will be matched. Care should be taken when
52 * checking for both specific models and families that the specific
53 * models are checked for first. While these defines are similar to
54 * the processor ID, they are not intended to be used by anything
55 * other that the OCTEON_IS_MODEL framework, and the values are
56 * subject to change at anytime without notice.
57 *
58 * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*
59 * macros should be used outside of this file. All other macros are
60 * for internal use only, and may change without notice.
61 */
62
63/* Flag bits in top byte */
64/* Ignores revision in model checks */
65#define OM_IGNORE_REVISION 0x01000000
66/* Check submodels */
67#define OM_CHECK_SUBMODEL 0x02000000
68/* Match all models previous than the one specified */
69#define OM_MATCH_PREVIOUS_MODELS 0x04000000
70/* Ignores the minor revison on newer parts */
71#define OM_IGNORE_MINOR_REVISION 0x08000000
72#define OM_FLAG_MASK 0xff000000
73
74/*
75 * CN5XXX models with new revision encoding
76 */
77#define OCTEON_CN58XX_PASS1_0 0x000d0300
78#define OCTEON_CN58XX_PASS1_1 0x000d0301
79#define OCTEON_CN58XX_PASS1_2 0x000d0303
80#define OCTEON_CN58XX_PASS2_0 0x000d0308
81#define OCTEON_CN58XX_PASS2_1 0x000d0309
82#define OCTEON_CN58XX_PASS2_2 0x000d030a
83#define OCTEON_CN58XX_PASS2_3 0x000d030b
84
85#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
86#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \
87 | OM_IGNORE_MINOR_REVISION)
88#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
89 | OM_IGNORE_MINOR_REVISION)
90#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
91#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
92
93#define OCTEON_CN56XX_PASS1_0 0x000d0400
94#define OCTEON_CN56XX_PASS1_1 0x000d0401
95#define OCTEON_CN56XX_PASS2_0 0x000d0408
96#define OCTEON_CN56XX_PASS2_1 0x000d0409
97
98#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
99#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \
100 | OM_IGNORE_MINOR_REVISION)
101#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
102 | OM_IGNORE_MINOR_REVISION)
103#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
104#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
105
106#define OCTEON_CN57XX OCTEON_CN56XX
107#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1
108#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2
109
110#define OCTEON_CN55XX OCTEON_CN56XX
111#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1
112#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2
113
114#define OCTEON_CN54XX OCTEON_CN56XX
115#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1
116#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2
117
118#define OCTEON_CN50XX_PASS1_0 0x000d0600
119
120#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
121#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \
122 | OM_IGNORE_MINOR_REVISION)
123#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
124
125/*
126 * NOTE: Octeon CN5000F model is not identifiable using the
127 * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
128 */
129
130#define OCTEON_CN52XX_PASS1_0 0x000d0700
131#define OCTEON_CN52XX_PASS2_0 0x000d0708
132
133#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
134#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \
135 | OM_IGNORE_MINOR_REVISION)
136#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
137 | OM_IGNORE_MINOR_REVISION)
138#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
139#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
140
141/*
142 * CN3XXX models with old revision enconding
143 */
144#define OCTEON_CN38XX_PASS1 0x000d0000
145#define OCTEON_CN38XX_PASS2 0x000d0001
146#define OCTEON_CN38XX_PASS3 0x000d0003
147#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
148
149#define OCTEON_CN36XX OCTEON_CN38XX
150#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2
151#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3
152
153/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
154#define OCTEON_CN31XX_PASS1 0x000d0100
155#define OCTEON_CN31XX_PASS1_1 0x000d0102
156#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
157
158/*
159 * This model is only used for internal checks, it is not a valid
160 * model for the OCTEON_MODEL environment variable. This matches the
161 * CN3010 and CN3005 but NOT the CN3020.
162 */
163#define OCTEON_CN30XX_PASS1 0x000d0200
164#define OCTEON_CN30XX_PASS1_1 0x000d0202
165#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
166
167#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
168#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
169#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
170#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
171 | OM_CHECK_SUBMODEL)
172
173#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
174#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
175#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
176#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
177 | OM_CHECK_SUBMODEL)
178
179#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
180#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
181#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
182#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
183 | OM_CHECK_SUBMODEL)
184
185
186
187/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
188#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
189 | OM_MATCH_PREVIOUS_MODELS \
190 | OM_IGNORE_REVISION)
191
192/* The revision byte (low byte) has two different encodings.
193 * CN3XXX:
194 *
195 * bits
196 * <7:5>: reserved (0)
197 * <4>: alternate package
198 * <3:0>: revision
199 *
200 * CN5XXX:
201 *
202 * bits
203 * <7>: reserved (0)
204 * <6>: alternate package
205 * <5:3>: major revision
206 * <2:0>: minor revision
207 *
208 */
209
210/* Masks used for the various types of model/family/revision matching */
211#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
212#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
213#define OCTEON_38XX_MODEL_MASK 0x00ffff10
214#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \
215 | OCTEON_38XX_MODEL_MASK)
216
217/* CN5XXX and later use different layout of bits in the revision ID field */
218#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
219#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
220#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
221#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \
222 | OCTEON_58XX_MODEL_MASK)
223#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
224 & 0x00fffff8)
225
226#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
227
228/* NOTE: This is for internal (to this file) use only. */
229static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
230 uint32_t chip_model)
231{
232 uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
233
234 if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
235 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
236 __OCTEON_MATCH_MASK__(chip_model, arg_model,
237 OCTEON_38XX_MODEL_MASK))
238 return 1;
239 if (((arg_model & OM_FLAG_MASK) == 0) &&
240 __OCTEON_MATCH_MASK__(chip_model, arg_model,
241 OCTEON_38XX_FAMILY_REV_MASK))
242 return 1;
243 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
244 __OCTEON_MATCH_MASK__(chip_model, arg_model,
245 OCTEON_38XX_FAMILY_MASK))
246 return 1;
247 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
248 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
249 OCTEON_38XX_MODEL_REV_MASK))
250 return 1;
251 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
252 ((chip_model & OCTEON_38XX_MODEL_MASK) <
253 (arg_model & OCTEON_38XX_MODEL_MASK)))
254 return 1;
255 } else {
256 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
257 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
258 OCTEON_58XX_MODEL_MASK))
259 return 1;
260 if (((arg_model & OM_FLAG_MASK) == 0) &&
261 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
262 OCTEON_58XX_FAMILY_REV_MASK))
263 return 1;
264 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
265 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
266 OCTEON_58XX_MODEL_MINOR_REV_MASK))
267 return 1;
268 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
269 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
270 OCTEON_58XX_FAMILY_MASK))
271 return 1;
272 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
273 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
274 OCTEON_58XX_MODEL_REV_MASK))
275 return 1;
276 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
277 ((chip_model & OCTEON_58XX_MODEL_MASK) <
278 (arg_model & OCTEON_58XX_MODEL_MASK)))
279 return 1;
280 }
281 return 0;
282}
283
284/* forward declarations */
285static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
286static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
287
288/* NOTE: This for internal use only!!!!! */
289static inline int __octeon_is_model_runtime__(uint32_t model)
290{
291 uint32_t cpuid = cvmx_get_proc_id();
292
293 /*
294 * Check for special case of mismarked 3005 samples. We only
295 * need to check if the sub model isn't being ignored.
296 */
297 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
298 if (cpuid == OCTEON_CN3010_PASS1 \
299 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
300 cpuid |= 0x10;
301 }
302 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
303}
304
305/*
306 * The OCTEON_IS_MODEL macro should be used for all Octeon model
307 * checking done in a program. This should be kept runtime if at all
308 * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be
309 * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
310 * support is required.
311 */
312#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
313#define OCTEON_IS_COMMON_BINARY() 1
314#undef OCTEON_MODEL
315
316const char *octeon_model_get_string(uint32_t chip_id);
317const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
318
319#include "octeon-feature.h"
320
321#endif /* __OCTEON_MODEL_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
new file mode 100644
index 000000000000..edc676084cda
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -0,0 +1,248 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __ASM_OCTEON_OCTEON_H
9#define __ASM_OCTEON_OCTEON_H
10
11#include "cvmx.h"
12
13extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
14 uint64_t alignment,
15 uint64_t min_addr,
16 uint64_t max_addr,
17 int do_locking);
18extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
19 int do_locking);
20extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
21 uint64_t min_addr, uint64_t max_addr,
22 int do_locking);
23extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
24 char *name);
25extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
26 uint64_t max_addr, uint64_t align,
27 char *name);
28extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
29 char *name);
30extern int octeon_bootmem_free_named(char *name);
31extern void octeon_bootmem_lock(void);
32extern void octeon_bootmem_unlock(void);
33
34extern int octeon_is_simulation(void);
35extern int octeon_is_pci_host(void);
36extern int octeon_usb_is_ref_clk(void);
37extern uint64_t octeon_get_clock_rate(void);
38extern const char *octeon_board_type_string(void);
39extern const char *octeon_get_pci_interrupts(void);
40extern int octeon_get_southbridge_interrupt(void);
41extern int octeon_get_boot_coremask(void);
42extern int octeon_get_boot_num_arguments(void);
43extern const char *octeon_get_boot_argument(int arg);
44extern void octeon_hal_setup_reserved32(void);
45extern void octeon_user_io_init(void);
46struct octeon_cop2_state;
47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48extern void octeon_crypto_disable(struct octeon_cop2_state *state,
49 unsigned long flags);
50
51extern void octeon_init_cvmcount(void);
52
53#define OCTEON_ARGV_MAX_ARGS 64
54#define OCTOEN_SERIAL_LEN 20
55
56struct octeon_boot_descriptor {
57 /* Start of block referenced by assembly code - do not change! */
58 uint32_t desc_version;
59 uint32_t desc_size;
60 uint64_t stack_top;
61 uint64_t heap_base;
62 uint64_t heap_end;
63 /* Only used by bootloader */
64 uint64_t entry_point;
65 uint64_t desc_vaddr;
66 /* End of This block referenced by assembly code - do not change! */
67 uint32_t exception_base_addr;
68 uint32_t stack_size;
69 uint32_t heap_size;
70 /* Argc count for application. */
71 uint32_t argc;
72 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
73
74#define BOOT_FLAG_INIT_CORE (1 << 0)
75#define OCTEON_BL_FLAG_DEBUG (1 << 1)
76#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
77 /* If set, use uart1 for console */
78#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
79 /* If set, use PCI console */
80#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
81 /* Call exit on break on serial port */
82#define OCTEON_BL_FLAG_BREAK (1 << 5)
83
84 uint32_t flags;
85 uint32_t core_mask;
86 /* DRAM size in megabyes. */
87 uint32_t dram_size;
88 /* physical address of free memory descriptor block. */
89 uint32_t phy_mem_desc_addr;
90 /* used to pass flags from app to debugger. */
91 uint32_t debugger_flags_base_addr;
92 /* CPU clock speed, in hz. */
93 uint32_t eclock_hz;
94 /* DRAM clock speed, in hz. */
95 uint32_t dclock_hz;
96 /* SPI4 clock in hz. */
97 uint32_t spi_clock_hz;
98 uint16_t board_type;
99 uint8_t board_rev_major;
100 uint8_t board_rev_minor;
101 uint16_t chip_type;
102 uint8_t chip_rev_major;
103 uint8_t chip_rev_minor;
104 char board_serial_number[OCTOEN_SERIAL_LEN];
105 uint8_t mac_addr_base[6];
106 uint8_t mac_addr_count;
107 uint64_t cvmx_desc_vaddr;
108};
109
110union octeon_cvmemctl {
111 uint64_t u64;
112 struct {
113 /* RO 1 = BIST fail, 0 = BIST pass */
114 uint64_t tlbbist:1;
115 /* RO 1 = BIST fail, 0 = BIST pass */
116 uint64_t l1cbist:1;
117 /* RO 1 = BIST fail, 0 = BIST pass */
118 uint64_t l1dbist:1;
119 /* RO 1 = BIST fail, 0 = BIST pass */
120 uint64_t dcmbist:1;
121 /* RO 1 = BIST fail, 0 = BIST pass */
122 uint64_t ptgbist:1;
123 /* RO 1 = BIST fail, 0 = BIST pass */
124 uint64_t wbfbist:1;
125 /* Reserved */
126 uint64_t reserved:22;
127 /* R/W If set, marked write-buffer entries time out
128 * the same as as other entries; if clear, marked
129 * write-buffer entries use the maximum timeout. */
130 uint64_t dismarkwblongto:1;
131 /* R/W If set, a merged store does not clear the
132 * write-buffer entry timeout state. */
133 uint64_t dismrgclrwbto:1;
134 /* R/W Two bits that are the MSBs of the resultant
135 * CVMSEG LM word location for an IOBDMA. The other 8
136 * bits come from the SCRADDR field of the IOBDMA. */
137 uint64_t iobdmascrmsb:2;
138 /* R/W If set, SYNCWS and SYNCS only order marked
139 * stores; if clear, SYNCWS and SYNCS only order
140 * unmarked stores. SYNCWSMARKED has no effect when
141 * DISSYNCWS is set. */
142 uint64_t syncwsmarked:1;
143 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
144 * SYNC. */
145 uint64_t dissyncws:1;
146 /* R/W If set, no stall happens on write buffer
147 * full. */
148 uint64_t diswbfst:1;
149 /* R/W If set (and SX set), supervisor-level
150 * loads/stores can use XKPHYS addresses with
151 * VA<48>==0 */
152 uint64_t xkmemenas:1;
153 /* R/W If set (and UX set), user-level loads/stores
154 * can use XKPHYS addresses with VA<48>==0 */
155 uint64_t xkmemenau:1;
156 /* R/W If set (and SX set), supervisor-level
157 * loads/stores can use XKPHYS addresses with
158 * VA<48>==1 */
159 uint64_t xkioenas:1;
160 /* R/W If set (and UX set), user-level loads/stores
161 * can use XKPHYS addresses with VA<48>==1 */
162 uint64_t xkioenau:1;
163 /* R/W If set, all stores act as SYNCW (NOMERGE must
164 * be set when this is set) RW, reset to 0. */
165 uint64_t allsyncw:1;
166 /* R/W If set, no stores merge, and all stores reach
167 * the coherent bus in order. */
168 uint64_t nomerge:1;
169 /* R/W Selects the bit in the counter used for DID
170 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
171 * 214. Actual time-out is between 1x and 2x this
172 * interval. For example, with DIDTTO=3, expiration
173 * interval is between 16K and 32K. */
174 uint64_t didtto:2;
175 /* R/W If set, the (mem) CSR clock never turns off. */
176 uint64_t csrckalwys:1;
177 /* R/W If set, mclk never turns off. */
178 uint64_t mclkalwys:1;
179 /* R/W Selects the bit in the counter used for write
180 * buffer flush time-outs (WBFLT+11) is the bit
181 * position in an internal counter used to determine
182 * expiration. The write buffer expires between 1x and
183 * 2x this interval. For example, with WBFLT = 0, a
184 * write buffer expires between 2K and 4K cycles after
185 * the write buffer entry is allocated. */
186 uint64_t wbfltime:3;
187 /* R/W If set, do not put Istream in the L2 cache. */
188 uint64_t istrnol2:1;
189 /* R/W The write buffer threshold. */
190 uint64_t wbthresh:4;
191 /* Reserved */
192 uint64_t reserved2:2;
193 /* R/W If set, CVMSEG is available for loads/stores in
194 * kernel/debug mode. */
195 uint64_t cvmsegenak:1;
196 /* R/W If set, CVMSEG is available for loads/stores in
197 * supervisor mode. */
198 uint64_t cvmsegenas:1;
199 /* R/W If set, CVMSEG is available for loads/stores in
200 * user mode. */
201 uint64_t cvmsegenau:1;
202 /* R/W Size of local memory in cache blocks, 54 (6912
203 * bytes) is max legal value. */
204 uint64_t lmemsz:6;
205 } s;
206};
207
208struct octeon_cf_data {
209 unsigned long base_region_bias;
210 unsigned int base_region; /* The chip select region used by CF */
211 int is16bit; /* 0 - 8bit, !0 - 16bit */
212 int dma_engine; /* -1 for no DMA */
213};
214
215extern void octeon_write_lcd(const char *s);
216extern void octeon_check_cpu_bist(void);
217extern int octeon_get_boot_debug_flag(void);
218extern int octeon_get_boot_uart(void);
219
220struct uart_port;
221extern unsigned int octeon_serial_in(struct uart_port *, int);
222extern void octeon_serial_out(struct uart_port *, int, int);
223
224/**
225 * Write a 32bit value to the Octeon NPI register space
226 *
227 * @address: Address to write to
228 * @val: Value to write
229 */
230static inline void octeon_npi_write32(uint64_t address, uint32_t val)
231{
232 cvmx_write64_uint32(address ^ 4, val);
233 cvmx_read64_uint32(address ^ 4);
234}
235
236
237/**
238 * Read a 32bit value from the Octeon NPI register space
239 *
240 * @address: Address to read
241 * Returns The result
242 */
243static inline uint32_t octeon_npi_read32(uint64_t address)
244{
245 return cvmx_read64_uint32(address ^ 4);
246}
247
248#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 18ee58e39445..0f926aa0cb47 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -118,6 +118,60 @@ union mips_watch_reg_state {
118 struct mips3264_watch_reg_state mips3264; 118 struct mips3264_watch_reg_state mips3264;
119}; 119};
120 120
121#ifdef CONFIG_CPU_CAVIUM_OCTEON
122
123struct octeon_cop2_state {
124 /* DMFC2 rt, 0x0201 */
125 unsigned long cop2_crc_iv;
126 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
127 unsigned long cop2_crc_length;
128 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
129 unsigned long cop2_crc_poly;
130 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
131 unsigned long cop2_llm_dat[2];
132 /* DMFC2 rt, 0x0084 */
133 unsigned long cop2_3des_iv;
134 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
135 unsigned long cop2_3des_key[3];
136 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
137 unsigned long cop2_3des_result;
138 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
139 unsigned long cop2_aes_inp0;
140 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
141 unsigned long cop2_aes_iv[2];
142 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
143 * rt, 0x0107 */
144 unsigned long cop2_aes_key[4];
145 /* DMFC2 rt, 0x0110 */
146 unsigned long cop2_aes_keylen;
147 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
148 unsigned long cop2_aes_result[2];
149 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
150 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
151 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
152 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
153 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
154 unsigned long cop2_hsh_datw[15];
155 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
156 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
157 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
158 unsigned long cop2_hsh_ivw[8];
159 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
160 unsigned long cop2_gfm_mult[2];
161 /* DMFC2 rt, 0x025E - Pass2 */
162 unsigned long cop2_gfm_poly;
163 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
164 unsigned long cop2_gfm_result[2];
165};
166#define INIT_OCTEON_COP2 {0,}
167
168struct octeon_cvmseg_state {
169 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
170 [cpu_dcache_line_size() / sizeof(unsigned long)];
171};
172
173#endif
174
121typedef struct { 175typedef struct {
122 unsigned long seg; 176 unsigned long seg;
123} mm_segment_t; 177} mm_segment_t;
@@ -160,6 +214,10 @@ struct thread_struct {
160 unsigned long trap_no; 214 unsigned long trap_no;
161 unsigned long irix_trampoline; /* Wheee... */ 215 unsigned long irix_trampoline; /* Wheee... */
162 unsigned long irix_oldctx; 216 unsigned long irix_oldctx;
217#ifdef CONFIG_CPU_CAVIUM_OCTEON
218 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
219 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
220#endif
163 struct mips_abi *abi; 221 struct mips_abi *abi;
164}; 222};
165 223
@@ -171,6 +229,13 @@ struct thread_struct {
171#define FPAFF_INIT 229#define FPAFF_INIT
172#endif /* CONFIG_MIPS_MT_FPAFF */ 230#endif /* CONFIG_MIPS_MT_FPAFF */
173 231
232#ifdef CONFIG_CPU_CAVIUM_OCTEON
233#define OCTEON_INIT \
234 .cp2 = INIT_OCTEON_COP2,
235#else
236#define OCTEON_INIT
237#endif /* CONFIG_CPU_CAVIUM_OCTEON */
238
174#define INIT_THREAD { \ 239#define INIT_THREAD { \
175 /* \ 240 /* \
176 * Saved main processor registers \ 241 * Saved main processor registers \
@@ -221,6 +286,10 @@ struct thread_struct {
221 .trap_no = 0, \ 286 .trap_no = 0, \
222 .irix_trampoline = 0, \ 287 .irix_trampoline = 0, \
223 .irix_oldctx = 0, \ 288 .irix_oldctx = 0, \
289 /* \
290 * Cavium Octeon specifics (null if not Octeon) \
291 */ \
292 OCTEON_INIT \
224} 293}
225 294
226struct task_struct; 295struct task_struct;
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index c2c8bac43307..1f30d16d4669 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -48,6 +48,10 @@ struct pt_regs {
48#ifdef CONFIG_MIPS_MT_SMTC 48#ifdef CONFIG_MIPS_MT_SMTC
49 unsigned long cp0_tcstatus; 49 unsigned long cp0_tcstatus;
50#endif /* CONFIG_MIPS_MT_SMTC */ 50#endif /* CONFIG_MIPS_MT_SMTC */
51#ifdef CONFIG_CPU_CAVIUM_OCTEON
52 unsigned long long mpl[3]; /* MTM{0,1,2} */
53 unsigned long long mtp[3]; /* MTP{0,1,2} */
54#endif
51} __attribute__ ((aligned (8))); 55} __attribute__ ((aligned (8)));
52 56
53/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ 57/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 86557b5d1b3f..40e5ef1d4d26 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
37 37
38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ 38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
39#define SMP_CALL_FUNCTION 0x2 39#define SMP_CALL_FUNCTION 0x2
40/* Octeon - Tell another core to flush its icache */
41#define SMP_ICACHE_FLUSH 0x4
42
40 43
41extern void asmlinkage smp_bootstrap(void); 44extern void asmlinkage smp_bootstrap(void);
42 45
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 4c37c4e5f72e..db0fa7b5aeaf 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -194,6 +194,19 @@
194 LONG_S $31, PT_R31(sp) 194 LONG_S $31, PT_R31(sp)
195 ori $28, sp, _THREAD_MASK 195 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK 196 xori $28, _THREAD_MASK
197#ifdef CONFIG_CPU_CAVIUM_OCTEON
198 .set mips64
199 pref 0, 0($28) /* Prefetch the current pointer */
200 pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
201 /* The Octeon multiplier state is affected by general multiply
202 instructions. It must be saved before and kernel code might
203 corrupt it */
204 jal octeon_mult_save
205 LONG_L v1, 0($28) /* Load the current pointer */
206 /* Restore $31(ra) that was changed by the jal */
207 LONG_L ra, PT_R31(sp)
208 pref 0, 0(v1) /* Prefetch the current thread */
209#endif
197 .set pop 210 .set pop
198 .endm 211 .endm
199 212
@@ -324,6 +337,10 @@
324 DVPE 5 # dvpe a1 337 DVPE 5 # dvpe a1
325 jal mips_ihb 338 jal mips_ihb
326#endif /* CONFIG_MIPS_MT_SMTC */ 339#endif /* CONFIG_MIPS_MT_SMTC */
340#ifdef CONFIG_CPU_CAVIUM_OCTEON
341 /* Restore the Octeon multiplier state */
342 jal octeon_mult_restore
343#endif
327 mfc0 a0, CP0_STATUS 344 mfc0 a0, CP0_STATUS
328 ori a0, STATMASK 345 ori a0, STATMASK
329 xori a0, STATMASK 346 xori a0, STATMASK
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 9601ea950542..38a30d2ee959 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -50,27 +50,35 @@ extern int (*perf_irq)(void);
50/* 50/*
51 * Initialize the calling CPU's compare interrupt as clockevent device 51 * Initialize the calling CPU's compare interrupt as clockevent device
52 */ 52 */
53#ifdef CONFIG_CEVT_R4K 53#ifdef CONFIG_CEVT_R4K_LIB
54extern int mips_clockevent_init(void);
55extern unsigned int __weak get_c0_compare_int(void); 54extern unsigned int __weak get_c0_compare_int(void);
56#else 55extern int r4k_clockevent_init(void);
56#endif
57
57static inline int mips_clockevent_init(void) 58static inline int mips_clockevent_init(void)
58{ 59{
60#ifdef CONFIG_CEVT_R4K
61 return r4k_clockevent_init();
62#else
59 return -ENXIO; 63 return -ENXIO;
60}
61#endif 64#endif
65}
62 66
63/* 67/*
64 * Initialize the count register as a clocksource 68 * Initialize the count register as a clocksource
65 */ 69 */
66#ifdef CONFIG_CSRC_R4K 70#ifdef CONFIG_CSRC_R4K_LIB
67extern int init_mips_clocksource(void); 71extern int init_r4k_clocksource(void);
68#else 72#endif
73
69static inline int init_mips_clocksource(void) 74static inline int init_mips_clocksource(void)
70{ 75{
76#ifdef CONFIG_CSRC_R4K
77 return init_r4k_clocksource();
78#else
71 return 0; 79 return 0;
72}
73#endif 80#endif
81}
74 82
75extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); 83extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
76extern void clockevent_set_clock(struct clock_event_device *cd, 84extern void clockevent_set_clock(struct clock_event_device *cd,
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index b1372c27f136..e96122159928 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
9 time.o topology.o traps.o unaligned.o watch.o 9 time.o topology.o traps.o unaligned.o watch.o
10 10
11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
12obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 12obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o 13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o 14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
@@ -17,7 +17,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
20obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 20obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
23 23
@@ -43,6 +43,7 @@ obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
43obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 43obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
44obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o 44obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
45obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o 45obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
46obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
46 47
47obj-$(CONFIG_SMP) += smp.o 48obj-$(CONFIG_SMP) += smp.o
48obj-$(CONFIG_SMP_UP) += smp-up.o 49obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 72942226fcdd..c901c22d7ad0 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -64,6 +64,10 @@ void output_ptreg_defines(void)
64#ifdef CONFIG_MIPS_MT_SMTC 64#ifdef CONFIG_MIPS_MT_SMTC
65 OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); 65 OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus);
66#endif /* CONFIG_MIPS_MT_SMTC */ 66#endif /* CONFIG_MIPS_MT_SMTC */
67#ifdef CONFIG_CPU_CAVIUM_OCTEON
68 OFFSET(PT_MPL, pt_regs, mpl);
69 OFFSET(PT_MTP, pt_regs, mtp);
70#endif /* CONFIG_CPU_CAVIUM_OCTEON */
67 DEFINE(PT_SIZE, sizeof(struct pt_regs)); 71 DEFINE(PT_SIZE, sizeof(struct pt_regs));
68 BLANK(); 72 BLANK();
69} 73}
@@ -295,3 +299,30 @@ void output_irq_cpustat_t_defines(void)
295 DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t)); 299 DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t));
296 BLANK(); 300 BLANK();
297} 301}
302
303#ifdef CONFIG_CPU_CAVIUM_OCTEON
304void output_octeon_cop2_state_defines(void)
305{
306 COMMENT("Octeon specific octeon_cop2_state offsets.");
307 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
308 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
309 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
310 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
311 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
312 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
313 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
314 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
315 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
316 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
317 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
318 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
319 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
320 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
321 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
322 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
323 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
324 OFFSET(THREAD_CP2, task_struct, thread.cp2);
325 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
326 BLANK();
327}
328#endif
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 6b5df8bfab85..0176ed015c89 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -205,6 +205,39 @@ int __compute_return_epc(struct pt_regs *regs)
205 break; 205 break;
206 } 206 }
207 break; 207 break;
208#ifdef CONFIG_CPU_CAVIUM_OCTEON
209 case lwc2_op: /* This is bbit0 on Octeon */
210 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
211 == 0)
212 epc = epc + 4 + (insn.i_format.simmediate << 2);
213 else
214 epc += 8;
215 regs->cp0_epc = epc;
216 break;
217 case ldc2_op: /* This is bbit032 on Octeon */
218 if ((regs->regs[insn.i_format.rs] &
219 (1ull<<(insn.i_format.rt+32))) == 0)
220 epc = epc + 4 + (insn.i_format.simmediate << 2);
221 else
222 epc += 8;
223 regs->cp0_epc = epc;
224 break;
225 case swc2_op: /* This is bbit1 on Octeon */
226 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
227 epc = epc + 4 + (insn.i_format.simmediate << 2);
228 else
229 epc += 8;
230 regs->cp0_epc = epc;
231 break;
232 case sdc2_op: /* This is bbit132 on Octeon */
233 if (regs->regs[insn.i_format.rs] &
234 (1ull<<(insn.i_format.rt+32)))
235 epc = epc + 4 + (insn.i_format.simmediate << 2);
236 else
237 epc += 8;
238 regs->cp0_epc = epc;
239 break;
240#endif
208 } 241 }
209 242
210 return 0; 243 return 0;
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index e1ec83b68031..0015e442572b 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -160,7 +160,7 @@ int c0_compare_int_usable(void)
160 160
161#ifndef CONFIG_MIPS_MT_SMTC 161#ifndef CONFIG_MIPS_MT_SMTC
162 162
163int __cpuinit mips_clockevent_init(void) 163int __cpuinit r4k_clockevent_init(void)
164{ 164{
165 uint64_t mips_freq = mips_hpt_frequency; 165 uint64_t mips_freq = mips_hpt_frequency;
166 unsigned int cpu = smp_processor_id(); 166 unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c9207b5fd923..a7162a4484cf 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -96,6 +96,9 @@ int allow_au1k_wait;
96 96
97static void au1k_wait(void) 97static void au1k_wait(void)
98{ 98{
99 if (!allow_au1k_wait)
100 return;
101
99 /* using the wait instruction makes CP0 counter unusable */ 102 /* using the wait instruction makes CP0 counter unusable */
100 __asm__(" .set mips3 \n" 103 __asm__(" .set mips3 \n"
101 " cache 0x14, 0(%0) \n" 104 " cache 0x14, 0(%0) \n"
@@ -154,6 +157,7 @@ void __init check_wait(void)
154 case CPU_25KF: 157 case CPU_25KF:
155 case CPU_PR4450: 158 case CPU_PR4450:
156 case CPU_BCM3302: 159 case CPU_BCM3302:
160 case CPU_CAVIUM_OCTEON:
157 cpu_wait = r4k_wait; 161 cpu_wait = r4k_wait;
158 break; 162 break;
159 163
@@ -185,8 +189,7 @@ void __init check_wait(void)
185 case CPU_AU1200: 189 case CPU_AU1200:
186 case CPU_AU1210: 190 case CPU_AU1210:
187 case CPU_AU1250: 191 case CPU_AU1250:
188 if (allow_au1k_wait) 192 cpu_wait = au1k_wait;
189 cpu_wait = au1k_wait;
190 break; 193 break;
191 case CPU_20KC: 194 case CPU_20KC:
192 /* 195 /*
@@ -875,6 +878,27 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
875 } 878 }
876} 879}
877 880
881static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
882{
883 decode_configs(c);
884 switch (c->processor_id & 0xff00) {
885 case PRID_IMP_CAVIUM_CN38XX:
886 case PRID_IMP_CAVIUM_CN31XX:
887 case PRID_IMP_CAVIUM_CN30XX:
888 case PRID_IMP_CAVIUM_CN58XX:
889 case PRID_IMP_CAVIUM_CN56XX:
890 case PRID_IMP_CAVIUM_CN50XX:
891 case PRID_IMP_CAVIUM_CN52XX:
892 c->cputype = CPU_CAVIUM_OCTEON;
893 __cpu_name[cpu] = "Cavium Octeon";
894 break;
895 default:
896 printk(KERN_INFO "Unknown Octeon chip!\n");
897 c->cputype = CPU_UNKNOWN;
898 break;
899 }
900}
901
878const char *__cpu_name[NR_CPUS]; 902const char *__cpu_name[NR_CPUS];
879 903
880__cpuinit void cpu_probe(void) 904__cpuinit void cpu_probe(void)
@@ -909,6 +933,9 @@ __cpuinit void cpu_probe(void)
909 case PRID_COMP_NXP: 933 case PRID_COMP_NXP:
910 cpu_probe_nxp(c, cpu); 934 cpu_probe_nxp(c, cpu);
911 break; 935 break;
936 case PRID_COMP_CAVIUM:
937 cpu_probe_cavium(c, cpu);
938 break;
912 } 939 }
913 940
914 BUG_ON(!__cpu_name[cpu]); 941 BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 74fb74583b4e..f1a2893931ed 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = {
22 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 22 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
23}; 23};
24 24
25int __init init_mips_clocksource(void) 25int __init init_r4k_clocksource(void)
26{ 26{
27 if (!cpu_has_counter || !mips_hpt_frequency) 27 if (!cpu_has_counter || !mips_hpt_frequency)
28 return -ENXIO; 28 return -ENXIO;
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 757d48f0d80f..fb6f73148df2 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -385,10 +385,14 @@ NESTED(nmi_handler, PT_SIZE, sp)
385 .endm 385 .endm
386 386
387 .macro __build_clear_fpe 387 .macro __build_clear_fpe
388 .set push
389 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
390 .set mips1
388 cfc1 a1, fcr31 391 cfc1 a1, fcr31
389 li a2, ~(0x3f << 12) 392 li a2, ~(0x3f << 12)
390 and a2, a1 393 and a2, a1
391 ctc1 a2, fcr31 394 ctc1 a2, fcr31
395 .set pop
392 TRACE_IRQS_ON 396 TRACE_IRQS_ON
393 STI 397 STI
394 .endm 398 .endm
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 4b4007b3083a..a0ff2b66e22b 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -111,6 +111,7 @@ int show_interrupts(struct seq_file *p, void *v)
111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
112#endif 112#endif
113 seq_printf(p, " %14s", irq_desc[i].chip->name); 113 seq_printf(p, " %14s", irq_desc[i].chip->name);
114 seq_printf(p, "-%-8s", irq_desc[i].name);
114 seq_printf(p, " %s", action->name); 115 seq_printf(p, " %s", action->name);
115 116
116 for (action=action->next; action; action = action->next) 117 for (action=action->next; action; action = action->next)
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
new file mode 100644
index 000000000000..d52389672b06
--- /dev/null
+++ b/arch/mips/kernel/octeon_switch.S
@@ -0,0 +1,506 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * written by Carsten Langgaard, carstenl@mips.com
12 */
13#include <asm/asm.h>
14#include <asm/cachectl.h>
15#include <asm/fpregdef.h>
16#include <asm/mipsregs.h>
17#include <asm/asm-offsets.h>
18#include <asm/page.h>
19#include <asm/pgtable-bits.h>
20#include <asm/regdef.h>
21#include <asm/stackframe.h>
22#include <asm/thread_info.h>
23
24#include <asm/asmmacro.h>
25
26/*
27 * Offset to the current process status flags, the first 32 bytes of the
28 * stack are not used.
29 */
30#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
31
32/*
33 * task_struct *resume(task_struct *prev, task_struct *next,
34 * struct thread_info *next_ti)
35 */
36 .align 7
37 LEAF(resume)
38 .set arch=octeon
39#ifndef CONFIG_CPU_HAS_LLSC
40 sw zero, ll_bit
41#endif
42 mfc0 t1, CP0_STATUS
43 LONG_S t1, THREAD_STATUS(a0)
44 cpu_save_nonscratch a0
45 LONG_S ra, THREAD_REG31(a0)
46
47 /* check if we need to save COP2 registers */
48 PTR_L t2, TASK_THREAD_INFO(a0)
49 LONG_L t0, ST_OFF(t2)
50 bbit0 t0, 30, 1f
51
52 /* Disable COP2 in the stored process state */
53 li t1, ST0_CU2
54 xor t0, t1
55 LONG_S t0, ST_OFF(t2)
56
57 /* Enable COP2 so we can save it */
58 mfc0 t0, CP0_STATUS
59 or t0, t1
60 mtc0 t0, CP0_STATUS
61
62 /* Save COP2 */
63 daddu a0, THREAD_CP2
64 jal octeon_cop2_save
65 dsubu a0, THREAD_CP2
66
67 /* Disable COP2 now that we are done */
68 mfc0 t0, CP0_STATUS
69 li t1, ST0_CU2
70 xor t0, t1
71 mtc0 t0, CP0_STATUS
72
731:
74#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
75 /* Check if we need to store CVMSEG state */
76 mfc0 t0, $11,7 /* CvmMemCtl */
77 bbit0 t0, 6, 3f /* Is user access enabled? */
78
79 /* Store the CVMSEG state */
80 /* Extract the size of CVMSEG */
81 andi t0, 0x3f
82 /* Multiply * (cache line size/sizeof(long)/2) */
83 sll t0, 7-LONGLOG-1
84 li t1, -32768 /* Base address of CVMSEG */
85 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
86 synciobdma
872:
88 .set noreorder
89 LONG_L t8, 0(t1) /* Load from CVMSEG */
90 subu t0, 1 /* Decrement loop var */
91 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
92 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
93 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
94 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
95 bnez t0, 2b /* Loop until we've copied it all */
96 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
97 .set reorder
98
99 /* Disable access to CVMSEG */
100 mfc0 t0, $11,7 /* CvmMemCtl */
101 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
102 mtc0 t0, $11,7 /* CvmMemCtl */
103#endif
1043:
105 /*
106 * The order of restoring the registers takes care of the race
107 * updating $28, $29 and kernelsp without disabling ints.
108 */
109 move $28, a2
110 cpu_restore_nonscratch a1
111
112#if (_THREAD_SIZE - 32) < 0x8000
113 PTR_ADDIU t0, $28, _THREAD_SIZE - 32
114#else
115 PTR_LI t0, _THREAD_SIZE - 32
116 PTR_ADDU t0, $28
117#endif
118 set_saved_sp t0, t1, t2
119
120 mfc0 t1, CP0_STATUS /* Do we really need this? */
121 li a3, 0xff01
122 and t1, a3
123 LONG_L a2, THREAD_STATUS(a1)
124 nor a3, $0, a3
125 and a2, a3
126 or a2, t1
127 mtc0 a2, CP0_STATUS
128 move v0, a0
129 jr ra
130 END(resume)
131
132/*
133 * void octeon_cop2_save(struct octeon_cop2_state *a0)
134 */
135 .align 7
136 LEAF(octeon_cop2_save)
137
138 dmfc0 t9, $9,7 /* CvmCtl register. */
139
140 /* Save the COP2 CRC state */
141 dmfc2 t0, 0x0201
142 dmfc2 t1, 0x0202
143 dmfc2 t2, 0x0200
144 sd t0, OCTEON_CP2_CRC_IV(a0)
145 sd t1, OCTEON_CP2_CRC_LENGTH(a0)
146 sd t2, OCTEON_CP2_CRC_POLY(a0)
147 /* Skip next instructions if CvmCtl[NODFA_CP2] set */
148 bbit1 t9, 28, 1f
149
150 /* Save the LLM state */
151 dmfc2 t0, 0x0402
152 dmfc2 t1, 0x040A
153 sd t0, OCTEON_CP2_LLM_DAT(a0)
154 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
155
1561: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
157
158 /* Save the COP2 crypto state */
159 /* this part is mostly common to both pass 1 and later revisions */
160 dmfc2 t0, 0x0084
161 dmfc2 t1, 0x0080
162 dmfc2 t2, 0x0081
163 dmfc2 t3, 0x0082
164 sd t0, OCTEON_CP2_3DES_IV(a0)
165 dmfc2 t0, 0x0088
166 sd t1, OCTEON_CP2_3DES_KEY(a0)
167 dmfc2 t1, 0x0111 /* only necessary for pass 1 */
168 sd t2, OCTEON_CP2_3DES_KEY+8(a0)
169 dmfc2 t2, 0x0102
170 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
171 dmfc2 t3, 0x0103
172 sd t0, OCTEON_CP2_3DES_RESULT(a0)
173 dmfc2 t0, 0x0104
174 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
175 dmfc2 t1, 0x0105
176 sd t2, OCTEON_CP2_AES_IV(a0)
177 dmfc2 t2, 0x0106
178 sd t3, OCTEON_CP2_AES_IV+8(a0)
179 dmfc2 t3, 0x0107
180 sd t0, OCTEON_CP2_AES_KEY(a0)
181 dmfc2 t0, 0x0110
182 sd t1, OCTEON_CP2_AES_KEY+8(a0)
183 dmfc2 t1, 0x0100
184 sd t2, OCTEON_CP2_AES_KEY+16(a0)
185 dmfc2 t2, 0x0101
186 sd t3, OCTEON_CP2_AES_KEY+24(a0)
187 mfc0 t3, $15,0 /* Get the processor ID register */
188 sd t0, OCTEON_CP2_AES_KEYLEN(a0)
189 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
190 sd t1, OCTEON_CP2_AES_RESULT(a0)
191 sd t2, OCTEON_CP2_AES_RESULT+8(a0)
192 /* Skip to the Pass1 version of the remainder of the COP2 state */
193 beq t3, t0, 2f
194
195 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
196 dmfc2 t1, 0x0240
197 dmfc2 t2, 0x0241
198 dmfc2 t3, 0x0242
199 dmfc2 t0, 0x0243
200 sd t1, OCTEON_CP2_HSH_DATW(a0)
201 dmfc2 t1, 0x0244
202 sd t2, OCTEON_CP2_HSH_DATW+8(a0)
203 dmfc2 t2, 0x0245
204 sd t3, OCTEON_CP2_HSH_DATW+16(a0)
205 dmfc2 t3, 0x0246
206 sd t0, OCTEON_CP2_HSH_DATW+24(a0)
207 dmfc2 t0, 0x0247
208 sd t1, OCTEON_CP2_HSH_DATW+32(a0)
209 dmfc2 t1, 0x0248
210 sd t2, OCTEON_CP2_HSH_DATW+40(a0)
211 dmfc2 t2, 0x0249
212 sd t3, OCTEON_CP2_HSH_DATW+48(a0)
213 dmfc2 t3, 0x024A
214 sd t0, OCTEON_CP2_HSH_DATW+56(a0)
215 dmfc2 t0, 0x024B
216 sd t1, OCTEON_CP2_HSH_DATW+64(a0)
217 dmfc2 t1, 0x024C
218 sd t2, OCTEON_CP2_HSH_DATW+72(a0)
219 dmfc2 t2, 0x024D
220 sd t3, OCTEON_CP2_HSH_DATW+80(a0)
221 dmfc2 t3, 0x024E
222 sd t0, OCTEON_CP2_HSH_DATW+88(a0)
223 dmfc2 t0, 0x0250
224 sd t1, OCTEON_CP2_HSH_DATW+96(a0)
225 dmfc2 t1, 0x0251
226 sd t2, OCTEON_CP2_HSH_DATW+104(a0)
227 dmfc2 t2, 0x0252
228 sd t3, OCTEON_CP2_HSH_DATW+112(a0)
229 dmfc2 t3, 0x0253
230 sd t0, OCTEON_CP2_HSH_IVW(a0)
231 dmfc2 t0, 0x0254
232 sd t1, OCTEON_CP2_HSH_IVW+8(a0)
233 dmfc2 t1, 0x0255
234 sd t2, OCTEON_CP2_HSH_IVW+16(a0)
235 dmfc2 t2, 0x0256
236 sd t3, OCTEON_CP2_HSH_IVW+24(a0)
237 dmfc2 t3, 0x0257
238 sd t0, OCTEON_CP2_HSH_IVW+32(a0)
239 dmfc2 t0, 0x0258
240 sd t1, OCTEON_CP2_HSH_IVW+40(a0)
241 dmfc2 t1, 0x0259
242 sd t2, OCTEON_CP2_HSH_IVW+48(a0)
243 dmfc2 t2, 0x025E
244 sd t3, OCTEON_CP2_HSH_IVW+56(a0)
245 dmfc2 t3, 0x025A
246 sd t0, OCTEON_CP2_GFM_MULT(a0)
247 dmfc2 t0, 0x025B
248 sd t1, OCTEON_CP2_GFM_MULT+8(a0)
249 sd t2, OCTEON_CP2_GFM_POLY(a0)
250 sd t3, OCTEON_CP2_GFM_RESULT(a0)
251 sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
252 jr ra
253
2542: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
255 dmfc2 t3, 0x0040
256 dmfc2 t0, 0x0041
257 dmfc2 t1, 0x0042
258 dmfc2 t2, 0x0043
259 sd t3, OCTEON_CP2_HSH_DATW(a0)
260 dmfc2 t3, 0x0044
261 sd t0, OCTEON_CP2_HSH_DATW+8(a0)
262 dmfc2 t0, 0x0045
263 sd t1, OCTEON_CP2_HSH_DATW+16(a0)
264 dmfc2 t1, 0x0046
265 sd t2, OCTEON_CP2_HSH_DATW+24(a0)
266 dmfc2 t2, 0x0048
267 sd t3, OCTEON_CP2_HSH_DATW+32(a0)
268 dmfc2 t3, 0x0049
269 sd t0, OCTEON_CP2_HSH_DATW+40(a0)
270 dmfc2 t0, 0x004A
271 sd t1, OCTEON_CP2_HSH_DATW+48(a0)
272 sd t2, OCTEON_CP2_HSH_IVW(a0)
273 sd t3, OCTEON_CP2_HSH_IVW+8(a0)
274 sd t0, OCTEON_CP2_HSH_IVW+16(a0)
275
2763: /* pass 1 or CvmCtl[NOCRYPTO] set */
277 jr ra
278 END(octeon_cop2_save)
279
280/*
281 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
282 */
283 .align 7
284 .set push
285 .set noreorder
286 LEAF(octeon_cop2_restore)
287 /* First cache line was prefetched before the call */
288 pref 4, 128(a0)
289 dmfc0 t9, $9,7 /* CvmCtl register. */
290
291 pref 4, 256(a0)
292 ld t0, OCTEON_CP2_CRC_IV(a0)
293 pref 4, 384(a0)
294 ld t1, OCTEON_CP2_CRC_LENGTH(a0)
295 ld t2, OCTEON_CP2_CRC_POLY(a0)
296
297 /* Restore the COP2 CRC state */
298 dmtc2 t0, 0x0201
299 dmtc2 t1, 0x1202
300 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
301 dmtc2 t2, 0x4200
302
303 /* Restore the LLM state */
304 ld t0, OCTEON_CP2_LLM_DAT(a0)
305 ld t1, OCTEON_CP2_LLM_DAT+8(a0)
306 dmtc2 t0, 0x0402
307 dmtc2 t1, 0x040A
308
3092:
310 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
311 nop
312
313 /* Restore the COP2 crypto state common to pass 1 and pass 2 */
314 ld t0, OCTEON_CP2_3DES_IV(a0)
315 ld t1, OCTEON_CP2_3DES_KEY(a0)
316 ld t2, OCTEON_CP2_3DES_KEY+8(a0)
317 dmtc2 t0, 0x0084
318 ld t0, OCTEON_CP2_3DES_KEY+16(a0)
319 dmtc2 t1, 0x0080
320 ld t1, OCTEON_CP2_3DES_RESULT(a0)
321 dmtc2 t2, 0x0081
322 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
323 dmtc2 t0, 0x0082
324 ld t0, OCTEON_CP2_AES_IV(a0)
325 dmtc2 t1, 0x0098
326 ld t1, OCTEON_CP2_AES_IV+8(a0)
327 dmtc2 t2, 0x010A /* only really needed for pass 1 */
328 ld t2, OCTEON_CP2_AES_KEY(a0)
329 dmtc2 t0, 0x0102
330 ld t0, OCTEON_CP2_AES_KEY+8(a0)
331 dmtc2 t1, 0x0103
332 ld t1, OCTEON_CP2_AES_KEY+16(a0)
333 dmtc2 t2, 0x0104
334 ld t2, OCTEON_CP2_AES_KEY+24(a0)
335 dmtc2 t0, 0x0105
336 ld t0, OCTEON_CP2_AES_KEYLEN(a0)
337 dmtc2 t1, 0x0106
338 ld t1, OCTEON_CP2_AES_RESULT(a0)
339 dmtc2 t2, 0x0107
340 ld t2, OCTEON_CP2_AES_RESULT+8(a0)
341 mfc0 t3, $15,0 /* Get the processor ID register */
342 dmtc2 t0, 0x0110
343 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
344 dmtc2 t1, 0x0100
345 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
346 dmtc2 t2, 0x0101
347
348 /* this code is specific for pass 1 */
349 ld t0, OCTEON_CP2_HSH_DATW(a0)
350 ld t1, OCTEON_CP2_HSH_DATW+8(a0)
351 ld t2, OCTEON_CP2_HSH_DATW+16(a0)
352 dmtc2 t0, 0x0040
353 ld t0, OCTEON_CP2_HSH_DATW+24(a0)
354 dmtc2 t1, 0x0041
355 ld t1, OCTEON_CP2_HSH_DATW+32(a0)
356 dmtc2 t2, 0x0042
357 ld t2, OCTEON_CP2_HSH_DATW+40(a0)
358 dmtc2 t0, 0x0043
359 ld t0, OCTEON_CP2_HSH_DATW+48(a0)
360 dmtc2 t1, 0x0044
361 ld t1, OCTEON_CP2_HSH_IVW(a0)
362 dmtc2 t2, 0x0045
363 ld t2, OCTEON_CP2_HSH_IVW+8(a0)
364 dmtc2 t0, 0x0046
365 ld t0, OCTEON_CP2_HSH_IVW+16(a0)
366 dmtc2 t1, 0x0048
367 dmtc2 t2, 0x0049
368 b done_restore /* unconditional branch */
369 dmtc2 t0, 0x004A
370
3713: /* this is post-pass1 code */
372 ld t2, OCTEON_CP2_HSH_DATW(a0)
373 ld t0, OCTEON_CP2_HSH_DATW+8(a0)
374 ld t1, OCTEON_CP2_HSH_DATW+16(a0)
375 dmtc2 t2, 0x0240
376 ld t2, OCTEON_CP2_HSH_DATW+24(a0)
377 dmtc2 t0, 0x0241
378 ld t0, OCTEON_CP2_HSH_DATW+32(a0)
379 dmtc2 t1, 0x0242
380 ld t1, OCTEON_CP2_HSH_DATW+40(a0)
381 dmtc2 t2, 0x0243
382 ld t2, OCTEON_CP2_HSH_DATW+48(a0)
383 dmtc2 t0, 0x0244
384 ld t0, OCTEON_CP2_HSH_DATW+56(a0)
385 dmtc2 t1, 0x0245
386 ld t1, OCTEON_CP2_HSH_DATW+64(a0)
387 dmtc2 t2, 0x0246
388 ld t2, OCTEON_CP2_HSH_DATW+72(a0)
389 dmtc2 t0, 0x0247
390 ld t0, OCTEON_CP2_HSH_DATW+80(a0)
391 dmtc2 t1, 0x0248
392 ld t1, OCTEON_CP2_HSH_DATW+88(a0)
393 dmtc2 t2, 0x0249
394 ld t2, OCTEON_CP2_HSH_DATW+96(a0)
395 dmtc2 t0, 0x024A
396 ld t0, OCTEON_CP2_HSH_DATW+104(a0)
397 dmtc2 t1, 0x024B
398 ld t1, OCTEON_CP2_HSH_DATW+112(a0)
399 dmtc2 t2, 0x024C
400 ld t2, OCTEON_CP2_HSH_IVW(a0)
401 dmtc2 t0, 0x024D
402 ld t0, OCTEON_CP2_HSH_IVW+8(a0)
403 dmtc2 t1, 0x024E
404 ld t1, OCTEON_CP2_HSH_IVW+16(a0)
405 dmtc2 t2, 0x0250
406 ld t2, OCTEON_CP2_HSH_IVW+24(a0)
407 dmtc2 t0, 0x0251
408 ld t0, OCTEON_CP2_HSH_IVW+32(a0)
409 dmtc2 t1, 0x0252
410 ld t1, OCTEON_CP2_HSH_IVW+40(a0)
411 dmtc2 t2, 0x0253
412 ld t2, OCTEON_CP2_HSH_IVW+48(a0)
413 dmtc2 t0, 0x0254
414 ld t0, OCTEON_CP2_HSH_IVW+56(a0)
415 dmtc2 t1, 0x0255
416 ld t1, OCTEON_CP2_GFM_MULT(a0)
417 dmtc2 t2, 0x0256
418 ld t2, OCTEON_CP2_GFM_MULT+8(a0)
419 dmtc2 t0, 0x0257
420 ld t0, OCTEON_CP2_GFM_POLY(a0)
421 dmtc2 t1, 0x0258
422 ld t1, OCTEON_CP2_GFM_RESULT(a0)
423 dmtc2 t2, 0x0259
424 ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
425 dmtc2 t0, 0x025E
426 dmtc2 t1, 0x025A
427 dmtc2 t2, 0x025B
428
429done_restore:
430 jr ra
431 nop
432 END(octeon_cop2_restore)
433 .set pop
434
435/*
436 * void octeon_mult_save()
437 * sp is assumed to point to a struct pt_regs
438 *
439 * NOTE: This is called in SAVE_SOME in stackframe.h. It can only
440 * safely modify k0 and k1.
441 */
442 .align 7
443 .set push
444 .set noreorder
445 LEAF(octeon_mult_save)
446 dmfc0 k0, $9,7 /* CvmCtl register. */
447 bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */
448 nop
449
450 /* Save the multiplier state */
451 v3mulu k0, $0, $0
452 v3mulu k1, $0, $0
453 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
454 v3mulu k0, $0, $0
455 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
456 ori k1, $0, 1
457 v3mulu k1, k1, $0
458 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
459 v3mulu k0, $0, $0
460 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
461 v3mulu k1, $0, $0
462 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
463 jr ra
464 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
465
4661: /* Resume here if CvmCtl[NOMUL] */
467 jr ra
468 END(octeon_mult_save)
469 .set pop
470
471/*
472 * void octeon_mult_restore()
473 * sp is assumed to point to a struct pt_regs
474 *
475 * NOTE: This is called in RESTORE_SOME in stackframe.h.
476 */
477 .align 7
478 .set push
479 .set noreorder
480 LEAF(octeon_mult_restore)
481 dmfc0 k1, $9,7 /* CvmCtl register. */
482 ld v0, PT_MPL(sp) /* MPL0 */
483 ld v1, PT_MPL+8(sp) /* MPL1 */
484 ld k0, PT_MPL+16(sp) /* MPL2 */
485 bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */
486 /* Normally falls through, so no time wasted here */
487 nop
488
489 /* Restore the multiplier state */
490 ld k1, PT_MTP+16(sp) /* P2 */
491 MTM0 v0 /* MPL0 */
492 ld v0, PT_MTP+8(sp) /* P1 */
493 MTM1 v1 /* MPL1 */
494 ld v1, PT_MTP(sp) /* P0 */
495 MTM2 k0 /* MPL2 */
496 MTP2 k1 /* P2 */
497 MTP1 v0 /* P1 */
498 jr ra
499 MTP0 v1 /* P0 */
500
5011: /* Resume here if CvmCtl[NOMUL] */
502 jr ra
503 nop
504 END(octeon_mult_restore)
505 .set pop
506
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 1ca34104e593..c4f9ac17474a 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -49,19 +49,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
49 int ret; 49 int ret;
50 50
51 switch (request) { 51 switch (request) {
52 /* when I and D space are separate, these will need to be fixed. */
53 case PTRACE_PEEKTEXT: /* read word at location addr. */
54 case PTRACE_PEEKDATA: {
55 unsigned int tmp;
56 int copied;
57
58 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
59 ret = -EIO;
60 if (copied != sizeof(tmp))
61 break;
62 ret = put_user(tmp, (unsigned int __user *) (unsigned long) data);
63 break;
64 }
65 52
66 /* 53 /*
67 * Read 4 bytes of the other process' storage 54 * Read 4 bytes of the other process' storage
@@ -208,16 +195,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
208 break; 195 break;
209 } 196 }
210 197
211 /* when I and D space are separate, this will have to be fixed. */
212 case PTRACE_POKETEXT: /* write the word at location addr. */
213 case PTRACE_POKEDATA:
214 ret = 0;
215 if (access_process_vm(child, addr, &data, sizeof(data), 1)
216 == sizeof(data))
217 break;
218 ret = -EIO;
219 break;
220
221 /* 198 /*
222 * Write 4 bytes into the other process' storage 199 * Write 4 bytes into the other process' storage
223 * data is the 4 bytes that the user wants written 200 * data is the 4 bytes that the user wants written
@@ -332,50 +309,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
332 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data); 309 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
333 break; 310 break;
334 311
335 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
336 case PTRACE_CONT: { /* restart after signal. */
337 ret = -EIO;
338 if (!valid_signal(data))
339 break;
340 if (request == PTRACE_SYSCALL) {
341 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
342 }
343 else {
344 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
345 }
346 child->exit_code = data;
347 wake_up_process(child);
348 ret = 0;
349 break;
350 }
351
352 /*
353 * make the child exit. Best I can do is send it a sigkill.
354 * perhaps it should be put in the status that it wants to
355 * exit.
356 */
357 case PTRACE_KILL:
358 ret = 0;
359 if (child->exit_state == EXIT_ZOMBIE) /* already dead */
360 break;
361 child->exit_code = SIGKILL;
362 wake_up_process(child);
363 break;
364
365 case PTRACE_GET_THREAD_AREA: 312 case PTRACE_GET_THREAD_AREA:
366 ret = put_user(task_thread_info(child)->tp_value, 313 ret = put_user(task_thread_info(child)->tp_value,
367 (unsigned int __user *) (unsigned long) data); 314 (unsigned int __user *) (unsigned long) data);
368 break; 315 break;
369 316
370 case PTRACE_DETACH: /* detach a process that was attached. */
371 ret = ptrace_detach(child, data);
372 break;
373
374 case PTRACE_GETEVENTMSG:
375 ret = put_user(child->ptrace_message,
376 (unsigned int __user *) (unsigned long) data);
377 break;
378
379 case PTRACE_GET_THREAD_AREA_3264: 317 case PTRACE_GET_THREAD_AREA_3264:
380 ret = put_user(task_thread_info(child)->tp_value, 318 ret = put_user(task_thread_info(child)->tp_value,
381 (unsigned long __user *) (unsigned long) data); 319 (unsigned long __user *) (unsigned long) data);
@@ -392,7 +330,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
392 break; 330 break;
393 331
394 default: 332 default:
395 ret = ptrace_request(child, request, addr, data); 333 ret = compat_ptrace_request(child, request, addr, data);
396 break; 334 break;
397 } 335 }
398out: 336out:
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 353056110f2b..f6083c6bfaa4 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -47,6 +47,7 @@
47#include <asm/mmu_context.h> 47#include <asm/mmu_context.h>
48#include <asm/types.h> 48#include <asm/types.h>
49#include <asm/stacktrace.h> 49#include <asm/stacktrace.h>
50#include <asm/irq.h>
50 51
51extern void check_wait(void); 52extern void check_wait(void);
52extern asmlinkage void r4k_wait(void); 53extern asmlinkage void r4k_wait(void);
@@ -78,6 +79,10 @@ extern asmlinkage void handle_reserved(void);
78extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 79extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
79 struct mips_fpu_struct *ctx, int has_fpu); 80 struct mips_fpu_struct *ctx, int has_fpu);
80 81
82#ifdef CONFIG_CPU_CAVIUM_OCTEON
83extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
84#endif
85
81void (*board_be_init)(void); 86void (*board_be_init)(void);
82int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 87int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
83void (*board_nmi_handler_setup)(void); 88void (*board_nmi_handler_setup)(void);
@@ -860,6 +865,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
860 unsigned int opcode; 865 unsigned int opcode;
861 unsigned int cpid; 866 unsigned int cpid;
862 int status; 867 int status;
868 unsigned long __maybe_unused flags;
863 869
864 die_if_kernel("do_cpu invoked from kernel context!", regs); 870 die_if_kernel("do_cpu invoked from kernel context!", regs);
865 871
@@ -915,6 +921,17 @@ asmlinkage void do_cpu(struct pt_regs *regs)
915 return; 921 return;
916 922
917 case 2: 923 case 2:
924#ifdef CONFIG_CPU_CAVIUM_OCTEON
925 prefetch(&current->thread.cp2);
926 local_irq_save(flags);
927 KSTK_STATUS(current) |= ST0_CU2;
928 status = read_c0_status();
929 write_c0_status(status | ST0_CU2);
930 octeon_cop2_restore(&(current->thread.cp2));
931 write_c0_status(status & ~ST0_CU2);
932 local_irq_restore(flags);
933 return;
934#endif
918 case 3: 935 case 3:
919 break; 936 break;
920 } 937 }
@@ -1488,6 +1505,10 @@ void __cpuinit per_cpu_trap_init(void)
1488 write_c0_hwrena(enable); 1505 write_c0_hwrena(enable);
1489 } 1506 }
1490 1507
1508#ifdef CONFIG_CPU_CAVIUM_OCTEON
1509 write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
1510#endif
1511
1491#ifdef CONFIG_MIPS_MT_SMTC 1512#ifdef CONFIG_MIPS_MT_SMTC
1492 if (!secondaryTC) { 1513 if (!secondaryTC) {
1493#endif /* CONFIG_MIPS_MT_SMTC */ 1514#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index dbcf6511b74e..c13c7ad2cdae 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o
27obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o 27obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
28obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o 28obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o 29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
30 31
31# libgcc-style stuff needed in the kernel 32# libgcc-style stuff needed in the kernel
32obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o 33obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 95ba32b5b720..d7ec95522292 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o 27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o 28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
29obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o 29obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
30 31
31obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 32obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
32obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 33obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
new file mode 100644
index 000000000000..44d01a0a8490
--- /dev/null
+++ b/arch/mips/mm/c-octeon.c
@@ -0,0 +1,307 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2007 Cavium Networks
7 */
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/mm.h>
12#include <linux/bitops.h>
13#include <linux/cpu.h>
14#include <linux/io.h>
15
16#include <asm/bcache.h>
17#include <asm/bootinfo.h>
18#include <asm/cacheops.h>
19#include <asm/cpu-features.h>
20#include <asm/page.h>
21#include <asm/pgtable.h>
22#include <asm/r4kcache.h>
23#include <asm/system.h>
24#include <asm/mmu_context.h>
25#include <asm/war.h>
26
27#include <asm/octeon/octeon.h>
28
29unsigned long long cache_err_dcache[NR_CPUS];
30
31/**
32 * Octeon automatically flushes the dcache on tlb changes, so
33 * from Linux's viewpoint it acts much like a physically
34 * tagged cache. No flushing is needed
35 *
36 */
37static void octeon_flush_data_cache_page(unsigned long addr)
38{
39 /* Nothing to do */
40}
41
42static inline void octeon_local_flush_icache(void)
43{
44 asm volatile ("synci 0($0)");
45}
46
47/*
48 * Flush local I-cache for the specified range.
49 */
50static void local_octeon_flush_icache_range(unsigned long start,
51 unsigned long end)
52{
53 octeon_local_flush_icache();
54}
55
56/**
57 * Flush caches as necessary for all cores affected by a
58 * vma. If no vma is supplied, all cores are flushed.
59 *
60 * @vma: VMA to flush or NULL to flush all icaches.
61 */
62static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
63{
64 extern void octeon_send_ipi_single(int cpu, unsigned int action);
65#ifdef CONFIG_SMP
66 int cpu;
67 cpumask_t mask;
68#endif
69
70 mb();
71 octeon_local_flush_icache();
72#ifdef CONFIG_SMP
73 preempt_disable();
74 cpu = smp_processor_id();
75
76 /*
77 * If we have a vma structure, we only need to worry about
78 * cores it has been used on
79 */
80 if (vma)
81 mask = vma->vm_mm->cpu_vm_mask;
82 else
83 mask = cpu_online_map;
84 cpu_clear(cpu, mask);
85 for_each_cpu_mask(cpu, mask)
86 octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
87
88 preempt_enable();
89#endif
90}
91
92
93/**
94 * Called to flush the icache on all cores
95 */
96static void octeon_flush_icache_all(void)
97{
98 octeon_flush_icache_all_cores(NULL);
99}
100
101
102/**
103 * Called to flush all memory associated with a memory
104 * context.
105 *
106 * @mm: Memory context to flush
107 */
108static void octeon_flush_cache_mm(struct mm_struct *mm)
109{
110 /*
111 * According to the R4K version of this file, CPUs without
112 * dcache aliases don't need to do anything here
113 */
114}
115
116
117/**
118 * Flush a range of kernel addresses out of the icache
119 *
120 */
121static void octeon_flush_icache_range(unsigned long start, unsigned long end)
122{
123 octeon_flush_icache_all_cores(NULL);
124}
125
126
127/**
128 * Flush the icache for a trampoline. These are used for interrupt
129 * and exception hooking.
130 *
131 * @addr: Address to flush
132 */
133static void octeon_flush_cache_sigtramp(unsigned long addr)
134{
135 struct vm_area_struct *vma;
136
137 vma = find_vma(current->mm, addr);
138 octeon_flush_icache_all_cores(vma);
139}
140
141
142/**
143 * Flush a range out of a vma
144 *
145 * @vma: VMA to flush
146 * @start:
147 * @end:
148 */
149static void octeon_flush_cache_range(struct vm_area_struct *vma,
150 unsigned long start, unsigned long end)
151{
152 if (vma->vm_flags & VM_EXEC)
153 octeon_flush_icache_all_cores(vma);
154}
155
156
157/**
158 * Flush a specific page of a vma
159 *
160 * @vma: VMA to flush page for
161 * @page: Page to flush
162 * @pfn:
163 */
164static void octeon_flush_cache_page(struct vm_area_struct *vma,
165 unsigned long page, unsigned long pfn)
166{
167 if (vma->vm_flags & VM_EXEC)
168 octeon_flush_icache_all_cores(vma);
169}
170
171
172/**
173 * Probe Octeon's caches
174 *
175 */
176static void __devinit probe_octeon(void)
177{
178 unsigned long icache_size;
179 unsigned long dcache_size;
180 unsigned int config1;
181 struct cpuinfo_mips *c = &current_cpu_data;
182
183 switch (c->cputype) {
184 case CPU_CAVIUM_OCTEON:
185 config1 = read_c0_config1();
186 c->icache.linesz = 2 << ((config1 >> 19) & 7);
187 c->icache.sets = 64 << ((config1 >> 22) & 7);
188 c->icache.ways = 1 + ((config1 >> 16) & 7);
189 c->icache.flags |= MIPS_CACHE_VTAG;
190 icache_size =
191 c->icache.sets * c->icache.ways * c->icache.linesz;
192 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
193 c->dcache.linesz = 128;
194 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
195 c->dcache.sets = 1; /* CN3XXX has one Dcache set */
196 else
197 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
198 c->dcache.ways = 64;
199 dcache_size =
200 c->dcache.sets * c->dcache.ways * c->dcache.linesz;
201 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
202 c->options |= MIPS_CPU_PREFETCH;
203 break;
204
205 default:
206 panic("Unsupported Cavium Networks CPU type\n");
207 break;
208 }
209
210 /* compute a couple of other cache variables */
211 c->icache.waysize = icache_size / c->icache.ways;
212 c->dcache.waysize = dcache_size / c->dcache.ways;
213
214 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
215 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
216
217 if (smp_processor_id() == 0) {
218 pr_notice("Primary instruction cache %ldkB, %s, %d way, "
219 "%d sets, linesize %d bytes.\n",
220 icache_size >> 10,
221 cpu_has_vtag_icache ?
222 "virtually tagged" : "physically tagged",
223 c->icache.ways, c->icache.sets, c->icache.linesz);
224
225 pr_notice("Primary data cache %ldkB, %d-way, %d sets, "
226 "linesize %d bytes.\n",
227 dcache_size >> 10, c->dcache.ways,
228 c->dcache.sets, c->dcache.linesz);
229 }
230}
231
232
233/**
234 * Setup the Octeon cache flush routines
235 *
236 */
237void __devinit octeon_cache_init(void)
238{
239 extern unsigned long ebase;
240 extern char except_vec2_octeon;
241
242 memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80);
243 octeon_flush_cache_sigtramp(ebase + 0x100);
244
245 probe_octeon();
246
247 shm_align_mask = PAGE_SIZE - 1;
248
249 flush_cache_all = octeon_flush_icache_all;
250 __flush_cache_all = octeon_flush_icache_all;
251 flush_cache_mm = octeon_flush_cache_mm;
252 flush_cache_page = octeon_flush_cache_page;
253 flush_cache_range = octeon_flush_cache_range;
254 flush_cache_sigtramp = octeon_flush_cache_sigtramp;
255 flush_icache_all = octeon_flush_icache_all;
256 flush_data_cache_page = octeon_flush_data_cache_page;
257 flush_icache_range = octeon_flush_icache_range;
258 local_flush_icache_range = local_octeon_flush_icache_range;
259
260 build_clear_page();
261 build_copy_page();
262}
263
264/**
265 * Handle a cache error exception
266 */
267
268static void cache_parity_error_octeon(int non_recoverable)
269{
270 unsigned long coreid = cvmx_get_core_num();
271 uint64_t icache_err = read_octeon_c0_icacheerr();
272
273 pr_err("Cache error exception:\n");
274 pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
275 if (icache_err & 1) {
276 pr_err("CacheErr (Icache) == %llx\n",
277 (unsigned long long)icache_err);
278 write_octeon_c0_icacheerr(0);
279 }
280 if (cache_err_dcache[coreid] & 1) {
281 pr_err("CacheErr (Dcache) == %llx\n",
282 (unsigned long long)cache_err_dcache[coreid]);
283 cache_err_dcache[coreid] = 0;
284 }
285
286 if (non_recoverable)
287 panic("Can't handle cache error: nested exception");
288}
289
290/**
291 * Called when the the exception is not recoverable
292 */
293
294asmlinkage void cache_parity_error_octeon_recoverable(void)
295{
296 cache_parity_error_octeon(0);
297}
298
299/**
300 * Called when the the exception is recoverable
301 */
302
303asmlinkage void cache_parity_error_octeon_non_recoverable(void)
304{
305 cache_parity_error_octeon(1);
306}
307
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 1eb7c71e3d6a..98ad0a82c29e 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void)
182 tx39_cache_init(); 182 tx39_cache_init();
183 } 183 }
184 184
185 if (cpu_has_octeon_cache) {
186 extern void __weak octeon_cache_init(void);
187
188 octeon_cache_init();
189 }
190
185 setup_protection_map(); 191 setup_protection_map();
186} 192}
187 193
diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S
new file mode 100644
index 000000000000..3db8553fcd34
--- /dev/null
+++ b/arch/mips/mm/cex-oct.S
@@ -0,0 +1,70 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Cavium Networks
7 * Cache error handler
8 */
9
10#include <asm/asm.h>
11#include <asm/regdef.h>
12#include <asm/mipsregs.h>
13#include <asm/stackframe.h>
14
15/*
16 * Handle cache error. Indicate to the second level handler whether
17 * the exception is recoverable.
18 */
19 LEAF(except_vec2_octeon)
20
21 .set push
22 .set mips64r2
23 .set noreorder
24 .set noat
25
26
27 /* due to an errata we need to read the COP0 CacheErr (Dcache)
28 * before any cache/DRAM access */
29
30 rdhwr k0, $0 /* get core_id */
31 PTR_LA k1, cache_err_dcache
32 sll k0, k0, 3
33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */
34
35 dmfc0 k0, CP0_CACHEERR, 1
36 sd k0, (k1)
37 dmtc0 $0, CP0_CACHEERR, 1
38
39 /* check whether this is a nested exception */
40 mfc0 k1, CP0_STATUS
41 andi k1, k1, ST0_EXL
42 beqz k1, 1f
43 nop
44 j cache_parity_error_octeon_non_recoverable
45 nop
46
47 /* exception is recoverable */
481: j handle_cache_err
49 nop
50
51 .set pop
52 END(except_vec2_octeon)
53
54 /* We need to jump to handle_cache_err so that the previous handler
55 * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
56 * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */
57 LEAF(handle_cache_err)
58 .set push
59 .set noreorder
60 .set noat
61
62 SAVE_ALL
63 KMODE
64 jal cache_parity_error_octeon_recoverable
65 nop
66 j ret_from_exception
67 nop
68
69 .set pop
70 END(handle_cache_err)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index e6708b3ad343..546e6977d4ff 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -111,7 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
111void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, 111void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
112 dma_addr_t dma_handle) 112 dma_addr_t dma_handle)
113{ 113{
114 plat_unmap_dma_mem(dma_handle); 114 plat_unmap_dma_mem(dev, dma_handle);
115 free_pages((unsigned long) vaddr, get_order(size)); 115 free_pages((unsigned long) vaddr, get_order(size));
116} 116}
117 117
@@ -122,7 +122,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
122{ 122{
123 unsigned long addr = (unsigned long) vaddr; 123 unsigned long addr = (unsigned long) vaddr;
124 124
125 plat_unmap_dma_mem(dma_handle); 125 plat_unmap_dma_mem(dev, dma_handle);
126 126
127 if (!plat_device_is_coherent(dev)) 127 if (!plat_device_is_coherent(dev))
128 addr = CAC_ADDR(addr); 128 addr = CAC_ADDR(addr);
@@ -173,7 +173,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
173 __dma_sync(dma_addr_to_virt(dma_addr), size, 173 __dma_sync(dma_addr_to_virt(dma_addr), size,
174 direction); 174 direction);
175 175
176 plat_unmap_dma_mem(dma_addr); 176 plat_unmap_dma_mem(dev, dma_addr);
177} 177}
178 178
179EXPORT_SYMBOL(dma_unmap_single); 179EXPORT_SYMBOL(dma_unmap_single);
@@ -229,7 +229,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
229 dma_cache_wback_inv(addr, size); 229 dma_cache_wback_inv(addr, size);
230 } 230 }
231 231
232 plat_unmap_dma_mem(dma_address); 232 plat_unmap_dma_mem(dev, dma_address);
233} 233}
234 234
235EXPORT_SYMBOL(dma_unmap_page); 235EXPORT_SYMBOL(dma_unmap_page);
@@ -249,7 +249,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
249 if (addr) 249 if (addr)
250 __dma_sync(addr, sg->length, direction); 250 __dma_sync(addr, sg->length, direction);
251 } 251 }
252 plat_unmap_dma_mem(sg->dma_address); 252 plat_unmap_dma_mem(dev, sg->dma_address);
253 } 253 }
254} 254}
255 255
@@ -275,6 +275,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
275{ 275{
276 BUG_ON(direction == DMA_NONE); 276 BUG_ON(direction == DMA_NONE);
277 277
278 plat_extra_sync_for_device(dev);
278 if (!plat_device_is_coherent(dev)) { 279 if (!plat_device_is_coherent(dev)) {
279 unsigned long addr; 280 unsigned long addr;
280 281
@@ -305,6 +306,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
305{ 306{
306 BUG_ON(direction == DMA_NONE); 307 BUG_ON(direction == DMA_NONE);
307 308
309 plat_extra_sync_for_device(dev);
308 if (!plat_device_is_coherent(dev)) { 310 if (!plat_device_is_coherent(dev)) {
309 unsigned long addr; 311 unsigned long addr;
310 312
@@ -351,22 +353,14 @@ EXPORT_SYMBOL(dma_sync_sg_for_device);
351 353
352int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) 354int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
353{ 355{
354 return 0; 356 return plat_dma_mapping_error(dev, dma_addr);
355} 357}
356 358
357EXPORT_SYMBOL(dma_mapping_error); 359EXPORT_SYMBOL(dma_mapping_error);
358 360
359int dma_supported(struct device *dev, u64 mask) 361int dma_supported(struct device *dev, u64 mask)
360{ 362{
361 /* 363 return plat_dma_supported(dev, mask);
362 * we fall back to GFP_DMA when the mask isn't all 1s,
363 * so we can't guarantee allocations that must be
364 * within a tighter range than GFP_DMA..
365 */
366 if (mask < DMA_BIT_MASK(24))
367 return 0;
368
369 return 1;
370} 364}
371 365
372EXPORT_SYMBOL(dma_supported); 366EXPORT_SYMBOL(dma_supported);
@@ -383,6 +377,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
383{ 377{
384 BUG_ON(direction == DMA_NONE); 378 BUG_ON(direction == DMA_NONE);
385 379
380 plat_extra_sync_for_device(dev);
386 if (!plat_device_is_coherent(dev)) 381 if (!plat_device_is_coherent(dev))
387 __dma_sync((unsigned long)vaddr, size, direction); 382 __dma_sync((unsigned long)vaddr, size, direction);
388} 383}
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 5ce2fa745626..9619f66e531e 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -478,7 +478,10 @@ void __cpuinit tlb_init(void)
478 probe_tlb(config); 478 probe_tlb(config);
479 write_c0_pagemask(PM_DEFAULT_MASK); 479 write_c0_pagemask(PM_DEFAULT_MASK);
480 write_c0_wired(0); 480 write_c0_wired(0);
481 write_c0_framemask(0); 481 if (current_cpu_type() == CPU_R10000 ||
482 current_cpu_type() == CPU_R12000 ||
483 current_cpu_type() == CPU_R14000)
484 write_c0_framemask(0);
482 temp_tlb_entry = current_cpu_data.tlbsize - 1; 485 temp_tlb_entry = current_cpu_data.tlbsize - 1;
483 486
484 /* From this point on the ARC firmware is dead. */ 487 /* From this point on the ARC firmware is dead. */
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 979cf9197282..42942038d0fd 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
317 case CPU_BCM3302: 317 case CPU_BCM3302:
318 case CPU_BCM4710: 318 case CPU_BCM4710:
319 case CPU_LOONGSON2: 319 case CPU_LOONGSON2:
320 case CPU_CAVIUM_OCTEON:
320 if (m4kc_tlbp_war()) 321 if (m4kc_tlbp_war())
321 uasm_i_nop(p); 322 uasm_i_nop(p);
322 tlbw(p); 323 tlbw(p);
diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile
index 5ddad7bd60ac..0d428278356d 100644
--- a/arch/parisc/Makefile
+++ b/arch/parisc/Makefile
@@ -77,7 +77,7 @@ libs-y += arch/parisc/lib/ `$(CC) -print-libgcc-file-name`
77 77
78drivers-$(CONFIG_OPROFILE) += arch/parisc/oprofile/ 78drivers-$(CONFIG_OPROFILE) += arch/parisc/oprofile/
79 79
80PALO := $(shell if which palo; then : ; \ 80PALO := $(shell if (which palo 2>&1); then : ; \
81 elif [ -x /sbin/palo ]; then echo /sbin/palo; \ 81 elif [ -x /sbin/palo ]; then echo /sbin/palo; \
82 fi) 82 fi)
83 83
diff --git a/arch/parisc/include/asm/Kbuild b/arch/parisc/include/asm/Kbuild
index f88b252e419c..2121d99f8364 100644
--- a/arch/parisc/include/asm/Kbuild
+++ b/arch/parisc/include/asm/Kbuild
@@ -1,3 +1,4 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3unifdef-y += pdc.h 3unifdef-y += pdc.h
4unifdef-y += swab.h
diff --git a/arch/parisc/include/asm/byteorder.h b/arch/parisc/include/asm/byteorder.h
index db148313de5d..da66029c4cb2 100644
--- a/arch/parisc/include/asm/byteorder.h
+++ b/arch/parisc/include/asm/byteorder.h
@@ -1,82 +1,7 @@
1#ifndef _PARISC_BYTEORDER_H 1#ifndef _PARISC_BYTEORDER_H
2#define _PARISC_BYTEORDER_H 2#define _PARISC_BYTEORDER_H
3 3
4#include <asm/types.h> 4#include <asm/swab.h>
5#include <linux/compiler.h>
6
7#ifdef __GNUC__
8
9static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
10{
11 __asm__("dep %0, 15, 8, %0\n\t" /* deposit 00ab -> 0bab */
12 "shd %%r0, %0, 8, %0" /* shift 000000ab -> 00ba */
13 : "=r" (x)
14 : "0" (x));
15 return x;
16}
17
18static __inline__ __attribute_const__ __u32 ___arch__swab24(__u32 x)
19{
20 __asm__("shd %0, %0, 8, %0\n\t" /* shift xabcxabc -> cxab */
21 "dep %0, 15, 8, %0\n\t" /* deposit cxab -> cbab */
22 "shd %%r0, %0, 8, %0" /* shift 0000cbab -> 0cba */
23 : "=r" (x)
24 : "0" (x));
25 return x;
26}
27
28static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
29{
30 unsigned int temp;
31 __asm__("shd %0, %0, 16, %1\n\t" /* shift abcdabcd -> cdab */
32 "dep %1, 15, 8, %1\n\t" /* deposit cdab -> cbab */
33 "shd %0, %1, 8, %0" /* shift abcdcbab -> dcba */
34 : "=r" (x), "=&r" (temp)
35 : "0" (x));
36 return x;
37}
38
39
40#if BITS_PER_LONG > 32
41/*
42** From "PA-RISC 2.0 Architecture", HP Professional Books.
43** See Appendix I page 8 , "Endian Byte Swapping".
44**
45** Pretty cool algorithm: (* == zero'd bits)
46** PERMH 01234567 -> 67452301 into %0
47** HSHL 67452301 -> 7*5*3*1* into %1
48** HSHR 67452301 -> *6*4*2*0 into %0
49** OR %0 | %1 -> 76543210 into %0 (all done!)
50*/
51static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) {
52 __u64 temp;
53 __asm__("permh,3210 %0, %0\n\t"
54 "hshl %0, 8, %1\n\t"
55 "hshr,u %0, 8, %0\n\t"
56 "or %1, %0, %0"
57 : "=r" (x), "=&r" (temp)
58 : "0" (x));
59 return x;
60}
61#define __arch__swab64(x) ___arch__swab64(x)
62#define __BYTEORDER_HAS_U64__
63#elif !defined(__STRICT_ANSI__)
64static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
65{
66 __u32 t1 = ___arch__swab32((__u32) x);
67 __u32 t2 = ___arch__swab32((__u32) (x >> 32));
68 return (((__u64) t1 << 32) | t2);
69}
70#define __arch__swab64(x) ___arch__swab64(x)
71#define __BYTEORDER_HAS_U64__
72#endif
73
74#define __arch__swab16(x) ___arch__swab16(x)
75#define __arch__swab24(x) ___arch__swab24(x)
76#define __arch__swab32(x) ___arch__swab32(x)
77
78#endif /* __GNUC__ */
79
80#include <linux/byteorder/big_endian.h> 5#include <linux/byteorder/big_endian.h>
81 6
82#endif /* _PARISC_BYTEORDER_H */ 7#endif /* _PARISC_BYTEORDER_H */
diff --git a/arch/parisc/include/asm/checksum.h b/arch/parisc/include/asm/checksum.h
index e9639ccc3fce..c84b2fcb18a9 100644
--- a/arch/parisc/include/asm/checksum.h
+++ b/arch/parisc/include/asm/checksum.h
@@ -182,7 +182,7 @@ static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
182#endif 182#endif
183 : "=r" (sum), "=r" (saddr), "=r" (daddr), "=r" (len) 183 : "=r" (sum), "=r" (saddr), "=r" (daddr), "=r" (len)
184 : "0" (sum), "1" (saddr), "2" (daddr), "3" (len), "r" (proto) 184 : "0" (sum), "1" (saddr), "2" (daddr), "3" (len), "r" (proto)
185 : "r19", "r20", "r21", "r22"); 185 : "r19", "r20", "r21", "r22", "memory");
186 return csum_fold(sum); 186 return csum_fold(sum);
187} 187}
188 188
diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h
index 55ddb1842107..d3031d1f9d03 100644
--- a/arch/parisc/include/asm/io.h
+++ b/arch/parisc/include/asm/io.h
@@ -4,12 +4,6 @@
4#include <linux/types.h> 4#include <linux/types.h>
5#include <asm/pgtable.h> 5#include <asm/pgtable.h>
6 6
7extern unsigned long parisc_vmerge_boundary;
8extern unsigned long parisc_vmerge_max_size;
9
10#define BIO_VMERGE_BOUNDARY parisc_vmerge_boundary
11#define BIO_VMERGE_MAX_SIZE parisc_vmerge_max_size
12
13#define virt_to_phys(a) ((unsigned long)__pa(a)) 7#define virt_to_phys(a) ((unsigned long)__pa(a))
14#define phys_to_virt(a) __va(a) 8#define phys_to_virt(a) __va(a)
15#define virt_to_bus virt_to_phys 9#define virt_to_bus virt_to_phys
@@ -182,9 +176,9 @@ static inline void __raw_writeq(unsigned long long b, volatile void __iomem *add
182 176
183/* readb can never be const, so use __fswab instead of le*_to_cpu */ 177/* readb can never be const, so use __fswab instead of le*_to_cpu */
184#define readb(addr) __raw_readb(addr) 178#define readb(addr) __raw_readb(addr)
185#define readw(addr) __fswab16(__raw_readw(addr)) 179#define readw(addr) le16_to_cpu(__raw_readw(addr))
186#define readl(addr) __fswab32(__raw_readl(addr)) 180#define readl(addr) le32_to_cpu(__raw_readl(addr))
187#define readq(addr) __fswab64(__raw_readq(addr)) 181#define readq(addr) le64_to_cpu(__raw_readq(addr))
188#define writeb(b, addr) __raw_writeb(b, addr) 182#define writeb(b, addr) __raw_writeb(b, addr)
189#define writew(b, addr) __raw_writew(cpu_to_le16(b), addr) 183#define writew(b, addr) __raw_writew(cpu_to_le16(b), addr)
190#define writel(b, addr) __raw_writel(cpu_to_le32(b), addr) 184#define writel(b, addr) __raw_writel(cpu_to_le32(b), addr)
diff --git a/arch/parisc/include/asm/mmu_context.h b/arch/parisc/include/asm/mmu_context.h
index 85856c74ad1d..354b2aca990e 100644
--- a/arch/parisc/include/asm/mmu_context.h
+++ b/arch/parisc/include/asm/mmu_context.h
@@ -34,16 +34,21 @@ destroy_context(struct mm_struct *mm)
34 mm->context = 0; 34 mm->context = 0;
35} 35}
36 36
37static inline void load_context(mm_context_t context) 37static inline unsigned long __space_to_prot(mm_context_t context)
38{ 38{
39 mtsp(context, 3);
40#if SPACEID_SHIFT == 0 39#if SPACEID_SHIFT == 0
41 mtctl(context << 1,8); 40 return context << 1;
42#else 41#else
43 mtctl(context >> (SPACEID_SHIFT - 1),8); 42 return context >> (SPACEID_SHIFT - 1);
44#endif 43#endif
45} 44}
46 45
46static inline void load_context(mm_context_t context)
47{
48 mtsp(context, 3);
49 mtctl(__space_to_prot(context), 8);
50}
51
47static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) 52static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
48{ 53{
49 54
diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index 3c9d34844c83..9d64df8754ba 100644
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -17,6 +17,7 @@
17#include <asm/ptrace.h> 17#include <asm/ptrace.h>
18#include <asm/types.h> 18#include <asm/types.h>
19#include <asm/system.h> 19#include <asm/system.h>
20#include <asm/percpu.h>
20#endif /* __ASSEMBLY__ */ 21#endif /* __ASSEMBLY__ */
21 22
22#define KERNEL_STACK_SIZE (4*PAGE_SIZE) 23#define KERNEL_STACK_SIZE (4*PAGE_SIZE)
@@ -109,8 +110,7 @@ struct cpuinfo_parisc {
109}; 110};
110 111
111extern struct system_cpuinfo_parisc boot_cpu_data; 112extern struct system_cpuinfo_parisc boot_cpu_data;
112extern struct cpuinfo_parisc cpu_data[NR_CPUS]; 113DECLARE_PER_CPU(struct cpuinfo_parisc, cpu_data);
113#define current_cpu_data cpu_data[smp_processor_id()]
114 114
115#define CPU_HVERSION ((boot_cpu_data.hversion >> 4) & 0x0FFF) 115#define CPU_HVERSION ((boot_cpu_data.hversion >> 4) & 0x0FFF)
116 116
diff --git a/arch/parisc/include/asm/swab.h b/arch/parisc/include/asm/swab.h
new file mode 100644
index 000000000000..3ff16c5a3358
--- /dev/null
+++ b/arch/parisc/include/asm/swab.h
@@ -0,0 +1,66 @@
1#ifndef _PARISC_SWAB_H
2#define _PARISC_SWAB_H
3
4#include <asm/types.h>
5#include <linux/compiler.h>
6
7#define __SWAB_64_THRU_32__
8
9static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
10{
11 __asm__("dep %0, 15, 8, %0\n\t" /* deposit 00ab -> 0bab */
12 "shd %%r0, %0, 8, %0" /* shift 000000ab -> 00ba */
13 : "=r" (x)
14 : "0" (x));
15 return x;
16}
17#define __arch_swab16 __arch_swab16
18
19static inline __attribute_const__ __u32 __arch_swab24(__u32 x)
20{
21 __asm__("shd %0, %0, 8, %0\n\t" /* shift xabcxabc -> cxab */
22 "dep %0, 15, 8, %0\n\t" /* deposit cxab -> cbab */
23 "shd %%r0, %0, 8, %0" /* shift 0000cbab -> 0cba */
24 : "=r" (x)
25 : "0" (x));
26 return x;
27}
28
29static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
30{
31 unsigned int temp;
32 __asm__("shd %0, %0, 16, %1\n\t" /* shift abcdabcd -> cdab */
33 "dep %1, 15, 8, %1\n\t" /* deposit cdab -> cbab */
34 "shd %0, %1, 8, %0" /* shift abcdcbab -> dcba */
35 : "=r" (x), "=&r" (temp)
36 : "0" (x));
37 return x;
38}
39#define __arch_swab32 __arch_swab32
40
41#if BITS_PER_LONG > 32
42/*
43** From "PA-RISC 2.0 Architecture", HP Professional Books.
44** See Appendix I page 8 , "Endian Byte Swapping".
45**
46** Pretty cool algorithm: (* == zero'd bits)
47** PERMH 01234567 -> 67452301 into %0
48** HSHL 67452301 -> 7*5*3*1* into %1
49** HSHR 67452301 -> *6*4*2*0 into %0
50** OR %0 | %1 -> 76543210 into %0 (all done!)
51*/
52static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
53{
54 __u64 temp;
55 __asm__("permh,3210 %0, %0\n\t"
56 "hshl %0, 8, %1\n\t"
57 "hshr,u %0, 8, %0\n\t"
58 "or %1, %0, %0"
59 : "=r" (x), "=&r" (temp)
60 : "0" (x));
61 return x;
62}
63#define __arch_swab64 __arch_swab64
64#endif /* BITS_PER_LONG > 32 */
65
66#endif /* _PARISC_SWAB_H */
diff --git a/arch/parisc/include/asm/uaccess.h b/arch/parisc/include/asm/uaccess.h
index 4878b9501f24..1c6dbb6f6e56 100644
--- a/arch/parisc/include/asm/uaccess.h
+++ b/arch/parisc/include/asm/uaccess.h
@@ -241,4 +241,6 @@ unsigned long copy_in_user(void __user *dst, const void __user *src, unsigned lo
241#define __copy_to_user_inatomic __copy_to_user 241#define __copy_to_user_inatomic __copy_to_user
242#define __copy_from_user_inatomic __copy_from_user 242#define __copy_from_user_inatomic __copy_from_user
243 243
244int fixup_exception(struct pt_regs *regs);
245
244#endif /* __PARISC_UACCESS_H */ 246#endif /* __PARISC_UACCESS_H */
diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c
index 884b7ce16a3b..994bcd980909 100644
--- a/arch/parisc/kernel/drivers.c
+++ b/arch/parisc/kernel/drivers.c
@@ -549,6 +549,38 @@ static int parisc_generic_match(struct device *dev, struct device_driver *drv)
549 return match_device(to_parisc_driver(drv), to_parisc_device(dev)); 549 return match_device(to_parisc_driver(drv), to_parisc_device(dev));
550} 550}
551 551
552static ssize_t make_modalias(struct device *dev, char *buf)
553{
554 const struct parisc_device *padev = to_parisc_device(dev);
555 const struct parisc_device_id *id = &padev->id;
556
557 return sprintf(buf, "parisc:t%02Xhv%04Xrev%02Xsv%08X\n",
558 (u8)id->hw_type, (u16)id->hversion, (u8)id->hversion_rev,
559 (u32)id->sversion);
560}
561
562static int parisc_uevent(struct device *dev, struct kobj_uevent_env *env)
563{
564 const struct parisc_device *padev;
565 char modalias[40];
566
567 if (!dev)
568 return -ENODEV;
569
570 padev = to_parisc_device(dev);
571 if (!padev)
572 return -ENODEV;
573
574 if (add_uevent_var(env, "PARISC_NAME=%s", padev->name))
575 return -ENOMEM;
576
577 make_modalias(dev, modalias);
578 if (add_uevent_var(env, "MODALIAS=%s", modalias))
579 return -ENOMEM;
580
581 return 0;
582}
583
552#define pa_dev_attr(name, field, format_string) \ 584#define pa_dev_attr(name, field, format_string) \
553static ssize_t name##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 585static ssize_t name##_show(struct device *dev, struct device_attribute *attr, char *buf) \
554{ \ 586{ \
@@ -566,12 +598,7 @@ pa_dev_attr_id(sversion, "0x%05x\n");
566 598
567static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, char *buf) 599static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, char *buf)
568{ 600{
569 struct parisc_device *padev = to_parisc_device(dev); 601 return make_modalias(dev, buf);
570 struct parisc_device_id *id = &padev->id;
571
572 return sprintf(buf, "parisc:t%02Xhv%04Xrev%02Xsv%08X\n",
573 (u8)id->hw_type, (u16)id->hversion, (u8)id->hversion_rev,
574 (u32)id->sversion);
575} 602}
576 603
577static struct device_attribute parisc_device_attrs[] = { 604static struct device_attribute parisc_device_attrs[] = {
@@ -587,6 +614,7 @@ static struct device_attribute parisc_device_attrs[] = {
587struct bus_type parisc_bus_type = { 614struct bus_type parisc_bus_type = {
588 .name = "parisc", 615 .name = "parisc",
589 .match = parisc_generic_match, 616 .match = parisc_generic_match,
617 .uevent = parisc_uevent,
590 .dev_attrs = parisc_device_attrs, 618 .dev_attrs = parisc_device_attrs,
591 .probe = parisc_driver_probe, 619 .probe = parisc_driver_probe,
592 .remove = parisc_driver_remove, 620 .remove = parisc_driver_remove,
diff --git a/arch/parisc/kernel/hpmc.S b/arch/parisc/kernel/hpmc.S
index 2cbf13b3ef11..5595a2f31181 100644
--- a/arch/parisc/kernel/hpmc.S
+++ b/arch/parisc/kernel/hpmc.S
@@ -80,6 +80,7 @@ END(hpmc_pim_data)
80 80
81 .import intr_save, code 81 .import intr_save, code
82ENTRY(os_hpmc) 82ENTRY(os_hpmc)
83.os_hpmc:
83 84
84 /* 85 /*
85 * registers modified: 86 * registers modified:
@@ -295,5 +296,10 @@ os_hpmc_6:
295 b . 296 b .
296 nop 297 nop
297ENDPROC(os_hpmc) 298ENDPROC(os_hpmc)
298ENTRY(os_hpmc_end) /* this label used to compute os_hpmc checksum */ 299.os_hpmc_end:
299 nop 300 nop
301.data
302.align 4
303 .export os_hpmc_size
304os_hpmc_size:
305 .word .os_hpmc_end-.os_hpmc
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index 4cea935e2f99..ac2c822928c7 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -298,7 +298,7 @@ unsigned long txn_affinity_addr(unsigned int irq, int cpu)
298 irq_desc[irq].affinity = cpumask_of_cpu(cpu); 298 irq_desc[irq].affinity = cpumask_of_cpu(cpu);
299#endif 299#endif
300 300
301 return cpu_data[cpu].txn_addr; 301 return per_cpu(cpu_data, cpu).txn_addr;
302} 302}
303 303
304 304
@@ -309,8 +309,9 @@ unsigned long txn_alloc_addr(unsigned int virt_irq)
309 next_cpu++; /* assign to "next" CPU we want this bugger on */ 309 next_cpu++; /* assign to "next" CPU we want this bugger on */
310 310
311 /* validate entry */ 311 /* validate entry */
312 while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr || 312 while ((next_cpu < NR_CPUS) &&
313 !cpu_online(next_cpu))) 313 (!per_cpu(cpu_data, next_cpu).txn_addr ||
314 !cpu_online(next_cpu)))
314 next_cpu++; 315 next_cpu++;
315 316
316 if (next_cpu >= NR_CPUS) 317 if (next_cpu >= NR_CPUS)
@@ -359,7 +360,7 @@ void do_cpu_irq_mask(struct pt_regs *regs)
359 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", 360 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
360 irq, smp_processor_id(), cpu); 361 irq, smp_processor_id(), cpu);
361 gsc_writel(irq + CPU_IRQ_BASE, 362 gsc_writel(irq + CPU_IRQ_BASE,
362 cpu_data[cpu].hpa); 363 per_cpu(cpu_data, cpu).hpa);
363 goto set_out; 364 goto set_out;
364 } 365 }
365#endif 366#endif
@@ -421,5 +422,5 @@ void __init init_IRQ(void)
421 422
422void ack_bad_irq(unsigned int irq) 423void ack_bad_irq(unsigned int irq)
423{ 424{
424 printk("unexpected IRQ %d\n", irq); 425 printk(KERN_WARNING "unexpected IRQ %d\n", irq);
425} 426}
diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c
index ccb68090781e..1ff366cb9685 100644
--- a/arch/parisc/kernel/pdc_cons.c
+++ b/arch/parisc/kernel/pdc_cons.c
@@ -52,7 +52,7 @@
52#include <linux/tty.h> 52#include <linux/tty.h>
53#include <asm/pdc.h> /* for iodc_call() proto and friends */ 53#include <asm/pdc.h> /* for iodc_call() proto and friends */
54 54
55static spinlock_t pdc_console_lock = SPIN_LOCK_UNLOCKED; 55static DEFINE_SPINLOCK(pdc_console_lock);
56 56
57static void pdc_console_write(struct console *co, const char *s, unsigned count) 57static void pdc_console_write(struct console *co, const char *s, unsigned count)
58{ 58{
diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c
index f696f57faa15..75099efb3bf3 100644
--- a/arch/parisc/kernel/perf.c
+++ b/arch/parisc/kernel/perf.c
@@ -541,9 +541,9 @@ static int __init perf_init(void)
541 spin_lock_init(&perf_lock); 541 spin_lock_init(&perf_lock);
542 542
543 /* TODO: this only lets us access the first cpu.. what to do for SMP? */ 543 /* TODO: this only lets us access the first cpu.. what to do for SMP? */
544 cpu_device = cpu_data[0].dev; 544 cpu_device = per_cpu(cpu_data, 0).dev;
545 printk("Performance monitoring counters enabled for %s\n", 545 printk("Performance monitoring counters enabled for %s\n",
546 cpu_data[0].dev->name); 546 per_cpu(cpu_data, 0).dev->name);
547 547
548 return 0; 548 return 0;
549} 549}
diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c
index 370086fb8333..ecb609342feb 100644
--- a/arch/parisc/kernel/processor.c
+++ b/arch/parisc/kernel/processor.c
@@ -3,7 +3,7 @@
3 * Initial setup-routines for HP 9000 based hardware. 3 * Initial setup-routines for HP 9000 based hardware.
4 * 4 *
5 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
6 * Modifications for PA-RISC (C) 1999 Helge Deller <deller@gmx.de> 6 * Modifications for PA-RISC (C) 1999-2008 Helge Deller <deller@gmx.de>
7 * Modifications copyright 1999 SuSE GmbH (Philipp Rumpf) 7 * Modifications copyright 1999 SuSE GmbH (Philipp Rumpf)
8 * Modifications copyright 2000 Martin K. Petersen <mkp@mkp.net> 8 * Modifications copyright 2000 Martin K. Petersen <mkp@mkp.net>
9 * Modifications copyright 2000 Philipp Rumpf <prumpf@tux.org> 9 * Modifications copyright 2000 Philipp Rumpf <prumpf@tux.org>
@@ -46,7 +46,7 @@
46struct system_cpuinfo_parisc boot_cpu_data __read_mostly; 46struct system_cpuinfo_parisc boot_cpu_data __read_mostly;
47EXPORT_SYMBOL(boot_cpu_data); 47EXPORT_SYMBOL(boot_cpu_data);
48 48
49struct cpuinfo_parisc cpu_data[NR_CPUS] __read_mostly; 49DEFINE_PER_CPU(struct cpuinfo_parisc, cpu_data);
50 50
51extern int update_cr16_clocksource(void); /* from time.c */ 51extern int update_cr16_clocksource(void); /* from time.c */
52 52
@@ -69,6 +69,23 @@ extern int update_cr16_clocksource(void); /* from time.c */
69*/ 69*/
70 70
71/** 71/**
72 * init_cpu_profiler - enable/setup per cpu profiling hooks.
73 * @cpunum: The processor instance.
74 *
75 * FIXME: doesn't do much yet...
76 */
77static void __cpuinit
78init_percpu_prof(unsigned long cpunum)
79{
80 struct cpuinfo_parisc *p;
81
82 p = &per_cpu(cpu_data, cpunum);
83 p->prof_counter = 1;
84 p->prof_multiplier = 1;
85}
86
87
88/**
72 * processor_probe - Determine if processor driver should claim this device. 89 * processor_probe - Determine if processor driver should claim this device.
73 * @dev: The device which has been found. 90 * @dev: The device which has been found.
74 * 91 *
@@ -147,7 +164,7 @@ static int __cpuinit processor_probe(struct parisc_device *dev)
147 } 164 }
148#endif 165#endif
149 166
150 p = &cpu_data[cpuid]; 167 p = &per_cpu(cpu_data, cpuid);
151 boot_cpu_data.cpu_count++; 168 boot_cpu_data.cpu_count++;
152 169
153 /* initialize counters - CPU 0 gets it_value set in time_init() */ 170 /* initialize counters - CPU 0 gets it_value set in time_init() */
@@ -162,12 +179,9 @@ static int __cpuinit processor_probe(struct parisc_device *dev)
162#ifdef CONFIG_SMP 179#ifdef CONFIG_SMP
163 /* 180 /*
164 ** FIXME: review if any other initialization is clobbered 181 ** FIXME: review if any other initialization is clobbered
165 ** for boot_cpu by the above memset(). 182 ** for boot_cpu by the above memset().
166 */ 183 */
167 184 init_percpu_prof(cpuid);
168 /* stolen from init_percpu_prof() */
169 cpu_data[cpuid].prof_counter = 1;
170 cpu_data[cpuid].prof_multiplier = 1;
171#endif 185#endif
172 186
173 /* 187 /*
@@ -261,19 +275,6 @@ void __init collect_boot_cpu_data(void)
261} 275}
262 276
263 277
264/**
265 * init_cpu_profiler - enable/setup per cpu profiling hooks.
266 * @cpunum: The processor instance.
267 *
268 * FIXME: doesn't do much yet...
269 */
270static inline void __init
271init_percpu_prof(int cpunum)
272{
273 cpu_data[cpunum].prof_counter = 1;
274 cpu_data[cpunum].prof_multiplier = 1;
275}
276
277 278
278/** 279/**
279 * init_per_cpu - Handle individual processor initializations. 280 * init_per_cpu - Handle individual processor initializations.
@@ -293,7 +294,7 @@ init_percpu_prof(int cpunum)
293 * 294 *
294 * o Enable CPU profiling hooks. 295 * o Enable CPU profiling hooks.
295 */ 296 */
296int __init init_per_cpu(int cpunum) 297int __cpuinit init_per_cpu(int cpunum)
297{ 298{
298 int ret; 299 int ret;
299 struct pdc_coproc_cfg coproc_cfg; 300 struct pdc_coproc_cfg coproc_cfg;
@@ -307,8 +308,8 @@ int __init init_per_cpu(int cpunum)
307 /* FWIW, FP rev/model is a more accurate way to determine 308 /* FWIW, FP rev/model is a more accurate way to determine
308 ** CPU type. CPU rev/model has some ambiguous cases. 309 ** CPU type. CPU rev/model has some ambiguous cases.
309 */ 310 */
310 cpu_data[cpunum].fp_rev = coproc_cfg.revision; 311 per_cpu(cpu_data, cpunum).fp_rev = coproc_cfg.revision;
311 cpu_data[cpunum].fp_model = coproc_cfg.model; 312 per_cpu(cpu_data, cpunum).fp_model = coproc_cfg.model;
312 313
313 printk(KERN_INFO "FP[%d] enabled: Rev %ld Model %ld\n", 314 printk(KERN_INFO "FP[%d] enabled: Rev %ld Model %ld\n",
314 cpunum, coproc_cfg.revision, coproc_cfg.model); 315 cpunum, coproc_cfg.revision, coproc_cfg.model);
@@ -344,16 +345,17 @@ int __init init_per_cpu(int cpunum)
344int 345int
345show_cpuinfo (struct seq_file *m, void *v) 346show_cpuinfo (struct seq_file *m, void *v)
346{ 347{
347 int n; 348 unsigned long cpu;
348 349
349 for(n=0; n<boot_cpu_data.cpu_count; n++) { 350 for_each_online_cpu(cpu) {
351 const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
350#ifdef CONFIG_SMP 352#ifdef CONFIG_SMP
351 if (0 == cpu_data[n].hpa) 353 if (0 == cpuinfo->hpa)
352 continue; 354 continue;
353#endif 355#endif
354 seq_printf(m, "processor\t: %d\n" 356 seq_printf(m, "processor\t: %lu\n"
355 "cpu family\t: PA-RISC %s\n", 357 "cpu family\t: PA-RISC %s\n",
356 n, boot_cpu_data.family_name); 358 cpu, boot_cpu_data.family_name);
357 359
358 seq_printf(m, "cpu\t\t: %s\n", boot_cpu_data.cpu_name ); 360 seq_printf(m, "cpu\t\t: %s\n", boot_cpu_data.cpu_name );
359 361
@@ -365,8 +367,8 @@ show_cpuinfo (struct seq_file *m, void *v)
365 seq_printf(m, "model\t\t: %s\n" 367 seq_printf(m, "model\t\t: %s\n"
366 "model name\t: %s\n", 368 "model name\t: %s\n",
367 boot_cpu_data.pdc.sys_model_name, 369 boot_cpu_data.pdc.sys_model_name,
368 cpu_data[n].dev ? 370 cpuinfo->dev ?
369 cpu_data[n].dev->name : "Unknown" ); 371 cpuinfo->dev->name : "Unknown");
370 372
371 seq_printf(m, "hversion\t: 0x%08x\n" 373 seq_printf(m, "hversion\t: 0x%08x\n"
372 "sversion\t: 0x%08x\n", 374 "sversion\t: 0x%08x\n",
@@ -377,8 +379,8 @@ show_cpuinfo (struct seq_file *m, void *v)
377 show_cache_info(m); 379 show_cache_info(m);
378 380
379 seq_printf(m, "bogomips\t: %lu.%02lu\n", 381 seq_printf(m, "bogomips\t: %lu.%02lu\n",
380 cpu_data[n].loops_per_jiffy / (500000 / HZ), 382 cpuinfo->loops_per_jiffy / (500000 / HZ),
381 (cpu_data[n].loops_per_jiffy / (5000 / HZ)) % 100); 383 (cpuinfo->loops_per_jiffy / (5000 / HZ)) % 100);
382 384
383 seq_printf(m, "software id\t: %ld\n\n", 385 seq_printf(m, "software id\t: %ld\n\n",
384 boot_cpu_data.pdc.model.sw_id); 386 boot_cpu_data.pdc.model.sw_id);
diff --git a/arch/parisc/kernel/setup.c b/arch/parisc/kernel/setup.c
index 7d27853ff8c8..82131ca8e05c 100644
--- a/arch/parisc/kernel/setup.c
+++ b/arch/parisc/kernel/setup.c
@@ -58,11 +58,6 @@ int parisc_bus_is_phys __read_mostly = 1; /* Assume no IOMMU is present */
58EXPORT_SYMBOL(parisc_bus_is_phys); 58EXPORT_SYMBOL(parisc_bus_is_phys);
59#endif 59#endif
60 60
61/* This sets the vmerge boundary and size, it's here because it has to
62 * be available on all platforms (zero means no-virtual merging) */
63unsigned long parisc_vmerge_boundary = 0;
64unsigned long parisc_vmerge_max_size = 0;
65
66void __init setup_cmdline(char **cmdline_p) 61void __init setup_cmdline(char **cmdline_p)
67{ 62{
68 extern unsigned int boot_args[]; 63 extern unsigned int boot_args[];
@@ -321,7 +316,7 @@ static int __init parisc_init(void)
321 316
322 processor_init(); 317 processor_init();
323 printk(KERN_INFO "CPU(s): %d x %s at %d.%06d MHz\n", 318 printk(KERN_INFO "CPU(s): %d x %s at %d.%06d MHz\n",
324 boot_cpu_data.cpu_count, 319 num_present_cpus(),
325 boot_cpu_data.cpu_name, 320 boot_cpu_data.cpu_name,
326 boot_cpu_data.cpu_hz / 1000000, 321 boot_cpu_data.cpu_hz / 1000000,
327 boot_cpu_data.cpu_hz % 1000000 ); 322 boot_cpu_data.cpu_hz % 1000000 );
@@ -387,8 +382,8 @@ void start_parisc(void)
387 if (ret >= 0 && coproc_cfg.ccr_functional) { 382 if (ret >= 0 && coproc_cfg.ccr_functional) {
388 mtctl(coproc_cfg.ccr_functional, 10); 383 mtctl(coproc_cfg.ccr_functional, 10);
389 384
390 cpu_data[cpunum].fp_rev = coproc_cfg.revision; 385 per_cpu(cpu_data, cpunum).fp_rev = coproc_cfg.revision;
391 cpu_data[cpunum].fp_model = coproc_cfg.model; 386 per_cpu(cpu_data, cpunum).fp_model = coproc_cfg.model;
392 387
393 asm volatile ("fstd %fr0,8(%sp)"); 388 asm volatile ("fstd %fr0,8(%sp)");
394 } else { 389 } else {
diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c
index 80bc000523fa..9995d7ed5819 100644
--- a/arch/parisc/kernel/smp.c
+++ b/arch/parisc/kernel/smp.c
@@ -56,16 +56,17 @@ static int smp_debug_lvl = 0;
56 if (lvl >= smp_debug_lvl) \ 56 if (lvl >= smp_debug_lvl) \
57 printk(printargs); 57 printk(printargs);
58#else 58#else
59#define smp_debug(lvl, ...) 59#define smp_debug(lvl, ...) do { } while(0)
60#endif /* DEBUG_SMP */ 60#endif /* DEBUG_SMP */
61 61
62DEFINE_SPINLOCK(smp_lock); 62DEFINE_SPINLOCK(smp_lock);
63 63
64volatile struct task_struct *smp_init_current_idle_task; 64volatile struct task_struct *smp_init_current_idle_task;
65 65
66static volatile int cpu_now_booting __read_mostly = 0; /* track which CPU is booting */ 66/* track which CPU is booting */
67static volatile int cpu_now_booting __cpuinitdata;
67 68
68static int parisc_max_cpus __read_mostly = 1; 69static int parisc_max_cpus __cpuinitdata = 1;
69 70
70DEFINE_PER_CPU(spinlock_t, ipi_lock) = SPIN_LOCK_UNLOCKED; 71DEFINE_PER_CPU(spinlock_t, ipi_lock) = SPIN_LOCK_UNLOCKED;
71 72
@@ -123,7 +124,7 @@ irqreturn_t
123ipi_interrupt(int irq, void *dev_id) 124ipi_interrupt(int irq, void *dev_id)
124{ 125{
125 int this_cpu = smp_processor_id(); 126 int this_cpu = smp_processor_id();
126 struct cpuinfo_parisc *p = &cpu_data[this_cpu]; 127 struct cpuinfo_parisc *p = &per_cpu(cpu_data, this_cpu);
127 unsigned long ops; 128 unsigned long ops;
128 unsigned long flags; 129 unsigned long flags;
129 130
@@ -202,13 +203,13 @@ ipi_interrupt(int irq, void *dev_id)
202static inline void 203static inline void
203ipi_send(int cpu, enum ipi_message_type op) 204ipi_send(int cpu, enum ipi_message_type op)
204{ 205{
205 struct cpuinfo_parisc *p = &cpu_data[cpu]; 206 struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpu);
206 spinlock_t *lock = &per_cpu(ipi_lock, cpu); 207 spinlock_t *lock = &per_cpu(ipi_lock, cpu);
207 unsigned long flags; 208 unsigned long flags;
208 209
209 spin_lock_irqsave(lock, flags); 210 spin_lock_irqsave(lock, flags);
210 p->pending_ipi |= 1 << op; 211 p->pending_ipi |= 1 << op;
211 gsc_writel(IPI_IRQ - CPU_IRQ_BASE, cpu_data[cpu].hpa); 212 gsc_writel(IPI_IRQ - CPU_IRQ_BASE, p->hpa);
212 spin_unlock_irqrestore(lock, flags); 213 spin_unlock_irqrestore(lock, flags);
213} 214}
214 215
@@ -224,10 +225,7 @@ send_IPI_mask(cpumask_t mask, enum ipi_message_type op)
224static inline void 225static inline void
225send_IPI_single(int dest_cpu, enum ipi_message_type op) 226send_IPI_single(int dest_cpu, enum ipi_message_type op)
226{ 227{
227 if (dest_cpu == NO_PROC_ID) { 228 BUG_ON(dest_cpu == NO_PROC_ID);
228 BUG();
229 return;
230 }
231 229
232 ipi_send(dest_cpu, op); 230 ipi_send(dest_cpu, op);
233} 231}
@@ -309,8 +307,7 @@ smp_cpu_init(int cpunum)
309 /* Initialise the idle task for this CPU */ 307 /* Initialise the idle task for this CPU */
310 atomic_inc(&init_mm.mm_count); 308 atomic_inc(&init_mm.mm_count);
311 current->active_mm = &init_mm; 309 current->active_mm = &init_mm;
312 if(current->mm) 310 BUG_ON(current->mm);
313 BUG();
314 enter_lazy_tlb(&init_mm, current); 311 enter_lazy_tlb(&init_mm, current);
315 312
316 init_IRQ(); /* make sure no IRQs are enabled or pending */ 313 init_IRQ(); /* make sure no IRQs are enabled or pending */
@@ -345,6 +342,7 @@ void __init smp_callin(void)
345 */ 342 */
346int __cpuinit smp_boot_one_cpu(int cpuid) 343int __cpuinit smp_boot_one_cpu(int cpuid)
347{ 344{
345 const struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpuid);
348 struct task_struct *idle; 346 struct task_struct *idle;
349 long timeout; 347 long timeout;
350 348
@@ -376,7 +374,7 @@ int __cpuinit smp_boot_one_cpu(int cpuid)
376 smp_init_current_idle_task = idle ; 374 smp_init_current_idle_task = idle ;
377 mb(); 375 mb();
378 376
379 printk("Releasing cpu %d now, hpa=%lx\n", cpuid, cpu_data[cpuid].hpa); 377 printk(KERN_INFO "Releasing cpu %d now, hpa=%lx\n", cpuid, p->hpa);
380 378
381 /* 379 /*
382 ** This gets PDC to release the CPU from a very tight loop. 380 ** This gets PDC to release the CPU from a very tight loop.
@@ -387,7 +385,7 @@ int __cpuinit smp_boot_one_cpu(int cpuid)
387 ** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the 385 ** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the
388 ** contents of memory are valid." 386 ** contents of memory are valid."
389 */ 387 */
390 gsc_writel(TIMER_IRQ - CPU_IRQ_BASE, cpu_data[cpuid].hpa); 388 gsc_writel(TIMER_IRQ - CPU_IRQ_BASE, p->hpa);
391 mb(); 389 mb();
392 390
393 /* 391 /*
@@ -419,12 +417,12 @@ alive:
419 return 0; 417 return 0;
420} 418}
421 419
422void __devinit smp_prepare_boot_cpu(void) 420void __init smp_prepare_boot_cpu(void)
423{ 421{
424 int bootstrap_processor=cpu_data[0].cpuid; /* CPU ID of BSP */ 422 int bootstrap_processor = per_cpu(cpu_data, 0).cpuid;
425 423
426 /* Setup BSP mappings */ 424 /* Setup BSP mappings */
427 printk("SMP: bootstrap CPU ID is %d\n",bootstrap_processor); 425 printk(KERN_INFO "SMP: bootstrap CPU ID is %d\n", bootstrap_processor);
428 426
429 cpu_set(bootstrap_processor, cpu_online_map); 427 cpu_set(bootstrap_processor, cpu_online_map);
430 cpu_set(bootstrap_processor, cpu_present_map); 428 cpu_set(bootstrap_processor, cpu_present_map);
diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c
index 4d09203bc693..9d46c43a4152 100644
--- a/arch/parisc/kernel/time.c
+++ b/arch/parisc/kernel/time.c
@@ -60,7 +60,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id)
60 unsigned long cycles_elapsed, ticks_elapsed; 60 unsigned long cycles_elapsed, ticks_elapsed;
61 unsigned long cycles_remainder; 61 unsigned long cycles_remainder;
62 unsigned int cpu = smp_processor_id(); 62 unsigned int cpu = smp_processor_id();
63 struct cpuinfo_parisc *cpuinfo = &cpu_data[cpu]; 63 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
64 64
65 /* gcc can optimize for "read-only" case with a local clocktick */ 65 /* gcc can optimize for "read-only" case with a local clocktick */
66 unsigned long cpt = clocktick; 66 unsigned long cpt = clocktick;
@@ -213,7 +213,7 @@ void __init start_cpu_itimer(void)
213 213
214 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ 214 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
215 215
216 cpu_data[cpu].it_value = next_tick; 216 per_cpu(cpu_data, cpu).it_value = next_tick;
217} 217}
218 218
219struct platform_device rtc_parisc_dev = { 219struct platform_device rtc_parisc_dev = {
diff --git a/arch/parisc/kernel/topology.c b/arch/parisc/kernel/topology.c
index d71cb018a21e..f5159381fdd6 100644
--- a/arch/parisc/kernel/topology.c
+++ b/arch/parisc/kernel/topology.c
@@ -22,14 +22,14 @@
22#include <linux/cpu.h> 22#include <linux/cpu.h>
23#include <linux/cache.h> 23#include <linux/cache.h>
24 24
25static struct cpu cpu_devices[NR_CPUS] __read_mostly; 25static DEFINE_PER_CPU(struct cpu, cpu_devices);
26 26
27static int __init topology_init(void) 27static int __init topology_init(void)
28{ 28{
29 int num; 29 int num;
30 30
31 for_each_present_cpu(num) { 31 for_each_present_cpu(num) {
32 register_cpu(&cpu_devices[num], num); 32 register_cpu(&per_cpu(cpu_devices, num), num);
33 } 33 }
34 return 0; 34 return 0;
35} 35}
diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c
index 4c771cd580ec..ba658d2086f7 100644
--- a/arch/parisc/kernel/traps.c
+++ b/arch/parisc/kernel/traps.c
@@ -745,6 +745,10 @@ void handle_interruption(int code, struct pt_regs *regs)
745 /* Fall Through */ 745 /* Fall Through */
746 case 27: 746 case 27:
747 /* Data memory protection ID trap */ 747 /* Data memory protection ID trap */
748 if (code == 27 && !user_mode(regs) &&
749 fixup_exception(regs))
750 return;
751
748 die_if_kernel("Protection id trap", regs, code); 752 die_if_kernel("Protection id trap", regs, code);
749 si.si_code = SEGV_MAPERR; 753 si.si_code = SEGV_MAPERR;
750 si.si_signo = SIGSEGV; 754 si.si_signo = SIGSEGV;
@@ -821,8 +825,8 @@ void handle_interruption(int code, struct pt_regs *regs)
821 825
822int __init check_ivt(void *iva) 826int __init check_ivt(void *iva)
823{ 827{
828 extern u32 os_hpmc_size;
824 extern const u32 os_hpmc[]; 829 extern const u32 os_hpmc[];
825 extern const u32 os_hpmc_end[];
826 830
827 int i; 831 int i;
828 u32 check = 0; 832 u32 check = 0;
@@ -839,8 +843,7 @@ int __init check_ivt(void *iva)
839 *ivap++ = 0; 843 *ivap++ = 0;
840 844
841 /* Compute Checksum for HPMC handler */ 845 /* Compute Checksum for HPMC handler */
842 846 length = os_hpmc_size;
843 length = os_hpmc_end - os_hpmc;
844 ivap[7] = length; 847 ivap[7] = length;
845 848
846 hpmcp = (u32 *)os_hpmc; 849 hpmcp = (u32 *)os_hpmc;
diff --git a/arch/parisc/kernel/unwind.c b/arch/parisc/kernel/unwind.c
index 6773c582e457..69dad5a850a8 100644
--- a/arch/parisc/kernel/unwind.c
+++ b/arch/parisc/kernel/unwind.c
@@ -372,7 +372,7 @@ void unwind_frame_init_from_blocked_task(struct unwind_frame_info *info, struct
372 struct pt_regs *r = &t->thread.regs; 372 struct pt_regs *r = &t->thread.regs;
373 struct pt_regs *r2; 373 struct pt_regs *r2;
374 374
375 r2 = kmalloc(sizeof(struct pt_regs), GFP_KERNEL); 375 r2 = kmalloc(sizeof(struct pt_regs), GFP_ATOMIC);
376 if (!r2) 376 if (!r2)
377 return; 377 return;
378 *r2 = *r; 378 *r2 = *r;
diff --git a/arch/parisc/lib/iomap.c b/arch/parisc/lib/iomap.c
index 9abed07db7fc..5069e8b2ca71 100644
--- a/arch/parisc/lib/iomap.c
+++ b/arch/parisc/lib/iomap.c
@@ -261,7 +261,7 @@ static const struct iomap_ops iomem_ops = {
261 iomem_write32r, 261 iomem_write32r,
262}; 262};
263 263
264const struct iomap_ops *iomap_ops[8] = { 264static const struct iomap_ops *iomap_ops[8] = {
265 [0] = &ioport_ops, 265 [0] = &ioport_ops,
266 [7] = &iomem_ops 266 [7] = &iomem_ops
267}; 267};
diff --git a/arch/parisc/lib/memcpy.c b/arch/parisc/lib/memcpy.c
index 2d68431fc22e..bbda909c866e 100644
--- a/arch/parisc/lib/memcpy.c
+++ b/arch/parisc/lib/memcpy.c
@@ -275,7 +275,7 @@ handle_store_error:
275 275
276 276
277/* Returns 0 for success, otherwise, returns number of bytes not transferred. */ 277/* Returns 0 for success, otherwise, returns number of bytes not transferred. */
278unsigned long pa_memcpy(void *dstp, const void *srcp, unsigned long len) 278static unsigned long pa_memcpy(void *dstp, const void *srcp, unsigned long len)
279{ 279{
280 register unsigned long src, dst, t1, t2, t3; 280 register unsigned long src, dst, t1, t2, t3;
281 register unsigned char *pcs, *pcd; 281 register unsigned char *pcs, *pcd;
diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c
index b2e3e9a8cece..92c7fa4ecc3f 100644
--- a/arch/parisc/mm/fault.c
+++ b/arch/parisc/mm/fault.c
@@ -139,13 +139,41 @@ parisc_acctyp(unsigned long code, unsigned int inst)
139 } 139 }
140#endif 140#endif
141 141
142int fixup_exception(struct pt_regs *regs)
143{
144 const struct exception_table_entry *fix;
145
146 fix = search_exception_tables(regs->iaoq[0]);
147 if (fix) {
148 struct exception_data *d;
149 d = &__get_cpu_var(exception_data);
150 d->fault_ip = regs->iaoq[0];
151 d->fault_space = regs->isr;
152 d->fault_addr = regs->ior;
153
154 regs->iaoq[0] = ((fix->fixup) & ~3);
155 /*
156 * NOTE: In some cases the faulting instruction
157 * may be in the delay slot of a branch. We
158 * don't want to take the branch, so we don't
159 * increment iaoq[1], instead we set it to be
160 * iaoq[0]+4, and clear the B bit in the PSW
161 */
162 regs->iaoq[1] = regs->iaoq[0] + 4;
163 regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
164
165 return 1;
166 }
167
168 return 0;
169}
170
142void do_page_fault(struct pt_regs *regs, unsigned long code, 171void do_page_fault(struct pt_regs *regs, unsigned long code,
143 unsigned long address) 172 unsigned long address)
144{ 173{
145 struct vm_area_struct *vma, *prev_vma; 174 struct vm_area_struct *vma, *prev_vma;
146 struct task_struct *tsk = current; 175 struct task_struct *tsk = current;
147 struct mm_struct *mm = tsk->mm; 176 struct mm_struct *mm = tsk->mm;
148 const struct exception_table_entry *fix;
149 unsigned long acc_type; 177 unsigned long acc_type;
150 int fault; 178 int fault;
151 179
@@ -229,32 +257,8 @@ bad_area:
229 257
230no_context: 258no_context:
231 259
232 if (!user_mode(regs)) { 260 if (!user_mode(regs) && fixup_exception(regs)) {
233 fix = search_exception_tables(regs->iaoq[0]); 261 return;
234
235 if (fix) {
236 struct exception_data *d;
237
238 d = &__get_cpu_var(exception_data);
239 d->fault_ip = regs->iaoq[0];
240 d->fault_space = regs->isr;
241 d->fault_addr = regs->ior;
242
243 regs->iaoq[0] = ((fix->fixup) & ~3);
244
245 /*
246 * NOTE: In some cases the faulting instruction
247 * may be in the delay slot of a branch. We
248 * don't want to take the branch, so we don't
249 * increment iaoq[1], instead we set it to be
250 * iaoq[0]+4, and clear the B bit in the PSW
251 */
252
253 regs->iaoq[1] = regs->iaoq[0] + 4;
254 regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
255
256 return;
257 }
258 } 262 }
259 263
260 parisc_terminate("Bad Address (null pointer deref?)", regs, code, address); 264 parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 9708b3423bbd..e78c355c7bac 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -88,6 +88,21 @@
88 compatible = "gef,fpga-regs"; 88 compatible = "gef,fpga-regs";
89 reg = <0x4 0x0 0x40>; 89 reg = <0x4 0x0 0x40>;
90 }; 90 };
91
92 wdt@4,2000 {
93 compatible = "gef,fpga-wdt";
94 reg = <0x4 0x2000 0x8>;
95 interrupts = <0x1a 0x4>;
96 interrupt-parent = <&gef_pic>;
97 };
98 /* Second watchdog available, driver currently supports one.
99 wdt@4,2010 {
100 compatible = "gef,fpga-wdt";
101 reg = <0x4 0x2010 0x8>;
102 interrupts = <0x1b 0x4>;
103 interrupt-parent = <&gef_pic>;
104 };
105 */
91 gef_pic: pic@4,4000 { 106 gef_pic: pic@4,4000 {
92 #interrupt-cells = <1>; 107 #interrupt-cells = <1>;
93 interrupt-controller; 108 interrupt-controller;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index b9da42105066..0668d1048779 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -313,7 +313,7 @@
313 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>; 313 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
314 clock-frequency = <33333333>; 314 clock-frequency = <33333333>;
315 interrupt-parent = <&mpic>; 315 interrupt-parent = <&mpic>;
316 interrupts = <26 2>; 316 interrupts = <25 2>;
317 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 317 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
318 interrupt-map = < 318 interrupt-map = <
319 /* IDSEL 0x0 */ 319 /* IDSEL 0x0 */
@@ -350,7 +350,7 @@
350 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>; 350 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
351 clock-frequency = <33333333>; 351 clock-frequency = <33333333>;
352 interrupt-parent = <&mpic>; 352 interrupt-parent = <&mpic>;
353 interrupts = <25 2>; 353 interrupts = <26 2>;
354 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 354 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
355 interrupt-map = < 355 interrupt-map = <
356 /* IDSEL 0x0 */ 356 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 21459e161d02..3dcc001b8ed3 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -724,7 +724,7 @@
724 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; 724 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
725 clock-frequency = <33333333>; 725 clock-frequency = <33333333>;
726 interrupt-parent = <&mpic>; 726 interrupt-parent = <&mpic>;
727 interrupts = <26 2>; 727 interrupts = <25 2>;
728 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 728 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
729 interrupt-map = < 729 interrupt-map = <
730 /* IDSEL 0x0 */ 730 /* IDSEL 0x0 */
@@ -761,7 +761,7 @@
761 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; 761 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
762 clock-frequency = <33333333>; 762 clock-frequency = <33333333>;
763 interrupt-parent = <&mpic>; 763 interrupt-parent = <&mpic>;
764 interrupts = <27 2>; 764 interrupts = <26 2>;
765 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 765 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
766 interrupt-map = < 766 interrupt-map = <
767 /* IDSEL 0x0 */ 767 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index c114c4ee9931..fd462efa9e61 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -457,7 +457,7 @@
457 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>; 457 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
458 clock-frequency = <33333333>; 458 clock-frequency = <33333333>;
459 interrupt-parent = <&mpic>; 459 interrupt-parent = <&mpic>;
460 interrupts = <26 2>; 460 interrupts = <25 2>;
461 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 461 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
462 interrupt-map = < 462 interrupt-map = <
463 /* IDSEL 0x0 */ 463 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index 04ecda18d206..e35230f2ac93 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -208,7 +208,7 @@
208 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>; 208 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
209 clock-frequency = <33333333>; 209 clock-frequency = <33333333>;
210 interrupt-parent = <&mpic>; 210 interrupt-parent = <&mpic>;
211 interrupts = <27 2>; 211 interrupts = <26 2>;
212 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 212 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
213 interrupt-map = < 213 interrupt-map = <
214 /* IDSEL 0x0 */ 214 /* IDSEL 0x0 */
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index cd1ffa449327..391874c7b436 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -1164,6 +1164,7 @@ CONFIG_WATCHDOG=y
1164# CONFIG_SOFT_WATCHDOG is not set 1164# CONFIG_SOFT_WATCHDOG is not set
1165# CONFIG_ALIM7101_WDT is not set 1165# CONFIG_ALIM7101_WDT is not set
1166# CONFIG_8xxx_WDT is not set 1166# CONFIG_8xxx_WDT is not set
1167CONFIG_GEF_WDT=y
1167 1168
1168# 1169#
1169# PCI-based Watchdog Cards 1170# PCI-based Watchdog Cards
diff --git a/arch/powerpc/include/asm/cell-pmu.h b/arch/powerpc/include/asm/cell-pmu.h
index 8066eede3a0c..b4b7338ad79e 100644
--- a/arch/powerpc/include/asm/cell-pmu.h
+++ b/arch/powerpc/include/asm/cell-pmu.h
@@ -37,9 +37,11 @@
37#define CBE_PM_STOP_AT_MAX 0x40000000 37#define CBE_PM_STOP_AT_MAX 0x40000000
38#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3) 38#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
39#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28) 39#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
40#define CBE_PM_TRACE_BUF_OVFLW(bit) (((bit) & 0x1) << 17)
40#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18) 41#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
41#define CBE_PM_FREEZE_ALL_CTRS 0x00100000 42#define CBE_PM_FREEZE_ALL_CTRS 0x00100000
42#define CBE_PM_ENABLE_EXT_TRACE 0x00008000 43#define CBE_PM_ENABLE_EXT_TRACE 0x00008000
44#define CBE_PM_SPU_ADDR_TRACE_SET(msk) (((msk) & 0x3) << 9)
43 45
44/* Macros for the trace_address register. */ 46/* Macros for the trace_address register. */
45#define CBE_PM_TRACE_BUF_FULL 0x00000800 47#define CBE_PM_TRACE_BUF_FULL 0x00000800
diff --git a/arch/powerpc/include/asm/oprofile_impl.h b/arch/powerpc/include/asm/oprofile_impl.h
index 95035c602ba6..639dc96077ab 100644
--- a/arch/powerpc/include/asm/oprofile_impl.h
+++ b/arch/powerpc/include/asm/oprofile_impl.h
@@ -32,6 +32,12 @@ struct op_system_config {
32 unsigned long mmcr0; 32 unsigned long mmcr0;
33 unsigned long mmcr1; 33 unsigned long mmcr1;
34 unsigned long mmcra; 34 unsigned long mmcra;
35#ifdef CONFIG_OPROFILE_CELL
36 /* Register for oprofile user tool to check cell kernel profiling
37 * suport.
38 */
39 unsigned long cell_support;
40#endif
35#endif 41#endif
36 unsigned long enable_kernel; 42 unsigned long enable_kernel;
37 unsigned long enable_user; 43 unsigned long enable_user;
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index a0a15311d0d8..2701753d9937 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -624,7 +624,7 @@ struct ucc_slow_pram {
624#define UCC_GETH_UCCE_RXF1 0x00000002 624#define UCC_GETH_UCCE_RXF1 0x00000002
625#define UCC_GETH_UCCE_RXF0 0x00000001 625#define UCC_GETH_UCCE_RXF0 0x00000001
626 626
627/* UPSMR, when used as a UART */ 627/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
628#define UCC_UART_UPSMR_FLC 0x8000 628#define UCC_UART_UPSMR_FLC 0x8000
629#define UCC_UART_UPSMR_SL 0x4000 629#define UCC_UART_UPSMR_SL 0x4000
630#define UCC_UART_UPSMR_CL_MASK 0x3000 630#define UCC_UART_UPSMR_CL_MASK 0x3000
@@ -652,6 +652,23 @@ struct ucc_slow_pram {
652#define UCC_UART_UPSMR_TPM_EVEN 0x0002 652#define UCC_UART_UPSMR_TPM_EVEN 0x0002
653#define UCC_UART_UPSMR_TPM_HIGH 0x0003 653#define UCC_UART_UPSMR_TPM_HIGH 0x0003
654 654
655/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
656#define UCC_GETH_UPSMR_FTFE 0x80000000
657#define UCC_GETH_UPSMR_PTPE 0x40000000
658#define UCC_GETH_UPSMR_ECM 0x04000000
659#define UCC_GETH_UPSMR_HSE 0x02000000
660#define UCC_GETH_UPSMR_PRO 0x00400000
661#define UCC_GETH_UPSMR_CAP 0x00200000
662#define UCC_GETH_UPSMR_RSH 0x00100000
663#define UCC_GETH_UPSMR_RPM 0x00080000
664#define UCC_GETH_UPSMR_R10M 0x00040000
665#define UCC_GETH_UPSMR_RLPB 0x00020000
666#define UCC_GETH_UPSMR_TBIM 0x00010000
667#define UCC_GETH_UPSMR_RES1 0x00002000
668#define UCC_GETH_UPSMR_RMM 0x00001000
669#define UCC_GETH_UPSMR_CAM 0x00000400
670#define UCC_GETH_UPSMR_BRO 0x00000200
671
655/* UCC Transmit On Demand Register (UTODR) */ 672/* UCC Transmit On Demand Register (UTODR) */
656#define UCC_SLOW_TOD 0x8000 673#define UCC_SLOW_TOD 0x8000
657#define UCC_FAST_TOD 0x8000 674#define UCC_FAST_TOD 0x8000
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 9937fe44555f..19ee491e9e23 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -56,6 +56,10 @@
56#include "head_booke.h" 56#include "head_booke.h"
57#endif 57#endif
58 58
59#if defined(CONFIG_FSL_BOOKE)
60#include "../mm/mmu_decl.h"
61#endif
62
59int main(void) 63int main(void)
60{ 64{
61 DEFINE(THREAD, offsetof(struct task_struct, thread)); 65 DEFINE(THREAD, offsetof(struct task_struct, thread));
@@ -382,6 +386,9 @@ int main(void)
382 DEFINE(PGD_T_LOG2, PGD_T_LOG2); 386 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
383 DEFINE(PTE_T_LOG2, PTE_T_LOG2); 387 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
384#endif 388#endif
389#ifdef CONFIG_FSL_BOOKE
390 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
391#endif
385 392
386#ifdef CONFIG_KVM_EXIT_TIMING 393#ifdef CONFIG_KVM_EXIT_TIMING
387 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu, 394 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 11b549acc034..2f32720a44ae 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -389,10 +389,6 @@ skpinv: addi r6,r6,1 /* Increment */
389#endif 389#endif
390#endif 390#endif
391 391
392 mfspr r3,SPRN_TLB1CFG
393 andi. r3,r3,0xfff
394 lis r4,num_tlbcam_entries@ha
395 stw r3,num_tlbcam_entries@l(r4)
396/* 392/*
397 * Decide what sort of machine this is and initialize the MMU. 393 * Decide what sort of machine this is and initialize the MMU.
398 */ 394 */
@@ -909,7 +905,7 @@ KernelSPE:
909_GLOBAL(loadcam_entry) 905_GLOBAL(loadcam_entry)
910 lis r4,TLBCAM@ha 906 lis r4,TLBCAM@ha
911 addi r4,r4,TLBCAM@l 907 addi r4,r4,TLBCAM@l
912 mulli r5,r3,20 908 mulli r5,r3,TLBCAM_SIZE
913 add r3,r5,r4 909 add r3,r5,r4
914 lwz r4,0(r3) 910 lwz r4,0(r3)
915 mtspr SPRN_MAS0,r4 911 mtspr SPRN_MAS0,r4
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 23cee39534fd..1971e4ee3d6e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -56,18 +56,11 @@
56 56
57extern void loadcam_entry(unsigned int index); 57extern void loadcam_entry(unsigned int index);
58unsigned int tlbcam_index; 58unsigned int tlbcam_index;
59unsigned int num_tlbcam_entries;
60static unsigned long __cam0, __cam1, __cam2; 59static unsigned long __cam0, __cam1, __cam2;
61 60
62#define NUM_TLBCAMS (16) 61#define NUM_TLBCAMS (16)
63 62
64struct tlbcam { 63struct tlbcam TLBCAM[NUM_TLBCAMS];
65 u32 MAS0;
66 u32 MAS1;
67 u32 MAS2;
68 u32 MAS3;
69 u32 MAS7;
70} TLBCAM[NUM_TLBCAMS];
71 64
72struct tlbcamrange { 65struct tlbcamrange {
73 unsigned long start; 66 unsigned long start;
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index ad123bced404..d1f9c62dc177 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -75,6 +75,15 @@ extern void _tlbia(void);
75#endif /* CONFIG_PPC_MMU_NOHASH */ 75#endif /* CONFIG_PPC_MMU_NOHASH */
76 76
77#ifdef CONFIG_PPC32 77#ifdef CONFIG_PPC32
78
79struct tlbcam {
80 u32 MAS0;
81 u32 MAS1;
82 u32 MAS2;
83 u32 MAS3;
84 u32 MAS7;
85};
86
78extern void mapin_ram(void); 87extern void mapin_ram(void);
79extern int map_page(unsigned long va, phys_addr_t pa, int flags); 88extern int map_page(unsigned long va, phys_addr_t pa, int flags);
80extern void setbat(int index, unsigned long virt, phys_addr_t phys, 89extern void setbat(int index, unsigned long virt, phys_addr_t phys,
@@ -90,8 +99,6 @@ extern unsigned int rtas_data, rtas_size;
90struct hash_pte; 99struct hash_pte;
91extern struct hash_pte *Hash, *Hash_end; 100extern struct hash_pte *Hash, *Hash_end;
92extern unsigned long Hash_size, Hash_mask; 101extern unsigned long Hash_size, Hash_mask;
93
94extern unsigned int num_tlbcam_entries;
95#endif 102#endif
96 103
97extern unsigned long ioremap_bot; 104extern unsigned long ioremap_bot;
diff --git a/arch/powerpc/oprofile/cell/pr_util.h b/arch/powerpc/oprofile/cell/pr_util.h
index dfdbffa06818..964b93974d89 100644
--- a/arch/powerpc/oprofile/cell/pr_util.h
+++ b/arch/powerpc/oprofile/cell/pr_util.h
@@ -30,6 +30,10 @@
30extern struct delayed_work spu_work; 30extern struct delayed_work spu_work;
31extern int spu_prof_running; 31extern int spu_prof_running;
32 32
33#define TRACE_ARRAY_SIZE 1024
34
35extern spinlock_t oprof_spu_smpl_arry_lck;
36
33struct spu_overlay_info { /* map of sections within an SPU overlay */ 37struct spu_overlay_info { /* map of sections within an SPU overlay */
34 unsigned int vma; /* SPU virtual memory address from elf */ 38 unsigned int vma; /* SPU virtual memory address from elf */
35 unsigned int size; /* size of section from elf */ 39 unsigned int size; /* size of section from elf */
@@ -89,10 +93,11 @@ void vma_map_free(struct vma_to_fileoffset_map *map);
89 * Entry point for SPU profiling. 93 * Entry point for SPU profiling.
90 * cycles_reset is the SPU_CYCLES count value specified by the user. 94 * cycles_reset is the SPU_CYCLES count value specified by the user.
91 */ 95 */
92int start_spu_profiling(unsigned int cycles_reset); 96int start_spu_profiling_cycles(unsigned int cycles_reset);
93 97void start_spu_profiling_events(void);
94void stop_spu_profiling(void);
95 98
99void stop_spu_profiling_cycles(void);
100void stop_spu_profiling_events(void);
96 101
97/* add the necessary profiling hooks */ 102/* add the necessary profiling hooks */
98int spu_sync_start(void); 103int spu_sync_start(void);
diff --git a/arch/powerpc/oprofile/cell/spu_profiler.c b/arch/powerpc/oprofile/cell/spu_profiler.c
index 83faa958b9d4..9305ddaac512 100644
--- a/arch/powerpc/oprofile/cell/spu_profiler.c
+++ b/arch/powerpc/oprofile/cell/spu_profiler.c
@@ -18,11 +18,21 @@
18#include <asm/cell-pmu.h> 18#include <asm/cell-pmu.h>
19#include "pr_util.h" 19#include "pr_util.h"
20 20
21#define TRACE_ARRAY_SIZE 1024
22#define SCALE_SHIFT 14 21#define SCALE_SHIFT 14
23 22
24static u32 *samples; 23static u32 *samples;
25 24
25/* spu_prof_running is a flag used to indicate if spu profiling is enabled
26 * or not. It is set by the routines start_spu_profiling_cycles() and
27 * start_spu_profiling_events(). The flag is cleared by the routines
28 * stop_spu_profiling_cycles() and stop_spu_profiling_events(). These
29 * routines are called via global_start() and global_stop() which are called in
30 * op_powerpc_start() and op_powerpc_stop(). These routines are called once
31 * per system as a result of the user starting/stopping oprofile. Hence, only
32 * one CPU per user at a time will be changing the value of spu_prof_running.
33 * In general, OProfile does not protect against multiple users trying to run
34 * OProfile at a time.
35 */
26int spu_prof_running; 36int spu_prof_running;
27static unsigned int profiling_interval; 37static unsigned int profiling_interval;
28 38
@@ -31,8 +41,8 @@ static unsigned int profiling_interval;
31 41
32#define SPU_PC_MASK 0xFFFF 42#define SPU_PC_MASK 0xFFFF
33 43
34static DEFINE_SPINLOCK(sample_array_lock); 44DEFINE_SPINLOCK(oprof_spu_smpl_arry_lck);
35unsigned long sample_array_lock_flags; 45unsigned long oprof_spu_smpl_arry_lck_flags;
36 46
37void set_spu_profiling_frequency(unsigned int freq_khz, unsigned int cycles_reset) 47void set_spu_profiling_frequency(unsigned int freq_khz, unsigned int cycles_reset)
38{ 48{
@@ -145,13 +155,13 @@ static enum hrtimer_restart profile_spus(struct hrtimer *timer)
145 * sample array must be loaded and then processed for a given 155 * sample array must be loaded and then processed for a given
146 * cpu. The sample array is not per cpu. 156 * cpu. The sample array is not per cpu.
147 */ 157 */
148 spin_lock_irqsave(&sample_array_lock, 158 spin_lock_irqsave(&oprof_spu_smpl_arry_lck,
149 sample_array_lock_flags); 159 oprof_spu_smpl_arry_lck_flags);
150 num_samples = cell_spu_pc_collection(cpu); 160 num_samples = cell_spu_pc_collection(cpu);
151 161
152 if (num_samples == 0) { 162 if (num_samples == 0) {
153 spin_unlock_irqrestore(&sample_array_lock, 163 spin_unlock_irqrestore(&oprof_spu_smpl_arry_lck,
154 sample_array_lock_flags); 164 oprof_spu_smpl_arry_lck_flags);
155 continue; 165 continue;
156 } 166 }
157 167
@@ -162,8 +172,8 @@ static enum hrtimer_restart profile_spus(struct hrtimer *timer)
162 num_samples); 172 num_samples);
163 } 173 }
164 174
165 spin_unlock_irqrestore(&sample_array_lock, 175 spin_unlock_irqrestore(&oprof_spu_smpl_arry_lck,
166 sample_array_lock_flags); 176 oprof_spu_smpl_arry_lck_flags);
167 177
168 } 178 }
169 smp_wmb(); /* insure spu event buffer updates are written */ 179 smp_wmb(); /* insure spu event buffer updates are written */
@@ -182,13 +192,13 @@ static enum hrtimer_restart profile_spus(struct hrtimer *timer)
182 192
183static struct hrtimer timer; 193static struct hrtimer timer;
184/* 194/*
185 * Entry point for SPU profiling. 195 * Entry point for SPU cycle profiling.
186 * NOTE: SPU profiling is done system-wide, not per-CPU. 196 * NOTE: SPU profiling is done system-wide, not per-CPU.
187 * 197 *
188 * cycles_reset is the count value specified by the user when 198 * cycles_reset is the count value specified by the user when
189 * setting up OProfile to count SPU_CYCLES. 199 * setting up OProfile to count SPU_CYCLES.
190 */ 200 */
191int start_spu_profiling(unsigned int cycles_reset) 201int start_spu_profiling_cycles(unsigned int cycles_reset)
192{ 202{
193 ktime_t kt; 203 ktime_t kt;
194 204
@@ -212,10 +222,30 @@ int start_spu_profiling(unsigned int cycles_reset)
212 return 0; 222 return 0;
213} 223}
214 224
215void stop_spu_profiling(void) 225/*
226 * Entry point for SPU event profiling.
227 * NOTE: SPU profiling is done system-wide, not per-CPU.
228 *
229 * cycles_reset is the count value specified by the user when
230 * setting up OProfile to count SPU_CYCLES.
231 */
232void start_spu_profiling_events(void)
233{
234 spu_prof_running = 1;
235 schedule_delayed_work(&spu_work, DEFAULT_TIMER_EXPIRE);
236
237 return;
238}
239
240void stop_spu_profiling_cycles(void)
216{ 241{
217 spu_prof_running = 0; 242 spu_prof_running = 0;
218 hrtimer_cancel(&timer); 243 hrtimer_cancel(&timer);
219 kfree(samples); 244 kfree(samples);
220 pr_debug("SPU_PROF: stop_spu_profiling issued\n"); 245 pr_debug("SPU_PROF: stop_spu_profiling_cycles issued\n");
246}
247
248void stop_spu_profiling_events(void)
249{
250 spu_prof_running = 0;
221} 251}
diff --git a/arch/powerpc/oprofile/common.c b/arch/powerpc/oprofile/common.c
index 17807acb05d9..21f16edf6c8d 100644
--- a/arch/powerpc/oprofile/common.c
+++ b/arch/powerpc/oprofile/common.c
@@ -132,6 +132,28 @@ static int op_powerpc_create_files(struct super_block *sb, struct dentry *root)
132 oprofilefs_create_ulong(sb, root, "mmcr0", &sys.mmcr0); 132 oprofilefs_create_ulong(sb, root, "mmcr0", &sys.mmcr0);
133 oprofilefs_create_ulong(sb, root, "mmcr1", &sys.mmcr1); 133 oprofilefs_create_ulong(sb, root, "mmcr1", &sys.mmcr1);
134 oprofilefs_create_ulong(sb, root, "mmcra", &sys.mmcra); 134 oprofilefs_create_ulong(sb, root, "mmcra", &sys.mmcra);
135#ifdef CONFIG_OPROFILE_CELL
136 /* create a file the user tool can check to see what level of profiling
137 * support exits with this kernel. Initialize bit mask to indicate
138 * what support the kernel has:
139 * bit 0 - Supports SPU event profiling in addition to PPU
140 * event and cycles; and SPU cycle profiling
141 * bits 1-31 - Currently unused.
142 *
143 * If the file does not exist, then the kernel only supports SPU
144 * cycle profiling, PPU event and cycle profiling.
145 */
146 oprofilefs_create_ulong(sb, root, "cell_support", &sys.cell_support);
147 sys.cell_support = 0x1; /* Note, the user OProfile tool must check
148 * that this bit is set before attempting to
149 * user SPU event profiling. Older kernels
150 * will not have this file, hence the user
151 * tool is not allowed to do SPU event
152 * profiling on older kernels. Older kernels
153 * will accept SPU events but collected data
154 * is garbage.
155 */
156#endif
135#endif 157#endif
136 158
137 for (i = 0; i < model->num_counters; ++i) { 159 for (i = 0; i < model->num_counters; ++i) {
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index 25a4ec2514a3..ae06c6236d9c 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -40,14 +40,15 @@
40#include "../platforms/cell/interrupt.h" 40#include "../platforms/cell/interrupt.h"
41#include "cell/pr_util.h" 41#include "cell/pr_util.h"
42 42
43static void cell_global_stop_spu(void); 43#define PPU_PROFILING 0
44#define SPU_PROFILING_CYCLES 1
45#define SPU_PROFILING_EVENTS 2
44 46
45/* 47#define SPU_EVENT_NUM_START 4100
46 * spu_cycle_reset is the number of cycles between samples. 48#define SPU_EVENT_NUM_STOP 4399
47 * This variable is used for SPU profiling and should ONLY be set 49#define SPU_PROFILE_EVENT_ADDR 4363 /* spu, address trace, decimal */
48 * at the beginning of cell_reg_setup; otherwise, it's read-only. 50#define SPU_PROFILE_EVENT_ADDR_MASK_A 0x146 /* sub unit set to zero */
49 */ 51#define SPU_PROFILE_EVENT_ADDR_MASK_B 0x186 /* sub unit set to zero */
50static unsigned int spu_cycle_reset;
51 52
52#define NUM_SPUS_PER_NODE 8 53#define NUM_SPUS_PER_NODE 8
53#define SPU_CYCLES_EVENT_NUM 2 /* event number for SPU_CYCLES */ 54#define SPU_CYCLES_EVENT_NUM 2 /* event number for SPU_CYCLES */
@@ -66,6 +67,21 @@ static unsigned int spu_cycle_reset;
66 67
67#define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */ 68#define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */
68 69
70/* Minumum HW interval timer setting to send value to trace buffer is 10 cycle.
71 * To configure counter to send value every N cycles set counter to
72 * 2^32 - 1 - N.
73 */
74#define NUM_INTERVAL_CYC 0xFFFFFFFF - 10
75
76/*
77 * spu_cycle_reset is the number of cycles between samples.
78 * This variable is used for SPU profiling and should ONLY be set
79 * at the beginning of cell_reg_setup; otherwise, it's read-only.
80 */
81static unsigned int spu_cycle_reset;
82static unsigned int profiling_mode;
83static int spu_evnt_phys_spu_indx;
84
69struct pmc_cntrl_data { 85struct pmc_cntrl_data {
70 unsigned long vcntr; 86 unsigned long vcntr;
71 unsigned long evnts; 87 unsigned long evnts;
@@ -105,6 +121,8 @@ struct pm_cntrl {
105 u16 trace_mode; 121 u16 trace_mode;
106 u16 freeze; 122 u16 freeze;
107 u16 count_mode; 123 u16 count_mode;
124 u16 spu_addr_trace;
125 u8 trace_buf_ovflw;
108}; 126};
109 127
110static struct { 128static struct {
@@ -122,7 +140,7 @@ static struct {
122#define GET_INPUT_CONTROL(x) ((x & 0x00000004) >> 2) 140#define GET_INPUT_CONTROL(x) ((x & 0x00000004) >> 2)
123 141
124static DEFINE_PER_CPU(unsigned long[NR_PHYS_CTRS], pmc_values); 142static DEFINE_PER_CPU(unsigned long[NR_PHYS_CTRS], pmc_values);
125 143static unsigned long spu_pm_cnt[MAX_NUMNODES * NUM_SPUS_PER_NODE];
126static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS]; 144static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS];
127 145
128/* 146/*
@@ -152,6 +170,7 @@ static u32 hdw_thread;
152 170
153static u32 virt_cntr_inter_mask; 171static u32 virt_cntr_inter_mask;
154static struct timer_list timer_virt_cntr; 172static struct timer_list timer_virt_cntr;
173static struct timer_list timer_spu_event_swap;
155 174
156/* 175/*
157 * pm_signal needs to be global since it is initialized in 176 * pm_signal needs to be global since it is initialized in
@@ -165,7 +184,7 @@ static int spu_rtas_token; /* token for SPU cycle profiling */
165static u32 reset_value[NR_PHYS_CTRS]; 184static u32 reset_value[NR_PHYS_CTRS];
166static int num_counters; 185static int num_counters;
167static int oprofile_running; 186static int oprofile_running;
168static DEFINE_SPINLOCK(virt_cntr_lock); 187static DEFINE_SPINLOCK(cntr_lock);
169 188
170static u32 ctr_enabled; 189static u32 ctr_enabled;
171 190
@@ -336,13 +355,13 @@ static void set_pm_event(u32 ctr, int event, u32 unit_mask)
336 for (i = 0; i < NUM_DEBUG_BUS_WORDS; i++) { 355 for (i = 0; i < NUM_DEBUG_BUS_WORDS; i++) {
337 if (bus_word & (1 << i)) { 356 if (bus_word & (1 << i)) {
338 pm_regs.debug_bus_control |= 357 pm_regs.debug_bus_control |=
339 (bus_type << (30 - (2 * i))); 358 (bus_type << (30 - (2 * i)));
340 359
341 for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) { 360 for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) {
342 if (input_bus[j] == 0xff) { 361 if (input_bus[j] == 0xff) {
343 input_bus[j] = i; 362 input_bus[j] = i;
344 pm_regs.group_control |= 363 pm_regs.group_control |=
345 (i << (30 - (2 * j))); 364 (i << (30 - (2 * j)));
346 365
347 break; 366 break;
348 } 367 }
@@ -367,12 +386,16 @@ static void write_pm_cntrl(int cpu)
367 if (pm_regs.pm_cntrl.stop_at_max == 1) 386 if (pm_regs.pm_cntrl.stop_at_max == 1)
368 val |= CBE_PM_STOP_AT_MAX; 387 val |= CBE_PM_STOP_AT_MAX;
369 388
370 if (pm_regs.pm_cntrl.trace_mode == 1) 389 if (pm_regs.pm_cntrl.trace_mode != 0)
371 val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode); 390 val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode);
372 391
392 if (pm_regs.pm_cntrl.trace_buf_ovflw == 1)
393 val |= CBE_PM_TRACE_BUF_OVFLW(pm_regs.pm_cntrl.trace_buf_ovflw);
373 if (pm_regs.pm_cntrl.freeze == 1) 394 if (pm_regs.pm_cntrl.freeze == 1)
374 val |= CBE_PM_FREEZE_ALL_CTRS; 395 val |= CBE_PM_FREEZE_ALL_CTRS;
375 396
397 val |= CBE_PM_SPU_ADDR_TRACE_SET(pm_regs.pm_cntrl.spu_addr_trace);
398
376 /* 399 /*
377 * Routine set_count_mode must be called previously to set 400 * Routine set_count_mode must be called previously to set
378 * the count mode based on the user selection of user and kernel. 401 * the count mode based on the user selection of user and kernel.
@@ -441,7 +464,7 @@ static void cell_virtual_cntr(unsigned long data)
441 * not both playing with the counters on the same node. 464 * not both playing with the counters on the same node.
442 */ 465 */
443 466
444 spin_lock_irqsave(&virt_cntr_lock, flags); 467 spin_lock_irqsave(&cntr_lock, flags);
445 468
446 prev_hdw_thread = hdw_thread; 469 prev_hdw_thread = hdw_thread;
447 470
@@ -480,7 +503,7 @@ static void cell_virtual_cntr(unsigned long data)
480 cbe_disable_pm_interrupts(cpu); 503 cbe_disable_pm_interrupts(cpu);
481 for (i = 0; i < num_counters; i++) { 504 for (i = 0; i < num_counters; i++) {
482 per_cpu(pmc_values, cpu + prev_hdw_thread)[i] 505 per_cpu(pmc_values, cpu + prev_hdw_thread)[i]
483 = cbe_read_ctr(cpu, i); 506 = cbe_read_ctr(cpu, i);
484 507
485 if (per_cpu(pmc_values, cpu + next_hdw_thread)[i] 508 if (per_cpu(pmc_values, cpu + next_hdw_thread)[i]
486 == 0xFFFFFFFF) 509 == 0xFFFFFFFF)
@@ -527,7 +550,7 @@ static void cell_virtual_cntr(unsigned long data)
527 cbe_enable_pm(cpu); 550 cbe_enable_pm(cpu);
528 } 551 }
529 552
530 spin_unlock_irqrestore(&virt_cntr_lock, flags); 553 spin_unlock_irqrestore(&cntr_lock, flags);
531 554
532 mod_timer(&timer_virt_cntr, jiffies + HZ / 10); 555 mod_timer(&timer_virt_cntr, jiffies + HZ / 10);
533} 556}
@@ -541,38 +564,146 @@ static void start_virt_cntrs(void)
541 add_timer(&timer_virt_cntr); 564 add_timer(&timer_virt_cntr);
542} 565}
543 566
544/* This function is called once for all cpus combined */ 567static int cell_reg_setup_spu_cycles(struct op_counter_config *ctr,
545static int cell_reg_setup(struct op_counter_config *ctr,
546 struct op_system_config *sys, int num_ctrs) 568 struct op_system_config *sys, int num_ctrs)
547{ 569{
548 int i, j, cpu; 570 spu_cycle_reset = ctr[0].count;
549 spu_cycle_reset = 0;
550 571
551 if (ctr[0].event == SPU_CYCLES_EVENT_NUM) { 572 /*
552 spu_cycle_reset = ctr[0].count; 573 * Each node will need to make the rtas call to start
574 * and stop SPU profiling. Get the token once and store it.
575 */
576 spu_rtas_token = rtas_token("ibm,cbe-spu-perftools");
577
578 if (unlikely(spu_rtas_token == RTAS_UNKNOWN_SERVICE)) {
579 printk(KERN_ERR
580 "%s: rtas token ibm,cbe-spu-perftools unknown\n",
581 __func__);
582 return -EIO;
583 }
584 return 0;
585}
586
587/* Unfortunately, the hardware will only support event profiling
588 * on one SPU per node at a time. Therefore, we must time slice
589 * the profiling across all SPUs in the node. Note, we do this
590 * in parallel for each node. The following routine is called
591 * periodically based on kernel timer to switch which SPU is
592 * being monitored in a round robbin fashion.
593 */
594static void spu_evnt_swap(unsigned long data)
595{
596 int node;
597 int cur_phys_spu, nxt_phys_spu, cur_spu_evnt_phys_spu_indx;
598 unsigned long flags;
599 int cpu;
600 int ret;
601 u32 interrupt_mask;
602
603
604 /* enable interrupts on cntr 0 */
605 interrupt_mask = CBE_PM_CTR_OVERFLOW_INTR(0);
606
607 hdw_thread = 0;
608
609 /* Make sure spu event interrupt handler and spu event swap
610 * don't access the counters simultaneously.
611 */
612 spin_lock_irqsave(&cntr_lock, flags);
613
614 cur_spu_evnt_phys_spu_indx = spu_evnt_phys_spu_indx;
615
616 if (++(spu_evnt_phys_spu_indx) == NUM_SPUS_PER_NODE)
617 spu_evnt_phys_spu_indx = 0;
618
619 pm_signal[0].sub_unit = spu_evnt_phys_spu_indx;
620 pm_signal[1].sub_unit = spu_evnt_phys_spu_indx;
621 pm_signal[2].sub_unit = spu_evnt_phys_spu_indx;
622
623 /* switch the SPU being profiled on each node */
624 for_each_online_cpu(cpu) {
625 if (cbe_get_hw_thread_id(cpu))
626 continue;
627
628 node = cbe_cpu_to_node(cpu);
629 cur_phys_spu = (node * NUM_SPUS_PER_NODE)
630 + cur_spu_evnt_phys_spu_indx;
631 nxt_phys_spu = (node * NUM_SPUS_PER_NODE)
632 + spu_evnt_phys_spu_indx;
553 633
554 /* 634 /*
555 * Each node will need to make the rtas call to start 635 * stop counters, save counter values, restore counts
556 * and stop SPU profiling. Get the token once and store it. 636 * for previous physical SPU
557 */ 637 */
558 spu_rtas_token = rtas_token("ibm,cbe-spu-perftools"); 638 cbe_disable_pm(cpu);
639 cbe_disable_pm_interrupts(cpu);
559 640
560 if (unlikely(spu_rtas_token == RTAS_UNKNOWN_SERVICE)) { 641 spu_pm_cnt[cur_phys_spu]
561 printk(KERN_ERR 642 = cbe_read_ctr(cpu, 0);
562 "%s: rtas token ibm,cbe-spu-perftools unknown\n", 643
563 __func__); 644 /* restore previous count for the next spu to sample */
564 return -EIO; 645 /* NOTE, hardware issue, counter will not start if the
565 } 646 * counter value is at max (0xFFFFFFFF).
647 */
648 if (spu_pm_cnt[nxt_phys_spu] >= 0xFFFFFFFF)
649 cbe_write_ctr(cpu, 0, 0xFFFFFFF0);
650 else
651 cbe_write_ctr(cpu, 0, spu_pm_cnt[nxt_phys_spu]);
652
653 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
654
655 /* setup the debug bus measure the one event and
656 * the two events to route the next SPU's PC on
657 * the debug bus
658 */
659 ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu), 3);
660 if (ret)
661 printk(KERN_ERR "%s: pm_rtas_activate_signals failed, "
662 "SPU event swap\n", __func__);
663
664 /* clear the trace buffer, don't want to take PC for
665 * previous SPU*/
666 cbe_write_pm(cpu, trace_address, 0);
667
668 enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
669
670 /* Enable interrupts on the CPU thread that is starting */
671 cbe_enable_pm_interrupts(cpu, hdw_thread,
672 interrupt_mask);
673 cbe_enable_pm(cpu);
566 } 674 }
567 675
568 pm_rtas_token = rtas_token("ibm,cbe-perftools"); 676 spin_unlock_irqrestore(&cntr_lock, flags);
569 677
678 /* swap approximately every 0.1 seconds */
679 mod_timer(&timer_spu_event_swap, jiffies + HZ / 25);
680}
681
682static void start_spu_event_swap(void)
683{
684 init_timer(&timer_spu_event_swap);
685 timer_spu_event_swap.function = spu_evnt_swap;
686 timer_spu_event_swap.data = 0UL;
687 timer_spu_event_swap.expires = jiffies + HZ / 25;
688 add_timer(&timer_spu_event_swap);
689}
690
691static int cell_reg_setup_spu_events(struct op_counter_config *ctr,
692 struct op_system_config *sys, int num_ctrs)
693{
694 int i;
695
696 /* routine is called once for all nodes */
697
698 spu_evnt_phys_spu_indx = 0;
570 /* 699 /*
571 * For all events excetp PPU CYCLEs, each node will need to make 700 * For all events except PPU CYCLEs, each node will need to make
572 * the rtas cbe-perftools call to setup and reset the debug bus. 701 * the rtas cbe-perftools call to setup and reset the debug bus.
573 * Make the token lookup call once and store it in the global 702 * Make the token lookup call once and store it in the global
574 * variable pm_rtas_token. 703 * variable pm_rtas_token.
575 */ 704 */
705 pm_rtas_token = rtas_token("ibm,cbe-perftools");
706
576 if (unlikely(pm_rtas_token == RTAS_UNKNOWN_SERVICE)) { 707 if (unlikely(pm_rtas_token == RTAS_UNKNOWN_SERVICE)) {
577 printk(KERN_ERR 708 printk(KERN_ERR
578 "%s: rtas token ibm,cbe-perftools unknown\n", 709 "%s: rtas token ibm,cbe-perftools unknown\n",
@@ -580,6 +711,58 @@ static int cell_reg_setup(struct op_counter_config *ctr,
580 return -EIO; 711 return -EIO;
581 } 712 }
582 713
714 /* setup the pm_control register settings,
715 * settings will be written per node by the
716 * cell_cpu_setup() function.
717 */
718 pm_regs.pm_cntrl.trace_buf_ovflw = 1;
719
720 /* Use the occurrence trace mode to have SPU PC saved
721 * to the trace buffer. Occurrence data in trace buffer
722 * is not used. Bit 2 must be set to store SPU addresses.
723 */
724 pm_regs.pm_cntrl.trace_mode = 2;
725
726 pm_regs.pm_cntrl.spu_addr_trace = 0x1; /* using debug bus
727 event 2 & 3 */
728
729 /* setup the debug bus event array with the SPU PC routing events.
730 * Note, pm_signal[0] will be filled in by set_pm_event() call below.
731 */
732 pm_signal[1].signal_group = SPU_PROFILE_EVENT_ADDR / 100;
733 pm_signal[1].bus_word = GET_BUS_WORD(SPU_PROFILE_EVENT_ADDR_MASK_A);
734 pm_signal[1].bit = SPU_PROFILE_EVENT_ADDR % 100;
735 pm_signal[1].sub_unit = spu_evnt_phys_spu_indx;
736
737 pm_signal[2].signal_group = SPU_PROFILE_EVENT_ADDR / 100;
738 pm_signal[2].bus_word = GET_BUS_WORD(SPU_PROFILE_EVENT_ADDR_MASK_B);
739 pm_signal[2].bit = SPU_PROFILE_EVENT_ADDR % 100;
740 pm_signal[2].sub_unit = spu_evnt_phys_spu_indx;
741
742 /* Set the user selected spu event to profile on,
743 * note, only one SPU profiling event is supported
744 */
745 num_counters = 1; /* Only support one SPU event at a time */
746 set_pm_event(0, ctr[0].event, ctr[0].unit_mask);
747
748 reset_value[0] = 0xFFFFFFFF - ctr[0].count;
749
750 /* global, used by cell_cpu_setup */
751 ctr_enabled |= 1;
752
753 /* Initialize the count for each SPU to the reset value */
754 for (i=0; i < MAX_NUMNODES * NUM_SPUS_PER_NODE; i++)
755 spu_pm_cnt[i] = reset_value[0];
756
757 return 0;
758}
759
760static int cell_reg_setup_ppu(struct op_counter_config *ctr,
761 struct op_system_config *sys, int num_ctrs)
762{
763 /* routine is called once for all nodes */
764 int i, j, cpu;
765
583 num_counters = num_ctrs; 766 num_counters = num_ctrs;
584 767
585 if (unlikely(num_ctrs > NR_PHYS_CTRS)) { 768 if (unlikely(num_ctrs > NR_PHYS_CTRS)) {
@@ -589,14 +772,6 @@ static int cell_reg_setup(struct op_counter_config *ctr,
589 __func__); 772 __func__);
590 return -EIO; 773 return -EIO;
591 } 774 }
592 pm_regs.group_control = 0;
593 pm_regs.debug_bus_control = 0;
594
595 /* setup the pm_control register */
596 memset(&pm_regs.pm_cntrl, 0, sizeof(struct pm_cntrl));
597 pm_regs.pm_cntrl.stop_at_max = 1;
598 pm_regs.pm_cntrl.trace_mode = 0;
599 pm_regs.pm_cntrl.freeze = 1;
600 775
601 set_count_mode(sys->enable_kernel, sys->enable_user); 776 set_count_mode(sys->enable_kernel, sys->enable_user);
602 777
@@ -665,6 +840,63 @@ static int cell_reg_setup(struct op_counter_config *ctr,
665} 840}
666 841
667 842
843/* This function is called once for all cpus combined */
844static int cell_reg_setup(struct op_counter_config *ctr,
845 struct op_system_config *sys, int num_ctrs)
846{
847 int ret=0;
848 spu_cycle_reset = 0;
849
850 /* initialize the spu_arr_trace value, will be reset if
851 * doing spu event profiling.
852 */
853 pm_regs.group_control = 0;
854 pm_regs.debug_bus_control = 0;
855 pm_regs.pm_cntrl.stop_at_max = 1;
856 pm_regs.pm_cntrl.trace_mode = 0;
857 pm_regs.pm_cntrl.freeze = 1;
858 pm_regs.pm_cntrl.trace_buf_ovflw = 0;
859 pm_regs.pm_cntrl.spu_addr_trace = 0;
860
861 /*
862 * For all events except PPU CYCLEs, each node will need to make
863 * the rtas cbe-perftools call to setup and reset the debug bus.
864 * Make the token lookup call once and store it in the global
865 * variable pm_rtas_token.
866 */
867 pm_rtas_token = rtas_token("ibm,cbe-perftools");
868
869 if (unlikely(pm_rtas_token == RTAS_UNKNOWN_SERVICE)) {
870 printk(KERN_ERR
871 "%s: rtas token ibm,cbe-perftools unknown\n",
872 __func__);
873 return -EIO;
874 }
875
876 if (ctr[0].event == SPU_CYCLES_EVENT_NUM) {
877 profiling_mode = SPU_PROFILING_CYCLES;
878 ret = cell_reg_setup_spu_cycles(ctr, sys, num_ctrs);
879 } else if ((ctr[0].event >= SPU_EVENT_NUM_START) &&
880 (ctr[0].event <= SPU_EVENT_NUM_STOP)) {
881 profiling_mode = SPU_PROFILING_EVENTS;
882 spu_cycle_reset = ctr[0].count;
883
884 /* for SPU event profiling, need to setup the
885 * pm_signal array with the events to route the
886 * SPU PC before making the FW call. Note, only
887 * one SPU event for profiling can be specified
888 * at a time.
889 */
890 cell_reg_setup_spu_events(ctr, sys, num_ctrs);
891 } else {
892 profiling_mode = PPU_PROFILING;
893 ret = cell_reg_setup_ppu(ctr, sys, num_ctrs);
894 }
895
896 return ret;
897}
898
899
668 900
669/* This function is called once for each cpu */ 901/* This function is called once for each cpu */
670static int cell_cpu_setup(struct op_counter_config *cntr) 902static int cell_cpu_setup(struct op_counter_config *cntr)
@@ -672,8 +904,13 @@ static int cell_cpu_setup(struct op_counter_config *cntr)
672 u32 cpu = smp_processor_id(); 904 u32 cpu = smp_processor_id();
673 u32 num_enabled = 0; 905 u32 num_enabled = 0;
674 int i; 906 int i;
907 int ret;
675 908
676 if (spu_cycle_reset) 909 /* Cycle based SPU profiling does not use the performance
910 * counters. The trace array is configured to collect
911 * the data.
912 */
913 if (profiling_mode == SPU_PROFILING_CYCLES)
677 return 0; 914 return 0;
678 915
679 /* There is one performance monitor per processor chip (i.e. node), 916 /* There is one performance monitor per processor chip (i.e. node),
@@ -686,7 +923,6 @@ static int cell_cpu_setup(struct op_counter_config *cntr)
686 cbe_disable_pm(cpu); 923 cbe_disable_pm(cpu);
687 cbe_disable_pm_interrupts(cpu); 924 cbe_disable_pm_interrupts(cpu);
688 925
689 cbe_write_pm(cpu, pm_interval, 0);
690 cbe_write_pm(cpu, pm_start_stop, 0); 926 cbe_write_pm(cpu, pm_start_stop, 0);
691 cbe_write_pm(cpu, group_control, pm_regs.group_control); 927 cbe_write_pm(cpu, group_control, pm_regs.group_control);
692 cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control); 928 cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);
@@ -703,7 +939,20 @@ static int cell_cpu_setup(struct op_counter_config *cntr)
703 * The pm_rtas_activate_signals will return -EIO if the FW 939 * The pm_rtas_activate_signals will return -EIO if the FW
704 * call failed. 940 * call failed.
705 */ 941 */
706 return pm_rtas_activate_signals(cbe_cpu_to_node(cpu), num_enabled); 942 if (profiling_mode == SPU_PROFILING_EVENTS) {
943 /* For SPU event profiling also need to setup the
944 * pm interval timer
945 */
946 ret = pm_rtas_activate_signals(cbe_cpu_to_node(cpu),
947 num_enabled+2);
948 /* store PC from debug bus to Trace buffer as often
949 * as possible (every 10 cycles)
950 */
951 cbe_write_pm(cpu, pm_interval, NUM_INTERVAL_CYC);
952 return ret;
953 } else
954 return pm_rtas_activate_signals(cbe_cpu_to_node(cpu),
955 num_enabled);
707} 956}
708 957
709#define ENTRIES 303 958#define ENTRIES 303
@@ -885,7 +1134,122 @@ static struct notifier_block cpu_freq_notifier_block = {
885}; 1134};
886#endif 1135#endif
887 1136
888static int cell_global_start_spu(struct op_counter_config *ctr) 1137/*
1138 * Note the generic OProfile stop calls do not support returning
1139 * an error on stop. Hence, will not return an error if the FW
1140 * calls fail on stop. Failure to reset the debug bus is not an issue.
1141 * Failure to disable the SPU profiling is not an issue. The FW calls
1142 * to enable the performance counters and debug bus will work even if
1143 * the hardware was not cleanly reset.
1144 */
1145static void cell_global_stop_spu_cycles(void)
1146{
1147 int subfunc, rtn_value;
1148 unsigned int lfsr_value;
1149 int cpu;
1150
1151 oprofile_running = 0;
1152 smp_wmb();
1153
1154#ifdef CONFIG_CPU_FREQ
1155 cpufreq_unregister_notifier(&cpu_freq_notifier_block,
1156 CPUFREQ_TRANSITION_NOTIFIER);
1157#endif
1158
1159 for_each_online_cpu(cpu) {
1160 if (cbe_get_hw_thread_id(cpu))
1161 continue;
1162
1163 subfunc = 3; /*
1164 * 2 - activate SPU tracing,
1165 * 3 - deactivate
1166 */
1167 lfsr_value = 0x8f100000;
1168
1169 rtn_value = rtas_call(spu_rtas_token, 3, 1, NULL,
1170 subfunc, cbe_cpu_to_node(cpu),
1171 lfsr_value);
1172
1173 if (unlikely(rtn_value != 0)) {
1174 printk(KERN_ERR
1175 "%s: rtas call ibm,cbe-spu-perftools " \
1176 "failed, return = %d\n",
1177 __func__, rtn_value);
1178 }
1179
1180 /* Deactivate the signals */
1181 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
1182 }
1183
1184 stop_spu_profiling_cycles();
1185}
1186
1187static void cell_global_stop_spu_events(void)
1188{
1189 int cpu;
1190 oprofile_running = 0;
1191
1192 stop_spu_profiling_events();
1193 smp_wmb();
1194
1195 for_each_online_cpu(cpu) {
1196 if (cbe_get_hw_thread_id(cpu))
1197 continue;
1198
1199 cbe_sync_irq(cbe_cpu_to_node(cpu));
1200 /* Stop the counters */
1201 cbe_disable_pm(cpu);
1202 cbe_write_pm07_control(cpu, 0, 0);
1203
1204 /* Deactivate the signals */
1205 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
1206
1207 /* Deactivate interrupts */
1208 cbe_disable_pm_interrupts(cpu);
1209 }
1210 del_timer_sync(&timer_spu_event_swap);
1211}
1212
1213static void cell_global_stop_ppu(void)
1214{
1215 int cpu;
1216
1217 /*
1218 * This routine will be called once for the system.
1219 * There is one performance monitor per node, so we
1220 * only need to perform this function once per node.
1221 */
1222 del_timer_sync(&timer_virt_cntr);
1223 oprofile_running = 0;
1224 smp_wmb();
1225
1226 for_each_online_cpu(cpu) {
1227 if (cbe_get_hw_thread_id(cpu))
1228 continue;
1229
1230 cbe_sync_irq(cbe_cpu_to_node(cpu));
1231 /* Stop the counters */
1232 cbe_disable_pm(cpu);
1233
1234 /* Deactivate the signals */
1235 pm_rtas_reset_signals(cbe_cpu_to_node(cpu));
1236
1237 /* Deactivate interrupts */
1238 cbe_disable_pm_interrupts(cpu);
1239 }
1240}
1241
1242static void cell_global_stop(void)
1243{
1244 if (profiling_mode == PPU_PROFILING)
1245 cell_global_stop_ppu();
1246 else if (profiling_mode == SPU_PROFILING_EVENTS)
1247 cell_global_stop_spu_events();
1248 else
1249 cell_global_stop_spu_cycles();
1250}
1251
1252static int cell_global_start_spu_cycles(struct op_counter_config *ctr)
889{ 1253{
890 int subfunc; 1254 int subfunc;
891 unsigned int lfsr_value; 1255 unsigned int lfsr_value;
@@ -951,18 +1315,18 @@ static int cell_global_start_spu(struct op_counter_config *ctr)
951 1315
952 /* start profiling */ 1316 /* start profiling */
953 ret = rtas_call(spu_rtas_token, 3, 1, NULL, subfunc, 1317 ret = rtas_call(spu_rtas_token, 3, 1, NULL, subfunc,
954 cbe_cpu_to_node(cpu), lfsr_value); 1318 cbe_cpu_to_node(cpu), lfsr_value);
955 1319
956 if (unlikely(ret != 0)) { 1320 if (unlikely(ret != 0)) {
957 printk(KERN_ERR 1321 printk(KERN_ERR
958 "%s: rtas call ibm,cbe-spu-perftools failed, return = %d\n", 1322 "%s: rtas call ibm,cbe-spu-perftools failed, " \
959 __func__, ret); 1323 "return = %d\n", __func__, ret);
960 rtas_error = -EIO; 1324 rtas_error = -EIO;
961 goto out; 1325 goto out;
962 } 1326 }
963 } 1327 }
964 1328
965 rtas_error = start_spu_profiling(spu_cycle_reset); 1329 rtas_error = start_spu_profiling_cycles(spu_cycle_reset);
966 if (rtas_error) 1330 if (rtas_error)
967 goto out_stop; 1331 goto out_stop;
968 1332
@@ -970,11 +1334,74 @@ static int cell_global_start_spu(struct op_counter_config *ctr)
970 return 0; 1334 return 0;
971 1335
972out_stop: 1336out_stop:
973 cell_global_stop_spu(); /* clean up the PMU/debug bus */ 1337 cell_global_stop_spu_cycles(); /* clean up the PMU/debug bus */
974out: 1338out:
975 return rtas_error; 1339 return rtas_error;
976} 1340}
977 1341
1342static int cell_global_start_spu_events(struct op_counter_config *ctr)
1343{
1344 int cpu;
1345 u32 interrupt_mask = 0;
1346 int rtn = 0;
1347
1348 hdw_thread = 0;
1349
1350 /* spu event profiling, uses the performance counters to generate
1351 * an interrupt. The hardware is setup to store the SPU program
1352 * counter into the trace array. The occurrence mode is used to
1353 * enable storing data to the trace buffer. The bits are set
1354 * to send/store the SPU address in the trace buffer. The debug
1355 * bus must be setup to route the SPU program counter onto the
1356 * debug bus. The occurrence data in the trace buffer is not used.
1357 */
1358
1359 /* This routine gets called once for the system.
1360 * There is one performance monitor per node, so we
1361 * only need to perform this function once per node.
1362 */
1363
1364 for_each_online_cpu(cpu) {
1365 if (cbe_get_hw_thread_id(cpu))
1366 continue;
1367
1368 /*
1369 * Setup SPU event-based profiling.
1370 * Set perf_mon_control bit 0 to a zero before
1371 * enabling spu collection hardware.
1372 *
1373 * Only support one SPU event on one SPU per node.
1374 */
1375 if (ctr_enabled & 1) {
1376 cbe_write_ctr(cpu, 0, reset_value[0]);
1377 enable_ctr(cpu, 0, pm_regs.pm07_cntrl);
1378 interrupt_mask |=
1379 CBE_PM_CTR_OVERFLOW_INTR(0);
1380 } else {
1381 /* Disable counter */
1382 cbe_write_pm07_control(cpu, 0, 0);
1383 }
1384
1385 cbe_get_and_clear_pm_interrupts(cpu);
1386 cbe_enable_pm_interrupts(cpu, hdw_thread, interrupt_mask);
1387 cbe_enable_pm(cpu);
1388
1389 /* clear the trace buffer */
1390 cbe_write_pm(cpu, trace_address, 0);
1391 }
1392
1393 /* Start the timer to time slice collecting the event profile
1394 * on each of the SPUs. Note, can collect profile on one SPU
1395 * per node at a time.
1396 */
1397 start_spu_event_swap();
1398 start_spu_profiling_events();
1399 oprofile_running = 1;
1400 smp_wmb();
1401
1402 return rtn;
1403}
1404
978static int cell_global_start_ppu(struct op_counter_config *ctr) 1405static int cell_global_start_ppu(struct op_counter_config *ctr)
979{ 1406{
980 u32 cpu, i; 1407 u32 cpu, i;
@@ -994,8 +1421,7 @@ static int cell_global_start_ppu(struct op_counter_config *ctr)
994 if (ctr_enabled & (1 << i)) { 1421 if (ctr_enabled & (1 << i)) {
995 cbe_write_ctr(cpu, i, reset_value[i]); 1422 cbe_write_ctr(cpu, i, reset_value[i]);
996 enable_ctr(cpu, i, pm_regs.pm07_cntrl); 1423 enable_ctr(cpu, i, pm_regs.pm07_cntrl);
997 interrupt_mask |= 1424 interrupt_mask |= CBE_PM_CTR_OVERFLOW_INTR(i);
998 CBE_PM_CTR_OVERFLOW_INTR(i);
999 } else { 1425 } else {
1000 /* Disable counter */ 1426 /* Disable counter */
1001 cbe_write_pm07_control(cpu, i, 0); 1427 cbe_write_pm07_control(cpu, i, 0);
@@ -1024,99 +1450,162 @@ static int cell_global_start_ppu(struct op_counter_config *ctr)
1024 1450
1025static int cell_global_start(struct op_counter_config *ctr) 1451static int cell_global_start(struct op_counter_config *ctr)
1026{ 1452{
1027 if (spu_cycle_reset) 1453 if (profiling_mode == SPU_PROFILING_CYCLES)
1028 return cell_global_start_spu(ctr); 1454 return cell_global_start_spu_cycles(ctr);
1455 else if (profiling_mode == SPU_PROFILING_EVENTS)
1456 return cell_global_start_spu_events(ctr);
1029 else 1457 else
1030 return cell_global_start_ppu(ctr); 1458 return cell_global_start_ppu(ctr);
1031} 1459}
1032 1460
1033/* 1461
1034 * Note the generic OProfile stop calls do not support returning 1462/* The SPU interrupt handler
1035 * an error on stop. Hence, will not return an error if the FW 1463 *
1036 * calls fail on stop. Failure to reset the debug bus is not an issue. 1464 * SPU event profiling works as follows:
1037 * Failure to disable the SPU profiling is not an issue. The FW calls 1465 * The pm_signal[0] holds the one SPU event to be measured. It is routed on
1038 * to enable the performance counters and debug bus will work even if 1466 * the debug bus using word 0 or 1. The value of pm_signal[1] and
1039 * the hardware was not cleanly reset. 1467 * pm_signal[2] contain the necessary events to route the SPU program
1468 * counter for the selected SPU onto the debug bus using words 2 and 3.
1469 * The pm_interval register is setup to write the SPU PC value into the
1470 * trace buffer at the maximum rate possible. The trace buffer is configured
1471 * to store the PCs, wrapping when it is full. The performance counter is
1472 * intialized to the max hardware count minus the number of events, N, between
1473 * samples. Once the N events have occured, a HW counter overflow occurs
1474 * causing the generation of a HW counter interrupt which also stops the
1475 * writing of the SPU PC values to the trace buffer. Hence the last PC
1476 * written to the trace buffer is the SPU PC that we want. Unfortunately,
1477 * we have to read from the beginning of the trace buffer to get to the
1478 * last value written. We just hope the PPU has nothing better to do then
1479 * service this interrupt. The PC for the specific SPU being profiled is
1480 * extracted from the trace buffer processed and stored. The trace buffer
1481 * is cleared, interrupts are cleared, the counter is reset to max - N.
1482 * A kernel timer is used to periodically call the routine spu_evnt_swap()
1483 * to switch to the next physical SPU in the node to profile in round robbin
1484 * order. This way data is collected for all SPUs on the node. It does mean
1485 * that we need to use a relatively small value of N to ensure enough samples
1486 * on each SPU are collected each SPU is being profiled 1/8 of the time.
1487 * It may also be necessary to use a longer sample collection period.
1040 */ 1488 */
1041static void cell_global_stop_spu(void) 1489static void cell_handle_interrupt_spu(struct pt_regs *regs,
1490 struct op_counter_config *ctr)
1042{ 1491{
1043 int subfunc, rtn_value; 1492 u32 cpu, cpu_tmp;
1044 unsigned int lfsr_value; 1493 u64 trace_entry;
1045 int cpu; 1494 u32 interrupt_mask;
1495 u64 trace_buffer[2];
1496 u64 last_trace_buffer;
1497 u32 sample;
1498 u32 trace_addr;
1499 unsigned long sample_array_lock_flags;
1500 int spu_num;
1501 unsigned long flags;
1046 1502
1047 oprofile_running = 0; 1503 /* Make sure spu event interrupt handler and spu event swap
1504 * don't access the counters simultaneously.
1505 */
1506 cpu = smp_processor_id();
1507 spin_lock_irqsave(&cntr_lock, flags);
1048 1508
1049#ifdef CONFIG_CPU_FREQ 1509 cpu_tmp = cpu;
1050 cpufreq_unregister_notifier(&cpu_freq_notifier_block, 1510 cbe_disable_pm(cpu);
1051 CPUFREQ_TRANSITION_NOTIFIER);
1052#endif
1053 1511
1054 for_each_online_cpu(cpu) { 1512 interrupt_mask = cbe_get_and_clear_pm_interrupts(cpu);
1055 if (cbe_get_hw_thread_id(cpu))
1056 continue;
1057 1513
1058 subfunc = 3; /* 1514 sample = 0xABCDEF;
1059 * 2 - activate SPU tracing, 1515 trace_entry = 0xfedcba;
1060 * 3 - deactivate 1516 last_trace_buffer = 0xdeadbeaf;
1061 */
1062 lfsr_value = 0x8f100000;
1063 1517
1064 rtn_value = rtas_call(spu_rtas_token, 3, 1, NULL, 1518 if ((oprofile_running == 1) && (interrupt_mask != 0)) {
1065 subfunc, cbe_cpu_to_node(cpu), 1519 /* disable writes to trace buff */
1066 lfsr_value); 1520 cbe_write_pm(cpu, pm_interval, 0);
1067 1521
1068 if (unlikely(rtn_value != 0)) { 1522 /* only have one perf cntr being used, cntr 0 */
1069 printk(KERN_ERR 1523 if ((interrupt_mask & CBE_PM_CTR_OVERFLOW_INTR(0))
1070 "%s: rtas call ibm,cbe-spu-perftools failed, return = %d\n", 1524 && ctr[0].enabled)
1071 __func__, rtn_value); 1525 /* The SPU PC values will be read
1526 * from the trace buffer, reset counter
1527 */
1528
1529 cbe_write_ctr(cpu, 0, reset_value[0]);
1530
1531 trace_addr = cbe_read_pm(cpu, trace_address);
1532
1533 while (!(trace_addr & CBE_PM_TRACE_BUF_EMPTY)) {
1534 /* There is data in the trace buffer to process
1535 * Read the buffer until you get to the last
1536 * entry. This is the value we want.
1537 */
1538
1539 cbe_read_trace_buffer(cpu, trace_buffer);
1540 trace_addr = cbe_read_pm(cpu, trace_address);
1072 } 1541 }
1073 1542
1074 /* Deactivate the signals */ 1543 /* SPU Address 16 bit count format for 128 bit
1075 pm_rtas_reset_signals(cbe_cpu_to_node(cpu)); 1544 * HW trace buffer is used for the SPU PC storage
1076 } 1545 * HDR bits 0:15
1546 * SPU Addr 0 bits 16:31
1547 * SPU Addr 1 bits 32:47
1548 * unused bits 48:127
1549 *
1550 * HDR: bit4 = 1 SPU Address 0 valid
1551 * HDR: bit5 = 1 SPU Address 1 valid
1552 * - unfortunately, the valid bits don't seem to work
1553 *
1554 * Note trace_buffer[0] holds bits 0:63 of the HW
1555 * trace buffer, trace_buffer[1] holds bits 64:127
1556 */
1077 1557
1078 stop_spu_profiling(); 1558 trace_entry = trace_buffer[0]
1079} 1559 & 0x00000000FFFF0000;
1080 1560
1081static void cell_global_stop_ppu(void) 1561 /* only top 16 of the 18 bit SPU PC address
1082{ 1562 * is stored in trace buffer, hence shift right
1083 int cpu; 1563 * by 16 -2 bits */
1564 sample = trace_entry >> 14;
1565 last_trace_buffer = trace_buffer[0];
1084 1566
1085 /* 1567 spu_num = spu_evnt_phys_spu_indx
1086 * This routine will be called once for the system. 1568 + (cbe_cpu_to_node(cpu) * NUM_SPUS_PER_NODE);
1087 * There is one performance monitor per node, so we
1088 * only need to perform this function once per node.
1089 */
1090 del_timer_sync(&timer_virt_cntr);
1091 oprofile_running = 0;
1092 smp_wmb();
1093 1569
1094 for_each_online_cpu(cpu) { 1570 /* make sure only one process at a time is calling
1095 if (cbe_get_hw_thread_id(cpu)) 1571 * spu_sync_buffer()
1096 continue; 1572 */
1573 spin_lock_irqsave(&oprof_spu_smpl_arry_lck,
1574 sample_array_lock_flags);
1575 spu_sync_buffer(spu_num, &sample, 1);
1576 spin_unlock_irqrestore(&oprof_spu_smpl_arry_lck,
1577 sample_array_lock_flags);
1097 1578
1098 cbe_sync_irq(cbe_cpu_to_node(cpu)); 1579 smp_wmb(); /* insure spu event buffer updates are written
1099 /* Stop the counters */ 1580 * don't want events intermingled... */
1100 cbe_disable_pm(cpu);
1101 1581
1102 /* Deactivate the signals */ 1582 /* The counters were frozen by the interrupt.
1103 pm_rtas_reset_signals(cbe_cpu_to_node(cpu)); 1583 * Reenable the interrupt and restart the counters.
1584 */
1585 cbe_write_pm(cpu, pm_interval, NUM_INTERVAL_CYC);
1586 cbe_enable_pm_interrupts(cpu, hdw_thread,
1587 virt_cntr_inter_mask);
1104 1588
1105 /* Deactivate interrupts */ 1589 /* clear the trace buffer, re-enable writes to trace buff */
1106 cbe_disable_pm_interrupts(cpu); 1590 cbe_write_pm(cpu, trace_address, 0);
1107 } 1591 cbe_write_pm(cpu, pm_interval, NUM_INTERVAL_CYC);
1108}
1109 1592
1110static void cell_global_stop(void) 1593 /* The writes to the various performance counters only writes
1111{ 1594 * to a latch. The new values (interrupt setting bits, reset
1112 if (spu_cycle_reset) 1595 * counter value etc.) are not copied to the actual registers
1113 cell_global_stop_spu(); 1596 * until the performance monitor is enabled. In order to get
1114 else 1597 * this to work as desired, the permormance monitor needs to
1115 cell_global_stop_ppu(); 1598 * be disabled while writing to the latches. This is a
1599 * HW design issue.
1600 */
1601 write_pm_cntrl(cpu);
1602 cbe_enable_pm(cpu);
1603 }
1604 spin_unlock_irqrestore(&cntr_lock, flags);
1116} 1605}
1117 1606
1118static void cell_handle_interrupt(struct pt_regs *regs, 1607static void cell_handle_interrupt_ppu(struct pt_regs *regs,
1119 struct op_counter_config *ctr) 1608 struct op_counter_config *ctr)
1120{ 1609{
1121 u32 cpu; 1610 u32 cpu;
1122 u64 pc; 1611 u64 pc;
@@ -1132,7 +1621,7 @@ static void cell_handle_interrupt(struct pt_regs *regs,
1132 * routine are not running at the same time. See the 1621 * routine are not running at the same time. See the
1133 * cell_virtual_cntr() routine for additional comments. 1622 * cell_virtual_cntr() routine for additional comments.
1134 */ 1623 */
1135 spin_lock_irqsave(&virt_cntr_lock, flags); 1624 spin_lock_irqsave(&cntr_lock, flags);
1136 1625
1137 /* 1626 /*
1138 * Need to disable and reenable the performance counters 1627 * Need to disable and reenable the performance counters
@@ -1185,7 +1674,16 @@ static void cell_handle_interrupt(struct pt_regs *regs,
1185 */ 1674 */
1186 cbe_enable_pm(cpu); 1675 cbe_enable_pm(cpu);
1187 } 1676 }
1188 spin_unlock_irqrestore(&virt_cntr_lock, flags); 1677 spin_unlock_irqrestore(&cntr_lock, flags);
1678}
1679
1680static void cell_handle_interrupt(struct pt_regs *regs,
1681 struct op_counter_config *ctr)
1682{
1683 if (profiling_mode == PPU_PROFILING)
1684 cell_handle_interrupt_ppu(regs, ctr);
1685 else
1686 cell_handle_interrupt_spu(regs, ctr);
1189} 1687}
1190 1688
1191/* 1689/*
@@ -1195,7 +1693,8 @@ static void cell_handle_interrupt(struct pt_regs *regs,
1195 */ 1693 */
1196static int cell_sync_start(void) 1694static int cell_sync_start(void)
1197{ 1695{
1198 if (spu_cycle_reset) 1696 if ((profiling_mode == SPU_PROFILING_CYCLES) ||
1697 (profiling_mode == SPU_PROFILING_EVENTS))
1199 return spu_sync_start(); 1698 return spu_sync_start();
1200 else 1699 else
1201 return DO_GENERIC_SYNC; 1700 return DO_GENERIC_SYNC;
@@ -1203,7 +1702,8 @@ static int cell_sync_start(void)
1203 1702
1204static int cell_sync_stop(void) 1703static int cell_sync_stop(void)
1205{ 1704{
1206 if (spu_cycle_reset) 1705 if ((profiling_mode == SPU_PROFILING_CYCLES) ||
1706 (profiling_mode == SPU_PROFILING_EVENTS))
1207 return spu_sync_stop(); 1707 return spu_sync_stop();
1208 else 1708 else
1209 return 1; 1709 return 1;
diff --git a/arch/powerpc/platforms/cell/cbe_cpufreq.c b/arch/powerpc/platforms/cell/cbe_cpufreq.c
index ec7c8f45a215..e6506cd0ff94 100644
--- a/arch/powerpc/platforms/cell/cbe_cpufreq.c
+++ b/arch/powerpc/platforms/cell/cbe_cpufreq.c
@@ -118,7 +118,7 @@ static int cbe_cpufreq_cpu_init(struct cpufreq_policy *policy)
118 policy->cur = cbe_freqs[cur_pmode].frequency; 118 policy->cur = cbe_freqs[cur_pmode].frequency;
119 119
120#ifdef CONFIG_SMP 120#ifdef CONFIG_SMP
121 policy->cpus = per_cpu(cpu_sibling_map, policy->cpu); 121 cpumask_copy(policy->cpus, &per_cpu(cpu_sibling_map, policy->cpu));
122#endif 122#endif
123 123
124 cpufreq_frequency_table_get_attr(cbe_freqs, policy->cpu); 124 cpufreq_frequency_table_get_attr(cbe_freqs, policy->cpu);
diff --git a/arch/powerpc/platforms/cell/cpufreq_spudemand.c b/arch/powerpc/platforms/cell/cpufreq_spudemand.c
index a3c6c01bd6db..968c1c0b4d5b 100644
--- a/arch/powerpc/platforms/cell/cpufreq_spudemand.c
+++ b/arch/powerpc/platforms/cell/cpufreq_spudemand.c
@@ -110,7 +110,7 @@ static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event)
110 } 110 }
111 111
112 /* initialize spu_gov_info for all affected cpus */ 112 /* initialize spu_gov_info for all affected cpus */
113 for_each_cpu_mask(i, policy->cpus) { 113 for_each_cpu(i, policy->cpus) {
114 affected_info = &per_cpu(spu_gov_info, i); 114 affected_info = &per_cpu(spu_gov_info, i);
115 affected_info->policy = policy; 115 affected_info->policy = policy;
116 } 116 }
@@ -127,7 +127,7 @@ static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event)
127 spu_gov_cancel_work(info); 127 spu_gov_cancel_work(info);
128 128
129 /* clean spu_gov_info for all affected cpus */ 129 /* clean spu_gov_info for all affected cpus */
130 for_each_cpu_mask (i, policy->cpus) { 130 for_each_cpu (i, policy->cpus) {
131 info = &per_cpu(spu_gov_info, i); 131 info = &per_cpu(spu_gov_info, i);
132 info->policy = NULL; 132 info->policy = NULL;
133 } 133 }
diff --git a/arch/powerpc/platforms/cell/spufs/spufs.h b/arch/powerpc/platforms/cell/spufs/spufs.h
index 15c62d3ca129..3bf908e2873a 100644
--- a/arch/powerpc/platforms/cell/spufs/spufs.h
+++ b/arch/powerpc/platforms/cell/spufs/spufs.h
@@ -314,7 +314,7 @@ extern char *isolated_loader;
314 * we need to call spu_release(ctx) before sleeping, and 314 * we need to call spu_release(ctx) before sleeping, and
315 * then spu_acquire(ctx) when awoken. 315 * then spu_acquire(ctx) when awoken.
316 * 316 *
317 * Returns with state_mutex re-acquired when successfull or 317 * Returns with state_mutex re-acquired when successful or
318 * with -ERESTARTSYS and the state_mutex dropped when interrupted. 318 * with -ERESTARTSYS and the state_mutex dropped when interrupted.
319 */ 319 */
320 320
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index 8c619963becc..1db6b9e037fc 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -249,6 +249,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249); 250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
251DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575); 251DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
252DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
252 253
253static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev) 254static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev)
254{ 255{
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
index 86db47c1b665..be2527a516ea 100644
--- a/arch/powerpc/platforms/pasemi/cpufreq.c
+++ b/arch/powerpc/platforms/pasemi/cpufreq.c
@@ -213,7 +213,7 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
213 pr_debug("current astate is at %d\n",cur_astate); 213 pr_debug("current astate is at %d\n",cur_astate);
214 214
215 policy->cur = pas_freqs[cur_astate].frequency; 215 policy->cur = pas_freqs[cur_astate].frequency;
216 policy->cpus = cpu_online_map; 216 cpumask_copy(policy->cpus, &cpu_online_map);
217 217
218 ppc_proc_freq = policy->cur * 1000ul; 218 ppc_proc_freq = policy->cur * 1000ul;
219 219
diff --git a/arch/powerpc/platforms/powermac/cpufreq_64.c b/arch/powerpc/platforms/powermac/cpufreq_64.c
index 4dfb4bc242b5..beb38333b6d2 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_64.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_64.c
@@ -362,7 +362,7 @@ static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
362 /* secondary CPUs are tied to the primary one by the 362 /* secondary CPUs are tied to the primary one by the
363 * cpufreq core if in the secondary policy we tell it that 363 * cpufreq core if in the secondary policy we tell it that
364 * it actually must be one policy together with all others. */ 364 * it actually must be one policy together with all others. */
365 policy->cpus = cpu_online_map; 365 cpumask_copy(policy->cpus, &cpu_online_map);
366 cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu); 366 cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
367 367
368 return cpufreq_frequency_table_cpuinfo(policy, 368 return cpufreq_frequency_table_cpuinfo(policy,
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f611d0369cc8..9817f63723dd 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -28,63 +28,104 @@
28#include <sysdev/fsl_pci.h> 28#include <sysdev/fsl_pci.h>
29 29
30#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) 30#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
31static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
32 unsigned int index, const struct resource *res,
33 resource_size_t offset)
34{
35 resource_size_t pci_addr = res->start - offset;
36 resource_size_t phys_addr = res->start;
37 resource_size_t size = res->end - res->start + 1;
38 u32 flags = 0x80044000; /* enable & mem R/W */
39 unsigned int i;
40
41 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
42 (u64)res->start, (u64)size);
43
44 if (res->flags & IORESOURCE_PREFETCH)
45 flags |= 0x10000000; /* enable relaxed ordering */
46
47 for (i = 0; size > 0; i++) {
48 unsigned int bits = min(__ilog2(size),
49 __ffs(pci_addr | phys_addr));
50
51 if (index + i >= 5)
52 return -1;
53
54 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
55 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
56 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
57 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
58
59 pci_addr += (resource_size_t)1U << bits;
60 phys_addr += (resource_size_t)1U << bits;
61 size -= (resource_size_t)1U << bits;
62 }
63
64 return i;
65}
66
31/* atmu setup for fsl pci/pcie controller */ 67/* atmu setup for fsl pci/pcie controller */
32static void __init setup_pci_atmu(struct pci_controller *hose, 68static void __init setup_pci_atmu(struct pci_controller *hose,
33 struct resource *rsrc) 69 struct resource *rsrc)
34{ 70{
35 struct ccsr_pci __iomem *pci; 71 struct ccsr_pci __iomem *pci;
36 int i; 72 int i, j, n;
37 73
38 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 74 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
39 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); 75 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
40 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 76 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
77 if (!pci) {
78 dev_err(hose->parent, "Unable to map ATMU registers\n");
79 return;
80 }
41 81
42 /* Disable all windows (except powar0 since its ignored) */ 82 /* Disable all windows (except powar0 since it's ignored) */
43 for(i = 1; i < 5; i++) 83 for(i = 1; i < 5; i++)
44 out_be32(&pci->pow[i].powar, 0); 84 out_be32(&pci->pow[i].powar, 0);
45 for(i = 0; i < 3; i++) 85 for(i = 0; i < 3; i++)
46 out_be32(&pci->piw[i].piwar, 0); 86 out_be32(&pci->piw[i].piwar, 0);
47 87
48 /* Setup outbound MEM window */ 88 /* Setup outbound MEM window */
49 for(i = 0; i < 3; i++) 89 for(i = 0, j = 1; i < 3; i++) {
50 if (hose->mem_resources[i].flags & IORESOURCE_MEM){ 90 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
51 resource_size_t pci_addr_start = 91 continue;
52 hose->mem_resources[i].start - 92
53 hose->pci_mem_offset; 93 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
54 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 94 hose->pci_mem_offset);
55 (u64)hose->mem_resources[i].start, 95
56 (u64)hose->mem_resources[i].end 96 if (n < 0 || j >= 5) {
57 - (u64)hose->mem_resources[i].start + 1); 97 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
58 out_be32(&pci->pow[i+1].potar, (pci_addr_start >> 12)); 98 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
59 out_be32(&pci->pow[i+1].potear, 0); 99 } else
60 out_be32(&pci->pow[i+1].powbar, 100 j += n;
61 (hose->mem_resources[i].start >> 12)); 101 }
62 /* Enable, Mem R/W */
63 out_be32(&pci->pow[i+1].powar, 0x80044000
64 | (__ilog2(hose->mem_resources[i].end
65 - hose->mem_resources[i].start + 1) - 1));
66 }
67 102
68 /* Setup outbound IO window */ 103 /* Setup outbound IO window */
69 if (hose->io_resource.flags & IORESOURCE_IO){ 104 if (hose->io_resource.flags & IORESOURCE_IO) {
70 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 105 if (j >= 5) {
71 "phy base 0x%016llx.\n", 106 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
72 (u64)hose->io_resource.start, 107 } else {
73 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1, 108 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
74 (u64)hose->io_base_phys); 109 "phy base 0x%016llx.\n",
75 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)); 110 (u64)hose->io_resource.start,
76 out_be32(&pci->pow[i+1].potear, 0); 111 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
77 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)); 112 (u64)hose->io_base_phys);
78 /* Enable, IO R/W */ 113 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
79 out_be32(&pci->pow[i+1].powar, 0x80088000 114 out_be32(&pci->pow[j].potear, 0);
80 | (__ilog2(hose->io_resource.end 115 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
81 - hose->io_resource.start + 1) - 1)); 116 /* Enable, IO R/W */
117 out_be32(&pci->pow[j].powar, 0x80088000
118 | (__ilog2(hose->io_resource.end
119 - hose->io_resource.start + 1) - 1));
120 }
82 } 121 }
83 122
84 /* Setup 2G inbound Memory Window @ 1 */ 123 /* Setup 2G inbound Memory Window @ 1 */
85 out_be32(&pci->piw[2].pitar, 0x00000000); 124 out_be32(&pci->piw[2].pitar, 0x00000000);
86 out_be32(&pci->piw[2].piwbar,0x00000000); 125 out_be32(&pci->piw[2].piwbar,0x00000000);
87 out_be32(&pci->piw[2].piwar, PIWAR_2G); 126 out_be32(&pci->piw[2].piwar, PIWAR_2G);
127
128 iounmap(pci);
88} 129}
89 130
90static void __init setup_pci_cmd(struct pci_controller *hose) 131static void __init setup_pci_cmd(struct pci_controller *hose)
diff --git a/arch/s390/include/asm/chpid.h b/arch/s390/include/asm/chpid.h
index dfe3c7f3439a..fc71d8a6709b 100644
--- a/arch/s390/include/asm/chpid.h
+++ b/arch/s390/include/asm/chpid.h
@@ -9,7 +9,7 @@
9#define _ASM_S390_CHPID_H _ASM_S390_CHPID_H 9#define _ASM_S390_CHPID_H _ASM_S390_CHPID_H
10 10
11#include <linux/string.h> 11#include <linux/string.h>
12#include <asm/types.h> 12#include <linux/types.h>
13 13
14#define __MAX_CHPID 255 14#define __MAX_CHPID 255
15 15
diff --git a/arch/s390/include/asm/chsc.h b/arch/s390/include/asm/chsc.h
index d38d0cf62d4b..807997f7414b 100644
--- a/arch/s390/include/asm/chsc.h
+++ b/arch/s390/include/asm/chsc.h
@@ -8,6 +8,7 @@
8#ifndef _ASM_CHSC_H 8#ifndef _ASM_CHSC_H
9#define _ASM_CHSC_H 9#define _ASM_CHSC_H
10 10
11#include <linux/types.h>
11#include <asm/chpid.h> 12#include <asm/chpid.h>
12#include <asm/schid.h> 13#include <asm/schid.h>
13 14
diff --git a/arch/s390/include/asm/cmb.h b/arch/s390/include/asm/cmb.h
index 50196857d27a..39ae03294794 100644
--- a/arch/s390/include/asm/cmb.h
+++ b/arch/s390/include/asm/cmb.h
@@ -1,5 +1,8 @@
1#ifndef S390_CMB_H 1#ifndef S390_CMB_H
2#define S390_CMB_H 2#define S390_CMB_H
3
4#include <linux/types.h>
5
3/** 6/**
4 * struct cmbdata - channel measurement block data for user space 7 * struct cmbdata - channel measurement block data for user space
5 * @size: size of the stored data 8 * @size: size of the stored data
diff --git a/arch/s390/include/asm/dasd.h b/arch/s390/include/asm/dasd.h
index 55b2b80cdf6e..e2db6f16d9c8 100644
--- a/arch/s390/include/asm/dasd.h
+++ b/arch/s390/include/asm/dasd.h
@@ -14,6 +14,7 @@
14 14
15#ifndef DASD_H 15#ifndef DASD_H
16#define DASD_H 16#define DASD_H
17#include <linux/types.h>
17#include <linux/ioctl.h> 18#include <linux/ioctl.h>
18 19
19#define DASD_IOCTL_LETTER 'D' 20#define DASD_IOCTL_LETTER 'D'
@@ -78,6 +79,7 @@ typedef struct dasd_information2_t {
78#define DASD_FEATURE_USEDIAG 0x02 79#define DASD_FEATURE_USEDIAG 0x02
79#define DASD_FEATURE_INITIAL_ONLINE 0x04 80#define DASD_FEATURE_INITIAL_ONLINE 0x04
80#define DASD_FEATURE_ERPLOG 0x08 81#define DASD_FEATURE_ERPLOG 0x08
82#define DASD_FEATURE_FAILFAST 0x10
81 83
82#define DASD_PARTN_BITS 2 84#define DASD_PARTN_BITS 2
83 85
diff --git a/arch/s390/include/asm/kvm.h b/arch/s390/include/asm/kvm.h
index d74002f95794..e1f54654e3ae 100644
--- a/arch/s390/include/asm/kvm.h
+++ b/arch/s390/include/asm/kvm.h
@@ -13,7 +13,7 @@
13 * Author(s): Carsten Otte <cotte@de.ibm.com> 13 * Author(s): Carsten Otte <cotte@de.ibm.com>
14 * Christian Borntraeger <borntraeger@de.ibm.com> 14 * Christian Borntraeger <borntraeger@de.ibm.com>
15 */ 15 */
16#include <asm/types.h> 16#include <linux/types.h>
17 17
18/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ 18/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
19struct kvm_pic_state { 19struct kvm_pic_state {
diff --git a/arch/s390/include/asm/posix_types.h b/arch/s390/include/asm/posix_types.h
index 397d93fba3a7..8cc113f92523 100644
--- a/arch/s390/include/asm/posix_types.h
+++ b/arch/s390/include/asm/posix_types.h
@@ -68,11 +68,7 @@ typedef unsigned short __kernel_old_dev_t;
68#endif /* __s390x__ */ 68#endif /* __s390x__ */
69 69
70typedef struct { 70typedef struct {
71#if defined(__KERNEL__) || defined(__USE_ALL)
72 int val[2]; 71 int val[2];
73#else /* !defined(__KERNEL__) && !defined(__USE_ALL)*/
74 int __val[2];
75#endif /* !defined(__KERNEL__) && !defined(__USE_ALL)*/
76} __kernel_fsid_t; 72} __kernel_fsid_t;
77 73
78 74
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index 5396f9f12263..8920025c3c02 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -272,12 +272,15 @@ typedef struct
272#define PSW_ASC_SECONDARY 0x0000800000000000UL 272#define PSW_ASC_SECONDARY 0x0000800000000000UL
273#define PSW_ASC_HOME 0x0000C00000000000UL 273#define PSW_ASC_HOME 0x0000C00000000000UL
274 274
275extern long psw_user32_bits;
276
277#endif /* __s390x__ */ 275#endif /* __s390x__ */
278 276
277#ifdef __KERNEL__
279extern long psw_kernel_bits; 278extern long psw_kernel_bits;
280extern long psw_user_bits; 279extern long psw_user_bits;
280#ifdef CONFIG_64BIT
281extern long psw_user32_bits;
282#endif
283#endif
281 284
282/* This macro merges a NEW PSW mask specified by the user into 285/* This macro merges a NEW PSW mask specified by the user into
283 the currently active PSW mask CURRENT, modifying only those 286 the currently active PSW mask CURRENT, modifying only those
diff --git a/arch/s390/include/asm/qeth.h b/arch/s390/include/asm/qeth.h
index 930d378ef75a..06cbd1e8c943 100644
--- a/arch/s390/include/asm/qeth.h
+++ b/arch/s390/include/asm/qeth.h
@@ -10,6 +10,7 @@
10 */ 10 */
11#ifndef __ASM_S390_QETH_IOCTL_H__ 11#ifndef __ASM_S390_QETH_IOCTL_H__
12#define __ASM_S390_QETH_IOCTL_H__ 12#define __ASM_S390_QETH_IOCTL_H__
13#include <linux/types.h>
13#include <linux/ioctl.h> 14#include <linux/ioctl.h>
14 15
15#define SIOC_QETH_ARP_SET_NO_ENTRIES (SIOCDEVPRIVATE) 16#define SIOC_QETH_ARP_SET_NO_ENTRIES (SIOCDEVPRIVATE)
diff --git a/arch/s390/include/asm/schid.h b/arch/s390/include/asm/schid.h
index 825503cf3dc2..3e4d401b4e45 100644
--- a/arch/s390/include/asm/schid.h
+++ b/arch/s390/include/asm/schid.h
@@ -1,6 +1,8 @@
1#ifndef ASM_SCHID_H 1#ifndef ASM_SCHID_H
2#define ASM_SCHID_H 2#define ASM_SCHID_H
3 3
4#include <linux/types.h>
5
4struct subchannel_id { 6struct subchannel_id {
5 __u32 cssid : 8; 7 __u32 cssid : 8;
6 __u32 : 4; 8 __u32 : 4;
diff --git a/arch/s390/include/asm/swab.h b/arch/s390/include/asm/swab.h
index bd9321aa55a9..eb18dc1f327b 100644
--- a/arch/s390/include/asm/swab.h
+++ b/arch/s390/include/asm/swab.h
@@ -9,7 +9,7 @@
9 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) 9 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
10 */ 10 */
11 11
12#include <asm/types.h> 12#include <linux/types.h>
13 13
14#ifndef __s390x__ 14#ifndef __s390x__
15# define __SWAB_64_THRU_32__ 15# define __SWAB_64_THRU_32__
diff --git a/arch/s390/include/asm/types.h b/arch/s390/include/asm/types.h
index 41c547656130..3dc3fc228812 100644
--- a/arch/s390/include/asm/types.h
+++ b/arch/s390/include/asm/types.h
@@ -9,11 +9,7 @@
9#ifndef _S390_TYPES_H 9#ifndef _S390_TYPES_H
10#define _S390_TYPES_H 10#define _S390_TYPES_H
11 11
12#ifndef __s390x__ 12#include <asm-generic/int-ll64.h>
13# include <asm-generic/int-ll64.h>
14#else
15# include <asm-generic/int-l64.h>
16#endif
17 13
18#ifndef __ASSEMBLY__ 14#ifndef __ASSEMBLY__
19 15
diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h
index 6b1896345eda..a65afc91e8aa 100644
--- a/arch/s390/kernel/entry.h
+++ b/arch/s390/kernel/entry.h
@@ -54,7 +54,5 @@ long sys_sigreturn(void);
54long sys_rt_sigreturn(void); 54long sys_rt_sigreturn(void);
55long sys32_sigreturn(void); 55long sys32_sigreturn(void);
56long sys32_rt_sigreturn(void); 56long sys32_rt_sigreturn(void);
57long old_select(struct sel_arg_struct __user *arg);
58long sys_ptrace(long request, long pid, long addr, long data);
59 57
60#endif /* _ENTRY_H */ 58#endif /* _ENTRY_H */
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 9c0ccb532a45..2d337cbb9329 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -685,7 +685,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
685 if (MACHINE_HAS_IEEE) 685 if (MACHINE_HAS_IEEE)
686 lowcore->extended_save_area_addr = (u32) save_area; 686 lowcore->extended_save_area_addr = (u32) save_area;
687#else 687#else
688 BUG_ON(vdso_alloc_per_cpu(smp_processor_id(), lowcore)); 688 if (vdso_alloc_per_cpu(smp_processor_id(), lowcore))
689 BUG();
689#endif 690#endif
690 set_prefix((u32)(unsigned long) lowcore); 691 set_prefix((u32)(unsigned long) lowcore);
691 local_mcck_enable(); 692 local_mcck_enable();
diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c
index 4fe952e557ac..c34be4568b80 100644
--- a/arch/s390/kernel/sys_s390.c
+++ b/arch/s390/kernel/sys_s390.c
@@ -103,25 +103,6 @@ out:
103 return error; 103 return error;
104} 104}
105 105
106#ifndef CONFIG_64BIT
107struct sel_arg_struct {
108 unsigned long n;
109 fd_set __user *inp, *outp, *exp;
110 struct timeval __user *tvp;
111};
112
113asmlinkage long old_select(struct sel_arg_struct __user *arg)
114{
115 struct sel_arg_struct a;
116
117 if (copy_from_user(&a, arg, sizeof(a)))
118 return -EFAULT;
119 /* sys_select() does the appropriate kernel locking */
120 return sys_select(a.n, a.inp, a.outp, a.exp, a.tvp);
121
122}
123#endif /* CONFIG_64BIT */
124
125/* 106/*
126 * sys_ipc() is the de-multiplexer for the SysV IPC calls.. 107 * sys_ipc() is the de-multiplexer for the SysV IPC calls..
127 * 108 *
diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c
index 25a6a82f1c02..690e17819686 100644
--- a/arch/s390/kernel/vdso.c
+++ b/arch/s390/kernel/vdso.c
@@ -322,7 +322,8 @@ static int __init vdso_init(void)
322 vdso64_pagelist[vdso64_pages - 1] = virt_to_page(vdso_data); 322 vdso64_pagelist[vdso64_pages - 1] = virt_to_page(vdso_data);
323 vdso64_pagelist[vdso64_pages] = NULL; 323 vdso64_pagelist[vdso64_pages] = NULL;
324#ifndef CONFIG_SMP 324#ifndef CONFIG_SMP
325 BUG_ON(vdso_alloc_per_cpu(0, S390_lowcore)); 325 if (vdso_alloc_per_cpu(0, &S390_lowcore))
326 BUG();
326#endif 327#endif
327 vdso_init_cr5(); 328 vdso_init_cr5();
328#endif /* CONFIG_64BIT */ 329#endif /* CONFIG_64BIT */
diff --git a/arch/s390/kernel/vdso32/gettimeofday.S b/arch/s390/kernel/vdso32/gettimeofday.S
index c32f29c3d70c..ad8acfc949fb 100644
--- a/arch/s390/kernel/vdso32/gettimeofday.S
+++ b/arch/s390/kernel/vdso32/gettimeofday.S
@@ -13,10 +13,6 @@
13#include <asm/asm-offsets.h> 13#include <asm/asm-offsets.h>
14#include <asm/unistd.h> 14#include <asm/unistd.h>
15 15
16#include <asm/vdso.h>
17#include <asm/asm-offsets.h>
18#include <asm/unistd.h>
19
20 .text 16 .text
21 .align 4 17 .align 4
22 .globl __kernel_gettimeofday 18 .globl __kernel_gettimeofday
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index a0775e1f08df..8300309698fa 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -47,7 +47,7 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu)
47 vcpu->run->s390_reset_flags |= KVM_S390_RESET_IPL; 47 vcpu->run->s390_reset_flags |= KVM_S390_RESET_IPL;
48 vcpu->run->s390_reset_flags |= KVM_S390_RESET_CPU_INIT; 48 vcpu->run->s390_reset_flags |= KVM_S390_RESET_CPU_INIT;
49 vcpu->run->exit_reason = KVM_EXIT_S390_RESET; 49 vcpu->run->exit_reason = KVM_EXIT_S390_RESET;
50 VCPU_EVENT(vcpu, 3, "requesting userspace resets %lx", 50 VCPU_EVENT(vcpu, 3, "requesting userspace resets %llx",
51 vcpu->run->s390_reset_flags); 51 vcpu->run->s390_reset_flags);
52 return -EREMOTE; 52 return -EREMOTE;
53} 53}
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 2960702b4824..f4fe28a2521a 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -160,7 +160,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
160 break; 160 break;
161 161
162 case KVM_S390_INT_VIRTIO: 162 case KVM_S390_INT_VIRTIO:
163 VCPU_EVENT(vcpu, 4, "interrupt: virtio parm:%x,parm64:%lx", 163 VCPU_EVENT(vcpu, 4, "interrupt: virtio parm:%x,parm64:%llx",
164 inti->ext.ext_params, inti->ext.ext_params2); 164 inti->ext.ext_params, inti->ext.ext_params2);
165 vcpu->stat.deliver_virtio_interrupt++; 165 vcpu->stat.deliver_virtio_interrupt++;
166 rc = put_guest_u16(vcpu, __LC_EXT_INT_CODE, 0x2603); 166 rc = put_guest_u16(vcpu, __LC_EXT_INT_CODE, 0x2603);
@@ -360,7 +360,7 @@ int kvm_s390_handle_wait(struct kvm_vcpu *vcpu)
360 vcpu->arch.ckc_timer.expires = jiffies + sltime; 360 vcpu->arch.ckc_timer.expires = jiffies + sltime;
361 361
362 add_timer(&vcpu->arch.ckc_timer); 362 add_timer(&vcpu->arch.ckc_timer);
363 VCPU_EVENT(vcpu, 5, "enabled wait timer:%lx jiffies", sltime); 363 VCPU_EVENT(vcpu, 5, "enabled wait timer:%llx jiffies", sltime);
364no_timer: 364no_timer:
365 spin_lock_bh(&vcpu->arch.local_int.float_int->lock); 365 spin_lock_bh(&vcpu->arch.local_int.float_int->lock);
366 spin_lock_bh(&vcpu->arch.local_int.lock); 366 spin_lock_bh(&vcpu->arch.local_int.lock);
@@ -491,7 +491,7 @@ int kvm_s390_inject_vm(struct kvm *kvm,
491 491
492 switch (s390int->type) { 492 switch (s390int->type) {
493 case KVM_S390_INT_VIRTIO: 493 case KVM_S390_INT_VIRTIO:
494 VM_EVENT(kvm, 5, "inject: virtio parm:%x,parm64:%lx", 494 VM_EVENT(kvm, 5, "inject: virtio parm:%x,parm64:%llx",
495 s390int->parm, s390int->parm64); 495 s390int->parm, s390int->parm64);
496 inti->type = s390int->type; 496 inti->type = s390int->type;
497 inti->ext.ext_params = s390int->parm; 497 inti->ext.ext_params = s390int->parm;
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index cce40ff2913b..3605df45dd41 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -118,7 +118,7 @@ static int handle_store_cpu_address(struct kvm_vcpu *vcpu)
118 goto out; 118 goto out;
119 } 119 }
120 120
121 VCPU_EVENT(vcpu, 5, "storing cpu address to %lx", useraddr); 121 VCPU_EVENT(vcpu, 5, "storing cpu address to %llx", useraddr);
122out: 122out:
123 return 0; 123 return 0;
124} 124}
diff --git a/arch/sh/include/asm/mmu.h b/arch/sh/include/asm/mmu.h
index fdcb93bc6d11..6c43625bb1a5 100644
--- a/arch/sh/include/asm/mmu.h
+++ b/arch/sh/include/asm/mmu.h
@@ -9,7 +9,6 @@ typedef struct {
9 mm_context_id_t id; 9 mm_context_id_t id;
10 void *vdso; 10 void *vdso;
11#else 11#else
12 struct vm_list_struct *vmlist;
13 unsigned long end_brk; 12 unsigned long end_brk;
14#endif 13#endif
15#ifdef CONFIG_BINFMT_ELF_FDPIC 14#ifdef CONFIG_BINFMT_ELF_FDPIC
diff --git a/arch/sparc/configs/sparc32_defconfig b/arch/sparc/configs/sparc32_defconfig
index 2e3a149ea0e7..09ab46e4c59d 100644
--- a/arch/sparc/configs/sparc32_defconfig
+++ b/arch/sparc/configs/sparc32_defconfig
@@ -1,15 +1,21 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.25 3# Linux kernel version: 2.6.28
4# Tue Apr 29 01:28:58 2008 4# Thu Jan 8 16:45:44 2009
5# 5#
6# CONFIG_64BIT is not set
7CONFIG_SPARC=y
8CONFIG_SPARC32=y
9# CONFIG_SPARC64 is not set
10CONFIG_ARCH_DEFCONFIG="arch/sparc/configs/sparc32_defconfig"
11CONFIG_BITS=32
12CONFIG_AUDIT_ARCH=y
6CONFIG_MMU=y 13CONFIG_MMU=y
7CONFIG_HIGHMEM=y 14CONFIG_HIGHMEM=y
8CONFIG_ZONE_DMA=y 15CONFIG_ZONE_DMA=y
9CONFIG_GENERIC_ISA_DMA=y 16CONFIG_GENERIC_ISA_DMA=y
10CONFIG_ARCH_NO_VIRT_TO_BUS=y 17CONFIG_ARCH_NO_VIRT_TO_BUS=y
11CONFIG_OF=y 18CONFIG_OF=y
12CONFIG_HZ=100
13CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
14 20
15# 21#
@@ -66,31 +72,30 @@ CONFIG_SIGNALFD=y
66CONFIG_TIMERFD=y 72CONFIG_TIMERFD=y
67CONFIG_EVENTFD=y 73CONFIG_EVENTFD=y
68CONFIG_SHMEM=y 74CONFIG_SHMEM=y
75CONFIG_AIO=y
69CONFIG_VM_EVENT_COUNTERS=y 76CONFIG_VM_EVENT_COUNTERS=y
77CONFIG_PCI_QUIRKS=y
70CONFIG_SLAB=y 78CONFIG_SLAB=y
71# CONFIG_SLUB is not set 79# CONFIG_SLUB is not set
72# CONFIG_SLOB is not set 80# CONFIG_SLOB is not set
73# CONFIG_PROFILING is not set 81# CONFIG_PROFILING is not set
74# CONFIG_MARKERS is not set
75CONFIG_HAVE_OPROFILE=y 82CONFIG_HAVE_OPROFILE=y
76# CONFIG_HAVE_KPROBES is not set 83CONFIG_HAVE_ARCH_TRACEHOOK=y
77# CONFIG_HAVE_KRETPROBES is not set 84# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
78CONFIG_PROC_PAGE_MONITOR=y
79CONFIG_SLABINFO=y 85CONFIG_SLABINFO=y
80CONFIG_RT_MUTEXES=y 86CONFIG_RT_MUTEXES=y
81# CONFIG_TINY_SHMEM is not set
82CONFIG_BASE_SMALL=0 87CONFIG_BASE_SMALL=0
83CONFIG_MODULES=y 88CONFIG_MODULES=y
89# CONFIG_MODULE_FORCE_LOAD is not set
84CONFIG_MODULE_UNLOAD=y 90CONFIG_MODULE_UNLOAD=y
85# CONFIG_MODULE_FORCE_UNLOAD is not set 91# CONFIG_MODULE_FORCE_UNLOAD is not set
86# CONFIG_MODVERSIONS is not set 92# CONFIG_MODVERSIONS is not set
87# CONFIG_MODULE_SRCVERSION_ALL is not set 93# CONFIG_MODULE_SRCVERSION_ALL is not set
88CONFIG_KMOD=y
89CONFIG_BLOCK=y 94CONFIG_BLOCK=y
90# CONFIG_LBD is not set 95# CONFIG_LBD is not set
91# CONFIG_BLK_DEV_IO_TRACE is not set 96# CONFIG_BLK_DEV_IO_TRACE is not set
92# CONFIG_LSF is not set
93# CONFIG_BLK_DEV_BSG is not set 97# CONFIG_BLK_DEV_BSG is not set
98# CONFIG_BLK_DEV_INTEGRITY is not set
94 99
95# 100#
96# IO Schedulers 101# IO Schedulers
@@ -105,59 +110,73 @@ CONFIG_DEFAULT_CFQ=y
105# CONFIG_DEFAULT_NOOP is not set 110# CONFIG_DEFAULT_NOOP is not set
106CONFIG_DEFAULT_IOSCHED="cfq" 111CONFIG_DEFAULT_IOSCHED="cfq"
107CONFIG_CLASSIC_RCU=y 112CONFIG_CLASSIC_RCU=y
113# CONFIG_TREE_RCU is not set
114# CONFIG_PREEMPT_RCU is not set
115# CONFIG_TREE_RCU_TRACE is not set
116# CONFIG_PREEMPT_RCU_TRACE is not set
117# CONFIG_FREEZER is not set
108 118
109# 119#
110# General machine setup 120# Processor type and features
111# 121#
112# CONFIG_SMP is not set 122# CONFIG_SMP is not set
113CONFIG_SPARC=y 123# CONFIG_HZ_100 is not set
114CONFIG_SPARC32=y 124CONFIG_HZ_250=y
115CONFIG_SBUS=y 125# CONFIG_HZ_300 is not set
116CONFIG_SBUSCHAR=y 126# CONFIG_HZ_1000 is not set
117CONFIG_SERIAL_CONSOLE=y 127CONFIG_HZ=250
118CONFIG_SUN_AUXIO=y 128# CONFIG_SCHED_HRTICK is not set
119CONFIG_SUN_IO=y
120CONFIG_RWSEM_GENERIC_SPINLOCK=y 129CONFIG_RWSEM_GENERIC_SPINLOCK=y
121CONFIG_GENERIC_FIND_NEXT_BIT=y 130CONFIG_GENERIC_FIND_NEXT_BIT=y
122CONFIG_GENERIC_HWEIGHT=y 131CONFIG_GENERIC_HWEIGHT=y
123CONFIG_GENERIC_CALIBRATE_DELAY=y 132CONFIG_GENERIC_CALIBRATE_DELAY=y
124CONFIG_ARCH_MAY_HAVE_PC_FDC=y 133CONFIG_ARCH_MAY_HAVE_PC_FDC=y
125# CONFIG_ARCH_HAS_ILOG2_U32 is not set
126# CONFIG_ARCH_HAS_ILOG2_U64 is not set
127CONFIG_EMULATED_CMPXCHG=y 134CONFIG_EMULATED_CMPXCHG=y
128CONFIG_SUN_PM=y
129# CONFIG_SUN4 is not set
130CONFIG_PCI=y
131CONFIG_PCI_SYSCALL=y
132# CONFIG_ARCH_SUPPORTS_MSI is not set
133CONFIG_PCI_LEGACY=y
134# CONFIG_PCI_DEBUG is not set
135# CONFIG_NO_DMA is not set
136CONFIG_SUN_OPENPROMFS=m
137# CONFIG_SPARC_LED is not set
138CONFIG_BINFMT_ELF=y
139CONFIG_BINFMT_MISC=m
140CONFIG_SELECT_MEMORY_MODEL=y 135CONFIG_SELECT_MEMORY_MODEL=y
141CONFIG_FLATMEM_MANUAL=y 136CONFIG_FLATMEM_MANUAL=y
142# CONFIG_DISCONTIGMEM_MANUAL is not set 137# CONFIG_DISCONTIGMEM_MANUAL is not set
143# CONFIG_SPARSEMEM_MANUAL is not set 138# CONFIG_SPARSEMEM_MANUAL is not set
144CONFIG_FLATMEM=y 139CONFIG_FLATMEM=y
145CONFIG_FLAT_NODE_MEM_MAP=y 140CONFIG_FLAT_NODE_MEM_MAP=y
146# CONFIG_SPARSEMEM_STATIC is not set 141CONFIG_PAGEFLAGS_EXTENDED=y
147# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
148CONFIG_SPLIT_PTLOCK_CPUS=4 142CONFIG_SPLIT_PTLOCK_CPUS=4
149# CONFIG_RESOURCES_64BIT is not set 143# CONFIG_PHYS_ADDR_T_64BIT is not set
150CONFIG_ZONE_DMA_FLAG=1 144CONFIG_ZONE_DMA_FLAG=1
151CONFIG_BOUNCE=y 145CONFIG_BOUNCE=y
146CONFIG_UNEVICTABLE_LRU=y
147CONFIG_SUN_PM=y
148# CONFIG_SPARC_LED is not set
149CONFIG_SERIAL_CONSOLE=y
152 150
153# 151#
154# Networking 152# Bus options (PCI etc.)
155# 153#
154CONFIG_SBUS=y
155CONFIG_SBUSCHAR=y
156CONFIG_PCI=y
157CONFIG_PCI_SYSCALL=y
158# CONFIG_ARCH_SUPPORTS_MSI is not set
159CONFIG_PCI_LEGACY=y
160# CONFIG_PCI_DEBUG is not set
161# CONFIG_PCI_STUB is not set
162# CONFIG_PCCARD is not set
163CONFIG_SUN_OPENPROMFS=m
164CONFIG_SPARC32_PCI=y
165
166#
167# Executable file formats
168#
169CONFIG_BINFMT_ELF=y
170# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
171# CONFIG_HAVE_AOUT is not set
172CONFIG_BINFMT_MISC=m
156CONFIG_NET=y 173CONFIG_NET=y
157 174
158# 175#
159# Networking options 176# Networking options
160# 177#
178# CONFIG_NET_NS is not set
179CONFIG_COMPAT_NET_DEV_OPS=y
161CONFIG_PACKET=y 180CONFIG_PACKET=y
162# CONFIG_PACKET_MMAP is not set 181# CONFIG_PACKET_MMAP is not set
163CONFIG_UNIX=y 182CONFIG_UNIX=y
@@ -166,6 +185,7 @@ CONFIG_XFRM_USER=m
166# CONFIG_XFRM_SUB_POLICY is not set 185# CONFIG_XFRM_SUB_POLICY is not set
167# CONFIG_XFRM_MIGRATE is not set 186# CONFIG_XFRM_MIGRATE is not set
168# CONFIG_XFRM_STATISTICS is not set 187# CONFIG_XFRM_STATISTICS is not set
188CONFIG_XFRM_IPCOMP=y
169CONFIG_NET_KEY=m 189CONFIG_NET_KEY=m
170# CONFIG_NET_KEY_MIGRATE is not set 190# CONFIG_NET_KEY_MIGRATE is not set
171CONFIG_INET=y 191CONFIG_INET=y
@@ -221,6 +241,7 @@ CONFIG_IPV6_TUNNEL=m
221# CONFIG_TIPC is not set 241# CONFIG_TIPC is not set
222# CONFIG_ATM is not set 242# CONFIG_ATM is not set
223# CONFIG_BRIDGE is not set 243# CONFIG_BRIDGE is not set
244# CONFIG_NET_DSA is not set
224# CONFIG_VLAN_8021Q is not set 245# CONFIG_VLAN_8021Q is not set
225# CONFIG_DECNET is not set 246# CONFIG_DECNET is not set
226# CONFIG_LLC2 is not set 247# CONFIG_LLC2 is not set
@@ -231,6 +252,7 @@ CONFIG_IPV6_TUNNEL=m
231# CONFIG_ECONET is not set 252# CONFIG_ECONET is not set
232# CONFIG_WAN_ROUTER is not set 253# CONFIG_WAN_ROUTER is not set
233# CONFIG_NET_SCHED is not set 254# CONFIG_NET_SCHED is not set
255# CONFIG_DCB is not set
234 256
235# 257#
236# Network testing 258# Network testing
@@ -241,14 +263,14 @@ CONFIG_NET_PKTGEN=m
241# CONFIG_IRDA is not set 263# CONFIG_IRDA is not set
242# CONFIG_BT is not set 264# CONFIG_BT is not set
243# CONFIG_AF_RXRPC is not set 265# CONFIG_AF_RXRPC is not set
244 266# CONFIG_PHONET is not set
245# 267CONFIG_WIRELESS=y
246# Wireless
247#
248# CONFIG_CFG80211 is not set 268# CONFIG_CFG80211 is not set
269CONFIG_WIRELESS_OLD_REGULATORY=y
249# CONFIG_WIRELESS_EXT is not set 270# CONFIG_WIRELESS_EXT is not set
271# CONFIG_LIB80211 is not set
250# CONFIG_MAC80211 is not set 272# CONFIG_MAC80211 is not set
251# CONFIG_IEEE80211 is not set 273# CONFIG_WIMAX is not set
252# CONFIG_RFKILL is not set 274# CONFIG_RFKILL is not set
253# CONFIG_NET_9P is not set 275# CONFIG_NET_9P is not set
254 276
@@ -262,7 +284,9 @@ CONFIG_NET_PKTGEN=m
262CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 284CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
263CONFIG_STANDALONE=y 285CONFIG_STANDALONE=y
264CONFIG_PREVENT_FIRMWARE_BUILD=y 286CONFIG_PREVENT_FIRMWARE_BUILD=y
265# CONFIG_FW_LOADER is not set 287CONFIG_FW_LOADER=y
288CONFIG_FIRMWARE_IN_KERNEL=y
289CONFIG_EXTRA_FIRMWARE=""
266# CONFIG_DEBUG_DRIVER is not set 290# CONFIG_DEBUG_DRIVER is not set
267# CONFIG_DEBUG_DEVRES is not set 291# CONFIG_DEBUG_DEVRES is not set
268# CONFIG_SYS_HYPERVISOR is not set 292# CONFIG_SYS_HYPERVISOR is not set
@@ -286,12 +310,15 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
286# CONFIG_BLK_DEV_XIP is not set 310# CONFIG_BLK_DEV_XIP is not set
287# CONFIG_CDROM_PKTCDVD is not set 311# CONFIG_CDROM_PKTCDVD is not set
288# CONFIG_ATA_OVER_ETH is not set 312# CONFIG_ATA_OVER_ETH is not set
313# CONFIG_BLK_DEV_HD is not set
289CONFIG_MISC_DEVICES=y 314CONFIG_MISC_DEVICES=y
290# CONFIG_PHANTOM is not set 315# CONFIG_PHANTOM is not set
291# CONFIG_EEPROM_93CX6 is not set 316# CONFIG_EEPROM_93CX6 is not set
292# CONFIG_SGI_IOC4 is not set 317# CONFIG_SGI_IOC4 is not set
293# CONFIG_TIFM_CORE is not set 318# CONFIG_TIFM_CORE is not set
294# CONFIG_ENCLOSURE_SERVICES is not set 319# CONFIG_ENCLOSURE_SERVICES is not set
320# CONFIG_HP_ILO is not set
321# CONFIG_C2PORT is not set
295CONFIG_HAVE_IDE=y 322CONFIG_HAVE_IDE=y
296# CONFIG_IDE is not set 323# CONFIG_IDE is not set
297 324
@@ -335,6 +362,7 @@ CONFIG_SCSI_SPI_ATTRS=y
335# CONFIG_SCSI_SRP_ATTRS is not set 362# CONFIG_SCSI_SRP_ATTRS is not set
336CONFIG_SCSI_LOWLEVEL=y 363CONFIG_SCSI_LOWLEVEL=y
337# CONFIG_ISCSI_TCP is not set 364# CONFIG_ISCSI_TCP is not set
365# CONFIG_SCSI_CXGB3_ISCSI is not set
338# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 366# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
339# CONFIG_SCSI_3W_9XXX is not set 367# CONFIG_SCSI_3W_9XXX is not set
340# CONFIG_SCSI_ACARD is not set 368# CONFIG_SCSI_ACARD is not set
@@ -348,6 +376,8 @@ CONFIG_SCSI_LOWLEVEL=y
348# CONFIG_MEGARAID_LEGACY is not set 376# CONFIG_MEGARAID_LEGACY is not set
349# CONFIG_MEGARAID_SAS is not set 377# CONFIG_MEGARAID_SAS is not set
350# CONFIG_SCSI_HPTIOP is not set 378# CONFIG_SCSI_HPTIOP is not set
379# CONFIG_LIBFC is not set
380# CONFIG_FCOE is not set
351# CONFIG_SCSI_DMX3191D is not set 381# CONFIG_SCSI_DMX3191D is not set
352# CONFIG_SCSI_FUTURE_DOMAIN is not set 382# CONFIG_SCSI_FUTURE_DOMAIN is not set
353# CONFIG_SCSI_IPS is not set 383# CONFIG_SCSI_IPS is not set
@@ -367,6 +397,7 @@ CONFIG_SCSI_QLOGICPTI=m
367# CONFIG_SCSI_DEBUG is not set 397# CONFIG_SCSI_DEBUG is not set
368CONFIG_SCSI_SUNESP=y 398CONFIG_SCSI_SUNESP=y
369# CONFIG_SCSI_SRP is not set 399# CONFIG_SCSI_SRP is not set
400# CONFIG_SCSI_DH is not set
370# CONFIG_ATA is not set 401# CONFIG_ATA is not set
371# CONFIG_MD is not set 402# CONFIG_MD is not set
372# CONFIG_FUSION is not set 403# CONFIG_FUSION is not set
@@ -374,11 +405,14 @@ CONFIG_SCSI_SUNESP=y
374# 405#
375# IEEE 1394 (FireWire) support 406# IEEE 1394 (FireWire) support
376# 407#
408
409#
410# Enable only one of the two stacks, unless you know what you are doing
411#
377# CONFIG_FIREWIRE is not set 412# CONFIG_FIREWIRE is not set
378# CONFIG_IEEE1394 is not set 413# CONFIG_IEEE1394 is not set
379# CONFIG_I2O is not set 414# CONFIG_I2O is not set
380CONFIG_NETDEVICES=y 415CONFIG_NETDEVICES=y
381# CONFIG_NETDEVICES_MULTIQUEUE is not set
382CONFIG_DUMMY=m 416CONFIG_DUMMY=m
383# CONFIG_BONDING is not set 417# CONFIG_BONDING is not set
384# CONFIG_MACVLAN is not set 418# CONFIG_MACVLAN is not set
@@ -402,14 +436,16 @@ CONFIG_SUNQE=m
402# CONFIG_IBM_NEW_EMAC_RGMII is not set 436# CONFIG_IBM_NEW_EMAC_RGMII is not set
403# CONFIG_IBM_NEW_EMAC_TAH is not set 437# CONFIG_IBM_NEW_EMAC_TAH is not set
404# CONFIG_IBM_NEW_EMAC_EMAC4 is not set 438# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
439# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
440# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
441# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
405# CONFIG_NET_PCI is not set 442# CONFIG_NET_PCI is not set
406# CONFIG_B44 is not set 443# CONFIG_B44 is not set
444# CONFIG_ATL2 is not set
407CONFIG_NETDEV_1000=y 445CONFIG_NETDEV_1000=y
408# CONFIG_ACENIC is not set 446# CONFIG_ACENIC is not set
409# CONFIG_DL2K is not set 447# CONFIG_DL2K is not set
410# CONFIG_E1000 is not set 448# CONFIG_E1000 is not set
411# CONFIG_E1000E is not set
412# CONFIG_E1000E_ENABLED is not set
413# CONFIG_IP1000 is not set 449# CONFIG_IP1000 is not set
414# CONFIG_IGB is not set 450# CONFIG_IGB is not set
415# CONFIG_MYRI_SBUS is not set 451# CONFIG_MYRI_SBUS is not set
@@ -425,18 +461,25 @@ CONFIG_NETDEV_1000=y
425# CONFIG_BNX2 is not set 461# CONFIG_BNX2 is not set
426# CONFIG_QLA3XXX is not set 462# CONFIG_QLA3XXX is not set
427# CONFIG_ATL1 is not set 463# CONFIG_ATL1 is not set
464# CONFIG_ATL1E is not set
465# CONFIG_JME is not set
428CONFIG_NETDEV_10000=y 466CONFIG_NETDEV_10000=y
429# CONFIG_CHELSIO_T1 is not set 467# CONFIG_CHELSIO_T1 is not set
468CONFIG_CHELSIO_T3_DEPENDS=y
430# CONFIG_CHELSIO_T3 is not set 469# CONFIG_CHELSIO_T3 is not set
470# CONFIG_ENIC is not set
431# CONFIG_IXGBE is not set 471# CONFIG_IXGBE is not set
432# CONFIG_IXGB is not set 472# CONFIG_IXGB is not set
433# CONFIG_S2IO is not set 473# CONFIG_S2IO is not set
434# CONFIG_MYRI10GE is not set 474# CONFIG_MYRI10GE is not set
435# CONFIG_NETXEN_NIC is not set 475# CONFIG_NETXEN_NIC is not set
436# CONFIG_NIU is not set 476# CONFIG_NIU is not set
477# CONFIG_MLX4_EN is not set
437# CONFIG_MLX4_CORE is not set 478# CONFIG_MLX4_CORE is not set
438# CONFIG_TEHUTI is not set 479# CONFIG_TEHUTI is not set
439# CONFIG_BNX2X is not set 480# CONFIG_BNX2X is not set
481# CONFIG_QLGE is not set
482# CONFIG_SFC is not set
440# CONFIG_TR is not set 483# CONFIG_TR is not set
441 484
442# 485#
@@ -445,6 +488,10 @@ CONFIG_NETDEV_10000=y
445# CONFIG_WLAN_PRE80211 is not set 488# CONFIG_WLAN_PRE80211 is not set
446# CONFIG_WLAN_80211 is not set 489# CONFIG_WLAN_80211 is not set
447# CONFIG_IWLWIFI_LEDS is not set 490# CONFIG_IWLWIFI_LEDS is not set
491
492#
493# Enable WiMAX (Networking options) to see the WiMAX drivers
494#
448# CONFIG_WAN is not set 495# CONFIG_WAN is not set
449# CONFIG_FDDI is not set 496# CONFIG_FDDI is not set
450# CONFIG_HIPPI is not set 497# CONFIG_HIPPI is not set
@@ -492,9 +539,11 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
492CONFIG_MOUSE_PS2_SYNAPTICS=y 539CONFIG_MOUSE_PS2_SYNAPTICS=y
493CONFIG_MOUSE_PS2_LIFEBOOK=y 540CONFIG_MOUSE_PS2_LIFEBOOK=y
494CONFIG_MOUSE_PS2_TRACKPOINT=y 541CONFIG_MOUSE_PS2_TRACKPOINT=y
542# CONFIG_MOUSE_PS2_ELANTECH is not set
495# CONFIG_MOUSE_PS2_TOUCHKIT is not set 543# CONFIG_MOUSE_PS2_TOUCHKIT is not set
496CONFIG_MOUSE_SERIAL=m 544CONFIG_MOUSE_SERIAL=m
497# CONFIG_MOUSE_APPLETOUCH is not set 545# CONFIG_MOUSE_APPLETOUCH is not set
546# CONFIG_MOUSE_BCM5974 is not set
498# CONFIG_MOUSE_VSXXXAA is not set 547# CONFIG_MOUSE_VSXXXAA is not set
499# CONFIG_INPUT_JOYSTICK is not set 548# CONFIG_INPUT_JOYSTICK is not set
500# CONFIG_INPUT_TABLET is not set 549# CONFIG_INPUT_TABLET is not set
@@ -516,15 +565,18 @@ CONFIG_SERIO_LIBPS2=m
516# Character devices 565# Character devices
517# 566#
518CONFIG_VT=y 567CONFIG_VT=y
568CONFIG_CONSOLE_TRANSLATIONS=y
519CONFIG_VT_CONSOLE=y 569CONFIG_VT_CONSOLE=y
520CONFIG_HW_CONSOLE=y 570CONFIG_HW_CONSOLE=y
521# CONFIG_VT_HW_CONSOLE_BINDING is not set 571# CONFIG_VT_HW_CONSOLE_BINDING is not set
572CONFIG_DEVKMEM=y
522# CONFIG_SERIAL_NONSTANDARD is not set 573# CONFIG_SERIAL_NONSTANDARD is not set
523# CONFIG_NOZOMI is not set 574# CONFIG_NOZOMI is not set
524 575
525# 576#
526# Serial drivers 577# Serial drivers
527# 578#
579# CONFIG_SERIAL_8250 is not set
528 580
529# 581#
530# Non-8250 serial port support 582# Non-8250 serial port support
@@ -540,23 +592,20 @@ CONFIG_SERIAL_CORE_CONSOLE=y
540CONFIG_CONSOLE_POLL=y 592CONFIG_CONSOLE_POLL=y
541# CONFIG_SERIAL_JSM is not set 593# CONFIG_SERIAL_JSM is not set
542CONFIG_UNIX98_PTYS=y 594CONFIG_UNIX98_PTYS=y
595# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
543CONFIG_LEGACY_PTYS=y 596CONFIG_LEGACY_PTYS=y
544CONFIG_LEGACY_PTY_COUNT=256 597CONFIG_LEGACY_PTY_COUNT=256
545# CONFIG_IPMI_HANDLER is not set 598# CONFIG_IPMI_HANDLER is not set
546CONFIG_HW_RANDOM=m 599CONFIG_HW_RANDOM=m
547CONFIG_JS_RTC=m
548# CONFIG_R3964 is not set 600# CONFIG_R3964 is not set
549# CONFIG_APPLICOM is not set 601# CONFIG_APPLICOM is not set
550# CONFIG_RAW_DRIVER is not set 602# CONFIG_RAW_DRIVER is not set
551# CONFIG_TCG_TPM is not set 603# CONFIG_TCG_TPM is not set
552CONFIG_DEVPORT=y 604CONFIG_DEVPORT=y
553# CONFIG_I2C is not set 605# CONFIG_I2C is not set
554
555#
556# SPI support
557#
558# CONFIG_SPI is not set 606# CONFIG_SPI is not set
559# CONFIG_SPI_MASTER is not set 607CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
608# CONFIG_GPIOLIB is not set
560# CONFIG_W1 is not set 609# CONFIG_W1 is not set
561# CONFIG_POWER_SUPPLY is not set 610# CONFIG_POWER_SUPPLY is not set
562CONFIG_HWMON=y 611CONFIG_HWMON=y
@@ -577,25 +626,38 @@ CONFIG_HWMON=y
577# CONFIG_SENSORS_W83627EHF is not set 626# CONFIG_SENSORS_W83627EHF is not set
578# CONFIG_HWMON_DEBUG_CHIP is not set 627# CONFIG_HWMON_DEBUG_CHIP is not set
579# CONFIG_THERMAL is not set 628# CONFIG_THERMAL is not set
629# CONFIG_THERMAL_HWMON is not set
580# CONFIG_WATCHDOG is not set 630# CONFIG_WATCHDOG is not set
631CONFIG_SSB_POSSIBLE=y
581 632
582# 633#
583# Sonics Silicon Backplane 634# Sonics Silicon Backplane
584# 635#
585CONFIG_SSB_POSSIBLE=y
586# CONFIG_SSB is not set 636# CONFIG_SSB is not set
587 637
588# 638#
589# Multifunction device drivers 639# Multifunction device drivers
590# 640#
641# CONFIG_MFD_CORE is not set
591# CONFIG_MFD_SM501 is not set 642# CONFIG_MFD_SM501 is not set
592# CONFIG_HTC_PASIC3 is not set 643# CONFIG_HTC_PASIC3 is not set
644# CONFIG_MFD_TMIO is not set
645# CONFIG_REGULATOR is not set
593 646
594# 647#
595# Multimedia devices 648# Multimedia devices
596# 649#
650
651#
652# Multimedia core support
653#
597# CONFIG_VIDEO_DEV is not set 654# CONFIG_VIDEO_DEV is not set
598# CONFIG_DVB_CORE is not set 655# CONFIG_DVB_CORE is not set
656# CONFIG_VIDEO_MEDIA is not set
657
658#
659# Multimedia drivers
660#
599# CONFIG_DAB is not set 661# CONFIG_DAB is not set
600 662
601# 663#
@@ -616,15 +678,17 @@ CONFIG_SSB_POSSIBLE=y
616# 678#
617# CONFIG_PROM_CONSOLE is not set 679# CONFIG_PROM_CONSOLE is not set
618CONFIG_DUMMY_CONSOLE=y 680CONFIG_DUMMY_CONSOLE=y
619
620#
621# Sound
622#
623# CONFIG_SOUND is not set 681# CONFIG_SOUND is not set
624CONFIG_HID_SUPPORT=y 682CONFIG_HID_SUPPORT=y
625CONFIG_HID=y 683CONFIG_HID=y
626# CONFIG_HID_DEBUG is not set 684# CONFIG_HID_DEBUG is not set
627# CONFIG_HIDRAW is not set 685# CONFIG_HIDRAW is not set
686# CONFIG_HID_PID is not set
687
688#
689# Special HID drivers
690#
691CONFIG_HID_COMPAT=y
628CONFIG_USB_SUPPORT=y 692CONFIG_USB_SUPPORT=y
629CONFIG_USB_ARCH_HAS_HCD=y 693CONFIG_USB_ARCH_HAS_HCD=y
630CONFIG_USB_ARCH_HAS_OHCI=y 694CONFIG_USB_ARCH_HAS_OHCI=y
@@ -632,32 +696,71 @@ CONFIG_USB_ARCH_HAS_EHCI=y
632# CONFIG_USB is not set 696# CONFIG_USB is not set
633 697
634# 698#
635# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 699# Enable Host or Gadget support to see Inventra options
700#
701
702#
703# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
636# 704#
637# CONFIG_USB_GADGET is not set 705# CONFIG_USB_GADGET is not set
706
707#
708# OTG and related infrastructure
709#
710# CONFIG_UWB is not set
638# CONFIG_MMC is not set 711# CONFIG_MMC is not set
639# CONFIG_MEMSTICK is not set 712# CONFIG_MEMSTICK is not set
640# CONFIG_NEW_LEDS is not set 713# CONFIG_NEW_LEDS is not set
714# CONFIG_ACCESSIBILITY is not set
641# CONFIG_INFINIBAND is not set 715# CONFIG_INFINIBAND is not set
642# CONFIG_RTC_CLASS is not set 716CONFIG_RTC_LIB=y
717CONFIG_RTC_CLASS=y
718CONFIG_RTC_HCTOSYS=y
719CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
720# CONFIG_RTC_DEBUG is not set
721
722#
723# RTC interfaces
724#
725CONFIG_RTC_INTF_SYSFS=y
726CONFIG_RTC_INTF_PROC=y
727CONFIG_RTC_INTF_DEV=y
728# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
729# CONFIG_RTC_DRV_TEST is not set
730
731#
732# SPI RTC drivers
733#
734
735#
736# Platform RTC drivers
737#
738# CONFIG_RTC_DRV_DS1286 is not set
739# CONFIG_RTC_DRV_DS1511 is not set
740# CONFIG_RTC_DRV_DS1553 is not set
741# CONFIG_RTC_DRV_DS1742 is not set
742# CONFIG_RTC_DRV_STK17TA8 is not set
743# CONFIG_RTC_DRV_M48T86 is not set
744# CONFIG_RTC_DRV_M48T35 is not set
745CONFIG_RTC_DRV_M48T59=y
746# CONFIG_RTC_DRV_BQ4802 is not set
747# CONFIG_RTC_DRV_V3020 is not set
748
749#
750# on-CPU RTC drivers
751#
752# CONFIG_DMADEVICES is not set
643# CONFIG_UIO is not set 753# CONFIG_UIO is not set
754# CONFIG_STAGING is not set
644 755
645# 756#
646# Misc Linux/SPARC drivers 757# Misc Linux/SPARC drivers
647# 758#
648CONFIG_SUN_OPENPROMIO=m 759CONFIG_SUN_OPENPROMIO=m
649CONFIG_SUN_MOSTEK_RTC=m
650# CONFIG_SUN_BPP is not set
651# CONFIG_SUN_VIDEOPIX is not set
652# CONFIG_TADPOLE_TS102_UCTRL is not set 760# CONFIG_TADPOLE_TS102_UCTRL is not set
653# CONFIG_SUN_JSFLASH is not set 761# CONFIG_SUN_JSFLASH is not set
654 762
655# 763#
656# Unix98 PTY support
657#
658CONFIG_UNIX98_PTY_COUNT=256
659
660#
661# File systems 764# File systems
662# 765#
663CONFIG_EXT2_FS=y 766CONFIG_EXT2_FS=y
@@ -666,11 +769,12 @@ CONFIG_EXT2_FS_POSIX_ACL=y
666CONFIG_EXT2_FS_SECURITY=y 769CONFIG_EXT2_FS_SECURITY=y
667# CONFIG_EXT2_FS_XIP is not set 770# CONFIG_EXT2_FS_XIP is not set
668# CONFIG_EXT3_FS is not set 771# CONFIG_EXT3_FS is not set
669# CONFIG_EXT4DEV_FS is not set 772# CONFIG_EXT4_FS is not set
670CONFIG_FS_MBCACHE=y 773CONFIG_FS_MBCACHE=y
671# CONFIG_REISERFS_FS is not set 774# CONFIG_REISERFS_FS is not set
672# CONFIG_JFS_FS is not set 775# CONFIG_JFS_FS is not set
673CONFIG_FS_POSIX_ACL=y 776CONFIG_FS_POSIX_ACL=y
777CONFIG_FILE_LOCKING=y
674# CONFIG_XFS_FS is not set 778# CONFIG_XFS_FS is not set
675# CONFIG_OCFS2_FS is not set 779# CONFIG_OCFS2_FS is not set
676CONFIG_DNOTIFY=y 780CONFIG_DNOTIFY=y
@@ -702,14 +806,12 @@ CONFIG_ISO9660_FS=m
702CONFIG_PROC_FS=y 806CONFIG_PROC_FS=y
703CONFIG_PROC_KCORE=y 807CONFIG_PROC_KCORE=y
704CONFIG_PROC_SYSCTL=y 808CONFIG_PROC_SYSCTL=y
809CONFIG_PROC_PAGE_MONITOR=y
705CONFIG_SYSFS=y 810CONFIG_SYSFS=y
706# CONFIG_TMPFS is not set 811# CONFIG_TMPFS is not set
707# CONFIG_HUGETLB_PAGE is not set 812# CONFIG_HUGETLB_PAGE is not set
708# CONFIG_CONFIGFS_FS is not set 813# CONFIG_CONFIGFS_FS is not set
709 814CONFIG_MISC_FILESYSTEMS=y
710#
711# Miscellaneous filesystems
712#
713# CONFIG_ADFS_FS is not set 815# CONFIG_ADFS_FS is not set
714# CONFIG_AFFS_FS is not set 816# CONFIG_AFFS_FS is not set
715# CONFIG_HFS_FS is not set 817# CONFIG_HFS_FS is not set
@@ -720,6 +822,7 @@ CONFIG_SYSFS=y
720# CONFIG_CRAMFS is not set 822# CONFIG_CRAMFS is not set
721# CONFIG_VXFS_FS is not set 823# CONFIG_VXFS_FS is not set
722# CONFIG_MINIX_FS is not set 824# CONFIG_MINIX_FS is not set
825# CONFIG_OMFS_FS is not set
723# CONFIG_HPFS_FS is not set 826# CONFIG_HPFS_FS is not set
724# CONFIG_QNX4FS_FS is not set 827# CONFIG_QNX4FS_FS is not set
725CONFIG_ROMFS_FS=m 828CONFIG_ROMFS_FS=m
@@ -729,13 +832,13 @@ CONFIG_NETWORK_FILESYSTEMS=y
729CONFIG_NFS_FS=y 832CONFIG_NFS_FS=y
730# CONFIG_NFS_V3 is not set 833# CONFIG_NFS_V3 is not set
731# CONFIG_NFS_V4 is not set 834# CONFIG_NFS_V4 is not set
732# CONFIG_NFSD is not set
733CONFIG_ROOT_NFS=y 835CONFIG_ROOT_NFS=y
836# CONFIG_NFSD is not set
734CONFIG_LOCKD=y 837CONFIG_LOCKD=y
735CONFIG_NFS_COMMON=y 838CONFIG_NFS_COMMON=y
736CONFIG_SUNRPC=y 839CONFIG_SUNRPC=y
737CONFIG_SUNRPC_GSS=m 840CONFIG_SUNRPC_GSS=m
738# CONFIG_SUNRPC_BIND34 is not set 841# CONFIG_SUNRPC_REGISTER_V4 is not set
739CONFIG_RPCSEC_GSS_KRB5=m 842CONFIG_RPCSEC_GSS_KRB5=m
740# CONFIG_RPCSEC_GSS_SPKM3 is not set 843# CONFIG_RPCSEC_GSS_SPKM3 is not set
741# CONFIG_SMB_FS is not set 844# CONFIG_SMB_FS is not set
@@ -806,9 +909,12 @@ CONFIG_MAGIC_SYSRQ=y
806# CONFIG_HEADERS_CHECK is not set 909# CONFIG_HEADERS_CHECK is not set
807CONFIG_DEBUG_KERNEL=y 910CONFIG_DEBUG_KERNEL=y
808CONFIG_DETECT_SOFTLOCKUP=y 911CONFIG_DETECT_SOFTLOCKUP=y
912# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
913CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
809# CONFIG_SCHED_DEBUG is not set 914# CONFIG_SCHED_DEBUG is not set
810# CONFIG_SCHEDSTATS is not set 915# CONFIG_SCHEDSTATS is not set
811# CONFIG_TIMER_STATS is not set 916# CONFIG_TIMER_STATS is not set
917# CONFIG_DEBUG_OBJECTS is not set
812# CONFIG_DEBUG_SLAB is not set 918# CONFIG_DEBUG_SLAB is not set
813# CONFIG_DEBUG_RT_MUTEXES is not set 919# CONFIG_DEBUG_RT_MUTEXES is not set
814# CONFIG_RT_MUTEX_TESTER is not set 920# CONFIG_RT_MUTEX_TESTER is not set
@@ -822,37 +928,59 @@ CONFIG_DEBUG_BUGVERBOSE=y
822# CONFIG_DEBUG_INFO is not set 928# CONFIG_DEBUG_INFO is not set
823# CONFIG_DEBUG_VM is not set 929# CONFIG_DEBUG_VM is not set
824# CONFIG_DEBUG_WRITECOUNT is not set 930# CONFIG_DEBUG_WRITECOUNT is not set
931CONFIG_DEBUG_MEMORY_INIT=y
825# CONFIG_DEBUG_LIST is not set 932# CONFIG_DEBUG_LIST is not set
826# CONFIG_DEBUG_SG is not set 933# CONFIG_DEBUG_SG is not set
827CONFIG_FRAME_POINTER=y 934# CONFIG_DEBUG_NOTIFIERS is not set
828# CONFIG_BOOT_PRINTK_DELAY is not set 935# CONFIG_BOOT_PRINTK_DELAY is not set
829# CONFIG_RCU_TORTURE_TEST is not set 936# CONFIG_RCU_TORTURE_TEST is not set
937# CONFIG_RCU_CPU_STALL_DETECTOR is not set
830# CONFIG_BACKTRACE_SELF_TEST is not set 938# CONFIG_BACKTRACE_SELF_TEST is not set
939# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
831# CONFIG_FAULT_INJECTION is not set 940# CONFIG_FAULT_INJECTION is not set
941# CONFIG_SYSCTL_SYSCALL_CHECK is not set
942
943#
944# Tracers
945#
946# CONFIG_SCHED_TRACER is not set
947# CONFIG_CONTEXT_SWITCH_TRACER is not set
948# CONFIG_BOOT_TRACER is not set
949# CONFIG_TRACE_BRANCH_PROFILING is not set
950# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
832# CONFIG_SAMPLES is not set 951# CONFIG_SAMPLES is not set
833CONFIG_KGDB=y
834CONFIG_HAVE_ARCH_KGDB=y 952CONFIG_HAVE_ARCH_KGDB=y
953CONFIG_KGDB=y
835CONFIG_KGDB_SERIAL_CONSOLE=y 954CONFIG_KGDB_SERIAL_CONSOLE=y
836CONFIG_KGDB_TESTS=y 955CONFIG_KGDB_TESTS=y
837# CONFIG_KGDB_TESTS_ON_BOOT is not set 956# CONFIG_KGDB_TESTS_ON_BOOT is not set
838# CONFIG_DEBUG_STACK_USAGE is not set 957# CONFIG_DEBUG_STACK_USAGE is not set
958# CONFIG_STACK_DEBUG is not set
839 959
840# 960#
841# Security options 961# Security options
842# 962#
843# CONFIG_KEYS is not set 963# CONFIG_KEYS is not set
844# CONFIG_SECURITY is not set 964# CONFIG_SECURITY is not set
965# CONFIG_SECURITYFS is not set
845# CONFIG_SECURITY_FILE_CAPABILITIES is not set 966# CONFIG_SECURITY_FILE_CAPABILITIES is not set
846CONFIG_CRYPTO=y 967CONFIG_CRYPTO=y
847 968
848# 969#
849# Crypto core or helper 970# Crypto core or helper
850# 971#
972# CONFIG_CRYPTO_FIPS is not set
851CONFIG_CRYPTO_ALGAPI=y 973CONFIG_CRYPTO_ALGAPI=y
974CONFIG_CRYPTO_ALGAPI2=y
852CONFIG_CRYPTO_AEAD=y 975CONFIG_CRYPTO_AEAD=y
976CONFIG_CRYPTO_AEAD2=y
853CONFIG_CRYPTO_BLKCIPHER=y 977CONFIG_CRYPTO_BLKCIPHER=y
978CONFIG_CRYPTO_BLKCIPHER2=y
854CONFIG_CRYPTO_HASH=y 979CONFIG_CRYPTO_HASH=y
980CONFIG_CRYPTO_HASH2=y
981CONFIG_CRYPTO_RNG2=y
855CONFIG_CRYPTO_MANAGER=y 982CONFIG_CRYPTO_MANAGER=y
983CONFIG_CRYPTO_MANAGER2=y
856# CONFIG_CRYPTO_GF128MUL is not set 984# CONFIG_CRYPTO_GF128MUL is not set
857CONFIG_CRYPTO_NULL=m 985CONFIG_CRYPTO_NULL=m
858# CONFIG_CRYPTO_CRYPTD is not set 986# CONFIG_CRYPTO_CRYPTD is not set
@@ -890,6 +1018,10 @@ CONFIG_CRYPTO_CRC32C=m
890CONFIG_CRYPTO_MD4=y 1018CONFIG_CRYPTO_MD4=y
891CONFIG_CRYPTO_MD5=y 1019CONFIG_CRYPTO_MD5=y
892CONFIG_CRYPTO_MICHAEL_MIC=m 1020CONFIG_CRYPTO_MICHAEL_MIC=m
1021# CONFIG_CRYPTO_RMD128 is not set
1022# CONFIG_CRYPTO_RMD160 is not set
1023# CONFIG_CRYPTO_RMD256 is not set
1024# CONFIG_CRYPTO_RMD320 is not set
893CONFIG_CRYPTO_SHA1=y 1025CONFIG_CRYPTO_SHA1=y
894CONFIG_CRYPTO_SHA256=m 1026CONFIG_CRYPTO_SHA256=m
895CONFIG_CRYPTO_SHA512=m 1027CONFIG_CRYPTO_SHA512=m
@@ -921,15 +1053,21 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m
921# 1053#
922CONFIG_CRYPTO_DEFLATE=y 1054CONFIG_CRYPTO_DEFLATE=y
923# CONFIG_CRYPTO_LZO is not set 1055# CONFIG_CRYPTO_LZO is not set
1056
1057#
1058# Random Number Generation
1059#
1060# CONFIG_CRYPTO_ANSI_CPRNG is not set
924# CONFIG_CRYPTO_HW is not set 1061# CONFIG_CRYPTO_HW is not set
925 1062
926# 1063#
927# Library routines 1064# Library routines
928# 1065#
929CONFIG_BITREVERSE=y 1066CONFIG_BITREVERSE=y
930# CONFIG_GENERIC_FIND_FIRST_BIT is not set 1067CONFIG_GENERIC_FIND_LAST_BIT=y
931# CONFIG_CRC_CCITT is not set 1068# CONFIG_CRC_CCITT is not set
932# CONFIG_CRC16 is not set 1069# CONFIG_CRC16 is not set
1070# CONFIG_CRC_T10DIF is not set
933# CONFIG_CRC_ITU_T is not set 1071# CONFIG_CRC_ITU_T is not set
934CONFIG_CRC32=y 1072CONFIG_CRC32=y
935# CONFIG_CRC7 is not set 1073# CONFIG_CRC7 is not set
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
index 73d45521db04..33e31ce6b31f 100644
--- a/arch/sparc/include/asm/oplib_32.h
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -177,17 +177,6 @@ extern void prom_putsegment(int context, unsigned long virt_addr,
177 177
178/* PROM device tree traversal functions... */ 178/* PROM device tree traversal functions... */
179 179
180#ifdef PROMLIB_INTERNAL
181
182/* Internal version of prom_getchild. */
183extern int __prom_getchild(int parent_node);
184
185/* Internal version of prom_getsibling. */
186extern int __prom_getsibling(int node);
187
188#endif
189
190
191/* Get the child node of the given node, or zero if no child exists. */ 180/* Get the child node of the given node, or zero if no child exists. */
192extern int prom_getchild(int parent_node); 181extern int prom_getchild(int parent_node);
193 182
diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h
index 6d2c2ca98039..a5db0317b5fb 100644
--- a/arch/sparc/include/asm/oplib_64.h
+++ b/arch/sparc/include/asm/oplib_64.h
@@ -218,16 +218,6 @@ extern void prom_unmap(unsigned long size, unsigned long vaddr);
218 218
219/* PROM device tree traversal functions... */ 219/* PROM device tree traversal functions... */
220 220
221#ifdef PROMLIB_INTERNAL
222
223/* Internal version of prom_getchild. */
224extern int __prom_getchild(int parent_node);
225
226/* Internal version of prom_getsibling. */
227extern int __prom_getsibling(int node);
228
229#endif
230
231/* Get the child node of the given node, or zero if no child exists. */ 221/* Get the child node of the given node, or zero if no child exists. */
232extern int prom_getchild(int parent_node); 222extern int prom_getchild(int parent_node);
233 223
diff --git a/arch/sparc/include/asm/signal.h b/arch/sparc/include/asm/signal.h
index 41535e77b255..cba45206b7f2 100644
--- a/arch/sparc/include/asm/signal.h
+++ b/arch/sparc/include/asm/signal.h
@@ -84,7 +84,11 @@
84 84
85#define __OLD_NSIG 32 85#define __OLD_NSIG 32
86#define __NEW_NSIG 64 86#define __NEW_NSIG 64
87#ifdef __arch64__
87#define _NSIG_BPW 64 88#define _NSIG_BPW 64
89#else
90#define _NSIG_BPW 32
91#endif
88#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW) 92#define _NSIG_WORDS (__NEW_NSIG / _NSIG_BPW)
89 93
90#define SIGRTMIN 32 94#define SIGRTMIN 32
diff --git a/arch/sparc/include/asm/topology_64.h b/arch/sparc/include/asm/topology_64.h
index b8a65b64e1df..5bc0b8fd6374 100644
--- a/arch/sparc/include/asm/topology_64.h
+++ b/arch/sparc/include/asm/topology_64.h
@@ -47,6 +47,10 @@ static inline int pcibus_to_node(struct pci_bus *pbus)
47 (pcibus_to_node(bus) == -1 ? \ 47 (pcibus_to_node(bus) == -1 ? \
48 CPU_MASK_ALL : \ 48 CPU_MASK_ALL : \
49 node_to_cpumask(pcibus_to_node(bus))) 49 node_to_cpumask(pcibus_to_node(bus)))
50#define cpumask_of_pcibus(bus) \
51 (pcibus_to_node(bus) == -1 ? \
52 CPU_MASK_ALL_PTR : \
53 cpumask_of_node(pcibus_to_node(bus)))
50 54
51#define SD_NODE_INIT (struct sched_domain) { \ 55#define SD_NODE_INIT (struct sched_domain) { \
52 .min_interval = 8, \ 56 .min_interval = 8, \
diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c
index 09c857215a52..45c41232fc4c 100644
--- a/arch/sparc/kernel/auxio_32.c
+++ b/arch/sparc/kernel/auxio_32.c
@@ -76,6 +76,7 @@ unsigned char get_auxio(void)
76 return sbus_readb(auxio_register); 76 return sbus_readb(auxio_register);
77 return 0; 77 return 0;
78} 78}
79EXPORT_SYMBOL(get_auxio);
79 80
80void set_auxio(unsigned char bits_on, unsigned char bits_off) 81void set_auxio(unsigned char bits_on, unsigned char bits_off)
81{ 82{
@@ -102,7 +103,7 @@ void set_auxio(unsigned char bits_on, unsigned char bits_off)
102 }; 103 };
103 spin_unlock_irqrestore(&auxio_lock, flags); 104 spin_unlock_irqrestore(&auxio_lock, flags);
104} 105}
105 106EXPORT_SYMBOL(set_auxio);
106 107
107/* sun4m power control register (AUXIO2) */ 108/* sun4m power control register (AUXIO2) */
108 109
diff --git a/arch/sparc/kernel/auxio_64.c b/arch/sparc/kernel/auxio_64.c
index 8b67347d4221..9f52db2d441c 100644
--- a/arch/sparc/kernel/auxio_64.c
+++ b/arch/sparc/kernel/auxio_64.c
@@ -72,6 +72,7 @@ void auxio_set_led(int on)
72 bit = (ebus ? AUXIO_PCIO_LED : AUXIO_AUX1_LED); 72 bit = (ebus ? AUXIO_PCIO_LED : AUXIO_AUX1_LED);
73 __auxio_set_bit(bit, on, ebus); 73 __auxio_set_bit(bit, on, ebus);
74} 74}
75EXPORT_SYMBOL(auxio_set_led);
75 76
76static void __auxio_sbus_set_lte(int on) 77static void __auxio_sbus_set_lte(int on)
77{ 78{
@@ -90,6 +91,7 @@ void auxio_set_lte(int on)
90 break; 91 break;
91 } 92 }
92} 93}
94EXPORT_SYMBOL(auxio_set_lte);
93 95
94static struct of_device_id __initdata auxio_match[] = { 96static struct of_device_id __initdata auxio_match[] = {
95 { 97 {
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 6c2da2420f76..f0b825505da5 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -5,6 +5,7 @@
5 */ 5 */
6 6
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/module.h>
8#include <linux/init.h> 9#include <linux/init.h>
9#include <linux/smp.h> 10#include <linux/smp.h>
10#include <linux/threads.h> 11#include <linux/threads.h>
@@ -20,6 +21,7 @@
20#include "kernel.h" 21#include "kernel.h"
21 22
22DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; 23DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
24EXPORT_PER_CPU_SYMBOL(__cpu_data);
23 25
24struct cpu_info { 26struct cpu_info {
25 int psr_vers; 27 int psr_vers;
diff --git a/arch/sparc/kernel/idprom.c b/arch/sparc/kernel/idprom.c
index c16135e0c151..57922f69c3f7 100644
--- a/arch/sparc/kernel/idprom.c
+++ b/arch/sparc/kernel/idprom.c
@@ -8,11 +8,14 @@
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/module.h>
11 12
12#include <asm/oplib.h> 13#include <asm/oplib.h>
13#include <asm/idprom.h> 14#include <asm/idprom.h>
14 15
15struct idprom *idprom; 16struct idprom *idprom;
17EXPORT_SYMBOL(idprom);
18
16static struct idprom idprom_buffer; 19static struct idprom idprom_buffer;
17 20
18#ifdef CONFIG_SPARC32 21#ifdef CONFIG_SPARC32
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 7ce14f05eb48..87ea0d03d975 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -120,6 +120,7 @@ void __iomem *ioremap(unsigned long offset, unsigned long size)
120 sprintf(name, "phys_%08x", (u32)offset); 120 sprintf(name, "phys_%08x", (u32)offset);
121 return _sparc_alloc_io(0, offset, size, name); 121 return _sparc_alloc_io(0, offset, size, name);
122} 122}
123EXPORT_SYMBOL(ioremap);
123 124
124/* 125/*
125 * Comlimentary to ioremap(). 126 * Comlimentary to ioremap().
@@ -141,6 +142,7 @@ void iounmap(volatile void __iomem *virtual)
141 kfree(res); 142 kfree(res);
142 } 143 }
143} 144}
145EXPORT_SYMBOL(iounmap);
144 146
145void __iomem *of_ioremap(struct resource *res, unsigned long offset, 147void __iomem *of_ioremap(struct resource *res, unsigned long offset,
146 unsigned long size, char *name) 148 unsigned long size, char *name)
@@ -237,6 +239,7 @@ void sbus_set_sbus64(struct device *dev, int x)
237{ 239{
238 printk("sbus_set_sbus64: unsupported\n"); 240 printk("sbus_set_sbus64: unsupported\n");
239} 241}
242EXPORT_SYMBOL(sbus_set_sbus64);
240 243
241/* 244/*
242 * Allocate a chunk of memory suitable for DMA. 245 * Allocate a chunk of memory suitable for DMA.
@@ -436,6 +439,7 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t len, dma_addr_t *pba)
436 *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */ 439 *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */
437 return (void *) res->start; 440 return (void *) res->start;
438} 441}
442EXPORT_SYMBOL(pci_alloc_consistent);
439 443
440/* Free and unmap a consistent DMA buffer. 444/* Free and unmap a consistent DMA buffer.
441 * cpu_addr is what was returned from pci_alloc_consistent, 445 * cpu_addr is what was returned from pci_alloc_consistent,
@@ -477,6 +481,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t n, void *p, dma_addr_t ba)
477 481
478 free_pages(pgp, get_order(n)); 482 free_pages(pgp, get_order(n));
479} 483}
484EXPORT_SYMBOL(pci_free_consistent);
480 485
481/* Map a single buffer of the indicated size for DMA in streaming mode. 486/* Map a single buffer of the indicated size for DMA in streaming mode.
482 * The 32-bit bus address to use is returned. 487 * The 32-bit bus address to use is returned.
@@ -491,6 +496,7 @@ dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size,
491 /* IIep is write-through, not flushing. */ 496 /* IIep is write-through, not flushing. */
492 return virt_to_phys(ptr); 497 return virt_to_phys(ptr);
493} 498}
499EXPORT_SYMBOL(pci_map_single);
494 500
495/* Unmap a single streaming mode DMA translation. The dma_addr and size 501/* Unmap a single streaming mode DMA translation. The dma_addr and size
496 * must match what was provided for in a previous pci_map_single call. All 502 * must match what was provided for in a previous pci_map_single call. All
@@ -508,6 +514,7 @@ void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t ba, size_t size,
508 (size + PAGE_SIZE-1) & PAGE_MASK); 514 (size + PAGE_SIZE-1) & PAGE_MASK);
509 } 515 }
510} 516}
517EXPORT_SYMBOL(pci_unmap_single);
511 518
512/* 519/*
513 * Same as pci_map_single, but with pages. 520 * Same as pci_map_single, but with pages.
@@ -519,6 +526,7 @@ dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
519 /* IIep is write-through, not flushing. */ 526 /* IIep is write-through, not flushing. */
520 return page_to_phys(page) + offset; 527 return page_to_phys(page) + offset;
521} 528}
529EXPORT_SYMBOL(pci_map_page);
522 530
523void pci_unmap_page(struct pci_dev *hwdev, 531void pci_unmap_page(struct pci_dev *hwdev,
524 dma_addr_t dma_address, size_t size, int direction) 532 dma_addr_t dma_address, size_t size, int direction)
@@ -526,6 +534,7 @@ void pci_unmap_page(struct pci_dev *hwdev,
526 BUG_ON(direction == PCI_DMA_NONE); 534 BUG_ON(direction == PCI_DMA_NONE);
527 /* mmu_inval_dma_area XXX */ 535 /* mmu_inval_dma_area XXX */
528} 536}
537EXPORT_SYMBOL(pci_unmap_page);
529 538
530/* Map a set of buffers described by scatterlist in streaming 539/* Map a set of buffers described by scatterlist in streaming
531 * mode for DMA. This is the scather-gather version of the 540 * mode for DMA. This is the scather-gather version of the
@@ -557,6 +566,7 @@ int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents,
557 } 566 }
558 return nents; 567 return nents;
559} 568}
569EXPORT_SYMBOL(pci_map_sg);
560 570
561/* Unmap a set of streaming mode DMA translations. 571/* Unmap a set of streaming mode DMA translations.
562 * Again, cpu read rules concerning calls here are the same as for 572 * Again, cpu read rules concerning calls here are the same as for
@@ -578,6 +588,7 @@ void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents,
578 } 588 }
579 } 589 }
580} 590}
591EXPORT_SYMBOL(pci_unmap_sg);
581 592
582/* Make physical memory consistent for a single 593/* Make physical memory consistent for a single
583 * streaming mode DMA translation before or after a transfer. 594 * streaming mode DMA translation before or after a transfer.
@@ -597,6 +608,7 @@ void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t ba, size_t si
597 (size + PAGE_SIZE-1) & PAGE_MASK); 608 (size + PAGE_SIZE-1) & PAGE_MASK);
598 } 609 }
599} 610}
611EXPORT_SYMBOL(pci_dma_sync_single_for_cpu);
600 612
601void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t size, int direction) 613void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t size, int direction)
602{ 614{
@@ -606,6 +618,7 @@ void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t
606 (size + PAGE_SIZE-1) & PAGE_MASK); 618 (size + PAGE_SIZE-1) & PAGE_MASK);
607 } 619 }
608} 620}
621EXPORT_SYMBOL(pci_dma_sync_single_for_device);
609 622
610/* Make physical memory consistent for a set of streaming 623/* Make physical memory consistent for a set of streaming
611 * mode DMA translations after a transfer. 624 * mode DMA translations after a transfer.
@@ -628,6 +641,7 @@ void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sgl, int
628 } 641 }
629 } 642 }
630} 643}
644EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu);
631 645
632void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, int direction) 646void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, int direction)
633{ 647{
@@ -644,6 +658,7 @@ void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl,
644 } 658 }
645 } 659 }
646} 660}
661EXPORT_SYMBOL(pci_dma_sync_sg_for_device);
647#endif /* CONFIG_PCI */ 662#endif /* CONFIG_PCI */
648 663
649#ifdef CONFIG_PROC_FS 664#ifdef CONFIG_PROC_FS
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index 1eff942fe22f..44dd5ee64339 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -294,6 +294,7 @@ void synchronize_irq(unsigned int irq)
294 while (sparc_irq[cpu_irq].flags & SPARC_IRQ_INPROGRESS) 294 while (sparc_irq[cpu_irq].flags & SPARC_IRQ_INPROGRESS)
295 cpu_relax(); 295 cpu_relax();
296} 296}
297EXPORT_SYMBOL(synchronize_irq);
297#endif /* SMP */ 298#endif /* SMP */
298 299
299void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs) 300void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs)
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 923e9bbb9fe2..4638fba799e4 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -1077,6 +1077,7 @@ int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
1077 1077
1078 return (device_mask & dma_addr_mask) == dma_addr_mask; 1078 return (device_mask & dma_addr_mask) == dma_addr_mask;
1079} 1079}
1080EXPORT_SYMBOL(pci_dma_supported);
1080 1081
1081void pci_resource_to_user(const struct pci_dev *pdev, int bar, 1082void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1082 const struct resource *rp, resource_size_t *start, 1083 const struct resource *rp, resource_size_t *start,
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index 75ed98be3edf..85e7037429b9 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -956,6 +956,7 @@ void outsb(unsigned long addr, const void *src, unsigned long count)
956 /* addr += 1; */ 956 /* addr += 1; */
957 } 957 }
958} 958}
959EXPORT_SYMBOL(outsb);
959 960
960void outsw(unsigned long addr, const void *src, unsigned long count) 961void outsw(unsigned long addr, const void *src, unsigned long count)
961{ 962{
@@ -966,6 +967,7 @@ void outsw(unsigned long addr, const void *src, unsigned long count)
966 /* addr += 2; */ 967 /* addr += 2; */
967 } 968 }
968} 969}
970EXPORT_SYMBOL(outsw);
969 971
970void outsl(unsigned long addr, const void *src, unsigned long count) 972void outsl(unsigned long addr, const void *src, unsigned long count)
971{ 973{
@@ -976,6 +978,7 @@ void outsl(unsigned long addr, const void *src, unsigned long count)
976 /* addr += 4; */ 978 /* addr += 4; */
977 } 979 }
978} 980}
981EXPORT_SYMBOL(outsl);
979 982
980void insb(unsigned long addr, void *dst, unsigned long count) 983void insb(unsigned long addr, void *dst, unsigned long count)
981{ 984{
@@ -986,6 +989,7 @@ void insb(unsigned long addr, void *dst, unsigned long count)
986 /* addr += 1; */ 989 /* addr += 1; */
987 } 990 }
988} 991}
992EXPORT_SYMBOL(insb);
989 993
990void insw(unsigned long addr, void *dst, unsigned long count) 994void insw(unsigned long addr, void *dst, unsigned long count)
991{ 995{
@@ -996,6 +1000,7 @@ void insw(unsigned long addr, void *dst, unsigned long count)
996 /* addr += 2; */ 1000 /* addr += 2; */
997 } 1001 }
998} 1002}
1003EXPORT_SYMBOL(insw);
999 1004
1000void insl(unsigned long addr, void *dst, unsigned long count) 1005void insl(unsigned long addr, void *dst, unsigned long count)
1001{ 1006{
@@ -1009,5 +1014,6 @@ void insl(unsigned long addr, void *dst, unsigned long count)
1009 /* addr += 4; */ 1014 /* addr += 4; */
1010 } 1015 }
1011} 1016}
1017EXPORT_SYMBOL(insl);
1012 1018
1013subsys_initcall(pcic_init); 1019subsys_initcall(pcic_init);
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index 5a8d8ced33da..f4bee35a1b46 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -44,6 +44,7 @@
44 * Set in pm platform drivers (apc.c and pmc.c) 44 * Set in pm platform drivers (apc.c and pmc.c)
45 */ 45 */
46void (*pm_idle)(void); 46void (*pm_idle)(void);
47EXPORT_SYMBOL(pm_idle);
47 48
48/* 49/*
49 * Power-off handler instantiation for pm.h compliance 50 * Power-off handler instantiation for pm.h compliance
@@ -673,6 +674,7 @@ pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
673 "g1", "g2", "g3", "o0", "o1", "memory", "cc"); 674 "g1", "g2", "g3", "o0", "o1", "memory", "cc");
674 return retval; 675 return retval;
675} 676}
677EXPORT_SYMBOL(kernel_thread);
676 678
677unsigned long get_wchan(struct task_struct *task) 679unsigned long get_wchan(struct task_struct *task)
678{ 680{
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index d5e2acef9877..cc8b5604442c 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -678,6 +678,7 @@ pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
678 "g1", "g2", "g3", "o0", "o1", "memory", "cc"); 678 "g1", "g2", "g3", "o0", "o1", "memory", "cc");
679 return retval; 679 return retval;
680} 680}
681EXPORT_SYMBOL(kernel_thread);
681 682
682typedef struct { 683typedef struct {
683 union { 684 union {
@@ -743,6 +744,7 @@ int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs)
743 } 744 }
744 return 1; 745 return 1;
745} 746}
747EXPORT_SYMBOL(dump_fpu);
746 748
747/* 749/*
748 * sparc_execve() executes a new program after the asm stub has set 750 * sparc_execve() executes a new program after the asm stub has set
diff --git a/arch/sparc/kernel/psycho_common.c b/arch/sparc/kernel/psycho_common.c
index 40689ae3c9b0..8f1478475421 100644
--- a/arch/sparc/kernel/psycho_common.c
+++ b/arch/sparc/kernel/psycho_common.c
@@ -11,19 +11,19 @@
11#include "iommu_common.h" 11#include "iommu_common.h"
12#include "psycho_common.h" 12#include "psycho_common.h"
13 13
14#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL 14#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002ULL
15#define PSYCHO_STCERR_WRITE 0x0000000000000002UL 15#define PSYCHO_STCERR_WRITE 0x0000000000000002ULL
16#define PSYCHO_STCERR_READ 0x0000000000000001UL 16#define PSYCHO_STCERR_READ 0x0000000000000001ULL
17#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL 17#define PSYCHO_STCTAG_PPN 0x0fffffff00000000ULL
18#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL 18#define PSYCHO_STCTAG_VPN 0x00000000ffffe000ULL
19#define PSYCHO_STCTAG_VALID 0x0000000000000002UL 19#define PSYCHO_STCTAG_VALID 0x0000000000000002ULL
20#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL 20#define PSYCHO_STCTAG_WRITE 0x0000000000000001ULL
21#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL 21#define PSYCHO_STCLINE_LINDX 0x0000000001e00000ULL
22#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL 22#define PSYCHO_STCLINE_SPTR 0x00000000001f8000ULL
23#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL 23#define PSYCHO_STCLINE_LADDR 0x0000000000007f00ULL
24#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL 24#define PSYCHO_STCLINE_EPTR 0x00000000000000fcULL
25#define PSYCHO_STCLINE_VALID 0x0000000000000002UL 25#define PSYCHO_STCLINE_VALID 0x0000000000000002ULL
26#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL 26#define PSYCHO_STCLINE_FOFN 0x0000000000000001ULL
27 27
28static DEFINE_SPINLOCK(stc_buf_lock); 28static DEFINE_SPINLOCK(stc_buf_lock);
29static unsigned long stc_error_buf[128]; 29static unsigned long stc_error_buf[128];
@@ -144,10 +144,10 @@ static void psycho_record_iommu_tags_and_data(struct pci_pbm_info *pbm,
144#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL) 144#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
145#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL) 145#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
146#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL) 146#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
147#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL 147#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffULL
148#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL) 148#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
149#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL) 149#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
150#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL 150#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffULL
151 151
152static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm, 152static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm,
153 u64 *tag, u64 *data) 153 u64 *tag, u64 *data)
@@ -190,7 +190,7 @@ static void psycho_dump_iommu_tags_and_data(struct pci_pbm_info *pbm,
190 pbm->name, i, 190 pbm->name, i,
191 ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0), 191 ((data_val & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
192 ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0), 192 ((data_val & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
193 (data_val & PSYCHO_IOMMU_DATA_PPAGE)<<IOMMU_PAGE_SHIFT); 193 (data_val & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
194 } 194 }
195} 195}
196 196
@@ -285,20 +285,20 @@ static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm)
285 return ret; 285 return ret;
286} 286}
287 287
288#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL 288#define PSYCHO_PCIAFSR_PMA 0x8000000000000000ULL
289#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL 289#define PSYCHO_PCIAFSR_PTA 0x4000000000000000ULL
290#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL 290#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000ULL
291#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL 291#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000ULL
292#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL 292#define PSYCHO_PCIAFSR_SMA 0x0800000000000000ULL
293#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL 293#define PSYCHO_PCIAFSR_STA 0x0400000000000000ULL
294#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL 294#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000ULL
295#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL 295#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000ULL
296#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL 296#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000ULL
297#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL 297#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000ULL
298#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL 298#define PSYCHO_PCIAFSR_BLK 0x0000000080000000ULL
299#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL 299#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000ULL
300#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL 300#define PSYCHO_PCIAFSR_MID 0x000000003e000000ULL
301#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL 301#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffULL
302 302
303irqreturn_t psycho_pcierr_intr(int irq, void *dev_id) 303irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
304{ 304{
diff --git a/arch/sparc/kernel/sbus.c b/arch/sparc/kernel/sbus.c
index 2ead310066d1..406e0872504e 100644
--- a/arch/sparc/kernel/sbus.c
+++ b/arch/sparc/kernel/sbus.c
@@ -117,6 +117,7 @@ void sbus_set_sbus64(struct device *dev, int bursts)
117 val |= (1UL << 4UL); 117 val |= (1UL << 4UL);
118 upa_writeq(val, cfg_reg); 118 upa_writeq(val, cfg_reg);
119} 119}
120EXPORT_SYMBOL(sbus_set_sbus64);
120 121
121/* INO number to IMAP register offset for SYSIO external IRQ's. 122/* INO number to IMAP register offset for SYSIO external IRQ's.
122 * This should conform to both Sunfire/Wildfire server and Fusion 123 * This should conform to both Sunfire/Wildfire server and Fusion
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index c96c65d1b58b..998cadb4e7f2 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -199,7 +199,9 @@ extern unsigned short ram_flags;
199extern int root_mountflags; 199extern int root_mountflags;
200 200
201char reboot_command[COMMAND_LINE_SIZE]; 201char reboot_command[COMMAND_LINE_SIZE];
202
202enum sparc_cpu sparc_cpu_model; 203enum sparc_cpu sparc_cpu_model;
204EXPORT_SYMBOL(sparc_cpu_model);
203 205
204struct tt_entry *sparc_ttable; 206struct tt_entry *sparc_ttable;
205 207
@@ -391,6 +393,7 @@ void sun_do_break(void)
391 393
392 prom_cmdline(); 394 prom_cmdline();
393} 395}
396EXPORT_SYMBOL(sun_do_break);
394 397
395int stop_a_enabled = 1; 398int stop_a_enabled = 1;
396 399
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 555db7452ebe..49d061f4ae9d 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -58,6 +58,7 @@
58 * operations in asm/ns87303.h 58 * operations in asm/ns87303.h
59 */ 59 */
60DEFINE_SPINLOCK(ns87303_lock); 60DEFINE_SPINLOCK(ns87303_lock);
61EXPORT_SYMBOL(ns87303_lock);
61 62
62struct screen_info screen_info = { 63struct screen_info screen_info = {
63 0, 0, /* orig-x, orig-y */ 64 0, 0, /* orig-x, orig-y */
@@ -425,5 +426,7 @@ void sun_do_break(void)
425 426
426 prom_cmdline(); 427 prom_cmdline();
427} 428}
429EXPORT_SYMBOL(sun_do_break);
428 430
429int stop_a_enabled = 1; 431int stop_a_enabled = 1;
432EXPORT_SYMBOL(stop_a_enabled);
diff --git a/arch/sparc/kernel/sparc_ksyms_32.c b/arch/sparc/kernel/sparc_ksyms_32.c
index e1e97639231b..baeab8720237 100644
--- a/arch/sparc/kernel/sparc_ksyms_32.c
+++ b/arch/sparc/kernel/sparc_ksyms_32.c
@@ -5,49 +5,14 @@
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 */ 6 */
7 7
8/* Tell string.h we don't want memcpy etc. as cpp defines */
9#define EXPORT_SYMTAB_STROPS
10#define PROMLIB_INTERNAL
11
12#include <linux/module.h> 8#include <linux/module.h>
13#include <linux/init.h> 9#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/in6.h>
20#include <linux/spinlock.h>
21#include <linux/mm.h>
22#include <linux/syscalls.h>
23#ifdef CONFIG_PCI
24#include <linux/pci.h>
25#endif
26#include <linux/pm.h>
27#ifdef CONFIG_HIGHMEM
28#include <linux/highmem.h>
29#endif
30 10
31#include <asm/oplib.h>
32#include <asm/delay.h>
33#include <asm/system.h>
34#include <asm/auxio.h>
35#include <asm/pgtable.h> 11#include <asm/pgtable.h>
36#include <asm/io.h>
37#include <asm/irq.h>
38#include <asm/idprom.h>
39#include <asm/head.h>
40#include <asm/smp.h>
41#include <asm/ptrace.h>
42#include <asm/uaccess.h> 12#include <asm/uaccess.h>
43#include <asm/checksum.h> 13#include <asm/delay.h>
44#ifdef CONFIG_SBUS 14#include <asm/head.h>
45#include <asm/dma.h> 15#include <asm/dma.h>
46#endif
47#include <asm/io-unit.h>
48#include <asm/bug.h>
49
50extern spinlock_t rtc_lock;
51 16
52struct poll { 17struct poll {
53 int fd; 18 int fd;
@@ -55,72 +20,15 @@ struct poll {
55 short revents; 20 short revents;
56}; 21};
57 22
58extern void (*__copy_1page)(void *, const void *); 23/* from entry.S */
59extern void __memmove(void *, const void *, __kernel_size_t);
60extern void (*bzero_1page)(void *);
61extern void *__bzero(void *, size_t);
62extern void *__memscan_zero(void *, size_t);
63extern void *__memscan_generic(void *, int, size_t);
64extern int __strncmp(const char *, const char *, __kernel_size_t);
65
66extern int __ashrdi3(int, int);
67extern int __ashldi3(int, int);
68extern int __lshrdi3(int, int);
69extern int __muldi3(int, int);
70extern int __divdi3(int, int);
71
72/* Private functions with odd calling conventions. */
73extern void ___atomic24_add(void);
74extern void ___atomic24_sub(void);
75extern void ___rw_read_enter(void);
76extern void ___rw_read_try(void);
77extern void ___rw_read_exit(void);
78extern void ___rw_write_enter(void);
79
80/* Alias functions whose names begin with "." and export the aliases.
81 * The module references will be fixed up by module_frob_arch_sections.
82 */
83extern int _Div(int, int);
84extern int _Mul(int, int);
85extern int _Rem(int, int);
86extern unsigned _Udiv(unsigned, unsigned);
87extern unsigned _Umul(unsigned, unsigned);
88extern unsigned _Urem(unsigned, unsigned);
89
90/* used by various drivers */
91EXPORT_SYMBOL(sparc_cpu_model);
92EXPORT_SYMBOL(kernel_thread);
93#ifdef CONFIG_SMP
94// XXX find what uses (or used) these. AV: see asm/spinlock.h
95EXPORT_SYMBOL(___rw_read_enter);
96EXPORT_SYMBOL(___rw_read_try);
97EXPORT_SYMBOL(___rw_read_exit);
98EXPORT_SYMBOL(___rw_write_enter);
99#endif
100
101EXPORT_SYMBOL(sparc_valid_addr_bitmap);
102EXPORT_SYMBOL(phys_base);
103EXPORT_SYMBOL(pfn_base);
104
105/* Atomic operations. */
106EXPORT_SYMBOL(___atomic24_add);
107EXPORT_SYMBOL(___atomic24_sub);
108
109/* Per-CPU information table */
110EXPORT_PER_CPU_SYMBOL(__cpu_data);
111
112#ifdef CONFIG_SMP
113/* IRQ implementation. */
114EXPORT_SYMBOL(synchronize_irq);
115#endif
116
117EXPORT_SYMBOL(__udelay); 24EXPORT_SYMBOL(__udelay);
118EXPORT_SYMBOL(__ndelay); 25EXPORT_SYMBOL(__ndelay);
119EXPORT_SYMBOL(rtc_lock);
120EXPORT_SYMBOL(set_auxio);
121EXPORT_SYMBOL(get_auxio);
122EXPORT_SYMBOL(io_remap_pfn_range);
123 26
27/* from head_32.S */
28EXPORT_SYMBOL(__ret_efault);
29EXPORT_SYMBOL(empty_zero_page);
30
31/* Defined using magic */
124#ifndef CONFIG_SMP 32#ifndef CONFIG_SMP
125EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32)); 33EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32));
126#else 34#else
@@ -132,122 +40,7 @@ EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_sgl));
132EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_one)); 40EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_one));
133EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_sgl)); 41EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_sgl));
134EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one)); 42EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one));
135
136EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached)); 43EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached));
137 44
138#ifdef CONFIG_SBUS 45/* Exporting a symbol from /init/main.c */
139EXPORT_SYMBOL(sbus_set_sbus64);
140#endif
141#ifdef CONFIG_PCI
142EXPORT_SYMBOL(insb);
143EXPORT_SYMBOL(outsb);
144EXPORT_SYMBOL(insw);
145EXPORT_SYMBOL(outsw);
146EXPORT_SYMBOL(insl);
147EXPORT_SYMBOL(outsl);
148EXPORT_SYMBOL(pci_alloc_consistent);
149EXPORT_SYMBOL(pci_free_consistent);
150EXPORT_SYMBOL(pci_map_single);
151EXPORT_SYMBOL(pci_unmap_single);
152EXPORT_SYMBOL(pci_dma_sync_single_for_cpu);
153EXPORT_SYMBOL(pci_dma_sync_single_for_device);
154EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu);
155EXPORT_SYMBOL(pci_dma_sync_sg_for_device);
156EXPORT_SYMBOL(pci_map_sg);
157EXPORT_SYMBOL(pci_unmap_sg);
158EXPORT_SYMBOL(pci_map_page);
159EXPORT_SYMBOL(pci_unmap_page);
160/* Actually, ioremap/iounmap are not PCI specific. But it is ok for drivers. */
161EXPORT_SYMBOL(ioremap);
162EXPORT_SYMBOL(iounmap);
163#endif
164
165/* in arch/sparc/mm/highmem.c */
166#ifdef CONFIG_HIGHMEM
167EXPORT_SYMBOL(kmap_atomic);
168EXPORT_SYMBOL(kunmap_atomic);
169#endif
170
171/* prom symbols */
172EXPORT_SYMBOL(idprom);
173EXPORT_SYMBOL(prom_root_node);
174EXPORT_SYMBOL(prom_getchild);
175EXPORT_SYMBOL(prom_getsibling);
176EXPORT_SYMBOL(prom_searchsiblings);
177EXPORT_SYMBOL(prom_firstprop);
178EXPORT_SYMBOL(prom_nextprop);
179EXPORT_SYMBOL(prom_getproplen);
180EXPORT_SYMBOL(prom_getproperty);
181EXPORT_SYMBOL(prom_node_has_property);
182EXPORT_SYMBOL(prom_setprop);
183EXPORT_SYMBOL(saved_command_line); 46EXPORT_SYMBOL(saved_command_line);
184EXPORT_SYMBOL(prom_apply_obio_ranges);
185EXPORT_SYMBOL(prom_feval);
186EXPORT_SYMBOL(prom_getbool);
187EXPORT_SYMBOL(prom_getstring);
188EXPORT_SYMBOL(prom_getint);
189EXPORT_SYMBOL(prom_getintdefault);
190EXPORT_SYMBOL(prom_finddevice);
191EXPORT_SYMBOL(romvec);
192EXPORT_SYMBOL(__prom_getchild);
193EXPORT_SYMBOL(__prom_getsibling);
194
195/* sparc library symbols */
196EXPORT_SYMBOL(memscan);
197EXPORT_SYMBOL(strlen);
198EXPORT_SYMBOL(strncmp);
199EXPORT_SYMBOL(page_kernel);
200
201/* Special internal versions of library functions. */
202EXPORT_SYMBOL(__copy_1page);
203EXPORT_SYMBOL(__memcpy);
204EXPORT_SYMBOL(__memset);
205EXPORT_SYMBOL(bzero_1page);
206EXPORT_SYMBOL(__bzero);
207EXPORT_SYMBOL(__memscan_zero);
208EXPORT_SYMBOL(__memscan_generic);
209EXPORT_SYMBOL(__strncmp);
210EXPORT_SYMBOL(__memmove);
211
212/* Moving data to/from userspace. */
213EXPORT_SYMBOL(__copy_user);
214EXPORT_SYMBOL(__strncpy_from_user);
215EXPORT_SYMBOL(__strnlen_user);
216
217/* Networking helper routines. */
218EXPORT_SYMBOL(__csum_partial_copy_sparc_generic);
219EXPORT_SYMBOL(csum_partial);
220
221/* Cache flushing. */
222EXPORT_SYMBOL(sparc_flush_page_to_ram);
223
224/* For when serial stuff is built as modules. */
225EXPORT_SYMBOL(sun_do_break);
226
227EXPORT_SYMBOL(__ret_efault);
228
229EXPORT_SYMBOL(memcmp);
230EXPORT_SYMBOL(memcpy);
231EXPORT_SYMBOL(memset);
232EXPORT_SYMBOL(memmove);
233EXPORT_SYMBOL(__ashrdi3);
234EXPORT_SYMBOL(__ashldi3);
235EXPORT_SYMBOL(__lshrdi3);
236EXPORT_SYMBOL(__muldi3);
237EXPORT_SYMBOL(__divdi3);
238
239EXPORT_SYMBOL(_Rem);
240EXPORT_SYMBOL(_Urem);
241EXPORT_SYMBOL(_Mul);
242EXPORT_SYMBOL(_Umul);
243EXPORT_SYMBOL(_Div);
244EXPORT_SYMBOL(_Udiv);
245
246#ifdef CONFIG_DEBUG_BUGVERBOSE
247EXPORT_SYMBOL(do_BUG);
248#endif
249
250/* Sun Power Management Idle Handler */
251EXPORT_SYMBOL(pm_idle);
252
253EXPORT_SYMBOL(empty_zero_page);
diff --git a/arch/sparc/kernel/sparc_ksyms_64.c b/arch/sparc/kernel/sparc_ksyms_64.c
index 0133211ab634..da8f804feb49 100644
--- a/arch/sparc/kernel/sparc_ksyms_64.c
+++ b/arch/sparc/kernel/sparc_ksyms_64.c
@@ -5,50 +5,16 @@
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 */ 6 */
7 7
8/* Tell string.h we don't want memcpy etc. as cpp defines */
9#define EXPORT_SYMTAB_STROPS
10#define PROMLIB_INTERNAL
11
12#include <linux/module.h> 8#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/string.h>
15#include <linux/sched.h>
16#include <linux/in6.h>
17#include <linux/pci.h> 9#include <linux/pci.h>
18#include <linux/interrupt.h>
19#include <linux/fs_struct.h>
20#include <linux/fs.h>
21#include <linux/mm.h>
22#include <linux/socket.h>
23#include <linux/syscalls.h>
24#include <linux/percpu.h>
25#include <linux/init.h> 10#include <linux/init.h>
26#include <linux/rwsem.h>
27#include <net/compat.h>
28 11
29#include <asm/oplib.h> 12#include <asm/spinlock.h>
30#include <asm/system.h> 13#include <asm/system.h>
31#include <asm/auxio.h>
32#include <asm/pgtable.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/idprom.h>
36#include <asm/elf.h>
37#include <asm/head.h>
38#include <asm/smp.h>
39#include <asm/ptrace.h>
40#include <asm/uaccess.h>
41#include <asm/checksum.h>
42#include <asm/fpumacro.h>
43#include <asm/pgalloc.h>
44#include <asm/cacheflush.h>
45#ifdef CONFIG_SBUS
46#include <asm/dma.h>
47#endif
48#include <asm/ns87303.h>
49#include <asm/timer.h>
50#include <asm/cpudata.h> 14#include <asm/cpudata.h>
51#include <asm/ftrace.h> 15#include <asm/uaccess.h>
16#include <asm/spitfire.h>
17#include <asm/oplib.h>
52#include <asm/hypervisor.h> 18#include <asm/hypervisor.h>
53 19
54struct poll { 20struct poll {
@@ -57,42 +23,6 @@ struct poll {
57 short revents; 23 short revents;
58}; 24};
59 25
60extern void die_if_kernel(char *str, struct pt_regs *regs);
61extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
62extern void *__bzero(void *, size_t);
63extern void *__memscan_zero(void *, size_t);
64extern void *__memscan_generic(void *, int, size_t);
65extern __kernel_size_t strlen(const char *);
66extern void sys_sigsuspend(void);
67extern int compat_sys_ioctl(unsigned int fd, unsigned int cmd, u32 arg);
68extern int (*handle_mathemu)(struct pt_regs *, struct fpustate *);
69extern long sparc32_open(const char __user * filename, int flags, int mode);
70extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
71 unsigned long pfn, unsigned long size, pgprot_t prot);
72
73extern int __ashrdi3(int, int);
74
75extern int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs);
76
77extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
78extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
79 unsigned long *);
80extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *,
81 unsigned long *, unsigned long *);
82extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *,
83 unsigned long *, unsigned long *, unsigned long *);
84
85extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *);
86extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *,
87 unsigned long *);
88extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *,
89 unsigned long *, unsigned long *);
90extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *,
91 unsigned long *, unsigned long *, unsigned long *);
92
93/* Per-CPU information table */
94EXPORT_PER_CPU_SYMBOL(__cpu_data);
95
96/* used by various drivers */ 26/* used by various drivers */
97#ifdef CONFIG_SMP 27#ifdef CONFIG_SMP
98/* Out of line rw-locking implementation. */ 28/* Out of line rw-locking implementation. */
@@ -103,68 +33,24 @@ EXPORT_SYMBOL(__write_unlock);
103EXPORT_SYMBOL(__write_trylock); 33EXPORT_SYMBOL(__write_trylock);
104#endif /* CONFIG_SMP */ 34#endif /* CONFIG_SMP */
105 35
106#ifdef CONFIG_MCOUNT 36/* from helpers.S */
107EXPORT_SYMBOL(_mcount);
108#endif
109
110EXPORT_SYMBOL(sparc64_get_clock_tick);
111
112/* RW semaphores */
113EXPORT_SYMBOL(__down_read);
114EXPORT_SYMBOL(__down_read_trylock);
115EXPORT_SYMBOL(__down_write);
116EXPORT_SYMBOL(__down_write_trylock);
117EXPORT_SYMBOL(__up_read);
118EXPORT_SYMBOL(__up_write);
119EXPORT_SYMBOL(__downgrade_write);
120
121/* Atomic counter implementation. */
122EXPORT_SYMBOL(atomic_add);
123EXPORT_SYMBOL(atomic_add_ret);
124EXPORT_SYMBOL(atomic_sub);
125EXPORT_SYMBOL(atomic_sub_ret);
126EXPORT_SYMBOL(atomic64_add);
127EXPORT_SYMBOL(atomic64_add_ret);
128EXPORT_SYMBOL(atomic64_sub);
129EXPORT_SYMBOL(atomic64_sub_ret);
130
131/* Atomic bit operations. */
132EXPORT_SYMBOL(test_and_set_bit);
133EXPORT_SYMBOL(test_and_clear_bit);
134EXPORT_SYMBOL(test_and_change_bit);
135EXPORT_SYMBOL(set_bit);
136EXPORT_SYMBOL(clear_bit);
137EXPORT_SYMBOL(change_bit);
138
139EXPORT_SYMBOL(__flushw_user); 37EXPORT_SYMBOL(__flushw_user);
38EXPORT_SYMBOL_GPL(real_hard_smp_processor_id);
140 39
40/* from head_64.S */
41EXPORT_SYMBOL(__ret_efault);
141EXPORT_SYMBOL(tlb_type); 42EXPORT_SYMBOL(tlb_type);
142EXPORT_SYMBOL(sun4v_chip_type); 43EXPORT_SYMBOL(sun4v_chip_type);
143EXPORT_SYMBOL(get_fb_unmapped_area); 44EXPORT_SYMBOL(prom_root_node);
144EXPORT_SYMBOL(flush_icache_range);
145
146EXPORT_SYMBOL(flush_dcache_page);
147#ifdef DCACHE_ALIASING_POSSIBLE
148EXPORT_SYMBOL(__flush_dcache_range);
149#endif
150 45
46/* from hvcalls.S */
151EXPORT_SYMBOL(sun4v_niagara_getperf); 47EXPORT_SYMBOL(sun4v_niagara_getperf);
152EXPORT_SYMBOL(sun4v_niagara_setperf); 48EXPORT_SYMBOL(sun4v_niagara_setperf);
153EXPORT_SYMBOL(sun4v_niagara2_getperf); 49EXPORT_SYMBOL(sun4v_niagara2_getperf);
154EXPORT_SYMBOL(sun4v_niagara2_setperf); 50EXPORT_SYMBOL(sun4v_niagara2_setperf);
155 51
156EXPORT_SYMBOL(auxio_set_led);
157EXPORT_SYMBOL(auxio_set_lte);
158#ifdef CONFIG_SBUS
159EXPORT_SYMBOL(sbus_set_sbus64);
160#endif
161EXPORT_SYMBOL(outsb);
162EXPORT_SYMBOL(outsw);
163EXPORT_SYMBOL(outsl);
164EXPORT_SYMBOL(insb);
165EXPORT_SYMBOL(insw);
166EXPORT_SYMBOL(insl);
167#ifdef CONFIG_PCI 52#ifdef CONFIG_PCI
53/* inline functions in asm/pci_64.h */
168EXPORT_SYMBOL(pci_alloc_consistent); 54EXPORT_SYMBOL(pci_alloc_consistent);
169EXPORT_SYMBOL(pci_free_consistent); 55EXPORT_SYMBOL(pci_free_consistent);
170EXPORT_SYMBOL(pci_map_single); 56EXPORT_SYMBOL(pci_map_single);
@@ -173,112 +59,7 @@ EXPORT_SYMBOL(pci_map_sg);
173EXPORT_SYMBOL(pci_unmap_sg); 59EXPORT_SYMBOL(pci_unmap_sg);
174EXPORT_SYMBOL(pci_dma_sync_single_for_cpu); 60EXPORT_SYMBOL(pci_dma_sync_single_for_cpu);
175EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu); 61EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu);
176EXPORT_SYMBOL(pci_dma_supported);
177#endif 62#endif
178 63
179/* I/O device mmaping on Sparc64. */ 64/* Exporting a symbol from /init/main.c */
180EXPORT_SYMBOL(io_remap_pfn_range);
181
182EXPORT_SYMBOL(dump_fpu);
183
184/* math-emu wants this */
185EXPORT_SYMBOL(die_if_kernel);
186
187/* Kernel thread creation. */
188EXPORT_SYMBOL(kernel_thread);
189
190/* prom symbols */
191EXPORT_SYMBOL(idprom);
192EXPORT_SYMBOL(prom_root_node);
193EXPORT_SYMBOL(prom_getchild);
194EXPORT_SYMBOL(prom_getsibling);
195EXPORT_SYMBOL(prom_searchsiblings);
196EXPORT_SYMBOL(prom_firstprop);
197EXPORT_SYMBOL(prom_nextprop);
198EXPORT_SYMBOL(prom_getproplen);
199EXPORT_SYMBOL(prom_getproperty);
200EXPORT_SYMBOL(prom_node_has_property);
201EXPORT_SYMBOL(prom_setprop);
202EXPORT_SYMBOL(saved_command_line); 65EXPORT_SYMBOL(saved_command_line);
203EXPORT_SYMBOL(prom_finddevice);
204EXPORT_SYMBOL(prom_feval);
205EXPORT_SYMBOL(prom_getbool);
206EXPORT_SYMBOL(prom_getstring);
207EXPORT_SYMBOL(prom_getint);
208EXPORT_SYMBOL(prom_getintdefault);
209EXPORT_SYMBOL(__prom_getchild);
210EXPORT_SYMBOL(__prom_getsibling);
211
212/* sparc library symbols */
213EXPORT_SYMBOL(strlen);
214EXPORT_SYMBOL(__strlen_user);
215EXPORT_SYMBOL(__strnlen_user);
216
217/* Special internal versions of library functions. */
218EXPORT_SYMBOL(_clear_page);
219EXPORT_SYMBOL(clear_user_page);
220EXPORT_SYMBOL(copy_user_page);
221EXPORT_SYMBOL(__bzero);
222EXPORT_SYMBOL(__memscan_zero);
223EXPORT_SYMBOL(__memscan_generic);
224EXPORT_SYMBOL(__memset);
225
226EXPORT_SYMBOL(csum_partial);
227EXPORT_SYMBOL(csum_partial_copy_nocheck);
228EXPORT_SYMBOL(__csum_partial_copy_from_user);
229EXPORT_SYMBOL(__csum_partial_copy_to_user);
230EXPORT_SYMBOL(ip_fast_csum);
231
232/* Moving data to/from/in userspace. */
233EXPORT_SYMBOL(___copy_to_user);
234EXPORT_SYMBOL(___copy_from_user);
235EXPORT_SYMBOL(___copy_in_user);
236EXPORT_SYMBOL(copy_to_user_fixup);
237EXPORT_SYMBOL(copy_from_user_fixup);
238EXPORT_SYMBOL(copy_in_user_fixup);
239EXPORT_SYMBOL(__strncpy_from_user);
240EXPORT_SYMBOL(__clear_user);
241
242/* Various address conversion macros use this. */
243EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
244
245/* No version information on this, heavily used in inline asm,
246 * and will always be 'void __ret_efault(void)'.
247 */
248EXPORT_SYMBOL(__ret_efault);
249
250/* No version information on these, as gcc produces such symbols. */
251EXPORT_SYMBOL(memcmp);
252EXPORT_SYMBOL(memcpy);
253EXPORT_SYMBOL(memset);
254EXPORT_SYMBOL(memmove);
255EXPORT_SYMBOL(strncmp);
256
257void VISenter(void);
258/* RAID code needs this */
259EXPORT_SYMBOL(VISenter);
260
261/* for input/keybdev */
262EXPORT_SYMBOL(sun_do_break);
263EXPORT_SYMBOL(stop_a_enabled);
264
265#ifdef CONFIG_DEBUG_BUGVERBOSE
266EXPORT_SYMBOL(do_BUG);
267#endif
268
269/* for ns8703 */
270EXPORT_SYMBOL(ns87303_lock);
271
272EXPORT_SYMBOL(tick_ops);
273
274EXPORT_SYMBOL(xor_vis_2);
275EXPORT_SYMBOL(xor_vis_3);
276EXPORT_SYMBOL(xor_vis_4);
277EXPORT_SYMBOL(xor_vis_5);
278
279EXPORT_SYMBOL(xor_niagara_2);
280EXPORT_SYMBOL(xor_niagara_3);
281EXPORT_SYMBOL(xor_niagara_4);
282EXPORT_SYMBOL(xor_niagara_5);
283
284EXPORT_SYMBOL_GPL(real_hard_smp_processor_id);
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index 16ab0cb731c5..50afaed99c8a 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -60,7 +60,7 @@ extern int __smp4d_processor_id(void);
60#define SMP_PRINTK(x) 60#define SMP_PRINTK(x)
61#endif 61#endif
62 62
63static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val) 63static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
64{ 64{
65 __asm__ __volatile__("swap [%1], %0\n\t" : 65 __asm__ __volatile__("swap [%1], %0\n\t" :
66 "=&r" (val), "=&r" (ptr) : 66 "=&r" (val), "=&r" (ptr) :
@@ -115,7 +115,7 @@ void __cpuinit smp4d_callin(void)
115 local_flush_tlb_all(); 115 local_flush_tlb_all();
116 116
117 /* Allow master to continue. */ 117 /* Allow master to continue. */
118 swap((unsigned long *)&cpu_callin_map[cpuid], 1); 118 sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
119 local_flush_cache_all(); 119 local_flush_cache_all();
120 local_flush_tlb_all(); 120 local_flush_tlb_all();
121 121
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index 4f8d60586b07..8040376c4890 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -54,7 +54,8 @@ extern int __smp4m_processor_id(void);
54#define SMP_PRINTK(x) 54#define SMP_PRINTK(x)
55#endif 55#endif
56 56
57static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val) 57static inline unsigned long
58swap_ulong(volatile unsigned long *ptr, unsigned long val)
58{ 59{
59 __asm__ __volatile__("swap [%1], %0\n\t" : 60 __asm__ __volatile__("swap [%1], %0\n\t" :
60 "=&r" (val), "=&r" (ptr) : 61 "=&r" (val), "=&r" (ptr) :
@@ -90,7 +91,7 @@ void __cpuinit smp4m_callin(void)
90 * to call the scheduler code. 91 * to call the scheduler code.
91 */ 92 */
92 /* Allow master to continue. */ 93 /* Allow master to continue. */
93 swap(&cpu_callin_map[cpuid], 1); 94 swap_ulong(&cpu_callin_map[cpuid], 1);
94 95
95 /* XXX: What's up with all the flushes? */ 96 /* XXX: What's up with all the flushes? */
96 local_flush_cache_all(); 97 local_flush_cache_all();
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 39749e32dc7e..09058fc39e73 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -23,6 +23,7 @@
23#include <linux/ipc.h> 23#include <linux/ipc.h>
24#include <linux/personality.h> 24#include <linux/personality.h>
25#include <linux/random.h> 25#include <linux/random.h>
26#include <linux/module.h>
26 27
27#include <asm/uaccess.h> 28#include <asm/uaccess.h>
28#include <asm/utrap.h> 29#include <asm/utrap.h>
@@ -354,6 +355,7 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr, u
354 355
355 return addr; 356 return addr;
356} 357}
358EXPORT_SYMBOL(get_fb_unmapped_area);
357 359
358/* Essentially the same as PowerPC... */ 360/* Essentially the same as PowerPC... */
359void arch_pick_mmap_layout(struct mm_struct *mm) 361void arch_pick_mmap_layout(struct mm_struct *mm)
diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c
index 00f7383c7657..614ac7b4a9dd 100644
--- a/arch/sparc/kernel/time_32.c
+++ b/arch/sparc/kernel/time_32.c
@@ -48,6 +48,8 @@
48#include "irq.h" 48#include "irq.h"
49 49
50DEFINE_SPINLOCK(rtc_lock); 50DEFINE_SPINLOCK(rtc_lock);
51EXPORT_SYMBOL(rtc_lock);
52
51static int set_rtc_mmss(unsigned long); 53static int set_rtc_mmss(unsigned long);
52static int sbus_do_settimeofday(struct timespec *tv); 54static int sbus_do_settimeofday(struct timespec *tv);
53 55
diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c
index 54405d362148..2db3c2229b95 100644
--- a/arch/sparc/kernel/time_64.c
+++ b/arch/sparc/kernel/time_64.c
@@ -176,6 +176,7 @@ static struct sparc64_tick_ops tick_operations __read_mostly = {
176}; 176};
177 177
178struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; 178struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations;
179EXPORT_SYMBOL(tick_ops);
179 180
180static void stick_disable_irq(void) 181static void stick_disable_irq(void)
181{ 182{
@@ -639,6 +640,7 @@ unsigned long sparc64_get_clock_tick(unsigned int cpu)
639 return ft->clock_tick_ref; 640 return ft->clock_tick_ref;
640 return cpu_data(cpu).clock_tick; 641 return cpu_data(cpu).clock_tick;
641} 642}
643EXPORT_SYMBOL(sparc64_get_clock_tick);
642 644
643#ifdef CONFIG_CPU_FREQ 645#ifdef CONFIG_CPU_FREQ
644 646
diff --git a/arch/sparc/kernel/traps_32.c b/arch/sparc/kernel/traps_32.c
index 213645be6e92..358283341b47 100644
--- a/arch/sparc/kernel/traps_32.c
+++ b/arch/sparc/kernel/traps_32.c
@@ -424,6 +424,7 @@ void do_BUG(const char *file, int line)
424 // bust_spinlocks(1); XXX Not in our original BUG() 424 // bust_spinlocks(1); XXX Not in our original BUG()
425 printk("kernel BUG at %s:%d!\n", file, line); 425 printk("kernel BUG at %s:%d!\n", file, line);
426} 426}
427EXPORT_SYMBOL(do_BUG);
427#endif 428#endif
428 429
429/* Since we have our mappings set up, on multiprocessors we can spin them 430/* Since we have our mappings set up, on multiprocessors we can spin them
diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c
index bca3b4e09c41..c2d153d46586 100644
--- a/arch/sparc/kernel/traps_64.c
+++ b/arch/sparc/kernel/traps_64.c
@@ -128,6 +128,7 @@ void do_BUG(const char *file, int line)
128 bust_spinlocks(1); 128 bust_spinlocks(1);
129 printk("kernel BUG at %s:%d!\n", file, line); 129 printk("kernel BUG at %s:%d!\n", file, line);
130} 130}
131EXPORT_SYMBOL(do_BUG);
131#endif 132#endif
132 133
133static DEFINE_SPINLOCK(dimm_handler_lock); 134static DEFINE_SPINLOCK(dimm_handler_lock);
@@ -2261,6 +2262,7 @@ void die_if_kernel(char *str, struct pt_regs *regs)
2261 do_exit(SIGKILL); 2262 do_exit(SIGKILL);
2262 do_exit(SIGSEGV); 2263 do_exit(SIGSEGV);
2263} 2264}
2265EXPORT_SYMBOL(die_if_kernel);
2264 2266
2265#define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) 2267#define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2266#define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) 2268#define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c
index f164d5a850f9..379209982a07 100644
--- a/arch/sparc/kernel/unaligned_64.c
+++ b/arch/sparc/kernel/unaligned_64.c
@@ -589,7 +589,6 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
589 unsigned long pc = regs->tpc; 589 unsigned long pc = regs->tpc;
590 unsigned long tstate = regs->tstate; 590 unsigned long tstate = regs->tstate;
591 u32 insn; 591 u32 insn;
592 u32 first, second;
593 u64 value; 592 u64 value;
594 u8 freg; 593 u8 freg;
595 int flag; 594 int flag;
@@ -601,19 +600,20 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
601 pc = (u32)pc; 600 pc = (u32)pc;
602 if (get_user(insn, (u32 __user *) pc) != -EFAULT) { 601 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
603 int asi = decode_asi(insn, regs); 602 int asi = decode_asi(insn, regs);
603 u32 first, second;
604 int err; 604 int err;
605 605
606 if ((asi > ASI_SNFL) || 606 if ((asi > ASI_SNFL) ||
607 (asi < ASI_P)) 607 (asi < ASI_P))
608 goto daex; 608 goto daex;
609 first = second = 0;
609 err = get_user(first, (u32 __user *)sfar); 610 err = get_user(first, (u32 __user *)sfar);
610 if (!err) 611 if (!err)
611 err = get_user(second, (u32 __user *)(sfar + 4)); 612 err = get_user(second, (u32 __user *)(sfar + 4));
612 if (err) { 613 if (err) {
613 if (asi & 0x2) /* NF */ { 614 if (!(asi & 0x2))
614 first = 0; second = 0;
615 } else
616 goto daex; 615 goto daex;
616 first = second = 0;
617 } 617 }
618 save_and_clear_fpu(); 618 save_and_clear_fpu();
619 freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20); 619 freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
index 375016e19144..273fc85269fc 100644
--- a/arch/sparc/lib/Makefile
+++ b/arch/sparc/lib/Makefile
@@ -42,3 +42,4 @@ lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o
42 42
43obj-y += iomap.o 43obj-y += iomap.o
44obj-$(CONFIG_SPARC32) += atomic32.o 44obj-$(CONFIG_SPARC32) += atomic32.o
45obj-y += ksyms.o
diff --git a/arch/sparc/lib/PeeCeeI.c b/arch/sparc/lib/PeeCeeI.c
index 46053e6ddd7b..6529f8657597 100644
--- a/arch/sparc/lib/PeeCeeI.c
+++ b/arch/sparc/lib/PeeCeeI.c
@@ -4,6 +4,8 @@
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) 4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */ 5 */
6 6
7#include <linux/module.h>
8
7#include <asm/io.h> 9#include <asm/io.h>
8#include <asm/byteorder.h> 10#include <asm/byteorder.h>
9 11
@@ -15,6 +17,7 @@ void outsb(unsigned long __addr, const void *src, unsigned long count)
15 while (count--) 17 while (count--)
16 outb(*p++, addr); 18 outb(*p++, addr);
17} 19}
20EXPORT_SYMBOL(outsb);
18 21
19void outsw(unsigned long __addr, const void *src, unsigned long count) 22void outsw(unsigned long __addr, const void *src, unsigned long count)
20{ 23{
@@ -25,6 +28,7 @@ void outsw(unsigned long __addr, const void *src, unsigned long count)
25 src += sizeof(u16); 28 src += sizeof(u16);
26 } 29 }
27} 30}
31EXPORT_SYMBOL(outsw);
28 32
29void outsl(unsigned long __addr, const void *src, unsigned long count) 33void outsl(unsigned long __addr, const void *src, unsigned long count)
30{ 34{
@@ -78,6 +82,7 @@ void outsl(unsigned long __addr, const void *src, unsigned long count)
78 break; 82 break;
79 } 83 }
80} 84}
85EXPORT_SYMBOL(outsl);
81 86
82void insb(unsigned long __addr, void *dst, unsigned long count) 87void insb(unsigned long __addr, void *dst, unsigned long count)
83{ 88{
@@ -105,6 +110,7 @@ void insb(unsigned long __addr, void *dst, unsigned long count)
105 *pb++ = inb(addr); 110 *pb++ = inb(addr);
106 } 111 }
107} 112}
113EXPORT_SYMBOL(insb);
108 114
109void insw(unsigned long __addr, void *dst, unsigned long count) 115void insw(unsigned long __addr, void *dst, unsigned long count)
110{ 116{
@@ -132,6 +138,7 @@ void insw(unsigned long __addr, void *dst, unsigned long count)
132 *ps = le16_to_cpu(inw(addr)); 138 *ps = le16_to_cpu(inw(addr));
133 } 139 }
134} 140}
141EXPORT_SYMBOL(insw);
135 142
136void insl(unsigned long __addr, void *dst, unsigned long count) 143void insl(unsigned long __addr, void *dst, unsigned long count)
137{ 144{
@@ -200,4 +207,5 @@ void insl(unsigned long __addr, void *dst, unsigned long count)
200 } 207 }
201 } 208 }
202} 209}
210EXPORT_SYMBOL(insl);
203 211
diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c
new file mode 100644
index 000000000000..704b12668388
--- /dev/null
+++ b/arch/sparc/lib/ksyms.c
@@ -0,0 +1,196 @@
1/*
2 * Export of symbols defined in assembler
3 */
4
5/* Tell string.h we don't want memcpy etc. as cpp defines */
6#define EXPORT_SYMTAB_STROPS
7
8#include <linux/module.h>
9#include <linux/string.h>
10#include <linux/types.h>
11
12#include <asm/checksum.h>
13#include <asm/uaccess.h>
14#include <asm/ftrace.h>
15
16/* string functions */
17EXPORT_SYMBOL(strlen);
18EXPORT_SYMBOL(__strlen_user);
19EXPORT_SYMBOL(__strnlen_user);
20EXPORT_SYMBOL(strncmp);
21
22/* mem* functions */
23extern void *__memscan_zero(void *, size_t);
24extern void *__memscan_generic(void *, int, size_t);
25extern void *__bzero(void *, size_t);
26
27EXPORT_SYMBOL(memscan);
28EXPORT_SYMBOL(__memscan_zero);
29EXPORT_SYMBOL(__memscan_generic);
30EXPORT_SYMBOL(memcmp);
31EXPORT_SYMBOL(memcpy);
32EXPORT_SYMBOL(memset);
33EXPORT_SYMBOL(__memset);
34EXPORT_SYMBOL(memmove);
35EXPORT_SYMBOL(__bzero);
36
37/* Moving data to/from/in userspace. */
38EXPORT_SYMBOL(__strncpy_from_user);
39
40/* Networking helper routines. */
41EXPORT_SYMBOL(csum_partial);
42
43#ifdef CONFIG_MCOUNT
44EXPORT_SYMBOL(_mcount);
45#endif
46
47/*
48 * sparc
49 */
50#ifdef CONFIG_SPARC32
51extern int __ashrdi3(int, int);
52extern int __ashldi3(int, int);
53extern int __lshrdi3(int, int);
54extern int __muldi3(int, int);
55extern int __divdi3(int, int);
56
57extern void (*__copy_1page)(void *, const void *);
58extern void (*bzero_1page)(void *);
59
60extern int __strncmp(const char *, const char *, __kernel_size_t);
61
62extern void ___rw_read_enter(void);
63extern void ___rw_read_try(void);
64extern void ___rw_read_exit(void);
65extern void ___rw_write_enter(void);
66extern void ___atomic24_add(void);
67extern void ___atomic24_sub(void);
68
69/* Alias functions whose names begin with "." and export the aliases.
70 * The module references will be fixed up by module_frob_arch_sections.
71 */
72extern int _Div(int, int);
73extern int _Mul(int, int);
74extern int _Rem(int, int);
75extern unsigned _Udiv(unsigned, unsigned);
76extern unsigned _Umul(unsigned, unsigned);
77extern unsigned _Urem(unsigned, unsigned);
78
79/* Networking helper routines. */
80EXPORT_SYMBOL(__csum_partial_copy_sparc_generic);
81
82/* Special internal versions of library functions. */
83EXPORT_SYMBOL(__copy_1page);
84EXPORT_SYMBOL(__memcpy);
85EXPORT_SYMBOL(__memmove);
86EXPORT_SYMBOL(bzero_1page);
87
88/* string functions */
89EXPORT_SYMBOL(__strncmp);
90
91/* Moving data to/from/in userspace. */
92EXPORT_SYMBOL(__copy_user);
93
94/* Used by asm/spinlock.h */
95#ifdef CONFIG_SMP
96EXPORT_SYMBOL(___rw_read_enter);
97EXPORT_SYMBOL(___rw_read_try);
98EXPORT_SYMBOL(___rw_read_exit);
99EXPORT_SYMBOL(___rw_write_enter);
100#endif
101
102/* Atomic operations. */
103EXPORT_SYMBOL(___atomic24_add);
104EXPORT_SYMBOL(___atomic24_sub);
105
106EXPORT_SYMBOL(__ashrdi3);
107EXPORT_SYMBOL(__ashldi3);
108EXPORT_SYMBOL(__lshrdi3);
109EXPORT_SYMBOL(__muldi3);
110EXPORT_SYMBOL(__divdi3);
111
112EXPORT_SYMBOL(_Rem);
113EXPORT_SYMBOL(_Urem);
114EXPORT_SYMBOL(_Mul);
115EXPORT_SYMBOL(_Umul);
116EXPORT_SYMBOL(_Div);
117EXPORT_SYMBOL(_Udiv);
118#endif
119
120/*
121 * sparc64
122 */
123#ifdef CONFIG_SPARC64
124/* Networking helper routines. */
125EXPORT_SYMBOL(csum_partial_copy_nocheck);
126EXPORT_SYMBOL(__csum_partial_copy_from_user);
127EXPORT_SYMBOL(__csum_partial_copy_to_user);
128EXPORT_SYMBOL(ip_fast_csum);
129
130/* Moving data to/from/in userspace. */
131EXPORT_SYMBOL(___copy_to_user);
132EXPORT_SYMBOL(___copy_from_user);
133EXPORT_SYMBOL(___copy_in_user);
134EXPORT_SYMBOL(__clear_user);
135
136/* RW semaphores */
137EXPORT_SYMBOL(__down_read);
138EXPORT_SYMBOL(__down_read_trylock);
139EXPORT_SYMBOL(__down_write);
140EXPORT_SYMBOL(__down_write_trylock);
141EXPORT_SYMBOL(__up_read);
142EXPORT_SYMBOL(__up_write);
143EXPORT_SYMBOL(__downgrade_write);
144
145/* Atomic counter implementation. */
146EXPORT_SYMBOL(atomic_add);
147EXPORT_SYMBOL(atomic_add_ret);
148EXPORT_SYMBOL(atomic_sub);
149EXPORT_SYMBOL(atomic_sub_ret);
150EXPORT_SYMBOL(atomic64_add);
151EXPORT_SYMBOL(atomic64_add_ret);
152EXPORT_SYMBOL(atomic64_sub);
153EXPORT_SYMBOL(atomic64_sub_ret);
154
155/* Atomic bit operations. */
156EXPORT_SYMBOL(test_and_set_bit);
157EXPORT_SYMBOL(test_and_clear_bit);
158EXPORT_SYMBOL(test_and_change_bit);
159EXPORT_SYMBOL(set_bit);
160EXPORT_SYMBOL(clear_bit);
161EXPORT_SYMBOL(change_bit);
162
163/* Special internal versions of library functions. */
164EXPORT_SYMBOL(_clear_page);
165EXPORT_SYMBOL(clear_user_page);
166EXPORT_SYMBOL(copy_user_page);
167
168/* RAID code needs this */
169void VISenter(void);
170EXPORT_SYMBOL(VISenter);
171
172extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
173extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
174 unsigned long *);
175extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *,
176 unsigned long *, unsigned long *);
177extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *,
178 unsigned long *, unsigned long *, unsigned long *);
179EXPORT_SYMBOL(xor_vis_2);
180EXPORT_SYMBOL(xor_vis_3);
181EXPORT_SYMBOL(xor_vis_4);
182EXPORT_SYMBOL(xor_vis_5);
183
184extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *);
185extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *,
186 unsigned long *);
187extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *,
188 unsigned long *, unsigned long *);
189extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *,
190 unsigned long *, unsigned long *, unsigned long *);
191
192EXPORT_SYMBOL(xor_niagara_2);
193EXPORT_SYMBOL(xor_niagara_3);
194EXPORT_SYMBOL(xor_niagara_4);
195EXPORT_SYMBOL(xor_niagara_5);
196#endif
diff --git a/arch/sparc/lib/user_fixup.c b/arch/sparc/lib/user_fixup.c
index 05a361b0a1a4..ac96ae236709 100644
--- a/arch/sparc/lib/user_fixup.c
+++ b/arch/sparc/lib/user_fixup.c
@@ -7,6 +7,8 @@
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/string.h> 8#include <linux/string.h>
9#include <linux/errno.h> 9#include <linux/errno.h>
10#include <linux/module.h>
11
10#include <asm/uaccess.h> 12#include <asm/uaccess.h>
11 13
12/* Calculating the exact fault address when using 14/* Calculating the exact fault address when using
@@ -40,6 +42,7 @@ unsigned long copy_from_user_fixup(void *to, const void __user *from, unsigned l
40 42
41 return size; 43 return size;
42} 44}
45EXPORT_SYMBOL(copy_from_user_fixup);
43 46
44unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned long size) 47unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned long size)
45{ 48{
@@ -47,6 +50,7 @@ unsigned long copy_to_user_fixup(void __user *to, const void *from, unsigned lon
47 50
48 return compute_size((unsigned long) to, size, &offset); 51 return compute_size((unsigned long) to, size, &offset);
49} 52}
53EXPORT_SYMBOL(copy_to_user_fixup);
50 54
51unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned long size) 55unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned long size)
52{ 56{
@@ -64,3 +68,4 @@ unsigned long copy_in_user_fixup(void __user *to, void __user *from, unsigned lo
64 68
65 return size; 69 return size;
66} 70}
71EXPORT_SYMBOL(copy_in_user_fixup);
diff --git a/arch/sparc/mm/generic_32.c b/arch/sparc/mm/generic_32.c
index a289261da9fd..5edcac184eaf 100644
--- a/arch/sparc/mm/generic_32.c
+++ b/arch/sparc/mm/generic_32.c
@@ -95,3 +95,4 @@ int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
95 flush_tlb_range(vma, beg, end); 95 flush_tlb_range(vma, beg, end);
96 return error; 96 return error;
97} 97}
98EXPORT_SYMBOL(io_remap_pfn_range);
diff --git a/arch/sparc/mm/generic_64.c b/arch/sparc/mm/generic_64.c
index f362c2037013..04f2bf4cd571 100644
--- a/arch/sparc/mm/generic_64.c
+++ b/arch/sparc/mm/generic_64.c
@@ -161,3 +161,4 @@ int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
161 flush_tlb_range(vma, beg, end); 161 flush_tlb_range(vma, beg, end);
162 return error; 162 return error;
163} 163}
164EXPORT_SYMBOL(io_remap_pfn_range);
diff --git a/arch/sparc/mm/highmem.c b/arch/sparc/mm/highmem.c
index 01fc6c254292..752d0c9fb544 100644
--- a/arch/sparc/mm/highmem.c
+++ b/arch/sparc/mm/highmem.c
@@ -62,6 +62,7 @@ void *kmap_atomic(struct page *page, enum km_type type)
62 62
63 return (void*) vaddr; 63 return (void*) vaddr;
64} 64}
65EXPORT_SYMBOL(kmap_atomic);
65 66
66void kunmap_atomic(void *kvaddr, enum km_type type) 67void kunmap_atomic(void *kvaddr, enum km_type type)
67{ 68{
@@ -98,6 +99,7 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
98 99
99 pagefault_enable(); 100 pagefault_enable();
100} 101}
102EXPORT_SYMBOL(kunmap_atomic);
101 103
102/* We may be fed a pagetable here by ptep_to_xxx and others. */ 104/* We may be fed a pagetable here by ptep_to_xxx and others. */
103struct page *kmap_atomic_to_page(void *ptr) 105struct page *kmap_atomic_to_page(void *ptr)
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index fec926021f49..cbb282dab5a7 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -38,11 +38,16 @@
38DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 38DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
39 39
40unsigned long *sparc_valid_addr_bitmap; 40unsigned long *sparc_valid_addr_bitmap;
41EXPORT_SYMBOL(sparc_valid_addr_bitmap);
41 42
42unsigned long phys_base; 43unsigned long phys_base;
44EXPORT_SYMBOL(phys_base);
45
43unsigned long pfn_base; 46unsigned long pfn_base;
47EXPORT_SYMBOL(pfn_base);
44 48
45unsigned long page_kernel; 49unsigned long page_kernel;
50EXPORT_SYMBOL(page_kernel);
46 51
47struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1]; 52struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
48unsigned long sparc_unmapped_base; 53unsigned long sparc_unmapped_base;
@@ -522,3 +527,4 @@ void sparc_flush_page_to_ram(struct page *page)
522 if (vaddr) 527 if (vaddr)
523 __flush_page_to_ram(vaddr); 528 __flush_page_to_ram(vaddr);
524} 529}
530EXPORT_SYMBOL(sparc_flush_page_to_ram);
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index c77c7ef5d5d4..00373ce2d8fb 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -146,6 +146,7 @@ static void __init read_obp_memory(const char *property,
146} 146}
147 147
148unsigned long *sparc64_valid_addr_bitmap __read_mostly; 148unsigned long *sparc64_valid_addr_bitmap __read_mostly;
149EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
149 150
150/* Kernel physical address base and size in bytes. */ 151/* Kernel physical address base and size in bytes. */
151unsigned long kern_base __read_mostly; 152unsigned long kern_base __read_mostly;
@@ -369,6 +370,7 @@ void flush_dcache_page(struct page *page)
369out: 370out:
370 put_cpu(); 371 put_cpu();
371} 372}
373EXPORT_SYMBOL(flush_dcache_page);
372 374
373void __kprobes flush_icache_range(unsigned long start, unsigned long end) 375void __kprobes flush_icache_range(unsigned long start, unsigned long end)
374{ 376{
@@ -396,6 +398,7 @@ void __kprobes flush_icache_range(unsigned long start, unsigned long end)
396 } 398 }
397 } 399 }
398} 400}
401EXPORT_SYMBOL(flush_icache_range);
399 402
400void mmu_info(struct seq_file *m) 403void mmu_info(struct seq_file *m)
401{ 404{
@@ -599,6 +602,7 @@ void __flush_dcache_range(unsigned long start, unsigned long end)
599 "i" (ASI_DCACHE_INVALIDATE)); 602 "i" (ASI_DCACHE_INVALIDATE));
600 } 603 }
601} 604}
605EXPORT_SYMBOL(__flush_dcache_range);
602 606
603/* get_new_mmu_context() uses "cache + 1". */ 607/* get_new_mmu_context() uses "cache + 1". */
604DEFINE_SPINLOCK(ctx_alloc_lock); 608DEFINE_SPINLOCK(ctx_alloc_lock);
diff --git a/arch/sparc/prom/init_32.c b/arch/sparc/prom/init_32.c
index 873217c6d823..6193c33ed4d4 100644
--- a/arch/sparc/prom/init_32.c
+++ b/arch/sparc/prom/init_32.c
@@ -8,16 +8,20 @@
8 8
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/module.h>
11 12
12#include <asm/openprom.h> 13#include <asm/openprom.h>
13#include <asm/oplib.h> 14#include <asm/oplib.h>
14 15
15struct linux_romvec *romvec; 16struct linux_romvec *romvec;
17EXPORT_SYMBOL(romvec);
18
16enum prom_major_version prom_vers; 19enum prom_major_version prom_vers;
17unsigned int prom_rev, prom_prev; 20unsigned int prom_rev, prom_prev;
18 21
19/* The root node of the prom device tree. */ 22/* The root node of the prom device tree. */
20int prom_root_node; 23int prom_root_node;
24EXPORT_SYMBOL(prom_root_node);
21 25
22/* Pointer to the device tree operations structure. */ 26/* Pointer to the device tree operations structure. */
23struct linux_nodeops *prom_nodeops; 27struct linux_nodeops *prom_nodeops;
diff --git a/arch/sparc/prom/misc_32.c b/arch/sparc/prom/misc_32.c
index cf6c3f6d36c3..4d61c540bb3d 100644
--- a/arch/sparc/prom/misc_32.c
+++ b/arch/sparc/prom/misc_32.c
@@ -8,6 +8,8 @@
8#include <linux/types.h> 8#include <linux/types.h>
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/sched.h> 10#include <linux/sched.h>
11#include <linux/module.h>
12
11#include <asm/openprom.h> 13#include <asm/openprom.h>
12#include <asm/oplib.h> 14#include <asm/oplib.h>
13#include <asm/auxio.h> 15#include <asm/auxio.h>
@@ -44,6 +46,7 @@ prom_feval(char *fstring)
44 restore_current(); 46 restore_current();
45 spin_unlock_irqrestore(&prom_lock, flags); 47 spin_unlock_irqrestore(&prom_lock, flags);
46} 48}
49EXPORT_SYMBOL(prom_feval);
47 50
48/* Drop into the prom, with the chance to continue with the 'go' 51/* Drop into the prom, with the chance to continue with the 'go'
49 * prom command. 52 * prom command.
diff --git a/arch/sparc/prom/misc_64.c b/arch/sparc/prom/misc_64.c
index 9b0c0760901e..eedffb4fec2d 100644
--- a/arch/sparc/prom/misc_64.c
+++ b/arch/sparc/prom/misc_64.c
@@ -11,6 +11,8 @@
11#include <linux/sched.h> 11#include <linux/sched.h>
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/module.h>
15
14#include <asm/openprom.h> 16#include <asm/openprom.h>
15#include <asm/oplib.h> 17#include <asm/oplib.h>
16#include <asm/system.h> 18#include <asm/system.h>
@@ -54,6 +56,7 @@ void prom_feval(const char *fstring)
54 p1275_cmd("interpret", P1275_ARG(0, P1275_ARG_IN_STRING) | 56 p1275_cmd("interpret", P1275_ARG(0, P1275_ARG_IN_STRING) |
55 P1275_INOUT(1, 1), fstring); 57 P1275_INOUT(1, 1), fstring);
56} 58}
59EXPORT_SYMBOL(prom_feval);
57 60
58#ifdef CONFIG_SMP 61#ifdef CONFIG_SMP
59extern void smp_capture(void); 62extern void smp_capture(void);
diff --git a/arch/sparc/prom/ranges.c b/arch/sparc/prom/ranges.c
index 64579a376419..cd5790853ff6 100644
--- a/arch/sparc/prom/ranges.c
+++ b/arch/sparc/prom/ranges.c
@@ -6,6 +6,8 @@
6 */ 6 */
7 7
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/module.h>
10
9#include <asm/openprom.h> 11#include <asm/openprom.h>
10#include <asm/oplib.h> 12#include <asm/oplib.h>
11#include <asm/types.h> 13#include <asm/types.h>
@@ -62,6 +64,7 @@ prom_apply_obio_ranges(struct linux_prom_registers *regs, int nregs)
62 if(num_obio_ranges) 64 if(num_obio_ranges)
63 prom_adjust_regs(regs, nregs, promlib_obio_ranges, num_obio_ranges); 65 prom_adjust_regs(regs, nregs, promlib_obio_ranges, num_obio_ranges);
64} 66}
67EXPORT_SYMBOL(prom_apply_obio_ranges);
65 68
66void __init prom_ranges_init(void) 69void __init prom_ranges_init(void)
67{ 70{
diff --git a/arch/sparc/prom/tree_32.c b/arch/sparc/prom/tree_32.c
index 6d8187357331..646d244b1fdb 100644
--- a/arch/sparc/prom/tree_32.c
+++ b/arch/sparc/prom/tree_32.c
@@ -5,13 +5,12 @@
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */ 6 */
7 7
8#define PROMLIB_INTERNAL
9
10#include <linux/string.h> 8#include <linux/string.h>
11#include <linux/types.h> 9#include <linux/types.h>
12#include <linux/kernel.h> 10#include <linux/kernel.h>
13#include <linux/sched.h> 11#include <linux/sched.h>
14#include <linux/ctype.h> 12#include <linux/ctype.h>
13#include <linux/module.h>
15 14
16#include <asm/openprom.h> 15#include <asm/openprom.h>
17#include <asm/oplib.h> 16#include <asm/oplib.h>
@@ -50,6 +49,7 @@ int prom_getchild(int node)
50 49
51 return cnode; 50 return cnode;
52} 51}
52EXPORT_SYMBOL(prom_getchild);
53 53
54/* Internal version of prom_getsibling that does not alter return values. */ 54/* Internal version of prom_getsibling that does not alter return values. */
55int __prom_getsibling(int node) 55int __prom_getsibling(int node)
@@ -81,6 +81,7 @@ int prom_getsibling(int node)
81 81
82 return sibnode; 82 return sibnode;
83} 83}
84EXPORT_SYMBOL(prom_getsibling);
84 85
85/* Return the length in bytes of property 'prop' at node 'node'. 86/* Return the length in bytes of property 'prop' at node 'node'.
86 * Return -1 on error. 87 * Return -1 on error.
@@ -99,6 +100,7 @@ int prom_getproplen(int node, const char *prop)
99 spin_unlock_irqrestore(&prom_lock, flags); 100 spin_unlock_irqrestore(&prom_lock, flags);
100 return ret; 101 return ret;
101} 102}
103EXPORT_SYMBOL(prom_getproplen);
102 104
103/* Acquire a property 'prop' at node 'node' and place it in 105/* Acquire a property 'prop' at node 'node' and place it in
104 * 'buffer' which has a size of 'bufsize'. If the acquisition 106 * 'buffer' which has a size of 'bufsize'. If the acquisition
@@ -119,6 +121,7 @@ int prom_getproperty(int node, const char *prop, char *buffer, int bufsize)
119 spin_unlock_irqrestore(&prom_lock, flags); 121 spin_unlock_irqrestore(&prom_lock, flags);
120 return ret; 122 return ret;
121} 123}
124EXPORT_SYMBOL(prom_getproperty);
122 125
123/* Acquire an integer property and return its value. Returns -1 126/* Acquire an integer property and return its value. Returns -1
124 * on failure. 127 * on failure.
@@ -132,6 +135,7 @@ int prom_getint(int node, char *prop)
132 135
133 return -1; 136 return -1;
134} 137}
138EXPORT_SYMBOL(prom_getint);
135 139
136/* Acquire an integer property, upon error return the passed default 140/* Acquire an integer property, upon error return the passed default
137 * integer. 141 * integer.
@@ -145,6 +149,7 @@ int prom_getintdefault(int node, char *property, int deflt)
145 149
146 return retval; 150 return retval;
147} 151}
152EXPORT_SYMBOL(prom_getintdefault);
148 153
149/* Acquire a boolean property, 1=TRUE 0=FALSE. */ 154/* Acquire a boolean property, 1=TRUE 0=FALSE. */
150int prom_getbool(int node, char *prop) 155int prom_getbool(int node, char *prop)
@@ -155,6 +160,7 @@ int prom_getbool(int node, char *prop)
155 if(retval == -1) return 0; 160 if(retval == -1) return 0;
156 return 1; 161 return 1;
157} 162}
163EXPORT_SYMBOL(prom_getbool);
158 164
159/* Acquire a property whose value is a string, returns a null 165/* Acquire a property whose value is a string, returns a null
160 * string on error. The char pointer is the user supplied string 166 * string on error. The char pointer is the user supplied string
@@ -169,6 +175,7 @@ void prom_getstring(int node, char *prop, char *user_buf, int ubuf_size)
169 user_buf[0] = 0; 175 user_buf[0] = 0;
170 return; 176 return;
171} 177}
178EXPORT_SYMBOL(prom_getstring);
172 179
173 180
174/* Does the device at node 'node' have name 'name'? 181/* Does the device at node 'node' have name 'name'?
@@ -204,6 +211,7 @@ int prom_searchsiblings(int node_start, char *nodename)
204 211
205 return 0; 212 return 0;
206} 213}
214EXPORT_SYMBOL(prom_searchsiblings);
207 215
208/* Interal version of nextprop that does not alter return values. */ 216/* Interal version of nextprop that does not alter return values. */
209char * __prom_nextprop(int node, char * oprop) 217char * __prom_nextprop(int node, char * oprop)
@@ -228,6 +236,7 @@ char * prom_firstprop(int node, char *bufer)
228 236
229 return __prom_nextprop(node, ""); 237 return __prom_nextprop(node, "");
230} 238}
239EXPORT_SYMBOL(prom_firstprop);
231 240
232/* Return the property type string after property type 'oprop' 241/* Return the property type string after property type 'oprop'
233 * at node 'node' . Returns empty string if no more 242 * at node 'node' . Returns empty string if no more
@@ -240,6 +249,7 @@ char * prom_nextprop(int node, char *oprop, char *buffer)
240 249
241 return __prom_nextprop(node, oprop); 250 return __prom_nextprop(node, oprop);
242} 251}
252EXPORT_SYMBOL(prom_nextprop);
243 253
244int prom_finddevice(char *name) 254int prom_finddevice(char *name)
245{ 255{
@@ -287,6 +297,7 @@ int prom_finddevice(char *name)
287 } 297 }
288 return node; 298 return node;
289} 299}
300EXPORT_SYMBOL(prom_finddevice);
290 301
291int prom_node_has_property(int node, char *prop) 302int prom_node_has_property(int node, char *prop)
292{ 303{
@@ -299,6 +310,7 @@ int prom_node_has_property(int node, char *prop)
299 } while (*current_property); 310 } while (*current_property);
300 return 0; 311 return 0;
301} 312}
313EXPORT_SYMBOL(prom_node_has_property);
302 314
303/* Set property 'pname' at node 'node' to value 'value' which has a length 315/* Set property 'pname' at node 'node' to value 'value' which has a length
304 * of 'size' bytes. Return the number of bytes the prom accepted. 316 * of 'size' bytes. Return the number of bytes the prom accepted.
@@ -316,6 +328,7 @@ int prom_setprop(int node, const char *pname, char *value, int size)
316 spin_unlock_irqrestore(&prom_lock, flags); 328 spin_unlock_irqrestore(&prom_lock, flags);
317 return ret; 329 return ret;
318} 330}
331EXPORT_SYMBOL(prom_setprop);
319 332
320int prom_inst2pkg(int inst) 333int prom_inst2pkg(int inst)
321{ 334{
diff --git a/arch/sparc/prom/tree_64.c b/arch/sparc/prom/tree_64.c
index 281aea44790b..8ea73ddc61dc 100644
--- a/arch/sparc/prom/tree_64.c
+++ b/arch/sparc/prom/tree_64.c
@@ -10,6 +10,7 @@
10#include <linux/types.h> 10#include <linux/types.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/sched.h> 12#include <linux/sched.h>
13#include <linux/module.h>
13 14
14#include <asm/openprom.h> 15#include <asm/openprom.h>
15#include <asm/oplib.h> 16#include <asm/oplib.h>
@@ -32,6 +33,7 @@ inline int prom_getchild(int node)
32 if(cnode == -1) return 0; 33 if(cnode == -1) return 0;
33 return (int)cnode; 34 return (int)cnode;
34} 35}
36EXPORT_SYMBOL(prom_getchild);
35 37
36inline int prom_getparent(int node) 38inline int prom_getparent(int node)
37{ 39{
@@ -63,6 +65,7 @@ inline int prom_getsibling(int node)
63 65
64 return sibnode; 66 return sibnode;
65} 67}
68EXPORT_SYMBOL(prom_getsibling);
66 69
67/* Return the length in bytes of property 'prop' at node 'node'. 70/* Return the length in bytes of property 'prop' at node 'node'.
68 * Return -1 on error. 71 * Return -1 on error.
@@ -75,6 +78,7 @@ inline int prom_getproplen(int node, const char *prop)
75 P1275_INOUT(2, 1), 78 P1275_INOUT(2, 1),
76 node, prop); 79 node, prop);
77} 80}
81EXPORT_SYMBOL(prom_getproplen);
78 82
79/* Acquire a property 'prop' at node 'node' and place it in 83/* Acquire a property 'prop' at node 'node' and place it in
80 * 'buffer' which has a size of 'bufsize'. If the acquisition 84 * 'buffer' which has a size of 'bufsize'. If the acquisition
@@ -97,6 +101,7 @@ inline int prom_getproperty(int node, const char *prop,
97 node, prop, buffer, P1275_SIZE(plen)); 101 node, prop, buffer, P1275_SIZE(plen));
98 } 102 }
99} 103}
104EXPORT_SYMBOL(prom_getproperty);
100 105
101/* Acquire an integer property and return its value. Returns -1 106/* Acquire an integer property and return its value. Returns -1
102 * on failure. 107 * on failure.
@@ -110,6 +115,7 @@ inline int prom_getint(int node, const char *prop)
110 115
111 return -1; 116 return -1;
112} 117}
118EXPORT_SYMBOL(prom_getint);
113 119
114/* Acquire an integer property, upon error return the passed default 120/* Acquire an integer property, upon error return the passed default
115 * integer. 121 * integer.
@@ -124,6 +130,7 @@ int prom_getintdefault(int node, const char *property, int deflt)
124 130
125 return retval; 131 return retval;
126} 132}
133EXPORT_SYMBOL(prom_getintdefault);
127 134
128/* Acquire a boolean property, 1=TRUE 0=FALSE. */ 135/* Acquire a boolean property, 1=TRUE 0=FALSE. */
129int prom_getbool(int node, const char *prop) 136int prom_getbool(int node, const char *prop)
@@ -134,6 +141,7 @@ int prom_getbool(int node, const char *prop)
134 if(retval == -1) return 0; 141 if(retval == -1) return 0;
135 return 1; 142 return 1;
136} 143}
144EXPORT_SYMBOL(prom_getbool);
137 145
138/* Acquire a property whose value is a string, returns a null 146/* Acquire a property whose value is a string, returns a null
139 * string on error. The char pointer is the user supplied string 147 * string on error. The char pointer is the user supplied string
@@ -148,7 +156,7 @@ void prom_getstring(int node, const char *prop, char *user_buf, int ubuf_size)
148 user_buf[0] = 0; 156 user_buf[0] = 0;
149 return; 157 return;
150} 158}
151 159EXPORT_SYMBOL(prom_getstring);
152 160
153/* Does the device at node 'node' have name 'name'? 161/* Does the device at node 'node' have name 'name'?
154 * YES = 1 NO = 0 162 * YES = 1 NO = 0
@@ -181,6 +189,7 @@ int prom_searchsiblings(int node_start, const char *nodename)
181 189
182 return 0; 190 return 0;
183} 191}
192EXPORT_SYMBOL(prom_searchsiblings);
184 193
185/* Return the first property type for node 'node'. 194/* Return the first property type for node 'node'.
186 * buffer should be at least 32B in length 195 * buffer should be at least 32B in length
@@ -194,6 +203,7 @@ inline char *prom_firstprop(int node, char *buffer)
194 node, (char *) 0x0, buffer); 203 node, (char *) 0x0, buffer);
195 return buffer; 204 return buffer;
196} 205}
206EXPORT_SYMBOL(prom_firstprop);
197 207
198/* Return the property type string after property type 'oprop' 208/* Return the property type string after property type 'oprop'
199 * at node 'node' . Returns NULL string if no more 209 * at node 'node' . Returns NULL string if no more
@@ -217,6 +227,7 @@ inline char *prom_nextprop(int node, const char *oprop, char *buffer)
217 node, oprop, buffer); 227 node, oprop, buffer);
218 return buffer; 228 return buffer;
219} 229}
230EXPORT_SYMBOL(prom_nextprop);
220 231
221int 232int
222prom_finddevice(const char *name) 233prom_finddevice(const char *name)
@@ -228,6 +239,7 @@ prom_finddevice(const char *name)
228 P1275_INOUT(1, 1), 239 P1275_INOUT(1, 1),
229 name); 240 name);
230} 241}
242EXPORT_SYMBOL(prom_finddevice);
231 243
232int prom_node_has_property(int node, const char *prop) 244int prom_node_has_property(int node, const char *prop)
233{ 245{
@@ -241,7 +253,8 @@ int prom_node_has_property(int node, const char *prop)
241 } while (*buf); 253 } while (*buf);
242 return 0; 254 return 0;
243} 255}
244 256EXPORT_SYMBOL(prom_node_has_property);
257
245/* Set property 'pname' at node 'node' to value 'value' which has a length 258/* Set property 'pname' at node 'node' to value 'value' which has a length
246 * of 'size' bytes. Return the number of bytes the prom accepted. 259 * of 'size' bytes. Return the number of bytes the prom accepted.
247 */ 260 */
@@ -264,6 +277,7 @@ prom_setprop(int node, const char *pname, char *value, int size)
264 P1275_INOUT(4, 1), 277 P1275_INOUT(4, 1),
265 node, pname, value, P1275_SIZE(size)); 278 node, pname, value, P1275_SIZE(size));
266} 279}
280EXPORT_SYMBOL(prom_setprop);
267 281
268inline int prom_inst2pkg(int inst) 282inline int prom_inst2pkg(int inst)
269{ 283{
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 862adb9bf0d4..73f7fe8fd4d1 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -27,6 +27,7 @@ config X86
27 select HAVE_IOREMAP_PROT 27 select HAVE_IOREMAP_PROT
28 select HAVE_KPROBES 28 select HAVE_KPROBES
29 select ARCH_WANT_OPTIONAL_GPIOLIB 29 select ARCH_WANT_OPTIONAL_GPIOLIB
30 select ARCH_WANT_FRAME_POINTERS
30 select HAVE_KRETPROBES 31 select HAVE_KRETPROBES
31 select HAVE_FTRACE_MCOUNT_RECORD 32 select HAVE_FTRACE_MCOUNT_RECORD
32 select HAVE_DYNAMIC_FTRACE 33 select HAVE_DYNAMIC_FTRACE
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 9fa9dcdf344b..e02a359d2aa5 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -300,7 +300,7 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
300 return oldbit; 300 return oldbit;
301} 301}
302 302
303static inline int constant_test_bit(int nr, const volatile unsigned long *addr) 303static inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
304{ 304{
305 return ((1UL << (nr % BITS_PER_LONG)) & 305 return ((1UL << (nr % BITS_PER_LONG)) &
306 (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0; 306 (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
diff --git a/arch/x86/include/asm/es7000/apic.h b/arch/x86/include/asm/es7000/apic.h
index bc53d5ef1386..c58b9cc74465 100644
--- a/arch/x86/include/asm/es7000/apic.h
+++ b/arch/x86/include/asm/es7000/apic.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_ES7000_APIC_H 1#ifndef __ASM_ES7000_APIC_H
2#define __ASM_ES7000_APIC_H 2#define __ASM_ES7000_APIC_H
3 3
4#include <linux/gfp.h>
5
4#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu) 6#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
5#define esr_disable (1) 7#define esr_disable (1)
6 8
diff --git a/arch/x86/include/asm/es7000/mpparse.h b/arch/x86/include/asm/es7000/mpparse.h
index ed5a3caae141..c1629b090ec2 100644
--- a/arch/x86/include/asm/es7000/mpparse.h
+++ b/arch/x86/include/asm/es7000/mpparse.h
@@ -10,8 +10,7 @@ extern void setup_unisys(void);
10 10
11#ifndef CONFIG_X86_GENERICARCH 11#ifndef CONFIG_X86_GENERICARCH
12extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id); 12extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id);
13extern int mps_oem_check(struct mp_config_table *mpc, char *oem, 13extern int mps_oem_check(struct mpc_table *mpc, char *oem, char *productid);
14 char *productid);
15#endif 14#endif
16 15
17#ifdef CONFIG_ACPI 16#ifdef CONFIG_ACPI
diff --git a/arch/x86/include/asm/genapic_32.h b/arch/x86/include/asm/genapic_32.h
index 746f37a7963a..2c05b737ee22 100644
--- a/arch/x86/include/asm/genapic_32.h
+++ b/arch/x86/include/asm/genapic_32.h
@@ -15,9 +15,9 @@
15 * Copyright 2003 Andi Kleen, SuSE Labs. 15 * Copyright 2003 Andi Kleen, SuSE Labs.
16 */ 16 */
17 17
18struct mpc_config_bus; 18struct mpc_bus;
19struct mp_config_table; 19struct mpc_table;
20struct mpc_config_processor; 20struct mpc_cpu;
21 21
22struct genapic { 22struct genapic {
23 char *name; 23 char *name;
@@ -51,7 +51,7 @@ struct genapic {
51 /* When one of the next two hooks returns 1 the genapic 51 /* When one of the next two hooks returns 1 the genapic
52 is switched to this. Essentially they are additional probe 52 is switched to this. Essentially they are additional probe
53 functions. */ 53 functions. */
54 int (*mps_oem_check)(struct mp_config_table *mpc, char *oem, 54 int (*mps_oem_check)(struct mpc_table *mpc, char *oem,
55 char *productid); 55 char *productid);
56 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 56 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
57 57
diff --git a/arch/x86/include/asm/mach-default/mach_mpparse.h b/arch/x86/include/asm/mach-default/mach_mpparse.h
index 8c1ea21238a7..c70a263d68cd 100644
--- a/arch/x86/include/asm/mach-default/mach_mpparse.h
+++ b/arch/x86/include/asm/mach-default/mach_mpparse.h
@@ -1,8 +1,8 @@
1#ifndef _ASM_X86_MACH_DEFAULT_MACH_MPPARSE_H 1#ifndef _ASM_X86_MACH_DEFAULT_MACH_MPPARSE_H
2#define _ASM_X86_MACH_DEFAULT_MACH_MPPARSE_H 2#define _ASM_X86_MACH_DEFAULT_MACH_MPPARSE_H
3 3
4static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, 4static inline int
5 char *productid) 5mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
6{ 6{
7 return 0; 7 return 0;
8} 8}
diff --git a/arch/x86/include/asm/mach-default/mach_wakecpu.h b/arch/x86/include/asm/mach-default/mach_wakecpu.h
index ceb013660146..89897a6a65b9 100644
--- a/arch/x86/include/asm/mach-default/mach_wakecpu.h
+++ b/arch/x86/include/asm/mach-default/mach_wakecpu.h
@@ -24,7 +24,13 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low)
24{ 24{
25} 25}
26 26
27#ifdef CONFIG_SMP
27extern void __inquire_remote_apic(int apicid); 28extern void __inquire_remote_apic(int apicid);
29#else /* CONFIG_SMP */
30static inline void __inquire_remote_apic(int apicid)
31{
32}
33#endif /* CONFIG_SMP */
28 34
29static inline void inquire_remote_apic(int apicid) 35static inline void inquire_remote_apic(int apicid)
30{ 36{
diff --git a/arch/x86/include/asm/mach-generic/mach_mpparse.h b/arch/x86/include/asm/mach-generic/mach_mpparse.h
index 048f1d468535..9444ab8dca94 100644
--- a/arch/x86/include/asm/mach-generic/mach_mpparse.h
+++ b/arch/x86/include/asm/mach-generic/mach_mpparse.h
@@ -2,9 +2,8 @@
2#define _ASM_X86_MACH_GENERIC_MACH_MPPARSE_H 2#define _ASM_X86_MACH_GENERIC_MACH_MPPARSE_H
3 3
4 4
5extern int mps_oem_check(struct mp_config_table *mpc, char *oem, 5extern int mps_oem_check(struct mpc_table *, char *, char *);
6 char *productid);
7 6
8extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id); 7extern int acpi_madt_oem_check(char *, char *);
9 8
10#endif /* _ASM_X86_MACH_GENERIC_MACH_MPPARSE_H */ 9#endif /* _ASM_X86_MACH_GENERIC_MACH_MPPARSE_H */
diff --git a/arch/x86/include/asm/mach-generic/mach_mpspec.h b/arch/x86/include/asm/mach-generic/mach_mpspec.h
index bbab5ccfd4fe..3bc407226578 100644
--- a/arch/x86/include/asm/mach-generic/mach_mpspec.h
+++ b/arch/x86/include/asm/mach-generic/mach_mpspec.h
@@ -7,6 +7,6 @@
7/* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. */ 7/* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. */
8#define MAX_MP_BUSSES 260 8#define MAX_MP_BUSSES 260
9 9
10extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem, 10extern void numaq_mps_oem_check(struct mpc_table *, char *, char *);
11 char *productid); 11
12#endif /* _ASM_X86_MACH_GENERIC_MACH_MPSPEC_H */ 12#endif /* _ASM_X86_MACH_GENERIC_MACH_MPSPEC_H */
diff --git a/arch/x86/include/asm/mpspec_def.h b/arch/x86/include/asm/mpspec_def.h
index e3ace7d1d35d..59568bc4767f 100644
--- a/arch/x86/include/asm/mpspec_def.h
+++ b/arch/x86/include/asm/mpspec_def.h
@@ -39,17 +39,17 @@ struct intel_mp_floating {
39 39
40#define MPC_SIGNATURE "PCMP" 40#define MPC_SIGNATURE "PCMP"
41 41
42struct mp_config_table { 42struct mpc_table {
43 char mpc_signature[4]; 43 char signature[4];
44 unsigned short mpc_length; /* Size of table */ 44 unsigned short length; /* Size of table */
45 char mpc_spec; /* 0x01 */ 45 char spec; /* 0x01 */
46 char mpc_checksum; 46 char checksum;
47 char mpc_oem[8]; 47 char oem[8];
48 char mpc_productid[12]; 48 char productid[12];
49 unsigned int mpc_oemptr; /* 0 if not present */ 49 unsigned int oemptr; /* 0 if not present */
50 unsigned short mpc_oemsize; /* 0 if not present */ 50 unsigned short oemsize; /* 0 if not present */
51 unsigned short mpc_oemcount; 51 unsigned short oemcount;
52 unsigned int mpc_lapic; /* APIC address */ 52 unsigned int lapic; /* APIC address */
53 unsigned int reserved; 53 unsigned int reserved;
54}; 54};
55 55
@@ -70,20 +70,20 @@ struct mp_config_table {
70#define CPU_MODEL_MASK 0x00F0 70#define CPU_MODEL_MASK 0x00F0
71#define CPU_FAMILY_MASK 0x0F00 71#define CPU_FAMILY_MASK 0x0F00
72 72
73struct mpc_config_processor { 73struct mpc_cpu {
74 unsigned char mpc_type; 74 unsigned char type;
75 unsigned char mpc_apicid; /* Local APIC number */ 75 unsigned char apicid; /* Local APIC number */
76 unsigned char mpc_apicver; /* Its versions */ 76 unsigned char apicver; /* Its versions */
77 unsigned char mpc_cpuflag; 77 unsigned char cpuflag;
78 unsigned int mpc_cpufeature; 78 unsigned int cpufeature;
79 unsigned int mpc_featureflag; /* CPUID feature value */ 79 unsigned int featureflag; /* CPUID feature value */
80 unsigned int mpc_reserved[2]; 80 unsigned int reserved[2];
81}; 81};
82 82
83struct mpc_config_bus { 83struct mpc_bus {
84 unsigned char mpc_type; 84 unsigned char type;
85 unsigned char mpc_busid; 85 unsigned char busid;
86 unsigned char mpc_bustype[6]; 86 unsigned char bustype[6];
87}; 87};
88 88
89/* List of Bus Type string values, Intel MP Spec. */ 89/* List of Bus Type string values, Intel MP Spec. */
@@ -108,22 +108,22 @@ struct mpc_config_bus {
108 108
109#define MPC_APIC_USABLE 0x01 109#define MPC_APIC_USABLE 0x01
110 110
111struct mpc_config_ioapic { 111struct mpc_ioapic {
112 unsigned char mpc_type; 112 unsigned char type;
113 unsigned char mpc_apicid; 113 unsigned char apicid;
114 unsigned char mpc_apicver; 114 unsigned char apicver;
115 unsigned char mpc_flags; 115 unsigned char flags;
116 unsigned int mpc_apicaddr; 116 unsigned int apicaddr;
117}; 117};
118 118
119struct mpc_config_intsrc { 119struct mpc_intsrc {
120 unsigned char mpc_type; 120 unsigned char type;
121 unsigned char mpc_irqtype; 121 unsigned char irqtype;
122 unsigned short mpc_irqflag; 122 unsigned short irqflag;
123 unsigned char mpc_srcbus; 123 unsigned char srcbus;
124 unsigned char mpc_srcbusirq; 124 unsigned char srcbusirq;
125 unsigned char mpc_dstapic; 125 unsigned char dstapic;
126 unsigned char mpc_dstirq; 126 unsigned char dstirq;
127}; 127};
128 128
129enum mp_irq_source_types { 129enum mp_irq_source_types {
@@ -139,24 +139,24 @@ enum mp_irq_source_types {
139 139
140#define MP_APIC_ALL 0xFF 140#define MP_APIC_ALL 0xFF
141 141
142struct mpc_config_lintsrc { 142struct mpc_lintsrc {
143 unsigned char mpc_type; 143 unsigned char type;
144 unsigned char mpc_irqtype; 144 unsigned char irqtype;
145 unsigned short mpc_irqflag; 145 unsigned short irqflag;
146 unsigned char mpc_srcbusid; 146 unsigned char srcbusid;
147 unsigned char mpc_srcbusirq; 147 unsigned char srcbusirq;
148 unsigned char mpc_destapic; 148 unsigned char destapic;
149 unsigned char mpc_destapiclint; 149 unsigned char destapiclint;
150}; 150};
151 151
152#define MPC_OEM_SIGNATURE "_OEM" 152#define MPC_OEM_SIGNATURE "_OEM"
153 153
154struct mp_config_oemtable { 154struct mpc_oemtable {
155 char oem_signature[4]; 155 char signature[4];
156 unsigned short oem_length; /* Size of table */ 156 unsigned short length; /* Size of table */
157 char oem_rev; /* 0x01 */ 157 char rev; /* 0x01 */
158 char oem_checksum; 158 char checksum;
159 char mpc_oem[8]; 159 char mpc[8];
160}; 160};
161 161
162/* 162/*
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index cb988aab716d..14080d22edb3 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -58,15 +58,15 @@ struct mtrr_gentry {
58#endif /* !__i386__ */ 58#endif /* !__i386__ */
59 59
60struct mtrr_var_range { 60struct mtrr_var_range {
61 u32 base_lo; 61 __u32 base_lo;
62 u32 base_hi; 62 __u32 base_hi;
63 u32 mask_lo; 63 __u32 mask_lo;
64 u32 mask_hi; 64 __u32 mask_hi;
65}; 65};
66 66
67/* In the Intel processor's MTRR interface, the MTRR type is always held in 67/* In the Intel processor's MTRR interface, the MTRR type is always held in
68 an 8 bit field: */ 68 an 8 bit field: */
69typedef u8 mtrr_type; 69typedef __u8 mtrr_type;
70 70
71#define MTRR_NUM_FIXED_RANGES 88 71#define MTRR_NUM_FIXED_RANGES 88
72#define MTRR_MAX_VAR_RANGES 256 72#define MTRR_MAX_VAR_RANGES 256
diff --git a/arch/x86/include/asm/numaq/mpparse.h b/arch/x86/include/asm/numaq/mpparse.h
index 252292e077b6..a2eeefcd1cc7 100644
--- a/arch/x86/include/asm/numaq/mpparse.h
+++ b/arch/x86/include/asm/numaq/mpparse.h
@@ -1,7 +1,6 @@
1#ifndef __ASM_NUMAQ_MPPARSE_H 1#ifndef __ASM_NUMAQ_MPPARSE_H
2#define __ASM_NUMAQ_MPPARSE_H 2#define __ASM_NUMAQ_MPPARSE_H
3 3
4extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem, 4extern void numaq_mps_oem_check(struct mpc_table *, char *, char *);
5 char *productid);
6 5
7#endif /* __ASM_NUMAQ_MPPARSE_H */ 6#endif /* __ASM_NUMAQ_MPPARSE_H */
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index 4fcd53fd5f43..ebe858cdc8a3 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -25,9 +25,9 @@ extern int wakeup_secondary_cpu_via_init(int apicid, unsigned long start_eip);
25/* 25/*
26 * Any setup quirks to be performed? 26 * Any setup quirks to be performed?
27 */ 27 */
28struct mpc_config_processor; 28struct mpc_cpu;
29struct mpc_config_bus; 29struct mpc_bus;
30struct mp_config_oemtable; 30struct mpc_oemtable;
31struct x86_quirks { 31struct x86_quirks {
32 int (*arch_pre_time_init)(void); 32 int (*arch_pre_time_init)(void);
33 int (*arch_time_init)(void); 33 int (*arch_time_init)(void);
@@ -39,10 +39,10 @@ struct x86_quirks {
39 int (*mach_find_smp_config)(unsigned int reserve); 39 int (*mach_find_smp_config)(unsigned int reserve);
40 40
41 int *mpc_record; 41 int *mpc_record;
42 int (*mpc_apic_id)(struct mpc_config_processor *m); 42 int (*mpc_apic_id)(struct mpc_cpu *m);
43 void (*mpc_oem_bus_info)(struct mpc_config_bus *m, char *name); 43 void (*mpc_oem_bus_info)(struct mpc_bus *m, char *name);
44 void (*mpc_oem_pci_bus)(struct mpc_config_bus *m); 44 void (*mpc_oem_pci_bus)(struct mpc_bus *m);
45 void (*smp_read_mpc_oem)(struct mp_config_oemtable *oemtable, 45 void (*smp_read_mpc_oem)(struct mpc_oemtable *oemtable,
46 unsigned short oemsize); 46 unsigned short oemsize);
47 int (*setup_ioapic_ids)(void); 47 int (*setup_ioapic_ids)(void);
48 int (*update_genapic)(void); 48 int (*update_genapic)(void);
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index 830b9fcb6427..19953df61c52 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -18,9 +18,26 @@
18#include <asm/pda.h> 18#include <asm/pda.h>
19#include <asm/thread_info.h> 19#include <asm/thread_info.h>
20 20
21#ifdef CONFIG_X86_64
22
23extern cpumask_var_t cpu_callin_mask;
24extern cpumask_var_t cpu_callout_mask;
25extern cpumask_var_t cpu_initialized_mask;
26extern cpumask_var_t cpu_sibling_setup_mask;
27
28#else /* CONFIG_X86_32 */
29
30extern cpumask_t cpu_callin_map;
21extern cpumask_t cpu_callout_map; 31extern cpumask_t cpu_callout_map;
22extern cpumask_t cpu_initialized; 32extern cpumask_t cpu_initialized;
23extern cpumask_t cpu_callin_map; 33extern cpumask_t cpu_sibling_setup_map;
34
35#define cpu_callin_mask ((struct cpumask *)&cpu_callin_map)
36#define cpu_callout_mask ((struct cpumask *)&cpu_callout_map)
37#define cpu_initialized_mask ((struct cpumask *)&cpu_initialized)
38#define cpu_sibling_setup_mask ((struct cpumask *)&cpu_sibling_setup_map)
39
40#endif /* CONFIG_X86_32 */
24 41
25extern void (*mtrr_hook)(void); 42extern void (*mtrr_hook)(void);
26extern void zap_low_mappings(void); 43extern void zap_low_mappings(void);
@@ -29,7 +46,6 @@ extern int __cpuinit get_local_pda(int cpu);
29 46
30extern int smp_num_siblings; 47extern int smp_num_siblings;
31extern unsigned int num_processors; 48extern unsigned int num_processors;
32extern cpumask_t cpu_initialized;
33 49
34DECLARE_PER_CPU(cpumask_t, cpu_sibling_map); 50DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
35DECLARE_PER_CPU(cpumask_t, cpu_core_map); 51DECLARE_PER_CPU(cpumask_t, cpu_core_map);
@@ -38,6 +54,16 @@ DECLARE_PER_CPU(u16, cpu_llc_id);
38DECLARE_PER_CPU(int, cpu_number); 54DECLARE_PER_CPU(int, cpu_number);
39#endif 55#endif
40 56
57static inline struct cpumask *cpu_sibling_mask(int cpu)
58{
59 return &per_cpu(cpu_sibling_map, cpu);
60}
61
62static inline struct cpumask *cpu_core_mask(int cpu)
63{
64 return &per_cpu(cpu_core_map, cpu);
65}
66
41DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid); 67DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid);
42DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); 68DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
43 69
@@ -149,7 +175,7 @@ void smp_store_cpu_info(int id);
149/* We don't mark CPUs online until __cpu_up(), so we need another measure */ 175/* We don't mark CPUs online until __cpu_up(), so we need another measure */
150static inline int num_booting_cpus(void) 176static inline int num_booting_cpus(void)
151{ 177{
152 return cpus_weight(cpu_callout_map); 178 return cpumask_weight(cpu_callout_mask);
153} 179}
154#else 180#else
155static inline void prefill_possible_map(void) 181static inline void prefill_possible_map(void)
diff --git a/arch/x86/include/asm/summit/apic.h b/arch/x86/include/asm/summit/apic.h
index 4bb5fb34f030..93d2c8667cfe 100644
--- a/arch/x86/include/asm/summit/apic.h
+++ b/arch/x86/include/asm/summit/apic.h
@@ -2,6 +2,7 @@
2#define __ASM_SUMMIT_APIC_H 2#define __ASM_SUMMIT_APIC_H
3 3
4#include <asm/smp.h> 4#include <asm/smp.h>
5#include <linux/gfp.h>
5 6
6#define esr_disable (1) 7#define esr_disable (1)
7#define NO_BALANCE_IRQ (0) 8#define NO_BALANCE_IRQ (0)
diff --git a/arch/x86/include/asm/summit/mpparse.h b/arch/x86/include/asm/summit/mpparse.h
index 013ce6fab2d5..380e86c02363 100644
--- a/arch/x86/include/asm/summit/mpparse.h
+++ b/arch/x86/include/asm/summit/mpparse.h
@@ -11,7 +11,7 @@ extern void setup_summit(void);
11#define setup_summit() {} 11#define setup_summit() {}
12#endif 12#endif
13 13
14static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, 14static inline int mps_oem_check(struct mpc_table *mpc, char *oem,
15 char *productid) 15 char *productid)
16{ 16{
17 if (!strncmp(oem, "IBM ENSW", 8) && 17 if (!strncmp(oem, "IBM ENSW", 8) &&
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 29dc0c89d4af..d37593c2f438 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -47,7 +47,7 @@
47#endif 47#endif
48 48
49static int __initdata acpi_force = 0; 49static int __initdata acpi_force = 0;
50 50u32 acpi_rsdt_forced;
51#ifdef CONFIG_ACPI 51#ifdef CONFIG_ACPI
52int acpi_disabled = 0; 52int acpi_disabled = 0;
53#else 53#else
@@ -1374,6 +1374,17 @@ static void __init acpi_process_madt(void)
1374 "Invalid BIOS MADT, disabling ACPI\n"); 1374 "Invalid BIOS MADT, disabling ACPI\n");
1375 disable_acpi(); 1375 disable_acpi();
1376 } 1376 }
1377 } else {
1378 /*
1379 * ACPI found no MADT, and so ACPI wants UP PIC mode.
1380 * In the event an MPS table was found, forget it.
1381 * Boot with "acpi=off" to use MPS on such a system.
1382 */
1383 if (smp_found_config) {
1384 printk(KERN_WARNING PREFIX
1385 "No APIC-table, disabling MPS\n");
1386 smp_found_config = 0;
1387 }
1377 } 1388 }
1378 1389
1379 /* 1390 /*
@@ -1809,6 +1820,10 @@ static int __init parse_acpi(char *arg)
1809 disable_acpi(); 1820 disable_acpi();
1810 acpi_ht = 1; 1821 acpi_ht = 1;
1811 } 1822 }
1823 /* acpi=rsdt use RSDT instead of XSDT */
1824 else if (strcmp(arg, "rsdt") == 0) {
1825 acpi_rsdt_forced = 1;
1826 }
1812 /* "acpi=noirq" disables ACPI interrupt routing */ 1827 /* "acpi=noirq" disables ACPI interrupt routing */
1813 else if (strcmp(arg, "noirq") == 0) { 1828 else if (strcmp(arg, "noirq") == 0) {
1814 acpi_noirq_set(); 1829 acpi_noirq_set();
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index c2502eb9aa83..bbbe4bbb6f34 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -56,6 +56,7 @@ static struct cstate_entry *cpu_cstate_entry; /* per CPU ptr */
56static short mwait_supported[ACPI_PROCESSOR_MAX_POWER]; 56static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
57 57
58#define MWAIT_SUBSTATE_MASK (0xf) 58#define MWAIT_SUBSTATE_MASK (0xf)
59#define MWAIT_CSTATE_MASK (0xf)
59#define MWAIT_SUBSTATE_SIZE (4) 60#define MWAIT_SUBSTATE_SIZE (4)
60 61
61#define CPUID_MWAIT_LEAF (5) 62#define CPUID_MWAIT_LEAF (5)
@@ -66,39 +67,20 @@ static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
66 67
67#define NATIVE_CSTATE_BEYOND_HALT (2) 68#define NATIVE_CSTATE_BEYOND_HALT (2)
68 69
69int acpi_processor_ffh_cstate_probe(unsigned int cpu, 70static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
70 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
71{ 71{
72 struct cstate_entry *percpu_entry; 72 struct acpi_processor_cx *cx = _cx;
73 struct cpuinfo_x86 *c = &cpu_data(cpu); 73 long retval;
74
75 cpumask_t saved_mask;
76 int retval;
77 unsigned int eax, ebx, ecx, edx; 74 unsigned int eax, ebx, ecx, edx;
78 unsigned int edx_part; 75 unsigned int edx_part;
79 unsigned int cstate_type; /* C-state type and not ACPI C-state type */ 76 unsigned int cstate_type; /* C-state type and not ACPI C-state type */
80 unsigned int num_cstate_subtype; 77 unsigned int num_cstate_subtype;
81 78
82 if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF )
83 return -1;
84
85 if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
86 return -1;
87
88 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
89 percpu_entry->states[cx->index].eax = 0;
90 percpu_entry->states[cx->index].ecx = 0;
91
92 /* Make sure we are running on right CPU */
93 saved_mask = current->cpus_allowed;
94 retval = set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
95 if (retval)
96 return -1;
97
98 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); 79 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
99 80
100 /* Check whether this particular cx_type (in CST) is supported or not */ 81 /* Check whether this particular cx_type (in CST) is supported or not */
101 cstate_type = (cx->address >> MWAIT_SUBSTATE_SIZE) + 1; 82 cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
83 MWAIT_CSTATE_MASK) + 1;
102 edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE); 84 edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
103 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK; 85 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
104 86
@@ -114,21 +96,45 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
114 retval = -1; 96 retval = -1;
115 goto out; 97 goto out;
116 } 98 }
117 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
118
119 /* Use the hint in CST */
120 percpu_entry->states[cx->index].eax = cx->address;
121 99
122 if (!mwait_supported[cstate_type]) { 100 if (!mwait_supported[cstate_type]) {
123 mwait_supported[cstate_type] = 1; 101 mwait_supported[cstate_type] = 1;
124 printk(KERN_DEBUG "Monitor-Mwait will be used to enter C-%d " 102 printk(KERN_DEBUG
125 "state\n", cx->type); 103 "Monitor-Mwait will be used to enter C-%d "
104 "state\n", cx->type);
126 } 105 }
127 snprintf(cx->desc, ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x", 106 snprintf(cx->desc,
128 cx->address); 107 ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
129 108 cx->address);
130out: 109out:
131 set_cpus_allowed_ptr(current, &saved_mask); 110 return retval;
111}
112
113int acpi_processor_ffh_cstate_probe(unsigned int cpu,
114 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
115{
116 struct cstate_entry *percpu_entry;
117 struct cpuinfo_x86 *c = &cpu_data(cpu);
118 long retval;
119
120 if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
121 return -1;
122
123 if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
124 return -1;
125
126 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
127 percpu_entry->states[cx->index].eax = 0;
128 percpu_entry->states[cx->index].ecx = 0;
129
130 /* Make sure we are running on right CPU */
131
132 retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
133 if (retval == 0) {
134 /* Use the hint in CST */
135 percpu_entry->states[cx->index].eax = cx->address;
136 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
137 }
132 return retval; 138 return retval;
133} 139}
134EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); 140EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 806b4e9051b4..707c1f6f95fa 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -159,6 +159,8 @@ static int __init acpi_sleep_setup(char *str)
159#endif 159#endif
160 if (strncmp(str, "old_ordering", 12) == 0) 160 if (strncmp(str, "old_ordering", 12) == 0)
161 acpi_old_suspend_ordering(); 161 acpi_old_suspend_ordering();
162 if (strncmp(str, "s4_nonvs", 8) == 0)
163 acpi_s4_no_nvs();
162 str = strchr(str, ','); 164 str = strchr(str, ',');
163 if (str != NULL) 165 if (str != NULL)
164 str += strspn(str, ", \t"); 166 str += strspn(str, ", \t");
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
index b13d3c4dbd42..0f830e4f5675 100644
--- a/arch/x86/kernel/apic.c
+++ b/arch/x86/kernel/apic.c
@@ -31,9 +31,11 @@
31#include <linux/dmi.h> 31#include <linux/dmi.h>
32#include <linux/dmar.h> 32#include <linux/dmar.h>
33#include <linux/ftrace.h> 33#include <linux/ftrace.h>
34#include <linux/smp.h>
35#include <linux/nmi.h>
36#include <linux/timex.h>
34 37
35#include <asm/atomic.h> 38#include <asm/atomic.h>
36#include <asm/smp.h>
37#include <asm/mtrr.h> 39#include <asm/mtrr.h>
38#include <asm/mpspec.h> 40#include <asm/mpspec.h>
39#include <asm/desc.h> 41#include <asm/desc.h>
@@ -41,12 +43,11 @@
41#include <asm/hpet.h> 43#include <asm/hpet.h>
42#include <asm/pgalloc.h> 44#include <asm/pgalloc.h>
43#include <asm/i8253.h> 45#include <asm/i8253.h>
44#include <asm/nmi.h>
45#include <asm/idle.h> 46#include <asm/idle.h>
46#include <asm/proto.h> 47#include <asm/proto.h>
47#include <asm/timex.h>
48#include <asm/apic.h> 48#include <asm/apic.h>
49#include <asm/i8259.h> 49#include <asm/i8259.h>
50#include <asm/smp.h>
50 51
51#include <mach_apic.h> 52#include <mach_apic.h>
52#include <mach_apicdef.h> 53#include <mach_apicdef.h>
@@ -687,7 +688,7 @@ static int __init calibrate_APIC_clock(void)
687 local_irq_enable(); 688 local_irq_enable();
688 689
689 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 690 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
690 pr_warning("APIC timer disabled due to verification failure.\n"); 691 pr_warning("APIC timer disabled due to verification failure\n");
691 return -1; 692 return -1;
692 } 693 }
693 694
@@ -2087,14 +2088,12 @@ __cpuinit int apic_is_clustered_box(void)
2087 /* are we being called early in kernel startup? */ 2088 /* are we being called early in kernel startup? */
2088 if (bios_cpu_apicid) { 2089 if (bios_cpu_apicid) {
2089 id = bios_cpu_apicid[i]; 2090 id = bios_cpu_apicid[i];
2090 } 2091 } else if (i < nr_cpu_ids) {
2091 else if (i < nr_cpu_ids) {
2092 if (cpu_present(i)) 2092 if (cpu_present(i))
2093 id = per_cpu(x86_bios_cpu_apicid, i); 2093 id = per_cpu(x86_bios_cpu_apicid, i);
2094 else 2094 else
2095 continue; 2095 continue;
2096 } 2096 } else
2097 else
2098 break; 2097 break;
2099 2098
2100 if (id != BAD_APICID) 2099 if (id != BAD_APICID)
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 3a26525a3f31..98807bb095ad 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -160,9 +160,9 @@
160 * Work around byte swap bug in one of the Vaio's BIOS's 160 * Work around byte swap bug in one of the Vaio's BIOS's
161 * (Marc Boucher <marc@mbsi.ca>). 161 * (Marc Boucher <marc@mbsi.ca>).
162 * Exposed the disable flag to dmi so that we can handle known 162 * Exposed the disable flag to dmi so that we can handle known
163 * broken APM (Alan Cox <alan@redhat.com>). 163 * broken APM (Alan Cox <alan@lxorguk.ukuu.org.uk>).
164 * 1.14ac: If the BIOS says "I slowed the CPU down" then don't spin 164 * 1.14ac: If the BIOS says "I slowed the CPU down" then don't spin
165 * calling it - instead idle. (Alan Cox <alan@redhat.com>) 165 * calling it - instead idle. (Alan Cox <alan@lxorguk.ukuu.org.uk>)
166 * If an APM idle fails log it and idle sensibly 166 * If an APM idle fails log it and idle sensibly
167 * 1.15: Don't queue events to clients who open the device O_WRONLY. 167 * 1.15: Don't queue events to clients who open the device O_WRONLY.
168 * Don't expect replies from clients who open the device O_RDONLY. 168 * Don't expect replies from clients who open the device O_RDONLY.
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3f95a40f718a..83492b1f93b1 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -40,6 +40,26 @@
40 40
41#include "cpu.h" 41#include "cpu.h"
42 42
43#ifdef CONFIG_X86_64
44
45/* all of these masks are initialized in setup_cpu_local_masks() */
46cpumask_var_t cpu_callin_mask;
47cpumask_var_t cpu_callout_mask;
48cpumask_var_t cpu_initialized_mask;
49
50/* representing cpus for which sibling maps can be computed */
51cpumask_var_t cpu_sibling_setup_mask;
52
53#else /* CONFIG_X86_32 */
54
55cpumask_t cpu_callin_map;
56cpumask_t cpu_callout_map;
57cpumask_t cpu_initialized;
58cpumask_t cpu_sibling_setup_map;
59
60#endif /* CONFIG_X86_32 */
61
62
43static struct cpu_dev *this_cpu __cpuinitdata; 63static struct cpu_dev *this_cpu __cpuinitdata;
44 64
45#ifdef CONFIG_X86_64 65#ifdef CONFIG_X86_64
@@ -856,8 +876,6 @@ static __init int setup_disablecpuid(char *arg)
856} 876}
857__setup("clearcpuid=", setup_disablecpuid); 877__setup("clearcpuid=", setup_disablecpuid);
858 878
859cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
860
861#ifdef CONFIG_X86_64 879#ifdef CONFIG_X86_64
862struct x8664_pda **_cpu_pda __read_mostly; 880struct x8664_pda **_cpu_pda __read_mostly;
863EXPORT_SYMBOL(_cpu_pda); 881EXPORT_SYMBOL(_cpu_pda);
@@ -976,7 +994,7 @@ void __cpuinit cpu_init(void)
976 994
977 me = current; 995 me = current;
978 996
979 if (cpu_test_and_set(cpu, cpu_initialized)) 997 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
980 panic("CPU#%d already initialized!\n", cpu); 998 panic("CPU#%d already initialized!\n", cpu);
981 999
982 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1000 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
@@ -1085,7 +1103,7 @@ void __cpuinit cpu_init(void)
1085 struct tss_struct *t = &per_cpu(init_tss, cpu); 1103 struct tss_struct *t = &per_cpu(init_tss, cpu);
1086 struct thread_struct *thread = &curr->thread; 1104 struct thread_struct *thread = &curr->thread;
1087 1105
1088 if (cpu_test_and_set(cpu, cpu_initialized)) { 1106 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1089 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); 1107 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1090 for (;;) local_irq_enable(); 1108 for (;;) local_irq_enable();
1091 } 1109 }
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index 28102ad1a363..6f11e029e8c5 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -145,7 +145,7 @@ typedef union {
145 145
146struct drv_cmd { 146struct drv_cmd {
147 unsigned int type; 147 unsigned int type;
148 cpumask_t mask; 148 cpumask_var_t mask;
149 drv_addr_union addr; 149 drv_addr_union addr;
150 u32 val; 150 u32 val;
151}; 151};
@@ -193,7 +193,7 @@ static void drv_read(struct drv_cmd *cmd)
193 cpumask_t saved_mask = current->cpus_allowed; 193 cpumask_t saved_mask = current->cpus_allowed;
194 cmd->val = 0; 194 cmd->val = 0;
195 195
196 set_cpus_allowed_ptr(current, &cmd->mask); 196 set_cpus_allowed_ptr(current, cmd->mask);
197 do_drv_read(cmd); 197 do_drv_read(cmd);
198 set_cpus_allowed_ptr(current, &saved_mask); 198 set_cpus_allowed_ptr(current, &saved_mask);
199} 199}
@@ -203,8 +203,8 @@ static void drv_write(struct drv_cmd *cmd)
203 cpumask_t saved_mask = current->cpus_allowed; 203 cpumask_t saved_mask = current->cpus_allowed;
204 unsigned int i; 204 unsigned int i;
205 205
206 for_each_cpu_mask_nr(i, cmd->mask) { 206 for_each_cpu(i, cmd->mask) {
207 set_cpus_allowed_ptr(current, &cpumask_of_cpu(i)); 207 set_cpus_allowed_ptr(current, cpumask_of(i));
208 do_drv_write(cmd); 208 do_drv_write(cmd);
209 } 209 }
210 210
@@ -212,22 +212,22 @@ static void drv_write(struct drv_cmd *cmd)
212 return; 212 return;
213} 213}
214 214
215static u32 get_cur_val(const cpumask_t *mask) 215static u32 get_cur_val(const struct cpumask *mask)
216{ 216{
217 struct acpi_processor_performance *perf; 217 struct acpi_processor_performance *perf;
218 struct drv_cmd cmd; 218 struct drv_cmd cmd;
219 219
220 if (unlikely(cpus_empty(*mask))) 220 if (unlikely(cpumask_empty(mask)))
221 return 0; 221 return 0;
222 222
223 switch (per_cpu(drv_data, first_cpu(*mask))->cpu_feature) { 223 switch (per_cpu(drv_data, cpumask_first(mask))->cpu_feature) {
224 case SYSTEM_INTEL_MSR_CAPABLE: 224 case SYSTEM_INTEL_MSR_CAPABLE:
225 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; 225 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
226 cmd.addr.msr.reg = MSR_IA32_PERF_STATUS; 226 cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
227 break; 227 break;
228 case SYSTEM_IO_CAPABLE: 228 case SYSTEM_IO_CAPABLE:
229 cmd.type = SYSTEM_IO_CAPABLE; 229 cmd.type = SYSTEM_IO_CAPABLE;
230 perf = per_cpu(drv_data, first_cpu(*mask))->acpi_data; 230 perf = per_cpu(drv_data, cpumask_first(mask))->acpi_data;
231 cmd.addr.io.port = perf->control_register.address; 231 cmd.addr.io.port = perf->control_register.address;
232 cmd.addr.io.bit_width = perf->control_register.bit_width; 232 cmd.addr.io.bit_width = perf->control_register.bit_width;
233 break; 233 break;
@@ -235,7 +235,7 @@ static u32 get_cur_val(const cpumask_t *mask)
235 return 0; 235 return 0;
236 } 236 }
237 237
238 cmd.mask = *mask; 238 cpumask_copy(cmd.mask, mask);
239 239
240 drv_read(&cmd); 240 drv_read(&cmd);
241 241
@@ -244,6 +244,30 @@ static u32 get_cur_val(const cpumask_t *mask)
244 return cmd.val; 244 return cmd.val;
245} 245}
246 246
247struct perf_cur {
248 union {
249 struct {
250 u32 lo;
251 u32 hi;
252 } split;
253 u64 whole;
254 } aperf_cur, mperf_cur;
255};
256
257
258static long read_measured_perf_ctrs(void *_cur)
259{
260 struct perf_cur *cur = _cur;
261
262 rdmsr(MSR_IA32_APERF, cur->aperf_cur.split.lo, cur->aperf_cur.split.hi);
263 rdmsr(MSR_IA32_MPERF, cur->mperf_cur.split.lo, cur->mperf_cur.split.hi);
264
265 wrmsr(MSR_IA32_APERF, 0, 0);
266 wrmsr(MSR_IA32_MPERF, 0, 0);
267
268 return 0;
269}
270
247/* 271/*
248 * Return the measured active (C0) frequency on this CPU since last call 272 * Return the measured active (C0) frequency on this CPU since last call
249 * to this function. 273 * to this function.
@@ -260,31 +284,12 @@ static u32 get_cur_val(const cpumask_t *mask)
260static unsigned int get_measured_perf(struct cpufreq_policy *policy, 284static unsigned int get_measured_perf(struct cpufreq_policy *policy,
261 unsigned int cpu) 285 unsigned int cpu)
262{ 286{
263 union { 287 struct perf_cur cur;
264 struct {
265 u32 lo;
266 u32 hi;
267 } split;
268 u64 whole;
269 } aperf_cur, mperf_cur;
270
271 cpumask_t saved_mask;
272 unsigned int perf_percent; 288 unsigned int perf_percent;
273 unsigned int retval; 289 unsigned int retval;
274 290
275 saved_mask = current->cpus_allowed; 291 if (!work_on_cpu(cpu, read_measured_perf_ctrs, &cur))
276 set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
277 if (get_cpu() != cpu) {
278 /* We were not able to run on requested processor */
279 put_cpu();
280 return 0; 292 return 0;
281 }
282
283 rdmsr(MSR_IA32_APERF, aperf_cur.split.lo, aperf_cur.split.hi);
284 rdmsr(MSR_IA32_MPERF, mperf_cur.split.lo, mperf_cur.split.hi);
285
286 wrmsr(MSR_IA32_APERF, 0,0);
287 wrmsr(MSR_IA32_MPERF, 0,0);
288 293
289#ifdef __i386__ 294#ifdef __i386__
290 /* 295 /*
@@ -292,37 +297,39 @@ static unsigned int get_measured_perf(struct cpufreq_policy *policy,
292 * Get an approximate value. Return failure in case we cannot get 297 * Get an approximate value. Return failure in case we cannot get
293 * an approximate value. 298 * an approximate value.
294 */ 299 */
295 if (unlikely(aperf_cur.split.hi || mperf_cur.split.hi)) { 300 if (unlikely(cur.aperf_cur.split.hi || cur.mperf_cur.split.hi)) {
296 int shift_count; 301 int shift_count;
297 u32 h; 302 u32 h;
298 303
299 h = max_t(u32, aperf_cur.split.hi, mperf_cur.split.hi); 304 h = max_t(u32, cur.aperf_cur.split.hi, cur.mperf_cur.split.hi);
300 shift_count = fls(h); 305 shift_count = fls(h);
301 306
302 aperf_cur.whole >>= shift_count; 307 cur.aperf_cur.whole >>= shift_count;
303 mperf_cur.whole >>= shift_count; 308 cur.mperf_cur.whole >>= shift_count;
304 } 309 }
305 310
306 if (((unsigned long)(-1) / 100) < aperf_cur.split.lo) { 311 if (((unsigned long)(-1) / 100) < cur.aperf_cur.split.lo) {
307 int shift_count = 7; 312 int shift_count = 7;
308 aperf_cur.split.lo >>= shift_count; 313 cur.aperf_cur.split.lo >>= shift_count;
309 mperf_cur.split.lo >>= shift_count; 314 cur.mperf_cur.split.lo >>= shift_count;
310 } 315 }
311 316
312 if (aperf_cur.split.lo && mperf_cur.split.lo) 317 if (cur.aperf_cur.split.lo && cur.mperf_cur.split.lo)
313 perf_percent = (aperf_cur.split.lo * 100) / mperf_cur.split.lo; 318 perf_percent = (cur.aperf_cur.split.lo * 100) /
319 cur.mperf_cur.split.lo;
314 else 320 else
315 perf_percent = 0; 321 perf_percent = 0;
316 322
317#else 323#else
318 if (unlikely(((unsigned long)(-1) / 100) < aperf_cur.whole)) { 324 if (unlikely(((unsigned long)(-1) / 100) < cur.aperf_cur.whole)) {
319 int shift_count = 7; 325 int shift_count = 7;
320 aperf_cur.whole >>= shift_count; 326 cur.aperf_cur.whole >>= shift_count;
321 mperf_cur.whole >>= shift_count; 327 cur.mperf_cur.whole >>= shift_count;
322 } 328 }
323 329
324 if (aperf_cur.whole && mperf_cur.whole) 330 if (cur.aperf_cur.whole && cur.mperf_cur.whole)
325 perf_percent = (aperf_cur.whole * 100) / mperf_cur.whole; 331 perf_percent = (cur.aperf_cur.whole * 100) /
332 cur.mperf_cur.whole;
326 else 333 else
327 perf_percent = 0; 334 perf_percent = 0;
328 335
@@ -330,10 +337,6 @@ static unsigned int get_measured_perf(struct cpufreq_policy *policy,
330 337
331 retval = per_cpu(drv_data, policy->cpu)->max_freq * perf_percent / 100; 338 retval = per_cpu(drv_data, policy->cpu)->max_freq * perf_percent / 100;
332 339
333 put_cpu();
334 set_cpus_allowed_ptr(current, &saved_mask);
335
336 dprintk("cpu %d: performance percent %d\n", cpu, perf_percent);
337 return retval; 340 return retval;
338} 341}
339 342
@@ -351,7 +354,7 @@ static unsigned int get_cur_freq_on_cpu(unsigned int cpu)
351 } 354 }
352 355
353 cached_freq = data->freq_table[data->acpi_data->state].frequency; 356 cached_freq = data->freq_table[data->acpi_data->state].frequency;
354 freq = extract_freq(get_cur_val(&cpumask_of_cpu(cpu)), data); 357 freq = extract_freq(get_cur_val(cpumask_of(cpu)), data);
355 if (freq != cached_freq) { 358 if (freq != cached_freq) {
356 /* 359 /*
357 * The dreaded BIOS frequency change behind our back. 360 * The dreaded BIOS frequency change behind our back.
@@ -386,7 +389,6 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
386 struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu); 389 struct acpi_cpufreq_data *data = per_cpu(drv_data, policy->cpu);
387 struct acpi_processor_performance *perf; 390 struct acpi_processor_performance *perf;
388 struct cpufreq_freqs freqs; 391 struct cpufreq_freqs freqs;
389 cpumask_t online_policy_cpus;
390 struct drv_cmd cmd; 392 struct drv_cmd cmd;
391 unsigned int next_state = 0; /* Index into freq_table */ 393 unsigned int next_state = 0; /* Index into freq_table */
392 unsigned int next_perf_state = 0; /* Index into perf table */ 394 unsigned int next_perf_state = 0; /* Index into perf table */
@@ -401,20 +403,18 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
401 return -ENODEV; 403 return -ENODEV;
402 } 404 }
403 405
406 if (unlikely(!alloc_cpumask_var(&cmd.mask, GFP_KERNEL)))
407 return -ENOMEM;
408
404 perf = data->acpi_data; 409 perf = data->acpi_data;
405 result = cpufreq_frequency_table_target(policy, 410 result = cpufreq_frequency_table_target(policy,
406 data->freq_table, 411 data->freq_table,
407 target_freq, 412 target_freq,
408 relation, &next_state); 413 relation, &next_state);
409 if (unlikely(result)) 414 if (unlikely(result)) {
410 return -ENODEV; 415 result = -ENODEV;
411 416 goto out;
412#ifdef CONFIG_HOTPLUG_CPU 417 }
413 /* cpufreq holds the hotplug lock, so we are safe from here on */
414 cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
415#else
416 online_policy_cpus = policy->cpus;
417#endif
418 418
419 next_perf_state = data->freq_table[next_state].index; 419 next_perf_state = data->freq_table[next_state].index;
420 if (perf->state == next_perf_state) { 420 if (perf->state == next_perf_state) {
@@ -425,7 +425,7 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
425 } else { 425 } else {
426 dprintk("Already at target state (P%d)\n", 426 dprintk("Already at target state (P%d)\n",
427 next_perf_state); 427 next_perf_state);
428 return 0; 428 goto out;
429 } 429 }
430 } 430 }
431 431
@@ -444,19 +444,19 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
444 cmd.val = (u32) perf->states[next_perf_state].control; 444 cmd.val = (u32) perf->states[next_perf_state].control;
445 break; 445 break;
446 default: 446 default:
447 return -ENODEV; 447 result = -ENODEV;
448 goto out;
448 } 449 }
449 450
450 cpus_clear(cmd.mask); 451 /* cpufreq holds the hotplug lock, so we are safe from here on */
451
452 if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) 452 if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY)
453 cmd.mask = online_policy_cpus; 453 cpumask_and(cmd.mask, cpu_online_mask, policy->cpus);
454 else 454 else
455 cpu_set(policy->cpu, cmd.mask); 455 cpumask_copy(cmd.mask, cpumask_of(policy->cpu));
456 456
457 freqs.old = perf->states[perf->state].core_frequency * 1000; 457 freqs.old = perf->states[perf->state].core_frequency * 1000;
458 freqs.new = data->freq_table[next_state].frequency; 458 freqs.new = data->freq_table[next_state].frequency;
459 for_each_cpu_mask_nr(i, cmd.mask) { 459 for_each_cpu(i, cmd.mask) {
460 freqs.cpu = i; 460 freqs.cpu = i;
461 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 461 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
462 } 462 }
@@ -464,19 +464,22 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
464 drv_write(&cmd); 464 drv_write(&cmd);
465 465
466 if (acpi_pstate_strict) { 466 if (acpi_pstate_strict) {
467 if (!check_freqs(&cmd.mask, freqs.new, data)) { 467 if (!check_freqs(cmd.mask, freqs.new, data)) {
468 dprintk("acpi_cpufreq_target failed (%d)\n", 468 dprintk("acpi_cpufreq_target failed (%d)\n",
469 policy->cpu); 469 policy->cpu);
470 return -EAGAIN; 470 result = -EAGAIN;
471 goto out;
471 } 472 }
472 } 473 }
473 474
474 for_each_cpu_mask_nr(i, cmd.mask) { 475 for_each_cpu(i, cmd.mask) {
475 freqs.cpu = i; 476 freqs.cpu = i;
476 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 477 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
477 } 478 }
478 perf->state = next_perf_state; 479 perf->state = next_perf_state;
479 480
481out:
482 free_cpumask_var(cmd.mask);
480 return result; 483 return result;
481} 484}
482 485
@@ -626,15 +629,15 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
626 */ 629 */
627 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || 630 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL ||
628 policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { 631 policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
629 cpumask_copy(&policy->cpus, perf->shared_cpu_map); 632 cpumask_copy(policy->cpus, perf->shared_cpu_map);
630 } 633 }
631 cpumask_copy(&policy->related_cpus, perf->shared_cpu_map); 634 cpumask_copy(policy->related_cpus, perf->shared_cpu_map);
632 635
633#ifdef CONFIG_SMP 636#ifdef CONFIG_SMP
634 dmi_check_system(sw_any_bug_dmi_table); 637 dmi_check_system(sw_any_bug_dmi_table);
635 if (bios_with_sw_any_bug && cpus_weight(policy->cpus) == 1) { 638 if (bios_with_sw_any_bug && cpumask_weight(policy->cpus) == 1) {
636 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; 639 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
637 policy->cpus = per_cpu(cpu_core_map, cpu); 640 cpumask_copy(policy->cpus, cpu_core_mask(cpu));
638 } 641 }
639#endif 642#endif
640 643
diff --git a/arch/x86/kernel/cpu/cpufreq/longhaul.c b/arch/x86/kernel/cpu/cpufreq/longhaul.c
index b0461856acfb..a4cff5d6e380 100644
--- a/arch/x86/kernel/cpu/cpufreq/longhaul.c
+++ b/arch/x86/kernel/cpu/cpufreq/longhaul.c
@@ -982,7 +982,7 @@ static int __init longhaul_init(void)
982 case 10: 982 case 10:
983 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n"); 983 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
984 default: 984 default:
985 ;; 985 ;
986 } 986 }
987 987
988 return -ENODEV; 988 return -ENODEV;
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index beea4466b063..b585e04cbc9e 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -122,7 +122,7 @@ static int cpufreq_p4_target(struct cpufreq_policy *policy,
122 return 0; 122 return 0;
123 123
124 /* notifiers */ 124 /* notifiers */
125 for_each_cpu_mask_nr(i, policy->cpus) { 125 for_each_cpu(i, policy->cpus) {
126 freqs.cpu = i; 126 freqs.cpu = i;
127 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 127 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
128 } 128 }
@@ -130,11 +130,11 @@ static int cpufreq_p4_target(struct cpufreq_policy *policy,
130 /* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software 130 /* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
131 * Developer's Manual, Volume 3 131 * Developer's Manual, Volume 3
132 */ 132 */
133 for_each_cpu_mask_nr(i, policy->cpus) 133 for_each_cpu(i, policy->cpus)
134 cpufreq_p4_setdc(i, p4clockmod_table[newstate].index); 134 cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
135 135
136 /* notifiers */ 136 /* notifiers */
137 for_each_cpu_mask_nr(i, policy->cpus) { 137 for_each_cpu(i, policy->cpus) {
138 freqs.cpu = i; 138 freqs.cpu = i;
139 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 139 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
140 } 140 }
@@ -203,7 +203,7 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
203 unsigned int i; 203 unsigned int i;
204 204
205#ifdef CONFIG_SMP 205#ifdef CONFIG_SMP
206 policy->cpus = per_cpu(cpu_sibling_map, policy->cpu); 206 cpumask_copy(policy->cpus, &per_cpu(cpu_sibling_map, policy->cpu));
207#endif 207#endif
208 208
209 /* Errata workaround */ 209 /* Errata workaround */
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index c3c9adbaa26f..5c28b37dea11 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1199,10 +1199,10 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1199 set_cpus_allowed_ptr(current, &oldmask); 1199 set_cpus_allowed_ptr(current, &oldmask);
1200 1200
1201 if (cpu_family == CPU_HW_PSTATE) 1201 if (cpu_family == CPU_HW_PSTATE)
1202 pol->cpus = cpumask_of_cpu(pol->cpu); 1202 cpumask_copy(pol->cpus, cpumask_of(pol->cpu));
1203 else 1203 else
1204 pol->cpus = per_cpu(cpu_core_map, pol->cpu); 1204 cpumask_copy(pol->cpus, &per_cpu(cpu_core_map, pol->cpu));
1205 data->available_cores = &(pol->cpus); 1205 data->available_cores = pol->cpus;
1206 1206
1207 /* Take a crude guess here. 1207 /* Take a crude guess here.
1208 * That guess was in microseconds, so multiply with 1000 */ 1208 * That guess was in microseconds, so multiply with 1000 */
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index 65cfb5d7f77f..8ecc75b6c7c3 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -53,7 +53,7 @@ struct powernow_k8_data {
53 /* we need to keep track of associated cores, but let cpufreq 53 /* we need to keep track of associated cores, but let cpufreq
54 * handle hotplug events - so just point at cpufreq pol->cpus 54 * handle hotplug events - so just point at cpufreq pol->cpus
55 * structure */ 55 * structure */
56 cpumask_t *available_cores; 56 struct cpumask *available_cores;
57}; 57};
58 58
59 59
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
index f0ea6fa2f53c..f08998278a3a 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -458,11 +458,6 @@ static int centrino_verify (struct cpufreq_policy *policy)
458 * 458 *
459 * Sets a new CPUFreq policy. 459 * Sets a new CPUFreq policy.
460 */ 460 */
461struct allmasks {
462 cpumask_t saved_mask;
463 cpumask_t covered_cpus;
464};
465
466static int centrino_target (struct cpufreq_policy *policy, 461static int centrino_target (struct cpufreq_policy *policy,
467 unsigned int target_freq, 462 unsigned int target_freq,
468 unsigned int relation) 463 unsigned int relation)
@@ -472,12 +467,15 @@ static int centrino_target (struct cpufreq_policy *policy,
472 struct cpufreq_freqs freqs; 467 struct cpufreq_freqs freqs;
473 int retval = 0; 468 int retval = 0;
474 unsigned int j, k, first_cpu, tmp; 469 unsigned int j, k, first_cpu, tmp;
475 CPUMASK_ALLOC(allmasks); 470 cpumask_var_t saved_mask, covered_cpus;
476 CPUMASK_PTR(saved_mask, allmasks);
477 CPUMASK_PTR(covered_cpus, allmasks);
478 471
479 if (unlikely(allmasks == NULL)) 472 if (unlikely(!alloc_cpumask_var(&saved_mask, GFP_KERNEL)))
480 return -ENOMEM; 473 return -ENOMEM;
474 if (unlikely(!alloc_cpumask_var(&covered_cpus, GFP_KERNEL))) {
475 free_cpumask_var(saved_mask);
476 return -ENOMEM;
477 }
478 cpumask_copy(saved_mask, &current->cpus_allowed);
481 479
482 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) { 480 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
483 retval = -ENODEV; 481 retval = -ENODEV;
@@ -493,11 +491,9 @@ static int centrino_target (struct cpufreq_policy *policy,
493 goto out; 491 goto out;
494 } 492 }
495 493
496 *saved_mask = current->cpus_allowed;
497 first_cpu = 1; 494 first_cpu = 1;
498 cpus_clear(*covered_cpus); 495 for_each_cpu(j, policy->cpus) {
499 for_each_cpu_mask_nr(j, policy->cpus) { 496 const struct cpumask *mask;
500 const cpumask_t *mask;
501 497
502 /* cpufreq holds the hotplug lock, so we are safe here */ 498 /* cpufreq holds the hotplug lock, so we are safe here */
503 if (!cpu_online(j)) 499 if (!cpu_online(j))
@@ -508,9 +504,9 @@ static int centrino_target (struct cpufreq_policy *policy,
508 * Make sure we are running on CPU that wants to change freq 504 * Make sure we are running on CPU that wants to change freq
509 */ 505 */
510 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) 506 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
511 mask = &policy->cpus; 507 mask = policy->cpus;
512 else 508 else
513 mask = &cpumask_of_cpu(j); 509 mask = cpumask_of(j);
514 510
515 set_cpus_allowed_ptr(current, mask); 511 set_cpus_allowed_ptr(current, mask);
516 preempt_disable(); 512 preempt_disable();
@@ -542,7 +538,7 @@ static int centrino_target (struct cpufreq_policy *policy,
542 dprintk("target=%dkHz old=%d new=%d msr=%04x\n", 538 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
543 target_freq, freqs.old, freqs.new, msr); 539 target_freq, freqs.old, freqs.new, msr);
544 540
545 for_each_cpu_mask_nr(k, policy->cpus) { 541 for_each_cpu(k, policy->cpus) {
546 if (!cpu_online(k)) 542 if (!cpu_online(k))
547 continue; 543 continue;
548 freqs.cpu = k; 544 freqs.cpu = k;
@@ -567,7 +563,7 @@ static int centrino_target (struct cpufreq_policy *policy,
567 preempt_enable(); 563 preempt_enable();
568 } 564 }
569 565
570 for_each_cpu_mask_nr(k, policy->cpus) { 566 for_each_cpu(k, policy->cpus) {
571 if (!cpu_online(k)) 567 if (!cpu_online(k))
572 continue; 568 continue;
573 freqs.cpu = k; 569 freqs.cpu = k;
@@ -590,7 +586,7 @@ static int centrino_target (struct cpufreq_policy *policy,
590 tmp = freqs.new; 586 tmp = freqs.new;
591 freqs.new = freqs.old; 587 freqs.new = freqs.old;
592 freqs.old = tmp; 588 freqs.old = tmp;
593 for_each_cpu_mask_nr(j, policy->cpus) { 589 for_each_cpu(j, policy->cpus) {
594 if (!cpu_online(j)) 590 if (!cpu_online(j))
595 continue; 591 continue;
596 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 592 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
@@ -605,7 +601,8 @@ migrate_end:
605 preempt_enable(); 601 preempt_enable();
606 set_cpus_allowed_ptr(current, saved_mask); 602 set_cpus_allowed_ptr(current, saved_mask);
607out: 603out:
608 CPUMASK_FREE(allmasks); 604 free_cpumask_var(saved_mask);
605 free_cpumask_var(covered_cpus);
609 return retval; 606 return retval;
610} 607}
611 608
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
index 04d0376b64b0..dedc1e98f168 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
@@ -229,7 +229,7 @@ static unsigned int speedstep_detect_chipset (void)
229 return 0; 229 return 0;
230} 230}
231 231
232static unsigned int _speedstep_get(const cpumask_t *cpus) 232static unsigned int _speedstep_get(const struct cpumask *cpus)
233{ 233{
234 unsigned int speed; 234 unsigned int speed;
235 cpumask_t cpus_allowed; 235 cpumask_t cpus_allowed;
@@ -244,7 +244,7 @@ static unsigned int _speedstep_get(const cpumask_t *cpus)
244 244
245static unsigned int speedstep_get(unsigned int cpu) 245static unsigned int speedstep_get(unsigned int cpu)
246{ 246{
247 return _speedstep_get(&cpumask_of_cpu(cpu)); 247 return _speedstep_get(cpumask_of(cpu));
248} 248}
249 249
250/** 250/**
@@ -267,7 +267,7 @@ static int speedstep_target (struct cpufreq_policy *policy,
267 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], target_freq, relation, &newstate)) 267 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], target_freq, relation, &newstate))
268 return -EINVAL; 268 return -EINVAL;
269 269
270 freqs.old = _speedstep_get(&policy->cpus); 270 freqs.old = _speedstep_get(policy->cpus);
271 freqs.new = speedstep_freqs[newstate].frequency; 271 freqs.new = speedstep_freqs[newstate].frequency;
272 freqs.cpu = policy->cpu; 272 freqs.cpu = policy->cpu;
273 273
@@ -279,20 +279,20 @@ static int speedstep_target (struct cpufreq_policy *policy,
279 279
280 cpus_allowed = current->cpus_allowed; 280 cpus_allowed = current->cpus_allowed;
281 281
282 for_each_cpu_mask_nr(i, policy->cpus) { 282 for_each_cpu(i, policy->cpus) {
283 freqs.cpu = i; 283 freqs.cpu = i;
284 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 284 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
285 } 285 }
286 286
287 /* switch to physical CPU where state is to be changed */ 287 /* switch to physical CPU where state is to be changed */
288 set_cpus_allowed_ptr(current, &policy->cpus); 288 set_cpus_allowed_ptr(current, policy->cpus);
289 289
290 speedstep_set_state(newstate); 290 speedstep_set_state(newstate);
291 291
292 /* allow to be run on all CPUs */ 292 /* allow to be run on all CPUs */
293 set_cpus_allowed_ptr(current, &cpus_allowed); 293 set_cpus_allowed_ptr(current, &cpus_allowed);
294 294
295 for_each_cpu_mask_nr(i, policy->cpus) { 295 for_each_cpu(i, policy->cpus) {
296 freqs.cpu = i; 296 freqs.cpu = i;
297 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 297 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
298 } 298 }
@@ -322,11 +322,11 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
322 322
323 /* only run on CPU to be set, or on its sibling */ 323 /* only run on CPU to be set, or on its sibling */
324#ifdef CONFIG_SMP 324#ifdef CONFIG_SMP
325 policy->cpus = per_cpu(cpu_sibling_map, policy->cpu); 325 cpumask_copy(policy->cpus, &per_cpu(cpu_sibling_map, policy->cpu));
326#endif 326#endif
327 327
328 cpus_allowed = current->cpus_allowed; 328 cpus_allowed = current->cpus_allowed;
329 set_cpus_allowed_ptr(current, &policy->cpus); 329 set_cpus_allowed_ptr(current, policy->cpus);
330 330
331 /* detect low and high frequency and transition latency */ 331 /* detect low and high frequency and transition latency */
332 result = speedstep_get_freqs(speedstep_processor, 332 result = speedstep_get_freqs(speedstep_processor,
@@ -339,7 +339,7 @@ static int speedstep_cpu_init(struct cpufreq_policy *policy)
339 return result; 339 return result;
340 340
341 /* get current speed setting */ 341 /* get current speed setting */
342 speed = _speedstep_get(&policy->cpus); 342 speed = _speedstep_get(policy->cpus);
343 if (!speed) 343 if (!speed)
344 return -EIO; 344 return -EIO;
345 345
diff --git a/arch/x86/kernel/cpu/mcheck/mce_32.c b/arch/x86/kernel/cpu/mcheck/mce_32.c
index 0ebf3fc6a610..dfaebce3633e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_32.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_32.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * mce.c - x86 Machine Check Exception Reporting 2 * mce.c - x86 Machine Check Exception Reporting
3 * (c) 2002 Alan Cox <alan@redhat.com>, Dave Jones <davej@redhat.com> 3 * (c) 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>, Dave Jones <davej@redhat.com>
4 */ 4 */
5 5
6#include <linux/init.h> 6#include <linux/init.h>
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index a5a5e0530370..8ae8c4ff094d 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -462,7 +462,7 @@ out_free:
462 return err; 462 return err;
463} 463}
464 464
465static long local_allocate_threshold_blocks(void *_bank) 465static __cpuinit long local_allocate_threshold_blocks(void *_bank)
466{ 466{
467 unsigned int *bank = _bank; 467 unsigned int *bank = _bank;
468 468
diff --git a/arch/x86/kernel/cpu/mcheck/p5.c b/arch/x86/kernel/cpu/mcheck/p5.c
index bfa5817afdda..c9f77ea69edc 100644
--- a/arch/x86/kernel/cpu/mcheck/p5.c
+++ b/arch/x86/kernel/cpu/mcheck/p5.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * P5 specific Machine Check Exception Reporting 2 * P5 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@redhat.com> 3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
4 */ 4 */
5 5
6#include <linux/init.h> 6#include <linux/init.h>
diff --git a/arch/x86/kernel/cpu/mcheck/p6.c b/arch/x86/kernel/cpu/mcheck/p6.c
index 62efc9c2b3af..2ac52d7b434b 100644
--- a/arch/x86/kernel/cpu/mcheck/p6.c
+++ b/arch/x86/kernel/cpu/mcheck/p6.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * P6 specific Machine Check Exception Reporting 2 * P6 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@redhat.com> 3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
4 */ 4 */
5 5
6#include <linux/init.h> 6#include <linux/init.h>
diff --git a/arch/x86/kernel/cpu/mcheck/winchip.c b/arch/x86/kernel/cpu/mcheck/winchip.c
index f2be3e190c6b..2a043d89811d 100644
--- a/arch/x86/kernel/cpu/mcheck/winchip.c
+++ b/arch/x86/kernel/cpu/mcheck/winchip.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * IDT Winchip specific Machine Check Exception Reporting 2 * IDT Winchip specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@redhat.com> 3 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
4 */ 4 */
5 5
6#include <linux/init.h> 6#include <linux/init.h>
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 65a13943e098..e85826829cf2 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -665,6 +665,27 @@ void __init e820_mark_nosave_regions(unsigned long limit_pfn)
665} 665}
666#endif 666#endif
667 667
668#ifdef CONFIG_HIBERNATION
669/**
670 * Mark ACPI NVS memory region, so that we can save/restore it during
671 * hibernation and the subsequent resume.
672 */
673static int __init e820_mark_nvs_memory(void)
674{
675 int i;
676
677 for (i = 0; i < e820.nr_map; i++) {
678 struct e820entry *ei = &e820.map[i];
679
680 if (ei->type == E820_NVS)
681 hibernate_nvs_register(ei->addr, ei->size);
682 }
683
684 return 0;
685}
686core_initcall(e820_mark_nvs_memory);
687#endif
688
668/* 689/*
669 * Early reserved memory areas. 690 * Early reserved memory areas.
670 */ 691 */
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 744aa7fc49d5..76b8cd953dee 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -201,6 +201,12 @@ struct chipset {
201 void (*f)(int num, int slot, int func); 201 void (*f)(int num, int slot, int func);
202}; 202};
203 203
204/*
205 * Only works for devices on the root bus. If you add any devices
206 * not on bus 0 readd another loop level in early_quirks(). But
207 * be careful because at least the Nvidia quirk here relies on
208 * only matching on bus 0.
209 */
204static struct chipset early_qrk[] __initdata = { 210static struct chipset early_qrk[] __initdata = {
205 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 211 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
206 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs }, 212 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
@@ -267,17 +273,17 @@ static int __init check_dev_quirk(int num, int slot, int func)
267 273
268void __init early_quirks(void) 274void __init early_quirks(void)
269{ 275{
270 int num, slot, func; 276 int slot, func;
271 277
272 if (!early_pci_allowed()) 278 if (!early_pci_allowed())
273 return; 279 return;
274 280
275 /* Poor man's PCI discovery */ 281 /* Poor man's PCI discovery */
276 for (num = 0; num < 32; num++) 282 /* Only scan the root bus */
277 for (slot = 0; slot < 32; slot++) 283 for (slot = 0; slot < 32; slot++)
278 for (func = 0; func < 8; func++) { 284 for (func = 0; func < 8; func++) {
279 /* Only probe function 0 on single fn devices */ 285 /* Only probe function 0 on single fn devices */
280 if (check_dev_quirk(num, slot, func)) 286 if (check_dev_quirk(0, slot, func))
281 break; 287 break;
282 } 288 }
283} 289}
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 26cfdc1d7c7f..0e275d495563 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -305,7 +305,7 @@ ENTRY(early_idt_handler)
305 call dump_stack 305 call dump_stack
306#ifdef CONFIG_KALLSYMS 306#ifdef CONFIG_KALLSYMS
307 leaq early_idt_ripmsg(%rip),%rdi 307 leaq early_idt_ripmsg(%rip),%rdi
308 movq 8(%rsp),%rsi # get rip again 308 movq 0(%rsp),%rsi # get rip again
309 call __print_symbol 309 call __print_symbol
310#endif 310#endif
311#endif /* EARLY_PRINTK */ 311#endif /* EARLY_PRINTK */
diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c
index 4b8a53d841f7..11d5093eb281 100644
--- a/arch/x86/kernel/i8259.c
+++ b/arch/x86/kernel/i8259.c
@@ -11,15 +11,15 @@
11#include <linux/kernel_stat.h> 11#include <linux/kernel_stat.h>
12#include <linux/sysdev.h> 12#include <linux/sysdev.h>
13#include <linux/bitops.h> 13#include <linux/bitops.h>
14#include <linux/acpi.h>
15#include <linux/io.h>
16#include <linux/delay.h>
14 17
15#include <asm/acpi.h>
16#include <asm/atomic.h> 18#include <asm/atomic.h>
17#include <asm/system.h> 19#include <asm/system.h>
18#include <asm/io.h>
19#include <asm/timer.h> 20#include <asm/timer.h>
20#include <asm/hw_irq.h> 21#include <asm/hw_irq.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
22#include <asm/delay.h>
23#include <asm/desc.h> 23#include <asm/desc.h>
24#include <asm/apic.h> 24#include <asm/apic.h>
25#include <asm/arch_hooks.h> 25#include <asm/arch_hooks.h>
@@ -323,7 +323,7 @@ void init_8259A(int auto_eoi)
323 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ 323 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
324 324
325 /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64, 325 /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
326 to 0x20-0x27 on i386 */ 326 to 0x20-0x27 on i386 */
327 outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR); 327 outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
328 328
329 /* 8259A-1 (the master) has a slave on IR2 */ 329 /* 8259A-1 (the master) has a slave on IR2 */
diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c
index 3639442aa7a4..1c4a1302536c 100644
--- a/arch/x86/kernel/io_apic.c
+++ b/arch/x86/kernel/io_apic.c
@@ -129,7 +129,6 @@ static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
129 node = cpu_to_node(cpu); 129 node = cpu_to_node(cpu);
130 130
131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); 131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132 printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node);
133 132
134 return pin; 133 return pin;
135} 134}
@@ -227,7 +226,6 @@ static struct irq_cfg *get_one_free_irq_cfg(int cpu)
227 cpumask_clear(cfg->old_domain); 226 cpumask_clear(cfg->old_domain);
228 } 227 }
229 } 228 }
230 printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
231 229
232 return cfg; 230 return cfg;
233} 231}
diff --git a/arch/x86/kernel/ioport.c b/arch/x86/kernel/ioport.c
index 191914302744..b12208f4dfee 100644
--- a/arch/x86/kernel/ioport.c
+++ b/arch/x86/kernel/ioport.c
@@ -35,8 +35,8 @@ static void set_bitmap(unsigned long *bitmap, unsigned int base,
35 */ 35 */
36asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on) 36asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on)
37{ 37{
38 struct thread_struct * t = &current->thread; 38 struct thread_struct *t = &current->thread;
39 struct tss_struct * tss; 39 struct tss_struct *tss;
40 unsigned int i, max_long, bytes, bytes_updated; 40 unsigned int i, max_long, bytes, bytes_updated;
41 41
42 if ((from + num <= from) || (from + num > IO_BITMAP_BITS)) 42 if ((from + num <= from) || (from + num > IO_BITMAP_BITS))
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index bce53e1352a0..3973e2df7f87 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -5,10 +5,10 @@
5#include <linux/interrupt.h> 5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h> 6#include <linux/kernel_stat.h>
7#include <linux/seq_file.h> 7#include <linux/seq_file.h>
8#include <linux/smp.h>
8 9
9#include <asm/apic.h> 10#include <asm/apic.h>
10#include <asm/io_apic.h> 11#include <asm/io_apic.h>
11#include <asm/smp.h>
12#include <asm/irq.h> 12#include <asm/irq.h>
13 13
14atomic_t irq_err_count; 14atomic_t irq_err_count;
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 9dc5588f336a..74b9ff7341e9 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -15,9 +15,9 @@
15#include <linux/notifier.h> 15#include <linux/notifier.h>
16#include <linux/cpu.h> 16#include <linux/cpu.h>
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/uaccess.h>
18 19
19#include <asm/apic.h> 20#include <asm/apic.h>
20#include <asm/uaccess.h>
21 21
22DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); 22DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
23EXPORT_PER_CPU_SYMBOL(irq_stat); 23EXPORT_PER_CPU_SYMBOL(irq_stat);
@@ -93,7 +93,7 @@ execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
93 return 0; 93 return 0;
94 94
95 /* build the stack frame on the IRQ stack */ 95 /* build the stack frame on the IRQ stack */
96 isp = (u32 *) ((char*)irqctx + sizeof(*irqctx)); 96 isp = (u32 *) ((char *)irqctx + sizeof(*irqctx));
97 irqctx->tinfo.task = curctx->tinfo.task; 97 irqctx->tinfo.task = curctx->tinfo.task;
98 irqctx->tinfo.previous_esp = current_stack_pointer; 98 irqctx->tinfo.previous_esp = current_stack_pointer;
99 99
@@ -137,7 +137,7 @@ void __cpuinit irq_ctx_init(int cpu)
137 137
138 hardirq_ctx[cpu] = irqctx; 138 hardirq_ctx[cpu] = irqctx;
139 139
140 irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE]; 140 irqctx = (union irq_ctx *) &softirq_stack[cpu*THREAD_SIZE];
141 irqctx->tinfo.task = NULL; 141 irqctx->tinfo.task = NULL;
142 irqctx->tinfo.exec_domain = NULL; 142 irqctx->tinfo.exec_domain = NULL;
143 irqctx->tinfo.cpu = cpu; 143 irqctx->tinfo.cpu = cpu;
@@ -147,7 +147,7 @@ void __cpuinit irq_ctx_init(int cpu)
147 softirq_ctx[cpu] = irqctx; 147 softirq_ctx[cpu] = irqctx;
148 148
149 printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n", 149 printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n",
150 cpu,hardirq_ctx[cpu],softirq_ctx[cpu]); 150 cpu, hardirq_ctx[cpu], softirq_ctx[cpu]);
151} 151}
152 152
153void irq_ctx_exit(int cpu) 153void irq_ctx_exit(int cpu)
@@ -174,7 +174,7 @@ asmlinkage void do_softirq(void)
174 irqctx->tinfo.previous_esp = current_stack_pointer; 174 irqctx->tinfo.previous_esp = current_stack_pointer;
175 175
176 /* build the stack frame on the softirq stack */ 176 /* build the stack frame on the softirq stack */
177 isp = (u32*) ((char*)irqctx + sizeof(*irqctx)); 177 isp = (u32 *) ((char *)irqctx + sizeof(*irqctx));
178 178
179 call_on_stack(__do_softirq, isp); 179 call_on_stack(__do_softirq, isp);
180 /* 180 /*
diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c
index 6383d50f82ea..63c88e6ec025 100644
--- a/arch/x86/kernel/irq_64.c
+++ b/arch/x86/kernel/irq_64.c
@@ -14,10 +14,10 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/ftrace.h> 16#include <linux/ftrace.h>
17#include <asm/uaccess.h> 17#include <linux/uaccess.h>
18#include <linux/smp.h>
18#include <asm/io_apic.h> 19#include <asm/io_apic.h>
19#include <asm/idle.h> 20#include <asm/idle.h>
20#include <asm/smp.h>
21 21
22/* 22/*
23 * Probabilistic stack overflow check: 23 * Probabilistic stack overflow check:
@@ -142,18 +142,18 @@ extern void call_softirq(void);
142 142
143asmlinkage void do_softirq(void) 143asmlinkage void do_softirq(void)
144{ 144{
145 __u32 pending; 145 __u32 pending;
146 unsigned long flags; 146 unsigned long flags;
147 147
148 if (in_interrupt()) 148 if (in_interrupt())
149 return; 149 return;
150 150
151 local_irq_save(flags); 151 local_irq_save(flags);
152 pending = local_softirq_pending(); 152 pending = local_softirq_pending();
153 /* Switch to interrupt stack */ 153 /* Switch to interrupt stack */
154 if (pending) { 154 if (pending) {
155 call_softirq(); 155 call_softirq();
156 WARN_ON_ONCE(softirq_count()); 156 WARN_ON_ONCE(softirq_count());
157 } 157 }
158 local_irq_restore(flags); 158 local_irq_restore(flags);
159} 159}
diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c
index 84723295f88a..1507ad4e674d 100644
--- a/arch/x86/kernel/irqinit_32.c
+++ b/arch/x86/kernel/irqinit_32.c
@@ -9,18 +9,18 @@
9#include <linux/kernel_stat.h> 9#include <linux/kernel_stat.h>
10#include <linux/sysdev.h> 10#include <linux/sysdev.h>
11#include <linux/bitops.h> 11#include <linux/bitops.h>
12#include <linux/io.h>
13#include <linux/delay.h>
12 14
13#include <asm/atomic.h> 15#include <asm/atomic.h>
14#include <asm/system.h> 16#include <asm/system.h>
15#include <asm/io.h>
16#include <asm/timer.h> 17#include <asm/timer.h>
17#include <asm/pgtable.h> 18#include <asm/pgtable.h>
18#include <asm/delay.h>
19#include <asm/desc.h> 19#include <asm/desc.h>
20#include <asm/apic.h> 20#include <asm/apic.h>
21#include <asm/arch_hooks.h> 21#include <asm/arch_hooks.h>
22#include <asm/i8259.h> 22#include <asm/i8259.h>
23 23#include <asm/traps.h>
24 24
25 25
26/* 26/*
@@ -34,12 +34,10 @@
34 * leads to races. IBM designers who came up with it should 34 * leads to races. IBM designers who came up with it should
35 * be shot. 35 * be shot.
36 */ 36 */
37
38 37
39static irqreturn_t math_error_irq(int cpl, void *dev_id) 38static irqreturn_t math_error_irq(int cpl, void *dev_id)
40{ 39{
41 extern void math_error(void __user *); 40 outb(0, 0xF0);
42 outb(0,0xF0);
43 if (ignore_fpu_irq || !boot_cpu_data.hard_math) 41 if (ignore_fpu_irq || !boot_cpu_data.hard_math)
44 return IRQ_NONE; 42 return IRQ_NONE;
45 math_error((void __user *)get_irq_regs()->ip); 43 math_error((void __user *)get_irq_regs()->ip);
@@ -56,7 +54,7 @@ static struct irqaction fpu_irq = {
56 .name = "fpu", 54 .name = "fpu",
57}; 55};
58 56
59void __init init_ISA_irqs (void) 57void __init init_ISA_irqs(void)
60{ 58{
61 int i; 59 int i;
62 60
diff --git a/arch/x86/kernel/irqinit_64.c b/arch/x86/kernel/irqinit_64.c
index 31ebfe38e96c..da481a1e3f30 100644
--- a/arch/x86/kernel/irqinit_64.c
+++ b/arch/x86/kernel/irqinit_64.c
@@ -11,14 +11,14 @@
11#include <linux/kernel_stat.h> 11#include <linux/kernel_stat.h>
12#include <linux/sysdev.h> 12#include <linux/sysdev.h>
13#include <linux/bitops.h> 13#include <linux/bitops.h>
14#include <linux/acpi.h>
15#include <linux/io.h>
16#include <linux/delay.h>
14 17
15#include <asm/acpi.h>
16#include <asm/atomic.h> 18#include <asm/atomic.h>
17#include <asm/system.h> 19#include <asm/system.h>
18#include <asm/io.h>
19#include <asm/hw_irq.h> 20#include <asm/hw_irq.h>
20#include <asm/pgtable.h> 21#include <asm/pgtable.h>
21#include <asm/delay.h>
22#include <asm/desc.h> 22#include <asm/desc.h>
23#include <asm/apic.h> 23#include <asm/apic.h>
24#include <asm/i8259.h> 24#include <asm/i8259.h>
@@ -81,7 +81,7 @@ int vector_used_by_percpu_irq(unsigned int vector)
81 return 0; 81 return 0;
82} 82}
83 83
84void __init init_ISA_irqs(void) 84static void __init init_ISA_irqs(void)
85{ 85{
86 int i; 86 int i;
87 87
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index c5c5b8df1dbc..a649a4ccad43 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -2,7 +2,7 @@
2 * Intel Multiprocessor Specification 1.1 and 1.4 2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines. 3 * compliant MP-table parsing routines.
4 * 4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> 7 * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de>
8 */ 8 */
@@ -17,7 +17,6 @@
17#include <linux/acpi.h> 17#include <linux/acpi.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/smp.h> 19#include <linux/smp.h>
20#include <linux/acpi.h>
21 20
22#include <asm/mtrr.h> 21#include <asm/mtrr.h>
23#include <asm/mpspec.h> 22#include <asm/mpspec.h>
@@ -28,6 +27,7 @@
28#include <asm/e820.h> 27#include <asm/e820.h>
29#include <asm/trampoline.h> 28#include <asm/trampoline.h>
30#include <asm/setup.h> 29#include <asm/setup.h>
30#include <asm/smp.h>
31 31
32#include <mach_apic.h> 32#include <mach_apic.h>
33#ifdef CONFIG_X86_32 33#ifdef CONFIG_X86_32
@@ -49,12 +49,12 @@ static int __init mpf_checksum(unsigned char *mp, int len)
49 return sum & 0xFF; 49 return sum & 0xFF;
50} 50}
51 51
52static void __init MP_processor_info(struct mpc_config_processor *m) 52static void __init MP_processor_info(struct mpc_cpu *m)
53{ 53{
54 int apicid; 54 int apicid;
55 char *bootup_cpu = ""; 55 char *bootup_cpu = "";
56 56
57 if (!(m->mpc_cpuflag & CPU_ENABLED)) { 57 if (!(m->cpuflag & CPU_ENABLED)) {
58 disabled_cpus++; 58 disabled_cpus++;
59 return; 59 return;
60 } 60 }
@@ -62,54 +62,54 @@ static void __init MP_processor_info(struct mpc_config_processor *m)
62 if (x86_quirks->mpc_apic_id) 62 if (x86_quirks->mpc_apic_id)
63 apicid = x86_quirks->mpc_apic_id(m); 63 apicid = x86_quirks->mpc_apic_id(m);
64 else 64 else
65 apicid = m->mpc_apicid; 65 apicid = m->apicid;
66 66
67 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { 67 if (m->cpuflag & CPU_BOOTPROCESSOR) {
68 bootup_cpu = " (Bootup-CPU)"; 68 bootup_cpu = " (Bootup-CPU)";
69 boot_cpu_physical_apicid = m->mpc_apicid; 69 boot_cpu_physical_apicid = m->apicid;
70 } 70 }
71 71
72 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); 72 printk(KERN_INFO "Processor #%d%s\n", m->apicid, bootup_cpu);
73 generic_processor_info(apicid, m->mpc_apicver); 73 generic_processor_info(apicid, m->apicver);
74} 74}
75 75
76#ifdef CONFIG_X86_IO_APIC 76#ifdef CONFIG_X86_IO_APIC
77static void __init MP_bus_info(struct mpc_config_bus *m) 77static void __init MP_bus_info(struct mpc_bus *m)
78{ 78{
79 char str[7]; 79 char str[7];
80 memcpy(str, m->mpc_bustype, 6); 80 memcpy(str, m->bustype, 6);
81 str[6] = 0; 81 str[6] = 0;
82 82
83 if (x86_quirks->mpc_oem_bus_info) 83 if (x86_quirks->mpc_oem_bus_info)
84 x86_quirks->mpc_oem_bus_info(m, str); 84 x86_quirks->mpc_oem_bus_info(m, str);
85 else 85 else
86 apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->mpc_busid, str); 86 apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str);
87 87
88#if MAX_MP_BUSSES < 256 88#if MAX_MP_BUSSES < 256
89 if (m->mpc_busid >= MAX_MP_BUSSES) { 89 if (m->busid >= MAX_MP_BUSSES) {
90 printk(KERN_WARNING "MP table busid value (%d) for bustype %s " 90 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
91 " is too large, max. supported is %d\n", 91 " is too large, max. supported is %d\n",
92 m->mpc_busid, str, MAX_MP_BUSSES - 1); 92 m->busid, str, MAX_MP_BUSSES - 1);
93 return; 93 return;
94 } 94 }
95#endif 95#endif
96 96
97 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { 97 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
98 set_bit(m->mpc_busid, mp_bus_not_pci); 98 set_bit(m->busid, mp_bus_not_pci);
99#if defined(CONFIG_EISA) || defined(CONFIG_MCA) 99#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
100 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; 100 mp_bus_id_to_type[m->busid] = MP_BUS_ISA;
101#endif 101#endif
102 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { 102 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
103 if (x86_quirks->mpc_oem_pci_bus) 103 if (x86_quirks->mpc_oem_pci_bus)
104 x86_quirks->mpc_oem_pci_bus(m); 104 x86_quirks->mpc_oem_pci_bus(m);
105 105
106 clear_bit(m->mpc_busid, mp_bus_not_pci); 106 clear_bit(m->busid, mp_bus_not_pci);
107#if defined(CONFIG_EISA) || defined(CONFIG_MCA) 107#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
108 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; 108 mp_bus_id_to_type[m->busid] = MP_BUS_PCI;
109 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { 109 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
110 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; 110 mp_bus_id_to_type[m->busid] = MP_BUS_EISA;
111 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) { 111 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) {
112 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; 112 mp_bus_id_to_type[m->busid] = MP_BUS_MCA;
113#endif 113#endif
114 } else 114 } else
115 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); 115 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
@@ -133,32 +133,31 @@ static int bad_ioapic(unsigned long address)
133 return 0; 133 return 0;
134} 134}
135 135
136static void __init MP_ioapic_info(struct mpc_config_ioapic *m) 136static void __init MP_ioapic_info(struct mpc_ioapic *m)
137{ 137{
138 if (!(m->mpc_flags & MPC_APIC_USABLE)) 138 if (!(m->flags & MPC_APIC_USABLE))
139 return; 139 return;
140 140
141 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", 141 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
142 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); 142 m->apicid, m->apicver, m->apicaddr);
143 143
144 if (bad_ioapic(m->mpc_apicaddr)) 144 if (bad_ioapic(m->apicaddr))
145 return; 145 return;
146 146
147 mp_ioapics[nr_ioapics].mp_apicaddr = m->mpc_apicaddr; 147 mp_ioapics[nr_ioapics].mp_apicaddr = m->apicaddr;
148 mp_ioapics[nr_ioapics].mp_apicid = m->mpc_apicid; 148 mp_ioapics[nr_ioapics].mp_apicid = m->apicid;
149 mp_ioapics[nr_ioapics].mp_type = m->mpc_type; 149 mp_ioapics[nr_ioapics].mp_type = m->type;
150 mp_ioapics[nr_ioapics].mp_apicver = m->mpc_apicver; 150 mp_ioapics[nr_ioapics].mp_apicver = m->apicver;
151 mp_ioapics[nr_ioapics].mp_flags = m->mpc_flags; 151 mp_ioapics[nr_ioapics].mp_flags = m->flags;
152 nr_ioapics++; 152 nr_ioapics++;
153} 153}
154 154
155static void print_MP_intsrc_info(struct mpc_config_intsrc *m) 155static void print_MP_intsrc_info(struct mpc_intsrc *m)
156{ 156{
157 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," 157 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
158 " IRQ %02x, APIC ID %x, APIC INT %02x\n", 158 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
159 m->mpc_irqtype, m->mpc_irqflag & 3, 159 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
160 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, 160 m->srcbusirq, m->dstapic, m->dstirq);
161 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
162} 161}
163 162
164static void __init print_mp_irq_info(struct mp_config_intsrc *mp_irq) 163static void __init print_mp_irq_info(struct mp_config_intsrc *mp_irq)
@@ -170,52 +169,52 @@ static void __init print_mp_irq_info(struct mp_config_intsrc *mp_irq)
170 mp_irq->mp_srcbusirq, mp_irq->mp_dstapic, mp_irq->mp_dstirq); 169 mp_irq->mp_srcbusirq, mp_irq->mp_dstapic, mp_irq->mp_dstirq);
171} 170}
172 171
173static void __init assign_to_mp_irq(struct mpc_config_intsrc *m, 172static void __init assign_to_mp_irq(struct mpc_intsrc *m,
174 struct mp_config_intsrc *mp_irq) 173 struct mp_config_intsrc *mp_irq)
175{ 174{
176 mp_irq->mp_dstapic = m->mpc_dstapic; 175 mp_irq->mp_dstapic = m->dstapic;
177 mp_irq->mp_type = m->mpc_type; 176 mp_irq->mp_type = m->type;
178 mp_irq->mp_irqtype = m->mpc_irqtype; 177 mp_irq->mp_irqtype = m->irqtype;
179 mp_irq->mp_irqflag = m->mpc_irqflag; 178 mp_irq->mp_irqflag = m->irqflag;
180 mp_irq->mp_srcbus = m->mpc_srcbus; 179 mp_irq->mp_srcbus = m->srcbus;
181 mp_irq->mp_srcbusirq = m->mpc_srcbusirq; 180 mp_irq->mp_srcbusirq = m->srcbusirq;
182 mp_irq->mp_dstirq = m->mpc_dstirq; 181 mp_irq->mp_dstirq = m->dstirq;
183} 182}
184 183
185static void __init assign_to_mpc_intsrc(struct mp_config_intsrc *mp_irq, 184static void __init assign_to_mpc_intsrc(struct mp_config_intsrc *mp_irq,
186 struct mpc_config_intsrc *m) 185 struct mpc_intsrc *m)
187{ 186{
188 m->mpc_dstapic = mp_irq->mp_dstapic; 187 m->dstapic = mp_irq->mp_dstapic;
189 m->mpc_type = mp_irq->mp_type; 188 m->type = mp_irq->mp_type;
190 m->mpc_irqtype = mp_irq->mp_irqtype; 189 m->irqtype = mp_irq->mp_irqtype;
191 m->mpc_irqflag = mp_irq->mp_irqflag; 190 m->irqflag = mp_irq->mp_irqflag;
192 m->mpc_srcbus = mp_irq->mp_srcbus; 191 m->srcbus = mp_irq->mp_srcbus;
193 m->mpc_srcbusirq = mp_irq->mp_srcbusirq; 192 m->srcbusirq = mp_irq->mp_srcbusirq;
194 m->mpc_dstirq = mp_irq->mp_dstirq; 193 m->dstirq = mp_irq->mp_dstirq;
195} 194}
196 195
197static int __init mp_irq_mpc_intsrc_cmp(struct mp_config_intsrc *mp_irq, 196static int __init mp_irq_mpc_intsrc_cmp(struct mp_config_intsrc *mp_irq,
198 struct mpc_config_intsrc *m) 197 struct mpc_intsrc *m)
199{ 198{
200 if (mp_irq->mp_dstapic != m->mpc_dstapic) 199 if (mp_irq->mp_dstapic != m->dstapic)
201 return 1; 200 return 1;
202 if (mp_irq->mp_type != m->mpc_type) 201 if (mp_irq->mp_type != m->type)
203 return 2; 202 return 2;
204 if (mp_irq->mp_irqtype != m->mpc_irqtype) 203 if (mp_irq->mp_irqtype != m->irqtype)
205 return 3; 204 return 3;
206 if (mp_irq->mp_irqflag != m->mpc_irqflag) 205 if (mp_irq->mp_irqflag != m->irqflag)
207 return 4; 206 return 4;
208 if (mp_irq->mp_srcbus != m->mpc_srcbus) 207 if (mp_irq->mp_srcbus != m->srcbus)
209 return 5; 208 return 5;
210 if (mp_irq->mp_srcbusirq != m->mpc_srcbusirq) 209 if (mp_irq->mp_srcbusirq != m->srcbusirq)
211 return 6; 210 return 6;
212 if (mp_irq->mp_dstirq != m->mpc_dstirq) 211 if (mp_irq->mp_dstirq != m->dstirq)
213 return 7; 212 return 7;
214 213
215 return 0; 214 return 0;
216} 215}
217 216
218static void __init MP_intsrc_info(struct mpc_config_intsrc *m) 217static void __init MP_intsrc_info(struct mpc_intsrc *m)
219{ 218{
220 int i; 219 int i;
221 220
@@ -233,57 +232,55 @@ static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
233 232
234#endif 233#endif
235 234
236static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) 235static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
237{ 236{
238 apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x," 237 apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x,"
239 " IRQ %02x, APIC ID %x, APIC LINT %02x\n", 238 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
240 m->mpc_irqtype, m->mpc_irqflag & 3, 239 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid,
241 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, 240 m->srcbusirq, m->destapic, m->destapiclint);
242 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
243} 241}
244 242
245/* 243/*
246 * Read/parse the MPC 244 * Read/parse the MPC
247 */ 245 */
248 246
249static int __init smp_check_mpc(struct mp_config_table *mpc, char *oem, 247static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)
250 char *str)
251{ 248{
252 249
253 if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { 250 if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) {
254 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", 251 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
255 mpc->mpc_signature[0], mpc->mpc_signature[1], 252 mpc->signature[0], mpc->signature[1],
256 mpc->mpc_signature[2], mpc->mpc_signature[3]); 253 mpc->signature[2], mpc->signature[3]);
257 return 0; 254 return 0;
258 } 255 }
259 if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { 256 if (mpf_checksum((unsigned char *)mpc, mpc->length)) {
260 printk(KERN_ERR "MPTABLE: checksum error!\n"); 257 printk(KERN_ERR "MPTABLE: checksum error!\n");
261 return 0; 258 return 0;
262 } 259 }
263 if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { 260 if (mpc->spec != 0x01 && mpc->spec != 0x04) {
264 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", 261 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
265 mpc->mpc_spec); 262 mpc->spec);
266 return 0; 263 return 0;
267 } 264 }
268 if (!mpc->mpc_lapic) { 265 if (!mpc->lapic) {
269 printk(KERN_ERR "MPTABLE: null local APIC address!\n"); 266 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
270 return 0; 267 return 0;
271 } 268 }
272 memcpy(oem, mpc->mpc_oem, 8); 269 memcpy(oem, mpc->oem, 8);
273 oem[8] = 0; 270 oem[8] = 0;
274 printk(KERN_INFO "MPTABLE: OEM ID: %s\n", oem); 271 printk(KERN_INFO "MPTABLE: OEM ID: %s\n", oem);
275 272
276 memcpy(str, mpc->mpc_productid, 12); 273 memcpy(str, mpc->productid, 12);
277 str[12] = 0; 274 str[12] = 0;
278 275
279 printk(KERN_INFO "MPTABLE: Product ID: %s\n", str); 276 printk(KERN_INFO "MPTABLE: Product ID: %s\n", str);
280 277
281 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); 278 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->lapic);
282 279
283 return 1; 280 return 1;
284} 281}
285 282
286static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) 283static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
287{ 284{
288 char str[16]; 285 char str[16];
289 char oem[10]; 286 char oem[10];
@@ -308,14 +305,14 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
308#endif 305#endif
309 /* save the local APIC address, it might be non-default */ 306 /* save the local APIC address, it might be non-default */
310 if (!acpi_lapic) 307 if (!acpi_lapic)
311 mp_lapic_addr = mpc->mpc_lapic; 308 mp_lapic_addr = mpc->lapic;
312 309
313 if (early) 310 if (early)
314 return 1; 311 return 1;
315 312
316 if (mpc->mpc_oemptr && x86_quirks->smp_read_mpc_oem) { 313 if (mpc->oemptr && x86_quirks->smp_read_mpc_oem) {
317 struct mp_config_oemtable *oem_table = (struct mp_config_oemtable *)(unsigned long)mpc->mpc_oemptr; 314 struct mpc_oemtable *oem_table = (void *)(long)mpc->oemptr;
318 x86_quirks->smp_read_mpc_oem(oem_table, mpc->mpc_oemsize); 315 x86_quirks->smp_read_mpc_oem(oem_table, mpc->oemsize);
319 } 316 }
320 317
321 /* 318 /*
@@ -324,12 +321,11 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
324 if (x86_quirks->mpc_record) 321 if (x86_quirks->mpc_record)
325 *x86_quirks->mpc_record = 0; 322 *x86_quirks->mpc_record = 0;
326 323
327 while (count < mpc->mpc_length) { 324 while (count < mpc->length) {
328 switch (*mpt) { 325 switch (*mpt) {
329 case MP_PROCESSOR: 326 case MP_PROCESSOR:
330 { 327 {
331 struct mpc_config_processor *m = 328 struct mpc_cpu *m = (struct mpc_cpu *)mpt;
332 (struct mpc_config_processor *)mpt;
333 /* ACPI may have already provided this data */ 329 /* ACPI may have already provided this data */
334 if (!acpi_lapic) 330 if (!acpi_lapic)
335 MP_processor_info(m); 331 MP_processor_info(m);
@@ -339,8 +335,7 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
339 } 335 }
340 case MP_BUS: 336 case MP_BUS:
341 { 337 {
342 struct mpc_config_bus *m = 338 struct mpc_bus *m = (struct mpc_bus *)mpt;
343 (struct mpc_config_bus *)mpt;
344#ifdef CONFIG_X86_IO_APIC 339#ifdef CONFIG_X86_IO_APIC
345 MP_bus_info(m); 340 MP_bus_info(m);
346#endif 341#endif
@@ -351,30 +346,28 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
351 case MP_IOAPIC: 346 case MP_IOAPIC:
352 { 347 {
353#ifdef CONFIG_X86_IO_APIC 348#ifdef CONFIG_X86_IO_APIC
354 struct mpc_config_ioapic *m = 349 struct mpc_ioapic *m = (struct mpc_ioapic *)mpt;
355 (struct mpc_config_ioapic *)mpt;
356 MP_ioapic_info(m); 350 MP_ioapic_info(m);
357#endif 351#endif
358 mpt += sizeof(struct mpc_config_ioapic); 352 mpt += sizeof(struct mpc_ioapic);
359 count += sizeof(struct mpc_config_ioapic); 353 count += sizeof(struct mpc_ioapic);
360 break; 354 break;
361 } 355 }
362 case MP_INTSRC: 356 case MP_INTSRC:
363 { 357 {
364#ifdef CONFIG_X86_IO_APIC 358#ifdef CONFIG_X86_IO_APIC
365 struct mpc_config_intsrc *m = 359 struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
366 (struct mpc_config_intsrc *)mpt;
367 360
368 MP_intsrc_info(m); 361 MP_intsrc_info(m);
369#endif 362#endif
370 mpt += sizeof(struct mpc_config_intsrc); 363 mpt += sizeof(struct mpc_intsrc);
371 count += sizeof(struct mpc_config_intsrc); 364 count += sizeof(struct mpc_intsrc);
372 break; 365 break;
373 } 366 }
374 case MP_LINTSRC: 367 case MP_LINTSRC:
375 { 368 {
376 struct mpc_config_lintsrc *m = 369 struct mpc_lintsrc *m =
377 (struct mpc_config_lintsrc *)mpt; 370 (struct mpc_lintsrc *)mpt;
378 MP_lintsrc_info(m); 371 MP_lintsrc_info(m);
379 mpt += sizeof(*m); 372 mpt += sizeof(*m);
380 count += sizeof(*m); 373 count += sizeof(*m);
@@ -385,8 +378,8 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
385 printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n"); 378 printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n");
386 printk(KERN_ERR "type %x\n", *mpt); 379 printk(KERN_ERR "type %x\n", *mpt);
387 print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, 380 print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16,
388 1, mpc, mpc->mpc_length, 1); 381 1, mpc, mpc->length, 1);
389 count = mpc->mpc_length; 382 count = mpc->length;
390 break; 383 break;
391 } 384 }
392 if (x86_quirks->mpc_record) 385 if (x86_quirks->mpc_record)
@@ -417,16 +410,16 @@ static int __init ELCR_trigger(unsigned int irq)
417 410
418static void __init construct_default_ioirq_mptable(int mpc_default_type) 411static void __init construct_default_ioirq_mptable(int mpc_default_type)
419{ 412{
420 struct mpc_config_intsrc intsrc; 413 struct mpc_intsrc intsrc;
421 int i; 414 int i;
422 int ELCR_fallback = 0; 415 int ELCR_fallback = 0;
423 416
424 intsrc.mpc_type = MP_INTSRC; 417 intsrc.type = MP_INTSRC;
425 intsrc.mpc_irqflag = 0; /* conforming */ 418 intsrc.irqflag = 0; /* conforming */
426 intsrc.mpc_srcbus = 0; 419 intsrc.srcbus = 0;
427 intsrc.mpc_dstapic = mp_ioapics[0].mp_apicid; 420 intsrc.dstapic = mp_ioapics[0].mp_apicid;
428 421
429 intsrc.mpc_irqtype = mp_INT; 422 intsrc.irqtype = mp_INT;
430 423
431 /* 424 /*
432 * If true, we have an ISA/PCI system with no IRQ entries 425 * If true, we have an ISA/PCI system with no IRQ entries
@@ -469,30 +462,30 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
469 * irqflag field (level sensitive, active high polarity). 462 * irqflag field (level sensitive, active high polarity).
470 */ 463 */
471 if (ELCR_trigger(i)) 464 if (ELCR_trigger(i))
472 intsrc.mpc_irqflag = 13; 465 intsrc.irqflag = 13;
473 else 466 else
474 intsrc.mpc_irqflag = 0; 467 intsrc.irqflag = 0;
475 } 468 }
476 469
477 intsrc.mpc_srcbusirq = i; 470 intsrc.srcbusirq = i;
478 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ 471 intsrc.dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
479 MP_intsrc_info(&intsrc); 472 MP_intsrc_info(&intsrc);
480 } 473 }
481 474
482 intsrc.mpc_irqtype = mp_ExtINT; 475 intsrc.irqtype = mp_ExtINT;
483 intsrc.mpc_srcbusirq = 0; 476 intsrc.srcbusirq = 0;
484 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ 477 intsrc.dstirq = 0; /* 8259A to INTIN0 */
485 MP_intsrc_info(&intsrc); 478 MP_intsrc_info(&intsrc);
486} 479}
487 480
488 481
489static void __init construct_ioapic_table(int mpc_default_type) 482static void __init construct_ioapic_table(int mpc_default_type)
490{ 483{
491 struct mpc_config_ioapic ioapic; 484 struct mpc_ioapic ioapic;
492 struct mpc_config_bus bus; 485 struct mpc_bus bus;
493 486
494 bus.mpc_type = MP_BUS; 487 bus.type = MP_BUS;
495 bus.mpc_busid = 0; 488 bus.busid = 0;
496 switch (mpc_default_type) { 489 switch (mpc_default_type) {
497 default: 490 default:
498 printk(KERN_ERR "???\nUnknown standard configuration %d\n", 491 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
@@ -500,29 +493,29 @@ static void __init construct_ioapic_table(int mpc_default_type)
500 /* fall through */ 493 /* fall through */
501 case 1: 494 case 1:
502 case 5: 495 case 5:
503 memcpy(bus.mpc_bustype, "ISA ", 6); 496 memcpy(bus.bustype, "ISA ", 6);
504 break; 497 break;
505 case 2: 498 case 2:
506 case 6: 499 case 6:
507 case 3: 500 case 3:
508 memcpy(bus.mpc_bustype, "EISA ", 6); 501 memcpy(bus.bustype, "EISA ", 6);
509 break; 502 break;
510 case 4: 503 case 4:
511 case 7: 504 case 7:
512 memcpy(bus.mpc_bustype, "MCA ", 6); 505 memcpy(bus.bustype, "MCA ", 6);
513 } 506 }
514 MP_bus_info(&bus); 507 MP_bus_info(&bus);
515 if (mpc_default_type > 4) { 508 if (mpc_default_type > 4) {
516 bus.mpc_busid = 1; 509 bus.busid = 1;
517 memcpy(bus.mpc_bustype, "PCI ", 6); 510 memcpy(bus.bustype, "PCI ", 6);
518 MP_bus_info(&bus); 511 MP_bus_info(&bus);
519 } 512 }
520 513
521 ioapic.mpc_type = MP_IOAPIC; 514 ioapic.type = MP_IOAPIC;
522 ioapic.mpc_apicid = 2; 515 ioapic.apicid = 2;
523 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; 516 ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
524 ioapic.mpc_flags = MPC_APIC_USABLE; 517 ioapic.flags = MPC_APIC_USABLE;
525 ioapic.mpc_apicaddr = 0xFEC00000; 518 ioapic.apicaddr = 0xFEC00000;
526 MP_ioapic_info(&ioapic); 519 MP_ioapic_info(&ioapic);
527 520
528 /* 521 /*
@@ -536,8 +529,8 @@ static inline void __init construct_ioapic_table(int mpc_default_type) { }
536 529
537static inline void __init construct_default_ISA_mptable(int mpc_default_type) 530static inline void __init construct_default_ISA_mptable(int mpc_default_type)
538{ 531{
539 struct mpc_config_processor processor; 532 struct mpc_cpu processor;
540 struct mpc_config_lintsrc lintsrc; 533 struct mpc_lintsrc lintsrc;
541 int linttypes[2] = { mp_ExtINT, mp_NMI }; 534 int linttypes[2] = { mp_ExtINT, mp_NMI };
542 int i; 535 int i;
543 536
@@ -549,30 +542,30 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
549 /* 542 /*
550 * 2 CPUs, numbered 0 & 1. 543 * 2 CPUs, numbered 0 & 1.
551 */ 544 */
552 processor.mpc_type = MP_PROCESSOR; 545 processor.type = MP_PROCESSOR;
553 /* Either an integrated APIC or a discrete 82489DX. */ 546 /* Either an integrated APIC or a discrete 82489DX. */
554 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; 547 processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
555 processor.mpc_cpuflag = CPU_ENABLED; 548 processor.cpuflag = CPU_ENABLED;
556 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | 549 processor.cpufeature = (boot_cpu_data.x86 << 8) |
557 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; 550 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
558 processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; 551 processor.featureflag = boot_cpu_data.x86_capability[0];
559 processor.mpc_reserved[0] = 0; 552 processor.reserved[0] = 0;
560 processor.mpc_reserved[1] = 0; 553 processor.reserved[1] = 0;
561 for (i = 0; i < 2; i++) { 554 for (i = 0; i < 2; i++) {
562 processor.mpc_apicid = i; 555 processor.apicid = i;
563 MP_processor_info(&processor); 556 MP_processor_info(&processor);
564 } 557 }
565 558
566 construct_ioapic_table(mpc_default_type); 559 construct_ioapic_table(mpc_default_type);
567 560
568 lintsrc.mpc_type = MP_LINTSRC; 561 lintsrc.type = MP_LINTSRC;
569 lintsrc.mpc_irqflag = 0; /* conforming */ 562 lintsrc.irqflag = 0; /* conforming */
570 lintsrc.mpc_srcbusid = 0; 563 lintsrc.srcbusid = 0;
571 lintsrc.mpc_srcbusirq = 0; 564 lintsrc.srcbusirq = 0;
572 lintsrc.mpc_destapic = MP_APIC_ALL; 565 lintsrc.destapic = MP_APIC_ALL;
573 for (i = 0; i < 2; i++) { 566 for (i = 0; i < 2; i++) {
574 lintsrc.mpc_irqtype = linttypes[i]; 567 lintsrc.irqtype = linttypes[i];
575 lintsrc.mpc_destapiclint = i; 568 lintsrc.destapiclint = i;
576 MP_lintsrc_info(&lintsrc); 569 MP_lintsrc_info(&lintsrc);
577 } 570 }
578} 571}
@@ -657,15 +650,15 @@ static void __init __get_smp_config(unsigned int early)
657 * ISA defaults and hope it will work. 650 * ISA defaults and hope it will work.
658 */ 651 */
659 if (!mp_irq_entries) { 652 if (!mp_irq_entries) {
660 struct mpc_config_bus bus; 653 struct mpc_bus bus;
661 654
662 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " 655 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
663 "using default mptable. " 656 "using default mptable. "
664 "(tell your hw vendor)\n"); 657 "(tell your hw vendor)\n");
665 658
666 bus.mpc_type = MP_BUS; 659 bus.type = MP_BUS;
667 bus.mpc_busid = 0; 660 bus.busid = 0;
668 memcpy(bus.mpc_bustype, "ISA ", 6); 661 memcpy(bus.bustype, "ISA ", 6);
669 MP_bus_info(&bus); 662 MP_bus_info(&bus);
670 663
671 construct_default_ioirq_mptable(0); 664 construct_default_ioirq_mptable(0);
@@ -803,14 +796,14 @@ void __init find_smp_config(void)
803#ifdef CONFIG_X86_IO_APIC 796#ifdef CONFIG_X86_IO_APIC
804static u8 __initdata irq_used[MAX_IRQ_SOURCES]; 797static u8 __initdata irq_used[MAX_IRQ_SOURCES];
805 798
806static int __init get_MP_intsrc_index(struct mpc_config_intsrc *m) 799static int __init get_MP_intsrc_index(struct mpc_intsrc *m)
807{ 800{
808 int i; 801 int i;
809 802
810 if (m->mpc_irqtype != mp_INT) 803 if (m->irqtype != mp_INT)
811 return 0; 804 return 0;
812 805
813 if (m->mpc_irqflag != 0x0f) 806 if (m->irqflag != 0x0f)
814 return 0; 807 return 0;
815 808
816 /* not legacy */ 809 /* not legacy */
@@ -822,9 +815,9 @@ static int __init get_MP_intsrc_index(struct mpc_config_intsrc *m)
822 if (mp_irqs[i].mp_irqflag != 0x0f) 815 if (mp_irqs[i].mp_irqflag != 0x0f)
823 continue; 816 continue;
824 817
825 if (mp_irqs[i].mp_srcbus != m->mpc_srcbus) 818 if (mp_irqs[i].mp_srcbus != m->srcbus)
826 continue; 819 continue;
827 if (mp_irqs[i].mp_srcbusirq != m->mpc_srcbusirq) 820 if (mp_irqs[i].mp_srcbusirq != m->srcbusirq)
828 continue; 821 continue;
829 if (irq_used[i]) { 822 if (irq_used[i]) {
830 /* already claimed */ 823 /* already claimed */
@@ -840,10 +833,10 @@ static int __init get_MP_intsrc_index(struct mpc_config_intsrc *m)
840 833
841#define SPARE_SLOT_NUM 20 834#define SPARE_SLOT_NUM 20
842 835
843static struct mpc_config_intsrc __initdata *m_spare[SPARE_SLOT_NUM]; 836static struct mpc_intsrc __initdata *m_spare[SPARE_SLOT_NUM];
844#endif 837#endif
845 838
846static int __init replace_intsrc_all(struct mp_config_table *mpc, 839static int __init replace_intsrc_all(struct mpc_table *mpc,
847 unsigned long mpc_new_phys, 840 unsigned long mpc_new_phys,
848 unsigned long mpc_new_length) 841 unsigned long mpc_new_length)
849{ 842{
@@ -855,36 +848,33 @@ static int __init replace_intsrc_all(struct mp_config_table *mpc,
855 int count = sizeof(*mpc); 848 int count = sizeof(*mpc);
856 unsigned char *mpt = ((unsigned char *)mpc) + count; 849 unsigned char *mpt = ((unsigned char *)mpc) + count;
857 850
858 printk(KERN_INFO "mpc_length %x\n", mpc->mpc_length); 851 printk(KERN_INFO "mpc_length %x\n", mpc->length);
859 while (count < mpc->mpc_length) { 852 while (count < mpc->length) {
860 switch (*mpt) { 853 switch (*mpt) {
861 case MP_PROCESSOR: 854 case MP_PROCESSOR:
862 { 855 {
863 struct mpc_config_processor *m = 856 struct mpc_cpu *m = (struct mpc_cpu *)mpt;
864 (struct mpc_config_processor *)mpt;
865 mpt += sizeof(*m); 857 mpt += sizeof(*m);
866 count += sizeof(*m); 858 count += sizeof(*m);
867 break; 859 break;
868 } 860 }
869 case MP_BUS: 861 case MP_BUS:
870 { 862 {
871 struct mpc_config_bus *m = 863 struct mpc_bus *m = (struct mpc_bus *)mpt;
872 (struct mpc_config_bus *)mpt;
873 mpt += sizeof(*m); 864 mpt += sizeof(*m);
874 count += sizeof(*m); 865 count += sizeof(*m);
875 break; 866 break;
876 } 867 }
877 case MP_IOAPIC: 868 case MP_IOAPIC:
878 { 869 {
879 mpt += sizeof(struct mpc_config_ioapic); 870 mpt += sizeof(struct mpc_ioapic);
880 count += sizeof(struct mpc_config_ioapic); 871 count += sizeof(struct mpc_ioapic);
881 break; 872 break;
882 } 873 }
883 case MP_INTSRC: 874 case MP_INTSRC:
884 { 875 {
885#ifdef CONFIG_X86_IO_APIC 876#ifdef CONFIG_X86_IO_APIC
886 struct mpc_config_intsrc *m = 877 struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
887 (struct mpc_config_intsrc *)mpt;
888 878
889 printk(KERN_INFO "OLD "); 879 printk(KERN_INFO "OLD ");
890 print_MP_intsrc_info(m); 880 print_MP_intsrc_info(m);
@@ -905,14 +895,14 @@ static int __init replace_intsrc_all(struct mp_config_table *mpc,
905 nr_m_spare++; 895 nr_m_spare++;
906 } 896 }
907#endif 897#endif
908 mpt += sizeof(struct mpc_config_intsrc); 898 mpt += sizeof(struct mpc_intsrc);
909 count += sizeof(struct mpc_config_intsrc); 899 count += sizeof(struct mpc_intsrc);
910 break; 900 break;
911 } 901 }
912 case MP_LINTSRC: 902 case MP_LINTSRC:
913 { 903 {
914 struct mpc_config_lintsrc *m = 904 struct mpc_lintsrc *m =
915 (struct mpc_config_lintsrc *)mpt; 905 (struct mpc_lintsrc *)mpt;
916 mpt += sizeof(*m); 906 mpt += sizeof(*m);
917 count += sizeof(*m); 907 count += sizeof(*m);
918 break; 908 break;
@@ -922,7 +912,7 @@ static int __init replace_intsrc_all(struct mp_config_table *mpc,
922 printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n"); 912 printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n");
923 printk(KERN_ERR "type %x\n", *mpt); 913 printk(KERN_ERR "type %x\n", *mpt);
924 print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, 914 print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16,
925 1, mpc, mpc->mpc_length, 1); 915 1, mpc, mpc->length, 1);
926 goto out; 916 goto out;
927 } 917 }
928 } 918 }
@@ -944,9 +934,8 @@ static int __init replace_intsrc_all(struct mp_config_table *mpc,
944 assign_to_mpc_intsrc(&mp_irqs[i], m_spare[nr_m_spare]); 934 assign_to_mpc_intsrc(&mp_irqs[i], m_spare[nr_m_spare]);
945 m_spare[nr_m_spare] = NULL; 935 m_spare[nr_m_spare] = NULL;
946 } else { 936 } else {
947 struct mpc_config_intsrc *m = 937 struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
948 (struct mpc_config_intsrc *)mpt; 938 count += sizeof(struct mpc_intsrc);
949 count += sizeof(struct mpc_config_intsrc);
950 if (!mpc_new_phys) { 939 if (!mpc_new_phys) {
951 printk(KERN_INFO "No spare slots, try to append...take your risk, new mpc_length %x\n", count); 940 printk(KERN_INFO "No spare slots, try to append...take your risk, new mpc_length %x\n", count);
952 } else { 941 } else {
@@ -958,17 +947,16 @@ static int __init replace_intsrc_all(struct mp_config_table *mpc,
958 } 947 }
959 } 948 }
960 assign_to_mpc_intsrc(&mp_irqs[i], m); 949 assign_to_mpc_intsrc(&mp_irqs[i], m);
961 mpc->mpc_length = count; 950 mpc->length = count;
962 mpt += sizeof(struct mpc_config_intsrc); 951 mpt += sizeof(struct mpc_intsrc);
963 } 952 }
964 print_mp_irq_info(&mp_irqs[i]); 953 print_mp_irq_info(&mp_irqs[i]);
965 } 954 }
966#endif 955#endif
967out: 956out:
968 /* update checksum */ 957 /* update checksum */
969 mpc->mpc_checksum = 0; 958 mpc->checksum = 0;
970 mpc->mpc_checksum -= mpf_checksum((unsigned char *)mpc, 959 mpc->checksum -= mpf_checksum((unsigned char *)mpc, mpc->length);
971 mpc->mpc_length);
972 960
973 return 0; 961 return 0;
974} 962}
@@ -1014,8 +1002,7 @@ static int __init update_mp_table(void)
1014 char str[16]; 1002 char str[16];
1015 char oem[10]; 1003 char oem[10];
1016 struct intel_mp_floating *mpf; 1004 struct intel_mp_floating *mpf;
1017 struct mp_config_table *mpc; 1005 struct mpc_table *mpc, *mpc_new;
1018 struct mp_config_table *mpc_new;
1019 1006
1020 if (!enable_update_mptable) 1007 if (!enable_update_mptable)
1021 return 0; 1008 return 0;
@@ -1041,7 +1028,7 @@ static int __init update_mp_table(void)
1041 printk(KERN_INFO "mpf: %lx\n", virt_to_phys(mpf)); 1028 printk(KERN_INFO "mpf: %lx\n", virt_to_phys(mpf));
1042 printk(KERN_INFO "mpf_physptr: %x\n", mpf->mpf_physptr); 1029 printk(KERN_INFO "mpf_physptr: %x\n", mpf->mpf_physptr);
1043 1030
1044 if (mpc_new_phys && mpc->mpc_length > mpc_new_length) { 1031 if (mpc_new_phys && mpc->length > mpc_new_length) {
1045 mpc_new_phys = 0; 1032 mpc_new_phys = 0;
1046 printk(KERN_INFO "mpc_new_length is %ld, please use alloc_mptable=8k\n", 1033 printk(KERN_INFO "mpc_new_length is %ld, please use alloc_mptable=8k\n",
1047 mpc_new_length); 1034 mpc_new_length);
@@ -1050,10 +1037,10 @@ static int __init update_mp_table(void)
1050 if (!mpc_new_phys) { 1037 if (!mpc_new_phys) {
1051 unsigned char old, new; 1038 unsigned char old, new;
1052 /* check if we can change the postion */ 1039 /* check if we can change the postion */
1053 mpc->mpc_checksum = 0; 1040 mpc->checksum = 0;
1054 old = mpf_checksum((unsigned char *)mpc, mpc->mpc_length); 1041 old = mpf_checksum((unsigned char *)mpc, mpc->length);
1055 mpc->mpc_checksum = 0xff; 1042 mpc->checksum = 0xff;
1056 new = mpf_checksum((unsigned char *)mpc, mpc->mpc_length); 1043 new = mpf_checksum((unsigned char *)mpc, mpc->length);
1057 if (old == new) { 1044 if (old == new) {
1058 printk(KERN_INFO "mpc is readonly, please try alloc_mptable instead\n"); 1045 printk(KERN_INFO "mpc is readonly, please try alloc_mptable instead\n");
1059 return 0; 1046 return 0;
@@ -1062,7 +1049,7 @@ static int __init update_mp_table(void)
1062 } else { 1049 } else {
1063 mpf->mpf_physptr = mpc_new_phys; 1050 mpf->mpf_physptr = mpc_new_phys;
1064 mpc_new = phys_to_virt(mpc_new_phys); 1051 mpc_new = phys_to_virt(mpc_new_phys);
1065 memcpy(mpc_new, mpc, mpc->mpc_length); 1052 memcpy(mpc_new, mpc, mpc->length);
1066 mpc = mpc_new; 1053 mpc = mpc_new;
1067 /* check if we can modify that */ 1054 /* check if we can modify that */
1068 if (mpc_new_phys - mpf->mpf_physptr) { 1055 if (mpc_new_phys - mpf->mpf_physptr) {
diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c
index 45a09ccdc214..7228979f1e7f 100644
--- a/arch/x86/kernel/nmi.c
+++ b/arch/x86/kernel/nmi.c
@@ -26,7 +26,6 @@
26#include <linux/kernel_stat.h> 26#include <linux/kernel_stat.h>
27#include <linux/kdebug.h> 27#include <linux/kdebug.h>
28#include <linux/smp.h> 28#include <linux/smp.h>
29#include <linux/nmi.h>
30 29
31#include <asm/i8259.h> 30#include <asm/i8259.h>
32#include <asm/io_apic.h> 31#include <asm/io_apic.h>
diff --git a/arch/x86/kernel/numaq_32.c b/arch/x86/kernel/numaq_32.c
index 0deea37a53cf..f2191d4f2717 100644
--- a/arch/x86/kernel/numaq_32.c
+++ b/arch/x86/kernel/numaq_32.c
@@ -117,16 +117,15 @@ static inline int generate_logical_apicid(int quad, int phys_apicid)
117} 117}
118 118
119/* x86_quirks member */ 119/* x86_quirks member */
120static int mpc_apic_id(struct mpc_config_processor *m) 120static int mpc_apic_id(struct mpc_cpu *m)
121{ 121{
122 int quad = translation_table[mpc_record]->trans_quad; 122 int quad = translation_table[mpc_record]->trans_quad;
123 int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid); 123 int logical_apicid = generate_logical_apicid(quad, m->apicid);
124 124
125 printk(KERN_DEBUG "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n", 125 printk(KERN_DEBUG "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
126 m->mpc_apicid, 126 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
127 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 127 (m->cpufeature & CPU_MODEL_MASK) >> 4,
128 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, 128 m->apicver, quad, logical_apicid);
129 m->mpc_apicver, quad, logical_apicid);
130 return logical_apicid; 129 return logical_apicid;
131} 130}
132 131
@@ -135,26 +134,26 @@ int mp_bus_id_to_node[MAX_MP_BUSSES];
135int mp_bus_id_to_local[MAX_MP_BUSSES]; 134int mp_bus_id_to_local[MAX_MP_BUSSES];
136 135
137/* x86_quirks member */ 136/* x86_quirks member */
138static void mpc_oem_bus_info(struct mpc_config_bus *m, char *name) 137static void mpc_oem_bus_info(struct mpc_bus *m, char *name)
139{ 138{
140 int quad = translation_table[mpc_record]->trans_quad; 139 int quad = translation_table[mpc_record]->trans_quad;
141 int local = translation_table[mpc_record]->trans_local; 140 int local = translation_table[mpc_record]->trans_local;
142 141
143 mp_bus_id_to_node[m->mpc_busid] = quad; 142 mp_bus_id_to_node[m->busid] = quad;
144 mp_bus_id_to_local[m->mpc_busid] = local; 143 mp_bus_id_to_local[m->busid] = local;
145 printk(KERN_INFO "Bus #%d is %s (node %d)\n", 144 printk(KERN_INFO "Bus #%d is %s (node %d)\n",
146 m->mpc_busid, name, quad); 145 m->busid, name, quad);
147} 146}
148 147
149int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 148int quad_local_to_mp_bus_id [NR_CPUS/4][4];
150 149
151/* x86_quirks member */ 150/* x86_quirks member */
152static void mpc_oem_pci_bus(struct mpc_config_bus *m) 151static void mpc_oem_pci_bus(struct mpc_bus *m)
153{ 152{
154 int quad = translation_table[mpc_record]->trans_quad; 153 int quad = translation_table[mpc_record]->trans_quad;
155 int local = translation_table[mpc_record]->trans_local; 154 int local = translation_table[mpc_record]->trans_local;
156 155
157 quad_local_to_mp_bus_id[quad][local] = m->mpc_busid; 156 quad_local_to_mp_bus_id[quad][local] = m->busid;
158} 157}
159 158
160static void __init MP_translation_info(struct mpc_config_translation *m) 159static void __init MP_translation_info(struct mpc_config_translation *m)
@@ -186,7 +185,7 @@ static int __init mpf_checksum(unsigned char *mp, int len)
186 * Read/parse the MPC oem tables 185 * Read/parse the MPC oem tables
187 */ 186 */
188 187
189static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, 188static void __init smp_read_mpc_oem(struct mpc_oemtable *oemtable,
190 unsigned short oemsize) 189 unsigned short oemsize)
191{ 190{
192 int count = sizeof(*oemtable); /* the header size */ 191 int count = sizeof(*oemtable); /* the header size */
@@ -195,18 +194,18 @@ static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable,
195 mpc_record = 0; 194 mpc_record = 0;
196 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", 195 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n",
197 oemtable); 196 oemtable);
198 if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) { 197 if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) {
199 printk(KERN_WARNING 198 printk(KERN_WARNING
200 "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", 199 "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
201 oemtable->oem_signature[0], oemtable->oem_signature[1], 200 oemtable->signature[0], oemtable->signature[1],
202 oemtable->oem_signature[2], oemtable->oem_signature[3]); 201 oemtable->signature[2], oemtable->signature[3]);
203 return; 202 return;
204 } 203 }
205 if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) { 204 if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) {
206 printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); 205 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
207 return; 206 return;
208 } 207 }
209 while (count < oemtable->oem_length) { 208 while (count < oemtable->length) {
210 switch (*oemptr) { 209 switch (*oemptr) {
211 case MP_TRANSLATION: 210 case MP_TRANSLATION:
212 { 211 {
@@ -260,8 +259,7 @@ static struct x86_quirks numaq_x86_quirks __initdata = {
260 .update_genapic = numaq_update_genapic, 259 .update_genapic = numaq_update_genapic,
261}; 260};
262 261
263void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem, 262void numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
264 char *productid)
265{ 263{
266 if (strncmp(oem, "IBM NUMA", 8)) 264 if (strncmp(oem, "IBM NUMA", 8))
267 printk("Warning! Not a NUMA-Q system!\n"); 265 printk("Warning! Not a NUMA-Q system!\n");
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 3ba155d24884..a546f55c77b4 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -39,11 +39,12 @@
39#include <linux/prctl.h> 39#include <linux/prctl.h>
40#include <linux/dmi.h> 40#include <linux/dmi.h>
41#include <linux/ftrace.h> 41#include <linux/ftrace.h>
42#include <linux/uaccess.h>
43#include <linux/io.h>
44#include <linux/kdebug.h>
42 45
43#include <asm/uaccess.h>
44#include <asm/pgtable.h> 46#include <asm/pgtable.h>
45#include <asm/system.h> 47#include <asm/system.h>
46#include <asm/io.h>
47#include <asm/ldt.h> 48#include <asm/ldt.h>
48#include <asm/processor.h> 49#include <asm/processor.h>
49#include <asm/i387.h> 50#include <asm/i387.h>
@@ -56,10 +57,8 @@
56 57
57#include <asm/tlbflush.h> 58#include <asm/tlbflush.h>
58#include <asm/cpu.h> 59#include <asm/cpu.h>
59#include <asm/kdebug.h>
60#include <asm/idle.h> 60#include <asm/idle.h>
61#include <asm/syscalls.h> 61#include <asm/syscalls.h>
62#include <asm/smp.h>
63#include <asm/ds.h> 62#include <asm/ds.h>
64 63
65asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); 64asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
@@ -205,7 +204,7 @@ extern void kernel_thread_helper(void);
205/* 204/*
206 * Create a kernel thread 205 * Create a kernel thread
207 */ 206 */
208int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) 207int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
209{ 208{
210 struct pt_regs regs; 209 struct pt_regs regs;
211 210
@@ -266,7 +265,7 @@ void flush_thread(void)
266 tsk->thread.debugreg3 = 0; 265 tsk->thread.debugreg3 = 0;
267 tsk->thread.debugreg6 = 0; 266 tsk->thread.debugreg6 = 0;
268 tsk->thread.debugreg7 = 0; 267 tsk->thread.debugreg7 = 0;
269 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); 268 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
270 clear_tsk_thread_flag(tsk, TIF_DEBUG); 269 clear_tsk_thread_flag(tsk, TIF_DEBUG);
271 /* 270 /*
272 * Forget coprocessor state.. 271 * Forget coprocessor state..
@@ -293,9 +292,9 @@ void prepare_to_copy(struct task_struct *tsk)
293 292
294int copy_thread(int nr, unsigned long clone_flags, unsigned long sp, 293int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
295 unsigned long unused, 294 unsigned long unused,
296 struct task_struct * p, struct pt_regs * regs) 295 struct task_struct *p, struct pt_regs *regs)
297{ 296{
298 struct pt_regs * childregs; 297 struct pt_regs *childregs;
299 struct task_struct *tsk; 298 struct task_struct *tsk;
300 int err; 299 int err;
301 300
@@ -347,7 +346,7 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
347void 346void
348start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) 347start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
349{ 348{
350 __asm__("movl %0, %%gs" :: "r"(0)); 349 __asm__("movl %0, %%gs" : : "r"(0));
351 regs->fs = 0; 350 regs->fs = 0;
352 set_fs(USER_DS); 351 set_fs(USER_DS);
353 regs->ds = __USER_DS; 352 regs->ds = __USER_DS;
@@ -638,7 +637,7 @@ asmlinkage int sys_vfork(struct pt_regs regs)
638asmlinkage int sys_execve(struct pt_regs regs) 637asmlinkage int sys_execve(struct pt_regs regs)
639{ 638{
640 int error; 639 int error;
641 char * filename; 640 char *filename;
642 641
643 filename = getname((char __user *) regs.bx); 642 filename = getname((char __user *) regs.bx);
644 error = PTR_ERR(filename); 643 error = PTR_ERR(filename);
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index a4b619c33106..55c46074eba0 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -5,12 +5,11 @@
5#include <linux/percpu.h> 5#include <linux/percpu.h>
6#include <linux/kexec.h> 6#include <linux/kexec.h>
7#include <linux/crash_dump.h> 7#include <linux/crash_dump.h>
8#include <asm/smp.h> 8#include <linux/smp.h>
9#include <asm/percpu.h> 9#include <linux/topology.h>
10#include <asm/sections.h> 10#include <asm/sections.h>
11#include <asm/processor.h> 11#include <asm/processor.h>
12#include <asm/setup.h> 12#include <asm/setup.h>
13#include <asm/topology.h>
14#include <asm/mpspec.h> 13#include <asm/mpspec.h>
15#include <asm/apicdef.h> 14#include <asm/apicdef.h>
16#include <asm/highmem.h> 15#include <asm/highmem.h>
@@ -20,8 +19,8 @@ unsigned int num_processors;
20unsigned disabled_cpus __cpuinitdata; 19unsigned disabled_cpus __cpuinitdata;
21/* Processor that is doing the boot up */ 20/* Processor that is doing the boot up */
22unsigned int boot_cpu_physical_apicid = -1U; 21unsigned int boot_cpu_physical_apicid = -1U;
23unsigned int max_physical_apicid;
24EXPORT_SYMBOL(boot_cpu_physical_apicid); 22EXPORT_SYMBOL(boot_cpu_physical_apicid);
23unsigned int max_physical_apicid;
25 24
26/* Bitmask of physically existing CPUs */ 25/* Bitmask of physically existing CPUs */
27physid_mask_t phys_cpu_present_map; 26physid_mask_t phys_cpu_present_map;
@@ -131,7 +130,27 @@ static void __init setup_cpu_pda_map(void)
131 /* point to new pointer table */ 130 /* point to new pointer table */
132 _cpu_pda = new_cpu_pda; 131 _cpu_pda = new_cpu_pda;
133} 132}
134#endif 133
134#endif /* CONFIG_SMP && CONFIG_X86_64 */
135
136#ifdef CONFIG_X86_64
137
138/* correctly size the local cpu masks */
139static void setup_cpu_local_masks(void)
140{
141 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
142 alloc_bootmem_cpumask_var(&cpu_callin_mask);
143 alloc_bootmem_cpumask_var(&cpu_callout_mask);
144 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
145}
146
147#else /* CONFIG_X86_32 */
148
149static inline void setup_cpu_local_masks(void)
150{
151}
152
153#endif /* CONFIG_X86_32 */
135 154
136/* 155/*
137 * Great future plan: 156 * Great future plan:
@@ -187,6 +206,9 @@ void __init setup_per_cpu_areas(void)
187 206
188 /* Setup node to cpumask map */ 207 /* Setup node to cpumask map */
189 setup_node_to_cpumask_map(); 208 setup_node_to_cpumask_map();
209
210 /* Setup cpu initialized, callin, callout masks */
211 setup_cpu_local_masks();
190} 212}
191 213
192#endif 214#endif
@@ -280,8 +302,8 @@ static void __cpuinit numa_set_cpumask(int cpu, int enable)
280 302
281 cpulist_scnprintf(buf, sizeof(buf), mask); 303 cpulist_scnprintf(buf, sizeof(buf), mask);
282 printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n", 304 printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n",
283 enable? "numa_add_cpu":"numa_remove_cpu", cpu, node, buf); 305 enable ? "numa_add_cpu" : "numa_remove_cpu", cpu, node, buf);
284 } 306}
285 307
286void __cpuinit numa_add_cpu(int cpu) 308void __cpuinit numa_add_cpu(int cpu)
287{ 309{
diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c
index beea2649a240..e6faa3316bd2 100644
--- a/arch/x86/kernel/smp.c
+++ b/arch/x86/kernel/smp.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Intel SMP support routines. 2 * Intel SMP support routines.
3 * 3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com> 5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
6 * (c) 2002,2003 Andi Kleen, SuSE Labs. 6 * (c) 2002,2003 Andi Kleen, SuSE Labs.
7 * 7 *
@@ -128,16 +128,23 @@ void native_send_call_func_single_ipi(int cpu)
128 128
129void native_send_call_func_ipi(const struct cpumask *mask) 129void native_send_call_func_ipi(const struct cpumask *mask)
130{ 130{
131 cpumask_t allbutself; 131 cpumask_var_t allbutself;
132 132
133 allbutself = cpu_online_map; 133 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
134 cpu_clear(smp_processor_id(), allbutself); 134 send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
135 return;
136 }
135 137
136 if (cpus_equal(*mask, allbutself) && 138 cpumask_copy(allbutself, cpu_online_mask);
137 cpus_equal(cpu_online_map, cpu_callout_map)) 139 cpumask_clear_cpu(smp_processor_id(), allbutself);
140
141 if (cpumask_equal(mask, allbutself) &&
142 cpumask_equal(cpu_online_mask, cpu_callout_mask))
138 send_IPI_allbutself(CALL_FUNCTION_VECTOR); 143 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
139 else 144 else
140 send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 145 send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
146
147 free_cpumask_var(allbutself);
141} 148}
142 149
143/* 150/*
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 6bd4d9b73870..bb1a3b1fc87f 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * x86 SMP booting functions 2 * x86 SMP booting functions
3 * 3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs. 6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 * 7 *
@@ -102,9 +102,6 @@ EXPORT_SYMBOL(smp_num_siblings);
102/* Last level cache ID of each logical CPU */ 102/* Last level cache ID of each logical CPU */
103DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 103DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
104 104
105cpumask_t cpu_callin_map;
106cpumask_t cpu_callout_map;
107
108/* representing HT siblings of each logical CPU */ 105/* representing HT siblings of each logical CPU */
109DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); 106DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
110EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 107EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
@@ -120,9 +117,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_info);
120static atomic_t init_deasserted; 117static atomic_t init_deasserted;
121 118
122 119
123/* representing cpus for which sibling maps can be computed */
124static cpumask_t cpu_sibling_setup_map;
125
126/* Set if we find a B stepping CPU */ 120/* Set if we find a B stepping CPU */
127static int __cpuinitdata smp_b_stepping; 121static int __cpuinitdata smp_b_stepping;
128 122
@@ -140,7 +134,7 @@ EXPORT_SYMBOL(cpu_to_node_map);
140static void map_cpu_to_node(int cpu, int node) 134static void map_cpu_to_node(int cpu, int node)
141{ 135{
142 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 136 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
143 cpu_set(cpu, node_to_cpumask_map[node]); 137 cpumask_set_cpu(cpu, &node_to_cpumask_map[node]);
144 cpu_to_node_map[cpu] = node; 138 cpu_to_node_map[cpu] = node;
145} 139}
146 140
@@ -151,7 +145,7 @@ static void unmap_cpu_to_node(int cpu)
151 145
152 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 146 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
153 for (node = 0; node < MAX_NUMNODES; node++) 147 for (node = 0; node < MAX_NUMNODES; node++)
154 cpu_clear(cpu, node_to_cpumask_map[node]); 148 cpumask_clear_cpu(cpu, &node_to_cpumask_map[node]);
155 cpu_to_node_map[cpu] = 0; 149 cpu_to_node_map[cpu] = 0;
156} 150}
157#else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 151#else /* !(CONFIG_NUMA && CONFIG_X86_32) */
@@ -209,7 +203,7 @@ static void __cpuinit smp_callin(void)
209 */ 203 */
210 phys_id = read_apic_id(); 204 phys_id = read_apic_id();
211 cpuid = smp_processor_id(); 205 cpuid = smp_processor_id();
212 if (cpu_isset(cpuid, cpu_callin_map)) { 206 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
213 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 207 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
214 phys_id, cpuid); 208 phys_id, cpuid);
215 } 209 }
@@ -231,7 +225,7 @@ static void __cpuinit smp_callin(void)
231 /* 225 /*
232 * Has the boot CPU finished it's STARTUP sequence? 226 * Has the boot CPU finished it's STARTUP sequence?
233 */ 227 */
234 if (cpu_isset(cpuid, cpu_callout_map)) 228 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
235 break; 229 break;
236 cpu_relax(); 230 cpu_relax();
237 } 231 }
@@ -274,7 +268,7 @@ static void __cpuinit smp_callin(void)
274 /* 268 /*
275 * Allow the master to continue. 269 * Allow the master to continue.
276 */ 270 */
277 cpu_set(cpuid, cpu_callin_map); 271 cpumask_set_cpu(cpuid, cpu_callin_mask);
278} 272}
279 273
280static int __cpuinitdata unsafe_smp; 274static int __cpuinitdata unsafe_smp;
@@ -332,7 +326,7 @@ notrace static void __cpuinit start_secondary(void *unused)
332 ipi_call_lock(); 326 ipi_call_lock();
333 lock_vector_lock(); 327 lock_vector_lock();
334 __setup_vector_irq(smp_processor_id()); 328 __setup_vector_irq(smp_processor_id());
335 cpu_set(smp_processor_id(), cpu_online_map); 329 set_cpu_online(smp_processor_id(), true);
336 unlock_vector_lock(); 330 unlock_vector_lock();
337 ipi_call_unlock(); 331 ipi_call_unlock();
338 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 332 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
@@ -438,50 +432,52 @@ void __cpuinit set_cpu_sibling_map(int cpu)
438 int i; 432 int i;
439 struct cpuinfo_x86 *c = &cpu_data(cpu); 433 struct cpuinfo_x86 *c = &cpu_data(cpu);
440 434
441 cpu_set(cpu, cpu_sibling_setup_map); 435 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
442 436
443 if (smp_num_siblings > 1) { 437 if (smp_num_siblings > 1) {
444 for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { 438 for_each_cpu(i, cpu_sibling_setup_mask) {
445 if (c->phys_proc_id == cpu_data(i).phys_proc_id && 439 struct cpuinfo_x86 *o = &cpu_data(i);
446 c->cpu_core_id == cpu_data(i).cpu_core_id) { 440
447 cpu_set(i, per_cpu(cpu_sibling_map, cpu)); 441 if (c->phys_proc_id == o->phys_proc_id &&
448 cpu_set(cpu, per_cpu(cpu_sibling_map, i)); 442 c->cpu_core_id == o->cpu_core_id) {
449 cpu_set(i, per_cpu(cpu_core_map, cpu)); 443 cpumask_set_cpu(i, cpu_sibling_mask(cpu));
450 cpu_set(cpu, per_cpu(cpu_core_map, i)); 444 cpumask_set_cpu(cpu, cpu_sibling_mask(i));
451 cpu_set(i, c->llc_shared_map); 445 cpumask_set_cpu(i, cpu_core_mask(cpu));
452 cpu_set(cpu, cpu_data(i).llc_shared_map); 446 cpumask_set_cpu(cpu, cpu_core_mask(i));
447 cpumask_set_cpu(i, &c->llc_shared_map);
448 cpumask_set_cpu(cpu, &o->llc_shared_map);
453 } 449 }
454 } 450 }
455 } else { 451 } else {
456 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); 452 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
457 } 453 }
458 454
459 cpu_set(cpu, c->llc_shared_map); 455 cpumask_set_cpu(cpu, &c->llc_shared_map);
460 456
461 if (current_cpu_data.x86_max_cores == 1) { 457 if (current_cpu_data.x86_max_cores == 1) {
462 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); 458 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
463 c->booted_cores = 1; 459 c->booted_cores = 1;
464 return; 460 return;
465 } 461 }
466 462
467 for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { 463 for_each_cpu(i, cpu_sibling_setup_mask) {
468 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 464 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
469 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 465 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
470 cpu_set(i, c->llc_shared_map); 466 cpumask_set_cpu(i, &c->llc_shared_map);
471 cpu_set(cpu, cpu_data(i).llc_shared_map); 467 cpumask_set_cpu(cpu, &cpu_data(i).llc_shared_map);
472 } 468 }
473 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 469 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
474 cpu_set(i, per_cpu(cpu_core_map, cpu)); 470 cpumask_set_cpu(i, cpu_core_mask(cpu));
475 cpu_set(cpu, per_cpu(cpu_core_map, i)); 471 cpumask_set_cpu(cpu, cpu_core_mask(i));
476 /* 472 /*
477 * Does this new cpu bringup a new core? 473 * Does this new cpu bringup a new core?
478 */ 474 */
479 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { 475 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
480 /* 476 /*
481 * for each core in package, increment 477 * for each core in package, increment
482 * the booted_cores for this new cpu 478 * the booted_cores for this new cpu
483 */ 479 */
484 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) 480 if (cpumask_first(cpu_sibling_mask(i)) == i)
485 c->booted_cores++; 481 c->booted_cores++;
486 /* 482 /*
487 * increment the core count for all 483 * increment the core count for all
@@ -504,7 +500,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
504 * And for power savings, we return cpu_core_map 500 * And for power savings, we return cpu_core_map
505 */ 501 */
506 if (sched_mc_power_savings || sched_smt_power_savings) 502 if (sched_mc_power_savings || sched_smt_power_savings)
507 return &per_cpu(cpu_core_map, cpu); 503 return cpu_core_mask(cpu);
508 else 504 else
509 return &c->llc_shared_map; 505 return &c->llc_shared_map;
510} 506}
@@ -523,7 +519,7 @@ static void impress_friends(void)
523 */ 519 */
524 pr_debug("Before bogomips.\n"); 520 pr_debug("Before bogomips.\n");
525 for_each_possible_cpu(cpu) 521 for_each_possible_cpu(cpu)
526 if (cpu_isset(cpu, cpu_callout_map)) 522 if (cpumask_test_cpu(cpu, cpu_callout_mask))
527 bogosum += cpu_data(cpu).loops_per_jiffy; 523 bogosum += cpu_data(cpu).loops_per_jiffy;
528 printk(KERN_INFO 524 printk(KERN_INFO
529 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 525 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
@@ -904,19 +900,19 @@ do_rest:
904 * allow APs to start initializing. 900 * allow APs to start initializing.
905 */ 901 */
906 pr_debug("Before Callout %d.\n", cpu); 902 pr_debug("Before Callout %d.\n", cpu);
907 cpu_set(cpu, cpu_callout_map); 903 cpumask_set_cpu(cpu, cpu_callout_mask);
908 pr_debug("After Callout %d.\n", cpu); 904 pr_debug("After Callout %d.\n", cpu);
909 905
910 /* 906 /*
911 * Wait 5s total for a response 907 * Wait 5s total for a response
912 */ 908 */
913 for (timeout = 0; timeout < 50000; timeout++) { 909 for (timeout = 0; timeout < 50000; timeout++) {
914 if (cpu_isset(cpu, cpu_callin_map)) 910 if (cpumask_test_cpu(cpu, cpu_callin_mask))
915 break; /* It has booted */ 911 break; /* It has booted */
916 udelay(100); 912 udelay(100);
917 } 913 }
918 914
919 if (cpu_isset(cpu, cpu_callin_map)) { 915 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
920 /* number CPUs logically, starting from 1 (BSP is 0) */ 916 /* number CPUs logically, starting from 1 (BSP is 0) */
921 pr_debug("OK.\n"); 917 pr_debug("OK.\n");
922 printk(KERN_INFO "CPU%d: ", cpu); 918 printk(KERN_INFO "CPU%d: ", cpu);
@@ -941,9 +937,14 @@ restore_state:
941 if (boot_error) { 937 if (boot_error) {
942 /* Try to put things back the way they were before ... */ 938 /* Try to put things back the way they were before ... */
943 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 939 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
944 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ 940
945 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ 941 /* was set by do_boot_cpu() */
946 cpu_clear(cpu, cpu_present_map); 942 cpumask_clear_cpu(cpu, cpu_callout_mask);
943
944 /* was set by cpu_init() */
945 cpumask_clear_cpu(cpu, cpu_initialized_mask);
946
947 set_cpu_present(cpu, false);
947 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 948 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
948 } 949 }
949 950
@@ -977,7 +978,7 @@ int __cpuinit native_cpu_up(unsigned int cpu)
977 /* 978 /*
978 * Already booted CPU? 979 * Already booted CPU?
979 */ 980 */
980 if (cpu_isset(cpu, cpu_callin_map)) { 981 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
981 pr_debug("do_boot_cpu %d Already started\n", cpu); 982 pr_debug("do_boot_cpu %d Already started\n", cpu);
982 return -ENOSYS; 983 return -ENOSYS;
983 } 984 }
@@ -1032,8 +1033,9 @@ int __cpuinit native_cpu_up(unsigned int cpu)
1032 */ 1033 */
1033static __init void disable_smp(void) 1034static __init void disable_smp(void)
1034{ 1035{
1035 cpu_present_map = cpumask_of_cpu(0); 1036 /* use the read/write pointers to the present and possible maps */
1036 cpu_possible_map = cpumask_of_cpu(0); 1037 cpumask_copy(&cpu_present_map, cpumask_of(0));
1038 cpumask_copy(&cpu_possible_map, cpumask_of(0));
1037 smpboot_clear_io_apic_irqs(); 1039 smpboot_clear_io_apic_irqs();
1038 1040
1039 if (smp_found_config) 1041 if (smp_found_config)
@@ -1041,8 +1043,8 @@ static __init void disable_smp(void)
1041 else 1043 else
1042 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1044 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1043 map_cpu_to_logical_apicid(); 1045 map_cpu_to_logical_apicid();
1044 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 1046 cpumask_set_cpu(0, cpu_sibling_mask(0));
1045 cpu_set(0, per_cpu(cpu_core_map, 0)); 1047 cpumask_set_cpu(0, cpu_core_mask(0));
1046} 1048}
1047 1049
1048/* 1050/*
@@ -1064,14 +1066,14 @@ static int __init smp_sanity_check(unsigned max_cpus)
1064 nr = 0; 1066 nr = 0;
1065 for_each_present_cpu(cpu) { 1067 for_each_present_cpu(cpu) {
1066 if (nr >= 8) 1068 if (nr >= 8)
1067 cpu_clear(cpu, cpu_present_map); 1069 set_cpu_present(cpu, false);
1068 nr++; 1070 nr++;
1069 } 1071 }
1070 1072
1071 nr = 0; 1073 nr = 0;
1072 for_each_possible_cpu(cpu) { 1074 for_each_possible_cpu(cpu) {
1073 if (nr >= 8) 1075 if (nr >= 8)
1074 cpu_clear(cpu, cpu_possible_map); 1076 set_cpu_possible(cpu, false);
1075 nr++; 1077 nr++;
1076 } 1078 }
1077 1079
@@ -1167,7 +1169,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
1167 preempt_disable(); 1169 preempt_disable();
1168 smp_cpu_index_default(); 1170 smp_cpu_index_default();
1169 current_cpu_data = boot_cpu_data; 1171 current_cpu_data = boot_cpu_data;
1170 cpu_callin_map = cpumask_of_cpu(0); 1172 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1171 mb(); 1173 mb();
1172 /* 1174 /*
1173 * Setup boot CPU information 1175 * Setup boot CPU information
@@ -1242,8 +1244,8 @@ void __init native_smp_prepare_boot_cpu(void)
1242 init_gdt(me); 1244 init_gdt(me);
1243#endif 1245#endif
1244 switch_to_new_gdt(); 1246 switch_to_new_gdt();
1245 /* already set me in cpu_online_map in boot_cpu_init() */ 1247 /* already set me in cpu_online_mask in boot_cpu_init() */
1246 cpu_set(me, cpu_callout_map); 1248 cpumask_set_cpu(me, cpu_callout_mask);
1247 per_cpu(cpu_state, me) = CPU_ONLINE; 1249 per_cpu(cpu_state, me) = CPU_ONLINE;
1248} 1250}
1249 1251
@@ -1311,7 +1313,7 @@ __init void prefill_possible_map(void)
1311 possible, max_t(int, possible - num_processors, 0)); 1313 possible, max_t(int, possible - num_processors, 0));
1312 1314
1313 for (i = 0; i < possible; i++) 1315 for (i = 0; i < possible; i++)
1314 cpu_set(i, cpu_possible_map); 1316 set_cpu_possible(i, true);
1315 1317
1316 nr_cpu_ids = possible; 1318 nr_cpu_ids = possible;
1317} 1319}
@@ -1323,31 +1325,31 @@ static void remove_siblinginfo(int cpu)
1323 int sibling; 1325 int sibling;
1324 struct cpuinfo_x86 *c = &cpu_data(cpu); 1326 struct cpuinfo_x86 *c = &cpu_data(cpu);
1325 1327
1326 for_each_cpu_mask_nr(sibling, per_cpu(cpu_core_map, cpu)) { 1328 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1327 cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); 1329 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1328 /*/ 1330 /*/
1329 * last thread sibling in this cpu core going down 1331 * last thread sibling in this cpu core going down
1330 */ 1332 */
1331 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) 1333 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1332 cpu_data(sibling).booted_cores--; 1334 cpu_data(sibling).booted_cores--;
1333 } 1335 }
1334 1336
1335 for_each_cpu_mask_nr(sibling, per_cpu(cpu_sibling_map, cpu)) 1337 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1336 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); 1338 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1337 cpus_clear(per_cpu(cpu_sibling_map, cpu)); 1339 cpumask_clear(cpu_sibling_mask(cpu));
1338 cpus_clear(per_cpu(cpu_core_map, cpu)); 1340 cpumask_clear(cpu_core_mask(cpu));
1339 c->phys_proc_id = 0; 1341 c->phys_proc_id = 0;
1340 c->cpu_core_id = 0; 1342 c->cpu_core_id = 0;
1341 cpu_clear(cpu, cpu_sibling_setup_map); 1343 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1342} 1344}
1343 1345
1344static void __ref remove_cpu_from_maps(int cpu) 1346static void __ref remove_cpu_from_maps(int cpu)
1345{ 1347{
1346 cpu_clear(cpu, cpu_online_map); 1348 set_cpu_online(cpu, false);
1347 cpu_clear(cpu, cpu_callout_map); 1349 cpumask_clear_cpu(cpu, cpu_callout_mask);
1348 cpu_clear(cpu, cpu_callin_map); 1350 cpumask_clear_cpu(cpu, cpu_callin_mask);
1349 /* was set by cpu_init() */ 1351 /* was set by cpu_init() */
1350 cpu_clear(cpu, cpu_initialized); 1352 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1351 numa_remove_cpu(cpu); 1353 numa_remove_cpu(cpu);
1352} 1354}
1353 1355
diff --git a/arch/x86/kernel/time_32.c b/arch/x86/kernel/time_32.c
index 65309e4cb1c0..3985cac0ed47 100644
--- a/arch/x86/kernel/time_32.c
+++ b/arch/x86/kernel/time_32.c
@@ -105,8 +105,8 @@ irqreturn_t timer_interrupt(int irq, void *dev_id)
105 high bit of the PPI port B (0x61). Note that some PS/2s, 105 high bit of the PPI port B (0x61). Note that some PS/2s,
106 notably the 55SX, work fine if this is removed. */ 106 notably the 55SX, work fine if this is removed. */
107 107
108 u8 irq_v = inb_p( 0x61 ); /* read the current state */ 108 u8 irq_v = inb_p(0x61); /* read the current state */
109 outb_p( irq_v|0x80, 0x61 ); /* reset the IRQ */ 109 outb_p(irq_v | 0x80, 0x61); /* reset the IRQ */
110 } 110 }
111#endif 111#endif
112 112
diff --git a/arch/x86/kernel/time_64.c b/arch/x86/kernel/time_64.c
index 891e7a7c4334..e6e695acd725 100644
--- a/arch/x86/kernel/time_64.c
+++ b/arch/x86/kernel/time_64.c
@@ -17,10 +17,10 @@
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/time.h> 18#include <linux/time.h>
19#include <linux/mca.h> 19#include <linux/mca.h>
20#include <linux/nmi.h>
20 21
21#include <asm/i8253.h> 22#include <asm/i8253.h>
22#include <asm/hpet.h> 23#include <asm/hpet.h>
23#include <asm/nmi.h>
24#include <asm/vgtod.h> 24#include <asm/vgtod.h>
25#include <asm/time.h> 25#include <asm/time.h>
26#include <asm/timer.h> 26#include <asm/timer.h>
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index c9a666cdd3db..98c2d055284b 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -63,9 +63,6 @@
63#else 63#else
64#include <asm/processor-flags.h> 64#include <asm/processor-flags.h>
65#include <asm/arch_hooks.h> 65#include <asm/arch_hooks.h>
66#include <asm/nmi.h>
67#include <asm/smp.h>
68#include <asm/io.h>
69#include <asm/traps.h> 66#include <asm/traps.h>
70 67
71#include "cpu/mcheck/mce.h" 68#include "cpu/mcheck/mce.h"
diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/kernel/visws_quirks.c
index 0c9667f0752a..d801d06af068 100644
--- a/arch/x86/kernel/visws_quirks.c
+++ b/arch/x86/kernel/visws_quirks.c
@@ -176,33 +176,31 @@ static int __init visws_get_smp_config(unsigned int early)
176 * No problem for Linux. 176 * No problem for Linux.
177 */ 177 */
178 178
179static void __init MP_processor_info(struct mpc_config_processor *m) 179static void __init MP_processor_info(struct mpc_cpu *m)
180{ 180{
181 int ver, logical_apicid; 181 int ver, logical_apicid;
182 physid_mask_t apic_cpus; 182 physid_mask_t apic_cpus;
183 183
184 if (!(m->mpc_cpuflag & CPU_ENABLED)) 184 if (!(m->cpuflag & CPU_ENABLED))
185 return; 185 return;
186 186
187 logical_apicid = m->mpc_apicid; 187 logical_apicid = m->apicid;
188 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n", 188 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
189 m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "", 189 m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
190 m->mpc_apicid, 190 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
191 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, 191 (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
192 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
193 m->mpc_apicver);
194 192
195 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) 193 if (m->cpuflag & CPU_BOOTPROCESSOR)
196 boot_cpu_physical_apicid = m->mpc_apicid; 194 boot_cpu_physical_apicid = m->apicid;
197 195
198 ver = m->mpc_apicver; 196 ver = m->apicver;
199 if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) { 197 if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
200 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n", 198 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
201 m->mpc_apicid, MAX_APICS); 199 m->apicid, MAX_APICS);
202 return; 200 return;
203 } 201 }
204 202
205 apic_cpus = apicid_to_cpu_present(m->mpc_apicid); 203 apic_cpus = apicid_to_cpu_present(m->apicid);
206 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus); 204 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
207 /* 205 /*
208 * Validate version 206 * Validate version
@@ -210,15 +208,15 @@ static void __init MP_processor_info(struct mpc_config_processor *m)
210 if (ver == 0x0) { 208 if (ver == 0x0) {
211 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! " 209 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
212 "fixing up to 0x10. (tell your hw vendor)\n", 210 "fixing up to 0x10. (tell your hw vendor)\n",
213 m->mpc_apicid); 211 m->apicid);
214 ver = 0x10; 212 ver = 0x10;
215 } 213 }
216 apic_version[m->mpc_apicid] = ver; 214 apic_version[m->apicid] = ver;
217} 215}
218 216
219static int __init visws_find_smp_config(unsigned int reserve) 217static int __init visws_find_smp_config(unsigned int reserve)
220{ 218{
221 struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS); 219 struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
222 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS)); 220 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
223 221
224 if (ncpus > CO_CPU_MAX) { 222 if (ncpus > CO_CPU_MAX) {
diff --git a/arch/x86/mach-generic/es7000.c b/arch/x86/mach-generic/es7000.c
index 4ba5ccaa1584..c2ded1448024 100644
--- a/arch/x86/mach-generic/es7000.c
+++ b/arch/x86/mach-generic/es7000.c
@@ -43,12 +43,12 @@ static void __init enable_apic_mode(void)
43 return; 43 return;
44} 44}
45 45
46static __init int mps_oem_check(struct mp_config_table *mpc, char *oem, 46static __init int
47 char *productid) 47mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
48{ 48{
49 if (mpc->mpc_oemptr) { 49 if (mpc->oemptr) {
50 struct mp_config_oemtable *oem_table = 50 struct mpc_oemtable *oem_table =
51 (struct mp_config_oemtable *)mpc->mpc_oemptr; 51 (struct mpc_oemtable *)mpc->oemptr;
52 if (!strncmp(oem, "UNISYS", 6)) 52 if (!strncmp(oem, "UNISYS", 6))
53 return parse_unisys_oem((char *)oem_table); 53 return parse_unisys_oem((char *)oem_table);
54 } 54 }
diff --git a/arch/x86/mach-generic/numaq.c b/arch/x86/mach-generic/numaq.c
index 511d7941364f..3679e2255645 100644
--- a/arch/x86/mach-generic/numaq.c
+++ b/arch/x86/mach-generic/numaq.c
@@ -19,8 +19,7 @@
19#include <asm/numaq/wakecpu.h> 19#include <asm/numaq/wakecpu.h>
20#include <asm/numaq.h> 20#include <asm/numaq.h>
21 21
22static int mps_oem_check(struct mp_config_table *mpc, char *oem, 22static int mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
23 char *productid)
24{ 23{
25 numaq_mps_oem_check(mpc, oem, productid); 24 numaq_mps_oem_check(mpc, oem, productid);
26 return found_numaq; 25 return found_numaq;
diff --git a/arch/x86/mach-generic/probe.c b/arch/x86/mach-generic/probe.c
index c346d9d0226f..15a38daef1a8 100644
--- a/arch/x86/mach-generic/probe.c
+++ b/arch/x86/mach-generic/probe.c
@@ -110,8 +110,7 @@ void __init generic_apic_probe(void)
110 110
111/* These functions can switch the APIC even after the initial ->probe() */ 111/* These functions can switch the APIC even after the initial ->probe() */
112 112
113int __init mps_oem_check(struct mp_config_table *mpc, char *oem, 113int __init mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
114 char *productid)
115{ 114{
116 int i; 115 int i;
117 for (i = 0; apic_probe[i]; ++i) { 116 for (i = 0; apic_probe[i]; ++i) {
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 9e268b6b204e..90dfae511a41 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -534,7 +534,7 @@ static int vmalloc_fault(unsigned long address)
534 happen within a race in page table update. In the later 534 happen within a race in page table update. In the later
535 case just flush. */ 535 case just flush. */
536 536
537 pgd = pgd_offset(current->mm ?: &init_mm, address); 537 pgd = pgd_offset(current->active_mm, address);
538 pgd_ref = pgd_offset_k(address); 538 pgd_ref = pgd_offset_k(address);
539 if (pgd_none(*pgd_ref)) 539 if (pgd_none(*pgd_ref))
540 return -1; 540 return -1;
diff --git a/arch/x86/mm/k8topology_64.c b/arch/x86/mm/k8topology_64.c
index 41f1b5c00a1d..268f8255280f 100644
--- a/arch/x86/mm/k8topology_64.c
+++ b/arch/x86/mm/k8topology_64.c
@@ -81,7 +81,6 @@ int __init k8_scan_nodes(unsigned long start, unsigned long end)
81 unsigned numnodes, cores, bits, apicid_base; 81 unsigned numnodes, cores, bits, apicid_base;
82 unsigned long prevbase; 82 unsigned long prevbase;
83 struct bootnode nodes[8]; 83 struct bootnode nodes[8];
84 unsigned char nodeids[8];
85 int i, j, nb, found = 0; 84 int i, j, nb, found = 0;
86 u32 nodeid, reg; 85 u32 nodeid, reg;
87 86
@@ -110,7 +109,6 @@ int __init k8_scan_nodes(unsigned long start, unsigned long end)
110 limit = read_pci_config(0, nb, 1, 0x44 + i*8); 109 limit = read_pci_config(0, nb, 1, 0x44 + i*8);
111 110
112 nodeid = limit & 7; 111 nodeid = limit & 7;
113 nodeids[i] = nodeid;
114 if ((base & 3) == 0) { 112 if ((base & 3) == 0) {
115 if (i < numnodes) 113 if (i < numnodes)
116 printk("Skipping disabled node %d\n", i); 114 printk("Skipping disabled node %d\n", i);
@@ -179,9 +177,6 @@ int __init k8_scan_nodes(unsigned long start, unsigned long end)
179 177
180 nodes[nodeid].start = base; 178 nodes[nodeid].start = base;
181 nodes[nodeid].end = limit; 179 nodes[nodeid].end = limit;
182 e820_register_active_regions(nodeid,
183 nodes[nodeid].start >> PAGE_SHIFT,
184 nodes[nodeid].end >> PAGE_SHIFT);
185 180
186 prevbase = base; 181 prevbase = base;
187 182
@@ -211,12 +206,15 @@ int __init k8_scan_nodes(unsigned long start, unsigned long end)
211 } 206 }
212 207
213 for (i = 0; i < 8; i++) { 208 for (i = 0; i < 8; i++) {
214 if (nodes[i].start != nodes[i].end) { 209 if (nodes[i].start == nodes[i].end)
215 nodeid = nodeids[i]; 210 continue;
216 for (j = apicid_base; j < cores + apicid_base; j++) 211
217 apicid_to_node[(nodeid << bits) + j] = i; 212 e820_register_active_regions(i,
218 setup_node_bootmem(i, nodes[i].start, nodes[i].end); 213 nodes[i].start >> PAGE_SHIFT,
219 } 214 nodes[i].end >> PAGE_SHIFT);
215 for (j = apicid_base; j < cores + apicid_base; j++)
216 apicid_to_node[(i << bits) + j] = i;
217 setup_node_bootmem(i, nodes[i].start, nodes[i].end);
220 } 218 }
221 219
222 numa_init_array(); 220 numa_init_array();
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 98658f25f542..8fdf06e4edf9 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -2,7 +2,7 @@
2 * @file op_model_amd.c 2 * @file op_model_amd.c
3 * athlon / K7 / K8 / Family 10h model-specific MSR operations 3 * athlon / K7 / K8 / Family 10h model-specific MSR operations
4 * 4 *
5 * @remark Copyright 2002-2008 OProfile authors 5 * @remark Copyright 2002-2009 OProfile authors
6 * @remark Read the file COPYING 6 * @remark Read the file COPYING
7 * 7 *
8 * @author John Levon 8 * @author John Levon
@@ -10,7 +10,7 @@
10 * @author Graydon Hoare 10 * @author Graydon Hoare
11 * @author Robert Richter <robert.richter@amd.com> 11 * @author Robert Richter <robert.richter@amd.com>
12 * @author Barry Kasindorf 12 * @author Barry Kasindorf
13*/ 13 */
14 14
15#include <linux/oprofile.h> 15#include <linux/oprofile.h>
16#include <linux/device.h> 16#include <linux/device.h>
@@ -60,53 +60,10 @@ static unsigned long reset_value[NUM_COUNTERS];
60#define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */ 60#define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */
61#define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */ 61#define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */
62 62
63/* Codes used in cpu_buffer.c */ 63#define IBS_FETCH_SIZE 6
64/* This produces duplicate code, need to be fixed */ 64#define IBS_OP_SIZE 12
65#define IBS_FETCH_BEGIN 3
66#define IBS_OP_BEGIN 4
67
68/*
69 * The function interface needs to be fixed, something like add
70 * data. Should then be added to linux/oprofile.h.
71 */
72extern void
73oprofile_add_ibs_sample(struct pt_regs * const regs,
74 unsigned int * const ibs_sample, int ibs_code);
75
76struct ibs_fetch_sample {
77 /* MSRC001_1031 IBS Fetch Linear Address Register */
78 unsigned int ibs_fetch_lin_addr_low;
79 unsigned int ibs_fetch_lin_addr_high;
80 /* MSRC001_1030 IBS Fetch Control Register */
81 unsigned int ibs_fetch_ctl_low;
82 unsigned int ibs_fetch_ctl_high;
83 /* MSRC001_1032 IBS Fetch Physical Address Register */
84 unsigned int ibs_fetch_phys_addr_low;
85 unsigned int ibs_fetch_phys_addr_high;
86};
87
88struct ibs_op_sample {
89 /* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
90 unsigned int ibs_op_rip_low;
91 unsigned int ibs_op_rip_high;
92 /* MSRC001_1035 IBS Op Data Register */
93 unsigned int ibs_op_data1_low;
94 unsigned int ibs_op_data1_high;
95 /* MSRC001_1036 IBS Op Data 2 Register */
96 unsigned int ibs_op_data2_low;
97 unsigned int ibs_op_data2_high;
98 /* MSRC001_1037 IBS Op Data 3 Register */
99 unsigned int ibs_op_data3_low;
100 unsigned int ibs_op_data3_high;
101 /* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
102 unsigned int ibs_dc_linear_low;
103 unsigned int ibs_dc_linear_high;
104 /* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
105 unsigned int ibs_dc_phys_low;
106 unsigned int ibs_dc_phys_high;
107};
108 65
109static int ibs_allowed; /* AMD Family10h and later */ 66static int has_ibs; /* AMD Family10h and later */
110 67
111struct op_ibs_config { 68struct op_ibs_config {
112 unsigned long op_enabled; 69 unsigned long op_enabled;
@@ -197,31 +154,29 @@ static inline int
197op_amd_handle_ibs(struct pt_regs * const regs, 154op_amd_handle_ibs(struct pt_regs * const regs,
198 struct op_msrs const * const msrs) 155 struct op_msrs const * const msrs)
199{ 156{
200 unsigned int low, high; 157 u32 low, high;
201 struct ibs_fetch_sample ibs_fetch; 158 u64 msr;
202 struct ibs_op_sample ibs_op; 159 struct op_entry entry;
203 160
204 if (!ibs_allowed) 161 if (!has_ibs)
205 return 1; 162 return 1;
206 163
207 if (ibs_config.fetch_enabled) { 164 if (ibs_config.fetch_enabled) {
208 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); 165 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
209 if (high & IBS_FETCH_HIGH_VALID_BIT) { 166 if (high & IBS_FETCH_HIGH_VALID_BIT) {
210 ibs_fetch.ibs_fetch_ctl_high = high; 167 rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
211 ibs_fetch.ibs_fetch_ctl_low = low; 168 oprofile_write_reserve(&entry, regs, msr,
212 rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high); 169 IBS_FETCH_CODE, IBS_FETCH_SIZE);
213 ibs_fetch.ibs_fetch_lin_addr_high = high; 170 oprofile_add_data(&entry, (u32)msr);
214 ibs_fetch.ibs_fetch_lin_addr_low = low; 171 oprofile_add_data(&entry, (u32)(msr >> 32));
215 rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high); 172 oprofile_add_data(&entry, low);
216 ibs_fetch.ibs_fetch_phys_addr_high = high; 173 oprofile_add_data(&entry, high);
217 ibs_fetch.ibs_fetch_phys_addr_low = low; 174 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
218 175 oprofile_add_data(&entry, (u32)msr);
219 oprofile_add_ibs_sample(regs, 176 oprofile_add_data(&entry, (u32)(msr >> 32));
220 (unsigned int *)&ibs_fetch, 177 oprofile_write_commit(&entry);
221 IBS_FETCH_BEGIN);
222 178
223 /* reenable the IRQ */ 179 /* reenable the IRQ */
224 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
225 high &= ~IBS_FETCH_HIGH_VALID_BIT; 180 high &= ~IBS_FETCH_HIGH_VALID_BIT;
226 high |= IBS_FETCH_HIGH_ENABLE; 181 high |= IBS_FETCH_HIGH_ENABLE;
227 low &= IBS_FETCH_LOW_MAX_CNT_MASK; 182 low &= IBS_FETCH_LOW_MAX_CNT_MASK;
@@ -232,30 +187,29 @@ op_amd_handle_ibs(struct pt_regs * const regs,
232 if (ibs_config.op_enabled) { 187 if (ibs_config.op_enabled) {
233 rdmsr(MSR_AMD64_IBSOPCTL, low, high); 188 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
234 if (low & IBS_OP_LOW_VALID_BIT) { 189 if (low & IBS_OP_LOW_VALID_BIT) {
235 rdmsr(MSR_AMD64_IBSOPRIP, low, high); 190 rdmsrl(MSR_AMD64_IBSOPRIP, msr);
236 ibs_op.ibs_op_rip_low = low; 191 oprofile_write_reserve(&entry, regs, msr,
237 ibs_op.ibs_op_rip_high = high; 192 IBS_OP_CODE, IBS_OP_SIZE);
238 rdmsr(MSR_AMD64_IBSOPDATA, low, high); 193 oprofile_add_data(&entry, (u32)msr);
239 ibs_op.ibs_op_data1_low = low; 194 oprofile_add_data(&entry, (u32)(msr >> 32));
240 ibs_op.ibs_op_data1_high = high; 195 rdmsrl(MSR_AMD64_IBSOPDATA, msr);
241 rdmsr(MSR_AMD64_IBSOPDATA2, low, high); 196 oprofile_add_data(&entry, (u32)msr);
242 ibs_op.ibs_op_data2_low = low; 197 oprofile_add_data(&entry, (u32)(msr >> 32));
243 ibs_op.ibs_op_data2_high = high; 198 rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
244 rdmsr(MSR_AMD64_IBSOPDATA3, low, high); 199 oprofile_add_data(&entry, (u32)msr);
245 ibs_op.ibs_op_data3_low = low; 200 oprofile_add_data(&entry, (u32)(msr >> 32));
246 ibs_op.ibs_op_data3_high = high; 201 rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
247 rdmsr(MSR_AMD64_IBSDCLINAD, low, high); 202 oprofile_add_data(&entry, (u32)msr);
248 ibs_op.ibs_dc_linear_low = low; 203 oprofile_add_data(&entry, (u32)(msr >> 32));
249 ibs_op.ibs_dc_linear_high = high; 204 rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
250 rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high); 205 oprofile_add_data(&entry, (u32)msr);
251 ibs_op.ibs_dc_phys_low = low; 206 oprofile_add_data(&entry, (u32)(msr >> 32));
252 ibs_op.ibs_dc_phys_high = high; 207 rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
208 oprofile_add_data(&entry, (u32)msr);
209 oprofile_add_data(&entry, (u32)(msr >> 32));
210 oprofile_write_commit(&entry);
253 211
254 /* reenable the IRQ */ 212 /* reenable the IRQ */
255 oprofile_add_ibs_sample(regs,
256 (unsigned int *)&ibs_op,
257 IBS_OP_BEGIN);
258 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
259 high = 0; 213 high = 0;
260 low &= ~IBS_OP_LOW_VALID_BIT; 214 low &= ~IBS_OP_LOW_VALID_BIT;
261 low |= IBS_OP_LOW_ENABLE; 215 low |= IBS_OP_LOW_ENABLE;
@@ -305,14 +259,14 @@ static void op_amd_start(struct op_msrs const * const msrs)
305 } 259 }
306 260
307#ifdef CONFIG_OPROFILE_IBS 261#ifdef CONFIG_OPROFILE_IBS
308 if (ibs_allowed && ibs_config.fetch_enabled) { 262 if (has_ibs && ibs_config.fetch_enabled) {
309 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; 263 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
310 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */ 264 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
311 + IBS_FETCH_HIGH_ENABLE; 265 + IBS_FETCH_HIGH_ENABLE;
312 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); 266 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
313 } 267 }
314 268
315 if (ibs_allowed && ibs_config.op_enabled) { 269 if (has_ibs && ibs_config.op_enabled) {
316 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) 270 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
317 + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */ 271 + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
318 + IBS_OP_LOW_ENABLE; 272 + IBS_OP_LOW_ENABLE;
@@ -341,14 +295,14 @@ static void op_amd_stop(struct op_msrs const * const msrs)
341 } 295 }
342 296
343#ifdef CONFIG_OPROFILE_IBS 297#ifdef CONFIG_OPROFILE_IBS
344 if (ibs_allowed && ibs_config.fetch_enabled) { 298 if (has_ibs && ibs_config.fetch_enabled) {
345 /* clear max count and enable */ 299 /* clear max count and enable */
346 low = 0; 300 low = 0;
347 high = 0; 301 high = 0;
348 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); 302 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
349 } 303 }
350 304
351 if (ibs_allowed && ibs_config.op_enabled) { 305 if (has_ibs && ibs_config.op_enabled) {
352 /* clear max count and enable */ 306 /* clear max count and enable */
353 low = 0; 307 low = 0;
354 high = 0; 308 high = 0;
@@ -409,6 +363,7 @@ static int init_ibs_nmi(void)
409 | IBSCTL_LVTOFFSETVAL); 363 | IBSCTL_LVTOFFSETVAL);
410 pci_read_config_dword(cpu_cfg, IBSCTL, &value); 364 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
411 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { 365 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
366 pci_dev_put(cpu_cfg);
412 printk(KERN_DEBUG "Failed to setup IBS LVT offset, " 367 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
413 "IBSCTL = 0x%08x", value); 368 "IBSCTL = 0x%08x", value);
414 return 1; 369 return 1;
@@ -436,20 +391,20 @@ static int init_ibs_nmi(void)
436/* uninitialize the APIC for the IBS interrupts if needed */ 391/* uninitialize the APIC for the IBS interrupts if needed */
437static void clear_ibs_nmi(void) 392static void clear_ibs_nmi(void)
438{ 393{
439 if (ibs_allowed) 394 if (has_ibs)
440 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); 395 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
441} 396}
442 397
443/* initialize the APIC for the IBS interrupts if available */ 398/* initialize the APIC for the IBS interrupts if available */
444static void ibs_init(void) 399static void ibs_init(void)
445{ 400{
446 ibs_allowed = boot_cpu_has(X86_FEATURE_IBS); 401 has_ibs = boot_cpu_has(X86_FEATURE_IBS);
447 402
448 if (!ibs_allowed) 403 if (!has_ibs)
449 return; 404 return;
450 405
451 if (init_ibs_nmi()) { 406 if (init_ibs_nmi()) {
452 ibs_allowed = 0; 407 has_ibs = 0;
453 return; 408 return;
454 } 409 }
455 410
@@ -458,7 +413,7 @@ static void ibs_init(void)
458 413
459static void ibs_exit(void) 414static void ibs_exit(void)
460{ 415{
461 if (!ibs_allowed) 416 if (!has_ibs)
462 return; 417 return;
463 418
464 clear_ibs_nmi(); 419 clear_ibs_nmi();
@@ -478,7 +433,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
478 if (ret) 433 if (ret)
479 return ret; 434 return ret;
480 435
481 if (!ibs_allowed) 436 if (!has_ibs)
482 return ret; 437 return ret;
483 438
484 /* model specific files */ 439 /* model specific files */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 17:21:08 -0500